repo_name string | path string | copies string | size string | content string | license string |
|---|---|---|---|---|---|
speef/linux | sound/soc/codecs/alc5632.c | 2401 | 39321 | /*
* alc5632.c -- ALC5632 ALSA SoC Audio Codec
*
* Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
*
* Authors: Leon Romanovsky <leon@leon.nu>
* Andrey Danin <danindrey@mail.ru>
* Ilya Petrov <ilya.muromec@gmail.com>
* Marc Dietrich <marvin24@gmx.de>
*
* Based on alc5623.c by Arnaud Patard
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include "alc5632.h"
/*
* ALC5632 register cache
*/
static struct reg_default alc5632_reg_defaults[] = {
{ 2, 0x8080 }, /* R2 - Speaker Output Volume */
{ 4, 0x8080 }, /* R4 - Headphone Output Volume */
{ 6, 0x8080 }, /* R6 - AUXOUT Volume */
{ 8, 0xC800 }, /* R8 - Phone Input */
{ 10, 0xE808 }, /* R10 - LINE_IN Volume */
{ 12, 0x1010 }, /* R12 - STEREO DAC Input Volume */
{ 14, 0x0808 }, /* R14 - MIC Input Volume */
{ 16, 0xEE0F }, /* R16 - Stereo DAC and MIC Routing Control */
{ 18, 0xCBCB }, /* R18 - ADC Record Gain */
{ 20, 0x7F7F }, /* R20 - ADC Record Mixer Control */
{ 24, 0xE010 }, /* R24 - Voice DAC Volume */
{ 28, 0x8008 }, /* R28 - Output Mixer Control */
{ 34, 0x0000 }, /* R34 - Microphone Control */
{ 36, 0x00C0 }, /* R36 - Codec Digital MIC/Digital Boost
Control */
{ 46, 0x0000 }, /* R46 - Stereo DAC/Voice DAC/Stereo ADC
Function Select */
{ 52, 0x8000 }, /* R52 - Main Serial Data Port Control
(Stereo I2S) */
{ 54, 0x0000 }, /* R54 - Extend Serial Data Port Control
(VoDAC_I2S/PCM) */
{ 58, 0x0000 }, /* R58 - Power Management Addition 1 */
{ 60, 0x0000 }, /* R60 - Power Management Addition 2 */
{ 62, 0x8000 }, /* R62 - Power Management Addition 3 */
{ 64, 0x0C0A }, /* R64 - General Purpose Control Register 1 */
{ 66, 0x0000 }, /* R66 - General Purpose Control Register 2 */
{ 68, 0x0000 }, /* R68 - PLL1 Control */
{ 70, 0x0000 }, /* R70 - PLL2 Control */
{ 76, 0xBE3E }, /* R76 - GPIO Pin Configuration */
{ 78, 0xBE3E }, /* R78 - GPIO Pin Polarity */
{ 80, 0x0000 }, /* R80 - GPIO Pin Sticky */
{ 82, 0x0000 }, /* R82 - GPIO Pin Wake Up */
{ 86, 0x0000 }, /* R86 - Pin Sharing */
{ 90, 0x0009 }, /* R90 - Soft Volume Control Setting */
{ 92, 0x0000 }, /* R92 - GPIO_Output Pin Control */
{ 94, 0x3000 }, /* R94 - MISC Control */
{ 96, 0x3075 }, /* R96 - Stereo DAC Clock Control_1 */
{ 98, 0x1010 }, /* R98 - Stereo DAC Clock Control_2 */
{ 100, 0x3110 }, /* R100 - VoDAC_PCM Clock Control_1 */
{ 104, 0x0553 }, /* R104 - Pseudo Stereo and Spatial Effect
Block Control */
{ 106, 0x0000 }, /* R106 - Private Register Address */
};
/* codec private data */
struct alc5632_priv {
struct regmap *regmap;
u8 id;
unsigned int sysclk;
};
static bool alc5632_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case ALC5632_RESET:
case ALC5632_PWR_DOWN_CTRL_STATUS:
case ALC5632_GPIO_PIN_STATUS:
case ALC5632_OVER_CURR_STATUS:
case ALC5632_HID_CTRL_DATA:
case ALC5632_EQ_CTRL:
case ALC5632_VENDOR_ID1:
case ALC5632_VENDOR_ID2:
return true;
default:
break;
}
return false;
}
static inline int alc5632_reset(struct regmap *map)
{
return regmap_write(map, ALC5632_RESET, 0x59B4);
}
static int amp_mixer_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
/* to power-on/off class-d amp generators/speaker */
/* need to write to 'index-46h' register : */
/* so write index num (here 0x46) to reg 0x6a */
/* and then 0xffff/0 to reg 0x6c */
snd_soc_write(w->codec, ALC5632_HID_CTRL_INDEX, 0x46);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
snd_soc_write(w->codec, ALC5632_HID_CTRL_DATA, 0xFFFF);
break;
case SND_SOC_DAPM_POST_PMD:
snd_soc_write(w->codec, ALC5632_HID_CTRL_DATA, 0);
break;
}
return 0;
}
/*
* ALC5632 Controls
*/
/* -34.5db min scale, 1.5db steps, no mute */
static const DECLARE_TLV_DB_SCALE(vol_tlv, -3450, 150, 0);
/* -46.5db min scale, 1.5db steps, no mute */
static const DECLARE_TLV_DB_SCALE(hp_tlv, -4650, 150, 0);
/* -16.5db min scale, 1.5db steps, no mute */
static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -1650, 150, 0);
static const unsigned int boost_tlv[] = {
TLV_DB_RANGE_HEAD(2),
0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
};
/* 0db min scale, 6 db steps, no mute */
static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0);
/* 0db min scalem 0.75db steps, no mute */
static const DECLARE_TLV_DB_SCALE(vdac_tlv, -3525, 75, 0);
static const struct snd_kcontrol_new alc5632_vol_snd_controls[] = {
/* left starts at bit 8, right at bit 0 */
/* 31 steps (5 bit), -46.5db scale */
SOC_DOUBLE_TLV("Speaker Playback Volume",
ALC5632_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
/* bit 15 mutes left, bit 7 right */
SOC_DOUBLE("Speaker Playback Switch",
ALC5632_SPK_OUT_VOL, 15, 7, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume",
ALC5632_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Headphone Playback Switch",
ALC5632_HP_OUT_VOL, 15, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5632_snd_controls[] = {
SOC_DOUBLE_TLV("Auxout Playback Volume",
ALC5632_AUX_OUT_VOL, 8, 0, 31, 1, hp_tlv),
SOC_DOUBLE("Auxout Playback Switch",
ALC5632_AUX_OUT_VOL, 15, 7, 1, 1),
SOC_SINGLE_TLV("Voice DAC Playback Volume",
ALC5632_VOICE_DAC_VOL, 0, 63, 0, vdac_tlv),
SOC_SINGLE("Voice DAC Playback Switch",
ALC5632_VOICE_DAC_VOL, 12, 1, 1),
SOC_SINGLE_TLV("Phone Playback Volume",
ALC5632_PHONE_IN_VOL, 8, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("LineIn Playback Volume",
ALC5632_LINE_IN_VOL, 8, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("Master Playback Volume",
ALC5632_STEREO_DAC_IN_VOL, 8, 0, 63, 1, vdac_tlv),
SOC_DOUBLE("Master Playback Switch",
ALC5632_STEREO_DAC_IN_VOL, 15, 7, 1, 1),
SOC_SINGLE_TLV("Mic1 Playback Volume",
ALC5632_MIC_VOL, 8, 31, 1, vol_tlv),
SOC_SINGLE_TLV("Mic2 Playback Volume",
ALC5632_MIC_VOL, 0, 31, 1, vol_tlv),
SOC_DOUBLE_TLV("Rec Capture Volume",
ALC5632_ADC_REC_GAIN, 8, 0, 31, 0, adc_rec_tlv),
SOC_SINGLE_TLV("Mic 1 Boost Volume",
ALC5632_MIC_CTRL, 10, 3, 0, boost_tlv),
SOC_SINGLE_TLV("Mic 2 Boost Volume",
ALC5632_MIC_CTRL, 8, 3, 0, boost_tlv),
SOC_SINGLE_TLV("DMIC Boost Capture Volume",
ALC5632_DIGI_BOOST_CTRL, 0, 7, 0, dig_tlv),
SOC_SINGLE("DMIC En Capture Switch",
ALC5632_DIGI_BOOST_CTRL, 15, 1, 0),
SOC_SINGLE("DMIC PreFilter Capture Switch",
ALC5632_DIGI_BOOST_CTRL, 12, 1, 0),
};
/*
* DAPM Controls
*/
static const struct snd_kcontrol_new alc5632_hp_mixer_controls[] = {
SOC_DAPM_SINGLE("LI2HP Playback Switch", ALC5632_LINE_IN_VOL, 15, 1, 1),
SOC_DAPM_SINGLE("PHONE2HP Playback Switch", ALC5632_PHONE_IN_VOL, 15, 1, 1),
SOC_DAPM_SINGLE("MIC12HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 15, 1, 1),
SOC_DAPM_SINGLE("MIC22HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 11, 1, 1),
SOC_DAPM_SINGLE("VOICE2HP Playback Switch", ALC5632_VOICE_DAC_VOL, 15, 1, 1),
};
static const struct snd_kcontrol_new alc5632_hpl_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2HP_L Playback Switch", ALC5632_ADC_REC_GAIN, 15, 1, 1),
SOC_DAPM_SINGLE("DACL2HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 3, 1, 1),
};
static const struct snd_kcontrol_new alc5632_hpr_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2HP_R Playback Switch", ALC5632_ADC_REC_GAIN, 7, 1, 1),
SOC_DAPM_SINGLE("DACR2HP Playback Switch", ALC5632_MIC_ROUTING_CTRL, 2, 1, 1),
};
static const struct snd_kcontrol_new alc5632_mono_mixer_controls[] = {
SOC_DAPM_SINGLE("ADC2MONO_L Playback Switch", ALC5632_ADC_REC_GAIN, 14, 1, 1),
SOC_DAPM_SINGLE("ADC2MONO_R Playback Switch", ALC5632_ADC_REC_GAIN, 6, 1, 1),
SOC_DAPM_SINGLE("LI2MONO Playback Switch", ALC5632_LINE_IN_VOL, 13, 1, 1),
SOC_DAPM_SINGLE("MIC12MONO Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 13, 1, 1),
SOC_DAPM_SINGLE("MIC22MONO Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 9, 1, 1),
SOC_DAPM_SINGLE("DAC2MONO Playback Switch", ALC5632_MIC_ROUTING_CTRL, 0, 1, 1),
SOC_DAPM_SINGLE("VOICE2MONO Playback Switch", ALC5632_VOICE_DAC_VOL, 13, 1, 1),
};
static const struct snd_kcontrol_new alc5632_speaker_mixer_controls[] = {
SOC_DAPM_SINGLE("LI2SPK Playback Switch", ALC5632_LINE_IN_VOL, 14, 1, 1),
SOC_DAPM_SINGLE("PHONE2SPK Playback Switch", ALC5632_PHONE_IN_VOL, 14, 1, 1),
SOC_DAPM_SINGLE("MIC12SPK Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 14, 1, 1),
SOC_DAPM_SINGLE("MIC22SPK Playback Switch",
ALC5632_MIC_ROUTING_CTRL, 10, 1, 1),
SOC_DAPM_SINGLE("DAC2SPK Playback Switch", ALC5632_MIC_ROUTING_CTRL, 1, 1, 1),
SOC_DAPM_SINGLE("VOICE2SPK Playback Switch", ALC5632_VOICE_DAC_VOL, 14, 1, 1),
};
/* Left Record Mixer */
static const struct snd_kcontrol_new alc5632_captureL_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC12REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 14, 1, 1),
SOC_DAPM_SINGLE("MIC22REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 13, 1, 1),
SOC_DAPM_SINGLE("LIL2REC Capture Switch", ALC5632_ADC_REC_MIXER, 12, 1, 1),
SOC_DAPM_SINGLE("PH2REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 11, 1, 1),
SOC_DAPM_SINGLE("HPL2REC Capture Switch", ALC5632_ADC_REC_MIXER, 10, 1, 1),
SOC_DAPM_SINGLE("SPK2REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 9, 1, 1),
SOC_DAPM_SINGLE("MONO2REC_L Capture Switch", ALC5632_ADC_REC_MIXER, 8, 1, 1),
};
/* Right Record Mixer */
static const struct snd_kcontrol_new alc5632_captureR_mixer_controls[] = {
SOC_DAPM_SINGLE("MIC12REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 6, 1, 1),
SOC_DAPM_SINGLE("MIC22REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 5, 1, 1),
SOC_DAPM_SINGLE("LIR2REC Capture Switch", ALC5632_ADC_REC_MIXER, 4, 1, 1),
SOC_DAPM_SINGLE("PH2REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 3, 1, 1),
SOC_DAPM_SINGLE("HPR2REC Capture Switch", ALC5632_ADC_REC_MIXER, 2, 1, 1),
SOC_DAPM_SINGLE("SPK2REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 1, 1, 1),
SOC_DAPM_SINGLE("MONO2REC_R Capture Switch", ALC5632_ADC_REC_MIXER, 0, 1, 1),
};
/* Dmic Mixer */
static const struct snd_kcontrol_new alc5632_dmicl_mixer_controls[] = {
SOC_DAPM_SINGLE("DMICL2ADC Capture Switch", ALC5632_DIGI_BOOST_CTRL, 7, 1, 1),
};
static const struct snd_kcontrol_new alc5632_dmicr_mixer_controls[] = {
SOC_DAPM_SINGLE("DMICR2ADC Capture Switch", ALC5632_DIGI_BOOST_CTRL, 6, 1, 1),
};
static const char * const alc5632_spk_n_sour_sel[] = {
"RN/-R", "RP/+R", "LN/-R", "Mute"};
static const char * const alc5632_hpl_out_input_sel[] = {
"Vmid", "HP Left Mix"};
static const char * const alc5632_hpr_out_input_sel[] = {
"Vmid", "HP Right Mix"};
static const char * const alc5632_spkout_input_sel[] = {
"Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
static const char * const alc5632_aux_out_input_sel[] = {
"Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
static const char * const alc5632_adcr_func_sel[] = {
"Stereo ADC", "Voice ADC"};
static const char * const alc5632_i2s_out_sel[] = {
"ADC LR", "Voice Stereo Digital"};
/* auxout output mux */
static const struct soc_enum alc5632_aux_out_input_enum =
SOC_ENUM_SINGLE(ALC5632_OUTPUT_MIXER_CTRL, 6, 4, alc5632_aux_out_input_sel);
static const struct snd_kcontrol_new alc5632_auxout_mux_controls =
SOC_DAPM_ENUM("AuxOut Mux", alc5632_aux_out_input_enum);
/* speaker output mux */
static const struct soc_enum alc5632_spkout_input_enum =
SOC_ENUM_SINGLE(ALC5632_OUTPUT_MIXER_CTRL, 10, 4, alc5632_spkout_input_sel);
static const struct snd_kcontrol_new alc5632_spkout_mux_controls =
SOC_DAPM_ENUM("SpeakerOut Mux", alc5632_spkout_input_enum);
/* headphone left output mux */
static const struct soc_enum alc5632_hpl_out_input_enum =
SOC_ENUM_SINGLE(ALC5632_OUTPUT_MIXER_CTRL, 9, 2, alc5632_hpl_out_input_sel);
static const struct snd_kcontrol_new alc5632_hpl_out_mux_controls =
SOC_DAPM_ENUM("Left Headphone Mux", alc5632_hpl_out_input_enum);
/* headphone right output mux */
static const struct soc_enum alc5632_hpr_out_input_enum =
SOC_ENUM_SINGLE(ALC5632_OUTPUT_MIXER_CTRL, 8, 2, alc5632_hpr_out_input_sel);
static const struct snd_kcontrol_new alc5632_hpr_out_mux_controls =
SOC_DAPM_ENUM("Right Headphone Mux", alc5632_hpr_out_input_enum);
/* speaker output N select */
static const struct soc_enum alc5632_spk_n_sour_enum =
SOC_ENUM_SINGLE(ALC5632_OUTPUT_MIXER_CTRL, 14, 4, alc5632_spk_n_sour_sel);
static const struct snd_kcontrol_new alc5632_spkoutn_mux_controls =
SOC_DAPM_ENUM("SpeakerOut N Mux", alc5632_spk_n_sour_enum);
/* speaker amplifier */
static const char *alc5632_amp_names[] = {"AB Amp", "D Amp"};
static const struct soc_enum alc5632_amp_enum =
SOC_ENUM_SINGLE(ALC5632_OUTPUT_MIXER_CTRL, 13, 2, alc5632_amp_names);
static const struct snd_kcontrol_new alc5632_amp_mux_controls =
SOC_DAPM_ENUM("AB-D Amp Mux", alc5632_amp_enum);
/* ADC output select */
static const struct soc_enum alc5632_adcr_func_enum =
SOC_ENUM_SINGLE(ALC5632_DAC_FUNC_SELECT, 5, 2, alc5632_adcr_func_sel);
static const struct snd_kcontrol_new alc5632_adcr_func_controls =
SOC_DAPM_ENUM("ADCR Mux", alc5632_adcr_func_enum);
/* I2S out select */
static const struct soc_enum alc5632_i2s_out_enum =
SOC_ENUM_SINGLE(ALC5632_I2S_OUT_CTL, 5, 2, alc5632_i2s_out_sel);
static const struct snd_kcontrol_new alc5632_i2s_out_controls =
SOC_DAPM_ENUM("I2SOut Mux", alc5632_i2s_out_enum);
static const struct snd_soc_dapm_widget alc5632_dapm_widgets[] = {
/* Muxes */
SND_SOC_DAPM_MUX("AuxOut Mux", SND_SOC_NOPM, 0, 0,
&alc5632_auxout_mux_controls),
SND_SOC_DAPM_MUX("SpeakerOut Mux", SND_SOC_NOPM, 0, 0,
&alc5632_spkout_mux_controls),
SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0,
&alc5632_hpl_out_mux_controls),
SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0,
&alc5632_hpr_out_mux_controls),
SND_SOC_DAPM_MUX("SpeakerOut N Mux", SND_SOC_NOPM, 0, 0,
&alc5632_spkoutn_mux_controls),
SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
&alc5632_adcr_func_controls),
SND_SOC_DAPM_MUX("I2SOut Mux", ALC5632_PWR_MANAG_ADD1, 11, 0,
&alc5632_i2s_out_controls),
/* output mixers */
SND_SOC_DAPM_MIXER("HP Mix", SND_SOC_NOPM, 0, 0,
&alc5632_hp_mixer_controls[0],
ARRAY_SIZE(alc5632_hp_mixer_controls)),
SND_SOC_DAPM_MIXER("HPR Mix", ALC5632_PWR_MANAG_ADD2, 4, 0,
&alc5632_hpr_mixer_controls[0],
ARRAY_SIZE(alc5632_hpr_mixer_controls)),
SND_SOC_DAPM_MIXER("HPL Mix", ALC5632_PWR_MANAG_ADD2, 5, 0,
&alc5632_hpl_mixer_controls[0],
ARRAY_SIZE(alc5632_hpl_mixer_controls)),
SND_SOC_DAPM_MIXER("HPOut Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Mono Mix", ALC5632_PWR_MANAG_ADD2, 2, 0,
&alc5632_mono_mixer_controls[0],
ARRAY_SIZE(alc5632_mono_mixer_controls)),
SND_SOC_DAPM_MIXER("Speaker Mix", ALC5632_PWR_MANAG_ADD2, 3, 0,
&alc5632_speaker_mixer_controls[0],
ARRAY_SIZE(alc5632_speaker_mixer_controls)),
SND_SOC_DAPM_MIXER("DMICL Mix", SND_SOC_NOPM, 0, 0,
&alc5632_dmicl_mixer_controls[0],
ARRAY_SIZE(alc5632_dmicl_mixer_controls)),
SND_SOC_DAPM_MIXER("DMICR Mix", SND_SOC_NOPM, 0, 0,
&alc5632_dmicr_mixer_controls[0],
ARRAY_SIZE(alc5632_dmicr_mixer_controls)),
/* input mixers */
SND_SOC_DAPM_MIXER("Left Capture Mix", ALC5632_PWR_MANAG_ADD2, 1, 0,
&alc5632_captureL_mixer_controls[0],
ARRAY_SIZE(alc5632_captureL_mixer_controls)),
SND_SOC_DAPM_MIXER("Right Capture Mix", ALC5632_PWR_MANAG_ADD2, 0, 0,
&alc5632_captureR_mixer_controls[0],
ARRAY_SIZE(alc5632_captureR_mixer_controls)),
SND_SOC_DAPM_AIF_IN("AIFRXL", "Left HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("AIFRXR", "Right HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("VAIFRX", "Voice Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("VAIFTX", "Voice Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("Voice DAC", NULL, ALC5632_PWR_MANAG_ADD2, 10, 0),
SND_SOC_DAPM_DAC("Left DAC", NULL, ALC5632_PWR_MANAG_ADD2, 9, 0),
SND_SOC_DAPM_DAC("Right DAC", NULL, ALC5632_PWR_MANAG_ADD2, 8, 0),
SND_SOC_DAPM_ADC("Left ADC", NULL, ALC5632_PWR_MANAG_ADD2, 7, 0),
SND_SOC_DAPM_ADC("Right ADC", NULL, ALC5632_PWR_MANAG_ADD2, 6, 0),
SND_SOC_DAPM_MIXER("DAC Left Channel", ALC5632_PWR_MANAG_ADD1, 15, 0, NULL, 0),
SND_SOC_DAPM_MIXER("DAC Right Channel",
ALC5632_PWR_MANAG_ADD1, 14, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I2S Mix", ALC5632_PWR_MANAG_ADD1, 11, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Phone Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Line Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("Voice Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("ADCLR", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Headphone", ALC5632_PWR_MANAG_ADD3, 11, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Headphone", ALC5632_PWR_MANAG_ADD3, 10, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left Speaker", ALC5632_PWR_MANAG_ADD3, 13, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right Speaker", ALC5632_PWR_MANAG_ADD3, 12, 0, NULL, 0),
SND_SOC_DAPM_PGA("Aux Out", ALC5632_PWR_MANAG_ADD3, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Left LineIn", ALC5632_PWR_MANAG_ADD3, 7, 0, NULL, 0),
SND_SOC_DAPM_PGA("Right LineIn", ALC5632_PWR_MANAG_ADD3, 6, 0, NULL, 0),
SND_SOC_DAPM_PGA("Phone", ALC5632_PWR_MANAG_ADD3, 5, 0, NULL, 0),
SND_SOC_DAPM_PGA("Phone ADMix", ALC5632_PWR_MANAG_ADD3, 4, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC1 PGA", ALC5632_PWR_MANAG_ADD3, 3, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 PGA", ALC5632_PWR_MANAG_ADD3, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC1 Pre Amp", ALC5632_PWR_MANAG_ADD3, 1, 0, NULL, 0),
SND_SOC_DAPM_PGA("MIC2 Pre Amp", ALC5632_PWR_MANAG_ADD3, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", ALC5632_PWR_MANAG_ADD1, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS2", ALC5632_PWR_MANAG_ADD1, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA_E("D Amp", ALC5632_PWR_MANAG_ADD2, 14, 0, NULL, 0,
amp_mixer_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_PGA("AB Amp", ALC5632_PWR_MANAG_ADD2, 15, 0, NULL, 0),
SND_SOC_DAPM_MUX("AB-D Amp Mux", ALC5632_PWR_MANAG_ADD1, 10, 0,
&alc5632_amp_mux_controls),
SND_SOC_DAPM_OUTPUT("AUXOUT"),
SND_SOC_DAPM_OUTPUT("HPL"),
SND_SOC_DAPM_OUTPUT("HPR"),
SND_SOC_DAPM_OUTPUT("SPKOUT"),
SND_SOC_DAPM_OUTPUT("SPKOUTN"),
SND_SOC_DAPM_INPUT("LINEINL"),
SND_SOC_DAPM_INPUT("LINEINR"),
SND_SOC_DAPM_INPUT("PHONEP"),
SND_SOC_DAPM_INPUT("PHONEN"),
SND_SOC_DAPM_INPUT("DMICDAT"),
SND_SOC_DAPM_INPUT("MIC1"),
SND_SOC_DAPM_INPUT("MIC2"),
SND_SOC_DAPM_VMID("Vmid"),
};
static const struct snd_soc_dapm_route alc5632_dapm_routes[] = {
/* Playback streams */
{"Left DAC", NULL, "AIFRXL"},
{"Right DAC", NULL, "AIFRXR"},
/* virtual mixer - mixes left & right channels */
{"I2S Mix", NULL, "Left DAC"},
{"I2S Mix", NULL, "Right DAC"},
{"Line Mix", NULL, "Right LineIn"},
{"Line Mix", NULL, "Left LineIn"},
{"Phone Mix", NULL, "Phone"},
{"Phone Mix", NULL, "Phone ADMix"},
{"AUXOUT", NULL, "Aux Out"},
/* DAC */
{"DAC Right Channel", NULL, "I2S Mix"},
{"DAC Left Channel", NULL, "I2S Mix"},
/* HP mixer */
{"HPL Mix", "ADC2HP_L Playback Switch", "Left Capture Mix"},
{"HPL Mix", NULL, "HP Mix"},
{"HPR Mix", "ADC2HP_R Playback Switch", "Right Capture Mix"},
{"HPR Mix", NULL, "HP Mix"},
{"HP Mix", "LI2HP Playback Switch", "Line Mix"},
{"HP Mix", "PHONE2HP Playback Switch", "Phone Mix"},
{"HP Mix", "MIC12HP Playback Switch", "MIC1 PGA"},
{"HP Mix", "MIC22HP Playback Switch", "MIC2 PGA"},
{"HP Mix", "VOICE2HP Playback Switch", "Voice Mix"},
{"HPR Mix", "DACR2HP Playback Switch", "DAC Right Channel"},
{"HPL Mix", "DACL2HP Playback Switch", "DAC Left Channel"},
{"HPOut Mix", NULL, "HP Mix"},
{"HPOut Mix", NULL, "HPR Mix"},
{"HPOut Mix", NULL, "HPL Mix"},
/* speaker mixer */
{"Speaker Mix", "LI2SPK Playback Switch", "Line Mix"},
{"Speaker Mix", "PHONE2SPK Playback Switch", "Phone Mix"},
{"Speaker Mix", "MIC12SPK Playback Switch", "MIC1 PGA"},
{"Speaker Mix", "MIC22SPK Playback Switch", "MIC2 PGA"},
{"Speaker Mix", "DAC2SPK Playback Switch", "DAC Left Channel"},
{"Speaker Mix", "VOICE2SPK Playback Switch", "Voice Mix"},
/* mono mixer */
{"Mono Mix", "ADC2MONO_L Playback Switch", "Left Capture Mix"},
{"Mono Mix", "ADC2MONO_R Playback Switch", "Right Capture Mix"},
{"Mono Mix", "LI2MONO Playback Switch", "Line Mix"},
{"Mono Mix", "MIC12MONO Playback Switch", "MIC1 PGA"},
{"Mono Mix", "MIC22MONO Playback Switch", "MIC2 PGA"},
{"Mono Mix", "DAC2MONO Playback Switch", "DAC Left Channel"},
{"Mono Mix", "VOICE2MONO Playback Switch", "Voice Mix"},
/* Left record mixer */
{"Left Capture Mix", "LIL2REC Capture Switch", "LINEINL"},
{"Left Capture Mix", "PH2REC_L Capture Switch", "PHONEN"},
{"Left Capture Mix", "MIC12REC_L Capture Switch", "MIC1 Pre Amp"},
{"Left Capture Mix", "MIC22REC_L Capture Switch", "MIC2 Pre Amp"},
{"Left Capture Mix", "HPL2REC Capture Switch", "HPL Mix"},
{"Left Capture Mix", "SPK2REC_L Capture Switch", "Speaker Mix"},
{"Left Capture Mix", "MONO2REC_L Capture Switch", "Mono Mix"},
/*Right record mixer */
{"Right Capture Mix", "LIR2REC Capture Switch", "LINEINR"},
{"Right Capture Mix", "PH2REC_R Capture Switch", "PHONEP"},
{"Right Capture Mix", "MIC12REC_R Capture Switch", "MIC1 Pre Amp"},
{"Right Capture Mix", "MIC22REC_R Capture Switch", "MIC2 Pre Amp"},
{"Right Capture Mix", "HPR2REC Capture Switch", "HPR Mix"},
{"Right Capture Mix", "SPK2REC_R Capture Switch", "Speaker Mix"},
{"Right Capture Mix", "MONO2REC_R Capture Switch", "Mono Mix"},
/* headphone left mux */
{"Left Headphone Mux", "HP Left Mix", "HPL Mix"},
{"Left Headphone Mux", "Vmid", "Vmid"},
/* headphone right mux */
{"Right Headphone Mux", "HP Right Mix", "HPR Mix"},
{"Right Headphone Mux", "Vmid", "Vmid"},
/* speaker out mux */
{"SpeakerOut Mux", "Vmid", "Vmid"},
{"SpeakerOut Mux", "HPOut Mix", "HPOut Mix"},
{"SpeakerOut Mux", "Speaker Mix", "Speaker Mix"},
{"SpeakerOut Mux", "Mono Mix", "Mono Mix"},
/* Mono/Aux Out mux */
{"AuxOut Mux", "Vmid", "Vmid"},
{"AuxOut Mux", "HPOut Mix", "HPOut Mix"},
{"AuxOut Mux", "Speaker Mix", "Speaker Mix"},
{"AuxOut Mux", "Mono Mix", "Mono Mix"},
/* output pga */
{"HPL", NULL, "Left Headphone"},
{"Left Headphone", NULL, "Left Headphone Mux"},
{"HPR", NULL, "Right Headphone"},
{"Right Headphone", NULL, "Right Headphone Mux"},
{"Aux Out", NULL, "AuxOut Mux"},
/* input pga */
{"Left LineIn", NULL, "LINEINL"},
{"Right LineIn", NULL, "LINEINR"},
{"Phone", NULL, "PHONEP"},
{"MIC1 Pre Amp", NULL, "MIC1"},
{"MIC2 Pre Amp", NULL, "MIC2"},
{"MIC1 PGA", NULL, "MIC1 Pre Amp"},
{"MIC2 PGA", NULL, "MIC2 Pre Amp"},
/* left ADC */
{"Left ADC", NULL, "Left Capture Mix"},
{"DMICL Mix", "DMICL2ADC Capture Switch", "DMICDAT"},
{"Left ADC", NULL, "DMICL Mix"},
{"ADCLR", NULL, "Left ADC"},
/* right ADC */
{"Right ADC", NULL, "Right Capture Mix"},
{"DMICR Mix", "DMICR2ADC Capture Switch", "DMICDAT"},
{"Right ADC", NULL, "DMICR Mix"},
{"ADCR Mux", "Stereo ADC", "Right ADC"},
{"ADCR Mux", "Voice ADC", "Right ADC"},
{"ADCLR", NULL, "ADCR Mux"},
{"VAIFTX", NULL, "ADCR Mux"},
/* Digital I2S out */
{"I2SOut Mux", "ADC LR", "ADCLR"},
{"I2SOut Mux", "Voice Stereo Digital", "VAIFRX"},
{"AIFTXL", NULL, "I2SOut Mux"},
{"AIFTXR", NULL, "I2SOut Mux"},
/* Voice Mix */
{"Voice DAC", NULL, "VAIFRX"},
{"Voice Mix", NULL, "Voice DAC"},
/* Speaker Output */
{"SpeakerOut N Mux", "RN/-R", "Left Speaker"},
{"SpeakerOut N Mux", "RP/+R", "Left Speaker"},
{"SpeakerOut N Mux", "LN/-R", "Left Speaker"},
{"SpeakerOut N Mux", "Mute", "Vmid"},
{"SpeakerOut N Mux", "RN/-R", "Right Speaker"},
{"SpeakerOut N Mux", "RP/+R", "Right Speaker"},
{"SpeakerOut N Mux", "LN/-R", "Right Speaker"},
{"SpeakerOut N Mux", "Mute", "Vmid"},
{"AB Amp", NULL, "SpeakerOut Mux"},
{"D Amp", NULL, "SpeakerOut Mux"},
{"AB-D Amp Mux", "AB Amp", "AB Amp"},
{"AB-D Amp Mux", "D Amp", "D Amp"},
{"Left Speaker", NULL, "AB-D Amp Mux"},
{"Right Speaker", NULL, "AB-D Amp Mux"},
{"SPKOUT", NULL, "Left Speaker"},
{"SPKOUT", NULL, "Right Speaker"},
{"SPKOUTN", NULL, "SpeakerOut N Mux"},
};
/* PLL divisors */
struct _pll_div {
u32 pll_in;
u32 pll_out;
u16 regvalue;
};
/* Note : pll code from original alc5632 driver. Not sure of how good it is */
/* usefull only for master mode */
static const struct _pll_div codec_master_pll_div[] = {
{ 2048000, 8192000, 0x0ea0},
{ 3686400, 8192000, 0x4e27},
{ 12000000, 8192000, 0x456b},
{ 13000000, 8192000, 0x495f},
{ 13100000, 8192000, 0x0320},
{ 2048000, 11289600, 0xf637},
{ 3686400, 11289600, 0x2f22},
{ 12000000, 11289600, 0x3e2f},
{ 13000000, 11289600, 0x4d5b},
{ 13100000, 11289600, 0x363b},
{ 2048000, 16384000, 0x1ea0},
{ 3686400, 16384000, 0x9e27},
{ 12000000, 16384000, 0x452b},
{ 13000000, 16384000, 0x542f},
{ 13100000, 16384000, 0x03a0},
{ 2048000, 16934400, 0xe625},
{ 3686400, 16934400, 0x9126},
{ 12000000, 16934400, 0x4d2c},
{ 13000000, 16934400, 0x742f},
{ 13100000, 16934400, 0x3c27},
{ 2048000, 22579200, 0x2aa0},
{ 3686400, 22579200, 0x2f20},
{ 12000000, 22579200, 0x7e2f},
{ 13000000, 22579200, 0x742f},
{ 13100000, 22579200, 0x3c27},
{ 2048000, 24576000, 0x2ea0},
{ 3686400, 24576000, 0xee27},
{ 12000000, 24576000, 0x2915},
{ 13000000, 24576000, 0x772e},
{ 13100000, 24576000, 0x0d20},
};
/* FOUT = MCLK*(N+2)/((M+2)*(K+2))
N: bit 15:8 (div 2 .. div 257)
K: bit 6:4 typical 2
M: bit 3:0 (div 2 .. div 17)
same as for 5623 - thanks!
*/
static const struct _pll_div codec_slave_pll_div[] = {
{ 1024000, 16384000, 0x3ea0},
{ 1411200, 22579200, 0x3ea0},
{ 1536000, 24576000, 0x3ea0},
{ 2048000, 16384000, 0x1ea0},
{ 2822400, 22579200, 0x1ea0},
{ 3072000, 24576000, 0x1ea0},
};
static int alc5632_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
int i;
struct snd_soc_codec *codec = codec_dai->codec;
int gbl_clk = 0, pll_div = 0;
u16 reg;
if (pll_id < ALC5632_PLL_FR_MCLK || pll_id > ALC5632_PLL_FR_VBCLK)
return -EINVAL;
/* Disable PLL power */
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL1,
0);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL2,
0);
/* pll is not used in slave mode */
reg = snd_soc_read(codec, ALC5632_DAI_CONTROL);
if (reg & ALC5632_DAI_SDP_SLAVE_MODE)
return 0;
if (!freq_in || !freq_out)
return 0;
switch (pll_id) {
case ALC5632_PLL_FR_MCLK:
for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++) {
if (codec_master_pll_div[i].pll_in == freq_in
&& codec_master_pll_div[i].pll_out == freq_out) {
/* PLL source from MCLK */
pll_div = codec_master_pll_div[i].regvalue;
break;
}
}
break;
case ALC5632_PLL_FR_BCLK:
for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
if (codec_slave_pll_div[i].pll_in == freq_in
&& codec_slave_pll_div[i].pll_out == freq_out) {
/* PLL source from Bitclk */
gbl_clk = ALC5632_PLL_FR_BCLK;
pll_div = codec_slave_pll_div[i].regvalue;
break;
}
}
break;
case ALC5632_PLL_FR_VBCLK:
for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
if (codec_slave_pll_div[i].pll_in == freq_in
&& codec_slave_pll_div[i].pll_out == freq_out) {
/* PLL source from voice clock */
gbl_clk = ALC5632_PLL_FR_VBCLK;
pll_div = codec_slave_pll_div[i].regvalue;
break;
}
}
break;
default:
return -EINVAL;
}
if (!pll_div)
return -EINVAL;
/* choose MCLK/BCLK/VBCLK */
snd_soc_write(codec, ALC5632_GPCR2, gbl_clk);
/* choose PLL1 clock rate */
snd_soc_write(codec, ALC5632_PLL1_CTRL, pll_div);
/* enable PLL1 */
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL1,
ALC5632_PWR_ADD2_PLL1);
/* enable PLL2 */
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_ADD2_PLL2,
ALC5632_PWR_ADD2_PLL2);
/* use PLL1 as main SYSCLK */
snd_soc_update_bits(codec, ALC5632_GPCR1,
ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1,
ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1);
return 0;
}
struct _coeff_div {
u16 fs;
u16 regvalue;
};
/* codec hifi mclk (after PLL) clock divider coefficients */
/* values inspired from column BCLK=32Fs of Appendix A table */
static const struct _coeff_div coeff_div[] = {
{512*1, 0x3075},
};
static int get_coeff(struct snd_soc_codec *codec, int rate)
{
struct alc5632_priv *alc5632 = snd_soc_codec_get_drvdata(codec);
int i;
for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
if (coeff_div[i].fs * rate == alc5632->sysclk)
return i;
}
return -EINVAL;
}
/*
* Clock after PLL and dividers
*/
static int alc5632_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct alc5632_priv *alc5632 = snd_soc_codec_get_drvdata(codec);
switch (freq) {
case 4096000:
case 8192000:
case 11289600:
case 12288000:
case 16384000:
case 16934400:
case 18432000:
case 22579200:
case 24576000:
alc5632->sysclk = freq;
return 0;
}
return -EINVAL;
}
static int alc5632_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
u16 iface = 0;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
iface = ALC5632_DAI_SDP_MASTER_MODE;
break;
case SND_SOC_DAIFMT_CBS_CFS:
iface = ALC5632_DAI_SDP_SLAVE_MODE;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
iface |= ALC5632_DAI_I2S_DF_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
iface |= ALC5632_DAI_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
iface |= ALC5632_DAI_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
iface |= ALC5632_DAI_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
iface |= ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL;
break;
case SND_SOC_DAIFMT_IB_NF:
iface |= ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
default:
return -EINVAL;
}
return snd_soc_write(codec, ALC5632_DAI_CONTROL, iface);
}
static int alc5632_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
int coeff, rate;
u16 iface;
iface = snd_soc_read(codec, ALC5632_DAI_CONTROL);
iface &= ~ALC5632_DAI_I2S_DL_MASK;
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
iface |= ALC5632_DAI_I2S_DL_16;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
iface |= ALC5632_DAI_I2S_DL_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
iface |= ALC5632_DAI_I2S_DL_24;
break;
default:
return -EINVAL;
}
/* set iface & srate */
snd_soc_write(codec, ALC5632_DAI_CONTROL, iface);
rate = params_rate(params);
coeff = get_coeff(codec, rate);
if (coeff < 0)
return -EINVAL;
coeff = coeff_div[coeff].regvalue;
snd_soc_write(codec, ALC5632_DAC_CLK_CTRL1, coeff);
return 0;
}
static int alc5632_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
u16 hp_mute = ALC5632_MISC_HP_DEPOP_MUTE_L
|ALC5632_MISC_HP_DEPOP_MUTE_R;
u16 mute_reg = snd_soc_read(codec, ALC5632_MISC_CTRL) & ~hp_mute;
if (mute)
mute_reg |= hp_mute;
return snd_soc_write(codec, ALC5632_MISC_CTRL, mute_reg);
}
#define ALC5632_ADD2_POWER_EN (ALC5632_PWR_ADD2_VREF)
#define ALC5632_ADD3_POWER_EN (ALC5632_PWR_ADD3_MIC1_BOOST_AD)
#define ALC5632_ADD1_POWER_EN \
(ALC5632_PWR_ADD1_DAC_REF \
| ALC5632_PWR_ADD1_SOFTGEN_EN \
| ALC5632_PWR_ADD1_HP_OUT_AMP \
| ALC5632_PWR_ADD1_HP_OUT_ENH_AMP \
| ALC5632_PWR_ADD1_MAIN_BIAS)
static void enable_power_depop(struct snd_soc_codec *codec)
{
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD1,
ALC5632_PWR_ADD1_SOFTGEN_EN,
ALC5632_PWR_ADD1_SOFTGEN_EN);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD3,
ALC5632_ADD3_POWER_EN,
ALC5632_ADD3_POWER_EN);
snd_soc_update_bits(codec, ALC5632_MISC_CTRL,
ALC5632_MISC_HP_DEPOP_MODE2_EN,
ALC5632_MISC_HP_DEPOP_MODE2_EN);
/* "normal" mode: 0 @ 26 */
/* set all PR0-7 mixers to 0 */
snd_soc_update_bits(codec, ALC5632_PWR_DOWN_CTRL_STATUS,
ALC5632_PWR_DOWN_CTRL_STATUS_MASK,
0);
msleep(500);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_ADD2_POWER_EN,
ALC5632_ADD2_POWER_EN);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD1,
ALC5632_ADD1_POWER_EN,
ALC5632_ADD1_POWER_EN);
/* disable HP Depop2 */
snd_soc_update_bits(codec, ALC5632_MISC_CTRL,
ALC5632_MISC_HP_DEPOP_MODE2_EN,
0);
}
static int alc5632_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
enable_power_depop(codec);
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
/* everything off except vref/vmid, */
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD1,
ALC5632_PWR_MANAG_ADD1_MASK,
ALC5632_PWR_ADD1_MAIN_BIAS);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_MANAG_ADD2_MASK,
ALC5632_PWR_ADD2_VREF);
/* "normal" mode: 0 @ 26 */
snd_soc_update_bits(codec, ALC5632_PWR_DOWN_CTRL_STATUS,
ALC5632_PWR_DOWN_CTRL_STATUS_MASK,
0xffff ^ (ALC5632_PWR_VREF_PR3
| ALC5632_PWR_VREF_PR2));
break;
case SND_SOC_BIAS_OFF:
/* everything off, dac mute, inactive */
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD2,
ALC5632_PWR_MANAG_ADD2_MASK, 0);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD3,
ALC5632_PWR_MANAG_ADD3_MASK, 0);
snd_soc_update_bits(codec, ALC5632_PWR_MANAG_ADD1,
ALC5632_PWR_MANAG_ADD1_MASK, 0);
break;
}
codec->dapm.bias_level = level;
return 0;
}
#define ALC5632_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \
| SNDRV_PCM_FMTBIT_S24_LE \
| SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops alc5632_dai_ops = {
.hw_params = alc5632_pcm_hw_params,
.digital_mute = alc5632_mute,
.set_fmt = alc5632_set_dai_fmt,
.set_sysclk = alc5632_set_dai_sysclk,
.set_pll = alc5632_set_dai_pll,
};
static struct snd_soc_dai_driver alc5632_dai = {
.name = "alc5632-hifi",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ALC5632_FORMATS,},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 48000,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = ALC5632_FORMATS,},
.ops = &alc5632_dai_ops,
.symmetric_rates = 1,
};
#ifdef CONFIG_PM
static int alc5632_suspend(struct snd_soc_codec *codec)
{
alc5632_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int alc5632_resume(struct snd_soc_codec *codec)
{
struct alc5632_priv *alc5632 = snd_soc_codec_get_drvdata(codec);
regcache_sync(alc5632->regmap);
alc5632_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
return 0;
}
#else
#define alc5632_suspend NULL
#define alc5632_resume NULL
#endif
static int alc5632_probe(struct snd_soc_codec *codec)
{
struct alc5632_priv *alc5632 = snd_soc_codec_get_drvdata(codec);
int ret;
codec->control_data = alc5632->regmap;
ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
if (ret != 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
return ret;
}
/* power on device */
alc5632_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
switch (alc5632->id) {
case 0x5c:
snd_soc_add_codec_controls(codec, alc5632_vol_snd_controls,
ARRAY_SIZE(alc5632_vol_snd_controls));
break;
default:
return -EINVAL;
}
return ret;
}
/* power down chip */
static int alc5632_remove(struct snd_soc_codec *codec)
{
alc5632_set_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static struct snd_soc_codec_driver soc_codec_device_alc5632 = {
.probe = alc5632_probe,
.remove = alc5632_remove,
.suspend = alc5632_suspend,
.resume = alc5632_resume,
.set_bias_level = alc5632_set_bias_level,
.controls = alc5632_snd_controls,
.num_controls = ARRAY_SIZE(alc5632_snd_controls),
.dapm_widgets = alc5632_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(alc5632_dapm_widgets),
.dapm_routes = alc5632_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(alc5632_dapm_routes),
};
static struct regmap_config alc5632_regmap = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ALC5632_MAX_REGISTER,
.reg_defaults = alc5632_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(alc5632_reg_defaults),
.volatile_reg = alc5632_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
/*
* alc5632 2 wire address is determined by A1 pin
* state during powerup.
* low = 0x1a
* high = 0x1b
*/
static int alc5632_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct alc5632_priv *alc5632;
int ret, ret1, ret2;
unsigned int vid1, vid2;
alc5632 = devm_kzalloc(&client->dev,
sizeof(struct alc5632_priv), GFP_KERNEL);
if (alc5632 == NULL)
return -ENOMEM;
i2c_set_clientdata(client, alc5632);
alc5632->regmap = devm_regmap_init_i2c(client, &alc5632_regmap);
if (IS_ERR(alc5632->regmap)) {
ret = PTR_ERR(alc5632->regmap);
dev_err(&client->dev, "regmap_init() failed: %d\n", ret);
return ret;
}
ret1 = regmap_read(alc5632->regmap, ALC5632_VENDOR_ID1, &vid1);
ret2 = regmap_read(alc5632->regmap, ALC5632_VENDOR_ID2, &vid2);
if (ret1 != 0 || ret2 != 0) {
dev_err(&client->dev,
"Failed to read chip ID: ret1=%d, ret2=%d\n", ret1, ret2);
return -EIO;
}
vid2 >>= 8;
if ((vid1 != 0x10EC) || (vid2 != id->driver_data)) {
dev_err(&client->dev,
"Device is not a ALC5632: VID1=0x%x, VID2=0x%x\n", vid1, vid2);
return -EINVAL;
}
ret = alc5632_reset(alc5632->regmap);
if (ret < 0) {
dev_err(&client->dev, "Failed to issue reset\n");
return ret;
}
alc5632->id = vid2;
switch (alc5632->id) {
case 0x5c:
alc5632_dai.name = "alc5632-hifi";
break;
default:
return -EINVAL;
}
ret = snd_soc_register_codec(&client->dev,
&soc_codec_device_alc5632, &alc5632_dai, 1);
if (ret < 0) {
dev_err(&client->dev, "Failed to register codec: %d\n", ret);
return ret;
}
return ret;
}
static int alc5632_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id alc5632_i2c_table[] = {
{"alc5632", 0x5c},
{}
};
MODULE_DEVICE_TABLE(i2c, alc5632_i2c_table);
/* i2c codec control layer */
static struct i2c_driver alc5632_i2c_driver = {
.driver = {
.name = "alc5632",
.owner = THIS_MODULE,
},
.probe = alc5632_i2c_probe,
.remove = alc5632_i2c_remove,
.id_table = alc5632_i2c_table,
};
module_i2c_driver(alc5632_i2c_driver);
MODULE_DESCRIPTION("ASoC ALC5632 driver");
MODULE_AUTHOR("Leon Romanovsky <leon@leon.nu>");
MODULE_LICENSE("GPL");
| gpl-2.0 |
eoghan2t9/Wildfire_S_3.0_Kernel | drivers/gpu/drm/nouveau/nouveau_i2c.c | 2657 | 7649 | /*
* Copyright 2009 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_i2c.h"
#include "nouveau_hw.h"
static void
nv04_i2c_setscl(void *data, int state)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
uint8_t val;
val = (NVReadVgaCrtc(dev, 0, i2c->wr) & 0xd0) | (state ? 0x20 : 0);
NVWriteVgaCrtc(dev, 0, i2c->wr, val | 0x01);
}
static void
nv04_i2c_setsda(void *data, int state)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
uint8_t val;
val = (NVReadVgaCrtc(dev, 0, i2c->wr) & 0xe0) | (state ? 0x10 : 0);
NVWriteVgaCrtc(dev, 0, i2c->wr, val | 0x01);
}
static int
nv04_i2c_getscl(void *data)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
return !!(NVReadVgaCrtc(dev, 0, i2c->rd) & 4);
}
static int
nv04_i2c_getsda(void *data)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
return !!(NVReadVgaCrtc(dev, 0, i2c->rd) & 8);
}
static void
nv4e_i2c_setscl(void *data, int state)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
uint8_t val;
val = (nv_rd32(dev, i2c->wr) & 0xd0) | (state ? 0x20 : 0);
nv_wr32(dev, i2c->wr, val | 0x01);
}
static void
nv4e_i2c_setsda(void *data, int state)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
uint8_t val;
val = (nv_rd32(dev, i2c->wr) & 0xe0) | (state ? 0x10 : 0);
nv_wr32(dev, i2c->wr, val | 0x01);
}
static int
nv4e_i2c_getscl(void *data)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
return !!((nv_rd32(dev, i2c->rd) >> 16) & 4);
}
static int
nv4e_i2c_getsda(void *data)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
return !!((nv_rd32(dev, i2c->rd) >> 16) & 8);
}
static int
nv50_i2c_getscl(void *data)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
return !!(nv_rd32(dev, i2c->rd) & 1);
}
static int
nv50_i2c_getsda(void *data)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
return !!(nv_rd32(dev, i2c->rd) & 2);
}
static void
nv50_i2c_setscl(void *data, int state)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
nv_wr32(dev, i2c->wr, 4 | (i2c->data ? 2 : 0) | (state ? 1 : 0));
}
static void
nv50_i2c_setsda(void *data, int state)
{
struct nouveau_i2c_chan *i2c = data;
struct drm_device *dev = i2c->dev;
nv_wr32(dev, i2c->wr,
(nv_rd32(dev, i2c->rd) & 1) | 4 | (state ? 2 : 0));
i2c->data = state;
}
static const uint32_t nv50_i2c_port[] = {
0x00e138, 0x00e150, 0x00e168, 0x00e180,
0x00e254, 0x00e274, 0x00e764, 0x00e780,
0x00e79c, 0x00e7b8
};
#define NV50_I2C_PORTS ARRAY_SIZE(nv50_i2c_port)
int
nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_i2c_chan *i2c;
int ret;
if (entry->chan)
return -EEXIST;
if (dev_priv->card_type >= NV_50 && entry->read >= NV50_I2C_PORTS) {
NV_ERROR(dev, "unknown i2c port %d\n", entry->read);
return -EINVAL;
}
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
if (i2c == NULL)
return -ENOMEM;
switch (entry->port_type) {
case 0:
i2c->bit.setsda = nv04_i2c_setsda;
i2c->bit.setscl = nv04_i2c_setscl;
i2c->bit.getsda = nv04_i2c_getsda;
i2c->bit.getscl = nv04_i2c_getscl;
i2c->rd = entry->read;
i2c->wr = entry->write;
break;
case 4:
i2c->bit.setsda = nv4e_i2c_setsda;
i2c->bit.setscl = nv4e_i2c_setscl;
i2c->bit.getsda = nv4e_i2c_getsda;
i2c->bit.getscl = nv4e_i2c_getscl;
i2c->rd = 0x600800 + entry->read;
i2c->wr = 0x600800 + entry->write;
break;
case 5:
i2c->bit.setsda = nv50_i2c_setsda;
i2c->bit.setscl = nv50_i2c_setscl;
i2c->bit.getsda = nv50_i2c_getsda;
i2c->bit.getscl = nv50_i2c_getscl;
i2c->rd = nv50_i2c_port[entry->read];
i2c->wr = i2c->rd;
break;
case 6:
i2c->rd = entry->read;
i2c->wr = entry->write;
break;
default:
NV_ERROR(dev, "DCB I2C port type %d unknown\n",
entry->port_type);
kfree(i2c);
return -EINVAL;
}
snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
"nouveau-%s-%d", pci_name(dev->pdev), index);
i2c->adapter.owner = THIS_MODULE;
i2c->adapter.dev.parent = &dev->pdev->dev;
i2c->dev = dev;
i2c_set_adapdata(&i2c->adapter, i2c);
if (entry->port_type < 6) {
i2c->adapter.algo_data = &i2c->bit;
i2c->bit.udelay = 40;
i2c->bit.timeout = usecs_to_jiffies(5000);
i2c->bit.data = i2c;
ret = i2c_bit_add_bus(&i2c->adapter);
} else {
i2c->adapter.algo = &nouveau_dp_i2c_algo;
ret = i2c_add_adapter(&i2c->adapter);
}
if (ret) {
NV_ERROR(dev, "Failed to register i2c %d\n", index);
kfree(i2c);
return ret;
}
entry->chan = i2c;
return 0;
}
void
nouveau_i2c_fini(struct drm_device *dev, struct dcb_i2c_entry *entry)
{
if (!entry->chan)
return;
i2c_del_adapter(&entry->chan->adapter);
kfree(entry->chan);
entry->chan = NULL;
}
struct nouveau_i2c_chan *
nouveau_i2c_find(struct drm_device *dev, int index)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct dcb_i2c_entry *i2c = &dev_priv->vbios.dcb.i2c[index];
if (index >= DCB_MAX_NUM_I2C_ENTRIES)
return NULL;
if (dev_priv->card_type >= NV_50 && (i2c->entry & 0x00000100)) {
uint32_t reg = 0xe500, val;
if (i2c->port_type == 6) {
reg += i2c->read * 0x50;
val = 0x2002;
} else {
reg += ((i2c->entry & 0x1e00) >> 9) * 0x50;
val = 0xe001;
}
nv_wr32(dev, reg, (nv_rd32(dev, reg) & ~0xf003) | val);
}
if (!i2c->chan && nouveau_i2c_init(dev, i2c, index))
return NULL;
return i2c->chan;
}
bool
nouveau_probe_i2c_addr(struct nouveau_i2c_chan *i2c, int addr)
{
uint8_t buf[] = { 0 };
struct i2c_msg msgs[] = {
{
.addr = addr,
.flags = 0,
.len = 1,
.buf = buf,
},
{
.addr = addr,
.flags = I2C_M_RD,
.len = 1,
.buf = buf,
}
};
return i2c_transfer(&i2c->adapter, msgs, 2) == 2;
}
int
nouveau_i2c_identify(struct drm_device *dev, const char *what,
struct i2c_board_info *info,
bool (*match)(struct nouveau_i2c_chan *,
struct i2c_board_info *),
int index)
{
struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, index);
int i;
NV_DEBUG(dev, "Probing %ss on I2C bus: %d\n", what, index);
for (i = 0; info[i].addr; i++) {
if (nouveau_probe_i2c_addr(i2c, info[i].addr) &&
(!match || match(i2c, &info[i]))) {
NV_INFO(dev, "Detected %s: %s\n", what, info[i].type);
return i;
}
}
NV_DEBUG(dev, "No devices found.\n");
return -ENODEV;
}
| gpl-2.0 |
Krabappel2548/kernel_msm8x60 | arch/arm/mm/fault-armv.c | 2913 | 6906 | /*
* linux/arch/arm/mm/fault-armv.c
*
* Copyright (C) 1995 Linus Torvalds
* Modifications for ARM processor (c) 1995-2002 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bitops.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/gfp.h>
#include <asm/bugs.h>
#include <asm/cacheflush.h>
#include <asm/cachetype.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include "mm.h"
static pteval_t shared_pte_mask = L_PTE_MT_BUFFERABLE;
#if __LINUX_ARM_ARCH__ < 6
/*
* We take the easy way out of this problem - we make the
* PTE uncacheable. However, we leave the write buffer on.
*
* Note that the pte lock held when calling update_mmu_cache must also
* guard the pte (somewhere else in the same mm) that we modify here.
* Therefore those configurations which might call adjust_pte (those
* without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
*/
static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
unsigned long pfn, pte_t *ptep)
{
pte_t entry = *ptep;
int ret;
/*
* If this page is present, it's actually being shared.
*/
ret = pte_present(entry);
/*
* If this page isn't present, or is already setup to
* fault (ie, is old), we can safely ignore any issues.
*/
if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
flush_cache_page(vma, address, pfn);
outer_flush_range((pfn << PAGE_SHIFT),
(pfn << PAGE_SHIFT) + PAGE_SIZE);
pte_val(entry) &= ~L_PTE_MT_MASK;
pte_val(entry) |= shared_pte_mask;
set_pte_at(vma->vm_mm, address, ptep, entry);
flush_tlb_page(vma, address);
}
return ret;
}
#if USE_SPLIT_PTLOCKS
/*
* If we are using split PTE locks, then we need to take the page
* lock here. Otherwise we are using shared mm->page_table_lock
* which is already locked, thus cannot take it.
*/
static inline void do_pte_lock(spinlock_t *ptl)
{
/*
* Use nested version here to indicate that we are already
* holding one similar spinlock.
*/
spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
}
static inline void do_pte_unlock(spinlock_t *ptl)
{
spin_unlock(ptl);
}
#else /* !USE_SPLIT_PTLOCKS */
static inline void do_pte_lock(spinlock_t *ptl) {}
static inline void do_pte_unlock(spinlock_t *ptl) {}
#endif /* USE_SPLIT_PTLOCKS */
static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
unsigned long pfn)
{
spinlock_t *ptl;
pgd_t *pgd;
pud_t *pud;
pmd_t *pmd;
pte_t *pte;
int ret;
pgd = pgd_offset(vma->vm_mm, address);
if (pgd_none_or_clear_bad(pgd))
return 0;
pud = pud_offset(pgd, address);
if (pud_none_or_clear_bad(pud))
return 0;
pmd = pmd_offset(pud, address);
if (pmd_none_or_clear_bad(pmd))
return 0;
/*
* This is called while another page table is mapped, so we
* must use the nested version. This also means we need to
* open-code the spin-locking.
*/
ptl = pte_lockptr(vma->vm_mm, pmd);
pte = pte_offset_map(pmd, address);
do_pte_lock(ptl);
ret = do_adjust_pte(vma, address, pfn, pte);
do_pte_unlock(ptl);
pte_unmap(pte);
return ret;
}
static void
make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep, unsigned long pfn)
{
struct mm_struct *mm = vma->vm_mm;
struct vm_area_struct *mpnt;
struct prio_tree_iter iter;
unsigned long offset;
pgoff_t pgoff;
int aliases = 0;
pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
/*
* If we have any shared mappings that are in the same mm
* space, then we need to handle them specially to maintain
* cache coherency.
*/
flush_dcache_mmap_lock(mapping);
vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
/*
* If this VMA is not in our MM, we can ignore it.
* Note that we intentionally mask out the VMA
* that we are fixing up.
*/
if (mpnt->vm_mm != mm || mpnt == vma)
continue;
if (!(mpnt->vm_flags & VM_MAYSHARE))
continue;
offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
}
flush_dcache_mmap_unlock(mapping);
if (aliases)
do_adjust_pte(vma, addr, pfn, ptep);
}
/*
* Take care of architecture specific things when placing a new PTE into
* a page table, or changing an existing PTE. Basically, there are two
* things that we need to take care of:
*
* 1. If PG_dcache_clean is not set for the page, we need to ensure
* that any cache entries for the kernels virtual memory
* range are written back to the page.
* 2. If we have multiple shared mappings of the same space in
* an object, we need to deal with the cache aliasing issues.
*
* Note that the pte lock will be held.
*/
void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
pte_t *ptep)
{
unsigned long pfn = pte_pfn(*ptep);
struct address_space *mapping;
struct page *page;
if (!pfn_valid(pfn))
return;
/*
* The zero page is never written to, so never has any dirty
* cache lines, and therefore never needs to be flushed.
*/
page = pfn_to_page(pfn);
if (page == ZERO_PAGE(0))
return;
mapping = page_mapping(page);
if (!test_and_set_bit(PG_dcache_clean, &page->flags))
__flush_dcache_page(mapping, page);
if (mapping) {
if (cache_is_vivt())
make_coherent(mapping, vma, addr, ptep, pfn);
else if (vma->vm_flags & VM_EXEC)
__flush_icache_all();
}
}
#endif /* __LINUX_ARM_ARCH__ < 6 */
/*
* Check whether the write buffer has physical address aliasing
* issues. If it has, we need to avoid them for the case where
* we have several shared mappings of the same object in user
* space.
*/
static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
{
register unsigned long zero = 0, one = 1, val;
local_irq_disable();
mb();
*p1 = one;
mb();
*p2 = zero;
mb();
val = *p1;
mb();
local_irq_enable();
return val != zero;
}
void __init check_writebuffer_bugs(void)
{
struct page *page;
const char *reason;
unsigned long v = 1;
printk(KERN_INFO "CPU: Testing write buffer coherency: ");
page = alloc_page(GFP_KERNEL);
if (page) {
unsigned long *p1, *p2;
pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
p1 = vmap(&page, 1, VM_IOREMAP, prot);
p2 = vmap(&page, 1, VM_IOREMAP, prot);
if (p1 && p2) {
v = check_writebuffer(p1, p2);
reason = "enabling work-around";
} else {
reason = "unable to map memory\n";
}
vunmap(p1);
vunmap(p2);
put_page(page);
} else {
reason = "unable to grab page\n";
}
if (v) {
printk("failed, %s\n", reason);
shared_pte_mask = L_PTE_MT_UNCACHED;
} else {
printk("ok\n");
}
}
| gpl-2.0 |
Electrex/Electroactive-N6 | drivers/gpu/drm/nouveau/nvc0_fbcon.c | 2913 | 7108 | /*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_fbcon.h"
int
nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct nouveau_fbdev *nfbdev = info->par;
struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
struct nouveau_channel *chan = drm->channel;
int ret;
ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11);
if (ret)
return ret;
if (rect->rop != ROP_COPY) {
BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1);
OUT_RING (chan, 1);
}
BEGIN_NVC0(chan, NvSub2D, 0x0588, 1);
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR)
OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
else
OUT_RING (chan, rect->color);
BEGIN_NVC0(chan, NvSub2D, 0x0600, 4);
OUT_RING (chan, rect->dx);
OUT_RING (chan, rect->dy);
OUT_RING (chan, rect->dx + rect->width);
OUT_RING (chan, rect->dy + rect->height);
if (rect->rop != ROP_COPY) {
BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1);
OUT_RING (chan, 3);
}
FIRE_RING(chan);
return 0;
}
int
nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct nouveau_fbdev *nfbdev = info->par;
struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
struct nouveau_channel *chan = drm->channel;
int ret;
ret = RING_SPACE(chan, 12);
if (ret)
return ret;
BEGIN_NVC0(chan, NvSub2D, 0x0110, 1);
OUT_RING (chan, 0);
BEGIN_NVC0(chan, NvSub2D, 0x08b0, 4);
OUT_RING (chan, region->dx);
OUT_RING (chan, region->dy);
OUT_RING (chan, region->width);
OUT_RING (chan, region->height);
BEGIN_NVC0(chan, NvSub2D, 0x08d0, 4);
OUT_RING (chan, 0);
OUT_RING (chan, region->sx);
OUT_RING (chan, 0);
OUT_RING (chan, region->sy);
FIRE_RING(chan);
return 0;
}
int
nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct nouveau_fbdev *nfbdev = info->par;
struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
struct nouveau_channel *chan = drm->channel;
uint32_t width, dwords, *data = (uint32_t *)image->data;
uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
uint32_t *palette = info->pseudo_palette;
int ret;
if (image->depth != 1)
return -ENODEV;
ret = RING_SPACE(chan, 11);
if (ret)
return ret;
width = ALIGN(image->width, 32);
dwords = (width * image->height) >> 5;
BEGIN_NVC0(chan, NvSub2D, 0x0814, 2);
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
OUT_RING (chan, palette[image->bg_color] | mask);
OUT_RING (chan, palette[image->fg_color] | mask);
} else {
OUT_RING (chan, image->bg_color);
OUT_RING (chan, image->fg_color);
}
BEGIN_NVC0(chan, NvSub2D, 0x0838, 2);
OUT_RING (chan, image->width);
OUT_RING (chan, image->height);
BEGIN_NVC0(chan, NvSub2D, 0x0850, 4);
OUT_RING (chan, 0);
OUT_RING (chan, image->dx);
OUT_RING (chan, 0);
OUT_RING (chan, image->dy);
while (dwords) {
int push = dwords > 2047 ? 2047 : dwords;
ret = RING_SPACE(chan, push + 1);
if (ret)
return ret;
dwords -= push;
BEGIN_NIC0(chan, NvSub2D, 0x0860, push);
OUT_RINGp(chan, data, push);
data += push;
}
FIRE_RING(chan);
return 0;
}
int
nvc0_fbcon_accel_init(struct fb_info *info)
{
struct nouveau_fbdev *nfbdev = info->par;
struct drm_device *dev = nfbdev->dev;
struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_channel *chan = drm->channel;
struct nouveau_object *object;
int ret, format;
ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, Nv2D,
0x902d, NULL, 0, &object);
if (ret)
return ret;
switch (info->var.bits_per_pixel) {
case 8:
format = 0xf3;
break;
case 15:
format = 0xf8;
break;
case 16:
format = 0xe8;
break;
case 32:
switch (info->var.transp.length) {
case 0: /* depth 24 */
case 8: /* depth 32, just use 24.. */
format = 0xe6;
break;
case 2: /* depth 30 */
format = 0xd1;
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;
}
ret = RING_SPACE(chan, 60);
if (ret) {
WARN_ON(1);
nouveau_fbcon_gpu_lockup(info);
return ret;
}
BEGIN_NVC0(chan, NvSub2D, 0x0000, 1);
OUT_RING (chan, 0x0000902d);
BEGIN_NVC0(chan, NvSub2D, 0x0290, 1);
OUT_RING (chan, 0);
BEGIN_NVC0(chan, NvSub2D, 0x0888, 1);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1);
OUT_RING (chan, 3);
BEGIN_NVC0(chan, NvSub2D, 0x02a0, 1);
OUT_RING (chan, 0x55);
BEGIN_NVC0(chan, NvSub2D, 0x08c0, 4);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x0580, 2);
OUT_RING (chan, 4);
OUT_RING (chan, format);
BEGIN_NVC0(chan, NvSub2D, 0x02e8, 2);
OUT_RING (chan, 2);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x0804, 1);
OUT_RING (chan, format);
BEGIN_NVC0(chan, NvSub2D, 0x0800, 1);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x0808, 3);
OUT_RING (chan, 0);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x081c, 1);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x0840, 4);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
BEGIN_NVC0(chan, NvSub2D, 0x0200, 10);
OUT_RING (chan, format);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, info->fix.line_length);
OUT_RING (chan, info->var.xres_virtual);
OUT_RING (chan, info->var.yres_virtual);
OUT_RING (chan, upper_32_bits(fb->vma.offset));
OUT_RING (chan, lower_32_bits(fb->vma.offset));
BEGIN_NVC0(chan, NvSub2D, 0x0230, 10);
OUT_RING (chan, format);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, 1);
OUT_RING (chan, 0);
OUT_RING (chan, info->fix.line_length);
OUT_RING (chan, info->var.xres_virtual);
OUT_RING (chan, info->var.yres_virtual);
OUT_RING (chan, upper_32_bits(fb->vma.offset));
OUT_RING (chan, lower_32_bits(fb->vma.offset));
FIRE_RING (chan);
return 0;
}
| gpl-2.0 |
chrisy/linux | net/netfilter/xt_HMARK.c | 2913 | 9364 | /*
* xt_HMARK - Netfilter module to set mark by means of hashing
*
* (C) 2012 by Hans Schillstrom <hans.schillstrom@ericsson.com>
* (C) 2012 by Pablo Neira Ayuso <pablo@netfilter.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/skbuff.h>
#include <linux/icmp.h>
#include <linux/netfilter/x_tables.h>
#include <linux/netfilter/xt_HMARK.h>
#include <net/ip.h>
#if IS_ENABLED(CONFIG_NF_CONNTRACK)
#include <net/netfilter/nf_conntrack.h>
#endif
#if IS_ENABLED(CONFIG_IP6_NF_IPTABLES)
#include <net/ipv6.h>
#include <linux/netfilter_ipv6/ip6_tables.h>
#endif
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Hans Schillstrom <hans.schillstrom@ericsson.com>");
MODULE_DESCRIPTION("Xtables: packet marking using hash calculation");
MODULE_ALIAS("ipt_HMARK");
MODULE_ALIAS("ip6t_HMARK");
struct hmark_tuple {
__be32 src;
__be32 dst;
union hmark_ports uports;
u8 proto;
};
static inline __be32 hmark_addr6_mask(const __be32 *addr32, const __be32 *mask)
{
return (addr32[0] & mask[0]) ^
(addr32[1] & mask[1]) ^
(addr32[2] & mask[2]) ^
(addr32[3] & mask[3]);
}
static inline __be32
hmark_addr_mask(int l3num, const __be32 *addr32, const __be32 *mask)
{
switch (l3num) {
case AF_INET:
return *addr32 & *mask;
case AF_INET6:
return hmark_addr6_mask(addr32, mask);
}
return 0;
}
static inline void hmark_swap_ports(union hmark_ports *uports,
const struct xt_hmark_info *info)
{
union hmark_ports hp;
u16 src, dst;
hp.b32 = (uports->b32 & info->port_mask.b32) | info->port_set.b32;
src = ntohs(hp.b16.src);
dst = ntohs(hp.b16.dst);
if (dst > src)
uports->v32 = (dst << 16) | src;
else
uports->v32 = (src << 16) | dst;
}
static int
hmark_ct_set_htuple(const struct sk_buff *skb, struct hmark_tuple *t,
const struct xt_hmark_info *info)
{
#if IS_ENABLED(CONFIG_NF_CONNTRACK)
enum ip_conntrack_info ctinfo;
struct nf_conn *ct = nf_ct_get(skb, &ctinfo);
struct nf_conntrack_tuple *otuple;
struct nf_conntrack_tuple *rtuple;
if (ct == NULL || nf_ct_is_untracked(ct))
return -1;
otuple = &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple;
rtuple = &ct->tuplehash[IP_CT_DIR_REPLY].tuple;
t->src = hmark_addr_mask(otuple->src.l3num, otuple->src.u3.ip6,
info->src_mask.ip6);
t->dst = hmark_addr_mask(otuple->src.l3num, rtuple->src.u3.ip6,
info->dst_mask.ip6);
if (info->flags & XT_HMARK_FLAG(XT_HMARK_METHOD_L3))
return 0;
t->proto = nf_ct_protonum(ct);
if (t->proto != IPPROTO_ICMP) {
t->uports.b16.src = otuple->src.u.all;
t->uports.b16.dst = rtuple->src.u.all;
hmark_swap_ports(&t->uports, info);
}
return 0;
#else
return -1;
#endif
}
/* This hash function is endian independent, to ensure consistent hashing if
* the cluster is composed of big and little endian systems. */
static inline u32
hmark_hash(struct hmark_tuple *t, const struct xt_hmark_info *info)
{
u32 hash;
u32 src = ntohl(t->src);
u32 dst = ntohl(t->dst);
if (dst < src)
swap(src, dst);
hash = jhash_3words(src, dst, t->uports.v32, info->hashrnd);
hash = hash ^ (t->proto & info->proto_mask);
return (((u64)hash * info->hmodulus) >> 32) + info->hoffset;
}
static void
hmark_set_tuple_ports(const struct sk_buff *skb, unsigned int nhoff,
struct hmark_tuple *t, const struct xt_hmark_info *info)
{
int protoff;
protoff = proto_ports_offset(t->proto);
if (protoff < 0)
return;
nhoff += protoff;
if (skb_copy_bits(skb, nhoff, &t->uports, sizeof(t->uports)) < 0)
return;
hmark_swap_ports(&t->uports, info);
}
#if IS_ENABLED(CONFIG_IP6_NF_IPTABLES)
static int get_inner6_hdr(const struct sk_buff *skb, int *offset)
{
struct icmp6hdr *icmp6h, _ih6;
icmp6h = skb_header_pointer(skb, *offset, sizeof(_ih6), &_ih6);
if (icmp6h == NULL)
return 0;
if (icmp6h->icmp6_type && icmp6h->icmp6_type < 128) {
*offset += sizeof(struct icmp6hdr);
return 1;
}
return 0;
}
static int
hmark_pkt_set_htuple_ipv6(const struct sk_buff *skb, struct hmark_tuple *t,
const struct xt_hmark_info *info)
{
struct ipv6hdr *ip6, _ip6;
int flag = IP6_FH_F_AUTH;
unsigned int nhoff = 0;
u16 fragoff = 0;
int nexthdr;
ip6 = (struct ipv6hdr *) (skb->data + skb_network_offset(skb));
nexthdr = ipv6_find_hdr(skb, &nhoff, -1, &fragoff, &flag);
if (nexthdr < 0)
return 0;
/* No need to check for icmp errors on fragments */
if ((flag & IP6_FH_F_FRAG) || (nexthdr != IPPROTO_ICMPV6))
goto noicmp;
/* Use inner header in case of ICMP errors */
if (get_inner6_hdr(skb, &nhoff)) {
ip6 = skb_header_pointer(skb, nhoff, sizeof(_ip6), &_ip6);
if (ip6 == NULL)
return -1;
/* If AH present, use SPI like in ESP. */
flag = IP6_FH_F_AUTH;
nexthdr = ipv6_find_hdr(skb, &nhoff, -1, &fragoff, &flag);
if (nexthdr < 0)
return -1;
}
noicmp:
t->src = hmark_addr6_mask(ip6->saddr.s6_addr32, info->src_mask.ip6);
t->dst = hmark_addr6_mask(ip6->daddr.s6_addr32, info->dst_mask.ip6);
if (info->flags & XT_HMARK_FLAG(XT_HMARK_METHOD_L3))
return 0;
t->proto = nexthdr;
if (t->proto == IPPROTO_ICMPV6)
return 0;
if (flag & IP6_FH_F_FRAG)
return 0;
hmark_set_tuple_ports(skb, nhoff, t, info);
return 0;
}
static unsigned int
hmark_tg_v6(struct sk_buff *skb, const struct xt_action_param *par)
{
const struct xt_hmark_info *info = par->targinfo;
struct hmark_tuple t;
memset(&t, 0, sizeof(struct hmark_tuple));
if (info->flags & XT_HMARK_FLAG(XT_HMARK_CT)) {
if (hmark_ct_set_htuple(skb, &t, info) < 0)
return XT_CONTINUE;
} else {
if (hmark_pkt_set_htuple_ipv6(skb, &t, info) < 0)
return XT_CONTINUE;
}
skb->mark = hmark_hash(&t, info);
return XT_CONTINUE;
}
#endif
static int get_inner_hdr(const struct sk_buff *skb, int iphsz, int *nhoff)
{
const struct icmphdr *icmph;
struct icmphdr _ih;
/* Not enough header? */
icmph = skb_header_pointer(skb, *nhoff + iphsz, sizeof(_ih), &_ih);
if (icmph == NULL || icmph->type > NR_ICMP_TYPES)
return 0;
/* Error message? */
if (icmph->type != ICMP_DEST_UNREACH &&
icmph->type != ICMP_SOURCE_QUENCH &&
icmph->type != ICMP_TIME_EXCEEDED &&
icmph->type != ICMP_PARAMETERPROB &&
icmph->type != ICMP_REDIRECT)
return 0;
*nhoff += iphsz + sizeof(_ih);
return 1;
}
static int
hmark_pkt_set_htuple_ipv4(const struct sk_buff *skb, struct hmark_tuple *t,
const struct xt_hmark_info *info)
{
struct iphdr *ip, _ip;
int nhoff = skb_network_offset(skb);
ip = (struct iphdr *) (skb->data + nhoff);
if (ip->protocol == IPPROTO_ICMP) {
/* Use inner header in case of ICMP errors */
if (get_inner_hdr(skb, ip->ihl * 4, &nhoff)) {
ip = skb_header_pointer(skb, nhoff, sizeof(_ip), &_ip);
if (ip == NULL)
return -1;
}
}
t->src = ip->saddr & info->src_mask.ip;
t->dst = ip->daddr & info->dst_mask.ip;
if (info->flags & XT_HMARK_FLAG(XT_HMARK_METHOD_L3))
return 0;
t->proto = ip->protocol;
/* ICMP has no ports, skip */
if (t->proto == IPPROTO_ICMP)
return 0;
/* follow-up fragments don't contain ports, skip all fragments */
if (ip->frag_off & htons(IP_MF | IP_OFFSET))
return 0;
hmark_set_tuple_ports(skb, (ip->ihl * 4) + nhoff, t, info);
return 0;
}
static unsigned int
hmark_tg_v4(struct sk_buff *skb, const struct xt_action_param *par)
{
const struct xt_hmark_info *info = par->targinfo;
struct hmark_tuple t;
memset(&t, 0, sizeof(struct hmark_tuple));
if (info->flags & XT_HMARK_FLAG(XT_HMARK_CT)) {
if (hmark_ct_set_htuple(skb, &t, info) < 0)
return XT_CONTINUE;
} else {
if (hmark_pkt_set_htuple_ipv4(skb, &t, info) < 0)
return XT_CONTINUE;
}
skb->mark = hmark_hash(&t, info);
return XT_CONTINUE;
}
static int hmark_tg_check(const struct xt_tgchk_param *par)
{
const struct xt_hmark_info *info = par->targinfo;
if (!info->hmodulus) {
pr_info("xt_HMARK: hash modulus can't be zero\n");
return -EINVAL;
}
if (info->proto_mask &&
(info->flags & XT_HMARK_FLAG(XT_HMARK_METHOD_L3))) {
pr_info("xt_HMARK: proto mask must be zero with L3 mode\n");
return -EINVAL;
}
if (info->flags & XT_HMARK_FLAG(XT_HMARK_SPI_MASK) &&
(info->flags & (XT_HMARK_FLAG(XT_HMARK_SPORT_MASK) |
XT_HMARK_FLAG(XT_HMARK_DPORT_MASK)))) {
pr_info("xt_HMARK: spi-mask and port-mask can't be combined\n");
return -EINVAL;
}
if (info->flags & XT_HMARK_FLAG(XT_HMARK_SPI) &&
(info->flags & (XT_HMARK_FLAG(XT_HMARK_SPORT) |
XT_HMARK_FLAG(XT_HMARK_DPORT)))) {
pr_info("xt_HMARK: spi-set and port-set can't be combined\n");
return -EINVAL;
}
return 0;
}
static struct xt_target hmark_tg_reg[] __read_mostly = {
{
.name = "HMARK",
.family = NFPROTO_IPV4,
.target = hmark_tg_v4,
.targetsize = sizeof(struct xt_hmark_info),
.checkentry = hmark_tg_check,
.me = THIS_MODULE,
},
#if IS_ENABLED(CONFIG_IP6_NF_IPTABLES)
{
.name = "HMARK",
.family = NFPROTO_IPV6,
.target = hmark_tg_v6,
.targetsize = sizeof(struct xt_hmark_info),
.checkentry = hmark_tg_check,
.me = THIS_MODULE,
},
#endif
};
static int __init hmark_tg_init(void)
{
return xt_register_targets(hmark_tg_reg, ARRAY_SIZE(hmark_tg_reg));
}
static void __exit hmark_tg_exit(void)
{
xt_unregister_targets(hmark_tg_reg, ARRAY_SIZE(hmark_tg_reg));
}
module_init(hmark_tg_init);
module_exit(hmark_tg_exit);
| gpl-2.0 |
mohamaadhosein/VIPER-KERNEL-D802 | arch/sparc/mm/gup.c | 5217 | 4282 | /*
* Lockless get_user_pages_fast for sparc, cribbed from powerpc
*
* Copyright (C) 2008 Nick Piggin
* Copyright (C) 2008 Novell Inc.
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/vmstat.h>
#include <linux/pagemap.h>
#include <linux/rwsem.h>
#include <asm/pgtable.h>
/*
* The performance critical leaf functions are made noinline otherwise gcc
* inlines everything into a single function which results in too much
* register pressure.
*/
static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
unsigned long end, int write, struct page **pages, int *nr)
{
unsigned long mask, result;
pte_t *ptep;
if (tlb_type == hypervisor) {
result = _PAGE_PRESENT_4V|_PAGE_P_4V;
if (write)
result |= _PAGE_WRITE_4V;
} else {
result = _PAGE_PRESENT_4U|_PAGE_P_4U;
if (write)
result |= _PAGE_WRITE_4U;
}
mask = result | _PAGE_SPECIAL;
ptep = pte_offset_kernel(&pmd, addr);
do {
struct page *page, *head;
pte_t pte = *ptep;
if ((pte_val(pte) & mask) != result)
return 0;
VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
/* The hugepage case is simplified on sparc64 because
* we encode the sub-page pfn offsets into the
* hugepage PTEs. We could optimize this in the future
* use page_cache_add_speculative() for the hugepage case.
*/
page = pte_page(pte);
head = compound_head(page);
if (!page_cache_get_speculative(head))
return 0;
if (unlikely(pte_val(pte) != pte_val(*ptep))) {
put_page(head);
return 0;
}
if (head != page)
get_huge_page_tail(page);
pages[*nr] = page;
(*nr)++;
} while (ptep++, addr += PAGE_SIZE, addr != end);
return 1;
}
static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
int write, struct page **pages, int *nr)
{
unsigned long next;
pmd_t *pmdp;
pmdp = pmd_offset(&pud, addr);
do {
pmd_t pmd = *pmdp;
next = pmd_addr_end(addr, end);
if (pmd_none(pmd))
return 0;
if (!gup_pte_range(pmd, addr, next, write, pages, nr))
return 0;
} while (pmdp++, addr = next, addr != end);
return 1;
}
static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
int write, struct page **pages, int *nr)
{
unsigned long next;
pud_t *pudp;
pudp = pud_offset(&pgd, addr);
do {
pud_t pud = *pudp;
next = pud_addr_end(addr, end);
if (pud_none(pud))
return 0;
if (!gup_pmd_range(pud, addr, next, write, pages, nr))
return 0;
} while (pudp++, addr = next, addr != end);
return 1;
}
int get_user_pages_fast(unsigned long start, int nr_pages, int write,
struct page **pages)
{
struct mm_struct *mm = current->mm;
unsigned long addr, len, end;
unsigned long next;
pgd_t *pgdp;
int nr = 0;
start &= PAGE_MASK;
addr = start;
len = (unsigned long) nr_pages << PAGE_SHIFT;
end = start + len;
/*
* XXX: batch / limit 'nr', to avoid large irq off latency
* needs some instrumenting to determine the common sizes used by
* important workloads (eg. DB2), and whether limiting the batch size
* will decrease performance.
*
* It seems like we're in the clear for the moment. Direct-IO is
* the main guy that batches up lots of get_user_pages, and even
* they are limited to 64-at-a-time which is not so many.
*/
/*
* This doesn't prevent pagetable teardown, but does prevent
* the pagetables from being freed on sparc.
*
* So long as we atomically load page table pointers versus teardown,
* we can follow the address down to the the page and take a ref on it.
*/
local_irq_disable();
pgdp = pgd_offset(mm, addr);
do {
pgd_t pgd = *pgdp;
next = pgd_addr_end(addr, end);
if (pgd_none(pgd))
goto slow;
if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
goto slow;
} while (pgdp++, addr = next, addr != end);
local_irq_enable();
VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
return nr;
{
int ret;
slow:
local_irq_enable();
/* Try to get the remaining pages with get_user_pages */
start += nr << PAGE_SHIFT;
pages += nr;
down_read(&mm->mmap_sem);
ret = get_user_pages(current, mm, start,
(end - start) >> PAGE_SHIFT, write, 0, pages, NULL);
up_read(&mm->mmap_sem);
/* Have to be a bit careful with return values */
if (nr > 0) {
if (ret < 0)
ret = nr;
else
ret += nr;
}
return ret;
}
}
| gpl-2.0 |
robreardon/android_kernel_motorola_olympus | drivers/s390/block/dasd_devmap.c | 8033 | 34673 | /*
* File...........: linux/drivers/s390/block/dasd_devmap.c
* Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
* Horst Hummel <Horst.Hummel@de.ibm.com>
* Carsten Otte <Cotte@de.ibm.com>
* Martin Schwidefsky <schwidefsky@de.ibm.com>
* Bugreports.to..: <Linux390@de.ibm.com>
* (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999-2001
*
* Device mapping and dasd= parameter parsing functions. All devmap
* functions may not be called from interrupt context. In particular
* dasd_get_device is a no-no from interrupt context.
*
*/
#define KMSG_COMPONENT "dasd"
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/debug.h>
#include <asm/uaccess.h>
#include <asm/ipl.h>
/* This is ugly... */
#define PRINTK_HEADER "dasd_devmap:"
#define DASD_BUS_ID_SIZE 20
#include "dasd_int.h"
struct kmem_cache *dasd_page_cache;
EXPORT_SYMBOL_GPL(dasd_page_cache);
/*
* dasd_devmap_t is used to store the features and the relation
* between device number and device index. To find a dasd_devmap_t
* that corresponds to a device number of a device index each
* dasd_devmap_t is added to two linked lists, one to search by
* the device number and one to search by the device index. As
* soon as big minor numbers are available the device index list
* can be removed since the device number will then be identical
* to the device index.
*/
struct dasd_devmap {
struct list_head list;
char bus_id[DASD_BUS_ID_SIZE];
unsigned int devindex;
unsigned short features;
struct dasd_device *device;
};
/*
* Parameter parsing functions for dasd= parameter. The syntax is:
* <devno> : (0x)?[0-9a-fA-F]+
* <busid> : [0-0a-f]\.[0-9a-f]\.(0x)?[0-9a-fA-F]+
* <feature> : ro
* <feature_list> : \(<feature>(:<feature>)*\)
* <devno-range> : <devno>(-<devno>)?<feature_list>?
* <busid-range> : <busid>(-<busid>)?<feature_list>?
* <devices> : <devno-range>|<busid-range>
* <dasd_module> : dasd_diag_mod|dasd_eckd_mod|dasd_fba_mod
*
* <dasd> : autodetect|probeonly|<devices>(,<devices>)*
*/
int dasd_probeonly = 0; /* is true, when probeonly mode is active */
int dasd_autodetect = 0; /* is true, when autodetection is active */
int dasd_nopav = 0; /* is true, when PAV is disabled */
EXPORT_SYMBOL_GPL(dasd_nopav);
int dasd_nofcx; /* disable High Performance Ficon */
EXPORT_SYMBOL_GPL(dasd_nofcx);
/*
* char *dasd[] is intended to hold the ranges supplied by the dasd= statement
* it is named 'dasd' to directly be filled by insmod with the comma separated
* strings when running as a module.
*/
static char *dasd[256];
module_param_array(dasd, charp, NULL, 0);
/*
* Single spinlock to protect devmap and servermap structures and lists.
*/
static DEFINE_SPINLOCK(dasd_devmap_lock);
/*
* Hash lists for devmap structures.
*/
static struct list_head dasd_hashlists[256];
int dasd_max_devindex;
static struct dasd_devmap *dasd_add_busid(const char *, int);
static inline int
dasd_hash_busid(const char *bus_id)
{
int hash, i;
hash = 0;
for (i = 0; (i < DASD_BUS_ID_SIZE) && *bus_id; i++, bus_id++)
hash += *bus_id;
return hash & 0xff;
}
#ifndef MODULE
/*
* The parameter parsing functions for builtin-drivers are called
* before kmalloc works. Store the pointers to the parameters strings
* into dasd[] for later processing.
*/
static int __init
dasd_call_setup(char *str)
{
static int count = 0;
if (count < 256)
dasd[count++] = str;
return 1;
}
__setup ("dasd=", dasd_call_setup);
#endif /* #ifndef MODULE */
#define DASD_IPLDEV "ipldev"
/*
* Read a device busid/devno from a string.
*/
static int
dasd_busid(char **str, int *id0, int *id1, int *devno)
{
int val, old_style;
/* Interpret ipldev busid */
if (strncmp(DASD_IPLDEV, *str, strlen(DASD_IPLDEV)) == 0) {
if (ipl_info.type != IPL_TYPE_CCW) {
pr_err("The IPL device is not a CCW device\n");
return -EINVAL;
}
*id0 = 0;
*id1 = ipl_info.data.ccw.dev_id.ssid;
*devno = ipl_info.data.ccw.dev_id.devno;
*str += strlen(DASD_IPLDEV);
return 0;
}
/* check for leading '0x' */
old_style = 0;
if ((*str)[0] == '0' && (*str)[1] == 'x') {
*str += 2;
old_style = 1;
}
if (!isxdigit((*str)[0])) /* We require at least one hex digit */
return -EINVAL;
val = simple_strtoul(*str, str, 16);
if (old_style || (*str)[0] != '.') {
*id0 = *id1 = 0;
if (val < 0 || val > 0xffff)
return -EINVAL;
*devno = val;
return 0;
}
/* New style x.y.z busid */
if (val < 0 || val > 0xff)
return -EINVAL;
*id0 = val;
(*str)++;
if (!isxdigit((*str)[0])) /* We require at least one hex digit */
return -EINVAL;
val = simple_strtoul(*str, str, 16);
if (val < 0 || val > 0xff || (*str)++[0] != '.')
return -EINVAL;
*id1 = val;
if (!isxdigit((*str)[0])) /* We require at least one hex digit */
return -EINVAL;
val = simple_strtoul(*str, str, 16);
if (val < 0 || val > 0xffff)
return -EINVAL;
*devno = val;
return 0;
}
/*
* Read colon separated list of dasd features. Currently there is
* only one: "ro" for read-only devices. The default feature set
* is empty (value 0).
*/
static int
dasd_feature_list(char *str, char **endp)
{
int features, len, rc;
rc = 0;
if (*str != '(') {
*endp = str;
return DASD_FEATURE_DEFAULT;
}
str++;
features = 0;
while (1) {
for (len = 0;
str[len] && str[len] != ':' && str[len] != ')'; len++);
if (len == 2 && !strncmp(str, "ro", 2))
features |= DASD_FEATURE_READONLY;
else if (len == 4 && !strncmp(str, "diag", 4))
features |= DASD_FEATURE_USEDIAG;
else if (len == 3 && !strncmp(str, "raw", 3))
features |= DASD_FEATURE_USERAW;
else if (len == 6 && !strncmp(str, "erplog", 6))
features |= DASD_FEATURE_ERPLOG;
else if (len == 8 && !strncmp(str, "failfast", 8))
features |= DASD_FEATURE_FAILFAST;
else {
pr_warning("%*s is not a supported device option\n",
len, str);
rc = -EINVAL;
}
str += len;
if (*str != ':')
break;
str++;
}
if (*str != ')') {
pr_warning("A closing parenthesis ')' is missing in the "
"dasd= parameter\n");
rc = -EINVAL;
} else
str++;
*endp = str;
if (rc != 0)
return rc;
return features;
}
/*
* Try to match the first element on the comma separated parse string
* with one of the known keywords. If a keyword is found, take the approprate
* action and return a pointer to the residual string. If the first element
* could not be matched to any keyword then return an error code.
*/
static char *
dasd_parse_keyword( char *parsestring ) {
char *nextcomma, *residual_str;
int length;
nextcomma = strchr(parsestring,',');
if (nextcomma) {
length = nextcomma - parsestring;
residual_str = nextcomma + 1;
} else {
length = strlen(parsestring);
residual_str = parsestring + length;
}
if (strncmp("autodetect", parsestring, length) == 0) {
dasd_autodetect = 1;
pr_info("The autodetection mode has been activated\n");
return residual_str;
}
if (strncmp("probeonly", parsestring, length) == 0) {
dasd_probeonly = 1;
pr_info("The probeonly mode has been activated\n");
return residual_str;
}
if (strncmp("nopav", parsestring, length) == 0) {
if (MACHINE_IS_VM)
pr_info("'nopav' is not supported on z/VM\n");
else {
dasd_nopav = 1;
pr_info("PAV support has be deactivated\n");
}
return residual_str;
}
if (strncmp("nofcx", parsestring, length) == 0) {
dasd_nofcx = 1;
pr_info("High Performance FICON support has been "
"deactivated\n");
return residual_str;
}
if (strncmp("fixedbuffers", parsestring, length) == 0) {
if (dasd_page_cache)
return residual_str;
dasd_page_cache =
kmem_cache_create("dasd_page_cache", PAGE_SIZE,
PAGE_SIZE, SLAB_CACHE_DMA,
NULL);
if (!dasd_page_cache)
DBF_EVENT(DBF_WARNING, "%s", "Failed to create slab, "
"fixed buffer mode disabled.");
else
DBF_EVENT(DBF_INFO, "%s",
"turning on fixed buffer mode");
return residual_str;
}
return ERR_PTR(-EINVAL);
}
/*
* Try to interprete the first element on the comma separated parse string
* as a device number or a range of devices. If the interpretation is
* successful, create the matching dasd_devmap entries and return a pointer
* to the residual string.
* If interpretation fails or in case of an error, return an error code.
*/
static char *
dasd_parse_range( char *parsestring ) {
struct dasd_devmap *devmap;
int from, from_id0, from_id1;
int to, to_id0, to_id1;
int features, rc;
char bus_id[DASD_BUS_ID_SIZE+1], *str;
str = parsestring;
rc = dasd_busid(&str, &from_id0, &from_id1, &from);
if (rc == 0) {
to = from;
to_id0 = from_id0;
to_id1 = from_id1;
if (*str == '-') {
str++;
rc = dasd_busid(&str, &to_id0, &to_id1, &to);
}
}
if (rc == 0 &&
(from_id0 != to_id0 || from_id1 != to_id1 || from > to))
rc = -EINVAL;
if (rc) {
pr_err("%s is not a valid device range\n", parsestring);
return ERR_PTR(rc);
}
features = dasd_feature_list(str, &str);
if (features < 0)
return ERR_PTR(-EINVAL);
/* each device in dasd= parameter should be set initially online */
features |= DASD_FEATURE_INITIAL_ONLINE;
while (from <= to) {
sprintf(bus_id, "%01x.%01x.%04x",
from_id0, from_id1, from++);
devmap = dasd_add_busid(bus_id, features);
if (IS_ERR(devmap))
return (char *)devmap;
}
if (*str == ',')
return str + 1;
if (*str == '\0')
return str;
pr_warning("The dasd= parameter value %s has an invalid ending\n",
str);
return ERR_PTR(-EINVAL);
}
static char *
dasd_parse_next_element( char *parsestring ) {
char * residual_str;
residual_str = dasd_parse_keyword(parsestring);
if (!IS_ERR(residual_str))
return residual_str;
residual_str = dasd_parse_range(parsestring);
return residual_str;
}
/*
* Parse parameters stored in dasd[]
* The 'dasd=...' parameter allows to specify a comma separated list of
* keywords and device ranges. When the dasd driver is build into the kernel,
* the complete list will be stored as one element of the dasd[] array.
* When the dasd driver is build as a module, then the list is broken into
* it's elements and each dasd[] entry contains one element.
*/
int
dasd_parse(void)
{
int rc, i;
char *parsestring;
rc = 0;
for (i = 0; i < 256; i++) {
if (dasd[i] == NULL)
break;
parsestring = dasd[i];
/* loop over the comma separated list in the parsestring */
while (*parsestring) {
parsestring = dasd_parse_next_element(parsestring);
if(IS_ERR(parsestring)) {
rc = PTR_ERR(parsestring);
break;
}
}
if (rc) {
DBF_EVENT(DBF_ALERT, "%s", "invalid range found");
break;
}
}
return rc;
}
/*
* Add a devmap for the device specified by busid. It is possible that
* the devmap already exists (dasd= parameter). The order of the devices
* added through this function will define the kdevs for the individual
* devices.
*/
static struct dasd_devmap *
dasd_add_busid(const char *bus_id, int features)
{
struct dasd_devmap *devmap, *new, *tmp;
int hash;
new = (struct dasd_devmap *)
kzalloc(sizeof(struct dasd_devmap), GFP_KERNEL);
if (!new)
return ERR_PTR(-ENOMEM);
spin_lock(&dasd_devmap_lock);
devmap = NULL;
hash = dasd_hash_busid(bus_id);
list_for_each_entry(tmp, &dasd_hashlists[hash], list)
if (strncmp(tmp->bus_id, bus_id, DASD_BUS_ID_SIZE) == 0) {
devmap = tmp;
break;
}
if (!devmap) {
/* This bus_id is new. */
new->devindex = dasd_max_devindex++;
strncpy(new->bus_id, bus_id, DASD_BUS_ID_SIZE);
new->features = features;
new->device = NULL;
list_add(&new->list, &dasd_hashlists[hash]);
devmap = new;
new = NULL;
}
spin_unlock(&dasd_devmap_lock);
kfree(new);
return devmap;
}
/*
* Find devmap for device with given bus_id.
*/
static struct dasd_devmap *
dasd_find_busid(const char *bus_id)
{
struct dasd_devmap *devmap, *tmp;
int hash;
spin_lock(&dasd_devmap_lock);
devmap = ERR_PTR(-ENODEV);
hash = dasd_hash_busid(bus_id);
list_for_each_entry(tmp, &dasd_hashlists[hash], list) {
if (strncmp(tmp->bus_id, bus_id, DASD_BUS_ID_SIZE) == 0) {
devmap = tmp;
break;
}
}
spin_unlock(&dasd_devmap_lock);
return devmap;
}
/*
* Check if busid has been added to the list of dasd ranges.
*/
int
dasd_busid_known(const char *bus_id)
{
return IS_ERR(dasd_find_busid(bus_id)) ? -ENOENT : 0;
}
/*
* Forget all about the device numbers added so far.
* This may only be called at module unload or system shutdown.
*/
static void
dasd_forget_ranges(void)
{
struct dasd_devmap *devmap, *n;
int i;
spin_lock(&dasd_devmap_lock);
for (i = 0; i < 256; i++) {
list_for_each_entry_safe(devmap, n, &dasd_hashlists[i], list) {
BUG_ON(devmap->device != NULL);
list_del(&devmap->list);
kfree(devmap);
}
}
spin_unlock(&dasd_devmap_lock);
}
/*
* Find the device struct by its device index.
*/
struct dasd_device *
dasd_device_from_devindex(int devindex)
{
struct dasd_devmap *devmap, *tmp;
struct dasd_device *device;
int i;
spin_lock(&dasd_devmap_lock);
devmap = NULL;
for (i = 0; (i < 256) && !devmap; i++)
list_for_each_entry(tmp, &dasd_hashlists[i], list)
if (tmp->devindex == devindex) {
/* Found the devmap for the device. */
devmap = tmp;
break;
}
if (devmap && devmap->device) {
device = devmap->device;
dasd_get_device(device);
} else
device = ERR_PTR(-ENODEV);
spin_unlock(&dasd_devmap_lock);
return device;
}
/*
* Return devmap for cdev. If no devmap exists yet, create one and
* connect it to the cdev.
*/
static struct dasd_devmap *
dasd_devmap_from_cdev(struct ccw_device *cdev)
{
struct dasd_devmap *devmap;
devmap = dasd_find_busid(dev_name(&cdev->dev));
if (IS_ERR(devmap))
devmap = dasd_add_busid(dev_name(&cdev->dev),
DASD_FEATURE_DEFAULT);
return devmap;
}
/*
* Create a dasd device structure for cdev.
*/
struct dasd_device *
dasd_create_device(struct ccw_device *cdev)
{
struct dasd_devmap *devmap;
struct dasd_device *device;
unsigned long flags;
int rc;
devmap = dasd_devmap_from_cdev(cdev);
if (IS_ERR(devmap))
return (void *) devmap;
device = dasd_alloc_device();
if (IS_ERR(device))
return device;
atomic_set(&device->ref_count, 3);
spin_lock(&dasd_devmap_lock);
if (!devmap->device) {
devmap->device = device;
device->devindex = devmap->devindex;
device->features = devmap->features;
get_device(&cdev->dev);
device->cdev = cdev;
rc = 0;
} else
/* Someone else was faster. */
rc = -EBUSY;
spin_unlock(&dasd_devmap_lock);
if (rc) {
dasd_free_device(device);
return ERR_PTR(rc);
}
spin_lock_irqsave(get_ccwdev_lock(cdev), flags);
dev_set_drvdata(&cdev->dev, device);
spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags);
return device;
}
/*
* Wait queue for dasd_delete_device waits.
*/
static DECLARE_WAIT_QUEUE_HEAD(dasd_delete_wq);
/*
* Remove a dasd device structure. The passed referenced
* is destroyed.
*/
void
dasd_delete_device(struct dasd_device *device)
{
struct ccw_device *cdev;
struct dasd_devmap *devmap;
unsigned long flags;
/* First remove device pointer from devmap. */
devmap = dasd_find_busid(dev_name(&device->cdev->dev));
BUG_ON(IS_ERR(devmap));
spin_lock(&dasd_devmap_lock);
if (devmap->device != device) {
spin_unlock(&dasd_devmap_lock);
dasd_put_device(device);
return;
}
devmap->device = NULL;
spin_unlock(&dasd_devmap_lock);
/* Disconnect dasd_device structure from ccw_device structure. */
spin_lock_irqsave(get_ccwdev_lock(device->cdev), flags);
dev_set_drvdata(&device->cdev->dev, NULL);
spin_unlock_irqrestore(get_ccwdev_lock(device->cdev), flags);
/*
* Drop ref_count by 3, one for the devmap reference, one for
* the cdev reference and one for the passed reference.
*/
atomic_sub(3, &device->ref_count);
/* Wait for reference counter to drop to zero. */
wait_event(dasd_delete_wq, atomic_read(&device->ref_count) == 0);
/* Disconnect dasd_device structure from ccw_device structure. */
cdev = device->cdev;
device->cdev = NULL;
/* Put ccw_device structure. */
put_device(&cdev->dev);
/* Now the device structure can be freed. */
dasd_free_device(device);
}
/*
* Reference counter dropped to zero. Wake up waiter
* in dasd_delete_device.
*/
void
dasd_put_device_wake(struct dasd_device *device)
{
wake_up(&dasd_delete_wq);
}
EXPORT_SYMBOL_GPL(dasd_put_device_wake);
/*
* Return dasd_device structure associated with cdev.
* This function needs to be called with the ccw device
* lock held. It can be used from interrupt context.
*/
struct dasd_device *
dasd_device_from_cdev_locked(struct ccw_device *cdev)
{
struct dasd_device *device = dev_get_drvdata(&cdev->dev);
if (!device)
return ERR_PTR(-ENODEV);
dasd_get_device(device);
return device;
}
/*
* Return dasd_device structure associated with cdev.
*/
struct dasd_device *
dasd_device_from_cdev(struct ccw_device *cdev)
{
struct dasd_device *device;
unsigned long flags;
spin_lock_irqsave(get_ccwdev_lock(cdev), flags);
device = dasd_device_from_cdev_locked(cdev);
spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags);
return device;
}
void dasd_add_link_to_gendisk(struct gendisk *gdp, struct dasd_device *device)
{
struct dasd_devmap *devmap;
devmap = dasd_find_busid(dev_name(&device->cdev->dev));
if (IS_ERR(devmap))
return;
spin_lock(&dasd_devmap_lock);
gdp->private_data = devmap;
spin_unlock(&dasd_devmap_lock);
}
struct dasd_device *dasd_device_from_gendisk(struct gendisk *gdp)
{
struct dasd_device *device;
struct dasd_devmap *devmap;
if (!gdp->private_data)
return NULL;
device = NULL;
spin_lock(&dasd_devmap_lock);
devmap = gdp->private_data;
if (devmap && devmap->device) {
device = devmap->device;
dasd_get_device(device);
}
spin_unlock(&dasd_devmap_lock);
return device;
}
/*
* SECTION: files in sysfs
*/
/*
* failfast controls the behaviour, if no path is available
*/
static ssize_t dasd_ff_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct dasd_devmap *devmap;
int ff_flag;
devmap = dasd_find_busid(dev_name(dev));
if (!IS_ERR(devmap))
ff_flag = (devmap->features & DASD_FEATURE_FAILFAST) != 0;
else
ff_flag = (DASD_FEATURE_DEFAULT & DASD_FEATURE_FAILFAST) != 0;
return snprintf(buf, PAGE_SIZE, ff_flag ? "1\n" : "0\n");
}
static ssize_t dasd_ff_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
int val;
char *endp;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
val = simple_strtoul(buf, &endp, 0);
if (((endp + 1) < (buf + count)) || (val > 1))
return -EINVAL;
spin_lock(&dasd_devmap_lock);
if (val)
devmap->features |= DASD_FEATURE_FAILFAST;
else
devmap->features &= ~DASD_FEATURE_FAILFAST;
if (devmap->device)
devmap->device->features = devmap->features;
spin_unlock(&dasd_devmap_lock);
return count;
}
static DEVICE_ATTR(failfast, 0644, dasd_ff_show, dasd_ff_store);
/*
* readonly controls the readonly status of a dasd
*/
static ssize_t
dasd_ro_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_devmap *devmap;
int ro_flag;
devmap = dasd_find_busid(dev_name(dev));
if (!IS_ERR(devmap))
ro_flag = (devmap->features & DASD_FEATURE_READONLY) != 0;
else
ro_flag = (DASD_FEATURE_DEFAULT & DASD_FEATURE_READONLY) != 0;
return snprintf(buf, PAGE_SIZE, ro_flag ? "1\n" : "0\n");
}
static ssize_t
dasd_ro_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
struct dasd_device *device;
int val;
char *endp;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
val = simple_strtoul(buf, &endp, 0);
if (((endp + 1) < (buf + count)) || (val > 1))
return -EINVAL;
spin_lock(&dasd_devmap_lock);
if (val)
devmap->features |= DASD_FEATURE_READONLY;
else
devmap->features &= ~DASD_FEATURE_READONLY;
device = devmap->device;
if (device) {
device->features = devmap->features;
val = val || test_bit(DASD_FLAG_DEVICE_RO, &device->flags);
}
spin_unlock(&dasd_devmap_lock);
if (device && device->block && device->block->gdp)
set_disk_ro(device->block->gdp, val);
return count;
}
static DEVICE_ATTR(readonly, 0644, dasd_ro_show, dasd_ro_store);
/*
* erplog controls the logging of ERP related data
* (e.g. failing channel programs).
*/
static ssize_t
dasd_erplog_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_devmap *devmap;
int erplog;
devmap = dasd_find_busid(dev_name(dev));
if (!IS_ERR(devmap))
erplog = (devmap->features & DASD_FEATURE_ERPLOG) != 0;
else
erplog = (DASD_FEATURE_DEFAULT & DASD_FEATURE_ERPLOG) != 0;
return snprintf(buf, PAGE_SIZE, erplog ? "1\n" : "0\n");
}
static ssize_t
dasd_erplog_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
int val;
char *endp;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
val = simple_strtoul(buf, &endp, 0);
if (((endp + 1) < (buf + count)) || (val > 1))
return -EINVAL;
spin_lock(&dasd_devmap_lock);
if (val)
devmap->features |= DASD_FEATURE_ERPLOG;
else
devmap->features &= ~DASD_FEATURE_ERPLOG;
if (devmap->device)
devmap->device->features = devmap->features;
spin_unlock(&dasd_devmap_lock);
return count;
}
static DEVICE_ATTR(erplog, 0644, dasd_erplog_show, dasd_erplog_store);
/*
* use_diag controls whether the driver should use diag rather than ssch
* to talk to the device
*/
static ssize_t
dasd_use_diag_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_devmap *devmap;
int use_diag;
devmap = dasd_find_busid(dev_name(dev));
if (!IS_ERR(devmap))
use_diag = (devmap->features & DASD_FEATURE_USEDIAG) != 0;
else
use_diag = (DASD_FEATURE_DEFAULT & DASD_FEATURE_USEDIAG) != 0;
return sprintf(buf, use_diag ? "1\n" : "0\n");
}
static ssize_t
dasd_use_diag_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
ssize_t rc;
int val;
char *endp;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
val = simple_strtoul(buf, &endp, 0);
if (((endp + 1) < (buf + count)) || (val > 1))
return -EINVAL;
spin_lock(&dasd_devmap_lock);
/* Changing diag discipline flag is only allowed in offline state. */
rc = count;
if (!devmap->device && !(devmap->features & DASD_FEATURE_USERAW)) {
if (val)
devmap->features |= DASD_FEATURE_USEDIAG;
else
devmap->features &= ~DASD_FEATURE_USEDIAG;
} else
rc = -EPERM;
spin_unlock(&dasd_devmap_lock);
return rc;
}
static DEVICE_ATTR(use_diag, 0644, dasd_use_diag_show, dasd_use_diag_store);
/*
* use_raw controls whether the driver should give access to raw eckd data or
* operate in standard mode
*/
static ssize_t
dasd_use_raw_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_devmap *devmap;
int use_raw;
devmap = dasd_find_busid(dev_name(dev));
if (!IS_ERR(devmap))
use_raw = (devmap->features & DASD_FEATURE_USERAW) != 0;
else
use_raw = (DASD_FEATURE_DEFAULT & DASD_FEATURE_USERAW) != 0;
return sprintf(buf, use_raw ? "1\n" : "0\n");
}
static ssize_t
dasd_use_raw_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
ssize_t rc;
unsigned long val;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
if ((strict_strtoul(buf, 10, &val) != 0) || val > 1)
return -EINVAL;
spin_lock(&dasd_devmap_lock);
/* Changing diag discipline flag is only allowed in offline state. */
rc = count;
if (!devmap->device && !(devmap->features & DASD_FEATURE_USEDIAG)) {
if (val)
devmap->features |= DASD_FEATURE_USERAW;
else
devmap->features &= ~DASD_FEATURE_USERAW;
} else
rc = -EPERM;
spin_unlock(&dasd_devmap_lock);
return rc;
}
static DEVICE_ATTR(raw_track_access, 0644, dasd_use_raw_show,
dasd_use_raw_store);
static ssize_t
dasd_discipline_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct dasd_device *device;
ssize_t len;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (IS_ERR(device))
goto out;
else if (!device->discipline) {
dasd_put_device(device);
goto out;
} else {
len = snprintf(buf, PAGE_SIZE, "%s\n",
device->discipline->name);
dasd_put_device(device);
return len;
}
out:
len = snprintf(buf, PAGE_SIZE, "none\n");
return len;
}
static DEVICE_ATTR(discipline, 0444, dasd_discipline_show, NULL);
static ssize_t
dasd_device_status_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct dasd_device *device;
ssize_t len;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (!IS_ERR(device)) {
switch (device->state) {
case DASD_STATE_NEW:
len = snprintf(buf, PAGE_SIZE, "new\n");
break;
case DASD_STATE_KNOWN:
len = snprintf(buf, PAGE_SIZE, "detected\n");
break;
case DASD_STATE_BASIC:
len = snprintf(buf, PAGE_SIZE, "basic\n");
break;
case DASD_STATE_UNFMT:
len = snprintf(buf, PAGE_SIZE, "unformatted\n");
break;
case DASD_STATE_READY:
len = snprintf(buf, PAGE_SIZE, "ready\n");
break;
case DASD_STATE_ONLINE:
len = snprintf(buf, PAGE_SIZE, "online\n");
break;
default:
len = snprintf(buf, PAGE_SIZE, "no stat\n");
break;
}
dasd_put_device(device);
} else
len = snprintf(buf, PAGE_SIZE, "unknown\n");
return len;
}
static DEVICE_ATTR(status, 0444, dasd_device_status_show, NULL);
static ssize_t dasd_alias_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dasd_device *device;
struct dasd_uid uid;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (IS_ERR(device))
return sprintf(buf, "0\n");
if (device->discipline && device->discipline->get_uid &&
!device->discipline->get_uid(device, &uid)) {
if (uid.type == UA_BASE_PAV_ALIAS ||
uid.type == UA_HYPER_PAV_ALIAS) {
dasd_put_device(device);
return sprintf(buf, "1\n");
}
}
dasd_put_device(device);
return sprintf(buf, "0\n");
}
static DEVICE_ATTR(alias, 0444, dasd_alias_show, NULL);
static ssize_t dasd_vendor_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dasd_device *device;
struct dasd_uid uid;
char *vendor;
device = dasd_device_from_cdev(to_ccwdev(dev));
vendor = "";
if (IS_ERR(device))
return snprintf(buf, PAGE_SIZE, "%s\n", vendor);
if (device->discipline && device->discipline->get_uid &&
!device->discipline->get_uid(device, &uid))
vendor = uid.vendor;
dasd_put_device(device);
return snprintf(buf, PAGE_SIZE, "%s\n", vendor);
}
static DEVICE_ATTR(vendor, 0444, dasd_vendor_show, NULL);
#define UID_STRLEN ( /* vendor */ 3 + 1 + /* serial */ 14 + 1 +\
/* SSID */ 4 + 1 + /* unit addr */ 2 + 1 +\
/* vduit */ 32 + 1)
static ssize_t
dasd_uid_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_device *device;
struct dasd_uid uid;
char uid_string[UID_STRLEN];
char ua_string[3];
device = dasd_device_from_cdev(to_ccwdev(dev));
uid_string[0] = 0;
if (IS_ERR(device))
return snprintf(buf, PAGE_SIZE, "%s\n", uid_string);
if (device->discipline && device->discipline->get_uid &&
!device->discipline->get_uid(device, &uid)) {
switch (uid.type) {
case UA_BASE_DEVICE:
snprintf(ua_string, sizeof(ua_string), "%02x",
uid.real_unit_addr);
break;
case UA_BASE_PAV_ALIAS:
snprintf(ua_string, sizeof(ua_string), "%02x",
uid.base_unit_addr);
break;
case UA_HYPER_PAV_ALIAS:
snprintf(ua_string, sizeof(ua_string), "xx");
break;
default:
/* should not happen, treat like base device */
snprintf(ua_string, sizeof(ua_string), "%02x",
uid.real_unit_addr);
break;
}
if (strlen(uid.vduit) > 0)
snprintf(uid_string, sizeof(uid_string),
"%s.%s.%04x.%s.%s",
uid.vendor, uid.serial, uid.ssid, ua_string,
uid.vduit);
else
snprintf(uid_string, sizeof(uid_string),
"%s.%s.%04x.%s",
uid.vendor, uid.serial, uid.ssid, ua_string);
}
dasd_put_device(device);
return snprintf(buf, PAGE_SIZE, "%s\n", uid_string);
}
static DEVICE_ATTR(uid, 0444, dasd_uid_show, NULL);
/*
* extended error-reporting
*/
static ssize_t
dasd_eer_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_devmap *devmap;
int eer_flag;
devmap = dasd_find_busid(dev_name(dev));
if (!IS_ERR(devmap) && devmap->device)
eer_flag = dasd_eer_enabled(devmap->device);
else
eer_flag = 0;
return snprintf(buf, PAGE_SIZE, eer_flag ? "1\n" : "0\n");
}
static ssize_t
dasd_eer_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
int val, rc;
char *endp;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
if (!devmap->device)
return -ENODEV;
val = simple_strtoul(buf, &endp, 0);
if (((endp + 1) < (buf + count)) || (val > 1))
return -EINVAL;
if (val) {
rc = dasd_eer_enable(devmap->device);
if (rc)
return rc;
} else
dasd_eer_disable(devmap->device);
return count;
}
static DEVICE_ATTR(eer_enabled, 0644, dasd_eer_show, dasd_eer_store);
/*
* expiration time for default requests
*/
static ssize_t
dasd_expires_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dasd_device *device;
int len;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (IS_ERR(device))
return -ENODEV;
len = snprintf(buf, PAGE_SIZE, "%lu\n", device->default_expires);
dasd_put_device(device);
return len;
}
static ssize_t
dasd_expires_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_device *device;
unsigned long val;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (IS_ERR(device))
return -ENODEV;
if ((strict_strtoul(buf, 10, &val) != 0) ||
(val > DASD_EXPIRES_MAX) || val == 0) {
dasd_put_device(device);
return -EINVAL;
}
if (val)
device->default_expires = val;
dasd_put_device(device);
return count;
}
static DEVICE_ATTR(expires, 0644, dasd_expires_show, dasd_expires_store);
static ssize_t dasd_reservation_policy_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dasd_devmap *devmap;
int rc = 0;
devmap = dasd_find_busid(dev_name(dev));
if (IS_ERR(devmap)) {
rc = snprintf(buf, PAGE_SIZE, "ignore\n");
} else {
spin_lock(&dasd_devmap_lock);
if (devmap->features & DASD_FEATURE_FAILONSLCK)
rc = snprintf(buf, PAGE_SIZE, "fail\n");
else
rc = snprintf(buf, PAGE_SIZE, "ignore\n");
spin_unlock(&dasd_devmap_lock);
}
return rc;
}
static ssize_t dasd_reservation_policy_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_devmap *devmap;
int rc;
devmap = dasd_devmap_from_cdev(to_ccwdev(dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
rc = 0;
spin_lock(&dasd_devmap_lock);
if (sysfs_streq("ignore", buf))
devmap->features &= ~DASD_FEATURE_FAILONSLCK;
else if (sysfs_streq("fail", buf))
devmap->features |= DASD_FEATURE_FAILONSLCK;
else
rc = -EINVAL;
if (devmap->device)
devmap->device->features = devmap->features;
spin_unlock(&dasd_devmap_lock);
if (rc)
return rc;
else
return count;
}
static DEVICE_ATTR(reservation_policy, 0644,
dasd_reservation_policy_show, dasd_reservation_policy_store);
static ssize_t dasd_reservation_state_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dasd_device *device;
int rc = 0;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (IS_ERR(device))
return snprintf(buf, PAGE_SIZE, "none\n");
if (test_bit(DASD_FLAG_IS_RESERVED, &device->flags))
rc = snprintf(buf, PAGE_SIZE, "reserved\n");
else if (test_bit(DASD_FLAG_LOCK_STOLEN, &device->flags))
rc = snprintf(buf, PAGE_SIZE, "lost\n");
else
rc = snprintf(buf, PAGE_SIZE, "none\n");
dasd_put_device(device);
return rc;
}
static ssize_t dasd_reservation_state_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct dasd_device *device;
int rc = 0;
device = dasd_device_from_cdev(to_ccwdev(dev));
if (IS_ERR(device))
return -ENODEV;
if (sysfs_streq("reset", buf))
clear_bit(DASD_FLAG_LOCK_STOLEN, &device->flags);
else
rc = -EINVAL;
dasd_put_device(device);
if (rc)
return rc;
else
return count;
}
static DEVICE_ATTR(last_known_reservation_state, 0644,
dasd_reservation_state_show, dasd_reservation_state_store);
static struct attribute * dasd_attrs[] = {
&dev_attr_readonly.attr,
&dev_attr_discipline.attr,
&dev_attr_status.attr,
&dev_attr_alias.attr,
&dev_attr_vendor.attr,
&dev_attr_uid.attr,
&dev_attr_use_diag.attr,
&dev_attr_raw_track_access.attr,
&dev_attr_eer_enabled.attr,
&dev_attr_erplog.attr,
&dev_attr_failfast.attr,
&dev_attr_expires.attr,
&dev_attr_reservation_policy.attr,
&dev_attr_last_known_reservation_state.attr,
NULL,
};
static struct attribute_group dasd_attr_group = {
.attrs = dasd_attrs,
};
/*
* Return value of the specified feature.
*/
int
dasd_get_feature(struct ccw_device *cdev, int feature)
{
struct dasd_devmap *devmap;
devmap = dasd_find_busid(dev_name(&cdev->dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
return ((devmap->features & feature) != 0);
}
/*
* Set / reset given feature.
* Flag indicates wether to set (!=0) or the reset (=0) the feature.
*/
int
dasd_set_feature(struct ccw_device *cdev, int feature, int flag)
{
struct dasd_devmap *devmap;
devmap = dasd_find_busid(dev_name(&cdev->dev));
if (IS_ERR(devmap))
return PTR_ERR(devmap);
spin_lock(&dasd_devmap_lock);
if (flag)
devmap->features |= feature;
else
devmap->features &= ~feature;
if (devmap->device)
devmap->device->features = devmap->features;
spin_unlock(&dasd_devmap_lock);
return 0;
}
int
dasd_add_sysfs_files(struct ccw_device *cdev)
{
return sysfs_create_group(&cdev->dev.kobj, &dasd_attr_group);
}
void
dasd_remove_sysfs_files(struct ccw_device *cdev)
{
sysfs_remove_group(&cdev->dev.kobj, &dasd_attr_group);
}
int
dasd_devmap_init(void)
{
int i;
/* Initialize devmap structures. */
dasd_max_devindex = 0;
for (i = 0; i < 256; i++)
INIT_LIST_HEAD(&dasd_hashlists[i]);
return 0;
}
void
dasd_devmap_exit(void)
{
dasd_forget_ranges();
}
| gpl-2.0 |
venkat66/android_kernel_lenovo_msm8916 | drivers/soc/qcom/ipc_router_hsic_xprt.c | 98 | 21533 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* IPC ROUTER HSIC XPRT module.
*/
#define DEBUG
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/of.h>
#include <linux/ipc_router_xprt.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <soc/qcom/subsystem_restart.h>
#include <mach/ipc_bridge.h>
static int msm_ipc_router_hsic_xprt_debug_mask;
module_param_named(debug_mask, msm_ipc_router_hsic_xprt_debug_mask,
int, S_IRUGO | S_IWUSR | S_IWGRP);
#if defined(DEBUG)
#define D(x...) do { \
if (msm_ipc_router_hsic_xprt_debug_mask) \
pr_info(x); \
} while (0)
#else
#define D(x...) do { } while (0)
#endif
#define NUM_HSIC_XPRTS 1
#define XPRT_NAME_LEN 32
/**
* msm_ipc_router_hsic_xprt - IPC Router's HSIC XPRT structure
* @list: IPC router's HSIC XPRTs list.
* @ch_name: Name of the HSIC endpoint exported by ipc_bridge driver.
* @xprt_name: Name of the XPRT to be registered with IPC Router.
* @driver: Platform drivers register by this XPRT.
* @xprt: IPC Router XPRT structure to contain HSIC XPRT specific info.
* @pdev: Platform device registered by IPC Bridge function driver.
* @hsic_xprt_wq: Workqueue to queue read & other XPRT related works.
* @read_work: Read Work to perform read operation from HSIC's ipc_bridge.
* @in_pkt: Pointer to any partially read packet.
* @ss_reset_lock: Lock to protect access to the ss_reset flag.
* @ss_reset: flag used to check SSR state.
* @sft_close_complete: Variable to indicate completion of SSR handling
* by IPC Router.
* @xprt_version: IPC Router header version supported by this XPRT.
* @xprt_option: XPRT specific options to be handled by IPC Router.
*/
struct msm_ipc_router_hsic_xprt {
struct list_head list;
char ch_name[XPRT_NAME_LEN];
char xprt_name[XPRT_NAME_LEN];
struct platform_driver driver;
struct msm_ipc_router_xprt xprt;
struct platform_device *pdev;
struct workqueue_struct *hsic_xprt_wq;
struct delayed_work read_work;
struct rr_packet *in_pkt;
struct mutex ss_reset_lock;
int ss_reset;
struct completion sft_close_complete;
unsigned xprt_version;
unsigned xprt_option;
};
struct msm_ipc_router_hsic_xprt_work {
struct msm_ipc_router_xprt *xprt;
struct work_struct work;
};
static void hsic_xprt_read_data(struct work_struct *work);
/**
* msm_ipc_router_hsic_xprt_config - Config. Info. of each HSIC XPRT
* @ch_name: Name of the HSIC endpoint exported by ipc_bridge driver.
* @xprt_name: Name of the XPRT to be registered with IPC Router.
* @hsic_pdev_id: ID to differentiate among multiple ipc_bridge endpoints.
* @link_id: Network Cluster ID to which this XPRT belongs to.
* @xprt_version: IPC Router header version supported by this XPRT.
*/
struct msm_ipc_router_hsic_xprt_config {
char ch_name[XPRT_NAME_LEN];
char xprt_name[XPRT_NAME_LEN];
int hsic_pdev_id;
uint32_t link_id;
unsigned xprt_version;
};
struct msm_ipc_router_hsic_xprt_config hsic_xprt_cfg[] = {
{"ipc_bridge", "ipc_rtr_ipc_bridge1", 1, 1, 3},
};
#define MODULE_NAME "ipc_router_hsic_xprt"
#define IPC_ROUTER_HSIC_XPRT_WAIT_TIMEOUT 3000
static int ipc_router_hsic_xprt_probe_done;
static struct delayed_work ipc_router_hsic_xprt_probe_work;
static DEFINE_MUTEX(hsic_remote_xprt_list_lock_lha1);
static LIST_HEAD(hsic_remote_xprt_list);
/**
* find_hsic_xprt_list() - Find xprt item specific to an HSIC endpoint
* @name: Name of the platform device to find in list
*
* @return: pointer to msm_ipc_router_hsic_xprt if matching endpoint is found,
* else NULL.
*
* This function is used to find specific xprt item from the global xprt list
*/
static struct msm_ipc_router_hsic_xprt *
find_hsic_xprt_list(const char *name)
{
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
mutex_lock(&hsic_remote_xprt_list_lock_lha1);
list_for_each_entry(hsic_xprtp, &hsic_remote_xprt_list, list) {
if (!strcmp(name, hsic_xprtp->ch_name)) {
mutex_unlock(&hsic_remote_xprt_list_lock_lha1);
return hsic_xprtp;
}
}
mutex_unlock(&hsic_remote_xprt_list_lock_lha1);
return NULL;
}
/**
* msm_ipc_router_hsic_get_xprt_version() - Get IPC Router header version
* supported by the XPRT
* @xprt: XPRT for which the version information is required.
*
* @return: IPC Router header version supported by the XPRT.
*/
static int msm_ipc_router_hsic_get_xprt_version(
struct msm_ipc_router_xprt *xprt)
{
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
if (!xprt)
return -EINVAL;
hsic_xprtp = container_of(xprt, struct msm_ipc_router_hsic_xprt, xprt);
return (int)hsic_xprtp->xprt_version;
}
/**
* msm_ipc_router_hsic_get_xprt_option() - Get XPRT options
* @xprt: XPRT for which the option information is required.
*
* @return: Options supported by the XPRT.
*/
static int msm_ipc_router_hsic_get_xprt_option(
struct msm_ipc_router_xprt *xprt)
{
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
if (!xprt)
return -EINVAL;
hsic_xprtp = container_of(xprt, struct msm_ipc_router_hsic_xprt, xprt);
return (int)hsic_xprtp->xprt_option;
}
/**
* msm_ipc_router_hsic_remote_write_avail() - Get available write space
* @xprt: XPRT for which the available write space info. is required.
*
* @return: Write space in bytes on success, 0 on SSR.
*/
static int msm_ipc_router_hsic_remote_write_avail(
struct msm_ipc_router_xprt *xprt)
{
struct ipc_bridge_platform_data *pdata;
int write_avail;
struct msm_ipc_router_hsic_xprt *hsic_xprtp =
container_of(xprt, struct msm_ipc_router_hsic_xprt, xprt);
mutex_lock(&hsic_xprtp->ss_reset_lock);
if (hsic_xprtp->ss_reset || !hsic_xprtp->pdev) {
write_avail = 0;
} else {
pdata = hsic_xprtp->pdev->dev.platform_data;
write_avail = pdata->max_write_size;
}
mutex_unlock(&hsic_xprtp->ss_reset_lock);
return write_avail;
}
/**
* msm_ipc_router_hsic_remote_write() - Write to XPRT
* @data: Data to be written to the XPRT.
* @len: Length of the data to be written.
* @xprt: XPRT to which the data has to be written.
*
* @return: Data Length on success, standard Linux error codes on failure.
*/
static int msm_ipc_router_hsic_remote_write(void *data,
uint32_t len, struct msm_ipc_router_xprt *xprt)
{
struct rr_packet *pkt = (struct rr_packet *)data;
struct sk_buff *skb;
struct ipc_bridge_platform_data *pdata;
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
int ret;
if (!pkt || pkt->length != len || !xprt) {
pr_err("%s: Invalid input parameters\n", __func__);
return -EINVAL;
}
hsic_xprtp = container_of(xprt, struct msm_ipc_router_hsic_xprt, xprt);
mutex_lock(&hsic_xprtp->ss_reset_lock);
if (hsic_xprtp->ss_reset) {
pr_err("%s: Trying to write on a reset link\n", __func__);
mutex_unlock(&hsic_xprtp->ss_reset_lock);
return -ENETRESET;
}
if (!hsic_xprtp->pdev) {
pr_err("%s: Trying to write on a closed link\n", __func__);
mutex_unlock(&hsic_xprtp->ss_reset_lock);
return -ENODEV;
}
pdata = hsic_xprtp->pdev->dev.platform_data;
if (!pdata || !pdata->write) {
pr_err("%s on a uninitialized link\n", __func__);
mutex_unlock(&hsic_xprtp->ss_reset_lock);
return -EFAULT;
}
skb = skb_peek(pkt->pkt_fragment_q);
if (!skb) {
pr_err("%s SKB is NULL\n", __func__);
mutex_unlock(&hsic_xprtp->ss_reset_lock);
return -EINVAL;
}
D("%s: About to write %d bytes\n", __func__, len);
ret = pdata->write(hsic_xprtp->pdev, skb->data, skb->len);
if (ret == skb->len)
ret = len;
D("%s: Finished writing %d bytes\n", __func__, len);
mutex_unlock(&hsic_xprtp->ss_reset_lock);
return ret;
}
/**
* msm_ipc_router_hsic_remote_close() - Close the XPRT
* @xprt: XPRT which needs to be closed.
*
* @return: 0 on success, standard Linux error codes on failure.
*/
static int msm_ipc_router_hsic_remote_close(
struct msm_ipc_router_xprt *xprt)
{
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
struct ipc_bridge_platform_data *pdata;
if (!xprt)
return -EINVAL;
hsic_xprtp = container_of(xprt, struct msm_ipc_router_hsic_xprt, xprt);
mutex_lock(&hsic_xprtp->ss_reset_lock);
hsic_xprtp->ss_reset = 1;
mutex_unlock(&hsic_xprtp->ss_reset_lock);
flush_workqueue(hsic_xprtp->hsic_xprt_wq);
destroy_workqueue(hsic_xprtp->hsic_xprt_wq);
pdata = hsic_xprtp->pdev->dev.platform_data;
if (pdata && pdata->close)
pdata->close(hsic_xprtp->pdev);
hsic_xprtp->pdev = NULL;
return 0;
}
/**
* hsic_xprt_read_data() - Read work to read from the XPRT
* @work: Read work to be executed.
*
* This function is a read work item queued on a XPRT specific workqueue.
* The work parameter contains information regarding the XPRT on which this
* read work has to be performed. The work item keeps reading from the HSIC
* endpoint, until the endpoint returns an error.
*/
static void hsic_xprt_read_data(struct work_struct *work)
{
int pkt_size;
struct sk_buff *skb = NULL;
void *data;
struct ipc_bridge_platform_data *pdata;
struct delayed_work *rwork = to_delayed_work(work);
struct msm_ipc_router_hsic_xprt *hsic_xprtp =
container_of(rwork, struct msm_ipc_router_hsic_xprt, read_work);
while (1) {
mutex_lock(&hsic_xprtp->ss_reset_lock);
if (hsic_xprtp->ss_reset) {
mutex_unlock(&hsic_xprtp->ss_reset_lock);
break;
}
pdata = hsic_xprtp->pdev->dev.platform_data;
mutex_unlock(&hsic_xprtp->ss_reset_lock);
while (!hsic_xprtp->in_pkt) {
hsic_xprtp->in_pkt = kzalloc(sizeof(struct rr_packet),
GFP_KERNEL);
if (hsic_xprtp->in_pkt)
break;
pr_err("%s: packet allocation failure\n", __func__);
msleep(100);
}
while (!hsic_xprtp->in_pkt->pkt_fragment_q) {
hsic_xprtp->in_pkt->pkt_fragment_q =
kmalloc(sizeof(struct sk_buff_head),
GFP_KERNEL);
if (hsic_xprtp->in_pkt->pkt_fragment_q)
break;
pr_err("%s: Couldn't alloc pkt_fragment_q\n",
__func__);
msleep(100);
}
skb_queue_head_init(hsic_xprtp->in_pkt->pkt_fragment_q);
D("%s: Allocated rr_packet\n", __func__);
while (!skb) {
skb = alloc_skb(pdata->max_read_size, GFP_KERNEL);
if (skb)
break;
pr_err("%s: Couldn't alloc SKB\n", __func__);
msleep(100);
}
data = skb_put(skb, pdata->max_read_size);
pkt_size = pdata->read(hsic_xprtp->pdev, data,
pdata->max_read_size);
if (pkt_size < 0) {
pr_err("%s: Error %d @ read operation\n",
__func__, pkt_size);
kfree_skb(skb);
kfree(hsic_xprtp->in_pkt->pkt_fragment_q);
kfree(hsic_xprtp->in_pkt);
break;
}
skb_queue_tail(hsic_xprtp->in_pkt->pkt_fragment_q, skb);
hsic_xprtp->in_pkt->length = pkt_size;
D("%s: Packet size read %d\n", __func__, pkt_size);
msm_ipc_router_xprt_notify(&hsic_xprtp->xprt,
IPC_ROUTER_XPRT_EVENT_DATA, (void *)hsic_xprtp->in_pkt);
release_pkt(hsic_xprtp->in_pkt);
hsic_xprtp->in_pkt = NULL;
skb = NULL;
}
}
/**
* hsic_xprt_sft_close_done() - Completion of XPRT reset
* @xprt: XPRT on which the reset operation is complete.
*
* This function is used by IPC Router to signal this HSIC XPRT Abstraction
* Layer(XAL) that the reset of XPRT is completely handled by IPC Router.
*/
static void hsic_xprt_sft_close_done(struct msm_ipc_router_xprt *xprt)
{
struct msm_ipc_router_hsic_xprt *hsic_xprtp =
container_of(xprt, struct msm_ipc_router_hsic_xprt, xprt);
complete_all(&hsic_xprtp->sft_close_complete);
}
/**
* msm_ipc_router_hsic_remote_remove() - Remove an HSIC endpoint
* @pdev: Platform device corresponding to HSIC endpoint.
*
* @return: 0 on success, standard Linux error codes on error.
*
* This function is called when the underlying ipc_bridge driver unregisters
* a platform device, mapped to an HSIC endpoint, during SSR.
*/
static int msm_ipc_router_hsic_remote_remove(struct platform_device *pdev)
{
struct ipc_bridge_platform_data *pdata;
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
hsic_xprtp = find_hsic_xprt_list(pdev->name);
if (!hsic_xprtp) {
pr_err("%s No device with name %s\n", __func__, pdev->name);
return -ENODEV;
}
mutex_lock(&hsic_xprtp->ss_reset_lock);
hsic_xprtp->ss_reset = 1;
mutex_unlock(&hsic_xprtp->ss_reset_lock);
flush_workqueue(hsic_xprtp->hsic_xprt_wq);
destroy_workqueue(hsic_xprtp->hsic_xprt_wq);
init_completion(&hsic_xprtp->sft_close_complete);
msm_ipc_router_xprt_notify(&hsic_xprtp->xprt,
IPC_ROUTER_XPRT_EVENT_CLOSE, NULL);
D("%s: Notified IPC Router of %s CLOSE\n",
__func__, hsic_xprtp->xprt.name);
wait_for_completion(&hsic_xprtp->sft_close_complete);
hsic_xprtp->pdev = NULL;
pdata = pdev->dev.platform_data;
if (pdata && pdata->close)
pdata->close(pdev);
return 0;
}
/**
* msm_ipc_router_hsic_remote_probe() - Probe an HSIC endpoint
* @pdev: Platform device corresponding to HSIC endpoint.
*
* @return: 0 on success, standard Linux error codes on error.
*
* This function is called when the underlying ipc_bridge driver registers
* a platform device, mapped to an HSIC endpoint.
*/
static int msm_ipc_router_hsic_remote_probe(struct platform_device *pdev)
{
int rc;
struct ipc_bridge_platform_data *pdata;
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
pdata = pdev->dev.platform_data;
if (!pdata || !pdata->open || !pdata->read ||
!pdata->write || !pdata->close) {
pr_err("%s: pdata or pdata->operations is NULL\n", __func__);
return -EINVAL;
}
hsic_xprtp = find_hsic_xprt_list(pdev->name);
if (!hsic_xprtp) {
pr_err("%s No device with name %s\n", __func__, pdev->name);
return -ENODEV;
}
hsic_xprtp->hsic_xprt_wq =
create_singlethread_workqueue(pdev->name);
if (!hsic_xprtp->hsic_xprt_wq) {
pr_err("%s: WQ creation failed for %s\n",
__func__, pdev->name);
return -EFAULT;
}
rc = pdata->open(pdev);
if (rc < 0) {
pr_err("%s: Channel open failed for %s.%d\n",
__func__, pdev->name, pdev->id);
destroy_workqueue(hsic_xprtp->hsic_xprt_wq);
return rc;
}
hsic_xprtp->pdev = pdev;
msm_ipc_router_xprt_notify(&hsic_xprtp->xprt,
IPC_ROUTER_XPRT_EVENT_OPEN, NULL);
D("%s: Notified IPC Router of %s OPEN\n",
__func__, hsic_xprtp->xprt.name);
queue_delayed_work(hsic_xprtp->hsic_xprt_wq,
&hsic_xprtp->read_work, 0);
return 0;
}
/**
* msm_ipc_router_hsic_driver_register() - register HSIC XPRT drivers
*
* @hsic_xprtp: pointer to IPC router hsic xprt structure.
*
* @return: 0 on success, standard Linux error codes on error.
*
* This function is called when a new XPRT is added to register platform
* drivers for new XPRT.
*/
static int msm_ipc_router_hsic_driver_register(
struct msm_ipc_router_hsic_xprt *hsic_xprtp)
{
int ret;
struct msm_ipc_router_hsic_xprt *hsic_xprtp_item;
hsic_xprtp_item = find_hsic_xprt_list(hsic_xprtp->ch_name);
mutex_lock(&hsic_remote_xprt_list_lock_lha1);
list_add(&hsic_xprtp->list, &hsic_remote_xprt_list);
mutex_unlock(&hsic_remote_xprt_list_lock_lha1);
if (!hsic_xprtp_item) {
hsic_xprtp->driver.driver.name = hsic_xprtp->ch_name;
hsic_xprtp->driver.driver.owner = THIS_MODULE;
hsic_xprtp->driver.probe = msm_ipc_router_hsic_remote_probe;
hsic_xprtp->driver.remove = msm_ipc_router_hsic_remote_remove;
ret = platform_driver_register(&hsic_xprtp->driver);
if (ret) {
pr_err("%s: Failed to register platform driver[%s]\n",
__func__, hsic_xprtp->ch_name);
return ret;
}
} else {
pr_err("%s Already driver registered %s\n",
__func__, hsic_xprtp->ch_name);
}
return 0;
}
/**
* msm_ipc_router_hsic_config_init() - init HSIC xprt configs
*
* @hsic_xprt_config: pointer to HSIC xprt configurations.
*
* @return: 0 on success, standard Linux error codes on error.
*
* This function is called to initialize the HSIC XPRT pointer with
* the HSIC XPRT configurations either from device tree or static arrays.
*/
static int msm_ipc_router_hsic_config_init(
struct msm_ipc_router_hsic_xprt_config *hsic_xprt_config)
{
struct msm_ipc_router_hsic_xprt *hsic_xprtp;
hsic_xprtp = kzalloc(sizeof(struct msm_ipc_router_hsic_xprt),
GFP_KERNEL);
if (IS_ERR_OR_NULL(hsic_xprtp)) {
pr_err("%s: kzalloc() failed for hsic_xprtp id:%s\n",
__func__, hsic_xprt_config->ch_name);
return -ENOMEM;
}
hsic_xprtp->xprt.link_id = hsic_xprt_config->link_id;
hsic_xprtp->xprt_version = hsic_xprt_config->xprt_version;
strlcpy(hsic_xprtp->ch_name, hsic_xprt_config->ch_name,
XPRT_NAME_LEN);
strlcpy(hsic_xprtp->xprt_name, hsic_xprt_config->xprt_name,
XPRT_NAME_LEN);
hsic_xprtp->xprt.name = hsic_xprtp->xprt_name;
hsic_xprtp->xprt.get_version =
msm_ipc_router_hsic_get_xprt_version;
hsic_xprtp->xprt.get_option =
msm_ipc_router_hsic_get_xprt_option;
hsic_xprtp->xprt.read_avail = NULL;
hsic_xprtp->xprt.read = NULL;
hsic_xprtp->xprt.write_avail =
msm_ipc_router_hsic_remote_write_avail;
hsic_xprtp->xprt.write = msm_ipc_router_hsic_remote_write;
hsic_xprtp->xprt.close = msm_ipc_router_hsic_remote_close;
hsic_xprtp->xprt.sft_close_done = hsic_xprt_sft_close_done;
hsic_xprtp->xprt.priv = NULL;
hsic_xprtp->in_pkt = NULL;
INIT_DELAYED_WORK(&hsic_xprtp->read_work, hsic_xprt_read_data);
mutex_init(&hsic_xprtp->ss_reset_lock);
hsic_xprtp->ss_reset = 0;
hsic_xprtp->xprt_option = 0;
msm_ipc_router_hsic_driver_register(hsic_xprtp);
return 0;
}
/**
* parse_devicetree() - parse device tree binding
*
* @node: pointer to device tree node
* @hsic_xprt_config: pointer to HSIC XPRT configurations
*
* @return: 0 on success, -ENODEV on failure.
*/
static int parse_devicetree(struct device_node *node,
struct msm_ipc_router_hsic_xprt_config *hsic_xprt_config)
{
int ret;
int link_id;
int version;
char *key;
const char *ch_name;
const char *remote_ss;
key = "qcom,ch-name";
ch_name = of_get_property(node, key, NULL);
if (!ch_name)
goto error;
strlcpy(hsic_xprt_config->ch_name, ch_name, XPRT_NAME_LEN);
key = "qcom,xprt-remote";
remote_ss = of_get_property(node, key, NULL);
if (!remote_ss)
goto error;
key = "qcom,xprt-linkid";
ret = of_property_read_u32(node, key, &link_id);
if (ret)
goto error;
hsic_xprt_config->link_id = link_id;
key = "qcom,xprt-version";
ret = of_property_read_u32(node, key, &version);
if (ret)
goto error;
hsic_xprt_config->xprt_version = version;
scnprintf(hsic_xprt_config->xprt_name, XPRT_NAME_LEN, "%s_%s",
remote_ss, hsic_xprt_config->ch_name);
return 0;
error:
pr_err("%s: missing key: %s\n", __func__, key);
return -ENODEV;
}
/**
* msm_ipc_router_hsic_xprt_probe() - Probe an HSIC xprt
* @pdev: Platform device corresponding to HSIC xprt.
*
* @return: 0 on success, standard Linux error codes on error.
*
* This function is called when the underlying device tree driver registers
* a platform device, mapped to an HSIC transport.
*/
static int msm_ipc_router_hsic_xprt_probe(
struct platform_device *pdev)
{
int ret;
struct msm_ipc_router_hsic_xprt_config hsic_xprt_config;
if (pdev && pdev->dev.of_node) {
mutex_lock(&hsic_remote_xprt_list_lock_lha1);
ipc_router_hsic_xprt_probe_done = 1;
mutex_unlock(&hsic_remote_xprt_list_lock_lha1);
ret = parse_devicetree(pdev->dev.of_node,
&hsic_xprt_config);
if (ret) {
pr_err(" failed to parse device tree\n");
return ret;
}
ret = msm_ipc_router_hsic_config_init(
&hsic_xprt_config);
if (ret) {
pr_err(" %s init failed\n", __func__);
return ret;
}
}
return ret;
}
/**
* ipc_router_hsic_xprt_probe_worker() - probe worker for non DT configurations
*
* @work: work item to process
*
* This function is called by schedule_delay_work after 3sec and check if
* device tree probe is done or not. If device tree probe fails the default
* configurations read from static array.
*/
static void ipc_router_hsic_xprt_probe_worker(struct work_struct *work)
{
int i, ret;
BUG_ON(ARRAY_SIZE(hsic_xprt_cfg) != NUM_HSIC_XPRTS);
mutex_lock(&hsic_remote_xprt_list_lock_lha1);
if (!ipc_router_hsic_xprt_probe_done) {
mutex_unlock(&hsic_remote_xprt_list_lock_lha1);
for (i = 0; i < ARRAY_SIZE(hsic_xprt_cfg); i++) {
ret = msm_ipc_router_hsic_config_init(
&hsic_xprt_cfg[i]);
if (ret)
pr_err(" %s init failed config idx %d\n",
__func__, i);
}
mutex_lock(&hsic_remote_xprt_list_lock_lha1);
}
mutex_unlock(&hsic_remote_xprt_list_lock_lha1);
}
static struct of_device_id msm_ipc_router_hsic_xprt_match_table[] = {
{ .compatible = "qcom,ipc_router_hsic_xprt" },
{},
};
static struct platform_driver msm_ipc_router_hsic_xprt_driver = {
.probe = msm_ipc_router_hsic_xprt_probe,
.driver = {
.name = MODULE_NAME,
.owner = THIS_MODULE,
.of_match_table = msm_ipc_router_hsic_xprt_match_table,
},
};
static int __init msm_ipc_router_hsic_xprt_init(void)
{
int rc;
rc = platform_driver_register(&msm_ipc_router_hsic_xprt_driver);
if (rc) {
pr_err("%s: msm_ipc_router_hsic_xprt_driver register failed %d\n",
__func__, rc);
return rc;
}
INIT_DELAYED_WORK(&ipc_router_hsic_xprt_probe_work,
ipc_router_hsic_xprt_probe_worker);
schedule_delayed_work(&ipc_router_hsic_xprt_probe_work,
msecs_to_jiffies(IPC_ROUTER_HSIC_XPRT_WAIT_TIMEOUT));
return 0;
}
module_init(msm_ipc_router_hsic_xprt_init);
MODULE_DESCRIPTION("IPC Router HSIC XPRT");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
lanxy88/lanxy88-shooterplayer | Thirdparty/openssl-0.9.8x/crypto/asn1/tasn_prn.c | 98 | 6992 | /* tasn_prn.c */
/* Written by Dr Stephen N Henson (steve@openssl.org) for the OpenSSL
* project 2000.
*/
/* ====================================================================
* Copyright (c) 2000 The OpenSSL Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* 3. All advertising materials mentioning features or use of this
* software must display the following acknowledgment:
* "This product includes software developed by the OpenSSL Project
* for use in the OpenSSL Toolkit. (http://www.OpenSSL.org/)"
*
* 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
* endorse or promote products derived from this software without
* prior written permission. For written permission, please contact
* licensing@OpenSSL.org.
*
* 5. Products derived from this software may not be called "OpenSSL"
* nor may "OpenSSL" appear in their names without prior written
* permission of the OpenSSL Project.
*
* 6. Redistributions of any form whatsoever must retain the following
* acknowledgment:
* "This product includes software developed by the OpenSSL Project
* for use in the OpenSSL Toolkit (http://www.OpenSSL.org/)"
*
* THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
* EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR
* ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
* ====================================================================
*
* This product includes cryptographic software written by Eric Young
* (eay@cryptsoft.com). This product includes software written by Tim
* Hudson (tjh@cryptsoft.com).
*
*/
#include <stddef.h>
#include <openssl/asn1.h>
#include <openssl/objects.h>
#include <openssl/buffer.h>
#include <openssl/err.h>
#include <openssl/nasn.h>
/* Print routines. Print out a whole structure from a template.
*/
static int asn1_item_print_nm(BIO *out, void *fld, int indent, const ASN1_ITEM *it, const char *name);
int ASN1_item_print(BIO *out, void *fld, int indent, const ASN1_ITEM *it)
{
return asn1_item_print_nm(out, fld, indent, it, it->sname);
}
static int asn1_item_print_nm(BIO *out, void *fld, int indent, const ASN1_ITEM *it, const char *name)
{
ASN1_STRING *str;
const ASN1_TEMPLATE *tt;
void *tmpfld;
int i;
if(!fld) {
BIO_printf(out, "%*s%s ABSENT\n", indent, "", name);
return 1;
}
switch(it->itype) {
case ASN1_ITYPE_PRIMITIVE:
if(it->templates)
return ASN1_template_print(out, fld, indent, it->templates);
return asn1_primitive_print(out, fld, it->utype, indent, name);
break;
case ASN1_ITYPE_MSTRING:
str = fld;
return asn1_primitive_print(out, fld, str->type, indent, name);
case ASN1_ITYPE_EXTERN:
BIO_printf(out, "%*s%s:EXTERNAL TYPE %s %s\n", indent, "", name, it->sname, fld ? "" : "ABSENT");
return 1;
case ASN1_ITYPE_COMPAT:
BIO_printf(out, "%*s%s:COMPATIBLE TYPE %s %s\n", indent, "", name, it->sname, fld ? "" : "ABSENT");
return 1;
case ASN1_ITYPE_CHOICE:
/* CHOICE type, get selector */
i = asn1_get_choice_selector(fld, it);
/* This should never happen... */
if((i < 0) || (i >= it->tcount)) {
BIO_printf(out, "%s selector [%d] out of range\n", it->sname, i);
return 1;
}
tt = it->templates + i;
tmpfld = asn1_get_field(fld, tt);
return ASN1_template_print(out, tmpfld, indent, tt);
case ASN1_ITYPE_SEQUENCE:
BIO_printf(out, "%*s%s {\n", indent, "", name);
/* Get each field entry */
for(i = 0, tt = it->templates; i < it->tcount; i++, tt++) {
tmpfld = asn1_get_field(fld, tt);
ASN1_template_print(out, tmpfld, indent + 2, tt);
}
BIO_printf(out, "%*s}\n", indent, "");
return 1;
default:
return 0;
}
}
int ASN1_template_print(BIO *out, void *fld, int indent, const ASN1_TEMPLATE *tt)
{
int i, flags;
#if 0
if(!fld) return 0;
#endif
flags = tt->flags;
if(flags & ASN1_TFLG_SK_MASK) {
char *tname;
void *skitem;
/* SET OF, SEQUENCE OF */
if(flags & ASN1_TFLG_SET_OF) tname = "SET";
else tname = "SEQUENCE";
if(fld) {
BIO_printf(out, "%*s%s OF %s {\n", indent, "", tname, tt->field_name);
for(i = 0; i < sk_num(fld); i++) {
skitem = sk_value(fld, i);
asn1_item_print_nm(out, skitem, indent + 2, tt->item, "");
}
BIO_printf(out, "%*s}\n", indent, "");
} else
BIO_printf(out, "%*s%s OF %s ABSENT\n", indent, "", tname, tt->field_name);
return 1;
}
return asn1_item_print_nm(out, fld, indent, tt->item, tt->field_name);
}
static int asn1_primitive_print(BIO *out, void *fld, long utype, int indent, const char *name)
{
ASN1_STRING *str = fld;
if(fld) {
if(utype == V_ASN1_BOOLEAN) {
int *bool = fld;
if(*bool == -1) printf("BOOL MISSING\n");
BIO_printf(out, "%*s%s:%s", indent, "", "BOOLEAN", *bool ? "TRUE" : "FALSE");
} else if((utype == V_ASN1_INTEGER)
|| (utype == V_ASN1_ENUMERATED)) {
char *s, *nm;
s = i2s_ASN1_INTEGER(NULL, fld);
if(utype == V_ASN1_INTEGER) nm = "INTEGER";
else nm = "ENUMERATED";
BIO_printf(out, "%*s%s:%s", indent, "", nm, s);
OPENSSL_free(s);
} else if(utype == V_ASN1_NULL) {
BIO_printf(out, "%*s%s", indent, "", "NULL");
} else if(utype == V_ASN1_UTCTIME) {
BIO_printf(out, "%*s%s:%s:", indent, "", name, "UTCTIME");
ASN1_UTCTIME_print(out, str);
} else if(utype == V_ASN1_GENERALIZEDTIME) {
BIO_printf(out, "%*s%s:%s:", indent, "", name, "GENERALIZEDTIME");
ASN1_GENERALIZEDTIME_print(out, str);
} else if(utype == V_ASN1_OBJECT) {
char objbuf[80], *ln;
ln = OBJ_nid2ln(OBJ_obj2nid(fld));
if(!ln) ln = "";
OBJ_obj2txt(objbuf, sizeof objbuf, fld, 1);
BIO_printf(out, "%*s%s:%s (%s)", indent, "", "OBJECT", ln, objbuf);
} else {
BIO_printf(out, "%*s%s:", indent, "", name);
ASN1_STRING_print_ex(out, str, ASN1_STRFLGS_DUMP_UNKNOWN|ASN1_STRFLGS_SHOW_TYPE);
}
BIO_printf(out, "\n");
} else BIO_printf(out, "%*s%s [ABSENT]\n", indent, "", name);
return 1;
}
| gpl-2.0 |
zarboz/Monarudo_M7_port | arch/arm/kernel/swp_emulate.c | 354 | 6465 | /*
* linux/arch/arm/kernel/swp_emulate.c
*
* Copyright (C) 2009 ARM Limited
* __user_* functions adapted from include/asm/uaccess.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Implements emulation of the SWP/SWPB instructions using load-exclusive and
* store-exclusive for processors that have them disabled (or future ones that
* might not implement them).
*
* Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
* Where: Rt = destination
* Rt2 = source
* Rn = address
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/proc_fs.h>
#include <linux/sched.h>
#include <linux/syscalls.h>
#include <linux/perf_event.h>
#include <asm/opcodes.h>
#include <asm/traps.h>
#include <asm/uaccess.h>
#define __user_swpX_asm(data, addr, res, temp, B) \
__asm__ __volatile__( \
" mov %2, %1\n" \
"0: ldrex"B" %1, [%3]\n" \
"1: strex"B" %0, %2, [%3]\n" \
" cmp %0, #0\n" \
" movne %0, %4\n" \
"2:\n" \
" .section .fixup,\"ax\"\n" \
" .align 2\n" \
"3: mov %0, %5\n" \
" b 2b\n" \
" .previous\n" \
" .section __ex_table,\"a\"\n" \
" .align 3\n" \
" .long 0b, 3b\n" \
" .long 1b, 3b\n" \
" .previous" \
: "=&r" (res), "+r" (data), "=&r" (temp) \
: "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \
: "cc", "memory")
#define __user_swp_asm(data, addr, res, temp) \
__user_swpX_asm(data, addr, res, temp, "")
#define __user_swpb_asm(data, addr, res, temp) \
__user_swpX_asm(data, addr, res, temp, "b")
#define EXTRACT_REG_NUM(instruction, offset) \
(((instruction) & (0xf << (offset))) >> (offset))
#define RN_OFFSET 16
#define RT_OFFSET 12
#define RT2_OFFSET 0
#define TYPE_SWPB (1 << 22)
static unsigned long swpcounter;
static unsigned long swpbcounter;
static unsigned long abtcounter;
static pid_t previous_pid;
#ifdef CONFIG_PROC_FS
static int proc_read_status(char *page, char **start, off_t off, int count,
int *eof, void *data)
{
char *p = page;
int len;
p += sprintf(p, "Emulated SWP:\t\t%lu\n", swpcounter);
p += sprintf(p, "Emulated SWPB:\t\t%lu\n", swpbcounter);
p += sprintf(p, "Aborted SWP{B}:\t\t%lu\n", abtcounter);
if (previous_pid != 0)
p += sprintf(p, "Last process:\t\t%d\n", previous_pid);
len = (p - page) - off;
if (len < 0)
len = 0;
*eof = (len <= count) ? 1 : 0;
*start = page + off;
return len;
}
#endif
static void set_segfault(struct pt_regs *regs, unsigned long addr)
{
siginfo_t info;
if (find_vma(current->mm, addr) == NULL)
info.si_code = SEGV_MAPERR;
else
info.si_code = SEGV_ACCERR;
info.si_signo = SIGSEGV;
info.si_errno = 0;
info.si_addr = (void *) instruction_pointer(regs);
pr_debug("SWP{B} emulation: access caused memory abort!\n");
arm_notify_die("Illegal memory access", regs, &info, 0, 0);
abtcounter++;
}
static int emulate_swpX(unsigned int address, unsigned int *data,
unsigned int type)
{
unsigned int res = 0;
if ((type != TYPE_SWPB) && (address & 0x3)) {
pr_debug("SWP instruction on unaligned pointer!\n");
return -EFAULT;
}
while (1) {
unsigned long temp;
smp_mb();
if (type == TYPE_SWPB)
__user_swpb_asm(*data, address, res, temp);
else
__user_swp_asm(*data, address, res, temp);
if (likely(res != -EAGAIN) || signal_pending(current))
break;
cond_resched();
}
if (res == 0) {
smp_mb();
if (type == TYPE_SWPB)
swpbcounter++;
else
swpcounter++;
}
return res;
}
static int check_condition(struct pt_regs *regs, unsigned int insn)
{
unsigned int base_cond, neg, cond = 0;
unsigned int cpsr_z, cpsr_c, cpsr_n, cpsr_v;
cpsr_n = (regs->ARM_cpsr & PSR_N_BIT) ? 1 : 0;
cpsr_z = (regs->ARM_cpsr & PSR_Z_BIT) ? 1 : 0;
cpsr_c = (regs->ARM_cpsr & PSR_C_BIT) ? 1 : 0;
cpsr_v = (regs->ARM_cpsr & PSR_V_BIT) ? 1 : 0;
base_cond = insn >> 29;
neg = insn & BIT(28) ? 1 : 0;
switch (base_cond) {
case 0x0:
cond = cpsr_z;
break;
case 0x1:
cond = cpsr_c;
break;
case 0x2:
cond = cpsr_n;
break;
case 0x3:
cond = cpsr_v;
break;
case 0x4:
cond = (cpsr_c == 1) && (cpsr_z == 0);
break;
case 0x5:
cond = (cpsr_n == cpsr_v);
break;
case 0x6:
cond = (cpsr_z == 0) && (cpsr_n == cpsr_v);
break;
case 0x7:
cond = 1;
break;
};
return cond && !neg;
}
static int swp_handler(struct pt_regs *regs, unsigned int instr)
{
unsigned int address, destreg, data, type;
unsigned int res = 0;
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->ARM_pc);
res = arm_check_condition(instr, regs->ARM_cpsr);
switch (res) {
case ARM_OPCODE_CONDTEST_PASS:
break;
case ARM_OPCODE_CONDTEST_FAIL:
regs->ARM_pc += 4;
return 0;
case ARM_OPCODE_CONDTEST_UNCOND:
return -EFAULT;
default:
return -EINVAL;
}
if (current->pid != previous_pid) {
pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n",
current->comm, (unsigned long)current->pid);
previous_pid = current->pid;
}
if (!check_condition(regs, instr)) {
regs->ARM_pc += 4;
return 0;
}
address = regs->uregs[EXTRACT_REG_NUM(instr, RN_OFFSET)];
data = regs->uregs[EXTRACT_REG_NUM(instr, RT2_OFFSET)];
destreg = EXTRACT_REG_NUM(instr, RT_OFFSET);
type = instr & TYPE_SWPB;
pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
EXTRACT_REG_NUM(instr, RN_OFFSET), address,
destreg, EXTRACT_REG_NUM(instr, RT2_OFFSET), data);
if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
pr_debug("SWP{B} emulation: access to %p not allowed!\n",
(void *)address);
res = -EFAULT;
} else {
res = emulate_swpX(address, &data, type);
}
if (res == 0) {
regs->ARM_pc += 4;
regs->uregs[destreg] = data;
} else if (res == -EFAULT) {
set_segfault(regs, address);
}
return 0;
}
static struct undef_hook swp_hook = {
.instr_mask = 0x0fb00ff0,
.instr_val = 0x01000090,
.cpsr_mask = MODE_MASK | PSR_T_BIT | PSR_J_BIT,
.cpsr_val = USR_MODE,
.fn = swp_handler
};
static int __init swp_emulation_init(void)
{
#ifdef CONFIG_PROC_FS
struct proc_dir_entry *res;
res = create_proc_entry("cpu/swp_emulation", S_IRUGO, NULL);
if (!res)
return -ENOMEM;
res->read_proc = proc_read_status;
#endif
printk(KERN_NOTICE "Registering SWP/SWPB emulation handler\n");
register_undef_hook(&swp_hook);
return 0;
}
late_initcall(swp_emulation_init);
| gpl-2.0 |
raiy/android_kernel_samsung_msm8660-common-1 | drivers/pci/pci-acpi.c | 1634 | 10641 | /*
* File: pci-acpi.c
* Purpose: Provide PCI support in ACPI
*
* Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com>
* Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com>
* Copyright (C) 2004 Intel Corp.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/pci-aspm.h>
#include <acpi/acpi.h>
#include <acpi/acpi_bus.h>
#include <linux/pci-acpi.h>
#include <linux/pm_runtime.h>
#include "pci.h"
static DEFINE_MUTEX(pci_acpi_pm_notify_mtx);
/**
* pci_acpi_wake_bus - Wake-up notification handler for root buses.
* @handle: ACPI handle of a device the notification is for.
* @event: Type of the signaled event.
* @context: PCI root bus to wake up devices on.
*/
static void pci_acpi_wake_bus(acpi_handle handle, u32 event, void *context)
{
struct pci_bus *pci_bus = context;
if (event == ACPI_NOTIFY_DEVICE_WAKE && pci_bus)
pci_pme_wakeup_bus(pci_bus);
}
/**
* pci_acpi_wake_dev - Wake-up notification handler for PCI devices.
* @handle: ACPI handle of a device the notification is for.
* @event: Type of the signaled event.
* @context: PCI device object to wake up.
*/
static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context)
{
struct pci_dev *pci_dev = context;
if (event == ACPI_NOTIFY_DEVICE_WAKE && pci_dev) {
pci_wakeup_event(pci_dev);
pci_check_pme_status(pci_dev);
pm_runtime_resume(&pci_dev->dev);
if (pci_dev->subordinate)
pci_pme_wakeup_bus(pci_dev->subordinate);
}
}
/**
* add_pm_notifier - Register PM notifier for given ACPI device.
* @dev: ACPI device to add the notifier for.
* @context: PCI device or bus to check for PME status if an event is signaled.
*
* NOTE: @dev need not be a run-wake or wake-up device to be a valid source of
* PM wake-up events. For example, wake-up events may be generated for bridges
* if one of the devices below the bridge is signaling PME, even if the bridge
* itself doesn't have a wake-up GPE associated with it.
*/
static acpi_status add_pm_notifier(struct acpi_device *dev,
acpi_notify_handler handler,
void *context)
{
acpi_status status = AE_ALREADY_EXISTS;
mutex_lock(&pci_acpi_pm_notify_mtx);
if (dev->wakeup.flags.notifier_present)
goto out;
status = acpi_install_notify_handler(dev->handle,
ACPI_SYSTEM_NOTIFY,
handler, context);
if (ACPI_FAILURE(status))
goto out;
dev->wakeup.flags.notifier_present = true;
out:
mutex_unlock(&pci_acpi_pm_notify_mtx);
return status;
}
/**
* remove_pm_notifier - Unregister PM notifier from given ACPI device.
* @dev: ACPI device to remove the notifier from.
*/
static acpi_status remove_pm_notifier(struct acpi_device *dev,
acpi_notify_handler handler)
{
acpi_status status = AE_BAD_PARAMETER;
mutex_lock(&pci_acpi_pm_notify_mtx);
if (!dev->wakeup.flags.notifier_present)
goto out;
status = acpi_remove_notify_handler(dev->handle,
ACPI_SYSTEM_NOTIFY,
handler);
if (ACPI_FAILURE(status))
goto out;
dev->wakeup.flags.notifier_present = false;
out:
mutex_unlock(&pci_acpi_pm_notify_mtx);
return status;
}
/**
* pci_acpi_add_bus_pm_notifier - Register PM notifier for given PCI bus.
* @dev: ACPI device to add the notifier for.
* @pci_bus: PCI bus to walk checking for PME status if an event is signaled.
*/
acpi_status pci_acpi_add_bus_pm_notifier(struct acpi_device *dev,
struct pci_bus *pci_bus)
{
return add_pm_notifier(dev, pci_acpi_wake_bus, pci_bus);
}
/**
* pci_acpi_remove_bus_pm_notifier - Unregister PCI bus PM notifier.
* @dev: ACPI device to remove the notifier from.
*/
acpi_status pci_acpi_remove_bus_pm_notifier(struct acpi_device *dev)
{
return remove_pm_notifier(dev, pci_acpi_wake_bus);
}
/**
* pci_acpi_add_pm_notifier - Register PM notifier for given PCI device.
* @dev: ACPI device to add the notifier for.
* @pci_dev: PCI device to check for the PME status if an event is signaled.
*/
acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
struct pci_dev *pci_dev)
{
return add_pm_notifier(dev, pci_acpi_wake_dev, pci_dev);
}
/**
* pci_acpi_remove_pm_notifier - Unregister PCI device PM notifier.
* @dev: ACPI device to remove the notifier from.
*/
acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
{
return remove_pm_notifier(dev, pci_acpi_wake_dev);
}
/*
* _SxD returns the D-state with the highest power
* (lowest D-state number) supported in the S-state "x".
*
* If the devices does not have a _PRW
* (Power Resources for Wake) supporting system wakeup from "x"
* then the OS is free to choose a lower power (higher number
* D-state) than the return value from _SxD.
*
* But if _PRW is enabled at S-state "x", the OS
* must not choose a power lower than _SxD --
* unless the device has an _SxW method specifying
* the lowest power (highest D-state number) the device
* may enter while still able to wake the system.
*
* ie. depending on global OS policy:
*
* if (_PRW at S-state x)
* choose from highest power _SxD to lowest power _SxW
* else // no _PRW at S-state x
* choose highest power _SxD or any lower power
*/
static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
{
int acpi_state;
acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL);
if (acpi_state < 0)
return PCI_POWER_ERROR;
switch (acpi_state) {
case ACPI_STATE_D0:
return PCI_D0;
case ACPI_STATE_D1:
return PCI_D1;
case ACPI_STATE_D2:
return PCI_D2;
case ACPI_STATE_D3:
return PCI_D3hot;
case ACPI_STATE_D3_COLD:
return PCI_D3cold;
}
return PCI_POWER_ERROR;
}
static bool acpi_pci_power_manageable(struct pci_dev *dev)
{
acpi_handle handle = DEVICE_ACPI_HANDLE(&dev->dev);
return handle ? acpi_bus_power_manageable(handle) : false;
}
static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
{
acpi_handle handle = DEVICE_ACPI_HANDLE(&dev->dev);
acpi_handle tmp;
static const u8 state_conv[] = {
[PCI_D0] = ACPI_STATE_D0,
[PCI_D1] = ACPI_STATE_D1,
[PCI_D2] = ACPI_STATE_D2,
[PCI_D3hot] = ACPI_STATE_D3,
[PCI_D3cold] = ACPI_STATE_D3
};
int error = -EINVAL;
/* If the ACPI device has _EJ0, ignore the device */
if (!handle || ACPI_SUCCESS(acpi_get_handle(handle, "_EJ0", &tmp)))
return -ENODEV;
switch (state) {
case PCI_D0:
case PCI_D1:
case PCI_D2:
case PCI_D3hot:
case PCI_D3cold:
error = acpi_bus_set_power(handle, state_conv[state]);
}
if (!error)
dev_printk(KERN_INFO, &dev->dev,
"power state changed by ACPI to D%d\n", state);
return error;
}
static bool acpi_pci_can_wakeup(struct pci_dev *dev)
{
acpi_handle handle = DEVICE_ACPI_HANDLE(&dev->dev);
return handle ? acpi_bus_can_wakeup(handle) : false;
}
static void acpi_pci_propagate_wakeup_enable(struct pci_bus *bus, bool enable)
{
while (bus->parent) {
if (!acpi_pm_device_sleep_wake(&bus->self->dev, enable))
return;
bus = bus->parent;
}
/* We have reached the root bus. */
if (bus->bridge)
acpi_pm_device_sleep_wake(bus->bridge, enable);
}
static int acpi_pci_sleep_wake(struct pci_dev *dev, bool enable)
{
if (acpi_pci_can_wakeup(dev))
return acpi_pm_device_sleep_wake(&dev->dev, enable);
acpi_pci_propagate_wakeup_enable(dev->bus, enable);
return 0;
}
/**
* acpi_dev_run_wake - Enable/disable wake-up for given device.
* @phys_dev: Device to enable/disable the platform to wake-up the system for.
* @enable: Whether enable or disable the wake-up functionality.
*
* Find the ACPI device object corresponding to @pci_dev and try to
* enable/disable the GPE associated with it.
*/
static int acpi_dev_run_wake(struct device *phys_dev, bool enable)
{
struct acpi_device *dev;
acpi_handle handle;
int error = -ENODEV;
if (!device_run_wake(phys_dev))
return -EINVAL;
handle = DEVICE_ACPI_HANDLE(phys_dev);
if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &dev))) {
dev_dbg(phys_dev, "ACPI handle has no context in %s!\n",
__func__);
return -ENODEV;
}
if (enable) {
acpi_enable_wakeup_device_power(dev, ACPI_STATE_S0);
acpi_enable_gpe(dev->wakeup.gpe_device, dev->wakeup.gpe_number);
} else {
acpi_disable_gpe(dev->wakeup.gpe_device, dev->wakeup.gpe_number);
acpi_disable_wakeup_device_power(dev);
}
return error;
}
static void acpi_pci_propagate_run_wake(struct pci_bus *bus, bool enable)
{
while (bus->parent) {
struct pci_dev *bridge = bus->self;
if (bridge->pme_interrupt)
return;
if (!acpi_dev_run_wake(&bridge->dev, enable))
return;
bus = bus->parent;
}
/* We have reached the root bus. */
if (bus->bridge)
acpi_dev_run_wake(bus->bridge, enable);
}
static int acpi_pci_run_wake(struct pci_dev *dev, bool enable)
{
if (dev->pme_interrupt)
return 0;
if (!acpi_dev_run_wake(&dev->dev, enable))
return 0;
acpi_pci_propagate_run_wake(dev->bus, enable);
return 0;
}
static struct pci_platform_pm_ops acpi_pci_platform_pm = {
.is_manageable = acpi_pci_power_manageable,
.set_state = acpi_pci_set_power_state,
.choose_state = acpi_pci_choose_state,
.can_wakeup = acpi_pci_can_wakeup,
.sleep_wake = acpi_pci_sleep_wake,
.run_wake = acpi_pci_run_wake,
};
/* ACPI bus type */
static int acpi_pci_find_device(struct device *dev, acpi_handle *handle)
{
struct pci_dev * pci_dev;
u64 addr;
pci_dev = to_pci_dev(dev);
/* Please ref to ACPI spec for the syntax of _ADR */
addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn);
*handle = acpi_get_child(DEVICE_ACPI_HANDLE(dev->parent), addr);
if (!*handle)
return -ENODEV;
return 0;
}
static int acpi_pci_find_root_bridge(struct device *dev, acpi_handle *handle)
{
int num;
unsigned int seg, bus;
/*
* The string should be the same as root bridge's name
* Please look at 'pci_scan_bus_parented'
*/
num = sscanf(dev_name(dev), "pci%04x:%02x", &seg, &bus);
if (num != 2)
return -ENODEV;
*handle = acpi_get_pci_rootbridge_handle(seg, bus);
if (!*handle)
return -ENODEV;
return 0;
}
static struct acpi_bus_type acpi_pci_bus = {
.bus = &pci_bus_type,
.find_device = acpi_pci_find_device,
.find_bridge = acpi_pci_find_root_bridge,
};
static int __init acpi_pci_init(void)
{
int ret;
if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) {
printk(KERN_INFO"ACPI FADT declares the system doesn't support MSI, so disable it\n");
pci_no_msi();
}
if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
printk(KERN_INFO"ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
pcie_no_aspm();
}
ret = register_acpi_bus_type(&acpi_pci_bus);
if (ret)
return 0;
pci_set_platform_pm(&acpi_pci_platform_pm);
return 0;
}
arch_initcall(acpi_pci_init);
| gpl-2.0 |
AOSP-YU/platform_kernel_cyanogen_msm8916 | drivers/staging/bcm/vendorspecificextn.c | 2146 | 4466 | #include "headers.h"
//-----------------------------------------------------------------------------
// Procedure: vendorextnGetSectionInfo
//
// Description: Finds the type of NVM used.
//
// Arguments:
// Adapter - ptr to Adapter object instance
// pNVMType - ptr to NVM type.
// Returns:
// STATUS_SUCCESS/STATUS_FAILURE
//
//-----------------------------------------------------------------------------
INT vendorextnGetSectionInfo(PVOID pContext, struct bcm_flash2x_vendor_info *pVendorInfo)
{
return STATUS_FAILURE;
}
//-----------------------------------------------------------------------------
// Procedure: vendorextnInit
//
// Description: Initializing the vendor extension NVM interface
//
// Arguments:
// Adapter - Pointer to MINI Adapter Structure.
// Returns:
// STATUS_SUCCESS/STATUS_FAILURE
//
//-----------------------------------------------------------------------------
INT vendorextnInit(struct bcm_mini_adapter *Adapter)
{
return STATUS_SUCCESS;
}
//-----------------------------------------------------------------------------
// Procedure: vendorextnExit
//
// Description: Free the resource associated with vendor extension NVM interface
//
// Arguments:
// Adapter - Pointer to MINI Adapter Structure.
// Returns:
// STATUS_SUCCESS/STATUS_FAILURE
//
//-----------------------------------------------------------------------------
INT vendorextnExit(struct bcm_mini_adapter *Adapter)
{
return STATUS_SUCCESS;
}
//------------------------------------------------------------------------
// Procedure: vendorextnIoctl
//
// Description: execute the vendor extension specific ioctl
//
//Arguments:
// Adapter -Beceem private Adapter Structure
// cmd -vendor extension specific Ioctl commad
// arg -input parameter sent by vendor
//
// Returns:
// CONTINUE_COMMON_PATH in case it is not meant to be processed by vendor ioctls
// STATUS_SUCCESS/STATUS_FAILURE as per the IOCTL return value
//
//--------------------------------------------------------------------------
INT vendorextnIoctl(struct bcm_mini_adapter *Adapter, UINT cmd, ULONG arg)
{
return CONTINUE_COMMON_PATH;
}
//------------------------------------------------------------------
// Procedure: vendorextnReadSection
//
// Description: Reads from a section of NVM
//
// Arguments:
// pContext - ptr to Adapter object instance
// pBuffer - Read the data from Vendor Area to this buffer
// SectionVal - Value of type of Section
// Offset - Read from the Offset of the Vendor Section.
// numOfBytes - Read numOfBytes from the Vendor section to Buffer
//
// Returns:
// STATUS_SUCCESS/STATUS_FAILURE
//
//------------------------------------------------------------------
INT vendorextnReadSection(PVOID pContext, PUCHAR pBuffer, enum bcm_flash2x_section_val SectionVal,
UINT offset, UINT numOfBytes)
{
return STATUS_FAILURE;
}
//------------------------------------------------------------------
// Procedure: vendorextnWriteSection
//
// Description: Write to a Section of NVM
//
// Arguments:
// pContext - ptr to Adapter object instance
// pBuffer - Write the data provided in the buffer
// SectionVal - Value of type of Section
// Offset - Writes to the Offset of the Vendor Section.
// numOfBytes - Write num Bytes after reading from pBuffer.
// bVerify - the Buffer Written should be verified.
//
// Returns:
// STATUS_SUCCESS/STATUS_FAILURE
//
//------------------------------------------------------------------
INT vendorextnWriteSection(PVOID pContext, PUCHAR pBuffer, enum bcm_flash2x_section_val SectionVal,
UINT offset, UINT numOfBytes, BOOLEAN bVerify)
{
return STATUS_FAILURE;
}
//------------------------------------------------------------------
// Procedure: vendorextnWriteSectionWithoutErase
//
// Description: Write to a Section of NVM without erasing the sector
//
// Arguments:
// pContext - ptr to Adapter object instance
// pBuffer - Write the data provided in the buffer
// SectionVal - Value of type of Section
// Offset - Writes to the Offset of the Vendor Section.
// numOfBytes - Write num Bytes after reading from pBuffer.
//
// Returns:
// STATUS_SUCCESS/STATUS_FAILURE
//
//------------------------------------------------------------------
INT vendorextnWriteSectionWithoutErase(PVOID pContext, PUCHAR pBuffer, enum bcm_flash2x_section_val SectionVal,
UINT offset, UINT numOfBytes)
{
return STATUS_FAILURE;
}
| gpl-2.0 |
Altaf-Mahdi/android_kernel_oneplus_msm8994 | net/netfilter/nf_conntrack_proto.c | 2146 | 13030 | /* L3/L4 protocol support for nf_conntrack. */
/* (C) 1999-2001 Paul `Rusty' Russell
* (C) 2002-2006 Netfilter Core Team <coreteam@netfilter.org>
* (C) 2003,2004 USAGI/WIDE Project <http://www.linux-ipv6.org>
* (C) 2006-2012 Patrick McHardy <kaber@trash.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/netfilter.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/vmalloc.h>
#include <linux/stddef.h>
#include <linux/err.h>
#include <linux/percpu.h>
#include <linux/notifier.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <net/netfilter/nf_conntrack.h>
#include <net/netfilter/nf_conntrack_l3proto.h>
#include <net/netfilter/nf_conntrack_l4proto.h>
#include <net/netfilter/nf_conntrack_core.h>
static struct nf_conntrack_l4proto __rcu **nf_ct_protos[PF_MAX] __read_mostly;
struct nf_conntrack_l3proto __rcu *nf_ct_l3protos[AF_MAX] __read_mostly;
EXPORT_SYMBOL_GPL(nf_ct_l3protos);
static DEFINE_MUTEX(nf_ct_proto_mutex);
#ifdef CONFIG_SYSCTL
static int
nf_ct_register_sysctl(struct net *net,
struct ctl_table_header **header,
const char *path,
struct ctl_table *table)
{
if (*header == NULL) {
*header = register_net_sysctl(net, path, table);
if (*header == NULL)
return -ENOMEM;
}
return 0;
}
static void
nf_ct_unregister_sysctl(struct ctl_table_header **header,
struct ctl_table **table,
unsigned int users)
{
if (users > 0)
return;
unregister_net_sysctl_table(*header);
kfree(*table);
*header = NULL;
*table = NULL;
}
#endif
struct nf_conntrack_l4proto *
__nf_ct_l4proto_find(u_int16_t l3proto, u_int8_t l4proto)
{
if (unlikely(l3proto >= AF_MAX || nf_ct_protos[l3proto] == NULL))
return &nf_conntrack_l4proto_generic;
return rcu_dereference(nf_ct_protos[l3proto][l4proto]);
}
EXPORT_SYMBOL_GPL(__nf_ct_l4proto_find);
/* this is guaranteed to always return a valid protocol helper, since
* it falls back to generic_protocol */
struct nf_conntrack_l3proto *
nf_ct_l3proto_find_get(u_int16_t l3proto)
{
struct nf_conntrack_l3proto *p;
rcu_read_lock();
p = __nf_ct_l3proto_find(l3proto);
if (!try_module_get(p->me))
p = &nf_conntrack_l3proto_generic;
rcu_read_unlock();
return p;
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_find_get);
void nf_ct_l3proto_put(struct nf_conntrack_l3proto *p)
{
module_put(p->me);
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_put);
int
nf_ct_l3proto_try_module_get(unsigned short l3proto)
{
int ret;
struct nf_conntrack_l3proto *p;
retry: p = nf_ct_l3proto_find_get(l3proto);
if (p == &nf_conntrack_l3proto_generic) {
ret = request_module("nf_conntrack-%d", l3proto);
if (!ret)
goto retry;
return -EPROTOTYPE;
}
return 0;
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_try_module_get);
void nf_ct_l3proto_module_put(unsigned short l3proto)
{
struct nf_conntrack_l3proto *p;
/* rcu_read_lock not necessary since the caller holds a reference, but
* taken anyways to avoid lockdep warnings in __nf_ct_l3proto_find()
*/
rcu_read_lock();
p = __nf_ct_l3proto_find(l3proto);
module_put(p->me);
rcu_read_unlock();
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_module_put);
struct nf_conntrack_l4proto *
nf_ct_l4proto_find_get(u_int16_t l3num, u_int8_t l4num)
{
struct nf_conntrack_l4proto *p;
rcu_read_lock();
p = __nf_ct_l4proto_find(l3num, l4num);
if (!try_module_get(p->me))
p = &nf_conntrack_l4proto_generic;
rcu_read_unlock();
return p;
}
EXPORT_SYMBOL_GPL(nf_ct_l4proto_find_get);
void nf_ct_l4proto_put(struct nf_conntrack_l4proto *p)
{
module_put(p->me);
}
EXPORT_SYMBOL_GPL(nf_ct_l4proto_put);
static int kill_l3proto(struct nf_conn *i, void *data)
{
return nf_ct_l3num(i) == ((struct nf_conntrack_l3proto *)data)->l3proto;
}
static int kill_l4proto(struct nf_conn *i, void *data)
{
struct nf_conntrack_l4proto *l4proto;
l4proto = (struct nf_conntrack_l4proto *)data;
return nf_ct_protonum(i) == l4proto->l4proto &&
nf_ct_l3num(i) == l4proto->l3proto;
}
static struct nf_ip_net *nf_ct_l3proto_net(struct net *net,
struct nf_conntrack_l3proto *l3proto)
{
if (l3proto->l3proto == PF_INET)
return &net->ct.nf_ct_proto;
else
return NULL;
}
static int nf_ct_l3proto_register_sysctl(struct net *net,
struct nf_conntrack_l3proto *l3proto)
{
int err = 0;
struct nf_ip_net *in = nf_ct_l3proto_net(net, l3proto);
/* nf_conntrack_l3proto_ipv6 doesn't support sysctl */
if (in == NULL)
return 0;
#if defined(CONFIG_SYSCTL) && defined(CONFIG_NF_CONNTRACK_PROC_COMPAT)
if (in->ctl_table != NULL) {
err = nf_ct_register_sysctl(net,
&in->ctl_table_header,
l3proto->ctl_table_path,
in->ctl_table);
if (err < 0) {
kfree(in->ctl_table);
in->ctl_table = NULL;
}
}
#endif
return err;
}
static void nf_ct_l3proto_unregister_sysctl(struct net *net,
struct nf_conntrack_l3proto *l3proto)
{
struct nf_ip_net *in = nf_ct_l3proto_net(net, l3proto);
if (in == NULL)
return;
#if defined(CONFIG_SYSCTL) && defined(CONFIG_NF_CONNTRACK_PROC_COMPAT)
if (in->ctl_table_header != NULL)
nf_ct_unregister_sysctl(&in->ctl_table_header,
&in->ctl_table,
0);
#endif
}
int nf_ct_l3proto_register(struct nf_conntrack_l3proto *proto)
{
int ret = 0;
struct nf_conntrack_l3proto *old;
if (proto->l3proto >= AF_MAX)
return -EBUSY;
if (proto->tuple_to_nlattr && !proto->nlattr_tuple_size)
return -EINVAL;
mutex_lock(&nf_ct_proto_mutex);
old = rcu_dereference_protected(nf_ct_l3protos[proto->l3proto],
lockdep_is_held(&nf_ct_proto_mutex));
if (old != &nf_conntrack_l3proto_generic) {
ret = -EBUSY;
goto out_unlock;
}
if (proto->nlattr_tuple_size)
proto->nla_size = 3 * proto->nlattr_tuple_size();
rcu_assign_pointer(nf_ct_l3protos[proto->l3proto], proto);
out_unlock:
mutex_unlock(&nf_ct_proto_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_register);
int nf_ct_l3proto_pernet_register(struct net *net,
struct nf_conntrack_l3proto *proto)
{
int ret = 0;
if (proto->init_net) {
ret = proto->init_net(net);
if (ret < 0)
return ret;
}
return nf_ct_l3proto_register_sysctl(net, proto);
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_pernet_register);
void nf_ct_l3proto_unregister(struct nf_conntrack_l3proto *proto)
{
BUG_ON(proto->l3proto >= AF_MAX);
mutex_lock(&nf_ct_proto_mutex);
BUG_ON(rcu_dereference_protected(nf_ct_l3protos[proto->l3proto],
lockdep_is_held(&nf_ct_proto_mutex)
) != proto);
rcu_assign_pointer(nf_ct_l3protos[proto->l3proto],
&nf_conntrack_l3proto_generic);
mutex_unlock(&nf_ct_proto_mutex);
synchronize_rcu();
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_unregister);
void nf_ct_l3proto_pernet_unregister(struct net *net,
struct nf_conntrack_l3proto *proto)
{
nf_ct_l3proto_unregister_sysctl(net, proto);
/* Remove all contrack entries for this protocol */
nf_ct_iterate_cleanup(net, kill_l3proto, proto);
}
EXPORT_SYMBOL_GPL(nf_ct_l3proto_pernet_unregister);
static struct nf_proto_net *nf_ct_l4proto_net(struct net *net,
struct nf_conntrack_l4proto *l4proto)
{
if (l4proto->get_net_proto) {
/* statically built-in protocols use static per-net */
return l4proto->get_net_proto(net);
} else if (l4proto->net_id) {
/* ... and loadable protocols use dynamic per-net */
return net_generic(net, *l4proto->net_id);
}
return NULL;
}
static
int nf_ct_l4proto_register_sysctl(struct net *net,
struct nf_proto_net *pn,
struct nf_conntrack_l4proto *l4proto)
{
int err = 0;
#ifdef CONFIG_SYSCTL
if (pn->ctl_table != NULL) {
err = nf_ct_register_sysctl(net,
&pn->ctl_table_header,
"net/netfilter",
pn->ctl_table);
if (err < 0) {
if (!pn->users) {
kfree(pn->ctl_table);
pn->ctl_table = NULL;
}
}
}
#ifdef CONFIG_NF_CONNTRACK_PROC_COMPAT
if (l4proto->l3proto != AF_INET6 && pn->ctl_compat_table != NULL) {
if (err < 0) {
nf_ct_kfree_compat_sysctl_table(pn);
goto out;
}
err = nf_ct_register_sysctl(net,
&pn->ctl_compat_header,
"net/ipv4/netfilter",
pn->ctl_compat_table);
if (err == 0)
goto out;
nf_ct_kfree_compat_sysctl_table(pn);
nf_ct_unregister_sysctl(&pn->ctl_table_header,
&pn->ctl_table,
pn->users);
}
out:
#endif /* CONFIG_NF_CONNTRACK_PROC_COMPAT */
#endif /* CONFIG_SYSCTL */
return err;
}
static
void nf_ct_l4proto_unregister_sysctl(struct net *net,
struct nf_proto_net *pn,
struct nf_conntrack_l4proto *l4proto)
{
#ifdef CONFIG_SYSCTL
if (pn->ctl_table_header != NULL)
nf_ct_unregister_sysctl(&pn->ctl_table_header,
&pn->ctl_table,
pn->users);
#ifdef CONFIG_NF_CONNTRACK_PROC_COMPAT
if (l4proto->l3proto != AF_INET6 && pn->ctl_compat_header != NULL)
nf_ct_unregister_sysctl(&pn->ctl_compat_header,
&pn->ctl_compat_table,
0);
#endif /* CONFIG_NF_CONNTRACK_PROC_COMPAT */
#endif /* CONFIG_SYSCTL */
}
/* FIXME: Allow NULL functions and sub in pointers to generic for
them. --RR */
int nf_ct_l4proto_register(struct nf_conntrack_l4proto *l4proto)
{
int ret = 0;
if (l4proto->l3proto >= PF_MAX)
return -EBUSY;
if ((l4proto->to_nlattr && !l4proto->nlattr_size)
|| (l4proto->tuple_to_nlattr && !l4proto->nlattr_tuple_size))
return -EINVAL;
mutex_lock(&nf_ct_proto_mutex);
if (!nf_ct_protos[l4proto->l3proto]) {
/* l3proto may be loaded latter. */
struct nf_conntrack_l4proto __rcu **proto_array;
int i;
proto_array = kmalloc(MAX_NF_CT_PROTO *
sizeof(struct nf_conntrack_l4proto *),
GFP_KERNEL);
if (proto_array == NULL) {
ret = -ENOMEM;
goto out_unlock;
}
for (i = 0; i < MAX_NF_CT_PROTO; i++)
RCU_INIT_POINTER(proto_array[i], &nf_conntrack_l4proto_generic);
/* Before making proto_array visible to lockless readers,
* we must make sure its content is committed to memory.
*/
smp_wmb();
nf_ct_protos[l4proto->l3proto] = proto_array;
} else if (rcu_dereference_protected(
nf_ct_protos[l4proto->l3proto][l4proto->l4proto],
lockdep_is_held(&nf_ct_proto_mutex)
) != &nf_conntrack_l4proto_generic) {
ret = -EBUSY;
goto out_unlock;
}
l4proto->nla_size = 0;
if (l4proto->nlattr_size)
l4proto->nla_size += l4proto->nlattr_size();
if (l4proto->nlattr_tuple_size)
l4proto->nla_size += 3 * l4proto->nlattr_tuple_size();
rcu_assign_pointer(nf_ct_protos[l4proto->l3proto][l4proto->l4proto],
l4proto);
out_unlock:
mutex_unlock(&nf_ct_proto_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(nf_ct_l4proto_register);
int nf_ct_l4proto_pernet_register(struct net *net,
struct nf_conntrack_l4proto *l4proto)
{
int ret = 0;
struct nf_proto_net *pn = NULL;
if (l4proto->init_net) {
ret = l4proto->init_net(net, l4proto->l3proto);
if (ret < 0)
goto out;
}
pn = nf_ct_l4proto_net(net, l4proto);
if (pn == NULL)
goto out;
ret = nf_ct_l4proto_register_sysctl(net, pn, l4proto);
if (ret < 0)
goto out;
pn->users++;
out:
return ret;
}
EXPORT_SYMBOL_GPL(nf_ct_l4proto_pernet_register);
void nf_ct_l4proto_unregister(struct nf_conntrack_l4proto *l4proto)
{
BUG_ON(l4proto->l3proto >= PF_MAX);
mutex_lock(&nf_ct_proto_mutex);
BUG_ON(rcu_dereference_protected(
nf_ct_protos[l4proto->l3proto][l4proto->l4proto],
lockdep_is_held(&nf_ct_proto_mutex)
) != l4proto);
rcu_assign_pointer(nf_ct_protos[l4proto->l3proto][l4proto->l4proto],
&nf_conntrack_l4proto_generic);
mutex_unlock(&nf_ct_proto_mutex);
synchronize_rcu();
}
EXPORT_SYMBOL_GPL(nf_ct_l4proto_unregister);
void nf_ct_l4proto_pernet_unregister(struct net *net,
struct nf_conntrack_l4proto *l4proto)
{
struct nf_proto_net *pn = NULL;
pn = nf_ct_l4proto_net(net, l4proto);
if (pn == NULL)
return;
pn->users--;
nf_ct_l4proto_unregister_sysctl(net, pn, l4proto);
/* Remove all contrack entries for this protocol */
nf_ct_iterate_cleanup(net, kill_l4proto, l4proto);
}
EXPORT_SYMBOL_GPL(nf_ct_l4proto_pernet_unregister);
int nf_conntrack_proto_pernet_init(struct net *net)
{
int err;
struct nf_proto_net *pn = nf_ct_l4proto_net(net,
&nf_conntrack_l4proto_generic);
err = nf_conntrack_l4proto_generic.init_net(net,
nf_conntrack_l4proto_generic.l3proto);
if (err < 0)
return err;
err = nf_ct_l4proto_register_sysctl(net,
pn,
&nf_conntrack_l4proto_generic);
if (err < 0)
return err;
pn->users++;
return 0;
}
void nf_conntrack_proto_pernet_fini(struct net *net)
{
struct nf_proto_net *pn = nf_ct_l4proto_net(net,
&nf_conntrack_l4proto_generic);
pn->users--;
nf_ct_l4proto_unregister_sysctl(net,
pn,
&nf_conntrack_l4proto_generic);
}
int nf_conntrack_proto_init(void)
{
unsigned int i;
for (i = 0; i < AF_MAX; i++)
rcu_assign_pointer(nf_ct_l3protos[i],
&nf_conntrack_l3proto_generic);
return 0;
}
void nf_conntrack_proto_fini(void)
{
unsigned int i;
/* free l3proto protocol tables */
for (i = 0; i < PF_MAX; i++)
kfree(nf_ct_protos[i]);
}
| gpl-2.0 |
libcg/android_kernel_samsung_smdk4412_hwc | net/ceph/osdmap.c | 2402 | 27356 |
#include <linux/ceph/ceph_debug.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <asm/div64.h>
#include <linux/ceph/libceph.h>
#include <linux/ceph/osdmap.h>
#include <linux/ceph/decode.h>
#include <linux/crush/hash.h>
#include <linux/crush/mapper.h>
char *ceph_osdmap_state_str(char *str, int len, int state)
{
int flag = 0;
if (!len)
goto done;
*str = '\0';
if (state) {
if (state & CEPH_OSD_EXISTS) {
snprintf(str, len, "exists");
flag = 1;
}
if (state & CEPH_OSD_UP) {
snprintf(str, len, "%s%s%s", str, (flag ? ", " : ""),
"up");
flag = 1;
}
} else {
snprintf(str, len, "doesn't exist");
}
done:
return str;
}
/* maps */
static int calc_bits_of(unsigned t)
{
int b = 0;
while (t) {
t = t >> 1;
b++;
}
return b;
}
/*
* the foo_mask is the smallest value 2^n-1 that is >= foo.
*/
static void calc_pg_masks(struct ceph_pg_pool_info *pi)
{
pi->pg_num_mask = (1 << calc_bits_of(le32_to_cpu(pi->v.pg_num)-1)) - 1;
pi->pgp_num_mask =
(1 << calc_bits_of(le32_to_cpu(pi->v.pgp_num)-1)) - 1;
pi->lpg_num_mask =
(1 << calc_bits_of(le32_to_cpu(pi->v.lpg_num)-1)) - 1;
pi->lpgp_num_mask =
(1 << calc_bits_of(le32_to_cpu(pi->v.lpgp_num)-1)) - 1;
}
/*
* decode crush map
*/
static int crush_decode_uniform_bucket(void **p, void *end,
struct crush_bucket_uniform *b)
{
dout("crush_decode_uniform_bucket %p to %p\n", *p, end);
ceph_decode_need(p, end, (1+b->h.size) * sizeof(u32), bad);
b->item_weight = ceph_decode_32(p);
return 0;
bad:
return -EINVAL;
}
static int crush_decode_list_bucket(void **p, void *end,
struct crush_bucket_list *b)
{
int j;
dout("crush_decode_list_bucket %p to %p\n", *p, end);
b->item_weights = kcalloc(b->h.size, sizeof(u32), GFP_NOFS);
if (b->item_weights == NULL)
return -ENOMEM;
b->sum_weights = kcalloc(b->h.size, sizeof(u32), GFP_NOFS);
if (b->sum_weights == NULL)
return -ENOMEM;
ceph_decode_need(p, end, 2 * b->h.size * sizeof(u32), bad);
for (j = 0; j < b->h.size; j++) {
b->item_weights[j] = ceph_decode_32(p);
b->sum_weights[j] = ceph_decode_32(p);
}
return 0;
bad:
return -EINVAL;
}
static int crush_decode_tree_bucket(void **p, void *end,
struct crush_bucket_tree *b)
{
int j;
dout("crush_decode_tree_bucket %p to %p\n", *p, end);
ceph_decode_32_safe(p, end, b->num_nodes, bad);
b->node_weights = kcalloc(b->num_nodes, sizeof(u32), GFP_NOFS);
if (b->node_weights == NULL)
return -ENOMEM;
ceph_decode_need(p, end, b->num_nodes * sizeof(u32), bad);
for (j = 0; j < b->num_nodes; j++)
b->node_weights[j] = ceph_decode_32(p);
return 0;
bad:
return -EINVAL;
}
static int crush_decode_straw_bucket(void **p, void *end,
struct crush_bucket_straw *b)
{
int j;
dout("crush_decode_straw_bucket %p to %p\n", *p, end);
b->item_weights = kcalloc(b->h.size, sizeof(u32), GFP_NOFS);
if (b->item_weights == NULL)
return -ENOMEM;
b->straws = kcalloc(b->h.size, sizeof(u32), GFP_NOFS);
if (b->straws == NULL)
return -ENOMEM;
ceph_decode_need(p, end, 2 * b->h.size * sizeof(u32), bad);
for (j = 0; j < b->h.size; j++) {
b->item_weights[j] = ceph_decode_32(p);
b->straws[j] = ceph_decode_32(p);
}
return 0;
bad:
return -EINVAL;
}
static struct crush_map *crush_decode(void *pbyval, void *end)
{
struct crush_map *c;
int err = -EINVAL;
int i, j;
void **p = &pbyval;
void *start = pbyval;
u32 magic;
dout("crush_decode %p to %p len %d\n", *p, end, (int)(end - *p));
c = kzalloc(sizeof(*c), GFP_NOFS);
if (c == NULL)
return ERR_PTR(-ENOMEM);
ceph_decode_need(p, end, 4*sizeof(u32), bad);
magic = ceph_decode_32(p);
if (magic != CRUSH_MAGIC) {
pr_err("crush_decode magic %x != current %x\n",
(unsigned)magic, (unsigned)CRUSH_MAGIC);
goto bad;
}
c->max_buckets = ceph_decode_32(p);
c->max_rules = ceph_decode_32(p);
c->max_devices = ceph_decode_32(p);
c->device_parents = kcalloc(c->max_devices, sizeof(u32), GFP_NOFS);
if (c->device_parents == NULL)
goto badmem;
c->bucket_parents = kcalloc(c->max_buckets, sizeof(u32), GFP_NOFS);
if (c->bucket_parents == NULL)
goto badmem;
c->buckets = kcalloc(c->max_buckets, sizeof(*c->buckets), GFP_NOFS);
if (c->buckets == NULL)
goto badmem;
c->rules = kcalloc(c->max_rules, sizeof(*c->rules), GFP_NOFS);
if (c->rules == NULL)
goto badmem;
/* buckets */
for (i = 0; i < c->max_buckets; i++) {
int size = 0;
u32 alg;
struct crush_bucket *b;
ceph_decode_32_safe(p, end, alg, bad);
if (alg == 0) {
c->buckets[i] = NULL;
continue;
}
dout("crush_decode bucket %d off %x %p to %p\n",
i, (int)(*p-start), *p, end);
switch (alg) {
case CRUSH_BUCKET_UNIFORM:
size = sizeof(struct crush_bucket_uniform);
break;
case CRUSH_BUCKET_LIST:
size = sizeof(struct crush_bucket_list);
break;
case CRUSH_BUCKET_TREE:
size = sizeof(struct crush_bucket_tree);
break;
case CRUSH_BUCKET_STRAW:
size = sizeof(struct crush_bucket_straw);
break;
default:
err = -EINVAL;
goto bad;
}
BUG_ON(size == 0);
b = c->buckets[i] = kzalloc(size, GFP_NOFS);
if (b == NULL)
goto badmem;
ceph_decode_need(p, end, 4*sizeof(u32), bad);
b->id = ceph_decode_32(p);
b->type = ceph_decode_16(p);
b->alg = ceph_decode_8(p);
b->hash = ceph_decode_8(p);
b->weight = ceph_decode_32(p);
b->size = ceph_decode_32(p);
dout("crush_decode bucket size %d off %x %p to %p\n",
b->size, (int)(*p-start), *p, end);
b->items = kcalloc(b->size, sizeof(__s32), GFP_NOFS);
if (b->items == NULL)
goto badmem;
b->perm = kcalloc(b->size, sizeof(u32), GFP_NOFS);
if (b->perm == NULL)
goto badmem;
b->perm_n = 0;
ceph_decode_need(p, end, b->size*sizeof(u32), bad);
for (j = 0; j < b->size; j++)
b->items[j] = ceph_decode_32(p);
switch (b->alg) {
case CRUSH_BUCKET_UNIFORM:
err = crush_decode_uniform_bucket(p, end,
(struct crush_bucket_uniform *)b);
if (err < 0)
goto bad;
break;
case CRUSH_BUCKET_LIST:
err = crush_decode_list_bucket(p, end,
(struct crush_bucket_list *)b);
if (err < 0)
goto bad;
break;
case CRUSH_BUCKET_TREE:
err = crush_decode_tree_bucket(p, end,
(struct crush_bucket_tree *)b);
if (err < 0)
goto bad;
break;
case CRUSH_BUCKET_STRAW:
err = crush_decode_straw_bucket(p, end,
(struct crush_bucket_straw *)b);
if (err < 0)
goto bad;
break;
}
}
/* rules */
dout("rule vec is %p\n", c->rules);
for (i = 0; i < c->max_rules; i++) {
u32 yes;
struct crush_rule *r;
ceph_decode_32_safe(p, end, yes, bad);
if (!yes) {
dout("crush_decode NO rule %d off %x %p to %p\n",
i, (int)(*p-start), *p, end);
c->rules[i] = NULL;
continue;
}
dout("crush_decode rule %d off %x %p to %p\n",
i, (int)(*p-start), *p, end);
/* len */
ceph_decode_32_safe(p, end, yes, bad);
#if BITS_PER_LONG == 32
err = -EINVAL;
if (yes > ULONG_MAX / sizeof(struct crush_rule_step))
goto bad;
#endif
r = c->rules[i] = kmalloc(sizeof(*r) +
yes*sizeof(struct crush_rule_step),
GFP_NOFS);
if (r == NULL)
goto badmem;
dout(" rule %d is at %p\n", i, r);
r->len = yes;
ceph_decode_copy_safe(p, end, &r->mask, 4, bad); /* 4 u8's */
ceph_decode_need(p, end, r->len*3*sizeof(u32), bad);
for (j = 0; j < r->len; j++) {
r->steps[j].op = ceph_decode_32(p);
r->steps[j].arg1 = ceph_decode_32(p);
r->steps[j].arg2 = ceph_decode_32(p);
}
}
/* ignore trailing name maps. */
dout("crush_decode success\n");
return c;
badmem:
err = -ENOMEM;
bad:
dout("crush_decode fail %d\n", err);
crush_destroy(c);
return ERR_PTR(err);
}
/*
* rbtree of pg_mapping for handling pg_temp (explicit mapping of pgid
* to a set of osds)
*/
static int pgid_cmp(struct ceph_pg l, struct ceph_pg r)
{
u64 a = *(u64 *)&l;
u64 b = *(u64 *)&r;
if (a < b)
return -1;
if (a > b)
return 1;
return 0;
}
static int __insert_pg_mapping(struct ceph_pg_mapping *new,
struct rb_root *root)
{
struct rb_node **p = &root->rb_node;
struct rb_node *parent = NULL;
struct ceph_pg_mapping *pg = NULL;
int c;
while (*p) {
parent = *p;
pg = rb_entry(parent, struct ceph_pg_mapping, node);
c = pgid_cmp(new->pgid, pg->pgid);
if (c < 0)
p = &(*p)->rb_left;
else if (c > 0)
p = &(*p)->rb_right;
else
return -EEXIST;
}
rb_link_node(&new->node, parent, p);
rb_insert_color(&new->node, root);
return 0;
}
static struct ceph_pg_mapping *__lookup_pg_mapping(struct rb_root *root,
struct ceph_pg pgid)
{
struct rb_node *n = root->rb_node;
struct ceph_pg_mapping *pg;
int c;
while (n) {
pg = rb_entry(n, struct ceph_pg_mapping, node);
c = pgid_cmp(pgid, pg->pgid);
if (c < 0)
n = n->rb_left;
else if (c > 0)
n = n->rb_right;
else
return pg;
}
return NULL;
}
/*
* rbtree of pg pool info
*/
static int __insert_pg_pool(struct rb_root *root, struct ceph_pg_pool_info *new)
{
struct rb_node **p = &root->rb_node;
struct rb_node *parent = NULL;
struct ceph_pg_pool_info *pi = NULL;
while (*p) {
parent = *p;
pi = rb_entry(parent, struct ceph_pg_pool_info, node);
if (new->id < pi->id)
p = &(*p)->rb_left;
else if (new->id > pi->id)
p = &(*p)->rb_right;
else
return -EEXIST;
}
rb_link_node(&new->node, parent, p);
rb_insert_color(&new->node, root);
return 0;
}
static struct ceph_pg_pool_info *__lookup_pg_pool(struct rb_root *root, int id)
{
struct ceph_pg_pool_info *pi;
struct rb_node *n = root->rb_node;
while (n) {
pi = rb_entry(n, struct ceph_pg_pool_info, node);
if (id < pi->id)
n = n->rb_left;
else if (id > pi->id)
n = n->rb_right;
else
return pi;
}
return NULL;
}
int ceph_pg_poolid_by_name(struct ceph_osdmap *map, const char *name)
{
struct rb_node *rbp;
for (rbp = rb_first(&map->pg_pools); rbp; rbp = rb_next(rbp)) {
struct ceph_pg_pool_info *pi =
rb_entry(rbp, struct ceph_pg_pool_info, node);
if (pi->name && strcmp(pi->name, name) == 0)
return pi->id;
}
return -ENOENT;
}
EXPORT_SYMBOL(ceph_pg_poolid_by_name);
static void __remove_pg_pool(struct rb_root *root, struct ceph_pg_pool_info *pi)
{
rb_erase(&pi->node, root);
kfree(pi->name);
kfree(pi);
}
static int __decode_pool(void **p, void *end, struct ceph_pg_pool_info *pi)
{
unsigned n, m;
ceph_decode_copy(p, &pi->v, sizeof(pi->v));
calc_pg_masks(pi);
/* num_snaps * snap_info_t */
n = le32_to_cpu(pi->v.num_snaps);
while (n--) {
ceph_decode_need(p, end, sizeof(u64) + 1 + sizeof(u64) +
sizeof(struct ceph_timespec), bad);
*p += sizeof(u64) + /* key */
1 + sizeof(u64) + /* u8, snapid */
sizeof(struct ceph_timespec);
m = ceph_decode_32(p); /* snap name */
*p += m;
}
*p += le32_to_cpu(pi->v.num_removed_snap_intervals) * sizeof(u64) * 2;
return 0;
bad:
return -EINVAL;
}
static int __decode_pool_names(void **p, void *end, struct ceph_osdmap *map)
{
struct ceph_pg_pool_info *pi;
u32 num, len, pool;
ceph_decode_32_safe(p, end, num, bad);
dout(" %d pool names\n", num);
while (num--) {
ceph_decode_32_safe(p, end, pool, bad);
ceph_decode_32_safe(p, end, len, bad);
dout(" pool %d len %d\n", pool, len);
pi = __lookup_pg_pool(&map->pg_pools, pool);
if (pi) {
kfree(pi->name);
pi->name = kmalloc(len + 1, GFP_NOFS);
if (pi->name) {
memcpy(pi->name, *p, len);
pi->name[len] = '\0';
dout(" name is %s\n", pi->name);
}
}
*p += len;
}
return 0;
bad:
return -EINVAL;
}
/*
* osd map
*/
void ceph_osdmap_destroy(struct ceph_osdmap *map)
{
dout("osdmap_destroy %p\n", map);
if (map->crush)
crush_destroy(map->crush);
while (!RB_EMPTY_ROOT(&map->pg_temp)) {
struct ceph_pg_mapping *pg =
rb_entry(rb_first(&map->pg_temp),
struct ceph_pg_mapping, node);
rb_erase(&pg->node, &map->pg_temp);
kfree(pg);
}
while (!RB_EMPTY_ROOT(&map->pg_pools)) {
struct ceph_pg_pool_info *pi =
rb_entry(rb_first(&map->pg_pools),
struct ceph_pg_pool_info, node);
__remove_pg_pool(&map->pg_pools, pi);
}
kfree(map->osd_state);
kfree(map->osd_weight);
kfree(map->osd_addr);
kfree(map);
}
/*
* adjust max osd value. reallocate arrays.
*/
static int osdmap_set_max_osd(struct ceph_osdmap *map, int max)
{
u8 *state;
struct ceph_entity_addr *addr;
u32 *weight;
state = kcalloc(max, sizeof(*state), GFP_NOFS);
addr = kcalloc(max, sizeof(*addr), GFP_NOFS);
weight = kcalloc(max, sizeof(*weight), GFP_NOFS);
if (state == NULL || addr == NULL || weight == NULL) {
kfree(state);
kfree(addr);
kfree(weight);
return -ENOMEM;
}
/* copy old? */
if (map->osd_state) {
memcpy(state, map->osd_state, map->max_osd*sizeof(*state));
memcpy(addr, map->osd_addr, map->max_osd*sizeof(*addr));
memcpy(weight, map->osd_weight, map->max_osd*sizeof(*weight));
kfree(map->osd_state);
kfree(map->osd_addr);
kfree(map->osd_weight);
}
map->osd_state = state;
map->osd_weight = weight;
map->osd_addr = addr;
map->max_osd = max;
return 0;
}
/*
* decode a full map.
*/
struct ceph_osdmap *osdmap_decode(void **p, void *end)
{
struct ceph_osdmap *map;
u16 version;
u32 len, max, i;
u8 ev;
int err = -EINVAL;
void *start = *p;
struct ceph_pg_pool_info *pi;
dout("osdmap_decode %p to %p len %d\n", *p, end, (int)(end - *p));
map = kzalloc(sizeof(*map), GFP_NOFS);
if (map == NULL)
return ERR_PTR(-ENOMEM);
map->pg_temp = RB_ROOT;
ceph_decode_16_safe(p, end, version, bad);
if (version > CEPH_OSDMAP_VERSION) {
pr_warning("got unknown v %d > %d of osdmap\n", version,
CEPH_OSDMAP_VERSION);
goto bad;
}
ceph_decode_need(p, end, 2*sizeof(u64)+6*sizeof(u32), bad);
ceph_decode_copy(p, &map->fsid, sizeof(map->fsid));
map->epoch = ceph_decode_32(p);
ceph_decode_copy(p, &map->created, sizeof(map->created));
ceph_decode_copy(p, &map->modified, sizeof(map->modified));
ceph_decode_32_safe(p, end, max, bad);
while (max--) {
ceph_decode_need(p, end, 4 + 1 + sizeof(pi->v), bad);
pi = kzalloc(sizeof(*pi), GFP_NOFS);
if (!pi)
goto bad;
pi->id = ceph_decode_32(p);
ev = ceph_decode_8(p); /* encoding version */
if (ev > CEPH_PG_POOL_VERSION) {
pr_warning("got unknown v %d > %d of ceph_pg_pool\n",
ev, CEPH_PG_POOL_VERSION);
kfree(pi);
goto bad;
}
err = __decode_pool(p, end, pi);
if (err < 0) {
kfree(pi);
goto bad;
}
__insert_pg_pool(&map->pg_pools, pi);
}
if (version >= 5 && __decode_pool_names(p, end, map) < 0)
goto bad;
ceph_decode_32_safe(p, end, map->pool_max, bad);
ceph_decode_32_safe(p, end, map->flags, bad);
max = ceph_decode_32(p);
/* (re)alloc osd arrays */
err = osdmap_set_max_osd(map, max);
if (err < 0)
goto bad;
dout("osdmap_decode max_osd = %d\n", map->max_osd);
/* osds */
err = -EINVAL;
ceph_decode_need(p, end, 3*sizeof(u32) +
map->max_osd*(1 + sizeof(*map->osd_weight) +
sizeof(*map->osd_addr)), bad);
*p += 4; /* skip length field (should match max) */
ceph_decode_copy(p, map->osd_state, map->max_osd);
*p += 4; /* skip length field (should match max) */
for (i = 0; i < map->max_osd; i++)
map->osd_weight[i] = ceph_decode_32(p);
*p += 4; /* skip length field (should match max) */
ceph_decode_copy(p, map->osd_addr, map->max_osd*sizeof(*map->osd_addr));
for (i = 0; i < map->max_osd; i++)
ceph_decode_addr(&map->osd_addr[i]);
/* pg_temp */
ceph_decode_32_safe(p, end, len, bad);
for (i = 0; i < len; i++) {
int n, j;
struct ceph_pg pgid;
struct ceph_pg_mapping *pg;
ceph_decode_need(p, end, sizeof(u32) + sizeof(u64), bad);
ceph_decode_copy(p, &pgid, sizeof(pgid));
n = ceph_decode_32(p);
ceph_decode_need(p, end, n * sizeof(u32), bad);
err = -ENOMEM;
pg = kmalloc(sizeof(*pg) + n*sizeof(u32), GFP_NOFS);
if (!pg)
goto bad;
pg->pgid = pgid;
pg->len = n;
for (j = 0; j < n; j++)
pg->osds[j] = ceph_decode_32(p);
err = __insert_pg_mapping(pg, &map->pg_temp);
if (err)
goto bad;
dout(" added pg_temp %llx len %d\n", *(u64 *)&pgid, len);
}
/* crush */
ceph_decode_32_safe(p, end, len, bad);
dout("osdmap_decode crush len %d from off 0x%x\n", len,
(int)(*p - start));
ceph_decode_need(p, end, len, bad);
map->crush = crush_decode(*p, end);
*p += len;
if (IS_ERR(map->crush)) {
err = PTR_ERR(map->crush);
map->crush = NULL;
goto bad;
}
/* ignore the rest of the map */
*p = end;
dout("osdmap_decode done %p %p\n", *p, end);
return map;
bad:
dout("osdmap_decode fail\n");
ceph_osdmap_destroy(map);
return ERR_PTR(err);
}
/*
* decode and apply an incremental map update.
*/
struct ceph_osdmap *osdmap_apply_incremental(void **p, void *end,
struct ceph_osdmap *map,
struct ceph_messenger *msgr)
{
struct crush_map *newcrush = NULL;
struct ceph_fsid fsid;
u32 epoch = 0;
struct ceph_timespec modified;
u32 len, pool;
__s32 new_pool_max, new_flags, max;
void *start = *p;
int err = -EINVAL;
u16 version;
struct rb_node *rbp;
ceph_decode_16_safe(p, end, version, bad);
if (version > CEPH_OSDMAP_INC_VERSION) {
pr_warning("got unknown v %d > %d of inc osdmap\n", version,
CEPH_OSDMAP_INC_VERSION);
goto bad;
}
ceph_decode_need(p, end, sizeof(fsid)+sizeof(modified)+2*sizeof(u32),
bad);
ceph_decode_copy(p, &fsid, sizeof(fsid));
epoch = ceph_decode_32(p);
BUG_ON(epoch != map->epoch+1);
ceph_decode_copy(p, &modified, sizeof(modified));
new_pool_max = ceph_decode_32(p);
new_flags = ceph_decode_32(p);
/* full map? */
ceph_decode_32_safe(p, end, len, bad);
if (len > 0) {
dout("apply_incremental full map len %d, %p to %p\n",
len, *p, end);
return osdmap_decode(p, min(*p+len, end));
}
/* new crush? */
ceph_decode_32_safe(p, end, len, bad);
if (len > 0) {
dout("apply_incremental new crush map len %d, %p to %p\n",
len, *p, end);
newcrush = crush_decode(*p, min(*p+len, end));
if (IS_ERR(newcrush))
return ERR_CAST(newcrush);
*p += len;
}
/* new flags? */
if (new_flags >= 0)
map->flags = new_flags;
if (new_pool_max >= 0)
map->pool_max = new_pool_max;
ceph_decode_need(p, end, 5*sizeof(u32), bad);
/* new max? */
max = ceph_decode_32(p);
if (max >= 0) {
err = osdmap_set_max_osd(map, max);
if (err < 0)
goto bad;
}
map->epoch++;
map->modified = modified;
if (newcrush) {
if (map->crush)
crush_destroy(map->crush);
map->crush = newcrush;
newcrush = NULL;
}
/* new_pool */
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
__u8 ev;
struct ceph_pg_pool_info *pi;
ceph_decode_32_safe(p, end, pool, bad);
ceph_decode_need(p, end, 1 + sizeof(pi->v), bad);
ev = ceph_decode_8(p); /* encoding version */
if (ev > CEPH_PG_POOL_VERSION) {
pr_warning("got unknown v %d > %d of ceph_pg_pool\n",
ev, CEPH_PG_POOL_VERSION);
goto bad;
}
pi = __lookup_pg_pool(&map->pg_pools, pool);
if (!pi) {
pi = kzalloc(sizeof(*pi), GFP_NOFS);
if (!pi) {
err = -ENOMEM;
goto bad;
}
pi->id = pool;
__insert_pg_pool(&map->pg_pools, pi);
}
err = __decode_pool(p, end, pi);
if (err < 0)
goto bad;
}
if (version >= 5 && __decode_pool_names(p, end, map) < 0)
goto bad;
/* old_pool */
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
struct ceph_pg_pool_info *pi;
ceph_decode_32_safe(p, end, pool, bad);
pi = __lookup_pg_pool(&map->pg_pools, pool);
if (pi)
__remove_pg_pool(&map->pg_pools, pi);
}
/* new_up */
err = -EINVAL;
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
u32 osd;
struct ceph_entity_addr addr;
ceph_decode_32_safe(p, end, osd, bad);
ceph_decode_copy_safe(p, end, &addr, sizeof(addr), bad);
ceph_decode_addr(&addr);
pr_info("osd%d up\n", osd);
BUG_ON(osd >= map->max_osd);
map->osd_state[osd] |= CEPH_OSD_UP;
map->osd_addr[osd] = addr;
}
/* new_state */
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
u32 osd;
u8 xorstate;
ceph_decode_32_safe(p, end, osd, bad);
xorstate = **(u8 **)p;
(*p)++; /* clean flag */
if (xorstate == 0)
xorstate = CEPH_OSD_UP;
if (xorstate & CEPH_OSD_UP)
pr_info("osd%d down\n", osd);
if (osd < map->max_osd)
map->osd_state[osd] ^= xorstate;
}
/* new_weight */
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
u32 osd, off;
ceph_decode_need(p, end, sizeof(u32)*2, bad);
osd = ceph_decode_32(p);
off = ceph_decode_32(p);
pr_info("osd%d weight 0x%x %s\n", osd, off,
off == CEPH_OSD_IN ? "(in)" :
(off == CEPH_OSD_OUT ? "(out)" : ""));
if (osd < map->max_osd)
map->osd_weight[osd] = off;
}
/* new_pg_temp */
rbp = rb_first(&map->pg_temp);
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
struct ceph_pg_mapping *pg;
int j;
struct ceph_pg pgid;
u32 pglen;
ceph_decode_need(p, end, sizeof(u64) + sizeof(u32), bad);
ceph_decode_copy(p, &pgid, sizeof(pgid));
pglen = ceph_decode_32(p);
/* remove any? */
while (rbp && pgid_cmp(rb_entry(rbp, struct ceph_pg_mapping,
node)->pgid, pgid) <= 0) {
struct ceph_pg_mapping *cur =
rb_entry(rbp, struct ceph_pg_mapping, node);
rbp = rb_next(rbp);
dout(" removed pg_temp %llx\n", *(u64 *)&cur->pgid);
rb_erase(&cur->node, &map->pg_temp);
kfree(cur);
}
if (pglen) {
/* insert */
ceph_decode_need(p, end, pglen*sizeof(u32), bad);
pg = kmalloc(sizeof(*pg) + sizeof(u32)*pglen, GFP_NOFS);
if (!pg) {
err = -ENOMEM;
goto bad;
}
pg->pgid = pgid;
pg->len = pglen;
for (j = 0; j < pglen; j++)
pg->osds[j] = ceph_decode_32(p);
err = __insert_pg_mapping(pg, &map->pg_temp);
if (err) {
kfree(pg);
goto bad;
}
dout(" added pg_temp %llx len %d\n", *(u64 *)&pgid,
pglen);
}
}
while (rbp) {
struct ceph_pg_mapping *cur =
rb_entry(rbp, struct ceph_pg_mapping, node);
rbp = rb_next(rbp);
dout(" removed pg_temp %llx\n", *(u64 *)&cur->pgid);
rb_erase(&cur->node, &map->pg_temp);
kfree(cur);
}
/* ignore the rest */
*p = end;
return map;
bad:
pr_err("corrupt inc osdmap epoch %d off %d (%p of %p-%p)\n",
epoch, (int)(*p - start), *p, start, end);
print_hex_dump(KERN_DEBUG, "osdmap: ",
DUMP_PREFIX_OFFSET, 16, 1,
start, end - start, true);
if (newcrush)
crush_destroy(newcrush);
return ERR_PTR(err);
}
/*
* calculate file layout from given offset, length.
* fill in correct oid, logical length, and object extent
* offset, length.
*
* for now, we write only a single su, until we can
* pass a stride back to the caller.
*/
void ceph_calc_file_object_mapping(struct ceph_file_layout *layout,
u64 off, u64 *plen,
u64 *ono,
u64 *oxoff, u64 *oxlen)
{
u32 osize = le32_to_cpu(layout->fl_object_size);
u32 su = le32_to_cpu(layout->fl_stripe_unit);
u32 sc = le32_to_cpu(layout->fl_stripe_count);
u32 bl, stripeno, stripepos, objsetno;
u32 su_per_object;
u64 t, su_offset;
dout("mapping %llu~%llu osize %u fl_su %u\n", off, *plen,
osize, su);
su_per_object = osize / su;
dout("osize %u / su %u = su_per_object %u\n", osize, su,
su_per_object);
BUG_ON((su & ~PAGE_MASK) != 0);
/* bl = *off / su; */
t = off;
do_div(t, su);
bl = t;
dout("off %llu / su %u = bl %u\n", off, su, bl);
stripeno = bl / sc;
stripepos = bl % sc;
objsetno = stripeno / su_per_object;
*ono = objsetno * sc + stripepos;
dout("objset %u * sc %u = ono %u\n", objsetno, sc, (unsigned)*ono);
/* *oxoff = *off % layout->fl_stripe_unit; # offset in su */
t = off;
su_offset = do_div(t, su);
*oxoff = su_offset + (stripeno % su_per_object) * su;
/*
* Calculate the length of the extent being written to the selected
* object. This is the minimum of the full length requested (plen) or
* the remainder of the current stripe being written to.
*/
*oxlen = min_t(u64, *plen, su - su_offset);
*plen = *oxlen;
dout(" obj extent %llu~%llu\n", *oxoff, *oxlen);
}
EXPORT_SYMBOL(ceph_calc_file_object_mapping);
/*
* calculate an object layout (i.e. pgid) from an oid,
* file_layout, and osdmap
*/
int ceph_calc_object_layout(struct ceph_object_layout *ol,
const char *oid,
struct ceph_file_layout *fl,
struct ceph_osdmap *osdmap)
{
unsigned num, num_mask;
struct ceph_pg pgid;
s32 preferred = (s32)le32_to_cpu(fl->fl_pg_preferred);
int poolid = le32_to_cpu(fl->fl_pg_pool);
struct ceph_pg_pool_info *pool;
unsigned ps;
BUG_ON(!osdmap);
pool = __lookup_pg_pool(&osdmap->pg_pools, poolid);
if (!pool)
return -EIO;
ps = ceph_str_hash(pool->v.object_hash, oid, strlen(oid));
if (preferred >= 0) {
ps += preferred;
num = le32_to_cpu(pool->v.lpg_num);
num_mask = pool->lpg_num_mask;
} else {
num = le32_to_cpu(pool->v.pg_num);
num_mask = pool->pg_num_mask;
}
pgid.ps = cpu_to_le16(ps);
pgid.preferred = cpu_to_le16(preferred);
pgid.pool = fl->fl_pg_pool;
if (preferred >= 0)
dout("calc_object_layout '%s' pgid %d.%xp%d\n", oid, poolid, ps,
(int)preferred);
else
dout("calc_object_layout '%s' pgid %d.%x\n", oid, poolid, ps);
ol->ol_pgid = pgid;
ol->ol_stripe_unit = fl->fl_object_stripe_unit;
return 0;
}
EXPORT_SYMBOL(ceph_calc_object_layout);
/*
* Calculate raw osd vector for the given pgid. Return pointer to osd
* array, or NULL on failure.
*/
static int *calc_pg_raw(struct ceph_osdmap *osdmap, struct ceph_pg pgid,
int *osds, int *num)
{
struct ceph_pg_mapping *pg;
struct ceph_pg_pool_info *pool;
int ruleno;
unsigned poolid, ps, pps;
int preferred;
/* pg_temp? */
pg = __lookup_pg_mapping(&osdmap->pg_temp, pgid);
if (pg) {
*num = pg->len;
return pg->osds;
}
/* crush */
poolid = le32_to_cpu(pgid.pool);
ps = le16_to_cpu(pgid.ps);
preferred = (s16)le16_to_cpu(pgid.preferred);
/* don't forcefeed bad device ids to crush */
if (preferred >= osdmap->max_osd ||
preferred >= osdmap->crush->max_devices)
preferred = -1;
pool = __lookup_pg_pool(&osdmap->pg_pools, poolid);
if (!pool)
return NULL;
ruleno = crush_find_rule(osdmap->crush, pool->v.crush_ruleset,
pool->v.type, pool->v.size);
if (ruleno < 0) {
pr_err("no crush rule pool %d ruleset %d type %d size %d\n",
poolid, pool->v.crush_ruleset, pool->v.type,
pool->v.size);
return NULL;
}
if (preferred >= 0)
pps = ceph_stable_mod(ps,
le32_to_cpu(pool->v.lpgp_num),
pool->lpgp_num_mask);
else
pps = ceph_stable_mod(ps,
le32_to_cpu(pool->v.pgp_num),
pool->pgp_num_mask);
pps += poolid;
*num = crush_do_rule(osdmap->crush, ruleno, pps, osds,
min_t(int, pool->v.size, *num),
preferred, osdmap->osd_weight);
return osds;
}
/*
* Return acting set for given pgid.
*/
int ceph_calc_pg_acting(struct ceph_osdmap *osdmap, struct ceph_pg pgid,
int *acting)
{
int rawosds[CEPH_PG_MAX_SIZE], *osds;
int i, o, num = CEPH_PG_MAX_SIZE;
osds = calc_pg_raw(osdmap, pgid, rawosds, &num);
if (!osds)
return -1;
/* primary is first up osd */
o = 0;
for (i = 0; i < num; i++)
if (ceph_osd_is_up(osdmap, osds[i]))
acting[o++] = osds[i];
return o;
}
/*
* Return primary osd for given pgid, or -1 if none.
*/
int ceph_calc_pg_primary(struct ceph_osdmap *osdmap, struct ceph_pg pgid)
{
int rawosds[CEPH_PG_MAX_SIZE], *osds;
int i, num = CEPH_PG_MAX_SIZE;
osds = calc_pg_raw(osdmap, pgid, rawosds, &num);
if (!osds)
return -1;
/* primary is first up osd */
for (i = 0; i < num; i++)
if (ceph_osd_is_up(osdmap, osds[i]))
return osds[i];
return -1;
}
EXPORT_SYMBOL(ceph_calc_pg_primary);
| gpl-2.0 |
eyosen/kernel_htc_endeavoru | arch/x86/pci/legacy.c | 3170 | 1631 | /*
* legacy.c - traditional, old school PCI bus probing
*/
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/pci_x86.h>
/*
* Discover remaining PCI buses in case there are peer host bridges.
* We use the number of last PCI bus provided by the PCI BIOS.
*/
static void __devinit pcibios_fixup_peer_bridges(void)
{
int n;
if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff)
return;
DBG("PCI: Peer bridge fixup\n");
for (n=0; n <= pcibios_last_bus; n++)
pcibios_scan_specific_bus(n);
}
int __init pci_legacy_init(void)
{
if (!raw_pci_ops) {
printk("PCI: System does not support PCI\n");
return 0;
}
printk("PCI: Probing PCI hardware\n");
pci_root_bus = pcibios_scan_root(0);
if (pci_root_bus)
pci_bus_add_devices(pci_root_bus);
return 0;
}
void __devinit pcibios_scan_specific_bus(int busn)
{
int devfn;
long node;
u32 l;
if (pci_find_bus(0, busn))
return;
node = get_mp_bus_to_node(busn);
for (devfn = 0; devfn < 256; devfn += 8) {
if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) &&
l != 0x0000 && l != 0xffff) {
DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l);
printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn);
pci_scan_bus_on_node(busn, &pci_root_ops, node);
return;
}
}
}
EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus);
int __init pci_subsys_init(void)
{
/*
* The init function returns an non zero value when
* pci_legacy_init should be invoked.
*/
if (x86_init.pci.init())
pci_legacy_init();
pcibios_fixup_peer_bridges();
x86_init.pci.init_irq();
pcibios_init();
return 0;
}
subsys_initcall(pci_subsys_init);
| gpl-2.0 |
frank-liu/SPADE-7x30-3.0 | drivers/ssb/driver_gige.c | 3682 | 7439 | /*
* Sonics Silicon Backplane
* Broadcom Gigabit Ethernet core driver
*
* Copyright 2008, Broadcom Corporation
* Copyright 2008, Michael Buesch <mb@bu3sch.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_driver_gige.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/slab.h>
/*
MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
MODULE_AUTHOR("Michael Buesch");
MODULE_LICENSE("GPL");
*/
static const struct ssb_device_id ssb_gige_tbl[] = {
SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
SSB_DEVTABLE_END
};
/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
{
return ssb_read8(dev->dev, offset);
}
static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
{
return ssb_read16(dev->dev, offset);
}
static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
{
return ssb_read32(dev->dev, offset);
}
static inline void gige_write8(struct ssb_gige *dev,
u16 offset, u8 value)
{
ssb_write8(dev->dev, offset, value);
}
static inline void gige_write16(struct ssb_gige *dev,
u16 offset, u16 value)
{
ssb_write16(dev->dev, offset, value);
}
static inline void gige_write32(struct ssb_gige *dev,
u16 offset, u32 value)
{
ssb_write32(dev->dev, offset, value);
}
static inline
u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
{
BUG_ON(offset >= 256);
return gige_read8(dev, SSB_GIGE_PCICFG + offset);
}
static inline
u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
{
BUG_ON(offset >= 256);
return gige_read16(dev, SSB_GIGE_PCICFG + offset);
}
static inline
u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
{
BUG_ON(offset >= 256);
return gige_read32(dev, SSB_GIGE_PCICFG + offset);
}
static inline
void gige_pcicfg_write8(struct ssb_gige *dev,
unsigned int offset, u8 value)
{
BUG_ON(offset >= 256);
gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
}
static inline
void gige_pcicfg_write16(struct ssb_gige *dev,
unsigned int offset, u16 value)
{
BUG_ON(offset >= 256);
gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
}
static inline
void gige_pcicfg_write32(struct ssb_gige *dev,
unsigned int offset, u32 value)
{
BUG_ON(offset >= 256);
gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
}
static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
{
struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
unsigned long flags;
if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
return PCIBIOS_DEVICE_NOT_FOUND;
if (reg >= 256)
return PCIBIOS_DEVICE_NOT_FOUND;
spin_lock_irqsave(&dev->lock, flags);
switch (size) {
case 1:
*val = gige_pcicfg_read8(dev, reg);
break;
case 2:
*val = gige_pcicfg_read16(dev, reg);
break;
case 4:
*val = gige_pcicfg_read32(dev, reg);
break;
default:
WARN_ON(1);
}
spin_unlock_irqrestore(&dev->lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 val)
{
struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
unsigned long flags;
if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
return PCIBIOS_DEVICE_NOT_FOUND;
if (reg >= 256)
return PCIBIOS_DEVICE_NOT_FOUND;
spin_lock_irqsave(&dev->lock, flags);
switch (size) {
case 1:
gige_pcicfg_write8(dev, reg, val);
break;
case 2:
gige_pcicfg_write16(dev, reg, val);
break;
case 4:
gige_pcicfg_write32(dev, reg, val);
break;
default:
WARN_ON(1);
}
spin_unlock_irqrestore(&dev->lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
{
struct ssb_gige *dev;
u32 base, tmslow, tmshigh;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->dev = sdev;
spin_lock_init(&dev->lock);
dev->pci_controller.pci_ops = &dev->pci_ops;
dev->pci_controller.io_resource = &dev->io_resource;
dev->pci_controller.mem_resource = &dev->mem_resource;
dev->pci_controller.io_map_base = 0x800;
dev->pci_ops.read = ssb_gige_pci_read_config;
dev->pci_ops.write = ssb_gige_pci_write_config;
dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
dev->io_resource.start = 0x800;
dev->io_resource.end = 0x8FF;
dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
if (!ssb_device_is_enabled(sdev))
ssb_device_enable(sdev, 0);
/* Setup BAR0. This is a 64k MMIO region. */
base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
dev->mem_resource.start = base;
dev->mem_resource.end = base + 0x10000 - 1;
dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
/* Enable the memory region. */
gige_pcicfg_write16(dev, PCI_COMMAND,
gige_pcicfg_read16(dev, PCI_COMMAND)
| PCI_COMMAND_MEMORY);
/* Write flushing is controlled by the Flush Status Control register.
* We want to flush every register write with a timeout and we want
* to disable the IRQ mask while flushing to avoid concurrency.
* Note that automatic write flushing does _not_ work from
* an IRQ handler. The driver must flush manually by reading a register.
*/
gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
/* Check if we have an RGMII or GMII PHY-bus.
* On RGMII do not bypass the DLLs */
tmslow = ssb_read32(sdev, SSB_TMSLOW);
tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
dev->has_rgmii = 1;
} else {
tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
dev->has_rgmii = 0;
}
tmslow |= SSB_GIGE_TMSLOW_DLLEN;
ssb_write32(sdev, SSB_TMSLOW, tmslow);
ssb_set_drvdata(sdev, dev);
register_pci_controller(&dev->pci_controller);
return 0;
}
bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
{
if (!pdev->resource[0].name)
return 0;
return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
}
EXPORT_SYMBOL(pdev_is_ssb_gige_core);
int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
struct pci_dev *pdev)
{
struct ssb_gige *dev = ssb_get_drvdata(sdev);
struct resource *res;
if (pdev->bus->ops != &dev->pci_ops) {
/* The PCI device is not on this SSB GigE bridge device. */
return -ENODEV;
}
/* Fixup the PCI resources. */
res = &(pdev->resource[0]);
res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
res->name = dev->mem_resource.name;
res->start = dev->mem_resource.start;
res->end = dev->mem_resource.end;
/* Fixup interrupt lines. */
pdev->irq = ssb_mips_irq(sdev) + 2;
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
return 0;
}
int ssb_gige_map_irq(struct ssb_device *sdev,
const struct pci_dev *pdev)
{
struct ssb_gige *dev = ssb_get_drvdata(sdev);
if (pdev->bus->ops != &dev->pci_ops) {
/* The PCI device is not on this SSB GigE bridge device. */
return -ENODEV;
}
return ssb_mips_irq(sdev) + 2;
}
static struct ssb_driver ssb_gige_driver = {
.name = "BCM-GigE",
.id_table = ssb_gige_tbl,
.probe = ssb_gige_probe,
};
int ssb_gige_init(void)
{
return ssb_driver_register(&ssb_gige_driver);
}
| gpl-2.0 |
Jamesjue/linux_kernel_db | arch/sh/kernel/sh_bios.c | 4450 | 4017 | /*
* C interface for trapping into the standard LinuxSH BIOS.
*
* Copyright (C) 2000 Greg Banks, Mitch Davis
* Copyright (C) 1999, 2000 Niibe Yutaka
* Copyright (C) 2002 M. R. Brown
* Copyright (C) 2004 - 2010 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/console.h>
#include <linux/tty.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <asm/sh_bios.h>
#define BIOS_CALL_CONSOLE_WRITE 0
#define BIOS_CALL_ETH_NODE_ADDR 10
#define BIOS_CALL_SHUTDOWN 11
#define BIOS_CALL_GDB_DETACH 0xff
void *gdb_vbr_vector = NULL;
static inline long sh_bios_call(long func, long arg0, long arg1, long arg2,
long arg3)
{
register long r0 __asm__("r0") = func;
register long r4 __asm__("r4") = arg0;
register long r5 __asm__("r5") = arg1;
register long r6 __asm__("r6") = arg2;
register long r7 __asm__("r7") = arg3;
if (!gdb_vbr_vector)
return -ENOSYS;
__asm__ __volatile__("trapa #0x3f":"=z"(r0)
:"0"(r0), "r"(r4), "r"(r5), "r"(r6), "r"(r7)
:"memory");
return r0;
}
void sh_bios_console_write(const char *buf, unsigned int len)
{
sh_bios_call(BIOS_CALL_CONSOLE_WRITE, (long)buf, (long)len, 0, 0);
}
void sh_bios_gdb_detach(void)
{
sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0);
}
EXPORT_SYMBOL_GPL(sh_bios_gdb_detach);
void sh_bios_get_node_addr(unsigned char *node_addr)
{
sh_bios_call(BIOS_CALL_ETH_NODE_ADDR, 0, (long)node_addr, 0, 0);
}
EXPORT_SYMBOL_GPL(sh_bios_get_node_addr);
void sh_bios_shutdown(unsigned int how)
{
sh_bios_call(BIOS_CALL_SHUTDOWN, how, 0, 0, 0);
}
/*
* Read the old value of the VBR register to initialise the vector
* through which debug and BIOS traps are delegated by the Linux trap
* handler.
*/
void sh_bios_vbr_init(void)
{
unsigned long vbr;
if (unlikely(gdb_vbr_vector))
return;
__asm__ __volatile__ ("stc vbr, %0" : "=r" (vbr));
if (vbr) {
gdb_vbr_vector = (void *)(vbr + 0x100);
printk(KERN_NOTICE "Setting GDB trap vector to %p\n",
gdb_vbr_vector);
} else
printk(KERN_NOTICE "SH-BIOS not detected\n");
}
/**
* sh_bios_vbr_reload - Re-load the system VBR from the BIOS vector.
*
* This can be used by save/restore code to reinitialize the system VBR
* from the fixed BIOS VBR. A no-op if no BIOS VBR is known.
*/
void sh_bios_vbr_reload(void)
{
if (gdb_vbr_vector)
__asm__ __volatile__ (
"ldc %0, vbr"
:
: "r" (((unsigned long) gdb_vbr_vector) - 0x100)
: "memory"
);
}
#ifdef CONFIG_EARLY_PRINTK
/*
* Print a string through the BIOS
*/
static void sh_console_write(struct console *co, const char *s,
unsigned count)
{
sh_bios_console_write(s, count);
}
/*
* Setup initial baud/bits/parity. We do two things here:
* - construct a cflag setting for the first rs_open()
* - initialize the serial port
* Return non-zero if we didn't find a serial port.
*/
static int __init sh_console_setup(struct console *co, char *options)
{
int cflag = CREAD | HUPCL | CLOCAL;
/*
* Now construct a cflag setting.
* TODO: this is a totally bogus cflag, as we have
* no idea what serial settings the BIOS is using, or
* even if its using the serial port at all.
*/
cflag |= B115200 | CS8 | /*no parity*/0;
co->cflag = cflag;
return 0;
}
static struct console bios_console = {
.name = "bios",
.write = sh_console_write,
.setup = sh_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
};
static int __init setup_early_printk(char *buf)
{
int keep_early = 0;
if (!buf)
return 0;
if (strstr(buf, "keep"))
keep_early = 1;
if (!strncmp(buf, "bios", 4))
early_console = &bios_console;
if (likely(early_console)) {
if (keep_early)
early_console->flags &= ~CON_BOOT;
else
early_console->flags |= CON_BOOT;
register_console(early_console);
}
return 0;
}
early_param("earlyprintk", setup_early_printk);
#endif
| gpl-2.0 |
sombree/android_kernel_samsung_jf | arch/powerpc/sysdev/qe_lib/qe.c | 4450 | 17579 | /*
* Copyright (C) 2006-2010 Freescale Semicondutor, Inc. All rights reserved.
*
* Authors: Shlomi Gridish <gridish@freescale.com>
* Li Yang <leoli@freescale.com>
* Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
*
* Description:
* General Purpose functions for the global management of the
* QUICC Engine (QE).
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/crc32.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/immap_qe.h>
#include <asm/qe.h>
#include <asm/prom.h>
#include <asm/rheap.h>
static void qe_snums_init(void);
static int qe_sdma_init(void);
static DEFINE_SPINLOCK(qe_lock);
DEFINE_SPINLOCK(cmxgcr_lock);
EXPORT_SYMBOL(cmxgcr_lock);
/* QE snum state */
enum qe_snum_state {
QE_SNUM_STATE_USED,
QE_SNUM_STATE_FREE
};
/* QE snum */
struct qe_snum {
u8 num;
enum qe_snum_state state;
};
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
struct qe_immap __iomem *qe_immr;
EXPORT_SYMBOL(qe_immr);
static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
static unsigned int qe_num_of_snum;
static phys_addr_t qebase = -1;
phys_addr_t get_qe_base(void)
{
struct device_node *qe;
int size;
const u32 *prop;
if (qebase != -1)
return qebase;
qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!qe) {
qe = of_find_node_by_type(NULL, "qe");
if (!qe)
return qebase;
}
prop = of_get_property(qe, "reg", &size);
if (prop && size >= sizeof(*prop))
qebase = of_translate_address(qe, prop);
of_node_put(qe);
return qebase;
}
EXPORT_SYMBOL(get_qe_base);
void qe_reset(void)
{
if (qe_immr == NULL)
qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
qe_snums_init();
qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
QE_CR_PROTOCOL_UNSPECIFIED, 0);
/* Reclaim the MURAM memory for our use. */
qe_muram_init();
if (qe_sdma_init())
panic("sdma init failed!");
}
int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
u32 ret;
spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
dev_shift = QE_CR_SNUM_SHIFT;
} else if (cmd == QE_ASSIGN_RISC) {
/* Here device is the SNUM, and mcnProtocol is
* e_QeCmdRiscAssignment value */
dev_shift = QE_CR_SNUM_SHIFT;
mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
} else {
if (device == QE_CR_SUBBLOCK_USB)
mcn_shift = QE_CR_MCN_USB_SHIFT;
else
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}
out_be32(&qe_immr->cp.cecdr, cmd_input);
out_be32(&qe_immr->cp.cecr,
(cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
mcn_protocol << mcn_shift));
}
/* wait for the QE_CR_FLG to clear */
ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
100, 0);
/* On timeout (e.g. failure), the expression will be false (ret == 0),
otherwise it will be true (ret == 1). */
spin_unlock_irqrestore(&qe_lock, flags);
return ret == 1;
}
EXPORT_SYMBOL(qe_issue_cmd);
/* Set a baud rate generator. This needs lots of work. There are
* 16 BRGs, which can be connected to the QE channels or output
* as clocks. The BRGs are in two different block of internal
* memory mapped space.
* The BRG clock is the QE clock divided by 2.
* It was set up long ago during the initial boot phase and is
* is given to us.
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
static unsigned int brg_clk = 0;
unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
int size;
const u32 *prop;
if (brg_clk)
return brg_clk;
qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!qe) {
qe = of_find_node_by_type(NULL, "qe");
if (!qe)
return brg_clk;
}
prop = of_get_property(qe, "brg-frequency", &size);
if (prop && size == sizeof(*prop))
brg_clk = *prop;
of_node_put(qe);
return brg_clk;
}
EXPORT_SYMBOL(qe_get_brg_clk);
/* Program the BRG to the given sampling rate and multiplier
*
* @brg: the BRG, QE_BRG1 - QE_BRG16
* @rate: the desired sampling rate
* @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
* GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
* then 'multiplier' should be 8.
*/
int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
{
u32 divisor, tempval;
u32 div16 = 0;
if ((brg < QE_BRG1) || (brg > QE_BRG16))
return -EINVAL;
divisor = qe_get_brg_clk() / (rate * multiplier);
if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
div16 = QE_BRGC_DIV16;
divisor /= 16;
}
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
that the BRG divisor must be even if you're not using divide-by-16
mode. */
if (!div16 && (divisor & 1) && (divisor > 3))
divisor++;
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
return 0;
}
EXPORT_SYMBOL(qe_setbrg);
/* Convert a string to a QE clock source enum
*
* This function takes a string, typically from a property in the device
* tree, and returns the corresponding "enum qe_clock" value.
*/
enum qe_clock qe_clock_source(const char *source)
{
unsigned int i;
if (strcasecmp(source, "none") == 0)
return QE_CLK_NONE;
if (strncasecmp(source, "brg", 3) == 0) {
i = simple_strtoul(source + 3, NULL, 10);
if ((i >= 1) && (i <= 16))
return (QE_BRG1 - 1) + i;
else
return QE_CLK_DUMMY;
}
if (strncasecmp(source, "clk", 3) == 0) {
i = simple_strtoul(source + 3, NULL, 10);
if ((i >= 1) && (i <= 24))
return (QE_CLK1 - 1) + i;
else
return QE_CLK_DUMMY;
}
return QE_CLK_DUMMY;
}
EXPORT_SYMBOL(qe_clock_source);
/* Initialize SNUMs (thread serial numbers) according to
* QE Module Control chapter, SNUM table
*/
static void qe_snums_init(void)
{
int i;
static const u8 snum_init_76[] = {
0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
0xF4, 0xF5, 0xFC, 0xFD,
};
static const u8 snum_init_46[] = {
0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
};
static const u8 *snum_init;
qe_num_of_snum = qe_get_num_of_snums();
if (qe_num_of_snum == 76)
snum_init = snum_init_76;
else
snum_init = snum_init_46;
for (i = 0; i < qe_num_of_snum; i++) {
snums[i].num = snum_init[i];
snums[i].state = QE_SNUM_STATE_FREE;
}
}
int qe_get_snum(void)
{
unsigned long flags;
int snum = -EBUSY;
int i;
spin_lock_irqsave(&qe_lock, flags);
for (i = 0; i < qe_num_of_snum; i++) {
if (snums[i].state == QE_SNUM_STATE_FREE) {
snums[i].state = QE_SNUM_STATE_USED;
snum = snums[i].num;
break;
}
}
spin_unlock_irqrestore(&qe_lock, flags);
return snum;
}
EXPORT_SYMBOL(qe_get_snum);
void qe_put_snum(u8 snum)
{
int i;
for (i = 0; i < qe_num_of_snum; i++) {
if (snums[i].num == snum) {
snums[i].state = QE_SNUM_STATE_FREE;
break;
}
}
}
EXPORT_SYMBOL(qe_put_snum);
static int qe_sdma_init(void)
{
struct sdma __iomem *sdma = &qe_immr->sdma;
static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
if (!sdma)
return -ENODEV;
/* allocate 2 internal temporary buffers (512 bytes size each) for
* the SDMA */
if (IS_ERR_VALUE(sdma_buf_offset)) {
sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
if (IS_ERR_VALUE(sdma_buf_offset))
return -ENOMEM;
}
out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
(0x1 << QE_SDMR_CEN_SHIFT)));
return 0;
}
/* The maximum number of RISCs we support */
#define MAX_QE_RISC 4
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
/*
* Set to 1 if QE firmware has been uploaded, and therefore
* qe_firmware_info contains valid data.
*/
static int qe_firmware_uploaded;
/*
* Upload a QE microcode
*
* This function is a worker function for qe_upload_firmware(). It does
* the actual uploading of the microcode.
*/
static void qe_upload_microcode(const void *base,
const struct qe_microcode *ucode)
{
const __be32 *code = base + be32_to_cpu(ucode->code_offset);
unsigned int i;
if (ucode->major || ucode->minor || ucode->revision)
printk(KERN_INFO "qe-firmware: "
"uploading microcode '%s' version %u.%u.%u\n",
ucode->id, ucode->major, ucode->minor, ucode->revision);
else
printk(KERN_INFO "qe-firmware: "
"uploading microcode '%s'\n", ucode->id);
/* Use auto-increment */
out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
for (i = 0; i < be32_to_cpu(ucode->count); i++)
out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
}
/*
* Upload a microcode to the I-RAM at a specific address.
*
* See Documentation/powerpc/qe_firmware.txt for information on QE microcode
* uploading.
*
* Currently, only version 1 is supported, so the 'version' field must be
* set to 1.
*
* The SOC model and revision are not validated, they are only displayed for
* informational purposes.
*
* 'calc_size' is the calculated size, in bytes, of the firmware structure and
* all of the microcode structures, minus the CRC.
*
* 'length' is the size that the structure says it is, including the CRC.
*/
int qe_upload_firmware(const struct qe_firmware *firmware)
{
unsigned int i;
unsigned int j;
u32 crc;
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
if (!firmware) {
printk(KERN_ERR "qe-firmware: invalid pointer\n");
return -EINVAL;
}
hdr = &firmware->header;
length = be32_to_cpu(hdr->length);
/* Check the magic */
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printk(KERN_ERR "qe-firmware: not a microcode\n");
return -EPERM;
}
/* Check the version */
if (hdr->version != 1) {
printk(KERN_ERR "qe-firmware: unsupported version\n");
return -EPERM;
}
/* Validate some of the fields */
if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
printk(KERN_ERR "qe-firmware: invalid data\n");
return -EINVAL;
}
/* Validate the length and check if there's a CRC */
calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
for (i = 0; i < firmware->count; i++)
/*
* For situations where the second RISC uses the same microcode
* as the first, the 'code_offset' and 'count' fields will be
* zero, so it's okay to add those.
*/
calc_size += sizeof(__be32) *
be32_to_cpu(firmware->microcode[i].count);
/* Validate the length */
if (length != calc_size + sizeof(__be32)) {
printk(KERN_ERR "qe-firmware: invalid length\n");
return -EPERM;
}
/* Validate the CRC */
crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
if (crc != crc32(0, firmware, calc_size)) {
printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
return -EIO;
}
/*
* If the microcode calls for it, split the I-RAM.
*/
if (!firmware->split)
setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
if (firmware->soc.model)
printk(KERN_INFO
"qe-firmware: firmware '%s' for %u V%u.%u\n",
firmware->id, be16_to_cpu(firmware->soc.model),
firmware->soc.major, firmware->soc.minor);
else
printk(KERN_INFO "qe-firmware: firmware '%s'\n",
firmware->id);
/*
* The QE only supports one microcode per RISC, so clear out all the
* saved microcode information and put in the new.
*/
memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
strcpy(qe_firmware_info.id, firmware->id);
qe_firmware_info.extended_modes = firmware->extended_modes;
memcpy(qe_firmware_info.vtraps, firmware->vtraps,
sizeof(firmware->vtraps));
/* Loop through each microcode. */
for (i = 0; i < firmware->count; i++) {
const struct qe_microcode *ucode = &firmware->microcode[i];
/* Upload a microcode if it's present */
if (ucode->code_offset)
qe_upload_microcode(firmware, ucode);
/* Program the traps for this processor */
for (j = 0; j < 16; j++) {
u32 trap = be32_to_cpu(ucode->traps[j]);
if (trap)
out_be32(&qe_immr->rsp[i].tibcr[j], trap);
}
/* Enable traps */
out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
}
qe_firmware_uploaded = 1;
return 0;
}
EXPORT_SYMBOL(qe_upload_firmware);
/*
* Get info on the currently-loaded firmware
*
* This function also checks the device tree to see if the boot loader has
* uploaded a firmware already.
*/
struct qe_firmware_info *qe_get_firmware_info(void)
{
static int initialized;
struct property *prop;
struct device_node *qe;
struct device_node *fw = NULL;
const char *sprop;
unsigned int i;
/*
* If we haven't checked yet, and a driver hasn't uploaded a firmware
* yet, then check the device tree for information.
*/
if (qe_firmware_uploaded)
return &qe_firmware_info;
if (initialized)
return NULL;
initialized = 1;
/*
* Newer device trees have an "fsl,qe" compatible property for the QE
* node, but we still need to support older device trees.
*/
qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!qe) {
qe = of_find_node_by_type(NULL, "qe");
if (!qe)
return NULL;
}
/* Find the 'firmware' child node */
for_each_child_of_node(qe, fw) {
if (strcmp(fw->name, "firmware") == 0)
break;
}
of_node_put(qe);
/* Did we find the 'firmware' node? */
if (!fw)
return NULL;
qe_firmware_uploaded = 1;
/* Copy the data into qe_firmware_info*/
sprop = of_get_property(fw, "id", NULL);
if (sprop)
strncpy(qe_firmware_info.id, sprop,
sizeof(qe_firmware_info.id) - 1);
prop = of_find_property(fw, "extended-modes", NULL);
if (prop && (prop->length == sizeof(u64))) {
const u64 *iprop = prop->value;
qe_firmware_info.extended_modes = *iprop;
}
prop = of_find_property(fw, "virtual-traps", NULL);
if (prop && (prop->length == 32)) {
const u32 *iprop = prop->value;
for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
qe_firmware_info.vtraps[i] = iprop[i];
}
of_node_put(fw);
return &qe_firmware_info;
}
EXPORT_SYMBOL(qe_get_firmware_info);
unsigned int qe_get_num_of_risc(void)
{
struct device_node *qe;
int size;
unsigned int num_of_risc = 0;
const u32 *prop;
qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!qe) {
/* Older devices trees did not have an "fsl,qe"
* compatible property, so we need to look for
* the QE node by name.
*/
qe = of_find_node_by_type(NULL, "qe");
if (!qe)
return num_of_risc;
}
prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
if (prop && size == sizeof(*prop))
num_of_risc = *prop;
of_node_put(qe);
return num_of_risc;
}
EXPORT_SYMBOL(qe_get_num_of_risc);
unsigned int qe_get_num_of_snums(void)
{
struct device_node *qe;
int size;
unsigned int num_of_snums;
const u32 *prop;
num_of_snums = 28; /* The default number of snum for threads is 28 */
qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!qe) {
/* Older devices trees did not have an "fsl,qe"
* compatible property, so we need to look for
* the QE node by name.
*/
qe = of_find_node_by_type(NULL, "qe");
if (!qe)
return num_of_snums;
}
prop = of_get_property(qe, "fsl,qe-num-snums", &size);
if (prop && size == sizeof(*prop)) {
num_of_snums = *prop;
if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
/* No QE ever has fewer than 28 SNUMs */
pr_err("QE: number of snum is invalid\n");
of_node_put(qe);
return -EINVAL;
}
}
of_node_put(qe);
return num_of_snums;
}
EXPORT_SYMBOL(qe_get_num_of_snums);
#if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
static int qe_resume(struct platform_device *ofdev)
{
if (!qe_alive_during_sleep())
qe_reset();
return 0;
}
static int qe_probe(struct platform_device *ofdev)
{
return 0;
}
static const struct of_device_id qe_ids[] = {
{ .compatible = "fsl,qe", },
{ },
};
static struct platform_driver qe_driver = {
.driver = {
.name = "fsl-qe",
.owner = THIS_MODULE,
.of_match_table = qe_ids,
},
.probe = qe_probe,
.resume = qe_resume,
};
static int __init qe_drv_init(void)
{
return platform_driver_register(&qe_driver);
}
device_initcall(qe_drv_init);
#endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */
| gpl-2.0 |
bond-os/linux | arch/um/drivers/daemon_user.c | 4706 | 4368 | /*
* Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
* Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
* James Leu (jleu@mindspring.net).
* Copyright (C) 2001 by various other people who didn't put their name here.
* Licensed under the GPL.
*/
#include <stdint.h>
#include <unistd.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <sys/time.h>
#include <sys/un.h>
#include "daemon.h"
#include "net_user.h"
#include "os.h"
#include "um_malloc.h"
#include "user.h"
enum request_type { REQ_NEW_CONTROL };
#define SWITCH_MAGIC 0xfeedface
struct request_v3 {
uint32_t magic;
uint32_t version;
enum request_type type;
struct sockaddr_un sock;
};
static struct sockaddr_un *new_addr(void *name, int len)
{
struct sockaddr_un *sun;
sun = uml_kmalloc(sizeof(struct sockaddr_un), UM_GFP_KERNEL);
if (sun == NULL) {
printk(UM_KERN_ERR "new_addr: allocation of sockaddr_un "
"failed\n");
return NULL;
}
sun->sun_family = AF_UNIX;
memcpy(sun->sun_path, name, len);
return sun;
}
static int connect_to_switch(struct daemon_data *pri)
{
struct sockaddr_un *ctl_addr = pri->ctl_addr;
struct sockaddr_un *local_addr = pri->local_addr;
struct sockaddr_un *sun;
struct request_v3 req;
int fd, n, err;
pri->control = socket(AF_UNIX, SOCK_STREAM, 0);
if (pri->control < 0) {
err = -errno;
printk(UM_KERN_ERR "daemon_open : control socket failed, "
"errno = %d\n", -err);
return err;
}
if (connect(pri->control, (struct sockaddr *) ctl_addr,
sizeof(*ctl_addr)) < 0) {
err = -errno;
printk(UM_KERN_ERR "daemon_open : control connect failed, "
"errno = %d\n", -err);
goto out;
}
fd = socket(AF_UNIX, SOCK_DGRAM, 0);
if (fd < 0) {
err = -errno;
printk(UM_KERN_ERR "daemon_open : data socket failed, "
"errno = %d\n", -err);
goto out;
}
if (bind(fd, (struct sockaddr *) local_addr, sizeof(*local_addr)) < 0) {
err = -errno;
printk(UM_KERN_ERR "daemon_open : data bind failed, "
"errno = %d\n", -err);
goto out_close;
}
sun = uml_kmalloc(sizeof(struct sockaddr_un), UM_GFP_KERNEL);
if (sun == NULL) {
printk(UM_KERN_ERR "new_addr: allocation of sockaddr_un "
"failed\n");
err = -ENOMEM;
goto out_close;
}
req.magic = SWITCH_MAGIC;
req.version = SWITCH_VERSION;
req.type = REQ_NEW_CONTROL;
req.sock = *local_addr;
n = write(pri->control, &req, sizeof(req));
if (n != sizeof(req)) {
printk(UM_KERN_ERR "daemon_open : control setup request "
"failed, err = %d\n", -errno);
err = -ENOTCONN;
goto out_free;
}
n = read(pri->control, sun, sizeof(*sun));
if (n != sizeof(*sun)) {
printk(UM_KERN_ERR "daemon_open : read of data socket failed, "
"err = %d\n", -errno);
err = -ENOTCONN;
goto out_free;
}
pri->data_addr = sun;
return fd;
out_free:
kfree(sun);
out_close:
close(fd);
out:
close(pri->control);
return err;
}
static int daemon_user_init(void *data, void *dev)
{
struct daemon_data *pri = data;
struct timeval tv;
struct {
char zero;
int pid;
int usecs;
} name;
if (!strcmp(pri->sock_type, "unix"))
pri->ctl_addr = new_addr(pri->ctl_sock,
strlen(pri->ctl_sock) + 1);
name.zero = 0;
name.pid = os_getpid();
gettimeofday(&tv, NULL);
name.usecs = tv.tv_usec;
pri->local_addr = new_addr(&name, sizeof(name));
pri->dev = dev;
pri->fd = connect_to_switch(pri);
if (pri->fd < 0) {
kfree(pri->local_addr);
pri->local_addr = NULL;
return pri->fd;
}
return 0;
}
static int daemon_open(void *data)
{
struct daemon_data *pri = data;
return pri->fd;
}
static void daemon_remove(void *data)
{
struct daemon_data *pri = data;
close(pri->fd);
pri->fd = -1;
close(pri->control);
pri->control = -1;
kfree(pri->data_addr);
pri->data_addr = NULL;
kfree(pri->ctl_addr);
pri->ctl_addr = NULL;
kfree(pri->local_addr);
pri->local_addr = NULL;
}
int daemon_user_write(int fd, void *buf, int len, struct daemon_data *pri)
{
struct sockaddr_un *data_addr = pri->data_addr;
return net_sendto(fd, buf, len, data_addr, sizeof(*data_addr));
}
const struct net_user_info daemon_user_info = {
.init = daemon_user_init,
.open = daemon_open,
.close = NULL,
.remove = daemon_remove,
.add_address = NULL,
.delete_address = NULL,
.mtu = ETH_MAX_PACKET,
.max_packet = ETH_MAX_PACKET + ETH_HEADER_OTHER,
};
| gpl-2.0 |
kldoc/android_kernel_lge_mako | arch/powerpc/boot/uartlite.c | 14178 | 1778 | /*
* Xilinx UARTLITE bootloader driver
*
* Copyright (C) 2007 Secret Lab Technologies Ltd.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "string.h"
#include "stdio.h"
#include "io.h"
#include "ops.h"
#define ULITE_RX 0x00
#define ULITE_TX 0x04
#define ULITE_STATUS 0x08
#define ULITE_CONTROL 0x0c
#define ULITE_STATUS_RXVALID 0x01
#define ULITE_STATUS_TXFULL 0x08
#define ULITE_CONTROL_RST_RX 0x02
static void * reg_base;
static int uartlite_open(void)
{
/* Clear the RX FIFO */
out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
return 0;
}
static void uartlite_putc(unsigned char c)
{
u32 reg = ULITE_STATUS_TXFULL;
while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
reg = in_be32(reg_base + ULITE_STATUS);
out_be32(reg_base + ULITE_TX, c);
}
static unsigned char uartlite_getc(void)
{
u32 reg = 0;
while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
reg = in_be32(reg_base + ULITE_STATUS);
return in_be32(reg_base + ULITE_RX);
}
static u8 uartlite_tstc(void)
{
u32 reg = in_be32(reg_base + ULITE_STATUS);
return reg & ULITE_STATUS_RXVALID;
}
int uartlite_console_init(void *devp, struct serial_console_data *scdp)
{
int n;
unsigned long reg_phys;
n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
if (n != sizeof(reg_base)) {
if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
return -1;
reg_base = (void *)reg_phys;
}
scdp->open = uartlite_open;
scdp->putc = uartlite_putc;
scdp->getc = uartlite_getc;
scdp->tstc = uartlite_tstc;
scdp->close = NULL;
return 0;
}
| gpl-2.0 |
android-legacy/android_kernel_exynos | arch/arm/mach-exynos/mdm_device.c | 99 | 5173 | #include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <mach/gpio-exynos4.h>
#include <plat/gpio-cfg.h>
#include <plat/devs.h>
#include <plat/ehci.h>
#include <linux/msm_charm.h>
#include <mach/mdm2.h>
#include "mdm_private.h"
#include <linux/cpufreq_pegasusq.h>
#include <mach/cpufreq.h>
#include <mach/dev.h>
static struct resource mdm_resources[] = {
{
.start = GPIO_MDM2AP_ERR_FATAL,
.end = GPIO_MDM2AP_ERR_FATAL,
.name = "MDM2AP_ERRFATAL",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_AP2MDM_ERR_FATAL,
.end = GPIO_AP2MDM_ERR_FATAL,
.name = "AP2MDM_ERRFATAL",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_MDM2AP_STATUS,
.end = GPIO_MDM2AP_STATUS,
.name = "MDM2AP_STATUS",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_AP2MDM_STATUS,
.end = GPIO_AP2MDM_STATUS,
.name = "AP2MDM_STATUS",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_AP2MDM_PON_RESET_N,
.end = GPIO_AP2MDM_PON_RESET_N,
.name = "AP2MDM_SOFT_RESET",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_AP2MDM_PMIC_RESET_N,
.end = GPIO_AP2MDM_PMIC_RESET_N,
.name = "AP2MDM_PMIC_PWR_EN",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_AP2MDM_WAKEUP,
.end = GPIO_AP2MDM_WAKEUP,
.name = "AP2MDM_WAKEUP",
.flags = IORESOURCE_IO,
},
};
#ifdef CONFIG_MDM_HSIC_PM
static struct resource mdm_pm_resource[] = {
{
.start = GPIO_AP2MDM_HSIC_PORT_ACTIVE,
.end = GPIO_AP2MDM_HSIC_PORT_ACTIVE,
.name = "AP2MDM_HSIC_ACTIVE",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_MDM2AP_HSIC_PWR_ACTIVE,
.end = GPIO_MDM2AP_HSIC_PWR_ACTIVE,
.name = "MDM2AP_DEVICE_PWR_ACTIVE",
.flags = IORESOURCE_IO,
},
{
.start = GPIO_MDM2AP_HSIC_RESUME_REQ,
.end = GPIO_MDM2AP_HSIC_RESUME_REQ,
.name = "MDM2AP_RESUME_REQ",
.flags = IORESOURCE_IO,
},
};
static int exynos_frequency_lock(struct device *dev);
static int exynos_frequency_unlock(struct device *dev);
static struct mdm_hsic_pm_platform_data mdm_hsic_pm_pdata = {
.freqlock = ATOMIC_INIT(0),
.freq_lock = exynos_frequency_lock,
.freq_unlock = exynos_frequency_unlock,
};
struct platform_device mdm_pm_device = {
.name = "mdm_hsic_pm0",
.id = -1,
.num_resources = ARRAY_SIZE(mdm_pm_resource),
.resource = mdm_pm_resource,
};
#endif
static struct mdm_platform_data mdm_platform_data = {
.mdm_version = "3.0",
.ramdump_delay_ms = 2000,
.early_power_on = 1,
.sfr_query = 0,
.vddmin_resource = NULL,
#ifdef CONFIG_USB_EHCI_S5P
.peripheral_platform_device_ehci = &s5p_device_ehci,
#endif
#ifdef CONFIG_USB_OHCI_S5P
.peripheral_platform_device_ohci = &s5p_device_ohci,
#endif
.ramdump_timeout_ms = 120000,
};
static int exynos_frequency_lock(struct device *dev)
{
unsigned int level, cpufreq = 1400; /* 200 ~ 1400 */
unsigned int busfreq = 400200; /* 100100 ~ 400200 */
int ret = 0;
struct device *busdev = dev_get("exynos-busfreq");
if (atomic_read(&mdm_hsic_pm_pdata.freqlock) == 0) {
/* cpu frequency lock */
ret = exynos_cpufreq_get_level(cpufreq * 1000, &level);
if (ret < 0) {
pr_err("ERR: exynos_cpufreq_get_level fail: %d\n",
ret);
goto exit;
}
ret = exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level);
if (ret < 0) {
pr_err("ERR: exynos_cpufreq_lock fail: %d\n", ret);
goto exit;
}
/* bus frequncy lock */
if (!busdev) {
pr_err("ERR: busdev is not exist\n");
ret = -ENODEV;
goto exit;
}
ret = dev_lock(busdev, dev, busfreq);
if (ret < 0) {
pr_err("ERR: dev_lock error: %d\n", ret);
goto exit;
}
/* lock minimum number of cpu cores */
cpufreq_pegasusq_min_cpu_lock(2);
atomic_set(&mdm_hsic_pm_pdata.freqlock, 1);
pr_debug("level=%d, cpufreq=%d MHz, busfreq=%06d\n",
level, cpufreq, busfreq);
}
exit:
return ret;
}
static int exynos_frequency_unlock(struct device *dev)
{
int ret = 0;
struct device *busdev = dev_get("exynos-busfreq");
if (atomic_read(&mdm_hsic_pm_pdata.freqlock) == 1) {
/* cpu frequency unlock */
exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF);
/* bus frequency unlock */
ret = dev_unlock(busdev, dev);
if (ret < 0) {
pr_err("ERR: dev_unlock error: %d\n", ret);
goto exit;
}
/* unlock minimum number of cpu cores */
cpufreq_pegasusq_min_cpu_unlock();
atomic_set(&mdm_hsic_pm_pdata.freqlock, 0);
pr_debug("success\n");
}
exit:
return ret;
}
struct platform_device mdm_device = {
.name = "mdm2_modem",
.id = -1,
.num_resources = ARRAY_SIZE(mdm_resources),
.resource = mdm_resources,
};
static int __init init_mdm_modem(void)
{
int ret;
pr_info("%s: registering modem dev, pm dev\n", __func__);
mdm_pm_device.dev.platform_data = &mdm_hsic_pm_pdata;
((struct mdm_hsic_pm_platform_data *)
mdm_pm_device.dev.platform_data)->dev =
&mdm_pm_device.dev;
#ifdef CONFIG_MDM_HSIC_PM
ret = platform_device_register(&mdm_pm_device);
if (ret < 0) {
pr_err("%s: fail to register mdm hsic pm dev(err:%d)\n",
__func__, ret);
return ret;
}
#endif
mdm_device.dev.platform_data = &mdm_platform_data;
ret = platform_device_register(&mdm_device);
if (ret < 0) {
pr_err("%s: fail to register mdm modem dev(err:%d)\n",
__func__, ret);
return ret;
}
return 0;
}
module_init(init_mdm_modem);
| gpl-2.0 |
TroNit/BlackDome_New_supersonic | arch/arm/mach-mx5/mm.c | 99 | 2493 | /*
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*
* Create static mapping between physical to virtual memory.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-v3.h>
/*
* Define the MX51 memory map.
*/
static struct map_desc mx51_io_desc[] __initdata = {
imx_map_entry(MX51, IRAM, MT_DEVICE),
imx_map_entry(MX51, DEBUG, MT_DEVICE),
imx_map_entry(MX51, AIPS1, MT_DEVICE),
imx_map_entry(MX51, SPBA0, MT_DEVICE),
imx_map_entry(MX51, AIPS2, MT_DEVICE),
};
/*
* Define the MX53 memory map.
*/
static struct map_desc mx53_io_desc[] __initdata = {
imx_map_entry(MX53, AIPS1, MT_DEVICE),
imx_map_entry(MX53, SPBA0, MT_DEVICE),
imx_map_entry(MX53, AIPS2, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx51_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}
void __init mx53_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX53);
mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
}
int imx51_register_gpios(void);
void __init mx51_init_irq(void)
{
unsigned long tzic_addr;
void __iomem *tzic_virt;
if (mx51_revision() < IMX_CHIP_REVISION_2_0)
tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
else
tzic_addr = MX51_TZIC_BASE_ADDR;
tzic_virt = ioremap(tzic_addr, SZ_16K);
if (!tzic_virt)
panic("unable to map TZIC interrupt controller\n");
tzic_init_irq(tzic_virt);
imx51_register_gpios();
}
int imx53_register_gpios(void);
void __init mx53_init_irq(void)
{
unsigned long tzic_addr;
void __iomem *tzic_virt;
tzic_addr = MX53_TZIC_BASE_ADDR;
tzic_virt = ioremap(tzic_addr, SZ_16K);
if (!tzic_virt)
panic("unable to map TZIC interrupt controller\n");
tzic_init_irq(tzic_virt);
imx53_register_gpios();
}
| gpl-2.0 |
smarkwell/asuswrt-merlin | release/src/router/samba-3.0.25b/testsuite/libsmbclient/src/unlink_print_job/unlink_print_job_4.c | 99 | 2216 | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <libsmbclient.h>
#define MAX_BUFF_SIZE 255
char g_workgroup[MAX_BUFF_SIZE];
char g_username[MAX_BUFF_SIZE];
char g_password[MAX_BUFF_SIZE];
char g_server[MAX_BUFF_SIZE];
char g_share[MAX_BUFF_SIZE];
char g_print_user[MAX_BUFF_SIZE];
char g_print_name[MAX_BUFF_SIZE];
unsigned int g_print_id;
unsigned int g_print_priority;
unsigned int g_print_size;
void auth_fn(const char *server, const char *share, char *workgroup, int wgmaxlen,
char *username, int unmaxlen, char *password, int pwmaxlen)
{
strncpy(workgroup, g_workgroup, wgmaxlen - 1);
strncpy(username, g_username, unmaxlen - 1);
strncpy(password, g_password, pwmaxlen - 1);
strcpy(g_server, server);
strcpy(g_share, share);
}
void print_list_fn(struct print_job_info *pji)
{
g_print_id = pji->id;
g_print_priority = pji->priority;
g_print_size = pji->size;
strcpy(g_print_user,pji->user);
strcpy(g_print_name,pji->name);
/* fprintf(stdout, "Print job: ID: %u, Prio: %u, Size: %u, User: %s, Name: %s\n",
pji->id, pji->priority, pji->size, pji->user, pji->name); */
}
int main(int argc, char** argv)
{
int err = -1;
int fd = 0;
int msg_len = 0;
char url[MAX_BUFF_SIZE];
char* message;
bzero(g_workgroup,MAX_BUFF_SIZE);
bzero(url,MAX_BUFF_SIZE);
bzero(g_print_user,MAX_BUFF_SIZE);
bzero(g_print_name,MAX_BUFF_SIZE);
g_print_id = 0;
g_print_priority = 0;
g_print_size = 0;
if ( argc == 7 )
{
strncpy(g_workgroup,argv[1],strlen(argv[1]));
strncpy(g_username,argv[2],strlen(argv[2]));
strncpy(g_password,argv[3],strlen(argv[3]));
strncpy(url,argv[4],strlen(argv[4]));
msg_len = strlen(argv[5])+1;
message = malloc(msg_len);
message[msg_len - 1] = 0;
strncpy(message,argv[5],msg_len);
/* printf("Message: %s\n",message); */
/* printf("Message len: %i\n",msg_len); */
smbc_init(auth_fn, 0);
smbc_unlink(url);
fd = smbc_open(url,O_RDWR | O_CREAT, 0666);
smbc_write(fd, message, msg_len);
smbc_close(fd);
free(message);
smbc_print_file(url,argv[6]);
smbc_list_print_jobs(argv[6],print_list_fn);
smbc_unlink_print_job(argv[6],g_print_id);
err = errno;
}
return err;
}
| gpl-2.0 |
rettigs/linux-yocto-3.14 | drivers/staging/comedi/drivers/ni_tio.c | 355 | 48205 | /*
comedi/drivers/ni_tio.c
Support for NI general purpose counters
Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
*/
/*
Driver: ni_tio
Description: National Instruments general purpose counters
Devices:
Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
Herman.Bruyninckx@mech.kuleuven.ac.be,
Wim.Meeussen@mech.kuleuven.ac.be,
Klaas.Gadeyne@mech.kuleuven.ac.be,
Frank Mori Hess <fmhess@users.sourceforge.net>
Updated: Thu Nov 16 09:50:32 EST 2006
Status: works
This module is not used directly by end-users. Rather, it
is used by other drivers (for example ni_660x and ni_pcimio)
to provide support for NI's general purpose counters. It was
originally based on the counter code from ni_660x.c and
ni_mio_common.c.
References:
DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
DAQ 6601/6602 User Manual (NI 322137B-01)
340934b.pdf DAQ-STC reference manual
*/
/*
TODO:
Support use of both banks X and Y
*/
#include <linux/module.h>
#include <linux/slab.h>
#include "ni_tio_internal.h"
static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
unsigned generic_clock_source);
static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
static inline enum Gi_Counting_Mode_Reg_Bits Gi_Alternate_Sync_Bit(enum
ni_gpct_variant
variant)
{
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
break;
case ni_gpct_variant_m_series:
return Gi_M_Series_Alternate_Sync_Bit;
break;
case ni_gpct_variant_660x:
return Gi_660x_Alternate_Sync_Bit;
break;
default:
BUG();
break;
}
return 0;
}
static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X2_Bit(enum
ni_gpct_variant
variant)
{
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
break;
case ni_gpct_variant_m_series:
return Gi_M_Series_Prescale_X2_Bit;
break;
case ni_gpct_variant_660x:
return Gi_660x_Prescale_X2_Bit;
break;
default:
BUG();
break;
}
return 0;
}
static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X8_Bit(enum
ni_gpct_variant
variant)
{
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
break;
case ni_gpct_variant_m_series:
return Gi_M_Series_Prescale_X8_Bit;
break;
case ni_gpct_variant_660x:
return Gi_660x_Prescale_X8_Bit;
break;
default:
BUG();
break;
}
return 0;
}
static inline enum Gi_Counting_Mode_Reg_Bits Gi_HW_Arm_Select_Mask(enum
ni_gpct_variant
variant)
{
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
break;
case ni_gpct_variant_m_series:
return Gi_M_Series_HW_Arm_Select_Mask;
break;
case ni_gpct_variant_660x:
return Gi_660x_HW_Arm_Select_Mask;
break;
default:
BUG();
break;
}
return 0;
}
/* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
enum ni_660x_clock_source {
NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
NI_660x_Source_Pin_i_Clock = 0x1,
NI_660x_Next_Gate_Clock = 0xa,
NI_660x_Timebase_2_Clock = 0x12, /* 100KHz */
NI_660x_Next_TC_Clock = 0x13,
NI_660x_Timebase_3_Clock = 0x1e, /* 80MHz */
NI_660x_Logic_Low_Clock = 0x1f,
};
static const unsigned ni_660x_max_rtsi_channel = 6;
static inline unsigned NI_660x_RTSI_Clock(unsigned n)
{
BUG_ON(n > ni_660x_max_rtsi_channel);
return 0xb + n;
}
static const unsigned ni_660x_max_source_pin = 7;
static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
{
BUG_ON(n > ni_660x_max_source_pin);
return 0x2 + n;
}
/* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
enum ni_m_series_clock_source {
NI_M_Series_Timebase_1_Clock = 0x0, /* 20MHz */
NI_M_Series_Timebase_2_Clock = 0x12, /* 100KHz */
NI_M_Series_Next_TC_Clock = 0x13,
NI_M_Series_Next_Gate_Clock = 0x14, /* when Gi_Src_SubSelect = 0 */
NI_M_Series_PXI_Star_Trigger_Clock = 0x14, /* when Gi_Src_SubSelect = 1 */
NI_M_Series_PXI10_Clock = 0x1d,
NI_M_Series_Timebase_3_Clock = 0x1e, /* 80MHz, when Gi_Src_SubSelect = 0 */
NI_M_Series_Analog_Trigger_Out_Clock = 0x1e, /* when Gi_Src_SubSelect = 1 */
NI_M_Series_Logic_Low_Clock = 0x1f,
};
static const unsigned ni_m_series_max_pfi_channel = 15;
static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
{
BUG_ON(n > ni_m_series_max_pfi_channel);
if (n < 10)
return 1 + n;
else
return 0xb + n;
}
static const unsigned ni_m_series_max_rtsi_channel = 7;
static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
{
BUG_ON(n > ni_m_series_max_rtsi_channel);
if (n == 7)
return 0x1b;
else
return 0xb + n;
}
enum ni_660x_gate_select {
NI_660x_Source_Pin_i_Gate_Select = 0x0,
NI_660x_Gate_Pin_i_Gate_Select = 0x1,
NI_660x_Next_SRC_Gate_Select = 0xa,
NI_660x_Next_Out_Gate_Select = 0x14,
NI_660x_Logic_Low_Gate_Select = 0x1f,
};
static const unsigned ni_660x_max_gate_pin = 7;
static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
{
BUG_ON(n > ni_660x_max_gate_pin);
return 0x2 + n;
}
static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
{
BUG_ON(n > ni_660x_max_rtsi_channel);
return 0xb + n;
}
enum ni_m_series_gate_select {
NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
NI_M_Series_AI_START2_Gate_Select = 0x12,
NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
NI_M_Series_Next_Out_Gate_Select = 0x14,
NI_M_Series_AI_START1_Gate_Select = 0x1c,
NI_M_Series_Next_SRC_Gate_Select = 0x1d,
NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
NI_M_Series_Logic_Low_Gate_Select = 0x1f,
};
static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
{
BUG_ON(n > ni_m_series_max_rtsi_channel);
if (n == 7)
return 0x1b;
return 0xb + n;
}
static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
{
BUG_ON(n > ni_m_series_max_pfi_channel);
if (n < 10)
return 1 + n;
return 0xb + n;
}
static inline unsigned Gi_Source_Select_Bits(unsigned source)
{
return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
}
static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
{
return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
}
enum ni_660x_second_gate_select {
NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
NI_660x_Next_SRC_Second_Gate_Select = 0xa,
NI_660x_Next_Out_Second_Gate_Select = 0x14,
NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
};
static const unsigned ni_660x_max_up_down_pin = 7;
static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
{
BUG_ON(n > ni_660x_max_up_down_pin);
return 0x2 + n;
}
static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
{
BUG_ON(n > ni_660x_max_rtsi_channel);
return 0xb + n;
}
static const unsigned int counter_status_mask =
COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device *dev,
void (*write_register) (struct
ni_gpct
*
counter,
unsigned
bits,
enum
ni_gpct_register
reg),
unsigned (*read_register)
(struct ni_gpct *counter,
enum ni_gpct_register reg),
enum ni_gpct_variant variant,
unsigned num_counters)
{
unsigned i;
struct ni_gpct_device *counter_dev =
kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
if (counter_dev == NULL)
return NULL;
counter_dev->dev = dev;
counter_dev->write_register = write_register;
counter_dev->read_register = read_register;
counter_dev->variant = variant;
spin_lock_init(&counter_dev->regs_lock);
BUG_ON(num_counters == 0);
counter_dev->counters =
kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
if (counter_dev->counters == NULL) {
kfree(counter_dev);
return NULL;
}
for (i = 0; i < num_counters; ++i) {
counter_dev->counters[i].counter_dev = counter_dev;
spin_lock_init(&counter_dev->counters[i].lock);
}
counter_dev->num_counters = num_counters;
return counter_dev;
}
EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
{
if (counter_dev->counters == NULL)
return;
kfree(counter_dev->counters);
kfree(counter_dev);
}
EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
static int ni_tio_second_gate_registers_present(const struct ni_gpct_device
*counter_dev)
{
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
return 0;
break;
case ni_gpct_variant_m_series:
case ni_gpct_variant_660x:
return 1;
break;
default:
BUG();
break;
}
return 0;
}
static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
{
unsigned cidx = counter->counter_index;
write_register(counter, Gi_Reset_Bit(cidx), NITIO_RESET_REG(cidx));
}
void ni_tio_init_counter(struct ni_gpct *counter)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
ni_tio_reset_count_and_disarm(counter);
/* initialize counter registers */
counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
write_register(counter, counter_dev->regs[NITIO_AUTO_INC_REG(cidx)],
NITIO_AUTO_INC_REG(cidx));
ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
~0, Gi_Synchronize_Gate_Bit);
ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
write_register(counter, counter_dev->regs[NITIO_LOADA_REG(cidx)],
NITIO_LOADA_REG(cidx));
counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
write_register(counter, counter_dev->regs[NITIO_LOADB_REG(cidx)],
NITIO_LOADB_REG(cidx));
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
if (ni_tio_counting_mode_registers_present(counter_dev))
ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
if (ni_tio_second_gate_registers_present(counter_dev)) {
counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
write_register(counter,
counter_dev->regs[NITIO_GATE2_REG(cidx)],
NITIO_GATE2_REG(cidx));
}
ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
}
EXPORT_SYMBOL_GPL(ni_tio_init_counter);
static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
{
unsigned cidx = counter->counter_index;
const unsigned bits = read_register(counter,
NITIO_SHARED_STATUS_REG(cidx));
unsigned int status = 0;
if (bits & Gi_Armed_Bit(cidx)) {
status |= COMEDI_COUNTER_ARMED;
if (bits & Gi_Counting_Bit(cidx))
status |= COMEDI_COUNTER_COUNTING;
}
return status;
}
static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
static const uint64_t min_normal_sync_period_ps = 25000;
const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
ni_tio_generic_clock_src_select
(counter));
if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
return;
switch (ni_tio_get_soft_copy(counter, counting_mode_reg) & Gi_Counting_Mode_Mask) {
case Gi_Counting_Mode_QuadratureX1_Bits:
case Gi_Counting_Mode_QuadratureX2_Bits:
case Gi_Counting_Mode_QuadratureX4_Bits:
case Gi_Counting_Mode_Sync_Source_Bits:
force_alt_sync = 1;
break;
default:
break;
}
/* It's not clear what we should do if clock_period is unknown, so we are not
using the alt sync bit in that case, but allow the caller to decide by using the
force_alt_sync parameter. */
if (force_alt_sync ||
(clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
ni_tio_set_bits(counter, counting_mode_reg,
Gi_Alternate_Sync_Bit(counter_dev->variant),
Gi_Alternate_Sync_Bit(counter_dev->variant));
} else {
ni_tio_set_bits(counter, counting_mode_reg,
Gi_Alternate_Sync_Bit(counter_dev->variant),
0x0);
}
}
static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
unsigned mode_reg_mask;
unsigned mode_reg_values;
unsigned input_select_bits = 0;
/* these bits map directly on to the mode register */
static const unsigned mode_reg_direct_mask =
NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
mode_reg_values = mode & mode_reg_direct_mask;
switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
break;
case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
mode_reg_values |= Gi_Reload_Source_Switching_Bit;
break;
case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
mode_reg_mask |= Gi_Gating_Mode_Mask;
mode_reg_values |= Gi_Level_Gating_Bits;
break;
default:
break;
}
ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
mode_reg_mask, mode_reg_values);
if (ni_tio_counting_mode_registers_present(counter_dev)) {
unsigned counting_mode_bits = 0;
counting_mode_bits |=
(mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
Gi_Counting_Mode_Mask;
counting_mode_bits |=
((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
if (mode & NI_GPCT_INDEX_ENABLE_BIT)
counting_mode_bits |= Gi_Index_Mode_Bit;
ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
Gi_Index_Mode_Bit, counting_mode_bits);
ni_tio_set_sync_mode(counter, 0);
}
ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
Gi_Up_Down_Mask,
(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
Gi_Up_Down_Shift);
if (mode & NI_GPCT_OR_GATE_BIT)
input_select_bits |= Gi_Or_Gate_Bit;
if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
input_select_bits |= Gi_Output_Polarity_Bit;
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
Gi_Output_Polarity_Bit, input_select_bits);
return 0;
}
int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
unsigned command_transient_bits = 0;
if (arm) {
switch (start_trigger) {
case NI_GPCT_ARM_IMMEDIATE:
command_transient_bits |= Gi_Arm_Bit;
break;
case NI_GPCT_ARM_PAIRED_IMMEDIATE:
command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
break;
default:
break;
}
if (ni_tio_counting_mode_registers_present(counter_dev)) {
unsigned counting_mode_bits = 0;
switch (start_trigger) {
case NI_GPCT_ARM_IMMEDIATE:
case NI_GPCT_ARM_PAIRED_IMMEDIATE:
break;
default:
if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
/* pass-through the least significant bits so we can figure out what select later */
unsigned hw_arm_select_bits =
(start_trigger <<
Gi_HW_Arm_Select_Shift) &
Gi_HW_Arm_Select_Mask
(counter_dev->variant);
counting_mode_bits |=
Gi_HW_Arm_Enable_Bit |
hw_arm_select_bits;
} else {
return -EINVAL;
}
break;
}
ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
Gi_HW_Arm_Select_Mask
(counter_dev->variant) |
Gi_HW_Arm_Enable_Bit,
counting_mode_bits);
}
} else {
command_transient_bits |= Gi_Disarm_Bit;
}
ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
0, 0, command_transient_bits);
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_arm);
static unsigned ni_660x_source_select_bits(unsigned int clock_source)
{
unsigned ni_660x_clock;
unsigned i;
const unsigned clock_select_bits =
clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
switch (clock_select_bits) {
case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Timebase_1_Clock;
break;
case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Timebase_2_Clock;
break;
case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Timebase_3_Clock;
break;
case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Logic_Low_Clock;
break;
case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Source_Pin_i_Clock;
break;
case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Next_Gate_Clock;
break;
case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
ni_660x_clock = NI_660x_Next_TC_Clock;
break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
ni_660x_clock = NI_660x_RTSI_Clock(i);
break;
}
}
if (i <= ni_660x_max_rtsi_channel)
break;
for (i = 0; i <= ni_660x_max_source_pin; ++i) {
if (clock_select_bits ==
NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
ni_660x_clock = NI_660x_Source_Pin_Clock(i);
break;
}
}
if (i <= ni_660x_max_source_pin)
break;
ni_660x_clock = 0;
BUG();
break;
}
return Gi_Source_Select_Bits(ni_660x_clock);
}
static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
{
unsigned ni_m_series_clock;
unsigned i;
const unsigned clock_select_bits =
clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
switch (clock_select_bits) {
case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
break;
case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
break;
case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
break;
case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
break;
case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
break;
case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Next_TC_Clock;
break;
case NI_GPCT_PXI10_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_PXI10_Clock;
break;
case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
break;
case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
break;
default:
for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
break;
}
}
if (i <= ni_m_series_max_rtsi_channel)
break;
for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
ni_m_series_clock = NI_M_Series_PFI_Clock(i);
break;
}
}
if (i <= ni_m_series_max_pfi_channel)
break;
printk(KERN_ERR "invalid clock source 0x%lx\n",
(unsigned long)clock_source);
BUG();
ni_m_series_clock = 0;
break;
}
return Gi_Source_Select_Bits(ni_m_series_clock);
};
static void ni_tio_set_source_subselect(struct ni_gpct *counter,
unsigned int clock_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
if (counter_dev->variant != ni_gpct_variant_m_series)
return;
switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
/* Gi_Source_Subselect is zero */
case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
break;
/* Gi_Source_Subselect is one */
case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
break;
/* Gi_Source_Subselect doesn't matter */
default:
return;
break;
}
write_register(counter, counter_dev->regs[second_gate_reg],
second_gate_reg);
}
static int ni_tio_set_clock_src(struct ni_gpct *counter,
unsigned int clock_source,
unsigned int period_ns)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
unsigned input_select_bits = 0;
static const uint64_t pico_per_nano = 1000;
/*FIXME: validate clock source */
switch (counter_dev->variant) {
case ni_gpct_variant_660x:
input_select_bits |= ni_660x_source_select_bits(clock_source);
break;
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
input_select_bits |=
ni_m_series_source_select_bits(clock_source);
break;
default:
BUG();
break;
}
if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
input_select_bits |= Gi_Source_Polarity_Bit;
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
input_select_bits);
ni_tio_set_source_subselect(counter, clock_source);
if (ni_tio_counting_mode_registers_present(counter_dev)) {
const unsigned prescaling_mode =
clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
unsigned counting_mode_bits = 0;
switch (prescaling_mode) {
case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
break;
case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
counting_mode_bits |=
Gi_Prescale_X2_Bit(counter_dev->variant);
break;
case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
counting_mode_bits |=
Gi_Prescale_X8_Bit(counter_dev->variant);
break;
default:
return -EINVAL;
break;
}
ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
Gi_Prescale_X2_Bit(counter_dev->variant) |
Gi_Prescale_X8_Bit(counter_dev->variant),
counting_mode_bits);
}
counter->clock_period_ps = pico_per_nano * period_ns;
ni_tio_set_sync_mode(counter, 0);
return 0;
}
static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned counting_mode_bits =
ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
unsigned bits = 0;
if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
Gi_Source_Polarity_Bit)
bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
return bits;
}
static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
unsigned clock_source = 0;
unsigned i;
const unsigned input_select =
(ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
switch (input_select) {
case NI_M_Series_Timebase_1_Clock:
clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
break;
case NI_M_Series_Timebase_2_Clock:
clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
break;
case NI_M_Series_Timebase_3_Clock:
if (counter_dev->regs[second_gate_reg] &
Gi_Source_Subselect_Bit)
clock_source =
NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
else
clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
break;
case NI_M_Series_Logic_Low_Clock:
clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
break;
case NI_M_Series_Next_Gate_Clock:
if (counter_dev->regs[second_gate_reg] &
Gi_Source_Subselect_Bit)
clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
else
clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
break;
case NI_M_Series_PXI10_Clock:
clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
break;
case NI_M_Series_Next_TC_Clock:
clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
break;
default:
for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
if (input_select == NI_M_Series_RTSI_Clock(i)) {
clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
break;
}
}
if (i <= ni_m_series_max_rtsi_channel)
break;
for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
if (input_select == NI_M_Series_PFI_Clock(i)) {
clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
break;
}
}
if (i <= ni_m_series_max_pfi_channel)
break;
BUG();
break;
}
clock_source |= ni_tio_clock_src_modifiers(counter);
return clock_source;
}
static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
{
unsigned clock_source = 0;
unsigned cidx = counter->counter_index;
const unsigned input_select =
(ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
unsigned i;
switch (input_select) {
case NI_660x_Timebase_1_Clock:
clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
break;
case NI_660x_Timebase_2_Clock:
clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
break;
case NI_660x_Timebase_3_Clock:
clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
break;
case NI_660x_Logic_Low_Clock:
clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
break;
case NI_660x_Source_Pin_i_Clock:
clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
break;
case NI_660x_Next_Gate_Clock:
clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
break;
case NI_660x_Next_TC_Clock:
clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (input_select == NI_660x_RTSI_Clock(i)) {
clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
break;
}
}
if (i <= ni_660x_max_rtsi_channel)
break;
for (i = 0; i <= ni_660x_max_source_pin; ++i) {
if (input_select == NI_660x_Source_Pin_Clock(i)) {
clock_source =
NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
break;
}
}
if (i <= ni_660x_max_source_pin)
break;
BUG();
break;
}
clock_source |= ni_tio_clock_src_modifiers(counter);
return clock_source;
}
static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
{
switch (counter->counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
return ni_m_series_clock_src_select(counter);
break;
case ni_gpct_variant_660x:
return ni_660x_clock_src_select(counter);
break;
default:
BUG();
break;
}
return 0;
}
static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
unsigned generic_clock_source)
{
uint64_t clock_period_ps;
switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
clock_period_ps = 50000;
break;
case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
clock_period_ps = 10000000;
break;
case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
clock_period_ps = 12500;
break;
case NI_GPCT_PXI10_CLOCK_SRC_BITS:
clock_period_ps = 100000;
break;
default:
/* clock period is specified by user with prescaling already taken into account. */
return counter->clock_period_ps;
break;
}
switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
break;
case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
clock_period_ps *= 2;
break;
case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
clock_period_ps *= 8;
break;
default:
BUG();
break;
}
return clock_period_ps;
}
static void ni_tio_get_clock_src(struct ni_gpct *counter,
unsigned int *clock_source,
unsigned int *period_ns)
{
static const unsigned pico_per_nano = 1000;
uint64_t temp64;
*clock_source = ni_tio_generic_clock_src_select(counter);
temp64 = ni_tio_clock_period_ps(counter, *clock_source);
do_div(temp64, pico_per_nano);
*period_ns = temp64;
}
static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
unsigned int gate_source)
{
const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
unsigned cidx = counter->counter_index;
unsigned mode_values = 0;
if (gate_source & CR_INVERT)
mode_values |= Gi_Gate_Polarity_Bit;
if (gate_source & CR_EDGE)
mode_values |= Gi_Rising_Edge_Gating_Bits;
else
mode_values |= Gi_Level_Gating_Bits;
ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
mode_mask, mode_values);
}
static int ni_660x_set_first_gate(struct ni_gpct *counter,
unsigned int gate_source)
{
const unsigned selected_gate = CR_CHAN(gate_source);
unsigned cidx = counter->counter_index;
/* bits of selected_gate that may be meaningful to input select register */
const unsigned selected_gate_mask = 0x1f;
unsigned ni_660x_gate_select;
unsigned i;
switch (selected_gate) {
case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
break;
case NI_GPCT_NEXT_OUT_GATE_SELECT:
case NI_GPCT_LOGIC_LOW_GATE_SELECT:
case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
case NI_GPCT_GATE_PIN_i_GATE_SELECT:
ni_660x_gate_select = selected_gate & selected_gate_mask;
break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
ni_660x_gate_select =
selected_gate & selected_gate_mask;
break;
}
}
if (i <= ni_660x_max_rtsi_channel)
break;
for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
if (selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
ni_660x_gate_select =
selected_gate & selected_gate_mask;
break;
}
}
if (i <= ni_660x_max_gate_pin)
break;
return -EINVAL;
break;
}
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
Gi_Gate_Select_Mask,
Gi_Gate_Select_Bits(ni_660x_gate_select));
return 0;
}
static int ni_m_series_set_first_gate(struct ni_gpct *counter,
unsigned int gate_source)
{
const unsigned selected_gate = CR_CHAN(gate_source);
unsigned cidx = counter->counter_index;
/* bits of selected_gate that may be meaningful to input select register */
const unsigned selected_gate_mask = 0x1f;
unsigned ni_m_series_gate_select;
unsigned i;
switch (selected_gate) {
case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
case NI_GPCT_AI_START2_GATE_SELECT:
case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
case NI_GPCT_NEXT_OUT_GATE_SELECT:
case NI_GPCT_AI_START1_GATE_SELECT:
case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
case NI_GPCT_LOGIC_LOW_GATE_SELECT:
ni_m_series_gate_select = selected_gate & selected_gate_mask;
break;
default:
for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
ni_m_series_gate_select =
selected_gate & selected_gate_mask;
break;
}
}
if (i <= ni_m_series_max_rtsi_channel)
break;
for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
if (selected_gate == NI_GPCT_PFI_GATE_SELECT(i)) {
ni_m_series_gate_select =
selected_gate & selected_gate_mask;
break;
}
}
if (i <= ni_m_series_max_pfi_channel)
break;
return -EINVAL;
break;
}
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
Gi_Gate_Select_Mask,
Gi_Gate_Select_Bits(ni_m_series_gate_select));
return 0;
}
static int ni_660x_set_second_gate(struct ni_gpct *counter,
unsigned int gate_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
const unsigned selected_second_gate = CR_CHAN(gate_source);
/* bits of second_gate that may be meaningful to second gate register */
static const unsigned selected_second_gate_mask = 0x1f;
unsigned ni_660x_second_gate_select;
unsigned i;
switch (selected_second_gate) {
case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
case NI_GPCT_SELECTED_GATE_GATE_SELECT:
case NI_GPCT_NEXT_OUT_GATE_SELECT:
case NI_GPCT_LOGIC_LOW_GATE_SELECT:
ni_660x_second_gate_select =
selected_second_gate & selected_second_gate_mask;
break;
case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
ni_660x_second_gate_select =
NI_660x_Next_SRC_Second_Gate_Select;
break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
ni_660x_second_gate_select =
selected_second_gate &
selected_second_gate_mask;
break;
}
}
if (i <= ni_660x_max_rtsi_channel)
break;
for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
if (selected_second_gate ==
NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
ni_660x_second_gate_select =
selected_second_gate &
selected_second_gate_mask;
break;
}
}
if (i <= ni_660x_max_up_down_pin)
break;
return -EINVAL;
break;
}
counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
counter_dev->regs[second_gate_reg] |=
Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
write_register(counter, counter_dev->regs[second_gate_reg],
second_gate_reg);
return 0;
}
static int ni_m_series_set_second_gate(struct ni_gpct *counter,
unsigned int gate_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
const unsigned selected_second_gate = CR_CHAN(gate_source);
/* bits of second_gate that may be meaningful to second gate register */
static const unsigned selected_second_gate_mask = 0x1f;
unsigned ni_m_series_second_gate_select;
/* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
the bits through for now. */
switch (selected_second_gate) {
default:
ni_m_series_second_gate_select =
selected_second_gate & selected_second_gate_mask;
break;
}
counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
counter_dev->regs[second_gate_reg] |=
Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
write_register(counter, counter_dev->regs[second_gate_reg],
second_gate_reg);
return 0;
}
int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
unsigned int gate_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
switch (gate_index) {
case 0:
if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
Gi_Gating_Mode_Mask,
Gi_Gating_Disabled_Bits);
return 0;
}
ni_tio_set_first_gate_modifiers(counter, gate_source);
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
return ni_m_series_set_first_gate(counter, gate_source);
break;
case ni_gpct_variant_660x:
return ni_660x_set_first_gate(counter, gate_source);
break;
default:
BUG();
break;
}
break;
case 1:
if (ni_tio_second_gate_registers_present(counter_dev) == 0)
return -EINVAL;
if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
counter_dev->regs[second_gate_reg] &=
~Gi_Second_Gate_Mode_Bit;
write_register(counter,
counter_dev->regs[second_gate_reg],
second_gate_reg);
return 0;
}
if (gate_source & CR_INVERT) {
counter_dev->regs[second_gate_reg] |=
Gi_Second_Gate_Polarity_Bit;
} else {
counter_dev->regs[second_gate_reg] &=
~Gi_Second_Gate_Polarity_Bit;
}
switch (counter_dev->variant) {
case ni_gpct_variant_m_series:
return ni_m_series_set_second_gate(counter,
gate_source);
break;
case ni_gpct_variant_660x:
return ni_660x_set_second_gate(counter, gate_source);
break;
default:
BUG();
break;
}
break;
default:
return -EINVAL;
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
unsigned int source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
if (counter_dev->variant == ni_gpct_variant_m_series) {
unsigned int abz_reg, shift, mask;
abz_reg = NITIO_ABZ_REG(cidx);
switch (index) {
case NI_GPCT_SOURCE_ENCODER_A:
shift = 10;
break;
case NI_GPCT_SOURCE_ENCODER_B:
shift = 5;
break;
case NI_GPCT_SOURCE_ENCODER_Z:
shift = 0;
break;
default:
return -EINVAL;
break;
}
mask = 0x1f << shift;
if (source > 0x1f) {
/* Disable gate */
source = 0x1f;
}
counter_dev->regs[abz_reg] &= ~mask;
counter_dev->regs[abz_reg] |= (source << shift) & mask;
write_register(counter, counter_dev->regs[abz_reg], abz_reg);
return 0;
}
return -EINVAL;
}
static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned
ni_660x_gate_select)
{
unsigned i;
switch (ni_660x_gate_select) {
case NI_660x_Source_Pin_i_Gate_Select:
return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
break;
case NI_660x_Gate_Pin_i_Gate_Select:
return NI_GPCT_GATE_PIN_i_GATE_SELECT;
break;
case NI_660x_Next_SRC_Gate_Select:
return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
break;
case NI_660x_Next_Out_Gate_Select:
return NI_GPCT_NEXT_OUT_GATE_SELECT;
break;
case NI_660x_Logic_Low_Gate_Select:
return NI_GPCT_LOGIC_LOW_GATE_SELECT;
break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
return NI_GPCT_RTSI_GATE_SELECT(i);
break;
}
}
if (i <= ni_660x_max_rtsi_channel)
break;
for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
if (ni_660x_gate_select ==
NI_660x_Gate_Pin_Gate_Select(i)) {
return NI_GPCT_GATE_PIN_GATE_SELECT(i);
break;
}
}
if (i <= ni_660x_max_gate_pin)
break;
BUG();
break;
}
return 0;
};
static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned
ni_m_series_gate_select)
{
unsigned i;
switch (ni_m_series_gate_select) {
case NI_M_Series_Timestamp_Mux_Gate_Select:
return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
break;
case NI_M_Series_AI_START2_Gate_Select:
return NI_GPCT_AI_START2_GATE_SELECT;
break;
case NI_M_Series_PXI_Star_Trigger_Gate_Select:
return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
break;
case NI_M_Series_Next_Out_Gate_Select:
return NI_GPCT_NEXT_OUT_GATE_SELECT;
break;
case NI_M_Series_AI_START1_Gate_Select:
return NI_GPCT_AI_START1_GATE_SELECT;
break;
case NI_M_Series_Next_SRC_Gate_Select:
return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
break;
case NI_M_Series_Analog_Trigger_Out_Gate_Select:
return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
break;
case NI_M_Series_Logic_Low_Gate_Select:
return NI_GPCT_LOGIC_LOW_GATE_SELECT;
break;
default:
for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
if (ni_m_series_gate_select ==
NI_M_Series_RTSI_Gate_Select(i)) {
return NI_GPCT_RTSI_GATE_SELECT(i);
break;
}
}
if (i <= ni_m_series_max_rtsi_channel)
break;
for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
if (ni_m_series_gate_select ==
NI_M_Series_PFI_Gate_Select(i)) {
return NI_GPCT_PFI_GATE_SELECT(i);
break;
}
}
if (i <= ni_m_series_max_pfi_channel)
break;
BUG();
break;
}
return 0;
};
static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned
ni_660x_gate_select)
{
unsigned i;
switch (ni_660x_gate_select) {
case NI_660x_Source_Pin_i_Second_Gate_Select:
return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
break;
case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
break;
case NI_660x_Next_SRC_Second_Gate_Select:
return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
break;
case NI_660x_Next_Out_Second_Gate_Select:
return NI_GPCT_NEXT_OUT_GATE_SELECT;
break;
case NI_660x_Selected_Gate_Second_Gate_Select:
return NI_GPCT_SELECTED_GATE_GATE_SELECT;
break;
case NI_660x_Logic_Low_Second_Gate_Select:
return NI_GPCT_LOGIC_LOW_GATE_SELECT;
break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (ni_660x_gate_select ==
NI_660x_RTSI_Second_Gate_Select(i)) {
return NI_GPCT_RTSI_GATE_SELECT(i);
break;
}
}
if (i <= ni_660x_max_rtsi_channel)
break;
for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
if (ni_660x_gate_select ==
NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
break;
}
}
if (i <= ni_660x_max_up_down_pin)
break;
BUG();
break;
}
return 0;
};
static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned
ni_m_series_gate_select)
{
/*FIXME: the second gate sources for the m series are undocumented, so we just return
* the raw bits for now. */
switch (ni_m_series_gate_select) {
default:
return ni_m_series_gate_select;
break;
}
return 0;
};
static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
unsigned int *gate_source)
{
struct ni_gpct_device *counter_dev = counter->counter_dev;
unsigned cidx = counter->counter_index;
const unsigned mode_bits =
ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
unsigned gate_select_bits;
switch (gate_index) {
case 0:
if ((mode_bits & Gi_Gating_Mode_Mask) ==
Gi_Gating_Disabled_Bits) {
*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
return 0;
} else {
gate_select_bits =
(ni_tio_get_soft_copy(counter,
NITIO_INPUT_SEL_REG(cidx)) &
Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
}
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
*gate_source =
ni_m_series_first_gate_to_generic_gate_source
(gate_select_bits);
break;
case ni_gpct_variant_660x:
*gate_source =
ni_660x_first_gate_to_generic_gate_source
(gate_select_bits);
break;
default:
BUG();
break;
}
if (mode_bits & Gi_Gate_Polarity_Bit)
*gate_source |= CR_INVERT;
if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
*gate_source |= CR_EDGE;
break;
case 1:
if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
|| (counter_dev->regs[second_gate_reg] &
Gi_Second_Gate_Mode_Bit)
== 0) {
*gate_source = NI_GPCT_DISABLED_GATE_SELECT;
return 0;
} else {
gate_select_bits =
(counter_dev->regs[second_gate_reg] &
Gi_Second_Gate_Select_Mask) >>
Gi_Second_Gate_Select_Shift;
}
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
*gate_source =
ni_m_series_second_gate_to_generic_gate_source
(gate_select_bits);
break;
case ni_gpct_variant_660x:
*gate_source =
ni_660x_second_gate_to_generic_gate_source
(gate_select_bits);
break;
default:
BUG();
break;
}
if (counter_dev->regs[second_gate_reg] &
Gi_Second_Gate_Polarity_Bit) {
*gate_source |= CR_INVERT;
}
/* second gate can't have edge/level mode set independently */
if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
*gate_source |= CR_EDGE;
break;
default:
return -EINVAL;
break;
}
return 0;
}
int ni_tio_insn_config(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
struct ni_gpct *counter = s->private;
switch (data[0]) {
case INSN_CONFIG_SET_COUNTER_MODE:
return ni_tio_set_counter_mode(counter, data[1]);
break;
case INSN_CONFIG_ARM:
return ni_tio_arm(counter, 1, data[1]);
break;
case INSN_CONFIG_DISARM:
ni_tio_arm(counter, 0, 0);
return 0;
break;
case INSN_CONFIG_GET_COUNTER_STATUS:
data[1] = ni_tio_counter_status(counter);
data[2] = counter_status_mask;
return 0;
break;
case INSN_CONFIG_SET_CLOCK_SRC:
return ni_tio_set_clock_src(counter, data[1], data[2]);
break;
case INSN_CONFIG_GET_CLOCK_SRC:
ni_tio_get_clock_src(counter, &data[1], &data[2]);
return 0;
break;
case INSN_CONFIG_SET_GATE_SRC:
return ni_tio_set_gate_src(counter, data[1], data[2]);
break;
case INSN_CONFIG_GET_GATE_SRC:
return ni_tio_get_gate_src(counter, data[1], &data[2]);
break;
case INSN_CONFIG_SET_OTHER_SRC:
return ni_tio_set_other_src(counter, data[1], data[2]);
break;
case INSN_CONFIG_RESET:
ni_tio_reset_count_and_disarm(counter);
return 0;
break;
default:
break;
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(ni_tio_insn_config);
int ni_tio_insn_read(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
struct ni_gpct *counter = s->private;
struct ni_gpct_device *counter_dev = counter->counter_dev;
const unsigned channel = CR_CHAN(insn->chanspec);
unsigned cidx = counter->counter_index;
unsigned first_read;
unsigned second_read;
unsigned correct_read;
if (insn->n < 1)
return 0;
switch (channel) {
case 0:
ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
Gi_Save_Trace_Bit, 0);
ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
/* The count doesn't get latched until the next clock edge, so it is possible the count
may change (once) while we are reading. Since the read of the SW_Save_Reg isn't
atomic (apparently even when it's a 32 bit register according to 660x docs),
we need to read twice and make sure the reading hasn't changed. If it has,
a third read will be correct since the count value will definitely have latched by then. */
first_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
second_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
if (first_read != second_read)
correct_read =
read_register(counter, NITIO_SW_SAVE_REG(cidx));
else
correct_read = first_read;
data[0] = correct_read;
return 0;
break;
case 1:
data[0] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
break;
case 2:
data[0] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_insn_read);
static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
{
unsigned cidx = counter->counter_index;
const unsigned bits =
read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
if (bits & Gi_Next_Load_Source_Bit(cidx))
return NITIO_LOADB_REG(cidx);
else
return NITIO_LOADA_REG(cidx);
}
int ni_tio_insn_write(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
struct ni_gpct *counter = s->private;
struct ni_gpct_device *counter_dev = counter->counter_dev;
const unsigned channel = CR_CHAN(insn->chanspec);
unsigned cidx = counter->counter_index;
unsigned load_reg;
if (insn->n < 1)
return 0;
switch (channel) {
case 0:
/* Unsafe if counter is armed. Should probably check status and return -EBUSY if armed. */
/* Don't disturb load source select, just use whichever load register is already selected. */
load_reg = ni_tio_next_load_register(counter);
write_register(counter, data[0], load_reg);
ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
0, 0, Gi_Load_Bit);
/* restore state of load reg to whatever the user set last set it to */
write_register(counter, counter_dev->regs[load_reg], load_reg);
break;
case 1:
counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
write_register(counter, data[0], NITIO_LOADA_REG(cidx));
break;
case 2:
counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
write_register(counter, data[0], NITIO_LOADB_REG(cidx));
break;
default:
return -EINVAL;
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_insn_write);
static int __init ni_tio_init_module(void)
{
return 0;
}
module_init(ni_tio_init_module);
static void __exit ni_tio_cleanup_module(void)
{
}
module_exit(ni_tio_cleanup_module);
MODULE_AUTHOR("Comedi <comedi@comedi.org>");
MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
MODULE_LICENSE("GPL");
| gpl-2.0 |
rcrobles/sxf-linux-4.3.5 | arch/sparc/kernel/iommu.c | 611 | 19362 | /* iommu.c: Generic sparc64 IOMMU support.
*
* Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
*/
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/iommu-helper.h>
#include <linux/bitmap.h>
#include <linux/iommu-common.h>
#ifdef CONFIG_PCI
#include <linux/pci.h>
#endif
#include <asm/iommu.h>
#include "iommu_common.h"
#include "kernel.h"
#define STC_CTXMATCH_ADDR(STC, CTX) \
((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
#define STC_FLUSHFLAG_INIT(STC) \
(*((STC)->strbuf_flushflag) = 0UL)
#define STC_FLUSHFLAG_SET(STC) \
(*((STC)->strbuf_flushflag) != 0UL)
#define iommu_read(__reg) \
({ u64 __ret; \
__asm__ __volatile__("ldxa [%1] %2, %0" \
: "=r" (__ret) \
: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
: "memory"); \
__ret; \
})
#define iommu_write(__reg, __val) \
__asm__ __volatile__("stxa %0, [%1] %2" \
: /* no outputs */ \
: "r" (__val), "r" (__reg), \
"i" (ASI_PHYS_BYPASS_EC_E))
/* Must be invoked under the IOMMU lock. */
static void iommu_flushall(struct iommu_map_table *iommu_map_table)
{
struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl);
if (iommu->iommu_flushinv) {
iommu_write(iommu->iommu_flushinv, ~(u64)0);
} else {
unsigned long tag;
int entry;
tag = iommu->iommu_tags;
for (entry = 0; entry < 16; entry++) {
iommu_write(tag, 0);
tag += 8;
}
/* Ensure completion of previous PIO writes. */
(void) iommu_read(iommu->write_complete_reg);
}
}
#define IOPTE_CONSISTENT(CTX) \
(IOPTE_VALID | IOPTE_CACHE | \
(((CTX) << 47) & IOPTE_CONTEXT))
#define IOPTE_STREAMING(CTX) \
(IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
/* Existing mappings are never marked invalid, instead they
* are pointed to a dummy page.
*/
#define IOPTE_IS_DUMMY(iommu, iopte) \
((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
{
unsigned long val = iopte_val(*iopte);
val &= ~IOPTE_PAGE;
val |= iommu->dummy_page_pa;
iopte_val(*iopte) = val;
}
int iommu_table_init(struct iommu *iommu, int tsbsize,
u32 dma_offset, u32 dma_addr_mask,
int numa_node)
{
unsigned long i, order, sz, num_tsb_entries;
struct page *page;
num_tsb_entries = tsbsize / sizeof(iopte_t);
/* Setup initial software IOMMU state. */
spin_lock_init(&iommu->lock);
iommu->ctx_lowest_free = 1;
iommu->tbl.table_map_base = dma_offset;
iommu->dma_addr_mask = dma_addr_mask;
/* Allocate and initialize the free area map. */
sz = num_tsb_entries / 8;
sz = (sz + 7UL) & ~7UL;
iommu->tbl.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
if (!iommu->tbl.map)
return -ENOMEM;
memset(iommu->tbl.map, 0, sz);
iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
(tlb_type != hypervisor ? iommu_flushall : NULL),
false, 1, false);
/* Allocate and initialize the dummy page which we
* set inactive IO PTEs to point to.
*/
page = alloc_pages_node(numa_node, GFP_KERNEL, 0);
if (!page) {
printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
goto out_free_map;
}
iommu->dummy_page = (unsigned long) page_address(page);
memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
/* Now allocate and setup the IOMMU page table itself. */
order = get_order(tsbsize);
page = alloc_pages_node(numa_node, GFP_KERNEL, order);
if (!page) {
printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
goto out_free_dummy_page;
}
iommu->page_table = (iopte_t *)page_address(page);
for (i = 0; i < num_tsb_entries; i++)
iopte_make_dummy(iommu, &iommu->page_table[i]);
return 0;
out_free_dummy_page:
free_page(iommu->dummy_page);
iommu->dummy_page = 0UL;
out_free_map:
kfree(iommu->tbl.map);
iommu->tbl.map = NULL;
return -ENOMEM;
}
static inline iopte_t *alloc_npages(struct device *dev,
struct iommu *iommu,
unsigned long npages)
{
unsigned long entry;
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
(unsigned long)(-1), 0);
if (unlikely(entry == DMA_ERROR_CODE))
return NULL;
return iommu->page_table + entry;
}
static int iommu_alloc_ctx(struct iommu *iommu)
{
int lowest = iommu->ctx_lowest_free;
int n = find_next_zero_bit(iommu->ctx_bitmap, IOMMU_NUM_CTXS, lowest);
if (unlikely(n == IOMMU_NUM_CTXS)) {
n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
if (unlikely(n == lowest)) {
printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
n = 0;
}
}
if (n)
__set_bit(n, iommu->ctx_bitmap);
return n;
}
static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
{
if (likely(ctx)) {
__clear_bit(ctx, iommu->ctx_bitmap);
if (ctx < iommu->ctx_lowest_free)
iommu->ctx_lowest_free = ctx;
}
}
static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_addrp, gfp_t gfp,
struct dma_attrs *attrs)
{
unsigned long order, first_page;
struct iommu *iommu;
struct page *page;
int npages, nid;
iopte_t *iopte;
void *ret;
size = IO_PAGE_ALIGN(size);
order = get_order(size);
if (order >= 10)
return NULL;
nid = dev->archdata.numa_node;
page = alloc_pages_node(nid, gfp, order);
if (unlikely(!page))
return NULL;
first_page = (unsigned long) page_address(page);
memset((char *)first_page, 0, PAGE_SIZE << order);
iommu = dev->archdata.iommu;
iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
if (unlikely(iopte == NULL)) {
free_pages(first_page, order);
return NULL;
}
*dma_addrp = (iommu->tbl.table_map_base +
((iopte - iommu->page_table) << IO_PAGE_SHIFT));
ret = (void *) first_page;
npages = size >> IO_PAGE_SHIFT;
first_page = __pa(first_page);
while (npages--) {
iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
IOPTE_WRITE |
(first_page & IOPTE_PAGE));
iopte++;
first_page += IO_PAGE_SIZE;
}
return ret;
}
static void dma_4u_free_coherent(struct device *dev, size_t size,
void *cpu, dma_addr_t dvma,
struct dma_attrs *attrs)
{
struct iommu *iommu;
unsigned long order, npages;
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
iommu = dev->archdata.iommu;
iommu_tbl_range_free(&iommu->tbl, dvma, npages, DMA_ERROR_CODE);
order = get_order(size);
if (order < 10)
free_pages((unsigned long)cpu, order);
}
static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t sz,
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
struct iommu *iommu;
struct strbuf *strbuf;
iopte_t *base;
unsigned long flags, npages, oaddr;
unsigned long i, base_paddr, ctx;
u32 bus_addr, ret;
unsigned long iopte_protection;
iommu = dev->archdata.iommu;
strbuf = dev->archdata.stc;
if (unlikely(direction == DMA_NONE))
goto bad_no_ctx;
oaddr = (unsigned long)(page_address(page) + offset);
npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
npages >>= IO_PAGE_SHIFT;
base = alloc_npages(dev, iommu, npages);
spin_lock_irqsave(&iommu->lock, flags);
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
spin_unlock_irqrestore(&iommu->lock, flags);
if (unlikely(!base))
goto bad;
bus_addr = (iommu->tbl.table_map_base +
((base - iommu->page_table) << IO_PAGE_SHIFT));
ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
base_paddr = __pa(oaddr & IO_PAGE_MASK);
if (strbuf->strbuf_enabled)
iopte_protection = IOPTE_STREAMING(ctx);
else
iopte_protection = IOPTE_CONSISTENT(ctx);
if (direction != DMA_TO_DEVICE)
iopte_protection |= IOPTE_WRITE;
for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
iopte_val(*base) = iopte_protection | base_paddr;
return ret;
bad:
iommu_free_ctx(iommu, ctx);
bad_no_ctx:
if (printk_ratelimit())
WARN_ON(1);
return DMA_ERROR_CODE;
}
static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
u32 vaddr, unsigned long ctx, unsigned long npages,
enum dma_data_direction direction)
{
int limit;
if (strbuf->strbuf_ctxflush &&
iommu->iommu_ctxflush) {
unsigned long matchreg, flushreg;
u64 val;
flushreg = strbuf->strbuf_ctxflush;
matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
iommu_write(flushreg, ctx);
val = iommu_read(matchreg);
val &= 0xffff;
if (!val)
goto do_flush_sync;
while (val) {
if (val & 0x1)
iommu_write(flushreg, ctx);
val >>= 1;
}
val = iommu_read(matchreg);
if (unlikely(val)) {
printk(KERN_WARNING "strbuf_flush: ctx flush "
"timeout matchreg[%llx] ctx[%lx]\n",
val, ctx);
goto do_page_flush;
}
} else {
unsigned long i;
do_page_flush:
for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
iommu_write(strbuf->strbuf_pflush, vaddr);
}
do_flush_sync:
/* If the device could not have possibly put dirty data into
* the streaming cache, no flush-flag synchronization needs
* to be performed.
*/
if (direction == DMA_TO_DEVICE)
return;
STC_FLUSHFLAG_INIT(strbuf);
iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
(void) iommu_read(iommu->write_complete_reg);
limit = 100000;
while (!STC_FLUSHFLAG_SET(strbuf)) {
limit--;
if (!limit)
break;
udelay(1);
rmb();
}
if (!limit)
printk(KERN_WARNING "strbuf_flush: flushflag timeout "
"vaddr[%08x] ctx[%lx] npages[%ld]\n",
vaddr, ctx, npages);
}
static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
size_t sz, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
struct iommu *iommu;
struct strbuf *strbuf;
iopte_t *base;
unsigned long flags, npages, ctx, i;
if (unlikely(direction == DMA_NONE)) {
if (printk_ratelimit())
WARN_ON(1);
return;
}
iommu = dev->archdata.iommu;
strbuf = dev->archdata.stc;
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
npages >>= IO_PAGE_SHIFT;
base = iommu->page_table +
((bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);
bus_addr &= IO_PAGE_MASK;
spin_lock_irqsave(&iommu->lock, flags);
/* Record the context, if any. */
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
/* Step 1: Kick data out of streaming buffers if necessary. */
if (strbuf->strbuf_enabled)
strbuf_flush(strbuf, iommu, bus_addr, ctx,
npages, direction);
/* Step 2: Clear out TSB entries. */
for (i = 0; i < npages; i++)
iopte_make_dummy(iommu, base + i);
iommu_free_ctx(iommu, ctx);
spin_unlock_irqrestore(&iommu->lock, flags);
iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, DMA_ERROR_CODE);
}
static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
int nelems, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
struct scatterlist *s, *outs, *segstart;
unsigned long flags, handle, prot, ctx;
dma_addr_t dma_next = 0, dma_addr;
unsigned int max_seg_size;
unsigned long seg_boundary_size;
int outcount, incount, i;
struct strbuf *strbuf;
struct iommu *iommu;
unsigned long base_shift;
BUG_ON(direction == DMA_NONE);
iommu = dev->archdata.iommu;
strbuf = dev->archdata.stc;
if (nelems == 0 || !iommu)
return 0;
spin_lock_irqsave(&iommu->lock, flags);
ctx = 0;
if (iommu->iommu_ctxflush)
ctx = iommu_alloc_ctx(iommu);
if (strbuf->strbuf_enabled)
prot = IOPTE_STREAMING(ctx);
else
prot = IOPTE_CONSISTENT(ctx);
if (direction != DMA_TO_DEVICE)
prot |= IOPTE_WRITE;
outs = s = segstart = &sglist[0];
outcount = 1;
incount = nelems;
handle = 0;
/* Init first segment length for backout at failure */
outs->dma_length = 0;
max_seg_size = dma_get_max_seg_size(dev);
seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT;
for_each_sg(sglist, s, nelems, i) {
unsigned long paddr, npages, entry, out_entry = 0, slen;
iopte_t *base;
slen = s->length;
/* Sanity check */
if (slen == 0) {
dma_next = 0;
continue;
}
/* Allocate iommu entries for that segment */
paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages,
&handle, (unsigned long)(-1), 0);
/* Handle failure */
if (unlikely(entry == DMA_ERROR_CODE)) {
if (printk_ratelimit())
printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
" npages %lx\n", iommu, paddr, npages);
goto iommu_map_failed;
}
base = iommu->page_table + entry;
/* Convert entry to a dma_addr_t */
dma_addr = iommu->tbl.table_map_base +
(entry << IO_PAGE_SHIFT);
dma_addr |= (s->offset & ~IO_PAGE_MASK);
/* Insert into HW table */
paddr &= IO_PAGE_MASK;
while (npages--) {
iopte_val(*base) = prot | paddr;
base++;
paddr += IO_PAGE_SIZE;
}
/* If we are in an open segment, try merging */
if (segstart != s) {
/* We cannot merge if:
* - allocated dma_addr isn't contiguous to previous allocation
*/
if ((dma_addr != dma_next) ||
(outs->dma_length + s->length > max_seg_size) ||
(is_span_boundary(out_entry, base_shift,
seg_boundary_size, outs, s))) {
/* Can't merge: create a new segment */
segstart = s;
outcount++;
outs = sg_next(outs);
} else {
outs->dma_length += s->length;
}
}
if (segstart == s) {
/* This is a new segment, fill entries */
outs->dma_address = dma_addr;
outs->dma_length = slen;
out_entry = entry;
}
/* Calculate next page pointer for contiguous check */
dma_next = dma_addr + slen;
}
spin_unlock_irqrestore(&iommu->lock, flags);
if (outcount < incount) {
outs = sg_next(outs);
outs->dma_address = DMA_ERROR_CODE;
outs->dma_length = 0;
}
return outcount;
iommu_map_failed:
for_each_sg(sglist, s, nelems, i) {
if (s->dma_length != 0) {
unsigned long vaddr, npages, entry, j;
iopte_t *base;
vaddr = s->dma_address & IO_PAGE_MASK;
npages = iommu_num_pages(s->dma_address, s->dma_length,
IO_PAGE_SIZE);
entry = (vaddr - iommu->tbl.table_map_base)
>> IO_PAGE_SHIFT;
base = iommu->page_table + entry;
for (j = 0; j < npages; j++)
iopte_make_dummy(iommu, base + j);
iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
DMA_ERROR_CODE);
s->dma_address = DMA_ERROR_CODE;
s->dma_length = 0;
}
if (s == outs)
break;
}
spin_unlock_irqrestore(&iommu->lock, flags);
return 0;
}
/* If contexts are being used, they are the same in all of the mappings
* we make for a particular SG.
*/
static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
{
unsigned long ctx = 0;
if (iommu->iommu_ctxflush) {
iopte_t *base;
u32 bus_addr;
struct iommu_map_table *tbl = &iommu->tbl;
bus_addr = sg->dma_address & IO_PAGE_MASK;
base = iommu->page_table +
((bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT);
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
}
return ctx;
}
static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
int nelems, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
unsigned long flags, ctx;
struct scatterlist *sg;
struct strbuf *strbuf;
struct iommu *iommu;
BUG_ON(direction == DMA_NONE);
iommu = dev->archdata.iommu;
strbuf = dev->archdata.stc;
ctx = fetch_sg_ctx(iommu, sglist);
spin_lock_irqsave(&iommu->lock, flags);
sg = sglist;
while (nelems--) {
dma_addr_t dma_handle = sg->dma_address;
unsigned int len = sg->dma_length;
unsigned long npages, entry;
iopte_t *base;
int i;
if (!len)
break;
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
entry = ((dma_handle - iommu->tbl.table_map_base)
>> IO_PAGE_SHIFT);
base = iommu->page_table + entry;
dma_handle &= IO_PAGE_MASK;
if (strbuf->strbuf_enabled)
strbuf_flush(strbuf, iommu, dma_handle, ctx,
npages, direction);
for (i = 0; i < npages; i++)
iopte_make_dummy(iommu, base + i);
iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
DMA_ERROR_CODE);
sg = sg_next(sg);
}
iommu_free_ctx(iommu, ctx);
spin_unlock_irqrestore(&iommu->lock, flags);
}
static void dma_4u_sync_single_for_cpu(struct device *dev,
dma_addr_t bus_addr, size_t sz,
enum dma_data_direction direction)
{
struct iommu *iommu;
struct strbuf *strbuf;
unsigned long flags, ctx, npages;
iommu = dev->archdata.iommu;
strbuf = dev->archdata.stc;
if (!strbuf->strbuf_enabled)
return;
spin_lock_irqsave(&iommu->lock, flags);
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
npages >>= IO_PAGE_SHIFT;
bus_addr &= IO_PAGE_MASK;
/* Step 1: Record the context, if any. */
ctx = 0;
if (iommu->iommu_ctxflush &&
strbuf->strbuf_ctxflush) {
iopte_t *iopte;
struct iommu_map_table *tbl = &iommu->tbl;
iopte = iommu->page_table +
((bus_addr - tbl->table_map_base)>>IO_PAGE_SHIFT);
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
}
/* Step 2: Kick data out of streaming buffers. */
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
spin_unlock_irqrestore(&iommu->lock, flags);
}
static void dma_4u_sync_sg_for_cpu(struct device *dev,
struct scatterlist *sglist, int nelems,
enum dma_data_direction direction)
{
struct iommu *iommu;
struct strbuf *strbuf;
unsigned long flags, ctx, npages, i;
struct scatterlist *sg, *sgprv;
u32 bus_addr;
iommu = dev->archdata.iommu;
strbuf = dev->archdata.stc;
if (!strbuf->strbuf_enabled)
return;
spin_lock_irqsave(&iommu->lock, flags);
/* Step 1: Record the context, if any. */
ctx = 0;
if (iommu->iommu_ctxflush &&
strbuf->strbuf_ctxflush) {
iopte_t *iopte;
struct iommu_map_table *tbl = &iommu->tbl;
iopte = iommu->page_table + ((sglist[0].dma_address -
tbl->table_map_base) >> IO_PAGE_SHIFT);
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
}
/* Step 2: Kick data out of streaming buffers. */
bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
sgprv = NULL;
for_each_sg(sglist, sg, nelems, i) {
if (sg->dma_length == 0)
break;
sgprv = sg;
}
npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
- bus_addr) >> IO_PAGE_SHIFT;
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
spin_unlock_irqrestore(&iommu->lock, flags);
}
static struct dma_map_ops sun4u_dma_ops = {
.alloc = dma_4u_alloc_coherent,
.free = dma_4u_free_coherent,
.map_page = dma_4u_map_page,
.unmap_page = dma_4u_unmap_page,
.map_sg = dma_4u_map_sg,
.unmap_sg = dma_4u_unmap_sg,
.sync_single_for_cpu = dma_4u_sync_single_for_cpu,
.sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
};
struct dma_map_ops *dma_ops = &sun4u_dma_ops;
EXPORT_SYMBOL(dma_ops);
int dma_supported(struct device *dev, u64 device_mask)
{
struct iommu *iommu = dev->archdata.iommu;
u64 dma_addr_mask = iommu->dma_addr_mask;
if (device_mask >= (1UL << 32UL))
return 0;
if ((device_mask & dma_addr_mask) == dma_addr_mask)
return 1;
#ifdef CONFIG_PCI
if (dev_is_pci(dev))
return pci64_dma_supported(to_pci_dev(dev), device_mask);
#endif
return 0;
}
EXPORT_SYMBOL(dma_supported);
| gpl-2.0 |
EloYGomeZ/caf-j1-exp | sound/soc/msm/mvs-dai.c | 867 | 3655 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* See the GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find it at http://www.fsf.org.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "msm_audio_mvs.h"
static struct snd_soc_dai_driver msm_mvs_codec_dais[] = {
{
.name = "mvs-codec-dai",
.playback = {
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_8000),
.rate_min = 8000,
.rate_max = 8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_8000),
.rate_min = 8000,
.rate_max = 8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
};
static struct snd_soc_dai_driver msm_mvs_cpu_dais[] = {
{
.name = "mvs-cpu-dai",
.playback = {
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_8000),
.rate_min = 8000,
.rate_max = 8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_8000),
.rate_min = 8000,
.rate_max = 8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
};
static struct snd_soc_codec_driver soc_codec_dev_msm = {
.compress_type = SND_SOC_FLAT_COMPRESSION,
};
static __devinit int asoc_mvs_codec_probe(struct platform_device *pdev)
{
dev_info(&pdev->dev, "%s: dev name %s\n", __func__, dev_name(&pdev->dev));
return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_msm,
msm_mvs_codec_dais, ARRAY_SIZE(msm_mvs_codec_dais));
}
static int __devexit asoc_mvs_codec_remove(struct platform_device *pdev)
{
snd_soc_unregister_dai(&pdev->dev);
return 0;
}
static __devinit int asoc_mvs_cpu_probe(struct platform_device *pdev)
{
dev_info(&pdev->dev, "%s: dev name %s\n", __func__, dev_name(&pdev->dev));
return snd_soc_register_dai(&pdev->dev, msm_mvs_cpu_dais);
}
static int __devexit asoc_mvs_cpu_remove(struct platform_device *pdev)
{
snd_soc_unregister_dai(&pdev->dev);
return 0;
}
static struct platform_driver asoc_mvs_codec_driver = {
.probe = asoc_mvs_codec_probe,
.remove = __devexit_p(asoc_mvs_codec_remove),
.driver = {
.name = "mvs-codec-dai",
.owner = THIS_MODULE,
},
};
static struct platform_driver asoc_mvs_cpu_driver = {
.probe = asoc_mvs_cpu_probe,
.remove = __devexit_p(asoc_mvs_cpu_remove),
.driver = {
.name = "mvs-cpu-dai",
.owner = THIS_MODULE,
},
};
static int __init mvs_codec_dai_init(void)
{
return platform_driver_register(&asoc_mvs_codec_driver);
}
static void __exit mvs_codec_dai_exit(void)
{
platform_driver_unregister(&asoc_mvs_codec_driver);
}
static int __init mvs_cpu_dai_init(void)
{
return platform_driver_register(&asoc_mvs_cpu_driver);
}
static void __exit mvs_cpu_dai_exit(void)
{
platform_driver_unregister(&asoc_mvs_cpu_driver);
}
module_init(mvs_codec_dai_init);
module_exit(mvs_codec_dai_exit);
module_init(mvs_cpu_dai_init);
module_exit(mvs_cpu_dai_exit);
/* Module information */
MODULE_DESCRIPTION("MSM Codec/Cpu Dai driver");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
ZhizhouTian/kernel-stable | drivers/net/wireless/iwlwifi/dvm/power.c | 1379 | 12902 | /******************************************************************************
*
* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project, as well
* as portions of the ieee80211 subsystem header files.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* Intel Linux Wireless <ilw@linux.intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <net/mac80211.h>
#include "iwl-io.h"
#include "iwl-debug.h"
#include "iwl-trans.h"
#include "iwl-modparams.h"
#include "dev.h"
#include "agn.h"
#include "commands.h"
#include "power.h"
static bool force_cam = true;
module_param(force_cam, bool, 0644);
MODULE_PARM_DESC(force_cam, "force continuously aware mode (no power saving at all)");
/*
* Setting power level allows the card to go to sleep when not busy.
*
* We calculate a sleep command based on the required latency, which
* we get from mac80211. In order to handle thermal throttling, we can
* also use pre-defined power levels.
*/
/*
* This defines the old power levels. They are still used by default
* (level 1) and for thermal throttle (levels 3 through 5)
*/
struct iwl_power_vec_entry {
struct iwl_powertable_cmd cmd;
u8 no_dtim; /* number of skip dtim */
};
#define IWL_DTIM_RANGE_0_MAX 2
#define IWL_DTIM_RANGE_1_MAX 10
#define NOSLP cpu_to_le16(0), 0, 0
#define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK | \
IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
IWL_POWER_ADVANCE_PM_ENA_MSK)
#define ASLP_TOUT(T) cpu_to_le32(T)
#define TU_TO_USEC 1024
#define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
cpu_to_le32(X1), \
cpu_to_le32(X2), \
cpu_to_le32(X3), \
cpu_to_le32(X4)}
/* default power management (not Tx power) table values */
/* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
};
/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
};
/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
{{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
{{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
{{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
{{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
{{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
};
/* advance power management */
/* DTIM 0 - 2 */
static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};
/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
/* DTIM 3 - 10 */
static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
};
/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
/* DTIM 11 - */
static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
{{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
};
static void iwl_static_sleep_cmd(struct iwl_priv *priv,
struct iwl_powertable_cmd *cmd,
enum iwl_power_level lvl, int period)
{
const struct iwl_power_vec_entry *table;
int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
int i;
u8 skip;
u32 slp_itrvl;
if (priv->lib->adv_pm) {
table = apm_range_2;
if (period <= IWL_DTIM_RANGE_1_MAX)
table = apm_range_1;
if (period <= IWL_DTIM_RANGE_0_MAX)
table = apm_range_0;
} else {
table = range_2;
if (period <= IWL_DTIM_RANGE_1_MAX)
table = range_1;
if (period <= IWL_DTIM_RANGE_0_MAX)
table = range_0;
}
if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM))
memset(cmd, 0, sizeof(*cmd));
else
*cmd = table[lvl].cmd;
if (period == 0) {
skip = 0;
period = 1;
for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
max_sleep[i] = 1;
} else {
skip = table[lvl].no_dtim;
for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
}
slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
/* figure out the listen interval based on dtim period and skip */
if (slp_itrvl == 0xFF)
cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
cpu_to_le32(period * (skip + 1));
slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
if (slp_itrvl > period)
cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
cpu_to_le32((slp_itrvl / period) * period);
if (skip)
cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
else
cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
if (priv->cfg->base_params->shadow_reg_enable)
cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
else
cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
if (iwl_advanced_bt_coexist(priv)) {
if (!priv->lib->bt_params->bt_sco_disable)
cmd->flags |= IWL_POWER_BT_SCO_ENA;
else
cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
}
slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
/* enforce max sleep interval */
for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
if (le32_to_cpu(cmd->sleep_interval[i]) >
(max_sleep[i] * period))
cmd->sleep_interval[i] =
cpu_to_le32(max_sleep[i] * period);
if (i != (IWL_POWER_VEC_SIZE - 1)) {
if (le32_to_cpu(cmd->sleep_interval[i]) >
le32_to_cpu(cmd->sleep_interval[i+1]))
cmd->sleep_interval[i] =
cmd->sleep_interval[i+1];
}
}
if (priv->power_data.bus_pm)
cmd->flags |= IWL_POWER_PCI_PM_MSK;
else
cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
skip, period);
/* The power level here is 0-4 (used as array index), but user expects
to see 1-5 (according to spec). */
IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
}
static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
struct iwl_powertable_cmd *cmd)
{
memset(cmd, 0, sizeof(*cmd));
if (priv->power_data.bus_pm)
cmd->flags |= IWL_POWER_PCI_PM_MSK;
IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
}
static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
{
IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
le32_to_cpu(cmd->sleep_interval[0]),
le32_to_cpu(cmd->sleep_interval[1]),
le32_to_cpu(cmd->sleep_interval[2]),
le32_to_cpu(cmd->sleep_interval[3]),
le32_to_cpu(cmd->sleep_interval[4]));
return iwl_dvm_send_cmd_pdu(priv, POWER_TABLE_CMD, 0,
sizeof(struct iwl_powertable_cmd), cmd);
}
static void iwl_power_build_cmd(struct iwl_priv *priv,
struct iwl_powertable_cmd *cmd)
{
bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
int dtimper;
if (force_cam) {
iwl_power_sleep_cam_cmd(priv, cmd);
return;
}
dtimper = priv->hw->conf.ps_dtim_period ?: 1;
if (priv->wowlan)
iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper);
else if (!priv->lib->no_idle_support &&
priv->hw->conf.flags & IEEE80211_CONF_IDLE)
iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
else if (iwl_tt_is_low_power_state(priv)) {
/* in thermal throttling low power state */
iwl_static_sleep_cmd(priv, cmd,
iwl_tt_current_power_mode(priv), dtimper);
} else if (!enabled)
iwl_power_sleep_cam_cmd(priv, cmd);
else if (priv->power_data.debug_sleep_level_override >= 0)
iwl_static_sleep_cmd(priv, cmd,
priv->power_data.debug_sleep_level_override,
dtimper);
else {
/* Note that the user parameter is 1-5 (according to spec),
but we pass 0-4 because it acts as an array index. */
if (iwlwifi_mod_params.power_level > IWL_POWER_INDEX_1 &&
iwlwifi_mod_params.power_level <= IWL_POWER_NUM)
iwl_static_sleep_cmd(priv, cmd,
iwlwifi_mod_params.power_level - 1, dtimper);
else
iwl_static_sleep_cmd(priv, cmd,
IWL_POWER_INDEX_1, dtimper);
}
}
int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
bool force)
{
int ret;
bool update_chains;
lockdep_assert_held(&priv->mutex);
/* Don't update the RX chain when chain noise calibration is running */
update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
return 0;
if (!iwl_is_ready_rf(priv))
return -EIO;
/* scan complete use sleep_power_next, need to be updated */
memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
return 0;
}
if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
iwl_dvm_set_pmi(priv, true);
ret = iwl_set_power(priv, cmd);
if (!ret) {
if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
iwl_dvm_set_pmi(priv, false);
if (update_chains)
iwl_update_chain_flags(priv);
else
IWL_DEBUG_POWER(priv,
"Cannot update the power, chain noise "
"calibration running: %d\n",
priv->chain_noise_data.state);
memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
} else
IWL_ERR(priv, "set power fail, ret = %d\n", ret);
return ret;
}
int iwl_power_update_mode(struct iwl_priv *priv, bool force)
{
struct iwl_powertable_cmd cmd;
iwl_power_build_cmd(priv, &cmd);
return iwl_power_set_mode(priv, &cmd, force);
}
/* initialize to default */
void iwl_power_initialize(struct iwl_priv *priv)
{
priv->power_data.bus_pm = priv->trans->pm_support;
priv->power_data.debug_sleep_level_override = -1;
memset(&priv->power_data.sleep_cmd, 0,
sizeof(priv->power_data.sleep_cmd));
}
| gpl-2.0 |
AndroidOpenDevelopment-Devices/android_kernel_moto_shamu | fs/ext4/migrate.c | 1635 | 16899 | /*
* Copyright IBM Corporation, 2007
* Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2.1 of the GNU Lesser General Public License
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*/
#include <linux/slab.h>
#include "ext4_jbd2.h"
#include "ext4_extents.h"
/*
* The contiguous blocks details which can be
* represented by a single extent
*/
struct migrate_struct {
ext4_lblk_t first_block, last_block, curr_block;
ext4_fsblk_t first_pblock, last_pblock;
};
static int finish_range(handle_t *handle, struct inode *inode,
struct migrate_struct *lb)
{
int retval = 0, needed;
struct ext4_extent newext;
struct ext4_ext_path *path;
if (lb->first_pblock == 0)
return 0;
/* Add the extent to temp inode*/
newext.ee_block = cpu_to_le32(lb->first_block);
newext.ee_len = cpu_to_le16(lb->last_block - lb->first_block + 1);
ext4_ext_store_pblock(&newext, lb->first_pblock);
path = ext4_ext_find_extent(inode, lb->first_block, NULL);
if (IS_ERR(path)) {
retval = PTR_ERR(path);
path = NULL;
goto err_out;
}
/*
* Calculate the credit needed to inserting this extent
* Since we are doing this in loop we may accumalate extra
* credit. But below we try to not accumalate too much
* of them by restarting the journal.
*/
needed = ext4_ext_calc_credits_for_single_extent(inode,
lb->last_block - lb->first_block + 1, path);
/*
* Make sure the credit we accumalated is not really high
*/
if (needed && ext4_handle_has_enough_credits(handle,
EXT4_RESERVE_TRANS_BLOCKS)) {
retval = ext4_journal_restart(handle, needed);
if (retval)
goto err_out;
} else if (needed) {
retval = ext4_journal_extend(handle, needed);
if (retval) {
/*
* IF not able to extend the journal restart the journal
*/
retval = ext4_journal_restart(handle, needed);
if (retval)
goto err_out;
}
}
retval = ext4_ext_insert_extent(handle, inode, path, &newext, 0);
err_out:
if (path) {
ext4_ext_drop_refs(path);
kfree(path);
}
lb->first_pblock = 0;
return retval;
}
static int update_extent_range(handle_t *handle, struct inode *inode,
ext4_fsblk_t pblock, struct migrate_struct *lb)
{
int retval;
/*
* See if we can add on to the existing range (if it exists)
*/
if (lb->first_pblock &&
(lb->last_pblock+1 == pblock) &&
(lb->last_block+1 == lb->curr_block)) {
lb->last_pblock = pblock;
lb->last_block = lb->curr_block;
lb->curr_block++;
return 0;
}
/*
* Start a new range.
*/
retval = finish_range(handle, inode, lb);
lb->first_pblock = lb->last_pblock = pblock;
lb->first_block = lb->last_block = lb->curr_block;
lb->curr_block++;
return retval;
}
static int update_ind_extent_range(handle_t *handle, struct inode *inode,
ext4_fsblk_t pblock,
struct migrate_struct *lb)
{
struct buffer_head *bh;
__le32 *i_data;
int i, retval = 0;
unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
bh = sb_bread(inode->i_sb, pblock);
if (!bh)
return -EIO;
i_data = (__le32 *)bh->b_data;
for (i = 0; i < max_entries; i++) {
if (i_data[i]) {
retval = update_extent_range(handle, inode,
le32_to_cpu(i_data[i]), lb);
if (retval)
break;
} else {
lb->curr_block++;
}
}
put_bh(bh);
return retval;
}
static int update_dind_extent_range(handle_t *handle, struct inode *inode,
ext4_fsblk_t pblock,
struct migrate_struct *lb)
{
struct buffer_head *bh;
__le32 *i_data;
int i, retval = 0;
unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
bh = sb_bread(inode->i_sb, pblock);
if (!bh)
return -EIO;
i_data = (__le32 *)bh->b_data;
for (i = 0; i < max_entries; i++) {
if (i_data[i]) {
retval = update_ind_extent_range(handle, inode,
le32_to_cpu(i_data[i]), lb);
if (retval)
break;
} else {
/* Only update the file block number */
lb->curr_block += max_entries;
}
}
put_bh(bh);
return retval;
}
static int update_tind_extent_range(handle_t *handle, struct inode *inode,
ext4_fsblk_t pblock,
struct migrate_struct *lb)
{
struct buffer_head *bh;
__le32 *i_data;
int i, retval = 0;
unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
bh = sb_bread(inode->i_sb, pblock);
if (!bh)
return -EIO;
i_data = (__le32 *)bh->b_data;
for (i = 0; i < max_entries; i++) {
if (i_data[i]) {
retval = update_dind_extent_range(handle, inode,
le32_to_cpu(i_data[i]), lb);
if (retval)
break;
} else {
/* Only update the file block number */
lb->curr_block += max_entries * max_entries;
}
}
put_bh(bh);
return retval;
}
static int extend_credit_for_blkdel(handle_t *handle, struct inode *inode)
{
int retval = 0, needed;
if (ext4_handle_has_enough_credits(handle, EXT4_RESERVE_TRANS_BLOCKS+1))
return 0;
/*
* We are freeing a blocks. During this we touch
* superblock, group descriptor and block bitmap.
* So allocate a credit of 3. We may update
* quota (user and group).
*/
needed = 3 + EXT4_MAXQUOTAS_TRANS_BLOCKS(inode->i_sb);
if (ext4_journal_extend(handle, needed) != 0)
retval = ext4_journal_restart(handle, needed);
return retval;
}
static int free_dind_blocks(handle_t *handle,
struct inode *inode, __le32 i_data)
{
int i;
__le32 *tmp_idata;
struct buffer_head *bh;
unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
bh = sb_bread(inode->i_sb, le32_to_cpu(i_data));
if (!bh)
return -EIO;
tmp_idata = (__le32 *)bh->b_data;
for (i = 0; i < max_entries; i++) {
if (tmp_idata[i]) {
extend_credit_for_blkdel(handle, inode);
ext4_free_blocks(handle, inode, NULL,
le32_to_cpu(tmp_idata[i]), 1,
EXT4_FREE_BLOCKS_METADATA |
EXT4_FREE_BLOCKS_FORGET);
}
}
put_bh(bh);
extend_credit_for_blkdel(handle, inode);
ext4_free_blocks(handle, inode, NULL, le32_to_cpu(i_data), 1,
EXT4_FREE_BLOCKS_METADATA |
EXT4_FREE_BLOCKS_FORGET);
return 0;
}
static int free_tind_blocks(handle_t *handle,
struct inode *inode, __le32 i_data)
{
int i, retval = 0;
__le32 *tmp_idata;
struct buffer_head *bh;
unsigned long max_entries = inode->i_sb->s_blocksize >> 2;
bh = sb_bread(inode->i_sb, le32_to_cpu(i_data));
if (!bh)
return -EIO;
tmp_idata = (__le32 *)bh->b_data;
for (i = 0; i < max_entries; i++) {
if (tmp_idata[i]) {
retval = free_dind_blocks(handle,
inode, tmp_idata[i]);
if (retval) {
put_bh(bh);
return retval;
}
}
}
put_bh(bh);
extend_credit_for_blkdel(handle, inode);
ext4_free_blocks(handle, inode, NULL, le32_to_cpu(i_data), 1,
EXT4_FREE_BLOCKS_METADATA |
EXT4_FREE_BLOCKS_FORGET);
return 0;
}
static int free_ind_block(handle_t *handle, struct inode *inode, __le32 *i_data)
{
int retval;
/* ei->i_data[EXT4_IND_BLOCK] */
if (i_data[0]) {
extend_credit_for_blkdel(handle, inode);
ext4_free_blocks(handle, inode, NULL,
le32_to_cpu(i_data[0]), 1,
EXT4_FREE_BLOCKS_METADATA |
EXT4_FREE_BLOCKS_FORGET);
}
/* ei->i_data[EXT4_DIND_BLOCK] */
if (i_data[1]) {
retval = free_dind_blocks(handle, inode, i_data[1]);
if (retval)
return retval;
}
/* ei->i_data[EXT4_TIND_BLOCK] */
if (i_data[2]) {
retval = free_tind_blocks(handle, inode, i_data[2]);
if (retval)
return retval;
}
return 0;
}
static int ext4_ext_swap_inode_data(handle_t *handle, struct inode *inode,
struct inode *tmp_inode)
{
int retval;
__le32 i_data[3];
struct ext4_inode_info *ei = EXT4_I(inode);
struct ext4_inode_info *tmp_ei = EXT4_I(tmp_inode);
/*
* One credit accounted for writing the
* i_data field of the original inode
*/
retval = ext4_journal_extend(handle, 1);
if (retval) {
retval = ext4_journal_restart(handle, 1);
if (retval)
goto err_out;
}
i_data[0] = ei->i_data[EXT4_IND_BLOCK];
i_data[1] = ei->i_data[EXT4_DIND_BLOCK];
i_data[2] = ei->i_data[EXT4_TIND_BLOCK];
down_write(&EXT4_I(inode)->i_data_sem);
/*
* if EXT4_STATE_EXT_MIGRATE is cleared a block allocation
* happened after we started the migrate. We need to
* fail the migrate
*/
if (!ext4_test_inode_state(inode, EXT4_STATE_EXT_MIGRATE)) {
retval = -EAGAIN;
up_write(&EXT4_I(inode)->i_data_sem);
goto err_out;
} else
ext4_clear_inode_state(inode, EXT4_STATE_EXT_MIGRATE);
/*
* We have the extent map build with the tmp inode.
* Now copy the i_data across
*/
ext4_set_inode_flag(inode, EXT4_INODE_EXTENTS);
memcpy(ei->i_data, tmp_ei->i_data, sizeof(ei->i_data));
/*
* Update i_blocks with the new blocks that got
* allocated while adding extents for extent index
* blocks.
*
* While converting to extents we need not
* update the orignal inode i_blocks for extent blocks
* via quota APIs. The quota update happened via tmp_inode already.
*/
spin_lock(&inode->i_lock);
inode->i_blocks += tmp_inode->i_blocks;
spin_unlock(&inode->i_lock);
up_write(&EXT4_I(inode)->i_data_sem);
/*
* We mark the inode dirty after, because we decrement the
* i_blocks when freeing the indirect meta-data blocks
*/
retval = free_ind_block(handle, inode, i_data);
ext4_mark_inode_dirty(handle, inode);
err_out:
return retval;
}
static int free_ext_idx(handle_t *handle, struct inode *inode,
struct ext4_extent_idx *ix)
{
int i, retval = 0;
ext4_fsblk_t block;
struct buffer_head *bh;
struct ext4_extent_header *eh;
block = ext4_idx_pblock(ix);
bh = sb_bread(inode->i_sb, block);
if (!bh)
return -EIO;
eh = (struct ext4_extent_header *)bh->b_data;
if (eh->eh_depth != 0) {
ix = EXT_FIRST_INDEX(eh);
for (i = 0; i < le16_to_cpu(eh->eh_entries); i++, ix++) {
retval = free_ext_idx(handle, inode, ix);
if (retval)
break;
}
}
put_bh(bh);
extend_credit_for_blkdel(handle, inode);
ext4_free_blocks(handle, inode, NULL, block, 1,
EXT4_FREE_BLOCKS_METADATA | EXT4_FREE_BLOCKS_FORGET);
return retval;
}
/*
* Free the extent meta data blocks only
*/
static int free_ext_block(handle_t *handle, struct inode *inode)
{
int i, retval = 0;
struct ext4_inode_info *ei = EXT4_I(inode);
struct ext4_extent_header *eh = (struct ext4_extent_header *)ei->i_data;
struct ext4_extent_idx *ix;
if (eh->eh_depth == 0)
/*
* No extra blocks allocated for extent meta data
*/
return 0;
ix = EXT_FIRST_INDEX(eh);
for (i = 0; i < le16_to_cpu(eh->eh_entries); i++, ix++) {
retval = free_ext_idx(handle, inode, ix);
if (retval)
return retval;
}
return retval;
}
int ext4_ext_migrate(struct inode *inode)
{
handle_t *handle;
int retval = 0, i;
__le32 *i_data;
struct ext4_inode_info *ei;
struct inode *tmp_inode = NULL;
struct migrate_struct lb;
unsigned long max_entries;
__u32 goal;
uid_t owner[2];
/*
* If the filesystem does not support extents, or the inode
* already is extent-based, error out.
*/
if (!EXT4_HAS_INCOMPAT_FEATURE(inode->i_sb,
EXT4_FEATURE_INCOMPAT_EXTENTS) ||
(ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)))
return -EINVAL;
if (S_ISLNK(inode->i_mode) && inode->i_blocks == 0)
/*
* don't migrate fast symlink
*/
return retval;
/*
* Worst case we can touch the allocation bitmaps, a bgd
* block, and a block to link in the orphan list. We do need
* need to worry about credits for modifying the quota inode.
*/
handle = ext4_journal_start(inode, EXT4_HT_MIGRATE,
4 + EXT4_MAXQUOTAS_TRANS_BLOCKS(inode->i_sb));
if (IS_ERR(handle)) {
retval = PTR_ERR(handle);
return retval;
}
goal = (((inode->i_ino - 1) / EXT4_INODES_PER_GROUP(inode->i_sb)) *
EXT4_INODES_PER_GROUP(inode->i_sb)) + 1;
owner[0] = i_uid_read(inode);
owner[1] = i_gid_read(inode);
tmp_inode = ext4_new_inode(handle, inode->i_sb->s_root->d_inode,
S_IFREG, NULL, goal, owner);
if (IS_ERR(tmp_inode)) {
retval = PTR_ERR(tmp_inode);
ext4_journal_stop(handle);
return retval;
}
i_size_write(tmp_inode, i_size_read(inode));
/*
* Set the i_nlink to zero so it will be deleted later
* when we drop inode reference.
*/
clear_nlink(tmp_inode);
ext4_ext_tree_init(handle, tmp_inode);
ext4_orphan_add(handle, tmp_inode);
ext4_journal_stop(handle);
/*
* start with one credit accounted for
* superblock modification.
*
* For the tmp_inode we already have committed the
* trascation that created the inode. Later as and
* when we add extents we extent the journal
*/
/*
* Even though we take i_mutex we can still cause block
* allocation via mmap write to holes. If we have allocated
* new blocks we fail migrate. New block allocation will
* clear EXT4_STATE_EXT_MIGRATE flag. The flag is updated
* with i_data_sem held to prevent racing with block
* allocation.
*/
down_read((&EXT4_I(inode)->i_data_sem));
ext4_set_inode_state(inode, EXT4_STATE_EXT_MIGRATE);
up_read((&EXT4_I(inode)->i_data_sem));
handle = ext4_journal_start(inode, EXT4_HT_MIGRATE, 1);
if (IS_ERR(handle)) {
/*
* It is impossible to update on-disk structures without
* a handle, so just rollback in-core changes and live other
* work to orphan_list_cleanup()
*/
ext4_orphan_del(NULL, tmp_inode);
retval = PTR_ERR(handle);
goto out;
}
ei = EXT4_I(inode);
i_data = ei->i_data;
memset(&lb, 0, sizeof(lb));
/* 32 bit block address 4 bytes */
max_entries = inode->i_sb->s_blocksize >> 2;
for (i = 0; i < EXT4_NDIR_BLOCKS; i++) {
if (i_data[i]) {
retval = update_extent_range(handle, tmp_inode,
le32_to_cpu(i_data[i]), &lb);
if (retval)
goto err_out;
} else
lb.curr_block++;
}
if (i_data[EXT4_IND_BLOCK]) {
retval = update_ind_extent_range(handle, tmp_inode,
le32_to_cpu(i_data[EXT4_IND_BLOCK]), &lb);
if (retval)
goto err_out;
} else
lb.curr_block += max_entries;
if (i_data[EXT4_DIND_BLOCK]) {
retval = update_dind_extent_range(handle, tmp_inode,
le32_to_cpu(i_data[EXT4_DIND_BLOCK]), &lb);
if (retval)
goto err_out;
} else
lb.curr_block += max_entries * max_entries;
if (i_data[EXT4_TIND_BLOCK]) {
retval = update_tind_extent_range(handle, tmp_inode,
le32_to_cpu(i_data[EXT4_TIND_BLOCK]), &lb);
if (retval)
goto err_out;
}
/*
* Build the last extent
*/
retval = finish_range(handle, tmp_inode, &lb);
err_out:
if (retval)
/*
* Failure case delete the extent information with the
* tmp_inode
*/
free_ext_block(handle, tmp_inode);
else {
retval = ext4_ext_swap_inode_data(handle, inode, tmp_inode);
if (retval)
/*
* if we fail to swap inode data free the extent
* details of the tmp inode
*/
free_ext_block(handle, tmp_inode);
}
/* We mark the tmp_inode dirty via ext4_ext_tree_init. */
if (ext4_journal_extend(handle, 1) != 0)
ext4_journal_restart(handle, 1);
/*
* Mark the tmp_inode as of size zero
*/
i_size_write(tmp_inode, 0);
/*
* set the i_blocks count to zero
* so that the ext4_delete_inode does the
* right job
*
* We don't need to take the i_lock because
* the inode is not visible to user space.
*/
tmp_inode->i_blocks = 0;
/* Reset the extent details */
ext4_ext_tree_init(handle, tmp_inode);
ext4_journal_stop(handle);
out:
unlock_new_inode(tmp_inode);
iput(tmp_inode);
return retval;
}
/*
* Migrate a simple extent-based inode to use the i_blocks[] array
*/
int ext4_ind_migrate(struct inode *inode)
{
struct ext4_extent_header *eh;
struct ext4_super_block *es = EXT4_SB(inode->i_sb)->s_es;
struct ext4_inode_info *ei = EXT4_I(inode);
struct ext4_extent *ex;
unsigned int i, len;
ext4_fsblk_t blk;
handle_t *handle;
int ret;
if (!EXT4_HAS_INCOMPAT_FEATURE(inode->i_sb,
EXT4_FEATURE_INCOMPAT_EXTENTS) ||
(!ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)))
return -EINVAL;
if (EXT4_HAS_RO_COMPAT_FEATURE(inode->i_sb,
EXT4_FEATURE_RO_COMPAT_BIGALLOC))
return -EOPNOTSUPP;
handle = ext4_journal_start(inode, EXT4_HT_MIGRATE, 1);
if (IS_ERR(handle))
return PTR_ERR(handle);
down_write(&EXT4_I(inode)->i_data_sem);
ret = ext4_ext_check_inode(inode);
if (ret)
goto errout;
eh = ext_inode_hdr(inode);
ex = EXT_FIRST_EXTENT(eh);
if (ext4_blocks_count(es) > EXT4_MAX_BLOCK_FILE_PHYS ||
eh->eh_depth != 0 || le16_to_cpu(eh->eh_entries) > 1) {
ret = -EOPNOTSUPP;
goto errout;
}
if (eh->eh_entries == 0)
blk = len = 0;
else {
len = le16_to_cpu(ex->ee_len);
blk = ext4_ext_pblock(ex);
if (len > EXT4_NDIR_BLOCKS) {
ret = -EOPNOTSUPP;
goto errout;
}
}
ext4_clear_inode_flag(inode, EXT4_INODE_EXTENTS);
memset(ei->i_data, 0, sizeof(ei->i_data));
for (i=0; i < len; i++)
ei->i_data[i] = cpu_to_le32(blk++);
ext4_mark_inode_dirty(handle, inode);
errout:
ext4_journal_stop(handle);
up_write(&EXT4_I(inode)->i_data_sem);
return ret;
}
| gpl-2.0 |
iDroid-Project/kernel_common | arch/arm/mach-at91/at91sam9263.c | 1635 | 8693 | /*
* arch/arm/mach-at91/at91sam9263.c
*
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/module.h>
#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9263.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9263_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
.length = AT91SAM9263_SRAM0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
.length = AT91SAM9263_SRAM1_SIZE,
.type = MT_DEVICE,
},
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
.name = "pioCDE_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
.name = "can_clk",
.pmc_mask = 1 << AT91SAM9263_ID_CAN,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
.name = "ac97_clk",
.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "macb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91SAM9263_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twodge_clk = {
.name = "2dge_clk",
.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioCDE_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&mmc0_clk,
&mmc1_clk,
&can_clk,
&twi_clk,
&spi0_clk,
&spi1_clk,
&ssc0_clk,
&ssc1_clk,
&ac97_clk,
&tcb_clk,
&pwm_clk,
&macb_clk,
&twodge_clk,
&udc_clk,
&isi_clk,
&lcdc_clk,
&dma_clk,
&ohci_clk,
// irq0 .. irq1
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};
static void __init at91sam9263_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9263_gpio[] = {
{
.id = AT91SAM9263_ID_PIOA,
.offset = AT91_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
.offset = AT91_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOC,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOD,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOE,
.clock = &pioCDE_clk,
}
};
static void at91sam9263_reset(void)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
static void at91sam9263_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}
/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
* -------------------------------------------------------------------- */
void __init at91sam9263_initialize(unsigned long main_clock)
{
/* Map peripherals */
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
at91_arch_reset = at91sam9263_reset;
pm_power_off = at91sam9263_poweroff;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9263_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5);
}
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
1, /* Parallel IO Controller A */
1, /* Parallel IO Controller B */
1, /* Parallel IO Controller C, D and E */
0,
0,
5, /* USART 0 */
5, /* USART 1 */
5, /* USART 2 */
0, /* Multimedia Card Interface 0 */
0, /* Multimedia Card Interface 1 */
3, /* CAN */
6, /* Two-Wire Interface */
5, /* Serial Peripheral Interface 0 */
5, /* Serial Peripheral Interface 1 */
4, /* Serial Synchronous Controller 0 */
4, /* Serial Synchronous Controller 1 */
5, /* AC97 Controller */
0, /* Timer Counter 0, 1 and 2 */
0, /* Pulse Width Modulation Controller */
3, /* Ethernet */
0,
0, /* 2D Graphic Engine */
2, /* USB Device Port */
0, /* Image Sensor Interface */
3, /* LDC Controller */
0, /* DMA Controller */
0,
2, /* USB Host port */
0, /* Advanced Interrupt Controller (IRQ0) */
0, /* Advanced Interrupt Controller (IRQ1) */
};
void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9263_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
| gpl-2.0 |
bshiznit/android_kernel_htc_flounder | drivers/video/backlight/pandora_bl.c | 2403 | 4561 | /*
* Backlight driver for Pandora handheld.
* Pandora uses TWL4030 PWM0 -> TPS61161 combo for control backlight.
* Based on pwm_bl.c
*
* Copyright 2009,2012 Gražvydas Ignotas <notasas@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/i2c/twl.h>
#include <linux/err.h>
#define TWL_PWM0_ON 0x00
#define TWL_PWM0_OFF 0x01
#define TWL_INTBR_GPBR1 0x0c
#define TWL_INTBR_PMBR1 0x0d
#define TWL_PMBR1_PWM0_MUXMASK 0x0c
#define TWL_PMBR1_PWM0 0x04
#define PWM0_CLK_ENABLE BIT(0)
#define PWM0_ENABLE BIT(2)
/* range accepted by hardware */
#define MIN_VALUE 9
#define MAX_VALUE 63
#define MAX_USER_VALUE (MAX_VALUE - MIN_VALUE)
#define PANDORABL_WAS_OFF BL_CORE_DRIVER1
static int pandora_backlight_update_status(struct backlight_device *bl)
{
int brightness = bl->props.brightness;
u8 r;
if (bl->props.power != FB_BLANK_UNBLANK)
brightness = 0;
if (bl->props.state & BL_CORE_FBBLANK)
brightness = 0;
if (bl->props.state & BL_CORE_SUSPENDED)
brightness = 0;
if ((unsigned int)brightness > MAX_USER_VALUE)
brightness = MAX_USER_VALUE;
if (brightness == 0) {
if (bl->props.state & PANDORABL_WAS_OFF)
goto done;
/* first disable PWM0 output, then clock */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &r, TWL_INTBR_GPBR1);
r &= ~PWM0_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
r &= ~PWM0_CLK_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
goto done;
}
if (bl->props.state & PANDORABL_WAS_OFF) {
/*
* set PWM duty cycle to max. TPS61161 seems to use this
* to calibrate it's PWM sensitivity when it starts.
*/
twl_i2c_write_u8(TWL_MODULE_PWM, MAX_VALUE, TWL_PWM0_OFF);
/* first enable clock, then PWM0 out */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &r, TWL_INTBR_GPBR1);
r &= ~PWM0_ENABLE;
r |= PWM0_CLK_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
r |= PWM0_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
/*
* TI made it very easy to enable digital control, so easy that
* it often triggers unintentionally and disabes PWM control,
* so wait until 1 wire mode detection window ends.
*/
usleep_range(2000, 10000);
}
twl_i2c_write_u8(TWL_MODULE_PWM, MIN_VALUE + brightness, TWL_PWM0_OFF);
done:
if (brightness != 0)
bl->props.state &= ~PANDORABL_WAS_OFF;
else
bl->props.state |= PANDORABL_WAS_OFF;
return 0;
}
static int pandora_backlight_get_brightness(struct backlight_device *bl)
{
return bl->props.brightness;
}
static const struct backlight_ops pandora_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = pandora_backlight_update_status,
.get_brightness = pandora_backlight_get_brightness,
};
static int pandora_backlight_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct backlight_device *bl;
u8 r;
memset(&props, 0, sizeof(props));
props.max_brightness = MAX_USER_VALUE;
props.type = BACKLIGHT_RAW;
bl = backlight_device_register(pdev->name, &pdev->dev,
NULL, &pandora_backlight_ops, &props);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
platform_set_drvdata(pdev, bl);
/* 64 cycle period, ON position 0 */
twl_i2c_write_u8(TWL_MODULE_PWM, 0x80, TWL_PWM0_ON);
bl->props.state |= PANDORABL_WAS_OFF;
bl->props.brightness = MAX_USER_VALUE;
backlight_update_status(bl);
/* enable PWM function in pin mux */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &r, TWL_INTBR_PMBR1);
r &= ~TWL_PMBR1_PWM0_MUXMASK;
r |= TWL_PMBR1_PWM0;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_PMBR1);
return 0;
}
static int pandora_backlight_remove(struct platform_device *pdev)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
backlight_device_unregister(bl);
return 0;
}
static struct platform_driver pandora_backlight_driver = {
.driver = {
.name = "pandora-backlight",
.owner = THIS_MODULE,
},
.probe = pandora_backlight_probe,
.remove = pandora_backlight_remove,
};
module_platform_driver(pandora_backlight_driver);
MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>");
MODULE_DESCRIPTION("Pandora Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pandora-backlight");
| gpl-2.0 |
EnJens/kernel_tf201_stock | drivers/net/can/sja1000/sja1000.c | 2915 | 16734 | /*
* sja1000.c - Philips SJA1000 network device driver
*
* Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
* 38106 Braunschweig, GERMANY
*
* Copyright (c) 2002-2007 Volkswagen Group Electronic Research
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Volkswagen nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Alternatively, provided that this notice is retained in full, this
* software may be distributed under the terms of the GNU General
* Public License ("GPL") version 2, in which case the provisions of the
* GPL apply INSTEAD OF those given above.
*
* The provided data structures and external interfaces from this code
* are not restricted to be used by modules with a GPL compatible license.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* Send feedback to <socketcan-users@lists.berlios.de>
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
#include "sja1000.h"
#define DRV_NAME "sja1000"
MODULE_AUTHOR("Oliver Hartkopp <oliver.hartkopp@volkswagen.de>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION(DRV_NAME "CAN netdevice driver");
static struct can_bittiming_const sja1000_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 1,
.tseg1_max = 16,
.tseg2_min = 1,
.tseg2_max = 8,
.sjw_max = 4,
.brp_min = 1,
.brp_max = 64,
.brp_inc = 1,
};
static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
{
unsigned long flags;
/*
* The command register needs some locking and time to settle
* the write_reg() operation - especially on SMP systems.
*/
spin_lock_irqsave(&priv->cmdreg_lock, flags);
priv->write_reg(priv, REG_CMR, val);
priv->read_reg(priv, REG_SR);
spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
}
static int sja1000_probe_chip(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
if (priv->reg_base && (priv->read_reg(priv, 0) == 0xFF)) {
printk(KERN_INFO "%s: probing @0x%lX failed\n",
DRV_NAME, dev->base_addr);
return 0;
}
return -1;
}
static void set_reset_mode(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
unsigned char status = priv->read_reg(priv, REG_MOD);
int i;
/* disable interrupts */
priv->write_reg(priv, REG_IER, IRQ_OFF);
for (i = 0; i < 100; i++) {
/* check reset bit */
if (status & MOD_RM) {
priv->can.state = CAN_STATE_STOPPED;
return;
}
priv->write_reg(priv, REG_MOD, MOD_RM); /* reset chip */
udelay(10);
status = priv->read_reg(priv, REG_MOD);
}
dev_err(dev->dev.parent, "setting SJA1000 into reset mode failed!\n");
}
static void set_normal_mode(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
unsigned char status = priv->read_reg(priv, REG_MOD);
int i;
for (i = 0; i < 100; i++) {
/* check reset bit */
if ((status & MOD_RM) == 0) {
priv->can.state = CAN_STATE_ERROR_ACTIVE;
/* enable interrupts */
if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
priv->write_reg(priv, REG_IER, IRQ_ALL);
else
priv->write_reg(priv, REG_IER,
IRQ_ALL & ~IRQ_BEI);
return;
}
/* set chip to normal mode */
priv->write_reg(priv, REG_MOD, 0x00);
udelay(10);
status = priv->read_reg(priv, REG_MOD);
}
dev_err(dev->dev.parent, "setting SJA1000 into normal mode failed!\n");
}
static void sja1000_start(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
/* leave reset mode */
if (priv->can.state != CAN_STATE_STOPPED)
set_reset_mode(dev);
/* Clear error counters and error code capture */
priv->write_reg(priv, REG_TXERR, 0x0);
priv->write_reg(priv, REG_RXERR, 0x0);
priv->read_reg(priv, REG_ECC);
/* leave reset mode */
set_normal_mode(dev);
}
static int sja1000_set_mode(struct net_device *dev, enum can_mode mode)
{
struct sja1000_priv *priv = netdev_priv(dev);
if (!priv->open_time)
return -EINVAL;
switch (mode) {
case CAN_MODE_START:
sja1000_start(dev);
if (netif_queue_stopped(dev))
netif_wake_queue(dev);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int sja1000_set_bittiming(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct can_bittiming *bt = &priv->can.bittiming;
u8 btr0, btr1;
btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
(((bt->phase_seg2 - 1) & 0x7) << 4);
if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
btr1 |= 0x80;
dev_info(dev->dev.parent,
"setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
priv->write_reg(priv, REG_BTR0, btr0);
priv->write_reg(priv, REG_BTR1, btr1);
return 0;
}
static int sja1000_get_berr_counter(const struct net_device *dev,
struct can_berr_counter *bec)
{
struct sja1000_priv *priv = netdev_priv(dev);
bec->txerr = priv->read_reg(priv, REG_TXERR);
bec->rxerr = priv->read_reg(priv, REG_RXERR);
return 0;
}
/*
* initialize SJA1000 chip:
* - reset chip
* - set output mode
* - set baudrate
* - enable interrupts
* - start operating mode
*/
static void chipset_init(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
/* set clock divider and output control register */
priv->write_reg(priv, REG_CDR, priv->cdr | CDR_PELICAN);
/* set acceptance filter (accept all) */
priv->write_reg(priv, REG_ACCC0, 0x00);
priv->write_reg(priv, REG_ACCC1, 0x00);
priv->write_reg(priv, REG_ACCC2, 0x00);
priv->write_reg(priv, REG_ACCC3, 0x00);
priv->write_reg(priv, REG_ACCM0, 0xFF);
priv->write_reg(priv, REG_ACCM1, 0xFF);
priv->write_reg(priv, REG_ACCM2, 0xFF);
priv->write_reg(priv, REG_ACCM3, 0xFF);
priv->write_reg(priv, REG_OCR, priv->ocr | OCR_MODE_NORMAL);
}
/*
* transmit a CAN message
* message layout in the sk_buff should be like this:
* xx xx xx xx ff ll 00 11 22 33 44 55 66 77
* [ can-id ] [flags] [len] [can data (up to 8 bytes]
*/
static netdev_tx_t sja1000_start_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct can_frame *cf = (struct can_frame *)skb->data;
uint8_t fi;
uint8_t dlc;
canid_t id;
uint8_t dreg;
int i;
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;
netif_stop_queue(dev);
fi = dlc = cf->can_dlc;
id = cf->can_id;
if (id & CAN_RTR_FLAG)
fi |= FI_RTR;
if (id & CAN_EFF_FLAG) {
fi |= FI_FF;
dreg = EFF_BUF;
priv->write_reg(priv, REG_FI, fi);
priv->write_reg(priv, REG_ID1, (id & 0x1fe00000) >> (5 + 16));
priv->write_reg(priv, REG_ID2, (id & 0x001fe000) >> (5 + 8));
priv->write_reg(priv, REG_ID3, (id & 0x00001fe0) >> 5);
priv->write_reg(priv, REG_ID4, (id & 0x0000001f) << 3);
} else {
dreg = SFF_BUF;
priv->write_reg(priv, REG_FI, fi);
priv->write_reg(priv, REG_ID1, (id & 0x000007f8) >> 3);
priv->write_reg(priv, REG_ID2, (id & 0x00000007) << 5);
}
for (i = 0; i < dlc; i++)
priv->write_reg(priv, dreg++, cf->data[i]);
can_put_echo_skb(skb, dev, 0);
sja1000_write_cmdreg(priv, CMD_TR);
return NETDEV_TX_OK;
}
static void sja1000_rx(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
struct can_frame *cf;
struct sk_buff *skb;
uint8_t fi;
uint8_t dreg;
canid_t id;
int i;
/* create zero'ed CAN frame buffer */
skb = alloc_can_skb(dev, &cf);
if (skb == NULL)
return;
fi = priv->read_reg(priv, REG_FI);
if (fi & FI_FF) {
/* extended frame format (EFF) */
dreg = EFF_BUF;
id = (priv->read_reg(priv, REG_ID1) << (5 + 16))
| (priv->read_reg(priv, REG_ID2) << (5 + 8))
| (priv->read_reg(priv, REG_ID3) << 5)
| (priv->read_reg(priv, REG_ID4) >> 3);
id |= CAN_EFF_FLAG;
} else {
/* standard frame format (SFF) */
dreg = SFF_BUF;
id = (priv->read_reg(priv, REG_ID1) << 3)
| (priv->read_reg(priv, REG_ID2) >> 5);
}
cf->can_dlc = get_can_dlc(fi & 0x0F);
if (fi & FI_RTR) {
id |= CAN_RTR_FLAG;
} else {
for (i = 0; i < cf->can_dlc; i++)
cf->data[i] = priv->read_reg(priv, dreg++);
}
cf->can_id = id;
/* release receive buffer */
sja1000_write_cmdreg(priv, CMD_RRB);
netif_rx(skb);
stats->rx_packets++;
stats->rx_bytes += cf->can_dlc;
}
static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
struct can_frame *cf;
struct sk_buff *skb;
enum can_state state = priv->can.state;
uint8_t ecc, alc;
skb = alloc_can_err_skb(dev, &cf);
if (skb == NULL)
return -ENOMEM;
if (isrc & IRQ_DOI) {
/* data overrun interrupt */
dev_dbg(dev->dev.parent, "data overrun interrupt\n");
cf->can_id |= CAN_ERR_CRTL;
cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
stats->rx_over_errors++;
stats->rx_errors++;
sja1000_write_cmdreg(priv, CMD_CDO); /* clear bit */
}
if (isrc & IRQ_EI) {
/* error warning interrupt */
dev_dbg(dev->dev.parent, "error warning interrupt\n");
if (status & SR_BS) {
state = CAN_STATE_BUS_OFF;
cf->can_id |= CAN_ERR_BUSOFF;
can_bus_off(dev);
} else if (status & SR_ES) {
state = CAN_STATE_ERROR_WARNING;
} else
state = CAN_STATE_ERROR_ACTIVE;
}
if (isrc & IRQ_BEI) {
/* bus error interrupt */
priv->can.can_stats.bus_error++;
stats->rx_errors++;
ecc = priv->read_reg(priv, REG_ECC);
cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
switch (ecc & ECC_MASK) {
case ECC_BIT:
cf->data[2] |= CAN_ERR_PROT_BIT;
break;
case ECC_FORM:
cf->data[2] |= CAN_ERR_PROT_FORM;
break;
case ECC_STUFF:
cf->data[2] |= CAN_ERR_PROT_STUFF;
break;
default:
cf->data[2] |= CAN_ERR_PROT_UNSPEC;
cf->data[3] = ecc & ECC_SEG;
break;
}
/* Error occurred during transmission? */
if ((ecc & ECC_DIR) == 0)
cf->data[2] |= CAN_ERR_PROT_TX;
}
if (isrc & IRQ_EPI) {
/* error passive interrupt */
dev_dbg(dev->dev.parent, "error passive interrupt\n");
if (status & SR_ES)
state = CAN_STATE_ERROR_PASSIVE;
else
state = CAN_STATE_ERROR_ACTIVE;
}
if (isrc & IRQ_ALI) {
/* arbitration lost interrupt */
dev_dbg(dev->dev.parent, "arbitration lost interrupt\n");
alc = priv->read_reg(priv, REG_ALC);
priv->can.can_stats.arbitration_lost++;
stats->tx_errors++;
cf->can_id |= CAN_ERR_LOSTARB;
cf->data[0] = alc & 0x1f;
}
if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
state == CAN_STATE_ERROR_PASSIVE)) {
uint8_t rxerr = priv->read_reg(priv, REG_RXERR);
uint8_t txerr = priv->read_reg(priv, REG_TXERR);
cf->can_id |= CAN_ERR_CRTL;
if (state == CAN_STATE_ERROR_WARNING) {
priv->can.can_stats.error_warning++;
cf->data[1] = (txerr > rxerr) ?
CAN_ERR_CRTL_TX_WARNING :
CAN_ERR_CRTL_RX_WARNING;
} else {
priv->can.can_stats.error_passive++;
cf->data[1] = (txerr > rxerr) ?
CAN_ERR_CRTL_TX_PASSIVE :
CAN_ERR_CRTL_RX_PASSIVE;
}
cf->data[6] = txerr;
cf->data[7] = rxerr;
}
priv->can.state = state;
netif_rx(skb);
stats->rx_packets++;
stats->rx_bytes += cf->can_dlc;
return 0;
}
irqreturn_t sja1000_interrupt(int irq, void *dev_id)
{
struct net_device *dev = (struct net_device *)dev_id;
struct sja1000_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
uint8_t isrc, status;
int n = 0;
/* Shared interrupts and IRQ off? */
if (priv->read_reg(priv, REG_IER) == IRQ_OFF)
return IRQ_NONE;
if (priv->pre_irq)
priv->pre_irq(priv);
while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
n++;
status = priv->read_reg(priv, REG_SR);
if (isrc & IRQ_WUI)
dev_warn(dev->dev.parent, "wakeup interrupt\n");
if (isrc & IRQ_TI) {
/* transmission complete interrupt */
stats->tx_bytes += priv->read_reg(priv, REG_FI) & 0xf;
stats->tx_packets++;
can_get_echo_skb(dev, 0);
netif_wake_queue(dev);
}
if (isrc & IRQ_RI) {
/* receive interrupt */
while (status & SR_RBS) {
sja1000_rx(dev);
status = priv->read_reg(priv, REG_SR);
}
}
if (isrc & (IRQ_DOI | IRQ_EI | IRQ_BEI | IRQ_EPI | IRQ_ALI)) {
/* error interrupt */
if (sja1000_err(dev, isrc, status))
break;
}
}
if (priv->post_irq)
priv->post_irq(priv);
if (n >= SJA1000_MAX_IRQ)
dev_dbg(dev->dev.parent, "%d messages handled in ISR", n);
return (n) ? IRQ_HANDLED : IRQ_NONE;
}
EXPORT_SYMBOL_GPL(sja1000_interrupt);
static int sja1000_open(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
int err;
/* set chip into reset mode */
set_reset_mode(dev);
/* common open */
err = open_candev(dev);
if (err)
return err;
/* register interrupt handler, if not done by the device driver */
if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER)) {
err = request_irq(dev->irq, sja1000_interrupt, priv->irq_flags,
dev->name, (void *)dev);
if (err) {
close_candev(dev);
return -EAGAIN;
}
}
/* init and start chi */
sja1000_start(dev);
priv->open_time = jiffies;
netif_start_queue(dev);
return 0;
}
static int sja1000_close(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
netif_stop_queue(dev);
set_reset_mode(dev);
if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER))
free_irq(dev->irq, (void *)dev);
close_candev(dev);
priv->open_time = 0;
return 0;
}
struct net_device *alloc_sja1000dev(int sizeof_priv)
{
struct net_device *dev;
struct sja1000_priv *priv;
dev = alloc_candev(sizeof(struct sja1000_priv) + sizeof_priv,
SJA1000_ECHO_SKB_MAX);
if (!dev)
return NULL;
priv = netdev_priv(dev);
priv->dev = dev;
priv->can.bittiming_const = &sja1000_bittiming_const;
priv->can.do_set_bittiming = sja1000_set_bittiming;
priv->can.do_set_mode = sja1000_set_mode;
priv->can.do_get_berr_counter = sja1000_get_berr_counter;
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
CAN_CTRLMODE_BERR_REPORTING;
spin_lock_init(&priv->cmdreg_lock);
if (sizeof_priv)
priv->priv = (void *)priv + sizeof(struct sja1000_priv);
return dev;
}
EXPORT_SYMBOL_GPL(alloc_sja1000dev);
void free_sja1000dev(struct net_device *dev)
{
free_candev(dev);
}
EXPORT_SYMBOL_GPL(free_sja1000dev);
static const struct net_device_ops sja1000_netdev_ops = {
.ndo_open = sja1000_open,
.ndo_stop = sja1000_close,
.ndo_start_xmit = sja1000_start_xmit,
};
int register_sja1000dev(struct net_device *dev)
{
if (!sja1000_probe_chip(dev))
return -ENODEV;
dev->flags |= IFF_ECHO; /* we support local echo */
dev->netdev_ops = &sja1000_netdev_ops;
set_reset_mode(dev);
chipset_init(dev);
return register_candev(dev);
}
EXPORT_SYMBOL_GPL(register_sja1000dev);
void unregister_sja1000dev(struct net_device *dev)
{
set_reset_mode(dev);
unregister_candev(dev);
}
EXPORT_SYMBOL_GPL(unregister_sja1000dev);
static __init int sja1000_init(void)
{
printk(KERN_INFO "%s CAN netdevice driver\n", DRV_NAME);
return 0;
}
module_init(sja1000_init);
static __exit void sja1000_exit(void)
{
printk(KERN_INFO "%s: driver removed\n", DRV_NAME);
}
module_exit(sja1000_exit);
| gpl-2.0 |
MCP1/android_kernel_motorola_msm8960-common | drivers/net/can/sja1000/sja1000.c | 2915 | 16734 | /*
* sja1000.c - Philips SJA1000 network device driver
*
* Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
* 38106 Braunschweig, GERMANY
*
* Copyright (c) 2002-2007 Volkswagen Group Electronic Research
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Volkswagen nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Alternatively, provided that this notice is retained in full, this
* software may be distributed under the terms of the GNU General
* Public License ("GPL") version 2, in which case the provisions of the
* GPL apply INSTEAD OF those given above.
*
* The provided data structures and external interfaces from this code
* are not restricted to be used by modules with a GPL compatible license.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* Send feedback to <socketcan-users@lists.berlios.de>
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
#include "sja1000.h"
#define DRV_NAME "sja1000"
MODULE_AUTHOR("Oliver Hartkopp <oliver.hartkopp@volkswagen.de>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION(DRV_NAME "CAN netdevice driver");
static struct can_bittiming_const sja1000_bittiming_const = {
.name = DRV_NAME,
.tseg1_min = 1,
.tseg1_max = 16,
.tseg2_min = 1,
.tseg2_max = 8,
.sjw_max = 4,
.brp_min = 1,
.brp_max = 64,
.brp_inc = 1,
};
static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
{
unsigned long flags;
/*
* The command register needs some locking and time to settle
* the write_reg() operation - especially on SMP systems.
*/
spin_lock_irqsave(&priv->cmdreg_lock, flags);
priv->write_reg(priv, REG_CMR, val);
priv->read_reg(priv, REG_SR);
spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
}
static int sja1000_probe_chip(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
if (priv->reg_base && (priv->read_reg(priv, 0) == 0xFF)) {
printk(KERN_INFO "%s: probing @0x%lX failed\n",
DRV_NAME, dev->base_addr);
return 0;
}
return -1;
}
static void set_reset_mode(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
unsigned char status = priv->read_reg(priv, REG_MOD);
int i;
/* disable interrupts */
priv->write_reg(priv, REG_IER, IRQ_OFF);
for (i = 0; i < 100; i++) {
/* check reset bit */
if (status & MOD_RM) {
priv->can.state = CAN_STATE_STOPPED;
return;
}
priv->write_reg(priv, REG_MOD, MOD_RM); /* reset chip */
udelay(10);
status = priv->read_reg(priv, REG_MOD);
}
dev_err(dev->dev.parent, "setting SJA1000 into reset mode failed!\n");
}
static void set_normal_mode(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
unsigned char status = priv->read_reg(priv, REG_MOD);
int i;
for (i = 0; i < 100; i++) {
/* check reset bit */
if ((status & MOD_RM) == 0) {
priv->can.state = CAN_STATE_ERROR_ACTIVE;
/* enable interrupts */
if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
priv->write_reg(priv, REG_IER, IRQ_ALL);
else
priv->write_reg(priv, REG_IER,
IRQ_ALL & ~IRQ_BEI);
return;
}
/* set chip to normal mode */
priv->write_reg(priv, REG_MOD, 0x00);
udelay(10);
status = priv->read_reg(priv, REG_MOD);
}
dev_err(dev->dev.parent, "setting SJA1000 into normal mode failed!\n");
}
static void sja1000_start(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
/* leave reset mode */
if (priv->can.state != CAN_STATE_STOPPED)
set_reset_mode(dev);
/* Clear error counters and error code capture */
priv->write_reg(priv, REG_TXERR, 0x0);
priv->write_reg(priv, REG_RXERR, 0x0);
priv->read_reg(priv, REG_ECC);
/* leave reset mode */
set_normal_mode(dev);
}
static int sja1000_set_mode(struct net_device *dev, enum can_mode mode)
{
struct sja1000_priv *priv = netdev_priv(dev);
if (!priv->open_time)
return -EINVAL;
switch (mode) {
case CAN_MODE_START:
sja1000_start(dev);
if (netif_queue_stopped(dev))
netif_wake_queue(dev);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int sja1000_set_bittiming(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct can_bittiming *bt = &priv->can.bittiming;
u8 btr0, btr1;
btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
(((bt->phase_seg2 - 1) & 0x7) << 4);
if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
btr1 |= 0x80;
dev_info(dev->dev.parent,
"setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
priv->write_reg(priv, REG_BTR0, btr0);
priv->write_reg(priv, REG_BTR1, btr1);
return 0;
}
static int sja1000_get_berr_counter(const struct net_device *dev,
struct can_berr_counter *bec)
{
struct sja1000_priv *priv = netdev_priv(dev);
bec->txerr = priv->read_reg(priv, REG_TXERR);
bec->rxerr = priv->read_reg(priv, REG_RXERR);
return 0;
}
/*
* initialize SJA1000 chip:
* - reset chip
* - set output mode
* - set baudrate
* - enable interrupts
* - start operating mode
*/
static void chipset_init(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
/* set clock divider and output control register */
priv->write_reg(priv, REG_CDR, priv->cdr | CDR_PELICAN);
/* set acceptance filter (accept all) */
priv->write_reg(priv, REG_ACCC0, 0x00);
priv->write_reg(priv, REG_ACCC1, 0x00);
priv->write_reg(priv, REG_ACCC2, 0x00);
priv->write_reg(priv, REG_ACCC3, 0x00);
priv->write_reg(priv, REG_ACCM0, 0xFF);
priv->write_reg(priv, REG_ACCM1, 0xFF);
priv->write_reg(priv, REG_ACCM2, 0xFF);
priv->write_reg(priv, REG_ACCM3, 0xFF);
priv->write_reg(priv, REG_OCR, priv->ocr | OCR_MODE_NORMAL);
}
/*
* transmit a CAN message
* message layout in the sk_buff should be like this:
* xx xx xx xx ff ll 00 11 22 33 44 55 66 77
* [ can-id ] [flags] [len] [can data (up to 8 bytes]
*/
static netdev_tx_t sja1000_start_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct can_frame *cf = (struct can_frame *)skb->data;
uint8_t fi;
uint8_t dlc;
canid_t id;
uint8_t dreg;
int i;
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;
netif_stop_queue(dev);
fi = dlc = cf->can_dlc;
id = cf->can_id;
if (id & CAN_RTR_FLAG)
fi |= FI_RTR;
if (id & CAN_EFF_FLAG) {
fi |= FI_FF;
dreg = EFF_BUF;
priv->write_reg(priv, REG_FI, fi);
priv->write_reg(priv, REG_ID1, (id & 0x1fe00000) >> (5 + 16));
priv->write_reg(priv, REG_ID2, (id & 0x001fe000) >> (5 + 8));
priv->write_reg(priv, REG_ID3, (id & 0x00001fe0) >> 5);
priv->write_reg(priv, REG_ID4, (id & 0x0000001f) << 3);
} else {
dreg = SFF_BUF;
priv->write_reg(priv, REG_FI, fi);
priv->write_reg(priv, REG_ID1, (id & 0x000007f8) >> 3);
priv->write_reg(priv, REG_ID2, (id & 0x00000007) << 5);
}
for (i = 0; i < dlc; i++)
priv->write_reg(priv, dreg++, cf->data[i]);
can_put_echo_skb(skb, dev, 0);
sja1000_write_cmdreg(priv, CMD_TR);
return NETDEV_TX_OK;
}
static void sja1000_rx(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
struct can_frame *cf;
struct sk_buff *skb;
uint8_t fi;
uint8_t dreg;
canid_t id;
int i;
/* create zero'ed CAN frame buffer */
skb = alloc_can_skb(dev, &cf);
if (skb == NULL)
return;
fi = priv->read_reg(priv, REG_FI);
if (fi & FI_FF) {
/* extended frame format (EFF) */
dreg = EFF_BUF;
id = (priv->read_reg(priv, REG_ID1) << (5 + 16))
| (priv->read_reg(priv, REG_ID2) << (5 + 8))
| (priv->read_reg(priv, REG_ID3) << 5)
| (priv->read_reg(priv, REG_ID4) >> 3);
id |= CAN_EFF_FLAG;
} else {
/* standard frame format (SFF) */
dreg = SFF_BUF;
id = (priv->read_reg(priv, REG_ID1) << 3)
| (priv->read_reg(priv, REG_ID2) >> 5);
}
cf->can_dlc = get_can_dlc(fi & 0x0F);
if (fi & FI_RTR) {
id |= CAN_RTR_FLAG;
} else {
for (i = 0; i < cf->can_dlc; i++)
cf->data[i] = priv->read_reg(priv, dreg++);
}
cf->can_id = id;
/* release receive buffer */
sja1000_write_cmdreg(priv, CMD_RRB);
netif_rx(skb);
stats->rx_packets++;
stats->rx_bytes += cf->can_dlc;
}
static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)
{
struct sja1000_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
struct can_frame *cf;
struct sk_buff *skb;
enum can_state state = priv->can.state;
uint8_t ecc, alc;
skb = alloc_can_err_skb(dev, &cf);
if (skb == NULL)
return -ENOMEM;
if (isrc & IRQ_DOI) {
/* data overrun interrupt */
dev_dbg(dev->dev.parent, "data overrun interrupt\n");
cf->can_id |= CAN_ERR_CRTL;
cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
stats->rx_over_errors++;
stats->rx_errors++;
sja1000_write_cmdreg(priv, CMD_CDO); /* clear bit */
}
if (isrc & IRQ_EI) {
/* error warning interrupt */
dev_dbg(dev->dev.parent, "error warning interrupt\n");
if (status & SR_BS) {
state = CAN_STATE_BUS_OFF;
cf->can_id |= CAN_ERR_BUSOFF;
can_bus_off(dev);
} else if (status & SR_ES) {
state = CAN_STATE_ERROR_WARNING;
} else
state = CAN_STATE_ERROR_ACTIVE;
}
if (isrc & IRQ_BEI) {
/* bus error interrupt */
priv->can.can_stats.bus_error++;
stats->rx_errors++;
ecc = priv->read_reg(priv, REG_ECC);
cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
switch (ecc & ECC_MASK) {
case ECC_BIT:
cf->data[2] |= CAN_ERR_PROT_BIT;
break;
case ECC_FORM:
cf->data[2] |= CAN_ERR_PROT_FORM;
break;
case ECC_STUFF:
cf->data[2] |= CAN_ERR_PROT_STUFF;
break;
default:
cf->data[2] |= CAN_ERR_PROT_UNSPEC;
cf->data[3] = ecc & ECC_SEG;
break;
}
/* Error occurred during transmission? */
if ((ecc & ECC_DIR) == 0)
cf->data[2] |= CAN_ERR_PROT_TX;
}
if (isrc & IRQ_EPI) {
/* error passive interrupt */
dev_dbg(dev->dev.parent, "error passive interrupt\n");
if (status & SR_ES)
state = CAN_STATE_ERROR_PASSIVE;
else
state = CAN_STATE_ERROR_ACTIVE;
}
if (isrc & IRQ_ALI) {
/* arbitration lost interrupt */
dev_dbg(dev->dev.parent, "arbitration lost interrupt\n");
alc = priv->read_reg(priv, REG_ALC);
priv->can.can_stats.arbitration_lost++;
stats->tx_errors++;
cf->can_id |= CAN_ERR_LOSTARB;
cf->data[0] = alc & 0x1f;
}
if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
state == CAN_STATE_ERROR_PASSIVE)) {
uint8_t rxerr = priv->read_reg(priv, REG_RXERR);
uint8_t txerr = priv->read_reg(priv, REG_TXERR);
cf->can_id |= CAN_ERR_CRTL;
if (state == CAN_STATE_ERROR_WARNING) {
priv->can.can_stats.error_warning++;
cf->data[1] = (txerr > rxerr) ?
CAN_ERR_CRTL_TX_WARNING :
CAN_ERR_CRTL_RX_WARNING;
} else {
priv->can.can_stats.error_passive++;
cf->data[1] = (txerr > rxerr) ?
CAN_ERR_CRTL_TX_PASSIVE :
CAN_ERR_CRTL_RX_PASSIVE;
}
cf->data[6] = txerr;
cf->data[7] = rxerr;
}
priv->can.state = state;
netif_rx(skb);
stats->rx_packets++;
stats->rx_bytes += cf->can_dlc;
return 0;
}
irqreturn_t sja1000_interrupt(int irq, void *dev_id)
{
struct net_device *dev = (struct net_device *)dev_id;
struct sja1000_priv *priv = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
uint8_t isrc, status;
int n = 0;
/* Shared interrupts and IRQ off? */
if (priv->read_reg(priv, REG_IER) == IRQ_OFF)
return IRQ_NONE;
if (priv->pre_irq)
priv->pre_irq(priv);
while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
n++;
status = priv->read_reg(priv, REG_SR);
if (isrc & IRQ_WUI)
dev_warn(dev->dev.parent, "wakeup interrupt\n");
if (isrc & IRQ_TI) {
/* transmission complete interrupt */
stats->tx_bytes += priv->read_reg(priv, REG_FI) & 0xf;
stats->tx_packets++;
can_get_echo_skb(dev, 0);
netif_wake_queue(dev);
}
if (isrc & IRQ_RI) {
/* receive interrupt */
while (status & SR_RBS) {
sja1000_rx(dev);
status = priv->read_reg(priv, REG_SR);
}
}
if (isrc & (IRQ_DOI | IRQ_EI | IRQ_BEI | IRQ_EPI | IRQ_ALI)) {
/* error interrupt */
if (sja1000_err(dev, isrc, status))
break;
}
}
if (priv->post_irq)
priv->post_irq(priv);
if (n >= SJA1000_MAX_IRQ)
dev_dbg(dev->dev.parent, "%d messages handled in ISR", n);
return (n) ? IRQ_HANDLED : IRQ_NONE;
}
EXPORT_SYMBOL_GPL(sja1000_interrupt);
static int sja1000_open(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
int err;
/* set chip into reset mode */
set_reset_mode(dev);
/* common open */
err = open_candev(dev);
if (err)
return err;
/* register interrupt handler, if not done by the device driver */
if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER)) {
err = request_irq(dev->irq, sja1000_interrupt, priv->irq_flags,
dev->name, (void *)dev);
if (err) {
close_candev(dev);
return -EAGAIN;
}
}
/* init and start chi */
sja1000_start(dev);
priv->open_time = jiffies;
netif_start_queue(dev);
return 0;
}
static int sja1000_close(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
netif_stop_queue(dev);
set_reset_mode(dev);
if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER))
free_irq(dev->irq, (void *)dev);
close_candev(dev);
priv->open_time = 0;
return 0;
}
struct net_device *alloc_sja1000dev(int sizeof_priv)
{
struct net_device *dev;
struct sja1000_priv *priv;
dev = alloc_candev(sizeof(struct sja1000_priv) + sizeof_priv,
SJA1000_ECHO_SKB_MAX);
if (!dev)
return NULL;
priv = netdev_priv(dev);
priv->dev = dev;
priv->can.bittiming_const = &sja1000_bittiming_const;
priv->can.do_set_bittiming = sja1000_set_bittiming;
priv->can.do_set_mode = sja1000_set_mode;
priv->can.do_get_berr_counter = sja1000_get_berr_counter;
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
CAN_CTRLMODE_BERR_REPORTING;
spin_lock_init(&priv->cmdreg_lock);
if (sizeof_priv)
priv->priv = (void *)priv + sizeof(struct sja1000_priv);
return dev;
}
EXPORT_SYMBOL_GPL(alloc_sja1000dev);
void free_sja1000dev(struct net_device *dev)
{
free_candev(dev);
}
EXPORT_SYMBOL_GPL(free_sja1000dev);
static const struct net_device_ops sja1000_netdev_ops = {
.ndo_open = sja1000_open,
.ndo_stop = sja1000_close,
.ndo_start_xmit = sja1000_start_xmit,
};
int register_sja1000dev(struct net_device *dev)
{
if (!sja1000_probe_chip(dev))
return -ENODEV;
dev->flags |= IFF_ECHO; /* we support local echo */
dev->netdev_ops = &sja1000_netdev_ops;
set_reset_mode(dev);
chipset_init(dev);
return register_candev(dev);
}
EXPORT_SYMBOL_GPL(register_sja1000dev);
void unregister_sja1000dev(struct net_device *dev)
{
set_reset_mode(dev);
unregister_candev(dev);
}
EXPORT_SYMBOL_GPL(unregister_sja1000dev);
static __init int sja1000_init(void)
{
printk(KERN_INFO "%s CAN netdevice driver\n", DRV_NAME);
return 0;
}
module_init(sja1000_init);
static __exit void sja1000_exit(void)
{
printk(KERN_INFO "%s: driver removed\n", DRV_NAME);
}
module_exit(sja1000_exit);
| gpl-2.0 |
h8rift/android_kernel_htc_msm8960-evita | drivers/of/of_mdio.c | 2915 | 5070 | /*
* OF helpers for the MDIO (Ethernet PHY) API
*
* Copyright (c) 2009 Secret Lab Technologies, Ltd.
*
* This file is released under the GPLv2
*
* This file provides helper functions for extracting PHY device information
* out of the OpenFirmware device tree and using it to populate an mii_bus.
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/netdevice.h>
#include <linux/err.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
#include <linux/module.h>
MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
MODULE_LICENSE("GPL");
/**
* of_mdiobus_register - Register mii_bus and create PHYs from the device tree
* @mdio: pointer to mii_bus structure
* @np: pointer to device_node of MDIO bus.
*
* This function registers the mii_bus structure and registers a phy_device
* for each child node of @np.
*/
int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
{
struct phy_device *phy;
struct device_node *child;
int rc, i;
/* Mask out all PHYs from auto probing. Instead the PHYs listed in
* the device tree are populated after the bus has been registered */
mdio->phy_mask = ~0;
/* Clear all the IRQ properties */
if (mdio->irq)
for (i=0; i<PHY_MAX_ADDR; i++)
mdio->irq[i] = PHY_POLL;
/* Register the MDIO bus */
rc = mdiobus_register(mdio);
if (rc)
return rc;
/* Loop over the child nodes and register a phy_device for each one */
for_each_child_of_node(np, child) {
const __be32 *paddr;
u32 addr;
int len;
/* A PHY must have a reg property in the range [0-31] */
paddr = of_get_property(child, "reg", &len);
if (!paddr || len < sizeof(*paddr)) {
dev_err(&mdio->dev, "%s has invalid PHY address\n",
child->full_name);
continue;
}
addr = be32_to_cpup(paddr);
if (addr >= 32) {
dev_err(&mdio->dev, "%s PHY address %i is too large\n",
child->full_name, addr);
continue;
}
if (mdio->irq) {
mdio->irq[addr] = irq_of_parse_and_map(child, 0);
if (!mdio->irq[addr])
mdio->irq[addr] = PHY_POLL;
}
phy = get_phy_device(mdio, addr);
if (!phy || IS_ERR(phy)) {
dev_err(&mdio->dev, "error probing PHY at address %i\n",
addr);
continue;
}
phy_scan_fixups(phy);
/* Associate the OF node with the device structure so it
* can be looked up later */
of_node_get(child);
phy->dev.of_node = child;
/* All data is now stored in the phy struct; register it */
rc = phy_device_register(phy);
if (rc) {
phy_device_free(phy);
of_node_put(child);
continue;
}
dev_dbg(&mdio->dev, "registered phy %s at address %i\n",
child->name, addr);
}
return 0;
}
EXPORT_SYMBOL(of_mdiobus_register);
/* Helper function for of_phy_find_device */
static int of_phy_match(struct device *dev, void *phy_np)
{
return dev->of_node == phy_np;
}
/**
* of_phy_find_device - Give a PHY node, find the phy_device
* @phy_np: Pointer to the phy's device tree node
*
* Returns a pointer to the phy_device.
*/
struct phy_device *of_phy_find_device(struct device_node *phy_np)
{
struct device *d;
if (!phy_np)
return NULL;
d = bus_find_device(&mdio_bus_type, NULL, phy_np, of_phy_match);
return d ? to_phy_device(d) : NULL;
}
EXPORT_SYMBOL(of_phy_find_device);
/**
* of_phy_connect - Connect to the phy described in the device tree
* @dev: pointer to net_device claiming the phy
* @phy_np: Pointer to device tree node for the PHY
* @hndlr: Link state callback for the network device
* @iface: PHY data interface type
*
* Returns a pointer to the phy_device if successful. NULL otherwise
*/
struct phy_device *of_phy_connect(struct net_device *dev,
struct device_node *phy_np,
void (*hndlr)(struct net_device *), u32 flags,
phy_interface_t iface)
{
struct phy_device *phy = of_phy_find_device(phy_np);
if (!phy)
return NULL;
return phy_connect_direct(dev, phy, hndlr, flags, iface) ? NULL : phy;
}
EXPORT_SYMBOL(of_phy_connect);
/**
* of_phy_connect_fixed_link - Parse fixed-link property and return a dummy phy
* @dev: pointer to net_device claiming the phy
* @hndlr: Link state callback for the network device
* @iface: PHY data interface type
*
* This function is a temporary stop-gap and will be removed soon. It is
* only to support the fs_enet, ucc_geth and gianfar Ethernet drivers. Do
* not call this function from new drivers.
*/
struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
void (*hndlr)(struct net_device *),
phy_interface_t iface)
{
struct device_node *net_np;
char bus_id[MII_BUS_ID_SIZE + 3];
struct phy_device *phy;
const __be32 *phy_id;
int sz;
if (!dev->dev.parent)
return NULL;
net_np = dev->dev.parent->of_node;
if (!net_np)
return NULL;
phy_id = of_get_property(net_np, "fixed-link", &sz);
if (!phy_id || sz < sizeof(*phy_id))
return NULL;
sprintf(bus_id, PHY_ID_FMT, "0", be32_to_cpu(phy_id[0]));
phy = phy_connect(dev, bus_id, hndlr, 0, iface);
return IS_ERR(phy) ? NULL : phy;
}
EXPORT_SYMBOL(of_phy_connect_fixed_link);
| gpl-2.0 |
languitar/android_kernel_lge_hammerhead | drivers/leds/leds-pmic-mpp.c | 3427 | 3504 | /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <mach/pmic.h>
#define LED_MPP(x) ((x) & 0xFF)
#define LED_CURR(x) ((x) >> 16)
struct pmic_mpp_led_data {
struct led_classdev cdev;
int curr;
int mpp;
};
static void pm_mpp_led_set(struct led_classdev *led_cdev,
enum led_brightness value)
{
struct pmic_mpp_led_data *led;
int ret;
led = container_of(led_cdev, struct pmic_mpp_led_data, cdev);
if (value < LED_OFF || value > led->cdev.max_brightness) {
dev_err(led->cdev.dev, "Invalid brightness value");
return;
}
ret = pmic_secure_mpp_config_i_sink(led->mpp, led->curr,
value ? PM_MPP__I_SINK__SWITCH_ENA :
PM_MPP__I_SINK__SWITCH_DIS);
if (ret)
dev_err(led_cdev->dev, "can't set mpp led\n");
}
static int pmic_mpp_led_probe(struct platform_device *pdev)
{
const struct led_platform_data *pdata = pdev->dev.platform_data;
struct pmic_mpp_led_data *led, *tmp_led;
int i, rc;
if (!pdata) {
dev_err(&pdev->dev, "platform data not supplied\n");
return -EINVAL;
}
led = kcalloc(pdata->num_leds, sizeof(*led), GFP_KERNEL);
if (!led) {
dev_err(&pdev->dev, "failed to alloc memory\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, led);
for (i = 0; i < pdata->num_leds; i++) {
tmp_led = &led[i];
tmp_led->cdev.name = pdata->leds[i].name;
tmp_led->cdev.brightness_set = pm_mpp_led_set;
tmp_led->cdev.brightness = LED_OFF;
tmp_led->cdev.max_brightness = LED_FULL;
tmp_led->mpp = LED_MPP(pdata->leds[i].flags);
tmp_led->curr = LED_CURR(pdata->leds[i].flags);
if (tmp_led->curr < PM_MPP__I_SINK__LEVEL_5mA ||
tmp_led->curr > PM_MPP__I_SINK__LEVEL_40mA) {
dev_err(&pdev->dev, "invalid current\n");
goto unreg_led_cdev;
}
rc = led_classdev_register(&pdev->dev, &tmp_led->cdev);
if (rc) {
dev_err(&pdev->dev, "failed to register led\n");
goto unreg_led_cdev;
}
}
return 0;
unreg_led_cdev:
while (i)
led_classdev_unregister(&led[--i].cdev);
kfree(led);
return rc;
}
static int __devexit pmic_mpp_led_remove(struct platform_device *pdev)
{
const struct led_platform_data *pdata = pdev->dev.platform_data;
struct pmic_mpp_led_data *led = platform_get_drvdata(pdev);
int i;
for (i = 0; i < pdata->num_leds; i++)
led_classdev_unregister(&led[i].cdev);
kfree(led);
return 0;
}
static struct platform_driver pmic_mpp_led_driver = {
.probe = pmic_mpp_led_probe,
.remove = __devexit_p(pmic_mpp_led_remove),
.driver = {
.name = "pmic-mpp-leds",
.owner = THIS_MODULE,
},
};
static int __init pmic_mpp_led_init(void)
{
return platform_driver_register(&pmic_mpp_led_driver);
}
module_init(pmic_mpp_led_init);
static void __exit pmic_mpp_led_exit(void)
{
platform_driver_unregister(&pmic_mpp_led_driver);
}
module_exit(pmic_mpp_led_exit);
MODULE_DESCRIPTION("PMIC MPP LEDs driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:pmic-mpp-leds");
| gpl-2.0 |
motley-git/TF201-Kernel | drivers/watchdog/indydog.c | 4195 | 5008 | /*
* IndyDog 0.3 A Hardware Watchdog Device for SGI IP22
*
* (c) Copyright 2002 Guido Guenther <agx@sigxcpu.org>,
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* based on softdog.c by Alan Cox <alan@lxorguk.ukuu.org.uk>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/uaccess.h>
#include <asm/sgi/mc.h>
#define PFX "indydog: "
static unsigned long indydog_alive;
static spinlock_t indydog_lock;
#define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
static int nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
static void indydog_start(void)
{
u32 mc_ctrl0;
spin_lock(&indydog_lock);
mc_ctrl0 = sgimc->cpuctrl0;
mc_ctrl0 = sgimc->cpuctrl0 | SGIMC_CCTRL0_WDOG;
sgimc->cpuctrl0 = mc_ctrl0;
spin_unlock(&indydog_lock);
}
static void indydog_stop(void)
{
u32 mc_ctrl0;
spin_lock(&indydog_lock);
mc_ctrl0 = sgimc->cpuctrl0;
mc_ctrl0 &= ~SGIMC_CCTRL0_WDOG;
sgimc->cpuctrl0 = mc_ctrl0;
spin_unlock(&indydog_lock);
printk(KERN_INFO PFX "Stopped watchdog timer.\n");
}
static void indydog_ping(void)
{
sgimc->watchdogt = 0;
}
/*
* Allow only one person to hold it open
*/
static int indydog_open(struct inode *inode, struct file *file)
{
if (test_and_set_bit(0, &indydog_alive))
return -EBUSY;
if (nowayout)
__module_get(THIS_MODULE);
/* Activate timer */
indydog_start();
indydog_ping();
printk(KERN_INFO "Started watchdog timer.\n");
return nonseekable_open(inode, file);
}
static int indydog_release(struct inode *inode, struct file *file)
{
/* Shut off the timer.
* Lock it in if it's a module and we defined ...NOWAYOUT */
if (!nowayout)
indydog_stop(); /* Turn the WDT off */
clear_bit(0, &indydog_alive);
return 0;
}
static ssize_t indydog_write(struct file *file, const char *data,
size_t len, loff_t *ppos)
{
/* Refresh the timer. */
if (len)
indydog_ping();
return len;
}
static long indydog_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
int options, retval = -EINVAL;
static const struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING,
.firmware_version = 0,
.identity = "Hardware Watchdog for SGI IP22",
};
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user((struct watchdog_info *)arg,
&ident, sizeof(ident)))
return -EFAULT;
return 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
return put_user(0, (int *)arg);
case WDIOC_SETOPTIONS:
{
if (get_user(options, (int *)arg))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
indydog_stop();
retval = 0;
}
if (options & WDIOS_ENABLECARD) {
indydog_start();
retval = 0;
}
return retval;
}
case WDIOC_KEEPALIVE:
indydog_ping();
return 0;
case WDIOC_GETTIMEOUT:
return put_user(WATCHDOG_TIMEOUT, (int *)arg);
default:
return -ENOTTY;
}
}
static int indydog_notify_sys(struct notifier_block *this,
unsigned long code, void *unused)
{
if (code == SYS_DOWN || code == SYS_HALT)
indydog_stop(); /* Turn the WDT off */
return NOTIFY_DONE;
}
static const struct file_operations indydog_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.write = indydog_write,
.unlocked_ioctl = indydog_ioctl,
.open = indydog_open,
.release = indydog_release,
};
static struct miscdevice indydog_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &indydog_fops,
};
static struct notifier_block indydog_notifier = {
.notifier_call = indydog_notify_sys,
};
static char banner[] __initdata =
KERN_INFO PFX "Hardware Watchdog Timer for SGI IP22: 0.3\n";
static int __init watchdog_init(void)
{
int ret;
spin_lock_init(&indydog_lock);
ret = register_reboot_notifier(&indydog_notifier);
if (ret) {
printk(KERN_ERR PFX
"cannot register reboot notifier (err=%d)\n", ret);
return ret;
}
ret = misc_register(&indydog_miscdev);
if (ret) {
printk(KERN_ERR PFX
"cannot register miscdev on minor=%d (err=%d)\n",
WATCHDOG_MINOR, ret);
unregister_reboot_notifier(&indydog_notifier);
return ret;
}
printk(banner);
return 0;
}
static void __exit watchdog_exit(void)
{
misc_deregister(&indydog_miscdev);
unregister_reboot_notifier(&indydog_notifier);
}
module_init(watchdog_init);
module_exit(watchdog_exit);
MODULE_AUTHOR("Guido Guenther <agx@sigxcpu.org>");
MODULE_DESCRIPTION("Hardware Watchdog Device for SGI IP22");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
| gpl-2.0 |
zhaochengw/android_kernel_nx403 | fs/hfsplus/catalog.c | 4963 | 11270 | /*
* linux/fs/hfsplus/catalog.c
*
* Copyright (C) 2001
* Brad Boyer (flar@allandria.com)
* (C) 2003 Ardis Technologies <roman@ardistech.com>
*
* Handling of catalog records
*/
#include "hfsplus_fs.h"
#include "hfsplus_raw.h"
int hfsplus_cat_case_cmp_key(const hfsplus_btree_key *k1,
const hfsplus_btree_key *k2)
{
__be32 k1p, k2p;
k1p = k1->cat.parent;
k2p = k2->cat.parent;
if (k1p != k2p)
return be32_to_cpu(k1p) < be32_to_cpu(k2p) ? -1 : 1;
return hfsplus_strcasecmp(&k1->cat.name, &k2->cat.name);
}
int hfsplus_cat_bin_cmp_key(const hfsplus_btree_key *k1,
const hfsplus_btree_key *k2)
{
__be32 k1p, k2p;
k1p = k1->cat.parent;
k2p = k2->cat.parent;
if (k1p != k2p)
return be32_to_cpu(k1p) < be32_to_cpu(k2p) ? -1 : 1;
return hfsplus_strcmp(&k1->cat.name, &k2->cat.name);
}
void hfsplus_cat_build_key(struct super_block *sb, hfsplus_btree_key *key,
u32 parent, struct qstr *str)
{
int len;
key->cat.parent = cpu_to_be32(parent);
if (str) {
hfsplus_asc2uni(sb, &key->cat.name, str->name, str->len);
len = be16_to_cpu(key->cat.name.length);
} else {
key->cat.name.length = 0;
len = 0;
}
key->key_len = cpu_to_be16(6 + 2 * len);
}
static void hfsplus_cat_build_key_uni(hfsplus_btree_key *key, u32 parent,
struct hfsplus_unistr *name)
{
int ustrlen;
ustrlen = be16_to_cpu(name->length);
key->cat.parent = cpu_to_be32(parent);
key->cat.name.length = cpu_to_be16(ustrlen);
ustrlen *= 2;
memcpy(key->cat.name.unicode, name->unicode, ustrlen);
key->key_len = cpu_to_be16(6 + ustrlen);
}
void hfsplus_cat_set_perms(struct inode *inode, struct hfsplus_perm *perms)
{
if (inode->i_flags & S_IMMUTABLE)
perms->rootflags |= HFSPLUS_FLG_IMMUTABLE;
else
perms->rootflags &= ~HFSPLUS_FLG_IMMUTABLE;
if (inode->i_flags & S_APPEND)
perms->rootflags |= HFSPLUS_FLG_APPEND;
else
perms->rootflags &= ~HFSPLUS_FLG_APPEND;
perms->userflags = HFSPLUS_I(inode)->userflags;
perms->mode = cpu_to_be16(inode->i_mode);
perms->owner = cpu_to_be32(inode->i_uid);
perms->group = cpu_to_be32(inode->i_gid);
if (S_ISREG(inode->i_mode))
perms->dev = cpu_to_be32(inode->i_nlink);
else if (S_ISBLK(inode->i_mode) || S_ISCHR(inode->i_mode))
perms->dev = cpu_to_be32(inode->i_rdev);
else
perms->dev = 0;
}
static int hfsplus_cat_build_record(hfsplus_cat_entry *entry,
u32 cnid, struct inode *inode)
{
struct hfsplus_sb_info *sbi = HFSPLUS_SB(inode->i_sb);
if (S_ISDIR(inode->i_mode)) {
struct hfsplus_cat_folder *folder;
folder = &entry->folder;
memset(folder, 0, sizeof(*folder));
folder->type = cpu_to_be16(HFSPLUS_FOLDER);
folder->id = cpu_to_be32(inode->i_ino);
HFSPLUS_I(inode)->create_date =
folder->create_date =
folder->content_mod_date =
folder->attribute_mod_date =
folder->access_date = hfsp_now2mt();
hfsplus_cat_set_perms(inode, &folder->permissions);
if (inode == sbi->hidden_dir)
/* invisible and namelocked */
folder->user_info.frFlags = cpu_to_be16(0x5000);
return sizeof(*folder);
} else {
struct hfsplus_cat_file *file;
file = &entry->file;
memset(file, 0, sizeof(*file));
file->type = cpu_to_be16(HFSPLUS_FILE);
file->flags = cpu_to_be16(HFSPLUS_FILE_THREAD_EXISTS);
file->id = cpu_to_be32(cnid);
HFSPLUS_I(inode)->create_date =
file->create_date =
file->content_mod_date =
file->attribute_mod_date =
file->access_date = hfsp_now2mt();
if (cnid == inode->i_ino) {
hfsplus_cat_set_perms(inode, &file->permissions);
if (S_ISLNK(inode->i_mode)) {
file->user_info.fdType =
cpu_to_be32(HFSP_SYMLINK_TYPE);
file->user_info.fdCreator =
cpu_to_be32(HFSP_SYMLINK_CREATOR);
} else {
file->user_info.fdType =
cpu_to_be32(sbi->type);
file->user_info.fdCreator =
cpu_to_be32(sbi->creator);
}
if (HFSPLUS_FLG_IMMUTABLE &
(file->permissions.rootflags |
file->permissions.userflags))
file->flags |=
cpu_to_be16(HFSPLUS_FILE_LOCKED);
} else {
file->user_info.fdType =
cpu_to_be32(HFSP_HARDLINK_TYPE);
file->user_info.fdCreator =
cpu_to_be32(HFSP_HFSPLUS_CREATOR);
file->user_info.fdFlags =
cpu_to_be16(0x100);
file->create_date =
HFSPLUS_I(sbi->hidden_dir)->create_date;
file->permissions.dev =
cpu_to_be32(HFSPLUS_I(inode)->linkid);
}
return sizeof(*file);
}
}
static int hfsplus_fill_cat_thread(struct super_block *sb,
hfsplus_cat_entry *entry, int type,
u32 parentid, struct qstr *str)
{
entry->type = cpu_to_be16(type);
entry->thread.reserved = 0;
entry->thread.parentID = cpu_to_be32(parentid);
hfsplus_asc2uni(sb, &entry->thread.nodeName, str->name, str->len);
return 10 + be16_to_cpu(entry->thread.nodeName.length) * 2;
}
/* Try to get a catalog entry for given catalog id */
int hfsplus_find_cat(struct super_block *sb, u32 cnid,
struct hfs_find_data *fd)
{
hfsplus_cat_entry tmp;
int err;
u16 type;
hfsplus_cat_build_key(sb, fd->search_key, cnid, NULL);
err = hfs_brec_read(fd, &tmp, sizeof(hfsplus_cat_entry));
if (err)
return err;
type = be16_to_cpu(tmp.type);
if (type != HFSPLUS_FOLDER_THREAD && type != HFSPLUS_FILE_THREAD) {
printk(KERN_ERR "hfs: found bad thread record in catalog\n");
return -EIO;
}
if (be16_to_cpu(tmp.thread.nodeName.length) > 255) {
printk(KERN_ERR "hfs: catalog name length corrupted\n");
return -EIO;
}
hfsplus_cat_build_key_uni(fd->search_key,
be32_to_cpu(tmp.thread.parentID),
&tmp.thread.nodeName);
return hfs_brec_find(fd);
}
int hfsplus_create_cat(u32 cnid, struct inode *dir,
struct qstr *str, struct inode *inode)
{
struct super_block *sb = dir->i_sb;
struct hfs_find_data fd;
hfsplus_cat_entry entry;
int entry_size;
int err;
dprint(DBG_CAT_MOD, "create_cat: %s,%u(%d)\n",
str->name, cnid, inode->i_nlink);
err = hfs_find_init(HFSPLUS_SB(sb)->cat_tree, &fd);
if (err)
return err;
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
entry_size = hfsplus_fill_cat_thread(sb, &entry,
S_ISDIR(inode->i_mode) ?
HFSPLUS_FOLDER_THREAD : HFSPLUS_FILE_THREAD,
dir->i_ino, str);
err = hfs_brec_find(&fd);
if (err != -ENOENT) {
if (!err)
err = -EEXIST;
goto err2;
}
err = hfs_brec_insert(&fd, &entry, entry_size);
if (err)
goto err2;
hfsplus_cat_build_key(sb, fd.search_key, dir->i_ino, str);
entry_size = hfsplus_cat_build_record(&entry, cnid, inode);
err = hfs_brec_find(&fd);
if (err != -ENOENT) {
/* panic? */
if (!err)
err = -EEXIST;
goto err1;
}
err = hfs_brec_insert(&fd, &entry, entry_size);
if (err)
goto err1;
dir->i_size++;
dir->i_mtime = dir->i_ctime = CURRENT_TIME_SEC;
hfsplus_mark_inode_dirty(dir, HFSPLUS_I_CAT_DIRTY);
hfs_find_exit(&fd);
return 0;
err1:
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
if (!hfs_brec_find(&fd))
hfs_brec_remove(&fd);
err2:
hfs_find_exit(&fd);
return err;
}
int hfsplus_delete_cat(u32 cnid, struct inode *dir, struct qstr *str)
{
struct super_block *sb = dir->i_sb;
struct hfs_find_data fd;
struct hfsplus_fork_raw fork;
struct list_head *pos;
int err, off;
u16 type;
dprint(DBG_CAT_MOD, "delete_cat: %s,%u\n",
str ? str->name : NULL, cnid);
err = hfs_find_init(HFSPLUS_SB(sb)->cat_tree, &fd);
if (err)
return err;
if (!str) {
int len;
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
err = hfs_brec_find(&fd);
if (err)
goto out;
off = fd.entryoffset +
offsetof(struct hfsplus_cat_thread, nodeName);
fd.search_key->cat.parent = cpu_to_be32(dir->i_ino);
hfs_bnode_read(fd.bnode,
&fd.search_key->cat.name.length, off, 2);
len = be16_to_cpu(fd.search_key->cat.name.length) * 2;
hfs_bnode_read(fd.bnode,
&fd.search_key->cat.name.unicode,
off + 2, len);
fd.search_key->key_len = cpu_to_be16(6 + len);
} else
hfsplus_cat_build_key(sb, fd.search_key, dir->i_ino, str);
err = hfs_brec_find(&fd);
if (err)
goto out;
type = hfs_bnode_read_u16(fd.bnode, fd.entryoffset);
if (type == HFSPLUS_FILE) {
#if 0
off = fd.entryoffset + offsetof(hfsplus_cat_file, data_fork);
hfs_bnode_read(fd.bnode, &fork, off, sizeof(fork));
hfsplus_free_fork(sb, cnid, &fork, HFSPLUS_TYPE_DATA);
#endif
off = fd.entryoffset +
offsetof(struct hfsplus_cat_file, rsrc_fork);
hfs_bnode_read(fd.bnode, &fork, off, sizeof(fork));
hfsplus_free_fork(sb, cnid, &fork, HFSPLUS_TYPE_RSRC);
}
list_for_each(pos, &HFSPLUS_I(dir)->open_dir_list) {
struct hfsplus_readdir_data *rd =
list_entry(pos, struct hfsplus_readdir_data, list);
if (fd.tree->keycmp(fd.search_key, (void *)&rd->key) < 0)
rd->file->f_pos--;
}
err = hfs_brec_remove(&fd);
if (err)
goto out;
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
err = hfs_brec_find(&fd);
if (err)
goto out;
err = hfs_brec_remove(&fd);
if (err)
goto out;
dir->i_size--;
dir->i_mtime = dir->i_ctime = CURRENT_TIME_SEC;
hfsplus_mark_inode_dirty(dir, HFSPLUS_I_CAT_DIRTY);
out:
hfs_find_exit(&fd);
return err;
}
int hfsplus_rename_cat(u32 cnid,
struct inode *src_dir, struct qstr *src_name,
struct inode *dst_dir, struct qstr *dst_name)
{
struct super_block *sb = src_dir->i_sb;
struct hfs_find_data src_fd, dst_fd;
hfsplus_cat_entry entry;
int entry_size, type;
int err;
dprint(DBG_CAT_MOD, "rename_cat: %u - %lu,%s - %lu,%s\n",
cnid, src_dir->i_ino, src_name->name,
dst_dir->i_ino, dst_name->name);
err = hfs_find_init(HFSPLUS_SB(sb)->cat_tree, &src_fd);
if (err)
return err;
dst_fd = src_fd;
/* find the old dir entry and read the data */
hfsplus_cat_build_key(sb, src_fd.search_key, src_dir->i_ino, src_name);
err = hfs_brec_find(&src_fd);
if (err)
goto out;
if (src_fd.entrylength > sizeof(entry) || src_fd.entrylength < 0) {
err = -EIO;
goto out;
}
hfs_bnode_read(src_fd.bnode, &entry, src_fd.entryoffset,
src_fd.entrylength);
/* create new dir entry with the data from the old entry */
hfsplus_cat_build_key(sb, dst_fd.search_key, dst_dir->i_ino, dst_name);
err = hfs_brec_find(&dst_fd);
if (err != -ENOENT) {
if (!err)
err = -EEXIST;
goto out;
}
err = hfs_brec_insert(&dst_fd, &entry, src_fd.entrylength);
if (err)
goto out;
dst_dir->i_size++;
dst_dir->i_mtime = dst_dir->i_ctime = CURRENT_TIME_SEC;
/* finally remove the old entry */
hfsplus_cat_build_key(sb, src_fd.search_key, src_dir->i_ino, src_name);
err = hfs_brec_find(&src_fd);
if (err)
goto out;
err = hfs_brec_remove(&src_fd);
if (err)
goto out;
src_dir->i_size--;
src_dir->i_mtime = src_dir->i_ctime = CURRENT_TIME_SEC;
/* remove old thread entry */
hfsplus_cat_build_key(sb, src_fd.search_key, cnid, NULL);
err = hfs_brec_find(&src_fd);
if (err)
goto out;
type = hfs_bnode_read_u16(src_fd.bnode, src_fd.entryoffset);
err = hfs_brec_remove(&src_fd);
if (err)
goto out;
/* create new thread entry */
hfsplus_cat_build_key(sb, dst_fd.search_key, cnid, NULL);
entry_size = hfsplus_fill_cat_thread(sb, &entry, type,
dst_dir->i_ino, dst_name);
err = hfs_brec_find(&dst_fd);
if (err != -ENOENT) {
if (!err)
err = -EEXIST;
goto out;
}
err = hfs_brec_insert(&dst_fd, &entry, entry_size);
hfsplus_mark_inode_dirty(dst_dir, HFSPLUS_I_CAT_DIRTY);
hfsplus_mark_inode_dirty(src_dir, HFSPLUS_I_CAT_DIRTY);
out:
hfs_bnode_put(dst_fd.bnode);
hfs_find_exit(&src_fd);
return err;
}
| gpl-2.0 |
PRJosh/kernel_msm | fs/hfsplus/catalog.c | 4963 | 11270 | /*
* linux/fs/hfsplus/catalog.c
*
* Copyright (C) 2001
* Brad Boyer (flar@allandria.com)
* (C) 2003 Ardis Technologies <roman@ardistech.com>
*
* Handling of catalog records
*/
#include "hfsplus_fs.h"
#include "hfsplus_raw.h"
int hfsplus_cat_case_cmp_key(const hfsplus_btree_key *k1,
const hfsplus_btree_key *k2)
{
__be32 k1p, k2p;
k1p = k1->cat.parent;
k2p = k2->cat.parent;
if (k1p != k2p)
return be32_to_cpu(k1p) < be32_to_cpu(k2p) ? -1 : 1;
return hfsplus_strcasecmp(&k1->cat.name, &k2->cat.name);
}
int hfsplus_cat_bin_cmp_key(const hfsplus_btree_key *k1,
const hfsplus_btree_key *k2)
{
__be32 k1p, k2p;
k1p = k1->cat.parent;
k2p = k2->cat.parent;
if (k1p != k2p)
return be32_to_cpu(k1p) < be32_to_cpu(k2p) ? -1 : 1;
return hfsplus_strcmp(&k1->cat.name, &k2->cat.name);
}
void hfsplus_cat_build_key(struct super_block *sb, hfsplus_btree_key *key,
u32 parent, struct qstr *str)
{
int len;
key->cat.parent = cpu_to_be32(parent);
if (str) {
hfsplus_asc2uni(sb, &key->cat.name, str->name, str->len);
len = be16_to_cpu(key->cat.name.length);
} else {
key->cat.name.length = 0;
len = 0;
}
key->key_len = cpu_to_be16(6 + 2 * len);
}
static void hfsplus_cat_build_key_uni(hfsplus_btree_key *key, u32 parent,
struct hfsplus_unistr *name)
{
int ustrlen;
ustrlen = be16_to_cpu(name->length);
key->cat.parent = cpu_to_be32(parent);
key->cat.name.length = cpu_to_be16(ustrlen);
ustrlen *= 2;
memcpy(key->cat.name.unicode, name->unicode, ustrlen);
key->key_len = cpu_to_be16(6 + ustrlen);
}
void hfsplus_cat_set_perms(struct inode *inode, struct hfsplus_perm *perms)
{
if (inode->i_flags & S_IMMUTABLE)
perms->rootflags |= HFSPLUS_FLG_IMMUTABLE;
else
perms->rootflags &= ~HFSPLUS_FLG_IMMUTABLE;
if (inode->i_flags & S_APPEND)
perms->rootflags |= HFSPLUS_FLG_APPEND;
else
perms->rootflags &= ~HFSPLUS_FLG_APPEND;
perms->userflags = HFSPLUS_I(inode)->userflags;
perms->mode = cpu_to_be16(inode->i_mode);
perms->owner = cpu_to_be32(inode->i_uid);
perms->group = cpu_to_be32(inode->i_gid);
if (S_ISREG(inode->i_mode))
perms->dev = cpu_to_be32(inode->i_nlink);
else if (S_ISBLK(inode->i_mode) || S_ISCHR(inode->i_mode))
perms->dev = cpu_to_be32(inode->i_rdev);
else
perms->dev = 0;
}
static int hfsplus_cat_build_record(hfsplus_cat_entry *entry,
u32 cnid, struct inode *inode)
{
struct hfsplus_sb_info *sbi = HFSPLUS_SB(inode->i_sb);
if (S_ISDIR(inode->i_mode)) {
struct hfsplus_cat_folder *folder;
folder = &entry->folder;
memset(folder, 0, sizeof(*folder));
folder->type = cpu_to_be16(HFSPLUS_FOLDER);
folder->id = cpu_to_be32(inode->i_ino);
HFSPLUS_I(inode)->create_date =
folder->create_date =
folder->content_mod_date =
folder->attribute_mod_date =
folder->access_date = hfsp_now2mt();
hfsplus_cat_set_perms(inode, &folder->permissions);
if (inode == sbi->hidden_dir)
/* invisible and namelocked */
folder->user_info.frFlags = cpu_to_be16(0x5000);
return sizeof(*folder);
} else {
struct hfsplus_cat_file *file;
file = &entry->file;
memset(file, 0, sizeof(*file));
file->type = cpu_to_be16(HFSPLUS_FILE);
file->flags = cpu_to_be16(HFSPLUS_FILE_THREAD_EXISTS);
file->id = cpu_to_be32(cnid);
HFSPLUS_I(inode)->create_date =
file->create_date =
file->content_mod_date =
file->attribute_mod_date =
file->access_date = hfsp_now2mt();
if (cnid == inode->i_ino) {
hfsplus_cat_set_perms(inode, &file->permissions);
if (S_ISLNK(inode->i_mode)) {
file->user_info.fdType =
cpu_to_be32(HFSP_SYMLINK_TYPE);
file->user_info.fdCreator =
cpu_to_be32(HFSP_SYMLINK_CREATOR);
} else {
file->user_info.fdType =
cpu_to_be32(sbi->type);
file->user_info.fdCreator =
cpu_to_be32(sbi->creator);
}
if (HFSPLUS_FLG_IMMUTABLE &
(file->permissions.rootflags |
file->permissions.userflags))
file->flags |=
cpu_to_be16(HFSPLUS_FILE_LOCKED);
} else {
file->user_info.fdType =
cpu_to_be32(HFSP_HARDLINK_TYPE);
file->user_info.fdCreator =
cpu_to_be32(HFSP_HFSPLUS_CREATOR);
file->user_info.fdFlags =
cpu_to_be16(0x100);
file->create_date =
HFSPLUS_I(sbi->hidden_dir)->create_date;
file->permissions.dev =
cpu_to_be32(HFSPLUS_I(inode)->linkid);
}
return sizeof(*file);
}
}
static int hfsplus_fill_cat_thread(struct super_block *sb,
hfsplus_cat_entry *entry, int type,
u32 parentid, struct qstr *str)
{
entry->type = cpu_to_be16(type);
entry->thread.reserved = 0;
entry->thread.parentID = cpu_to_be32(parentid);
hfsplus_asc2uni(sb, &entry->thread.nodeName, str->name, str->len);
return 10 + be16_to_cpu(entry->thread.nodeName.length) * 2;
}
/* Try to get a catalog entry for given catalog id */
int hfsplus_find_cat(struct super_block *sb, u32 cnid,
struct hfs_find_data *fd)
{
hfsplus_cat_entry tmp;
int err;
u16 type;
hfsplus_cat_build_key(sb, fd->search_key, cnid, NULL);
err = hfs_brec_read(fd, &tmp, sizeof(hfsplus_cat_entry));
if (err)
return err;
type = be16_to_cpu(tmp.type);
if (type != HFSPLUS_FOLDER_THREAD && type != HFSPLUS_FILE_THREAD) {
printk(KERN_ERR "hfs: found bad thread record in catalog\n");
return -EIO;
}
if (be16_to_cpu(tmp.thread.nodeName.length) > 255) {
printk(KERN_ERR "hfs: catalog name length corrupted\n");
return -EIO;
}
hfsplus_cat_build_key_uni(fd->search_key,
be32_to_cpu(tmp.thread.parentID),
&tmp.thread.nodeName);
return hfs_brec_find(fd);
}
int hfsplus_create_cat(u32 cnid, struct inode *dir,
struct qstr *str, struct inode *inode)
{
struct super_block *sb = dir->i_sb;
struct hfs_find_data fd;
hfsplus_cat_entry entry;
int entry_size;
int err;
dprint(DBG_CAT_MOD, "create_cat: %s,%u(%d)\n",
str->name, cnid, inode->i_nlink);
err = hfs_find_init(HFSPLUS_SB(sb)->cat_tree, &fd);
if (err)
return err;
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
entry_size = hfsplus_fill_cat_thread(sb, &entry,
S_ISDIR(inode->i_mode) ?
HFSPLUS_FOLDER_THREAD : HFSPLUS_FILE_THREAD,
dir->i_ino, str);
err = hfs_brec_find(&fd);
if (err != -ENOENT) {
if (!err)
err = -EEXIST;
goto err2;
}
err = hfs_brec_insert(&fd, &entry, entry_size);
if (err)
goto err2;
hfsplus_cat_build_key(sb, fd.search_key, dir->i_ino, str);
entry_size = hfsplus_cat_build_record(&entry, cnid, inode);
err = hfs_brec_find(&fd);
if (err != -ENOENT) {
/* panic? */
if (!err)
err = -EEXIST;
goto err1;
}
err = hfs_brec_insert(&fd, &entry, entry_size);
if (err)
goto err1;
dir->i_size++;
dir->i_mtime = dir->i_ctime = CURRENT_TIME_SEC;
hfsplus_mark_inode_dirty(dir, HFSPLUS_I_CAT_DIRTY);
hfs_find_exit(&fd);
return 0;
err1:
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
if (!hfs_brec_find(&fd))
hfs_brec_remove(&fd);
err2:
hfs_find_exit(&fd);
return err;
}
int hfsplus_delete_cat(u32 cnid, struct inode *dir, struct qstr *str)
{
struct super_block *sb = dir->i_sb;
struct hfs_find_data fd;
struct hfsplus_fork_raw fork;
struct list_head *pos;
int err, off;
u16 type;
dprint(DBG_CAT_MOD, "delete_cat: %s,%u\n",
str ? str->name : NULL, cnid);
err = hfs_find_init(HFSPLUS_SB(sb)->cat_tree, &fd);
if (err)
return err;
if (!str) {
int len;
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
err = hfs_brec_find(&fd);
if (err)
goto out;
off = fd.entryoffset +
offsetof(struct hfsplus_cat_thread, nodeName);
fd.search_key->cat.parent = cpu_to_be32(dir->i_ino);
hfs_bnode_read(fd.bnode,
&fd.search_key->cat.name.length, off, 2);
len = be16_to_cpu(fd.search_key->cat.name.length) * 2;
hfs_bnode_read(fd.bnode,
&fd.search_key->cat.name.unicode,
off + 2, len);
fd.search_key->key_len = cpu_to_be16(6 + len);
} else
hfsplus_cat_build_key(sb, fd.search_key, dir->i_ino, str);
err = hfs_brec_find(&fd);
if (err)
goto out;
type = hfs_bnode_read_u16(fd.bnode, fd.entryoffset);
if (type == HFSPLUS_FILE) {
#if 0
off = fd.entryoffset + offsetof(hfsplus_cat_file, data_fork);
hfs_bnode_read(fd.bnode, &fork, off, sizeof(fork));
hfsplus_free_fork(sb, cnid, &fork, HFSPLUS_TYPE_DATA);
#endif
off = fd.entryoffset +
offsetof(struct hfsplus_cat_file, rsrc_fork);
hfs_bnode_read(fd.bnode, &fork, off, sizeof(fork));
hfsplus_free_fork(sb, cnid, &fork, HFSPLUS_TYPE_RSRC);
}
list_for_each(pos, &HFSPLUS_I(dir)->open_dir_list) {
struct hfsplus_readdir_data *rd =
list_entry(pos, struct hfsplus_readdir_data, list);
if (fd.tree->keycmp(fd.search_key, (void *)&rd->key) < 0)
rd->file->f_pos--;
}
err = hfs_brec_remove(&fd);
if (err)
goto out;
hfsplus_cat_build_key(sb, fd.search_key, cnid, NULL);
err = hfs_brec_find(&fd);
if (err)
goto out;
err = hfs_brec_remove(&fd);
if (err)
goto out;
dir->i_size--;
dir->i_mtime = dir->i_ctime = CURRENT_TIME_SEC;
hfsplus_mark_inode_dirty(dir, HFSPLUS_I_CAT_DIRTY);
out:
hfs_find_exit(&fd);
return err;
}
int hfsplus_rename_cat(u32 cnid,
struct inode *src_dir, struct qstr *src_name,
struct inode *dst_dir, struct qstr *dst_name)
{
struct super_block *sb = src_dir->i_sb;
struct hfs_find_data src_fd, dst_fd;
hfsplus_cat_entry entry;
int entry_size, type;
int err;
dprint(DBG_CAT_MOD, "rename_cat: %u - %lu,%s - %lu,%s\n",
cnid, src_dir->i_ino, src_name->name,
dst_dir->i_ino, dst_name->name);
err = hfs_find_init(HFSPLUS_SB(sb)->cat_tree, &src_fd);
if (err)
return err;
dst_fd = src_fd;
/* find the old dir entry and read the data */
hfsplus_cat_build_key(sb, src_fd.search_key, src_dir->i_ino, src_name);
err = hfs_brec_find(&src_fd);
if (err)
goto out;
if (src_fd.entrylength > sizeof(entry) || src_fd.entrylength < 0) {
err = -EIO;
goto out;
}
hfs_bnode_read(src_fd.bnode, &entry, src_fd.entryoffset,
src_fd.entrylength);
/* create new dir entry with the data from the old entry */
hfsplus_cat_build_key(sb, dst_fd.search_key, dst_dir->i_ino, dst_name);
err = hfs_brec_find(&dst_fd);
if (err != -ENOENT) {
if (!err)
err = -EEXIST;
goto out;
}
err = hfs_brec_insert(&dst_fd, &entry, src_fd.entrylength);
if (err)
goto out;
dst_dir->i_size++;
dst_dir->i_mtime = dst_dir->i_ctime = CURRENT_TIME_SEC;
/* finally remove the old entry */
hfsplus_cat_build_key(sb, src_fd.search_key, src_dir->i_ino, src_name);
err = hfs_brec_find(&src_fd);
if (err)
goto out;
err = hfs_brec_remove(&src_fd);
if (err)
goto out;
src_dir->i_size--;
src_dir->i_mtime = src_dir->i_ctime = CURRENT_TIME_SEC;
/* remove old thread entry */
hfsplus_cat_build_key(sb, src_fd.search_key, cnid, NULL);
err = hfs_brec_find(&src_fd);
if (err)
goto out;
type = hfs_bnode_read_u16(src_fd.bnode, src_fd.entryoffset);
err = hfs_brec_remove(&src_fd);
if (err)
goto out;
/* create new thread entry */
hfsplus_cat_build_key(sb, dst_fd.search_key, cnid, NULL);
entry_size = hfsplus_fill_cat_thread(sb, &entry, type,
dst_dir->i_ino, dst_name);
err = hfs_brec_find(&dst_fd);
if (err != -ENOENT) {
if (!err)
err = -EEXIST;
goto out;
}
err = hfs_brec_insert(&dst_fd, &entry, entry_size);
hfsplus_mark_inode_dirty(dst_dir, HFSPLUS_I_CAT_DIRTY);
hfsplus_mark_inode_dirty(src_dir, HFSPLUS_I_CAT_DIRTY);
out:
hfs_bnode_put(dst_fd.bnode);
hfs_find_exit(&src_fd);
return err;
}
| gpl-2.0 |
Split-Screen/android_kernel_motorola_msm8939 | sound/pci/ctxfi/ctdaio.c | 8035 | 17649 | /**
* Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
*
* This source file is released under GPL v2 license (no other versions).
* See the COPYING file included in the main directory of this source
* distribution for the license terms and conditions.
*
* @File ctdaio.c
*
* @Brief
* This file contains the implementation of Digital Audio Input Output
* resource management object.
*
* @Author Liu Chun
* @Date May 23 2008
*
*/
#include "ctdaio.h"
#include "cthardware.h"
#include "ctimap.h"
#include <linux/slab.h>
#include <linux/kernel.h>
#define DAIO_OUT_MAX SPDIFOO
struct daio_usage {
unsigned short data;
};
struct daio_rsc_idx {
unsigned short left;
unsigned short right;
};
struct daio_rsc_idx idx_20k1[NUM_DAIOTYP] = {
[LINEO1] = {.left = 0x00, .right = 0x01},
[LINEO2] = {.left = 0x18, .right = 0x19},
[LINEO3] = {.left = 0x08, .right = 0x09},
[LINEO4] = {.left = 0x10, .right = 0x11},
[LINEIM] = {.left = 0x1b5, .right = 0x1bd},
[SPDIFOO] = {.left = 0x20, .right = 0x21},
[SPDIFIO] = {.left = 0x15, .right = 0x1d},
[SPDIFI1] = {.left = 0x95, .right = 0x9d},
};
struct daio_rsc_idx idx_20k2[NUM_DAIOTYP] = {
[LINEO1] = {.left = 0x40, .right = 0x41},
[LINEO2] = {.left = 0x60, .right = 0x61},
[LINEO3] = {.left = 0x50, .right = 0x51},
[LINEO4] = {.left = 0x70, .right = 0x71},
[LINEIM] = {.left = 0x45, .right = 0xc5},
[MIC] = {.left = 0x55, .right = 0xd5},
[SPDIFOO] = {.left = 0x00, .right = 0x01},
[SPDIFIO] = {.left = 0x05, .right = 0x85},
};
static int daio_master(struct rsc *rsc)
{
/* Actually, this is not the resource index of DAIO.
* For DAO, it is the input mapper index. And, for DAI,
* it is the output time-slot index. */
return rsc->conj = rsc->idx;
}
static int daio_index(const struct rsc *rsc)
{
return rsc->conj;
}
static int daio_out_next_conj(struct rsc *rsc)
{
return rsc->conj += 2;
}
static int daio_in_next_conj_20k1(struct rsc *rsc)
{
return rsc->conj += 0x200;
}
static int daio_in_next_conj_20k2(struct rsc *rsc)
{
return rsc->conj += 0x100;
}
static struct rsc_ops daio_out_rsc_ops = {
.master = daio_master,
.next_conj = daio_out_next_conj,
.index = daio_index,
.output_slot = NULL,
};
static struct rsc_ops daio_in_rsc_ops_20k1 = {
.master = daio_master,
.next_conj = daio_in_next_conj_20k1,
.index = NULL,
.output_slot = daio_index,
};
static struct rsc_ops daio_in_rsc_ops_20k2 = {
.master = daio_master,
.next_conj = daio_in_next_conj_20k2,
.index = NULL,
.output_slot = daio_index,
};
static unsigned int daio_device_index(enum DAIOTYP type, struct hw *hw)
{
switch (hw->chip_type) {
case ATC20K1:
switch (type) {
case SPDIFOO: return 0;
case SPDIFIO: return 0;
case SPDIFI1: return 1;
case LINEO1: return 4;
case LINEO2: return 7;
case LINEO3: return 5;
case LINEO4: return 6;
case LINEIM: return 7;
default: return -EINVAL;
}
case ATC20K2:
switch (type) {
case SPDIFOO: return 0;
case SPDIFIO: return 0;
case LINEO1: return 4;
case LINEO2: return 7;
case LINEO3: return 5;
case LINEO4: return 6;
case LINEIM: return 4;
case MIC: return 5;
default: return -EINVAL;
}
default:
return -EINVAL;
}
}
static int dao_rsc_reinit(struct dao *dao, const struct dao_desc *desc);
static int dao_spdif_get_spos(struct dao *dao, unsigned int *spos)
{
((struct hw *)dao->hw)->dao_get_spos(dao->ctrl_blk, spos);
return 0;
}
static int dao_spdif_set_spos(struct dao *dao, unsigned int spos)
{
((struct hw *)dao->hw)->dao_set_spos(dao->ctrl_blk, spos);
return 0;
}
static int dao_commit_write(struct dao *dao)
{
((struct hw *)dao->hw)->dao_commit_write(dao->hw,
daio_device_index(dao->daio.type, dao->hw), dao->ctrl_blk);
return 0;
}
static int dao_set_left_input(struct dao *dao, struct rsc *input)
{
struct imapper *entry;
struct daio *daio = &dao->daio;
int i;
entry = kzalloc((sizeof(*entry) * daio->rscl.msr), GFP_KERNEL);
if (!entry)
return -ENOMEM;
dao->ops->clear_left_input(dao);
/* Program master and conjugate resources */
input->ops->master(input);
daio->rscl.ops->master(&daio->rscl);
for (i = 0; i < daio->rscl.msr; i++, entry++) {
entry->slot = input->ops->output_slot(input);
entry->user = entry->addr = daio->rscl.ops->index(&daio->rscl);
dao->mgr->imap_add(dao->mgr, entry);
dao->imappers[i] = entry;
input->ops->next_conj(input);
daio->rscl.ops->next_conj(&daio->rscl);
}
input->ops->master(input);
daio->rscl.ops->master(&daio->rscl);
return 0;
}
static int dao_set_right_input(struct dao *dao, struct rsc *input)
{
struct imapper *entry;
struct daio *daio = &dao->daio;
int i;
entry = kzalloc((sizeof(*entry) * daio->rscr.msr), GFP_KERNEL);
if (!entry)
return -ENOMEM;
dao->ops->clear_right_input(dao);
/* Program master and conjugate resources */
input->ops->master(input);
daio->rscr.ops->master(&daio->rscr);
for (i = 0; i < daio->rscr.msr; i++, entry++) {
entry->slot = input->ops->output_slot(input);
entry->user = entry->addr = daio->rscr.ops->index(&daio->rscr);
dao->mgr->imap_add(dao->mgr, entry);
dao->imappers[daio->rscl.msr + i] = entry;
input->ops->next_conj(input);
daio->rscr.ops->next_conj(&daio->rscr);
}
input->ops->master(input);
daio->rscr.ops->master(&daio->rscr);
return 0;
}
static int dao_clear_left_input(struct dao *dao)
{
struct imapper *entry;
struct daio *daio = &dao->daio;
int i;
if (!dao->imappers[0])
return 0;
entry = dao->imappers[0];
dao->mgr->imap_delete(dao->mgr, entry);
/* Program conjugate resources */
for (i = 1; i < daio->rscl.msr; i++) {
entry = dao->imappers[i];
dao->mgr->imap_delete(dao->mgr, entry);
dao->imappers[i] = NULL;
}
kfree(dao->imappers[0]);
dao->imappers[0] = NULL;
return 0;
}
static int dao_clear_right_input(struct dao *dao)
{
struct imapper *entry;
struct daio *daio = &dao->daio;
int i;
if (!dao->imappers[daio->rscl.msr])
return 0;
entry = dao->imappers[daio->rscl.msr];
dao->mgr->imap_delete(dao->mgr, entry);
/* Program conjugate resources */
for (i = 1; i < daio->rscr.msr; i++) {
entry = dao->imappers[daio->rscl.msr + i];
dao->mgr->imap_delete(dao->mgr, entry);
dao->imappers[daio->rscl.msr + i] = NULL;
}
kfree(dao->imappers[daio->rscl.msr]);
dao->imappers[daio->rscl.msr] = NULL;
return 0;
}
static struct dao_rsc_ops dao_ops = {
.set_spos = dao_spdif_set_spos,
.commit_write = dao_commit_write,
.get_spos = dao_spdif_get_spos,
.reinit = dao_rsc_reinit,
.set_left_input = dao_set_left_input,
.set_right_input = dao_set_right_input,
.clear_left_input = dao_clear_left_input,
.clear_right_input = dao_clear_right_input,
};
static int dai_set_srt_srcl(struct dai *dai, struct rsc *src)
{
src->ops->master(src);
((struct hw *)dai->hw)->dai_srt_set_srcm(dai->ctrl_blk,
src->ops->index(src));
return 0;
}
static int dai_set_srt_srcr(struct dai *dai, struct rsc *src)
{
src->ops->master(src);
((struct hw *)dai->hw)->dai_srt_set_srco(dai->ctrl_blk,
src->ops->index(src));
return 0;
}
static int dai_set_srt_msr(struct dai *dai, unsigned int msr)
{
unsigned int rsr;
for (rsr = 0; msr > 1; msr >>= 1)
rsr++;
((struct hw *)dai->hw)->dai_srt_set_rsr(dai->ctrl_blk, rsr);
return 0;
}
static int dai_set_enb_src(struct dai *dai, unsigned int enb)
{
((struct hw *)dai->hw)->dai_srt_set_ec(dai->ctrl_blk, enb);
return 0;
}
static int dai_set_enb_srt(struct dai *dai, unsigned int enb)
{
((struct hw *)dai->hw)->dai_srt_set_et(dai->ctrl_blk, enb);
return 0;
}
static int dai_commit_write(struct dai *dai)
{
((struct hw *)dai->hw)->dai_commit_write(dai->hw,
daio_device_index(dai->daio.type, dai->hw), dai->ctrl_blk);
return 0;
}
static struct dai_rsc_ops dai_ops = {
.set_srt_srcl = dai_set_srt_srcl,
.set_srt_srcr = dai_set_srt_srcr,
.set_srt_msr = dai_set_srt_msr,
.set_enb_src = dai_set_enb_src,
.set_enb_srt = dai_set_enb_srt,
.commit_write = dai_commit_write,
};
static int daio_rsc_init(struct daio *daio,
const struct daio_desc *desc,
void *hw)
{
int err;
unsigned int idx_l, idx_r;
switch (((struct hw *)hw)->chip_type) {
case ATC20K1:
idx_l = idx_20k1[desc->type].left;
idx_r = idx_20k1[desc->type].right;
break;
case ATC20K2:
idx_l = idx_20k2[desc->type].left;
idx_r = idx_20k2[desc->type].right;
break;
default:
return -EINVAL;
}
err = rsc_init(&daio->rscl, idx_l, DAIO, desc->msr, hw);
if (err)
return err;
err = rsc_init(&daio->rscr, idx_r, DAIO, desc->msr, hw);
if (err)
goto error1;
/* Set daio->rscl/r->ops to daio specific ones */
if (desc->type <= DAIO_OUT_MAX) {
daio->rscl.ops = daio->rscr.ops = &daio_out_rsc_ops;
} else {
switch (((struct hw *)hw)->chip_type) {
case ATC20K1:
daio->rscl.ops = daio->rscr.ops = &daio_in_rsc_ops_20k1;
break;
case ATC20K2:
daio->rscl.ops = daio->rscr.ops = &daio_in_rsc_ops_20k2;
break;
default:
break;
}
}
daio->type = desc->type;
return 0;
error1:
rsc_uninit(&daio->rscl);
return err;
}
static int daio_rsc_uninit(struct daio *daio)
{
rsc_uninit(&daio->rscl);
rsc_uninit(&daio->rscr);
return 0;
}
static int dao_rsc_init(struct dao *dao,
const struct daio_desc *desc,
struct daio_mgr *mgr)
{
struct hw *hw = mgr->mgr.hw;
unsigned int conf;
int err;
err = daio_rsc_init(&dao->daio, desc, mgr->mgr.hw);
if (err)
return err;
dao->imappers = kzalloc(sizeof(void *)*desc->msr*2, GFP_KERNEL);
if (!dao->imappers) {
err = -ENOMEM;
goto error1;
}
dao->ops = &dao_ops;
dao->mgr = mgr;
dao->hw = hw;
err = hw->dao_get_ctrl_blk(&dao->ctrl_blk);
if (err)
goto error2;
hw->daio_mgr_dsb_dao(mgr->mgr.ctrl_blk,
daio_device_index(dao->daio.type, hw));
hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
conf = (desc->msr & 0x7) | (desc->passthru << 3);
hw->daio_mgr_dao_init(mgr->mgr.ctrl_blk,
daio_device_index(dao->daio.type, hw), conf);
hw->daio_mgr_enb_dao(mgr->mgr.ctrl_blk,
daio_device_index(dao->daio.type, hw));
hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
return 0;
error2:
kfree(dao->imappers);
dao->imappers = NULL;
error1:
daio_rsc_uninit(&dao->daio);
return err;
}
static int dao_rsc_uninit(struct dao *dao)
{
if (dao->imappers) {
if (dao->imappers[0])
dao_clear_left_input(dao);
if (dao->imappers[dao->daio.rscl.msr])
dao_clear_right_input(dao);
kfree(dao->imappers);
dao->imappers = NULL;
}
((struct hw *)dao->hw)->dao_put_ctrl_blk(dao->ctrl_blk);
dao->hw = dao->ctrl_blk = NULL;
daio_rsc_uninit(&dao->daio);
return 0;
}
static int dao_rsc_reinit(struct dao *dao, const struct dao_desc *desc)
{
struct daio_mgr *mgr = dao->mgr;
struct daio_desc dsc = {0};
dsc.type = dao->daio.type;
dsc.msr = desc->msr;
dsc.passthru = desc->passthru;
dao_rsc_uninit(dao);
return dao_rsc_init(dao, &dsc, mgr);
}
static int dai_rsc_init(struct dai *dai,
const struct daio_desc *desc,
struct daio_mgr *mgr)
{
int err;
struct hw *hw = mgr->mgr.hw;
unsigned int rsr, msr;
err = daio_rsc_init(&dai->daio, desc, mgr->mgr.hw);
if (err)
return err;
dai->ops = &dai_ops;
dai->hw = mgr->mgr.hw;
err = hw->dai_get_ctrl_blk(&dai->ctrl_blk);
if (err)
goto error1;
for (rsr = 0, msr = desc->msr; msr > 1; msr >>= 1)
rsr++;
hw->dai_srt_set_rsr(dai->ctrl_blk, rsr);
hw->dai_srt_set_drat(dai->ctrl_blk, 0);
/* default to disabling control of a SRC */
hw->dai_srt_set_ec(dai->ctrl_blk, 0);
hw->dai_srt_set_et(dai->ctrl_blk, 0); /* default to disabling SRT */
hw->dai_commit_write(hw,
daio_device_index(dai->daio.type, dai->hw), dai->ctrl_blk);
return 0;
error1:
daio_rsc_uninit(&dai->daio);
return err;
}
static int dai_rsc_uninit(struct dai *dai)
{
((struct hw *)dai->hw)->dai_put_ctrl_blk(dai->ctrl_blk);
dai->hw = dai->ctrl_blk = NULL;
daio_rsc_uninit(&dai->daio);
return 0;
}
static int daio_mgr_get_rsc(struct rsc_mgr *mgr, enum DAIOTYP type)
{
if (((struct daio_usage *)mgr->rscs)->data & (0x1 << type))
return -ENOENT;
((struct daio_usage *)mgr->rscs)->data |= (0x1 << type);
return 0;
}
static int daio_mgr_put_rsc(struct rsc_mgr *mgr, enum DAIOTYP type)
{
((struct daio_usage *)mgr->rscs)->data &= ~(0x1 << type);
return 0;
}
static int get_daio_rsc(struct daio_mgr *mgr,
const struct daio_desc *desc,
struct daio **rdaio)
{
int err;
struct dai *dai = NULL;
struct dao *dao = NULL;
unsigned long flags;
*rdaio = NULL;
/* Check whether there are sufficient daio resources to meet request. */
spin_lock_irqsave(&mgr->mgr_lock, flags);
err = daio_mgr_get_rsc(&mgr->mgr, desc->type);
spin_unlock_irqrestore(&mgr->mgr_lock, flags);
if (err) {
printk(KERN_ERR "Can't meet DAIO resource request!\n");
return err;
}
/* Allocate mem for daio resource */
if (desc->type <= DAIO_OUT_MAX) {
dao = kzalloc(sizeof(*dao), GFP_KERNEL);
if (!dao) {
err = -ENOMEM;
goto error;
}
err = dao_rsc_init(dao, desc, mgr);
if (err)
goto error;
*rdaio = &dao->daio;
} else {
dai = kzalloc(sizeof(*dai), GFP_KERNEL);
if (!dai) {
err = -ENOMEM;
goto error;
}
err = dai_rsc_init(dai, desc, mgr);
if (err)
goto error;
*rdaio = &dai->daio;
}
mgr->daio_enable(mgr, *rdaio);
mgr->commit_write(mgr);
return 0;
error:
if (dao)
kfree(dao);
else if (dai)
kfree(dai);
spin_lock_irqsave(&mgr->mgr_lock, flags);
daio_mgr_put_rsc(&mgr->mgr, desc->type);
spin_unlock_irqrestore(&mgr->mgr_lock, flags);
return err;
}
static int put_daio_rsc(struct daio_mgr *mgr, struct daio *daio)
{
unsigned long flags;
mgr->daio_disable(mgr, daio);
mgr->commit_write(mgr);
spin_lock_irqsave(&mgr->mgr_lock, flags);
daio_mgr_put_rsc(&mgr->mgr, daio->type);
spin_unlock_irqrestore(&mgr->mgr_lock, flags);
if (daio->type <= DAIO_OUT_MAX) {
dao_rsc_uninit(container_of(daio, struct dao, daio));
kfree(container_of(daio, struct dao, daio));
} else {
dai_rsc_uninit(container_of(daio, struct dai, daio));
kfree(container_of(daio, struct dai, daio));
}
return 0;
}
static int daio_mgr_enb_daio(struct daio_mgr *mgr, struct daio *daio)
{
struct hw *hw = mgr->mgr.hw;
if (DAIO_OUT_MAX >= daio->type) {
hw->daio_mgr_enb_dao(mgr->mgr.ctrl_blk,
daio_device_index(daio->type, hw));
} else {
hw->daio_mgr_enb_dai(mgr->mgr.ctrl_blk,
daio_device_index(daio->type, hw));
}
return 0;
}
static int daio_mgr_dsb_daio(struct daio_mgr *mgr, struct daio *daio)
{
struct hw *hw = mgr->mgr.hw;
if (DAIO_OUT_MAX >= daio->type) {
hw->daio_mgr_dsb_dao(mgr->mgr.ctrl_blk,
daio_device_index(daio->type, hw));
} else {
hw->daio_mgr_dsb_dai(mgr->mgr.ctrl_blk,
daio_device_index(daio->type, hw));
}
return 0;
}
static int daio_map_op(void *data, struct imapper *entry)
{
struct rsc_mgr *mgr = &((struct daio_mgr *)data)->mgr;
struct hw *hw = mgr->hw;
hw->daio_mgr_set_imaparc(mgr->ctrl_blk, entry->slot);
hw->daio_mgr_set_imapnxt(mgr->ctrl_blk, entry->next);
hw->daio_mgr_set_imapaddr(mgr->ctrl_blk, entry->addr);
hw->daio_mgr_commit_write(mgr->hw, mgr->ctrl_blk);
return 0;
}
static int daio_imap_add(struct daio_mgr *mgr, struct imapper *entry)
{
unsigned long flags;
int err;
spin_lock_irqsave(&mgr->imap_lock, flags);
if (!entry->addr && mgr->init_imap_added) {
input_mapper_delete(&mgr->imappers, mgr->init_imap,
daio_map_op, mgr);
mgr->init_imap_added = 0;
}
err = input_mapper_add(&mgr->imappers, entry, daio_map_op, mgr);
spin_unlock_irqrestore(&mgr->imap_lock, flags);
return err;
}
static int daio_imap_delete(struct daio_mgr *mgr, struct imapper *entry)
{
unsigned long flags;
int err;
spin_lock_irqsave(&mgr->imap_lock, flags);
err = input_mapper_delete(&mgr->imappers, entry, daio_map_op, mgr);
if (list_empty(&mgr->imappers)) {
input_mapper_add(&mgr->imappers, mgr->init_imap,
daio_map_op, mgr);
mgr->init_imap_added = 1;
}
spin_unlock_irqrestore(&mgr->imap_lock, flags);
return err;
}
static int daio_mgr_commit_write(struct daio_mgr *mgr)
{
struct hw *hw = mgr->mgr.hw;
hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
return 0;
}
int daio_mgr_create(void *hw, struct daio_mgr **rdaio_mgr)
{
int err, i;
struct daio_mgr *daio_mgr;
struct imapper *entry;
*rdaio_mgr = NULL;
daio_mgr = kzalloc(sizeof(*daio_mgr), GFP_KERNEL);
if (!daio_mgr)
return -ENOMEM;
err = rsc_mgr_init(&daio_mgr->mgr, DAIO, NUM_DAIOTYP, hw);
if (err)
goto error1;
spin_lock_init(&daio_mgr->mgr_lock);
spin_lock_init(&daio_mgr->imap_lock);
INIT_LIST_HEAD(&daio_mgr->imappers);
entry = kzalloc(sizeof(*entry), GFP_KERNEL);
if (!entry) {
err = -ENOMEM;
goto error2;
}
entry->slot = entry->addr = entry->next = entry->user = 0;
list_add(&entry->list, &daio_mgr->imappers);
daio_mgr->init_imap = entry;
daio_mgr->init_imap_added = 1;
daio_mgr->get_daio = get_daio_rsc;
daio_mgr->put_daio = put_daio_rsc;
daio_mgr->daio_enable = daio_mgr_enb_daio;
daio_mgr->daio_disable = daio_mgr_dsb_daio;
daio_mgr->imap_add = daio_imap_add;
daio_mgr->imap_delete = daio_imap_delete;
daio_mgr->commit_write = daio_mgr_commit_write;
for (i = 0; i < 8; i++) {
((struct hw *)hw)->daio_mgr_dsb_dao(daio_mgr->mgr.ctrl_blk, i);
((struct hw *)hw)->daio_mgr_dsb_dai(daio_mgr->mgr.ctrl_blk, i);
}
((struct hw *)hw)->daio_mgr_commit_write(hw, daio_mgr->mgr.ctrl_blk);
*rdaio_mgr = daio_mgr;
return 0;
error2:
rsc_mgr_uninit(&daio_mgr->mgr);
error1:
kfree(daio_mgr);
return err;
}
int daio_mgr_destroy(struct daio_mgr *daio_mgr)
{
unsigned long flags;
/* free daio input mapper list */
spin_lock_irqsave(&daio_mgr->imap_lock, flags);
free_input_mapper_list(&daio_mgr->imappers);
spin_unlock_irqrestore(&daio_mgr->imap_lock, flags);
rsc_mgr_uninit(&daio_mgr->mgr);
kfree(daio_mgr);
return 0;
}
| gpl-2.0 |
n-aizu/linux | drivers/media/pci/pt1/va1j5jf8007t.c | 8803 | 11580 | /*
* ISDB-T driver for VA1J5JF8007/VA1J5JF8011
*
* Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
*
* based on pt1dvr - http://pt1dvr.sourceforge.jp/
* by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include "dvb_frontend.h"
#include "dvb_math.h"
#include "va1j5jf8007t.h"
enum va1j5jf8007t_tune_state {
VA1J5JF8007T_IDLE,
VA1J5JF8007T_SET_FREQUENCY,
VA1J5JF8007T_CHECK_FREQUENCY,
VA1J5JF8007T_SET_MODULATION,
VA1J5JF8007T_CHECK_MODULATION,
VA1J5JF8007T_TRACK,
VA1J5JF8007T_ABORT,
};
struct va1j5jf8007t_state {
const struct va1j5jf8007t_config *config;
struct i2c_adapter *adap;
struct dvb_frontend fe;
enum va1j5jf8007t_tune_state tune_state;
};
static int va1j5jf8007t_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct va1j5jf8007t_state *state;
u8 addr;
int i;
u8 write_buf[1], read_buf[1];
struct i2c_msg msgs[2];
s32 word, x, y;
state = fe->demodulator_priv;
addr = state->config->demod_address;
word = 0;
for (i = 0; i < 3; i++) {
write_buf[0] = 0x8b + i;
msgs[0].addr = addr;
msgs[0].flags = 0;
msgs[0].len = sizeof(write_buf);
msgs[0].buf = write_buf;
msgs[1].addr = addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = sizeof(read_buf);
msgs[1].buf = read_buf;
if (i2c_transfer(state->adap, msgs, 2) != 2)
return -EREMOTEIO;
word <<= 8;
word |= read_buf[0];
}
if (!word)
return -EIO;
x = 10 * (intlog10(0x540000 * 100 / word) - (2 << 24));
y = (24ll << 46) / 1000000;
y = ((s64)y * x >> 30) - (16ll << 40) / 10000;
y = ((s64)y * x >> 29) + (398ll << 35) / 10000;
y = ((s64)y * x >> 30) + (5491ll << 29) / 10000;
y = ((s64)y * x >> 30) + (30965ll << 23) / 10000;
*snr = y >> 15;
return 0;
}
static int va1j5jf8007t_get_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
}
static int
va1j5jf8007t_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
struct va1j5jf8007t_state *state;
state = fe->demodulator_priv;
switch (state->tune_state) {
case VA1J5JF8007T_IDLE:
case VA1J5JF8007T_SET_FREQUENCY:
case VA1J5JF8007T_CHECK_FREQUENCY:
*status = 0;
return 0;
case VA1J5JF8007T_SET_MODULATION:
case VA1J5JF8007T_CHECK_MODULATION:
case VA1J5JF8007T_ABORT:
*status |= FE_HAS_SIGNAL;
return 0;
case VA1J5JF8007T_TRACK:
*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK;
return 0;
}
BUG();
}
struct va1j5jf8007t_cb_map {
u32 frequency;
u8 cb;
};
static const struct va1j5jf8007t_cb_map va1j5jf8007t_cb_maps[] = {
{ 90000000, 0x80 },
{ 140000000, 0x81 },
{ 170000000, 0xa1 },
{ 220000000, 0x62 },
{ 330000000, 0xa2 },
{ 402000000, 0xe2 },
{ 450000000, 0x64 },
{ 550000000, 0x84 },
{ 600000000, 0xa4 },
{ 700000000, 0xc4 },
};
static u8 va1j5jf8007t_lookup_cb(u32 frequency)
{
int i;
const struct va1j5jf8007t_cb_map *map;
for (i = 0; i < ARRAY_SIZE(va1j5jf8007t_cb_maps); i++) {
map = &va1j5jf8007t_cb_maps[i];
if (frequency < map->frequency)
return map->cb;
}
return 0xe4;
}
static int va1j5jf8007t_set_frequency(struct va1j5jf8007t_state *state)
{
u32 frequency;
u16 word;
u8 buf[6];
struct i2c_msg msg;
frequency = state->fe.dtv_property_cache.frequency;
word = (frequency + 71428) / 142857 + 399;
buf[0] = 0xfe;
buf[1] = 0xc2;
buf[2] = word >> 8;
buf[3] = word;
buf[4] = 0x80;
buf[5] = va1j5jf8007t_lookup_cb(frequency);
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(state->adap, &msg, 1) != 1)
return -EREMOTEIO;
return 0;
}
static int
va1j5jf8007t_check_frequency(struct va1j5jf8007t_state *state, int *lock)
{
u8 addr;
u8 write_buf[2], read_buf[1];
struct i2c_msg msgs[2];
addr = state->config->demod_address;
write_buf[0] = 0xfe;
write_buf[1] = 0xc3;
msgs[0].addr = addr;
msgs[0].flags = 0;
msgs[0].len = sizeof(write_buf);
msgs[0].buf = write_buf;
msgs[1].addr = addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = sizeof(read_buf);
msgs[1].buf = read_buf;
if (i2c_transfer(state->adap, msgs, 2) != 2)
return -EREMOTEIO;
*lock = read_buf[0] & 0x40;
return 0;
}
static int va1j5jf8007t_set_modulation(struct va1j5jf8007t_state *state)
{
u8 buf[2];
struct i2c_msg msg;
buf[0] = 0x01;
buf[1] = 0x40;
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(state->adap, &msg, 1) != 1)
return -EREMOTEIO;
return 0;
}
static int va1j5jf8007t_check_modulation(struct va1j5jf8007t_state *state,
int *lock, int *retry)
{
u8 addr;
u8 write_buf[1], read_buf[1];
struct i2c_msg msgs[2];
addr = state->config->demod_address;
write_buf[0] = 0x80;
msgs[0].addr = addr;
msgs[0].flags = 0;
msgs[0].len = sizeof(write_buf);
msgs[0].buf = write_buf;
msgs[1].addr = addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = sizeof(read_buf);
msgs[1].buf = read_buf;
if (i2c_transfer(state->adap, msgs, 2) != 2)
return -EREMOTEIO;
*lock = !(read_buf[0] & 0x10);
*retry = read_buf[0] & 0x80;
return 0;
}
static int
va1j5jf8007t_tune(struct dvb_frontend *fe,
bool re_tune,
unsigned int mode_flags, unsigned int *delay,
fe_status_t *status)
{
struct va1j5jf8007t_state *state;
int ret;
int lock = 0, retry = 0;
state = fe->demodulator_priv;
if (re_tune)
state->tune_state = VA1J5JF8007T_SET_FREQUENCY;
switch (state->tune_state) {
case VA1J5JF8007T_IDLE:
*delay = 3 * HZ;
*status = 0;
return 0;
case VA1J5JF8007T_SET_FREQUENCY:
ret = va1j5jf8007t_set_frequency(state);
if (ret < 0)
return ret;
state->tune_state = VA1J5JF8007T_CHECK_FREQUENCY;
*delay = 0;
*status = 0;
return 0;
case VA1J5JF8007T_CHECK_FREQUENCY:
ret = va1j5jf8007t_check_frequency(state, &lock);
if (ret < 0)
return ret;
if (!lock) {
*delay = (HZ + 999) / 1000;
*status = 0;
return 0;
}
state->tune_state = VA1J5JF8007T_SET_MODULATION;
*delay = 0;
*status = FE_HAS_SIGNAL;
return 0;
case VA1J5JF8007T_SET_MODULATION:
ret = va1j5jf8007t_set_modulation(state);
if (ret < 0)
return ret;
state->tune_state = VA1J5JF8007T_CHECK_MODULATION;
*delay = 0;
*status = FE_HAS_SIGNAL;
return 0;
case VA1J5JF8007T_CHECK_MODULATION:
ret = va1j5jf8007t_check_modulation(state, &lock, &retry);
if (ret < 0)
return ret;
if (!lock) {
if (!retry) {
state->tune_state = VA1J5JF8007T_ABORT;
*delay = 3 * HZ;
*status = FE_HAS_SIGNAL;
return 0;
}
*delay = (HZ + 999) / 1000;
*status = FE_HAS_SIGNAL;
return 0;
}
state->tune_state = VA1J5JF8007T_TRACK;
/* fall through */
case VA1J5JF8007T_TRACK:
*delay = 3 * HZ;
*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_LOCK;
return 0;
case VA1J5JF8007T_ABORT:
*delay = 3 * HZ;
*status = FE_HAS_SIGNAL;
return 0;
}
BUG();
}
static int va1j5jf8007t_init_frequency(struct va1j5jf8007t_state *state)
{
u8 buf[7];
struct i2c_msg msg;
buf[0] = 0xfe;
buf[1] = 0xc2;
buf[2] = 0x01;
buf[3] = 0x8f;
buf[4] = 0xc1;
buf[5] = 0x80;
buf[6] = 0x80;
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(state->adap, &msg, 1) != 1)
return -EREMOTEIO;
return 0;
}
static int va1j5jf8007t_set_sleep(struct va1j5jf8007t_state *state, int sleep)
{
u8 buf[2];
struct i2c_msg msg;
buf[0] = 0x03;
buf[1] = sleep ? 0x90 : 0x80;
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(state->adap, &msg, 1) != 1)
return -EREMOTEIO;
return 0;
}
static int va1j5jf8007t_sleep(struct dvb_frontend *fe)
{
struct va1j5jf8007t_state *state;
int ret;
state = fe->demodulator_priv;
ret = va1j5jf8007t_init_frequency(state);
if (ret < 0)
return ret;
return va1j5jf8007t_set_sleep(state, 1);
}
static int va1j5jf8007t_init(struct dvb_frontend *fe)
{
struct va1j5jf8007t_state *state;
state = fe->demodulator_priv;
state->tune_state = VA1J5JF8007T_IDLE;
return va1j5jf8007t_set_sleep(state, 0);
}
static void va1j5jf8007t_release(struct dvb_frontend *fe)
{
struct va1j5jf8007t_state *state;
state = fe->demodulator_priv;
kfree(state);
}
static struct dvb_frontend_ops va1j5jf8007t_ops = {
.delsys = { SYS_ISDBT },
.info = {
.name = "VA1J5JF8007/VA1J5JF8011 ISDB-T",
.frequency_min = 90000000,
.frequency_max = 770000000,
.frequency_stepsize = 142857,
.caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
},
.read_snr = va1j5jf8007t_read_snr,
.get_frontend_algo = va1j5jf8007t_get_frontend_algo,
.read_status = va1j5jf8007t_read_status,
.tune = va1j5jf8007t_tune,
.sleep = va1j5jf8007t_sleep,
.init = va1j5jf8007t_init,
.release = va1j5jf8007t_release,
};
static const u8 va1j5jf8007t_20mhz_prepare_bufs[][2] = {
{0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2},
{0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00},
{0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03},
{0xef, 0x01}
};
static const u8 va1j5jf8007t_25mhz_prepare_bufs[][2] = {
{0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83},
{0x3a, 0x00}, {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x0a}, {0x76, 0x4c},
{0x77, 0x03}, {0xef, 0x01}
};
int va1j5jf8007t_prepare(struct dvb_frontend *fe)
{
struct va1j5jf8007t_state *state;
const u8 (*bufs)[2];
int size;
u8 buf[2];
struct i2c_msg msg;
int i;
state = fe->demodulator_priv;
switch (state->config->frequency) {
case VA1J5JF8007T_20MHZ:
bufs = va1j5jf8007t_20mhz_prepare_bufs;
size = ARRAY_SIZE(va1j5jf8007t_20mhz_prepare_bufs);
break;
case VA1J5JF8007T_25MHZ:
bufs = va1j5jf8007t_25mhz_prepare_bufs;
size = ARRAY_SIZE(va1j5jf8007t_25mhz_prepare_bufs);
break;
default:
return -EINVAL;
}
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
for (i = 0; i < size; i++) {
memcpy(buf, bufs[i], sizeof(buf));
if (i2c_transfer(state->adap, &msg, 1) != 1)
return -EREMOTEIO;
}
return va1j5jf8007t_init_frequency(state);
}
struct dvb_frontend *
va1j5jf8007t_attach(const struct va1j5jf8007t_config *config,
struct i2c_adapter *adap)
{
struct va1j5jf8007t_state *state;
struct dvb_frontend *fe;
u8 buf[2];
struct i2c_msg msg;
state = kzalloc(sizeof(struct va1j5jf8007t_state), GFP_KERNEL);
if (!state)
return NULL;
state->config = config;
state->adap = adap;
fe = &state->fe;
memcpy(&fe->ops, &va1j5jf8007t_ops, sizeof(struct dvb_frontend_ops));
fe->demodulator_priv = state;
buf[0] = 0x01;
buf[1] = 0x80;
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.len = sizeof(buf);
msg.buf = buf;
if (i2c_transfer(state->adap, &msg, 1) != 1) {
kfree(state);
return NULL;
}
return fe;
}
| gpl-2.0 |
TEAM-Gummy/elite_kernel_jf | drivers/scsi/pcmcia/sym53c500_cs.c | 10851 | 23728 | /*
* sym53c500_cs.c Bob Tracy (rct@frus.com)
*
* A rewrite of the pcmcia-cs add-on driver for newer (circa 1997)
* New Media Bus Toaster PCMCIA SCSI cards using the Symbios Logic
* 53c500 controller: intended for use with 2.6 and later kernels.
* The pcmcia-cs add-on version of this driver is not supported
* beyond 2.4. It consisted of three files with history/copyright
* information as follows:
*
* SYM53C500.h
* Bob Tracy (rct@frus.com)
* Original by Tom Corner (tcorner@via.at).
* Adapted from NCR53c406a.h which is Copyrighted (C) 1994
* Normunds Saumanis (normunds@rx.tech.swh.lv)
*
* SYM53C500.c
* Bob Tracy (rct@frus.com)
* Original driver by Tom Corner (tcorner@via.at) was adapted
* from NCR53c406a.c which is Copyrighted (C) 1994, 1995, 1996
* Normunds Saumanis (normunds@fi.ibm.com)
*
* sym53c500.c
* Bob Tracy (rct@frus.com)
* Original by Tom Corner (tcorner@via.at) was adapted from a
* driver for the Qlogic SCSI card written by
* David Hinds (dhinds@allegro.stanford.edu).
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#define SYM53C500_DEBUG 0
#define VERBOSE_SYM53C500_DEBUG 0
/*
* Set this to 0 if you encounter kernel lockups while transferring
* data in PIO mode. Note this can be changed via "sysfs".
*/
#define USE_FAST_PIO 1
/* =============== End of user configurable parameters ============== */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <scsi/scsi_ioctl.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi.h>
#include <scsi/scsi_host.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/ds.h>
#include <pcmcia/ciscode.h>
/* ================================================================== */
#define SYNC_MODE 0 /* Synchronous transfer mode */
/* Default configuration */
#define C1_IMG 0x07 /* ID=7 */
#define C2_IMG 0x48 /* FE SCSI2 */
#define C3_IMG 0x20 /* CDB */
#define C4_IMG 0x04 /* ANE */
#define C5_IMG 0xa4 /* ? changed from b6= AA PI SIE POL */
#define C7_IMG 0x80 /* added for SYM53C500 t. corner */
/* Hardware Registers: offsets from io_port (base) */
/* Control Register Set 0 */
#define TC_LSB 0x00 /* transfer counter lsb */
#define TC_MSB 0x01 /* transfer counter msb */
#define SCSI_FIFO 0x02 /* scsi fifo register */
#define CMD_REG 0x03 /* command register */
#define STAT_REG 0x04 /* status register */
#define DEST_ID 0x04 /* selection/reselection bus id */
#define INT_REG 0x05 /* interrupt status register */
#define SRTIMOUT 0x05 /* select/reselect timeout reg */
#define SEQ_REG 0x06 /* sequence step register */
#define SYNCPRD 0x06 /* synchronous transfer period */
#define FIFO_FLAGS 0x07 /* indicates # of bytes in fifo */
#define SYNCOFF 0x07 /* synchronous offset register */
#define CONFIG1 0x08 /* configuration register */
#define CLKCONV 0x09 /* clock conversion register */
/* #define TESTREG 0x0A */ /* test mode register */
#define CONFIG2 0x0B /* configuration 2 register */
#define CONFIG3 0x0C /* configuration 3 register */
#define CONFIG4 0x0D /* configuration 4 register */
#define TC_HIGH 0x0E /* transfer counter high */
/* #define FIFO_BOTTOM 0x0F */ /* reserve FIFO byte register */
/* Control Register Set 1 */
/* #define JUMPER_SENSE 0x00 */ /* jumper sense port reg (r/w) */
/* #define SRAM_PTR 0x01 */ /* SRAM address pointer reg (r/w) */
/* #define SRAM_DATA 0x02 */ /* SRAM data register (r/w) */
#define PIO_FIFO 0x04 /* PIO FIFO registers (r/w) */
/* #define PIO_FIFO1 0x05 */ /* */
/* #define PIO_FIFO2 0x06 */ /* */
/* #define PIO_FIFO3 0x07 */ /* */
#define PIO_STATUS 0x08 /* PIO status (r/w) */
/* #define ATA_CMD 0x09 */ /* ATA command/status reg (r/w) */
/* #define ATA_ERR 0x0A */ /* ATA features/error reg (r/w) */
#define PIO_FLAG 0x0B /* PIO flag interrupt enable (r/w) */
#define CONFIG5 0x09 /* configuration 5 register */
/* #define SIGNATURE 0x0E */ /* signature register (r) */
/* #define CONFIG6 0x0F */ /* configuration 6 register (r) */
#define CONFIG7 0x0d
/* select register set 0 */
#define REG0(x) (outb(C4_IMG, (x) + CONFIG4))
/* select register set 1 */
#define REG1(x) outb(C7_IMG, (x) + CONFIG7); outb(C5_IMG, (x) + CONFIG5)
#if SYM53C500_DEBUG
#define DEB(x) x
#else
#define DEB(x)
#endif
#if VERBOSE_SYM53C500_DEBUG
#define VDEB(x) x
#else
#define VDEB(x)
#endif
#define LOAD_DMA_COUNT(x, count) \
outb(count & 0xff, (x) + TC_LSB); \
outb((count >> 8) & 0xff, (x) + TC_MSB); \
outb((count >> 16) & 0xff, (x) + TC_HIGH);
/* Chip commands */
#define DMA_OP 0x80
#define SCSI_NOP 0x00
#define FLUSH_FIFO 0x01
#define CHIP_RESET 0x02
#define SCSI_RESET 0x03
#define RESELECT 0x40
#define SELECT_NO_ATN 0x41
#define SELECT_ATN 0x42
#define SELECT_ATN_STOP 0x43
#define ENABLE_SEL 0x44
#define DISABLE_SEL 0x45
#define SELECT_ATN3 0x46
#define RESELECT3 0x47
#define TRANSFER_INFO 0x10
#define INIT_CMD_COMPLETE 0x11
#define MSG_ACCEPT 0x12
#define TRANSFER_PAD 0x18
#define SET_ATN 0x1a
#define RESET_ATN 0x1b
#define SEND_MSG 0x20
#define SEND_STATUS 0x21
#define SEND_DATA 0x22
#define DISCONN_SEQ 0x23
#define TERMINATE_SEQ 0x24
#define TARG_CMD_COMPLETE 0x25
#define DISCONN 0x27
#define RECV_MSG 0x28
#define RECV_CMD 0x29
#define RECV_DATA 0x2a
#define RECV_CMD_SEQ 0x2b
#define TARGET_ABORT_DMA 0x04
/* ================================================================== */
struct scsi_info_t {
struct pcmcia_device *p_dev;
struct Scsi_Host *host;
unsigned short manf_id;
};
/*
* Repository for per-instance host data.
*/
struct sym53c500_data {
struct scsi_cmnd *current_SC;
int fast_pio;
};
enum Phase {
idle,
data_out,
data_in,
command_ph,
status_ph,
message_out,
message_in
};
/* ================================================================== */
static void
chip_init(int io_port)
{
REG1(io_port);
outb(0x01, io_port + PIO_STATUS);
outb(0x00, io_port + PIO_FLAG);
outb(C4_IMG, io_port + CONFIG4); /* REG0(io_port); */
outb(C3_IMG, io_port + CONFIG3);
outb(C2_IMG, io_port + CONFIG2);
outb(C1_IMG, io_port + CONFIG1);
outb(0x05, io_port + CLKCONV); /* clock conversion factor */
outb(0x9C, io_port + SRTIMOUT); /* Selection timeout */
outb(0x05, io_port + SYNCPRD); /* Synchronous transfer period */
outb(SYNC_MODE, io_port + SYNCOFF); /* synchronous mode */
}
static void
SYM53C500_int_host_reset(int io_port)
{
outb(C4_IMG, io_port + CONFIG4); /* REG0(io_port); */
outb(CHIP_RESET, io_port + CMD_REG);
outb(SCSI_NOP, io_port + CMD_REG); /* required after reset */
outb(SCSI_RESET, io_port + CMD_REG);
chip_init(io_port);
}
static __inline__ int
SYM53C500_pio_read(int fast_pio, int base, unsigned char *request, unsigned int reqlen)
{
int i;
int len; /* current scsi fifo size */
REG1(base);
while (reqlen) {
i = inb(base + PIO_STATUS);
/* VDEB(printk("pio_status=%x\n", i)); */
if (i & 0x80)
return 0;
switch (i & 0x1e) {
default:
case 0x10: /* fifo empty */
len = 0;
break;
case 0x0:
len = 1;
break;
case 0x8: /* fifo 1/3 full */
len = 42;
break;
case 0xc: /* fifo 2/3 full */
len = 84;
break;
case 0xe: /* fifo full */
len = 128;
break;
}
if ((i & 0x40) && len == 0) { /* fifo empty and interrupt occurred */
return 0;
}
if (len) {
if (len > reqlen)
len = reqlen;
if (fast_pio && len > 3) {
insl(base + PIO_FIFO, request, len >> 2);
request += len & 0xfc;
reqlen -= len & 0xfc;
} else {
while (len--) {
*request++ = inb(base + PIO_FIFO);
reqlen--;
}
}
}
}
return 0;
}
static __inline__ int
SYM53C500_pio_write(int fast_pio, int base, unsigned char *request, unsigned int reqlen)
{
int i = 0;
int len; /* current scsi fifo size */
REG1(base);
while (reqlen && !(i & 0x40)) {
i = inb(base + PIO_STATUS);
/* VDEB(printk("pio_status=%x\n", i)); */
if (i & 0x80) /* error */
return 0;
switch (i & 0x1e) {
case 0x10:
len = 128;
break;
case 0x0:
len = 84;
break;
case 0x8:
len = 42;
break;
case 0xc:
len = 1;
break;
default:
case 0xe:
len = 0;
break;
}
if (len) {
if (len > reqlen)
len = reqlen;
if (fast_pio && len > 3) {
outsl(base + PIO_FIFO, request, len >> 2);
request += len & 0xfc;
reqlen -= len & 0xfc;
} else {
while (len--) {
outb(*request++, base + PIO_FIFO);
reqlen--;
}
}
}
}
return 0;
}
static irqreturn_t
SYM53C500_intr(int irq, void *dev_id)
{
unsigned long flags;
struct Scsi_Host *dev = dev_id;
DEB(unsigned char fifo_size;)
DEB(unsigned char seq_reg;)
unsigned char status, int_reg;
unsigned char pio_status;
int port_base = dev->io_port;
struct sym53c500_data *data =
(struct sym53c500_data *)dev->hostdata;
struct scsi_cmnd *curSC = data->current_SC;
int fast_pio = data->fast_pio;
spin_lock_irqsave(dev->host_lock, flags);
VDEB(printk("SYM53C500_intr called\n"));
REG1(port_base);
pio_status = inb(port_base + PIO_STATUS);
REG0(port_base);
status = inb(port_base + STAT_REG);
DEB(seq_reg = inb(port_base + SEQ_REG));
int_reg = inb(port_base + INT_REG);
DEB(fifo_size = inb(port_base + FIFO_FLAGS) & 0x1f);
#if SYM53C500_DEBUG
printk("status=%02x, seq_reg=%02x, int_reg=%02x, fifo_size=%02x",
status, seq_reg, int_reg, fifo_size);
printk(", pio=%02x\n", pio_status);
#endif /* SYM53C500_DEBUG */
if (int_reg & 0x80) { /* SCSI reset intr */
DEB(printk("SYM53C500: reset intr received\n"));
curSC->result = DID_RESET << 16;
goto idle_out;
}
if (pio_status & 0x80) {
printk("SYM53C500: Warning: PIO error!\n");
curSC->result = DID_ERROR << 16;
goto idle_out;
}
if (status & 0x20) { /* Parity error */
printk("SYM53C500: Warning: parity error!\n");
curSC->result = DID_PARITY << 16;
goto idle_out;
}
if (status & 0x40) { /* Gross error */
printk("SYM53C500: Warning: gross error!\n");
curSC->result = DID_ERROR << 16;
goto idle_out;
}
if (int_reg & 0x20) { /* Disconnect */
DEB(printk("SYM53C500: disconnect intr received\n"));
if (curSC->SCp.phase != message_in) { /* Unexpected disconnect */
curSC->result = DID_NO_CONNECT << 16;
} else { /* Command complete, return status and message */
curSC->result = (curSC->SCp.Status & 0xff)
| ((curSC->SCp.Message & 0xff) << 8) | (DID_OK << 16);
}
goto idle_out;
}
switch (status & 0x07) { /* scsi phase */
case 0x00: /* DATA-OUT */
if (int_reg & 0x10) { /* Target requesting info transfer */
struct scatterlist *sg;
int i;
curSC->SCp.phase = data_out;
VDEB(printk("SYM53C500: Data-Out phase\n"));
outb(FLUSH_FIFO, port_base + CMD_REG);
LOAD_DMA_COUNT(port_base, scsi_bufflen(curSC)); /* Max transfer size */
outb(TRANSFER_INFO | DMA_OP, port_base + CMD_REG);
scsi_for_each_sg(curSC, sg, scsi_sg_count(curSC), i) {
SYM53C500_pio_write(fast_pio, port_base,
sg_virt(sg), sg->length);
}
REG0(port_base);
}
break;
case 0x01: /* DATA-IN */
if (int_reg & 0x10) { /* Target requesting info transfer */
struct scatterlist *sg;
int i;
curSC->SCp.phase = data_in;
VDEB(printk("SYM53C500: Data-In phase\n"));
outb(FLUSH_FIFO, port_base + CMD_REG);
LOAD_DMA_COUNT(port_base, scsi_bufflen(curSC)); /* Max transfer size */
outb(TRANSFER_INFO | DMA_OP, port_base + CMD_REG);
scsi_for_each_sg(curSC, sg, scsi_sg_count(curSC), i) {
SYM53C500_pio_read(fast_pio, port_base,
sg_virt(sg), sg->length);
}
REG0(port_base);
}
break;
case 0x02: /* COMMAND */
curSC->SCp.phase = command_ph;
printk("SYM53C500: Warning: Unknown interrupt occurred in command phase!\n");
break;
case 0x03: /* STATUS */
curSC->SCp.phase = status_ph;
VDEB(printk("SYM53C500: Status phase\n"));
outb(FLUSH_FIFO, port_base + CMD_REG);
outb(INIT_CMD_COMPLETE, port_base + CMD_REG);
break;
case 0x04: /* Reserved */
case 0x05: /* Reserved */
printk("SYM53C500: WARNING: Reserved phase!!!\n");
break;
case 0x06: /* MESSAGE-OUT */
DEB(printk("SYM53C500: Message-Out phase\n"));
curSC->SCp.phase = message_out;
outb(SET_ATN, port_base + CMD_REG); /* Reject the message */
outb(MSG_ACCEPT, port_base + CMD_REG);
break;
case 0x07: /* MESSAGE-IN */
VDEB(printk("SYM53C500: Message-In phase\n"));
curSC->SCp.phase = message_in;
curSC->SCp.Status = inb(port_base + SCSI_FIFO);
curSC->SCp.Message = inb(port_base + SCSI_FIFO);
VDEB(printk("SCSI FIFO size=%d\n", inb(port_base + FIFO_FLAGS) & 0x1f));
DEB(printk("Status = %02x Message = %02x\n", curSC->SCp.Status, curSC->SCp.Message));
if (curSC->SCp.Message == SAVE_POINTERS || curSC->SCp.Message == DISCONNECT) {
outb(SET_ATN, port_base + CMD_REG); /* Reject message */
DEB(printk("Discarding SAVE_POINTERS message\n"));
}
outb(MSG_ACCEPT, port_base + CMD_REG);
break;
}
out:
spin_unlock_irqrestore(dev->host_lock, flags);
return IRQ_HANDLED;
idle_out:
curSC->SCp.phase = idle;
curSC->scsi_done(curSC);
goto out;
}
static void
SYM53C500_release(struct pcmcia_device *link)
{
struct scsi_info_t *info = link->priv;
struct Scsi_Host *shost = info->host;
dev_dbg(&link->dev, "SYM53C500_release\n");
/*
* Do this before releasing/freeing resources.
*/
scsi_remove_host(shost);
/*
* Interrupts getting hosed on card removal. Try
* the following code, mostly from qlogicfas.c.
*/
if (shost->irq)
free_irq(shost->irq, shost);
if (shost->io_port && shost->n_io_port)
release_region(shost->io_port, shost->n_io_port);
pcmcia_disable_device(link);
scsi_host_put(shost);
} /* SYM53C500_release */
static const char*
SYM53C500_info(struct Scsi_Host *SChost)
{
static char info_msg[256];
struct sym53c500_data *data =
(struct sym53c500_data *)SChost->hostdata;
DEB(printk("SYM53C500_info called\n"));
(void)snprintf(info_msg, sizeof(info_msg),
"SYM53C500 at 0x%lx, IRQ %d, %s PIO mode.",
SChost->io_port, SChost->irq, data->fast_pio ? "fast" : "slow");
return (info_msg);
}
static int
SYM53C500_queue_lck(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
{
int i;
int port_base = SCpnt->device->host->io_port;
struct sym53c500_data *data =
(struct sym53c500_data *)SCpnt->device->host->hostdata;
VDEB(printk("SYM53C500_queue called\n"));
DEB(printk("cmd=%02x, cmd_len=%02x, target=%02x, lun=%02x, bufflen=%d\n",
SCpnt->cmnd[0], SCpnt->cmd_len, SCpnt->device->id,
SCpnt->device->lun, scsi_bufflen(SCpnt)));
VDEB(for (i = 0; i < SCpnt->cmd_len; i++)
printk("cmd[%d]=%02x ", i, SCpnt->cmnd[i]));
VDEB(printk("\n"));
data->current_SC = SCpnt;
data->current_SC->scsi_done = done;
data->current_SC->SCp.phase = command_ph;
data->current_SC->SCp.Status = 0;
data->current_SC->SCp.Message = 0;
/* We are locked here already by the mid layer */
REG0(port_base);
outb(scmd_id(SCpnt), port_base + DEST_ID); /* set destination */
outb(FLUSH_FIFO, port_base + CMD_REG); /* reset the fifos */
for (i = 0; i < SCpnt->cmd_len; i++) {
outb(SCpnt->cmnd[i], port_base + SCSI_FIFO);
}
outb(SELECT_NO_ATN, port_base + CMD_REG);
return 0;
}
static DEF_SCSI_QCMD(SYM53C500_queue)
static int
SYM53C500_host_reset(struct scsi_cmnd *SCpnt)
{
int port_base = SCpnt->device->host->io_port;
DEB(printk("SYM53C500_host_reset called\n"));
spin_lock_irq(SCpnt->device->host->host_lock);
SYM53C500_int_host_reset(port_base);
spin_unlock_irq(SCpnt->device->host->host_lock);
return SUCCESS;
}
static int
SYM53C500_biosparm(struct scsi_device *disk,
struct block_device *dev,
sector_t capacity, int *info_array)
{
int size;
DEB(printk("SYM53C500_biosparm called\n"));
size = capacity;
info_array[0] = 64; /* heads */
info_array[1] = 32; /* sectors */
info_array[2] = size >> 11; /* cylinders */
if (info_array[2] > 1024) { /* big disk */
info_array[0] = 255;
info_array[1] = 63;
info_array[2] = size / (255 * 63);
}
return 0;
}
static ssize_t
SYM53C500_show_pio(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct Scsi_Host *SHp = class_to_shost(dev);
struct sym53c500_data *data =
(struct sym53c500_data *)SHp->hostdata;
return snprintf(buf, 4, "%d\n", data->fast_pio);
}
static ssize_t
SYM53C500_store_pio(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
int pio;
struct Scsi_Host *SHp = class_to_shost(dev);
struct sym53c500_data *data =
(struct sym53c500_data *)SHp->hostdata;
pio = simple_strtoul(buf, NULL, 0);
if (pio == 0 || pio == 1) {
data->fast_pio = pio;
return count;
}
else
return -EINVAL;
}
/*
* SCSI HBA device attributes we want to
* make available via sysfs.
*/
static struct device_attribute SYM53C500_pio_attr = {
.attr = {
.name = "fast_pio",
.mode = (S_IRUGO | S_IWUSR),
},
.show = SYM53C500_show_pio,
.store = SYM53C500_store_pio,
};
static struct device_attribute *SYM53C500_shost_attrs[] = {
&SYM53C500_pio_attr,
NULL,
};
/*
* scsi_host_template initializer
*/
static struct scsi_host_template sym53c500_driver_template = {
.module = THIS_MODULE,
.name = "SYM53C500",
.info = SYM53C500_info,
.queuecommand = SYM53C500_queue,
.eh_host_reset_handler = SYM53C500_host_reset,
.bios_param = SYM53C500_biosparm,
.proc_name = "SYM53C500",
.can_queue = 1,
.this_id = 7,
.sg_tablesize = 32,
.cmd_per_lun = 1,
.use_clustering = ENABLE_CLUSTERING,
.shost_attrs = SYM53C500_shost_attrs
};
static int SYM53C500_config_check(struct pcmcia_device *p_dev, void *priv_data)
{
p_dev->io_lines = 10;
p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
if (p_dev->resource[0]->start == 0)
return -ENODEV;
return pcmcia_request_io(p_dev);
}
static int
SYM53C500_config(struct pcmcia_device *link)
{
struct scsi_info_t *info = link->priv;
int ret;
int irq_level, port_base;
struct Scsi_Host *host;
struct scsi_host_template *tpnt = &sym53c500_driver_template;
struct sym53c500_data *data;
dev_dbg(&link->dev, "SYM53C500_config\n");
info->manf_id = link->manf_id;
ret = pcmcia_loop_config(link, SYM53C500_config_check, NULL);
if (ret)
goto failed;
if (!link->irq)
goto failed;
ret = pcmcia_enable_device(link);
if (ret)
goto failed;
/*
* That's the trouble with copying liberally from another driver.
* Some things probably aren't relevant, and I suspect this entire
* section dealing with manufacturer IDs can be scrapped. --rct
*/
if ((info->manf_id == MANFID_MACNICA) ||
(info->manf_id == MANFID_PIONEER) ||
(info->manf_id == 0x0098)) {
/* set ATAcmd */
outb(0xb4, link->resource[0]->start + 0xd);
outb(0x24, link->resource[0]->start + 0x9);
outb(0x04, link->resource[0]->start + 0xd);
}
/*
* irq_level == 0 implies tpnt->can_queue == 0, which
* is not supported in 2.6. Thus, only irq_level > 0
* will be allowed.
*
* Possible port_base values are as follows:
*
* 0x130, 0x230, 0x280, 0x290,
* 0x320, 0x330, 0x340, 0x350
*/
port_base = link->resource[0]->start;
irq_level = link->irq;
DEB(printk("SYM53C500: port_base=0x%x, irq=%d, fast_pio=%d\n",
port_base, irq_level, USE_FAST_PIO);)
chip_init(port_base);
host = scsi_host_alloc(tpnt, sizeof(struct sym53c500_data));
if (!host) {
printk("SYM53C500: Unable to register host, giving up.\n");
goto err_release;
}
data = (struct sym53c500_data *)host->hostdata;
if (irq_level > 0) {
if (request_irq(irq_level, SYM53C500_intr, IRQF_SHARED, "SYM53C500", host)) {
printk("SYM53C500: unable to allocate IRQ %d\n", irq_level);
goto err_free_scsi;
}
DEB(printk("SYM53C500: allocated IRQ %d\n", irq_level));
} else if (irq_level == 0) {
DEB(printk("SYM53C500: No interrupts detected\n"));
goto err_free_scsi;
} else {
DEB(printk("SYM53C500: Shouldn't get here!\n"));
goto err_free_scsi;
}
host->unique_id = port_base;
host->irq = irq_level;
host->io_port = port_base;
host->n_io_port = 0x10;
host->dma_channel = -1;
/*
* Note fast_pio is set to USE_FAST_PIO by
* default, but can be changed via "sysfs".
*/
data->fast_pio = USE_FAST_PIO;
info->host = host;
if (scsi_add_host(host, NULL))
goto err_free_irq;
scsi_scan_host(host);
return 0;
err_free_irq:
free_irq(irq_level, host);
err_free_scsi:
scsi_host_put(host);
err_release:
release_region(port_base, 0x10);
printk(KERN_INFO "sym53c500_cs: no SCSI devices found\n");
return -ENODEV;
failed:
SYM53C500_release(link);
return -ENODEV;
} /* SYM53C500_config */
static int sym53c500_resume(struct pcmcia_device *link)
{
struct scsi_info_t *info = link->priv;
/* See earlier comment about manufacturer IDs. */
if ((info->manf_id == MANFID_MACNICA) ||
(info->manf_id == MANFID_PIONEER) ||
(info->manf_id == 0x0098)) {
outb(0x80, link->resource[0]->start + 0xd);
outb(0x24, link->resource[0]->start + 0x9);
outb(0x04, link->resource[0]->start + 0xd);
}
/*
* If things don't work after a "resume",
* this is a good place to start looking.
*/
SYM53C500_int_host_reset(link->resource[0]->start);
return 0;
}
static void
SYM53C500_detach(struct pcmcia_device *link)
{
dev_dbg(&link->dev, "SYM53C500_detach\n");
SYM53C500_release(link);
kfree(link->priv);
link->priv = NULL;
} /* SYM53C500_detach */
static int
SYM53C500_probe(struct pcmcia_device *link)
{
struct scsi_info_t *info;
dev_dbg(&link->dev, "SYM53C500_attach()\n");
/* Create new SCSI device */
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->p_dev = link;
link->priv = info;
link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
return SYM53C500_config(link);
} /* SYM53C500_attach */
MODULE_AUTHOR("Bob Tracy <rct@frus.com>");
MODULE_DESCRIPTION("SYM53C500 PCMCIA SCSI driver");
MODULE_LICENSE("GPL");
static const struct pcmcia_device_id sym53c500_ids[] = {
PCMCIA_DEVICE_PROD_ID12("BASICS by New Media Corporation", "SCSI Sym53C500", 0x23c78a9d, 0x0099e7f7),
PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "SCSI Bus Toaster Sym53C500", 0x085a850b, 0x45432eb8),
PCMCIA_DEVICE_PROD_ID2("SCSI9000", 0x21648f44),
PCMCIA_DEVICE_NULL,
};
MODULE_DEVICE_TABLE(pcmcia, sym53c500_ids);
static struct pcmcia_driver sym53c500_cs_driver = {
.owner = THIS_MODULE,
.name = "sym53c500_cs",
.probe = SYM53C500_probe,
.remove = SYM53C500_detach,
.id_table = sym53c500_ids,
.resume = sym53c500_resume,
};
static int __init
init_sym53c500_cs(void)
{
return pcmcia_register_driver(&sym53c500_cs_driver);
}
static void __exit
exit_sym53c500_cs(void)
{
pcmcia_unregister_driver(&sym53c500_cs_driver);
}
module_init(init_sym53c500_cs);
module_exit(exit_sym53c500_cs);
| gpl-2.0 |
SM-G920P/kernel_samsung_exynos7420 | drivers/video/console/font_acorn_8x8.c | 14691 | 16047 | /* Acorn-like font definition, with PC graphics characters */
#include <linux/font.h>
static const unsigned char acorndata_8x8[] = {
/* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^@ */
/* 01 */ 0x7e, 0x81, 0xa5, 0x81, 0xbd, 0x99, 0x81, 0x7e, /* ^A */
/* 02 */ 0x7e, 0xff, 0xbd, 0xff, 0xc3, 0xe7, 0xff, 0x7e, /* ^B */
/* 03 */ 0x6c, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10, 0x00, /* ^C */
/* 04 */ 0x10, 0x38, 0x7c, 0xfe, 0x7c, 0x38, 0x10, 0x00, /* ^D */
/* 05 */ 0x00, 0x18, 0x3c, 0xe7, 0xe7, 0x3c, 0x18, 0x00, /* ^E */
/* 06 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 07 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 08 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 09 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 0A */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 0B */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 0C */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 0D */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 0E */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 0F */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 10 */ 0x00, 0x60, 0x78, 0x7e, 0x7e, 0x78, 0x60, 0x00, /* |> */
/* 11 */ 0x00, 0x06, 0x1e, 0x7e, 0x7e, 0x1e, 0x06, 0x00, /* <| */
/* 12 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 13 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 14 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 15 */ 0x3c, 0x60, 0x3c, 0x66, 0x3c, 0x06, 0x3c, 0x00,
/* 16 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 17 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 18 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 19 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 1A */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 1B */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 1C */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 1D */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 1E */ 0x00, 0x18, 0x18, 0x3c, 0x3c, 0x7e, 0x7e, 0x00, /* /\ */
/* 1F */ 0x00, 0x7e, 0x7e, 0x3c, 0x3c, 0x18, 0x18, 0x00, /* \/ */
/* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* */
/* 21 */ 0x18, 0x3c, 0x3c, 0x18, 0x18, 0x00, 0x18, 0x00, /* ! */
/* 22 */ 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, /* " */
/* 23 */ 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00, /* # */
/* 24 */ 0x0C, 0x3F, 0x68, 0x3E, 0x0B, 0x7E, 0x18, 0x00, /* $ */
/* 25 */ 0x60, 0x66, 0x0C, 0x18, 0x30, 0x66, 0x06, 0x00, /* % */
/* 26 */ 0x38, 0x6C, 0x6C, 0x38, 0x6D, 0x66, 0x3B, 0x00, /* & */
/* 27 */ 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, /* ' */
/* 28 */ 0x0C, 0x18, 0x30, 0x30, 0x30, 0x18, 0x0C, 0x00, /* ( */
/* 29 */ 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x18, 0x30, 0x00, /* ) */
/* 2A */ 0x00, 0x18, 0x7E, 0x3C, 0x7E, 0x18, 0x00, 0x00, /* * */
/* 2B */ 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00, /* + */
/* 2C */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30, /* , */
/* 2D */ 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, /* - */
/* 2E */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, /* . */
/* 2F */ 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00, 0x00, /* / */
/* 30 */ 0x3C, 0x66, 0x6E, 0x7E, 0x76, 0x66, 0x3C, 0x00, /* 0 */
/* 31 */ 0x18, 0x38, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00, /* 1 */
/* 32 */ 0x3C, 0x66, 0x06, 0x0C, 0x18, 0x30, 0x7E, 0x00, /* 2 */
/* 33 */ 0x3C, 0x66, 0x06, 0x1C, 0x06, 0x66, 0x3C, 0x00, /* 3 */
/* 34 */ 0x0C, 0x1C, 0x3C, 0x6C, 0x7E, 0x0C, 0x0C, 0x00, /* 4 */
/* 35 */ 0x7E, 0x60, 0x7C, 0x06, 0x06, 0x66, 0x3C, 0x00, /* 5 */
/* 36 */ 0x1C, 0x30, 0x60, 0x7C, 0x66, 0x66, 0x3C, 0x00, /* 6 */
/* 37 */ 0x7E, 0x06, 0x0C, 0x18, 0x30, 0x30, 0x30, 0x00, /* 7 */
/* 38 */ 0x3C, 0x66, 0x66, 0x3C, 0x66, 0x66, 0x3C, 0x00, /* 8 */
/* 39 */ 0x3C, 0x66, 0x66, 0x3E, 0x06, 0x0C, 0x38, 0x00, /* 9 */
/* 3A */ 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, /* : */
/* 3B */ 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x30, /* ; */
/* 3C */ 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00, /* < */
/* 3D */ 0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00, /* = */
/* 3E */ 0x30, 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00, /* > */
/* 3F */ 0x3C, 0x66, 0x0C, 0x18, 0x18, 0x00, 0x18, 0x00, /* ? */
/* 40 */ 0x3C, 0x66, 0x6E, 0x6A, 0x6E, 0x60, 0x3C, 0x00, /* @ */
/* 41 */ 0x3C, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00, /* A */
/* 42 */ 0x7C, 0x66, 0x66, 0x7C, 0x66, 0x66, 0x7C, 0x00, /* B */
/* 43 */ 0x3C, 0x66, 0x60, 0x60, 0x60, 0x66, 0x3C, 0x00, /* C */
/* 44 */ 0x78, 0x6C, 0x66, 0x66, 0x66, 0x6C, 0x78, 0x00, /* D */
/* 45 */ 0x7E, 0x60, 0x60, 0x7C, 0x60, 0x60, 0x7E, 0x00, /* E */
/* 46 */ 0x7E, 0x60, 0x60, 0x7C, 0x60, 0x60, 0x60, 0x00, /* F */
/* 47 */ 0x3C, 0x66, 0x60, 0x6E, 0x66, 0x66, 0x3C, 0x00, /* G */
/* 48 */ 0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00, /* H */
/* 49 */ 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00, /* I */
/* 4A */ 0x3E, 0x0C, 0x0C, 0x0C, 0x0C, 0x6C, 0x38, 0x00, /* J */
/* 4B */ 0x66, 0x6C, 0x78, 0x70, 0x78, 0x6C, 0x66, 0x00, /* K */
/* 4C */ 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x7E, 0x00, /* L */
/* 4D */ 0x63, 0x77, 0x7F, 0x6B, 0x6B, 0x63, 0x63, 0x00, /* M */
/* 4E */ 0x66, 0x66, 0x76, 0x7E, 0x6E, 0x66, 0x66, 0x00, /* N */
/* 4F */ 0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, /* O */
/* 50 */ 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x60, 0x60, 0x00, /* P */
/* 51 */ 0x3C, 0x66, 0x66, 0x66, 0x6A, 0x6C, 0x36, 0x00, /* Q */
/* 52 */ 0x7C, 0x66, 0x66, 0x7C, 0x6C, 0x66, 0x66, 0x00, /* R */
/* 53 */ 0x3C, 0x66, 0x60, 0x3C, 0x06, 0x66, 0x3C, 0x00, /* S */
/* 54 */ 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, /* T */
/* 55 */ 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, /* U */
/* 56 */ 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00, /* V */
/* 57 */ 0x63, 0x63, 0x6B, 0x6B, 0x7F, 0x77, 0x63, 0x00, /* W */
/* 58 */ 0x66, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x66, 0x00, /* X */
/* 59 */ 0x66, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18, 0x00, /* Y */
/* 5A */ 0x7E, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x7E, 0x00, /* Z */
/* 5B */ 0x7C, 0x60, 0x60, 0x60, 0x60, 0x60, 0x7C, 0x00, /* [ */
/* 5C */ 0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x00, 0x00, /* \ */
/* 5D */ 0x3E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x3E, 0x00, /* ] */
/* 5E */ 0x3C, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^ */
/* 5F */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, /* _ */
/* 60 */ 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ` */
/* 61 */ 0x00, 0x00, 0x3C, 0x06, 0x3E, 0x66, 0x3E, 0x00, /* a */
/* 62 */ 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x00, /* b */
/* 63 */ 0x00, 0x00, 0x3C, 0x66, 0x60, 0x66, 0x3C, 0x00, /* c */
/* 64 */ 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x3E, 0x00, /* d */
/* 65 */ 0x00, 0x00, 0x3C, 0x66, 0x7E, 0x60, 0x3C, 0x00, /* e */
/* 66 */ 0x1C, 0x30, 0x30, 0x7C, 0x30, 0x30, 0x30, 0x00, /* f */
/* 67 */ 0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x3C, /* g */
/* 68 */ 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x00, /* h */
/* 69 */ 0x18, 0x00, 0x38, 0x18, 0x18, 0x18, 0x3C, 0x00, /* i */
/* 6A */ 0x18, 0x00, 0x38, 0x18, 0x18, 0x18, 0x18, 0x70, /* j */
/* 6B */ 0x60, 0x60, 0x66, 0x6C, 0x78, 0x6C, 0x66, 0x00, /* k */
/* 6C */ 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, /* l */
/* 6D */ 0x00, 0x00, 0x36, 0x7F, 0x6B, 0x6B, 0x63, 0x00, /* m */
/* 6E */ 0x00, 0x00, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x00, /* n */
/* 6F */ 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C, 0x00, /* o */
/* 70 */ 0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x60, /* p */
/* 71 */ 0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x07, /* q */
/* 72 */ 0x00, 0x00, 0x6C, 0x76, 0x60, 0x60, 0x60, 0x00, /* r */
/* 73 */ 0x00, 0x00, 0x3E, 0x60, 0x3C, 0x06, 0x7C, 0x00, /* s */
/* 74 */ 0x30, 0x30, 0x7C, 0x30, 0x30, 0x30, 0x1C, 0x00, /* t */
/* 75 */ 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x3E, 0x00, /* u */
/* 76 */ 0x00, 0x00, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00, /* v */
/* 77 */ 0x00, 0x00, 0x63, 0x6B, 0x6B, 0x7F, 0x36, 0x00, /* w */
/* 78 */ 0x00, 0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x00, /* x */
/* 79 */ 0x00, 0x00, 0x66, 0x66, 0x66, 0x3E, 0x06, 0x3C, /* y */
/* 7A */ 0x00, 0x00, 0x7E, 0x0C, 0x18, 0x30, 0x7E, 0x00, /* z */
/* 7B */ 0x0C, 0x18, 0x18, 0x70, 0x18, 0x18, 0x0C, 0x00, /* { */
/* 7C */ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, /* | */
/* 7D */ 0x30, 0x18, 0x18, 0x0E, 0x18, 0x18, 0x30, 0x00, /* } */
/* 7E */ 0x31, 0x6B, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, /* ~ */
/* 7F */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* */
/* 80 */ 0x3c, 0x66, 0x60, 0x60, 0x66, 0x3c, 0x30, 0x60,
/* 81 */ 0x66, 0x00, 0x66, 0x66, 0x66, 0x66, 0x3e, 0x00,
/* 82 */ 0x0c, 0x18, 0x3c, 0x66, 0x7e, 0x60, 0x3c, 0x00,
/* 83 */ 0x18, 0x66, 0x3c, 0x06, 0x3e, 0x66, 0x3e, 0x00,
/* 84 */ 0x66, 0x00, 0x3c, 0x06, 0x3e, 0x66, 0x3e, 0x00,
/* 85 */ 0x30, 0x18, 0x3c, 0x06, 0x3e, 0x66, 0x3e, 0x00,
/* 86 */ 0x3c, 0x66, 0x3c, 0x06, 0x3e, 0x66, 0x3e, 0x00,
/* 87 */ 0x00, 0x00, 0x3c, 0x66, 0x60, 0x66, 0x3c, 0x60,
/* 88 */ 0x3c, 0x66, 0x3c, 0x66, 0x7e, 0x60, 0x3c, 0x00,
/* 89 */ 0x66, 0x00, 0x3c, 0x66, 0x7e, 0x60, 0x3c, 0x00,
/* 8A */ 0x30, 0x18, 0x3c, 0x66, 0x7e, 0x60, 0x3c, 0x00,
/* 8B */ 0x66, 0x00, 0x00, 0x38, 0x18, 0x18, 0x3c, 0x00,
/* 8C */ 0x3c, 0x66, 0x00, 0x38, 0x18, 0x18, 0x3c, 0x00,
/* 8D */ 0x30, 0x18, 0x00, 0x38, 0x18, 0x18, 0x3c, 0x00,
/* 8E */ 0x66, 0x66, 0x00, 0x3c, 0x66, 0x7e, 0x66, 0x00,
/* 8F */ 0x18, 0x66, 0x00, 0x3c, 0x66, 0x7e, 0x66, 0x00,
/* 90 */ 0x0c, 0x18, 0x7e, 0x60, 0x7c, 0x60, 0x7e, 0x00,
/* 91 */ 0x00, 0x00, 0x3f, 0x0d, 0x3f, 0x6c, 0x3f, 0x00,
/* 92 */ 0x3f, 0x66, 0x66, 0x7f, 0x66, 0x66, 0x67, 0x00,
/* 93 */ 0x3c, 0x66, 0x00, 0x3c, 0x66, 0x66, 0x3c, 0x00,
/* 94 */ 0x66, 0x00, 0x00, 0x3c, 0x66, 0x66, 0x3c, 0x00,
/* 95 */ 0x30, 0x18, 0x00, 0x3c, 0x66, 0x66, 0x3c, 0x00,
/* 96 */ 0x3c, 0x66, 0x00, 0x66, 0x66, 0x66, 0x3e, 0x00,
/* 97 */ 0x30, 0x18, 0x00, 0x66, 0x66, 0x66, 0x3e, 0x00,
/* 98 */ 0x66, 0x00, 0x66, 0x66, 0x66, 0x3e, 0x06, 0x3c,
/* 99 */ 0x66, 0x00, 0x3c, 0x66, 0x66, 0x66, 0x3c, 0x00,
/* 9A */ 0x66, 0x00, 0x66, 0x66, 0x66, 0x66, 0x3c, 0x00,
/* 9B */ 0x08, 0x3e, 0x6b, 0x68, 0x6b, 0x3e, 0x08, 0x00,
/* 9C */ 0x1c, 0x36, 0x30, 0x7c, 0x30, 0x30, 0x7e, 0x00,
/* 9D */ 0x66, 0x3c, 0x18, 0x18, 0x7e, 0x18, 0x18, 0x00,
/* 9E */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* 9F */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* A0 */ 0x0c, 0x18, 0x3c, 0x06, 0x3e, 0x66, 0x3e, 0x00,
/* A1 */ 0x0c, 0x18, 0x00, 0x38, 0x18, 0x18, 0x3c, 0x00,
/* A2 */ 0x0c, 0x18, 0x00, 0x3c, 0x66, 0x66, 0x3c, 0x00,
/* A3 */ 0x0c, 0x18, 0x00, 0x66, 0x66, 0x66, 0x3e, 0x00,
/* A4 */ 0x36, 0x6c, 0x00, 0x7c, 0x66, 0x66, 0x66, 0x00,
/* A5 */ 0x36, 0x6c, 0x00, 0x66, 0x76, 0x6e, 0x66, 0x00,
/* A6 */ 0x1c, 0x06, 0x1e, 0x36, 0x1e, 0x00, 0x3e, 0x00,
/* A7 */ 0x1c, 0x36, 0x36, 0x36, 0x1c, 0x00, 0x3e, 0x00,
/* A8 */ 0x18, 0x00, 0x18, 0x18, 0x30, 0x66, 0x3c, 0x00,
/* A9 */ 0x7e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* AA */ 0x7e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* AB */ 0x40, 0xc0, 0x40, 0x4f, 0x41, 0x0f, 0x08, 0x0f,
/* AC */ 0x40, 0xc0, 0x40, 0x48, 0x48, 0x0a, 0x0f, 0x02,
/* AD */ 0x18, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00,
/* AE */ 0x00, 0x33, 0x66, 0xcc, 0xcc, 0x66, 0x33, 0x00,
/* AF */ 0x00, 0xcc, 0x66, 0x33, 0x33, 0x66, 0xcc, 0x00,
/* B0 */ 0x22, 0x88, 0x22, 0x88, 0x22, 0x88, 0x22, 0x88,
/* B1 */ 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa,
/* B2 */ 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77, 0xdd, 0x77,
/* B3 */ 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
/* B4 */ 0x18, 0x18, 0x18, 0xf8, 0x18, 0x18, 0x18, 0x18,
/* B5 */ 0x18, 0x18, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18,
/* B6 */ 0x66, 0x66, 0x66, 0xe6, 0x66, 0x66, 0x66, 0x66,
/* B7 */ 0x00, 0x00, 0x00, 0xfe, 0x66, 0x66, 0x66, 0x66,
/* B8 */ 0x00, 0x00, 0xf8, 0x18, 0xf8, 0x18, 0x18, 0x18,
/* B9 */ 0x66, 0x66, 0xe6, 0x06, 0xe6, 0x66, 0x66, 0x66,
/* BA */ 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66,
/* BB */ 0x00, 0x00, 0xfe, 0x06, 0xe6, 0x66, 0x66, 0x66,
/* BC */ 0x66, 0x66, 0xe6, 0x06, 0xfe, 0x00, 0x00, 0x00,
/* BD */ 0x66, 0x66, 0x66, 0xfe, 0x00, 0x00, 0x00, 0x00,
/* BE */ 0x18, 0x18, 0xf8, 0x18, 0xf8, 0x00, 0x00, 0x00,
/* BF */ 0x00, 0x00, 0x00, 0xf8, 0x18, 0x18, 0x18, 0x18,
/* C0 */ 0x18, 0x18, 0x18, 0x1f, 0x00, 0x00, 0x00, 0x00,
/* C1 */ 0x18, 0x18, 0x18, 0xff, 0x00, 0x00, 0x00, 0x00,
/* C2 */ 0x00, 0x00, 0x00, 0xff, 0x18, 0x18, 0x18, 0x18,
/* C3 */ 0x18, 0x18, 0x18, 0x1f, 0x18, 0x18, 0x18, 0x18,
/* C4 */ 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00,
/* C5 */ 0x18, 0x18, 0x18, 0xff, 0x18, 0x18, 0x18, 0x18,
/* C6 */ 0x18, 0x18, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18,
/* C7 */ 0x66, 0x66, 0x66, 0x67, 0x66, 0x66, 0x66, 0x66,
/* C8 */ 0x66, 0x66, 0x67, 0x60, 0x7f, 0x00, 0x00, 0x00,
/* C9 */ 0x00, 0x00, 0x7f, 0x60, 0x67, 0x66, 0x66, 0x66,
/* CA */ 0x66, 0x66, 0xe7, 0x00, 0xff, 0x00, 0x00, 0x00,
/* CB */ 0x00, 0x00, 0xff, 0x00, 0xe7, 0x66, 0x66, 0x66,
/* CC */ 0x66, 0x66, 0x67, 0x60, 0x67, 0x66, 0x66, 0x66,
/* CD */ 0x00, 0x00, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00,
/* CE */ 0x66, 0x66, 0xe7, 0x00, 0xe7, 0x66, 0x66, 0x66,
/* CF */ 0x18, 0x18, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00,
/* D0 */ 0x66, 0x66, 0x66, 0xff, 0x00, 0x00, 0x00, 0x00,
/* D1 */ 0x00, 0x00, 0xff, 0x00, 0xff, 0x18, 0x18, 0x18,
/* D2 */ 0x00, 0x00, 0x00, 0xff, 0x66, 0x66, 0x66, 0x66,
/* D3 */ 0x66, 0x66, 0x66, 0x7f, 0x00, 0x00, 0x00, 0x00,
/* D4 */ 0x18, 0x18, 0x1f, 0x18, 0x1f, 0x00, 0x00, 0x00,
/* D5 */ 0x00, 0x00, 0x1f, 0x18, 0x1f, 0x18, 0x18, 0x18,
/* D6 */ 0x00, 0x00, 0x00, 0x7f, 0x66, 0x66, 0x66, 0x66,
/* D7 */ 0x66, 0x66, 0x66, 0xff, 0x66, 0x66, 0x66, 0x66,
/* D8 */ 0x18, 0x18, 0xff, 0x18, 0xff, 0x18, 0x18, 0x18,
/* D9 */ 0x18, 0x18, 0x18, 0xf8, 0x00, 0x00, 0x00, 0x00,
/* DA */ 0x00, 0x00, 0x00, 0x1f, 0x18, 0x18, 0x18, 0x18,
/* DB */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
/* DC */ 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
/* DD */ 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0,
/* DE */ 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
/* DF */ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
/* E0 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E1 */ 0x3c, 0x66, 0x66, 0x6c, 0x66, 0x66, 0x6c, 0xc0,
/* E2 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E3 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E4 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E5 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E6 */ 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x3e, 0x60,
/* E7 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E8 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* E9 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* EA */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* EB */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* EC */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* ED */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* EE */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* EF */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F0 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F1 */ 0x18, 0x18, 0x7e, 0x18, 0x18, 0x00, 0x7e, 0x00,
/* F2 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F3 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F4 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F5 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F6 */ 0x00, 0x18, 0x00, 0xff, 0x00, 0x18, 0x00, 0x00,
/* F7 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* F8 */ 0x3c, 0x66, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00,
/* F9 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* FA */ 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00,
/* FB */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* FC */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* FD */ 0x38, 0x04, 0x18, 0x20, 0x3c, 0x00, 0x00, 0x00,
/* FE */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00,
/* FF */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
const struct font_desc font_acorn_8x8 = {
.idx = ACORN8x8_IDX,
.name = "Acorn8x8",
.width = 8,
.height = 8,
.data = acorndata_8x8,
#ifdef CONFIG_ARCH_ACORN
.pref = 20,
#else
.pref = 0,
#endif
};
| gpl-2.0 |
zidier215/Telegram | TMessagesProj/jni/boringssl/crypto/asn1/tasn_dec.c | 100 | 32744 | /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
* The implementation was written so as to conform with Netscapes SSL.
*
* This library is free for commercial and non-commercial use as long as
* the following conditions are aheared to. The following conditions
* apply to all code found in this distribution, be it the RC4, RSA,
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
* included with this distribution is covered by the same copyright terms
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed.
* If this package is used in a product, Eric Young should be given attribution
* as the author of the parts of the library used.
* This can be in the form of a textual message at program startup or
* in documentation (online or textual) provided with the package.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* "This product includes cryptographic software written by
* Eric Young (eay@cryptsoft.com)"
* The word 'cryptographic' can be left out if the rouines from the library
* being used are not cryptographic related :-).
* 4. If you include any Windows specific code (or a derivative thereof) from
* the apps directory (application code) you must include an acknowledgement:
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
*
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The licence and distribution terms for any publically available version or
* derivative of this code cannot be changed. i.e. this code cannot simply be
* copied and put under another distribution licence
* [including the GNU Public Licence.] */
#include <openssl/asn1.h>
#include <string.h>
#include <openssl/asn1t.h>
#include <openssl/buf.h>
#include <openssl/err.h>
#include <openssl/mem.h>
#include "../internal.h"
static int asn1_check_eoc(const unsigned char **in, long len);
static int asn1_find_end(const unsigned char **in, long len, char inf);
static int asn1_collect(BUF_MEM *buf, const unsigned char **in, long len,
char inf, int tag, int aclass, int depth);
static int collect_data(BUF_MEM *buf, const unsigned char **p, long plen);
static int asn1_check_tlen(long *olen, int *otag, unsigned char *oclass,
char *inf, char *cst,
const unsigned char **in, long len,
int exptag, int expclass, char opt,
ASN1_TLC *ctx);
static int asn1_template_ex_d2i(ASN1_VALUE **pval,
const unsigned char **in, long len,
const ASN1_TEMPLATE *tt, char opt,
ASN1_TLC *ctx);
static int asn1_template_noexp_d2i(ASN1_VALUE **val,
const unsigned char **in, long len,
const ASN1_TEMPLATE *tt, char opt,
ASN1_TLC *ctx);
static int asn1_d2i_ex_primitive(ASN1_VALUE **pval,
const unsigned char **in, long len,
const ASN1_ITEM *it,
int tag, int aclass, char opt, ASN1_TLC *ctx);
/* Table to convert tags to bit values, used for MSTRING type */
static const unsigned long tag2bit[32] = {
0, 0, 0, B_ASN1_BIT_STRING, /* tags 0 - 3 */
B_ASN1_OCTET_STRING, 0, 0, B_ASN1_UNKNOWN,/* tags 4- 7 */
B_ASN1_UNKNOWN, B_ASN1_UNKNOWN, B_ASN1_UNKNOWN, B_ASN1_UNKNOWN,/* tags 8-11 */
B_ASN1_UTF8STRING,B_ASN1_UNKNOWN,B_ASN1_UNKNOWN,B_ASN1_UNKNOWN,/* tags 12-15 */
B_ASN1_SEQUENCE,0,B_ASN1_NUMERICSTRING,B_ASN1_PRINTABLESTRING, /* tags 16-19 */
B_ASN1_T61STRING,B_ASN1_VIDEOTEXSTRING,B_ASN1_IA5STRING, /* tags 20-22 */
B_ASN1_UTCTIME, B_ASN1_GENERALIZEDTIME, /* tags 23-24 */
B_ASN1_GRAPHICSTRING,B_ASN1_ISO64STRING,B_ASN1_GENERALSTRING, /* tags 25-27 */
B_ASN1_UNIVERSALSTRING,B_ASN1_UNKNOWN,B_ASN1_BMPSTRING,B_ASN1_UNKNOWN, /* tags 28-31 */
};
unsigned long ASN1_tag2bit(int tag)
{
if ((tag < 0) || (tag > 30)) return 0;
return tag2bit[tag];
}
/* Macro to initialize and invalidate the cache */
#define asn1_tlc_clear(c) if (c) (c)->valid = 0
/* Version to avoid compiler warning about 'c' always non-NULL */
#define asn1_tlc_clear_nc(c) (c)->valid = 0
/* Decode an ASN1 item, this currently behaves just
* like a standard 'd2i' function. 'in' points to
* a buffer to read the data from, in future we will
* have more advanced versions that can input data
* a piece at a time and this will simply be a special
* case.
*/
ASN1_VALUE *ASN1_item_d2i(ASN1_VALUE **pval,
const unsigned char **in, long len, const ASN1_ITEM *it)
{
ASN1_TLC c;
ASN1_VALUE *ptmpval = NULL;
if (!pval)
pval = &ptmpval;
asn1_tlc_clear_nc(&c);
if (ASN1_item_ex_d2i(pval, in, len, it, -1, 0, 0, &c) > 0)
return *pval;
return NULL;
}
int ASN1_template_d2i(ASN1_VALUE **pval,
const unsigned char **in, long len, const ASN1_TEMPLATE *tt)
{
ASN1_TLC c;
asn1_tlc_clear_nc(&c);
return asn1_template_ex_d2i(pval, in, len, tt, 0, &c);
}
/* Decode an item, taking care of IMPLICIT tagging, if any.
* If 'opt' set and tag mismatch return -1 to handle OPTIONAL
*/
int ASN1_item_ex_d2i(ASN1_VALUE **pval, const unsigned char **in, long len,
const ASN1_ITEM *it,
int tag, int aclass, char opt, ASN1_TLC *ctx)
{
const ASN1_TEMPLATE *tt, *errtt = NULL;
const ASN1_COMPAT_FUNCS *cf;
const ASN1_EXTERN_FUNCS *ef;
const ASN1_AUX *aux = it->funcs;
ASN1_aux_cb *asn1_cb;
const unsigned char *p = NULL, *q;
unsigned char *wp=NULL; /* BIG FAT WARNING! BREAKS CONST WHERE USED */
unsigned char imphack = 0, oclass;
char seq_eoc, seq_nolen, cst, isopt;
long tmplen;
int i;
int otag;
int ret = 0;
ASN1_VALUE **pchptr, *ptmpval;
if (!pval)
return 0;
if (aux && aux->asn1_cb)
asn1_cb = aux->asn1_cb;
else asn1_cb = 0;
switch(it->itype)
{
case ASN1_ITYPE_PRIMITIVE:
if (it->templates)
{
/* tagging or OPTIONAL is currently illegal on an item
* template because the flags can't get passed down.
* In practice this isn't a problem: we include the
* relevant flags from the item template in the
* template itself.
*/
if ((tag != -1) || opt)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_ILLEGAL_OPTIONS_ON_ITEM_TEMPLATE);
goto err;
}
return asn1_template_ex_d2i(pval, in, len,
it->templates, opt, ctx);
}
return asn1_d2i_ex_primitive(pval, in, len, it,
tag, aclass, opt, ctx);
break;
case ASN1_ITYPE_MSTRING:
p = *in;
/* Just read in tag and class */
ret = asn1_check_tlen(NULL, &otag, &oclass, NULL, NULL,
&p, len, -1, 0, 1, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
/* Must be UNIVERSAL class */
if (oclass != V_ASN1_UNIVERSAL)
{
/* If OPTIONAL, assume this is OK */
if (opt) return -1;
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MSTRING_NOT_UNIVERSAL);
goto err;
}
/* Check tag matches bit map */
if (!(ASN1_tag2bit(otag) & it->utype))
{
/* If OPTIONAL, assume this is OK */
if (opt)
return -1;
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MSTRING_WRONG_TAG);
goto err;
}
return asn1_d2i_ex_primitive(pval, in, len,
it, otag, 0, 0, ctx);
case ASN1_ITYPE_EXTERN:
/* Use new style d2i */
ef = it->funcs;
return ef->asn1_ex_d2i(pval, in, len,
it, tag, aclass, opt, ctx);
case ASN1_ITYPE_COMPAT:
/* we must resort to old style evil hackery */
cf = it->funcs;
/* If OPTIONAL see if it is there */
if (opt)
{
int exptag;
p = *in;
if (tag == -1)
exptag = it->utype;
else exptag = tag;
/* Don't care about anything other than presence
* of expected tag */
ret = asn1_check_tlen(NULL, NULL, NULL, NULL, NULL,
&p, len, exptag, aclass, 1, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
if (ret == -1)
return -1;
}
/* This is the old style evil hack IMPLICIT handling:
* since the underlying code is expecting a tag and
* class other than the one present we change the
* buffer temporarily then change it back afterwards.
* This doesn't and never did work for tags > 30.
*
* Yes this is *horrible* but it is only needed for
* old style d2i which will hopefully not be around
* for much longer.
* FIXME: should copy the buffer then modify it so
* the input buffer can be const: we should *always*
* copy because the old style d2i might modify the
* buffer.
*/
if (tag != -1)
{
wp = *(unsigned char **)in;
imphack = *wp;
if (p == NULL)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
*wp = (unsigned char)((*p & V_ASN1_CONSTRUCTED)
| it->utype);
}
ptmpval = cf->asn1_d2i(pval, in, len);
if (tag != -1)
*wp = imphack;
if (ptmpval)
return 1;
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
case ASN1_ITYPE_CHOICE:
if (asn1_cb && !asn1_cb(ASN1_OP_D2I_PRE, pval, it, NULL))
goto auxerr;
if (*pval)
{
/* Free up and zero CHOICE value if initialised */
i = asn1_get_choice_selector(pval, it);
if ((i >= 0) && (i < it->tcount))
{
tt = it->templates + i;
pchptr = asn1_get_field_ptr(pval, tt);
ASN1_template_free(pchptr, tt);
asn1_set_choice_selector(pval, -1, it);
}
}
else if (!ASN1_item_ex_new(pval, it))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
/* CHOICE type, try each possibility in turn */
p = *in;
for (i = 0, tt=it->templates; i < it->tcount; i++, tt++)
{
pchptr = asn1_get_field_ptr(pval, tt);
/* We mark field as OPTIONAL so its absence
* can be recognised.
*/
ret = asn1_template_ex_d2i(pchptr, &p, len, tt, 1, ctx);
/* If field not present, try the next one */
if (ret == -1)
continue;
/* If positive return, read OK, break loop */
if (ret > 0)
break;
/* Otherwise must be an ASN1 parsing error */
errtt = tt;
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
/* Did we fall off the end without reading anything? */
if (i == it->tcount)
{
/* If OPTIONAL, this is OK */
if (opt)
{
/* Free and zero it */
ASN1_item_ex_free(pval, it);
return -1;
}
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NO_MATCHING_CHOICE_TYPE);
goto err;
}
asn1_set_choice_selector(pval, i, it);
*in = p;
if (asn1_cb && !asn1_cb(ASN1_OP_D2I_POST, pval, it, NULL))
goto auxerr;
return 1;
case ASN1_ITYPE_NDEF_SEQUENCE:
case ASN1_ITYPE_SEQUENCE:
p = *in;
tmplen = len;
/* If no IMPLICIT tagging set to SEQUENCE, UNIVERSAL */
if (tag == -1)
{
tag = V_ASN1_SEQUENCE;
aclass = V_ASN1_UNIVERSAL;
}
/* Get SEQUENCE length and update len, p */
ret = asn1_check_tlen(&len, NULL, NULL, &seq_eoc, &cst,
&p, len, tag, aclass, opt, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
else if (ret == -1)
return -1;
if (aux && (aux->flags & ASN1_AFLG_BROKEN))
{
len = tmplen - (p - *in);
seq_nolen = 1;
}
/* If indefinite we don't do a length check */
else seq_nolen = seq_eoc;
if (!cst)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_SEQUENCE_NOT_CONSTRUCTED);
goto err;
}
if (!*pval && !ASN1_item_ex_new(pval, it))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
if (asn1_cb && !asn1_cb(ASN1_OP_D2I_PRE, pval, it, NULL))
goto auxerr;
/* Free up and zero any ADB found */
for (i = 0, tt = it->templates; i < it->tcount; i++, tt++)
{
if (tt->flags & ASN1_TFLG_ADB_MASK)
{
const ASN1_TEMPLATE *seqtt;
ASN1_VALUE **pseqval;
seqtt = asn1_do_adb(pval, tt, 1);
pseqval = asn1_get_field_ptr(pval, seqtt);
ASN1_template_free(pseqval, seqtt);
}
}
/* Get each field entry */
for (i = 0, tt = it->templates; i < it->tcount; i++, tt++)
{
const ASN1_TEMPLATE *seqtt;
ASN1_VALUE **pseqval;
seqtt = asn1_do_adb(pval, tt, 1);
if (!seqtt)
goto err;
pseqval = asn1_get_field_ptr(pval, seqtt);
/* Have we ran out of data? */
if (!len)
break;
q = p;
if (asn1_check_eoc(&p, len))
{
if (!seq_eoc)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_UNEXPECTED_EOC);
goto err;
}
len -= p - q;
seq_eoc = 0;
q = p;
break;
}
/* This determines the OPTIONAL flag value. The field
* cannot be omitted if it is the last of a SEQUENCE
* and there is still data to be read. This isn't
* strictly necessary but it increases efficiency in
* some cases.
*/
if (i == (it->tcount - 1))
isopt = 0;
else isopt = (char)(seqtt->flags & ASN1_TFLG_OPTIONAL);
/* attempt to read in field, allowing each to be
* OPTIONAL */
ret = asn1_template_ex_d2i(pseqval, &p, len,
seqtt, isopt, ctx);
if (!ret)
{
errtt = seqtt;
goto err;
}
else if (ret == -1)
{
/* OPTIONAL component absent.
* Free and zero the field.
*/
ASN1_template_free(pseqval, seqtt);
continue;
}
/* Update length */
len -= p - q;
}
/* Check for EOC if expecting one */
if (seq_eoc && !asn1_check_eoc(&p, len))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MISSING_EOC);
goto err;
}
/* Check all data read */
if (!seq_nolen && len)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_SEQUENCE_LENGTH_MISMATCH);
goto err;
}
/* If we get here we've got no more data in the SEQUENCE,
* however we may not have read all fields so check all
* remaining are OPTIONAL and clear any that are.
*/
for (; i < it->tcount; tt++, i++)
{
const ASN1_TEMPLATE *seqtt;
seqtt = asn1_do_adb(pval, tt, 1);
if (!seqtt)
goto err;
if (seqtt->flags & ASN1_TFLG_OPTIONAL)
{
ASN1_VALUE **pseqval;
pseqval = asn1_get_field_ptr(pval, seqtt);
ASN1_template_free(pseqval, seqtt);
}
else
{
errtt = seqtt;
OPENSSL_PUT_ERROR(ASN1, ASN1_R_FIELD_MISSING);
goto err;
}
}
/* Save encoding */
if (!asn1_enc_save(pval, *in, p - *in, it))
goto auxerr;
*in = p;
if (asn1_cb && !asn1_cb(ASN1_OP_D2I_POST, pval, it, NULL))
goto auxerr;
return 1;
default:
return 0;
}
auxerr:
OPENSSL_PUT_ERROR(ASN1, ASN1_R_AUX_ERROR);
err:
ASN1_item_ex_free(pval, it);
if (errtt)
ERR_add_error_data(4, "Field=", errtt->field_name,
", Type=", it->sname);
else
ERR_add_error_data(2, "Type=", it->sname);
return 0;
}
/* Templates are handled with two separate functions.
* One handles any EXPLICIT tag and the other handles the rest.
*/
static int asn1_template_ex_d2i(ASN1_VALUE **val,
const unsigned char **in, long inlen,
const ASN1_TEMPLATE *tt, char opt,
ASN1_TLC *ctx)
{
int flags, aclass;
int ret;
long len;
const unsigned char *p, *q;
char exp_eoc;
if (!val)
return 0;
flags = tt->flags;
aclass = flags & ASN1_TFLG_TAG_CLASS;
p = *in;
/* Check if EXPLICIT tag expected */
if (flags & ASN1_TFLG_EXPTAG)
{
char cst;
/* Need to work out amount of data available to the inner
* content and where it starts: so read in EXPLICIT header to
* get the info.
*/
ret = asn1_check_tlen(&len, NULL, NULL, &exp_eoc, &cst,
&p, inlen, tt->tag, aclass, opt, ctx);
q = p;
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
else if (ret == -1)
return -1;
if (!cst)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_EXPLICIT_TAG_NOT_CONSTRUCTED);
return 0;
}
/* We've found the field so it can't be OPTIONAL now */
ret = asn1_template_noexp_d2i(val, &p, len, tt, 0, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
/* We read the field in OK so update length */
len -= p - q;
if (exp_eoc)
{
/* If NDEF we must have an EOC here */
if (!asn1_check_eoc(&p, len))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MISSING_EOC);
goto err;
}
}
else
{
/* Otherwise we must hit the EXPLICIT tag end or its
* an error */
if (len)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_EXPLICIT_LENGTH_MISMATCH);
goto err;
}
}
}
else
return asn1_template_noexp_d2i(val, in, inlen,
tt, opt, ctx);
*in = p;
return 1;
err:
ASN1_template_free(val, tt);
return 0;
}
static int asn1_template_noexp_d2i(ASN1_VALUE **val,
const unsigned char **in, long len,
const ASN1_TEMPLATE *tt, char opt,
ASN1_TLC *ctx)
{
int flags, aclass;
int ret;
const unsigned char *p;
if (!val)
return 0;
flags = tt->flags;
aclass = flags & ASN1_TFLG_TAG_CLASS;
p = *in;
if (flags & ASN1_TFLG_SK_MASK)
{
/* SET OF, SEQUENCE OF */
int sktag, skaclass;
char sk_eoc;
/* First work out expected inner tag value */
if (flags & ASN1_TFLG_IMPTAG)
{
sktag = tt->tag;
skaclass = aclass;
}
else
{
skaclass = V_ASN1_UNIVERSAL;
if (flags & ASN1_TFLG_SET_OF)
sktag = V_ASN1_SET;
else
sktag = V_ASN1_SEQUENCE;
}
/* Get the tag */
ret = asn1_check_tlen(&len, NULL, NULL, &sk_eoc, NULL,
&p, len, sktag, skaclass, opt, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
else if (ret == -1)
return -1;
if (!*val)
*val = (ASN1_VALUE *)sk_new_null();
else
{
/* We've got a valid STACK: free up any items present */
STACK_OF(ASN1_VALUE) *sktmp
= (STACK_OF(ASN1_VALUE) *)*val;
ASN1_VALUE *vtmp;
while(sk_ASN1_VALUE_num(sktmp) > 0)
{
vtmp = sk_ASN1_VALUE_pop(sktmp);
ASN1_item_ex_free(&vtmp,
ASN1_ITEM_ptr(tt->item));
}
}
if (!*val)
{
OPENSSL_PUT_ERROR(ASN1, ERR_R_MALLOC_FAILURE);
goto err;
}
/* Read as many items as we can */
while(len > 0)
{
ASN1_VALUE *skfield;
const unsigned char *q = p;
/* See if EOC found */
if (asn1_check_eoc(&p, len))
{
if (!sk_eoc)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_UNEXPECTED_EOC);
goto err;
}
len -= p - q;
sk_eoc = 0;
break;
}
skfield = NULL;
if (!ASN1_item_ex_d2i(&skfield, &p, len,
ASN1_ITEM_ptr(tt->item),
-1, 0, 0, ctx))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
len -= p - q;
if (!sk_ASN1_VALUE_push((STACK_OF(ASN1_VALUE) *)*val,
skfield))
{
OPENSSL_PUT_ERROR(ASN1, ERR_R_MALLOC_FAILURE);
goto err;
}
}
if (sk_eoc)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MISSING_EOC);
goto err;
}
}
else if (flags & ASN1_TFLG_IMPTAG)
{
/* IMPLICIT tagging */
ret = ASN1_item_ex_d2i(val, &p, len,
ASN1_ITEM_ptr(tt->item), tt->tag, aclass, opt, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
else if (ret == -1)
return -1;
}
else
{
/* Nothing special */
ret = ASN1_item_ex_d2i(val, &p, len, ASN1_ITEM_ptr(tt->item),
-1, 0, opt, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
goto err;
}
else if (ret == -1)
return -1;
}
*in = p;
return 1;
err:
ASN1_template_free(val, tt);
return 0;
}
static int asn1_d2i_ex_primitive(ASN1_VALUE **pval,
const unsigned char **in, long inlen,
const ASN1_ITEM *it,
int tag, int aclass, char opt, ASN1_TLC *ctx)
OPENSSL_SUPPRESS_POTENTIALLY_UNINITIALIZED_WARNINGS
{
int ret = 0, utype;
long plen;
char cst, inf, free_cont = 0;
const unsigned char *p;
BUF_MEM buf;
const unsigned char *cont = NULL;
long len;
if (!pval)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_ILLEGAL_NULL);
return 0; /* Should never happen */
}
if (it->itype == ASN1_ITYPE_MSTRING)
{
utype = tag;
tag = -1;
}
else
utype = it->utype;
if (utype == V_ASN1_ANY)
{
/* If type is ANY need to figure out type from tag */
unsigned char oclass;
if (tag >= 0)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_ILLEGAL_TAGGED_ANY);
return 0;
}
if (opt)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_ILLEGAL_OPTIONAL_ANY);
return 0;
}
p = *in;
ret = asn1_check_tlen(NULL, &utype, &oclass, NULL, NULL,
&p, inlen, -1, 0, 0, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
if (oclass != V_ASN1_UNIVERSAL)
utype = V_ASN1_OTHER;
}
if (tag == -1)
{
tag = utype;
aclass = V_ASN1_UNIVERSAL;
}
p = *in;
/* Check header */
ret = asn1_check_tlen(&plen, NULL, NULL, &inf, &cst,
&p, inlen, tag, aclass, opt, ctx);
if (!ret)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
else if (ret == -1)
return -1;
ret = 0;
/* SEQUENCE, SET and "OTHER" are left in encoded form */
if ((utype == V_ASN1_SEQUENCE)
|| (utype == V_ASN1_SET) || (utype == V_ASN1_OTHER))
{
/* Clear context cache for type OTHER because the auto clear
* when we have a exact match wont work
*/
if (utype == V_ASN1_OTHER)
{
asn1_tlc_clear(ctx);
}
/* SEQUENCE and SET must be constructed */
else if (!cst)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_TYPE_NOT_CONSTRUCTED);
return 0;
}
cont = *in;
/* If indefinite length constructed find the real end */
if (inf)
{
if (!asn1_find_end(&p, plen, inf))
goto err;
len = p - cont;
}
else
{
len = p - cont + plen;
p += plen;
buf.data = NULL;
}
}
else if (cst)
{
if (utype == V_ASN1_NULL || utype == V_ASN1_BOOLEAN
|| utype == V_ASN1_OBJECT || utype == V_ASN1_INTEGER
|| utype == V_ASN1_ENUMERATED)
{
/* These types only have primitive encodings. */
OPENSSL_PUT_ERROR(ASN1, ASN1_R_TYPE_NOT_PRIMITIVE);
return 0;
}
buf.length = 0;
buf.max = 0;
buf.data = NULL;
/* Should really check the internal tags are correct but
* some things may get this wrong. The relevant specs
* say that constructed string types should be OCTET STRINGs
* internally irrespective of the type. So instead just check
* for UNIVERSAL class and ignore the tag.
*/
if (!asn1_collect(&buf, &p, plen, inf, -1, V_ASN1_UNIVERSAL, 0))
{
free_cont = 1;
goto err;
}
len = buf.length;
/* Append a final null to string */
if (!BUF_MEM_grow_clean(&buf, len + 1))
{
OPENSSL_PUT_ERROR(ASN1, ERR_R_MALLOC_FAILURE);
return 0;
}
buf.data[len] = 0;
cont = (const unsigned char *)buf.data;
free_cont = 1;
}
else
{
cont = p;
len = plen;
p += plen;
}
/* We now have content length and type: translate into a structure */
if (!asn1_ex_c2i(pval, cont, len, utype, &free_cont, it))
goto err;
*in = p;
ret = 1;
err:
if (free_cont && buf.data) OPENSSL_free(buf.data);
return ret;
}
/* Translate ASN1 content octets into a structure */
int asn1_ex_c2i(ASN1_VALUE **pval, const unsigned char *cont, int len,
int utype, char *free_cont, const ASN1_ITEM *it)
{
ASN1_VALUE **opval = NULL;
ASN1_STRING *stmp;
ASN1_TYPE *typ = NULL;
int ret = 0;
const ASN1_PRIMITIVE_FUNCS *pf;
ASN1_INTEGER **tint;
pf = it->funcs;
if (pf && pf->prim_c2i)
return pf->prim_c2i(pval, cont, len, utype, free_cont, it);
/* If ANY type clear type and set pointer to internal value */
if (it->utype == V_ASN1_ANY)
{
if (!*pval)
{
typ = ASN1_TYPE_new();
if (typ == NULL)
goto err;
*pval = (ASN1_VALUE *)typ;
}
else
typ = (ASN1_TYPE *)*pval;
if (utype != typ->type)
ASN1_TYPE_set(typ, utype, NULL);
opval = pval;
pval = &typ->value.asn1_value;
}
switch(utype)
{
case V_ASN1_OBJECT:
if (!c2i_ASN1_OBJECT((ASN1_OBJECT **)pval, &cont, len))
goto err;
break;
case V_ASN1_NULL:
if (len)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NULL_IS_WRONG_LENGTH);
goto err;
}
*pval = (ASN1_VALUE *)1;
break;
case V_ASN1_BOOLEAN:
if (len != 1)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_BOOLEAN_IS_WRONG_LENGTH);
goto err;
}
else
{
ASN1_BOOLEAN *tbool;
tbool = (ASN1_BOOLEAN *)pval;
*tbool = *cont;
}
break;
case V_ASN1_BIT_STRING:
if (!c2i_ASN1_BIT_STRING((ASN1_BIT_STRING **)pval, &cont, len))
goto err;
break;
case V_ASN1_INTEGER:
case V_ASN1_NEG_INTEGER:
case V_ASN1_ENUMERATED:
case V_ASN1_NEG_ENUMERATED:
tint = (ASN1_INTEGER **)pval;
if (!c2i_ASN1_INTEGER(tint, &cont, len))
goto err;
/* Fixup type to match the expected form */
(*tint)->type = utype | ((*tint)->type & V_ASN1_NEG);
break;
case V_ASN1_OCTET_STRING:
case V_ASN1_NUMERICSTRING:
case V_ASN1_PRINTABLESTRING:
case V_ASN1_T61STRING:
case V_ASN1_VIDEOTEXSTRING:
case V_ASN1_IA5STRING:
case V_ASN1_UTCTIME:
case V_ASN1_GENERALIZEDTIME:
case V_ASN1_GRAPHICSTRING:
case V_ASN1_VISIBLESTRING:
case V_ASN1_GENERALSTRING:
case V_ASN1_UNIVERSALSTRING:
case V_ASN1_BMPSTRING:
case V_ASN1_UTF8STRING:
case V_ASN1_OTHER:
case V_ASN1_SET:
case V_ASN1_SEQUENCE:
default:
if (utype == V_ASN1_BMPSTRING && (len & 1))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_BMPSTRING_IS_WRONG_LENGTH);
goto err;
}
if (utype == V_ASN1_UNIVERSALSTRING && (len & 3))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_UNIVERSALSTRING_IS_WRONG_LENGTH);
goto err;
}
/* All based on ASN1_STRING and handled the same */
if (!*pval)
{
stmp = ASN1_STRING_type_new(utype);
if (!stmp)
{
OPENSSL_PUT_ERROR(ASN1, ERR_R_MALLOC_FAILURE);
goto err;
}
*pval = (ASN1_VALUE *)stmp;
}
else
{
stmp = (ASN1_STRING *)*pval;
stmp->type = utype;
}
/* If we've already allocated a buffer use it */
if (*free_cont)
{
if (stmp->data)
OPENSSL_free(stmp->data);
stmp->data = (unsigned char *)cont; /* UGLY CAST! RL */
stmp->length = len;
*free_cont = 0;
}
else
{
if (!ASN1_STRING_set(stmp, cont, len))
{
OPENSSL_PUT_ERROR(ASN1, ERR_R_MALLOC_FAILURE);
ASN1_STRING_free(stmp);
*pval = NULL;
goto err;
}
}
break;
}
/* If ASN1_ANY and NULL type fix up value */
if (typ && (utype == V_ASN1_NULL))
typ->value.ptr = NULL;
ret = 1;
err:
if (!ret)
{
ASN1_TYPE_free(typ);
if (opval)
*opval = NULL;
}
return ret;
}
/* This function finds the end of an ASN1 structure when passed its maximum
* length, whether it is indefinite length and a pointer to the content.
* This is more efficient than calling asn1_collect because it does not
* recurse on each indefinite length header.
*/
static int asn1_find_end(const unsigned char **in, long len, char inf)
{
int expected_eoc;
long plen;
const unsigned char *p = *in, *q;
/* If not indefinite length constructed just add length */
if (inf == 0)
{
*in += len;
return 1;
}
expected_eoc = 1;
/* Indefinite length constructed form. Find the end when enough EOCs
* are found. If more indefinite length constructed headers
* are encountered increment the expected eoc count otherwise just
* skip to the end of the data.
*/
while (len > 0)
{
if(asn1_check_eoc(&p, len))
{
expected_eoc--;
if (expected_eoc == 0)
break;
len -= 2;
continue;
}
q = p;
/* Just read in a header: only care about the length */
if(!asn1_check_tlen(&plen, NULL, NULL, &inf, NULL, &p, len,
-1, 0, 0, NULL))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
if (inf)
expected_eoc++;
else
p += plen;
len -= p - q;
}
if (expected_eoc)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MISSING_EOC);
return 0;
}
*in = p;
return 1;
}
/* This function collects the asn1 data from a constructred string
* type into a buffer. The values of 'in' and 'len' should refer
* to the contents of the constructed type and 'inf' should be set
* if it is indefinite length.
*/
#ifndef ASN1_MAX_STRING_NEST
/* This determines how many levels of recursion are permitted in ASN1
* string types. If it is not limited stack overflows can occur. If set
* to zero no recursion is allowed at all. Although zero should be adequate
* examples exist that require a value of 1. So 5 should be more than enough.
*/
#define ASN1_MAX_STRING_NEST 5
#endif
static int asn1_collect(BUF_MEM *buf, const unsigned char **in, long len,
char inf, int tag, int aclass, int depth)
{
const unsigned char *p, *q;
long plen;
char cst, ininf;
p = *in;
inf &= 1;
/* If no buffer and not indefinite length constructed just pass over
* the encoded data */
if (!buf && !inf)
{
*in += len;
return 1;
}
while(len > 0)
{
q = p;
/* Check for EOC */
if (asn1_check_eoc(&p, len))
{
/* EOC is illegal outside indefinite length
* constructed form */
if (!inf)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_UNEXPECTED_EOC);
return 0;
}
inf = 0;
break;
}
if (!asn1_check_tlen(&plen, NULL, NULL, &ininf, &cst, &p,
len, tag, aclass, 0, NULL))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_ERROR);
return 0;
}
/* If indefinite length constructed update max length */
if (cst)
{
if (depth >= ASN1_MAX_STRING_NEST)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_NESTED_ASN1_STRING);
return 0;
}
if (!asn1_collect(buf, &p, plen, ininf, tag, aclass,
depth + 1))
return 0;
}
else if (plen && !collect_data(buf, &p, plen))
return 0;
len -= p - q;
}
if (inf)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_MISSING_EOC);
return 0;
}
*in = p;
return 1;
}
static int collect_data(BUF_MEM *buf, const unsigned char **p, long plen)
{
int len;
if (buf)
{
len = buf->length;
if (!BUF_MEM_grow_clean(buf, len + plen))
{
OPENSSL_PUT_ERROR(ASN1, ERR_R_MALLOC_FAILURE);
return 0;
}
memcpy(buf->data + len, *p, plen);
}
*p += plen;
return 1;
}
/* Check for ASN1 EOC and swallow it if found */
static int asn1_check_eoc(const unsigned char **in, long len)
{
const unsigned char *p;
if (len < 2) return 0;
p = *in;
if (!p[0] && !p[1])
{
*in += 2;
return 1;
}
return 0;
}
/* Check an ASN1 tag and length: a bit like ASN1_get_object
* but it sets the length for indefinite length constructed
* form, we don't know the exact length but we can set an
* upper bound to the amount of data available minus the
* header length just read.
*/
static int asn1_check_tlen(long *olen, int *otag, unsigned char *oclass,
char *inf, char *cst,
const unsigned char **in, long len,
int exptag, int expclass, char opt,
ASN1_TLC *ctx)
{
int i;
int ptag, pclass;
long plen;
const unsigned char *p, *q;
p = *in;
q = p;
if (ctx && ctx->valid)
{
i = ctx->ret;
plen = ctx->plen;
pclass = ctx->pclass;
ptag = ctx->ptag;
p += ctx->hdrlen;
}
else
{
i = ASN1_get_object(&p, &plen, &ptag, &pclass, len);
if (ctx)
{
ctx->ret = i;
ctx->plen = plen;
ctx->pclass = pclass;
ctx->ptag = ptag;
ctx->hdrlen = p - q;
ctx->valid = 1;
/* If definite length, and no error, length +
* header can't exceed total amount of data available.
*/
if (!(i & 0x81) && ((plen + ctx->hdrlen) > len))
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_TOO_LONG);
asn1_tlc_clear(ctx);
return 0;
}
}
}
if (i & 0x80)
{
OPENSSL_PUT_ERROR(ASN1, ASN1_R_BAD_OBJECT_HEADER);
asn1_tlc_clear(ctx);
return 0;
}
if (exptag >= 0)
{
if ((exptag != ptag) || (expclass != pclass))
{
/* If type is OPTIONAL, not an error:
* indicate missing type.
*/
if (opt) return -1;
asn1_tlc_clear(ctx);
OPENSSL_PUT_ERROR(ASN1, ASN1_R_WRONG_TAG);
return 0;
}
/* We have a tag and class match:
* assume we are going to do something with it */
asn1_tlc_clear(ctx);
}
if (i & 1)
plen = len - (p - q);
if (inf)
*inf = i & 1;
if (cst)
*cst = i & V_ASN1_CONSTRUCTED;
if (olen)
*olen = plen;
if (oclass)
*oclass = pclass;
if (otag)
*otag = ptag;
*in = p;
return 1;
}
| gpl-2.0 |
siddhartha100/Kernel | drivers/mmc/host/sdhci.c | 100 | 95048 | /*
* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
*
* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* Thanks to the following companies for their support:
*
* - JMicron (hardware and technical support)
*/
#include <linux/delay.h>
#include <linux/highmem.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/scatterlist.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/leds.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/slot-gpio.h>
#include "sdhci.h"
#define DRIVER_NAME "sdhci"
#define DBG(f, x...) \
pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
defined(CONFIG_MMC_SDHCI_MODULE))
#define SDHCI_USE_LEDS_CLASS
#endif
#define MAX_TUNING_LOOP 40
static unsigned int debug_quirks = 0;
static unsigned int debug_quirks2;
static void sdhci_finish_data(struct sdhci_host *);
static void sdhci_finish_command(struct sdhci_host *);
static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
static void sdhci_tuning_timer(unsigned long data);
static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
static int sdhci_pre_dma_transfer(struct sdhci_host *host,
struct mmc_data *data,
struct sdhci_host_next *next);
static int sdhci_do_get_cd(struct sdhci_host *host);
#ifdef CONFIG_PM
static int sdhci_runtime_pm_get(struct sdhci_host *host);
static int sdhci_runtime_pm_put(struct sdhci_host *host);
static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
#else
static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
{
return 0;
}
static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
{
return 0;
}
static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
{
}
static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
{
}
#endif
static void sdhci_dumpregs(struct sdhci_host *host)
{
pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
mmc_hostname(host->mmc));
pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
sdhci_readl(host, SDHCI_DMA_ADDRESS),
sdhci_readw(host, SDHCI_HOST_VERSION));
pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
sdhci_readw(host, SDHCI_BLOCK_SIZE),
sdhci_readw(host, SDHCI_BLOCK_COUNT));
pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
sdhci_readl(host, SDHCI_ARGUMENT),
sdhci_readw(host, SDHCI_TRANSFER_MODE));
pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
sdhci_readl(host, SDHCI_PRESENT_STATE),
sdhci_readb(host, SDHCI_HOST_CONTROL));
pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
sdhci_readb(host, SDHCI_POWER_CONTROL),
sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
sdhci_readw(host, SDHCI_CLOCK_CONTROL));
pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
sdhci_readl(host, SDHCI_INT_STATUS));
pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
sdhci_readl(host, SDHCI_INT_ENABLE),
sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
sdhci_readw(host, SDHCI_ACMD12_ERR),
sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
sdhci_readl(host, SDHCI_CAPABILITIES),
sdhci_readl(host, SDHCI_CAPABILITIES_1));
pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
sdhci_readw(host, SDHCI_COMMAND),
sdhci_readl(host, SDHCI_MAX_CURRENT));
pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
sdhci_readw(host, SDHCI_HOST_CONTROL2));
if (host->flags & SDHCI_USE_ADMA) {
if (host->flags & SDHCI_USE_64_BIT_DMA)
pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
readl(host->ioaddr + SDHCI_ADMA_ERROR),
readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
else
pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
readl(host->ioaddr + SDHCI_ADMA_ERROR),
readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
}
pr_debug(DRIVER_NAME ": ===========================================\n");
}
/*****************************************************************************\
* *
* Low level functions *
* *
\*****************************************************************************/
static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
u32 present;
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
(host->mmc->caps & MMC_CAP_NONREMOVABLE))
return;
if (enable) {
present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
SDHCI_CARD_PRESENT;
host->ier |= present ? SDHCI_INT_CARD_REMOVE :
SDHCI_INT_CARD_INSERT;
} else {
host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
}
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
static void sdhci_enable_card_detection(struct sdhci_host *host)
{
sdhci_set_card_detection(host, true);
}
static void sdhci_disable_card_detection(struct sdhci_host *host)
{
sdhci_set_card_detection(host, false);
}
void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
if (mask & SDHCI_RESET_ALL) {
host->clock = 0;
/* Reset-all turns off SD Bus Power */
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_off(host);
}
/* Wait max 100 ms */
timeout = 100;
/* hw clears the bit when it's done */
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
pr_err("%s: Reset 0x%x never completed.\n",
mmc_hostname(host->mmc), (int)mask);
sdhci_dumpregs(host);
return;
}
timeout--;
mdelay(1);
}
}
EXPORT_SYMBOL_GPL(sdhci_reset);
static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
{
if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
SDHCI_CARD_PRESENT))
return;
}
host->ops->reset(host, mask);
if (mask & SDHCI_RESET_ALL) {
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host->ops->enable_dma)
host->ops->enable_dma(host);
}
/* Resetting the controller clears many */
host->preset_enabled = false;
}
}
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
static void sdhci_init(struct sdhci_host *host, int soft)
{
if (soft)
sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
else
sdhci_do_reset(host, SDHCI_RESET_ALL);
host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
SDHCI_INT_RESPONSE;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
if (soft) {
/* force clock reconfiguration */
host->clock = 0;
sdhci_set_ios(host->mmc, &host->mmc->ios);
}
}
static void sdhci_reinit(struct sdhci_host *host)
{
sdhci_init(host, 0);
/*
* Retuning stuffs are affected by different cards inserted and only
* applicable to UHS-I cards. So reset these fields to their initial
* value when card is removed.
*/
if (host->flags & SDHCI_USING_RETUNING_TIMER) {
host->flags &= ~SDHCI_USING_RETUNING_TIMER;
del_timer_sync(&host->tuning_timer);
host->flags &= ~SDHCI_NEEDS_RETUNING;
}
sdhci_enable_card_detection(host);
}
static void sdhci_activate_led(struct sdhci_host *host)
{
u8 ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl |= SDHCI_CTRL_LED;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
static void sdhci_deactivate_led(struct sdhci_host *host)
{
u8 ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_LED;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
#ifdef SDHCI_USE_LEDS_CLASS
static void sdhci_led_control(struct led_classdev *led,
enum led_brightness brightness)
{
struct sdhci_host *host = container_of(led, struct sdhci_host, led);
unsigned long flags;
spin_lock_irqsave(&host->lock, flags);
if (host->runtime_suspended)
goto out;
if (brightness == LED_OFF)
sdhci_deactivate_led(host);
else
sdhci_activate_led(host);
out:
spin_unlock_irqrestore(&host->lock, flags);
}
#endif
/*****************************************************************************\
* *
* Core functions *
* *
\*****************************************************************************/
static void sdhci_read_block_pio(struct sdhci_host *host)
{
unsigned long flags;
size_t blksize, len, chunk;
u32 uninitialized_var(scratch);
u8 *buf;
DBG("PIO reading\n");
blksize = host->data->blksz;
chunk = 0;
local_irq_save(flags);
while (blksize) {
if (!sg_miter_next(&host->sg_miter))
BUG();
len = min(host->sg_miter.length, blksize);
blksize -= len;
host->sg_miter.consumed = len;
buf = host->sg_miter.addr;
while (len) {
if (chunk == 0) {
scratch = sdhci_readl(host, SDHCI_BUFFER);
chunk = 4;
}
*buf = scratch & 0xFF;
buf++;
scratch >>= 8;
chunk--;
len--;
}
}
sg_miter_stop(&host->sg_miter);
local_irq_restore(flags);
}
static void sdhci_write_block_pio(struct sdhci_host *host)
{
unsigned long flags;
size_t blksize, len, chunk;
u32 scratch;
u8 *buf;
DBG("PIO writing\n");
blksize = host->data->blksz;
chunk = 0;
scratch = 0;
local_irq_save(flags);
while (blksize) {
if (!sg_miter_next(&host->sg_miter))
BUG();
len = min(host->sg_miter.length, blksize);
blksize -= len;
host->sg_miter.consumed = len;
buf = host->sg_miter.addr;
while (len) {
scratch |= (u32)*buf << (chunk * 8);
buf++;
chunk++;
len--;
if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
sdhci_writel(host, scratch, SDHCI_BUFFER);
chunk = 0;
scratch = 0;
}
}
}
sg_miter_stop(&host->sg_miter);
local_irq_restore(flags);
}
static void sdhci_transfer_pio(struct sdhci_host *host)
{
u32 mask;
BUG_ON(!host->data);
if (host->blocks == 0)
return;
if (host->data->flags & MMC_DATA_READ)
mask = SDHCI_DATA_AVAILABLE;
else
mask = SDHCI_SPACE_AVAILABLE;
/*
* Some controllers (JMicron JMB38x) mess up the buffer bits
* for transfers < 4 bytes. As long as it is just one block,
* we can ignore the bits.
*/
if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
(host->data->blocks == 1))
mask = ~0;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
udelay(100);
if (host->data->flags & MMC_DATA_READ)
sdhci_read_block_pio(host);
else
sdhci_write_block_pio(host);
host->blocks--;
if (host->blocks == 0)
break;
}
DBG("PIO transfer complete.\n");
}
static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
{
local_irq_save(*flags);
return kmap_atomic(sg_page(sg)) + sg->offset;
}
static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
{
kunmap_atomic(buffer);
local_irq_restore(*flags);
}
static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
dma_addr_t addr, int len, unsigned cmd)
{
struct sdhci_adma2_64_desc *dma_desc = desc;
/* 32-bit and 64-bit descriptors have these members in same position */
dma_desc->cmd = cpu_to_le16(cmd);
dma_desc->len = cpu_to_le16(len);
dma_desc->addr_lo = cpu_to_le32((u32)addr);
if (host->flags & SDHCI_USE_64_BIT_DMA)
dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
}
static void sdhci_adma_mark_end(void *desc)
{
struct sdhci_adma2_64_desc *dma_desc = desc;
/* 32-bit and 64-bit descriptors have 'cmd' in same position */
dma_desc->cmd |= cpu_to_le16(ADMA2_END);
}
static int sdhci_adma_table_pre(struct sdhci_host *host,
struct mmc_data *data)
{
int direction;
void *desc;
void *align;
dma_addr_t addr;
dma_addr_t align_addr;
int len, offset;
struct scatterlist *sg;
int i;
char *buffer;
unsigned long flags;
/*
* The spec does not specify endianness of descriptor table.
* We currently guess that it is LE.
*/
if (data->flags & MMC_DATA_READ)
direction = DMA_FROM_DEVICE;
else
direction = DMA_TO_DEVICE;
host->align_addr = dma_map_single(mmc_dev(host->mmc),
host->align_buffer, host->align_buffer_sz, direction);
if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
goto fail;
BUG_ON(host->align_addr & host->align_mask);
host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
if (host->sg_count < 0)
goto unmap_align;
desc = host->adma_table;
align = host->align_buffer;
align_addr = host->align_addr;
for_each_sg(data->sg, sg, host->sg_count, i) {
addr = sg_dma_address(sg);
len = sg_dma_len(sg);
/*
* The SDHCI specification states that ADMA
* addresses must be 32-bit aligned. If they
* aren't, then we use a bounce buffer for
* the (up to three) bytes that screw up the
* alignment.
*/
offset = (host->align_sz - (addr & host->align_mask)) &
host->align_mask;
if (offset) {
if (data->flags & MMC_DATA_WRITE) {
buffer = sdhci_kmap_atomic(sg, &flags);
memcpy(align, buffer, offset);
sdhci_kunmap_atomic(buffer, &flags);
}
/* tran, valid */
sdhci_adma_write_desc(host, desc, align_addr, offset,
ADMA2_TRAN_VALID);
BUG_ON(offset > 65536);
align += host->align_sz;
align_addr += host->align_sz;
desc += host->desc_sz;
addr += offset;
len -= offset;
}
BUG_ON(len > 65536);
/* tran, valid */
sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
desc += host->desc_sz;
/*
* If this triggers then we have a calculation bug
* somewhere. :/
*/
WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
}
if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
/*
* Mark the last descriptor as the terminating descriptor
*/
if (desc != host->adma_table) {
desc -= host->desc_sz;
sdhci_adma_mark_end(desc);
}
} else {
/*
* Add a terminating entry.
*/
/* nop, end, valid */
sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
}
/*
* Resync align buffer as we might have changed it.
*/
if (data->flags & MMC_DATA_WRITE) {
dma_sync_single_for_device(mmc_dev(host->mmc),
host->align_addr, host->align_buffer_sz, direction);
}
return 0;
unmap_align:
dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
host->align_buffer_sz, direction);
fail:
return -EINVAL;
}
static void sdhci_adma_table_post(struct sdhci_host *host,
struct mmc_data *data)
{
int direction;
struct scatterlist *sg;
int i, size;
void *align;
char *buffer;
unsigned long flags;
bool has_unaligned;
if (data->flags & MMC_DATA_READ)
direction = DMA_FROM_DEVICE;
else
direction = DMA_TO_DEVICE;
dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
host->align_buffer_sz, direction);
/* Do a quick scan of the SG list for any unaligned mappings */
has_unaligned = false;
for_each_sg(data->sg, sg, host->sg_count, i)
if (sg_dma_address(sg) & host->align_mask) {
has_unaligned = true;
break;
}
if (has_unaligned && data->flags & MMC_DATA_READ) {
dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
data->sg_len, direction);
align = host->align_buffer;
for_each_sg(data->sg, sg, host->sg_count, i) {
if (sg_dma_address(sg) & host->align_mask) {
size = host->align_sz -
(sg_dma_address(sg) & host->align_mask);
buffer = sdhci_kmap_atomic(sg, &flags);
memcpy(buffer, align, size);
sdhci_kunmap_atomic(buffer, &flags);
align += host->align_sz;
}
}
}
if (!data->host_cookie)
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
data->sg_len, direction);
}
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
struct mmc_data *data = cmd->data;
unsigned target_timeout, current_timeout;
/*
* If the host controller provides us with an incorrect timeout
* value, just skip the check and use 0xE. The hardware may take
* longer to time out, but that's much better than having a too-short
* timeout value.
*/
if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
return 0xE;
/* Unspecified timeout, assume max */
if (!data && !cmd->busy_timeout)
return 0xE;
/* timeout in us */
if (!data)
target_timeout = cmd->busy_timeout * 1000;
else {
target_timeout = data->timeout_ns / 1000;
if (host->clock)
target_timeout += data->timeout_clks / host->clock;
}
/*
* Figure out needed cycles.
* We do this in steps in order to fit inside a 32 bit int.
* The first step is the minimum timeout, which will have a
* minimum resolution of 6 bits:
* (1) 2^13*1000 > 2^22,
* (2) host->timeout_clk < 2^16
* =>
* (1) / (2) > 2^6
*/
count = 0;
current_timeout = (1 << 13) * 1000 / host->timeout_clk;
while (current_timeout < target_timeout) {
count++;
current_timeout <<= 1;
if (count >= 0xF)
break;
}
if (count >= 0xF) {
DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
mmc_hostname(host->mmc), count, cmd->opcode);
count = 0xE;
}
return count;
}
static void sdhci_set_transfer_irqs(struct sdhci_host *host)
{
u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
if (host->flags & SDHCI_REQ_USE_DMA)
host->ier = (host->ier & ~pio_irqs) | dma_irqs;
else
host->ier = (host->ier & ~dma_irqs) | pio_irqs;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
}
static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
if (host->ops->set_timeout) {
host->ops->set_timeout(host, cmd);
} else {
count = sdhci_calc_timeout(host, cmd);
sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
}
}
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 ctrl;
struct mmc_data *data = cmd->data;
int ret;
WARN_ON(host->data);
if (data || (cmd->flags & MMC_RSP_BUSY))
sdhci_set_timeout(host, cmd);
if (!data)
return;
/* Sanity checks */
BUG_ON(data->blksz * data->blocks > 524288);
BUG_ON(data->blksz > host->mmc->max_blk_size);
BUG_ON(data->blocks > 65535);
host->data = data;
host->data_early = 0;
host->data->bytes_xfered = 0;
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
host->flags |= SDHCI_REQ_USE_DMA;
/*
* FIXME: This doesn't account for merging when mapping the
* scatterlist.
*/
if (host->flags & SDHCI_REQ_USE_DMA) {
int broken, i;
struct scatterlist *sg;
broken = 0;
if (host->flags & SDHCI_USE_ADMA) {
if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
broken = 1;
} else {
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
broken = 1;
}
if (unlikely(broken)) {
for_each_sg(data->sg, sg, data->sg_len, i) {
if (sg->length & 0x3) {
DBG("Reverting to PIO because of "
"transfer size (%d)\n",
sg->length);
host->flags &= ~SDHCI_REQ_USE_DMA;
break;
}
}
}
}
/*
* The assumption here being that alignment is the same after
* translation to device address space.
*/
if (host->flags & SDHCI_REQ_USE_DMA) {
int broken, i;
struct scatterlist *sg;
broken = 0;
if (host->flags & SDHCI_USE_ADMA) {
/*
* As we use 3 byte chunks to work around
* alignment problems, we need to check this
* quirk.
*/
if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
broken = 1;
} else {
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
broken = 1;
}
if (unlikely(broken)) {
for_each_sg(data->sg, sg, data->sg_len, i) {
if (sg->offset & 0x3) {
DBG("Reverting to PIO because of "
"bad alignment\n");
host->flags &= ~SDHCI_REQ_USE_DMA;
break;
}
}
}
}
if (host->flags & SDHCI_REQ_USE_DMA) {
if (host->flags & SDHCI_USE_ADMA) {
ret = sdhci_adma_table_pre(host, data);
if (ret) {
/*
* This only happens when someone fed
* us an invalid request.
*/
WARN_ON(1);
host->flags &= ~SDHCI_REQ_USE_DMA;
} else {
sdhci_writel(host, host->adma_addr,
SDHCI_ADMA_ADDRESS);
if (host->flags & SDHCI_USE_64_BIT_DMA)
sdhci_writel(host,
(u64)host->adma_addr >> 32,
SDHCI_ADMA_ADDRESS_HI);
}
} else {
int sg_cnt;
sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
if (sg_cnt == 0) {
/*
* This only happens when someone fed
* us an invalid request.
*/
WARN_ON(1);
host->flags &= ~SDHCI_REQ_USE_DMA;
} else {
WARN_ON(sg_cnt != 1);
sdhci_writel(host, sg_dma_address(data->sg),
SDHCI_DMA_ADDRESS);
}
}
}
/*
* Always adjust the DMA selection as some controllers
* (e.g. JMicron) can't do PIO properly when the selection
* is ADMA.
*/
if (host->version >= SDHCI_SPEC_200) {
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
if ((host->flags & SDHCI_REQ_USE_DMA) &&
(host->flags & SDHCI_USE_ADMA)) {
if (host->flags & SDHCI_USE_64_BIT_DMA)
ctrl |= SDHCI_CTRL_ADMA64;
else
ctrl |= SDHCI_CTRL_ADMA32;
} else {
ctrl |= SDHCI_CTRL_SDMA;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
if (!(host->flags & SDHCI_REQ_USE_DMA)) {
int flags;
flags = SG_MITER_ATOMIC;
if (host->data->flags & MMC_DATA_READ)
flags |= SG_MITER_TO_SG;
else
flags |= SG_MITER_FROM_SG;
sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
host->blocks = data->blocks;
}
sdhci_set_transfer_irqs(host);
/* Set the DMA boundary value and block size */
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
data->blksz), SDHCI_BLOCK_SIZE);
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
}
static void sdhci_set_transfer_mode(struct sdhci_host *host,
struct mmc_command *cmd)
{
u16 mode = 0;
struct mmc_data *data = cmd->data;
if (data == NULL) {
if (host->quirks2 &
SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
} else {
/* clear Auto CMD settings for no data CMDs */
mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
}
return;
}
WARN_ON(!host->data);
if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
mode = SDHCI_TRNS_BLK_CNT_EN;
if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
/*
* If we are sending CMD23, CMD12 never gets sent
* on successful completion (so no Auto-CMD12).
*/
if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
(cmd->opcode != SD_IO_RW_EXTENDED))
mode |= SDHCI_TRNS_AUTO_CMD12;
else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
mode |= SDHCI_TRNS_AUTO_CMD23;
sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
}
}
if (data->flags & MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
if (host->flags & SDHCI_REQ_USE_DMA)
mode |= SDHCI_TRNS_DMA;
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
}
static void sdhci_finish_data(struct sdhci_host *host)
{
struct mmc_data *data;
BUG_ON(!host->data);
data = host->data;
host->data = NULL;
if (host->flags & SDHCI_REQ_USE_DMA) {
if (host->flags & SDHCI_USE_ADMA)
sdhci_adma_table_post(host, data);
else {
if (!data->host_cookie)
dma_unmap_sg(mmc_dev(host->mmc),
data->sg, data->sg_len,
(data->flags & MMC_DATA_READ) ?
DMA_FROM_DEVICE : DMA_TO_DEVICE);
}
}
/*
* The specification states that the block count register must
* be updated, but it does not specify at what point in the
* data flow. That makes the register entirely useless to read
* back so we have to assume that nothing made it to the card
* in the event of an error.
*/
if (data->error)
data->bytes_xfered = 0;
else
data->bytes_xfered = data->blksz * data->blocks;
/*
* Need to send CMD12 if -
* a) open-ended multiblock transfer (no CMD23)
* b) error in multiblock transfer
*/
if (data->stop &&
(data->error ||
!host->mrq->sbc)) {
/*
* The controller needs a reset of internal state machines
* upon error conditions.
*/
if (data->error) {
sdhci_do_reset(host, SDHCI_RESET_CMD);
sdhci_do_reset(host, SDHCI_RESET_DATA);
}
sdhci_send_command(host, data->stop);
} else
tasklet_schedule(&host->finish_tasklet);
}
void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
{
int flags;
u32 mask;
unsigned long timeout;
WARN_ON(host->cmd);
/* Wait max 10 ms */
timeout = 10;
mask = SDHCI_CMD_INHIBIT;
if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
mask |= SDHCI_DATA_INHIBIT;
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (host->mrq->data && (cmd == host->mrq->data->stop))
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (timeout == 0) {
pr_err("%s: Controller never released "
"inhibit bit(s).\n", mmc_hostname(host->mmc));
sdhci_dumpregs(host);
cmd->error = -EIO;
tasklet_schedule(&host->finish_tasklet);
return;
}
timeout--;
mdelay(1);
}
timeout = jiffies;
if (!cmd->data && cmd->busy_timeout > 9000)
timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
else
timeout += 10 * HZ;
mod_timer(&host->timer, timeout);
host->cmd = cmd;
host->busy_handle = 0;
sdhci_prepare_data(host, cmd);
sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
sdhci_set_transfer_mode(host, cmd);
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
pr_err("%s: Unsupported response type!\n",
mmc_hostname(host->mmc));
cmd->error = -EINVAL;
tasklet_schedule(&host->finish_tasklet);
return;
}
if (!(cmd->flags & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
else if (cmd->flags & MMC_RSP_136)
flags = SDHCI_CMD_RESP_LONG;
else if (cmd->flags & MMC_RSP_BUSY)
flags = SDHCI_CMD_RESP_SHORT_BUSY;
else
flags = SDHCI_CMD_RESP_SHORT;
if (cmd->flags & MMC_RSP_CRC)
flags |= SDHCI_CMD_CRC;
if (cmd->flags & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
/* CMD19 is special in that the Data Present Select should be set */
if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
}
EXPORT_SYMBOL_GPL(sdhci_send_command);
static void sdhci_finish_command(struct sdhci_host *host)
{
int i;
BUG_ON(host->cmd == NULL);
if (host->cmd->flags & MMC_RSP_PRESENT) {
if (host->cmd->flags & MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0;i < 4;i++) {
host->cmd->resp[i] = sdhci_readl(host,
SDHCI_RESPONSE + (3-i)*4) << 8;
if (i != 3)
host->cmd->resp[i] |=
sdhci_readb(host,
SDHCI_RESPONSE + (3-i)*4-1);
}
} else {
host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
}
}
host->cmd->error = 0;
/* Finished CMD23, now send actual command. */
if (host->cmd == host->mrq->sbc) {
host->cmd = NULL;
sdhci_send_command(host, host->mrq->cmd);
} else {
/* Processed actual command. */
if (host->data && host->data_early)
sdhci_finish_data(host);
if (!host->cmd->data)
tasklet_schedule(&host->finish_tasklet);
host->cmd = NULL;
}
}
static u16 sdhci_get_preset_value(struct sdhci_host *host)
{
u16 preset = 0;
switch (host->timing) {
case MMC_TIMING_UHS_SDR12:
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
break;
case MMC_TIMING_UHS_SDR25:
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
break;
case MMC_TIMING_UHS_SDR50:
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
break;
case MMC_TIMING_UHS_SDR104:
case MMC_TIMING_MMC_HS200:
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
break;
case MMC_TIMING_UHS_DDR50:
preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
break;
case MMC_TIMING_MMC_HS400:
preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
break;
default:
pr_warn("%s: Invalid UHS-I mode selected\n",
mmc_hostname(host->mmc));
preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
break;
}
return preset;
}
void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
int div = 0; /* Initialized for compiler warning */
int real_div = div, clk_mul = 1;
u16 clk = 0;
unsigned long timeout;
host->mmc->actual_clock = 0;
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
return;
if (host->version >= SDHCI_SPEC_300) {
if (host->preset_enabled) {
u16 pre_val;
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
pre_val = sdhci_get_preset_value(host);
div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
>> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
if (host->clk_mul &&
(pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
clk = SDHCI_PROG_CLOCK_MODE;
real_div = div + 1;
clk_mul = host->clk_mul;
} else {
real_div = max_t(int, 1, div << 1);
}
goto clock_set;
}
/*
* Check if the Host Controller supports Programmable Clock
* Mode.
*/
if (host->clk_mul) {
for (div = 1; div <= 1024; div++) {
if ((host->max_clk * host->clk_mul / div)
<= clock)
break;
}
/*
* Set Programmable Clock Mode in the Clock
* Control register.
*/
clk = SDHCI_PROG_CLOCK_MODE;
real_div = div;
clk_mul = host->clk_mul;
div--;
} else {
/* Version 3.00 divisors must be a multiple of 2. */
if (host->max_clk <= clock)
div = 1;
else {
for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
div += 2) {
if ((host->max_clk / div) <= clock)
break;
}
}
real_div = div;
div >>= 1;
}
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
if ((host->max_clk / div) <= clock)
break;
}
real_div = div;
div >>= 1;
}
clock_set:
if (real_div)
host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
clk |= SDHCI_CLOCK_INT_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
/* Wait max 20 ms */
timeout = 20;
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
& SDHCI_CLOCK_INT_STABLE)) {
if (timeout == 0) {
pr_err("%s: Internal clock never "
"stabilised.\n", mmc_hostname(host->mmc));
sdhci_dumpregs(host);
return;
}
timeout--;
mdelay(1);
}
clk |= SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}
EXPORT_SYMBOL_GPL(sdhci_set_clock);
static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
unsigned short vdd)
{
struct mmc_host *mmc = host->mmc;
u8 pwr = 0;
if (!IS_ERR(mmc->supply.vmmc)) {
spin_unlock_irq(&host->lock);
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
spin_lock_irq(&host->lock);
if (mode != MMC_POWER_OFF)
sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
else
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
return;
}
if (mode != MMC_POWER_OFF) {
switch (1 << vdd) {
case MMC_VDD_165_195:
pwr = SDHCI_POWER_180;
break;
case MMC_VDD_29_30:
case MMC_VDD_30_31:
pwr = SDHCI_POWER_300;
break;
case MMC_VDD_32_33:
case MMC_VDD_33_34:
pwr = SDHCI_POWER_330;
break;
default:
BUG();
}
}
if (host->pwr == pwr)
return;
host->pwr = pwr;
if (pwr == 0) {
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_off(host);
vdd = 0;
} else {
/*
* Spec says that we should clear the power reg before setting
* a new value. Some controllers don't seem to like this though.
*/
if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
/*
* At least the Marvell CaFe chip gets confused if we set the
* voltage and set turn on power at the same time, so set the
* voltage first.
*/
if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
sdhci_runtime_pm_bus_on(host);
/*
* Some controllers need an extra 10ms delay of 10ms before
* they can apply clock after applying power
*/
if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
mdelay(10);
}
}
/*****************************************************************************\
* *
* MMC callbacks *
* *
\*****************************************************************************/
static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct sdhci_host *host;
int present;
unsigned long flags;
u32 tuning_opcode;
host = mmc_priv(mmc);
sdhci_runtime_pm_get(host);
/* Firstly check card presence */
present = sdhci_do_get_cd(host);
spin_lock_irqsave(&host->lock, flags);
WARN_ON(host->mrq != NULL);
#ifndef SDHCI_USE_LEDS_CLASS
sdhci_activate_led(host);
#endif
/*
* Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
* requests if Auto-CMD12 is enabled.
*/
if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
if (mrq->stop) {
mrq->data->stop = NULL;
mrq->stop = NULL;
}
}
host->mrq = mrq;
if (!present || host->flags & SDHCI_DEVICE_DEAD) {
host->mrq->cmd->error = -ENOMEDIUM;
tasklet_schedule(&host->finish_tasklet);
} else {
u32 present_state;
present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
/*
* Check if the re-tuning timer has already expired and there
* is no on-going data transfer and DAT0 is not busy. If so,
* we need to execute tuning procedure before sending command.
*/
if ((host->flags & SDHCI_NEEDS_RETUNING) &&
!(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
(present_state & SDHCI_DATA_0_LVL_MASK)) {
if (mmc->card) {
/* eMMC uses cmd21 but sd and sdio use cmd19 */
tuning_opcode =
mmc->card->type == MMC_TYPE_MMC ?
MMC_SEND_TUNING_BLOCK_HS200 :
MMC_SEND_TUNING_BLOCK;
/* Here we need to set the host->mrq to NULL,
* in case the pending finish_tasklet
* finishes it incorrectly.
*/
host->mrq = NULL;
spin_unlock_irqrestore(&host->lock, flags);
sdhci_execute_tuning(mmc, tuning_opcode);
spin_lock_irqsave(&host->lock, flags);
/* Restore original mmc_request structure */
host->mrq = mrq;
}
}
if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
sdhci_send_command(host, mrq->sbc);
else
sdhci_send_command(host, mrq->cmd);
}
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
}
void sdhci_set_bus_width(struct sdhci_host *host, int width)
{
u8 ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (width == MMC_BUS_WIDTH_8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if (host->version >= SDHCI_SPEC_300)
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
if (host->version >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (width == MMC_BUS_WIDTH_4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
{
u16 ctrl_2;
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
if ((timing == MMC_TIMING_MMC_HS200) ||
(timing == MMC_TIMING_UHS_SDR104))
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
else if (timing == MMC_TIMING_UHS_SDR12)
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
else if (timing == MMC_TIMING_UHS_SDR25)
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
else if (timing == MMC_TIMING_UHS_SDR50)
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
else if ((timing == MMC_TIMING_UHS_DDR50) ||
(timing == MMC_TIMING_MMC_DDR52))
ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
else if (timing == MMC_TIMING_MMC_HS400)
ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
{
unsigned long flags;
u8 ctrl;
struct mmc_host *mmc = host->mmc;
spin_lock_irqsave(&host->lock, flags);
if (host->flags & SDHCI_DEVICE_DEAD) {
spin_unlock_irqrestore(&host->lock, flags);
if (!IS_ERR(mmc->supply.vmmc) &&
ios->power_mode == MMC_POWER_OFF)
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
return;
}
/*
* Reset the chip on each power off.
* Should clear out any weird states.
*/
if (ios->power_mode == MMC_POWER_OFF) {
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
sdhci_reinit(host);
}
if (host->version >= SDHCI_SPEC_300 &&
(ios->power_mode == MMC_POWER_UP) &&
!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
sdhci_enable_preset_value(host, false);
if (!ios->clock || ios->clock != host->clock) {
host->ops->set_clock(host, ios->clock);
host->clock = ios->clock;
if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
host->clock) {
host->timeout_clk = host->mmc->actual_clock ?
host->mmc->actual_clock / 1000 :
host->clock / 1000;
host->mmc->max_busy_timeout =
host->ops->get_max_timeout_count ?
host->ops->get_max_timeout_count(host) :
1 << 27;
host->mmc->max_busy_timeout /= host->timeout_clk;
}
}
sdhci_set_power(host, ios->power_mode, ios->vdd);
if (host->ops->platform_send_init_74_clocks)
host->ops->platform_send_init_74_clocks(host, ios->power_mode);
host->ops->set_bus_width(host, ios->bus_width);
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if ((ios->timing == MMC_TIMING_SD_HS ||
ios->timing == MMC_TIMING_MMC_HS)
&& !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
if (host->version >= SDHCI_SPEC_300) {
u16 clk, ctrl_2;
/* In case of UHS-I modes, set High Speed Enable */
if ((ios->timing == MMC_TIMING_MMC_HS400) ||
(ios->timing == MMC_TIMING_MMC_HS200) ||
(ios->timing == MMC_TIMING_MMC_DDR52) ||
(ios->timing == MMC_TIMING_UHS_SDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR104) ||
(ios->timing == MMC_TIMING_UHS_DDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR25))
ctrl |= SDHCI_CTRL_HISPD;
if (!host->preset_enabled) {
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
/*
* We only need to set Driver Strength if the
* preset value enable is not set.
*/
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
} else {
/*
* According to SDHC Spec v3.00, if the Preset Value
* Enable in the Host Control 2 register is set, we
* need to reset SD Clock Enable before changing High
* Speed Enable to avoid generating clock gliches.
*/
/* Reset SD Clock Enable */
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
/* Re-enable SD Clock */
host->ops->set_clock(host, host->clock);
}
/* Reset SD Clock Enable */
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
clk &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
host->ops->set_uhs_signaling(host, ios->timing);
host->timing = ios->timing;
if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
((ios->timing == MMC_TIMING_UHS_SDR12) ||
(ios->timing == MMC_TIMING_UHS_SDR25) ||
(ios->timing == MMC_TIMING_UHS_SDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR104) ||
(ios->timing == MMC_TIMING_UHS_DDR50))) {
u16 preset;
sdhci_enable_preset_value(host, true);
preset = sdhci_get_preset_value(host);
ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
>> SDHCI_PRESET_DRV_SHIFT;
}
/* Re-enable SD Clock */
host->ops->set_clock(host, host->clock);
} else
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
/*
* Some (ENE) controllers go apeshit on some ios operation,
* signalling timeout and CRC errors even on CMD0. Resetting
* it on each ios seems to solve the problem.
*/
if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
}
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
sdhci_runtime_pm_get(host);
sdhci_do_set_ios(host, ios);
sdhci_runtime_pm_put(host);
}
static int sdhci_do_get_cd(struct sdhci_host *host)
{
int gpio_cd = mmc_gpio_get_cd(host->mmc);
if (host->flags & SDHCI_DEVICE_DEAD)
return 0;
/* If polling/nonremovable, assume that the card is always present. */
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
(host->mmc->caps & MMC_CAP_NONREMOVABLE))
return 1;
/* Try slot gpio detect */
if (!IS_ERR_VALUE(gpio_cd))
return !!gpio_cd;
/* Host native card detect */
return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
}
static int sdhci_get_cd(struct mmc_host *mmc)
{
struct sdhci_host *host = mmc_priv(mmc);
int ret;
sdhci_runtime_pm_get(host);
ret = sdhci_do_get_cd(host);
sdhci_runtime_pm_put(host);
return ret;
}
static int sdhci_check_ro(struct sdhci_host *host)
{
unsigned long flags;
int is_readonly;
spin_lock_irqsave(&host->lock, flags);
if (host->flags & SDHCI_DEVICE_DEAD)
is_readonly = 0;
else if (host->ops->get_ro)
is_readonly = host->ops->get_ro(host);
else
is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
& SDHCI_WRITE_PROTECT);
spin_unlock_irqrestore(&host->lock, flags);
/* This quirk needs to be replaced by a callback-function later */
return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
!is_readonly : is_readonly;
}
#define SAMPLE_COUNT 5
static int sdhci_do_get_ro(struct sdhci_host *host)
{
int i, ro_count;
if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
return sdhci_check_ro(host);
ro_count = 0;
for (i = 0; i < SAMPLE_COUNT; i++) {
if (sdhci_check_ro(host)) {
if (++ro_count > SAMPLE_COUNT / 2)
return 1;
}
msleep(30);
}
return 0;
}
static void sdhci_hw_reset(struct mmc_host *mmc)
{
struct sdhci_host *host = mmc_priv(mmc);
if (host->ops && host->ops->hw_reset)
host->ops->hw_reset(host);
}
static int sdhci_get_ro(struct mmc_host *mmc)
{
struct sdhci_host *host = mmc_priv(mmc);
int ret;
sdhci_runtime_pm_get(host);
ret = sdhci_do_get_ro(host);
sdhci_runtime_pm_put(host);
return ret;
}
static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
{
if (!(host->flags & SDHCI_DEVICE_DEAD)) {
if (enable)
host->ier |= SDHCI_INT_CARD_INT;
else
host->ier &= ~SDHCI_INT_CARD_INT;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
mmiowb();
}
}
static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
sdhci_runtime_pm_get(host);
spin_lock_irqsave(&host->lock, flags);
if (enable)
host->flags |= SDHCI_SDIO_IRQ_ENABLED;
else
host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
sdhci_enable_sdio_irq_nolock(host, enable);
spin_unlock_irqrestore(&host->lock, flags);
sdhci_runtime_pm_put(host);
}
static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
struct mmc_ios *ios)
{
struct mmc_host *mmc = host->mmc;
u16 ctrl;
int ret;
/*
* Signal Voltage Switching is only applicable for Host Controllers
* v3.00 and above.
*/
if (host->version < SDHCI_SPEC_300)
return 0;
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
switch (ios->signal_voltage) {
case MMC_SIGNAL_VOLTAGE_330:
/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
ctrl &= ~SDHCI_CTRL_VDD_180;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
if (!IS_ERR(mmc->supply.vqmmc)) {
ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
3600000);
if (ret) {
pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
mmc_hostname(mmc));
return -EIO;
}
}
/* Wait for 5ms */
usleep_range(5000, 5500);
/* 3.3V regulator output should be stable within 5 ms */
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (!(ctrl & SDHCI_CTRL_VDD_180))
return 0;
pr_warn("%s: 3.3V regulator output did not became stable\n",
mmc_hostname(mmc));
return -EAGAIN;
case MMC_SIGNAL_VOLTAGE_180:
if (!IS_ERR(mmc->supply.vqmmc)) {
ret = regulator_set_voltage(mmc->supply.vqmmc,
1700000, 1950000);
if (ret) {
pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
mmc_hostname(mmc));
return -EIO;
}
}
/*
* Enable 1.8V Signal Enable in the Host Control2
* register
*/
ctrl |= SDHCI_CTRL_VDD_180;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
/* Some controller need to do more when switching */
if (host->ops->voltage_switch)
host->ops->voltage_switch(host);
/* 1.8V regulator output should be stable within 5 ms */
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (ctrl & SDHCI_CTRL_VDD_180)
return 0;
pr_warn("%s: 1.8V regulator output did not became stable\n",
mmc_hostname(mmc));
return -EAGAIN;
case MMC_SIGNAL_VOLTAGE_120:
if (!IS_ERR(mmc->supply.vqmmc)) {
ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1300000);
if (ret) {
pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
mmc_hostname(mmc));
return -EIO;
}
}
return 0;
default:
/* No signal voltage switch required */
return 0;
}
}
static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
int err;
if (host->version < SDHCI_SPEC_300)
return 0;
sdhci_runtime_pm_get(host);
err = sdhci_do_start_signal_voltage_switch(host, ios);
sdhci_runtime_pm_put(host);
return err;
}
static int sdhci_card_busy(struct mmc_host *mmc)
{
struct sdhci_host *host = mmc_priv(mmc);
u32 present_state;
sdhci_runtime_pm_get(host);
/* Check whether DAT[3:0] is 0000 */
present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
sdhci_runtime_pm_put(host);
return !(present_state & SDHCI_DATA_LVL_MASK);
}
static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
spin_lock_irqsave(&host->lock, flags);
host->flags |= SDHCI_HS400_TUNING;
spin_unlock_irqrestore(&host->lock, flags);
return 0;
}
static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
int tuning_loop_counter = MAX_TUNING_LOOP;
int err = 0;
unsigned long flags;
unsigned int tuning_count = 0;
bool hs400_tuning;
sdhci_runtime_pm_get(host);
spin_lock_irqsave(&host->lock, flags);
hs400_tuning = host->flags & SDHCI_HS400_TUNING;
host->flags &= ~SDHCI_HS400_TUNING;
if (host->tuning_mode == SDHCI_TUNING_MODE_1)
tuning_count = host->tuning_count;
/*
* The Host Controller needs tuning only in case of SDR104 mode
* and for SDR50 mode when Use Tuning for SDR50 is set in the
* Capabilities register.
* If the Host Controller supports the HS200 mode then the
* tuning function has to be executed.
*/
switch (host->timing) {
/* HS400 tuning is done in HS200 mode */
case MMC_TIMING_MMC_HS400:
err = -EINVAL;
goto out_unlock;
case MMC_TIMING_MMC_HS200:
/*
* Periodic re-tuning for HS400 is not expected to be needed, so
* disable it here.
*/
if (hs400_tuning)
tuning_count = 0;
break;
case MMC_TIMING_UHS_SDR104:
break;
case MMC_TIMING_UHS_SDR50:
if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
host->flags & SDHCI_SDR104_NEEDS_TUNING)
break;
/* FALLTHROUGH */
default:
goto out_unlock;
}
if (host->ops->platform_execute_tuning) {
spin_unlock_irqrestore(&host->lock, flags);
err = host->ops->platform_execute_tuning(host, opcode);
sdhci_runtime_pm_put(host);
return err;
}
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl |= SDHCI_CTRL_EXEC_TUNING;
if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
ctrl |= SDHCI_CTRL_TUNED_CLK;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
/*
* As per the Host Controller spec v3.00, tuning command
* generates Buffer Read Ready interrupt, so enable that.
*
* Note: The spec clearly says that when tuning sequence
* is being performed, the controller does not generate
* interrupts other than Buffer Read Ready interrupt. But
* to make sure we don't hit a controller bug, we _only_
* enable Buffer Read Ready interrupt here.
*/
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
/*
* Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
* of loops reaches 40 times or a timeout of 150ms occurs.
*/
do {
struct mmc_command cmd = {0};
struct mmc_request mrq = {NULL};
cmd.opcode = opcode;
cmd.arg = 0;
cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
cmd.retries = 0;
cmd.data = NULL;
cmd.error = 0;
if (tuning_loop_counter-- == 0)
break;
mrq.cmd = &cmd;
host->mrq = &mrq;
/*
* In response to CMD19, the card sends 64 bytes of tuning
* block to the Host Controller. So we set the block size
* to 64 here.
*/
if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
SDHCI_BLOCK_SIZE);
else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
SDHCI_BLOCK_SIZE);
} else {
sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
SDHCI_BLOCK_SIZE);
}
/*
* The tuning block is sent by the card to the host controller.
* So we set the TRNS_READ bit in the Transfer Mode register.
* This also takes care of setting DMA Enable and Multi Block
* Select in the same register to 0.
*/
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
sdhci_send_command(host, &cmd);
host->cmd = NULL;
host->mrq = NULL;
spin_unlock_irqrestore(&host->lock, flags);
/* Wait for Buffer Read Ready interrupt */
wait_event_interruptible_timeout(host->buf_ready_int,
(host->tuning_done == 1),
msecs_to_jiffies(50));
spin_lock_irqsave(&host->lock, flags);
if (!host->tuning_done) {
pr_info(DRIVER_NAME ": Timeout waiting for "
"Buffer Read Ready interrupt during tuning "
"procedure, falling back to fixed sampling "
"clock\n");
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
err = -EIO;
goto out;
}
host->tuning_done = 0;
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* eMMC spec does not require a delay between tuning cycles */
if (opcode == MMC_SEND_TUNING_BLOCK)
mdelay(1);
} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
/*
* The Host Driver has exhausted the maximum number of loops allowed,
* so use fixed sampling frequency.
*/
if (tuning_loop_counter < 0) {
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
}
if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
pr_info(DRIVER_NAME ": Tuning procedure"
" failed, falling back to fixed sampling"
" clock\n");
err = -EIO;
}
out:
host->flags &= ~SDHCI_NEEDS_RETUNING;
if (tuning_count) {
host->flags |= SDHCI_USING_RETUNING_TIMER;
mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
}
/*
* In case tuning fails, host controllers which support re-tuning can
* try tuning again at a later time, when the re-tuning timer expires.
* So for these controllers, we return 0. Since there might be other
* controllers who do not have this capability, we return error for
* them. SDHCI_USING_RETUNING_TIMER means the host is currently using
* a retuning timer to do the retuning for the card.
*/
if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
err = 0;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
out_unlock:
spin_unlock_irqrestore(&host->lock, flags);
sdhci_runtime_pm_put(host);
return err;
}
static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
{
/* Host Controller v3.00 defines preset value registers */
if (host->version < SDHCI_SPEC_300)
return;
/*
* We only enable or disable Preset Value if they are not already
* enabled or disabled respectively. Otherwise, we bail out.
*/
if (host->preset_enabled != enable) {
u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (enable)
ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
else
ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
if (enable)
host->flags |= SDHCI_PV_ENABLED;
else
host->flags &= ~SDHCI_PV_ENABLED;
host->preset_enabled = enable;
}
}
static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
int err)
{
struct sdhci_host *host = mmc_priv(mmc);
struct mmc_data *data = mrq->data;
if (host->flags & SDHCI_REQ_USE_DMA) {
if (data->host_cookie)
dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
data->flags & MMC_DATA_WRITE ?
DMA_TO_DEVICE : DMA_FROM_DEVICE);
mrq->data->host_cookie = 0;
}
}
static int sdhci_pre_dma_transfer(struct sdhci_host *host,
struct mmc_data *data,
struct sdhci_host_next *next)
{
int sg_count;
if (!next && data->host_cookie &&
data->host_cookie != host->next_data.cookie) {
pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
__func__, data->host_cookie, host->next_data.cookie);
data->host_cookie = 0;
}
/* Check if next job is already prepared */
if (next ||
(!next && data->host_cookie != host->next_data.cookie)) {
sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
data->sg_len,
data->flags & MMC_DATA_WRITE ?
DMA_TO_DEVICE : DMA_FROM_DEVICE);
} else {
sg_count = host->next_data.sg_count;
host->next_data.sg_count = 0;
}
if (sg_count == 0)
return -EINVAL;
if (next) {
next->sg_count = sg_count;
data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
} else
host->sg_count = sg_count;
return sg_count;
}
static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
bool is_first_req)
{
struct sdhci_host *host = mmc_priv(mmc);
if (mrq->data->host_cookie) {
mrq->data->host_cookie = 0;
return;
}
if (host->flags & SDHCI_REQ_USE_DMA)
if (sdhci_pre_dma_transfer(host,
mrq->data,
&host->next_data) < 0)
mrq->data->host_cookie = 0;
}
static void sdhci_card_event(struct mmc_host *mmc)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
int present;
/* First check if client has provided their own card event */
if (host->ops->card_event)
host->ops->card_event(host);
present = sdhci_do_get_cd(host);
spin_lock_irqsave(&host->lock, flags);
/* Check host->mrq first in case we are runtime suspended */
if (host->mrq && !present) {
pr_err("%s: Card removed during transfer!\n",
mmc_hostname(host->mmc));
pr_err("%s: Resetting controller.\n",
mmc_hostname(host->mmc));
sdhci_do_reset(host, SDHCI_RESET_CMD);
sdhci_do_reset(host, SDHCI_RESET_DATA);
host->mrq->cmd->error = -ENOMEDIUM;
tasklet_schedule(&host->finish_tasklet);
}
spin_unlock_irqrestore(&host->lock, flags);
}
static const struct mmc_host_ops sdhci_ops = {
.request = sdhci_request,
.post_req = sdhci_post_req,
.pre_req = sdhci_pre_req,
.set_ios = sdhci_set_ios,
.get_cd = sdhci_get_cd,
.get_ro = sdhci_get_ro,
.hw_reset = sdhci_hw_reset,
.enable_sdio_irq = sdhci_enable_sdio_irq,
.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
.prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
.execute_tuning = sdhci_execute_tuning,
.card_event = sdhci_card_event,
.card_busy = sdhci_card_busy,
};
/*****************************************************************************\
* *
* Tasklets *
* *
\*****************************************************************************/
static void sdhci_tasklet_finish(unsigned long param)
{
struct sdhci_host *host;
unsigned long flags;
struct mmc_request *mrq;
host = (struct sdhci_host*)param;
spin_lock_irqsave(&host->lock, flags);
/*
* If this tasklet gets rescheduled while running, it will
* be run again afterwards but without any active request.
*/
if (!host->mrq) {
spin_unlock_irqrestore(&host->lock, flags);
return;
}
del_timer(&host->timer);
mrq = host->mrq;
/*
* The controller needs a reset of internal state machines
* upon error conditions.
*/
if (!(host->flags & SDHCI_DEVICE_DEAD) &&
((mrq->cmd && mrq->cmd->error) ||
(mrq->sbc && mrq->sbc->error) ||
(mrq->data && ((mrq->data->error && !mrq->data->stop) ||
(mrq->data->stop && mrq->data->stop->error))) ||
(host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
/* Some controllers need this kick or reset won't work here */
if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
/* This is to force an update */
host->ops->set_clock(host, host->clock);
/* Spec says we should do both at the same time, but Ricoh
controllers do not like that. */
sdhci_do_reset(host, SDHCI_RESET_CMD);
sdhci_do_reset(host, SDHCI_RESET_DATA);
}
host->mrq = NULL;
host->cmd = NULL;
host->data = NULL;
#ifndef SDHCI_USE_LEDS_CLASS
sdhci_deactivate_led(host);
#endif
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
mmc_request_done(host->mmc, mrq);
sdhci_runtime_pm_put(host);
}
static void sdhci_timeout_timer(unsigned long data)
{
struct sdhci_host *host;
unsigned long flags;
host = (struct sdhci_host*)data;
spin_lock_irqsave(&host->lock, flags);
if (host->mrq) {
pr_err("%s: Timeout waiting for hardware "
"interrupt.\n", mmc_hostname(host->mmc));
sdhci_dumpregs(host);
if (host->data) {
host->data->error = -ETIMEDOUT;
sdhci_finish_data(host);
} else {
if (host->cmd)
host->cmd->error = -ETIMEDOUT;
else
host->mrq->cmd->error = -ETIMEDOUT;
tasklet_schedule(&host->finish_tasklet);
}
}
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
}
static void sdhci_tuning_timer(unsigned long data)
{
struct sdhci_host *host;
unsigned long flags;
host = (struct sdhci_host *)data;
spin_lock_irqsave(&host->lock, flags);
host->flags |= SDHCI_NEEDS_RETUNING;
spin_unlock_irqrestore(&host->lock, flags);
}
/*****************************************************************************\
* *
* Interrupt handling *
* *
\*****************************************************************************/
static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
{
BUG_ON(intmask == 0);
if (!host->cmd) {
pr_err("%s: Got command interrupt 0x%08x even "
"though no command operation was in progress.\n",
mmc_hostname(host->mmc), (unsigned)intmask);
sdhci_dumpregs(host);
return;
}
if (intmask & SDHCI_INT_TIMEOUT)
host->cmd->error = -ETIMEDOUT;
else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
SDHCI_INT_INDEX))
host->cmd->error = -EILSEQ;
if (host->cmd->error) {
tasklet_schedule(&host->finish_tasklet);
return;
}
/*
* The host can send and interrupt when the busy state has
* ended, allowing us to wait without wasting CPU cycles.
* Unfortunately this is overloaded on the "data complete"
* interrupt, so we need to take some care when handling
* it.
*
* Note: The 1.0 specification is a bit ambiguous about this
* feature so there might be some problems with older
* controllers.
*/
if (host->cmd->flags & MMC_RSP_BUSY) {
if (host->cmd->data)
DBG("Cannot wait for busy signal when also "
"doing a data transfer");
else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
&& !host->busy_handle) {
/* Mark that command complete before busy is ended */
host->busy_handle = 1;
return;
}
/* The controller does not support the end-of-busy IRQ,
* fall through and take the SDHCI_INT_RESPONSE */
} else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
*mask &= ~SDHCI_INT_DATA_END;
}
if (intmask & SDHCI_INT_RESPONSE)
sdhci_finish_command(host);
}
#ifdef CONFIG_MMC_DEBUG
static void sdhci_adma_show_error(struct sdhci_host *host)
{
const char *name = mmc_hostname(host->mmc);
void *desc = host->adma_table;
sdhci_dumpregs(host);
while (true) {
struct sdhci_adma2_64_desc *dma_desc = desc;
if (host->flags & SDHCI_USE_64_BIT_DMA)
DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
name, desc, le32_to_cpu(dma_desc->addr_hi),
le32_to_cpu(dma_desc->addr_lo),
le16_to_cpu(dma_desc->len),
le16_to_cpu(dma_desc->cmd));
else
DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
name, desc, le32_to_cpu(dma_desc->addr_lo),
le16_to_cpu(dma_desc->len),
le16_to_cpu(dma_desc->cmd));
desc += host->desc_sz;
if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
break;
}
}
#else
static void sdhci_adma_show_error(struct sdhci_host *host) { }
#endif
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
u32 command;
BUG_ON(intmask == 0);
/* CMD19 generates _only_ Buffer Read Ready interrupt */
if (intmask & SDHCI_INT_DATA_AVAIL) {
command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
if (command == MMC_SEND_TUNING_BLOCK ||
command == MMC_SEND_TUNING_BLOCK_HS200) {
host->tuning_done = 1;
wake_up(&host->buf_ready_int);
return;
}
}
if (!host->data) {
/*
* The "data complete" interrupt is also used to
* indicate that a busy state has ended. See comment
* above in sdhci_cmd_irq().
*/
if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
if (intmask & SDHCI_INT_DATA_TIMEOUT) {
host->cmd->error = -ETIMEDOUT;
tasklet_schedule(&host->finish_tasklet);
return;
}
if (intmask & SDHCI_INT_DATA_END) {
/*
* Some cards handle busy-end interrupt
* before the command completed, so make
* sure we do things in the proper order.
*/
if (host->busy_handle)
sdhci_finish_command(host);
else
host->busy_handle = 1;
return;
}
}
pr_err("%s: Got data interrupt 0x%08x even "
"though no data operation was in progress.\n",
mmc_hostname(host->mmc), (unsigned)intmask);
sdhci_dumpregs(host);
return;
}
if (intmask & SDHCI_INT_DATA_TIMEOUT)
host->data->error = -ETIMEDOUT;
else if (intmask & SDHCI_INT_DATA_END_BIT)
host->data->error = -EILSEQ;
else if ((intmask & SDHCI_INT_DATA_CRC) &&
SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
!= MMC_BUS_TEST_R)
host->data->error = -EILSEQ;
else if (intmask & SDHCI_INT_ADMA_ERROR) {
pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
sdhci_adma_show_error(host);
host->data->error = -EIO;
if (host->ops->adma_workaround)
host->ops->adma_workaround(host, intmask);
}
if (host->data->error)
sdhci_finish_data(host);
else {
if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
sdhci_transfer_pio(host);
/*
* We currently don't do anything fancy with DMA
* boundaries, but as we can't disable the feature
* we need to at least restart the transfer.
*
* According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
* should return a valid address to continue from, but as
* some controllers are faulty, don't trust them.
*/
if (intmask & SDHCI_INT_DMA_END) {
u32 dmastart, dmanow;
dmastart = sg_dma_address(host->data->sg);
dmanow = dmastart + host->data->bytes_xfered;
/*
* Force update to the next DMA block boundary.
*/
dmanow = (dmanow &
~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
SDHCI_DEFAULT_BOUNDARY_SIZE;
host->data->bytes_xfered = dmanow - dmastart;
DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
" next 0x%08x\n",
mmc_hostname(host->mmc), dmastart,
host->data->bytes_xfered, dmanow);
sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
}
if (intmask & SDHCI_INT_DATA_END) {
if (host->cmd) {
/*
* Data managed to finish before the
* command completed. Make sure we do
* things in the proper order.
*/
host->data_early = 1;
} else {
sdhci_finish_data(host);
}
}
}
}
static irqreturn_t sdhci_irq(int irq, void *dev_id)
{
irqreturn_t result = IRQ_NONE;
struct sdhci_host *host = dev_id;
u32 intmask, mask, unexpected = 0;
int max_loops = 16;
spin_lock(&host->lock);
if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
spin_unlock(&host->lock);
return IRQ_NONE;
}
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
if (!intmask || intmask == 0xffffffff) {
result = IRQ_NONE;
goto out;
}
do {
/* Clear selected interrupts. */
mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
SDHCI_INT_BUS_POWER);
sdhci_writel(host, mask, SDHCI_INT_STATUS);
DBG("*** %s got interrupt: 0x%08x\n",
mmc_hostname(host->mmc), intmask);
if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
SDHCI_CARD_PRESENT;
/*
* There is a observation on i.mx esdhc. INSERT
* bit will be immediately set again when it gets
* cleared, if a card is inserted. We have to mask
* the irq to prevent interrupt storm which will
* freeze the system. And the REMOVE gets the
* same situation.
*
* More testing are needed here to ensure it works
* for other platforms though.
*/
host->ier &= ~(SDHCI_INT_CARD_INSERT |
SDHCI_INT_CARD_REMOVE);
host->ier |= present ? SDHCI_INT_CARD_REMOVE :
SDHCI_INT_CARD_INSERT;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
SDHCI_INT_CARD_REMOVE);
result = IRQ_WAKE_THREAD;
}
if (intmask & SDHCI_INT_CMD_MASK)
sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
&intmask);
if (intmask & SDHCI_INT_DATA_MASK)
sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
if (intmask & SDHCI_INT_BUS_POWER)
pr_err("%s: Card is consuming too much power!\n",
mmc_hostname(host->mmc));
if (intmask & SDHCI_INT_CARD_INT) {
sdhci_enable_sdio_irq_nolock(host, false);
host->thread_isr |= SDHCI_INT_CARD_INT;
result = IRQ_WAKE_THREAD;
}
intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
SDHCI_INT_CARD_INT);
if (intmask) {
unexpected |= intmask;
sdhci_writel(host, intmask, SDHCI_INT_STATUS);
}
if (result == IRQ_NONE)
result = IRQ_HANDLED;
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
} while (intmask && --max_loops);
out:
spin_unlock(&host->lock);
if (unexpected) {
pr_err("%s: Unexpected interrupt 0x%08x.\n",
mmc_hostname(host->mmc), unexpected);
sdhci_dumpregs(host);
}
return result;
}
static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
{
struct sdhci_host *host = dev_id;
unsigned long flags;
u32 isr;
spin_lock_irqsave(&host->lock, flags);
isr = host->thread_isr;
host->thread_isr = 0;
spin_unlock_irqrestore(&host->lock, flags);
if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
sdhci_card_event(host->mmc);
mmc_detect_change(host->mmc, msecs_to_jiffies(200));
}
if (isr & SDHCI_INT_CARD_INT) {
sdio_run_irqs(host->mmc);
spin_lock_irqsave(&host->lock, flags);
if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
sdhci_enable_sdio_irq_nolock(host, true);
spin_unlock_irqrestore(&host->lock, flags);
}
return isr ? IRQ_HANDLED : IRQ_NONE;
}
/*****************************************************************************\
* *
* Suspend/resume *
* *
\*****************************************************************************/
#ifdef CONFIG_PM
void sdhci_enable_irq_wakeups(struct sdhci_host *host)
{
u8 val;
u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
| SDHCI_WAKE_ON_INT;
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
val |= mask ;
/* Avoid fake wake up */
if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
}
EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
{
u8 val;
u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
| SDHCI_WAKE_ON_INT;
val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
val &= ~mask;
sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
}
int sdhci_suspend_host(struct sdhci_host *host)
{
sdhci_disable_card_detection(host);
/* Disable tuning since we are suspending */
if (host->flags & SDHCI_USING_RETUNING_TIMER) {
del_timer_sync(&host->tuning_timer);
host->flags &= ~SDHCI_NEEDS_RETUNING;
}
if (!device_may_wakeup(mmc_dev(host->mmc))) {
host->ier = 0;
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
free_irq(host->irq, host);
} else {
sdhci_enable_irq_wakeups(host);
enable_irq_wake(host->irq);
}
return 0;
}
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
int sdhci_resume_host(struct sdhci_host *host)
{
int ret = 0;
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host->ops->enable_dma)
host->ops->enable_dma(host);
}
if (!device_may_wakeup(mmc_dev(host->mmc))) {
ret = request_threaded_irq(host->irq, sdhci_irq,
sdhci_thread_irq, IRQF_SHARED,
mmc_hostname(host->mmc), host);
if (ret)
return ret;
} else {
sdhci_disable_irq_wakeups(host);
disable_irq_wake(host->irq);
}
if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
(host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
/* Card keeps power but host controller does not */
sdhci_init(host, 0);
host->pwr = 0;
host->clock = 0;
sdhci_do_set_ios(host, &host->mmc->ios);
} else {
sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
mmiowb();
}
sdhci_enable_card_detection(host);
/* Set the re-tuning expiration flag */
if (host->flags & SDHCI_USING_RETUNING_TIMER)
host->flags |= SDHCI_NEEDS_RETUNING;
return ret;
}
EXPORT_SYMBOL_GPL(sdhci_resume_host);
static int sdhci_runtime_pm_get(struct sdhci_host *host)
{
return pm_runtime_get_sync(host->mmc->parent);
}
static int sdhci_runtime_pm_put(struct sdhci_host *host)
{
pm_runtime_mark_last_busy(host->mmc->parent);
return pm_runtime_put_autosuspend(host->mmc->parent);
}
static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
{
if (host->runtime_suspended || host->bus_on)
return;
host->bus_on = true;
pm_runtime_get_noresume(host->mmc->parent);
}
static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
{
if (host->runtime_suspended || !host->bus_on)
return;
host->bus_on = false;
pm_runtime_put_noidle(host->mmc->parent);
}
int sdhci_runtime_suspend_host(struct sdhci_host *host)
{
unsigned long flags;
/* Disable tuning since we are suspending */
if (host->flags & SDHCI_USING_RETUNING_TIMER) {
del_timer_sync(&host->tuning_timer);
host->flags &= ~SDHCI_NEEDS_RETUNING;
}
spin_lock_irqsave(&host->lock, flags);
host->ier &= SDHCI_INT_CARD_INT;
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
spin_unlock_irqrestore(&host->lock, flags);
synchronize_hardirq(host->irq);
spin_lock_irqsave(&host->lock, flags);
host->runtime_suspended = true;
spin_unlock_irqrestore(&host->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
int sdhci_runtime_resume_host(struct sdhci_host *host)
{
unsigned long flags;
int host_flags = host->flags;
if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host->ops->enable_dma)
host->ops->enable_dma(host);
}
sdhci_init(host, 0);
/* Force clock and power re-program */
host->pwr = 0;
host->clock = 0;
sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
sdhci_do_set_ios(host, &host->mmc->ios);
if ((host_flags & SDHCI_PV_ENABLED) &&
!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
spin_lock_irqsave(&host->lock, flags);
sdhci_enable_preset_value(host, true);
spin_unlock_irqrestore(&host->lock, flags);
}
/* Set the re-tuning expiration flag */
if (host->flags & SDHCI_USING_RETUNING_TIMER)
host->flags |= SDHCI_NEEDS_RETUNING;
spin_lock_irqsave(&host->lock, flags);
host->runtime_suspended = false;
/* Enable SDIO IRQ */
if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
sdhci_enable_sdio_irq_nolock(host, true);
/* Enable Card Detection */
sdhci_enable_card_detection(host);
spin_unlock_irqrestore(&host->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
#endif /* CONFIG_PM */
/*****************************************************************************\
* *
* Device allocation/registration *
* *
\*****************************************************************************/
struct sdhci_host *sdhci_alloc_host(struct device *dev,
size_t priv_size)
{
struct mmc_host *mmc;
struct sdhci_host *host;
WARN_ON(dev == NULL);
mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
if (!mmc)
return ERR_PTR(-ENOMEM);
host = mmc_priv(mmc);
host->mmc = mmc;
return host;
}
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
int sdhci_add_host(struct sdhci_host *host)
{
struct mmc_host *mmc;
u32 caps[2] = {0, 0};
u32 max_current_caps;
unsigned int ocr_avail;
unsigned int override_timeout_clk;
int ret;
WARN_ON(host == NULL);
if (host == NULL)
return -EINVAL;
mmc = host->mmc;
if (debug_quirks)
host->quirks = debug_quirks;
if (debug_quirks2)
host->quirks2 = debug_quirks2;
override_timeout_clk = host->timeout_clk;
sdhci_do_reset(host, SDHCI_RESET_ALL);
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->version = (host->version & SDHCI_SPEC_VER_MASK)
>> SDHCI_SPEC_VER_SHIFT;
if (host->version > SDHCI_SPEC_300) {
pr_err("%s: Unknown controller version (%d). "
"You may experience problems.\n", mmc_hostname(mmc),
host->version);
}
caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
sdhci_readl(host, SDHCI_CAPABILITIES);
if (host->version >= SDHCI_SPEC_300)
caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
host->caps1 :
sdhci_readl(host, SDHCI_CAPABILITIES_1);
if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
host->flags |= SDHCI_USE_SDMA;
else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
DBG("Controller doesn't have SDMA capability\n");
else
host->flags |= SDHCI_USE_SDMA;
if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
(host->flags & SDHCI_USE_SDMA)) {
DBG("Disabling DMA as it is marked broken\n");
host->flags &= ~SDHCI_USE_SDMA;
}
if ((host->version >= SDHCI_SPEC_200) &&
(caps[0] & SDHCI_CAN_DO_ADMA2))
host->flags |= SDHCI_USE_ADMA;
if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
(host->flags & SDHCI_USE_ADMA)) {
DBG("Disabling ADMA as it is marked broken\n");
host->flags &= ~SDHCI_USE_ADMA;
}
/*
* It is assumed that a 64-bit capable device has set a 64-bit DMA mask
* and *must* do 64-bit DMA. A driver has the opportunity to change
* that during the first call to ->enable_dma(). Similarly
* SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
* implement.
*/
if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
host->flags |= SDHCI_USE_64_BIT_DMA;
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host->ops->enable_dma) {
if (host->ops->enable_dma(host)) {
pr_warn("%s: No suitable DMA available - falling back to PIO\n",
mmc_hostname(mmc));
host->flags &=
~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
}
}
}
/* SDMA does not support 64-bit DMA */
if (host->flags & SDHCI_USE_64_BIT_DMA)
host->flags &= ~SDHCI_USE_SDMA;
if (host->flags & SDHCI_USE_ADMA) {
/*
* The DMA descriptor table size is calculated as the maximum
* number of segments times 2, to allow for an alignment
* descriptor for each segment, plus 1 for a nop end descriptor,
* all multipled by the descriptor size.
*/
if (host->flags & SDHCI_USE_64_BIT_DMA) {
host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
SDHCI_ADMA2_64_DESC_SZ;
host->align_buffer_sz = SDHCI_MAX_SEGS *
SDHCI_ADMA2_64_ALIGN;
host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
host->align_sz = SDHCI_ADMA2_64_ALIGN;
host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
} else {
host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
SDHCI_ADMA2_32_DESC_SZ;
host->align_buffer_sz = SDHCI_MAX_SEGS *
SDHCI_ADMA2_32_ALIGN;
host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
host->align_sz = SDHCI_ADMA2_32_ALIGN;
host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
}
host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
host->adma_table_sz,
&host->adma_addr,
GFP_KERNEL);
host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
if (!host->adma_table || !host->align_buffer) {
dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
host->adma_table, host->adma_addr);
kfree(host->align_buffer);
pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
mmc_hostname(mmc));
host->flags &= ~SDHCI_USE_ADMA;
host->adma_table = NULL;
host->align_buffer = NULL;
} else if (host->adma_addr & host->align_mask) {
pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
mmc_hostname(mmc));
host->flags &= ~SDHCI_USE_ADMA;
dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
host->adma_table, host->adma_addr);
kfree(host->align_buffer);
host->adma_table = NULL;
host->align_buffer = NULL;
}
}
/*
* If we use DMA, then it's up to the caller to set the DMA
* mask, but PIO does not need the hw shim so we set a new
* mask here in that case.
*/
if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
host->dma_mask = DMA_BIT_MASK(64);
mmc_dev(mmc)->dma_mask = &host->dma_mask;
}
if (host->version >= SDHCI_SPEC_300)
host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
else
host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
host->max_clk *= 1000000;
if (host->max_clk == 0 || host->quirks &
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
if (!host->ops->get_max_clock) {
pr_err("%s: Hardware doesn't specify base clock "
"frequency.\n", mmc_hostname(mmc));
return -ENODEV;
}
host->max_clk = host->ops->get_max_clock(host);
}
host->next_data.cookie = 1;
/*
* In case of Host Controller v3.00, find out whether clock
* multiplier is supported.
*/
host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
SDHCI_CLOCK_MUL_SHIFT;
/*
* In case the value in Clock Multiplier is 0, then programmable
* clock mode is not supported, otherwise the actual clock
* multiplier is one more than the value of Clock Multiplier
* in the Capabilities Register.
*/
if (host->clk_mul)
host->clk_mul += 1;
/*
* Set host parameters.
*/
mmc->ops = &sdhci_ops;
mmc->f_max = host->max_clk;
if (host->ops->get_min_clock)
mmc->f_min = host->ops->get_min_clock(host);
else if (host->version >= SDHCI_SPEC_300) {
if (host->clk_mul) {
mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
mmc->f_max = host->max_clk * host->clk_mul;
} else
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
} else
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
SDHCI_TIMEOUT_CLK_SHIFT;
if (host->timeout_clk == 0) {
if (host->ops->get_timeout_clock) {
host->timeout_clk =
host->ops->get_timeout_clock(host);
} else {
pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
mmc_hostname(mmc));
return -ENODEV;
}
}
if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
host->timeout_clk *= 1000;
mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
host->ops->get_max_timeout_count(host) : 1 << 27;
mmc->max_busy_timeout /= host->timeout_clk;
}
if (override_timeout_clk)
host->timeout_clk = override_timeout_clk;
mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
host->flags |= SDHCI_AUTO_CMD12;
/* Auto-CMD23 stuff only works in ADMA or PIO. */
if ((host->version >= SDHCI_SPEC_300) &&
((host->flags & SDHCI_USE_ADMA) ||
!(host->flags & SDHCI_USE_SDMA)) &&
!(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
host->flags |= SDHCI_AUTO_CMD23;
DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
} else {
DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
}
/*
* A controller may support 8-bit width, but the board itself
* might not have the pins brought out. Boards that support
* 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
* their platform code before calling sdhci_add_host(), and we
* won't assume 8-bit width for hosts without that CAP.
*/
if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
mmc->caps |= MMC_CAP_4_BIT_DATA;
if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
mmc->caps &= ~MMC_CAP_CMD23;
if (caps[0] & SDHCI_CAN_DO_HISPD)
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
!(mmc->caps & MMC_CAP_NONREMOVABLE))
mmc->caps |= MMC_CAP_NEEDS_POLL;
/* If there are external regulators, get them */
if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
return -EPROBE_DEFER;
/* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
if (!IS_ERR(mmc->supply.vqmmc)) {
ret = regulator_enable(mmc->supply.vqmmc);
if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
1950000))
caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
if (ret) {
pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
mmc_hostname(mmc), ret);
mmc->supply.vqmmc = ERR_PTR(-EINVAL);
}
}
if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50))
mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
/* SDR104 supports also implies SDR50 support */
if (caps[1] & SDHCI_SUPPORT_SDR104) {
mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
/* SD3.0: SDR104 is supported so (for eMMC) the caps2
* field can be promoted to support HS200.
*/
if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
mmc->caps2 |= MMC_CAP2_HS200;
} else if (caps[1] & SDHCI_SUPPORT_SDR50)
mmc->caps |= MMC_CAP_UHS_SDR50;
if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
(caps[1] & SDHCI_SUPPORT_HS400))
mmc->caps2 |= MMC_CAP2_HS400;
if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
(IS_ERR(mmc->supply.vqmmc) ||
!regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
1300000)))
mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
!(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
mmc->caps |= MMC_CAP_UHS_DDR50;
/* Does the host need tuning for SDR50? */
if (caps[1] & SDHCI_USE_SDR50_TUNING)
host->flags |= SDHCI_SDR50_NEEDS_TUNING;
/* Does the host need tuning for SDR104 / HS200? */
if (mmc->caps2 & MMC_CAP2_HS200)
host->flags |= SDHCI_SDR104_NEEDS_TUNING;
/* Driver Type(s) (A, C, D) supported by the host */
if (caps[1] & SDHCI_DRIVER_TYPE_A)
mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
if (caps[1] & SDHCI_DRIVER_TYPE_C)
mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
if (caps[1] & SDHCI_DRIVER_TYPE_D)
mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
/* Initial value for re-tuning timer count */
host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
SDHCI_RETUNING_TIMER_COUNT_SHIFT;
/*
* In case Re-tuning Timer is not disabled, the actual value of
* re-tuning timer will be 2 ^ (n - 1).
*/
if (host->tuning_count)
host->tuning_count = 1 << (host->tuning_count - 1);
/* Re-tuning mode supported by the Host Controller */
host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
SDHCI_RETUNING_MODE_SHIFT;
ocr_avail = 0;
/*
* According to SD Host Controller spec v3.00, if the Host System
* can afford more than 150mA, Host Driver should set XPC to 1. Also
* the value is meaningful only if Voltage Support in the Capabilities
* register is set. The actual current value is 4 times the register
* value.
*/
max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
int curr = regulator_get_current_limit(mmc->supply.vmmc);
if (curr > 0) {
/* convert to SDHCI_MAX_CURRENT format */
curr = curr/1000; /* convert to mA */
curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
max_current_caps =
(curr << SDHCI_MAX_CURRENT_330_SHIFT) |
(curr << SDHCI_MAX_CURRENT_300_SHIFT) |
(curr << SDHCI_MAX_CURRENT_180_SHIFT);
}
}
if (caps[0] & SDHCI_CAN_VDD_330) {
ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->max_current_330 = ((max_current_caps &
SDHCI_MAX_CURRENT_330_MASK) >>
SDHCI_MAX_CURRENT_330_SHIFT) *
SDHCI_MAX_CURRENT_MULTIPLIER;
}
if (caps[0] & SDHCI_CAN_VDD_300) {
ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
mmc->max_current_300 = ((max_current_caps &
SDHCI_MAX_CURRENT_300_MASK) >>
SDHCI_MAX_CURRENT_300_SHIFT) *
SDHCI_MAX_CURRENT_MULTIPLIER;
}
if (caps[0] & SDHCI_CAN_VDD_180) {
ocr_avail |= MMC_VDD_165_195;
mmc->max_current_180 = ((max_current_caps &
SDHCI_MAX_CURRENT_180_MASK) >>
SDHCI_MAX_CURRENT_180_SHIFT) *
SDHCI_MAX_CURRENT_MULTIPLIER;
}
/* If OCR set by external regulators, use it instead */
if (mmc->ocr_avail)
ocr_avail = mmc->ocr_avail;
if (host->ocr_mask)
ocr_avail &= host->ocr_mask;
mmc->ocr_avail = ocr_avail;
mmc->ocr_avail_sdio = ocr_avail;
if (host->ocr_avail_sdio)
mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
mmc->ocr_avail_sd = ocr_avail;
if (host->ocr_avail_sd)
mmc->ocr_avail_sd &= host->ocr_avail_sd;
else /* normal SD controllers don't support 1.8V */
mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
mmc->ocr_avail_mmc = ocr_avail;
if (host->ocr_avail_mmc)
mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
if (mmc->ocr_avail == 0) {
pr_err("%s: Hardware doesn't report any "
"support voltages.\n", mmc_hostname(mmc));
return -ENODEV;
}
spin_lock_init(&host->lock);
/*
* Maximum number of segments. Depends on if the hardware
* can do scatter/gather or not.
*/
if (host->flags & SDHCI_USE_ADMA)
mmc->max_segs = SDHCI_MAX_SEGS;
else if (host->flags & SDHCI_USE_SDMA)
mmc->max_segs = 1;
else /* PIO */
mmc->max_segs = SDHCI_MAX_SEGS;
/*
* Maximum number of sectors in one transfer. Limited by SDMA boundary
* size (512KiB). Note some tuning modes impose a 4MiB limit, but this
* is less anyway.
*/
mmc->max_req_size = 524288;
/*
* Maximum segment size. Could be one segment with the maximum number
* of bytes. When doing hardware scatter/gather, each entry cannot
* be larger than 64 KiB though.
*/
if (host->flags & SDHCI_USE_ADMA) {
if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
mmc->max_seg_size = 65535;
else
mmc->max_seg_size = 65536;
} else {
mmc->max_seg_size = mmc->max_req_size;
}
/*
* Maximum block size. This varies from controller to controller and
* is specified in the capabilities register.
*/
if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
mmc->max_blk_size = 2;
} else {
mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
SDHCI_MAX_BLOCK_SHIFT;
if (mmc->max_blk_size >= 3) {
pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
mmc_hostname(mmc));
mmc->max_blk_size = 0;
}
}
mmc->max_blk_size = 512 << mmc->max_blk_size;
/*
* Maximum block count.
*/
mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
/*
* Init tasklets.
*/
tasklet_init(&host->finish_tasklet,
sdhci_tasklet_finish, (unsigned long)host);
setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
init_waitqueue_head(&host->buf_ready_int);
if (host->version >= SDHCI_SPEC_300) {
/* Initialize re-tuning timer */
init_timer(&host->tuning_timer);
host->tuning_timer.data = (unsigned long)host;
host->tuning_timer.function = sdhci_tuning_timer;
}
sdhci_init(host, 0);
ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
IRQF_SHARED, mmc_hostname(mmc), host);
if (ret) {
pr_err("%s: Failed to request IRQ %d: %d\n",
mmc_hostname(mmc), host->irq, ret);
goto untasklet;
}
#ifdef CONFIG_MMC_DEBUG
sdhci_dumpregs(host);
#endif
#ifdef SDHCI_USE_LEDS_CLASS
snprintf(host->led_name, sizeof(host->led_name),
"%s::", mmc_hostname(mmc));
host->led.name = host->led_name;
host->led.brightness = LED_OFF;
host->led.default_trigger = mmc_hostname(mmc);
host->led.brightness_set = sdhci_led_control;
ret = led_classdev_register(mmc_dev(mmc), &host->led);
if (ret) {
pr_err("%s: Failed to register LED device: %d\n",
mmc_hostname(mmc), ret);
goto reset;
}
#endif
mmiowb();
mmc_add_host(mmc);
pr_info("%s: SDHCI controller on %s [%s] using %s\n",
mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
(host->flags & SDHCI_USE_ADMA) ?
(host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
sdhci_enable_card_detection(host);
return 0;
#ifdef SDHCI_USE_LEDS_CLASS
reset:
sdhci_do_reset(host, SDHCI_RESET_ALL);
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
free_irq(host->irq, host);
#endif
untasklet:
tasklet_kill(&host->finish_tasklet);
return ret;
}
EXPORT_SYMBOL_GPL(sdhci_add_host);
void sdhci_remove_host(struct sdhci_host *host, int dead)
{
struct mmc_host *mmc = host->mmc;
unsigned long flags;
if (dead) {
spin_lock_irqsave(&host->lock, flags);
host->flags |= SDHCI_DEVICE_DEAD;
if (host->mrq) {
pr_err("%s: Controller removed during "
" transfer!\n", mmc_hostname(mmc));
host->mrq->cmd->error = -ENOMEDIUM;
tasklet_schedule(&host->finish_tasklet);
}
spin_unlock_irqrestore(&host->lock, flags);
}
sdhci_disable_card_detection(host);
mmc_remove_host(mmc);
#ifdef SDHCI_USE_LEDS_CLASS
led_classdev_unregister(&host->led);
#endif
if (!dead)
sdhci_do_reset(host, SDHCI_RESET_ALL);
sdhci_writel(host, 0, SDHCI_INT_ENABLE);
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
free_irq(host->irq, host);
del_timer_sync(&host->timer);
tasklet_kill(&host->finish_tasklet);
if (!IS_ERR(mmc->supply.vqmmc))
regulator_disable(mmc->supply.vqmmc);
if (host->adma_table)
dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
host->adma_table, host->adma_addr);
kfree(host->align_buffer);
host->adma_table = NULL;
host->align_buffer = NULL;
}
EXPORT_SYMBOL_GPL(sdhci_remove_host);
void sdhci_free_host(struct sdhci_host *host)
{
mmc_free_host(host->mmc);
}
EXPORT_SYMBOL_GPL(sdhci_free_host);
/*****************************************************************************\
* *
* Driver init/exit *
* *
\*****************************************************************************/
static int __init sdhci_drv_init(void)
{
pr_info(DRIVER_NAME
": Secure Digital Host Controller Interface driver\n");
pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
return 0;
}
static void __exit sdhci_drv_exit(void)
{
}
module_init(sdhci_drv_init);
module_exit(sdhci_drv_exit);
module_param(debug_quirks, uint, 0444);
module_param(debug_quirks2, uint, 0444);
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
MODULE_LICENSE("GPL");
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
| gpl-2.0 |
KINGbabasula/android_kernel_samsung_i9105P | sound/caph/chal/capri/src/chal_caph_cfifo.c | 100 | 41189 | /*******************************************************************************************
Copyright 2010 Broadcom Corporation. All rights reserved.
Unless you and Broadcom execute a separate written software license agreement governing use
of this software, this software is licensed to you under the terms of the GNU General Public
License version 2, available at http://www.gnu.org/copyleft/gpl.html (the "GPL").
Notwithstanding the above, under no circumstances may you combine this software in any way
with any other Broadcom software provided under a license other than the GPL, without
Broadcom's express prior written consent.
*******************************************************************************************/
/**
*
* @file chal_caph_cfifo.c
*
* @brief chal layer driver for caph cfifo driver
*
****************************************************************************/
#include "chal_caph_cfifo.h"
#include <mach/rdb/brcm_rdb_cph_cfifo.h>
#include <chal/chal_util.h>
/*
* ****************************************************************************
* G L O B A L S E C T I O N
* ****************************************************************************
*/
/*
* ****************************************************************************
* global variable definitions
* ****************************************************************************
*/
/*
* ****************************************************************************
* L O C A L S E C T I O N
* ****************************************************************************
*/
/*
* ****************************************************************************
* local macro declarations
* ****************************************************************************
*/
/* Max number of FIFOs supported by Hardware */
#define CHAL_CAPH_CFIFO_MAX_FIFOS 16
/* Max number of Timestamp chnnels supported by Hardware */
#define CHAL_CAPH_CFIFO_MAX_TS_CHANNELS 4
/* PADDR register size for each channel */
#define CHAL_CAPH_CFIFO_PADDR_REG_SIZE ((CPH_CFIFO_CH2_PADDR_OFFSET-CPH_CFIFO_CH1_PADDR_OFFSET)/sizeof(cUInt32))
/* Control register size for each channel */
#define CHAL_CAPH_CFIFO_CR_REG_SIZE ((CPH_CFIFO_CPH_CR_2_OFFSET - CPH_CFIFO_CPH_CR_1_OFFSET)/sizeof(cUInt32))
/* CTL register size for each channel */
#define CHAL_CAPH_CFIFO_CTL_REG_SIZE ((CPH_CFIFO_CPH_CTL_2_OFFSET - CPH_CFIFO_CPH_CTL_1_OFFSET)/sizeof(cUInt32))
/* Time stamp register size for each channel */
#define CHAL_CAPH_CFIFO_TS_REG_SIZE ((CPH_CFIFO_CPH_CFIFO_TIMESTAMP_CH2_OFFSET-CPH_CFIFO_CPH_CFIFO_TIMESTAMP_CH1_OFFSET)/sizeof(cUInt32))
/* Read CFIFO_CTL_X register contents */
#define CHAL_READ_CFIFO_CTL_IDX(b, i, val) \
if(i < 8) \
{ \
val = BRCM_READ_REG_IDX( b, CPH_CFIFO_CPH_CTL_1 , ((i/2)*CHAL_CAPH_CFIFO_CTL_REG_SIZE)); \
} \
else \
{ \
val = BRCM_READ_REG_IDX( b, CPH_CFIFO_CPH_CTL_5 , (((i-8)/2)*CHAL_CAPH_CFIFO_CTL_REG_SIZE)); \
}
/* Write CFIFO_CTL_X register */
#define CHAL_WRITE_CFIFO_CTL_IDX(b, i, val) \
if(i < 8) \
{ \
BRCM_WRITE_REG_IDX( b, CPH_CFIFO_CPH_CTL_1 , ((i/2)*CHAL_CAPH_CFIFO_CTL_REG_SIZE), val); \
} \
else \
{ \
BRCM_WRITE_REG_IDX( b, CPH_CFIFO_CPH_CTL_5 , (((i-8)/2)*CHAL_CAPH_CFIFO_CTL_REG_SIZE), val); \
}
/*
* ****************************************************************************
* local typedef declarations
* ****************************************************************************
*/
typedef struct
{
cUInt32 base; /* Register Base address */
_Bool alloc_status[CHAL_CAPH_CFIFO_MAX_FIFOS]; /* allocation status for each FIFO */
cUInt16 addr[CHAL_CAPH_CFIFO_MAX_FIFOS]; /* Size of each FIFO */
cUInt16 size[CHAL_CAPH_CFIFO_MAX_FIFOS]; /* Size of each FIFO */
} chal_caph_cfifo_cb_t;
/*
* ****************************************************************************
* local variable definitions
* ****************************************************************************
*/
/* chal control block where all information is stored */
static chal_caph_cfifo_cb_t chal_caph_cfifo_cb;
/*
* ****************************************************************************
* local function declarations
* ****************************************************************************
*/
/*
* ******************************************************************************
* local function definitions
* ******************************************************************************
*/
/****************************************************************************
*
* Function Name: CHAL_HANDLE chal_caph_cfifo_init(cUInt32 baseAddress)
*
* Description: init CAPH CFIFO block
*
****************************************************************************/
CHAL_HANDLE chal_caph_cfifo_init(cUInt32 baseAddress)
{
cUInt8 fifo;
/* Go through all the FIFOs and set them not allocated */
for(fifo=0; fifo < CHAL_CAPH_CFIFO_MAX_FIFOS; fifo++)
{
chal_caph_cfifo_cb.alloc_status[fifo] = FALSE;
}
/* Set the register base address to the caller supplied base address */
chal_caph_cfifo_cb.base = baseAddress;
return(CHAL_HANDLE)(&chal_caph_cfifo_cb);
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_deinit(CHAL_HANDLE handle)
*
* Description: deinit CAPH CFIFO block
*
****************************************************************************/
void chal_caph_cfifo_deinit(CHAL_HANDLE handle)
{
chal_caph_cfifo_cb_t *pchal_cb = (chal_caph_cfifo_cb_t*)handle;
cUInt8 fifo;
/* Go through all the FIFOs and set them not allocated */
for(fifo=0; fifo < CHAL_CAPH_CFIFO_MAX_FIFOS; fifo++)
{
pchal_cb->alloc_status[fifo] = FALSE;
}
/* Reset the register base address */
pchal_cb->base = 0;
return;
}
/****************************************************************************
*
* Function Name: cUInt16 chal_caph_cfifo_get_fifo_addr(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo)
*
* Description: get CAPH CFIFO address
*
****************************************************************************/
cUInt32 chal_caph_cfifo_get_fifo_addr(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 addr = 0;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
addr = (base + index*CHAL_CAPH_CFIFO_PADDR_REG_SIZE*sizeof(cUInt32));
break;
}
}
return addr;
}
/****************************************************************************
*
* Function Name: cUInt16 chal_caph_cfifo_get_fifo_addr_offset(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo)
*
* Description: get CAPH CFIFO address
*
****************************************************************************/
cUInt32 chal_caph_cfifo_get_fifo_addr_offset(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo)
{
cUInt8 index;
cUInt32 addr = 0;
(void)handle;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
addr = (index*CHAL_CAPH_CFIFO_PADDR_REG_SIZE*sizeof(cUInt32));
break;
}
}
return addr;
}
/****************************************************************************
*
* Function Name: cUInt16 chal_caph_cfifo_get_fifo_addr(CAPH_CFIFO_e fifo)
*
*
* Description: index to the CFIFO
*
****************************************************************************/
int chal_caph_cfifo_get_fifo_index(CAPH_CFIFO_e fifo)
{
cUInt8 index;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
return index;
}
}
return -1;
}
/****************************************************************************
*
* Function Name: CAPH_CFIFO_CHANNEL_e chal_caph_cfifo_alloc_channel(CHAL_HANDLE handle)
*
* Description: allocate CAPH CFIFO channel
*
****************************************************************************/
CAPH_CFIFO_e chal_caph_cfifo_alloc_channel(CHAL_HANDLE handle)
{
chal_caph_cfifo_cb_t *pchal_cb = (chal_caph_cfifo_cb_t*)handle;
cUInt32 fifo = 0;
if(fifo==0)
{
/* Look for a free (non-allocated) channel */
for(;fifo<CHAL_CAPH_CFIFO_MAX_FIFOS;fifo++)
{
if(pchal_cb->alloc_status[fifo] == FALSE)
{
/* Found one */
break;
}
}
}
if(fifo < CHAL_CAPH_CFIFO_MAX_FIFOS)
{
/* Found a free channel */
pchal_cb->alloc_status[fifo] = TRUE;
}
/* Convert to CAPH_CFIFO_CHANNEL_e format and return */
return (CAPH_CFIFO_e)(1UL << fifo);
}
/****************************************************************************
*
* Function Name: CAPH_CFIFO_CHANNEL_e chal_caph_cfifo_alloc_channel(CHAL_HANDLE handle, CAPH_CFIFO_e channel)
*
* Description: allocate a given CAPH CFIFO channel
*
****************************************************************************/
CAPH_CFIFO_e chal_caph_cfifo_alloc_given_channel(CHAL_HANDLE handle, CAPH_CFIFO_e channel)
{
chal_caph_cfifo_cb_t *pchal_cb = (chal_caph_cfifo_cb_t*)handle;
cUInt32 ch = 0;
if(channel != CAPH_CFIFO_VOID)
{
/* Look whether the given channel is allocated or not */
for(;ch<CHAL_CAPH_CFIFO_MAX_FIFOS;ch++)
{
if((1UL << ch)&channel)
{
if(pchal_cb->alloc_status[ch] == FALSE)
{
/* Requested channel is not allocated */
break;
}
}
}
/* Requested channel is already allocated */
}
else
{
/* Look for a free (non-allocated) channel */
for(;ch<CHAL_CAPH_CFIFO_MAX_FIFOS;ch++)
{
if(pchal_cb->alloc_status[ch] == FALSE)
{
/* Found one */
break;
}
}
}
if(ch < CHAL_CAPH_CFIFO_MAX_FIFOS)
{
/* Found a free channel */
pchal_cb->alloc_status[ch] = TRUE;
}
/* Convert to CAPH_DMA_CHANNEL_e format and return */
return (CAPH_CFIFO_e)(1UL << ch);
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_free_channel(CHAL_HANDLE handle,
* CAPH_CFIFO_CHANNEL_e channel)
*
* Description: free CAPH CFIFO channel
*
****************************************************************************/
void chal_caph_cfifo_free_channel(CHAL_HANDLE handle, CAPH_CFIFO_e fifo)
{
chal_caph_cfifo_cb_t *pchal_cb = (chal_caph_cfifo_cb_t*)handle;
cUInt8 index;
/* Find the channel we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the channel we are looking for, make this channel free for next allocation */
pchal_cb->alloc_status[index] = FALSE;
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_enable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: enable CAPH CFIFOs
*
****************************************************************************/
void chal_caph_cfifo_enable(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, enable the FIFO */
reg_val = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
reg_val |= CPH_CFIFO_CPH_CR_1_CH1_CENTRAL_FIFO_ENABLE_MASK;
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), reg_val);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_disable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: disable CAPH CFIFOs
*
****************************************************************************/
void chal_caph_cfifo_disable(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
reg_val = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
reg_val &= ~CPH_CFIFO_CPH_CR_1_CH1_CENTRAL_FIFO_ENABLE_MASK;
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), reg_val);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_set_direction(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* CAPH_CFIFO_CHNL_DIRECTION_e direction)
*
* Description: config CAPH CFIFO channel transfer direction
*
****************************************************************************/
void chal_caph_cfifo_set_direction(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
CAPH_CFIFO_CHNL_DIRECTION_e direction)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
reg_val = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1 , (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* configure direction */
reg_val &= ~CPH_CFIFO_CPH_CR_1_CH1_IN_OUT_MASK;
reg_val |= (direction << CPH_CFIFO_CPH_CR_1_CH1_IN_OUT_SHIFT);
/* Apply the settings to the register */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_set_address(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* cUInt32 address)
*
* Description: config CAPH CFIFO channel start address
*
****************************************************************************/
void chal_caph_cfifo_set_address(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
cUInt32 address)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* Need to revisit this function as we will be pre-configuring the FIFO size and address */
/* How does the caller knows how to get address and size */
/* found the FIFO we are looking for*/
CHAL_READ_CFIFO_CTL_IDX(base, index, reg_val);
((chal_caph_cfifo_cb_t*)handle)->addr[index] = address;
address /= sizeof(cUInt32);
if(index&0x01)
{
/* configure start address */
reg_val &= ~CPH_CFIFO_CPH_CTL_1_CH2_START_ADDR_MASK;
reg_val |= ((address&CPH_CFIFO_CPH_CTL_1_CH1_START_ADDR_MASK) << CPH_CFIFO_CPH_CTL_1_CH2_START_ADDR_SHIFT);
}
else
{
/* configure start address */
reg_val &= ~CPH_CFIFO_CPH_CTL_1_CH1_START_ADDR_MASK;
reg_val |= ((address&CPH_CFIFO_CPH_CTL_1_CH1_START_ADDR_MASK) << CPH_CFIFO_CPH_CTL_1_CH1_START_ADDR_SHIFT);
}
/* Apply the settings to the register */
CHAL_WRITE_CFIFO_CTL_IDX(base, index, reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_set_size(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* cUInt16 size)
*
* Description: config CAPH CFIFO channel
*
****************************************************************************/
void chal_caph_cfifo_set_size(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
cUInt16 size)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 reg_val;
/* Convert ths size to 32bit value */
size = size/sizeof(cUInt32);
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* Need to revisit this function as we will be pre-configuring the FIFO size and address */
/* How does the caller knows how to get address and size */
/* found the FIFO we are looking for */
CHAL_READ_CFIFO_CTL_IDX(base, index, reg_val);
((chal_caph_cfifo_cb_t*)handle)->size[index] = size;
/* Convert it in to register format */
if(size >= 128)
{
size = (size/64) - 1;
}
else
{
size = 0;
}
if(index&0x01)
{
/* configure size */
reg_val &= ~CPH_CFIFO_CPH_CTL_1_CH2_RING_SIZE_MASK;
reg_val |= ((size&0x1F) << CPH_CFIFO_CPH_CTL_1_CH2_RING_SIZE_SHIFT);
}
else
{
/* configure size */
reg_val &= ~CPH_CFIFO_CPH_CTL_1_CH1_RING_SIZE_MASK;
reg_val |= ((size&0x1F) << CPH_CFIFO_CPH_CTL_1_CH1_RING_SIZE_SHIFT);
}
/* Apply the settings to the register */
CHAL_WRITE_CFIFO_CTL_IDX(base, index, reg_val);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_queue_add_fifo(CHAL_HANDLE handle,
* cUInt16 fifo,
* CAPH_CFIFO_QUEUE_e queue)
*
* Description: add fifos to queue
*
****************************************************************************/
void chal_caph_cfifo_queue_add_fifo(CHAL_HANDLE handle,
cUInt16 fifo,
CAPH_CFIFO_QUEUE_e queue)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt32 arb;
switch(queue)
{
case CAPH_CFIFO_QUEUE2:
/* put it in Q2*/
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_1);
arb |= (fifo << CPH_CFIFO_CPH_ARB_CTL_1_Q2_MASK_SHIFT);
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_1, arb);
break;
case CAPH_CFIFO_QUEUE3:
/* put it in Q3 */
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_2);
arb |= (fifo << CPH_CFIFO_CPH_ARB_CTL_2_Q3_MASK_SHIFT);
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_2, arb);
break;
default:
/* put it in Q1 (default) */
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_1);
arb |= (fifo << CPH_CFIFO_CPH_ARB_CTL_1_Q1_MASK_SHIFT);
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_1, arb);
break;
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_queue_remove_fifo(CHAL_HANDLE handle,
* cUInt16 fifo,
* CAPH_CFIFO_QUEUE_e queue)
*
* Description: remove fifos from queue
*
****************************************************************************/
void chal_caph_cfifo_queue_remove_fifo(CHAL_HANDLE handle,
cUInt16 fifo,
CAPH_CFIFO_QUEUE_e queue)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt32 arb;
cUInt32 rem_arb;
switch(queue)
{
case CAPH_CFIFO_QUEUE2:
/* take it from Q2 */
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_1);
rem_arb = (fifo << CPH_CFIFO_CPH_ARB_CTL_1_Q2_MASK_SHIFT);
arb &= ~rem_arb;
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_1, arb);
break;
case CAPH_CFIFO_QUEUE3:
/* take it from Q3 */
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_2);
rem_arb = (fifo << CPH_CFIFO_CPH_ARB_CTL_2_Q3_MASK_SHIFT);
arb &= ~rem_arb;
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_2, arb);
break;
default:
/* take it from Q1 (default) */
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_1);
rem_arb = (fifo << CPH_CFIFO_CPH_ARB_CTL_1_Q1_MASK_SHIFT);
arb &= ~rem_arb;
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_1, arb);
break;
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_set_panic_timer(CHAL_HANDLE handle,
* cUInt8 timeout)
*
* Description: set CFIFO channel panic timeout value
*
****************************************************************************/
void chal_caph_cfifo_set_panic_timer(CHAL_HANDLE handle,
cUInt8 timeout)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt32 reg_val;
/* Read the panic timer value */
reg_val = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_2);
/* Clear the current timeout value */
reg_val &= ~CPH_CFIFO_CPH_ARB_CTL_2_CH_TIMER_DEFAULTS_MASK;
/* Add the new timeout value */
reg_val |= (timeout << CPH_CFIFO_CPH_ARB_CTL_2_CH_TIMER_DEFAULTS_SHIFT);
/* Program the panic timer value */
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_2, reg_val);
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_set_arb(CHAL_HANDLE handle,
* cUInt32 key)
*
* Description: set arb pattern
*
****************************************************************************/
void chal_caph_cfifo_set_arb(CHAL_HANDLE handle,
cUInt32 key)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt32 arb;
/* Get the current arbitration pattern */
arb = BRCM_READ_REG( base, CPH_CFIFO_CPH_ARB_CTL_3);
/* clear and set the new pattern */
arb &= ~ CPH_CFIFO_CPH_ARB_CTL_3_ARB_PATTERN_MASK;
arb |= ((key & CPH_CFIFO_CPH_ARB_CTL_3_ARB_PATTERN_MASK) << CPH_CFIFO_CPH_ARB_CTL_3_ARB_PATTERN_SHIFT);
/* Apply the changes to the Hardware */
BRCM_WRITE_REG(base, CPH_CFIFO_CPH_ARB_CTL_3, arb);
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_set_fifo_thres(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* cUInt16 thres,
* cUInt16 thres2)
*
* Description: set fifo thresholds
*
****************************************************************************/
void chal_caph_cfifo_set_fifo_thres(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
cUInt16 thres,
cUInt16 thres2)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 cr;
/* Convert them to 32bit sizes */
thres = thres/sizeof(cUInt32);
thres2 = thres2/sizeof(cUInt32);
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Clear and configure the threshold */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_THRES_MASK;
thres &= (CPH_CFIFO_CPH_CR_1_CH1_THRES_MASK >> CPH_CFIFO_CPH_CR_1_CH1_THRES_SHIFT);
cr |= (thres << CPH_CFIFO_CPH_CR_1_CH1_THRES_SHIFT);
/* Clear and configure the threshold2 */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_THRES2_MASK;
thres2 &= (CPH_CFIFO_CPH_CR_1_CH1_THRES2_MASK >> CPH_CFIFO_CPH_CR_1_CH1_THRES2_SHIFT);
cr |= (thres2 << CPH_CFIFO_CPH_CR_1_CH1_THRES2_SHIFT);
/* Apply the changes to hardware */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
break;
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_clr_fifo(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: clear fifo
*
****************************************************************************/
void chal_caph_cfifo_clr_fifo(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 cr;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Send Reset Pulse to the Hardware. First make sure it is 0, set to 1, then clear to 0 */
/* Clear Reset */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_CLR_FIFO_MASK;
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
/* Start Reset process on Hardware*/
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
cr |= CPH_CFIFO_CPH_CR_1_CH1_CLR_FIFO_MASK;
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
/* Clear Reset */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_CLR_FIFO_MASK;
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_int_enable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: enable the fifo int
*
****************************************************************************/
void chal_caph_cfifo_int_enable(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 cr;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Enable interrupt */
cr |= CPH_CFIFO_CPH_CR_1_CH1_INTR_EN_MASK;
/* Apply the setting to Hardware */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_int_err_enable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: enable the fifo err int
*
****************************************************************************/
void chal_caph_cfifo_int_err_enable(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 cr;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Enable interrupt */
cr |= CPH_CFIFO_CPH_CR_1_CH1_ERR_INT_ENABLE_MASK;
/* Apply the setting to Hardware */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_int_disable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: enable the fifo int
*
****************************************************************************/
void chal_caph_cfifo_int_disable(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 cr;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Enable interrupt */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_INTR_EN_MASK;
/* Apply the setting to Hardware */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
}
}
return;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_int_err_disable(CHAL_HANDLE handle,
* cUInt16 fifo)
*
* Description: enable the fifo err int
*
****************************************************************************/
void chal_caph_cfifo_int_err_disable(CHAL_HANDLE handle,
cUInt16 fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 cr;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* Enable interrupt */
cr &= ~CPH_CFIFO_CPH_CR_1_CH1_ERR_INT_ENABLE_MASK;
/* Apply the setting to Hardware */
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE), cr);
}
}
return;
}
/****************************************************************************
*
* Function Name: cUInt32 chal_caph_cfifo_read_fifo_status(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo)
*
* Description: read fifo status
*
****************************************************************************/
cUInt32 chal_caph_cfifo_read_fifo_status(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 status = 0;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++)
{
if((1UL << index)&fifo)
{
/* found the FIFO we are looking for, Disable the FIFO */
status = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_SR_1, (index*CHAL_CAPH_CFIFO_CR_REG_SIZE));
/* status >>= CPH_CFIFO_CPH_SR_1_CH1_EMPTY_ENTRY_SHIFT;*/
break;
}
}
return status;
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_write_fifo(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* cUInt32* data,
* cUInt16 size,
* _Bool forceovf)
*
* Description: write fifo
*
****************************************************************************/
cUInt16 chal_caph_cfifo_write_fifo(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
cUInt32* data,
cUInt16 size,
_Bool forceovf)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 findex;
cUInt16 dindex;
cUInt32 fsize = 0;
cUInt32 cr = 0;
/* Convert the size into 32bit words */
size = size/sizeof(cUInt32);
/* Find the FIFOs we are looking for */
for(findex = 0; findex < CHAL_CAPH_CFIFO_MAX_FIFOS; findex++)
{
if((1UL << findex)&fifo)
{
/* Check whether the FIFO is writable or not */
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (findex*CHAL_CAPH_CFIFO_CR_REG_SIZE));
if(cr & CPH_CFIFO_CPH_CR_1_CH1_IN_OUT_MASK)
{
fsize = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_SR_1, (findex*CHAL_CAPH_CFIFO_CR_REG_SIZE));
fsize &= CPH_CFIFO_CPH_SR_1_CH1_EMPTY_ENTRY_MASK;
fsize >>= CPH_CFIFO_CPH_SR_1_CH1_EMPTY_ENTRY_SHIFT;
if(forceovf == FALSE)
{
if(size > fsize)
{
size = fsize;
}
}
dindex = 0;
while(dindex<size)
{
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CH1_PADDR, (findex*CHAL_CAPH_CFIFO_PADDR_REG_SIZE), data[dindex++]);
}
}
break;
}
}
return (size*sizeof(cUInt32));
}
/****************************************************************************
*
* Function Name: void chal_caph_cfifo_read_fifo(CHAL_HANDLE handle,
* CAPH_CFIFO_e fifo,
* cUInt32* data,
* cUInt16 size,
* _Bool forceudf)
*
* Description: read fifo
*
****************************************************************************/
cUInt16 chal_caph_cfifo_read_fifo(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo,
cUInt32* data,
cUInt16 size,
_Bool forceudf)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 findex;
cUInt16 dindex;
cUInt32 fsize = 0;
cUInt32 cr = 0;
/* Convert the size into 32bit words */
size = size/sizeof(cUInt32);
/* Find the FIFOs we are looking for */
for(findex = 0; findex < CHAL_CAPH_CFIFO_MAX_FIFOS; findex++)
{
if((1UL << findex)&fifo)
{
/* Check whether the FIFO is writable or not */
/* found the FIFO we are looking for, Disable the FIFO */
cr = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CR_1, (findex*CHAL_CAPH_CFIFO_CR_REG_SIZE));
if(!(cr & CPH_CFIFO_CPH_CR_1_CH1_IN_OUT_MASK))
{
fsize = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_SR_1, (findex*CHAL_CAPH_CFIFO_CR_REG_SIZE));
fsize &= CPH_CFIFO_CPH_SR_1_CH1_EMPTY_ENTRY_MASK;
fsize >>= CPH_CFIFO_CPH_SR_1_CH1_EMPTY_ENTRY_SHIFT;
fsize = ((chal_caph_cfifo_cb_t*)handle)->size[findex] - fsize;
if(forceudf == FALSE)
{
if(size > fsize)
{
size = fsize;
}
}
dindex = 0;
while(dindex<size)
{
data[dindex++] = BRCM_READ_REG_IDX(base, CPH_CFIFO_CH1_PADDR, (findex*CHAL_CAPH_CFIFO_PADDR_REG_SIZE) );
}
}
break;
}
}
return (size*sizeof(cUInt32));
}
/****************************************************************************
*
* Function Name: cUInt32 chal_caph_cfifo_read_timestamp(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo)
*
* Description: read TS for channel 1 to 4
*
****************************************************************************/
cUInt32 chal_caph_cfifo_read_timestamp(CHAL_HANDLE handle,
CAPH_CFIFO_e fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t*)handle)->base;
cUInt8 index;
cUInt32 ts = 0;
/* Find the FIFOs we are looking for */
for(index = 0; index < CHAL_CAPH_CFIFO_MAX_TS_CHANNELS; index++)
{
if((1UL << index)&fifo)
{
/* Check whether the FIFO is writable or not */
/* found the FIFO we are looking for, Disable the FIFO */
ts = BRCM_READ_REG_IDX( base, CPH_CFIFO_CPH_CFIFO_TIMESTAMP_CH1, (index*CHAL_CAPH_CFIFO_TS_REG_SIZE));
break;
}
}
return ts;
}
/****************************************************************************
*
* Function Name: cVoid chal_caph_fifo_clear_register(CHAL_HANDLE handle,
CAPH_CFIFO_e chal_fifo)
*
* Description: Clears the cfifo register
*
****************************************************************************/
cVoid chal_caph_fifo_clear_register(CHAL_HANDLE handle, CAPH_CFIFO_e chal_fifo)
{
cUInt32 base = ((chal_caph_cfifo_cb_t *) handle)->base;
cUInt8 index;
cUInt32 cr = 0;
/* found the FIFO we are looking for, clear the FIFO */
for (index = 0; index < CHAL_CAPH_CFIFO_MAX_FIFOS; index++) {
if ((1UL << index) & chal_fifo) {
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CH1_PADDR,
index * CHAL_CAPH_CFIFO_PADDR_REG_SIZE, cr);
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_CR_1,
index * CHAL_CAPH_CFIFO_CR_REG_SIZE, cr);
BRCM_WRITE_REG_IDX(base, CPH_CFIFO_CPH_SR_1,
index * CHAL_CAPH_CFIFO_CR_REG_SIZE, cr);
}
}
return;
}
#if defined( __KERNEL__ )
#include <linux/module.h>
EXPORT_SYMBOL(chal_caph_cfifo_init);
EXPORT_SYMBOL(chal_caph_cfifo_deinit);
EXPORT_SYMBOL(chal_caph_cfifo_get_fifo_addr);
EXPORT_SYMBOL(chal_caph_cfifo_get_fifo_addr_offset);
EXPORT_SYMBOL(chal_caph_cfifo_get_fifo_index);
EXPORT_SYMBOL(chal_caph_cfifo_alloc_channel);
EXPORT_SYMBOL(chal_caph_cfifo_alloc_given_channel);
EXPORT_SYMBOL(chal_caph_cfifo_free_channel);
EXPORT_SYMBOL(chal_caph_cfifo_enable);
EXPORT_SYMBOL(chal_caph_cfifo_disable);
EXPORT_SYMBOL(chal_caph_cfifo_set_direction);
EXPORT_SYMBOL(chal_caph_cfifo_set_address);
EXPORT_SYMBOL(chal_caph_cfifo_set_size);
EXPORT_SYMBOL(chal_caph_cfifo_queue_add_fifo);
EXPORT_SYMBOL(chal_caph_cfifo_queue_remove_fifo);
EXPORT_SYMBOL(chal_caph_cfifo_set_panic_timer);
EXPORT_SYMBOL(chal_caph_cfifo_set_arb);
EXPORT_SYMBOL(chal_caph_cfifo_set_fifo_thres);
EXPORT_SYMBOL(chal_caph_cfifo_clr_fifo);
EXPORT_SYMBOL(chal_caph_cfifo_int_enable);
EXPORT_SYMBOL(chal_caph_cfifo_int_err_enable);
EXPORT_SYMBOL(chal_caph_cfifo_int_disable);
EXPORT_SYMBOL(chal_caph_cfifo_int_err_disable);
EXPORT_SYMBOL(chal_caph_cfifo_read_fifo_status);
EXPORT_SYMBOL(chal_caph_cfifo_write_fifo);
EXPORT_SYMBOL(chal_caph_cfifo_read_fifo);
EXPORT_SYMBOL(chal_caph_cfifo_read_timestamp);
EXPORT_SYMBOL(chal_caph_fifo_clear_register);
#endif
| gpl-2.0 |
zlatinski/omap-android-drm-kms | drivers/mmc/core/bus.c | 356 | 7483 | /*
* linux/drivers/mmc/core/bus.c
*
* Copyright (C) 2003 Russell King, All Rights Reserved.
* Copyright (C) 2007 Pierre Ossman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* MMC card bus driver model
*/
#include <linux/export.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/stat.h>
#include <linux/pm_runtime.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include "core.h"
#include "sdio_cis.h"
#include "bus.h"
#define to_mmc_driver(d) container_of(d, struct mmc_driver, drv)
static ssize_t mmc_type_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct mmc_card *card = mmc_dev_to_card(dev);
switch (card->type) {
case MMC_TYPE_MMC:
return sprintf(buf, "MMC\n");
case MMC_TYPE_SD:
return sprintf(buf, "SD\n");
case MMC_TYPE_SDIO:
return sprintf(buf, "SDIO\n");
case MMC_TYPE_SD_COMBO:
return sprintf(buf, "SDcombo\n");
default:
return -EFAULT;
}
}
static struct device_attribute mmc_dev_attrs[] = {
__ATTR(type, S_IRUGO, mmc_type_show, NULL),
__ATTR_NULL,
};
/*
* This currently matches any MMC driver to any MMC card - drivers
* themselves make the decision whether to drive this card in their
* probe method.
*/
static int mmc_bus_match(struct device *dev, struct device_driver *drv)
{
return 1;
}
static int
mmc_bus_uevent(struct device *dev, struct kobj_uevent_env *env)
{
struct mmc_card *card = mmc_dev_to_card(dev);
const char *type;
int retval = 0;
switch (card->type) {
case MMC_TYPE_MMC:
type = "MMC";
break;
case MMC_TYPE_SD:
type = "SD";
break;
case MMC_TYPE_SDIO:
type = "SDIO";
break;
case MMC_TYPE_SD_COMBO:
type = "SDcombo";
break;
default:
type = NULL;
}
if (type) {
retval = add_uevent_var(env, "MMC_TYPE=%s", type);
if (retval)
return retval;
}
retval = add_uevent_var(env, "MMC_NAME=%s", mmc_card_name(card));
if (retval)
return retval;
/*
* Request the mmc_block device. Note: that this is a direct request
* for the module it carries no information as to what is inserted.
*/
retval = add_uevent_var(env, "MODALIAS=mmc:block");
return retval;
}
static int mmc_bus_probe(struct device *dev)
{
struct mmc_driver *drv = to_mmc_driver(dev->driver);
struct mmc_card *card = mmc_dev_to_card(dev);
return drv->probe(card);
}
static int mmc_bus_remove(struct device *dev)
{
struct mmc_driver *drv = to_mmc_driver(dev->driver);
struct mmc_card *card = mmc_dev_to_card(dev);
drv->remove(card);
return 0;
}
static int mmc_bus_suspend(struct device *dev)
{
struct mmc_driver *drv = to_mmc_driver(dev->driver);
struct mmc_card *card = mmc_dev_to_card(dev);
int ret = 0;
if (dev->driver && drv->suspend)
ret = drv->suspend(card);
return ret;
}
static int mmc_bus_resume(struct device *dev)
{
struct mmc_driver *drv = to_mmc_driver(dev->driver);
struct mmc_card *card = mmc_dev_to_card(dev);
int ret = 0;
if (dev->driver && drv->resume)
ret = drv->resume(card);
return ret;
}
#ifdef CONFIG_PM_RUNTIME
static int mmc_runtime_suspend(struct device *dev)
{
struct mmc_card *card = mmc_dev_to_card(dev);
return mmc_power_save_host(card->host);
}
static int mmc_runtime_resume(struct device *dev)
{
struct mmc_card *card = mmc_dev_to_card(dev);
return mmc_power_restore_host(card->host);
}
static int mmc_runtime_idle(struct device *dev)
{
return pm_runtime_suspend(dev);
}
#endif /* !CONFIG_PM_RUNTIME */
static const struct dev_pm_ops mmc_bus_pm_ops = {
SET_RUNTIME_PM_OPS(mmc_runtime_suspend, mmc_runtime_resume,
mmc_runtime_idle)
SET_SYSTEM_SLEEP_PM_OPS(mmc_bus_suspend, mmc_bus_resume)
};
static struct bus_type mmc_bus_type = {
.name = "mmc",
.dev_attrs = mmc_dev_attrs,
.match = mmc_bus_match,
.uevent = mmc_bus_uevent,
.probe = mmc_bus_probe,
.remove = mmc_bus_remove,
.pm = &mmc_bus_pm_ops,
};
int mmc_register_bus(void)
{
return bus_register(&mmc_bus_type);
}
void mmc_unregister_bus(void)
{
bus_unregister(&mmc_bus_type);
}
/**
* mmc_register_driver - register a media driver
* @drv: MMC media driver
*/
int mmc_register_driver(struct mmc_driver *drv)
{
drv->drv.bus = &mmc_bus_type;
return driver_register(&drv->drv);
}
EXPORT_SYMBOL(mmc_register_driver);
/**
* mmc_unregister_driver - unregister a media driver
* @drv: MMC media driver
*/
void mmc_unregister_driver(struct mmc_driver *drv)
{
drv->drv.bus = &mmc_bus_type;
driver_unregister(&drv->drv);
}
EXPORT_SYMBOL(mmc_unregister_driver);
static void mmc_release_card(struct device *dev)
{
struct mmc_card *card = mmc_dev_to_card(dev);
sdio_free_common_cis(card);
if (card->info)
kfree(card->info);
kfree(card);
}
/*
* Allocate and initialise a new MMC card structure.
*/
struct mmc_card *mmc_alloc_card(struct mmc_host *host, struct device_type *type)
{
struct mmc_card *card;
card = kzalloc(sizeof(struct mmc_card), GFP_KERNEL);
if (!card)
return ERR_PTR(-ENOMEM);
card->host = host;
device_initialize(&card->dev);
card->dev.parent = mmc_classdev(host);
card->dev.bus = &mmc_bus_type;
card->dev.release = mmc_release_card;
card->dev.type = type;
return card;
}
/*
* Register a new MMC card with the driver model.
*/
int mmc_add_card(struct mmc_card *card)
{
int ret;
const char *type;
const char *uhs_bus_speed_mode = "";
static const char *const uhs_speeds[] = {
[UHS_SDR12_BUS_SPEED] = "SDR12 ",
[UHS_SDR25_BUS_SPEED] = "SDR25 ",
[UHS_SDR50_BUS_SPEED] = "SDR50 ",
[UHS_SDR104_BUS_SPEED] = "SDR104 ",
[UHS_DDR50_BUS_SPEED] = "DDR50 ",
};
dev_set_name(&card->dev, "%s:%04x", mmc_hostname(card->host), card->rca);
switch (card->type) {
case MMC_TYPE_MMC:
type = "MMC";
break;
case MMC_TYPE_SD:
type = "SD";
if (mmc_card_blockaddr(card)) {
if (mmc_card_ext_capacity(card))
type = "SDXC";
else
type = "SDHC";
}
break;
case MMC_TYPE_SDIO:
type = "SDIO";
break;
case MMC_TYPE_SD_COMBO:
type = "SD-combo";
if (mmc_card_blockaddr(card))
type = "SDHC-combo";
break;
default:
type = "?";
break;
}
if (mmc_sd_card_uhs(card) &&
(card->sd_bus_speed < ARRAY_SIZE(uhs_speeds)))
uhs_bus_speed_mode = uhs_speeds[card->sd_bus_speed];
if (mmc_host_is_spi(card->host)) {
pr_info("%s: new %s%s%s card on SPI\n",
mmc_hostname(card->host),
mmc_card_highspeed(card) ? "high speed " : "",
mmc_card_ddr_mode(card) ? "DDR " : "",
type);
} else {
pr_info("%s: new %s%s%s%s%s card at address %04x\n",
mmc_hostname(card->host),
mmc_card_uhs(card) ? "ultra high speed " :
(mmc_card_highspeed(card) ? "high speed " : ""),
(mmc_card_hs200(card) ? "HS200 " : ""),
mmc_card_ddr_mode(card) ? "DDR " : "",
uhs_bus_speed_mode, type, card->rca);
}
#ifdef CONFIG_DEBUG_FS
mmc_add_card_debugfs(card);
#endif
ret = device_add(&card->dev);
if (ret)
return ret;
mmc_card_set_present(card);
return 0;
}
/*
* Unregister a new MMC card with the driver model, and
* (eventually) free it.
*/
void mmc_remove_card(struct mmc_card *card)
{
#ifdef CONFIG_DEBUG_FS
mmc_remove_card_debugfs(card);
#endif
if (mmc_card_present(card)) {
if (mmc_host_is_spi(card->host)) {
pr_info("%s: SPI card removed\n",
mmc_hostname(card->host));
} else {
pr_info("%s: card %04x removed\n",
mmc_hostname(card->host), card->rca);
}
device_del(&card->dev);
}
put_device(&card->dev);
}
| gpl-2.0 |
asyan4ik/android_kernel_huawei_h60 | sound/pci/rme9652/hdspm.c | 356 | 179409 | /*
* ALSA driver for RME Hammerfall DSP MADI audio interface(s)
*
* Copyright (c) 2003 Winfried Ritsch (IEM)
* code based on hdsp.c Paul Davis
* Marcus Andersson
* Thomas Charbonnel
* Modified 2006-06-01 for AES32 support by Remy Bruno
* <remy.bruno@trinnov.com>
*
* Modified 2009-04-13 for proper metering by Florian Faber
* <faber@faberman.de>
*
* Modified 2009-04-14 for native float support by Florian Faber
* <faber@faberman.de>
*
* Modified 2009-04-26 fixed bug in rms metering by Florian Faber
* <faber@faberman.de>
*
* Modified 2009-04-30 added hw serial number support by Florian Faber
*
* Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
*
* Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/math64.h>
#include <asm/io.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/info.h>
#include <sound/asoundef.h>
#include <sound/rawmidi.h>
#include <sound/hwdep.h>
#include <sound/initval.h>
#include <sound/hdspm.h>
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
MODULE_AUTHOR
(
"Winfried Ritsch <ritsch_AT_iem.at>, "
"Paul Davis <paul@linuxaudiosystems.com>, "
"Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
"Remy Bruno <remy.bruno@trinnov.com>, "
"Florian Faber <faberman@linuxproaudio.org>, "
"Adrian Knoth <adi@drcomp.erfurt.thur.de>"
);
MODULE_DESCRIPTION("RME HDSPM");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
/* --- Write registers. ---
These are defined as byte-offsets from the iobase value. */
#define HDSPM_WR_SETTINGS 0
#define HDSPM_outputBufferAddress 32
#define HDSPM_inputBufferAddress 36
#define HDSPM_controlRegister 64
#define HDSPM_interruptConfirmation 96
#define HDSPM_control2Reg 256 /* not in specs ???????? */
#define HDSPM_freqReg 256 /* for AES32 */
#define HDSPM_midiDataOut0 352 /* just believe in old code */
#define HDSPM_midiDataOut1 356
#define HDSPM_eeprom_wr 384 /* for AES32 */
/* DMA enable for 64 channels, only Bit 0 is relevant */
#define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
#define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
/* 16 page addresses for each of the 64 channels DMA buffer in and out
(each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
#define HDSPM_pageAddressBufferOut 8192
#define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
#define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
#define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
/* --- Read registers. ---
These are defined as byte-offsets from the iobase value */
#define HDSPM_statusRegister 0
/*#define HDSPM_statusRegister2 96 */
/* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
* offset 192, for AES32 *and* MADI
* => need to check that offset 192 is working on MADI */
#define HDSPM_statusRegister2 192
#define HDSPM_timecodeRegister 128
/* AIO, RayDAT */
#define HDSPM_RD_STATUS_0 0
#define HDSPM_RD_STATUS_1 64
#define HDSPM_RD_STATUS_2 128
#define HDSPM_RD_STATUS_3 192
#define HDSPM_RD_TCO 256
#define HDSPM_RD_PLL_FREQ 512
#define HDSPM_WR_TCO 128
#define HDSPM_TCO1_TCO_lock 0x00000001
#define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
#define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
#define HDSPM_TCO1_LTC_Input_valid 0x00000008
#define HDSPM_TCO1_WCK_Input_valid 0x00000010
#define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
#define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
#define HDSPM_TCO1_set_TC 0x00000100
#define HDSPM_TCO1_set_drop_frame_flag 0x00000200
#define HDSPM_TCO1_LTC_Format_LSB 0x00000400
#define HDSPM_TCO1_LTC_Format_MSB 0x00000800
#define HDSPM_TCO2_TC_run 0x00010000
#define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
#define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
#define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
#define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
#define HDSPM_TCO2_set_jam_sync 0x00200000
#define HDSPM_TCO2_set_flywheel 0x00400000
#define HDSPM_TCO2_set_01_4 0x01000000
#define HDSPM_TCO2_set_pull_down 0x02000000
#define HDSPM_TCO2_set_pull_up 0x04000000
#define HDSPM_TCO2_set_freq 0x08000000
#define HDSPM_TCO2_set_term_75R 0x10000000
#define HDSPM_TCO2_set_input_LSB 0x20000000
#define HDSPM_TCO2_set_input_MSB 0x40000000
#define HDSPM_TCO2_set_freq_from_app 0x80000000
#define HDSPM_midiDataOut0 352
#define HDSPM_midiDataOut1 356
#define HDSPM_midiDataOut2 368
#define HDSPM_midiDataIn0 360
#define HDSPM_midiDataIn1 364
#define HDSPM_midiDataIn2 372
#define HDSPM_midiDataIn3 376
/* status is data bytes in MIDI-FIFO (0-128) */
#define HDSPM_midiStatusOut0 384
#define HDSPM_midiStatusOut1 388
#define HDSPM_midiStatusOut2 400
#define HDSPM_midiStatusIn0 392
#define HDSPM_midiStatusIn1 396
#define HDSPM_midiStatusIn2 404
#define HDSPM_midiStatusIn3 408
/* the meters are regular i/o-mapped registers, but offset
considerably from the rest. the peak registers are reset
when read; the least-significant 4 bits are full-scale counters;
the actual peak value is in the most-significant 24 bits.
*/
#define HDSPM_MADI_INPUT_PEAK 4096
#define HDSPM_MADI_PLAYBACK_PEAK 4352
#define HDSPM_MADI_OUTPUT_PEAK 4608
#define HDSPM_MADI_INPUT_RMS_L 6144
#define HDSPM_MADI_PLAYBACK_RMS_L 6400
#define HDSPM_MADI_OUTPUT_RMS_L 6656
#define HDSPM_MADI_INPUT_RMS_H 7168
#define HDSPM_MADI_PLAYBACK_RMS_H 7424
#define HDSPM_MADI_OUTPUT_RMS_H 7680
/* --- Control Register bits --------- */
#define HDSPM_Start (1<<0) /* start engine */
#define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
#define HDSPM_Latency1 (1<<2) /* where n is defined */
#define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
#define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
#define HDSPM_c0Master 0x1 /* Master clock bit in settings
register [RayDAT, AIO] */
#define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
#define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
#define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
#define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
#define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
#define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
#define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
56channelMODE=0 */ /* MADI ONLY*/
#define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
#define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
0=off, 1=on */ /* MADI ONLY */
#define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
#define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
* -- MADI ONLY
*/
#define HDSPM_InputSelect1 (1<<15) /* should be 0 */
#define HDSPM_SyncRef2 (1<<13)
#define HDSPM_SyncRef3 (1<<25)
#define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
#define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
AES additional bits in
lower 5 Audiodatabits ??? */
#define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
#define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
#define HDSPM_Midi0InterruptEnable 0x0400000
#define HDSPM_Midi1InterruptEnable 0x0800000
#define HDSPM_Midi2InterruptEnable 0x0200000
#define HDSPM_Midi3InterruptEnable 0x4000000
#define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
#define HDSPe_FLOAT_FORMAT 0x2000000
#define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
#define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
#define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
#define HDSPM_wclk_sel (1<<30)
/* --- bit helper defines */
#define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
#define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
#define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
#define HDSPM_InputOptical 0
#define HDSPM_InputCoaxial (HDSPM_InputSelect0)
#define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
HDSPM_SyncRef2|HDSPM_SyncRef3)
#define HDSPM_c0_SyncRef0 0x2
#define HDSPM_c0_SyncRef1 0x4
#define HDSPM_c0_SyncRef2 0x8
#define HDSPM_c0_SyncRef3 0x10
#define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
#define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
#define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
#define HDSPM_SYNC_FROM_TCO 2
#define HDSPM_SYNC_FROM_SYNC_IN 3
#define HDSPM_Frequency32KHz HDSPM_Frequency0
#define HDSPM_Frequency44_1KHz HDSPM_Frequency1
#define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
#define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
#define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
#define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
HDSPM_Frequency0)
#define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
#define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
#define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
HDSPM_Frequency0)
/* Synccheck Status */
#define HDSPM_SYNC_CHECK_NO_LOCK 0
#define HDSPM_SYNC_CHECK_LOCK 1
#define HDSPM_SYNC_CHECK_SYNC 2
/* AutoSync References - used by "autosync_ref" control switch */
#define HDSPM_AUTOSYNC_FROM_WORD 0
#define HDSPM_AUTOSYNC_FROM_MADI 1
#define HDSPM_AUTOSYNC_FROM_TCO 2
#define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
#define HDSPM_AUTOSYNC_FROM_NONE 4
/* Possible sources of MADI input */
#define HDSPM_OPTICAL 0 /* optical */
#define HDSPM_COAXIAL 1 /* BNC */
#define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
#define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
#define hdspm_encode_in(x) (((x)&0x3)<<14)
#define hdspm_decode_in(x) (((x)>>14)&0x3)
/* --- control2 register bits --- */
#define HDSPM_TMS (1<<0)
#define HDSPM_TCK (1<<1)
#define HDSPM_TDI (1<<2)
#define HDSPM_JTAG (1<<3)
#define HDSPM_PWDN (1<<4)
#define HDSPM_PROGRAM (1<<5)
#define HDSPM_CONFIG_MODE_0 (1<<6)
#define HDSPM_CONFIG_MODE_1 (1<<7)
/*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
#define HDSPM_BIGENDIAN_MODE (1<<9)
#define HDSPM_RD_MULTIPLE (1<<10)
/* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
that do not conflict with specific bits for AES32 seem to be valid also
for the AES32
*/
#define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
#define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
#define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
* (like inp0)
*/
#define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
#define HDSPM_madiSync (1<<18) /* MADI is in sync */
#define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
#define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
#define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
#define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
#define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
/* since 64byte accurate, last 6 bits are not used */
#define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
#define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
#define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
#define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
#define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
#define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
* Interrupt
*/
#define HDSPM_tco_detect 0x08000000
#define HDSPM_tco_lock 0x20000000
#define HDSPM_s2_tco_detect 0x00000040
#define HDSPM_s2_AEBO_D 0x00000080
#define HDSPM_s2_AEBI_D 0x00000100
#define HDSPM_midi0IRQPending 0x40000000
#define HDSPM_midi1IRQPending 0x80000000
#define HDSPM_midi2IRQPending 0x20000000
#define HDSPM_midi2IRQPendingAES 0x00000020
#define HDSPM_midi3IRQPending 0x00200000
/* --- status bit helpers */
#define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
HDSPM_madiFreq2|HDSPM_madiFreq3)
#define HDSPM_madiFreq32 (HDSPM_madiFreq0)
#define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
#define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
#define HDSPM_madiFreq64 (HDSPM_madiFreq2)
#define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
#define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
#define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
#define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
#define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
/* Status2 Register bits */ /* MADI ONLY */
#define HDSPM_version0 (1<<0) /* not really defined but I guess */
#define HDSPM_version1 (1<<1) /* in former cards it was ??? */
#define HDSPM_version2 (1<<2)
#define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
#define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
#define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
#define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
#define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
/* missing Bit for 111=128, 1000=176.4, 1001=192 */
#define HDSPM_SyncRef0 0x10000 /* Sync Reference */
#define HDSPM_SyncRef1 0x20000
#define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
#define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
#define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
#define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
#define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
#define HDSPM_wcFreq32 (HDSPM_wc_freq0)
#define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
#define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
#define HDSPM_wcFreq64 (HDSPM_wc_freq2)
#define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
#define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
#define HDSPM_status1_F_0 0x0400000
#define HDSPM_status1_F_1 0x0800000
#define HDSPM_status1_F_2 0x1000000
#define HDSPM_status1_F_3 0x2000000
#define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
#define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
HDSPM_SelSyncRef2)
#define HDSPM_SelSyncRef_WORD 0
#define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
#define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
#define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
#define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
HDSPM_SelSyncRef2)
/*
For AES32, bits for status, status2 and timecode are different
*/
/* status */
#define HDSPM_AES32_wcLock 0x0200000
#define HDSPM_AES32_wcSync 0x0100000
#define HDSPM_AES32_wcFreq_bit 22
/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
HDSPM_bit2freq */
#define HDSPM_AES32_syncref_bit 16
/* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
#define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
#define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
#define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
#define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
#define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
#define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
#define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
#define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
#define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
#define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
/* status2 */
/* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
#define HDSPM_LockAES 0x80
#define HDSPM_LockAES1 0x80
#define HDSPM_LockAES2 0x40
#define HDSPM_LockAES3 0x20
#define HDSPM_LockAES4 0x10
#define HDSPM_LockAES5 0x8
#define HDSPM_LockAES6 0x4
#define HDSPM_LockAES7 0x2
#define HDSPM_LockAES8 0x1
/*
Timecode
After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
AES i+1
bits 3210
0001 32kHz
0010 44.1kHz
0011 48kHz
0100 64kHz
0101 88.2kHz
0110 96kHz
0111 128kHz
1000 176.4kHz
1001 192kHz
NB: Timecode register doesn't seem to work on AES32 card revision 230
*/
/* Mixer Values */
#define UNITY_GAIN 32768 /* = 65536/2 */
#define MINUS_INFINITY_GAIN 0
/* Number of channels for different Speed Modes */
#define MADI_SS_CHANNELS 64
#define MADI_DS_CHANNELS 32
#define MADI_QS_CHANNELS 16
#define RAYDAT_SS_CHANNELS 36
#define RAYDAT_DS_CHANNELS 20
#define RAYDAT_QS_CHANNELS 12
#define AIO_IN_SS_CHANNELS 14
#define AIO_IN_DS_CHANNELS 10
#define AIO_IN_QS_CHANNELS 8
#define AIO_OUT_SS_CHANNELS 16
#define AIO_OUT_DS_CHANNELS 12
#define AIO_OUT_QS_CHANNELS 10
#define AES32_CHANNELS 16
/* the size of a substream (1 mono data stream) */
#define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
#define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
/* the size of the area we need to allocate for DMA transfers. the
size is the same regardless of the number of channels, and
also the latency to use.
for one direction !!!
*/
#define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
#define HDSPM_RAYDAT_REV 211
#define HDSPM_AIO_REV 212
#define HDSPM_MADIFACE_REV 213
/* speed factor modes */
#define HDSPM_SPEED_SINGLE 0
#define HDSPM_SPEED_DOUBLE 1
#define HDSPM_SPEED_QUAD 2
/* names for speed modes */
static char *hdspm_speed_names[] = { "single", "double", "quad" };
static char *texts_autosync_aes_tco[] = { "Word Clock",
"AES1", "AES2", "AES3", "AES4",
"AES5", "AES6", "AES7", "AES8",
"TCO" };
static char *texts_autosync_aes[] = { "Word Clock",
"AES1", "AES2", "AES3", "AES4",
"AES5", "AES6", "AES7", "AES8" };
static char *texts_autosync_madi_tco[] = { "Word Clock",
"MADI", "TCO", "Sync In" };
static char *texts_autosync_madi[] = { "Word Clock",
"MADI", "Sync In" };
static char *texts_autosync_raydat_tco[] = {
"Word Clock",
"ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
"AES", "SPDIF", "TCO", "Sync In"
};
static char *texts_autosync_raydat[] = {
"Word Clock",
"ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
"AES", "SPDIF", "Sync In"
};
static char *texts_autosync_aio_tco[] = {
"Word Clock",
"ADAT", "AES", "SPDIF", "TCO", "Sync In"
};
static char *texts_autosync_aio[] = { "Word Clock",
"ADAT", "AES", "SPDIF", "Sync In" };
static char *texts_freq[] = {
"No Lock",
"32 kHz",
"44.1 kHz",
"48 kHz",
"64 kHz",
"88.2 kHz",
"96 kHz",
"128 kHz",
"176.4 kHz",
"192 kHz"
};
static char *texts_ports_madi[] = {
"MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
"MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
"MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
"MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
"MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
"MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
"MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
"MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
"MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
"MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
"MADI.61", "MADI.62", "MADI.63", "MADI.64",
};
static char *texts_ports_raydat_ss[] = {
"ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
"ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
"ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
"ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
"ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
"ADAT4.7", "ADAT4.8",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R"
};
static char *texts_ports_raydat_ds[] = {
"ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
"ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
"ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
"ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R"
};
static char *texts_ports_raydat_qs[] = {
"ADAT1.1", "ADAT1.2",
"ADAT2.1", "ADAT2.2",
"ADAT3.1", "ADAT3.2",
"ADAT4.1", "ADAT4.2",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R"
};
static char *texts_ports_aio_in_ss[] = {
"Analogue.L", "Analogue.R",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R",
"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
"ADAT.7", "ADAT.8"
};
static char *texts_ports_aio_out_ss[] = {
"Analogue.L", "Analogue.R",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R",
"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
"ADAT.7", "ADAT.8",
"Phone.L", "Phone.R"
};
static char *texts_ports_aio_in_ds[] = {
"Analogue.L", "Analogue.R",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R",
"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
};
static char *texts_ports_aio_out_ds[] = {
"Analogue.L", "Analogue.R",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R",
"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
"Phone.L", "Phone.R"
};
static char *texts_ports_aio_in_qs[] = {
"Analogue.L", "Analogue.R",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R",
"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
};
static char *texts_ports_aio_out_qs[] = {
"Analogue.L", "Analogue.R",
"AES.L", "AES.R",
"SPDIF.L", "SPDIF.R",
"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
"Phone.L", "Phone.R"
};
static char *texts_ports_aes32[] = {
"AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
"AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
"AES.15", "AES.16"
};
/* These tables map the ALSA channels 1..N to the channels that we
need to use in order to find the relevant channel buffer. RME
refers to this kind of mapping as between "the ADAT channel and
the DMA channel." We index it using the logical audio channel,
and the value is the DMA channel (i.e. channel buffer number)
where the data for that channel can be read/written from/to.
*/
static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37, 38, 39,
40, 41, 42, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63
};
static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
0, 1, /* AES */
2, 3, /* SPDIF */
-1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
};
static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
4, 5, 6, 7, /* ADAT 1 */
8, 9, 10, 11, /* ADAT 2 */
12, 13, 14, 15, /* ADAT 3 */
16, 17, 18, 19, /* ADAT 4 */
0, 1, /* AES */
2, 3, /* SPDIF */
-1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
};
static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
4, 5, /* ADAT 1 */
6, 7, /* ADAT 2 */
8, 9, /* ADAT 3 */
10, 11, /* ADAT 4 */
0, 1, /* AES */
2, 3, /* SPDIF */
-1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
};
static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
0, 1, /* line in */
8, 9, /* aes in, */
10, 11, /* spdif in */
12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
-1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
};
static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
0, 1, /* line out */
8, 9, /* aes out */
10, 11, /* spdif out */
12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
6, 7, /* phone out */
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
};
static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
0, 1, /* line in */
8, 9, /* aes in */
10, 11, /* spdif in */
12, 14, 16, 18, /* adat in */
-1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1
};
static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
0, 1, /* line out */
8, 9, /* aes out */
10, 11, /* spdif out */
12, 14, 16, 18, /* adat out */
6, 7, /* phone out */
-1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1
};
static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
0, 1, /* line in */
8, 9, /* aes in */
10, 11, /* spdif in */
12, 16, /* adat in */
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1
};
static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
0, 1, /* line out */
8, 9, /* aes out */
10, 11, /* spdif out */
12, 16, /* adat out */
6, 7, /* phone out */
-1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1
};
static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1
};
struct hdspm_midi {
struct hdspm *hdspm;
int id;
struct snd_rawmidi *rmidi;
struct snd_rawmidi_substream *input;
struct snd_rawmidi_substream *output;
char istimer; /* timer in use */
struct timer_list timer;
spinlock_t lock;
int pending;
int dataIn;
int statusIn;
int dataOut;
int statusOut;
int ie;
int irq;
};
struct hdspm_tco {
int input;
int framerate;
int wordclock;
int samplerate;
int pull;
int term; /* 0 = off, 1 = on */
};
struct hdspm {
spinlock_t lock;
/* only one playback and/or capture stream */
struct snd_pcm_substream *capture_substream;
struct snd_pcm_substream *playback_substream;
char *card_name; /* for procinfo */
unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
uint8_t io_type;
int monitor_outs; /* set up monitoring outs init flag */
u32 control_register; /* cached value */
u32 control2_register; /* cached value */
u32 settings_register;
struct hdspm_midi midi[4];
struct tasklet_struct midi_tasklet;
size_t period_bytes;
unsigned char ss_in_channels;
unsigned char ds_in_channels;
unsigned char qs_in_channels;
unsigned char ss_out_channels;
unsigned char ds_out_channels;
unsigned char qs_out_channels;
unsigned char max_channels_in;
unsigned char max_channels_out;
signed char *channel_map_in;
signed char *channel_map_out;
signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
char **port_names_in;
char **port_names_out;
char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
unsigned char *playback_buffer; /* suitably aligned address */
unsigned char *capture_buffer; /* suitably aligned address */
pid_t capture_pid; /* process id which uses capture */
pid_t playback_pid; /* process id which uses capture */
int running; /* running status */
int last_external_sample_rate; /* samplerate mystic ... */
int last_internal_sample_rate;
int system_sample_rate;
int dev; /* Hardware vars... */
int irq;
unsigned long port;
void __iomem *iobase;
int irq_count; /* for debug */
int midiPorts;
struct snd_card *card; /* one card */
struct snd_pcm *pcm; /* has one pcm */
struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
struct pci_dev *pci; /* and an pci info */
/* Mixer vars */
/* fast alsa mixer */
struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
/* but input to much, so not used */
struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
/* full mixer accessible over mixer ioctl or hwdep-device */
struct hdspm_mixer *mixer;
struct hdspm_tco *tco; /* NULL if no TCO detected */
char **texts_autosync;
int texts_autosync_items;
cycles_t last_interrupt;
unsigned int serial;
struct hdspm_peak_rms peak_rms;
};
static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
{
.vendor = PCI_VENDOR_ID_XILINX,
.device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.class = 0,
.class_mask = 0,
.driver_data = 0},
{0,}
};
MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
/* prototypes */
static int snd_hdspm_create_alsa_devices(struct snd_card *card,
struct hdspm *hdspm);
static int snd_hdspm_create_pcm(struct snd_card *card,
struct hdspm *hdspm);
static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
static int hdspm_autosync_ref(struct hdspm *hdspm);
static int snd_hdspm_set_defaults(struct hdspm *hdspm);
static int hdspm_system_clock_mode(struct hdspm *hdspm);
static void hdspm_set_sgbuf(struct hdspm *hdspm,
struct snd_pcm_substream *substream,
unsigned int reg, int channels);
static inline int HDSPM_bit2freq(int n)
{
static const int bit2freq_tab[] = {
0, 32000, 44100, 48000, 64000, 88200,
96000, 128000, 176400, 192000 };
if (n < 1 || n > 9)
return 0;
return bit2freq_tab[n];
}
/* Write/read to/from HDSPM with Adresses in Bytes
not words but only 32Bit writes are allowed */
static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
unsigned int val)
{
writel(val, hdspm->iobase + reg);
}
static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
{
return readl(hdspm->iobase + reg);
}
/* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
mixer is write only on hardware so we have to cache him for read
each fader is a u32, but uses only the first 16 bit */
static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
unsigned int in)
{
if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
return 0;
return hdspm->mixer->ch[chan].in[in];
}
static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
unsigned int pb)
{
if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
return 0;
return hdspm->mixer->ch[chan].pb[pb];
}
static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
unsigned int in, unsigned short data)
{
if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
return -1;
hdspm_write(hdspm,
HDSPM_MADI_mixerBase +
((in + 128 * chan) * sizeof(u32)),
(hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
return 0;
}
static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
unsigned int pb, unsigned short data)
{
if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
return -1;
hdspm_write(hdspm,
HDSPM_MADI_mixerBase +
((64 + pb + 128 * chan) * sizeof(u32)),
(hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
return 0;
}
/* enable DMA for specific channels, now available for DSP-MADI */
static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
{
hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
}
static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
{
hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
}
/* check if same process is writing and reading */
static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
{
unsigned long flags;
int ret = 1;
spin_lock_irqsave(&hdspm->lock, flags);
if ((hdspm->playback_pid != hdspm->capture_pid) &&
(hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
ret = 0;
}
spin_unlock_irqrestore(&hdspm->lock, flags);
return ret;
}
/* round arbitary sample rates to commonly known rates */
static int hdspm_round_frequency(int rate)
{
if (rate < 38050)
return 32000;
if (rate < 46008)
return 44100;
else
return 48000;
}
static int hdspm_tco_sync_check(struct hdspm *hdspm);
static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
/* check for external sample rate */
static int hdspm_external_sample_rate(struct hdspm *hdspm)
{
unsigned int status, status2, timecode;
int syncref, rate = 0, rate_bits;
switch (hdspm->io_type) {
case AES32:
status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
status = hdspm_read(hdspm, HDSPM_statusRegister);
timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
syncref = hdspm_autosync_ref(hdspm);
if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
status & HDSPM_AES32_wcLock)
return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
status2 & (HDSPM_LockAES >>
(syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
return 0;
break;
case MADIface:
status = hdspm_read(hdspm, HDSPM_statusRegister);
if (!(status & HDSPM_madiLock)) {
rate = 0; /* no lock */
} else {
switch (status & (HDSPM_status1_freqMask)) {
case HDSPM_status1_F_0*1:
rate = 32000; break;
case HDSPM_status1_F_0*2:
rate = 44100; break;
case HDSPM_status1_F_0*3:
rate = 48000; break;
case HDSPM_status1_F_0*4:
rate = 64000; break;
case HDSPM_status1_F_0*5:
rate = 88200; break;
case HDSPM_status1_F_0*6:
rate = 96000; break;
case HDSPM_status1_F_0*7:
rate = 128000; break;
case HDSPM_status1_F_0*8:
rate = 176400; break;
case HDSPM_status1_F_0*9:
rate = 192000; break;
default:
rate = 0; break;
}
}
break;
case MADI:
case AIO:
case RayDAT:
status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
status = hdspm_read(hdspm, HDSPM_statusRegister);
rate = 0;
/* if wordclock has synced freq and wordclock is valid */
if ((status2 & HDSPM_wcLock) != 0 &&
(status2 & HDSPM_SelSyncRef0) == 0) {
rate_bits = status2 & HDSPM_wcFreqMask;
switch (rate_bits) {
case HDSPM_wcFreq32:
rate = 32000;
break;
case HDSPM_wcFreq44_1:
rate = 44100;
break;
case HDSPM_wcFreq48:
rate = 48000;
break;
case HDSPM_wcFreq64:
rate = 64000;
break;
case HDSPM_wcFreq88_2:
rate = 88200;
break;
case HDSPM_wcFreq96:
rate = 96000;
break;
default:
rate = 0;
break;
}
}
/* if rate detected and Syncref is Word than have it,
* word has priority to MADI
*/
if (rate != 0 &&
(status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
return rate;
/* maybe a madi input (which is taken if sel sync is madi) */
if (status & HDSPM_madiLock) {
rate_bits = status & HDSPM_madiFreqMask;
switch (rate_bits) {
case HDSPM_madiFreq32:
rate = 32000;
break;
case HDSPM_madiFreq44_1:
rate = 44100;
break;
case HDSPM_madiFreq48:
rate = 48000;
break;
case HDSPM_madiFreq64:
rate = 64000;
break;
case HDSPM_madiFreq88_2:
rate = 88200;
break;
case HDSPM_madiFreq96:
rate = 96000;
break;
case HDSPM_madiFreq128:
rate = 128000;
break;
case HDSPM_madiFreq176_4:
rate = 176400;
break;
case HDSPM_madiFreq192:
rate = 192000;
break;
default:
rate = 0;
break;
}
} /* endif HDSPM_madiLock */
/* check sample rate from TCO or SYNC_IN */
{
bool is_valid_input = 0;
bool has_sync = 0;
syncref = hdspm_autosync_ref(hdspm);
if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
is_valid_input = 1;
has_sync = (HDSPM_SYNC_CHECK_SYNC ==
hdspm_tco_sync_check(hdspm));
} else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
is_valid_input = 1;
has_sync = (HDSPM_SYNC_CHECK_SYNC ==
hdspm_sync_in_sync_check(hdspm));
}
if (is_valid_input && has_sync) {
rate = hdspm_round_frequency(
hdspm_get_pll_freq(hdspm));
}
}
/* QS and DS rates normally can not be detected
* automatically by the card. Only exception is MADI
* in 96k frame mode.
*
* So if we read SS values (32 .. 48k), check for
* user-provided DS/QS bits in the control register
* and multiply the base frequency accordingly.
*/
if (rate <= 48000) {
if (hdspm->control_register & HDSPM_QuadSpeed)
rate *= 4;
else if (hdspm->control_register &
HDSPM_DoubleSpeed)
rate *= 2;
}
break;
}
return rate;
}
/* return latency in samples per period */
static int hdspm_get_latency(struct hdspm *hdspm)
{
int n;
n = hdspm_decode_latency(hdspm->control_register);
/* Special case for new RME cards with 32 samples period size.
* The three latency bits in the control register
* (HDSP_LatencyMask) encode latency values of 64 samples as
* 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
* denotes 8192 samples, but on new cards like RayDAT or AIO,
* it corresponds to 32 samples.
*/
if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
n = -1;
return 1 << (n + 6);
}
/* Latency function */
static inline void hdspm_compute_period_size(struct hdspm *hdspm)
{
hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
}
static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
{
int position;
position = hdspm_read(hdspm, HDSPM_statusRegister);
switch (hdspm->io_type) {
case RayDAT:
case AIO:
position &= HDSPM_BufferPositionMask;
position /= 4; /* Bytes per sample */
break;
default:
position = (position & HDSPM_BufferID) ?
(hdspm->period_bytes / 4) : 0;
}
return position;
}
static inline void hdspm_start_audio(struct hdspm * s)
{
s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
hdspm_write(s, HDSPM_controlRegister, s->control_register);
}
static inline void hdspm_stop_audio(struct hdspm * s)
{
s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
hdspm_write(s, HDSPM_controlRegister, s->control_register);
}
/* should I silence all or only opened ones ? doit all for first even is 4MB*/
static void hdspm_silence_playback(struct hdspm *hdspm)
{
int i;
int n = hdspm->period_bytes;
void *buf = hdspm->playback_buffer;
if (buf == NULL)
return;
for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
memset(buf, 0, n);
buf += HDSPM_CHANNEL_BUFFER_BYTES;
}
}
static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
{
int n;
spin_lock_irq(&s->lock);
if (32 == frames) {
/* Special case for new RME cards like RayDAT/AIO which
* support period sizes of 32 samples. Since latency is
* encoded in the three bits of HDSP_LatencyMask, we can only
* have values from 0 .. 7. While 0 still means 64 samples and
* 6 represents 4096 samples on all cards, 7 represents 8192
* on older cards and 32 samples on new cards.
*
* In other words, period size in samples is calculated by
* 2^(n+6) with n ranging from 0 .. 7.
*/
n = 7;
} else {
frames >>= 7;
n = 0;
while (frames) {
n++;
frames >>= 1;
}
}
s->control_register &= ~HDSPM_LatencyMask;
s->control_register |= hdspm_encode_latency(n);
hdspm_write(s, HDSPM_controlRegister, s->control_register);
hdspm_compute_period_size(s);
spin_unlock_irq(&s->lock);
return 0;
}
static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
{
u64 freq_const;
if (period == 0)
return 0;
switch (hdspm->io_type) {
case MADI:
case AES32:
freq_const = 110069313433624ULL;
break;
case RayDAT:
case AIO:
freq_const = 104857600000000ULL;
break;
case MADIface:
freq_const = 131072000000000ULL;
break;
default:
snd_BUG();
return 0;
}
return div_u64(freq_const, period);
}
static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
{
u64 n;
if (rate >= 112000)
rate /= 4;
else if (rate >= 56000)
rate /= 2;
switch (hdspm->io_type) {
case MADIface:
n = 131072000000000ULL; /* 125 MHz */
break;
case MADI:
case AES32:
n = 110069313433624ULL; /* 105 MHz */
break;
case RayDAT:
case AIO:
n = 104857600000000ULL; /* 100 MHz */
break;
default:
snd_BUG();
return;
}
n = div_u64(n, rate);
/* n should be less than 2^32 for being written to FREQ register */
snd_BUG_ON(n >> 32);
hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
}
/* dummy set rate lets see what happens */
static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
{
int current_rate;
int rate_bits;
int not_set = 0;
int current_speed, target_speed;
/* ASSUMPTION: hdspm->lock is either set, or there is no need for
it (e.g. during module initialization).
*/
if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
/* SLAVE --- */
if (called_internally) {
/* request from ctl or card initialization
just make a warning an remember setting
for future master mode switching */
snd_printk(KERN_WARNING "HDSPM: "
"Warning: device is not running "
"as a clock master.\n");
not_set = 1;
} else {
/* hw_param request while in AutoSync mode */
int external_freq =
hdspm_external_sample_rate(hdspm);
if (hdspm_autosync_ref(hdspm) ==
HDSPM_AUTOSYNC_FROM_NONE) {
snd_printk(KERN_WARNING "HDSPM: "
"Detected no Externel Sync \n");
not_set = 1;
} else if (rate != external_freq) {
snd_printk(KERN_WARNING "HDSPM: "
"Warning: No AutoSync source for "
"requested rate\n");
not_set = 1;
}
}
}
current_rate = hdspm->system_sample_rate;
/* Changing between Singe, Double and Quad speed is not
allowed if any substreams are open. This is because such a change
causes a shift in the location of the DMA buffers and a reduction
in the number of available buffers.
Note that a similar but essentially insoluble problem exists for
externally-driven rate changes. All we can do is to flag rate
changes in the read/write routines.
*/
if (current_rate <= 48000)
current_speed = HDSPM_SPEED_SINGLE;
else if (current_rate <= 96000)
current_speed = HDSPM_SPEED_DOUBLE;
else
current_speed = HDSPM_SPEED_QUAD;
if (rate <= 48000)
target_speed = HDSPM_SPEED_SINGLE;
else if (rate <= 96000)
target_speed = HDSPM_SPEED_DOUBLE;
else
target_speed = HDSPM_SPEED_QUAD;
switch (rate) {
case 32000:
rate_bits = HDSPM_Frequency32KHz;
break;
case 44100:
rate_bits = HDSPM_Frequency44_1KHz;
break;
case 48000:
rate_bits = HDSPM_Frequency48KHz;
break;
case 64000:
rate_bits = HDSPM_Frequency64KHz;
break;
case 88200:
rate_bits = HDSPM_Frequency88_2KHz;
break;
case 96000:
rate_bits = HDSPM_Frequency96KHz;
break;
case 128000:
rate_bits = HDSPM_Frequency128KHz;
break;
case 176400:
rate_bits = HDSPM_Frequency176_4KHz;
break;
case 192000:
rate_bits = HDSPM_Frequency192KHz;
break;
default:
return -EINVAL;
}
if (current_speed != target_speed
&& (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
snd_printk
(KERN_ERR "HDSPM: "
"cannot change from %s speed to %s speed mode "
"(capture PID = %d, playback PID = %d)\n",
hdspm_speed_names[current_speed],
hdspm_speed_names[target_speed],
hdspm->capture_pid, hdspm->playback_pid);
return -EBUSY;
}
hdspm->control_register &= ~HDSPM_FrequencyMask;
hdspm->control_register |= rate_bits;
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
/* For AES32, need to set DDS value in FREQ register
For MADI, also apparently */
hdspm_set_dds_value(hdspm, rate);
if (AES32 == hdspm->io_type && rate != current_rate)
hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
hdspm->system_sample_rate = rate;
if (rate <= 48000) {
hdspm->channel_map_in = hdspm->channel_map_in_ss;
hdspm->channel_map_out = hdspm->channel_map_out_ss;
hdspm->max_channels_in = hdspm->ss_in_channels;
hdspm->max_channels_out = hdspm->ss_out_channels;
hdspm->port_names_in = hdspm->port_names_in_ss;
hdspm->port_names_out = hdspm->port_names_out_ss;
} else if (rate <= 96000) {
hdspm->channel_map_in = hdspm->channel_map_in_ds;
hdspm->channel_map_out = hdspm->channel_map_out_ds;
hdspm->max_channels_in = hdspm->ds_in_channels;
hdspm->max_channels_out = hdspm->ds_out_channels;
hdspm->port_names_in = hdspm->port_names_in_ds;
hdspm->port_names_out = hdspm->port_names_out_ds;
} else {
hdspm->channel_map_in = hdspm->channel_map_in_qs;
hdspm->channel_map_out = hdspm->channel_map_out_qs;
hdspm->max_channels_in = hdspm->qs_in_channels;
hdspm->max_channels_out = hdspm->qs_out_channels;
hdspm->port_names_in = hdspm->port_names_in_qs;
hdspm->port_names_out = hdspm->port_names_out_qs;
}
if (not_set != 0)
return -1;
return 0;
}
/* mainly for init to 0 on load */
static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
{
int i, j;
unsigned int gain;
if (sgain > UNITY_GAIN)
gain = UNITY_GAIN;
else if (sgain < 0)
gain = 0;
else
gain = sgain;
for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
hdspm_write_in_gain(hdspm, i, j, gain);
hdspm_write_pb_gain(hdspm, i, j, gain);
}
}
/*----------------------------------------------------------------------------
MIDI
----------------------------------------------------------------------------*/
static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
int id)
{
/* the hardware already does the relevant bit-mask with 0xff */
return hdspm_read(hdspm, hdspm->midi[id].dataIn);
}
static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
int val)
{
/* the hardware already does the relevant bit-mask with 0xff */
return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
}
static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
{
return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
}
static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
{
int fifo_bytes_used;
fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
if (fifo_bytes_used < 128)
return 128 - fifo_bytes_used;
else
return 0;
}
static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
{
while (snd_hdspm_midi_input_available (hdspm, id))
snd_hdspm_midi_read_byte (hdspm, id);
}
static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
{
unsigned long flags;
int n_pending;
int to_write;
int i;
unsigned char buf[128];
/* Output is not interrupt driven */
spin_lock_irqsave (&hmidi->lock, flags);
if (hmidi->output &&
!snd_rawmidi_transmit_empty (hmidi->output)) {
n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
hmidi->id);
if (n_pending > 0) {
if (n_pending > (int)sizeof (buf))
n_pending = sizeof (buf);
to_write = snd_rawmidi_transmit (hmidi->output, buf,
n_pending);
if (to_write > 0) {
for (i = 0; i < to_write; ++i)
snd_hdspm_midi_write_byte (hmidi->hdspm,
hmidi->id,
buf[i]);
}
}
}
spin_unlock_irqrestore (&hmidi->lock, flags);
return 0;
}
static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
{
unsigned char buf[128]; /* this buffer is designed to match the MIDI
* input FIFO size
*/
unsigned long flags;
int n_pending;
int i;
spin_lock_irqsave (&hmidi->lock, flags);
n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
if (n_pending > 0) {
if (hmidi->input) {
if (n_pending > (int)sizeof (buf))
n_pending = sizeof (buf);
for (i = 0; i < n_pending; ++i)
buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
hmidi->id);
if (n_pending)
snd_rawmidi_receive (hmidi->input, buf,
n_pending);
} else {
/* flush the MIDI input FIFO */
while (n_pending--)
snd_hdspm_midi_read_byte (hmidi->hdspm,
hmidi->id);
}
}
hmidi->pending = 0;
spin_unlock_irqrestore(&hmidi->lock, flags);
spin_lock_irqsave(&hmidi->hdspm->lock, flags);
hmidi->hdspm->control_register |= hmidi->ie;
hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
hmidi->hdspm->control_register);
spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
return snd_hdspm_midi_output_write (hmidi);
}
static void
snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
{
struct hdspm *hdspm;
struct hdspm_midi *hmidi;
unsigned long flags;
hmidi = substream->rmidi->private_data;
hdspm = hmidi->hdspm;
spin_lock_irqsave (&hdspm->lock, flags);
if (up) {
if (!(hdspm->control_register & hmidi->ie)) {
snd_hdspm_flush_midi_input (hdspm, hmidi->id);
hdspm->control_register |= hmidi->ie;
}
} else {
hdspm->control_register &= ~hmidi->ie;
}
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
spin_unlock_irqrestore (&hdspm->lock, flags);
}
static void snd_hdspm_midi_output_timer(unsigned long data)
{
struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
unsigned long flags;
snd_hdspm_midi_output_write(hmidi);
spin_lock_irqsave (&hmidi->lock, flags);
/* this does not bump hmidi->istimer, because the
kernel automatically removed the timer when it
expired, and we are now adding it back, thus
leaving istimer wherever it was set before.
*/
if (hmidi->istimer) {
hmidi->timer.expires = 1 + jiffies;
add_timer(&hmidi->timer);
}
spin_unlock_irqrestore (&hmidi->lock, flags);
}
static void
snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
{
struct hdspm_midi *hmidi;
unsigned long flags;
hmidi = substream->rmidi->private_data;
spin_lock_irqsave (&hmidi->lock, flags);
if (up) {
if (!hmidi->istimer) {
init_timer(&hmidi->timer);
hmidi->timer.function = snd_hdspm_midi_output_timer;
hmidi->timer.data = (unsigned long) hmidi;
hmidi->timer.expires = 1 + jiffies;
add_timer(&hmidi->timer);
hmidi->istimer++;
}
} else {
if (hmidi->istimer && --hmidi->istimer <= 0)
del_timer (&hmidi->timer);
}
spin_unlock_irqrestore (&hmidi->lock, flags);
if (up)
snd_hdspm_midi_output_write(hmidi);
}
static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
{
struct hdspm_midi *hmidi;
hmidi = substream->rmidi->private_data;
spin_lock_irq (&hmidi->lock);
snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
hmidi->input = substream;
spin_unlock_irq (&hmidi->lock);
return 0;
}
static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
{
struct hdspm_midi *hmidi;
hmidi = substream->rmidi->private_data;
spin_lock_irq (&hmidi->lock);
hmidi->output = substream;
spin_unlock_irq (&hmidi->lock);
return 0;
}
static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
{
struct hdspm_midi *hmidi;
snd_hdspm_midi_input_trigger (substream, 0);
hmidi = substream->rmidi->private_data;
spin_lock_irq (&hmidi->lock);
hmidi->input = NULL;
spin_unlock_irq (&hmidi->lock);
return 0;
}
static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
{
struct hdspm_midi *hmidi;
snd_hdspm_midi_output_trigger (substream, 0);
hmidi = substream->rmidi->private_data;
spin_lock_irq (&hmidi->lock);
hmidi->output = NULL;
spin_unlock_irq (&hmidi->lock);
return 0;
}
static struct snd_rawmidi_ops snd_hdspm_midi_output =
{
.open = snd_hdspm_midi_output_open,
.close = snd_hdspm_midi_output_close,
.trigger = snd_hdspm_midi_output_trigger,
};
static struct snd_rawmidi_ops snd_hdspm_midi_input =
{
.open = snd_hdspm_midi_input_open,
.close = snd_hdspm_midi_input_close,
.trigger = snd_hdspm_midi_input_trigger,
};
static int snd_hdspm_create_midi(struct snd_card *card,
struct hdspm *hdspm, int id)
{
int err;
char buf[32];
hdspm->midi[id].id = id;
hdspm->midi[id].hdspm = hdspm;
spin_lock_init (&hdspm->midi[id].lock);
if (0 == id) {
if (MADIface == hdspm->io_type) {
/* MIDI-over-MADI on HDSPe MADIface */
hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
hdspm->midi[0].irq = HDSPM_midi2IRQPending;
} else {
hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
hdspm->midi[0].irq = HDSPM_midi0IRQPending;
}
} else if (1 == id) {
hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
hdspm->midi[1].irq = HDSPM_midi1IRQPending;
} else if ((2 == id) && (MADI == hdspm->io_type)) {
/* MIDI-over-MADI on HDSPe MADI */
hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
hdspm->midi[2].irq = HDSPM_midi2IRQPending;
} else if (2 == id) {
/* TCO MTC, read only */
hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
hdspm->midi[2].dataOut = -1;
hdspm->midi[2].statusOut = -1;
hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
} else if (3 == id) {
/* TCO MTC on HDSPe MADI */
hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
hdspm->midi[3].dataOut = -1;
hdspm->midi[3].statusOut = -1;
hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
hdspm->midi[3].irq = HDSPM_midi3IRQPending;
}
if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
(MADIface == hdspm->io_type)))) {
if ((id == 0) && (MADIface == hdspm->io_type)) {
sprintf(buf, "%s MIDIoverMADI", card->shortname);
} else if ((id == 2) && (MADI == hdspm->io_type)) {
sprintf(buf, "%s MIDIoverMADI", card->shortname);
} else {
sprintf(buf, "%s MIDI %d", card->shortname, id+1);
}
err = snd_rawmidi_new(card, buf, id, 1, 1,
&hdspm->midi[id].rmidi);
if (err < 0)
return err;
sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
card->id, id+1);
hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
SNDRV_RAWMIDI_STREAM_OUTPUT,
&snd_hdspm_midi_output);
snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
SNDRV_RAWMIDI_STREAM_INPUT,
&snd_hdspm_midi_input);
hdspm->midi[id].rmidi->info_flags |=
SNDRV_RAWMIDI_INFO_OUTPUT |
SNDRV_RAWMIDI_INFO_INPUT |
SNDRV_RAWMIDI_INFO_DUPLEX;
} else {
/* TCO MTC, read only */
sprintf(buf, "%s MTC %d", card->shortname, id+1);
err = snd_rawmidi_new(card, buf, id, 1, 1,
&hdspm->midi[id].rmidi);
if (err < 0)
return err;
sprintf(hdspm->midi[id].rmidi->name,
"%s MTC %d", card->id, id+1);
hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
SNDRV_RAWMIDI_STREAM_INPUT,
&snd_hdspm_midi_input);
hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
}
return 0;
}
static void hdspm_midi_tasklet(unsigned long arg)
{
struct hdspm *hdspm = (struct hdspm *)arg;
int i = 0;
while (i < hdspm->midiPorts) {
if (hdspm->midi[i].pending)
snd_hdspm_midi_input_read(&hdspm->midi[i]);
i++;
}
}
/*-----------------------------------------------------------------------------
Status Interface
----------------------------------------------------------------------------*/
/* get the system sample rate which is set */
static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
{
unsigned int period, rate;
period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
rate = hdspm_calc_dds_value(hdspm, period);
return rate;
}
/**
* Calculate the real sample rate from the
* current DDS value.
**/
static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
{
unsigned int rate;
rate = hdspm_get_pll_freq(hdspm);
if (rate > 207000) {
/* Unreasonable high sample rate as seen on PCI MADI cards. */
if (0 == hdspm_system_clock_mode(hdspm)) {
/* master mode, return internal sample rate */
rate = hdspm->system_sample_rate;
} else {
/* slave mode, return external sample rate */
rate = hdspm_external_sample_rate(hdspm);
}
}
return rate;
}
#define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_system_sample_rate, \
.put = snd_hdspm_put_system_sample_rate, \
.get = snd_hdspm_get_system_sample_rate \
}
static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 27000;
uinfo->value.integer.max = 207000;
uinfo->value.integer.step = 1;
return 0;
}
static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *
ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
return 0;
}
static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *
ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
return 0;
}
/**
* Returns the WordClock sample rate class for the given card.
**/
static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
{
int status;
switch (hdspm->io_type) {
case RayDAT:
case AIO:
status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
return (status >> 16) & 0xF;
break;
default:
break;
}
return 0;
}
/**
* Returns the TCO sample rate class for the given card.
**/
static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
{
int status;
if (hdspm->tco) {
switch (hdspm->io_type) {
case RayDAT:
case AIO:
status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
return (status >> 20) & 0xF;
break;
default:
break;
}
}
return 0;
}
/**
* Returns the SYNC_IN sample rate class for the given card.
**/
static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
{
int status;
if (hdspm->tco) {
switch (hdspm->io_type) {
case RayDAT:
case AIO:
status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
return (status >> 12) & 0xF;
break;
default:
break;
}
}
return 0;
}
/**
* Returns the sample rate class for input source <idx> for
* 'new style' cards like the AIO and RayDAT.
**/
static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
{
int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
return (status >> (idx*4)) & 0xF;
}
#define ENUMERATED_CTL_INFO(info, texts) \
{ \
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \
uinfo->count = 1; \
uinfo->value.enumerated.items = ARRAY_SIZE(texts); \
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \
uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; \
strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \
}
#define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.private_value = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
.info = snd_hdspm_info_autosync_sample_rate, \
.get = snd_hdspm_get_autosync_sample_rate \
}
static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
ENUMERATED_CTL_INFO(uinfo, texts_freq);
return 0;
}
static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *
ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
switch (hdspm->io_type) {
case RayDAT:
switch (kcontrol->private_value) {
case 0:
ucontrol->value.enumerated.item[0] =
hdspm_get_wc_sample_rate(hdspm);
break;
case 7:
ucontrol->value.enumerated.item[0] =
hdspm_get_tco_sample_rate(hdspm);
break;
case 8:
ucontrol->value.enumerated.item[0] =
hdspm_get_sync_in_sample_rate(hdspm);
break;
default:
ucontrol->value.enumerated.item[0] =
hdspm_get_s1_sample_rate(hdspm,
kcontrol->private_value-1);
}
break;
case AIO:
switch (kcontrol->private_value) {
case 0: /* WC */
ucontrol->value.enumerated.item[0] =
hdspm_get_wc_sample_rate(hdspm);
break;
case 4: /* TCO */
ucontrol->value.enumerated.item[0] =
hdspm_get_tco_sample_rate(hdspm);
break;
case 5: /* SYNC_IN */
ucontrol->value.enumerated.item[0] =
hdspm_get_sync_in_sample_rate(hdspm);
break;
default:
ucontrol->value.enumerated.item[0] =
hdspm_get_s1_sample_rate(hdspm,
ucontrol->id.index-1);
}
break;
case AES32:
switch (kcontrol->private_value) {
case 0: /* WC */
ucontrol->value.enumerated.item[0] =
hdspm_get_wc_sample_rate(hdspm);
break;
case 9: /* TCO */
ucontrol->value.enumerated.item[0] =
hdspm_get_tco_sample_rate(hdspm);
break;
case 10: /* SYNC_IN */
ucontrol->value.enumerated.item[0] =
hdspm_get_sync_in_sample_rate(hdspm);
break;
default: /* AES1 to AES8 */
ucontrol->value.enumerated.item[0] =
hdspm_get_s1_sample_rate(hdspm,
kcontrol->private_value-1);
break;
}
break;
case MADI:
case MADIface:
{
int rate = hdspm_external_sample_rate(hdspm);
int i, selected_rate = 0;
for (i = 1; i < 10; i++)
if (HDSPM_bit2freq(i) == rate) {
selected_rate = i;
break;
}
ucontrol->value.enumerated.item[0] = selected_rate;
}
break;
default:
break;
}
return 0;
}
#define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_system_clock_mode, \
.get = snd_hdspm_get_system_clock_mode, \
.put = snd_hdspm_put_system_clock_mode, \
}
/**
* Returns the system clock mode for the given card.
* @returns 0 - master, 1 - slave
**/
static int hdspm_system_clock_mode(struct hdspm *hdspm)
{
switch (hdspm->io_type) {
case AIO:
case RayDAT:
if (hdspm->settings_register & HDSPM_c0Master)
return 0;
break;
default:
if (hdspm->control_register & HDSPM_ClockModeMaster)
return 0;
}
return 1;
}
/**
* Sets the system clock mode.
* @param mode 0 - master, 1 - slave
**/
static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
{
switch (hdspm->io_type) {
case AIO:
case RayDAT:
if (0 == mode)
hdspm->settings_register |= HDSPM_c0Master;
else
hdspm->settings_register &= ~HDSPM_c0Master;
hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
break;
default:
if (0 == mode)
hdspm->control_register |= HDSPM_ClockModeMaster;
else
hdspm->control_register &= ~HDSPM_ClockModeMaster;
hdspm_write(hdspm, HDSPM_controlRegister,
hdspm->control_register);
}
}
static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "Master", "AutoSync" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
return 0;
}
static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.enumerated.item[0];
if (val < 0)
val = 0;
else if (val > 1)
val = 1;
hdspm_set_system_clock_mode(hdspm, val);
return 0;
}
#define HDSPM_INTERNAL_CLOCK(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.info = snd_hdspm_info_clock_source, \
.get = snd_hdspm_get_clock_source, \
.put = snd_hdspm_put_clock_source \
}
static int hdspm_clock_source(struct hdspm * hdspm)
{
switch (hdspm->system_sample_rate) {
case 32000: return 0;
case 44100: return 1;
case 48000: return 2;
case 64000: return 3;
case 88200: return 4;
case 96000: return 5;
case 128000: return 6;
case 176400: return 7;
case 192000: return 8;
}
return -1;
}
static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
{
int rate;
switch (mode) {
case 0:
rate = 32000; break;
case 1:
rate = 44100; break;
case 2:
rate = 48000; break;
case 3:
rate = 64000; break;
case 4:
rate = 88200; break;
case 5:
rate = 96000; break;
case 6:
rate = 128000; break;
case 7:
rate = 176400; break;
case 8:
rate = 192000; break;
default:
rate = 48000;
}
hdspm_set_rate(hdspm, rate, 1);
return 0;
}
static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 9;
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
uinfo->value.enumerated.item =
uinfo->value.enumerated.items - 1;
strcpy(uinfo->value.enumerated.name,
texts_freq[uinfo->value.enumerated.item+1]);
return 0;
}
static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
return 0;
}
static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.enumerated.item[0];
if (val < 0)
val = 0;
if (val > 9)
val = 9;
spin_lock_irq(&hdspm->lock);
if (val != hdspm_clock_source(hdspm))
change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
else
change = 0;
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_PREF_SYNC_REF(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_pref_sync_ref, \
.get = snd_hdspm_get_pref_sync_ref, \
.put = snd_hdspm_put_pref_sync_ref \
}
/**
* Returns the current preferred sync reference setting.
* The semantics of the return value are depending on the
* card, please see the comments for clarification.
**/
static int hdspm_pref_sync_ref(struct hdspm * hdspm)
{
switch (hdspm->io_type) {
case AES32:
switch (hdspm->control_register & HDSPM_SyncRefMask) {
case 0: return 0; /* WC */
case HDSPM_SyncRef0: return 1; /* AES 1 */
case HDSPM_SyncRef1: return 2; /* AES 2 */
case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
case HDSPM_SyncRef2: return 4; /* AES 4 */
case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
return 7; /* AES 7 */
case HDSPM_SyncRef3: return 8; /* AES 8 */
case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
}
break;
case MADI:
case MADIface:
if (hdspm->tco) {
switch (hdspm->control_register & HDSPM_SyncRefMask) {
case 0: return 0; /* WC */
case HDSPM_SyncRef0: return 1; /* MADI */
case HDSPM_SyncRef1: return 2; /* TCO */
case HDSPM_SyncRef1+HDSPM_SyncRef0:
return 3; /* SYNC_IN */
}
} else {
switch (hdspm->control_register & HDSPM_SyncRefMask) {
case 0: return 0; /* WC */
case HDSPM_SyncRef0: return 1; /* MADI */
case HDSPM_SyncRef1+HDSPM_SyncRef0:
return 2; /* SYNC_IN */
}
}
break;
case RayDAT:
if (hdspm->tco) {
switch ((hdspm->settings_register &
HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
case 0: return 0; /* WC */
case 3: return 1; /* ADAT 1 */
case 4: return 2; /* ADAT 2 */
case 5: return 3; /* ADAT 3 */
case 6: return 4; /* ADAT 4 */
case 1: return 5; /* AES */
case 2: return 6; /* SPDIF */
case 9: return 7; /* TCO */
case 10: return 8; /* SYNC_IN */
}
} else {
switch ((hdspm->settings_register &
HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
case 0: return 0; /* WC */
case 3: return 1; /* ADAT 1 */
case 4: return 2; /* ADAT 2 */
case 5: return 3; /* ADAT 3 */
case 6: return 4; /* ADAT 4 */
case 1: return 5; /* AES */
case 2: return 6; /* SPDIF */
case 10: return 7; /* SYNC_IN */
}
}
break;
case AIO:
if (hdspm->tco) {
switch ((hdspm->settings_register &
HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
case 0: return 0; /* WC */
case 3: return 1; /* ADAT */
case 1: return 2; /* AES */
case 2: return 3; /* SPDIF */
case 9: return 4; /* TCO */
case 10: return 5; /* SYNC_IN */
}
} else {
switch ((hdspm->settings_register &
HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
case 0: return 0; /* WC */
case 3: return 1; /* ADAT */
case 1: return 2; /* AES */
case 2: return 3; /* SPDIF */
case 10: return 4; /* SYNC_IN */
}
}
break;
}
return -1;
}
/**
* Set the preferred sync reference to <pref>. The semantics
* of <pref> are depending on the card type, see the comments
* for clarification.
**/
static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
{
int p = 0;
switch (hdspm->io_type) {
case AES32:
hdspm->control_register &= ~HDSPM_SyncRefMask;
switch (pref) {
case 0: /* WC */
break;
case 1: /* AES 1 */
hdspm->control_register |= HDSPM_SyncRef0;
break;
case 2: /* AES 2 */
hdspm->control_register |= HDSPM_SyncRef1;
break;
case 3: /* AES 3 */
hdspm->control_register |=
HDSPM_SyncRef1+HDSPM_SyncRef0;
break;
case 4: /* AES 4 */
hdspm->control_register |= HDSPM_SyncRef2;
break;
case 5: /* AES 5 */
hdspm->control_register |=
HDSPM_SyncRef2+HDSPM_SyncRef0;
break;
case 6: /* AES 6 */
hdspm->control_register |=
HDSPM_SyncRef2+HDSPM_SyncRef1;
break;
case 7: /* AES 7 */
hdspm->control_register |=
HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
break;
case 8: /* AES 8 */
hdspm->control_register |= HDSPM_SyncRef3;
break;
case 9: /* TCO */
hdspm->control_register |=
HDSPM_SyncRef3+HDSPM_SyncRef0;
break;
default:
return -1;
}
break;
case MADI:
case MADIface:
hdspm->control_register &= ~HDSPM_SyncRefMask;
if (hdspm->tco) {
switch (pref) {
case 0: /* WC */
break;
case 1: /* MADI */
hdspm->control_register |= HDSPM_SyncRef0;
break;
case 2: /* TCO */
hdspm->control_register |= HDSPM_SyncRef1;
break;
case 3: /* SYNC_IN */
hdspm->control_register |=
HDSPM_SyncRef0+HDSPM_SyncRef1;
break;
default:
return -1;
}
} else {
switch (pref) {
case 0: /* WC */
break;
case 1: /* MADI */
hdspm->control_register |= HDSPM_SyncRef0;
break;
case 2: /* SYNC_IN */
hdspm->control_register |=
HDSPM_SyncRef0+HDSPM_SyncRef1;
break;
default:
return -1;
}
}
break;
case RayDAT:
if (hdspm->tco) {
switch (pref) {
case 0: p = 0; break; /* WC */
case 1: p = 3; break; /* ADAT 1 */
case 2: p = 4; break; /* ADAT 2 */
case 3: p = 5; break; /* ADAT 3 */
case 4: p = 6; break; /* ADAT 4 */
case 5: p = 1; break; /* AES */
case 6: p = 2; break; /* SPDIF */
case 7: p = 9; break; /* TCO */
case 8: p = 10; break; /* SYNC_IN */
default: return -1;
}
} else {
switch (pref) {
case 0: p = 0; break; /* WC */
case 1: p = 3; break; /* ADAT 1 */
case 2: p = 4; break; /* ADAT 2 */
case 3: p = 5; break; /* ADAT 3 */
case 4: p = 6; break; /* ADAT 4 */
case 5: p = 1; break; /* AES */
case 6: p = 2; break; /* SPDIF */
case 7: p = 10; break; /* SYNC_IN */
default: return -1;
}
}
break;
case AIO:
if (hdspm->tco) {
switch (pref) {
case 0: p = 0; break; /* WC */
case 1: p = 3; break; /* ADAT */
case 2: p = 1; break; /* AES */
case 3: p = 2; break; /* SPDIF */
case 4: p = 9; break; /* TCO */
case 5: p = 10; break; /* SYNC_IN */
default: return -1;
}
} else {
switch (pref) {
case 0: p = 0; break; /* WC */
case 1: p = 3; break; /* ADAT */
case 2: p = 1; break; /* AES */
case 3: p = 2; break; /* SPDIF */
case 4: p = 10; break; /* SYNC_IN */
default: return -1;
}
}
break;
}
switch (hdspm->io_type) {
case RayDAT:
case AIO:
hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
break;
case MADI:
case MADIface:
case AES32:
hdspm_write(hdspm, HDSPM_controlRegister,
hdspm->control_register);
}
return 0;
}
static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = hdspm->texts_autosync_items;
if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
uinfo->value.enumerated.item =
uinfo->value.enumerated.items - 1;
strcpy(uinfo->value.enumerated.name,
hdspm->texts_autosync[uinfo->value.enumerated.item]);
return 0;
}
static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int psf = hdspm_pref_sync_ref(hdspm);
if (psf >= 0) {
ucontrol->value.enumerated.item[0] = psf;
return 0;
}
return -1;
}
static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int val, change = 0;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.enumerated.item[0];
if (val < 0)
val = 0;
else if (val >= hdspm->texts_autosync_items)
val = hdspm->texts_autosync_items-1;
spin_lock_irq(&hdspm->lock);
if (val != hdspm_pref_sync_ref(hdspm))
change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_AUTOSYNC_REF(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READ, \
.info = snd_hdspm_info_autosync_ref, \
.get = snd_hdspm_get_autosync_ref, \
}
static int hdspm_autosync_ref(struct hdspm *hdspm)
{
if (AES32 == hdspm->io_type) {
unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
unsigned int syncref =
(status >> HDSPM_AES32_syncref_bit) & 0xF;
if (syncref == 0)
return HDSPM_AES32_AUTOSYNC_FROM_WORD;
if (syncref <= 8)
return syncref;
return HDSPM_AES32_AUTOSYNC_FROM_NONE;
} else if (MADI == hdspm->io_type) {
/* This looks at the autosync selected sync reference */
unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
switch (status2 & HDSPM_SelSyncRefMask) {
case HDSPM_SelSyncRef_WORD:
return HDSPM_AUTOSYNC_FROM_WORD;
case HDSPM_SelSyncRef_MADI:
return HDSPM_AUTOSYNC_FROM_MADI;
case HDSPM_SelSyncRef_TCO:
return HDSPM_AUTOSYNC_FROM_TCO;
case HDSPM_SelSyncRef_SyncIn:
return HDSPM_AUTOSYNC_FROM_SYNC_IN;
case HDSPM_SelSyncRef_NVALID:
return HDSPM_AUTOSYNC_FROM_NONE;
default:
return 0;
}
}
return 0;
}
static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (AES32 == hdspm->io_type) {
static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
"AES4", "AES5", "AES6", "AES7", "AES8", "None"};
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 10;
if (uinfo->value.enumerated.item >=
uinfo->value.enumerated.items)
uinfo->value.enumerated.item =
uinfo->value.enumerated.items - 1;
strcpy(uinfo->value.enumerated.name,
texts[uinfo->value.enumerated.item]);
} else if (MADI == hdspm->io_type) {
static char *texts[] = {"Word Clock", "MADI", "TCO",
"Sync In", "None" };
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 5;
if (uinfo->value.enumerated.item >=
uinfo->value.enumerated.items)
uinfo->value.enumerated.item =
uinfo->value.enumerated.items - 1;
strcpy(uinfo->value.enumerated.name,
texts[uinfo->value.enumerated.item]);
}
return 0;
}
static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
return 0;
}
#define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_READ |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_video_input_format, \
.get = snd_hdspm_get_tco_video_input_format, \
}
static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = {"No video", "NTSC", "PAL"};
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
u32 status;
int ret = 0;
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
HDSPM_TCO1_Video_Input_Format_PAL)) {
case HDSPM_TCO1_Video_Input_Format_NTSC:
/* ntsc */
ret = 1;
break;
case HDSPM_TCO1_Video_Input_Format_PAL:
/* pal */
ret = 2;
break;
default:
/* no video */
ret = 0;
break;
}
ucontrol->value.enumerated.item[0] = ret;
return 0;
}
#define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.access = SNDRV_CTL_ELEM_ACCESS_READ |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_ltc_frames, \
.get = snd_hdspm_get_tco_ltc_frames, \
}
static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
"30 fps"};
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
{
u32 status;
int ret = 0;
status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
if (status & HDSPM_TCO1_LTC_Input_valid) {
switch (status & (HDSPM_TCO1_LTC_Format_LSB |
HDSPM_TCO1_LTC_Format_MSB)) {
case 0:
/* 24 fps */
ret = 1;
break;
case HDSPM_TCO1_LTC_Format_LSB:
/* 25 fps */
ret = 2;
break;
case HDSPM_TCO1_LTC_Format_MSB:
/* 25 fps */
ret = 3;
break;
default:
/* 30 fps */
ret = 4;
break;
}
}
return ret;
}
static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
return 0;
}
#define HDSPM_TOGGLE_SETTING(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.private_value = xindex, \
.info = snd_hdspm_info_toggle_setting, \
.get = snd_hdspm_get_toggle_setting, \
.put = snd_hdspm_put_toggle_setting \
}
static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
{
return (hdspm->control_register & regmask) ? 1 : 0;
}
static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
{
if (out)
hdspm->control_register |= regmask;
else
hdspm->control_register &= ~regmask;
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
return 0;
}
#define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info
static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
u32 regmask = kcontrol->private_value;
spin_lock_irq(&hdspm->lock);
ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
u32 regmask = kcontrol->private_value;
int change;
unsigned int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.integer.value[0] & 1;
spin_lock_irq(&hdspm->lock);
change = (int) val != hdspm_toggle_setting(hdspm, regmask);
hdspm_set_toggle_setting(hdspm, regmask, val);
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_INPUT_SELECT(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.info = snd_hdspm_info_input_select, \
.get = snd_hdspm_get_input_select, \
.put = snd_hdspm_put_input_select \
}
static int hdspm_input_select(struct hdspm * hdspm)
{
return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
}
static int hdspm_set_input_select(struct hdspm * hdspm, int out)
{
if (out)
hdspm->control_register |= HDSPM_InputSelect0;
else
hdspm->control_register &= ~HDSPM_InputSelect0;
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
return 0;
}
static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "optical", "coaxial" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
spin_lock_irq(&hdspm->lock);
ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
unsigned int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.integer.value[0] & 1;
spin_lock_irq(&hdspm->lock);
change = (int) val != hdspm_input_select(hdspm);
hdspm_set_input_select(hdspm, val);
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_DS_WIRE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.info = snd_hdspm_info_ds_wire, \
.get = snd_hdspm_get_ds_wire, \
.put = snd_hdspm_put_ds_wire \
}
static int hdspm_ds_wire(struct hdspm * hdspm)
{
return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
}
static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
{
if (ds)
hdspm->control_register |= HDSPM_DS_DoubleWire;
else
hdspm->control_register &= ~HDSPM_DS_DoubleWire;
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
return 0;
}
static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "Single", "Double" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
spin_lock_irq(&hdspm->lock);
ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
unsigned int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.integer.value[0] & 1;
spin_lock_irq(&hdspm->lock);
change = (int) val != hdspm_ds_wire(hdspm);
hdspm_set_ds_wire(hdspm, val);
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_QS_WIRE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.info = snd_hdspm_info_qs_wire, \
.get = snd_hdspm_get_qs_wire, \
.put = snd_hdspm_put_qs_wire \
}
static int hdspm_qs_wire(struct hdspm * hdspm)
{
if (hdspm->control_register & HDSPM_QS_DoubleWire)
return 1;
if (hdspm->control_register & HDSPM_QS_QuadWire)
return 2;
return 0;
}
static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
{
hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
switch (mode) {
case 0:
break;
case 1:
hdspm->control_register |= HDSPM_QS_DoubleWire;
break;
case 2:
hdspm->control_register |= HDSPM_QS_QuadWire;
break;
}
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
return 0;
}
static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "Single", "Double", "Quad" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
spin_lock_irq(&hdspm->lock);
ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.integer.value[0];
if (val < 0)
val = 0;
if (val > 2)
val = 2;
spin_lock_irq(&hdspm->lock);
change = val != hdspm_qs_wire(hdspm);
hdspm_set_qs_wire(hdspm, val);
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_MADI_SPEEDMODE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.info = snd_hdspm_info_madi_speedmode, \
.get = snd_hdspm_get_madi_speedmode, \
.put = snd_hdspm_put_madi_speedmode \
}
static int hdspm_madi_speedmode(struct hdspm *hdspm)
{
if (hdspm->control_register & HDSPM_QuadSpeed)
return 2;
if (hdspm->control_register & HDSPM_DoubleSpeed)
return 1;
return 0;
}
static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
{
hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
switch (mode) {
case 0:
break;
case 1:
hdspm->control_register |= HDSPM_DoubleSpeed;
break;
case 2:
hdspm->control_register |= HDSPM_QuadSpeed;
break;
}
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
return 0;
}
static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "Single", "Double", "Quad" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
spin_lock_irq(&hdspm->lock);
ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
int val;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
val = ucontrol->value.integer.value[0];
if (val < 0)
val = 0;
if (val > 2)
val = 2;
spin_lock_irq(&hdspm->lock);
change = val != hdspm_madi_speedmode(hdspm);
hdspm_set_madi_speedmode(hdspm, val);
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_MIXER(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
.name = xname, \
.index = xindex, \
.device = 0, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_mixer, \
.get = snd_hdspm_get_mixer, \
.put = snd_hdspm_put_mixer \
}
static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 3;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 65535;
uinfo->value.integer.step = 1;
return 0;
}
static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int source;
int destination;
source = ucontrol->value.integer.value[0];
if (source < 0)
source = 0;
else if (source >= 2 * HDSPM_MAX_CHANNELS)
source = 2 * HDSPM_MAX_CHANNELS - 1;
destination = ucontrol->value.integer.value[1];
if (destination < 0)
destination = 0;
else if (destination >= HDSPM_MAX_CHANNELS)
destination = HDSPM_MAX_CHANNELS - 1;
spin_lock_irq(&hdspm->lock);
if (source >= HDSPM_MAX_CHANNELS)
ucontrol->value.integer.value[2] =
hdspm_read_pb_gain(hdspm, destination,
source - HDSPM_MAX_CHANNELS);
else
ucontrol->value.integer.value[2] =
hdspm_read_in_gain(hdspm, destination, source);
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
int source;
int destination;
int gain;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
source = ucontrol->value.integer.value[0];
destination = ucontrol->value.integer.value[1];
if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
return -1;
if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
return -1;
gain = ucontrol->value.integer.value[2];
spin_lock_irq(&hdspm->lock);
if (source >= HDSPM_MAX_CHANNELS)
change = gain != hdspm_read_pb_gain(hdspm, destination,
source -
HDSPM_MAX_CHANNELS);
else
change = gain != hdspm_read_in_gain(hdspm, destination,
source);
if (change) {
if (source >= HDSPM_MAX_CHANNELS)
hdspm_write_pb_gain(hdspm, destination,
source - HDSPM_MAX_CHANNELS,
gain);
else
hdspm_write_in_gain(hdspm, destination, source,
gain);
}
spin_unlock_irq(&hdspm->lock);
return change;
}
/* The simple mixer control(s) provide gain control for the
basic 1:1 mappings of playback streams to output
streams.
*/
#define HDSPM_PLAYBACK_MIXER \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_playback_mixer, \
.get = snd_hdspm_get_playback_mixer, \
.put = snd_hdspm_put_playback_mixer \
}
static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 64;
uinfo->value.integer.step = 1;
return 0;
}
static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int channel;
channel = ucontrol->id.index - 1;
if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
return -EINVAL;
spin_lock_irq(&hdspm->lock);
ucontrol->value.integer.value[0] =
(hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int change;
int channel;
int gain;
if (!snd_hdspm_use_is_exclusive(hdspm))
return -EBUSY;
channel = ucontrol->id.index - 1;
if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
return -EINVAL;
gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
spin_lock_irq(&hdspm->lock);
change =
gain != hdspm_read_pb_gain(hdspm, channel,
channel);
if (change)
hdspm_write_pb_gain(hdspm, channel, channel,
gain);
spin_unlock_irq(&hdspm->lock);
return change;
}
#define HDSPM_SYNC_CHECK(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.private_value = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_sync_check, \
.get = snd_hdspm_get_sync_check \
}
#define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.private_value = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_tco_info_lock_check, \
.get = snd_hdspm_get_sync_check \
}
static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "No Lock", "Lock" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int hdspm_wc_sync_check(struct hdspm *hdspm)
{
int status, status2;
switch (hdspm->io_type) {
case AES32:
status = hdspm_read(hdspm, HDSPM_statusRegister);
if (status & HDSPM_AES32_wcLock) {
if (status & HDSPM_AES32_wcSync)
return 2;
else
return 1;
}
return 0;
break;
case MADI:
status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
if (status2 & HDSPM_wcLock) {
if (status2 & HDSPM_wcSync)
return 2;
else
return 1;
}
return 0;
break;
case RayDAT:
case AIO:
status = hdspm_read(hdspm, HDSPM_statusRegister);
if (status & 0x2000000)
return 2;
else if (status & 0x1000000)
return 1;
return 0;
break;
case MADIface:
break;
}
return 3;
}
static int hdspm_madi_sync_check(struct hdspm *hdspm)
{
int status = hdspm_read(hdspm, HDSPM_statusRegister);
if (status & HDSPM_madiLock) {
if (status & HDSPM_madiSync)
return 2;
else
return 1;
}
return 0;
}
static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
{
int status, lock, sync;
status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
lock = (status & (0x1<<idx)) ? 1 : 0;
sync = (status & (0x100<<idx)) ? 1 : 0;
if (lock && sync)
return 2;
else if (lock)
return 1;
return 0;
}
static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
{
int status, lock = 0, sync = 0;
switch (hdspm->io_type) {
case RayDAT:
case AIO:
status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
lock = (status & 0x400) ? 1 : 0;
sync = (status & 0x800) ? 1 : 0;
break;
case MADI:
status = hdspm_read(hdspm, HDSPM_statusRegister);
lock = (status & HDSPM_syncInLock) ? 1 : 0;
sync = (status & HDSPM_syncInSync) ? 1 : 0;
break;
case AES32:
status = hdspm_read(hdspm, HDSPM_statusRegister2);
lock = (status & 0x100000) ? 1 : 0;
sync = (status & 0x200000) ? 1 : 0;
break;
case MADIface:
break;
}
if (lock && sync)
return 2;
else if (lock)
return 1;
return 0;
}
static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
{
int status2, lock, sync;
status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
if (sync)
return 2;
else if (lock)
return 1;
return 0;
}
static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
{
u32 status;
status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
return (status & mask) ? 1 : 0;
}
static int hdspm_tco_sync_check(struct hdspm *hdspm)
{
int status;
if (hdspm->tco) {
switch (hdspm->io_type) {
case MADI:
case AES32:
status = hdspm_read(hdspm, HDSPM_statusRegister);
if (status & HDSPM_tcoLock) {
if (status & HDSPM_tcoSync)
return 2;
else
return 1;
}
return 0;
break;
case RayDAT:
case AIO:
status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
if (status & 0x8000000)
return 2; /* Sync */
if (status & 0x4000000)
return 1; /* Lock */
return 0; /* No signal */
break;
default:
break;
}
}
return 3; /* N/A */
}
static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
int val = -1;
switch (hdspm->io_type) {
case RayDAT:
switch (kcontrol->private_value) {
case 0: /* WC */
val = hdspm_wc_sync_check(hdspm); break;
case 7: /* TCO */
val = hdspm_tco_sync_check(hdspm); break;
case 8: /* SYNC IN */
val = hdspm_sync_in_sync_check(hdspm); break;
default:
val = hdspm_s1_sync_check(hdspm,
kcontrol->private_value-1);
}
break;
case AIO:
switch (kcontrol->private_value) {
case 0: /* WC */
val = hdspm_wc_sync_check(hdspm); break;
case 4: /* TCO */
val = hdspm_tco_sync_check(hdspm); break;
case 5: /* SYNC IN */
val = hdspm_sync_in_sync_check(hdspm); break;
default:
val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
}
break;
case MADI:
switch (kcontrol->private_value) {
case 0: /* WC */
val = hdspm_wc_sync_check(hdspm); break;
case 1: /* MADI */
val = hdspm_madi_sync_check(hdspm); break;
case 2: /* TCO */
val = hdspm_tco_sync_check(hdspm); break;
case 3: /* SYNC_IN */
val = hdspm_sync_in_sync_check(hdspm); break;
}
break;
case MADIface:
val = hdspm_madi_sync_check(hdspm); /* MADI */
break;
case AES32:
switch (kcontrol->private_value) {
case 0: /* WC */
val = hdspm_wc_sync_check(hdspm); break;
case 9: /* TCO */
val = hdspm_tco_sync_check(hdspm); break;
case 10 /* SYNC IN */:
val = hdspm_sync_in_sync_check(hdspm); break;
default: /* AES1 to AES8 */
val = hdspm_aes_sync_check(hdspm,
kcontrol->private_value-1);
}
break;
}
if (hdspm->tco) {
switch (kcontrol->private_value) {
case 11:
/* Check TCO for lock state of its current input */
val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
break;
case 12:
/* Check TCO for valid time code on LTC input. */
val = hdspm_tco_input_check(hdspm,
HDSPM_TCO1_LTC_Input_valid);
break;
default:
break;
}
}
if (-1 == val)
val = 3;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
/**
* TCO controls
**/
static void hdspm_tco_write(struct hdspm *hdspm)
{
unsigned int tc[4] = { 0, 0, 0, 0};
switch (hdspm->tco->input) {
case 0:
tc[2] |= HDSPM_TCO2_set_input_MSB;
break;
case 1:
tc[2] |= HDSPM_TCO2_set_input_LSB;
break;
default:
break;
}
switch (hdspm->tco->framerate) {
case 1:
tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
break;
case 2:
tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
break;
case 3:
tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
HDSPM_TCO1_set_drop_frame_flag;
break;
case 4:
tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
HDSPM_TCO1_LTC_Format_MSB;
break;
case 5:
tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
HDSPM_TCO1_LTC_Format_MSB +
HDSPM_TCO1_set_drop_frame_flag;
break;
default:
break;
}
switch (hdspm->tco->wordclock) {
case 1:
tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
break;
case 2:
tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
break;
default:
break;
}
switch (hdspm->tco->samplerate) {
case 1:
tc[2] |= HDSPM_TCO2_set_freq;
break;
case 2:
tc[2] |= HDSPM_TCO2_set_freq_from_app;
break;
default:
break;
}
switch (hdspm->tco->pull) {
case 1:
tc[2] |= HDSPM_TCO2_set_pull_up;
break;
case 2:
tc[2] |= HDSPM_TCO2_set_pull_down;
break;
case 3:
tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
break;
case 4:
tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
break;
default:
break;
}
if (1 == hdspm->tco->term) {
tc[2] |= HDSPM_TCO2_set_term_75R;
}
hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
}
#define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_sample_rate, \
.get = snd_hdspm_get_tco_sample_rate, \
.put = snd_hdspm_put_tco_sample_rate \
}
static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "44.1 kHz", "48 kHz" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
return 0;
}
static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
hdspm_tco_write(hdspm);
return 1;
}
return 0;
}
#define HDSPM_TCO_PULL(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_pull, \
.get = snd_hdspm_get_tco_pull, \
.put = snd_hdspm_put_tco_pull \
}
static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
return 0;
}
static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
hdspm->tco->pull = ucontrol->value.enumerated.item[0];
hdspm_tco_write(hdspm);
return 1;
}
return 0;
}
#define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_wck_conversion, \
.get = snd_hdspm_get_tco_wck_conversion, \
.put = snd_hdspm_put_tco_wck_conversion \
}
static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
return 0;
}
static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
hdspm_tco_write(hdspm);
return 1;
}
return 0;
}
#define HDSPM_TCO_FRAME_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_frame_rate, \
.get = snd_hdspm_get_tco_frame_rate, \
.put = snd_hdspm_put_tco_frame_rate \
}
static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "24 fps", "25 fps", "29.97fps",
"29.97 dfps", "30 fps", "30 dfps" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
return 0;
}
static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
hdspm_tco_write(hdspm);
return 1;
}
return 0;
}
#define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_sync_source, \
.get = snd_hdspm_get_tco_sync_source, \
.put = snd_hdspm_put_tco_sync_source \
}
static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[] = { "LTC", "Video", "WCK" };
ENUMERATED_CTL_INFO(uinfo, texts);
return 0;
}
static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm->tco->input;
return 0;
}
static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
hdspm->tco->input = ucontrol->value.enumerated.item[0];
hdspm_tco_write(hdspm);
return 1;
}
return 0;
}
#define HDSPM_TCO_WORD_TERM(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
.name = xname, \
.index = xindex, \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
.info = snd_hdspm_info_tco_word_term, \
.get = snd_hdspm_get_tco_word_term, \
.put = snd_hdspm_put_tco_word_term \
}
static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 1;
return 0;
}
static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
ucontrol->value.enumerated.item[0] = hdspm->tco->term;
return 0;
}
static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
hdspm->tco->term = ucontrol->value.enumerated.item[0];
hdspm_tco_write(hdspm);
return 1;
}
return 0;
}
static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
HDSPM_MIXER("Mixer", 0),
HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
HDSPM_SYNC_CHECK("WC SyncCheck", 0),
HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
HDSPM_INPUT_SELECT("Input Select", 0),
HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
};
static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
HDSPM_MIXER("Mixer", 0),
HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
};
static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
HDSPM_MIXER("Mixer", 0),
HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
HDSPM_SYNC_CHECK("WC SyncCheck", 0),
HDSPM_SYNC_CHECK("AES SyncCheck", 1),
HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
/*
HDSPM_INPUT_SELECT("Input Select", 0),
HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
HDSPM_SPDIF_IN("SPDIF In", 0);
HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
HDSPM_INPUT_LEVEL("Input Level", 0);
HDSPM_OUTPUT_LEVEL("Output Level", 0);
HDSPM_PHONES("Phones", 0);
*/
};
static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
HDSPM_MIXER("Mixer", 0),
HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
HDSPM_SYNC_CHECK("WC SyncCheck", 0),
HDSPM_SYNC_CHECK("AES SyncCheck", 1),
HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
};
static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
HDSPM_MIXER("Mixer", 0),
HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
HDSPM_SYNC_CHECK("WC Sync Check", 0),
HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
HDSPM_SYNC_CHECK("TCO Sync Check", 9),
HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
};
/* Control elements for the optional TCO module */
static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
HDSPM_TCO_PULL("TCO Pull", 0),
HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
};
static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
{
int i;
for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
if (hdspm->system_sample_rate > 48000) {
hdspm->playback_mixer_ctls[i]->vd[0].access =
SNDRV_CTL_ELEM_ACCESS_INACTIVE |
SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE;
} else {
hdspm->playback_mixer_ctls[i]->vd[0].access =
SNDRV_CTL_ELEM_ACCESS_READWRITE |
SNDRV_CTL_ELEM_ACCESS_VOLATILE;
}
snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
SNDRV_CTL_EVENT_MASK_INFO,
&hdspm->playback_mixer_ctls[i]->id);
}
return 0;
}
static int snd_hdspm_create_controls(struct snd_card *card,
struct hdspm *hdspm)
{
unsigned int idx, limit;
int err;
struct snd_kcontrol *kctl;
struct snd_kcontrol_new *list = NULL;
switch (hdspm->io_type) {
case MADI:
list = snd_hdspm_controls_madi;
limit = ARRAY_SIZE(snd_hdspm_controls_madi);
break;
case MADIface:
list = snd_hdspm_controls_madiface;
limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
break;
case AIO:
list = snd_hdspm_controls_aio;
limit = ARRAY_SIZE(snd_hdspm_controls_aio);
break;
case RayDAT:
list = snd_hdspm_controls_raydat;
limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
break;
case AES32:
list = snd_hdspm_controls_aes32;
limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
break;
}
if (NULL != list) {
for (idx = 0; idx < limit; idx++) {
err = snd_ctl_add(card,
snd_ctl_new1(&list[idx], hdspm));
if (err < 0)
return err;
}
}
/* create simple 1:1 playback mixer controls */
snd_hdspm_playback_mixer.name = "Chn";
if (hdspm->system_sample_rate >= 128000) {
limit = hdspm->qs_out_channels;
} else if (hdspm->system_sample_rate >= 64000) {
limit = hdspm->ds_out_channels;
} else {
limit = hdspm->ss_out_channels;
}
for (idx = 0; idx < limit; ++idx) {
snd_hdspm_playback_mixer.index = idx + 1;
kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
err = snd_ctl_add(card, kctl);
if (err < 0)
return err;
hdspm->playback_mixer_ctls[idx] = kctl;
}
if (hdspm->tco) {
/* add tco control elements */
list = snd_hdspm_controls_tco;
limit = ARRAY_SIZE(snd_hdspm_controls_tco);
for (idx = 0; idx < limit; idx++) {
err = snd_ctl_add(card,
snd_ctl_new1(&list[idx], hdspm));
if (err < 0)
return err;
}
}
return 0;
}
/*------------------------------------------------------------
/proc interface
------------------------------------------------------------*/
static void
snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
struct snd_info_buffer *buffer)
{
struct hdspm *hdspm = entry->private_data;
unsigned int status, status2, control, freq;
char *pref_sync_ref;
char *autosync_ref;
char *system_clock_mode;
char *insel;
int x, x2;
/* TCO stuff */
int a, ltc, frames, seconds, minutes, hours;
unsigned int period;
u64 freq_const = 0;
u32 rate;
status = hdspm_read(hdspm, HDSPM_statusRegister);
status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
control = hdspm->control_register;
freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
hdspm->card_name, hdspm->card->number + 1,
hdspm->firmware_rev,
(status2 & HDSPM_version0) |
(status2 & HDSPM_version1) | (status2 &
HDSPM_version2));
snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
(hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
hdspm->serial);
snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
snd_iprintf(buffer, "--- System ---\n");
snd_iprintf(buffer,
"IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
status & HDSPM_audioIRQPending,
(status & HDSPM_midi0IRQPending) ? 1 : 0,
(status & HDSPM_midi1IRQPending) ? 1 : 0,
hdspm->irq_count);
snd_iprintf(buffer,
"HW pointer: id = %d, rawptr = %d (%d->%d) "
"estimated= %ld (bytes)\n",
((status & HDSPM_BufferID) ? 1 : 0),
(status & HDSPM_BufferPositionMask),
(status & HDSPM_BufferPositionMask) %
(2 * (int)hdspm->period_bytes),
((status & HDSPM_BufferPositionMask) - 64) %
(2 * (int)hdspm->period_bytes),
(long) hdspm_hw_pointer(hdspm) * 4);
snd_iprintf(buffer,
"MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
snd_iprintf(buffer,
"MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
snd_iprintf(buffer,
"Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
"status2=0x%x\n",
hdspm->control_register, hdspm->control2_register,
status, status2);
if (status & HDSPM_tco_detect) {
snd_iprintf(buffer, "TCO module detected.\n");
a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
if (a & HDSPM_TCO1_LTC_Input_valid) {
snd_iprintf(buffer, " LTC valid, ");
switch (a & (HDSPM_TCO1_LTC_Format_LSB |
HDSPM_TCO1_LTC_Format_MSB)) {
case 0:
snd_iprintf(buffer, "24 fps, ");
break;
case HDSPM_TCO1_LTC_Format_LSB:
snd_iprintf(buffer, "25 fps, ");
break;
case HDSPM_TCO1_LTC_Format_MSB:
snd_iprintf(buffer, "29.97 fps, ");
break;
default:
snd_iprintf(buffer, "30 fps, ");
break;
}
if (a & HDSPM_TCO1_set_drop_frame_flag) {
snd_iprintf(buffer, "drop frame\n");
} else {
snd_iprintf(buffer, "full frame\n");
}
} else {
snd_iprintf(buffer, " no LTC\n");
}
if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
snd_iprintf(buffer, " Video: NTSC\n");
} else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
snd_iprintf(buffer, " Video: PAL\n");
} else {
snd_iprintf(buffer, " No video\n");
}
if (a & HDSPM_TCO1_TCO_lock) {
snd_iprintf(buffer, " Sync: lock\n");
} else {
snd_iprintf(buffer, " Sync: no lock\n");
}
switch (hdspm->io_type) {
case MADI:
case AES32:
freq_const = 110069313433624ULL;
break;
case RayDAT:
case AIO:
freq_const = 104857600000000ULL;
break;
case MADIface:
break; /* no TCO possible */
}
period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
snd_iprintf(buffer, " period: %u\n", period);
/* rate = freq_const/period; */
rate = div_u64(freq_const, period);
if (control & HDSPM_QuadSpeed) {
rate *= 4;
} else if (control & HDSPM_DoubleSpeed) {
rate *= 2;
}
snd_iprintf(buffer, " Frequency: %u Hz\n",
(unsigned int) rate);
ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
frames = ltc & 0xF;
ltc >>= 4;
frames += (ltc & 0x3) * 10;
ltc >>= 4;
seconds = ltc & 0xF;
ltc >>= 4;
seconds += (ltc & 0x7) * 10;
ltc >>= 4;
minutes = ltc & 0xF;
ltc >>= 4;
minutes += (ltc & 0x7) * 10;
ltc >>= 4;
hours = ltc & 0xF;
ltc >>= 4;
hours += (ltc & 0x3) * 10;
snd_iprintf(buffer,
" LTC In: %02d:%02d:%02d:%02d\n",
hours, minutes, seconds, frames);
} else {
snd_iprintf(buffer, "No TCO module detected.\n");
}
snd_iprintf(buffer, "--- Settings ---\n");
x = hdspm_get_latency(hdspm);
snd_iprintf(buffer,
"Size (Latency): %d samples (2 periods of %lu bytes)\n",
x, (unsigned long) hdspm->period_bytes);
snd_iprintf(buffer, "Line out: %s\n",
(hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
switch (hdspm->control_register & HDSPM_InputMask) {
case HDSPM_InputOptical:
insel = "Optical";
break;
case HDSPM_InputCoaxial:
insel = "Coaxial";
break;
default:
insel = "Unknown";
}
snd_iprintf(buffer,
"ClearTrackMarker = %s, Transmit in %s Channel Mode, "
"Auto Input %s\n",
(hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
(hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
(hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
if (!(hdspm->control_register & HDSPM_ClockModeMaster))
system_clock_mode = "AutoSync";
else
system_clock_mode = "Master";
snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
switch (hdspm_pref_sync_ref(hdspm)) {
case HDSPM_SYNC_FROM_WORD:
pref_sync_ref = "Word Clock";
break;
case HDSPM_SYNC_FROM_MADI:
pref_sync_ref = "MADI Sync";
break;
case HDSPM_SYNC_FROM_TCO:
pref_sync_ref = "TCO";
break;
case HDSPM_SYNC_FROM_SYNC_IN:
pref_sync_ref = "Sync In";
break;
default:
pref_sync_ref = "XXXX Clock";
break;
}
snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
pref_sync_ref);
snd_iprintf(buffer, "System Clock Frequency: %d\n",
hdspm->system_sample_rate);
snd_iprintf(buffer, "--- Status:\n");
x = status & HDSPM_madiSync;
x2 = status2 & HDSPM_wcSync;
snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
(status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
"NoLock",
(status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
"NoLock");
switch (hdspm_autosync_ref(hdspm)) {
case HDSPM_AUTOSYNC_FROM_SYNC_IN:
autosync_ref = "Sync In";
break;
case HDSPM_AUTOSYNC_FROM_TCO:
autosync_ref = "TCO";
break;
case HDSPM_AUTOSYNC_FROM_WORD:
autosync_ref = "Word Clock";
break;
case HDSPM_AUTOSYNC_FROM_MADI:
autosync_ref = "MADI Sync";
break;
case HDSPM_AUTOSYNC_FROM_NONE:
autosync_ref = "Input not valid";
break;
default:
autosync_ref = "---";
break;
}
snd_iprintf(buffer,
"AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
autosync_ref, hdspm_external_sample_rate(hdspm),
(status & HDSPM_madiFreqMask) >> 22,
(status2 & HDSPM_wcFreqMask) >> 5);
snd_iprintf(buffer, "Input: %s, Mode=%s\n",
(status & HDSPM_AB_int) ? "Coax" : "Optical",
(status & HDSPM_RX_64ch) ? "64 channels" :
"56 channels");
snd_iprintf(buffer, "\n");
}
static void
snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
struct snd_info_buffer *buffer)
{
struct hdspm *hdspm = entry->private_data;
unsigned int status;
unsigned int status2;
unsigned int timecode;
unsigned int wcLock, wcSync;
int pref_syncref;
char *autosync_ref;
int x;
status = hdspm_read(hdspm, HDSPM_statusRegister);
status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
hdspm->card_name, hdspm->card->number + 1,
hdspm->firmware_rev);
snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
snd_iprintf(buffer, "--- System ---\n");
snd_iprintf(buffer,
"IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
status & HDSPM_audioIRQPending,
(status & HDSPM_midi0IRQPending) ? 1 : 0,
(status & HDSPM_midi1IRQPending) ? 1 : 0,
hdspm->irq_count);
snd_iprintf(buffer,
"HW pointer: id = %d, rawptr = %d (%d->%d) "
"estimated= %ld (bytes)\n",
((status & HDSPM_BufferID) ? 1 : 0),
(status & HDSPM_BufferPositionMask),
(status & HDSPM_BufferPositionMask) %
(2 * (int)hdspm->period_bytes),
((status & HDSPM_BufferPositionMask) - 64) %
(2 * (int)hdspm->period_bytes),
(long) hdspm_hw_pointer(hdspm) * 4);
snd_iprintf(buffer,
"MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
snd_iprintf(buffer,
"MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
snd_iprintf(buffer,
"Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
"status2=0x%x\n",
hdspm->control_register, hdspm->control2_register,
status, status2);
snd_iprintf(buffer, "--- Settings ---\n");
x = hdspm_get_latency(hdspm);
snd_iprintf(buffer,
"Size (Latency): %d samples (2 periods of %lu bytes)\n",
x, (unsigned long) hdspm->period_bytes);
snd_iprintf(buffer, "Line out: %s\n",
(hdspm->
control_register & HDSPM_LineOut) ? "on " : "off");
snd_iprintf(buffer,
"ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
(hdspm->
control_register & HDSPM_clr_tms) ? "on" : "off",
(hdspm->
control_register & HDSPM_Emphasis) ? "on" : "off",
(hdspm->
control_register & HDSPM_Dolby) ? "on" : "off");
pref_syncref = hdspm_pref_sync_ref(hdspm);
if (pref_syncref == 0)
snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
else
snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
pref_syncref);
snd_iprintf(buffer, "System Clock Frequency: %d\n",
hdspm->system_sample_rate);
snd_iprintf(buffer, "Double speed: %s\n",
hdspm->control_register & HDSPM_DS_DoubleWire?
"Double wire" : "Single wire");
snd_iprintf(buffer, "Quad speed: %s\n",
hdspm->control_register & HDSPM_QS_DoubleWire?
"Double wire" :
hdspm->control_register & HDSPM_QS_QuadWire?
"Quad wire" : "Single wire");
snd_iprintf(buffer, "--- Status:\n");
wcLock = status & HDSPM_AES32_wcLock;
wcSync = wcLock && (status & HDSPM_AES32_wcSync);
snd_iprintf(buffer, "Word: %s Frequency: %d\n",
(wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
for (x = 0; x < 8; x++) {
snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
x+1,
(status2 & (HDSPM_LockAES >> x)) ?
"Sync " : "No Lock",
HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
}
switch (hdspm_autosync_ref(hdspm)) {
case HDSPM_AES32_AUTOSYNC_FROM_NONE:
autosync_ref = "None"; break;
case HDSPM_AES32_AUTOSYNC_FROM_WORD:
autosync_ref = "Word Clock"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES1:
autosync_ref = "AES1"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES2:
autosync_ref = "AES2"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES3:
autosync_ref = "AES3"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES4:
autosync_ref = "AES4"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES5:
autosync_ref = "AES5"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES6:
autosync_ref = "AES6"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES7:
autosync_ref = "AES7"; break;
case HDSPM_AES32_AUTOSYNC_FROM_AES8:
autosync_ref = "AES8"; break;
default:
autosync_ref = "---"; break;
}
snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
snd_iprintf(buffer, "\n");
}
static void
snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
struct hdspm *hdspm = entry->private_data;
unsigned int status1, status2, status3, control, i;
unsigned int lock, sync;
status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
control = hdspm->control_register;
snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
snd_iprintf(buffer, "Clock mode : %s\n",
(hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
snd_iprintf(buffer, "System frequency: %d Hz\n",
hdspm_get_system_sample_rate(hdspm));
snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
lock = 0x1;
sync = 0x100;
for (i = 0; i < 8; i++) {
snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
i,
(status1 & lock) ? 1 : 0,
(status1 & sync) ? 1 : 0,
texts_freq[(status2 >> (i * 4)) & 0xF]);
lock = lock<<1;
sync = sync<<1;
}
snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
(status1 & 0x1000000) ? 1 : 0,
(status1 & 0x2000000) ? 1 : 0,
texts_freq[(status1 >> 16) & 0xF]);
snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
(status1 & 0x4000000) ? 1 : 0,
(status1 & 0x8000000) ? 1 : 0,
texts_freq[(status1 >> 20) & 0xF]);
snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
(status3 & 0x400) ? 1 : 0,
(status3 & 0x800) ? 1 : 0,
texts_freq[(status2 >> 12) & 0xF]);
}
#ifdef CONFIG_SND_DEBUG
static void
snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
struct hdspm *hdspm = entry->private_data;
int j,i;
for (i = 0; i < 256 /* 1024*64 */; i += j) {
snd_iprintf(buffer, "0x%08X: ", i);
for (j = 0; j < 16; j += 4)
snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
snd_iprintf(buffer, "\n");
}
}
#endif
static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
struct hdspm *hdspm = entry->private_data;
int i;
snd_iprintf(buffer, "# generated by hdspm\n");
for (i = 0; i < hdspm->max_channels_in; i++) {
snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
}
}
static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
struct hdspm *hdspm = entry->private_data;
int i;
snd_iprintf(buffer, "# generated by hdspm\n");
for (i = 0; i < hdspm->max_channels_out; i++) {
snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
}
}
static void snd_hdspm_proc_init(struct hdspm *hdspm)
{
struct snd_info_entry *entry;
if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
switch (hdspm->io_type) {
case AES32:
snd_info_set_text_ops(entry, hdspm,
snd_hdspm_proc_read_aes32);
break;
case MADI:
snd_info_set_text_ops(entry, hdspm,
snd_hdspm_proc_read_madi);
break;
case MADIface:
/* snd_info_set_text_ops(entry, hdspm,
snd_hdspm_proc_read_madiface); */
break;
case RayDAT:
snd_info_set_text_ops(entry, hdspm,
snd_hdspm_proc_read_raydat);
break;
case AIO:
break;
}
}
if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
}
if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
}
#ifdef CONFIG_SND_DEBUG
/* debug file to read all hdspm registers */
if (!snd_card_proc_new(hdspm->card, "debug", &entry))
snd_info_set_text_ops(entry, hdspm,
snd_hdspm_proc_read_debug);
#endif
}
/*------------------------------------------------------------
hdspm intitialize
------------------------------------------------------------*/
static int snd_hdspm_set_defaults(struct hdspm * hdspm)
{
/* ASSUMPTION: hdspm->lock is either held, or there is no need to
hold it (e.g. during module initialization).
*/
/* set defaults: */
hdspm->settings_register = 0;
switch (hdspm->io_type) {
case MADI:
case MADIface:
hdspm->control_register =
0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
break;
case RayDAT:
case AIO:
hdspm->settings_register = 0x1 + 0x1000;
/* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
* line_out */
hdspm->control_register =
0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
break;
case AES32:
hdspm->control_register =
HDSPM_ClockModeMaster | /* Master Cloack Mode on */
hdspm_encode_latency(7) | /* latency max=8192samples */
HDSPM_SyncRef0 | /* AES1 is syncclock */
HDSPM_LineOut | /* Analog output in */
HDSPM_Professional; /* Professional mode */
break;
}
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
if (AES32 == hdspm->io_type) {
/* No control2 register for AES32 */
#ifdef SNDRV_BIG_ENDIAN
hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
#else
hdspm->control2_register = 0;
#endif
hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
}
hdspm_compute_period_size(hdspm);
/* silence everything */
all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
}
/* set a default rate so that the channel map is set up. */
hdspm_set_rate(hdspm, 48000, 1);
return 0;
}
/*------------------------------------------------------------
interrupt
------------------------------------------------------------*/
static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
{
struct hdspm *hdspm = (struct hdspm *) dev_id;
unsigned int status;
int i, audio, midi, schedule = 0;
/* cycles_t now; */
status = hdspm_read(hdspm, HDSPM_statusRegister);
audio = status & HDSPM_audioIRQPending;
midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
/* now = get_cycles(); */
/**
* LAT_2..LAT_0 period counter (win) counter (mac)
* 6 4096 ~256053425 ~514672358
* 5 2048 ~128024983 ~257373821
* 4 1024 ~64023706 ~128718089
* 3 512 ~32005945 ~64385999
* 2 256 ~16003039 ~32260176
* 1 128 ~7998738 ~16194507
* 0 64 ~3998231 ~8191558
**/
/*
snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
now-hdspm->last_interrupt, status & 0xFFC0);
hdspm->last_interrupt = now;
*/
if (!audio && !midi)
return IRQ_NONE;
hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
hdspm->irq_count++;
if (audio) {
if (hdspm->capture_substream)
snd_pcm_period_elapsed(hdspm->capture_substream);
if (hdspm->playback_substream)
snd_pcm_period_elapsed(hdspm->playback_substream);
}
if (midi) {
i = 0;
while (i < hdspm->midiPorts) {
if ((hdspm_read(hdspm,
hdspm->midi[i].statusIn) & 0xff) &&
(status & hdspm->midi[i].irq)) {
/* we disable interrupts for this input until
* processing is done
*/
hdspm->control_register &= ~hdspm->midi[i].ie;
hdspm_write(hdspm, HDSPM_controlRegister,
hdspm->control_register);
hdspm->midi[i].pending = 1;
schedule = 1;
}
i++;
}
if (schedule)
tasklet_hi_schedule(&hdspm->midi_tasklet);
}
return IRQ_HANDLED;
}
/*------------------------------------------------------------
pcm interface
------------------------------------------------------------*/
static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
*substream)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
return hdspm_hw_pointer(hdspm);
}
static int snd_hdspm_reset(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
struct snd_pcm_substream *other;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
other = hdspm->capture_substream;
else
other = hdspm->playback_substream;
if (hdspm->running)
runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
else
runtime->status->hw_ptr = 0;
if (other) {
struct snd_pcm_substream *s;
struct snd_pcm_runtime *oruntime = other->runtime;
snd_pcm_group_for_each_entry(s, substream) {
if (s == other) {
oruntime->status->hw_ptr =
runtime->status->hw_ptr;
break;
}
}
}
return 0;
}
static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
int err;
int i;
pid_t this_pid;
pid_t other_pid;
spin_lock_irq(&hdspm->lock);
if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
this_pid = hdspm->playback_pid;
other_pid = hdspm->capture_pid;
} else {
this_pid = hdspm->capture_pid;
other_pid = hdspm->playback_pid;
}
if (other_pid > 0 && this_pid != other_pid) {
/* The other stream is open, and not by the same
task as this one. Make sure that the parameters
that matter are the same.
*/
if (params_rate(params) != hdspm->system_sample_rate) {
spin_unlock_irq(&hdspm->lock);
_snd_pcm_hw_param_setempty(params,
SNDRV_PCM_HW_PARAM_RATE);
return -EBUSY;
}
if (params_period_size(params) != hdspm->period_bytes / 4) {
spin_unlock_irq(&hdspm->lock);
_snd_pcm_hw_param_setempty(params,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
return -EBUSY;
}
}
/* We're fine. */
spin_unlock_irq(&hdspm->lock);
/* how to make sure that the rate matches an externally-set one ? */
spin_lock_irq(&hdspm->lock);
err = hdspm_set_rate(hdspm, params_rate(params), 0);
if (err < 0) {
snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
spin_unlock_irq(&hdspm->lock);
_snd_pcm_hw_param_setempty(params,
SNDRV_PCM_HW_PARAM_RATE);
return err;
}
spin_unlock_irq(&hdspm->lock);
err = hdspm_set_interrupt_interval(hdspm,
params_period_size(params));
if (err < 0) {
snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
_snd_pcm_hw_param_setempty(params,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
return err;
}
/* Memory allocation, takashi's method, dont know if we should
* spinlock
*/
/* malloc all buffer even if not enabled to get sure */
/* Update for MADI rev 204: we need to allocate for all channels,
* otherwise it doesn't work at 96kHz */
err =
snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
if (err < 0) {
snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
return err;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
params_channels(params));
for (i = 0; i < params_channels(params); ++i)
snd_hdspm_enable_out(hdspm, i, 1);
hdspm->playback_buffer =
(unsigned char *) substream->runtime->dma_area;
snd_printdd("Allocated sample buffer for playback at %p\n",
hdspm->playback_buffer);
} else {
hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
params_channels(params));
for (i = 0; i < params_channels(params); ++i)
snd_hdspm_enable_in(hdspm, i, 1);
hdspm->capture_buffer =
(unsigned char *) substream->runtime->dma_area;
snd_printdd("Allocated sample buffer for capture at %p\n",
hdspm->capture_buffer);
}
/*
snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
"playback" : "capture",
snd_pcm_sgbuf_get_addr(substream, 0));
*/
/*
snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
"playback" : "capture",
params_rate(params), params_channels(params),
params_buffer_size(params));
*/
/* Switch to native float format if requested */
if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
hdspm->control_register |= HDSPe_FLOAT_FORMAT;
} else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
}
hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
return 0;
}
static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
{
int i;
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* params_channels(params) should be enough,
but to get sure in case of error */
for (i = 0; i < hdspm->max_channels_out; ++i)
snd_hdspm_enable_out(hdspm, i, 0);
hdspm->playback_buffer = NULL;
} else {
for (i = 0; i < hdspm->max_channels_in; ++i)
snd_hdspm_enable_in(hdspm, i, 0);
hdspm->capture_buffer = NULL;
}
snd_pcm_lib_free_pages(substream);
return 0;
}
static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
struct snd_pcm_channel_info *info)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
return -EINVAL;
}
if (hdspm->channel_map_out[info->channel] < 0) {
snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
return -EINVAL;
}
info->offset = hdspm->channel_map_out[info->channel] *
HDSPM_CHANNEL_BUFFER_BYTES;
} else {
if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
return -EINVAL;
}
if (hdspm->channel_map_in[info->channel] < 0) {
snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
return -EINVAL;
}
info->offset = hdspm->channel_map_in[info->channel] *
HDSPM_CHANNEL_BUFFER_BYTES;
}
info->first = 0;
info->step = 32;
return 0;
}
static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
unsigned int cmd, void *arg)
{
switch (cmd) {
case SNDRV_PCM_IOCTL1_RESET:
return snd_hdspm_reset(substream);
case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
{
struct snd_pcm_channel_info *info = arg;
return snd_hdspm_channel_info(substream, info);
}
default:
break;
}
return snd_pcm_lib_ioctl(substream, cmd, arg);
}
static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
struct snd_pcm_substream *other;
int running;
spin_lock(&hdspm->lock);
running = hdspm->running;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
running |= 1 << substream->stream;
break;
case SNDRV_PCM_TRIGGER_STOP:
running &= ~(1 << substream->stream);
break;
default:
snd_BUG();
spin_unlock(&hdspm->lock);
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
other = hdspm->capture_substream;
else
other = hdspm->playback_substream;
if (other) {
struct snd_pcm_substream *s;
snd_pcm_group_for_each_entry(s, substream) {
if (s == other) {
snd_pcm_trigger_done(s, substream);
if (cmd == SNDRV_PCM_TRIGGER_START)
running |= 1 << s->stream;
else
running &= ~(1 << s->stream);
goto _ok;
}
}
if (cmd == SNDRV_PCM_TRIGGER_START) {
if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
&& substream->stream ==
SNDRV_PCM_STREAM_CAPTURE)
hdspm_silence_playback(hdspm);
} else {
if (running &&
substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
hdspm_silence_playback(hdspm);
}
} else {
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
hdspm_silence_playback(hdspm);
}
_ok:
snd_pcm_trigger_done(substream, substream);
if (!hdspm->running && running)
hdspm_start_audio(hdspm);
else if (hdspm->running && !running)
hdspm_stop_audio(hdspm);
hdspm->running = running;
spin_unlock(&hdspm->lock);
return 0;
}
static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
{
return 0;
}
static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_NONINTERLEAVED |
SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_64000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
.rate_min = 32000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = HDSPM_MAX_CHANNELS,
.buffer_bytes_max =
HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
.period_bytes_min = (32 * 4),
.period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
.periods_min = 2,
.periods_max = 512,
.fifo_size = 0
};
static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_NONINTERLEAVED |
SNDRV_PCM_INFO_SYNC_START),
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_64000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
.rate_min = 32000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = HDSPM_MAX_CHANNELS,
.buffer_bytes_max =
HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
.period_bytes_min = (32 * 4),
.period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
.periods_min = 2,
.periods_max = 512,
.fifo_size = 0
};
static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct hdspm *hdspm = rule->private;
struct snd_interval *c =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_interval *r =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
if (r->min > 96000 && r->max <= 192000) {
struct snd_interval t = {
.min = hdspm->qs_in_channels,
.max = hdspm->qs_in_channels,
.integer = 1,
};
return snd_interval_refine(c, &t);
} else if (r->min > 48000 && r->max <= 96000) {
struct snd_interval t = {
.min = hdspm->ds_in_channels,
.max = hdspm->ds_in_channels,
.integer = 1,
};
return snd_interval_refine(c, &t);
} else if (r->max < 64000) {
struct snd_interval t = {
.min = hdspm->ss_in_channels,
.max = hdspm->ss_in_channels,
.integer = 1,
};
return snd_interval_refine(c, &t);
}
return 0;
}
static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule * rule)
{
struct hdspm *hdspm = rule->private;
struct snd_interval *c =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_interval *r =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
if (r->min > 96000 && r->max <= 192000) {
struct snd_interval t = {
.min = hdspm->qs_out_channels,
.max = hdspm->qs_out_channels,
.integer = 1,
};
return snd_interval_refine(c, &t);
} else if (r->min > 48000 && r->max <= 96000) {
struct snd_interval t = {
.min = hdspm->ds_out_channels,
.max = hdspm->ds_out_channels,
.integer = 1,
};
return snd_interval_refine(c, &t);
} else if (r->max < 64000) {
struct snd_interval t = {
.min = hdspm->ss_out_channels,
.max = hdspm->ss_out_channels,
.integer = 1,
};
return snd_interval_refine(c, &t);
} else {
}
return 0;
}
static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule * rule)
{
struct hdspm *hdspm = rule->private;
struct snd_interval *c =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_interval *r =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
if (c->min >= hdspm->ss_in_channels) {
struct snd_interval t = {
.min = 32000,
.max = 48000,
.integer = 1,
};
return snd_interval_refine(r, &t);
} else if (c->max <= hdspm->qs_in_channels) {
struct snd_interval t = {
.min = 128000,
.max = 192000,
.integer = 1,
};
return snd_interval_refine(r, &t);
} else if (c->max <= hdspm->ds_in_channels) {
struct snd_interval t = {
.min = 64000,
.max = 96000,
.integer = 1,
};
return snd_interval_refine(r, &t);
}
return 0;
}
static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct hdspm *hdspm = rule->private;
struct snd_interval *c =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_interval *r =
hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
if (c->min >= hdspm->ss_out_channels) {
struct snd_interval t = {
.min = 32000,
.max = 48000,
.integer = 1,
};
return snd_interval_refine(r, &t);
} else if (c->max <= hdspm->qs_out_channels) {
struct snd_interval t = {
.min = 128000,
.max = 192000,
.integer = 1,
};
return snd_interval_refine(r, &t);
} else if (c->max <= hdspm->ds_out_channels) {
struct snd_interval t = {
.min = 64000,
.max = 96000,
.integer = 1,
};
return snd_interval_refine(r, &t);
}
return 0;
}
static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
unsigned int list[3];
struct hdspm *hdspm = rule->private;
struct snd_interval *c = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
list[0] = hdspm->qs_in_channels;
list[1] = hdspm->ds_in_channels;
list[2] = hdspm->ss_in_channels;
return snd_interval_list(c, 3, list, 0);
}
static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
unsigned int list[3];
struct hdspm *hdspm = rule->private;
struct snd_interval *c = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
list[0] = hdspm->qs_out_channels;
list[1] = hdspm->ds_out_channels;
list[2] = hdspm->ss_out_channels;
return snd_interval_list(c, 3, list, 0);
}
static unsigned int hdspm_aes32_sample_rates[] = {
32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
};
static struct snd_pcm_hw_constraint_list
hdspm_hw_constraints_aes32_sample_rates = {
.count = ARRAY_SIZE(hdspm_aes32_sample_rates),
.list = hdspm_aes32_sample_rates,
.mask = 0
};
static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
spin_lock_irq(&hdspm->lock);
snd_pcm_set_sync(substream);
runtime->hw = snd_hdspm_playback_subinfo;
if (hdspm->capture_substream == NULL)
hdspm_stop_audio(hdspm);
hdspm->playback_pid = current->pid;
hdspm->playback_substream = substream;
spin_unlock_irq(&hdspm->lock);
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
switch (hdspm->io_type) {
case AIO:
case RayDAT:
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
32, 4096);
/* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
16384, 16384);
break;
default:
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
64, 8192);
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIODS,
2, 2);
break;
}
if (AES32 == hdspm->io_type) {
runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&hdspm_hw_constraints_aes32_sample_rates);
} else {
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
snd_hdspm_hw_rule_rate_out_channels, hdspm,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
}
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
snd_hdspm_hw_rule_out_channels, hdspm,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
snd_hdspm_hw_rule_out_channels_rate, hdspm,
SNDRV_PCM_HW_PARAM_RATE, -1);
return 0;
}
static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
spin_lock_irq(&hdspm->lock);
hdspm->playback_pid = -1;
hdspm->playback_substream = NULL;
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
spin_lock_irq(&hdspm->lock);
snd_pcm_set_sync(substream);
runtime->hw = snd_hdspm_capture_subinfo;
if (hdspm->playback_substream == NULL)
hdspm_stop_audio(hdspm);
hdspm->capture_pid = current->pid;
hdspm->capture_substream = substream;
spin_unlock_irq(&hdspm->lock);
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
switch (hdspm->io_type) {
case AIO:
case RayDAT:
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
32, 4096);
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
16384, 16384);
break;
default:
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
64, 8192);
snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIODS,
2, 2);
break;
}
if (AES32 == hdspm->io_type) {
runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&hdspm_hw_constraints_aes32_sample_rates);
} else {
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
snd_hdspm_hw_rule_rate_in_channels, hdspm,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
}
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
snd_hdspm_hw_rule_in_channels, hdspm,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
snd_hdspm_hw_rule_in_channels_rate, hdspm,
SNDRV_PCM_HW_PARAM_RATE, -1);
return 0;
}
static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
{
struct hdspm *hdspm = snd_pcm_substream_chip(substream);
spin_lock_irq(&hdspm->lock);
hdspm->capture_pid = -1;
hdspm->capture_substream = NULL;
spin_unlock_irq(&hdspm->lock);
return 0;
}
static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
{
/* we have nothing to initialize but the call is required */
return 0;
}
static inline int copy_u32_le(void __user *dest, void __iomem *src)
{
u32 val = readl(src);
return copy_to_user(dest, &val, 4);
}
static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
struct hdspm *hdspm = hw->private_data;
struct hdspm_mixer_ioctl mixer;
struct hdspm_config info;
struct hdspm_status status;
struct hdspm_version hdspm_version;
struct hdspm_peak_rms *levels;
struct hdspm_ltc ltc;
unsigned int statusregister;
long unsigned int s;
int i = 0;
switch (cmd) {
case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
levels = &hdspm->peak_rms;
for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
levels->input_peaks[i] =
readl(hdspm->iobase +
HDSPM_MADI_INPUT_PEAK + i*4);
levels->playback_peaks[i] =
readl(hdspm->iobase +
HDSPM_MADI_PLAYBACK_PEAK + i*4);
levels->output_peaks[i] =
readl(hdspm->iobase +
HDSPM_MADI_OUTPUT_PEAK + i*4);
levels->input_rms[i] =
((uint64_t) readl(hdspm->iobase +
HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
(uint64_t) readl(hdspm->iobase +
HDSPM_MADI_INPUT_RMS_L + i*4);
levels->playback_rms[i] =
((uint64_t)readl(hdspm->iobase +
HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
(uint64_t)readl(hdspm->iobase +
HDSPM_MADI_PLAYBACK_RMS_L + i*4);
levels->output_rms[i] =
((uint64_t)readl(hdspm->iobase +
HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
(uint64_t)readl(hdspm->iobase +
HDSPM_MADI_OUTPUT_RMS_L + i*4);
}
if (hdspm->system_sample_rate > 96000) {
levels->speed = qs;
} else if (hdspm->system_sample_rate > 48000) {
levels->speed = ds;
} else {
levels->speed = ss;
}
levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
if (0 != s) {
/* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
[Levels]\n", sizeof(struct hdspm_peak_rms), s);
*/
return -EFAULT;
}
break;
case SNDRV_HDSPM_IOCTL_GET_LTC:
ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
if (i & HDSPM_TCO1_LTC_Input_valid) {
switch (i & (HDSPM_TCO1_LTC_Format_LSB |
HDSPM_TCO1_LTC_Format_MSB)) {
case 0:
ltc.format = fps_24;
break;
case HDSPM_TCO1_LTC_Format_LSB:
ltc.format = fps_25;
break;
case HDSPM_TCO1_LTC_Format_MSB:
ltc.format = fps_2997;
break;
default:
ltc.format = 30;
break;
}
if (i & HDSPM_TCO1_set_drop_frame_flag) {
ltc.frame = drop_frame;
} else {
ltc.frame = full_frame;
}
} else {
ltc.format = format_invalid;
ltc.frame = frame_invalid;
}
if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
ltc.input_format = ntsc;
} else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
ltc.input_format = pal;
} else {
ltc.input_format = no_video;
}
s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
if (0 != s) {
/*
snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
return -EFAULT;
}
break;
case SNDRV_HDSPM_IOCTL_GET_CONFIG:
memset(&info, 0, sizeof(info));
spin_lock_irq(&hdspm->lock);
info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
info.system_sample_rate = hdspm->system_sample_rate;
info.autosync_sample_rate =
hdspm_external_sample_rate(hdspm);
info.system_clock_mode = hdspm_system_clock_mode(hdspm);
info.clock_source = hdspm_clock_source(hdspm);
info.autosync_ref = hdspm_autosync_ref(hdspm);
info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
info.passthru = 0;
spin_unlock_irq(&hdspm->lock);
if (copy_to_user(argp, &info, sizeof(info)))
return -EFAULT;
break;
case SNDRV_HDSPM_IOCTL_GET_STATUS:
memset(&status, 0, sizeof(status));
status.card_type = hdspm->io_type;
status.autosync_source = hdspm_autosync_ref(hdspm);
status.card_clock = 110069313433624ULL;
status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
switch (hdspm->io_type) {
case MADI:
case MADIface:
status.card_specific.madi.sync_wc =
hdspm_wc_sync_check(hdspm);
status.card_specific.madi.sync_madi =
hdspm_madi_sync_check(hdspm);
status.card_specific.madi.sync_tco =
hdspm_tco_sync_check(hdspm);
status.card_specific.madi.sync_in =
hdspm_sync_in_sync_check(hdspm);
statusregister =
hdspm_read(hdspm, HDSPM_statusRegister);
status.card_specific.madi.madi_input =
(statusregister & HDSPM_AB_int) ? 1 : 0;
status.card_specific.madi.channel_format =
(statusregister & HDSPM_RX_64ch) ? 1 : 0;
/* TODO: Mac driver sets it when f_s>48kHz */
status.card_specific.madi.frame_format = 0;
default:
break;
}
if (copy_to_user(argp, &status, sizeof(status)))
return -EFAULT;
break;
case SNDRV_HDSPM_IOCTL_GET_VERSION:
memset(&hdspm_version, 0, sizeof(hdspm_version));
hdspm_version.card_type = hdspm->io_type;
strncpy(hdspm_version.cardname, hdspm->card_name,
sizeof(hdspm_version.cardname));
hdspm_version.serial = hdspm->serial;
hdspm_version.firmware_rev = hdspm->firmware_rev;
hdspm_version.addons = 0;
if (hdspm->tco)
hdspm_version.addons |= HDSPM_ADDON_TCO;
if (copy_to_user(argp, &hdspm_version,
sizeof(hdspm_version)))
return -EFAULT;
break;
case SNDRV_HDSPM_IOCTL_GET_MIXER:
if (copy_from_user(&mixer, argp, sizeof(mixer)))
return -EFAULT;
if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
sizeof(struct hdspm_mixer)))
return -EFAULT;
break;
default:
return -EINVAL;
}
return 0;
}
static struct snd_pcm_ops snd_hdspm_playback_ops = {
.open = snd_hdspm_playback_open,
.close = snd_hdspm_playback_release,
.ioctl = snd_hdspm_ioctl,
.hw_params = snd_hdspm_hw_params,
.hw_free = snd_hdspm_hw_free,
.prepare = snd_hdspm_prepare,
.trigger = snd_hdspm_trigger,
.pointer = snd_hdspm_hw_pointer,
.page = snd_pcm_sgbuf_ops_page,
};
static struct snd_pcm_ops snd_hdspm_capture_ops = {
.open = snd_hdspm_capture_open,
.close = snd_hdspm_capture_release,
.ioctl = snd_hdspm_ioctl,
.hw_params = snd_hdspm_hw_params,
.hw_free = snd_hdspm_hw_free,
.prepare = snd_hdspm_prepare,
.trigger = snd_hdspm_trigger,
.pointer = snd_hdspm_hw_pointer,
.page = snd_pcm_sgbuf_ops_page,
};
static int snd_hdspm_create_hwdep(struct snd_card *card,
struct hdspm *hdspm)
{
struct snd_hwdep *hw;
int err;
err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
if (err < 0)
return err;
hdspm->hwdep = hw;
hw->private_data = hdspm;
strcpy(hw->name, "HDSPM hwdep interface");
hw->ops.open = snd_hdspm_hwdep_dummy_op;
hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
hw->ops.release = snd_hdspm_hwdep_dummy_op;
return 0;
}
/*------------------------------------------------------------
memory interface
------------------------------------------------------------*/
static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
{
int err;
struct snd_pcm *pcm;
size_t wanted;
pcm = hdspm->pcm;
wanted = HDSPM_DMA_AREA_BYTES;
err =
snd_pcm_lib_preallocate_pages_for_all(pcm,
SNDRV_DMA_TYPE_DEV_SG,
snd_dma_pci_data(hdspm->pci),
wanted,
wanted);
if (err < 0) {
snd_printdd("Could not preallocate %zd Bytes\n", wanted);
return err;
} else
snd_printdd(" Preallocated %zd Bytes\n", wanted);
return 0;
}
static void hdspm_set_sgbuf(struct hdspm *hdspm,
struct snd_pcm_substream *substream,
unsigned int reg, int channels)
{
int i;
/* continuous memory segment */
for (i = 0; i < (channels * 16); i++)
hdspm_write(hdspm, reg + 4 * i,
snd_pcm_sgbuf_get_addr(substream, 4096 * i));
}
/* ------------- ALSA Devices ---------------------------- */
static int snd_hdspm_create_pcm(struct snd_card *card,
struct hdspm *hdspm)
{
struct snd_pcm *pcm;
int err;
err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
if (err < 0)
return err;
hdspm->pcm = pcm;
pcm->private_data = hdspm;
strcpy(pcm->name, hdspm->card_name);
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
&snd_hdspm_playback_ops);
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
&snd_hdspm_capture_ops);
pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
err = snd_hdspm_preallocate_memory(hdspm);
if (err < 0)
return err;
return 0;
}
static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
{
int i;
for (i = 0; i < hdspm->midiPorts; i++)
snd_hdspm_flush_midi_input(hdspm, i);
}
static int snd_hdspm_create_alsa_devices(struct snd_card *card,
struct hdspm *hdspm)
{
int err, i;
snd_printdd("Create card...\n");
err = snd_hdspm_create_pcm(card, hdspm);
if (err < 0)
return err;
i = 0;
while (i < hdspm->midiPorts) {
err = snd_hdspm_create_midi(card, hdspm, i);
if (err < 0) {
return err;
}
i++;
}
err = snd_hdspm_create_controls(card, hdspm);
if (err < 0)
return err;
err = snd_hdspm_create_hwdep(card, hdspm);
if (err < 0)
return err;
snd_printdd("proc init...\n");
snd_hdspm_proc_init(hdspm);
hdspm->system_sample_rate = -1;
hdspm->last_external_sample_rate = -1;
hdspm->last_internal_sample_rate = -1;
hdspm->playback_pid = -1;
hdspm->capture_pid = -1;
hdspm->capture_substream = NULL;
hdspm->playback_substream = NULL;
snd_printdd("Set defaults...\n");
err = snd_hdspm_set_defaults(hdspm);
if (err < 0)
return err;
snd_printdd("Update mixer controls...\n");
hdspm_update_simple_mixer_controls(hdspm);
snd_printdd("Initializeing complete ???\n");
err = snd_card_register(card);
if (err < 0) {
snd_printk(KERN_ERR "HDSPM: error registering card\n");
return err;
}
snd_printdd("... yes now\n");
return 0;
}
static int snd_hdspm_create(struct snd_card *card,
struct hdspm *hdspm)
{
struct pci_dev *pci = hdspm->pci;
int err;
unsigned long io_extent;
hdspm->irq = -1;
hdspm->card = card;
spin_lock_init(&hdspm->lock);
pci_read_config_word(hdspm->pci,
PCI_CLASS_REVISION, &hdspm->firmware_rev);
strcpy(card->mixername, "Xilinx FPGA");
strcpy(card->driver, "HDSPM");
switch (hdspm->firmware_rev) {
case HDSPM_RAYDAT_REV:
hdspm->io_type = RayDAT;
hdspm->card_name = "RME RayDAT";
hdspm->midiPorts = 2;
break;
case HDSPM_AIO_REV:
hdspm->io_type = AIO;
hdspm->card_name = "RME AIO";
hdspm->midiPorts = 1;
break;
case HDSPM_MADIFACE_REV:
hdspm->io_type = MADIface;
hdspm->card_name = "RME MADIface";
hdspm->midiPorts = 1;
break;
default:
if ((hdspm->firmware_rev == 0xf0) ||
((hdspm->firmware_rev >= 0xe6) &&
(hdspm->firmware_rev <= 0xea))) {
hdspm->io_type = AES32;
hdspm->card_name = "RME AES32";
hdspm->midiPorts = 2;
} else if ((hdspm->firmware_rev == 0xd2) ||
((hdspm->firmware_rev >= 0xc8) &&
(hdspm->firmware_rev <= 0xcf))) {
hdspm->io_type = MADI;
hdspm->card_name = "RME MADI";
hdspm->midiPorts = 3;
} else {
snd_printk(KERN_ERR
"HDSPM: unknown firmware revision %x\n",
hdspm->firmware_rev);
return -ENODEV;
}
}
err = pci_enable_device(pci);
if (err < 0)
return err;
pci_set_master(hdspm->pci);
err = pci_request_regions(pci, "hdspm");
if (err < 0)
return err;
hdspm->port = pci_resource_start(pci, 0);
io_extent = pci_resource_len(pci, 0);
snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
hdspm->port, hdspm->port + io_extent - 1);
hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
if (!hdspm->iobase) {
snd_printk(KERN_ERR "HDSPM: "
"unable to remap region 0x%lx-0x%lx\n",
hdspm->port, hdspm->port + io_extent - 1);
return -EBUSY;
}
snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
(unsigned long)hdspm->iobase, hdspm->port,
hdspm->port + io_extent - 1);
if (request_irq(pci->irq, snd_hdspm_interrupt,
IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
return -EBUSY;
}
snd_printdd("use IRQ %d\n", pci->irq);
hdspm->irq = pci->irq;
snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
sizeof(struct hdspm_mixer));
hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
if (!hdspm->mixer) {
snd_printk(KERN_ERR "HDSPM: "
"unable to kmalloc Mixer memory of %d Bytes\n",
(int)sizeof(struct hdspm_mixer));
return -ENOMEM;
}
hdspm->port_names_in = NULL;
hdspm->port_names_out = NULL;
switch (hdspm->io_type) {
case AES32:
hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
channel_map_aes32;
hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
channel_map_aes32;
hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
channel_map_aes32;
hdspm->port_names_in_ss = hdspm->port_names_out_ss =
texts_ports_aes32;
hdspm->port_names_in_ds = hdspm->port_names_out_ds =
texts_ports_aes32;
hdspm->port_names_in_qs = hdspm->port_names_out_qs =
texts_ports_aes32;
hdspm->max_channels_out = hdspm->max_channels_in =
AES32_CHANNELS;
hdspm->port_names_in = hdspm->port_names_out =
texts_ports_aes32;
hdspm->channel_map_in = hdspm->channel_map_out =
channel_map_aes32;
break;
case MADI:
case MADIface:
hdspm->ss_in_channels = hdspm->ss_out_channels =
MADI_SS_CHANNELS;
hdspm->ds_in_channels = hdspm->ds_out_channels =
MADI_DS_CHANNELS;
hdspm->qs_in_channels = hdspm->qs_out_channels =
MADI_QS_CHANNELS;
hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
channel_map_unity_ss;
hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
channel_map_unity_ss;
hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
channel_map_unity_ss;
hdspm->port_names_in_ss = hdspm->port_names_out_ss =
texts_ports_madi;
hdspm->port_names_in_ds = hdspm->port_names_out_ds =
texts_ports_madi;
hdspm->port_names_in_qs = hdspm->port_names_out_qs =
texts_ports_madi;
break;
case AIO:
if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
}
hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
hdspm->channel_map_out_ss = channel_map_aio_out_ss;
hdspm->channel_map_out_ds = channel_map_aio_out_ds;
hdspm->channel_map_out_qs = channel_map_aio_out_qs;
hdspm->channel_map_in_ss = channel_map_aio_in_ss;
hdspm->channel_map_in_ds = channel_map_aio_in_ds;
hdspm->channel_map_in_qs = channel_map_aio_in_qs;
hdspm->port_names_in_ss = texts_ports_aio_in_ss;
hdspm->port_names_out_ss = texts_ports_aio_out_ss;
hdspm->port_names_in_ds = texts_ports_aio_in_ds;
hdspm->port_names_out_ds = texts_ports_aio_out_ds;
hdspm->port_names_in_qs = texts_ports_aio_in_qs;
hdspm->port_names_out_qs = texts_ports_aio_out_qs;
break;
case RayDAT:
hdspm->ss_in_channels = hdspm->ss_out_channels =
RAYDAT_SS_CHANNELS;
hdspm->ds_in_channels = hdspm->ds_out_channels =
RAYDAT_DS_CHANNELS;
hdspm->qs_in_channels = hdspm->qs_out_channels =
RAYDAT_QS_CHANNELS;
hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
channel_map_raydat_ss;
hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
channel_map_raydat_ds;
hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
channel_map_raydat_qs;
hdspm->channel_map_in = hdspm->channel_map_out =
channel_map_raydat_ss;
hdspm->port_names_in_ss = hdspm->port_names_out_ss =
texts_ports_raydat_ss;
hdspm->port_names_in_ds = hdspm->port_names_out_ds =
texts_ports_raydat_ds;
hdspm->port_names_in_qs = hdspm->port_names_out_qs =
texts_ports_raydat_qs;
break;
}
/* TCO detection */
switch (hdspm->io_type) {
case AIO:
case RayDAT:
if (hdspm_read(hdspm, HDSPM_statusRegister2) &
HDSPM_s2_tco_detect) {
hdspm->midiPorts++;
hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
GFP_KERNEL);
if (NULL != hdspm->tco) {
hdspm_tco_write(hdspm);
}
snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
} else {
hdspm->tco = NULL;
}
break;
case MADI:
if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
hdspm->midiPorts++;
hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
GFP_KERNEL);
if (NULL != hdspm->tco) {
hdspm_tco_write(hdspm);
}
snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
} else {
hdspm->tco = NULL;
}
break;
default:
hdspm->tco = NULL;
}
/* texts */
switch (hdspm->io_type) {
case AES32:
if (hdspm->tco) {
hdspm->texts_autosync = texts_autosync_aes_tco;
hdspm->texts_autosync_items = 10;
} else {
hdspm->texts_autosync = texts_autosync_aes;
hdspm->texts_autosync_items = 9;
}
break;
case MADI:
if (hdspm->tco) {
hdspm->texts_autosync = texts_autosync_madi_tco;
hdspm->texts_autosync_items = 4;
} else {
hdspm->texts_autosync = texts_autosync_madi;
hdspm->texts_autosync_items = 3;
}
break;
case MADIface:
break;
case RayDAT:
if (hdspm->tco) {
hdspm->texts_autosync = texts_autosync_raydat_tco;
hdspm->texts_autosync_items = 9;
} else {
hdspm->texts_autosync = texts_autosync_raydat;
hdspm->texts_autosync_items = 8;
}
break;
case AIO:
if (hdspm->tco) {
hdspm->texts_autosync = texts_autosync_aio_tco;
hdspm->texts_autosync_items = 6;
} else {
hdspm->texts_autosync = texts_autosync_aio;
hdspm->texts_autosync_items = 5;
}
break;
}
tasklet_init(&hdspm->midi_tasklet,
hdspm_midi_tasklet, (unsigned long) hdspm);
if (hdspm->io_type != MADIface) {
hdspm->serial = (hdspm_read(hdspm,
HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
/* id contains either a user-provided value or the default
* NULL. If it's the default, we're safe to
* fill card->id with the serial number.
*
* If the serial number is 0xFFFFFF, then we're dealing with
* an old PCI revision that comes without a sane number. In
* this case, we don't set card->id to avoid collisions
* when running with multiple cards.
*/
if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
sprintf(card->id, "HDSPMx%06x", hdspm->serial);
snd_card_set_id(card, card->id);
}
}
snd_printdd("create alsa devices.\n");
err = snd_hdspm_create_alsa_devices(card, hdspm);
if (err < 0)
return err;
snd_hdspm_initialize_midi_flush(hdspm);
return 0;
}
static int snd_hdspm_free(struct hdspm * hdspm)
{
if (hdspm->port) {
/* stop th audio, and cancel all interrupts */
hdspm->control_register &=
~(HDSPM_Start | HDSPM_AudioInterruptEnable |
HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
hdspm_write(hdspm, HDSPM_controlRegister,
hdspm->control_register);
}
if (hdspm->irq >= 0)
free_irq(hdspm->irq, (void *) hdspm);
kfree(hdspm->mixer);
if (hdspm->iobase)
iounmap(hdspm->iobase);
if (hdspm->port)
pci_release_regions(hdspm->pci);
pci_disable_device(hdspm->pci);
return 0;
}
static void snd_hdspm_card_free(struct snd_card *card)
{
struct hdspm *hdspm = card->private_data;
if (hdspm)
snd_hdspm_free(hdspm);
}
static int snd_hdspm_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
static int dev;
struct hdspm *hdspm;
struct snd_card *card;
int err;
if (dev >= SNDRV_CARDS)
return -ENODEV;
if (!enable[dev]) {
dev++;
return -ENOENT;
}
err = snd_card_create(index[dev], id[dev],
THIS_MODULE, sizeof(struct hdspm), &card);
if (err < 0)
return err;
hdspm = card->private_data;
card->private_free = snd_hdspm_card_free;
hdspm->dev = dev;
hdspm->pci = pci;
snd_card_set_dev(card, &pci->dev);
err = snd_hdspm_create(card, hdspm);
if (err < 0) {
snd_card_free(card);
return err;
}
if (hdspm->io_type != MADIface) {
sprintf(card->shortname, "%s_%x",
hdspm->card_name,
hdspm->serial);
sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
hdspm->card_name,
hdspm->serial,
hdspm->port, hdspm->irq);
} else {
sprintf(card->shortname, "%s", hdspm->card_name);
sprintf(card->longname, "%s at 0x%lx, irq %d",
hdspm->card_name, hdspm->port, hdspm->irq);
}
err = snd_card_register(card);
if (err < 0) {
snd_card_free(card);
return err;
}
pci_set_drvdata(pci, card);
dev++;
return 0;
}
static void snd_hdspm_remove(struct pci_dev *pci)
{
snd_card_free(pci_get_drvdata(pci));
pci_set_drvdata(pci, NULL);
}
static struct pci_driver hdspm_driver = {
.name = KBUILD_MODNAME,
.id_table = snd_hdspm_ids,
.probe = snd_hdspm_probe,
.remove = snd_hdspm_remove,
};
module_pci_driver(hdspm_driver);
| gpl-2.0 |
omonar/linux | drivers/staging/lustre/lnet/lnet/module.c | 356 | 3590 | /*
* GPL HEADER START
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 only,
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License version 2 for more details (a copy is included
* in the LICENSE file that accompanied this code).
*
* You should have received a copy of the GNU General Public License
* version 2 along with this program; If not, see
* http://www.sun.com/software/products/lustre/docs/GPLv2.pdf
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
* GPL HEADER END
*/
/*
* Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
* Use is subject to license terms.
*
* Copyright (c) 2012, Intel Corporation.
*/
/*
* This file is part of Lustre, http://www.lustre.org/
* Lustre is a trademark of Sun Microsystems, Inc.
*/
#define DEBUG_SUBSYSTEM S_LNET
#include "../../include/linux/lnet/lib-lnet.h"
static int config_on_load;
module_param(config_on_load, int, 0444);
MODULE_PARM_DESC(config_on_load, "configure network at module load");
static struct mutex lnet_config_mutex;
static int
lnet_configure(void *arg)
{
/* 'arg' only there so I can be passed to cfs_create_thread() */
int rc = 0;
LNET_MUTEX_LOCK(&lnet_config_mutex);
if (!the_lnet.ln_niinit_self) {
rc = LNetNIInit(LUSTRE_SRV_LNET_PID);
if (rc >= 0) {
the_lnet.ln_niinit_self = 1;
rc = 0;
}
}
LNET_MUTEX_UNLOCK(&lnet_config_mutex);
return rc;
}
static int
lnet_unconfigure(void)
{
int refcount;
LNET_MUTEX_LOCK(&lnet_config_mutex);
if (the_lnet.ln_niinit_self) {
the_lnet.ln_niinit_self = 0;
LNetNIFini();
}
LNET_MUTEX_LOCK(&the_lnet.ln_api_mutex);
refcount = the_lnet.ln_refcount;
LNET_MUTEX_UNLOCK(&the_lnet.ln_api_mutex);
LNET_MUTEX_UNLOCK(&lnet_config_mutex);
return (refcount == 0) ? 0 : -EBUSY;
}
static int
lnet_ioctl(unsigned int cmd, struct libcfs_ioctl_data *data)
{
int rc;
switch (cmd) {
case IOC_LIBCFS_CONFIGURE:
return lnet_configure(NULL);
case IOC_LIBCFS_UNCONFIGURE:
return lnet_unconfigure();
default:
/* Passing LNET_PID_ANY only gives me a ref if the net is up
* already; I'll need it to ensure the net can't go down while
* I'm called into it */
rc = LNetNIInit(LNET_PID_ANY);
if (rc >= 0) {
rc = LNetCtl(cmd, data);
LNetNIFini();
}
return rc;
}
}
static DECLARE_IOCTL_HANDLER(lnet_ioctl_handler, lnet_ioctl);
static int __init
init_lnet(void)
{
int rc;
mutex_init(&lnet_config_mutex);
rc = LNetInit();
if (rc != 0) {
CERROR("LNetInit: error %d\n", rc);
return rc;
}
rc = libcfs_register_ioctl(&lnet_ioctl_handler);
LASSERT(rc == 0);
if (config_on_load) {
/* Have to schedule a separate thread to avoid deadlocking
* in modload */
(void) kthread_run(lnet_configure, NULL, "lnet_initd");
}
return 0;
}
static void __exit
fini_lnet(void)
{
int rc;
rc = libcfs_deregister_ioctl(&lnet_ioctl_handler);
LASSERT(rc == 0);
LNetFini();
}
MODULE_AUTHOR("Peter J. Braam <braam@clusterfs.com>");
MODULE_DESCRIPTION("Portals v3.1");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.0.0");
module_init(init_lnet);
module_exit(fini_lnet);
| gpl-2.0 |
uberlaggydarwin/bugfree-wookie | fs/notify/inotify/inotify_user.c | 356 | 18568 | /*
* fs/inotify_user.c - inotify support for userspace
*
* Authors:
* John McCutchan <ttb@tentacle.dhs.org>
* Robert Love <rml@novell.com>
*
* Copyright (C) 2005 John McCutchan
* Copyright 2006 Hewlett-Packard Development Company, L.P.
*
* Copyright (C) 2009 Eric Paris <Red Hat Inc>
* inotify was largely rewriten to make use of the fsnotify infrastructure
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/file.h>
#include <linux/fs.h>
#include <linux/fsnotify_backend.h>
#include <linux/idr.h>
#include <linux/init.h>
#include <linux/inotify.h>
#include <linux/kernel.h>
#include <linux/namei.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/syscalls.h>
#include <linux/types.h>
#include <linux/anon_inodes.h>
#include <linux/uaccess.h>
#include <linux/poll.h>
#include <linux/wait.h>
#include "inotify.h"
#include <asm/ioctls.h>
static int inotify_max_user_instances __read_mostly;
static int inotify_max_queued_events __read_mostly;
static int inotify_max_user_watches __read_mostly;
static struct kmem_cache *inotify_inode_mark_cachep __read_mostly;
struct kmem_cache *event_priv_cachep __read_mostly;
#ifdef CONFIG_SYSCTL
#include <linux/sysctl.h>
static int zero;
ctl_table inotify_table[] = {
{
.procname = "max_user_instances",
.data = &inotify_max_user_instances,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec_minmax,
.extra1 = &zero,
},
{
.procname = "max_user_watches",
.data = &inotify_max_user_watches,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec_minmax,
.extra1 = &zero,
},
{
.procname = "max_queued_events",
.data = &inotify_max_queued_events,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec_minmax,
.extra1 = &zero
},
{ }
};
#endif
static inline __u32 inotify_arg_to_mask(u32 arg)
{
__u32 mask;
mask = (FS_IN_IGNORED | FS_EVENT_ON_CHILD | FS_UNMOUNT);
mask |= (arg & (IN_ALL_EVENTS | IN_ONESHOT | IN_EXCL_UNLINK));
return mask;
}
static inline u32 inotify_mask_to_arg(__u32 mask)
{
return mask & (IN_ALL_EVENTS | IN_ISDIR | IN_UNMOUNT | IN_IGNORED |
IN_Q_OVERFLOW);
}
static unsigned int inotify_poll(struct file *file, poll_table *wait)
{
struct fsnotify_group *group = file->private_data;
int ret = 0;
poll_wait(file, &group->notification_waitq, wait);
mutex_lock(&group->notification_mutex);
if (!fsnotify_notify_queue_is_empty(group))
ret = POLLIN | POLLRDNORM;
mutex_unlock(&group->notification_mutex);
return ret;
}
static struct fsnotify_event *get_one_event(struct fsnotify_group *group,
size_t count)
{
size_t event_size = sizeof(struct inotify_event);
struct fsnotify_event *event;
if (fsnotify_notify_queue_is_empty(group))
return NULL;
event = fsnotify_peek_notify_event(group);
pr_debug("%s: group=%p event=%p\n", __func__, group, event);
if (event->name_len)
event_size += roundup(event->name_len + 1, event_size);
if (event_size > count)
return ERR_PTR(-EINVAL);
fsnotify_remove_notify_event(group);
return event;
}
static ssize_t copy_event_to_user(struct fsnotify_group *group,
struct fsnotify_event *event,
char __user *buf)
{
struct inotify_event inotify_event;
struct fsnotify_event_private_data *fsn_priv;
struct inotify_event_private_data *priv;
size_t event_size = sizeof(struct inotify_event);
size_t name_len = 0;
pr_debug("%s: group=%p event=%p\n", __func__, group, event);
spin_lock(&event->lock);
fsn_priv = fsnotify_remove_priv_from_event(group, event);
spin_unlock(&event->lock);
if (!fsn_priv)
inotify_event.wd = -1;
else {
priv = container_of(fsn_priv, struct inotify_event_private_data,
fsnotify_event_priv_data);
inotify_event.wd = priv->wd;
inotify_free_event_priv(fsn_priv);
}
if (event->name_len)
name_len = roundup(event->name_len + 1, event_size);
inotify_event.len = name_len;
inotify_event.mask = inotify_mask_to_arg(event->mask);
inotify_event.cookie = event->sync_cookie;
if (copy_to_user(buf, &inotify_event, event_size))
return -EFAULT;
buf += event_size;
if (name_len) {
unsigned int len_to_zero = name_len - event->name_len;
if (copy_to_user(buf, event->file_name, event->name_len))
return -EFAULT;
buf += event->name_len;
if (clear_user(buf, len_to_zero))
return -EFAULT;
buf += len_to_zero;
event_size += name_len;
}
return event_size;
}
static ssize_t inotify_read(struct file *file, char __user *buf,
size_t count, loff_t *pos)
{
struct fsnotify_group *group;
struct fsnotify_event *kevent;
char __user *start;
int ret;
DEFINE_WAIT(wait);
start = buf;
group = file->private_data;
while (1) {
prepare_to_wait(&group->notification_waitq, &wait, TASK_INTERRUPTIBLE);
mutex_lock(&group->notification_mutex);
kevent = get_one_event(group, count);
mutex_unlock(&group->notification_mutex);
pr_debug("%s: group=%p kevent=%p\n", __func__, group, kevent);
if (kevent) {
ret = PTR_ERR(kevent);
if (IS_ERR(kevent))
break;
ret = copy_event_to_user(group, kevent, buf);
fsnotify_put_event(kevent);
if (ret < 0)
break;
buf += ret;
count -= ret;
continue;
}
ret = -EAGAIN;
if (file->f_flags & O_NONBLOCK)
break;
ret = -EINTR;
if (signal_pending(current))
break;
if (start != buf)
break;
schedule();
}
finish_wait(&group->notification_waitq, &wait);
if (start != buf && ret != -EFAULT)
ret = buf - start;
return ret;
}
static int inotify_fasync(int fd, struct file *file, int on)
{
struct fsnotify_group *group = file->private_data;
return fasync_helper(fd, file, on, &group->inotify_data.fa) >= 0 ? 0 : -EIO;
}
static int inotify_release(struct inode *ignored, struct file *file)
{
struct fsnotify_group *group = file->private_data;
pr_debug("%s: group=%p\n", __func__, group);
fsnotify_clear_marks_by_group(group);
fsnotify_put_group(group);
return 0;
}
static long inotify_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct fsnotify_group *group;
struct fsnotify_event_holder *holder;
struct fsnotify_event *event;
void __user *p;
int ret = -ENOTTY;
size_t send_len = 0;
group = file->private_data;
p = (void __user *) arg;
pr_debug("%s: group=%p cmd=%u\n", __func__, group, cmd);
switch (cmd) {
case FIONREAD:
mutex_lock(&group->notification_mutex);
list_for_each_entry(holder, &group->notification_list, event_list) {
event = holder->event;
send_len += sizeof(struct inotify_event);
if (event->name_len)
send_len += roundup(event->name_len + 1,
sizeof(struct inotify_event));
}
mutex_unlock(&group->notification_mutex);
ret = put_user(send_len, (int __user *) p);
break;
}
return ret;
}
static const struct file_operations inotify_fops = {
.poll = inotify_poll,
.read = inotify_read,
.fasync = inotify_fasync,
.release = inotify_release,
.unlocked_ioctl = inotify_ioctl,
.compat_ioctl = inotify_ioctl,
.llseek = noop_llseek,
};
static int inotify_find_inode(const char __user *dirname, struct path *path, unsigned flags)
{
int error;
error = user_path_at(AT_FDCWD, dirname, flags, path);
if (error)
return error;
error = inode_permission(path->dentry->d_inode, MAY_READ);
if (error)
path_put(path);
return error;
}
static int inotify_add_to_idr(struct idr *idr, spinlock_t *idr_lock,
int *last_wd,
struct inotify_inode_mark *i_mark)
{
int ret;
do {
if (unlikely(!idr_pre_get(idr, GFP_KERNEL)))
return -ENOMEM;
spin_lock(idr_lock);
ret = idr_get_new_above(idr, i_mark, *last_wd + 1,
&i_mark->wd);
if (!ret) {
*last_wd = i_mark->wd;
fsnotify_get_mark(&i_mark->fsn_mark);
}
spin_unlock(idr_lock);
} while (ret == -EAGAIN);
return ret;
}
static struct inotify_inode_mark *inotify_idr_find_locked(struct fsnotify_group *group,
int wd)
{
struct idr *idr = &group->inotify_data.idr;
spinlock_t *idr_lock = &group->inotify_data.idr_lock;
struct inotify_inode_mark *i_mark;
assert_spin_locked(idr_lock);
i_mark = idr_find(idr, wd);
if (i_mark) {
struct fsnotify_mark *fsn_mark = &i_mark->fsn_mark;
fsnotify_get_mark(fsn_mark);
BUG_ON(atomic_read(&fsn_mark->refcnt) < 2);
}
return i_mark;
}
static struct inotify_inode_mark *inotify_idr_find(struct fsnotify_group *group,
int wd)
{
struct inotify_inode_mark *i_mark;
spinlock_t *idr_lock = &group->inotify_data.idr_lock;
spin_lock(idr_lock);
i_mark = inotify_idr_find_locked(group, wd);
spin_unlock(idr_lock);
return i_mark;
}
static void do_inotify_remove_from_idr(struct fsnotify_group *group,
struct inotify_inode_mark *i_mark)
{
struct idr *idr = &group->inotify_data.idr;
spinlock_t *idr_lock = &group->inotify_data.idr_lock;
int wd = i_mark->wd;
assert_spin_locked(idr_lock);
idr_remove(idr, wd);
fsnotify_put_mark(&i_mark->fsn_mark);
}
static void inotify_remove_from_idr(struct fsnotify_group *group,
struct inotify_inode_mark *i_mark)
{
spinlock_t *idr_lock = &group->inotify_data.idr_lock;
struct inotify_inode_mark *found_i_mark = NULL;
int wd;
spin_lock(idr_lock);
wd = i_mark->wd;
if (wd == -1) {
WARN_ONCE(1, "%s: i_mark=%p i_mark->wd=%d i_mark->group=%p"
" i_mark->inode=%p\n", __func__, i_mark, i_mark->wd,
i_mark->fsn_mark.group, i_mark->fsn_mark.i.inode);
goto out;
}
found_i_mark = inotify_idr_find_locked(group, wd);
if (unlikely(!found_i_mark)) {
WARN_ONCE(1, "%s: i_mark=%p i_mark->wd=%d i_mark->group=%p"
" i_mark->inode=%p\n", __func__, i_mark, i_mark->wd,
i_mark->fsn_mark.group, i_mark->fsn_mark.i.inode);
goto out;
}
if (unlikely(found_i_mark != i_mark)) {
WARN_ONCE(1, "%s: i_mark=%p i_mark->wd=%d i_mark->group=%p "
"mark->inode=%p found_i_mark=%p found_i_mark->wd=%d "
"found_i_mark->group=%p found_i_mark->inode=%p\n",
__func__, i_mark, i_mark->wd, i_mark->fsn_mark.group,
i_mark->fsn_mark.i.inode, found_i_mark, found_i_mark->wd,
found_i_mark->fsn_mark.group,
found_i_mark->fsn_mark.i.inode);
goto out;
}
if (unlikely(atomic_read(&i_mark->fsn_mark.refcnt) < 3)) {
printk(KERN_ERR "%s: i_mark=%p i_mark->wd=%d i_mark->group=%p"
" i_mark->inode=%p\n", __func__, i_mark, i_mark->wd,
i_mark->fsn_mark.group, i_mark->fsn_mark.i.inode);
BUG();
}
do_inotify_remove_from_idr(group, i_mark);
out:
if (found_i_mark)
fsnotify_put_mark(&found_i_mark->fsn_mark);
i_mark->wd = -1;
spin_unlock(idr_lock);
}
void inotify_ignored_and_remove_idr(struct fsnotify_mark *fsn_mark,
struct fsnotify_group *group)
{
struct inotify_inode_mark *i_mark;
struct fsnotify_event *ignored_event, *notify_event;
struct inotify_event_private_data *event_priv;
struct fsnotify_event_private_data *fsn_event_priv;
int ret;
ignored_event = fsnotify_create_event(NULL, FS_IN_IGNORED, NULL,
FSNOTIFY_EVENT_NONE, NULL, 0,
GFP_NOFS);
if (!ignored_event)
return;
i_mark = container_of(fsn_mark, struct inotify_inode_mark, fsn_mark);
event_priv = kmem_cache_alloc(event_priv_cachep, GFP_NOFS);
if (unlikely(!event_priv))
goto skip_send_ignore;
fsn_event_priv = &event_priv->fsnotify_event_priv_data;
fsn_event_priv->group = group;
event_priv->wd = i_mark->wd;
notify_event = fsnotify_add_notify_event(group, ignored_event, fsn_event_priv, NULL);
if (notify_event) {
if (IS_ERR(notify_event))
ret = PTR_ERR(notify_event);
else
fsnotify_put_event(notify_event);
inotify_free_event_priv(fsn_event_priv);
}
skip_send_ignore:
fsnotify_put_event(ignored_event);
inotify_remove_from_idr(group, i_mark);
atomic_dec(&group->inotify_data.user->inotify_watches);
}
static void inotify_free_mark(struct fsnotify_mark *fsn_mark)
{
struct inotify_inode_mark *i_mark;
i_mark = container_of(fsn_mark, struct inotify_inode_mark, fsn_mark);
kmem_cache_free(inotify_inode_mark_cachep, i_mark);
}
static int inotify_update_existing_watch(struct fsnotify_group *group,
struct inode *inode,
u32 arg)
{
struct fsnotify_mark *fsn_mark;
struct inotify_inode_mark *i_mark;
__u32 old_mask, new_mask;
__u32 mask;
int add = (arg & IN_MASK_ADD);
int ret;
mask = inotify_arg_to_mask(arg);
if (unlikely(!(mask & IN_ALL_EVENTS)))
return -EINVAL;
fsn_mark = fsnotify_find_inode_mark(group, inode);
if (!fsn_mark)
return -ENOENT;
i_mark = container_of(fsn_mark, struct inotify_inode_mark, fsn_mark);
spin_lock(&fsn_mark->lock);
old_mask = fsn_mark->mask;
if (add)
fsnotify_set_mark_mask_locked(fsn_mark, (fsn_mark->mask | mask));
else
fsnotify_set_mark_mask_locked(fsn_mark, mask);
new_mask = fsn_mark->mask;
spin_unlock(&fsn_mark->lock);
if (old_mask != new_mask) {
int dropped = (old_mask & ~new_mask);
int do_inode = (new_mask & ~inode->i_fsnotify_mask);
if (dropped || do_inode)
fsnotify_recalc_inode_mask(inode);
}
ret = i_mark->wd;
fsnotify_put_mark(fsn_mark);
return ret;
}
static int inotify_new_watch(struct fsnotify_group *group,
struct inode *inode,
u32 arg)
{
struct inotify_inode_mark *tmp_i_mark;
__u32 mask;
int ret;
struct idr *idr = &group->inotify_data.idr;
spinlock_t *idr_lock = &group->inotify_data.idr_lock;
mask = inotify_arg_to_mask(arg);
if (unlikely(!(mask & IN_ALL_EVENTS)))
return -EINVAL;
tmp_i_mark = kmem_cache_alloc(inotify_inode_mark_cachep, GFP_KERNEL);
if (unlikely(!tmp_i_mark))
return -ENOMEM;
fsnotify_init_mark(&tmp_i_mark->fsn_mark, inotify_free_mark);
tmp_i_mark->fsn_mark.mask = mask;
tmp_i_mark->wd = -1;
ret = -ENOSPC;
if (atomic_read(&group->inotify_data.user->inotify_watches) >= inotify_max_user_watches)
goto out_err;
ret = inotify_add_to_idr(idr, idr_lock, &group->inotify_data.last_wd,
tmp_i_mark);
if (ret)
goto out_err;
ret = fsnotify_add_mark(&tmp_i_mark->fsn_mark, group, inode, NULL, 0);
if (ret) {
inotify_remove_from_idr(group, tmp_i_mark);
goto out_err;
}
atomic_inc(&group->inotify_data.user->inotify_watches);
ret = tmp_i_mark->wd;
out_err:
fsnotify_put_mark(&tmp_i_mark->fsn_mark);
return ret;
}
static int inotify_update_watch(struct fsnotify_group *group, struct inode *inode, u32 arg)
{
int ret = 0;
retry:
ret = inotify_update_existing_watch(group, inode, arg);
if (ret == -ENOENT)
ret = inotify_new_watch(group, inode, arg);
if (ret == -EEXIST)
goto retry;
return ret;
}
static struct fsnotify_group *inotify_new_group(unsigned int max_events)
{
struct fsnotify_group *group;
group = fsnotify_alloc_group(&inotify_fsnotify_ops);
if (IS_ERR(group))
return group;
group->max_events = max_events;
spin_lock_init(&group->inotify_data.idr_lock);
idr_init(&group->inotify_data.idr);
group->inotify_data.last_wd = 0;
group->inotify_data.fa = NULL;
group->inotify_data.user = get_current_user();
if (atomic_inc_return(&group->inotify_data.user->inotify_devs) >
inotify_max_user_instances) {
fsnotify_put_group(group);
return ERR_PTR(-EMFILE);
}
return group;
}
SYSCALL_DEFINE1(inotify_init1, int, flags)
{
struct fsnotify_group *group;
int ret;
BUILD_BUG_ON(IN_CLOEXEC != O_CLOEXEC);
BUILD_BUG_ON(IN_NONBLOCK != O_NONBLOCK);
if (flags & ~(IN_CLOEXEC | IN_NONBLOCK))
return -EINVAL;
group = inotify_new_group(inotify_max_queued_events);
if (IS_ERR(group))
return PTR_ERR(group);
ret = anon_inode_getfd("inotify", &inotify_fops, group,
O_RDONLY | flags);
if (ret < 0)
fsnotify_put_group(group);
return ret;
}
SYSCALL_DEFINE0(inotify_init)
{
return sys_inotify_init1(0);
}
SYSCALL_DEFINE3(inotify_add_watch, int, fd, const char __user *, pathname,
u32, mask)
{
struct fsnotify_group *group;
struct inode *inode;
struct path path;
struct file *filp;
int ret, fput_needed;
unsigned flags = 0;
filp = fget_light(fd, &fput_needed);
if (unlikely(!filp))
return -EBADF;
if (unlikely(filp->f_op != &inotify_fops)) {
ret = -EINVAL;
goto fput_and_out;
}
if (!(mask & IN_DONT_FOLLOW))
flags |= LOOKUP_FOLLOW;
if (mask & IN_ONLYDIR)
flags |= LOOKUP_DIRECTORY;
ret = inotify_find_inode(pathname, &path, flags);
if (ret)
goto fput_and_out;
inode = path.dentry->d_inode;
group = filp->private_data;
ret = inotify_update_watch(group, inode, mask);
path_put(&path);
fput_and_out:
fput_light(filp, fput_needed);
return ret;
}
SYSCALL_DEFINE2(inotify_rm_watch, int, fd, __s32, wd)
{
struct fsnotify_group *group;
struct inotify_inode_mark *i_mark;
struct file *filp;
int ret = 0, fput_needed;
filp = fget_light(fd, &fput_needed);
if (unlikely(!filp))
return -EBADF;
ret = -EINVAL;
if (unlikely(filp->f_op != &inotify_fops))
goto out;
group = filp->private_data;
ret = -EINVAL;
i_mark = inotify_idr_find(group, wd);
if (unlikely(!i_mark))
goto out;
ret = 0;
fsnotify_destroy_mark(&i_mark->fsn_mark);
fsnotify_put_mark(&i_mark->fsn_mark);
out:
fput_light(filp, fput_needed);
return ret;
}
static int __init inotify_user_setup(void)
{
BUILD_BUG_ON(IN_ACCESS != FS_ACCESS);
BUILD_BUG_ON(IN_MODIFY != FS_MODIFY);
BUILD_BUG_ON(IN_ATTRIB != FS_ATTRIB);
BUILD_BUG_ON(IN_CLOSE_WRITE != FS_CLOSE_WRITE);
BUILD_BUG_ON(IN_CLOSE_NOWRITE != FS_CLOSE_NOWRITE);
BUILD_BUG_ON(IN_OPEN != FS_OPEN);
BUILD_BUG_ON(IN_MOVED_FROM != FS_MOVED_FROM);
BUILD_BUG_ON(IN_MOVED_TO != FS_MOVED_TO);
BUILD_BUG_ON(IN_CREATE != FS_CREATE);
BUILD_BUG_ON(IN_DELETE != FS_DELETE);
BUILD_BUG_ON(IN_DELETE_SELF != FS_DELETE_SELF);
BUILD_BUG_ON(IN_MOVE_SELF != FS_MOVE_SELF);
BUILD_BUG_ON(IN_UNMOUNT != FS_UNMOUNT);
BUILD_BUG_ON(IN_Q_OVERFLOW != FS_Q_OVERFLOW);
BUILD_BUG_ON(IN_IGNORED != FS_IN_IGNORED);
BUILD_BUG_ON(IN_EXCL_UNLINK != FS_EXCL_UNLINK);
BUILD_BUG_ON(IN_ISDIR != FS_ISDIR);
BUILD_BUG_ON(IN_ONESHOT != FS_IN_ONESHOT);
BUG_ON(hweight32(ALL_INOTIFY_BITS) != 21);
inotify_inode_mark_cachep = KMEM_CACHE(inotify_inode_mark, SLAB_PANIC);
event_priv_cachep = KMEM_CACHE(inotify_event_private_data, SLAB_PANIC);
inotify_max_queued_events = 16384;
inotify_max_user_instances = 128;
inotify_max_user_watches = 8192;
return 0;
}
module_init(inotify_user_setup);
| gpl-2.0 |
yubo/linux-2-6-32-220-23-1-el6 | sound/oss/ad1848.c | 612 | 75959 | /*
* sound/oss/ad1848.c
*
* The low level driver for the AD1848/CS4248 codec chip which
* is used for example in the MS Sound System.
*
* The CS4231 which is used in the GUS MAX and some other cards is
* upwards compatible with AD1848 and this driver is able to drive it.
*
* CS4231A and AD1845 are upward compatible with CS4231. However
* the new features of these chips are different.
*
* CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
* CS4232A is an improved version of CS4232.
*
*
*
* Copyright (C) by Hannu Savolainen 1993-1997
*
* OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
* Version 2 (June 1991). See the "COPYING" file distributed with this software
* for more info.
*
*
* Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
* general sleep/wakeup clean up.
* Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
* of irqs. Use dev_id.
* Christoph Hellwig : adapted to module_init/module_exit
* Aki Laukkanen : added power management support
* Arnaldo C. de Melo : added missing restore_flags in ad1848_resume
* Miguel Freitas : added ISA PnP support
* Alan Cox : Added CS4236->4239 identification
* Daniel T. Cobra : Alernate config/mixer for later chips
* Alan Cox : Merged chip idents and config code
*
* TODO
* APM save restore assist code on IBM thinkpad
*
* Status:
* Tested. Believed fully functional.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/isapnp.h>
#include <linux/pnp.h>
#include <linux/spinlock.h>
#define DEB(x)
#define DEB1(x)
#include "sound_config.h"
#include "ad1848.h"
#include "ad1848_mixer.h"
typedef struct
{
spinlock_t lock;
int base;
int irq;
int dma1, dma2;
int dual_dma; /* 1, when two DMA channels allocated */
int subtype;
unsigned char MCE_bit;
unsigned char saved_regs[64]; /* Includes extended register space */
int debug_flag;
int audio_flags;
int record_dev, playback_dev;
int xfer_count;
int audio_mode;
int open_mode;
int intr_active;
char *chip_name, *name;
int model;
#define MD_1848 1
#define MD_4231 2
#define MD_4231A 3
#define MD_1845 4
#define MD_4232 5
#define MD_C930 6
#define MD_IWAVE 7
#define MD_4235 8 /* Crystal Audio CS4235 */
#define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
#define MD_4236 10 /* 4236 and higher */
#define MD_42xB 11 /* CS 42xB */
#define MD_4239 12 /* CS4239 */
/* Mixer parameters */
int recmask;
int supported_devices, orig_devices;
int supported_rec_devices, orig_rec_devices;
int *levels;
short mixer_reroute[32];
int dev_no;
volatile unsigned long timer_ticks;
int timer_running;
int irq_ok;
mixer_ents *mix_devices;
int mixer_output_port;
} ad1848_info;
typedef struct ad1848_port_info
{
int open_mode;
int speed;
unsigned char speed_bits;
int channels;
int audio_format;
unsigned char format_bits;
}
ad1848_port_info;
static struct address_info cfg;
static int nr_ad1848_devs;
static int deskpro_xl;
static int deskpro_m;
static int soundpro;
static volatile signed char irq2dev[17] = {
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1
};
#ifndef EXCLUDE_TIMERS
static int timer_installed = -1;
#endif
static int loaded;
static int ad_format_mask[13 /*devc->model */ ] =
{
0,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE /* CS4235 */,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
};
static ad1848_info adev_info[MAX_AUDIO_DEV];
#define io_Index_Addr(d) ((d)->base)
#define io_Indexed_Data(d) ((d)->base+1)
#define io_Status(d) ((d)->base+2)
#define io_Polled_IO(d) ((d)->base+3)
static struct {
unsigned char flags;
#define CAP_F_TIMER 0x01
} capabilities [10 /*devc->model */ ] = {
{0}
,{0} /* MD_1848 */
,{CAP_F_TIMER} /* MD_4231 */
,{CAP_F_TIMER} /* MD_4231A */
,{CAP_F_TIMER} /* MD_1845 */
,{CAP_F_TIMER} /* MD_4232 */
,{0} /* MD_C930 */
,{CAP_F_TIMER} /* MD_IWAVE */
,{0} /* MD_4235 */
,{CAP_F_TIMER} /* MD_1845_SSCAPE */
};
#ifdef CONFIG_PNP
static int isapnp = 1;
static int isapnpjump;
static int reverse;
static int audio_activated;
#else
static int isapnp;
#endif
static int ad1848_open(int dev, int mode);
static void ad1848_close(int dev);
static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
static void ad1848_halt(int dev);
static void ad1848_halt_input(int dev);
static void ad1848_halt_output(int dev);
static void ad1848_trigger(int dev, int bits);
static irqreturn_t adintr(int irq, void *dev_id);
#ifndef EXCLUDE_TIMERS
static int ad1848_tmr_install(int dev);
static void ad1848_tmr_reprogram(int dev);
#endif
static int ad_read(ad1848_info * devc, int reg)
{
int x;
int timeout = 900000;
while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
timeout--;
if(reg < 32)
{
outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
x = inb(io_Indexed_Data(devc));
}
else
{
int xreg, xra;
xreg = (reg & 0xff) - 32;
xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
x = inb(io_Indexed_Data(devc));
}
return x;
}
static void ad_write(ad1848_info * devc, int reg, int data)
{
int timeout = 900000;
while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
timeout--;
if(reg < 32)
{
outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
}
else
{
int xreg, xra;
xreg = (reg & 0xff) - 32;
xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
}
}
static void wait_for_calibration(ad1848_info * devc)
{
int timeout = 0;
/*
* Wait until the auto calibration process has finished.
*
* 1) Wait until the chip becomes ready (reads don't return 0x80).
* 2) Wait until the ACI bit of I11 gets on and then off.
*/
timeout = 100000;
while (timeout > 0 && inb(devc->base) == 0x80)
timeout--;
if (inb(devc->base) & 0x80)
printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
timeout = 100;
while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
timeout--;
if (!(ad_read(devc, 11) & 0x20))
return;
timeout = 80000;
while (timeout > 0 && (ad_read(devc, 11) & 0x20))
timeout--;
if (ad_read(devc, 11) & 0x20)
if ((devc->model != MD_1845) && (devc->model != MD_1845_SSCAPE))
printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
}
static void ad_mute(ad1848_info * devc)
{
int i;
unsigned char prev;
/*
* Save old register settings and mute output channels
*/
for (i = 6; i < 8; i++)
{
prev = devc->saved_regs[i] = ad_read(devc, i);
}
}
static void ad_unmute(ad1848_info * devc)
{
}
static void ad_enter_MCE(ad1848_info * devc)
{
int timeout = 1000;
unsigned short prev;
while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
timeout--;
devc->MCE_bit = 0x40;
prev = inb(io_Index_Addr(devc));
if (prev & 0x40)
{
return;
}
outb((devc->MCE_bit), io_Index_Addr(devc));
}
static void ad_leave_MCE(ad1848_info * devc)
{
unsigned char prev, acal;
int timeout = 1000;
while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
timeout--;
acal = ad_read(devc, 9);
devc->MCE_bit = 0x00;
prev = inb(io_Index_Addr(devc));
outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
if ((prev & 0x40) == 0) /* Not in MCE mode */
{
return;
}
outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
if (acal & 0x08) /* Auto calibration is enabled */
wait_for_calibration(devc);
}
static int ad1848_set_recmask(ad1848_info * devc, int mask)
{
unsigned char recdev;
int i, n;
unsigned long flags;
mask &= devc->supported_rec_devices;
/* Rename the mixer bits if necessary */
for (i = 0; i < 32; i++)
{
if (devc->mixer_reroute[i] != i)
{
if (mask & (1 << i))
{
mask &= ~(1 << i);
mask |= (1 << devc->mixer_reroute[i]);
}
}
}
n = 0;
for (i = 0; i < 32; i++) /* Count selected device bits */
if (mask & (1 << i))
n++;
spin_lock_irqsave(&devc->lock,flags);
if (!soundpro) {
if (n == 0)
mask = SOUND_MASK_MIC;
else if (n != 1) { /* Too many devices selected */
mask &= ~devc->recmask; /* Filter out active settings */
n = 0;
for (i = 0; i < 32; i++) /* Count selected device bits */
if (mask & (1 << i))
n++;
if (n != 1)
mask = SOUND_MASK_MIC;
}
switch (mask) {
case SOUND_MASK_MIC:
recdev = 2;
break;
case SOUND_MASK_LINE:
case SOUND_MASK_LINE3:
recdev = 0;
break;
case SOUND_MASK_CD:
case SOUND_MASK_LINE1:
recdev = 1;
break;
case SOUND_MASK_IMIX:
recdev = 3;
break;
default:
mask = SOUND_MASK_MIC;
recdev = 2;
}
recdev <<= 6;
ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
} else { /* soundpro */
unsigned char val;
int set_rec_bit;
int j;
for (i = 0; i < 32; i++) { /* For each bit */
if ((devc->supported_rec_devices & (1 << i)) == 0)
continue; /* Device not supported */
for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
continue;
/*
* This is tricky:
* set_rec_bit becomes 1 if the corresponding bit in mask is set
* then it gets flipped if the polarity is inverse
*/
set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
val = ad_read(devc, devc->mix_devices[i][j].recreg);
val &= ~(1 << devc->mix_devices[i][j].recpos);
val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
ad_write(devc, devc->mix_devices[i][j].recreg, val);
}
}
}
spin_unlock_irqrestore(&devc->lock,flags);
/* Rename the mixer bits back if necessary */
for (i = 0; i < 32; i++)
{
if (devc->mixer_reroute[i] != i)
{
if (mask & (1 << devc->mixer_reroute[i]))
{
mask &= ~(1 << devc->mixer_reroute[i]);
mask |= (1 << i);
}
}
}
devc->recmask = mask;
return mask;
}
static void change_bits(ad1848_info * devc, unsigned char *regval,
unsigned char *muteval, int dev, int chn, int newval)
{
unsigned char mask;
int shift;
int mute;
int mutemask;
int set_mute_bit;
set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
newval = 100 - newval;
mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
shift = devc->mix_devices[dev][chn].bitpos;
if (devc->mix_devices[dev][chn].mutepos == 8)
{ /* if there is no mute bit */
mute = 0; /* No mute bit; do nothing special */
mutemask = ~0; /* No mute bit; do nothing special */
}
else
{
mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
}
newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
*regval &= ~(mask << shift); /* Clear bits */
*regval |= (newval & mask) << shift; /* Set new value */
*muteval &= mutemask;
*muteval |= mute;
}
static int ad1848_mixer_get(ad1848_info * devc, int dev)
{
if (!((1 << dev) & devc->supported_devices))
return -EINVAL;
dev = devc->mixer_reroute[dev];
return devc->levels[dev];
}
static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
{
int regoffs, muteregoffs;
unsigned char val, muteval;
unsigned long flags;
regoffs = devc->mix_devices[dev][channel].regno;
muteregoffs = devc->mix_devices[dev][channel].mutereg;
val = ad_read(devc, regoffs);
if (muteregoffs != regoffs) {
muteval = ad_read(devc, muteregoffs);
change_bits(devc, &val, &muteval, dev, channel, value);
}
else
change_bits(devc, &val, &val, dev, channel, value);
spin_lock_irqsave(&devc->lock,flags);
ad_write(devc, regoffs, val);
devc->saved_regs[regoffs] = val;
if (muteregoffs != regoffs) {
ad_write(devc, muteregoffs, muteval);
devc->saved_regs[muteregoffs] = muteval;
}
spin_unlock_irqrestore(&devc->lock,flags);
}
static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
{
int left = value & 0x000000ff;
int right = (value & 0x0000ff00) >> 8;
int retvol;
if (dev > 31)
return -EINVAL;
if (!(devc->supported_devices & (1 << dev)))
return -EINVAL;
dev = devc->mixer_reroute[dev];
if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
return -EINVAL;
if (left > 100)
left = 100;
if (right > 100)
right = 100;
if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
right = left;
retvol = left | (right << 8);
/* Scale volumes */
left = mix_cvt[left];
right = mix_cvt[right];
devc->levels[dev] = retvol;
/*
* Set the left channel
*/
ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
/*
* Set the right channel
*/
if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
goto out;
ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
out:
return retvol;
}
static void ad1848_mixer_reset(ad1848_info * devc)
{
int i;
char name[32];
unsigned long flags;
devc->mix_devices = &(ad1848_mix_devices[0]);
sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
for (i = 0; i < 32; i++)
devc->mixer_reroute[i] = i;
devc->supported_rec_devices = MODE1_REC_DEVICES;
switch (devc->model)
{
case MD_4231:
case MD_4231A:
case MD_1845:
case MD_1845_SSCAPE:
devc->supported_devices = MODE2_MIXER_DEVICES;
break;
case MD_C930:
devc->supported_devices = C930_MIXER_DEVICES;
devc->mix_devices = &(c930_mix_devices[0]);
break;
case MD_IWAVE:
devc->supported_devices = MODE3_MIXER_DEVICES;
devc->mix_devices = &(iwave_mix_devices[0]);
break;
case MD_42xB:
case MD_4239:
devc->mix_devices = &(cs42xb_mix_devices[0]);
devc->supported_devices = MODE3_MIXER_DEVICES;
break;
case MD_4232:
case MD_4235:
case MD_4236:
devc->supported_devices = MODE3_MIXER_DEVICES;
break;
case MD_1848:
if (soundpro) {
devc->supported_devices = SPRO_MIXER_DEVICES;
devc->supported_rec_devices = SPRO_REC_DEVICES;
devc->mix_devices = &(spro_mix_devices[0]);
break;
}
default:
devc->supported_devices = MODE1_MIXER_DEVICES;
}
devc->orig_devices = devc->supported_devices;
devc->orig_rec_devices = devc->supported_rec_devices;
devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
{
if (devc->supported_devices & (1 << i))
ad1848_mixer_set(devc, i, devc->levels[i]);
}
ad1848_set_recmask(devc, SOUND_MASK_MIC);
devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
spin_lock_irqsave(&devc->lock,flags);
if (!soundpro) {
if (devc->mixer_output_port & AUDIO_SPEAKER)
ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
else
ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
} else {
/*
* From the "wouldn't it be nice if the mixer API had (better)
* support for custom stuff" category
*/
/* Enable surround mode and SB16 mixer */
ad_write(devc, 16, 0x60);
}
spin_unlock_irqrestore(&devc->lock,flags);
}
static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
{
ad1848_info *devc = mixer_devs[dev]->devc;
int val;
if (cmd == SOUND_MIXER_PRIVATE1)
{
if (get_user(val, (int __user *)arg))
return -EFAULT;
if (val != 0xffff)
{
unsigned long flags;
val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
devc->mixer_output_port = val;
val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
devc->mixer_output_port = val;
spin_lock_irqsave(&devc->lock,flags);
if (val & AUDIO_SPEAKER)
ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
else
ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
spin_unlock_irqrestore(&devc->lock,flags);
}
val = devc->mixer_output_port;
return put_user(val, (int __user *)arg);
}
if (cmd == SOUND_MIXER_PRIVATE2)
{
if (get_user(val, (int __user *)arg))
return -EFAULT;
return(ad1848_control(AD1848_MIXER_REROUTE, val));
}
if (((cmd >> 8) & 0xff) == 'M')
{
if (_SIOC_DIR(cmd) & _SIOC_WRITE)
{
switch (cmd & 0xff)
{
case SOUND_MIXER_RECSRC:
if (get_user(val, (int __user *)arg))
return -EFAULT;
val = ad1848_set_recmask(devc, val);
break;
default:
if (get_user(val, (int __user *)arg))
return -EFAULT;
val = ad1848_mixer_set(devc, cmd & 0xff, val);
break;
}
return put_user(val, (int __user *)arg);
}
else
{
switch (cmd & 0xff)
{
/*
* Return parameters
*/
case SOUND_MIXER_RECSRC:
val = devc->recmask;
break;
case SOUND_MIXER_DEVMASK:
val = devc->supported_devices;
break;
case SOUND_MIXER_STEREODEVS:
val = devc->supported_devices;
if (devc->model != MD_C930)
val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
break;
case SOUND_MIXER_RECMASK:
val = devc->supported_rec_devices;
break;
case SOUND_MIXER_CAPS:
val=SOUND_CAP_EXCL_INPUT;
break;
default:
val = ad1848_mixer_get(devc, cmd & 0xff);
break;
}
return put_user(val, (int __user *)arg);
}
}
else
return -EINVAL;
}
static int ad1848_set_speed(int dev, int arg)
{
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
/*
* The sampling speed is encoded in the least significant nibble of I8. The
* LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
* three bits select the divisor (indirectly):
*
* The available speeds are in the following table. Keep the speeds in
* the increasing order.
*/
typedef struct
{
int speed;
unsigned char bits;
}
speed_struct;
static speed_struct speed_table[] =
{
{5510, (0 << 1) | 1},
{5510, (0 << 1) | 1},
{6620, (7 << 1) | 1},
{8000, (0 << 1) | 0},
{9600, (7 << 1) | 0},
{11025, (1 << 1) | 1},
{16000, (1 << 1) | 0},
{18900, (2 << 1) | 1},
{22050, (3 << 1) | 1},
{27420, (2 << 1) | 0},
{32000, (3 << 1) | 0},
{33075, (6 << 1) | 1},
{37800, (4 << 1) | 1},
{44100, (5 << 1) | 1},
{48000, (6 << 1) | 0}
};
int i, n, selected = -1;
n = sizeof(speed_table) / sizeof(speed_struct);
if (arg <= 0)
return portc->speed;
if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
{
if (arg < 4000)
arg = 4000;
if (arg > 50000)
arg = 50000;
portc->speed = arg;
portc->speed_bits = speed_table[3].bits;
return portc->speed;
}
if (arg < speed_table[0].speed)
selected = 0;
if (arg > speed_table[n - 1].speed)
selected = n - 1;
for (i = 1 /*really */ ; selected == -1 && i < n; i++)
{
if (speed_table[i].speed == arg)
selected = i;
else if (speed_table[i].speed > arg)
{
int diff1, diff2;
diff1 = arg - speed_table[i - 1].speed;
diff2 = speed_table[i].speed - arg;
if (diff1 < diff2)
selected = i - 1;
else
selected = i;
}
}
if (selected == -1)
{
printk(KERN_WARNING "ad1848: Can't find speed???\n");
selected = 3;
}
portc->speed = speed_table[selected].speed;
portc->speed_bits = speed_table[selected].bits;
return portc->speed;
}
static short ad1848_set_channels(int dev, short arg)
{
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
if (arg != 1 && arg != 2)
return portc->channels;
portc->channels = arg;
return arg;
}
static unsigned int ad1848_set_bits(int dev, unsigned int arg)
{
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
static struct format_tbl
{
int format;
unsigned char bits;
}
format2bits[] =
{
{
0, 0
}
,
{
AFMT_MU_LAW, 1
}
,
{
AFMT_A_LAW, 3
}
,
{
AFMT_IMA_ADPCM, 5
}
,
{
AFMT_U8, 0
}
,
{
AFMT_S16_LE, 2
}
,
{
AFMT_S16_BE, 6
}
,
{
AFMT_S8, 0
}
,
{
AFMT_U16_LE, 0
}
,
{
AFMT_U16_BE, 0
}
};
int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
if (arg == 0)
return portc->audio_format;
if (!(arg & ad_format_mask[devc->model]))
arg = AFMT_U8;
portc->audio_format = arg;
for (i = 0; i < n; i++)
if (format2bits[i].format == arg)
{
if ((portc->format_bits = format2bits[i].bits) == 0)
return portc->audio_format = AFMT_U8; /* Was not supported */
return arg;
}
/* Still hanging here. Something must be terribly wrong */
portc->format_bits = 0;
return portc->audio_format = AFMT_U8;
}
static struct audio_driver ad1848_audio_driver =
{
.owner = THIS_MODULE,
.open = ad1848_open,
.close = ad1848_close,
.output_block = ad1848_output_block,
.start_input = ad1848_start_input,
.prepare_for_input = ad1848_prepare_for_input,
.prepare_for_output = ad1848_prepare_for_output,
.halt_io = ad1848_halt,
.halt_input = ad1848_halt_input,
.halt_output = ad1848_halt_output,
.trigger = ad1848_trigger,
.set_speed = ad1848_set_speed,
.set_bits = ad1848_set_bits,
.set_channels = ad1848_set_channels
};
static struct mixer_operations ad1848_mixer_operations =
{
.owner = THIS_MODULE,
.id = "SOUNDPORT",
.name = "AD1848/CS4248/CS4231",
.ioctl = ad1848_mixer_ioctl
};
static int ad1848_open(int dev, int mode)
{
ad1848_info *devc;
ad1848_port_info *portc;
unsigned long flags;
if (dev < 0 || dev >= num_audiodevs)
return -ENXIO;
devc = (ad1848_info *) audio_devs[dev]->devc;
portc = (ad1848_port_info *) audio_devs[dev]->portc;
/* here we don't have to protect against intr */
spin_lock(&devc->lock);
if (portc->open_mode || (devc->open_mode & mode))
{
spin_unlock(&devc->lock);
return -EBUSY;
}
devc->dual_dma = 0;
if (audio_devs[dev]->flags & DMA_DUPLEX)
{
devc->dual_dma = 1;
}
devc->intr_active = 0;
devc->audio_mode = 0;
devc->open_mode |= mode;
portc->open_mode = mode;
spin_unlock(&devc->lock);
ad1848_trigger(dev, 0);
if (mode & OPEN_READ)
devc->record_dev = dev;
if (mode & OPEN_WRITE)
devc->playback_dev = dev;
/*
* Mute output until the playback really starts. This decreases clicking (hope so).
*/
spin_lock_irqsave(&devc->lock,flags);
ad_mute(devc);
spin_unlock_irqrestore(&devc->lock,flags);
return 0;
}
static void ad1848_close(int dev)
{
unsigned long flags;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
DEB(printk("ad1848_close(void)\n"));
devc->intr_active = 0;
ad1848_halt(dev);
spin_lock_irqsave(&devc->lock,flags);
devc->audio_mode = 0;
devc->open_mode &= ~portc->open_mode;
portc->open_mode = 0;
ad_unmute(devc);
spin_unlock_irqrestore(&devc->lock,flags);
}
static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
{
unsigned long flags, cnt;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
cnt = count;
if (portc->audio_format == AFMT_IMA_ADPCM)
{
cnt /= 4;
}
else
{
if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
cnt >>= 1;
}
if (portc->channels > 1)
cnt >>= 1;
cnt--;
if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
intrflag &&
cnt == devc->xfer_count)
{
devc->audio_mode |= PCM_ENABLE_OUTPUT;
devc->intr_active = 1;
return; /*
* Auto DMA mode on. No need to react
*/
}
spin_lock_irqsave(&devc->lock,flags);
ad_write(devc, 15, (unsigned char) (cnt & 0xff));
ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
devc->xfer_count = cnt;
devc->audio_mode |= PCM_ENABLE_OUTPUT;
devc->intr_active = 1;
spin_unlock_irqrestore(&devc->lock,flags);
}
static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
{
unsigned long flags, cnt;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
cnt = count;
if (portc->audio_format == AFMT_IMA_ADPCM)
{
cnt /= 4;
}
else
{
if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
cnt >>= 1;
}
if (portc->channels > 1)
cnt >>= 1;
cnt--;
if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
intrflag &&
cnt == devc->xfer_count)
{
devc->audio_mode |= PCM_ENABLE_INPUT;
devc->intr_active = 1;
return; /*
* Auto DMA mode on. No need to react
*/
}
spin_lock_irqsave(&devc->lock,flags);
if (devc->model == MD_1848)
{
ad_write(devc, 15, (unsigned char) (cnt & 0xff));
ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
}
else
{
ad_write(devc, 31, (unsigned char) (cnt & 0xff));
ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
}
ad_unmute(devc);
devc->xfer_count = cnt;
devc->audio_mode |= PCM_ENABLE_INPUT;
devc->intr_active = 1;
spin_unlock_irqrestore(&devc->lock,flags);
}
static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
{
int timeout;
unsigned char fs, old_fs, tmp = 0;
unsigned long flags;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
ad_mute(devc);
spin_lock_irqsave(&devc->lock,flags);
fs = portc->speed_bits | (portc->format_bits << 5);
if (portc->channels > 1)
fs |= 0x10;
ad_enter_MCE(devc); /* Enables changes to the format select reg */
if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
{
fs &= 0xf0; /* Mask off the rate select bits */
ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
}
old_fs = ad_read(devc, 8);
if (devc->model == MD_4232 || devc->model >= MD_4236)
{
tmp = ad_read(devc, 16);
ad_write(devc, 16, tmp | 0x30);
}
if (devc->model == MD_IWAVE)
ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
ad_write(devc, 8, fs);
/*
* Write to I8 starts resynchronization. Wait until it completes.
*/
timeout = 0;
while (timeout < 100 && inb(devc->base) != 0x80)
timeout++;
timeout = 0;
while (timeout < 10000 && inb(devc->base) == 0x80)
timeout++;
if (devc->model >= MD_4232)
ad_write(devc, 16, tmp & ~0x30);
ad_leave_MCE(devc); /*
* Starts the calibration process.
*/
spin_unlock_irqrestore(&devc->lock,flags);
devc->xfer_count = 0;
#ifndef EXCLUDE_TIMERS
if (dev == timer_installed && devc->timer_running)
if ((fs & 0x01) != (old_fs & 0x01))
{
ad1848_tmr_reprogram(dev);
}
#endif
ad1848_halt_output(dev);
return 0;
}
static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
{
int timeout;
unsigned char fs, old_fs, tmp = 0;
unsigned long flags;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
if (devc->audio_mode)
return 0;
spin_lock_irqsave(&devc->lock,flags);
fs = portc->speed_bits | (portc->format_bits << 5);
if (portc->channels > 1)
fs |= 0x10;
ad_enter_MCE(devc); /* Enables changes to the format select reg */
if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
{
fs &= 0xf0; /* Mask off the rate select bits */
ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
}
if (devc->model == MD_4232)
{
tmp = ad_read(devc, 16);
ad_write(devc, 16, tmp | 0x30);
}
if (devc->model == MD_IWAVE)
ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
/*
* If mode >= 2 (CS4231), set I28. It's the capture format register.
*/
if (devc->model != MD_1848)
{
old_fs = ad_read(devc, 28);
ad_write(devc, 28, fs);
/*
* Write to I28 starts resynchronization. Wait until it completes.
*/
timeout = 0;
while (timeout < 100 && inb(devc->base) != 0x80)
timeout++;
timeout = 0;
while (timeout < 10000 && inb(devc->base) == 0x80)
timeout++;
if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
{
/*
* CS4231 compatible devices don't have separate sampling rate selection
* register for recording an playback. The I8 register is shared so we have to
* set the speed encoding bits of it too.
*/
unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
ad_write(devc, 8, tmp);
/*
* Write to I8 starts resynchronization. Wait until it completes.
*/
timeout = 0;
while (timeout < 100 && inb(devc->base) != 0x80)
timeout++;
timeout = 0;
while (timeout < 10000 && inb(devc->base) == 0x80)
timeout++;
}
}
else
{ /* For AD1848 set I8. */
old_fs = ad_read(devc, 8);
ad_write(devc, 8, fs);
/*
* Write to I8 starts resynchronization. Wait until it completes.
*/
timeout = 0;
while (timeout < 100 && inb(devc->base) != 0x80)
timeout++;
timeout = 0;
while (timeout < 10000 && inb(devc->base) == 0x80)
timeout++;
}
if (devc->model == MD_4232)
ad_write(devc, 16, tmp & ~0x30);
ad_leave_MCE(devc); /*
* Starts the calibration process.
*/
spin_unlock_irqrestore(&devc->lock,flags);
devc->xfer_count = 0;
#ifndef EXCLUDE_TIMERS
if (dev == timer_installed && devc->timer_running)
{
if ((fs & 0x01) != (old_fs & 0x01))
{
ad1848_tmr_reprogram(dev);
}
}
#endif
ad1848_halt_input(dev);
return 0;
}
static void ad1848_halt(int dev)
{
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
unsigned char bits = ad_read(devc, 9);
if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
ad1848_halt_output(dev);
if (bits & 0x02 && (portc->open_mode & OPEN_READ))
ad1848_halt_input(dev);
devc->audio_mode = 0;
}
static void ad1848_halt_input(int dev)
{
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
unsigned long flags;
if (!(ad_read(devc, 9) & 0x02))
return; /* Capture not enabled */
spin_lock_irqsave(&devc->lock,flags);
ad_mute(devc);
{
int tmout;
if(!isa_dma_bridge_buggy)
disable_dma(audio_devs[dev]->dmap_in->dma);
for (tmout = 0; tmout < 100000; tmout++)
if (ad_read(devc, 11) & 0x10)
break;
ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
if(!isa_dma_bridge_buggy)
enable_dma(audio_devs[dev]->dmap_in->dma);
devc->audio_mode &= ~PCM_ENABLE_INPUT;
}
outb(0, io_Status(devc)); /* Clear interrupt status */
outb(0, io_Status(devc)); /* Clear interrupt status */
devc->audio_mode &= ~PCM_ENABLE_INPUT;
spin_unlock_irqrestore(&devc->lock,flags);
}
static void ad1848_halt_output(int dev)
{
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
unsigned long flags;
if (!(ad_read(devc, 9) & 0x01))
return; /* Playback not enabled */
spin_lock_irqsave(&devc->lock,flags);
ad_mute(devc);
{
int tmout;
if(!isa_dma_bridge_buggy)
disable_dma(audio_devs[dev]->dmap_out->dma);
for (tmout = 0; tmout < 100000; tmout++)
if (ad_read(devc, 11) & 0x10)
break;
ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
if(!isa_dma_bridge_buggy)
enable_dma(audio_devs[dev]->dmap_out->dma);
devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
}
outb((0), io_Status(devc)); /* Clear interrupt status */
outb((0), io_Status(devc)); /* Clear interrupt status */
devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
spin_unlock_irqrestore(&devc->lock,flags);
}
static void ad1848_trigger(int dev, int state)
{
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
unsigned long flags;
unsigned char tmp, old;
spin_lock_irqsave(&devc->lock,flags);
state &= devc->audio_mode;
tmp = old = ad_read(devc, 9);
if (portc->open_mode & OPEN_READ)
{
if (state & PCM_ENABLE_INPUT)
tmp |= 0x02;
else
tmp &= ~0x02;
}
if (portc->open_mode & OPEN_WRITE)
{
if (state & PCM_ENABLE_OUTPUT)
tmp |= 0x01;
else
tmp &= ~0x01;
}
/* ad_mute(devc); */
if (tmp != old)
{
ad_write(devc, 9, tmp);
ad_unmute(devc);
}
spin_unlock_irqrestore(&devc->lock,flags);
}
static void ad1848_init_hw(ad1848_info * devc)
{
int i;
int *init_values;
/*
* Initial values for the indirect registers of CS4248/AD1848.
*/
static int init_values_a[] =
{
0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
/* Positions 16 to 31 just for CS4231/2 and ad1845 */
0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static int init_values_b[] =
{
/*
Values for the newer chips
Some of the register initialization values were changed. In
order to get rid of the click that preceded PCM playback,
calibration was disabled on the 10th byte. On that same byte,
dual DMA was enabled; on the 11th byte, ADC dithering was
enabled, since that is theoretically desirable; on the 13th
byte, Mode 3 was selected, to enable access to extended
registers.
*/
0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
/*
* Select initialisation data
*/
init_values = init_values_a;
if(devc->model >= MD_4236)
init_values = init_values_b;
for (i = 0; i < 16; i++)
ad_write(devc, i, init_values[i]);
ad_mute(devc); /* Initialize some variables */
ad_unmute(devc); /* Leave it unmuted now */
if (devc->model > MD_1848)
{
if (devc->model == MD_1845_SSCAPE)
ad_write(devc, 12, ad_read(devc, 12) | 0x50);
else
ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
if (devc->model == MD_IWAVE)
ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
if (devc->model != MD_1845_SSCAPE)
for (i = 16; i < 32; i++)
ad_write(devc, i, init_values[i]);
if (devc->model == MD_IWAVE)
ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
}
if (devc->model > MD_1848)
{
if (devc->audio_flags & DMA_DUPLEX)
ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
else
ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
if (devc->model == MD_IWAVE)
{ /* Some magic Interwave specific initialization */
ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
ad_write(devc, 17, 0xc2); /* Alternate feature enable */
}
}
else
{
devc->audio_flags &= ~DMA_DUPLEX;
ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
if (soundpro)
ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
}
outb((0), io_Status(devc)); /* Clear pending interrupts */
/*
* Toggle the MCE bit. It completes the initialization phase.
*/
ad_enter_MCE(devc); /* In case the bit was off */
ad_leave_MCE(devc);
ad1848_mixer_reset(devc);
}
int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
{
unsigned char tmp;
ad1848_info *devc = &adev_info[nr_ad1848_devs];
unsigned char tmp1 = 0xff, tmp2 = 0xff;
int optiC930 = 0; /* OPTi 82C930 flag */
int interwave = 0;
int ad1847_flag = 0;
int cs4248_flag = 0;
int sscape_flag = 0;
int io_base = ports->start;
int i;
DDB(printk("ad1848_detect(%x)\n", io_base));
if (ad_flags)
{
if (*ad_flags == 0x12345678)
{
interwave = 1;
*ad_flags = 0;
}
if (*ad_flags == 0x87654321)
{
sscape_flag = 1;
*ad_flags = 0;
}
if (*ad_flags == 0x12345677)
{
cs4248_flag = 1;
*ad_flags = 0;
}
}
if (nr_ad1848_devs >= MAX_AUDIO_DEV)
{
printk(KERN_ERR "ad1848 - Too many audio devices\n");
return 0;
}
spin_lock_init(&devc->lock);
devc->base = io_base;
devc->irq_ok = 0;
devc->timer_running = 0;
devc->MCE_bit = 0x40;
devc->irq = 0;
devc->open_mode = 0;
devc->chip_name = devc->name = "AD1848";
devc->model = MD_1848; /* AD1848 or CS4248 */
devc->levels = NULL;
devc->debug_flag = 0;
/*
* Check that the I/O address is in use.
*
* The bit 0x80 of the base I/O port is known to be 0 after the
* chip has performed its power on initialization. Just assume
* this has happened before the OS is starting.
*
* If the I/O address is unused, it typically returns 0xff.
*/
if (inb(devc->base) == 0xff)
{
DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
}
/*
* Wait for the device to stop initialization
*/
DDB(printk("ad1848_detect() - step 0\n"));
for (i = 0; i < 10000000; i++)
{
unsigned char x = inb(devc->base);
if (x == 0xff || !(x & 0x80))
break;
}
DDB(printk("ad1848_detect() - step A\n"));
if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
ad_leave_MCE(devc);
if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
{
DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
return 0;
}
/*
* Test if it's possible to change contents of the indirect registers.
* Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
* so try to avoid using it.
*/
DDB(printk("ad1848_detect() - step B\n"));
ad_write(devc, 0, 0xaa);
ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
{
if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
ad1847_flag = 1;
else
{
DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
return 0;
}
}
DDB(printk("ad1848_detect() - step C\n"));
ad_write(devc, 0, 0x45);
ad_write(devc, 1, 0xaa);
if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
{
if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
ad1847_flag = 1;
else
{
DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
return 0;
}
}
/*
* The indirect register I12 has some read only bits. Let's
* try to change them.
*/
DDB(printk("ad1848_detect() - step D\n"));
tmp = ad_read(devc, 12);
ad_write(devc, 12, (~tmp) & 0x0f);
if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
{
DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
return 0;
}
/*
* NOTE! Last 4 bits of the reg I12 tell the chip revision.
* 0x01=RevB and 0x0A=RevC.
*/
/*
* The original AD1848/CS4248 has just 15 indirect registers. This means
* that I0 and I16 should return the same value (etc.).
* However this doesn't work with CS4248. Actually it seems to be impossible
* to detect if the chip is a CS4231 or CS4248.
* Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
* with CS4231.
*/
/*
* OPTi 82C930 has mode2 control bit in another place. This test will fail
* with it. Accept this situation as a possible indication of this chip.
*/
DDB(printk("ad1848_detect() - step F\n"));
ad_write(devc, 12, 0); /* Mode2=disabled */
for (i = 0; i < 16; i++)
{
if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
{
DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
if (!ad1847_flag)
optiC930 = 1;
break;
}
}
/*
* Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
* The bit 0x80 is always 1 in CS4248 and CS4231.
*/
DDB(printk("ad1848_detect() - step G\n"));
if (ad_flags && *ad_flags == 400)
*ad_flags = 0;
else
ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
if (ad_flags)
*ad_flags = 0;
tmp1 = ad_read(devc, 12);
if (tmp1 & 0x80)
{
if (ad_flags)
*ad_flags |= AD_F_CS4248;
devc->chip_name = "CS4248"; /* Our best knowledge just now */
}
if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
{
/*
* CS4231 detected - is it?
*
* Verify that setting I0 doesn't change I16.
*/
DDB(printk("ad1848_detect() - step H\n"));
ad_write(devc, 16, 0); /* Set I16 to known value */
ad_write(devc, 0, 0x45);
if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
{
ad_write(devc, 0, 0xaa);
if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
{
DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
return 0;
}
/*
* Verify that some bits of I25 are read only.
*/
DDB(printk("ad1848_detect() - step I\n"));
tmp1 = ad_read(devc, 25); /* Original bits */
ad_write(devc, 25, ~tmp1); /* Invert all bits */
if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
{
int id;
/*
* It's at least CS4231
*/
devc->chip_name = "CS4231";
devc->model = MD_4231;
/*
* It could be an AD1845 or CS4231A as well.
* CS4231 and AD1845 report the same revision info in I25
* while the CS4231A reports different.
*/
id = ad_read(devc, 25);
if ((id & 0xe7) == 0x80) /* Device busy??? */
id = ad_read(devc, 25);
if ((id & 0xe7) == 0x80) /* Device still busy??? */
id = ad_read(devc, 25);
DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
if ((id & 0xe7) == 0x80) {
/*
* It must be a CS4231 or AD1845. The register I23 of
* CS4231 is undefined and it appears to be read only.
* AD1845 uses I23 for setting sample rate. Assume
* the chip is AD1845 if I23 is changeable.
*/
unsigned char tmp = ad_read(devc, 23);
ad_write(devc, 23, ~tmp);
if (interwave)
{
devc->model = MD_IWAVE;
devc->chip_name = "IWave";
}
else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
{
devc->chip_name = "AD1845";
devc->model = MD_1845;
}
else if (cs4248_flag)
{
if (ad_flags)
*ad_flags |= AD_F_CS4248;
devc->chip_name = "CS4248";
devc->model = MD_1848;
ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
}
ad_write(devc, 23, tmp); /* Restore */
}
else
{
switch (id & 0x1f) {
case 3: /* CS4236/CS4235/CS42xB/CS4239 */
{
int xid;
ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
ad_write(devc, 23, 0x9c); /* select extended register 25 */
xid = inb(io_Indexed_Data(devc));
ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
switch (xid & 0x1f)
{
case 0x00:
devc->chip_name = "CS4237B(B)";
devc->model = MD_42xB;
break;
case 0x08:
/* Seems to be a 4238 ?? */
devc->chip_name = "CS4238";
devc->model = MD_42xB;
break;
case 0x09:
devc->chip_name = "CS4238B";
devc->model = MD_42xB;
break;
case 0x0b:
devc->chip_name = "CS4236B";
devc->model = MD_4236;
break;
case 0x10:
devc->chip_name = "CS4237B";
devc->model = MD_42xB;
break;
case 0x1d:
devc->chip_name = "CS4235";
devc->model = MD_4235;
break;
case 0x1e:
devc->chip_name = "CS4239";
devc->model = MD_4239;
break;
default:
printk("Chip ident is %X.\n", xid&0x1F);
devc->chip_name = "CS42xx";
devc->model = MD_4232;
break;
}
}
break;
case 2: /* CS4232/CS4232A */
devc->chip_name = "CS4232";
devc->model = MD_4232;
break;
case 0:
if ((id & 0xe0) == 0xa0)
{
devc->chip_name = "CS4231A";
devc->model = MD_4231A;
}
else
{
devc->chip_name = "CS4321";
devc->model = MD_4231;
}
break;
default: /* maybe */
DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
if (optiC930)
{
devc->chip_name = "82C930";
devc->model = MD_C930;
}
else
{
devc->chip_name = "CS4231";
devc->model = MD_4231;
}
}
}
}
ad_write(devc, 25, tmp1); /* Restore bits */
DDB(printk("ad1848_detect() - step K\n"));
}
} else if (tmp1 == 0x0a) {
/*
* Is it perhaps a SoundPro CMI8330?
* If so, then we should be able to change indirect registers
* greater than I15 after activating MODE2, even though reading
* back I12 does not show it.
*/
/*
* Let's try comparing register values
*/
for (i = 0; i < 16; i++) {
if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
soundpro = 1;
devc->chip_name = "SoundPro CMI 8330";
break;
}
}
}
DDB(printk("ad1848_detect() - step L\n"));
if (ad_flags)
{
if (devc->model != MD_1848)
*ad_flags |= AD_F_CS4231;
}
DDB(printk("ad1848_detect() - Detected OK\n"));
if (devc->model == MD_1848 && ad1847_flag)
devc->chip_name = "AD1847";
if (sscape_flag == 1)
devc->model = MD_1845_SSCAPE;
return 1;
}
int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
int dma_capture, int share_dma, int *osp, struct module *owner)
{
/*
* NOTE! If irq < 0, there is another driver which has allocated the IRQ
* so that this driver doesn't need to allocate/deallocate it.
* The actually used IRQ is ABS(irq).
*/
int my_dev;
char dev_name[100];
int e;
ad1848_info *devc = &adev_info[nr_ad1848_devs];
ad1848_port_info *portc = NULL;
devc->irq = (irq > 0) ? irq : 0;
devc->open_mode = 0;
devc->timer_ticks = 0;
devc->dma1 = dma_playback;
devc->dma2 = dma_capture;
devc->subtype = cfg.card_subtype;
devc->audio_flags = DMA_AUTOMODE;
devc->playback_dev = devc->record_dev = 0;
if (name != NULL)
devc->name = name;
if (name != NULL && name[0] != 0)
sprintf(dev_name,
"%s (%s)", name, devc->chip_name);
else
sprintf(dev_name,
"Generic audio codec (%s)", devc->chip_name);
rename_region(ports, devc->name);
conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
if (devc->model == MD_1848 || devc->model == MD_C930)
devc->audio_flags |= DMA_HARDSTOP;
if (devc->model > MD_1848)
{
if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
devc->audio_flags &= ~DMA_DUPLEX;
else
devc->audio_flags |= DMA_DUPLEX;
}
portc = kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
if(portc==NULL) {
release_region(devc->base, 4);
return -1;
}
if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
dev_name,
&ad1848_audio_driver,
sizeof(struct audio_driver),
devc->audio_flags,
ad_format_mask[devc->model],
devc,
dma_playback,
dma_capture)) < 0)
{
release_region(devc->base, 4);
kfree(portc);
return -1;
}
audio_devs[my_dev]->portc = portc;
audio_devs[my_dev]->mixer_dev = -1;
if (owner)
audio_devs[my_dev]->d->owner = owner;
memset((char *) portc, 0, sizeof(*portc));
nr_ad1848_devs++;
ad1848_init_hw(devc);
if (irq > 0)
{
devc->dev_no = my_dev;
if (request_irq(devc->irq, adintr, 0, devc->name,
(void *)(long)my_dev) < 0)
{
printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
/* Don't free it either then.. */
devc->irq = 0;
}
if (capabilities[devc->model].flags & CAP_F_TIMER)
{
#ifndef CONFIG_SMP
int x;
unsigned char tmp = ad_read(devc, 16);
#endif
devc->timer_ticks = 0;
ad_write(devc, 21, 0x00); /* Timer MSB */
ad_write(devc, 20, 0x10); /* Timer LSB */
#ifndef CONFIG_SMP
ad_write(devc, 16, tmp | 0x40); /* Enable timer */
for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
if (devc->timer_ticks == 0)
printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
else
{
DDB(printk("Interrupt test OK\n"));
devc->irq_ok = 1;
}
#else
devc->irq_ok = 1;
#endif
}
else
devc->irq_ok = 1; /* Couldn't test. assume it's OK */
} else if (irq < 0)
irq2dev[-irq] = devc->dev_no = my_dev;
#ifndef EXCLUDE_TIMERS
if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
devc->irq_ok)
ad1848_tmr_install(my_dev);
#endif
if (!share_dma)
{
if (sound_alloc_dma(dma_playback, devc->name))
printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
if (dma_capture != dma_playback)
if (sound_alloc_dma(dma_capture, devc->name))
printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
}
if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
dev_name,
&ad1848_mixer_operations,
sizeof(struct mixer_operations),
devc)) >= 0)
{
audio_devs[my_dev]->mixer_dev = e;
if (owner)
mixer_devs[e]->owner = owner;
}
return my_dev;
}
int ad1848_control(int cmd, int arg)
{
ad1848_info *devc;
unsigned long flags;
if (nr_ad1848_devs < 1)
return -ENODEV;
devc = &adev_info[nr_ad1848_devs - 1];
switch (cmd)
{
case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
if (devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
return -EINVAL;
spin_lock_irqsave(&devc->lock,flags);
ad_enter_MCE(devc);
ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
ad_leave_MCE(devc);
spin_unlock_irqrestore(&devc->lock,flags);
break;
case AD1848_MIXER_REROUTE:
{
int o = (arg >> 8) & 0xff;
int n = arg & 0xff;
if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
return -EINVAL;
if (!(devc->supported_devices & (1 << o)) &&
!(devc->supported_rec_devices & (1 << o)))
return -EINVAL;
if (n == SOUND_MIXER_NONE)
{ /* Just hide this control */
ad1848_mixer_set(devc, o, 0); /* Shut up it */
devc->supported_devices &= ~(1 << o);
devc->supported_rec_devices &= ~(1 << o);
break;
}
/* Make the mixer control identified by o to appear as n */
if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
return -EINVAL;
devc->mixer_reroute[n] = o; /* Rename the control */
if (devc->supported_devices & (1 << o))
devc->supported_devices |= (1 << n);
if (devc->supported_rec_devices & (1 << o))
devc->supported_rec_devices |= (1 << n);
devc->supported_devices &= ~(1 << o);
devc->supported_rec_devices &= ~(1 << o);
}
break;
}
return 0;
}
void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
{
int i, mixer, dev = 0;
ad1848_info *devc = NULL;
for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
{
if (adev_info[i].base == io_base)
{
devc = &adev_info[i];
dev = devc->dev_no;
}
}
if (devc != NULL)
{
kfree(audio_devs[dev]->portc);
release_region(devc->base, 4);
if (!share_dma)
{
if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
free_irq(devc->irq, (void *)(long)devc->dev_no);
sound_free_dma(dma_playback);
if (dma_playback != dma_capture)
sound_free_dma(dma_capture);
}
mixer = audio_devs[devc->dev_no]->mixer_dev;
if(mixer>=0)
sound_unload_mixerdev(mixer);
nr_ad1848_devs--;
for ( ; i < nr_ad1848_devs ; i++)
adev_info[i] = adev_info[i+1];
}
else
printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
}
static irqreturn_t adintr(int irq, void *dev_id)
{
unsigned char status;
ad1848_info *devc;
int dev;
int alt_stat = 0xff;
unsigned char c930_stat = 0;
int cnt = 0;
dev = (long)dev_id;
devc = (ad1848_info *) audio_devs[dev]->devc;
interrupt_again: /* Jump back here if int status doesn't reset */
status = inb(io_Status(devc));
if (status == 0x80)
printk(KERN_DEBUG "adintr: Why?\n");
if (devc->model == MD_1848)
outb((0), io_Status(devc)); /* Clear interrupt status */
if (status & 0x01)
{
if (devc->model == MD_C930)
{ /* 82C930 has interrupt status register in MAD16 register MC11 */
spin_lock(&devc->lock);
/* 0xe0e is C930 address port
* 0xe0f is C930 data port
*/
outb(11, 0xe0e);
c930_stat = inb(0xe0f);
outb((~c930_stat), 0xe0f);
spin_unlock(&devc->lock);
alt_stat = (c930_stat << 2) & 0x30;
}
else if (devc->model != MD_1848)
{
spin_lock(&devc->lock);
alt_stat = ad_read(devc, 24);
ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
spin_unlock(&devc->lock);
}
if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
{
DMAbuf_inputintr(devc->record_dev);
}
if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
(alt_stat & 0x10))
{
DMAbuf_outputintr(devc->playback_dev, 1);
}
if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
{
devc->timer_ticks++;
#ifndef EXCLUDE_TIMERS
if (timer_installed == dev && devc->timer_running)
sound_timer_interrupt();
#endif
}
}
/*
* Sometimes playback or capture interrupts occur while a timer interrupt
* is being handled. The interrupt will not be retriggered if we don't
* handle it now. Check if an interrupt is still pending and restart
* the handler in this case.
*/
if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
{
goto interrupt_again;
}
return IRQ_HANDLED;
}
/*
* Experimental initialization sequence for the integrated sound system
* of the Compaq Deskpro M.
*/
static int init_deskpro_m(struct address_info *hw_config)
{
unsigned char tmp;
if ((tmp = inb(0xc44)) == 0xff)
{
DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
return 0;
}
outb(0x10, 0xc44);
outb(0x40, 0xc45);
outb(0x00, 0xc46);
outb(0xe8, 0xc47);
outb(0x14, 0xc44);
outb(0x40, 0xc45);
outb(0x00, 0xc46);
outb(0xe8, 0xc47);
outb(0x10, 0xc44);
return 1;
}
/*
* Experimental initialization sequence for the integrated sound system
* of Compaq Deskpro XL.
*/
static int init_deskpro(struct address_info *hw_config)
{
unsigned char tmp;
if ((tmp = inb(0xc44)) == 0xff)
{
DDB(printk("init_deskpro: Dead port 0xc44\n"));
return 0;
}
outb((tmp | 0x04), 0xc44); /* Select bank 1 */
if (inb(0xc44) != 0x04)
{
DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
return 0;
}
/*
* OK. It looks like a Deskpro so let's proceed.
*/
/*
* I/O port 0xc44 Audio configuration register.
*
* bits 0xc0: Audio revision bits
* 0x00 = Compaq Business Audio
* 0x40 = MS Sound System Compatible (reset default)
* 0x80 = Reserved
* 0xc0 = Reserved
* bit 0x20: No Wait State Enable
* 0x00 = Disabled (reset default, DMA mode)
* 0x20 = Enabled (programmed I/O mode)
* bit 0x10: MS Sound System Decode Enable
* 0x00 = Decoding disabled (reset default)
* 0x10 = Decoding enabled
* bit 0x08: FM Synthesis Decode Enable
* 0x00 = Decoding Disabled (reset default)
* 0x08 = Decoding enabled
* bit 0x04 Bank select
* 0x00 = Bank 0
* 0x04 = Bank 1
* bits 0x03 MSS Base address
* 0x00 = 0x530 (reset default)
* 0x01 = 0x604
* 0x02 = 0xf40
* 0x03 = 0xe80
*/
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc44 (before): ");
outb((tmp & ~0x04), 0xc44);
printk("%02x ", inb(0xc44));
outb((tmp | 0x04), 0xc44);
printk("%02x\n", inb(0xc44));
#endif
/* Set bank 1 of the register */
tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
switch (hw_config->io_base)
{
case 0x530:
tmp |= 0x00;
break;
case 0x604:
tmp |= 0x01;
break;
case 0xf40:
tmp |= 0x02;
break;
case 0xe80:
tmp |= 0x03;
break;
default:
DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
return 0;
}
outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc44 (after): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc44));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc44));
#endif
/*
* I/O port 0xc45 FM Address Decode/MSS ID Register.
*
* bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
* bank=0, bit 0x01: SBIC Power Control Bit
* 0x00 = Powered up
* 0x01 = Powered down
* bank=1, bits 0xfc: MSS ID (default=0x40)
*/
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc45 (before): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc45));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc45));
#endif
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc45 (after): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc45));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc45));
#endif
/*
* I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
*
* bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
* bank=1, bits 0xff: Audio addressing ASIC id
*/
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc46 (before): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc46));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc46));
#endif
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
outb((0x11), 0xc46); /* ASIC ID = 0x11 */
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc46 (after): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc46));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc46));
#endif
/*
* I/O port 0xc47 FM Address Decode Register.
*
* bank=0, bits 0xff: Decode enable selection for various FM address bits
* bank=1, bits 0xff: Reserved
*/
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc47 (before): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc47));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc47));
#endif
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
#ifdef DEBUGXL
/* Debug printing */
printk("Port 0xc47 (after): ");
outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
printk("%02x ", inb(0xc47));
outb((tmp | 0x04), 0xc44); /* Select bank=1 */
printk("%02x\n", inb(0xc47));
#endif
/*
* I/O port 0xc6f = Audio Disable Function Register
*/
#ifdef DEBUGXL
printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
#endif
outb((0x80), 0xc6f);
#ifdef DEBUGXL
printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
#endif
return 1;
}
int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
{
unsigned char tmp;
DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
{
/* check_opl3(0x388, hw_config); */
return ad1848_detect(ports, NULL, hw_config->osp);
}
if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
{
if (!init_deskpro(hw_config))
return 0;
}
if (deskpro_m) /* Compaq Deskpro M */
{
if (!init_deskpro_m(hw_config))
return 0;
}
/*
* Check if the IO port returns valid signature. The original MS Sound
* system returns 0x04 while some cards (AudioTrix Pro for example)
* return 0x00 or 0x0f.
*/
if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
{
int ret;
DDB(printk("I/O address is inactive (%x)\n", tmp));
if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
return 0;
return 1;
}
DDB(printk("MSS signature = %x\n", tmp & 0x3f));
if ((tmp & 0x3f) != 0x04 &&
(tmp & 0x3f) != 0x0f &&
(tmp & 0x3f) != 0x00)
{
int ret;
MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
return 0;
hw_config->card_subtype = 1;
return 1;
}
if ((hw_config->irq != 5) &&
(hw_config->irq != 7) &&
(hw_config->irq != 9) &&
(hw_config->irq != 10) &&
(hw_config->irq != 11) &&
(hw_config->irq != 12))
{
printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
return 0;
}
if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
{
printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
return 0;
}
/*
* Check that DMA0 is not in use with a 8 bit board.
*/
if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
{
printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
return 0;
}
if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
{
printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
return 0;
}
return ad1848_detect(ports, NULL, hw_config->osp);
}
void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
{
static signed char interrupt_bits[12] =
{
-1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
};
signed char bits;
char dma2_bit = 0;
static char dma_bits[4] =
{
1, 2, 0, 3
};
int config_port = hw_config->io_base + 0;
int version_port = hw_config->io_base + 3;
int dma = hw_config->dma;
int dma2 = hw_config->dma2;
if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
{
hw_config->slots[0] = ad1848_init("MS Sound System", ports,
hw_config->irq,
hw_config->dma,
hw_config->dma2, 0,
hw_config->osp,
owner);
return;
}
/*
* Set the IRQ and DMA addresses.
*/
bits = interrupt_bits[hw_config->irq];
if (bits == -1)
{
printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
release_region(ports->start, 4);
release_region(ports->start - 4, 4);
return;
}
outb((bits | 0x40), config_port);
if ((inb(version_port) & 0x40) == 0)
printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
/*
* Handle the capture DMA channel
*/
if (dma2 != -1 && dma2 != dma)
{
if (!((dma == 0 && dma2 == 1) ||
(dma == 1 && dma2 == 0) ||
(dma == 3 && dma2 == 0)))
{ /* Unsupported combination. Try to swap channels */
int tmp = dma;
dma = dma2;
dma2 = tmp;
}
if ((dma == 0 && dma2 == 1) ||
(dma == 1 && dma2 == 0) ||
(dma == 3 && dma2 == 0))
{
dma2_bit = 0x04; /* Enable capture DMA */
}
else
{
printk(KERN_WARNING "MSS: Invalid capture DMA\n");
dma2 = dma;
}
}
else
{
dma2 = dma;
}
hw_config->dma = dma;
hw_config->dma2 = dma2;
outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
hw_config->slots[0] = ad1848_init("MS Sound System", ports,
hw_config->irq,
dma, dma2, 0,
hw_config->osp,
THIS_MODULE);
}
void unload_ms_sound(struct address_info *hw_config)
{
ad1848_unload(hw_config->io_base + 4,
hw_config->irq,
hw_config->dma,
hw_config->dma2, 0);
sound_unload_audiodev(hw_config->slots[0]);
release_region(hw_config->io_base, 4);
}
#ifndef EXCLUDE_TIMERS
/*
* Timer stuff (for /dev/music).
*/
static unsigned int current_interval;
static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
{
unsigned long flags;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
unsigned long divider;
spin_lock_irqsave(&devc->lock,flags);
/*
* Length of the timer interval (in nanoseconds) depends on the
* selected crystal oscillator. Check this from bit 0x01 of I8.
*
* AD1845 has just one oscillator which has cycle time of 10.050 us
* (when a 24.576 MHz xtal oscillator is used).
*
* Convert requested interval to nanoseconds before computing
* the timer divider.
*/
if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
xtal_nsecs = 10050;
else if (ad_read(devc, 8) & 0x01)
xtal_nsecs = 9920;
else
xtal_nsecs = 9969;
divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
if (divider < 100) /* Don't allow shorter intervals than about 1ms */
divider = 100;
if (divider > 65535) /* Overflow check */
divider = 65535;
ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
ad_write(devc, 20, divider & 0xff); /* Set lower bits */
ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
devc->timer_running = 1;
spin_unlock_irqrestore(&devc->lock,flags);
return current_interval = (divider * xtal_nsecs + 500) / 1000;
}
static void ad1848_tmr_reprogram(int dev)
{
/*
* Audio driver has changed sampling rate so that a different xtal
* oscillator was selected. We have to reprogram the timer rate.
*/
ad1848_tmr_start(dev, current_interval);
sound_timer_syncinterval(current_interval);
}
static void ad1848_tmr_disable(int dev)
{
unsigned long flags;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
spin_lock_irqsave(&devc->lock,flags);
ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
devc->timer_running = 0;
spin_unlock_irqrestore(&devc->lock,flags);
}
static void ad1848_tmr_restart(int dev)
{
unsigned long flags;
ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
if (current_interval == 0)
return;
spin_lock_irqsave(&devc->lock,flags);
ad_write(devc, 16, ad_read(devc, 16) | 0x40);
devc->timer_running = 1;
spin_unlock_irqrestore(&devc->lock,flags);
}
static struct sound_lowlev_timer ad1848_tmr =
{
0,
2,
ad1848_tmr_start,
ad1848_tmr_disable,
ad1848_tmr_restart
};
static int ad1848_tmr_install(int dev)
{
if (timer_installed != -1)
return 0; /* Don't install another timer */
timer_installed = ad1848_tmr.dev = dev;
sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
return 1;
}
#endif /* EXCLUDE_TIMERS */
EXPORT_SYMBOL(ad1848_detect);
EXPORT_SYMBOL(ad1848_init);
EXPORT_SYMBOL(ad1848_unload);
EXPORT_SYMBOL(ad1848_control);
EXPORT_SYMBOL(probe_ms_sound);
EXPORT_SYMBOL(attach_ms_sound);
EXPORT_SYMBOL(unload_ms_sound);
static int __initdata io = -1;
static int __initdata irq = -1;
static int __initdata dma = -1;
static int __initdata dma2 = -1;
static int __initdata type = 0;
module_param(io, int, 0); /* I/O for a raw AD1848 card */
module_param(irq, int, 0); /* IRQ to use */
module_param(dma, int, 0); /* First DMA channel */
module_param(dma2, int, 0); /* Second DMA channel */
module_param(type, int, 0); /* Card type */
module_param(deskpro_xl, bool, 0); /* Special magic for Deskpro XL boxen */
module_param(deskpro_m, bool, 0); /* Special magic for Deskpro M box */
module_param(soundpro, bool, 0); /* More special magic for SoundPro chips */
#ifdef CONFIG_PNP
module_param(isapnp, int, 0);
module_param(isapnpjump, int, 0);
module_param(reverse, bool, 0);
MODULE_PARM_DESC(isapnp, "When set to 0, Plug & Play support will be disabled");
MODULE_PARM_DESC(isapnpjump, "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
MODULE_PARM_DESC(reverse, "When set to 1, will reverse ISAPnP search order");
static struct pnp_dev *ad1848_dev = NULL;
/* Please add new entries at the end of the table */
static struct {
char *name;
unsigned short card_vendor, card_device,
vendor, function;
short mss_io, irq, dma, dma2; /* index into isapnp table */
int type;
} ad1848_isapnp_list[] __initdata = {
{"CMI 8330 SoundPRO",
ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
0, 0, 0,-1, 0},
{"CS4232 based card",
ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
0, 0, 0, 1, 0},
{"CS4232 based card",
ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
0, 0, 0, 1, 0},
{"OPL3-SA2 WSS mode",
ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
1, 0, 0, 1, 1},
{"Advanced Gravis InterWave Audio",
ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
0, 0, 0, 1, 0},
{NULL}
};
static struct isapnp_device_id id_table[] __devinitdata = {
{ ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
{ ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
{ ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
/* The main driver for this card is opl3sa2
{ ISAPNP_ANY_ID, ISAPNP_ANY_ID,
ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
*/
{ ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
{0}
};
MODULE_DEVICE_TABLE(isapnp, id_table);
static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
{
int err;
err = pnp_device_attach(dev);
if (err < 0)
return(NULL);
if((err = pnp_activate_dev(dev)) < 0) {
printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
pnp_device_detach(dev);
return(NULL);
}
audio_activated = 1;
return(dev);
}
static struct pnp_dev __init *ad1848_init_generic(struct pnp_card *bus,
struct address_info *hw_config, int slot)
{
/* Configure Audio device */
if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
{
if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
{
hw_config->io_base = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
hw_config->irq = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
hw_config->dma = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
if(ad1848_isapnp_list[slot].dma2 != -1)
hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
else
hw_config->dma2 = -1;
hw_config->card_subtype = ad1848_isapnp_list[slot].type;
} else
return(NULL);
} else
return(NULL);
return(ad1848_dev);
}
static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
{
char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
/* Initialize this baby. */
if(ad1848_init_generic(bus, hw_config, slot)) {
/* We got it. */
printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
busname,
hw_config->io_base, hw_config->irq, hw_config->dma,
hw_config->dma2);
return 1;
}
return 0;
}
static int __init ad1848_isapnp_probe(struct address_info *hw_config)
{
static int first = 1;
int i;
/* Count entries in sb_isapnp_list */
for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
i--;
/* Check and adjust isapnpjump */
if( isapnpjump < 0 || isapnpjump > i) {
isapnpjump = reverse ? i : 0;
printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
}
if(!first || !reverse)
i = isapnpjump;
first = 0;
while(ad1848_isapnp_list[i].card_vendor != 0) {
static struct pnp_card *bus = NULL;
while ((bus = pnp_find_card(
ad1848_isapnp_list[i].card_vendor,
ad1848_isapnp_list[i].card_device,
bus))) {
if(ad1848_isapnp_init(hw_config, bus, i)) {
isapnpjump = i; /* start next search from here */
return 0;
}
}
i += reverse ? -1 : 1;
}
return -ENODEV;
}
#endif
static int __init init_ad1848(void)
{
printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
#ifdef CONFIG_PNP
if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
isapnp = 0;
}
#endif
if(io != -1) {
struct resource *ports;
if( isapnp == 0 )
{
if(irq == -1 || dma == -1) {
printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
return -EINVAL;
}
cfg.irq = irq;
cfg.io_base = io;
cfg.dma = dma;
cfg.dma2 = dma2;
cfg.card_subtype = type;
}
ports = request_region(io + 4, 4, "ad1848");
if (!ports)
return -EBUSY;
if (!request_region(io, 4, "WSS config")) {
release_region(io + 4, 4);
return -EBUSY;
}
if (!probe_ms_sound(&cfg, ports)) {
release_region(io + 4, 4);
release_region(io, 4);
return -ENODEV;
}
attach_ms_sound(&cfg, ports, THIS_MODULE);
loaded = 1;
}
return 0;
}
static void __exit cleanup_ad1848(void)
{
if(loaded)
unload_ms_sound(&cfg);
#ifdef CONFIG_PNP
if(ad1848_dev){
if(audio_activated)
pnp_device_detach(ad1848_dev);
}
#endif
}
module_init(init_ad1848);
module_exit(cleanup_ad1848);
#ifndef MODULE
static int __init setup_ad1848(char *str)
{
/* io, irq, dma, dma2, type */
int ints[6];
str = get_options(str, ARRAY_SIZE(ints), ints);
io = ints[1];
irq = ints[2];
dma = ints[3];
dma2 = ints[4];
type = ints[5];
return 1;
}
__setup("ad1848=", setup_ad1848);
#endif
MODULE_LICENSE("GPL");
| gpl-2.0 |
moonman/linux-imx6-3.14 | drivers/infiniband/hw/qib/qib_debugfs.c | 612 | 6547 | #ifdef CONFIG_DEBUG_FS
/*
* Copyright (c) 2013 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include "qib.h"
#include "qib_verbs.h"
#include "qib_debugfs.h"
static struct dentry *qib_dbg_root;
#define DEBUGFS_FILE(name) \
static const struct seq_operations _##name##_seq_ops = { \
.start = _##name##_seq_start, \
.next = _##name##_seq_next, \
.stop = _##name##_seq_stop, \
.show = _##name##_seq_show \
}; \
static int _##name##_open(struct inode *inode, struct file *s) \
{ \
struct seq_file *seq; \
int ret; \
ret = seq_open(s, &_##name##_seq_ops); \
if (ret) \
return ret; \
seq = s->private_data; \
seq->private = inode->i_private; \
return 0; \
} \
static const struct file_operations _##name##_file_ops = { \
.owner = THIS_MODULE, \
.open = _##name##_open, \
.read = seq_read, \
.llseek = seq_lseek, \
.release = seq_release \
};
#define DEBUGFS_FILE_CREATE(name) \
do { \
struct dentry *ent; \
ent = debugfs_create_file(#name , 0400, ibd->qib_ibdev_dbg, \
ibd, &_##name##_file_ops); \
if (!ent) \
pr_warn("create of " #name " failed\n"); \
} while (0)
static void *_opcode_stats_seq_start(struct seq_file *s, loff_t *pos)
{
struct qib_opcode_stats_perctx *opstats;
if (*pos >= ARRAY_SIZE(opstats->stats))
return NULL;
return pos;
}
static void *_opcode_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
{
struct qib_opcode_stats_perctx *opstats;
++*pos;
if (*pos >= ARRAY_SIZE(opstats->stats))
return NULL;
return pos;
}
static void _opcode_stats_seq_stop(struct seq_file *s, void *v)
{
/* nothing allocated */
}
static int _opcode_stats_seq_show(struct seq_file *s, void *v)
{
loff_t *spos = v;
loff_t i = *spos, j;
u64 n_packets = 0, n_bytes = 0;
struct qib_ibdev *ibd = (struct qib_ibdev *)s->private;
struct qib_devdata *dd = dd_from_dev(ibd);
for (j = 0; j < dd->first_user_ctxt; j++) {
if (!dd->rcd[j])
continue;
n_packets += dd->rcd[j]->opstats->stats[i].n_packets;
n_bytes += dd->rcd[j]->opstats->stats[i].n_bytes;
}
if (!n_packets && !n_bytes)
return SEQ_SKIP;
seq_printf(s, "%02llx %llu/%llu\n", i,
(unsigned long long) n_packets,
(unsigned long long) n_bytes);
return 0;
}
DEBUGFS_FILE(opcode_stats)
static void *_ctx_stats_seq_start(struct seq_file *s, loff_t *pos)
{
struct qib_ibdev *ibd = (struct qib_ibdev *)s->private;
struct qib_devdata *dd = dd_from_dev(ibd);
if (!*pos)
return SEQ_START_TOKEN;
if (*pos >= dd->first_user_ctxt)
return NULL;
return pos;
}
static void *_ctx_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
{
struct qib_ibdev *ibd = (struct qib_ibdev *)s->private;
struct qib_devdata *dd = dd_from_dev(ibd);
if (v == SEQ_START_TOKEN)
return pos;
++*pos;
if (*pos >= dd->first_user_ctxt)
return NULL;
return pos;
}
static void _ctx_stats_seq_stop(struct seq_file *s, void *v)
{
/* nothing allocated */
}
static int _ctx_stats_seq_show(struct seq_file *s, void *v)
{
loff_t *spos;
loff_t i, j;
u64 n_packets = 0;
struct qib_ibdev *ibd = (struct qib_ibdev *)s->private;
struct qib_devdata *dd = dd_from_dev(ibd);
if (v == SEQ_START_TOKEN) {
seq_puts(s, "Ctx:npkts\n");
return 0;
}
spos = v;
i = *spos;
if (!dd->rcd[i])
return SEQ_SKIP;
for (j = 0; j < ARRAY_SIZE(dd->rcd[i]->opstats->stats); j++)
n_packets += dd->rcd[i]->opstats->stats[j].n_packets;
if (!n_packets)
return SEQ_SKIP;
seq_printf(s, " %llu:%llu\n", i, n_packets);
return 0;
}
DEBUGFS_FILE(ctx_stats)
static void *_qp_stats_seq_start(struct seq_file *s, loff_t *pos)
{
struct qib_qp_iter *iter;
loff_t n = *pos;
rcu_read_lock();
iter = qib_qp_iter_init(s->private);
if (!iter)
return NULL;
while (n--) {
if (qib_qp_iter_next(iter)) {
kfree(iter);
return NULL;
}
}
return iter;
}
static void *_qp_stats_seq_next(struct seq_file *s, void *iter_ptr,
loff_t *pos)
{
struct qib_qp_iter *iter = iter_ptr;
(*pos)++;
if (qib_qp_iter_next(iter)) {
kfree(iter);
return NULL;
}
return iter;
}
static void _qp_stats_seq_stop(struct seq_file *s, void *iter_ptr)
{
rcu_read_unlock();
}
static int _qp_stats_seq_show(struct seq_file *s, void *iter_ptr)
{
struct qib_qp_iter *iter = iter_ptr;
if (!iter)
return 0;
qib_qp_iter_print(s, iter);
return 0;
}
DEBUGFS_FILE(qp_stats)
void qib_dbg_ibdev_init(struct qib_ibdev *ibd)
{
char name[10];
snprintf(name, sizeof(name), "qib%d", dd_from_dev(ibd)->unit);
ibd->qib_ibdev_dbg = debugfs_create_dir(name, qib_dbg_root);
if (!ibd->qib_ibdev_dbg) {
pr_warn("create of %s failed\n", name);
return;
}
DEBUGFS_FILE_CREATE(opcode_stats);
DEBUGFS_FILE_CREATE(ctx_stats);
DEBUGFS_FILE_CREATE(qp_stats);
return;
}
void qib_dbg_ibdev_exit(struct qib_ibdev *ibd)
{
if (!qib_dbg_root)
goto out;
debugfs_remove_recursive(ibd->qib_ibdev_dbg);
out:
ibd->qib_ibdev_dbg = NULL;
}
void qib_dbg_init(void)
{
qib_dbg_root = debugfs_create_dir(QIB_DRV_NAME, NULL);
if (!qib_dbg_root)
pr_warn("init of debugfs failed\n");
}
void qib_dbg_exit(void)
{
debugfs_remove_recursive(qib_dbg_root);
qib_dbg_root = NULL;
}
#endif
| gpl-2.0 |
gqk289/linux | drivers/pcmcia/sa1111_badge4.c | 1124 | 4038 | /*
* linux/drivers/pcmcia/sa1100_badge4.c
*
* BadgePAD 4 PCMCIA specific routines
*
* Christopher Hoover <ch@hpl.hp.com>
*
* Copyright (C) 2002 Hewlett-Packard Company
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <mach/badge4.h>
#include <asm/hardware/sa1111.h>
#include "sa1111_generic.h"
/*
* BadgePAD 4 Details
*
* PCM Vcc:
*
* PCM Vcc on BadgePAD 4 can be jumpered for 3v3 (short pins 1 and 3
* on JP6) or 5v0 (short pins 3 and 5 on JP6).
*
* PCM Vpp:
*
* PCM Vpp on BadgePAD 4 can be jumpered for 12v0 (short pins 4 and 6
* on JP6) or tied to PCM Vcc (short pins 2 and 4 on JP6). N.B.,
* 12v0 operation requires that the power supply actually supply 12v0
* via pin 7 of JP7.
*
* CF Vcc:
*
* CF Vcc on BadgePAD 4 can be jumpered either for 3v3 (short pins 1
* and 2 on JP10) or 5v0 (short pins 2 and 3 on JP10).
*
* Unfortunately there's no way programmatically to determine how a
* given board is jumpered. This code assumes a default jumpering
* as described below.
*
* If the defaults aren't correct, you may override them with a pcmv
* setup argument: pcmv=<pcm vcc>,<pcm vpp>,<cf vcc>. The units are
* tenths of volts; e.g. pcmv=33,120,50 indicates 3v3 PCM Vcc, 12v0
* PCM Vpp, and 5v0 CF Vcc.
*
*/
static int badge4_pcmvcc = 50; /* pins 3 and 5 jumpered on JP6 */
static int badge4_pcmvpp = 50; /* pins 2 and 4 jumpered on JP6 */
static int badge4_cfvcc = 33; /* pins 1 and 2 jumpered on JP10 */
static void complain_about_jumpering(const char *whom,
const char *supply,
int given, int wanted)
{
printk(KERN_ERR
"%s: %s %d.%dV wanted but board is jumpered for %s %d.%dV operation"
"; re-jumper the board and/or use pcmv=xx,xx,xx\n",
whom, supply,
wanted / 10, wanted % 10,
supply,
given / 10, given % 10);
}
static int
badge4_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_t *state)
{
int ret;
switch (skt->nr) {
case 0:
if ((state->Vcc != 0) &&
(state->Vcc != badge4_pcmvcc)) {
complain_about_jumpering(__func__, "pcmvcc",
badge4_pcmvcc, state->Vcc);
// Apply power regardless of the jumpering.
// return -1;
}
if ((state->Vpp != 0) &&
(state->Vpp != badge4_pcmvpp)) {
complain_about_jumpering(__func__, "pcmvpp",
badge4_pcmvpp, state->Vpp);
return -1;
}
break;
case 1:
if ((state->Vcc != 0) &&
(state->Vcc != badge4_cfvcc)) {
complain_about_jumpering(__func__, "cfvcc",
badge4_cfvcc, state->Vcc);
return -1;
}
break;
default:
return -1;
}
ret = sa1111_pcmcia_configure_socket(skt, state);
if (ret == 0) {
unsigned long flags;
int need5V;
local_irq_save(flags);
need5V = ((state->Vcc == 50) || (state->Vpp == 50));
badge4_set_5V(BADGE4_5V_PCMCIA_SOCK(skt->nr), need5V);
local_irq_restore(flags);
}
return ret;
}
static struct pcmcia_low_level badge4_pcmcia_ops = {
.owner = THIS_MODULE,
.configure_socket = badge4_pcmcia_configure_socket,
.first = 0,
.nr = 2,
};
int pcmcia_badge4_init(struct sa1111_dev *dev)
{
int ret = -ENODEV;
if (machine_is_badge4()) {
printk(KERN_INFO
"%s: badge4_pcmvcc=%d, badge4_pcmvpp=%d, badge4_cfvcc=%d\n",
__func__,
badge4_pcmvcc, badge4_pcmvpp, badge4_cfvcc);
sa11xx_drv_pcmcia_ops(&badge4_pcmcia_ops);
ret = sa1111_pcmcia_add(dev, &badge4_pcmcia_ops,
sa11xx_drv_pcmcia_add_one);
}
return ret;
}
static int __init pcmv_setup(char *s)
{
int v[4];
s = get_options(s, ARRAY_SIZE(v), v);
if (v[0] >= 1) badge4_pcmvcc = v[1];
if (v[0] >= 2) badge4_pcmvpp = v[2];
if (v[0] >= 3) badge4_cfvcc = v[3];
return 1;
}
__setup("pcmv=", pcmv_setup);
| gpl-2.0 |
PhenomX1998/android_kernel_oneplus_msm8996 | drivers/pci/ats.c | 1380 | 8777 | /*
* drivers/pci/ats.c
*
* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
* Copyright (C) 2011 Advanced Micro Devices,
*
* PCI Express I/O Virtualization (IOV) support.
* Address Translation Service 1.0
* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
*/
#include <linux/export.h>
#include <linux/pci-ats.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "pci.h"
static int ats_alloc_one(struct pci_dev *dev, int ps)
{
int pos;
u16 cap;
struct pci_ats *ats;
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
if (!pos)
return -ENODEV;
ats = kzalloc(sizeof(*ats), GFP_KERNEL);
if (!ats)
return -ENOMEM;
ats->pos = pos;
ats->stu = ps;
pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
PCI_ATS_MAX_QDEP;
dev->ats = ats;
return 0;
}
static void ats_free_one(struct pci_dev *dev)
{
kfree(dev->ats);
dev->ats = NULL;
}
/**
* pci_enable_ats - enable the ATS capability
* @dev: the PCI device
* @ps: the IOMMU page shift
*
* Returns 0 on success, or negative on failure.
*/
int pci_enable_ats(struct pci_dev *dev, int ps)
{
int rc;
u16 ctrl;
BUG_ON(dev->ats && dev->ats->is_enabled);
if (ps < PCI_ATS_MIN_STU)
return -EINVAL;
if (dev->is_physfn || dev->is_virtfn) {
struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
mutex_lock(&pdev->sriov->lock);
if (pdev->ats)
rc = pdev->ats->stu == ps ? 0 : -EINVAL;
else
rc = ats_alloc_one(pdev, ps);
if (!rc)
pdev->ats->ref_cnt++;
mutex_unlock(&pdev->sriov->lock);
if (rc)
return rc;
}
if (!dev->is_physfn) {
rc = ats_alloc_one(dev, ps);
if (rc)
return rc;
}
ctrl = PCI_ATS_CTRL_ENABLE;
if (!dev->is_virtfn)
ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
dev->ats->is_enabled = 1;
return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_ats);
/**
* pci_disable_ats - disable the ATS capability
* @dev: the PCI device
*/
void pci_disable_ats(struct pci_dev *dev)
{
u16 ctrl;
BUG_ON(!dev->ats || !dev->ats->is_enabled);
pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
ctrl &= ~PCI_ATS_CTRL_ENABLE;
pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
dev->ats->is_enabled = 0;
if (dev->is_physfn || dev->is_virtfn) {
struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
mutex_lock(&pdev->sriov->lock);
pdev->ats->ref_cnt--;
if (!pdev->ats->ref_cnt)
ats_free_one(pdev);
mutex_unlock(&pdev->sriov->lock);
}
if (!dev->is_physfn)
ats_free_one(dev);
}
EXPORT_SYMBOL_GPL(pci_disable_ats);
void pci_restore_ats_state(struct pci_dev *dev)
{
u16 ctrl;
if (!pci_ats_enabled(dev))
return;
if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS))
BUG();
ctrl = PCI_ATS_CTRL_ENABLE;
if (!dev->is_virtfn)
ctrl |= PCI_ATS_CTRL_STU(dev->ats->stu - PCI_ATS_MIN_STU);
pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
}
EXPORT_SYMBOL_GPL(pci_restore_ats_state);
/**
* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
* @dev: the PCI device
*
* Returns the queue depth on success, or negative on failure.
*
* The ATS spec uses 0 in the Invalidate Queue Depth field to
* indicate that the function can accept 32 Invalidate Request.
* But here we use the `real' values (i.e. 1~32) for the Queue
* Depth; and 0 indicates the function shares the Queue with
* other functions (doesn't exclusively own a Queue).
*/
int pci_ats_queue_depth(struct pci_dev *dev)
{
int pos;
u16 cap;
if (dev->is_virtfn)
return 0;
if (dev->ats)
return dev->ats->qdep;
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
if (!pos)
return -ENODEV;
pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
PCI_ATS_MAX_QDEP;
}
EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
#ifdef CONFIG_PCI_PRI
/**
* pci_enable_pri - Enable PRI capability
* @ pdev: PCI device structure
*
* Returns 0 on success, negative value on error
*/
int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
{
u16 control, status;
u32 max_requests;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return -EINVAL;
pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
if ((control & PCI_PRI_CTRL_ENABLE) ||
!(status & PCI_PRI_STATUS_STOPPED))
return -EBUSY;
pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
reqs = min(max_requests, reqs);
pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
control |= PCI_PRI_CTRL_ENABLE;
pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pri);
/**
* pci_disable_pri - Disable PRI capability
* @pdev: PCI device structure
*
* Only clears the enabled-bit, regardless of its former value
*/
void pci_disable_pri(struct pci_dev *pdev)
{
u16 control;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return;
pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
control &= ~PCI_PRI_CTRL_ENABLE;
pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_disable_pri);
/**
* pci_reset_pri - Resets device's PRI state
* @pdev: PCI device structure
*
* The PRI capability must be disabled before this function is called.
* Returns 0 on success, negative value on error.
*/
int pci_reset_pri(struct pci_dev *pdev)
{
u16 control;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return -EINVAL;
pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
if (control & PCI_PRI_CTRL_ENABLE)
return -EBUSY;
control |= PCI_PRI_CTRL_RESET;
pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
return 0;
}
EXPORT_SYMBOL_GPL(pci_reset_pri);
#endif /* CONFIG_PCI_PRI */
#ifdef CONFIG_PCI_PASID
/**
* pci_enable_pasid - Enable the PASID capability
* @pdev: PCI device structure
* @features: Features to enable
*
* Returns 0 on success, negative value on error. This function checks
* whether the features are actually supported by the device and returns
* an error if not.
*/
int pci_enable_pasid(struct pci_dev *pdev, int features)
{
u16 control, supported;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
if (!pos)
return -EINVAL;
pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control);
pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
if (control & PCI_PASID_CTRL_ENABLE)
return -EINVAL;
supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
/* User wants to enable anything unsupported? */
if ((supported & features) != features)
return -EINVAL;
control = PCI_PASID_CTRL_ENABLE | features;
pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pasid);
/**
* pci_disable_pasid - Disable the PASID capability
* @pdev: PCI device structure
*
*/
void pci_disable_pasid(struct pci_dev *pdev)
{
u16 control = 0;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
if (!pos)
return;
pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);
/**
* pci_pasid_features - Check which PASID features are supported
* @pdev: PCI device structure
*
* Returns a negative value when no PASI capability is present.
* Otherwise is returns a bitmask with supported features. Current
* features reported are:
* PCI_PASID_CAP_EXEC - Execute permission supported
* PCI_PASID_CAP_PRIV - Privileged mode supported
*/
int pci_pasid_features(struct pci_dev *pdev)
{
u16 supported;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
if (!pos)
return -EINVAL;
pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
return supported;
}
EXPORT_SYMBOL_GPL(pci_pasid_features);
#define PASID_NUMBER_SHIFT 8
#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
/**
* pci_max_pasid - Get maximum number of PASIDs supported by device
* @pdev: PCI device structure
*
* Returns negative value when PASID capability is not present.
* Otherwise it returns the numer of supported PASIDs.
*/
int pci_max_pasids(struct pci_dev *pdev)
{
u16 supported;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
if (!pos)
return -EINVAL;
pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
return (1 << supported);
}
EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */
| gpl-2.0 |
SerenityS/android_kernel_samsung_msm8916 | drivers/media/platform/omap3isp/isppreview.c | 1636 | 70742 | /*
* isppreview.c
*
* TI OMAP3 ISP driver - Preview module
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/uaccess.h>
#include "isp.h"
#include "ispreg.h"
#include "isppreview.h"
/* Default values in Office Fluorescent Light for RGBtoRGB Blending */
static struct omap3isp_prev_rgbtorgb flr_rgb2rgb = {
{ /* RGB-RGB Matrix */
{0x01E2, 0x0F30, 0x0FEE},
{0x0F9B, 0x01AC, 0x0FB9},
{0x0FE0, 0x0EC0, 0x0260}
}, /* RGB Offset */
{0x0000, 0x0000, 0x0000}
};
/* Default values in Office Fluorescent Light for RGB to YUV Conversion*/
static struct omap3isp_prev_csc flr_prev_csc = {
{ /* CSC Coef Matrix */
{66, 129, 25},
{-38, -75, 112},
{112, -94 , -18}
}, /* CSC Offset */
{0x0, 0x0, 0x0}
};
/* Default values in Office Fluorescent Light for CFA Gradient*/
#define FLR_CFA_GRADTHRS_HORZ 0x28
#define FLR_CFA_GRADTHRS_VERT 0x28
/* Default values in Office Fluorescent Light for Chroma Suppression*/
#define FLR_CSUP_GAIN 0x0D
#define FLR_CSUP_THRES 0xEB
/* Default values in Office Fluorescent Light for Noise Filter*/
#define FLR_NF_STRGTH 0x03
/* Default values for White Balance */
#define FLR_WBAL_DGAIN 0x100
#define FLR_WBAL_COEF 0x20
/* Default values in Office Fluorescent Light for Black Adjustment*/
#define FLR_BLKADJ_BLUE 0x0
#define FLR_BLKADJ_GREEN 0x0
#define FLR_BLKADJ_RED 0x0
#define DEF_DETECT_CORRECT_VAL 0xe
/*
* Margins and image size limits.
*
* The preview engine crops several rows and columns internally depending on
* which filters are enabled. To avoid format changes when the filters are
* enabled or disabled (which would prevent them from being turned on or off
* during streaming), the driver assumes all filters that can be configured
* during streaming are enabled when computing sink crop and source format
* limits.
*
* If a filter is disabled, additional cropping is automatically added at the
* preview engine input by the driver to avoid overflow at line and frame end.
* This is completely transparent for applications.
*
* Median filter 4 pixels
* Noise filter,
* Faulty pixels correction 4 pixels, 4 lines
* Color suppression 2 pixels
* or luma enhancement
* -------------------------------------------------------------
* Maximum total 10 pixels, 4 lines
*
* The color suppression and luma enhancement filters are applied after bayer to
* YUV conversion. They thus can crop one pixel on the left and one pixel on the
* right side of the image without changing the color pattern. When both those
* filters are disabled, the driver must crop the two pixels on the same side of
* the image to avoid changing the bayer pattern. The left margin is thus set to
* 6 pixels and the right margin to 4 pixels.
*/
#define PREV_MARGIN_LEFT 6
#define PREV_MARGIN_RIGHT 4
#define PREV_MARGIN_TOP 2
#define PREV_MARGIN_BOTTOM 2
#define PREV_MIN_IN_WIDTH 64
#define PREV_MIN_IN_HEIGHT 8
#define PREV_MAX_IN_HEIGHT 16384
#define PREV_MIN_OUT_WIDTH 0
#define PREV_MIN_OUT_HEIGHT 0
#define PREV_MAX_OUT_WIDTH_REV_1 1280
#define PREV_MAX_OUT_WIDTH_REV_2 3300
#define PREV_MAX_OUT_WIDTH_REV_15 4096
/*
* Coeficient Tables for the submodules in Preview.
* Array is initialised with the values from.the tables text file.
*/
/*
* CFA Filter Coefficient Table
*
*/
static u32 cfa_coef_table[4][OMAP3ISP_PREV_CFA_BLK_SIZE] = {
#include "cfa_coef_table.h"
};
/*
* Default Gamma Correction Table - All components
*/
static u32 gamma_table[] = {
#include "gamma_table.h"
};
/*
* Noise Filter Threshold table
*/
static u32 noise_filter_table[] = {
#include "noise_filter_table.h"
};
/*
* Luminance Enhancement Table
*/
static u32 luma_enhance_table[] = {
#include "luma_enhance_table.h"
};
/*
* preview_config_luma_enhancement - Configure the Luminance Enhancement table
*/
static void
preview_config_luma_enhancement(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_luma *yt = ¶ms->luma;
unsigned int i;
isp_reg_writel(isp, ISPPRV_YENH_TABLE_ADDR,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
for (i = 0; i < OMAP3ISP_PREV_YENH_TBL_SIZE; i++) {
isp_reg_writel(isp, yt->table[i],
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
}
}
/*
* preview_enable_luma_enhancement - Enable/disable Luminance Enhancement
*/
static void
preview_enable_luma_enhancement(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_YNENHEN);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_YNENHEN);
}
/*
* preview_enable_invalaw - Enable/disable Inverse A-Law decompression
*/
static void preview_enable_invalaw(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_INVALAW);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_INVALAW);
}
/*
* preview_config_hmed - Configure the Horizontal Median Filter
*/
static void preview_config_hmed(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_hmed *hmed = ¶ms->hmed;
isp_reg_writel(isp, (hmed->odddist == 1 ? 0 : ISPPRV_HMED_ODDDIST) |
(hmed->evendist == 1 ? 0 : ISPPRV_HMED_EVENDIST) |
(hmed->thres << ISPPRV_HMED_THRESHOLD_SHIFT),
OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED);
}
/*
* preview_enable_hmed - Enable/disable the Horizontal Median Filter
*/
static void preview_enable_hmed(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_HMEDEN);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_HMEDEN);
}
/*
* preview_config_cfa - Configure CFA Interpolation for Bayer formats
*
* The CFA table is organised in four blocks, one per Bayer component. The
* hardware expects blocks to follow the Bayer order of the input data, while
* the driver stores the table in GRBG order in memory. The blocks need to be
* reordered to support non-GRBG Bayer patterns.
*/
static void preview_config_cfa(struct isp_prev_device *prev,
const struct prev_params *params)
{
static const unsigned int cfa_coef_order[4][4] = {
{ 0, 1, 2, 3 }, /* GRBG */
{ 1, 0, 3, 2 }, /* RGGB */
{ 2, 3, 0, 1 }, /* BGGR */
{ 3, 2, 1, 0 }, /* GBRG */
};
const unsigned int *order = cfa_coef_order[prev->params.cfa_order];
const struct omap3isp_prev_cfa *cfa = ¶ms->cfa;
struct isp_device *isp = to_isp_device(prev);
unsigned int i;
unsigned int j;
isp_reg_writel(isp,
(cfa->gradthrs_vert << ISPPRV_CFA_GRADTH_VER_SHIFT) |
(cfa->gradthrs_horz << ISPPRV_CFA_GRADTH_HOR_SHIFT),
OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA);
isp_reg_writel(isp, ISPPRV_CFA_TABLE_ADDR,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
for (i = 0; i < 4; ++i) {
const __u32 *block = cfa->table[order[i]];
for (j = 0; j < OMAP3ISP_PREV_CFA_BLK_SIZE; ++j)
isp_reg_writel(isp, block[j], OMAP3_ISP_IOMEM_PREV,
ISPPRV_SET_TBL_DATA);
}
}
/*
* preview_config_chroma_suppression - Configure Chroma Suppression
*/
static void
preview_config_chroma_suppression(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_csup *cs = ¶ms->csup;
isp_reg_writel(isp,
cs->gain | (cs->thres << ISPPRV_CSUP_THRES_SHIFT) |
(cs->hypf_en << ISPPRV_CSUP_HPYF_SHIFT),
OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP);
}
/*
* preview_enable_chroma_suppression - Enable/disable Chrominance Suppression
*/
static void
preview_enable_chroma_suppression(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_SUPEN);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_SUPEN);
}
/*
* preview_config_whitebalance - Configure White Balance parameters
*
* Coefficient matrix always with default values.
*/
static void
preview_config_whitebalance(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_wbal *wbal = ¶ms->wbal;
u32 val;
isp_reg_writel(isp, wbal->dgain, OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN);
val = wbal->coef0 << ISPPRV_WBGAIN_COEF0_SHIFT;
val |= wbal->coef1 << ISPPRV_WBGAIN_COEF1_SHIFT;
val |= wbal->coef2 << ISPPRV_WBGAIN_COEF2_SHIFT;
val |= wbal->coef3 << ISPPRV_WBGAIN_COEF3_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN);
isp_reg_writel(isp,
ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_0_SHIFT |
ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_1_SHIFT |
ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_2_SHIFT |
ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_3_SHIFT |
ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_0_SHIFT |
ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_1_SHIFT |
ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_2_SHIFT |
ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_3_SHIFT |
ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_0_SHIFT |
ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_1_SHIFT |
ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_2_SHIFT |
ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_3_SHIFT |
ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_0_SHIFT |
ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_1_SHIFT |
ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_2_SHIFT |
ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_3_SHIFT,
OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL);
}
/*
* preview_config_blkadj - Configure Black Adjustment
*/
static void
preview_config_blkadj(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_blkadj *blkadj = ¶ms->blkadj;
isp_reg_writel(isp, (blkadj->blue << ISPPRV_BLKADJOFF_B_SHIFT) |
(blkadj->green << ISPPRV_BLKADJOFF_G_SHIFT) |
(blkadj->red << ISPPRV_BLKADJOFF_R_SHIFT),
OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF);
}
/*
* preview_config_rgb_blending - Configure RGB-RGB Blending
*/
static void
preview_config_rgb_blending(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_rgbtorgb *rgbrgb = ¶ms->rgb2rgb;
u32 val;
val = (rgbrgb->matrix[0][0] & 0xfff) << ISPPRV_RGB_MAT1_MTX_RR_SHIFT;
val |= (rgbrgb->matrix[0][1] & 0xfff) << ISPPRV_RGB_MAT1_MTX_GR_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1);
val = (rgbrgb->matrix[0][2] & 0xfff) << ISPPRV_RGB_MAT2_MTX_BR_SHIFT;
val |= (rgbrgb->matrix[1][0] & 0xfff) << ISPPRV_RGB_MAT2_MTX_RG_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2);
val = (rgbrgb->matrix[1][1] & 0xfff) << ISPPRV_RGB_MAT3_MTX_GG_SHIFT;
val |= (rgbrgb->matrix[1][2] & 0xfff) << ISPPRV_RGB_MAT3_MTX_BG_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3);
val = (rgbrgb->matrix[2][0] & 0xfff) << ISPPRV_RGB_MAT4_MTX_RB_SHIFT;
val |= (rgbrgb->matrix[2][1] & 0xfff) << ISPPRV_RGB_MAT4_MTX_GB_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4);
val = (rgbrgb->matrix[2][2] & 0xfff) << ISPPRV_RGB_MAT5_MTX_BB_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5);
val = (rgbrgb->offset[0] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT;
val |= (rgbrgb->offset[1] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1);
val = (rgbrgb->offset[2] & 0x3ff) << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2);
}
/*
* preview_config_csc - Configure Color Space Conversion (RGB to YCbYCr)
*/
static void
preview_config_csc(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_csc *csc = ¶ms->csc;
u32 val;
val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT;
val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT;
val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0);
val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT;
val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT;
val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1);
val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT;
val |= (csc->matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT;
val |= (csc->matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2);
val = (csc->offset[0] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT;
val |= (csc->offset[1] & 0xff) << ISPPRV_CSC_OFFSET_CB_SHIFT;
val |= (csc->offset[2] & 0xff) << ISPPRV_CSC_OFFSET_CR_SHIFT;
isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET);
}
/*
* preview_config_yc_range - Configure the max and min Y and C values
*/
static void
preview_config_yc_range(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_yclimit *yc = ¶ms->yclimit;
isp_reg_writel(isp,
yc->maxC << ISPPRV_SETUP_YC_MAXC_SHIFT |
yc->maxY << ISPPRV_SETUP_YC_MAXY_SHIFT |
yc->minC << ISPPRV_SETUP_YC_MINC_SHIFT |
yc->minY << ISPPRV_SETUP_YC_MINY_SHIFT,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC);
}
/*
* preview_config_dcor - Configure Couplet Defect Correction
*/
static void
preview_config_dcor(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_dcor *dcor = ¶ms->dcor;
isp_reg_writel(isp, dcor->detect_correct[0],
OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR0);
isp_reg_writel(isp, dcor->detect_correct[1],
OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR1);
isp_reg_writel(isp, dcor->detect_correct[2],
OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR2);
isp_reg_writel(isp, dcor->detect_correct[3],
OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR3);
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DCCOUP,
dcor->couplet_mode_en ? ISPPRV_PCR_DCCOUP : 0);
}
/*
* preview_enable_dcor - Enable/disable Couplet Defect Correction
*/
static void preview_enable_dcor(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DCOREN);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DCOREN);
}
/*
* preview_enable_drkframe_capture - Enable/disable Dark Frame Capture
*/
static void
preview_enable_drkframe_capture(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DRKFCAP);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DRKFCAP);
}
/*
* preview_enable_drkframe - Enable/disable Dark Frame Subtraction
*/
static void preview_enable_drkframe(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DRKFEN);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_DRKFEN);
}
/*
* preview_config_noisefilter - Configure the Noise Filter
*/
static void
preview_config_noisefilter(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_nf *nf = ¶ms->nf;
unsigned int i;
isp_reg_writel(isp, nf->spread, OMAP3_ISP_IOMEM_PREV, ISPPRV_NF);
isp_reg_writel(isp, ISPPRV_NF_TABLE_ADDR,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
for (i = 0; i < OMAP3ISP_PREV_NF_TBL_SIZE; i++) {
isp_reg_writel(isp, nf->table[i],
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
}
}
/*
* preview_enable_noisefilter - Enable/disable the Noise Filter
*/
static void
preview_enable_noisefilter(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_NFEN);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_NFEN);
}
/*
* preview_config_gammacorrn - Configure the Gamma Correction tables
*/
static void
preview_config_gammacorrn(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
const struct omap3isp_prev_gtables *gt = ¶ms->gamma;
unsigned int i;
isp_reg_writel(isp, ISPPRV_REDGAMMA_TABLE_ADDR,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
isp_reg_writel(isp, gt->red[i], OMAP3_ISP_IOMEM_PREV,
ISPPRV_SET_TBL_DATA);
isp_reg_writel(isp, ISPPRV_GREENGAMMA_TABLE_ADDR,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
isp_reg_writel(isp, gt->green[i], OMAP3_ISP_IOMEM_PREV,
ISPPRV_SET_TBL_DATA);
isp_reg_writel(isp, ISPPRV_BLUEGAMMA_TABLE_ADDR,
OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
isp_reg_writel(isp, gt->blue[i], OMAP3_ISP_IOMEM_PREV,
ISPPRV_SET_TBL_DATA);
}
/*
* preview_enable_gammacorrn - Enable/disable Gamma Correction
*
* When gamma correction is disabled, the module is bypassed and its output is
* the 8 MSB of the 10-bit input .
*/
static void
preview_enable_gammacorrn(struct isp_prev_device *prev, bool enable)
{
struct isp_device *isp = to_isp_device(prev);
if (enable)
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_GAMMA_BYPASS);
else
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_GAMMA_BYPASS);
}
/*
* preview_config_contrast - Configure the Contrast
*
* Value should be programmed before enabling the module.
*/
static void
preview_config_contrast(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT,
0xff << ISPPRV_CNT_BRT_CNT_SHIFT,
params->contrast << ISPPRV_CNT_BRT_CNT_SHIFT);
}
/*
* preview_config_brightness - Configure the Brightness
*/
static void
preview_config_brightness(struct isp_prev_device *prev,
const struct prev_params *params)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT,
0xff << ISPPRV_CNT_BRT_BRT_SHIFT,
params->brightness << ISPPRV_CNT_BRT_BRT_SHIFT);
}
/*
* preview_update_contrast - Updates the contrast.
* @contrast: Pointer to hold the current programmed contrast value.
*
* Value should be programmed before enabling the module.
*/
static void
preview_update_contrast(struct isp_prev_device *prev, u8 contrast)
{
struct prev_params *params;
unsigned long flags;
spin_lock_irqsave(&prev->params.lock, flags);
params = (prev->params.active & OMAP3ISP_PREV_CONTRAST)
? &prev->params.params[0] : &prev->params.params[1];
if (params->contrast != (contrast * ISPPRV_CONTRAST_UNITS)) {
params->contrast = contrast * ISPPRV_CONTRAST_UNITS;
params->update |= OMAP3ISP_PREV_CONTRAST;
}
spin_unlock_irqrestore(&prev->params.lock, flags);
}
/*
* preview_update_brightness - Updates the brightness in preview module.
* @brightness: Pointer to hold the current programmed brightness value.
*
*/
static void
preview_update_brightness(struct isp_prev_device *prev, u8 brightness)
{
struct prev_params *params;
unsigned long flags;
spin_lock_irqsave(&prev->params.lock, flags);
params = (prev->params.active & OMAP3ISP_PREV_BRIGHTNESS)
? &prev->params.params[0] : &prev->params.params[1];
if (params->brightness != (brightness * ISPPRV_BRIGHT_UNITS)) {
params->brightness = brightness * ISPPRV_BRIGHT_UNITS;
params->update |= OMAP3ISP_PREV_BRIGHTNESS;
}
spin_unlock_irqrestore(&prev->params.lock, flags);
}
static u32
preview_params_lock(struct isp_prev_device *prev, u32 update, bool shadow)
{
u32 active = prev->params.active;
if (shadow) {
/* Mark all shadow parameters we are going to touch as busy. */
prev->params.params[0].busy |= ~active & update;
prev->params.params[1].busy |= active & update;
} else {
/* Mark all active parameters we are going to touch as busy. */
update = (prev->params.params[0].update & active)
| (prev->params.params[1].update & ~active);
prev->params.params[0].busy |= active & update;
prev->params.params[1].busy |= ~active & update;
}
return update;
}
static void
preview_params_unlock(struct isp_prev_device *prev, u32 update, bool shadow)
{
u32 active = prev->params.active;
if (shadow) {
/* Set the update flag for shadow parameters that have been
* updated and clear the busy flag for all shadow parameters.
*/
prev->params.params[0].update |= (~active & update);
prev->params.params[1].update |= (active & update);
prev->params.params[0].busy &= active;
prev->params.params[1].busy &= ~active;
} else {
/* Clear the update flag for active parameters that have been
* applied and the busy flag for all active parameters.
*/
prev->params.params[0].update &= ~(active & update);
prev->params.params[1].update &= ~(~active & update);
prev->params.params[0].busy &= ~active;
prev->params.params[1].busy &= active;
}
}
static void preview_params_switch(struct isp_prev_device *prev)
{
u32 to_switch;
/* Switch active parameters with updated shadow parameters when the
* shadow parameter has been updated and neither the active not the
* shadow parameter is busy.
*/
to_switch = (prev->params.params[0].update & ~prev->params.active)
| (prev->params.params[1].update & prev->params.active);
to_switch &= ~(prev->params.params[0].busy |
prev->params.params[1].busy);
if (to_switch == 0)
return;
prev->params.active ^= to_switch;
/* Remove the update flag for the shadow copy of parameters we have
* switched.
*/
prev->params.params[0].update &= ~(~prev->params.active & to_switch);
prev->params.params[1].update &= ~(prev->params.active & to_switch);
}
/* preview parameters update structure */
struct preview_update {
void (*config)(struct isp_prev_device *, const struct prev_params *);
void (*enable)(struct isp_prev_device *, bool);
unsigned int param_offset;
unsigned int param_size;
unsigned int config_offset;
bool skip;
};
/* Keep the array indexed by the OMAP3ISP_PREV_* bit number. */
static const struct preview_update update_attrs[] = {
/* OMAP3ISP_PREV_LUMAENH */ {
preview_config_luma_enhancement,
preview_enable_luma_enhancement,
offsetof(struct prev_params, luma),
FIELD_SIZEOF(struct prev_params, luma),
offsetof(struct omap3isp_prev_update_config, luma),
}, /* OMAP3ISP_PREV_INVALAW */ {
NULL,
preview_enable_invalaw,
}, /* OMAP3ISP_PREV_HRZ_MED */ {
preview_config_hmed,
preview_enable_hmed,
offsetof(struct prev_params, hmed),
FIELD_SIZEOF(struct prev_params, hmed),
offsetof(struct omap3isp_prev_update_config, hmed),
}, /* OMAP3ISP_PREV_CFA */ {
preview_config_cfa,
NULL,
offsetof(struct prev_params, cfa),
FIELD_SIZEOF(struct prev_params, cfa),
offsetof(struct omap3isp_prev_update_config, cfa),
}, /* OMAP3ISP_PREV_CHROMA_SUPP */ {
preview_config_chroma_suppression,
preview_enable_chroma_suppression,
offsetof(struct prev_params, csup),
FIELD_SIZEOF(struct prev_params, csup),
offsetof(struct omap3isp_prev_update_config, csup),
}, /* OMAP3ISP_PREV_WB */ {
preview_config_whitebalance,
NULL,
offsetof(struct prev_params, wbal),
FIELD_SIZEOF(struct prev_params, wbal),
offsetof(struct omap3isp_prev_update_config, wbal),
}, /* OMAP3ISP_PREV_BLKADJ */ {
preview_config_blkadj,
NULL,
offsetof(struct prev_params, blkadj),
FIELD_SIZEOF(struct prev_params, blkadj),
offsetof(struct omap3isp_prev_update_config, blkadj),
}, /* OMAP3ISP_PREV_RGB2RGB */ {
preview_config_rgb_blending,
NULL,
offsetof(struct prev_params, rgb2rgb),
FIELD_SIZEOF(struct prev_params, rgb2rgb),
offsetof(struct omap3isp_prev_update_config, rgb2rgb),
}, /* OMAP3ISP_PREV_COLOR_CONV */ {
preview_config_csc,
NULL,
offsetof(struct prev_params, csc),
FIELD_SIZEOF(struct prev_params, csc),
offsetof(struct omap3isp_prev_update_config, csc),
}, /* OMAP3ISP_PREV_YC_LIMIT */ {
preview_config_yc_range,
NULL,
offsetof(struct prev_params, yclimit),
FIELD_SIZEOF(struct prev_params, yclimit),
offsetof(struct omap3isp_prev_update_config, yclimit),
}, /* OMAP3ISP_PREV_DEFECT_COR */ {
preview_config_dcor,
preview_enable_dcor,
offsetof(struct prev_params, dcor),
FIELD_SIZEOF(struct prev_params, dcor),
offsetof(struct omap3isp_prev_update_config, dcor),
}, /* Previously OMAP3ISP_PREV_GAMMABYPASS, not used anymore */ {
NULL,
NULL,
}, /* OMAP3ISP_PREV_DRK_FRM_CAPTURE */ {
NULL,
preview_enable_drkframe_capture,
}, /* OMAP3ISP_PREV_DRK_FRM_SUBTRACT */ {
NULL,
preview_enable_drkframe,
}, /* OMAP3ISP_PREV_LENS_SHADING */ {
NULL,
preview_enable_drkframe,
}, /* OMAP3ISP_PREV_NF */ {
preview_config_noisefilter,
preview_enable_noisefilter,
offsetof(struct prev_params, nf),
FIELD_SIZEOF(struct prev_params, nf),
offsetof(struct omap3isp_prev_update_config, nf),
}, /* OMAP3ISP_PREV_GAMMA */ {
preview_config_gammacorrn,
preview_enable_gammacorrn,
offsetof(struct prev_params, gamma),
FIELD_SIZEOF(struct prev_params, gamma),
offsetof(struct omap3isp_prev_update_config, gamma),
}, /* OMAP3ISP_PREV_CONTRAST */ {
preview_config_contrast,
NULL,
0, 0, 0, true,
}, /* OMAP3ISP_PREV_BRIGHTNESS */ {
preview_config_brightness,
NULL,
0, 0, 0, true,
},
};
/*
* preview_config - Copy and update local structure with userspace preview
* configuration.
* @prev: ISP preview engine
* @cfg: Configuration
*
* Return zero if success or -EFAULT if the configuration can't be copied from
* userspace.
*/
static int preview_config(struct isp_prev_device *prev,
struct omap3isp_prev_update_config *cfg)
{
unsigned long flags;
unsigned int i;
int rval = 0;
u32 update;
u32 active;
if (cfg->update == 0)
return 0;
/* Mark the shadow parameters we're going to update as busy. */
spin_lock_irqsave(&prev->params.lock, flags);
preview_params_lock(prev, cfg->update, true);
active = prev->params.active;
spin_unlock_irqrestore(&prev->params.lock, flags);
update = 0;
for (i = 0; i < ARRAY_SIZE(update_attrs); i++) {
const struct preview_update *attr = &update_attrs[i];
struct prev_params *params;
unsigned int bit = 1 << i;
if (attr->skip || !(cfg->update & bit))
continue;
params = &prev->params.params[!!(active & bit)];
if (cfg->flag & bit) {
void __user *from = *(void * __user *)
((void *)cfg + attr->config_offset);
void *to = (void *)params + attr->param_offset;
size_t size = attr->param_size;
if (to && from && size) {
if (copy_from_user(to, from, size)) {
rval = -EFAULT;
break;
}
}
params->features |= bit;
} else {
params->features &= ~bit;
}
update |= bit;
}
spin_lock_irqsave(&prev->params.lock, flags);
preview_params_unlock(prev, update, true);
preview_params_switch(prev);
spin_unlock_irqrestore(&prev->params.lock, flags);
return rval;
}
/*
* preview_setup_hw - Setup preview registers and/or internal memory
* @prev: pointer to preview private structure
* @update: Bitmask of parameters to setup
* @active: Bitmask of parameters active in set 0
* Note: can be called from interrupt context
* Return none
*/
static void preview_setup_hw(struct isp_prev_device *prev, u32 update,
u32 active)
{
unsigned int i;
u32 features;
if (update == 0)
return;
features = (prev->params.params[0].features & active)
| (prev->params.params[1].features & ~active);
for (i = 0; i < ARRAY_SIZE(update_attrs); i++) {
const struct preview_update *attr = &update_attrs[i];
struct prev_params *params;
unsigned int bit = 1 << i;
if (!(update & bit))
continue;
params = &prev->params.params[!(active & bit)];
if (params->features & bit) {
if (attr->config)
attr->config(prev, params);
if (attr->enable)
attr->enable(prev, true);
} else {
if (attr->enable)
attr->enable(prev, false);
}
}
}
/*
* preview_config_ycpos - Configure byte layout of YUV image.
* @mode: Indicates the required byte layout.
*/
static void
preview_config_ycpos(struct isp_prev_device *prev,
enum v4l2_mbus_pixelcode pixelcode)
{
struct isp_device *isp = to_isp_device(prev);
enum preview_ycpos_mode mode;
switch (pixelcode) {
case V4L2_MBUS_FMT_YUYV8_1X16:
mode = YCPOS_CrYCbY;
break;
case V4L2_MBUS_FMT_UYVY8_1X16:
mode = YCPOS_YCrYCb;
break;
default:
return;
}
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_YCPOS_CrYCbY,
mode << ISPPRV_PCR_YCPOS_SHIFT);
}
/*
* preview_config_averager - Enable / disable / configure averager
* @average: Average value to be configured.
*/
static void preview_config_averager(struct isp_prev_device *prev, u8 average)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_writel(isp, ISPPRV_AVE_EVENDIST_2 << ISPPRV_AVE_EVENDIST_SHIFT |
ISPPRV_AVE_ODDDIST_2 << ISPPRV_AVE_ODDDIST_SHIFT |
average, OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE);
}
/*
* preview_config_input_format - Configure the input format
* @prev: The preview engine
* @info: Sink pad format information
*
* Enable and configure CFA interpolation for Bayer formats and disable it for
* greyscale formats.
*
* The CFA table is organised in four blocks, one per Bayer component. The
* hardware expects blocks to follow the Bayer order of the input data, while
* the driver stores the table in GRBG order in memory. The blocks need to be
* reordered to support non-GRBG Bayer patterns.
*/
static void preview_config_input_format(struct isp_prev_device *prev,
const struct isp_format_info *info)
{
struct isp_device *isp = to_isp_device(prev);
struct prev_params *params;
if (info->width == 8)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_WIDTH);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_WIDTH);
switch (info->flavor) {
case V4L2_MBUS_FMT_SGRBG8_1X8:
prev->params.cfa_order = 0;
break;
case V4L2_MBUS_FMT_SRGGB8_1X8:
prev->params.cfa_order = 1;
break;
case V4L2_MBUS_FMT_SBGGR8_1X8:
prev->params.cfa_order = 2;
break;
case V4L2_MBUS_FMT_SGBRG8_1X8:
prev->params.cfa_order = 3;
break;
default:
/* Disable CFA for non-Bayer formats. */
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_CFAEN);
return;
}
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_CFAEN);
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_CFAFMT_MASK, ISPPRV_PCR_CFAFMT_BAYER);
params = (prev->params.active & OMAP3ISP_PREV_CFA)
? &prev->params.params[0] : &prev->params.params[1];
preview_config_cfa(prev, params);
}
/*
* preview_config_input_size - Configure the input frame size
*
* The preview engine crops several rows and columns internally depending on
* which processing blocks are enabled. The driver assumes all those blocks are
* enabled when reporting source pad formats to userspace. If this assumption is
* not true, rows and columns must be manually cropped at the preview engine
* input to avoid overflows at the end of lines and frames.
*
* See the explanation at the PREV_MARGIN_* definitions for more details.
*/
static void preview_config_input_size(struct isp_prev_device *prev, u32 active)
{
const struct v4l2_mbus_framefmt *format = &prev->formats[PREV_PAD_SINK];
struct isp_device *isp = to_isp_device(prev);
unsigned int sph = prev->crop.left;
unsigned int eph = prev->crop.left + prev->crop.width - 1;
unsigned int slv = prev->crop.top;
unsigned int elv = prev->crop.top + prev->crop.height - 1;
u32 features;
if (format->code != V4L2_MBUS_FMT_Y8_1X8 &&
format->code != V4L2_MBUS_FMT_Y10_1X10) {
sph -= 2;
eph += 2;
slv -= 2;
elv += 2;
}
features = (prev->params.params[0].features & active)
| (prev->params.params[1].features & ~active);
if (features & (OMAP3ISP_PREV_DEFECT_COR | OMAP3ISP_PREV_NF)) {
sph -= 2;
eph += 2;
slv -= 2;
elv += 2;
}
if (features & OMAP3ISP_PREV_HRZ_MED) {
sph -= 2;
eph += 2;
}
if (features & (OMAP3ISP_PREV_CHROMA_SUPP | OMAP3ISP_PREV_LUMAENH))
sph -= 2;
isp_reg_writel(isp, (sph << ISPPRV_HORZ_INFO_SPH_SHIFT) | eph,
OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO);
isp_reg_writel(isp, (slv << ISPPRV_VERT_INFO_SLV_SHIFT) | elv,
OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO);
}
/*
* preview_config_inlineoffset - Configures the Read address line offset.
* @prev: Preview module
* @offset: Line offset
*
* According to the TRM, the line offset must be aligned on a 32 bytes boundary.
* However, a hardware bug requires the memory start address to be aligned on a
* 64 bytes boundary, so the offset probably should be aligned on 64 bytes as
* well.
*/
static void
preview_config_inlineoffset(struct isp_prev_device *prev, u32 offset)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
ISPPRV_RADR_OFFSET);
}
/*
* preview_set_inaddr - Sets memory address of input frame.
* @addr: 32bit memory address aligned on 32byte boundary.
*
* Configures the memory address from which the input frame is to be read.
*/
static void preview_set_inaddr(struct isp_prev_device *prev, u32 addr)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_RSDR_ADDR);
}
/*
* preview_config_outlineoffset - Configures the Write address line offset.
* @offset: Line Offset for the preview output.
*
* The offset must be a multiple of 32 bytes.
*/
static void preview_config_outlineoffset(struct isp_prev_device *prev,
u32 offset)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
ISPPRV_WADD_OFFSET);
}
/*
* preview_set_outaddr - Sets the memory address to store output frame
* @addr: 32bit memory address aligned on 32byte boundary.
*
* Configures the memory address to which the output frame is written.
*/
static void preview_set_outaddr(struct isp_prev_device *prev, u32 addr)
{
struct isp_device *isp = to_isp_device(prev);
isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR);
}
static void preview_adjust_bandwidth(struct isp_prev_device *prev)
{
struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity);
struct isp_device *isp = to_isp_device(prev);
const struct v4l2_mbus_framefmt *ifmt = &prev->formats[PREV_PAD_SINK];
unsigned long l3_ick = pipe->l3_ick;
struct v4l2_fract *timeperframe;
unsigned int cycles_per_frame;
unsigned int requests_per_frame;
unsigned int cycles_per_request;
unsigned int minimum;
unsigned int maximum;
unsigned int value;
if (prev->input != PREVIEW_INPUT_MEMORY) {
isp_reg_clr(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP,
ISPSBL_SDR_REQ_PRV_EXP_MASK);
return;
}
/* Compute the minimum number of cycles per request, based on the
* pipeline maximum data rate. This is an absolute lower bound if we
* don't want SBL overflows, so round the value up.
*/
cycles_per_request = div_u64((u64)l3_ick / 2 * 256 + pipe->max_rate - 1,
pipe->max_rate);
minimum = DIV_ROUND_UP(cycles_per_request, 32);
/* Compute the maximum number of cycles per request, based on the
* requested frame rate. This is a soft upper bound to achieve a frame
* rate equal or higher than the requested value, so round the value
* down.
*/
timeperframe = &pipe->max_timeperframe;
requests_per_frame = DIV_ROUND_UP(ifmt->width * 2, 256) * ifmt->height;
cycles_per_frame = div_u64((u64)l3_ick * timeperframe->numerator,
timeperframe->denominator);
cycles_per_request = cycles_per_frame / requests_per_frame;
maximum = cycles_per_request / 32;
value = max(minimum, maximum);
dev_dbg(isp->dev, "%s: cycles per request = %u\n", __func__, value);
isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP,
ISPSBL_SDR_REQ_PRV_EXP_MASK,
value << ISPSBL_SDR_REQ_PRV_EXP_SHIFT);
}
/*
* omap3isp_preview_busy - Gets busy state of preview module.
*/
int omap3isp_preview_busy(struct isp_prev_device *prev)
{
struct isp_device *isp = to_isp_device(prev);
return isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR)
& ISPPRV_PCR_BUSY;
}
/*
* omap3isp_preview_restore_context - Restores the values of preview registers
*/
void omap3isp_preview_restore_context(struct isp_device *isp)
{
struct isp_prev_device *prev = &isp->isp_prev;
const u32 update = OMAP3ISP_PREV_FEATURES_END - 1;
prev->params.params[0].update = prev->params.active & update;
prev->params.params[1].update = ~prev->params.active & update;
preview_setup_hw(prev, update, prev->params.active);
prev->params.params[0].update = 0;
prev->params.params[1].update = 0;
}
/*
* preview_print_status - Dump preview module registers to the kernel log
*/
#define PREV_PRINT_REGISTER(isp, name)\
dev_dbg(isp->dev, "###PRV " #name "=0x%08x\n", \
isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_##name))
static void preview_print_status(struct isp_prev_device *prev)
{
struct isp_device *isp = to_isp_device(prev);
dev_dbg(isp->dev, "-------------Preview Register dump----------\n");
PREV_PRINT_REGISTER(isp, PCR);
PREV_PRINT_REGISTER(isp, HORZ_INFO);
PREV_PRINT_REGISTER(isp, VERT_INFO);
PREV_PRINT_REGISTER(isp, RSDR_ADDR);
PREV_PRINT_REGISTER(isp, RADR_OFFSET);
PREV_PRINT_REGISTER(isp, DSDR_ADDR);
PREV_PRINT_REGISTER(isp, DRKF_OFFSET);
PREV_PRINT_REGISTER(isp, WSDR_ADDR);
PREV_PRINT_REGISTER(isp, WADD_OFFSET);
PREV_PRINT_REGISTER(isp, AVE);
PREV_PRINT_REGISTER(isp, HMED);
PREV_PRINT_REGISTER(isp, NF);
PREV_PRINT_REGISTER(isp, WB_DGAIN);
PREV_PRINT_REGISTER(isp, WBGAIN);
PREV_PRINT_REGISTER(isp, WBSEL);
PREV_PRINT_REGISTER(isp, CFA);
PREV_PRINT_REGISTER(isp, BLKADJOFF);
PREV_PRINT_REGISTER(isp, RGB_MAT1);
PREV_PRINT_REGISTER(isp, RGB_MAT2);
PREV_PRINT_REGISTER(isp, RGB_MAT3);
PREV_PRINT_REGISTER(isp, RGB_MAT4);
PREV_PRINT_REGISTER(isp, RGB_MAT5);
PREV_PRINT_REGISTER(isp, RGB_OFF1);
PREV_PRINT_REGISTER(isp, RGB_OFF2);
PREV_PRINT_REGISTER(isp, CSC0);
PREV_PRINT_REGISTER(isp, CSC1);
PREV_PRINT_REGISTER(isp, CSC2);
PREV_PRINT_REGISTER(isp, CSC_OFFSET);
PREV_PRINT_REGISTER(isp, CNT_BRT);
PREV_PRINT_REGISTER(isp, CSUP);
PREV_PRINT_REGISTER(isp, SETUP_YC);
PREV_PRINT_REGISTER(isp, SET_TBL_ADDR);
PREV_PRINT_REGISTER(isp, CDC_THR0);
PREV_PRINT_REGISTER(isp, CDC_THR1);
PREV_PRINT_REGISTER(isp, CDC_THR2);
PREV_PRINT_REGISTER(isp, CDC_THR3);
dev_dbg(isp->dev, "--------------------------------------------\n");
}
/*
* preview_init_params - init image processing parameters.
* @prev: pointer to previewer private structure
*/
static void preview_init_params(struct isp_prev_device *prev)
{
struct prev_params *params;
unsigned int i;
spin_lock_init(&prev->params.lock);
prev->params.active = ~0;
prev->params.params[0].busy = 0;
prev->params.params[0].update = OMAP3ISP_PREV_FEATURES_END - 1;
prev->params.params[1].busy = 0;
prev->params.params[1].update = 0;
params = &prev->params.params[0];
/* Init values */
params->contrast = ISPPRV_CONTRAST_DEF * ISPPRV_CONTRAST_UNITS;
params->brightness = ISPPRV_BRIGHT_DEF * ISPPRV_BRIGHT_UNITS;
params->cfa.format = OMAP3ISP_CFAFMT_BAYER;
memcpy(params->cfa.table, cfa_coef_table,
sizeof(params->cfa.table));
params->cfa.gradthrs_horz = FLR_CFA_GRADTHRS_HORZ;
params->cfa.gradthrs_vert = FLR_CFA_GRADTHRS_VERT;
params->csup.gain = FLR_CSUP_GAIN;
params->csup.thres = FLR_CSUP_THRES;
params->csup.hypf_en = 0;
memcpy(params->luma.table, luma_enhance_table,
sizeof(params->luma.table));
params->nf.spread = FLR_NF_STRGTH;
memcpy(params->nf.table, noise_filter_table, sizeof(params->nf.table));
params->dcor.couplet_mode_en = 1;
for (i = 0; i < OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS; i++)
params->dcor.detect_correct[i] = DEF_DETECT_CORRECT_VAL;
memcpy(params->gamma.blue, gamma_table, sizeof(params->gamma.blue));
memcpy(params->gamma.green, gamma_table, sizeof(params->gamma.green));
memcpy(params->gamma.red, gamma_table, sizeof(params->gamma.red));
params->wbal.dgain = FLR_WBAL_DGAIN;
params->wbal.coef0 = FLR_WBAL_COEF;
params->wbal.coef1 = FLR_WBAL_COEF;
params->wbal.coef2 = FLR_WBAL_COEF;
params->wbal.coef3 = FLR_WBAL_COEF;
params->blkadj.red = FLR_BLKADJ_RED;
params->blkadj.green = FLR_BLKADJ_GREEN;
params->blkadj.blue = FLR_BLKADJ_BLUE;
params->rgb2rgb = flr_rgb2rgb;
params->csc = flr_prev_csc;
params->yclimit.minC = ISPPRV_YC_MIN;
params->yclimit.maxC = ISPPRV_YC_MAX;
params->yclimit.minY = ISPPRV_YC_MIN;
params->yclimit.maxY = ISPPRV_YC_MAX;
params->features = OMAP3ISP_PREV_CFA | OMAP3ISP_PREV_DEFECT_COR
| OMAP3ISP_PREV_NF | OMAP3ISP_PREV_GAMMA
| OMAP3ISP_PREV_BLKADJ | OMAP3ISP_PREV_YC_LIMIT
| OMAP3ISP_PREV_RGB2RGB | OMAP3ISP_PREV_COLOR_CONV
| OMAP3ISP_PREV_WB | OMAP3ISP_PREV_BRIGHTNESS
| OMAP3ISP_PREV_CONTRAST;
}
/*
* preview_max_out_width - Handle previewer hardware ouput limitations
* @isp_revision : ISP revision
* returns maximum width output for current isp revision
*/
static unsigned int preview_max_out_width(struct isp_prev_device *prev)
{
struct isp_device *isp = to_isp_device(prev);
switch (isp->revision) {
case ISP_REVISION_1_0:
return PREV_MAX_OUT_WIDTH_REV_1;
case ISP_REVISION_2_0:
default:
return PREV_MAX_OUT_WIDTH_REV_2;
case ISP_REVISION_15_0:
return PREV_MAX_OUT_WIDTH_REV_15;
}
}
static void preview_configure(struct isp_prev_device *prev)
{
struct isp_device *isp = to_isp_device(prev);
const struct isp_format_info *info;
struct v4l2_mbus_framefmt *format;
unsigned long flags;
u32 update;
u32 active;
spin_lock_irqsave(&prev->params.lock, flags);
/* Mark all active parameters we are going to touch as busy. */
update = preview_params_lock(prev, 0, false);
active = prev->params.active;
spin_unlock_irqrestore(&prev->params.lock, flags);
/* PREV_PAD_SINK */
format = &prev->formats[PREV_PAD_SINK];
info = omap3isp_video_format_info(format->code);
preview_adjust_bandwidth(prev);
preview_config_input_format(prev, info);
preview_config_input_size(prev, active);
if (prev->input == PREVIEW_INPUT_CCDC)
preview_config_inlineoffset(prev, 0);
else
preview_config_inlineoffset(prev, ALIGN(format->width, 0x20) *
info->bpp);
preview_setup_hw(prev, update, active);
/* PREV_PAD_SOURCE */
format = &prev->formats[PREV_PAD_SOURCE];
if (prev->output & PREVIEW_OUTPUT_MEMORY)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_SDRPORT);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_SDRPORT);
if (prev->output & PREVIEW_OUTPUT_RESIZER)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_RSZPORT);
else
isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_RSZPORT);
if (prev->output & PREVIEW_OUTPUT_MEMORY)
preview_config_outlineoffset(prev,
ALIGN(format->width, 0x10) * 2);
preview_config_averager(prev, 0);
preview_config_ycpos(prev, format->code);
spin_lock_irqsave(&prev->params.lock, flags);
preview_params_unlock(prev, update, false);
spin_unlock_irqrestore(&prev->params.lock, flags);
}
/* -----------------------------------------------------------------------------
* Interrupt handling
*/
static void preview_enable_oneshot(struct isp_prev_device *prev)
{
struct isp_device *isp = to_isp_device(prev);
/* The PCR.SOURCE bit is automatically reset to 0 when the PCR.ENABLE
* bit is set. As the preview engine is used in single-shot mode, we
* need to set PCR.SOURCE before enabling the preview engine.
*/
if (prev->input == PREVIEW_INPUT_MEMORY)
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_SOURCE);
isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
ISPPRV_PCR_EN | ISPPRV_PCR_ONESHOT);
}
void omap3isp_preview_isr_frame_sync(struct isp_prev_device *prev)
{
/*
* If ISP_VIDEO_DMAQUEUE_QUEUED is set, DMA queue had an underrun
* condition, the module was paused and now we have a buffer queued
* on the output again. Restart the pipeline if running in continuous
* mode.
*/
if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS &&
prev->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED) {
preview_enable_oneshot(prev);
isp_video_dmaqueue_flags_clr(&prev->video_out);
}
}
static void preview_isr_buffer(struct isp_prev_device *prev)
{
struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity);
struct isp_buffer *buffer;
int restart = 0;
if (prev->input == PREVIEW_INPUT_MEMORY) {
buffer = omap3isp_video_buffer_next(&prev->video_in);
if (buffer != NULL)
preview_set_inaddr(prev, buffer->isp_addr);
pipe->state |= ISP_PIPELINE_IDLE_INPUT;
}
if (prev->output & PREVIEW_OUTPUT_MEMORY) {
buffer = omap3isp_video_buffer_next(&prev->video_out);
if (buffer != NULL) {
preview_set_outaddr(prev, buffer->isp_addr);
restart = 1;
}
pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
}
switch (prev->state) {
case ISP_PIPELINE_STREAM_SINGLESHOT:
if (isp_pipeline_ready(pipe))
omap3isp_pipeline_set_stream(pipe,
ISP_PIPELINE_STREAM_SINGLESHOT);
break;
case ISP_PIPELINE_STREAM_CONTINUOUS:
/* If an underrun occurs, the video queue operation handler will
* restart the preview engine. Otherwise restart it immediately.
*/
if (restart)
preview_enable_oneshot(prev);
break;
case ISP_PIPELINE_STREAM_STOPPED:
default:
return;
}
}
/*
* omap3isp_preview_isr - ISP preview engine interrupt handler
*
* Manage the preview engine video buffers and configure shadowed registers.
*/
void omap3isp_preview_isr(struct isp_prev_device *prev)
{
unsigned long flags;
u32 update;
u32 active;
if (omap3isp_module_sync_is_stopping(&prev->wait, &prev->stopping))
return;
spin_lock_irqsave(&prev->params.lock, flags);
preview_params_switch(prev);
update = preview_params_lock(prev, 0, false);
active = prev->params.active;
spin_unlock_irqrestore(&prev->params.lock, flags);
preview_setup_hw(prev, update, active);
preview_config_input_size(prev, active);
if (prev->input == PREVIEW_INPUT_MEMORY ||
prev->output & PREVIEW_OUTPUT_MEMORY)
preview_isr_buffer(prev);
else if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS)
preview_enable_oneshot(prev);
spin_lock_irqsave(&prev->params.lock, flags);
preview_params_unlock(prev, update, false);
spin_unlock_irqrestore(&prev->params.lock, flags);
}
/* -----------------------------------------------------------------------------
* ISP video operations
*/
static int preview_video_queue(struct isp_video *video,
struct isp_buffer *buffer)
{
struct isp_prev_device *prev = &video->isp->isp_prev;
if (video->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
preview_set_inaddr(prev, buffer->isp_addr);
if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
preview_set_outaddr(prev, buffer->isp_addr);
return 0;
}
static const struct isp_video_operations preview_video_ops = {
.queue = preview_video_queue,
};
/* -----------------------------------------------------------------------------
* V4L2 subdev operations
*/
/*
* preview_s_ctrl - Handle set control subdev method
* @ctrl: pointer to v4l2 control structure
*/
static int preview_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct isp_prev_device *prev =
container_of(ctrl->handler, struct isp_prev_device, ctrls);
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
preview_update_brightness(prev, ctrl->val);
break;
case V4L2_CID_CONTRAST:
preview_update_contrast(prev, ctrl->val);
break;
}
return 0;
}
static const struct v4l2_ctrl_ops preview_ctrl_ops = {
.s_ctrl = preview_s_ctrl,
};
/*
* preview_ioctl - Handle preview module private ioctl's
* @prev: pointer to preview context structure
* @cmd: configuration command
* @arg: configuration argument
* return -EINVAL or zero on success
*/
static long preview_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
switch (cmd) {
case VIDIOC_OMAP3ISP_PRV_CFG:
return preview_config(prev, arg);
default:
return -ENOIOCTLCMD;
}
}
/*
* preview_set_stream - Enable/Disable streaming on preview subdev
* @sd : pointer to v4l2 subdev structure
* @enable: 1 == Enable, 0 == Disable
* return -EINVAL or zero on success
*/
static int preview_set_stream(struct v4l2_subdev *sd, int enable)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
struct isp_video *video_out = &prev->video_out;
struct isp_device *isp = to_isp_device(prev);
struct device *dev = to_device(prev);
if (prev->state == ISP_PIPELINE_STREAM_STOPPED) {
if (enable == ISP_PIPELINE_STREAM_STOPPED)
return 0;
omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_PREVIEW);
preview_configure(prev);
atomic_set(&prev->stopping, 0);
preview_print_status(prev);
}
switch (enable) {
case ISP_PIPELINE_STREAM_CONTINUOUS:
if (prev->output & PREVIEW_OUTPUT_MEMORY)
omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
if (video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED ||
!(prev->output & PREVIEW_OUTPUT_MEMORY))
preview_enable_oneshot(prev);
isp_video_dmaqueue_flags_clr(video_out);
break;
case ISP_PIPELINE_STREAM_SINGLESHOT:
if (prev->input == PREVIEW_INPUT_MEMORY)
omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_READ);
if (prev->output & PREVIEW_OUTPUT_MEMORY)
omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
preview_enable_oneshot(prev);
break;
case ISP_PIPELINE_STREAM_STOPPED:
if (omap3isp_module_sync_idle(&sd->entity, &prev->wait,
&prev->stopping))
dev_dbg(dev, "%s: stop timeout.\n", sd->name);
omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_READ);
omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_PREVIEW);
isp_video_dmaqueue_flags_clr(video_out);
break;
}
prev->state = enable;
return 0;
}
static struct v4l2_mbus_framefmt *
__preview_get_format(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh,
unsigned int pad, enum v4l2_subdev_format_whence which)
{
if (which == V4L2_SUBDEV_FORMAT_TRY)
return v4l2_subdev_get_try_format(fh, pad);
else
return &prev->formats[pad];
}
static struct v4l2_rect *
__preview_get_crop(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh,
enum v4l2_subdev_format_whence which)
{
if (which == V4L2_SUBDEV_FORMAT_TRY)
return v4l2_subdev_get_try_crop(fh, PREV_PAD_SINK);
else
return &prev->crop;
}
/* previewer format descriptions */
static const unsigned int preview_input_fmts[] = {
V4L2_MBUS_FMT_Y8_1X8,
V4L2_MBUS_FMT_SGRBG8_1X8,
V4L2_MBUS_FMT_SRGGB8_1X8,
V4L2_MBUS_FMT_SBGGR8_1X8,
V4L2_MBUS_FMT_SGBRG8_1X8,
V4L2_MBUS_FMT_Y10_1X10,
V4L2_MBUS_FMT_SGRBG10_1X10,
V4L2_MBUS_FMT_SRGGB10_1X10,
V4L2_MBUS_FMT_SBGGR10_1X10,
V4L2_MBUS_FMT_SGBRG10_1X10,
};
static const unsigned int preview_output_fmts[] = {
V4L2_MBUS_FMT_UYVY8_1X16,
V4L2_MBUS_FMT_YUYV8_1X16,
};
/*
* preview_try_format - Validate a format
* @prev: ISP preview engine
* @fh: V4L2 subdev file handle
* @pad: pad number
* @fmt: format to be validated
* @which: try/active format selector
*
* Validate and adjust the given format for the given pad based on the preview
* engine limits and the format and crop rectangles on other pads.
*/
static void preview_try_format(struct isp_prev_device *prev,
struct v4l2_subdev_fh *fh, unsigned int pad,
struct v4l2_mbus_framefmt *fmt,
enum v4l2_subdev_format_whence which)
{
enum v4l2_mbus_pixelcode pixelcode;
struct v4l2_rect *crop;
unsigned int i;
switch (pad) {
case PREV_PAD_SINK:
/* When reading data from the CCDC, the input size has already
* been mangled by the CCDC output pad so it can be accepted
* as-is.
*
* When reading data from memory, clamp the requested width and
* height. The TRM doesn't specify a minimum input height, make
* sure we got enough lines to enable the noise filter and color
* filter array interpolation.
*/
if (prev->input == PREVIEW_INPUT_MEMORY) {
fmt->width = clamp_t(u32, fmt->width, PREV_MIN_IN_WIDTH,
preview_max_out_width(prev));
fmt->height = clamp_t(u32, fmt->height,
PREV_MIN_IN_HEIGHT,
PREV_MAX_IN_HEIGHT);
}
fmt->colorspace = V4L2_COLORSPACE_SRGB;
for (i = 0; i < ARRAY_SIZE(preview_input_fmts); i++) {
if (fmt->code == preview_input_fmts[i])
break;
}
/* If not found, use SGRBG10 as default */
if (i >= ARRAY_SIZE(preview_input_fmts))
fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
break;
case PREV_PAD_SOURCE:
pixelcode = fmt->code;
*fmt = *__preview_get_format(prev, fh, PREV_PAD_SINK, which);
switch (pixelcode) {
case V4L2_MBUS_FMT_YUYV8_1X16:
case V4L2_MBUS_FMT_UYVY8_1X16:
fmt->code = pixelcode;
break;
default:
fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
break;
}
/* The preview module output size is configurable through the
* averager (horizontal scaling by 1/1, 1/2, 1/4 or 1/8). This
* is not supported yet, hardcode the output size to the crop
* rectangle size.
*/
crop = __preview_get_crop(prev, fh, which);
fmt->width = crop->width;
fmt->height = crop->height;
fmt->colorspace = V4L2_COLORSPACE_JPEG;
break;
}
fmt->field = V4L2_FIELD_NONE;
}
/*
* preview_try_crop - Validate a crop rectangle
* @prev: ISP preview engine
* @sink: format on the sink pad
* @crop: crop rectangle to be validated
*
* The preview engine crops lines and columns for its internal operation,
* depending on which filters are enabled. Enforce minimum crop margins to
* handle that transparently for userspace.
*
* See the explanation at the PREV_MARGIN_* definitions for more details.
*/
static void preview_try_crop(struct isp_prev_device *prev,
const struct v4l2_mbus_framefmt *sink,
struct v4l2_rect *crop)
{
unsigned int left = PREV_MARGIN_LEFT;
unsigned int right = sink->width - PREV_MARGIN_RIGHT;
unsigned int top = PREV_MARGIN_TOP;
unsigned int bottom = sink->height - PREV_MARGIN_BOTTOM;
/* When processing data on-the-fly from the CCDC, at least 2 pixels must
* be cropped from the left and right sides of the image. As we don't
* know which filters will be enabled, increase the left and right
* margins by two.
*/
if (prev->input == PREVIEW_INPUT_CCDC) {
left += 2;
right -= 2;
}
/* The CFA filter crops 4 lines and 4 columns in Bayer mode, and 2 lines
* and no columns in other modes. Increase the margins based on the sink
* format.
*/
if (sink->code != V4L2_MBUS_FMT_Y8_1X8 &&
sink->code != V4L2_MBUS_FMT_Y10_1X10) {
left += 2;
right -= 2;
top += 2;
bottom -= 2;
}
/* Restrict left/top to even values to keep the Bayer pattern. */
crop->left &= ~1;
crop->top &= ~1;
crop->left = clamp_t(u32, crop->left, left, right - PREV_MIN_OUT_WIDTH);
crop->top = clamp_t(u32, crop->top, top, bottom - PREV_MIN_OUT_HEIGHT);
crop->width = clamp_t(u32, crop->width, PREV_MIN_OUT_WIDTH,
right - crop->left);
crop->height = clamp_t(u32, crop->height, PREV_MIN_OUT_HEIGHT,
bottom - crop->top);
}
/*
* preview_enum_mbus_code - Handle pixel format enumeration
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @code : pointer to v4l2_subdev_mbus_code_enum structure
* return -EINVAL or zero on success
*/
static int preview_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh,
struct v4l2_subdev_mbus_code_enum *code)
{
switch (code->pad) {
case PREV_PAD_SINK:
if (code->index >= ARRAY_SIZE(preview_input_fmts))
return -EINVAL;
code->code = preview_input_fmts[code->index];
break;
case PREV_PAD_SOURCE:
if (code->index >= ARRAY_SIZE(preview_output_fmts))
return -EINVAL;
code->code = preview_output_fmts[code->index];
break;
default:
return -EINVAL;
}
return 0;
}
static int preview_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh,
struct v4l2_subdev_frame_size_enum *fse)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt format;
if (fse->index != 0)
return -EINVAL;
format.code = fse->code;
format.width = 1;
format.height = 1;
preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
fse->min_width = format.width;
fse->min_height = format.height;
if (format.code != fse->code)
return -EINVAL;
format.code = fse->code;
format.width = -1;
format.height = -1;
preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
fse->max_width = format.width;
fse->max_height = format.height;
return 0;
}
/*
* preview_get_selection - Retrieve a selection rectangle on a pad
* @sd: ISP preview V4L2 subdevice
* @fh: V4L2 subdev file handle
* @sel: Selection rectangle
*
* The only supported rectangles are the crop rectangles on the sink pad.
*
* Return 0 on success or a negative error code otherwise.
*/
static int preview_get_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh,
struct v4l2_subdev_selection *sel)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *format;
if (sel->pad != PREV_PAD_SINK)
return -EINVAL;
switch (sel->target) {
case V4L2_SEL_TGT_CROP_BOUNDS:
sel->r.left = 0;
sel->r.top = 0;
sel->r.width = INT_MAX;
sel->r.height = INT_MAX;
format = __preview_get_format(prev, fh, PREV_PAD_SINK,
sel->which);
preview_try_crop(prev, format, &sel->r);
break;
case V4L2_SEL_TGT_CROP:
sel->r = *__preview_get_crop(prev, fh, sel->which);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* preview_set_selection - Set a selection rectangle on a pad
* @sd: ISP preview V4L2 subdevice
* @fh: V4L2 subdev file handle
* @sel: Selection rectangle
*
* The only supported rectangle is the actual crop rectangle on the sink pad.
*
* Return 0 on success or a negative error code otherwise.
*/
static int preview_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh,
struct v4l2_subdev_selection *sel)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *format;
if (sel->target != V4L2_SEL_TGT_CROP ||
sel->pad != PREV_PAD_SINK)
return -EINVAL;
/* The crop rectangle can't be changed while streaming. */
if (prev->state != ISP_PIPELINE_STREAM_STOPPED)
return -EBUSY;
/* Modifying the crop rectangle always changes the format on the source
* pad. If the KEEP_CONFIG flag is set, just return the current crop
* rectangle.
*/
if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
sel->r = *__preview_get_crop(prev, fh, sel->which);
return 0;
}
format = __preview_get_format(prev, fh, PREV_PAD_SINK, sel->which);
preview_try_crop(prev, format, &sel->r);
*__preview_get_crop(prev, fh, sel->which) = sel->r;
/* Update the source format. */
format = __preview_get_format(prev, fh, PREV_PAD_SOURCE, sel->which);
preview_try_format(prev, fh, PREV_PAD_SOURCE, format, sel->which);
return 0;
}
/*
* preview_get_format - Handle get format by pads subdev method
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @fmt: pointer to v4l2 subdev format structure
* return -EINVAL or zero on success
*/
static int preview_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
struct v4l2_subdev_format *fmt)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *format;
format = __preview_get_format(prev, fh, fmt->pad, fmt->which);
if (format == NULL)
return -EINVAL;
fmt->format = *format;
return 0;
}
/*
* preview_set_format - Handle set format by pads subdev method
* @sd : pointer to v4l2 subdev structure
* @fh : V4L2 subdev file handle
* @fmt: pointer to v4l2 subdev format structure
* return -EINVAL or zero on success
*/
static int preview_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
struct v4l2_subdev_format *fmt)
{
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *format;
struct v4l2_rect *crop;
format = __preview_get_format(prev, fh, fmt->pad, fmt->which);
if (format == NULL)
return -EINVAL;
preview_try_format(prev, fh, fmt->pad, &fmt->format, fmt->which);
*format = fmt->format;
/* Propagate the format from sink to source */
if (fmt->pad == PREV_PAD_SINK) {
/* Reset the crop rectangle. */
crop = __preview_get_crop(prev, fh, fmt->which);
crop->left = 0;
crop->top = 0;
crop->width = fmt->format.width;
crop->height = fmt->format.height;
preview_try_crop(prev, &fmt->format, crop);
/* Update the source format. */
format = __preview_get_format(prev, fh, PREV_PAD_SOURCE,
fmt->which);
preview_try_format(prev, fh, PREV_PAD_SOURCE, format,
fmt->which);
}
return 0;
}
/*
* preview_init_formats - Initialize formats on all pads
* @sd: ISP preview V4L2 subdevice
* @fh: V4L2 subdev file handle
*
* Initialize all pad formats with default values. If fh is not NULL, try
* formats are initialized on the file handle. Otherwise active formats are
* initialized on the device.
*/
static int preview_init_formats(struct v4l2_subdev *sd,
struct v4l2_subdev_fh *fh)
{
struct v4l2_subdev_format format;
memset(&format, 0, sizeof(format));
format.pad = PREV_PAD_SINK;
format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
format.format.width = 4096;
format.format.height = 4096;
preview_set_format(sd, fh, &format);
return 0;
}
/* subdev core operations */
static const struct v4l2_subdev_core_ops preview_v4l2_core_ops = {
.ioctl = preview_ioctl,
};
/* subdev video operations */
static const struct v4l2_subdev_video_ops preview_v4l2_video_ops = {
.s_stream = preview_set_stream,
};
/* subdev pad operations */
static const struct v4l2_subdev_pad_ops preview_v4l2_pad_ops = {
.enum_mbus_code = preview_enum_mbus_code,
.enum_frame_size = preview_enum_frame_size,
.get_fmt = preview_get_format,
.set_fmt = preview_set_format,
.get_selection = preview_get_selection,
.set_selection = preview_set_selection,
};
/* subdev operations */
static const struct v4l2_subdev_ops preview_v4l2_ops = {
.core = &preview_v4l2_core_ops,
.video = &preview_v4l2_video_ops,
.pad = &preview_v4l2_pad_ops,
};
/* subdev internal operations */
static const struct v4l2_subdev_internal_ops preview_v4l2_internal_ops = {
.open = preview_init_formats,
};
/* -----------------------------------------------------------------------------
* Media entity operations
*/
/*
* preview_link_setup - Setup previewer connections.
* @entity : Pointer to media entity structure
* @local : Pointer to local pad array
* @remote : Pointer to remote pad array
* @flags : Link flags
* return -EINVAL or zero on success
*/
static int preview_link_setup(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags)
{
struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
switch (local->index | media_entity_type(remote->entity)) {
case PREV_PAD_SINK | MEDIA_ENT_T_DEVNODE:
/* read from memory */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (prev->input == PREVIEW_INPUT_CCDC)
return -EBUSY;
prev->input = PREVIEW_INPUT_MEMORY;
} else {
if (prev->input == PREVIEW_INPUT_MEMORY)
prev->input = PREVIEW_INPUT_NONE;
}
break;
case PREV_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
/* read from ccdc */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (prev->input == PREVIEW_INPUT_MEMORY)
return -EBUSY;
prev->input = PREVIEW_INPUT_CCDC;
} else {
if (prev->input == PREVIEW_INPUT_CCDC)
prev->input = PREVIEW_INPUT_NONE;
}
break;
/*
* The ISP core doesn't support pipelines with multiple video outputs.
* Revisit this when it will be implemented, and return -EBUSY for now.
*/
case PREV_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
/* write to memory */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (prev->output & ~PREVIEW_OUTPUT_MEMORY)
return -EBUSY;
prev->output |= PREVIEW_OUTPUT_MEMORY;
} else {
prev->output &= ~PREVIEW_OUTPUT_MEMORY;
}
break;
case PREV_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
/* write to resizer */
if (flags & MEDIA_LNK_FL_ENABLED) {
if (prev->output & ~PREVIEW_OUTPUT_RESIZER)
return -EBUSY;
prev->output |= PREVIEW_OUTPUT_RESIZER;
} else {
prev->output &= ~PREVIEW_OUTPUT_RESIZER;
}
break;
default:
return -EINVAL;
}
return 0;
}
/* media operations */
static const struct media_entity_operations preview_media_ops = {
.link_setup = preview_link_setup,
.link_validate = v4l2_subdev_link_validate,
};
void omap3isp_preview_unregister_entities(struct isp_prev_device *prev)
{
v4l2_device_unregister_subdev(&prev->subdev);
omap3isp_video_unregister(&prev->video_in);
omap3isp_video_unregister(&prev->video_out);
}
int omap3isp_preview_register_entities(struct isp_prev_device *prev,
struct v4l2_device *vdev)
{
int ret;
/* Register the subdev and video nodes. */
ret = v4l2_device_register_subdev(vdev, &prev->subdev);
if (ret < 0)
goto error;
ret = omap3isp_video_register(&prev->video_in, vdev);
if (ret < 0)
goto error;
ret = omap3isp_video_register(&prev->video_out, vdev);
if (ret < 0)
goto error;
return 0;
error:
omap3isp_preview_unregister_entities(prev);
return ret;
}
/* -----------------------------------------------------------------------------
* ISP previewer initialisation and cleanup
*/
/*
* preview_init_entities - Initialize subdev and media entity.
* @prev : Pointer to preview structure
* return -ENOMEM or zero on success
*/
static int preview_init_entities(struct isp_prev_device *prev)
{
struct v4l2_subdev *sd = &prev->subdev;
struct media_pad *pads = prev->pads;
struct media_entity *me = &sd->entity;
int ret;
prev->input = PREVIEW_INPUT_NONE;
v4l2_subdev_init(sd, &preview_v4l2_ops);
sd->internal_ops = &preview_v4l2_internal_ops;
strlcpy(sd->name, "OMAP3 ISP preview", sizeof(sd->name));
sd->grp_id = 1 << 16; /* group ID for isp subdevs */
v4l2_set_subdevdata(sd, prev);
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
v4l2_ctrl_handler_init(&prev->ctrls, 2);
v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_BRIGHTNESS,
ISPPRV_BRIGHT_LOW, ISPPRV_BRIGHT_HIGH,
ISPPRV_BRIGHT_STEP, ISPPRV_BRIGHT_DEF);
v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_CONTRAST,
ISPPRV_CONTRAST_LOW, ISPPRV_CONTRAST_HIGH,
ISPPRV_CONTRAST_STEP, ISPPRV_CONTRAST_DEF);
v4l2_ctrl_handler_setup(&prev->ctrls);
sd->ctrl_handler = &prev->ctrls;
pads[PREV_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
pads[PREV_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
me->ops = &preview_media_ops;
ret = media_entity_init(me, PREV_PADS_NUM, pads, 0);
if (ret < 0)
return ret;
preview_init_formats(sd, NULL);
/* According to the OMAP34xx TRM, video buffers need to be aligned on a
* 32 bytes boundary. However, an undocumented hardware bug requires a
* 64 bytes boundary at the preview engine input.
*/
prev->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
prev->video_in.ops = &preview_video_ops;
prev->video_in.isp = to_isp_device(prev);
prev->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3;
prev->video_in.bpl_alignment = 64;
prev->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
prev->video_out.ops = &preview_video_ops;
prev->video_out.isp = to_isp_device(prev);
prev->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3;
prev->video_out.bpl_alignment = 32;
ret = omap3isp_video_init(&prev->video_in, "preview");
if (ret < 0)
goto error_video_in;
ret = omap3isp_video_init(&prev->video_out, "preview");
if (ret < 0)
goto error_video_out;
/* Connect the video nodes to the previewer subdev. */
ret = media_entity_create_link(&prev->video_in.video.entity, 0,
&prev->subdev.entity, PREV_PAD_SINK, 0);
if (ret < 0)
goto error_link;
ret = media_entity_create_link(&prev->subdev.entity, PREV_PAD_SOURCE,
&prev->video_out.video.entity, 0, 0);
if (ret < 0)
goto error_link;
return 0;
error_link:
omap3isp_video_cleanup(&prev->video_out);
error_video_out:
omap3isp_video_cleanup(&prev->video_in);
error_video_in:
media_entity_cleanup(&prev->subdev.entity);
return ret;
}
/*
* omap3isp_preview_init - Previewer initialization.
* @dev : Pointer to ISP device
* return -ENOMEM or zero on success
*/
int omap3isp_preview_init(struct isp_device *isp)
{
struct isp_prev_device *prev = &isp->isp_prev;
init_waitqueue_head(&prev->wait);
preview_init_params(prev);
return preview_init_entities(prev);
}
void omap3isp_preview_cleanup(struct isp_device *isp)
{
struct isp_prev_device *prev = &isp->isp_prev;
v4l2_ctrl_handler_free(&prev->ctrls);
omap3isp_video_cleanup(&prev->video_in);
omap3isp_video_cleanup(&prev->video_out);
media_entity_cleanup(&prev->subdev.entity);
}
| gpl-2.0 |
wkritzinger/asuswrt-merlin | release/src-rt-7.14.114.x/src/linux/linux-2.6.36/arch/um/drivers/ubd_user.c | 4708 | 1280 | /*
* Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
* Copyright (C) 2001 Ridgerun,Inc (glonnon@ridgerun.com)
* Licensed under the GPL
*/
#include <stddef.h>
#include <unistd.h>
#include <errno.h>
#include <sched.h>
#include <signal.h>
#include <string.h>
#include <netinet/in.h>
#include <sys/time.h>
#include <sys/socket.h>
#include <sys/mman.h>
#include <sys/param.h>
#include "asm/types.h"
#include "user.h"
#include "ubd_user.h"
#include "os.h"
#include "cow.h"
#include <endian.h>
#include <byteswap.h>
void ignore_sigwinch_sig(void)
{
signal(SIGWINCH, SIG_IGN);
}
int start_io_thread(unsigned long sp, int *fd_out)
{
int pid, fds[2], err;
err = os_pipe(fds, 1, 1);
if(err < 0){
printk("start_io_thread - os_pipe failed, err = %d\n", -err);
goto out;
}
kernel_fd = fds[0];
*fd_out = fds[1];
err = os_set_fd_block(*fd_out, 0);
if (err) {
printk("start_io_thread - failed to set nonblocking I/O.\n");
goto out_close;
}
pid = clone(io_thread, (void *) sp, CLONE_FILES | CLONE_VM, NULL);
if(pid < 0){
err = -errno;
printk("start_io_thread - clone failed : errno = %d\n", errno);
goto out_close;
}
return(pid);
out_close:
os_close_file(fds[0]);
os_close_file(fds[1]);
kernel_fd = -1;
*fd_out = -1;
out:
return err;
}
| gpl-2.0 |
MattCrystal/oneXL | drivers/staging/iio/accel/sca3000_ring.c | 4964 | 9352 | /*
* sca3000_ring.c -- support VTI sca3000 series accelerometers via SPI
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* Copyright (c) 2009 Jonathan Cameron <jic23@cam.ac.uk>
*
*/
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
#include <linux/sched.h>
#include <linux/poll.h>
#include "../iio.h"
#include "../sysfs.h"
#include "../buffer.h"
#include "../ring_hw.h"
#include "sca3000.h"
/* RFC / future work
*
* The internal ring buffer doesn't actually change what it holds depending
* on which signals are enabled etc, merely whether you can read them.
* As such the scan mode selection is somewhat different than for a software
* ring buffer and changing it actually covers any data already in the buffer.
* Currently scan elements aren't configured so it doesn't matter.
*/
static int sca3000_read_data(struct sca3000_state *st,
uint8_t reg_address_high,
u8 **rx_p,
int len)
{
int ret;
struct spi_message msg;
struct spi_transfer xfer[2] = {
{
.len = 1,
.tx_buf = st->tx,
}, {
.len = len,
}
};
*rx_p = kmalloc(len, GFP_KERNEL);
if (*rx_p == NULL) {
ret = -ENOMEM;
goto error_ret;
}
xfer[1].rx_buf = *rx_p;
st->tx[0] = SCA3000_READ_REG(reg_address_high);
spi_message_init(&msg);
spi_message_add_tail(&xfer[0], &msg);
spi_message_add_tail(&xfer[1], &msg);
ret = spi_sync(st->us, &msg);
if (ret) {
dev_err(get_device(&st->us->dev), "problem reading register");
goto error_free_rx;
}
return 0;
error_free_rx:
kfree(*rx_p);
error_ret:
return ret;
}
/**
* sca3000_read_first_n_hw_rb() - main ring access, pulls data from ring
* @r: the ring
* @count: number of samples to try and pull
* @data: output the actual samples pulled from the hw ring
*
* Currently does not provide timestamps. As the hardware doesn't add them they
* can only be inferred approximately from ring buffer events such as 50% full
* and knowledge of when buffer was last emptied. This is left to userspace.
**/
static int sca3000_read_first_n_hw_rb(struct iio_buffer *r,
size_t count, char __user *buf)
{
struct iio_hw_buffer *hw_ring = iio_to_hw_buf(r);
struct iio_dev *indio_dev = hw_ring->private;
struct sca3000_state *st = iio_priv(indio_dev);
u8 *rx;
int ret, i, num_available, num_read = 0;
int bytes_per_sample = 1;
if (st->bpse == 11)
bytes_per_sample = 2;
mutex_lock(&st->lock);
if (count % bytes_per_sample) {
ret = -EINVAL;
goto error_ret;
}
ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_BUF_COUNT, 1);
if (ret)
goto error_ret;
else
num_available = st->rx[0];
/*
* num_available is the total number of samples available
* i.e. number of time points * number of channels.
*/
if (count > num_available * bytes_per_sample)
num_read = num_available*bytes_per_sample;
else
num_read = count;
ret = sca3000_read_data(st,
SCA3000_REG_ADDR_RING_OUT,
&rx, num_read);
if (ret)
goto error_ret;
for (i = 0; i < num_read; i++)
*(((u16 *)rx) + i) = be16_to_cpup((u16 *)rx + i);
if (copy_to_user(buf, rx, num_read))
ret = -EFAULT;
kfree(rx);
r->stufftoread = 0;
error_ret:
mutex_unlock(&st->lock);
return ret ? ret : num_read;
}
/* This is only valid with all 3 elements enabled */
static int sca3000_ring_get_length(struct iio_buffer *r)
{
return 64;
}
/* only valid if resolution is kept at 11bits */
static int sca3000_ring_get_bytes_per_datum(struct iio_buffer *r)
{
return 6;
}
static IIO_BUFFER_ENABLE_ATTR;
static IIO_BUFFER_LENGTH_ATTR;
/**
* sca3000_query_ring_int() is the hardware ring status interrupt enabled
**/
static ssize_t sca3000_query_ring_int(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
int ret, val;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = iio_priv(indio_dev);
mutex_lock(&st->lock);
ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_MASK, 1);
val = st->rx[0];
mutex_unlock(&st->lock);
if (ret)
return ret;
return sprintf(buf, "%d\n", !!(val & this_attr->address));
}
/**
* sca3000_set_ring_int() set state of ring status interrupt
**/
static ssize_t sca3000_set_ring_int(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t len)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = iio_priv(indio_dev);
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
long val;
int ret;
mutex_lock(&st->lock);
ret = strict_strtol(buf, 10, &val);
if (ret)
goto error_ret;
ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_MASK, 1);
if (ret)
goto error_ret;
if (val)
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_INT_MASK,
st->rx[0] | this_attr->address);
else
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_INT_MASK,
st->rx[0] & ~this_attr->address);
error_ret:
mutex_unlock(&st->lock);
return ret ? ret : len;
}
static IIO_DEVICE_ATTR(50_percent, S_IRUGO | S_IWUSR,
sca3000_query_ring_int,
sca3000_set_ring_int,
SCA3000_INT_MASK_RING_HALF);
static IIO_DEVICE_ATTR(75_percent, S_IRUGO | S_IWUSR,
sca3000_query_ring_int,
sca3000_set_ring_int,
SCA3000_INT_MASK_RING_THREE_QUARTER);
static ssize_t sca3000_show_buffer_scale(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = iio_priv(indio_dev);
return sprintf(buf, "0.%06d\n", 4*st->info->scale);
}
static IIO_DEVICE_ATTR(in_accel_scale,
S_IRUGO,
sca3000_show_buffer_scale,
NULL,
0);
/*
* Ring buffer attributes
* This device is a bit unusual in that the sampling frequency and bpse
* only apply to the ring buffer. At all times full rate and accuracy
* is available via direct reading from registers.
*/
static struct attribute *sca3000_ring_attributes[] = {
&dev_attr_length.attr,
&dev_attr_enable.attr,
&iio_dev_attr_50_percent.dev_attr.attr,
&iio_dev_attr_75_percent.dev_attr.attr,
&iio_dev_attr_in_accel_scale.dev_attr.attr,
NULL,
};
static struct attribute_group sca3000_ring_attr = {
.attrs = sca3000_ring_attributes,
.name = "buffer",
};
static struct iio_buffer *sca3000_rb_allocate(struct iio_dev *indio_dev)
{
struct iio_buffer *buf;
struct iio_hw_buffer *ring;
ring = kzalloc(sizeof *ring, GFP_KERNEL);
if (!ring)
return NULL;
ring->private = indio_dev;
buf = &ring->buf;
buf->stufftoread = 0;
buf->attrs = &sca3000_ring_attr;
iio_buffer_init(buf);
return buf;
}
static inline void sca3000_rb_free(struct iio_buffer *r)
{
kfree(iio_to_hw_buf(r));
}
static const struct iio_buffer_access_funcs sca3000_ring_access_funcs = {
.read_first_n = &sca3000_read_first_n_hw_rb,
.get_length = &sca3000_ring_get_length,
.get_bytes_per_datum = &sca3000_ring_get_bytes_per_datum,
};
int sca3000_configure_ring(struct iio_dev *indio_dev)
{
indio_dev->buffer = sca3000_rb_allocate(indio_dev);
if (indio_dev->buffer == NULL)
return -ENOMEM;
indio_dev->modes |= INDIO_BUFFER_HARDWARE;
indio_dev->buffer->access = &sca3000_ring_access_funcs;
return 0;
}
void sca3000_unconfigure_ring(struct iio_dev *indio_dev)
{
sca3000_rb_free(indio_dev->buffer);
}
static inline
int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
{
struct sca3000_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
if (state) {
printk(KERN_INFO "supposedly enabling ring buffer\n");
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_MODE,
(st->rx[0] | SCA3000_RING_BUF_ENABLE));
} else
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_MODE,
(st->rx[0] & ~SCA3000_RING_BUF_ENABLE));
error_ret:
mutex_unlock(&st->lock);
return ret;
}
/**
* sca3000_hw_ring_preenable() hw ring buffer preenable function
*
* Very simple enable function as the chip will allows normal reads
* during ring buffer operation so as long as it is indeed running
* before we notify the core, the precise ordering does not matter.
**/
static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
{
return __sca3000_hw_ring_state_set(indio_dev, 1);
}
static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
{
return __sca3000_hw_ring_state_set(indio_dev, 0);
}
static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
.preenable = &sca3000_hw_ring_preenable,
.postdisable = &sca3000_hw_ring_postdisable,
};
void sca3000_register_ring_funcs(struct iio_dev *indio_dev)
{
indio_dev->setup_ops = &sca3000_ring_setup_ops;
}
/**
* sca3000_ring_int_process() ring specific interrupt handling.
*
* This is only split from the main interrupt handler so as to
* reduce the amount of code if the ring buffer is not enabled.
**/
void sca3000_ring_int_process(u8 val, struct iio_buffer *ring)
{
if (val & (SCA3000_INT_STATUS_THREE_QUARTERS |
SCA3000_INT_STATUS_HALF)) {
ring->stufftoread = true;
wake_up_interruptible(&ring->pollq);
}
}
| gpl-2.0 |
Kalashnikitty/ville-kernel | drivers/acpi/apei/erst.c | 4964 | 29145 | /*
* APEI Error Record Serialization Table support
*
* ERST is a way provided by APEI to save and retrieve hardware error
* information to and from a persistent store.
*
* For more information about ERST, please refer to ACPI Specification
* version 4.0, section 17.4.
*
* Copyright 2010 Intel Corp.
* Author: Huang Ying <ying.huang@intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/acpi.h>
#include <linux/uaccess.h>
#include <linux/cper.h>
#include <linux/nmi.h>
#include <linux/hardirq.h>
#include <linux/pstore.h>
#include <acpi/apei.h>
#include "apei-internal.h"
#define ERST_PFX "ERST: "
/* ERST command status */
#define ERST_STATUS_SUCCESS 0x0
#define ERST_STATUS_NOT_ENOUGH_SPACE 0x1
#define ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x2
#define ERST_STATUS_FAILED 0x3
#define ERST_STATUS_RECORD_STORE_EMPTY 0x4
#define ERST_STATUS_RECORD_NOT_FOUND 0x5
#define ERST_TAB_ENTRY(tab) \
((struct acpi_whea_header *)((char *)(tab) + \
sizeof(struct acpi_table_erst)))
#define SPIN_UNIT 100 /* 100ns */
/* Firmware should respond within 1 milliseconds */
#define FIRMWARE_TIMEOUT (1 * NSEC_PER_MSEC)
#define FIRMWARE_MAX_STALL 50 /* 50us */
int erst_disable;
EXPORT_SYMBOL_GPL(erst_disable);
static struct acpi_table_erst *erst_tab;
/* ERST Error Log Address Range atrributes */
#define ERST_RANGE_RESERVED 0x0001
#define ERST_RANGE_NVRAM 0x0002
#define ERST_RANGE_SLOW 0x0004
/*
* ERST Error Log Address Range, used as buffer for reading/writing
* error records.
*/
static struct erst_erange {
u64 base;
u64 size;
void __iomem *vaddr;
u32 attr;
} erst_erange;
/*
* Prevent ERST interpreter to run simultaneously, because the
* corresponding firmware implementation may not work properly when
* invoked simultaneously.
*
* It is used to provide exclusive accessing for ERST Error Log
* Address Range too.
*/
static DEFINE_RAW_SPINLOCK(erst_lock);
static inline int erst_errno(int command_status)
{
switch (command_status) {
case ERST_STATUS_SUCCESS:
return 0;
case ERST_STATUS_HARDWARE_NOT_AVAILABLE:
return -ENODEV;
case ERST_STATUS_NOT_ENOUGH_SPACE:
return -ENOSPC;
case ERST_STATUS_RECORD_STORE_EMPTY:
case ERST_STATUS_RECORD_NOT_FOUND:
return -ENOENT;
default:
return -EINVAL;
}
}
static int erst_timedout(u64 *t, u64 spin_unit)
{
if ((s64)*t < spin_unit) {
pr_warning(FW_WARN ERST_PFX
"Firmware does not respond in time\n");
return 1;
}
*t -= spin_unit;
ndelay(spin_unit);
touch_nmi_watchdog();
return 0;
}
static int erst_exec_load_var1(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
return __apei_exec_read_register(entry, &ctx->var1);
}
static int erst_exec_load_var2(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
return __apei_exec_read_register(entry, &ctx->var2);
}
static int erst_exec_store_var1(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
return __apei_exec_write_register(entry, ctx->var1);
}
static int erst_exec_add(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
ctx->var1 += ctx->var2;
return 0;
}
static int erst_exec_subtract(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
ctx->var1 -= ctx->var2;
return 0;
}
static int erst_exec_add_value(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
int rc;
u64 val;
rc = __apei_exec_read_register(entry, &val);
if (rc)
return rc;
val += ctx->value;
rc = __apei_exec_write_register(entry, val);
return rc;
}
static int erst_exec_subtract_value(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
int rc;
u64 val;
rc = __apei_exec_read_register(entry, &val);
if (rc)
return rc;
val -= ctx->value;
rc = __apei_exec_write_register(entry, val);
return rc;
}
static int erst_exec_stall(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
u64 stall_time;
if (ctx->value > FIRMWARE_MAX_STALL) {
if (!in_nmi())
pr_warning(FW_WARN ERST_PFX
"Too long stall time for stall instruction: %llx.\n",
ctx->value);
stall_time = FIRMWARE_MAX_STALL;
} else
stall_time = ctx->value;
udelay(stall_time);
return 0;
}
static int erst_exec_stall_while_true(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
int rc;
u64 val;
u64 timeout = FIRMWARE_TIMEOUT;
u64 stall_time;
if (ctx->var1 > FIRMWARE_MAX_STALL) {
if (!in_nmi())
pr_warning(FW_WARN ERST_PFX
"Too long stall time for stall while true instruction: %llx.\n",
ctx->var1);
stall_time = FIRMWARE_MAX_STALL;
} else
stall_time = ctx->var1;
for (;;) {
rc = __apei_exec_read_register(entry, &val);
if (rc)
return rc;
if (val != ctx->value)
break;
if (erst_timedout(&timeout, stall_time * NSEC_PER_USEC))
return -EIO;
}
return 0;
}
static int erst_exec_skip_next_instruction_if_true(
struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
int rc;
u64 val;
rc = __apei_exec_read_register(entry, &val);
if (rc)
return rc;
if (val == ctx->value) {
ctx->ip += 2;
return APEI_EXEC_SET_IP;
}
return 0;
}
static int erst_exec_goto(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
ctx->ip = ctx->value;
return APEI_EXEC_SET_IP;
}
static int erst_exec_set_src_address_base(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
return __apei_exec_read_register(entry, &ctx->src_base);
}
static int erst_exec_set_dst_address_base(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
return __apei_exec_read_register(entry, &ctx->dst_base);
}
static int erst_exec_move_data(struct apei_exec_context *ctx,
struct acpi_whea_header *entry)
{
int rc;
u64 offset;
void *src, *dst;
/* ioremap does not work in interrupt context */
if (in_interrupt()) {
pr_warning(ERST_PFX
"MOVE_DATA can not be used in interrupt context");
return -EBUSY;
}
rc = __apei_exec_read_register(entry, &offset);
if (rc)
return rc;
src = ioremap(ctx->src_base + offset, ctx->var2);
if (!src)
return -ENOMEM;
dst = ioremap(ctx->dst_base + offset, ctx->var2);
if (!dst)
return -ENOMEM;
memmove(dst, src, ctx->var2);
iounmap(src);
iounmap(dst);
return 0;
}
static struct apei_exec_ins_type erst_ins_type[] = {
[ACPI_ERST_READ_REGISTER] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = apei_exec_read_register,
},
[ACPI_ERST_READ_REGISTER_VALUE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = apei_exec_read_register_value,
},
[ACPI_ERST_WRITE_REGISTER] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = apei_exec_write_register,
},
[ACPI_ERST_WRITE_REGISTER_VALUE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = apei_exec_write_register_value,
},
[ACPI_ERST_NOOP] = {
.flags = 0,
.run = apei_exec_noop,
},
[ACPI_ERST_LOAD_VAR1] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_load_var1,
},
[ACPI_ERST_LOAD_VAR2] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_load_var2,
},
[ACPI_ERST_STORE_VAR1] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_store_var1,
},
[ACPI_ERST_ADD] = {
.flags = 0,
.run = erst_exec_add,
},
[ACPI_ERST_SUBTRACT] = {
.flags = 0,
.run = erst_exec_subtract,
},
[ACPI_ERST_ADD_VALUE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_add_value,
},
[ACPI_ERST_SUBTRACT_VALUE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_subtract_value,
},
[ACPI_ERST_STALL] = {
.flags = 0,
.run = erst_exec_stall,
},
[ACPI_ERST_STALL_WHILE_TRUE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_stall_while_true,
},
[ACPI_ERST_SKIP_NEXT_IF_TRUE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_skip_next_instruction_if_true,
},
[ACPI_ERST_GOTO] = {
.flags = 0,
.run = erst_exec_goto,
},
[ACPI_ERST_SET_SRC_ADDRESS_BASE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_set_src_address_base,
},
[ACPI_ERST_SET_DST_ADDRESS_BASE] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_set_dst_address_base,
},
[ACPI_ERST_MOVE_DATA] = {
.flags = APEI_EXEC_INS_ACCESS_REGISTER,
.run = erst_exec_move_data,
},
};
static inline void erst_exec_ctx_init(struct apei_exec_context *ctx)
{
apei_exec_ctx_init(ctx, erst_ins_type, ARRAY_SIZE(erst_ins_type),
ERST_TAB_ENTRY(erst_tab), erst_tab->entries);
}
static int erst_get_erange(struct erst_erange *range)
{
struct apei_exec_context ctx;
int rc;
erst_exec_ctx_init(&ctx);
rc = apei_exec_run(&ctx, ACPI_ERST_GET_ERROR_RANGE);
if (rc)
return rc;
range->base = apei_exec_ctx_get_output(&ctx);
rc = apei_exec_run(&ctx, ACPI_ERST_GET_ERROR_LENGTH);
if (rc)
return rc;
range->size = apei_exec_ctx_get_output(&ctx);
rc = apei_exec_run(&ctx, ACPI_ERST_GET_ERROR_ATTRIBUTES);
if (rc)
return rc;
range->attr = apei_exec_ctx_get_output(&ctx);
return 0;
}
static ssize_t __erst_get_record_count(void)
{
struct apei_exec_context ctx;
int rc;
erst_exec_ctx_init(&ctx);
rc = apei_exec_run(&ctx, ACPI_ERST_GET_RECORD_COUNT);
if (rc)
return rc;
return apei_exec_ctx_get_output(&ctx);
}
ssize_t erst_get_record_count(void)
{
ssize_t count;
unsigned long flags;
if (erst_disable)
return -ENODEV;
raw_spin_lock_irqsave(&erst_lock, flags);
count = __erst_get_record_count();
raw_spin_unlock_irqrestore(&erst_lock, flags);
return count;
}
EXPORT_SYMBOL_GPL(erst_get_record_count);
#define ERST_RECORD_ID_CACHE_SIZE_MIN 16
#define ERST_RECORD_ID_CACHE_SIZE_MAX 1024
struct erst_record_id_cache {
struct mutex lock;
u64 *entries;
int len;
int size;
int refcount;
};
static struct erst_record_id_cache erst_record_id_cache = {
.lock = __MUTEX_INITIALIZER(erst_record_id_cache.lock),
.refcount = 0,
};
static int __erst_get_next_record_id(u64 *record_id)
{
struct apei_exec_context ctx;
int rc;
erst_exec_ctx_init(&ctx);
rc = apei_exec_run(&ctx, ACPI_ERST_GET_RECORD_ID);
if (rc)
return rc;
*record_id = apei_exec_ctx_get_output(&ctx);
return 0;
}
int erst_get_record_id_begin(int *pos)
{
int rc;
if (erst_disable)
return -ENODEV;
rc = mutex_lock_interruptible(&erst_record_id_cache.lock);
if (rc)
return rc;
erst_record_id_cache.refcount++;
mutex_unlock(&erst_record_id_cache.lock);
*pos = 0;
return 0;
}
EXPORT_SYMBOL_GPL(erst_get_record_id_begin);
/* erst_record_id_cache.lock must be held by caller */
static int __erst_record_id_cache_add_one(void)
{
u64 id, prev_id, first_id;
int i, rc;
u64 *entries;
unsigned long flags;
id = prev_id = first_id = APEI_ERST_INVALID_RECORD_ID;
retry:
raw_spin_lock_irqsave(&erst_lock, flags);
rc = __erst_get_next_record_id(&id);
raw_spin_unlock_irqrestore(&erst_lock, flags);
if (rc == -ENOENT)
return 0;
if (rc)
return rc;
if (id == APEI_ERST_INVALID_RECORD_ID)
return 0;
/* can not skip current ID, or loop back to first ID */
if (id == prev_id || id == first_id)
return 0;
if (first_id == APEI_ERST_INVALID_RECORD_ID)
first_id = id;
prev_id = id;
entries = erst_record_id_cache.entries;
for (i = 0; i < erst_record_id_cache.len; i++) {
if (entries[i] == id)
break;
}
/* record id already in cache, try next */
if (i < erst_record_id_cache.len)
goto retry;
if (erst_record_id_cache.len >= erst_record_id_cache.size) {
int new_size, alloc_size;
u64 *new_entries;
new_size = erst_record_id_cache.size * 2;
new_size = clamp_val(new_size, ERST_RECORD_ID_CACHE_SIZE_MIN,
ERST_RECORD_ID_CACHE_SIZE_MAX);
if (new_size <= erst_record_id_cache.size) {
if (printk_ratelimit())
pr_warning(FW_WARN ERST_PFX
"too many record ID!\n");
return 0;
}
alloc_size = new_size * sizeof(entries[0]);
if (alloc_size < PAGE_SIZE)
new_entries = kmalloc(alloc_size, GFP_KERNEL);
else
new_entries = vmalloc(alloc_size);
if (!new_entries)
return -ENOMEM;
memcpy(new_entries, entries,
erst_record_id_cache.len * sizeof(entries[0]));
if (erst_record_id_cache.size < PAGE_SIZE)
kfree(entries);
else
vfree(entries);
erst_record_id_cache.entries = entries = new_entries;
erst_record_id_cache.size = new_size;
}
entries[i] = id;
erst_record_id_cache.len++;
return 1;
}
/*
* Get the record ID of an existing error record on the persistent
* storage. If there is no error record on the persistent storage, the
* returned record_id is APEI_ERST_INVALID_RECORD_ID.
*/
int erst_get_record_id_next(int *pos, u64 *record_id)
{
int rc = 0;
u64 *entries;
if (erst_disable)
return -ENODEV;
/* must be enclosed by erst_get_record_id_begin/end */
BUG_ON(!erst_record_id_cache.refcount);
BUG_ON(*pos < 0 || *pos > erst_record_id_cache.len);
mutex_lock(&erst_record_id_cache.lock);
entries = erst_record_id_cache.entries;
for (; *pos < erst_record_id_cache.len; (*pos)++)
if (entries[*pos] != APEI_ERST_INVALID_RECORD_ID)
break;
/* found next record id in cache */
if (*pos < erst_record_id_cache.len) {
*record_id = entries[*pos];
(*pos)++;
goto out_unlock;
}
/* Try to add one more record ID to cache */
rc = __erst_record_id_cache_add_one();
if (rc < 0)
goto out_unlock;
/* successfully add one new ID */
if (rc == 1) {
*record_id = erst_record_id_cache.entries[*pos];
(*pos)++;
rc = 0;
} else {
*pos = -1;
*record_id = APEI_ERST_INVALID_RECORD_ID;
}
out_unlock:
mutex_unlock(&erst_record_id_cache.lock);
return rc;
}
EXPORT_SYMBOL_GPL(erst_get_record_id_next);
/* erst_record_id_cache.lock must be held by caller */
static void __erst_record_id_cache_compact(void)
{
int i, wpos = 0;
u64 *entries;
if (erst_record_id_cache.refcount)
return;
entries = erst_record_id_cache.entries;
for (i = 0; i < erst_record_id_cache.len; i++) {
if (entries[i] == APEI_ERST_INVALID_RECORD_ID)
continue;
if (wpos != i)
memcpy(&entries[wpos], &entries[i], sizeof(entries[i]));
wpos++;
}
erst_record_id_cache.len = wpos;
}
void erst_get_record_id_end(void)
{
/*
* erst_disable != 0 should be detected by invoker via the
* return value of erst_get_record_id_begin/next, so this
* function should not be called for erst_disable != 0.
*/
BUG_ON(erst_disable);
mutex_lock(&erst_record_id_cache.lock);
erst_record_id_cache.refcount--;
BUG_ON(erst_record_id_cache.refcount < 0);
__erst_record_id_cache_compact();
mutex_unlock(&erst_record_id_cache.lock);
}
EXPORT_SYMBOL_GPL(erst_get_record_id_end);
static int __erst_write_to_storage(u64 offset)
{
struct apei_exec_context ctx;
u64 timeout = FIRMWARE_TIMEOUT;
u64 val;
int rc;
erst_exec_ctx_init(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_WRITE);
if (rc)
return rc;
apei_exec_ctx_set_input(&ctx, offset);
rc = apei_exec_run(&ctx, ACPI_ERST_SET_RECORD_OFFSET);
if (rc)
return rc;
rc = apei_exec_run(&ctx, ACPI_ERST_EXECUTE_OPERATION);
if (rc)
return rc;
for (;;) {
rc = apei_exec_run(&ctx, ACPI_ERST_CHECK_BUSY_STATUS);
if (rc)
return rc;
val = apei_exec_ctx_get_output(&ctx);
if (!val)
break;
if (erst_timedout(&timeout, SPIN_UNIT))
return -EIO;
}
rc = apei_exec_run(&ctx, ACPI_ERST_GET_COMMAND_STATUS);
if (rc)
return rc;
val = apei_exec_ctx_get_output(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_END);
if (rc)
return rc;
return erst_errno(val);
}
static int __erst_read_from_storage(u64 record_id, u64 offset)
{
struct apei_exec_context ctx;
u64 timeout = FIRMWARE_TIMEOUT;
u64 val;
int rc;
erst_exec_ctx_init(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_READ);
if (rc)
return rc;
apei_exec_ctx_set_input(&ctx, offset);
rc = apei_exec_run(&ctx, ACPI_ERST_SET_RECORD_OFFSET);
if (rc)
return rc;
apei_exec_ctx_set_input(&ctx, record_id);
rc = apei_exec_run(&ctx, ACPI_ERST_SET_RECORD_ID);
if (rc)
return rc;
rc = apei_exec_run(&ctx, ACPI_ERST_EXECUTE_OPERATION);
if (rc)
return rc;
for (;;) {
rc = apei_exec_run(&ctx, ACPI_ERST_CHECK_BUSY_STATUS);
if (rc)
return rc;
val = apei_exec_ctx_get_output(&ctx);
if (!val)
break;
if (erst_timedout(&timeout, SPIN_UNIT))
return -EIO;
};
rc = apei_exec_run(&ctx, ACPI_ERST_GET_COMMAND_STATUS);
if (rc)
return rc;
val = apei_exec_ctx_get_output(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_END);
if (rc)
return rc;
return erst_errno(val);
}
static int __erst_clear_from_storage(u64 record_id)
{
struct apei_exec_context ctx;
u64 timeout = FIRMWARE_TIMEOUT;
u64 val;
int rc;
erst_exec_ctx_init(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_BEGIN_CLEAR);
if (rc)
return rc;
apei_exec_ctx_set_input(&ctx, record_id);
rc = apei_exec_run(&ctx, ACPI_ERST_SET_RECORD_ID);
if (rc)
return rc;
rc = apei_exec_run(&ctx, ACPI_ERST_EXECUTE_OPERATION);
if (rc)
return rc;
for (;;) {
rc = apei_exec_run(&ctx, ACPI_ERST_CHECK_BUSY_STATUS);
if (rc)
return rc;
val = apei_exec_ctx_get_output(&ctx);
if (!val)
break;
if (erst_timedout(&timeout, SPIN_UNIT))
return -EIO;
}
rc = apei_exec_run(&ctx, ACPI_ERST_GET_COMMAND_STATUS);
if (rc)
return rc;
val = apei_exec_ctx_get_output(&ctx);
rc = apei_exec_run_optional(&ctx, ACPI_ERST_END);
if (rc)
return rc;
return erst_errno(val);
}
/* NVRAM ERST Error Log Address Range is not supported yet */
static void pr_unimpl_nvram(void)
{
if (printk_ratelimit())
pr_warning(ERST_PFX
"NVRAM ERST Log Address Range is not implemented yet\n");
}
static int __erst_write_to_nvram(const struct cper_record_header *record)
{
/* do not print message, because printk is not safe for NMI */
return -ENOSYS;
}
static int __erst_read_to_erange_from_nvram(u64 record_id, u64 *offset)
{
pr_unimpl_nvram();
return -ENOSYS;
}
static int __erst_clear_from_nvram(u64 record_id)
{
pr_unimpl_nvram();
return -ENOSYS;
}
int erst_write(const struct cper_record_header *record)
{
int rc;
unsigned long flags;
struct cper_record_header *rcd_erange;
if (erst_disable)
return -ENODEV;
if (memcmp(record->signature, CPER_SIG_RECORD, CPER_SIG_SIZE))
return -EINVAL;
if (erst_erange.attr & ERST_RANGE_NVRAM) {
if (!raw_spin_trylock_irqsave(&erst_lock, flags))
return -EBUSY;
rc = __erst_write_to_nvram(record);
raw_spin_unlock_irqrestore(&erst_lock, flags);
return rc;
}
if (record->record_length > erst_erange.size)
return -EINVAL;
if (!raw_spin_trylock_irqsave(&erst_lock, flags))
return -EBUSY;
memcpy(erst_erange.vaddr, record, record->record_length);
rcd_erange = erst_erange.vaddr;
/* signature for serialization system */
memcpy(&rcd_erange->persistence_information, "ER", 2);
rc = __erst_write_to_storage(0);
raw_spin_unlock_irqrestore(&erst_lock, flags);
return rc;
}
EXPORT_SYMBOL_GPL(erst_write);
static int __erst_read_to_erange(u64 record_id, u64 *offset)
{
int rc;
if (erst_erange.attr & ERST_RANGE_NVRAM)
return __erst_read_to_erange_from_nvram(
record_id, offset);
rc = __erst_read_from_storage(record_id, 0);
if (rc)
return rc;
*offset = 0;
return 0;
}
static ssize_t __erst_read(u64 record_id, struct cper_record_header *record,
size_t buflen)
{
int rc;
u64 offset, len = 0;
struct cper_record_header *rcd_tmp;
rc = __erst_read_to_erange(record_id, &offset);
if (rc)
return rc;
rcd_tmp = erst_erange.vaddr + offset;
len = rcd_tmp->record_length;
if (len <= buflen)
memcpy(record, rcd_tmp, len);
return len;
}
/*
* If return value > buflen, the buffer size is not big enough,
* else if return value < 0, something goes wrong,
* else everything is OK, and return value is record length
*/
ssize_t erst_read(u64 record_id, struct cper_record_header *record,
size_t buflen)
{
ssize_t len;
unsigned long flags;
if (erst_disable)
return -ENODEV;
raw_spin_lock_irqsave(&erst_lock, flags);
len = __erst_read(record_id, record, buflen);
raw_spin_unlock_irqrestore(&erst_lock, flags);
return len;
}
EXPORT_SYMBOL_GPL(erst_read);
int erst_clear(u64 record_id)
{
int rc, i;
unsigned long flags;
u64 *entries;
if (erst_disable)
return -ENODEV;
rc = mutex_lock_interruptible(&erst_record_id_cache.lock);
if (rc)
return rc;
raw_spin_lock_irqsave(&erst_lock, flags);
if (erst_erange.attr & ERST_RANGE_NVRAM)
rc = __erst_clear_from_nvram(record_id);
else
rc = __erst_clear_from_storage(record_id);
raw_spin_unlock_irqrestore(&erst_lock, flags);
if (rc)
goto out;
entries = erst_record_id_cache.entries;
for (i = 0; i < erst_record_id_cache.len; i++) {
if (entries[i] == record_id)
entries[i] = APEI_ERST_INVALID_RECORD_ID;
}
__erst_record_id_cache_compact();
out:
mutex_unlock(&erst_record_id_cache.lock);
return rc;
}
EXPORT_SYMBOL_GPL(erst_clear);
static int __init setup_erst_disable(char *str)
{
erst_disable = 1;
return 0;
}
__setup("erst_disable", setup_erst_disable);
static int erst_check_table(struct acpi_table_erst *erst_tab)
{
if ((erst_tab->header_length !=
(sizeof(struct acpi_table_erst) - sizeof(erst_tab->header)))
&& (erst_tab->header_length != sizeof(struct acpi_table_erst)))
return -EINVAL;
if (erst_tab->header.length < sizeof(struct acpi_table_erst))
return -EINVAL;
if (erst_tab->entries !=
(erst_tab->header.length - sizeof(struct acpi_table_erst)) /
sizeof(struct acpi_erst_entry))
return -EINVAL;
return 0;
}
static int erst_open_pstore(struct pstore_info *psi);
static int erst_close_pstore(struct pstore_info *psi);
static ssize_t erst_reader(u64 *id, enum pstore_type_id *type,
struct timespec *time, char **buf,
struct pstore_info *psi);
static int erst_writer(enum pstore_type_id type, enum kmsg_dump_reason reason,
u64 *id, unsigned int part,
size_t size, struct pstore_info *psi);
static int erst_clearer(enum pstore_type_id type, u64 id,
struct pstore_info *psi);
static struct pstore_info erst_info = {
.owner = THIS_MODULE,
.name = "erst",
.open = erst_open_pstore,
.close = erst_close_pstore,
.read = erst_reader,
.write = erst_writer,
.erase = erst_clearer
};
#define CPER_CREATOR_PSTORE \
UUID_LE(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \
0x64, 0x90, 0xb8, 0x9d)
#define CPER_SECTION_TYPE_DMESG \
UUID_LE(0xc197e04e, 0xd545, 0x4a70, 0x9c, 0x17, 0xa5, 0x54, \
0x94, 0x19, 0xeb, 0x12)
#define CPER_SECTION_TYPE_MCE \
UUID_LE(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \
0x04, 0x4a, 0x38, 0xfc)
struct cper_pstore_record {
struct cper_record_header hdr;
struct cper_section_descriptor sec_hdr;
char data[];
} __packed;
static int reader_pos;
static int erst_open_pstore(struct pstore_info *psi)
{
int rc;
if (erst_disable)
return -ENODEV;
rc = erst_get_record_id_begin(&reader_pos);
return rc;
}
static int erst_close_pstore(struct pstore_info *psi)
{
erst_get_record_id_end();
return 0;
}
static ssize_t erst_reader(u64 *id, enum pstore_type_id *type,
struct timespec *time, char **buf,
struct pstore_info *psi)
{
int rc;
ssize_t len = 0;
u64 record_id;
struct cper_pstore_record *rcd;
size_t rcd_len = sizeof(*rcd) + erst_info.bufsize;
if (erst_disable)
return -ENODEV;
rcd = kmalloc(rcd_len, GFP_KERNEL);
if (!rcd) {
rc = -ENOMEM;
goto out;
}
skip:
rc = erst_get_record_id_next(&reader_pos, &record_id);
if (rc)
goto out;
/* no more record */
if (record_id == APEI_ERST_INVALID_RECORD_ID) {
rc = -EINVAL;
goto out;
}
len = erst_read(record_id, &rcd->hdr, rcd_len);
/* The record may be cleared by others, try read next record */
if (len == -ENOENT)
goto skip;
else if (len < sizeof(*rcd)) {
rc = -EIO;
goto out;
}
if (uuid_le_cmp(rcd->hdr.creator_id, CPER_CREATOR_PSTORE) != 0)
goto skip;
*buf = kmalloc(len, GFP_KERNEL);
if (*buf == NULL) {
rc = -ENOMEM;
goto out;
}
memcpy(*buf, rcd->data, len - sizeof(*rcd));
*id = record_id;
if (uuid_le_cmp(rcd->sec_hdr.section_type,
CPER_SECTION_TYPE_DMESG) == 0)
*type = PSTORE_TYPE_DMESG;
else if (uuid_le_cmp(rcd->sec_hdr.section_type,
CPER_SECTION_TYPE_MCE) == 0)
*type = PSTORE_TYPE_MCE;
else
*type = PSTORE_TYPE_UNKNOWN;
if (rcd->hdr.validation_bits & CPER_VALID_TIMESTAMP)
time->tv_sec = rcd->hdr.timestamp;
else
time->tv_sec = 0;
time->tv_nsec = 0;
out:
kfree(rcd);
return (rc < 0) ? rc : (len - sizeof(*rcd));
}
static int erst_writer(enum pstore_type_id type, enum kmsg_dump_reason reason,
u64 *id, unsigned int part,
size_t size, struct pstore_info *psi)
{
struct cper_pstore_record *rcd = (struct cper_pstore_record *)
(erst_info.buf - sizeof(*rcd));
int ret;
memset(rcd, 0, sizeof(*rcd));
memcpy(rcd->hdr.signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
rcd->hdr.revision = CPER_RECORD_REV;
rcd->hdr.signature_end = CPER_SIG_END;
rcd->hdr.section_count = 1;
rcd->hdr.error_severity = CPER_SEV_FATAL;
/* timestamp valid. platform_id, partition_id are invalid */
rcd->hdr.validation_bits = CPER_VALID_TIMESTAMP;
rcd->hdr.timestamp = get_seconds();
rcd->hdr.record_length = sizeof(*rcd) + size;
rcd->hdr.creator_id = CPER_CREATOR_PSTORE;
rcd->hdr.notification_type = CPER_NOTIFY_MCE;
rcd->hdr.record_id = cper_next_record_id();
rcd->hdr.flags = CPER_HW_ERROR_FLAGS_PREVERR;
rcd->sec_hdr.section_offset = sizeof(*rcd);
rcd->sec_hdr.section_length = size;
rcd->sec_hdr.revision = CPER_SEC_REV;
/* fru_id and fru_text is invalid */
rcd->sec_hdr.validation_bits = 0;
rcd->sec_hdr.flags = CPER_SEC_PRIMARY;
switch (type) {
case PSTORE_TYPE_DMESG:
rcd->sec_hdr.section_type = CPER_SECTION_TYPE_DMESG;
break;
case PSTORE_TYPE_MCE:
rcd->sec_hdr.section_type = CPER_SECTION_TYPE_MCE;
break;
default:
return -EINVAL;
}
rcd->sec_hdr.section_severity = CPER_SEV_FATAL;
ret = erst_write(&rcd->hdr);
*id = rcd->hdr.record_id;
return ret;
}
static int erst_clearer(enum pstore_type_id type, u64 id,
struct pstore_info *psi)
{
return erst_clear(id);
}
static int __init erst_init(void)
{
int rc = 0;
acpi_status status;
struct apei_exec_context ctx;
struct apei_resources erst_resources;
struct resource *r;
char *buf;
if (acpi_disabled)
goto err;
if (erst_disable) {
pr_info(ERST_PFX
"Error Record Serialization Table (ERST) support is disabled.\n");
goto err;
}
status = acpi_get_table(ACPI_SIG_ERST, 0,
(struct acpi_table_header **)&erst_tab);
if (status == AE_NOT_FOUND)
goto err;
else if (ACPI_FAILURE(status)) {
const char *msg = acpi_format_exception(status);
pr_err(ERST_PFX "Failed to get table, %s\n", msg);
rc = -EINVAL;
goto err;
}
rc = erst_check_table(erst_tab);
if (rc) {
pr_err(FW_BUG ERST_PFX "ERST table is invalid\n");
goto err;
}
apei_resources_init(&erst_resources);
erst_exec_ctx_init(&ctx);
rc = apei_exec_collect_resources(&ctx, &erst_resources);
if (rc)
goto err_fini;
rc = apei_resources_request(&erst_resources, "APEI ERST");
if (rc)
goto err_fini;
rc = apei_exec_pre_map_gars(&ctx);
if (rc)
goto err_release;
rc = erst_get_erange(&erst_erange);
if (rc) {
if (rc == -ENODEV)
pr_info(ERST_PFX
"The corresponding hardware device or firmware implementation "
"is not available.\n");
else
pr_err(ERST_PFX
"Failed to get Error Log Address Range.\n");
goto err_unmap_reg;
}
r = request_mem_region(erst_erange.base, erst_erange.size, "APEI ERST");
if (!r) {
pr_err(ERST_PFX
"Can not request iomem region <0x%16llx-0x%16llx> for ERST.\n",
(unsigned long long)erst_erange.base,
(unsigned long long)erst_erange.base + erst_erange.size);
rc = -EIO;
goto err_unmap_reg;
}
rc = -ENOMEM;
erst_erange.vaddr = ioremap_cache(erst_erange.base,
erst_erange.size);
if (!erst_erange.vaddr)
goto err_release_erange;
buf = kmalloc(erst_erange.size, GFP_KERNEL);
spin_lock_init(&erst_info.buf_lock);
if (buf) {
erst_info.buf = buf + sizeof(struct cper_pstore_record);
erst_info.bufsize = erst_erange.size -
sizeof(struct cper_pstore_record);
if (pstore_register(&erst_info)) {
pr_info(ERST_PFX "Could not register with persistent store\n");
kfree(buf);
}
}
pr_info(ERST_PFX
"Error Record Serialization Table (ERST) support is initialized.\n");
return 0;
err_release_erange:
release_mem_region(erst_erange.base, erst_erange.size);
err_unmap_reg:
apei_exec_post_unmap_gars(&ctx);
err_release:
apei_resources_release(&erst_resources);
err_fini:
apei_resources_fini(&erst_resources);
err:
erst_disable = 1;
return rc;
}
device_initcall(erst_init);
| gpl-2.0 |
b-man/msm-3.4 | drivers/staging/iio/accel/lis3l02dq_core.c | 4964 | 19772 | /*
* lis3l02dq.c support STMicroelectronics LISD02DQ
* 3d 2g Linear Accelerometers via SPI
*
* Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Settings:
* 16 bit left justified mode used.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include "../iio.h"
#include "../sysfs.h"
#include "../events.h"
#include "../buffer.h"
#include "lis3l02dq.h"
/* At the moment the spi framework doesn't allow global setting of cs_change.
* It's in the likely to be added comment at the top of spi.h.
* This means that use cannot be made of spi_write etc.
*/
/* direct copy of the irq_default_primary_handler */
#ifndef CONFIG_IIO_BUFFER
static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
{
return IRQ_WAKE_THREAD;
}
#endif
/**
* lis3l02dq_spi_read_reg_8() - read single byte from a single register
* @indio_dev: iio_dev for this actual device
* @reg_address: the address of the register to be read
* @val: pass back the resulting value
**/
int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
u8 reg_address, u8 *val)
{
struct lis3l02dq_state *st = iio_priv(indio_dev);
struct spi_message msg;
int ret;
struct spi_transfer xfer = {
.tx_buf = st->tx,
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
};
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
st->tx[1] = 0;
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->us, &msg);
*val = st->rx[1];
mutex_unlock(&st->buf_lock);
return ret;
}
/**
* lis3l02dq_spi_write_reg_8() - write single byte to a register
* @indio_dev: iio_dev for this device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
u8 val)
{
int ret;
struct lis3l02dq_state *st = iio_priv(indio_dev);
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
st->tx[1] = val;
ret = spi_write(st->us, st->tx, 2);
mutex_unlock(&st->buf_lock);
return ret;
}
/**
* lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
* @indio_dev: iio_dev for this device
* @lower_reg_address: the address of the lower of the two registers.
* Second register is assumed to have address one greater.
* @value: value to be written
**/
static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
u8 lower_reg_address,
s16 value)
{
int ret;
struct spi_message msg;
struct lis3l02dq_state *st = iio_priv(indio_dev);
struct spi_transfer xfers[] = { {
.tx_buf = st->tx,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
}, {
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
},
};
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
st->tx[1] = value & 0xFF;
st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
st->tx[3] = (value >> 8) & 0xFF;
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
mutex_unlock(&st->buf_lock);
return ret;
}
static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
u8 lower_reg_address,
int *val)
{
struct lis3l02dq_state *st = iio_priv(indio_dev);
struct spi_message msg;
int ret;
s16 tempval;
struct spi_transfer xfers[] = { {
.tx_buf = st->tx,
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
}, {
.tx_buf = st->tx + 2,
.rx_buf = st->rx + 2,
.bits_per_word = 8,
.len = 2,
},
};
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
st->tx[1] = 0;
st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
st->tx[3] = 0;
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
if (ret) {
dev_err(&st->us->dev, "problem when reading 16 bit register");
goto error_ret;
}
tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
*val = tempval;
error_ret:
mutex_unlock(&st->buf_lock);
return ret;
}
enum lis3l02dq_rm_ind {
LIS3L02DQ_ACCEL,
LIS3L02DQ_GAIN,
LIS3L02DQ_BIAS,
};
static u8 lis3l02dq_axis_map[3][3] = {
[LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
LIS3L02DQ_REG_OUT_Y_L_ADDR,
LIS3L02DQ_REG_OUT_Z_L_ADDR },
[LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
LIS3L02DQ_REG_GAIN_Y_ADDR,
LIS3L02DQ_REG_GAIN_Z_ADDR },
[LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
LIS3L02DQ_REG_OFFSET_Y_ADDR,
LIS3L02DQ_REG_OFFSET_Z_ADDR }
};
static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
u64 e,
int *val)
{
return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
}
static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
u64 event_code,
int val)
{
u16 value = val;
return lis3l02dq_spi_write_reg_s16(indio_dev,
LIS3L02DQ_REG_THS_L_ADDR,
value);
}
static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
int ret = -EINVAL, reg;
u8 uval;
s8 sval;
switch (mask) {
case IIO_CHAN_INFO_CALIBBIAS:
if (val > 255 || val < -256)
return -EINVAL;
sval = val;
reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (val & ~0xFF)
return -EINVAL;
uval = val;
reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
break;
}
return ret;
}
static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask)
{
u8 utemp;
s8 stemp;
ssize_t ret = 0;
u8 reg;
switch (mask) {
case 0:
/* Take the iio_dev status lock */
mutex_lock(&indio_dev->mlock);
if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
ret = -EBUSY;
} else {
reg = lis3l02dq_axis_map
[LIS3L02DQ_ACCEL][chan->address];
ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
}
mutex_unlock(&indio_dev->mlock);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = 9580;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_CHAN_INFO_CALIBSCALE:
reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
if (ret)
goto error_ret;
/* to match with what previous code does */
*val = utemp;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
/* to match with what previous code does */
*val = stemp;
return IIO_VAL_INT;
}
error_ret:
return ret;
}
static ssize_t lis3l02dq_read_frequency(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
int ret, len = 0;
s8 t;
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
(u8 *)&t);
if (ret)
return ret;
t &= LIS3L02DQ_DEC_MASK;
switch (t) {
case LIS3L02DQ_REG_CTRL_1_DF_128:
len = sprintf(buf, "280\n");
break;
case LIS3L02DQ_REG_CTRL_1_DF_64:
len = sprintf(buf, "560\n");
break;
case LIS3L02DQ_REG_CTRL_1_DF_32:
len = sprintf(buf, "1120\n");
break;
case LIS3L02DQ_REG_CTRL_1_DF_8:
len = sprintf(buf, "4480\n");
break;
}
return len;
}
static ssize_t lis3l02dq_write_frequency(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t len)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
unsigned long val;
int ret;
u8 t;
ret = kstrtoul(buf, 10, &val);
if (ret)
return ret;
mutex_lock(&indio_dev->mlock);
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
&t);
if (ret)
goto error_ret_mutex;
/* Wipe the bits clean */
t &= ~LIS3L02DQ_DEC_MASK;
switch (val) {
case 280:
t |= LIS3L02DQ_REG_CTRL_1_DF_128;
break;
case 560:
t |= LIS3L02DQ_REG_CTRL_1_DF_64;
break;
case 1120:
t |= LIS3L02DQ_REG_CTRL_1_DF_32;
break;
case 4480:
t |= LIS3L02DQ_REG_CTRL_1_DF_8;
break;
default:
ret = -EINVAL;
goto error_ret_mutex;
}
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
t);
error_ret_mutex:
mutex_unlock(&indio_dev->mlock);
return ret ? ret : len;
}
static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
{
struct lis3l02dq_state *st = iio_priv(indio_dev);
int ret;
u8 val, valtest;
st->us->mode = SPI_MODE_3;
spi_setup(st->us);
val = LIS3L02DQ_DEFAULT_CTRL1;
/* Write suitable defaults to ctrl1 */
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 1");
goto err_ret;
}
/* Repeat as sometimes doesn't work first time?*/
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 1");
goto err_ret;
}
/* Read back to check this has worked acts as loose test of correct
* chip */
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
&valtest);
if (ret || (valtest != val)) {
dev_err(&indio_dev->dev,
"device not playing ball %d %d\n", valtest, val);
ret = -EINVAL;
goto err_ret;
}
val = LIS3L02DQ_DEFAULT_CTRL2;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 2");
goto err_ret;
}
val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
val);
if (ret)
dev_err(&st->us->dev, "problem with interrupt cfg register");
err_ret:
return ret;
}
static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
lis3l02dq_read_frequency,
lis3l02dq_write_frequency);
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
u8 t;
s64 timestamp = iio_get_time_ns();
lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
&t);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
timestamp);
/* Ack and allow for new interrupts */
lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
&t);
return IRQ_HANDLED;
}
#define LIS3L02DQ_INFO_MASK \
(IIO_CHAN_INFO_SCALE_SHARED_BIT | \
IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT | \
IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT)
#define LIS3L02DQ_EVENT_MASK \
(IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) | \
IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
static struct iio_chan_spec lis3l02dq_channels[] = {
IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
IIO_CHAN_SOFT_TIMESTAMP(3)
};
static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
u64 event_code)
{
u8 val;
int ret;
u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
(IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
IIO_EV_DIR_RISING)));
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val);
if (ret < 0)
return ret;
return !!(val & mask);
}
int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
{
int ret;
u8 control, val;
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
&control);
control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
control);
if (ret)
goto error_ret;
/* Also for consistency clear the mask */
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val);
if (ret)
goto error_ret;
val &= ~0x3f;
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
val);
if (ret)
goto error_ret;
ret = control;
error_ret:
return ret;
}
static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
u64 event_code,
int state)
{
int ret = 0;
u8 val, control;
u8 currentlyset;
bool changed = false;
u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
(IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
IIO_EV_DIR_RISING)));
mutex_lock(&indio_dev->mlock);
/* read current control */
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
&control);
if (ret)
goto error_ret;
ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
&val);
if (ret < 0)
goto error_ret;
currentlyset = val & mask;
if (!currentlyset && state) {
changed = true;
val |= mask;
} else if (currentlyset && !state) {
changed = true;
val &= ~mask;
}
if (changed) {
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
val);
if (ret)
goto error_ret;
control = val & 0x3f ?
(control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
(control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
control);
if (ret)
goto error_ret;
}
error_ret:
mutex_unlock(&indio_dev->mlock);
return ret;
}
static struct attribute *lis3l02dq_attributes[] = {
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL
};
static const struct attribute_group lis3l02dq_attribute_group = {
.attrs = lis3l02dq_attributes,
};
static const struct iio_info lis3l02dq_info = {
.read_raw = &lis3l02dq_read_raw,
.write_raw = &lis3l02dq_write_raw,
.read_event_value = &lis3l02dq_read_thresh,
.write_event_value = &lis3l02dq_write_thresh,
.write_event_config = &lis3l02dq_write_event_config,
.read_event_config = &lis3l02dq_read_event_config,
.driver_module = THIS_MODULE,
.attrs = &lis3l02dq_attribute_group,
};
static int __devinit lis3l02dq_probe(struct spi_device *spi)
{
int ret;
struct lis3l02dq_state *st;
struct iio_dev *indio_dev;
indio_dev = iio_allocate_device(sizeof *st);
if (indio_dev == NULL) {
ret = -ENOMEM;
goto error_ret;
}
st = iio_priv(indio_dev);
/* this is only used tor removal purposes */
spi_set_drvdata(spi, indio_dev);
st->us = spi;
mutex_init(&st->buf_lock);
indio_dev->name = spi->dev.driver->name;
indio_dev->dev.parent = &spi->dev;
indio_dev->info = &lis3l02dq_info;
indio_dev->channels = lis3l02dq_channels;
indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
indio_dev->modes = INDIO_DIRECT_MODE;
ret = lis3l02dq_configure_buffer(indio_dev);
if (ret)
goto error_free_dev;
ret = iio_buffer_register(indio_dev,
lis3l02dq_channels,
ARRAY_SIZE(lis3l02dq_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the buffer\n");
goto error_unreg_buffer_funcs;
}
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
ret = request_threaded_irq(st->us->irq,
&lis3l02dq_th,
&lis3l02dq_event_handler,
IRQF_TRIGGER_RISING,
"lis3l02dq",
indio_dev);
if (ret)
goto error_uninitialize_buffer;
ret = lis3l02dq_probe_trigger(indio_dev);
if (ret)
goto error_free_interrupt;
}
/* Get the device into a sane initial state */
ret = lis3l02dq_initial_setup(indio_dev);
if (ret)
goto error_remove_trigger;
ret = iio_device_register(indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
if (indio_dev->modes & INDIO_BUFFER_TRIGGERED)
lis3l02dq_remove_trigger(indio_dev);
error_free_interrupt:
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
free_irq(st->us->irq, indio_dev);
error_uninitialize_buffer:
iio_buffer_unregister(indio_dev);
error_unreg_buffer_funcs:
lis3l02dq_unconfigure_buffer(indio_dev);
error_free_dev:
iio_free_device(indio_dev);
error_ret:
return ret;
}
/* Power down the device */
static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
{
int ret;
struct lis3l02dq_state *st = iio_priv(indio_dev);
u8 val = 0;
mutex_lock(&indio_dev->mlock);
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
val);
if (ret) {
dev_err(&st->us->dev, "problem with turning device off: ctrl1");
goto err_ret;
}
ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
val);
if (ret)
dev_err(&st->us->dev, "problem with turning device off: ctrl2");
err_ret:
mutex_unlock(&indio_dev->mlock);
return ret;
}
/* fixme, confirm ordering in this function */
static int lis3l02dq_remove(struct spi_device *spi)
{
int ret;
struct iio_dev *indio_dev = spi_get_drvdata(spi);
struct lis3l02dq_state *st = iio_priv(indio_dev);
iio_device_unregister(indio_dev);
ret = lis3l02dq_disable_all_events(indio_dev);
if (ret)
goto err_ret;
ret = lis3l02dq_stop_device(indio_dev);
if (ret)
goto err_ret;
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
free_irq(st->us->irq, indio_dev);
lis3l02dq_remove_trigger(indio_dev);
iio_buffer_unregister(indio_dev);
lis3l02dq_unconfigure_buffer(indio_dev);
iio_free_device(indio_dev);
err_ret:
return ret;
}
static struct spi_driver lis3l02dq_driver = {
.driver = {
.name = "lis3l02dq",
.owner = THIS_MODULE,
},
.probe = lis3l02dq_probe,
.remove = __devexit_p(lis3l02dq_remove),
};
module_spi_driver(lis3l02dq_driver);
MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:lis3l02dq");
| gpl-2.0 |
javelinanddart/android_kernel_htc_pyramid | drivers/staging/iio/accel/adis16203_core.c | 4964 | 12419 | /*
* ADIS16203 Programmable Digital Vibration Sensor driver
*
* Copyright 2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include "../iio.h"
#include "../sysfs.h"
#include "../buffer.h"
#include "adis16203.h"
#define DRIVER_NAME "adis16203"
/**
* adis16203_spi_write_reg_8() - write single byte to a register
* @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
static int adis16203_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
u8 val)
{
int ret;
struct adis16203_state *st = iio_priv(indio_dev);
mutex_lock(&st->buf_lock);
st->tx[0] = ADIS16203_WRITE_REG(reg_address);
st->tx[1] = val;
ret = spi_write(st->us, st->tx, 2);
mutex_unlock(&st->buf_lock);
return ret;
}
/**
* adis16203_spi_write_reg_16() - write 2 bytes to a pair of registers
* @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
static int adis16203_spi_write_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 value)
{
int ret;
struct spi_message msg;
struct adis16203_state *st = iio_priv(indio_dev);
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
}, {
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
},
};
mutex_lock(&st->buf_lock);
st->tx[0] = ADIS16203_WRITE_REG(lower_reg_address);
st->tx[1] = value & 0xFF;
st->tx[2] = ADIS16203_WRITE_REG(lower_reg_address + 1);
st->tx[3] = (value >> 8) & 0xFF;
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
mutex_unlock(&st->buf_lock);
return ret;
}
/**
* adis16203_spi_read_reg_16() - read 2 bytes from a 16-bit register
* @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
static int adis16203_spi_read_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 *val)
{
struct spi_message msg;
struct adis16203_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
.delay_usecs = 20,
}, {
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
.delay_usecs = 20,
},
};
mutex_lock(&st->buf_lock);
st->tx[0] = ADIS16203_READ_REG(lower_reg_address);
st->tx[1] = 0;
spi_message_init(&msg);
spi_message_add_tail(&xfers[0], &msg);
spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
if (ret) {
dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
lower_reg_address);
goto error_ret;
}
*val = (st->rx[0] << 8) | st->rx[1];
error_ret:
mutex_unlock(&st->buf_lock);
return ret;
}
static int adis16203_check_status(struct iio_dev *indio_dev)
{
u16 status;
int ret;
ret = adis16203_spi_read_reg_16(indio_dev,
ADIS16203_DIAG_STAT,
&status);
if (ret < 0) {
dev_err(&indio_dev->dev, "Reading status failed\n");
goto error_ret;
}
ret = status & 0x1F;
if (status & ADIS16203_DIAG_STAT_SELFTEST_FAIL)
dev_err(&indio_dev->dev, "Self test failure\n");
if (status & ADIS16203_DIAG_STAT_SPI_FAIL)
dev_err(&indio_dev->dev, "SPI failure\n");
if (status & ADIS16203_DIAG_STAT_FLASH_UPT)
dev_err(&indio_dev->dev, "Flash update failed\n");
if (status & ADIS16203_DIAG_STAT_POWER_HIGH)
dev_err(&indio_dev->dev, "Power supply above 3.625V\n");
if (status & ADIS16203_DIAG_STAT_POWER_LOW)
dev_err(&indio_dev->dev, "Power supply below 3.15V\n");
error_ret:
return ret;
}
static int adis16203_reset(struct iio_dev *indio_dev)
{
int ret;
ret = adis16203_spi_write_reg_8(indio_dev,
ADIS16203_GLOB_CMD,
ADIS16203_GLOB_CMD_SW_RESET);
if (ret)
dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
static ssize_t adis16203_write_reset(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
if (len < 1)
return -EINVAL;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
return adis16203_reset(indio_dev);
}
return -EINVAL;
}
int adis16203_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret = 0;
u16 msc;
ret = adis16203_spi_read_reg_16(indio_dev, ADIS16203_MSC_CTRL, &msc);
if (ret)
goto error_ret;
msc |= ADIS16203_MSC_CTRL_ACTIVE_HIGH;
msc &= ~ADIS16203_MSC_CTRL_DATA_RDY_DIO1;
if (enable)
msc |= ADIS16203_MSC_CTRL_DATA_RDY_EN;
else
msc &= ~ADIS16203_MSC_CTRL_DATA_RDY_EN;
ret = adis16203_spi_write_reg_16(indio_dev, ADIS16203_MSC_CTRL, msc);
error_ret:
return ret;
}
static int adis16203_self_test(struct iio_dev *indio_dev)
{
int ret;
ret = adis16203_spi_write_reg_16(indio_dev,
ADIS16203_MSC_CTRL,
ADIS16203_MSC_CTRL_SELF_TEST_EN);
if (ret) {
dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
adis16203_check_status(indio_dev);
err_ret:
return ret;
}
static int adis16203_initial_setup(struct iio_dev *indio_dev)
{
int ret;
/* Disable IRQ */
ret = adis16203_set_irq(indio_dev, false);
if (ret) {
dev_err(&indio_dev->dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
ret = adis16203_self_test(indio_dev);
if (ret) {
dev_err(&indio_dev->dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
ret = adis16203_check_status(indio_dev);
if (ret) {
adis16203_reset(indio_dev);
dev_err(&indio_dev->dev, "device not playing ball -> reset");
msleep(ADIS16203_STARTUP_DELAY);
ret = adis16203_check_status(indio_dev);
if (ret) {
dev_err(&indio_dev->dev, "giving up");
goto err_ret;
}
}
err_ret:
return ret;
}
enum adis16203_chan {
in_supply,
in_aux,
incli_x,
incli_y,
temp,
};
static u8 adis16203_addresses[5][2] = {
[in_supply] = { ADIS16203_SUPPLY_OUT },
[in_aux] = { ADIS16203_AUX_ADC },
[incli_x] = { ADIS16203_XINCL_OUT, ADIS16203_INCL_NULL},
[incli_y] = { ADIS16203_YINCL_OUT },
[temp] = { ADIS16203_TEMP_OUT }
};
static int adis16203_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
/* currently only one writable parameter which keeps this simple */
u8 addr = adis16203_addresses[chan->address][1];
return adis16203_spi_write_reg_16(indio_dev, addr, val & 0x3FFF);
}
static int adis16203_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2,
long mask)
{
int ret;
int bits;
u8 addr;
s16 val16;
switch (mask) {
case 0:
mutex_lock(&indio_dev->mlock);
addr = adis16203_addresses[chan->address][0];
ret = adis16203_spi_read_reg_16(indio_dev, addr, &val16);
if (ret) {
mutex_unlock(&indio_dev->mlock);
return ret;
}
if (val16 & ADIS16203_ERROR_ACTIVE) {
ret = adis16203_check_status(indio_dev);
if (ret) {
mutex_unlock(&indio_dev->mlock);
return ret;
}
}
val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
if (chan->scan_type.sign == 's')
val16 = (s16)(val16 <<
(16 - chan->scan_type.realbits)) >>
(16 - chan->scan_type.realbits);
*val = val16;
mutex_unlock(&indio_dev->mlock);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
*val = 0;
if (chan->channel == 0)
*val2 = 1220;
else
*val2 = 610;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_TEMP:
*val = 0;
*val2 = -470000;
return IIO_VAL_INT_PLUS_MICRO;
case IIO_INCLI:
*val = 0;
*val2 = 25000;
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OFFSET:
*val = 25;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
bits = 14;
mutex_lock(&indio_dev->mlock);
addr = adis16203_addresses[chan->address][1];
ret = adis16203_spi_read_reg_16(indio_dev, addr, &val16);
if (ret) {
mutex_unlock(&indio_dev->mlock);
return ret;
}
val16 &= (1 << bits) - 1;
val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
*val = val16;
mutex_unlock(&indio_dev->mlock);
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static struct iio_chan_spec adis16203_channels[] = {
IIO_CHAN(IIO_VOLTAGE, 0, 1, 0, "supply", 0, 0,
IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
in_supply, ADIS16203_SCAN_SUPPLY,
IIO_ST('u', 12, 16, 0), 0),
IIO_CHAN(IIO_VOLTAGE, 0, 1, 0, NULL, 1, 0,
IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
in_aux, ADIS16203_SCAN_AUX_ADC,
IIO_ST('u', 12, 16, 0), 0),
IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_X,
IIO_CHAN_INFO_SCALE_SHARED_BIT |
IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT,
incli_x, ADIS16203_SCAN_INCLI_X,
IIO_ST('s', 14, 16, 0), 0),
/* Fixme: Not what it appears to be - see data sheet */
IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_Y,
IIO_CHAN_INFO_SCALE_SHARED_BIT,
incli_y, ADIS16203_SCAN_INCLI_Y,
IIO_ST('s', 14, 16, 0), 0),
IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
IIO_CHAN_INFO_SCALE_SEPARATE_BIT |
IIO_CHAN_INFO_OFFSET_SEPARATE_BIT,
temp, ADIS16203_SCAN_TEMP,
IIO_ST('u', 12, 16, 0), 0),
IIO_CHAN_SOFT_TIMESTAMP(5),
};
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16203_write_reset, 0);
static struct attribute *adis16203_attributes[] = {
&iio_dev_attr_reset.dev_attr.attr,
NULL
};
static const struct attribute_group adis16203_attribute_group = {
.attrs = adis16203_attributes,
};
static const struct iio_info adis16203_info = {
.attrs = &adis16203_attribute_group,
.read_raw = &adis16203_read_raw,
.write_raw = &adis16203_write_raw,
.driver_module = THIS_MODULE,
};
static int __devinit adis16203_probe(struct spi_device *spi)
{
int ret;
struct iio_dev *indio_dev;
struct adis16203_state *st;
/* setup the industrialio driver allocated elements */
indio_dev = iio_allocate_device(sizeof(*st));
if (indio_dev == NULL) {
ret = -ENOMEM;
goto error_ret;
}
st = iio_priv(indio_dev);
/* this is only used for removal purposes */
spi_set_drvdata(spi, indio_dev);
st->us = spi;
mutex_init(&st->buf_lock);
indio_dev->name = spi->dev.driver->name;
indio_dev->dev.parent = &spi->dev;
indio_dev->channels = adis16203_channels;
indio_dev->num_channels = ARRAY_SIZE(adis16203_channels);
indio_dev->info = &adis16203_info;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16203_configure_ring(indio_dev);
if (ret)
goto error_free_dev;
ret = iio_buffer_register(indio_dev,
adis16203_channels,
ARRAY_SIZE(adis16203_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
ret = adis16203_probe_trigger(indio_dev);
if (ret)
goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
ret = adis16203_initial_setup(indio_dev);
if (ret)
goto error_remove_trigger;
ret = iio_device_register(indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
adis16203_remove_trigger(indio_dev);
error_uninitialize_ring:
iio_buffer_unregister(indio_dev);
error_unreg_ring_funcs:
adis16203_unconfigure_ring(indio_dev);
error_free_dev:
iio_free_device(indio_dev);
error_ret:
return ret;
}
static int adis16203_remove(struct spi_device *spi)
{
struct iio_dev *indio_dev = spi_get_drvdata(spi);
iio_device_unregister(indio_dev);
adis16203_remove_trigger(indio_dev);
iio_buffer_unregister(indio_dev);
adis16203_unconfigure_ring(indio_dev);
iio_free_device(indio_dev);
return 0;
}
static struct spi_driver adis16203_driver = {
.driver = {
.name = "adis16203",
.owner = THIS_MODULE,
},
.probe = adis16203_probe,
.remove = __devexit_p(adis16203_remove),
};
module_spi_driver(adis16203_driver);
MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
MODULE_DESCRIPTION("Analog Devices ADIS16203 Programmable Digital Vibration Sensor driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:adis16203");
| gpl-2.0 |
iHateWEBos/DNA_kitkat | security/integrity/digsig.c | 5220 | 1144 | /*
* Copyright (C) 2011 Intel Corporation
*
* Author:
* Dmitry Kasatkin <dmitry.kasatkin@intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 2 of the License.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/err.h>
#include <linux/rbtree.h>
#include <linux/key-type.h>
#include <linux/digsig.h>
#include "integrity.h"
static struct key *keyring[INTEGRITY_KEYRING_MAX];
static const char *keyring_name[INTEGRITY_KEYRING_MAX] = {
"_evm",
"_module",
"_ima",
};
int integrity_digsig_verify(const unsigned int id, const char *sig, int siglen,
const char *digest, int digestlen)
{
if (id >= INTEGRITY_KEYRING_MAX)
return -EINVAL;
if (!keyring[id]) {
keyring[id] =
request_key(&key_type_keyring, keyring_name[id], NULL);
if (IS_ERR(keyring[id])) {
int err = PTR_ERR(keyring[id]);
pr_err("no %s keyring: %d\n", keyring_name[id], err);
keyring[id] = NULL;
return err;
}
}
return digsig_verify(keyring[id], sig, siglen, digest, digestlen);
}
| gpl-2.0 |
F4uzan/f4kernel-u0 | arch/powerpc/oprofile/common.c | 6756 | 6329 | /*
* PPC 64 oprofile support:
* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
* PPC 32 oprofile support: (based on PPC 64 support)
* Copyright (C) Freescale Semiconductor, Inc 2004
* Author: Andy Fleming
*
* Based on alpha version.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/oprofile.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/errno.h>
#include <asm/ptrace.h>
#include <asm/pmc.h>
#include <asm/cputable.h>
#include <asm/oprofile_impl.h>
#include <asm/firmware.h>
static struct op_powerpc_model *model;
static struct op_counter_config ctr[OP_MAX_COUNTER];
static struct op_system_config sys;
static int op_per_cpu_rc;
static void op_handle_interrupt(struct pt_regs *regs)
{
model->handle_interrupt(regs, ctr);
}
static void op_powerpc_cpu_setup(void *dummy)
{
int ret;
ret = model->cpu_setup(ctr);
if (ret != 0)
op_per_cpu_rc = ret;
}
static int op_powerpc_setup(void)
{
int err;
op_per_cpu_rc = 0;
/* Grab the hardware */
err = reserve_pmc_hardware(op_handle_interrupt);
if (err)
return err;
/* Pre-compute the values to stuff in the hardware registers. */
op_per_cpu_rc = model->reg_setup(ctr, &sys, model->num_counters);
if (op_per_cpu_rc)
goto out;
/* Configure the registers on all cpus. If an error occurs on one
* of the cpus, op_per_cpu_rc will be set to the error */
on_each_cpu(op_powerpc_cpu_setup, NULL, 1);
out: if (op_per_cpu_rc) {
/* error on setup release the performance counter hardware */
release_pmc_hardware();
}
return op_per_cpu_rc;
}
static void op_powerpc_shutdown(void)
{
release_pmc_hardware();
}
static void op_powerpc_cpu_start(void *dummy)
{
/* If any of the cpus have return an error, set the
* global flag to the error so it can be returned
* to the generic OProfile caller.
*/
int ret;
ret = model->start(ctr);
if (ret != 0)
op_per_cpu_rc = ret;
}
static int op_powerpc_start(void)
{
op_per_cpu_rc = 0;
if (model->global_start)
return model->global_start(ctr);
if (model->start) {
on_each_cpu(op_powerpc_cpu_start, NULL, 1);
return op_per_cpu_rc;
}
return -EIO; /* No start function is defined for this
power architecture */
}
static inline void op_powerpc_cpu_stop(void *dummy)
{
model->stop();
}
static void op_powerpc_stop(void)
{
if (model->stop)
on_each_cpu(op_powerpc_cpu_stop, NULL, 1);
if (model->global_stop)
model->global_stop();
}
static int op_powerpc_create_files(struct super_block *sb, struct dentry *root)
{
int i;
#ifdef CONFIG_PPC64
/*
* There is one mmcr0, mmcr1 and mmcra for setting the events for
* all of the counters.
*/
oprofilefs_create_ulong(sb, root, "mmcr0", &sys.mmcr0);
oprofilefs_create_ulong(sb, root, "mmcr1", &sys.mmcr1);
oprofilefs_create_ulong(sb, root, "mmcra", &sys.mmcra);
#ifdef CONFIG_OPROFILE_CELL
/* create a file the user tool can check to see what level of profiling
* support exits with this kernel. Initialize bit mask to indicate
* what support the kernel has:
* bit 0 - Supports SPU event profiling in addition to PPU
* event and cycles; and SPU cycle profiling
* bits 1-31 - Currently unused.
*
* If the file does not exist, then the kernel only supports SPU
* cycle profiling, PPU event and cycle profiling.
*/
oprofilefs_create_ulong(sb, root, "cell_support", &sys.cell_support);
sys.cell_support = 0x1; /* Note, the user OProfile tool must check
* that this bit is set before attempting to
* user SPU event profiling. Older kernels
* will not have this file, hence the user
* tool is not allowed to do SPU event
* profiling on older kernels. Older kernels
* will accept SPU events but collected data
* is garbage.
*/
#endif
#endif
for (i = 0; i < model->num_counters; ++i) {
struct dentry *dir;
char buf[4];
snprintf(buf, sizeof buf, "%d", i);
dir = oprofilefs_mkdir(sb, root, buf);
oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled);
oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event);
oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count);
/*
* Classic PowerPC doesn't support per-counter
* control like this, but the options are
* expected, so they remain. For Freescale
* Book-E style performance monitors, we do
* support them.
*/
oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel);
oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user);
oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask);
}
oprofilefs_create_ulong(sb, root, "enable_kernel", &sys.enable_kernel);
oprofilefs_create_ulong(sb, root, "enable_user", &sys.enable_user);
/* Default to tracing both kernel and user */
sys.enable_kernel = 1;
sys.enable_user = 1;
return 0;
}
int __init oprofile_arch_init(struct oprofile_operations *ops)
{
if (!cur_cpu_spec->oprofile_cpu_type)
return -ENODEV;
switch (cur_cpu_spec->oprofile_type) {
#ifdef CONFIG_PPC_BOOK3S_64
#ifdef CONFIG_OPROFILE_CELL
case PPC_OPROFILE_CELL:
if (firmware_has_feature(FW_FEATURE_LPAR))
return -ENODEV;
model = &op_model_cell;
ops->sync_start = model->sync_start;
ops->sync_stop = model->sync_stop;
break;
#endif
case PPC_OPROFILE_RS64:
model = &op_model_rs64;
break;
case PPC_OPROFILE_POWER4:
model = &op_model_power4;
break;
case PPC_OPROFILE_PA6T:
model = &op_model_pa6t;
break;
#endif
#ifdef CONFIG_6xx
case PPC_OPROFILE_G4:
model = &op_model_7450;
break;
#endif
#if defined(CONFIG_FSL_EMB_PERFMON)
case PPC_OPROFILE_FSL_EMB:
model = &op_model_fsl_emb;
break;
#endif
default:
return -ENODEV;
}
model->num_counters = cur_cpu_spec->num_pmcs;
ops->cpu_type = cur_cpu_spec->oprofile_cpu_type;
ops->create_files = op_powerpc_create_files;
ops->setup = op_powerpc_setup;
ops->shutdown = op_powerpc_shutdown;
ops->start = op_powerpc_start;
ops->stop = op_powerpc_stop;
ops->backtrace = op_powerpc_backtrace;
printk(KERN_DEBUG "oprofile: using %s performance monitoring.\n",
ops->cpu_type);
return 0;
}
void oprofile_arch_exit(void)
{
}
| gpl-2.0 |
klin1344/kernel_ville_US | drivers/power/test_power.c | 7780 | 11380 | /*
* Power supply driver for testing.
*
* Copyright 2010 Anton Vorontsov <cbouatmailru@gmail.com>
*
* Dynamic module parameter code from the Virtual Battery Driver
* Copyright (C) 2008 Pylone, Inc.
* By: Masashi YOKOTA <yokota@pylone.jp>
* Originally found here:
* http://downloads.pylone.jp/src/virtual_battery/virtual_battery-0.0.1.tar.bz2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/power_supply.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/vermagic.h>
static int ac_online = 1;
static int battery_status = POWER_SUPPLY_STATUS_DISCHARGING;
static int battery_health = POWER_SUPPLY_HEALTH_GOOD;
static int battery_present = 1; /* true */
static int battery_technology = POWER_SUPPLY_TECHNOLOGY_LION;
static int battery_capacity = 50;
static int test_power_get_ac_property(struct power_supply *psy,
enum power_supply_property psp,
union power_supply_propval *val)
{
switch (psp) {
case POWER_SUPPLY_PROP_ONLINE:
val->intval = ac_online;
break;
default:
return -EINVAL;
}
return 0;
}
static int test_power_get_battery_property(struct power_supply *psy,
enum power_supply_property psp,
union power_supply_propval *val)
{
switch (psp) {
case POWER_SUPPLY_PROP_MODEL_NAME:
val->strval = "Test battery";
break;
case POWER_SUPPLY_PROP_MANUFACTURER:
val->strval = "Linux";
break;
case POWER_SUPPLY_PROP_SERIAL_NUMBER:
val->strval = UTS_RELEASE;
break;
case POWER_SUPPLY_PROP_STATUS:
val->intval = battery_status;
break;
case POWER_SUPPLY_PROP_CHARGE_TYPE:
val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST;
break;
case POWER_SUPPLY_PROP_HEALTH:
val->intval = battery_health;
break;
case POWER_SUPPLY_PROP_PRESENT:
val->intval = battery_present;
break;
case POWER_SUPPLY_PROP_TECHNOLOGY:
val->intval = battery_technology;
break;
case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
break;
case POWER_SUPPLY_PROP_CAPACITY:
case POWER_SUPPLY_PROP_CHARGE_NOW:
val->intval = battery_capacity;
break;
case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
case POWER_SUPPLY_PROP_CHARGE_FULL:
val->intval = 100;
break;
case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG:
case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW:
val->intval = 3600;
break;
default:
pr_info("%s: some properties deliberately report errors.\n",
__func__);
return -EINVAL;
}
return 0;
}
static enum power_supply_property test_power_ac_props[] = {
POWER_SUPPLY_PROP_ONLINE,
};
static enum power_supply_property test_power_battery_props[] = {
POWER_SUPPLY_PROP_STATUS,
POWER_SUPPLY_PROP_CHARGE_TYPE,
POWER_SUPPLY_PROP_HEALTH,
POWER_SUPPLY_PROP_PRESENT,
POWER_SUPPLY_PROP_TECHNOLOGY,
POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
POWER_SUPPLY_PROP_CHARGE_FULL,
POWER_SUPPLY_PROP_CHARGE_NOW,
POWER_SUPPLY_PROP_CAPACITY,
POWER_SUPPLY_PROP_CAPACITY_LEVEL,
POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
POWER_SUPPLY_PROP_MODEL_NAME,
POWER_SUPPLY_PROP_MANUFACTURER,
POWER_SUPPLY_PROP_SERIAL_NUMBER,
};
static char *test_power_ac_supplied_to[] = {
"test_battery",
};
static struct power_supply test_power_supplies[] = {
{
.name = "test_ac",
.type = POWER_SUPPLY_TYPE_MAINS,
.supplied_to = test_power_ac_supplied_to,
.num_supplicants = ARRAY_SIZE(test_power_ac_supplied_to),
.properties = test_power_ac_props,
.num_properties = ARRAY_SIZE(test_power_ac_props),
.get_property = test_power_get_ac_property,
}, {
.name = "test_battery",
.type = POWER_SUPPLY_TYPE_BATTERY,
.properties = test_power_battery_props,
.num_properties = ARRAY_SIZE(test_power_battery_props),
.get_property = test_power_get_battery_property,
},
};
static int __init test_power_init(void)
{
int i;
int ret;
for (i = 0; i < ARRAY_SIZE(test_power_supplies); i++) {
ret = power_supply_register(NULL, &test_power_supplies[i]);
if (ret) {
pr_err("%s: failed to register %s\n", __func__,
test_power_supplies[i].name);
goto failed;
}
}
return 0;
failed:
while (--i >= 0)
power_supply_unregister(&test_power_supplies[i]);
return ret;
}
module_init(test_power_init);
static void __exit test_power_exit(void)
{
int i;
/* Let's see how we handle changes... */
ac_online = 0;
battery_status = POWER_SUPPLY_STATUS_DISCHARGING;
for (i = 0; i < ARRAY_SIZE(test_power_supplies); i++)
power_supply_changed(&test_power_supplies[i]);
pr_info("%s: 'changed' event sent, sleeping for 10 seconds...\n",
__func__);
ssleep(10);
for (i = 0; i < ARRAY_SIZE(test_power_supplies); i++)
power_supply_unregister(&test_power_supplies[i]);
}
module_exit(test_power_exit);
#define MAX_KEYLENGTH 256
struct battery_property_map {
int value;
char const *key;
};
static struct battery_property_map map_ac_online[] = {
{ 0, "on" },
{ 1, "off" },
{ -1, NULL },
};
static struct battery_property_map map_status[] = {
{ POWER_SUPPLY_STATUS_CHARGING, "charging" },
{ POWER_SUPPLY_STATUS_DISCHARGING, "discharging" },
{ POWER_SUPPLY_STATUS_NOT_CHARGING, "not-charging" },
{ POWER_SUPPLY_STATUS_FULL, "full" },
{ -1, NULL },
};
static struct battery_property_map map_health[] = {
{ POWER_SUPPLY_HEALTH_GOOD, "good" },
{ POWER_SUPPLY_HEALTH_OVERHEAT, "overheat" },
{ POWER_SUPPLY_HEALTH_DEAD, "dead" },
{ POWER_SUPPLY_HEALTH_OVERVOLTAGE, "overvoltage" },
{ POWER_SUPPLY_HEALTH_UNSPEC_FAILURE, "failure" },
{ -1, NULL },
};
static struct battery_property_map map_present[] = {
{ 0, "false" },
{ 1, "true" },
{ -1, NULL },
};
static struct battery_property_map map_technology[] = {
{ POWER_SUPPLY_TECHNOLOGY_NiMH, "NiMH" },
{ POWER_SUPPLY_TECHNOLOGY_LION, "LION" },
{ POWER_SUPPLY_TECHNOLOGY_LIPO, "LIPO" },
{ POWER_SUPPLY_TECHNOLOGY_LiFe, "LiFe" },
{ POWER_SUPPLY_TECHNOLOGY_NiCd, "NiCd" },
{ POWER_SUPPLY_TECHNOLOGY_LiMn, "LiMn" },
{ -1, NULL },
};
static int map_get_value(struct battery_property_map *map, const char *key,
int def_val)
{
char buf[MAX_KEYLENGTH];
int cr;
strncpy(buf, key, MAX_KEYLENGTH);
buf[MAX_KEYLENGTH-1] = '\0';
cr = strnlen(buf, MAX_KEYLENGTH) - 1;
if (buf[cr] == '\n')
buf[cr] = '\0';
while (map->key) {
if (strncasecmp(map->key, buf, MAX_KEYLENGTH) == 0)
return map->value;
map++;
}
return def_val;
}
static const char *map_get_key(struct battery_property_map *map, int value,
const char *def_key)
{
while (map->key) {
if (map->value == value)
return map->key;
map++;
}
return def_key;
}
static int param_set_ac_online(const char *key, const struct kernel_param *kp)
{
ac_online = map_get_value(map_ac_online, key, ac_online);
power_supply_changed(&test_power_supplies[0]);
return 0;
}
static int param_get_ac_online(char *buffer, const struct kernel_param *kp)
{
strcpy(buffer, map_get_key(map_ac_online, ac_online, "unknown"));
return strlen(buffer);
}
static int param_set_battery_status(const char *key,
const struct kernel_param *kp)
{
battery_status = map_get_value(map_status, key, battery_status);
power_supply_changed(&test_power_supplies[1]);
return 0;
}
static int param_get_battery_status(char *buffer, const struct kernel_param *kp)
{
strcpy(buffer, map_get_key(map_status, battery_status, "unknown"));
return strlen(buffer);
}
static int param_set_battery_health(const char *key,
const struct kernel_param *kp)
{
battery_health = map_get_value(map_health, key, battery_health);
power_supply_changed(&test_power_supplies[1]);
return 0;
}
static int param_get_battery_health(char *buffer, const struct kernel_param *kp)
{
strcpy(buffer, map_get_key(map_health, battery_health, "unknown"));
return strlen(buffer);
}
static int param_set_battery_present(const char *key,
const struct kernel_param *kp)
{
battery_present = map_get_value(map_present, key, battery_present);
power_supply_changed(&test_power_supplies[0]);
return 0;
}
static int param_get_battery_present(char *buffer,
const struct kernel_param *kp)
{
strcpy(buffer, map_get_key(map_present, battery_present, "unknown"));
return strlen(buffer);
}
static int param_set_battery_technology(const char *key,
const struct kernel_param *kp)
{
battery_technology = map_get_value(map_technology, key,
battery_technology);
power_supply_changed(&test_power_supplies[1]);
return 0;
}
static int param_get_battery_technology(char *buffer,
const struct kernel_param *kp)
{
strcpy(buffer,
map_get_key(map_technology, battery_technology, "unknown"));
return strlen(buffer);
}
static int param_set_battery_capacity(const char *key,
const struct kernel_param *kp)
{
int tmp;
if (1 != sscanf(key, "%d", &tmp))
return -EINVAL;
battery_capacity = tmp;
power_supply_changed(&test_power_supplies[1]);
return 0;
}
#define param_get_battery_capacity param_get_int
static struct kernel_param_ops param_ops_ac_online = {
.set = param_set_ac_online,
.get = param_get_ac_online,
};
static struct kernel_param_ops param_ops_battery_status = {
.set = param_set_battery_status,
.get = param_get_battery_status,
};
static struct kernel_param_ops param_ops_battery_present = {
.set = param_set_battery_present,
.get = param_get_battery_present,
};
static struct kernel_param_ops param_ops_battery_technology = {
.set = param_set_battery_technology,
.get = param_get_battery_technology,
};
static struct kernel_param_ops param_ops_battery_health = {
.set = param_set_battery_health,
.get = param_get_battery_health,
};
static struct kernel_param_ops param_ops_battery_capacity = {
.set = param_set_battery_capacity,
.get = param_get_battery_capacity,
};
#define param_check_ac_online(name, p) __param_check(name, p, void);
#define param_check_battery_status(name, p) __param_check(name, p, void);
#define param_check_battery_present(name, p) __param_check(name, p, void);
#define param_check_battery_technology(name, p) __param_check(name, p, void);
#define param_check_battery_health(name, p) __param_check(name, p, void);
#define param_check_battery_capacity(name, p) __param_check(name, p, void);
module_param(ac_online, ac_online, 0644);
MODULE_PARM_DESC(ac_online, "AC charging state <on|off>");
module_param(battery_status, battery_status, 0644);
MODULE_PARM_DESC(battery_status,
"battery status <charging|discharging|not-charging|full>");
module_param(battery_present, battery_present, 0644);
MODULE_PARM_DESC(battery_present,
"battery presence state <good|overheat|dead|overvoltage|failure>");
module_param(battery_technology, battery_technology, 0644);
MODULE_PARM_DESC(battery_technology,
"battery technology <NiMH|LION|LIPO|LiFe|NiCd|LiMn>");
module_param(battery_health, battery_health, 0644);
MODULE_PARM_DESC(battery_health,
"battery health state <good|overheat|dead|overvoltage|failure>");
module_param(battery_capacity, battery_capacity, 0644);
MODULE_PARM_DESC(battery_capacity, "battery capacity (percentage)");
MODULE_DESCRIPTION("Power supply driver for testing");
MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
MODULE_LICENSE("GPL");
| gpl-2.0 |
mythos234/TornadoRX-5.1-H815 | drivers/media/dvb-frontends/dib3000mb.c | 8804 | 23294 | /*
* Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
* DiBcom (http://www.dibcom.fr/)
*
* Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
*
* based on GPL code from DibCom, which has
*
* Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation, version 2.
*
* Acknowledgements
*
* Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
* sources, on which this driver (and the dvb-dibusb) are based.
*
* see Documentation/dvb/README.dvb-usb for more information
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "dib3000.h"
#include "dib3000mb_priv.h"
/* Version information */
#define DRIVER_VERSION "0.1"
#define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
#define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
#define deb_info(args...) dprintk(0x01,args)
#define deb_i2c(args...) dprintk(0x02,args)
#define deb_srch(args...) dprintk(0x04,args)
#define deb_info(args...) dprintk(0x01,args)
#define deb_xfer(args...) dprintk(0x02,args)
#define deb_setf(args...) dprintk(0x04,args)
#define deb_getf(args...) dprintk(0x08,args)
static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
{
u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
u8 rb[2];
struct i2c_msg msg[] = {
{ .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 },
{ .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
};
if (i2c_transfer(state->i2c, msg, 2) != 2)
deb_i2c("i2c read error\n");
deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
(rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
return (rb[0] << 8) | rb[1];
}
static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
{
u8 b[] = {
(reg >> 8) & 0xff, reg & 0xff,
(val >> 8) & 0xff, val & 0xff,
};
struct i2c_msg msg[] = {
{ .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
};
deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
}
static int dib3000_search_status(u16 irq,u16 lock)
{
if (irq & 0x02) {
if (lock & 0x01) {
deb_srch("auto search succeeded\n");
return 1; // auto search succeeded
} else {
deb_srch("auto search not successful\n");
return 0; // auto search failed
}
} else if (irq & 0x01) {
deb_srch("auto search failed\n");
return 0; // auto search failed
}
return -1; // try again
}
/* for auto search */
static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */
{ /* fft */
{ /* gua */
{ 0, 1 }, /* 0 0 { 0,1 } */
{ 3, 9 }, /* 0 1 { 0,1 } */
},
{
{ 2, 5 }, /* 1 0 { 0,1 } */
{ 6, 11 }, /* 1 1 { 0,1 } */
}
};
static int dib3000mb_get_frontend(struct dvb_frontend* fe);
static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
{
struct dib3000_state* state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
fe_code_rate_t fe_cr = FEC_NONE;
int search_state, seq;
if (tuner && fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe);
if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
deb_setf("bandwidth: ");
switch (c->bandwidth_hz) {
case 8000000:
deb_setf("8 MHz\n");
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
break;
case 7000000:
deb_setf("7 MHz\n");
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
break;
case 6000000:
deb_setf("6 MHz\n");
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
break;
case 0:
return -EOPNOTSUPP;
default:
err("unknown bandwidth value.");
return -EINVAL;
}
}
wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
deb_setf("transmission mode: ");
switch (c->transmission_mode) {
case TRANSMISSION_MODE_2K:
deb_setf("2k\n");
wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
break;
case TRANSMISSION_MODE_8K:
deb_setf("8k\n");
wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
break;
case TRANSMISSION_MODE_AUTO:
deb_setf("auto\n");
break;
default:
return -EINVAL;
}
deb_setf("guard: ");
switch (c->guard_interval) {
case GUARD_INTERVAL_1_32:
deb_setf("1_32\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
break;
case GUARD_INTERVAL_1_16:
deb_setf("1_16\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
break;
case GUARD_INTERVAL_1_8:
deb_setf("1_8\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
break;
case GUARD_INTERVAL_1_4:
deb_setf("1_4\n");
wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
break;
case GUARD_INTERVAL_AUTO:
deb_setf("auto\n");
break;
default:
return -EINVAL;
}
deb_setf("inversion: ");
switch (c->inversion) {
case INVERSION_OFF:
deb_setf("off\n");
wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
break;
case INVERSION_AUTO:
deb_setf("auto ");
break;
case INVERSION_ON:
deb_setf("on\n");
wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
break;
default:
return -EINVAL;
}
deb_setf("modulation: ");
switch (c->modulation) {
case QPSK:
deb_setf("qpsk\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
break;
case QAM_16:
deb_setf("qam16\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
break;
case QAM_64:
deb_setf("qam64\n");
wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
break;
case QAM_AUTO:
break;
default:
return -EINVAL;
}
deb_setf("hierarchy: ");
switch (c->hierarchy) {
case HIERARCHY_NONE:
deb_setf("none ");
/* fall through */
case HIERARCHY_1:
deb_setf("alpha=1\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
break;
case HIERARCHY_2:
deb_setf("alpha=2\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
break;
case HIERARCHY_4:
deb_setf("alpha=4\n");
wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
break;
case HIERARCHY_AUTO:
deb_setf("alpha=auto\n");
break;
default:
return -EINVAL;
}
deb_setf("hierarchy: ");
if (c->hierarchy == HIERARCHY_NONE) {
deb_setf("none\n");
wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
fe_cr = c->code_rate_HP;
} else if (c->hierarchy != HIERARCHY_AUTO) {
deb_setf("on\n");
wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
fe_cr = c->code_rate_LP;
}
deb_setf("fec: ");
switch (fe_cr) {
case FEC_1_2:
deb_setf("1_2\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
break;
case FEC_2_3:
deb_setf("2_3\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
break;
case FEC_3_4:
deb_setf("3_4\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
break;
case FEC_5_6:
deb_setf("5_6\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
break;
case FEC_7_8:
deb_setf("7_8\n");
wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
break;
case FEC_NONE:
deb_setf("none ");
break;
case FEC_AUTO:
deb_setf("auto\n");
break;
default:
return -EINVAL;
}
seq = dib3000_seq
[c->transmission_mode == TRANSMISSION_MODE_AUTO]
[c->guard_interval == GUARD_INTERVAL_AUTO]
[c->inversion == INVERSION_AUTO];
deb_setf("seq? %d\n", seq);
wr(DIB3000MB_REG_SEQ, seq);
wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
if (c->transmission_mode == TRANSMISSION_MODE_2K) {
if (c->guard_interval == GUARD_INTERVAL_1_8) {
wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
} else {
wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
}
wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
} else {
wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
}
wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
/* wait for AGC lock */
msleep(70);
wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
/* something has to be auto searched */
if (c->modulation == QAM_AUTO ||
c->hierarchy == HIERARCHY_AUTO ||
fe_cr == FEC_AUTO ||
c->inversion == INVERSION_AUTO) {
int as_count=0;
deb_setf("autosearch enabled.\n");
wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
while ((search_state =
dib3000_search_status(
rd(DIB3000MB_REG_AS_IRQ_PENDING),
rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
msleep(1);
deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
if (search_state == 1) {
if (dib3000mb_get_frontend(fe) == 0) {
deb_setf("reading tuning data from frontend succeeded.\n");
return dib3000mb_set_frontend(fe, 0);
}
}
} else {
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
}
return 0;
}
static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
{
struct dib3000_state* state = fe->demodulator_priv;
deb_info("dib3000mb is getting up.\n");
wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
wr_foreach(dib3000mb_reg_impulse_noise,
dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
return 0;
}
static int dib3000mb_get_frontend(struct dvb_frontend* fe)
{
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dib3000_state* state = fe->demodulator_priv;
fe_code_rate_t *cr;
u16 tps_val;
int inv_test1,inv_test2;
u32 dds_val, threshold = 0x800000;
if (!rd(DIB3000MB_REG_TPS_LOCK))
return 0;
dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
if (dds_val < threshold)
inv_test1 = 0;
else if (dds_val == threshold)
inv_test1 = 1;
else
inv_test1 = 2;
dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
if (dds_val < threshold)
inv_test2 = 0;
else if (dds_val == threshold)
inv_test2 = 1;
else
inv_test2 = 2;
c->inversion =
((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
INVERSION_ON : INVERSION_OFF;
deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
case DIB3000_CONSTELLATION_QPSK:
deb_getf("QPSK ");
c->modulation = QPSK;
break;
case DIB3000_CONSTELLATION_16QAM:
deb_getf("QAM16 ");
c->modulation = QAM_16;
break;
case DIB3000_CONSTELLATION_64QAM:
deb_getf("QAM64 ");
c->modulation = QAM_64;
break;
default:
err("Unexpected constellation returned by TPS (%d)", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
if (rd(DIB3000MB_REG_TPS_HRCH)) {
deb_getf("HRCH ON\n");
cr = &c->code_rate_LP;
c->code_rate_HP = FEC_NONE;
switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
case DIB3000_ALPHA_0:
deb_getf("HIERARCHY_NONE ");
c->hierarchy = HIERARCHY_NONE;
break;
case DIB3000_ALPHA_1:
deb_getf("HIERARCHY_1 ");
c->hierarchy = HIERARCHY_1;
break;
case DIB3000_ALPHA_2:
deb_getf("HIERARCHY_2 ");
c->hierarchy = HIERARCHY_2;
break;
case DIB3000_ALPHA_4:
deb_getf("HIERARCHY_4 ");
c->hierarchy = HIERARCHY_4;
break;
default:
err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
} else {
deb_getf("HRCH OFF\n");
cr = &c->code_rate_HP;
c->code_rate_LP = FEC_NONE;
c->hierarchy = HIERARCHY_NONE;
tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
}
switch (tps_val) {
case DIB3000_FEC_1_2:
deb_getf("FEC_1_2 ");
*cr = FEC_1_2;
break;
case DIB3000_FEC_2_3:
deb_getf("FEC_2_3 ");
*cr = FEC_2_3;
break;
case DIB3000_FEC_3_4:
deb_getf("FEC_3_4 ");
*cr = FEC_3_4;
break;
case DIB3000_FEC_5_6:
deb_getf("FEC_5_6 ");
*cr = FEC_4_5;
break;
case DIB3000_FEC_7_8:
deb_getf("FEC_7_8 ");
*cr = FEC_7_8;
break;
default:
err("Unexpected FEC returned by TPS (%d)", tps_val);
break;
}
deb_getf("TPS: %d\n",tps_val);
switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
case DIB3000_GUARD_TIME_1_32:
deb_getf("GUARD_INTERVAL_1_32 ");
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case DIB3000_GUARD_TIME_1_16:
deb_getf("GUARD_INTERVAL_1_16 ");
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case DIB3000_GUARD_TIME_1_8:
deb_getf("GUARD_INTERVAL_1_8 ");
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case DIB3000_GUARD_TIME_1_4:
deb_getf("GUARD_INTERVAL_1_4 ");
c->guard_interval = GUARD_INTERVAL_1_4;
break;
default:
err("Unexpected Guard Time returned by TPS (%d)", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
case DIB3000_TRANSMISSION_MODE_2K:
deb_getf("TRANSMISSION_MODE_2K ");
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case DIB3000_TRANSMISSION_MODE_8K:
deb_getf("TRANSMISSION_MODE_8K ");
c->transmission_mode = TRANSMISSION_MODE_8K;
break;
default:
err("unexpected transmission mode return by TPS (%d)", tps_val);
break;
}
deb_getf("TPS: %d\n", tps_val);
return 0;
}
static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
{
struct dib3000_state* state = fe->demodulator_priv;
*stat = 0;
if (rd(DIB3000MB_REG_AGC_LOCK))
*stat |= FE_HAS_SIGNAL;
if (rd(DIB3000MB_REG_CARRIER_LOCK))
*stat |= FE_HAS_CARRIER;
if (rd(DIB3000MB_REG_VIT_LCK))
*stat |= FE_HAS_VITERBI;
if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
*stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
deb_getf("actual status is %2x\n",*stat);
deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
rd(DIB3000MB_REG_TPS_LOCK),
rd(DIB3000MB_REG_TPS_QAM),
rd(DIB3000MB_REG_TPS_HRCH),
rd(DIB3000MB_REG_TPS_VIT_ALPHA),
rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
rd(DIB3000MB_REG_TPS_GUARD_TIME),
rd(DIB3000MB_REG_TPS_FFT),
rd(DIB3000MB_REG_TPS_CELL_ID));
//*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
return 0;
}
static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
{
struct dib3000_state* state = fe->demodulator_priv;
*ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
return 0;
}
/* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
{
struct dib3000_state* state = fe->demodulator_priv;
*strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
return 0;
}
static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
{
struct dib3000_state* state = fe->demodulator_priv;
short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
rd(DIB3000MB_REG_NOISE_POWER_LSB);
*snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
return 0;
}
static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
{
struct dib3000_state* state = fe->demodulator_priv;
*unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
return 0;
}
static int dib3000mb_sleep(struct dvb_frontend* fe)
{
struct dib3000_state* state = fe->demodulator_priv;
deb_info("dib3000mb is going to bed.\n");
wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
return 0;
}
static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 800;
return 0;
}
static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
{
return dib3000mb_fe_init(fe, 0);
}
static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
{
return dib3000mb_set_frontend(fe, 1);
}
static void dib3000mb_release(struct dvb_frontend* fe)
{
struct dib3000_state *state = fe->demodulator_priv;
kfree(state);
}
/* pid filter and transfer stuff */
static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
{
struct dib3000_state *state = fe->demodulator_priv;
pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
wr(index+DIB3000MB_REG_FIRST_PID,pid);
return 0;
}
static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
{
struct dib3000_state *state = fe->demodulator_priv;
deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
if (onoff) {
wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
} else {
wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
}
return 0;
}
static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
{
struct dib3000_state *state = fe->demodulator_priv;
deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
wr(DIB3000MB_REG_PID_PARSE,onoff);
return 0;
}
static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
{
struct dib3000_state *state = fe->demodulator_priv;
if (onoff) {
wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
} else {
wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
}
return 0;
}
static struct dvb_frontend_ops dib3000mb_ops;
struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
{
struct dib3000_state* state = NULL;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
if (state == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
memcpy(&state->config,config,sizeof(struct dib3000_config));
/* check for the correct demod */
if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
goto error;
if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
goto error;
/* create dvb_frontend */
memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
/* set the xfer operations */
xfer_ops->pid_parse = dib3000mb_pid_parse;
xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
xfer_ops->pid_ctrl = dib3000mb_pid_control;
xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
return &state->frontend;
error:
kfree(state);
return NULL;
}
static struct dvb_frontend_ops dib3000mb_ops = {
.delsys = { SYS_DVBT },
.info = {
.name = "DiBcom 3000M-B DVB-T",
.frequency_min = 44250000,
.frequency_max = 867250000,
.frequency_stepsize = 62500,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.release = dib3000mb_release,
.init = dib3000mb_fe_init_nonmobile,
.sleep = dib3000mb_sleep,
.set_frontend = dib3000mb_set_frontend_and_tuner,
.get_frontend = dib3000mb_get_frontend,
.get_tune_settings = dib3000mb_fe_get_tune_settings,
.read_status = dib3000mb_read_status,
.read_ber = dib3000mb_read_ber,
.read_signal_strength = dib3000mb_read_signal_strength,
.read_snr = dib3000mb_read_snr,
.read_ucblocks = dib3000mb_read_unc_blocks,
};
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(dib3000mb_attach);
| gpl-2.0 |
houstar/linux-3.8.8 | sound/soc/sh/fsi.c | 101 | 50202 | /*
* Fifo-attached Serial Interface (FSI) support for SH7724
*
* Copyright (C) 2009 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* Based on ssi.c
* Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/pm_runtime.h>
#include <linux/io.h>
#include <linux/scatterlist.h>
#include <linux/sh_dma.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/workqueue.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <sound/sh_fsi.h>
/* PortA/PortB register */
#define REG_DO_FMT 0x0000
#define REG_DOFF_CTL 0x0004
#define REG_DOFF_ST 0x0008
#define REG_DI_FMT 0x000C
#define REG_DIFF_CTL 0x0010
#define REG_DIFF_ST 0x0014
#define REG_CKG1 0x0018
#define REG_CKG2 0x001C
#define REG_DIDT 0x0020
#define REG_DODT 0x0024
#define REG_MUTE_ST 0x0028
#define REG_OUT_DMAC 0x002C
#define REG_OUT_SEL 0x0030
#define REG_IN_DMAC 0x0038
/* master register */
#define MST_CLK_RST 0x0210
#define MST_SOFT_RST 0x0214
#define MST_FIFO_SZ 0x0218
/* core register (depend on FSI version) */
#define A_MST_CTLR 0x0180
#define B_MST_CTLR 0x01A0
#define CPU_INT_ST 0x01F4
#define CPU_IEMSK 0x01F8
#define CPU_IMSK 0x01FC
#define INT_ST 0x0200
#define IEMSK 0x0204
#define IMSK 0x0208
/* DO_FMT */
/* DI_FMT */
#define CR_BWS_MASK (0x3 << 20) /* FSI2 */
#define CR_BWS_24 (0x0 << 20) /* FSI2 */
#define CR_BWS_16 (0x1 << 20) /* FSI2 */
#define CR_BWS_20 (0x2 << 20) /* FSI2 */
#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
#define CR_MONO (0x0 << 4)
#define CR_MONO_D (0x1 << 4)
#define CR_PCM (0x2 << 4)
#define CR_I2S (0x3 << 4)
#define CR_TDM (0x4 << 4)
#define CR_TDM_D (0x5 << 4)
/* OUT_DMAC */
/* IN_DMAC */
#define VDMD_MASK (0x3 << 4)
#define VDMD_FRONT (0x0 << 4) /* Package in front */
#define VDMD_BACK (0x1 << 4) /* Package in back */
#define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
#define DMA_ON (0x1 << 0)
/* DOFF_CTL */
/* DIFF_CTL */
#define IRQ_HALF 0x00100000
#define FIFO_CLR 0x00000001
/* DOFF_ST */
#define ERR_OVER 0x00000010
#define ERR_UNDER 0x00000001
#define ST_ERR (ERR_OVER | ERR_UNDER)
/* CKG1 */
#define ACKMD_MASK 0x00007000
#define BPFMD_MASK 0x00000700
#define DIMD (1 << 4)
#define DOMD (1 << 0)
/* A/B MST_CTLR */
#define BP (1 << 4) /* Fix the signal of Biphase output */
#define SE (1 << 0) /* Fix the master clock */
/* CLK_RST */
#define CRB (1 << 4)
#define CRA (1 << 0)
/* IO SHIFT / MACRO */
#define BI_SHIFT 12
#define BO_SHIFT 8
#define AI_SHIFT 4
#define AO_SHIFT 0
#define AB_IO(param, shift) (param << shift)
/* SOFT_RST */
#define PBSR (1 << 12) /* Port B Software Reset */
#define PASR (1 << 8) /* Port A Software Reset */
#define IR (1 << 4) /* Interrupt Reset */
#define FSISR (1 << 0) /* Software Reset */
/* OUT_SEL (FSI2) */
#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
/* 1: Biphase and serial */
/* FIFO_SZ */
#define FIFO_SZ_MASK 0x7
#define FSI_RATES SNDRV_PCM_RATE_8000_96000
#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
typedef int (*set_rate_func)(struct device *dev, int rate, int enable);
/*
* bus options
*
* 0x000000BA
*
* A : sample widtht 16bit setting
* B : sample widtht 24bit setting
*/
#define SHIFT_16DATA 0
#define SHIFT_24DATA 4
#define PACKAGE_24BITBUS_BACK 0
#define PACKAGE_24BITBUS_FRONT 1
#define PACKAGE_16BITBUS_STREAM 2
#define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
#define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
/*
* FSI driver use below type name for variable
*
* xxx_num : number of data
* xxx_pos : position of data
* xxx_capa : capacity of data
*/
/*
* period/frame/sample image
*
* ex) PCM (2ch)
*
* period pos period pos
* [n] [n + 1]
* |<-------------------- period--------------------->|
* ==|============================================ ... =|==
* | |
* ||<----- frame ----->|<------ frame ----->| ... |
* |+--------------------+--------------------+- ... |
* ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
* |+--------------------+--------------------+- ... |
* ==|============================================ ... =|==
*/
/*
* FSI FIFO image
*
* | |
* | |
* | [ sample ] |
* | [ sample ] |
* | [ sample ] |
* | [ sample ] |
* --> go to codecs
*/
/*
* FSI clock
*
* FSIxCLK [CPG] (ick) -------> |
* |-> FSI_DIV (div)-> FSI2
* FSIxCK [external] (xck) ---> |
*/
/*
* struct
*/
struct fsi_stream_handler;
struct fsi_stream {
/*
* these are initialized by fsi_stream_init()
*/
struct snd_pcm_substream *substream;
int fifo_sample_capa; /* sample capacity of FSI FIFO */
int buff_sample_capa; /* sample capacity of ALSA buffer */
int buff_sample_pos; /* sample position of ALSA buffer */
int period_samples; /* sample number / 1 period */
int period_pos; /* current period position */
int sample_width; /* sample width */
int uerr_num;
int oerr_num;
/*
* bus options
*/
u32 bus_option;
/*
* thse are initialized by fsi_handler_init()
*/
struct fsi_stream_handler *handler;
struct fsi_priv *priv;
/*
* these are for DMAEngine
*/
struct dma_chan *chan;
struct sh_dmae_slave slave; /* see fsi_handler_init() */
struct work_struct work;
dma_addr_t dma;
};
struct fsi_clk {
/* see [FSI clock] */
struct clk *own;
struct clk *xck;
struct clk *ick;
struct clk *div;
int (*set_rate)(struct device *dev,
struct fsi_priv *fsi,
unsigned long rate);
unsigned long rate;
unsigned int count;
};
struct fsi_priv {
void __iomem *base;
struct fsi_master *master;
struct sh_fsi_port_info *info;
struct fsi_stream playback;
struct fsi_stream capture;
struct fsi_clk clock;
u32 fmt;
int chan_num:16;
int clk_master:1;
int clk_cpg:1;
int spdif:1;
int enable_stream:1;
int bit_clk_inv:1;
int lr_clk_inv:1;
long rate;
};
struct fsi_stream_handler {
int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
int enable);
};
#define fsi_stream_handler_call(io, func, args...) \
(!(io) ? -ENODEV : \
!((io)->handler->func) ? 0 : \
(io)->handler->func(args))
struct fsi_core {
int ver;
u32 int_st;
u32 iemsk;
u32 imsk;
u32 a_mclk;
u32 b_mclk;
};
struct fsi_master {
void __iomem *base;
int irq;
struct fsi_priv fsia;
struct fsi_priv fsib;
struct fsi_core *core;
spinlock_t lock;
};
static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
/*
* basic read write function
*/
static void __fsi_reg_write(u32 __iomem *reg, u32 data)
{
/* valid data area is 24bit */
data &= 0x00ffffff;
__raw_writel(data, reg);
}
static u32 __fsi_reg_read(u32 __iomem *reg)
{
return __raw_readl(reg);
}
static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
{
u32 val = __fsi_reg_read(reg);
val &= ~mask;
val |= data & mask;
__fsi_reg_write(reg, val);
}
#define fsi_reg_write(p, r, d)\
__fsi_reg_write((p->base + REG_##r), d)
#define fsi_reg_read(p, r)\
__fsi_reg_read((p->base + REG_##r))
#define fsi_reg_mask_set(p, r, m, d)\
__fsi_reg_mask_set((p->base + REG_##r), m, d)
#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
{
u32 ret;
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
ret = __fsi_reg_read(master->base + reg);
spin_unlock_irqrestore(&master->lock, flags);
return ret;
}
#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
static void _fsi_master_mask_set(struct fsi_master *master,
u32 reg, u32 mask, u32 data)
{
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
__fsi_reg_mask_set(master->base + reg, mask, data);
spin_unlock_irqrestore(&master->lock, flags);
}
/*
* basic function
*/
static int fsi_version(struct fsi_master *master)
{
return master->core->ver;
}
static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
{
return fsi->master;
}
static int fsi_is_clk_master(struct fsi_priv *fsi)
{
return fsi->clk_master;
}
static int fsi_is_port_a(struct fsi_priv *fsi)
{
return fsi->master->base == fsi->base;
}
static int fsi_is_spdif(struct fsi_priv *fsi)
{
return fsi->spdif;
}
static int fsi_is_enable_stream(struct fsi_priv *fsi)
{
return fsi->enable_stream;
}
static int fsi_is_play(struct snd_pcm_substream *substream)
{
return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
}
static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
return rtd->cpu_dai;
}
static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
{
struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
if (dai->id == 0)
return &master->fsia;
else
return &master->fsib;
}
static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
{
return fsi_get_priv_frm_dai(fsi_get_dai(substream));
}
static set_rate_func fsi_get_info_set_rate(struct fsi_priv *fsi)
{
if (!fsi->info)
return NULL;
return fsi->info->set_rate;
}
static u32 fsi_get_info_flags(struct fsi_priv *fsi)
{
if (!fsi->info)
return 0;
return fsi->info->flags;
}
static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
{
int is_play = fsi_stream_is_play(fsi, io);
int is_porta = fsi_is_port_a(fsi);
u32 shift;
if (is_porta)
shift = is_play ? AO_SHIFT : AI_SHIFT;
else
shift = is_play ? BO_SHIFT : BI_SHIFT;
return shift;
}
static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
{
return frames * fsi->chan_num;
}
static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
{
return samples / fsi->chan_num;
}
static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
struct fsi_stream *io)
{
int is_play = fsi_stream_is_play(fsi, io);
u32 status;
int frames;
status = is_play ?
fsi_reg_read(fsi, DOFF_ST) :
fsi_reg_read(fsi, DIFF_ST);
frames = 0x1ff & (status >> 8);
return fsi_frame2sample(fsi, frames);
}
static void fsi_count_fifo_err(struct fsi_priv *fsi)
{
u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
u32 istatus = fsi_reg_read(fsi, DIFF_ST);
if (ostatus & ERR_OVER)
fsi->playback.oerr_num++;
if (ostatus & ERR_UNDER)
fsi->playback.uerr_num++;
if (istatus & ERR_OVER)
fsi->capture.oerr_num++;
if (istatus & ERR_UNDER)
fsi->capture.uerr_num++;
fsi_reg_write(fsi, DOFF_ST, 0);
fsi_reg_write(fsi, DIFF_ST, 0);
}
/*
* fsi_stream_xx() function
*/
static inline int fsi_stream_is_play(struct fsi_priv *fsi,
struct fsi_stream *io)
{
return &fsi->playback == io;
}
static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
struct snd_pcm_substream *substream)
{
return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
}
static int fsi_stream_is_working(struct fsi_priv *fsi,
struct fsi_stream *io)
{
struct fsi_master *master = fsi_get_master(fsi);
unsigned long flags;
int ret;
spin_lock_irqsave(&master->lock, flags);
ret = !!(io->substream && io->substream->runtime);
spin_unlock_irqrestore(&master->lock, flags);
return ret;
}
static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
{
return io->priv;
}
static void fsi_stream_init(struct fsi_priv *fsi,
struct fsi_stream *io,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsi_master *master = fsi_get_master(fsi);
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
io->substream = substream;
io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
io->buff_sample_pos = 0;
io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
io->period_pos = 0;
io->sample_width = samples_to_bytes(runtime, 1);
io->bus_option = 0;
io->oerr_num = -1; /* ignore 1st err */
io->uerr_num = -1; /* ignore 1st err */
fsi_stream_handler_call(io, init, fsi, io);
spin_unlock_irqrestore(&master->lock, flags);
}
static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_soc_dai *dai = fsi_get_dai(io->substream);
struct fsi_master *master = fsi_get_master(fsi);
unsigned long flags;
spin_lock_irqsave(&master->lock, flags);
if (io->oerr_num > 0)
dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
if (io->uerr_num > 0)
dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
fsi_stream_handler_call(io, quit, fsi, io);
io->substream = NULL;
io->buff_sample_capa = 0;
io->buff_sample_pos = 0;
io->period_samples = 0;
io->period_pos = 0;
io->sample_width = 0;
io->bus_option = 0;
io->oerr_num = 0;
io->uerr_num = 0;
spin_unlock_irqrestore(&master->lock, flags);
}
static int fsi_stream_transfer(struct fsi_stream *io)
{
struct fsi_priv *fsi = fsi_stream_to_priv(io);
if (!fsi)
return -EIO;
return fsi_stream_handler_call(io, transfer, fsi, io);
}
#define fsi_stream_start(fsi, io)\
fsi_stream_handler_call(io, start_stop, fsi, io, 1)
#define fsi_stream_stop(fsi, io)\
fsi_stream_handler_call(io, start_stop, fsi, io, 0)
static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
{
struct fsi_stream *io;
int ret1, ret2;
io = &fsi->playback;
ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
io = &fsi->capture;
ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
if (ret1 < 0)
return ret1;
if (ret2 < 0)
return ret2;
return 0;
}
static int fsi_stream_remove(struct fsi_priv *fsi)
{
struct fsi_stream *io;
int ret1, ret2;
io = &fsi->playback;
ret1 = fsi_stream_handler_call(io, remove, fsi, io);
io = &fsi->capture;
ret2 = fsi_stream_handler_call(io, remove, fsi, io);
if (ret1 < 0)
return ret1;
if (ret2 < 0)
return ret2;
return 0;
}
/*
* format/bus/dma setting
*/
static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
u32 bus, struct device *dev)
{
struct fsi_master *master = fsi_get_master(fsi);
int is_play = fsi_stream_is_play(fsi, io);
u32 fmt = fsi->fmt;
if (fsi_version(master) >= 2) {
u32 dma = 0;
/*
* FSI2 needs DMA/Bus setting
*/
switch (bus) {
case PACKAGE_24BITBUS_FRONT:
fmt |= CR_BWS_24;
dma |= VDMD_FRONT;
dev_dbg(dev, "24bit bus / package in front\n");
break;
case PACKAGE_16BITBUS_STREAM:
fmt |= CR_BWS_16;
dma |= VDMD_STREAM;
dev_dbg(dev, "16bit bus / stream mode\n");
break;
case PACKAGE_24BITBUS_BACK:
default:
fmt |= CR_BWS_24;
dma |= VDMD_BACK;
dev_dbg(dev, "24bit bus / package in back\n");
break;
}
if (is_play)
fsi_reg_write(fsi, OUT_DMAC, dma);
else
fsi_reg_write(fsi, IN_DMAC, dma);
}
if (is_play)
fsi_reg_write(fsi, DO_FMT, fmt);
else
fsi_reg_write(fsi, DI_FMT, fmt);
}
/*
* irq function
*/
static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
{
u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
struct fsi_master *master = fsi_get_master(fsi);
fsi_core_mask_set(master, imsk, data, data);
fsi_core_mask_set(master, iemsk, data, data);
}
static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
{
u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
struct fsi_master *master = fsi_get_master(fsi);
fsi_core_mask_set(master, imsk, data, 0);
fsi_core_mask_set(master, iemsk, data, 0);
}
static u32 fsi_irq_get_status(struct fsi_master *master)
{
return fsi_core_read(master, int_st);
}
static void fsi_irq_clear_status(struct fsi_priv *fsi)
{
u32 data = 0;
struct fsi_master *master = fsi_get_master(fsi);
data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
/* clear interrupt factor */
fsi_core_mask_set(master, int_st, data, 0);
}
/*
* SPDIF master clock function
*
* These functions are used later FSI2
*/
static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
{
struct fsi_master *master = fsi_get_master(fsi);
u32 mask, val;
mask = BP | SE;
val = enable ? mask : 0;
fsi_is_port_a(fsi) ?
fsi_core_mask_set(master, a_mclk, mask, val) :
fsi_core_mask_set(master, b_mclk, mask, val);
}
/*
* clock function
*/
static int fsi_clk_init(struct device *dev,
struct fsi_priv *fsi,
int xck,
int ick,
int div,
int (*set_rate)(struct device *dev,
struct fsi_priv *fsi,
unsigned long rate))
{
struct fsi_clk *clock = &fsi->clock;
int is_porta = fsi_is_port_a(fsi);
clock->xck = NULL;
clock->ick = NULL;
clock->div = NULL;
clock->rate = 0;
clock->count = 0;
clock->set_rate = set_rate;
clock->own = devm_clk_get(dev, NULL);
if (IS_ERR(clock->own))
return -EINVAL;
/* external clock */
if (xck) {
clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
if (IS_ERR(clock->xck)) {
dev_err(dev, "can't get xck clock\n");
return -EINVAL;
}
if (clock->xck == clock->own) {
dev_err(dev, "cpu doesn't support xck clock\n");
return -EINVAL;
}
}
/* FSIACLK/FSIBCLK */
if (ick) {
clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
if (IS_ERR(clock->ick)) {
dev_err(dev, "can't get ick clock\n");
return -EINVAL;
}
if (clock->ick == clock->own) {
dev_err(dev, "cpu doesn't support ick clock\n");
return -EINVAL;
}
}
/* FSI-DIV */
if (div) {
clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
if (IS_ERR(clock->div)) {
dev_err(dev, "can't get div clock\n");
return -EINVAL;
}
if (clock->div == clock->own) {
dev_err(dev, "cpu doens't support div clock\n");
return -EINVAL;
}
}
return 0;
}
#define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
{
fsi->clock.rate = rate;
}
static int fsi_clk_is_valid(struct fsi_priv *fsi)
{
return fsi->clock.set_rate &&
fsi->clock.rate;
}
static int fsi_clk_enable(struct device *dev,
struct fsi_priv *fsi,
unsigned long rate)
{
struct fsi_clk *clock = &fsi->clock;
int ret = -EINVAL;
if (!fsi_clk_is_valid(fsi))
return ret;
if (0 == clock->count) {
ret = clock->set_rate(dev, fsi, rate);
if (ret < 0) {
fsi_clk_invalid(fsi);
return ret;
}
if (clock->xck)
clk_enable(clock->xck);
if (clock->ick)
clk_enable(clock->ick);
if (clock->div)
clk_enable(clock->div);
clock->count++;
}
return ret;
}
static int fsi_clk_disable(struct device *dev,
struct fsi_priv *fsi)
{
struct fsi_clk *clock = &fsi->clock;
if (!fsi_clk_is_valid(fsi))
return -EINVAL;
if (1 == clock->count--) {
if (clock->xck)
clk_disable(clock->xck);
if (clock->ick)
clk_disable(clock->ick);
if (clock->div)
clk_disable(clock->div);
}
return 0;
}
static int fsi_clk_set_ackbpf(struct device *dev,
struct fsi_priv *fsi,
int ackmd, int bpfmd)
{
u32 data = 0;
/* check ackmd/bpfmd relationship */
if (bpfmd > ackmd) {
dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
return -EINVAL;
}
/* ACKMD */
switch (ackmd) {
case 512:
data |= (0x0 << 12);
break;
case 256:
data |= (0x1 << 12);
break;
case 128:
data |= (0x2 << 12);
break;
case 64:
data |= (0x3 << 12);
break;
case 32:
data |= (0x4 << 12);
break;
default:
dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
return -EINVAL;
}
/* BPFMD */
switch (bpfmd) {
case 32:
data |= (0x0 << 8);
break;
case 64:
data |= (0x1 << 8);
break;
case 128:
data |= (0x2 << 8);
break;
case 256:
data |= (0x3 << 8);
break;
case 512:
data |= (0x4 << 8);
break;
case 16:
data |= (0x7 << 8);
break;
default:
dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
return -EINVAL;
}
dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
udelay(10);
return 0;
}
static int fsi_clk_set_rate_external(struct device *dev,
struct fsi_priv *fsi,
unsigned long rate)
{
struct clk *xck = fsi->clock.xck;
struct clk *ick = fsi->clock.ick;
unsigned long xrate;
int ackmd, bpfmd;
int ret = 0;
/* check clock rate */
xrate = clk_get_rate(xck);
if (xrate % rate) {
dev_err(dev, "unsupported clock rate\n");
return -EINVAL;
}
clk_set_parent(ick, xck);
clk_set_rate(ick, xrate);
bpfmd = fsi->chan_num * 32;
ackmd = xrate / rate;
dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
if (ret < 0)
dev_err(dev, "%s failed", __func__);
return ret;
}
static int fsi_clk_set_rate_cpg(struct device *dev,
struct fsi_priv *fsi,
unsigned long rate)
{
struct clk *ick = fsi->clock.ick;
struct clk *div = fsi->clock.div;
unsigned long target = 0; /* 12288000 or 11289600 */
unsigned long actual, cout;
unsigned long diff, min;
unsigned long best_cout, best_act;
int adj;
int ackmd, bpfmd;
int ret = -EINVAL;
if (!(12288000 % rate))
target = 12288000;
if (!(11289600 % rate))
target = 11289600;
if (!target) {
dev_err(dev, "unsupported rate\n");
return ret;
}
bpfmd = fsi->chan_num * 32;
ackmd = target / rate;
ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
if (ret < 0) {
dev_err(dev, "%s failed", __func__);
return ret;
}
/*
* The clock flow is
*
* [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
*
* But, it needs to find best match of CPG and FSI_DIV
* combination, since it is difficult to generate correct
* frequency of audio clock from ick clock only.
* Because ick is created from its parent clock.
*
* target = rate x [512/256/128/64]fs
* cout = round(target x adjustment)
* actual = cout / adjustment (by FSI-DIV) ~= target
* audio = actual
*/
min = ~0;
best_cout = 0;
best_act = 0;
for (adj = 1; adj < 0xffff; adj++) {
cout = target * adj;
if (cout > 100000000) /* max clock = 100MHz */
break;
/* cout/actual audio clock */
cout = clk_round_rate(ick, cout);
actual = cout / adj;
/* find best frequency */
diff = abs(actual - target);
if (diff < min) {
min = diff;
best_cout = cout;
best_act = actual;
}
}
ret = clk_set_rate(ick, best_cout);
if (ret < 0) {
dev_err(dev, "ick clock failed\n");
return -EIO;
}
ret = clk_set_rate(div, clk_round_rate(div, best_act));
if (ret < 0) {
dev_err(dev, "div clock failed\n");
return -EIO;
}
dev_dbg(dev, "ick/div = %ld/%ld\n",
clk_get_rate(ick), clk_get_rate(div));
return ret;
}
static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
long rate, int enable)
{
set_rate_func set_rate = fsi_get_info_set_rate(fsi);
int ret;
/*
* CAUTION
*
* set_rate will be deleted
*/
if (!set_rate) {
if (enable)
return fsi_clk_enable(dev, fsi, rate);
else
return fsi_clk_disable(dev, fsi);
}
ret = set_rate(dev, rate, enable);
if (ret < 0) /* error */
return ret;
if (!enable)
return 0;
if (ret > 0) {
u32 data = 0;
switch (ret & SH_FSI_ACKMD_MASK) {
default:
/* FALL THROUGH */
case SH_FSI_ACKMD_512:
data |= (0x0 << 12);
break;
case SH_FSI_ACKMD_256:
data |= (0x1 << 12);
break;
case SH_FSI_ACKMD_128:
data |= (0x2 << 12);
break;
case SH_FSI_ACKMD_64:
data |= (0x3 << 12);
break;
case SH_FSI_ACKMD_32:
data |= (0x4 << 12);
break;
}
switch (ret & SH_FSI_BPFMD_MASK) {
default:
/* FALL THROUGH */
case SH_FSI_BPFMD_32:
data |= (0x0 << 8);
break;
case SH_FSI_BPFMD_64:
data |= (0x1 << 8);
break;
case SH_FSI_BPFMD_128:
data |= (0x2 << 8);
break;
case SH_FSI_BPFMD_256:
data |= (0x3 << 8);
break;
case SH_FSI_BPFMD_512:
data |= (0x4 << 8);
break;
case SH_FSI_BPFMD_16:
data |= (0x7 << 8);
break;
}
fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
udelay(10);
ret = 0;
}
return ret;
}
/*
* pio data transfer handler
*/
static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
{
int i;
if (fsi_is_enable_stream(fsi)) {
/*
* stream mode
* see
* fsi_pio_push_init()
*/
u32 *buf = (u32 *)_buf;
for (i = 0; i < samples / 2; i++)
fsi_reg_write(fsi, DODT, buf[i]);
} else {
/* normal mode */
u16 *buf = (u16 *)_buf;
for (i = 0; i < samples; i++)
fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
}
}
static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
{
u16 *buf = (u16 *)_buf;
int i;
for (i = 0; i < samples; i++)
*(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
}
static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
{
u32 *buf = (u32 *)_buf;
int i;
for (i = 0; i < samples; i++)
fsi_reg_write(fsi, DODT, *(buf + i));
}
static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
{
u32 *buf = (u32 *)_buf;
int i;
for (i = 0; i < samples; i++)
*(buf + i) = fsi_reg_read(fsi, DIDT);
}
static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_pcm_runtime *runtime = io->substream->runtime;
return runtime->dma_area +
samples_to_bytes(runtime, io->buff_sample_pos);
}
static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
int samples)
{
struct snd_pcm_runtime *runtime;
struct snd_pcm_substream *substream;
u8 *buf;
int over_period;
if (!fsi_stream_is_working(fsi, io))
return -EINVAL;
over_period = 0;
substream = io->substream;
runtime = substream->runtime;
/* FSI FIFO has limit.
* So, this driver can not send periods data at a time
*/
if (io->buff_sample_pos >=
io->period_samples * (io->period_pos + 1)) {
over_period = 1;
io->period_pos = (io->period_pos + 1) % runtime->periods;
if (0 == io->period_pos)
io->buff_sample_pos = 0;
}
buf = fsi_pio_get_area(fsi, io);
switch (io->sample_width) {
case 2:
run16(fsi, buf, samples);
break;
case 4:
run32(fsi, buf, samples);
break;
default:
return -EINVAL;
}
/* update buff_sample_pos */
io->buff_sample_pos += samples;
if (over_period)
snd_pcm_period_elapsed(substream);
return 0;
}
static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
{
int sample_residues; /* samples in FSI fifo */
int sample_space; /* ALSA free samples space */
int samples;
sample_residues = fsi_get_current_fifo_samples(fsi, io);
sample_space = io->buff_sample_capa - io->buff_sample_pos;
samples = min(sample_residues, sample_space);
return fsi_pio_transfer(fsi, io,
fsi_pio_pop16,
fsi_pio_pop32,
samples);
}
static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
{
int sample_residues; /* ALSA residue samples */
int sample_space; /* FSI fifo free samples space */
int samples;
sample_residues = io->buff_sample_capa - io->buff_sample_pos;
sample_space = io->fifo_sample_capa -
fsi_get_current_fifo_samples(fsi, io);
samples = min(sample_residues, sample_space);
return fsi_pio_transfer(fsi, io,
fsi_pio_push16,
fsi_pio_push32,
samples);
}
static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
int enable)
{
struct fsi_master *master = fsi_get_master(fsi);
u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
if (enable)
fsi_irq_enable(fsi, io);
else
fsi_irq_disable(fsi, io);
if (fsi_is_clk_master(fsi))
fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
}
static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
{
/*
* we can use 16bit stream mode
* when "playback" and "16bit data"
* and platform allows "stream mode"
* see
* fsi_pio_push16()
*/
if (fsi_is_enable_stream(fsi))
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
else
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
return 0;
}
static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
{
/*
* always 24bit bus, package back when "capture"
*/
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
return 0;
}
static struct fsi_stream_handler fsi_pio_push_handler = {
.init = fsi_pio_push_init,
.transfer = fsi_pio_push,
.start_stop = fsi_pio_start_stop,
};
static struct fsi_stream_handler fsi_pio_pop_handler = {
.init = fsi_pio_pop_init,
.transfer = fsi_pio_pop,
.start_stop = fsi_pio_start_stop,
};
static irqreturn_t fsi_interrupt(int irq, void *data)
{
struct fsi_master *master = data;
u32 int_st = fsi_irq_get_status(master);
/* clear irq status */
fsi_master_mask_set(master, SOFT_RST, IR, 0);
fsi_master_mask_set(master, SOFT_RST, IR, IR);
if (int_st & AB_IO(1, AO_SHIFT))
fsi_stream_transfer(&master->fsia.playback);
if (int_st & AB_IO(1, BO_SHIFT))
fsi_stream_transfer(&master->fsib.playback);
if (int_st & AB_IO(1, AI_SHIFT))
fsi_stream_transfer(&master->fsia.capture);
if (int_st & AB_IO(1, BI_SHIFT))
fsi_stream_transfer(&master->fsib.capture);
fsi_count_fifo_err(&master->fsia);
fsi_count_fifo_err(&master->fsib);
fsi_irq_clear_status(&master->fsia);
fsi_irq_clear_status(&master->fsib);
return IRQ_HANDLED;
}
/*
* dma data transfer handler
*/
static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_pcm_runtime *runtime = io->substream->runtime;
struct snd_soc_dai *dai = fsi_get_dai(io->substream);
enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
DMA_TO_DEVICE : DMA_FROM_DEVICE;
/*
* 24bit data : 24bit bus / package in back
* 16bit data : 16bit bus / stream mode
*/
io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
io->dma = dma_map_single(dai->dev, runtime->dma_area,
snd_pcm_lib_buffer_bytes(io->substream), dir);
return 0;
}
static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io)
{
struct snd_soc_dai *dai = fsi_get_dai(io->substream);
enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
DMA_TO_DEVICE : DMA_FROM_DEVICE;
dma_unmap_single(dai->dev, io->dma,
snd_pcm_lib_buffer_bytes(io->substream), dir);
return 0;
}
static dma_addr_t fsi_dma_get_area(struct fsi_stream *io)
{
struct snd_pcm_runtime *runtime = io->substream->runtime;
return io->dma + samples_to_bytes(runtime, io->buff_sample_pos);
}
static void fsi_dma_complete(void *data)
{
struct fsi_stream *io = (struct fsi_stream *)data;
struct fsi_priv *fsi = fsi_stream_to_priv(io);
struct snd_pcm_runtime *runtime = io->substream->runtime;
struct snd_soc_dai *dai = fsi_get_dai(io->substream);
enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
DMA_TO_DEVICE : DMA_FROM_DEVICE;
dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io),
samples_to_bytes(runtime, io->period_samples), dir);
io->buff_sample_pos += io->period_samples;
io->period_pos++;
if (io->period_pos >= runtime->periods) {
io->period_pos = 0;
io->buff_sample_pos = 0;
}
fsi_count_fifo_err(fsi);
fsi_stream_transfer(io);
snd_pcm_period_elapsed(io->substream);
}
static void fsi_dma_do_work(struct work_struct *work)
{
struct fsi_stream *io = container_of(work, struct fsi_stream, work);
struct fsi_priv *fsi = fsi_stream_to_priv(io);
struct snd_soc_dai *dai;
struct dma_async_tx_descriptor *desc;
struct snd_pcm_runtime *runtime;
enum dma_data_direction dir;
int is_play = fsi_stream_is_play(fsi, io);
int len;
dma_addr_t buf;
if (!fsi_stream_is_working(fsi, io))
return;
dai = fsi_get_dai(io->substream);
runtime = io->substream->runtime;
dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
len = samples_to_bytes(runtime, io->period_samples);
buf = fsi_dma_get_area(io);
dma_sync_single_for_device(dai->dev, buf, len, dir);
desc = dmaengine_prep_slave_single(io->chan, buf, len, dir,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
return;
}
desc->callback = fsi_dma_complete;
desc->callback_param = io;
if (dmaengine_submit(desc) < 0) {
dev_err(dai->dev, "tx_submit() fail\n");
return;
}
dma_async_issue_pending(io->chan);
/*
* FIXME
*
* In DMAEngine case, codec and FSI cannot be started simultaneously
* since FSI is using the scheduler work queue.
* Therefore, in capture case, probably FSI FIFO will have got
* overflow error in this point.
* in that case, DMA cannot start transfer until error was cleared.
*/
if (!is_play) {
if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
fsi_reg_write(fsi, DIFF_ST, 0);
}
}
}
static bool fsi_dma_filter(struct dma_chan *chan, void *param)
{
struct sh_dmae_slave *slave = param;
chan->private = slave;
return true;
}
static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
{
schedule_work(&io->work);
return 0;
}
static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
int start)
{
struct fsi_master *master = fsi_get_master(fsi);
u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
u32 enable = start ? DMA_ON : 0;
fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
dmaengine_terminate_all(io->chan);
if (fsi_is_clk_master(fsi))
fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
}
static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
{
dma_cap_mask_t mask;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave);
if (!io->chan) {
/* switch to PIO handler */
if (fsi_stream_is_play(fsi, io))
fsi->playback.handler = &fsi_pio_push_handler;
else
fsi->capture.handler = &fsi_pio_pop_handler;
dev_info(dev, "switch handler (dma => pio)\n");
/* probe again */
return fsi_stream_probe(fsi, dev);
}
INIT_WORK(&io->work, fsi_dma_do_work);
return 0;
}
static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
{
cancel_work_sync(&io->work);
fsi_stream_stop(fsi, io);
if (io->chan)
dma_release_channel(io->chan);
io->chan = NULL;
return 0;
}
static struct fsi_stream_handler fsi_dma_push_handler = {
.init = fsi_dma_init,
.quit = fsi_dma_quit,
.probe = fsi_dma_probe,
.transfer = fsi_dma_transfer,
.remove = fsi_dma_remove,
.start_stop = fsi_dma_push_start_stop,
};
/*
* dai ops
*/
static void fsi_fifo_init(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
struct fsi_master *master = fsi_get_master(fsi);
int is_play = fsi_stream_is_play(fsi, io);
u32 shift, i;
int frame_capa;
/* get on-chip RAM capacity */
shift = fsi_master_read(master, FIFO_SZ);
shift >>= fsi_get_port_shift(fsi, io);
shift &= FIFO_SZ_MASK;
frame_capa = 256 << shift;
dev_dbg(dev, "fifo = %d words\n", frame_capa);
/*
* The maximum number of sample data varies depending
* on the number of channels selected for the format.
*
* FIFOs are used in 4-channel units in 3-channel mode
* and in 8-channel units in 5- to 7-channel mode
* meaning that more FIFOs than the required size of DPRAM
* are used.
*
* ex) if 256 words of DP-RAM is connected
* 1 channel: 256 (256 x 1 = 256)
* 2 channels: 128 (128 x 2 = 256)
* 3 channels: 64 ( 64 x 3 = 192)
* 4 channels: 64 ( 64 x 4 = 256)
* 5 channels: 32 ( 32 x 5 = 160)
* 6 channels: 32 ( 32 x 6 = 192)
* 7 channels: 32 ( 32 x 7 = 224)
* 8 channels: 32 ( 32 x 8 = 256)
*/
for (i = 1; i < fsi->chan_num; i <<= 1)
frame_capa >>= 1;
dev_dbg(dev, "%d channel %d store\n",
fsi->chan_num, frame_capa);
io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
/*
* set interrupt generation factor
* clear FIFO
*/
if (is_play) {
fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
} else {
fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
}
}
static int fsi_hw_startup(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
u32 flags = fsi_get_info_flags(fsi);
u32 data = 0;
/* clock setting */
if (fsi_is_clk_master(fsi))
data = DIMD | DOMD;
fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
/* clock inversion (CKG2) */
data = 0;
if (fsi->bit_clk_inv)
data |= (1 << 0);
if (fsi->lr_clk_inv)
data |= (1 << 4);
if (fsi_is_clk_master(fsi))
data <<= 8;
/* FIXME
*
* SH_FSI_xxx_INV style will be removed
*/
if (SH_FSI_LRM_INV & flags)
data |= 1 << 12;
if (SH_FSI_BRM_INV & flags)
data |= 1 << 8;
if (SH_FSI_LRS_INV & flags)
data |= 1 << 4;
if (SH_FSI_BRS_INV & flags)
data |= 1 << 0;
fsi_reg_write(fsi, CKG2, data);
/* spdif ? */
if (fsi_is_spdif(fsi)) {
fsi_spdif_clk_ctrl(fsi, 1);
fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
}
/*
* get bus settings
*/
data = 0;
switch (io->sample_width) {
case 2:
data = BUSOP_GET(16, io->bus_option);
break;
case 4:
data = BUSOP_GET(24, io->bus_option);
break;
}
fsi_format_bus_setup(fsi, io, data, dev);
/* irq clear */
fsi_irq_disable(fsi, io);
fsi_irq_clear_status(fsi);
/* fifo init */
fsi_fifo_init(fsi, io, dev);
/* start master clock */
if (fsi_is_clk_master(fsi))
return fsi_set_master_clk(dev, fsi, fsi->rate, 1);
return 0;
}
static int fsi_hw_shutdown(struct fsi_priv *fsi,
struct device *dev)
{
/* stop master clock */
if (fsi_is_clk_master(fsi))
return fsi_set_master_clk(dev, fsi, fsi->rate, 0);
return 0;
}
static int fsi_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
fsi_clk_invalid(fsi);
fsi->rate = 0;
return 0;
}
static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
fsi_clk_invalid(fsi);
fsi->rate = 0;
}
static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
struct fsi_stream *io = fsi_stream_get(fsi, substream);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
fsi_stream_init(fsi, io, substream);
if (!ret)
ret = fsi_hw_startup(fsi, io, dai->dev);
if (!ret)
ret = fsi_stream_transfer(io);
if (!ret)
fsi_stream_start(fsi, io);
break;
case SNDRV_PCM_TRIGGER_STOP:
if (!ret)
ret = fsi_hw_shutdown(fsi, dai->dev);
fsi_stream_stop(fsi, io);
fsi_stream_quit(fsi, io);
break;
}
return ret;
}
static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
{
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
fsi->fmt = CR_I2S;
fsi->chan_num = 2;
break;
case SND_SOC_DAIFMT_LEFT_J:
fsi->fmt = CR_PCM;
fsi->chan_num = 2;
break;
default:
return -EINVAL;
}
return 0;
}
static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
{
struct fsi_master *master = fsi_get_master(fsi);
if (fsi_version(master) < 2)
return -EINVAL;
fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
fsi->chan_num = 2;
return 0;
}
static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
set_rate_func set_rate = fsi_get_info_set_rate(fsi);
int ret;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
fsi->clk_master = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
/* set clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_IF:
fsi->bit_clk_inv = 0;
fsi->lr_clk_inv = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
fsi->bit_clk_inv = 1;
fsi->lr_clk_inv = 0;
break;
case SND_SOC_DAIFMT_IB_IF:
fsi->bit_clk_inv = 1;
fsi->lr_clk_inv = 1;
break;
case SND_SOC_DAIFMT_NB_NF:
default:
fsi->bit_clk_inv = 0;
fsi->lr_clk_inv = 0;
break;
}
if (fsi_is_clk_master(fsi)) {
/*
* CAUTION
*
* set_rate will be deleted
*/
if (set_rate)
dev_warn(dai->dev, "set_rate will be removed soon\n");
if (fsi->clk_cpg)
fsi_clk_init(dai->dev, fsi, 0, 1, 1,
fsi_clk_set_rate_cpg);
else
fsi_clk_init(dai->dev, fsi, 1, 1, 0,
fsi_clk_set_rate_external);
}
/* set format */
if (fsi_is_spdif(fsi))
ret = fsi_set_fmt_spdif(fsi);
else
ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return ret;
}
static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
if (fsi_is_clk_master(fsi)) {
fsi->rate = params_rate(params);
fsi_clk_valid(fsi, fsi->rate);
}
return 0;
}
static const struct snd_soc_dai_ops fsi_dai_ops = {
.startup = fsi_dai_startup,
.shutdown = fsi_dai_shutdown,
.trigger = fsi_dai_trigger,
.set_fmt = fsi_dai_set_fmt,
.hw_params = fsi_dai_hw_params,
};
/*
* pcm ops
*/
static struct snd_pcm_hardware fsi_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE,
.formats = FSI_FMTS,
.rates = FSI_RATES,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = 64 * 1024,
.period_bytes_min = 32,
.period_bytes_max = 8192,
.periods_min = 1,
.periods_max = 32,
.fifo_size = 256,
};
static int fsi_pcm_open(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
int ret = 0;
snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
return ret;
}
static int fsi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
return snd_pcm_lib_malloc_pages(substream,
params_buffer_bytes(hw_params));
}
static int fsi_hw_free(struct snd_pcm_substream *substream)
{
return snd_pcm_lib_free_pages(substream);
}
static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
{
struct fsi_priv *fsi = fsi_get_priv(substream);
struct fsi_stream *io = fsi_stream_get(fsi, substream);
return fsi_sample2frame(fsi, io->buff_sample_pos);
}
static struct snd_pcm_ops fsi_pcm_ops = {
.open = fsi_pcm_open,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = fsi_hw_params,
.hw_free = fsi_hw_free,
.pointer = fsi_pointer,
};
/*
* snd_soc_platform
*/
#define PREALLOC_BUFFER (32 * 1024)
#define PREALLOC_BUFFER_MAX (32 * 1024)
static void fsi_pcm_free(struct snd_pcm *pcm)
{
snd_pcm_lib_preallocate_free_for_all(pcm);
}
static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
/*
* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
* in MMAP mode (i.e. aplay -M)
*/
return snd_pcm_lib_preallocate_pages_for_all(
pcm,
SNDRV_DMA_TYPE_CONTINUOUS,
snd_dma_continuous_data(GFP_KERNEL),
PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
}
/*
* alsa struct
*/
static struct snd_soc_dai_driver fsi_soc_dai[] = {
{
.name = "fsia-dai",
.playback = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &fsi_dai_ops,
},
{
.name = "fsib-dai",
.playback = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = FSI_RATES,
.formats = FSI_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &fsi_dai_ops,
},
};
static struct snd_soc_platform_driver fsi_soc_platform = {
.ops = &fsi_pcm_ops,
.pcm_new = fsi_pcm_new,
.pcm_free = fsi_pcm_free,
};
/*
* platform function
*/
static void fsi_port_info_init(struct fsi_priv *fsi,
struct sh_fsi_port_info *info)
{
if (info->flags & SH_FSI_FMT_SPDIF)
fsi->spdif = 1;
if (info->flags & SH_FSI_CLK_CPG)
fsi->clk_cpg = 1;
if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
fsi->enable_stream = 1;
}
static void fsi_handler_init(struct fsi_priv *fsi,
struct sh_fsi_port_info *info)
{
fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
fsi->playback.priv = fsi;
fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
fsi->capture.priv = fsi;
if (info->tx_id) {
fsi->playback.slave.shdma_slave.slave_id = info->tx_id;
fsi->playback.handler = &fsi_dma_push_handler;
}
}
static int fsi_probe(struct platform_device *pdev)
{
struct fsi_master *master;
const struct platform_device_id *id_entry;
struct sh_fsi_platform_info *info = pdev->dev.platform_data;
struct sh_fsi_port_info nul_info, *pinfo;
struct fsi_priv *fsi;
struct resource *res;
unsigned int irq;
int ret;
nul_info.flags = 0;
nul_info.tx_id = 0;
nul_info.rx_id = 0;
id_entry = pdev->id_entry;
if (!id_entry) {
dev_err(&pdev->dev, "unknown fsi device\n");
return -ENODEV;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (!res || (int)irq <= 0) {
dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
return -ENODEV;
}
master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
if (!master) {
dev_err(&pdev->dev, "Could not allocate master\n");
return -ENOMEM;
}
master->base = devm_ioremap_nocache(&pdev->dev,
res->start, resource_size(res));
if (!master->base) {
dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
return -ENXIO;
}
/* master setting */
master->irq = irq;
master->core = (struct fsi_core *)id_entry->driver_data;
spin_lock_init(&master->lock);
/* FSI A setting */
pinfo = (info) ? &info->port_a : &nul_info;
fsi = &master->fsia;
fsi->base = master->base;
fsi->master = master;
fsi->info = pinfo;
fsi_port_info_init(fsi, pinfo);
fsi_handler_init(fsi, pinfo);
ret = fsi_stream_probe(fsi, &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "FSIA stream probe failed\n");
return ret;
}
/* FSI B setting */
pinfo = (info) ? &info->port_b : &nul_info;
fsi = &master->fsib;
fsi->base = master->base + 0x40;
fsi->master = master;
fsi->info = pinfo;
fsi_port_info_init(fsi, pinfo);
fsi_handler_init(fsi, pinfo);
ret = fsi_stream_probe(fsi, &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "FSIB stream probe failed\n");
goto exit_fsia;
}
pm_runtime_enable(&pdev->dev);
dev_set_drvdata(&pdev->dev, master);
ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
id_entry->name, master);
if (ret) {
dev_err(&pdev->dev, "irq request err\n");
goto exit_fsib;
}
ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
if (ret < 0) {
dev_err(&pdev->dev, "cannot snd soc register\n");
goto exit_fsib;
}
ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
ARRAY_SIZE(fsi_soc_dai));
if (ret < 0) {
dev_err(&pdev->dev, "cannot snd dai register\n");
goto exit_snd_soc;
}
return ret;
exit_snd_soc:
snd_soc_unregister_platform(&pdev->dev);
exit_fsib:
pm_runtime_disable(&pdev->dev);
fsi_stream_remove(&master->fsib);
exit_fsia:
fsi_stream_remove(&master->fsia);
return ret;
}
static int fsi_remove(struct platform_device *pdev)
{
struct fsi_master *master;
master = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
snd_soc_unregister_platform(&pdev->dev);
fsi_stream_remove(&master->fsia);
fsi_stream_remove(&master->fsib);
return 0;
}
static void __fsi_suspend(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
if (!fsi_stream_is_working(fsi, io))
return;
fsi_stream_stop(fsi, io);
fsi_hw_shutdown(fsi, dev);
}
static void __fsi_resume(struct fsi_priv *fsi,
struct fsi_stream *io,
struct device *dev)
{
if (!fsi_stream_is_working(fsi, io))
return;
fsi_hw_startup(fsi, io, dev);
fsi_stream_start(fsi, io);
}
static int fsi_suspend(struct device *dev)
{
struct fsi_master *master = dev_get_drvdata(dev);
struct fsi_priv *fsia = &master->fsia;
struct fsi_priv *fsib = &master->fsib;
__fsi_suspend(fsia, &fsia->playback, dev);
__fsi_suspend(fsia, &fsia->capture, dev);
__fsi_suspend(fsib, &fsib->playback, dev);
__fsi_suspend(fsib, &fsib->capture, dev);
return 0;
}
static int fsi_resume(struct device *dev)
{
struct fsi_master *master = dev_get_drvdata(dev);
struct fsi_priv *fsia = &master->fsia;
struct fsi_priv *fsib = &master->fsib;
__fsi_resume(fsia, &fsia->playback, dev);
__fsi_resume(fsia, &fsia->capture, dev);
__fsi_resume(fsib, &fsib->playback, dev);
__fsi_resume(fsib, &fsib->capture, dev);
return 0;
}
static struct dev_pm_ops fsi_pm_ops = {
.suspend = fsi_suspend,
.resume = fsi_resume,
};
static struct fsi_core fsi1_core = {
.ver = 1,
/* Interrupt */
.int_st = INT_ST,
.iemsk = IEMSK,
.imsk = IMSK,
};
static struct fsi_core fsi2_core = {
.ver = 2,
/* Interrupt */
.int_st = CPU_INT_ST,
.iemsk = CPU_IEMSK,
.imsk = CPU_IMSK,
.a_mclk = A_MST_CTLR,
.b_mclk = B_MST_CTLR,
};
static struct platform_device_id fsi_id_table[] = {
{ "sh_fsi", (kernel_ulong_t)&fsi1_core },
{ "sh_fsi2", (kernel_ulong_t)&fsi2_core },
{},
};
MODULE_DEVICE_TABLE(platform, fsi_id_table);
static struct platform_driver fsi_driver = {
.driver = {
.name = "fsi-pcm-audio",
.pm = &fsi_pm_ops,
},
.probe = fsi_probe,
.remove = fsi_remove,
.id_table = fsi_id_table,
};
module_platform_driver(fsi_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_ALIAS("platform:fsi-pcm-audio");
| gpl-2.0 |
find7a/android_kernel_oppo_msm8974 | kernel/rcutree.c | 101 | 84895 | /*
* Read-Copy Update mechanism for mutual exclusion
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright IBM Corporation, 2008
*
* Authors: Dipankar Sarma <dipankar@in.ibm.com>
* Manfred Spraul <manfred@colorfullife.com>
* Paul E. McKenney <paulmck@linux.vnet.ibm.com> Hierarchical version
*
* Based on the original work by Paul McKenney <paulmck@us.ibm.com>
* and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen.
*
* For detailed explanation of Read-Copy Update mechanism see -
* Documentation/RCU
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/rcupdate.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/nmi.h>
#include <linux/atomic.h>
#include <linux/bitops.h>
#include <linux/export.h>
#include <linux/completion.h>
#include <linux/moduleparam.h>
#include <linux/percpu.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/mutex.h>
#include <linux/time.h>
#include <linux/kernel_stat.h>
#include <linux/wait.h>
#include <linux/kthread.h>
#include <linux/prefetch.h>
#include <linux/delay.h>
#include <linux/stop_machine.h>
#include "rcutree.h"
#include <trace/events/rcu.h>
#include "rcu.h"
/* Data structures. */
static struct lock_class_key rcu_node_class[NUM_RCU_LVLS];
#define RCU_STATE_INITIALIZER(structname) { \
.level = { &structname##_state.node[0] }, \
.levelcnt = { \
NUM_RCU_LVL_0, /* root of hierarchy. */ \
NUM_RCU_LVL_1, \
NUM_RCU_LVL_2, \
NUM_RCU_LVL_3, \
NUM_RCU_LVL_4, /* == MAX_RCU_LVLS */ \
}, \
.fqs_state = RCU_GP_IDLE, \
.gpnum = -300, \
.completed = -300, \
.onofflock = __RAW_SPIN_LOCK_UNLOCKED(&structname##_state.onofflock), \
.orphan_nxttail = &structname##_state.orphan_nxtlist, \
.orphan_donetail = &structname##_state.orphan_donelist, \
.fqslock = __RAW_SPIN_LOCK_UNLOCKED(&structname##_state.fqslock), \
.n_force_qs = 0, \
.n_force_qs_ngp = 0, \
.name = #structname, \
}
struct rcu_state rcu_sched_state = RCU_STATE_INITIALIZER(rcu_sched);
DEFINE_PER_CPU(struct rcu_data, rcu_sched_data);
struct rcu_state rcu_bh_state = RCU_STATE_INITIALIZER(rcu_bh);
DEFINE_PER_CPU(struct rcu_data, rcu_bh_data);
static struct rcu_state *rcu_state;
/*
* The rcu_scheduler_active variable transitions from zero to one just
* before the first task is spawned. So when this variable is zero, RCU
* can assume that there is but one task, allowing RCU to (for example)
* optimized synchronize_sched() to a simple barrier(). When this variable
* is one, RCU must actually do all the hard work required to detect real
* grace periods. This variable is also used to suppress boot-time false
* positives from lockdep-RCU error checking.
*/
int rcu_scheduler_active __read_mostly;
EXPORT_SYMBOL_GPL(rcu_scheduler_active);
/*
* The rcu_scheduler_fully_active variable transitions from zero to one
* during the early_initcall() processing, which is after the scheduler
* is capable of creating new tasks. So RCU processing (for example,
* creating tasks for RCU priority boosting) must be delayed until after
* rcu_scheduler_fully_active transitions from zero to one. We also
* currently delay invocation of any RCU callbacks until after this point.
*
* It might later prove better for people registering RCU callbacks during
* early boot to take responsibility for these callbacks, but one step at
* a time.
*/
static int rcu_scheduler_fully_active __read_mostly;
#ifdef CONFIG_RCU_BOOST
/*
* Control variables for per-CPU and per-rcu_node kthreads. These
* handle all flavors of RCU.
*/
static DEFINE_PER_CPU(struct task_struct *, rcu_cpu_kthread_task);
DEFINE_PER_CPU(unsigned int, rcu_cpu_kthread_status);
DEFINE_PER_CPU(unsigned int, rcu_cpu_kthread_loops);
DEFINE_PER_CPU(char, rcu_cpu_has_work);
#endif /* #ifdef CONFIG_RCU_BOOST */
static void rcu_boost_kthread_setaffinity(struct rcu_node *rnp, int outgoingcpu);
static void invoke_rcu_core(void);
static void invoke_rcu_callbacks(struct rcu_state *rsp, struct rcu_data *rdp);
/*
* Track the rcutorture test sequence number and the update version
* number within a given test. The rcutorture_testseq is incremented
* on every rcutorture module load and unload, so has an odd value
* when a test is running. The rcutorture_vernum is set to zero
* when rcutorture starts and is incremented on each rcutorture update.
* These variables enable correlating rcutorture output with the
* RCU tracing information.
*/
unsigned long rcutorture_testseq;
unsigned long rcutorture_vernum;
/* State information for rcu_barrier() and friends. */
static DEFINE_PER_CPU(struct rcu_head, rcu_barrier_head) = {NULL};
static atomic_t rcu_barrier_cpu_count;
static DEFINE_MUTEX(rcu_barrier_mutex);
static struct completion rcu_barrier_completion;
/*
* Return true if an RCU grace period is in progress. The ACCESS_ONCE()s
* permit this function to be invoked without holding the root rcu_node
* structure's ->lock, but of course results can be subject to change.
*/
static int rcu_gp_in_progress(struct rcu_state *rsp)
{
return ACCESS_ONCE(rsp->completed) != ACCESS_ONCE(rsp->gpnum);
}
/*
* Note a quiescent state. Because we do not need to know
* how many quiescent states passed, just if there was at least
* one since the start of the grace period, this just sets a flag.
* The caller must have disabled preemption.
*/
void rcu_sched_qs(int cpu)
{
struct rcu_data *rdp = &per_cpu(rcu_sched_data, cpu);
rdp->passed_quiesce_gpnum = rdp->gpnum;
barrier();
if (rdp->passed_quiesce == 0)
trace_rcu_grace_period("rcu_sched", rdp->gpnum, "cpuqs");
rdp->passed_quiesce = 1;
}
void rcu_bh_qs(int cpu)
{
struct rcu_data *rdp = &per_cpu(rcu_bh_data, cpu);
rdp->passed_quiesce_gpnum = rdp->gpnum;
barrier();
if (rdp->passed_quiesce == 0)
trace_rcu_grace_period("rcu_bh", rdp->gpnum, "cpuqs");
rdp->passed_quiesce = 1;
}
/*
* Note a context switch. This is a quiescent state for RCU-sched,
* and requires special handling for preemptible RCU.
* The caller must have disabled preemption.
*/
void rcu_note_context_switch(int cpu)
{
trace_rcu_utilization("Start context switch");
rcu_sched_qs(cpu);
rcu_preempt_note_context_switch(cpu);
trace_rcu_utilization("End context switch");
}
EXPORT_SYMBOL_GPL(rcu_note_context_switch);
DEFINE_PER_CPU(struct rcu_dynticks, rcu_dynticks) = {
.dynticks_nesting = DYNTICK_TASK_EXIT_IDLE,
.dynticks = ATOMIC_INIT(1),
};
static long blimit = 10; /* Maximum callbacks per rcu_do_batch. */
static long qhimark = 10000; /* If this many pending, ignore blimit. */
static long qlowmark = 100; /* Once only this many pending, use blimit. */
module_param(blimit, long, 0);
module_param(qhimark, long, 0);
module_param(qlowmark, long, 0);
int rcu_cpu_stall_suppress __read_mostly; /* 1 = suppress stall warnings. */
int rcu_cpu_stall_timeout __read_mostly = CONFIG_RCU_CPU_STALL_TIMEOUT;
module_param(rcu_cpu_stall_suppress, int, 0644);
module_param(rcu_cpu_stall_timeout, int, 0644);
static void force_quiescent_state(struct rcu_state *rsp, int relaxed);
static int rcu_pending(int cpu);
/*
* Return the number of RCU-sched batches processed thus far for debug & stats.
*/
long rcu_batches_completed_sched(void)
{
return rcu_sched_state.completed;
}
EXPORT_SYMBOL_GPL(rcu_batches_completed_sched);
/*
* Return the number of RCU BH batches processed thus far for debug & stats.
*/
long rcu_batches_completed_bh(void)
{
return rcu_bh_state.completed;
}
EXPORT_SYMBOL_GPL(rcu_batches_completed_bh);
/*
* Force a quiescent state for RCU BH.
*/
void rcu_bh_force_quiescent_state(void)
{
force_quiescent_state(&rcu_bh_state, 0);
}
EXPORT_SYMBOL_GPL(rcu_bh_force_quiescent_state);
/*
* Record the number of times rcutorture tests have been initiated and
* terminated. This information allows the debugfs tracing stats to be
* correlated to the rcutorture messages, even when the rcutorture module
* is being repeatedly loaded and unloaded. In other words, we cannot
* store this state in rcutorture itself.
*/
void rcutorture_record_test_transition(void)
{
rcutorture_testseq++;
rcutorture_vernum = 0;
}
EXPORT_SYMBOL_GPL(rcutorture_record_test_transition);
/*
* Record the number of writer passes through the current rcutorture test.
* This is also used to correlate debugfs tracing stats with the rcutorture
* messages.
*/
void rcutorture_record_progress(unsigned long vernum)
{
rcutorture_vernum++;
}
EXPORT_SYMBOL_GPL(rcutorture_record_progress);
/*
* Force a quiescent state for RCU-sched.
*/
void rcu_sched_force_quiescent_state(void)
{
force_quiescent_state(&rcu_sched_state, 0);
}
EXPORT_SYMBOL_GPL(rcu_sched_force_quiescent_state);
/*
* Does the CPU have callbacks ready to be invoked?
*/
static int
cpu_has_callbacks_ready_to_invoke(struct rcu_data *rdp)
{
return &rdp->nxtlist != rdp->nxttail[RCU_DONE_TAIL];
}
/*
* Does the current CPU require a yet-as-unscheduled grace period?
*/
static int
cpu_needs_another_gp(struct rcu_state *rsp, struct rcu_data *rdp)
{
return *rdp->nxttail[RCU_DONE_TAIL +
ACCESS_ONCE(rsp->completed) != rdp->completed] &&
!rcu_gp_in_progress(rsp);
}
/*
* Return the root node of the specified rcu_state structure.
*/
static struct rcu_node *rcu_get_root(struct rcu_state *rsp)
{
return &rsp->node[0];
}
/*
* If the specified CPU is offline, tell the caller that it is in
* a quiescent state. Otherwise, whack it with a reschedule IPI.
* Grace periods can end up waiting on an offline CPU when that
* CPU is in the process of coming online -- it will be added to the
* rcu_node bitmasks before it actually makes it online. The same thing
* can happen while a CPU is in the process of coming online. Because this
* race is quite rare, we check for it after detecting that the grace
* period has been delayed rather than checking each and every CPU
* each and every time we start a new grace period.
*/
static int rcu_implicit_offline_qs(struct rcu_data *rdp)
{
/*
* If the CPU is offline for more than a jiffy, it is in a quiescent
* state. We can trust its state not to change because interrupts
* are disabled. The reason for the jiffy's worth of slack is to
* handle CPUs initializing on the way up and finding their way
* to the idle loop on the way down.
*/
if (cpu_is_offline(rdp->cpu) &&
ULONG_CMP_LT(rdp->rsp->gp_start + 2, jiffies)) {
trace_rcu_fqs(rdp->rsp->name, rdp->gpnum, rdp->cpu, "ofl");
rdp->offline_fqs++;
return 1;
}
return 0;
}
/*
* rcu_idle_enter_common - inform RCU that current CPU is moving towards idle
*
* If the new value of the ->dynticks_nesting counter now is zero,
* we really have entered idle, and must do the appropriate accounting.
* The caller must have disabled interrupts.
*/
static void rcu_idle_enter_common(struct rcu_dynticks *rdtp, long long oldval)
{
trace_rcu_dyntick("Start", oldval, 0);
if (!is_idle_task(current)) {
struct task_struct *idle = idle_task(smp_processor_id());
trace_rcu_dyntick("Error on entry: not idle task", oldval, 0);
ftrace_dump(DUMP_ALL);
WARN_ONCE(1, "Current pid: %d comm: %s / Idle pid: %d comm: %s",
current->pid, current->comm,
idle->pid, idle->comm); /* must be idle task! */
}
rcu_prepare_for_idle(smp_processor_id());
/* CPUs seeing atomic_inc() must see prior RCU read-side crit sects */
smp_mb__before_atomic_inc(); /* See above. */
atomic_inc(&rdtp->dynticks);
smp_mb__after_atomic_inc(); /* Force ordering with next sojourn. */
WARN_ON_ONCE(atomic_read(&rdtp->dynticks) & 0x1);
/*
* The idle task is not permitted to enter the idle loop while
* in an RCU read-side critical section.
*/
rcu_lockdep_assert(!lock_is_held(&rcu_lock_map),
"Illegal idle entry in RCU read-side critical section.");
rcu_lockdep_assert(!lock_is_held(&rcu_bh_lock_map),
"Illegal idle entry in RCU-bh read-side critical section.");
rcu_lockdep_assert(!lock_is_held(&rcu_sched_lock_map),
"Illegal idle entry in RCU-sched read-side critical section.");
}
/**
* rcu_idle_enter - inform RCU that current CPU is entering idle
*
* Enter idle mode, in other words, -leave- the mode in which RCU
* read-side critical sections can occur. (Though RCU read-side
* critical sections can occur in irq handlers in idle, a possibility
* handled by irq_enter() and irq_exit().)
*
* We crowbar the ->dynticks_nesting field to zero to allow for
* the possibility of usermode upcalls having messed up our count
* of interrupt nesting level during the prior busy period.
*/
void rcu_idle_enter(void)
{
unsigned long flags;
long long oldval;
struct rcu_dynticks *rdtp;
local_irq_save(flags);
rdtp = &__get_cpu_var(rcu_dynticks);
oldval = rdtp->dynticks_nesting;
WARN_ON_ONCE((oldval & DYNTICK_TASK_NEST_MASK) == 0);
if ((oldval & DYNTICK_TASK_NEST_MASK) == DYNTICK_TASK_NEST_VALUE)
rdtp->dynticks_nesting = 0;
else
rdtp->dynticks_nesting -= DYNTICK_TASK_NEST_VALUE;
rcu_idle_enter_common(rdtp, oldval);
local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(rcu_idle_enter);
/**
* rcu_irq_exit - inform RCU that current CPU is exiting irq towards idle
*
* Exit from an interrupt handler, which might possibly result in entering
* idle mode, in other words, leaving the mode in which read-side critical
* sections can occur.
*
* This code assumes that the idle loop never does anything that might
* result in unbalanced calls to irq_enter() and irq_exit(). If your
* architecture violates this assumption, RCU will give you what you
* deserve, good and hard. But very infrequently and irreproducibly.
*
* Use things like work queues to work around this limitation.
*
* You have been warned.
*/
void rcu_irq_exit(void)
{
unsigned long flags;
long long oldval;
struct rcu_dynticks *rdtp;
local_irq_save(flags);
rdtp = &__get_cpu_var(rcu_dynticks);
oldval = rdtp->dynticks_nesting;
rdtp->dynticks_nesting--;
WARN_ON_ONCE(rdtp->dynticks_nesting < 0);
if (rdtp->dynticks_nesting)
trace_rcu_dyntick("--=", oldval, rdtp->dynticks_nesting);
else
rcu_idle_enter_common(rdtp, oldval);
local_irq_restore(flags);
}
/*
* rcu_idle_exit_common - inform RCU that current CPU is moving away from idle
*
* If the new value of the ->dynticks_nesting counter was previously zero,
* we really have exited idle, and must do the appropriate accounting.
* The caller must have disabled interrupts.
*/
static void rcu_idle_exit_common(struct rcu_dynticks *rdtp, long long oldval)
{
smp_mb__before_atomic_inc(); /* Force ordering w/previous sojourn. */
atomic_inc(&rdtp->dynticks);
/* CPUs seeing atomic_inc() must see later RCU read-side crit sects */
smp_mb__after_atomic_inc(); /* See above. */
WARN_ON_ONCE(!(atomic_read(&rdtp->dynticks) & 0x1));
rcu_cleanup_after_idle(smp_processor_id());
trace_rcu_dyntick("End", oldval, rdtp->dynticks_nesting);
if (!is_idle_task(current)) {
struct task_struct *idle = idle_task(smp_processor_id());
trace_rcu_dyntick("Error on exit: not idle task",
oldval, rdtp->dynticks_nesting);
ftrace_dump(DUMP_ALL);
WARN_ONCE(1, "Current pid: %d comm: %s / Idle pid: %d comm: %s",
current->pid, current->comm,
idle->pid, idle->comm); /* must be idle task! */
}
}
/**
* rcu_idle_exit - inform RCU that current CPU is leaving idle
*
* Exit idle mode, in other words, -enter- the mode in which RCU
* read-side critical sections can occur.
*
* We crowbar the ->dynticks_nesting field to DYNTICK_TASK_NEST to
* allow for the possibility of usermode upcalls messing up our count
* of interrupt nesting level during the busy period that is just
* now starting.
*/
void rcu_idle_exit(void)
{
unsigned long flags;
struct rcu_dynticks *rdtp;
long long oldval;
local_irq_save(flags);
rdtp = &__get_cpu_var(rcu_dynticks);
oldval = rdtp->dynticks_nesting;
WARN_ON_ONCE(oldval < 0);
if (oldval & DYNTICK_TASK_NEST_MASK)
rdtp->dynticks_nesting += DYNTICK_TASK_NEST_VALUE;
else
rdtp->dynticks_nesting = DYNTICK_TASK_EXIT_IDLE;
rcu_idle_exit_common(rdtp, oldval);
local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(rcu_idle_exit);
/**
* rcu_irq_enter - inform RCU that current CPU is entering irq away from idle
*
* Enter an interrupt handler, which might possibly result in exiting
* idle mode, in other words, entering the mode in which read-side critical
* sections can occur.
*
* Note that the Linux kernel is fully capable of entering an interrupt
* handler that it never exits, for example when doing upcalls to
* user mode! This code assumes that the idle loop never does upcalls to
* user mode. If your architecture does do upcalls from the idle loop (or
* does anything else that results in unbalanced calls to the irq_enter()
* and irq_exit() functions), RCU will give you what you deserve, good
* and hard. But very infrequently and irreproducibly.
*
* Use things like work queues to work around this limitation.
*
* You have been warned.
*/
void rcu_irq_enter(void)
{
unsigned long flags;
struct rcu_dynticks *rdtp;
long long oldval;
local_irq_save(flags);
rdtp = &__get_cpu_var(rcu_dynticks);
oldval = rdtp->dynticks_nesting;
rdtp->dynticks_nesting++;
WARN_ON_ONCE(rdtp->dynticks_nesting == 0);
if (oldval)
trace_rcu_dyntick("++=", oldval, rdtp->dynticks_nesting);
else
rcu_idle_exit_common(rdtp, oldval);
local_irq_restore(flags);
}
/**
* rcu_nmi_enter - inform RCU of entry to NMI context
*
* If the CPU was idle with dynamic ticks active, and there is no
* irq handler running, this updates rdtp->dynticks_nmi to let the
* RCU grace-period handling know that the CPU is active.
*/
void rcu_nmi_enter(void)
{
struct rcu_dynticks *rdtp = &__get_cpu_var(rcu_dynticks);
if (rdtp->dynticks_nmi_nesting == 0 &&
(atomic_read(&rdtp->dynticks) & 0x1))
return;
rdtp->dynticks_nmi_nesting++;
smp_mb__before_atomic_inc(); /* Force delay from prior write. */
atomic_inc(&rdtp->dynticks);
/* CPUs seeing atomic_inc() must see later RCU read-side crit sects */
smp_mb__after_atomic_inc(); /* See above. */
WARN_ON_ONCE(!(atomic_read(&rdtp->dynticks) & 0x1));
}
/**
* rcu_nmi_exit - inform RCU of exit from NMI context
*
* If the CPU was idle with dynamic ticks active, and there is no
* irq handler running, this updates rdtp->dynticks_nmi to let the
* RCU grace-period handling know that the CPU is no longer active.
*/
void rcu_nmi_exit(void)
{
struct rcu_dynticks *rdtp = &__get_cpu_var(rcu_dynticks);
if (rdtp->dynticks_nmi_nesting == 0 ||
--rdtp->dynticks_nmi_nesting != 0)
return;
/* CPUs seeing atomic_inc() must see prior RCU read-side crit sects */
smp_mb__before_atomic_inc(); /* See above. */
atomic_inc(&rdtp->dynticks);
smp_mb__after_atomic_inc(); /* Force delay to next write. */
WARN_ON_ONCE(atomic_read(&rdtp->dynticks) & 0x1);
}
#ifdef CONFIG_PROVE_RCU
/**
* rcu_is_cpu_idle - see if RCU thinks that the current CPU is idle
*
* If the current CPU is in its idle loop and is neither in an interrupt
* or NMI handler, return true.
*/
int rcu_is_cpu_idle(void)
{
int ret;
preempt_disable();
ret = (atomic_read(&__get_cpu_var(rcu_dynticks).dynticks) & 0x1) == 0;
preempt_enable();
return ret;
}
EXPORT_SYMBOL(rcu_is_cpu_idle);
#ifdef CONFIG_HOTPLUG_CPU
/*
* Is the current CPU online? Disable preemption to avoid false positives
* that could otherwise happen due to the current CPU number being sampled,
* this task being preempted, its old CPU being taken offline, resuming
* on some other CPU, then determining that its old CPU is now offline.
* It is OK to use RCU on an offline processor during initial boot, hence
* the check for rcu_scheduler_fully_active. Note also that it is OK
* for a CPU coming online to use RCU for one jiffy prior to marking itself
* online in the cpu_online_mask. Similarly, it is OK for a CPU going
* offline to continue to use RCU for one jiffy after marking itself
* offline in the cpu_online_mask. This leniency is necessary given the
* non-atomic nature of the online and offline processing, for example,
* the fact that a CPU enters the scheduler after completing the CPU_DYING
* notifiers.
*
* This is also why RCU internally marks CPUs online during the
* CPU_UP_PREPARE phase and offline during the CPU_DEAD phase.
*
* Disable checking if in an NMI handler because we cannot safely report
* errors from NMI handlers anyway.
*/
bool rcu_lockdep_current_cpu_online(void)
{
struct rcu_data *rdp;
struct rcu_node *rnp;
bool ret;
if (in_nmi())
return 1;
preempt_disable();
rdp = &__get_cpu_var(rcu_sched_data);
rnp = rdp->mynode;
ret = (rdp->grpmask & rnp->qsmaskinit) ||
!rcu_scheduler_fully_active;
preempt_enable();
return ret;
}
EXPORT_SYMBOL_GPL(rcu_lockdep_current_cpu_online);
#endif /* #ifdef CONFIG_HOTPLUG_CPU */
#endif /* #ifdef CONFIG_PROVE_RCU */
/**
* rcu_is_cpu_rrupt_from_idle - see if idle or immediately interrupted from idle
*
* If the current CPU is idle or running at a first-level (not nested)
* interrupt from idle, return true. The caller must have at least
* disabled preemption.
*/
int rcu_is_cpu_rrupt_from_idle(void)
{
return __get_cpu_var(rcu_dynticks).dynticks_nesting <= 1;
}
/*
* Snapshot the specified CPU's dynticks counter so that we can later
* credit them with an implicit quiescent state. Return 1 if this CPU
* is in dynticks idle mode, which is an extended quiescent state.
*/
static int dyntick_save_progress_counter(struct rcu_data *rdp)
{
rdp->dynticks_snap = atomic_add_return(0, &rdp->dynticks->dynticks);
return (rdp->dynticks_snap & 0x1) == 0;
}
/*
* Return true if the specified CPU has passed through a quiescent
* state by virtue of being in or having passed through an dynticks
* idle state since the last call to dyntick_save_progress_counter()
* for this same CPU.
*/
static int rcu_implicit_dynticks_qs(struct rcu_data *rdp)
{
unsigned int curr;
unsigned int snap;
curr = (unsigned int)atomic_add_return(0, &rdp->dynticks->dynticks);
snap = (unsigned int)rdp->dynticks_snap;
/*
* If the CPU passed through or entered a dynticks idle phase with
* no active irq/NMI handlers, then we can safely pretend that the CPU
* already acknowledged the request to pass through a quiescent
* state. Either way, that CPU cannot possibly be in an RCU
* read-side critical section that started before the beginning
* of the current RCU grace period.
*/
if ((curr & 0x1) == 0 || UINT_CMP_GE(curr, snap + 2)) {
trace_rcu_fqs(rdp->rsp->name, rdp->gpnum, rdp->cpu, "dti");
rdp->dynticks_fqs++;
return 1;
}
/* Go check for the CPU being offline. */
return rcu_implicit_offline_qs(rdp);
}
static int jiffies_till_stall_check(void)
{
int till_stall_check = ACCESS_ONCE(rcu_cpu_stall_timeout);
/*
* Limit check must be consistent with the Kconfig limits
* for CONFIG_RCU_CPU_STALL_TIMEOUT.
*/
if (till_stall_check < 3) {
ACCESS_ONCE(rcu_cpu_stall_timeout) = 3;
till_stall_check = 3;
} else if (till_stall_check > 300) {
ACCESS_ONCE(rcu_cpu_stall_timeout) = 300;
till_stall_check = 300;
}
return till_stall_check * HZ + RCU_STALL_DELAY_DELTA;
}
static void record_gp_stall_check_time(struct rcu_state *rsp)
{
rsp->gp_start = jiffies;
rsp->jiffies_stall = jiffies + jiffies_till_stall_check();
}
static void print_other_cpu_stall(struct rcu_state *rsp)
{
int cpu;
long delta;
unsigned long flags;
int ndetected;
struct rcu_node *rnp = rcu_get_root(rsp);
/* Only let one CPU complain about others per time interval. */
raw_spin_lock_irqsave(&rnp->lock, flags);
delta = jiffies - rsp->jiffies_stall;
if (delta < RCU_STALL_RAT_DELAY || !rcu_gp_in_progress(rsp)) {
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
rsp->jiffies_stall = jiffies + 3 * jiffies_till_stall_check() + 3;
raw_spin_unlock_irqrestore(&rnp->lock, flags);
/*
* OK, time to rat on our buddy...
* See Documentation/RCU/stallwarn.txt for info on how to debug
* RCU CPU stall warnings.
*/
printk(KERN_ERR "INFO: %s detected stalls on CPUs/tasks:",
rsp->name);
print_cpu_stall_info_begin();
rcu_for_each_leaf_node(rsp, rnp) {
raw_spin_lock_irqsave(&rnp->lock, flags);
ndetected += rcu_print_task_stall(rnp);
raw_spin_unlock_irqrestore(&rnp->lock, flags);
if (rnp->qsmask == 0)
continue;
for (cpu = 0; cpu <= rnp->grphi - rnp->grplo; cpu++)
if (rnp->qsmask & (1UL << cpu)) {
print_cpu_stall_info(rsp, rnp->grplo + cpu);
ndetected++;
}
}
/*
* Now rat on any tasks that got kicked up to the root rcu_node
* due to CPU offlining.
*/
rnp = rcu_get_root(rsp);
raw_spin_lock_irqsave(&rnp->lock, flags);
ndetected = rcu_print_task_stall(rnp);
raw_spin_unlock_irqrestore(&rnp->lock, flags);
print_cpu_stall_info_end();
printk(KERN_CONT "(detected by %d, t=%ld jiffies)\n",
smp_processor_id(), (long)(jiffies - rsp->gp_start));
if (ndetected == 0)
printk(KERN_ERR "INFO: Stall ended before state dump start\n");
else if (!trigger_all_cpu_backtrace())
dump_stack();
/* If so configured, complain about tasks blocking the grace period. */
rcu_print_detail_task_stall(rsp);
force_quiescent_state(rsp, 0); /* Kick them all. */
}
static void print_cpu_stall(struct rcu_state *rsp)
{
unsigned long flags;
struct rcu_node *rnp = rcu_get_root(rsp);
/*
* OK, time to rat on ourselves...
* See Documentation/RCU/stallwarn.txt for info on how to debug
* RCU CPU stall warnings.
*/
printk(KERN_ERR "INFO: %s self-detected stall on CPU", rsp->name);
print_cpu_stall_info_begin();
print_cpu_stall_info(rsp, smp_processor_id());
print_cpu_stall_info_end();
printk(KERN_CONT " (t=%lu jiffies)\n", jiffies - rsp->gp_start);
if (!trigger_all_cpu_backtrace())
dump_stack();
raw_spin_lock_irqsave(&rnp->lock, flags);
if (ULONG_CMP_GE(jiffies, rsp->jiffies_stall))
rsp->jiffies_stall = jiffies +
3 * jiffies_till_stall_check() + 3;
raw_spin_unlock_irqrestore(&rnp->lock, flags);
set_need_resched(); /* kick ourselves to get things going. */
}
static void check_cpu_stall(struct rcu_state *rsp, struct rcu_data *rdp)
{
unsigned long j;
unsigned long js;
struct rcu_node *rnp;
if (rcu_cpu_stall_suppress)
return;
j = ACCESS_ONCE(jiffies);
js = ACCESS_ONCE(rsp->jiffies_stall);
rnp = rdp->mynode;
if ((ACCESS_ONCE(rnp->qsmask) & rdp->grpmask) && ULONG_CMP_GE(j, js)) {
/* We haven't checked in, so go dump stack. */
print_cpu_stall(rsp);
} else if (rcu_gp_in_progress(rsp) &&
ULONG_CMP_GE(j, js + RCU_STALL_RAT_DELAY)) {
/* They had a few time units to dump stack, so complain. */
print_other_cpu_stall(rsp);
}
}
static int rcu_panic(struct notifier_block *this, unsigned long ev, void *ptr)
{
rcu_cpu_stall_suppress = 1;
return NOTIFY_DONE;
}
/**
* rcu_cpu_stall_reset - prevent further stall warnings in current grace period
*
* Set the stall-warning timeout way off into the future, thus preventing
* any RCU CPU stall-warning messages from appearing in the current set of
* RCU grace periods.
*
* The caller must disable hard irqs.
*/
void rcu_cpu_stall_reset(void)
{
rcu_sched_state.jiffies_stall = jiffies + ULONG_MAX / 2;
rcu_bh_state.jiffies_stall = jiffies + ULONG_MAX / 2;
rcu_preempt_stall_reset();
}
static struct notifier_block rcu_panic_block = {
.notifier_call = rcu_panic,
};
static void __init check_cpu_stall_init(void)
{
atomic_notifier_chain_register(&panic_notifier_list, &rcu_panic_block);
}
/*
* Update CPU-local rcu_data state to record the newly noticed grace period.
* This is used both when we started the grace period and when we notice
* that someone else started the grace period. The caller must hold the
* ->lock of the leaf rcu_node structure corresponding to the current CPU,
* and must have irqs disabled.
*/
static void __note_new_gpnum(struct rcu_state *rsp, struct rcu_node *rnp, struct rcu_data *rdp)
{
if (rdp->gpnum != rnp->gpnum) {
/*
* If the current grace period is waiting for this CPU,
* set up to detect a quiescent state, otherwise don't
* go looking for one.
*/
rdp->gpnum = rnp->gpnum;
trace_rcu_grace_period(rsp->name, rdp->gpnum, "cpustart");
if (rnp->qsmask & rdp->grpmask) {
rdp->qs_pending = 1;
rdp->passed_quiesce = 0;
} else
rdp->qs_pending = 0;
zero_cpu_stall_ticks(rdp);
}
}
static void note_new_gpnum(struct rcu_state *rsp, struct rcu_data *rdp)
{
unsigned long flags;
struct rcu_node *rnp;
local_irq_save(flags);
rnp = rdp->mynode;
if (rdp->gpnum == ACCESS_ONCE(rnp->gpnum) || /* outside lock. */
!raw_spin_trylock(&rnp->lock)) { /* irqs already off, so later. */
local_irq_restore(flags);
return;
}
__note_new_gpnum(rsp, rnp, rdp);
raw_spin_unlock_irqrestore(&rnp->lock, flags);
}
/*
* Did someone else start a new RCU grace period start since we last
* checked? Update local state appropriately if so. Must be called
* on the CPU corresponding to rdp.
*/
static int
check_for_new_grace_period(struct rcu_state *rsp, struct rcu_data *rdp)
{
unsigned long flags;
int ret = 0;
local_irq_save(flags);
if (rdp->gpnum != rsp->gpnum) {
note_new_gpnum(rsp, rdp);
ret = 1;
}
local_irq_restore(flags);
return ret;
}
/*
* Advance this CPU's callbacks, but only if the current grace period
* has ended. This may be called only from the CPU to whom the rdp
* belongs. In addition, the corresponding leaf rcu_node structure's
* ->lock must be held by the caller, with irqs disabled.
*/
static void
__rcu_process_gp_end(struct rcu_state *rsp, struct rcu_node *rnp, struct rcu_data *rdp)
{
/* Did another grace period end? */
if (rdp->completed != rnp->completed) {
/* Advance callbacks. No harm if list empty. */
rdp->nxttail[RCU_DONE_TAIL] = rdp->nxttail[RCU_WAIT_TAIL];
rdp->nxttail[RCU_WAIT_TAIL] = rdp->nxttail[RCU_NEXT_READY_TAIL];
rdp->nxttail[RCU_NEXT_READY_TAIL] = rdp->nxttail[RCU_NEXT_TAIL];
/* Remember that we saw this grace-period completion. */
rdp->completed = rnp->completed;
trace_rcu_grace_period(rsp->name, rdp->gpnum, "cpuend");
/*
* If we were in an extended quiescent state, we may have
* missed some grace periods that others CPUs handled on
* our behalf. Catch up with this state to avoid noting
* spurious new grace periods. If another grace period
* has started, then rnp->gpnum will have advanced, so
* we will detect this later on.
*/
if (ULONG_CMP_LT(rdp->gpnum, rdp->completed))
rdp->gpnum = rdp->completed;
/*
* If RCU does not need a quiescent state from this CPU,
* then make sure that this CPU doesn't go looking for one.
*/
if ((rnp->qsmask & rdp->grpmask) == 0)
rdp->qs_pending = 0;
}
}
/*
* Advance this CPU's callbacks, but only if the current grace period
* has ended. This may be called only from the CPU to whom the rdp
* belongs.
*/
static void
rcu_process_gp_end(struct rcu_state *rsp, struct rcu_data *rdp)
{
unsigned long flags;
struct rcu_node *rnp;
local_irq_save(flags);
rnp = rdp->mynode;
if (rdp->completed == ACCESS_ONCE(rnp->completed) || /* outside lock. */
!raw_spin_trylock(&rnp->lock)) { /* irqs already off, so later. */
local_irq_restore(flags);
return;
}
__rcu_process_gp_end(rsp, rnp, rdp);
raw_spin_unlock_irqrestore(&rnp->lock, flags);
}
/*
* Do per-CPU grace-period initialization for running CPU. The caller
* must hold the lock of the leaf rcu_node structure corresponding to
* this CPU.
*/
static void
rcu_start_gp_per_cpu(struct rcu_state *rsp, struct rcu_node *rnp, struct rcu_data *rdp)
{
/* Prior grace period ended, so advance callbacks for current CPU. */
__rcu_process_gp_end(rsp, rnp, rdp);
/*
* Because this CPU just now started the new grace period, we know
* that all of its callbacks will be covered by this upcoming grace
* period, even the ones that were registered arbitrarily recently.
* Therefore, advance all outstanding callbacks to RCU_WAIT_TAIL.
*
* Other CPUs cannot be sure exactly when the grace period started.
* Therefore, their recently registered callbacks must pass through
* an additional RCU_NEXT_READY stage, so that they will be handled
* by the next RCU grace period.
*/
rdp->nxttail[RCU_NEXT_READY_TAIL] = rdp->nxttail[RCU_NEXT_TAIL];
rdp->nxttail[RCU_WAIT_TAIL] = rdp->nxttail[RCU_NEXT_TAIL];
/* Set state so that this CPU will detect the next quiescent state. */
__note_new_gpnum(rsp, rnp, rdp);
}
/*
* Start a new RCU grace period if warranted, re-initializing the hierarchy
* in preparation for detecting the next grace period. The caller must hold
* the root node's ->lock, which is released before return. Hard irqs must
* be disabled.
*
* Note that it is legal for a dying CPU (which is marked as offline) to
* invoke this function. This can happen when the dying CPU reports its
* quiescent state.
*/
static void
rcu_start_gp(struct rcu_state *rsp, unsigned long flags)
__releases(rcu_get_root(rsp)->lock)
{
struct rcu_data *rdp = this_cpu_ptr(rsp->rda);
struct rcu_node *rnp = rcu_get_root(rsp);
if (!rcu_scheduler_fully_active ||
!cpu_needs_another_gp(rsp, rdp)) {
/*
* Either the scheduler hasn't yet spawned the first
* non-idle task or this CPU does not need another
* grace period. Either way, don't start a new grace
* period.
*/
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
if (rsp->fqs_active) {
/*
* This CPU needs a grace period, but force_quiescent_state()
* is running. Tell it to start one on this CPU's behalf.
*/
rsp->fqs_need_gp = 1;
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
/* Advance to a new grace period and initialize state. */
rsp->gpnum++;
trace_rcu_grace_period(rsp->name, rsp->gpnum, "start");
WARN_ON_ONCE(rsp->fqs_state == RCU_GP_INIT);
rsp->fqs_state = RCU_GP_INIT; /* Hold off force_quiescent_state. */
rsp->jiffies_force_qs = jiffies + RCU_JIFFIES_TILL_FORCE_QS;
record_gp_stall_check_time(rsp);
raw_spin_unlock(&rnp->lock); /* leave irqs disabled. */
/* Exclude any concurrent CPU-hotplug operations. */
raw_spin_lock(&rsp->onofflock); /* irqs already disabled. */
/*
* Set the quiescent-state-needed bits in all the rcu_node
* structures for all currently online CPUs in breadth-first
* order, starting from the root rcu_node structure. This
* operation relies on the layout of the hierarchy within the
* rsp->node[] array. Note that other CPUs will access only
* the leaves of the hierarchy, which still indicate that no
* grace period is in progress, at least until the corresponding
* leaf node has been initialized. In addition, we have excluded
* CPU-hotplug operations.
*
* Note that the grace period cannot complete until we finish
* the initialization process, as there will be at least one
* qsmask bit set in the root node until that time, namely the
* one corresponding to this CPU, due to the fact that we have
* irqs disabled.
*/
rcu_for_each_node_breadth_first(rsp, rnp) {
raw_spin_lock(&rnp->lock); /* irqs already disabled. */
rcu_preempt_check_blocked_tasks(rnp);
rnp->qsmask = rnp->qsmaskinit;
rnp->gpnum = rsp->gpnum;
rnp->completed = rsp->completed;
if (rnp == rdp->mynode)
rcu_start_gp_per_cpu(rsp, rnp, rdp);
rcu_preempt_boost_start_gp(rnp);
trace_rcu_grace_period_init(rsp->name, rnp->gpnum,
rnp->level, rnp->grplo,
rnp->grphi, rnp->qsmask);
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
}
rnp = rcu_get_root(rsp);
raw_spin_lock(&rnp->lock); /* irqs already disabled. */
rsp->fqs_state = RCU_SIGNAL_INIT; /* force_quiescent_state now OK. */
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
raw_spin_unlock_irqrestore(&rsp->onofflock, flags);
}
/*
* Report a full set of quiescent states to the specified rcu_state
* data structure. This involves cleaning up after the prior grace
* period and letting rcu_start_gp() start up the next grace period
* if one is needed. Note that the caller must hold rnp->lock, as
* required by rcu_start_gp(), which will release it.
*/
static void rcu_report_qs_rsp(struct rcu_state *rsp, unsigned long flags)
__releases(rcu_get_root(rsp)->lock)
{
unsigned long gp_duration;
struct rcu_node *rnp = rcu_get_root(rsp);
struct rcu_data *rdp = this_cpu_ptr(rsp->rda);
WARN_ON_ONCE(!rcu_gp_in_progress(rsp));
/*
* Ensure that all grace-period and pre-grace-period activity
* is seen before the assignment to rsp->completed.
*/
smp_mb(); /* See above block comment. */
gp_duration = jiffies - rsp->gp_start;
if (gp_duration > rsp->gp_max)
rsp->gp_max = gp_duration;
/*
* We know the grace period is complete, but to everyone else
* it appears to still be ongoing. But it is also the case
* that to everyone else it looks like there is nothing that
* they can do to advance the grace period. It is therefore
* safe for us to drop the lock in order to mark the grace
* period as completed in all of the rcu_node structures.
*
* But if this CPU needs another grace period, it will take
* care of this while initializing the next grace period.
* We use RCU_WAIT_TAIL instead of the usual RCU_DONE_TAIL
* because the callbacks have not yet been advanced: Those
* callbacks are waiting on the grace period that just now
* completed.
*/
if (*rdp->nxttail[RCU_WAIT_TAIL] == NULL) {
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
/*
* Propagate new ->completed value to rcu_node structures
* so that other CPUs don't have to wait until the start
* of the next grace period to process their callbacks.
*/
rcu_for_each_node_breadth_first(rsp, rnp) {
raw_spin_lock(&rnp->lock); /* irqs already disabled. */
rnp->completed = rsp->gpnum;
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
}
rnp = rcu_get_root(rsp);
raw_spin_lock(&rnp->lock); /* irqs already disabled. */
}
rsp->completed = rsp->gpnum; /* Declare the grace period complete. */
trace_rcu_grace_period(rsp->name, rsp->completed, "end");
rsp->fqs_state = RCU_GP_IDLE;
rcu_start_gp(rsp, flags); /* releases root node's rnp->lock. */
}
/*
* Similar to rcu_report_qs_rdp(), for which it is a helper function.
* Allows quiescent states for a group of CPUs to be reported at one go
* to the specified rcu_node structure, though all the CPUs in the group
* must be represented by the same rcu_node structure (which need not be
* a leaf rcu_node structure, though it often will be). That structure's
* lock must be held upon entry, and it is released before return.
*/
static void
rcu_report_qs_rnp(unsigned long mask, struct rcu_state *rsp,
struct rcu_node *rnp, unsigned long flags)
__releases(rnp->lock)
{
struct rcu_node *rnp_c;
/* Walk up the rcu_node hierarchy. */
for (;;) {
if (!(rnp->qsmask & mask)) {
/* Our bit has already been cleared, so done. */
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
rnp->qsmask &= ~mask;
trace_rcu_quiescent_state_report(rsp->name, rnp->gpnum,
mask, rnp->qsmask, rnp->level,
rnp->grplo, rnp->grphi,
!!rnp->gp_tasks);
if (rnp->qsmask != 0 || rcu_preempt_blocked_readers_cgp(rnp)) {
/* Other bits still set at this level, so done. */
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
mask = rnp->grpmask;
if (rnp->parent == NULL) {
/* No more levels. Exit loop holding root lock. */
break;
}
raw_spin_unlock_irqrestore(&rnp->lock, flags);
rnp_c = rnp;
rnp = rnp->parent;
raw_spin_lock_irqsave(&rnp->lock, flags);
WARN_ON_ONCE(rnp_c->qsmask);
}
/*
* Get here if we are the last CPU to pass through a quiescent
* state for this grace period. Invoke rcu_report_qs_rsp()
* to clean up and start the next grace period if one is needed.
*/
rcu_report_qs_rsp(rsp, flags); /* releases rnp->lock. */
}
/*
* Record a quiescent state for the specified CPU to that CPU's rcu_data
* structure. This must be either called from the specified CPU, or
* called when the specified CPU is known to be offline (and when it is
* also known that no other CPU is concurrently trying to help the offline
* CPU). The lastcomp argument is used to make sure we are still in the
* grace period of interest. We don't want to end the current grace period
* based on quiescent states detected in an earlier grace period!
*/
static void
rcu_report_qs_rdp(int cpu, struct rcu_state *rsp, struct rcu_data *rdp, long lastgp)
{
unsigned long flags;
unsigned long mask;
struct rcu_node *rnp;
rnp = rdp->mynode;
raw_spin_lock_irqsave(&rnp->lock, flags);
if (lastgp != rnp->gpnum || rnp->completed == rnp->gpnum) {
/*
* The grace period in which this quiescent state was
* recorded has ended, so don't report it upwards.
* We will instead need a new quiescent state that lies
* within the current grace period.
*/
rdp->passed_quiesce = 0; /* need qs for new gp. */
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
mask = rdp->grpmask;
if ((rnp->qsmask & mask) == 0) {
raw_spin_unlock_irqrestore(&rnp->lock, flags);
} else {
rdp->qs_pending = 0;
/*
* This GP can't end until cpu checks in, so all of our
* callbacks can be processed during the next GP.
*/
rdp->nxttail[RCU_NEXT_READY_TAIL] = rdp->nxttail[RCU_NEXT_TAIL];
rcu_report_qs_rnp(mask, rsp, rnp, flags); /* rlses rnp->lock */
}
}
/*
* Check to see if there is a new grace period of which this CPU
* is not yet aware, and if so, set up local rcu_data state for it.
* Otherwise, see if this CPU has just passed through its first
* quiescent state for this grace period, and record that fact if so.
*/
static void
rcu_check_quiescent_state(struct rcu_state *rsp, struct rcu_data *rdp)
{
/* If there is now a new grace period, record and return. */
if (check_for_new_grace_period(rsp, rdp))
return;
/*
* Does this CPU still need to do its part for current grace period?
* If no, return and let the other CPUs do their part as well.
*/
if (!rdp->qs_pending)
return;
/*
* Was there a quiescent state since the beginning of the grace
* period? If no, then exit and wait for the next call.
*/
if (!rdp->passed_quiesce)
return;
/*
* Tell RCU we are done (but rcu_report_qs_rdp() will be the
* judge of that).
*/
rcu_report_qs_rdp(rdp->cpu, rsp, rdp, rdp->passed_quiesce_gpnum);
}
#ifdef CONFIG_HOTPLUG_CPU
/*
* Send the specified CPU's RCU callbacks to the orphanage. The
* specified CPU must be offline, and the caller must hold the
* ->onofflock.
*/
static void
rcu_send_cbs_to_orphanage(int cpu, struct rcu_state *rsp,
struct rcu_node *rnp, struct rcu_data *rdp)
{
int i;
/*
* Orphan the callbacks. First adjust the counts. This is safe
* because ->onofflock excludes _rcu_barrier()'s adoption of
* the callbacks, thus no memory barrier is required.
*/
if (rdp->nxtlist != NULL) {
rsp->qlen_lazy += rdp->qlen_lazy;
rsp->qlen += rdp->qlen;
rdp->n_cbs_orphaned += rdp->qlen;
rdp->qlen_lazy = 0;
rdp->qlen = 0;
}
/*
* Next, move those callbacks still needing a grace period to
* the orphanage, where some other CPU will pick them up.
* Some of the callbacks might have gone partway through a grace
* period, but that is too bad. They get to start over because we
* cannot assume that grace periods are synchronized across CPUs.
* We don't bother updating the ->nxttail[] array yet, instead
* we just reset the whole thing later on.
*/
if (*rdp->nxttail[RCU_DONE_TAIL] != NULL) {
*rsp->orphan_nxttail = *rdp->nxttail[RCU_DONE_TAIL];
rsp->orphan_nxttail = rdp->nxttail[RCU_NEXT_TAIL];
*rdp->nxttail[RCU_DONE_TAIL] = NULL;
}
/*
* Then move the ready-to-invoke callbacks to the orphanage,
* where some other CPU will pick them up. These will not be
* required to pass though another grace period: They are done.
*/
if (rdp->nxtlist != NULL) {
*rsp->orphan_donetail = rdp->nxtlist;
rsp->orphan_donetail = rdp->nxttail[RCU_DONE_TAIL];
}
/* Finally, initialize the rcu_data structure's list to empty. */
rdp->nxtlist = NULL;
for (i = 0; i < RCU_NEXT_SIZE; i++)
rdp->nxttail[i] = &rdp->nxtlist;
}
/*
* Adopt the RCU callbacks from the specified rcu_state structure's
* orphanage. The caller must hold the ->onofflock.
*/
static void rcu_adopt_orphan_cbs(struct rcu_state *rsp)
{
int i;
struct rcu_data *rdp = __this_cpu_ptr(rsp->rda);
/*
* If there is an rcu_barrier() operation in progress, then
* only the task doing that operation is permitted to adopt
* callbacks. To do otherwise breaks rcu_barrier() and friends
* by causing them to fail to wait for the callbacks in the
* orphanage.
*/
if (rsp->rcu_barrier_in_progress &&
rsp->rcu_barrier_in_progress != current)
return;
/* Do the accounting first. */
rdp->qlen_lazy += rsp->qlen_lazy;
rdp->qlen += rsp->qlen;
rdp->n_cbs_adopted += rsp->qlen;
rsp->qlen_lazy = 0;
rsp->qlen = 0;
/*
* We do not need a memory barrier here because the only way we
* can get here if there is an rcu_barrier() in flight is if
* we are the task doing the rcu_barrier().
*/
/* First adopt the ready-to-invoke callbacks. */
if (rsp->orphan_donelist != NULL) {
*rsp->orphan_donetail = *rdp->nxttail[RCU_DONE_TAIL];
*rdp->nxttail[RCU_DONE_TAIL] = rsp->orphan_donelist;
for (i = RCU_NEXT_SIZE - 1; i >= RCU_DONE_TAIL; i--)
if (rdp->nxttail[i] == rdp->nxttail[RCU_DONE_TAIL])
rdp->nxttail[i] = rsp->orphan_donetail;
rsp->orphan_donelist = NULL;
rsp->orphan_donetail = &rsp->orphan_donelist;
}
/* And then adopt the callbacks that still need a grace period. */
if (rsp->orphan_nxtlist != NULL) {
*rdp->nxttail[RCU_NEXT_TAIL] = rsp->orphan_nxtlist;
rdp->nxttail[RCU_NEXT_TAIL] = rsp->orphan_nxttail;
rsp->orphan_nxtlist = NULL;
rsp->orphan_nxttail = &rsp->orphan_nxtlist;
}
}
/*
* Trace the fact that this CPU is going offline.
*/
static void rcu_cleanup_dying_cpu(struct rcu_state *rsp)
{
RCU_TRACE(unsigned long mask);
RCU_TRACE(struct rcu_data *rdp = this_cpu_ptr(rsp->rda));
RCU_TRACE(struct rcu_node *rnp = rdp->mynode);
RCU_TRACE(mask = rdp->grpmask);
trace_rcu_grace_period(rsp->name,
rnp->gpnum + 1 - !!(rnp->qsmask & mask),
"cpuofl");
}
/*
* The CPU has been completely removed, and some other CPU is reporting
* this fact from process context. Do the remainder of the cleanup,
* including orphaning the outgoing CPU's RCU callbacks, and also
* adopting them, if there is no _rcu_barrier() instance running.
* There can only be one CPU hotplug operation at a time, so no other
* CPU can be attempting to update rcu_cpu_kthread_task.
*/
static void rcu_cleanup_dead_cpu(int cpu, struct rcu_state *rsp)
{
unsigned long flags;
unsigned long mask;
int need_report = 0;
struct rcu_data *rdp = per_cpu_ptr(rsp->rda, cpu);
struct rcu_node *rnp = rdp->mynode; /* Outgoing CPU's rdp & rnp. */
/* Adjust any no-longer-needed kthreads. */
rcu_boost_kthread_setaffinity(rnp, -1);
/* Remove the dead CPU from the bitmasks in the rcu_node hierarchy. */
/* Exclude any attempts to start a new grace period. */
raw_spin_lock_irqsave(&rsp->onofflock, flags);
/* Orphan the dead CPU's callbacks, and adopt them if appropriate. */
rcu_send_cbs_to_orphanage(cpu, rsp, rnp, rdp);
rcu_adopt_orphan_cbs(rsp);
/* Remove the outgoing CPU from the masks in the rcu_node hierarchy. */
mask = rdp->grpmask; /* rnp->grplo is constant. */
do {
raw_spin_lock(&rnp->lock); /* irqs already disabled. */
rnp->qsmaskinit &= ~mask;
if (rnp->qsmaskinit != 0) {
if (rnp != rdp->mynode)
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
break;
}
if (rnp == rdp->mynode)
need_report = rcu_preempt_offline_tasks(rsp, rnp, rdp);
else
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
mask = rnp->grpmask;
rnp = rnp->parent;
} while (rnp != NULL);
/*
* We still hold the leaf rcu_node structure lock here, and
* irqs are still disabled. The reason for this subterfuge is
* because invoking rcu_report_unblock_qs_rnp() with ->onofflock
* held leads to deadlock.
*/
raw_spin_unlock(&rsp->onofflock); /* irqs remain disabled. */
rnp = rdp->mynode;
if (need_report & RCU_OFL_TASKS_NORM_GP)
rcu_report_unblock_qs_rnp(rnp, flags);
else
raw_spin_unlock_irqrestore(&rnp->lock, flags);
if (need_report & RCU_OFL_TASKS_EXP_GP)
rcu_report_exp_rnp(rsp, rnp, true);
}
#else /* #ifdef CONFIG_HOTPLUG_CPU */
static void rcu_adopt_orphan_cbs(struct rcu_state *rsp)
{
}
static void rcu_cleanup_dying_cpu(struct rcu_state *rsp)
{
}
static void rcu_cleanup_dead_cpu(int cpu, struct rcu_state *rsp)
{
}
#endif /* #else #ifdef CONFIG_HOTPLUG_CPU */
/*
* Invoke any RCU callbacks that have made it to the end of their grace
* period. Thottle as specified by rdp->blimit.
*/
static void rcu_do_batch(struct rcu_state *rsp, struct rcu_data *rdp)
{
unsigned long flags;
struct rcu_head *next, *list, **tail;
long bl, count, count_lazy;
int i;
/* If no callbacks are ready, just return.*/
if (!cpu_has_callbacks_ready_to_invoke(rdp)) {
trace_rcu_batch_start(rsp->name, rdp->qlen_lazy, rdp->qlen, 0);
trace_rcu_batch_end(rsp->name, 0, !!ACCESS_ONCE(rdp->nxtlist),
need_resched(), is_idle_task(current),
rcu_is_callbacks_kthread());
return;
}
/*
* Extract the list of ready callbacks, disabling to prevent
* races with call_rcu() from interrupt handlers.
*/
local_irq_save(flags);
WARN_ON_ONCE(cpu_is_offline(smp_processor_id()));
bl = rdp->blimit;
trace_rcu_batch_start(rsp->name, rdp->qlen_lazy, rdp->qlen, bl);
list = rdp->nxtlist;
rdp->nxtlist = *rdp->nxttail[RCU_DONE_TAIL];
*rdp->nxttail[RCU_DONE_TAIL] = NULL;
tail = rdp->nxttail[RCU_DONE_TAIL];
for (i = RCU_NEXT_SIZE - 1; i >= 0; i--)
if (rdp->nxttail[i] == rdp->nxttail[RCU_DONE_TAIL])
rdp->nxttail[i] = &rdp->nxtlist;
local_irq_restore(flags);
/* Invoke callbacks. */
count = count_lazy = 0;
while (list) {
next = list->next;
prefetch(next);
debug_rcu_head_unqueue(list);
if (__rcu_reclaim(rsp->name, list))
count_lazy++;
list = next;
/* Stop only if limit reached and CPU has something to do. */
if (++count >= bl &&
(need_resched() ||
(!is_idle_task(current) && !rcu_is_callbacks_kthread())))
break;
}
local_irq_save(flags);
trace_rcu_batch_end(rsp->name, count, !!list, need_resched(),
is_idle_task(current),
rcu_is_callbacks_kthread());
/* Update count, and requeue any remaining callbacks. */
if (list != NULL) {
*tail = rdp->nxtlist;
rdp->nxtlist = list;
for (i = 0; i < RCU_NEXT_SIZE; i++)
if (&rdp->nxtlist == rdp->nxttail[i])
rdp->nxttail[i] = tail;
else
break;
}
smp_mb(); /* List handling before counting for rcu_barrier(). */
rdp->qlen_lazy -= count_lazy;
rdp->qlen -= count;
rdp->n_cbs_invoked += count;
/* Reinstate batch limit if we have worked down the excess. */
if (rdp->blimit == LONG_MAX && rdp->qlen <= qlowmark)
rdp->blimit = blimit;
/* Reset ->qlen_last_fqs_check trigger if enough CBs have drained. */
if (rdp->qlen == 0 && rdp->qlen_last_fqs_check != 0) {
rdp->qlen_last_fqs_check = 0;
rdp->n_force_qs_snap = rsp->n_force_qs;
} else if (rdp->qlen < rdp->qlen_last_fqs_check - qhimark)
rdp->qlen_last_fqs_check = rdp->qlen;
local_irq_restore(flags);
/* Re-invoke RCU core processing if there are callbacks remaining. */
if (cpu_has_callbacks_ready_to_invoke(rdp))
invoke_rcu_core();
}
/*
* Check to see if this CPU is in a non-context-switch quiescent state
* (user mode or idle loop for rcu, non-softirq execution for rcu_bh).
* Also schedule RCU core processing.
*
* This function must be called from hardirq context. It is normally
* invoked from the scheduling-clock interrupt. If rcu_pending returns
* false, there is no point in invoking rcu_check_callbacks().
*/
void rcu_check_callbacks(int cpu, int user)
{
trace_rcu_utilization("Start scheduler-tick");
increment_cpu_stall_ticks();
if (user || rcu_is_cpu_rrupt_from_idle()) {
/*
* Get here if this CPU took its interrupt from user
* mode or from the idle loop, and if this is not a
* nested interrupt. In this case, the CPU is in
* a quiescent state, so note it.
*
* No memory barrier is required here because both
* rcu_sched_qs() and rcu_bh_qs() reference only CPU-local
* variables that other CPUs neither access nor modify,
* at least not while the corresponding CPU is online.
*/
rcu_sched_qs(cpu);
rcu_bh_qs(cpu);
} else if (!in_softirq()) {
/*
* Get here if this CPU did not take its interrupt from
* softirq, in other words, if it is not interrupting
* a rcu_bh read-side critical section. This is an _bh
* critical section, so note it.
*/
rcu_bh_qs(cpu);
}
rcu_preempt_check_callbacks(cpu);
if (rcu_pending(cpu))
invoke_rcu_core();
trace_rcu_utilization("End scheduler-tick");
}
/*
* Scan the leaf rcu_node structures, processing dyntick state for any that
* have not yet encountered a quiescent state, using the function specified.
* Also initiate boosting for any threads blocked on the root rcu_node.
*
* The caller must have suppressed start of new grace periods.
*/
static void force_qs_rnp(struct rcu_state *rsp, int (*f)(struct rcu_data *))
{
unsigned long bit;
int cpu;
unsigned long flags;
unsigned long mask;
struct rcu_node *rnp;
rcu_for_each_leaf_node(rsp, rnp) {
mask = 0;
raw_spin_lock_irqsave(&rnp->lock, flags);
if (!rcu_gp_in_progress(rsp)) {
raw_spin_unlock_irqrestore(&rnp->lock, flags);
return;
}
if (rnp->qsmask == 0) {
rcu_initiate_boost(rnp, flags); /* releases rnp->lock */
continue;
}
cpu = rnp->grplo;
bit = 1;
for (; cpu <= rnp->grphi; cpu++, bit <<= 1) {
if ((rnp->qsmask & bit) != 0 &&
f(per_cpu_ptr(rsp->rda, cpu)))
mask |= bit;
}
if (mask != 0) {
/* rcu_report_qs_rnp() releases rnp->lock. */
rcu_report_qs_rnp(mask, rsp, rnp, flags);
continue;
}
raw_spin_unlock_irqrestore(&rnp->lock, flags);
}
rnp = rcu_get_root(rsp);
if (rnp->qsmask == 0) {
raw_spin_lock_irqsave(&rnp->lock, flags);
rcu_initiate_boost(rnp, flags); /* releases rnp->lock. */
}
}
/*
* Force quiescent states on reluctant CPUs, and also detect which
* CPUs are in dyntick-idle mode.
*/
static void force_quiescent_state(struct rcu_state *rsp, int relaxed)
{
unsigned long flags;
struct rcu_node *rnp = rcu_get_root(rsp);
trace_rcu_utilization("Start fqs");
if (!rcu_gp_in_progress(rsp)) {
trace_rcu_utilization("End fqs");
return; /* No grace period in progress, nothing to force. */
}
if (!raw_spin_trylock_irqsave(&rsp->fqslock, flags)) {
rsp->n_force_qs_lh++; /* Inexact, can lose counts. Tough! */
trace_rcu_utilization("End fqs");
return; /* Someone else is already on the job. */
}
if (relaxed && ULONG_CMP_GE(rsp->jiffies_force_qs, jiffies))
goto unlock_fqs_ret; /* no emergency and done recently. */
rsp->n_force_qs++;
raw_spin_lock(&rnp->lock); /* irqs already disabled */
rsp->jiffies_force_qs = jiffies + RCU_JIFFIES_TILL_FORCE_QS;
if(!rcu_gp_in_progress(rsp)) {
rsp->n_force_qs_ngp++;
raw_spin_unlock(&rnp->lock); /* irqs remain disabled */
goto unlock_fqs_ret; /* no GP in progress, time updated. */
}
rsp->fqs_active = 1;
switch (rsp->fqs_state) {
case RCU_GP_IDLE:
case RCU_GP_INIT:
break; /* grace period idle or initializing, ignore. */
case RCU_SAVE_DYNTICK:
if (RCU_SIGNAL_INIT != RCU_SAVE_DYNTICK)
break; /* So gcc recognizes the dead code. */
raw_spin_unlock(&rnp->lock); /* irqs remain disabled */
/* Record dyntick-idle state. */
force_qs_rnp(rsp, dyntick_save_progress_counter);
raw_spin_lock(&rnp->lock); /* irqs already disabled */
if (rcu_gp_in_progress(rsp))
rsp->fqs_state = RCU_FORCE_QS;
break;
case RCU_FORCE_QS:
/* Check dyntick-idle state, send IPI to laggarts. */
raw_spin_unlock(&rnp->lock); /* irqs remain disabled */
force_qs_rnp(rsp, rcu_implicit_dynticks_qs);
/* Leave state in case more forcing is required. */
raw_spin_lock(&rnp->lock); /* irqs already disabled */
break;
}
rsp->fqs_active = 0;
if (rsp->fqs_need_gp) {
raw_spin_unlock(&rsp->fqslock); /* irqs remain disabled */
rsp->fqs_need_gp = 0;
rcu_start_gp(rsp, flags); /* releases rnp->lock */
trace_rcu_utilization("End fqs");
return;
}
raw_spin_unlock(&rnp->lock); /* irqs remain disabled */
unlock_fqs_ret:
raw_spin_unlock_irqrestore(&rsp->fqslock, flags);
trace_rcu_utilization("End fqs");
}
/*
* This does the RCU core processing work for the specified rcu_state
* and rcu_data structures. This may be called only from the CPU to
* whom the rdp belongs.
*/
static void
__rcu_process_callbacks(struct rcu_state *rsp, struct rcu_data *rdp)
{
unsigned long flags;
WARN_ON_ONCE(rdp->beenonline == 0);
/*
* If an RCU GP has gone long enough, go check for dyntick
* idle CPUs and, if needed, send resched IPIs.
*/
if (ULONG_CMP_LT(ACCESS_ONCE(rsp->jiffies_force_qs), jiffies))
force_quiescent_state(rsp, 1);
/*
* Advance callbacks in response to end of earlier grace
* period that some other CPU ended.
*/
rcu_process_gp_end(rsp, rdp);
/* Update RCU state based on any recent quiescent states. */
rcu_check_quiescent_state(rsp, rdp);
/* Does this CPU require a not-yet-started grace period? */
if (cpu_needs_another_gp(rsp, rdp)) {
raw_spin_lock_irqsave(&rcu_get_root(rsp)->lock, flags);
rcu_start_gp(rsp, flags); /* releases above lock */
}
/* If there are callbacks ready, invoke them. */
if (cpu_has_callbacks_ready_to_invoke(rdp))
invoke_rcu_callbacks(rsp, rdp);
}
/*
* Do RCU core processing for the current CPU.
*/
static void rcu_process_callbacks(struct softirq_action *unused)
{
trace_rcu_utilization("Start RCU core");
__rcu_process_callbacks(&rcu_sched_state,
&__get_cpu_var(rcu_sched_data));
__rcu_process_callbacks(&rcu_bh_state, &__get_cpu_var(rcu_bh_data));
rcu_preempt_process_callbacks();
trace_rcu_utilization("End RCU core");
}
/*
* Schedule RCU callback invocation. If the specified type of RCU
* does not support RCU priority boosting, just do a direct call,
* otherwise wake up the per-CPU kernel kthread. Note that because we
* are running on the current CPU with interrupts disabled, the
* rcu_cpu_kthread_task cannot disappear out from under us.
*/
static void invoke_rcu_callbacks(struct rcu_state *rsp, struct rcu_data *rdp)
{
if (unlikely(!ACCESS_ONCE(rcu_scheduler_fully_active)))
return;
if (likely(!rsp->boost)) {
rcu_do_batch(rsp, rdp);
return;
}
invoke_rcu_callbacks_kthread();
}
static void invoke_rcu_core(void)
{
raise_softirq(RCU_SOFTIRQ);
}
static void
__call_rcu(struct rcu_head *head, void (*func)(struct rcu_head *rcu),
struct rcu_state *rsp, bool lazy)
{
unsigned long flags;
struct rcu_data *rdp;
WARN_ON_ONCE((unsigned long)head & 0x3); /* Misaligned rcu_head! */
debug_rcu_head_queue(head);
head->func = func;
head->next = NULL;
smp_mb(); /* Ensure RCU update seen before callback registry. */
/*
* Opportunistically note grace-period endings and beginnings.
* Note that we might see a beginning right after we see an
* end, but never vice versa, since this CPU has to pass through
* a quiescent state betweentimes.
*/
local_irq_save(flags);
rdp = this_cpu_ptr(rsp->rda);
/* Add the callback to our list. */
rdp->qlen++;
if (lazy)
rdp->qlen_lazy++;
else
rcu_idle_count_callbacks_posted();
smp_mb(); /* Count before adding callback for rcu_barrier(). */
*rdp->nxttail[RCU_NEXT_TAIL] = head;
rdp->nxttail[RCU_NEXT_TAIL] = &head->next;
if (__is_kfree_rcu_offset((unsigned long)func))
trace_rcu_kfree_callback(rsp->name, head, (unsigned long)func,
rdp->qlen_lazy, rdp->qlen);
else
trace_rcu_callback(rsp->name, head, rdp->qlen_lazy, rdp->qlen);
/* If interrupts were disabled, don't dive into RCU core. */
if (irqs_disabled_flags(flags)) {
local_irq_restore(flags);
return;
}
/*
* Force the grace period if too many callbacks or too long waiting.
* Enforce hysteresis, and don't invoke force_quiescent_state()
* if some other CPU has recently done so. Also, don't bother
* invoking force_quiescent_state() if the newly enqueued callback
* is the only one waiting for a grace period to complete.
*/
if (unlikely(rdp->qlen > rdp->qlen_last_fqs_check + qhimark)) {
/* Are we ignoring a completed grace period? */
rcu_process_gp_end(rsp, rdp);
check_for_new_grace_period(rsp, rdp);
/* Start a new grace period if one not already started. */
if (!rcu_gp_in_progress(rsp)) {
unsigned long nestflag;
struct rcu_node *rnp_root = rcu_get_root(rsp);
raw_spin_lock_irqsave(&rnp_root->lock, nestflag);
rcu_start_gp(rsp, nestflag); /* rlses rnp_root->lock */
} else {
/* Give the grace period a kick. */
rdp->blimit = LONG_MAX;
if (rsp->n_force_qs == rdp->n_force_qs_snap &&
*rdp->nxttail[RCU_DONE_TAIL] != head)
force_quiescent_state(rsp, 0);
rdp->n_force_qs_snap = rsp->n_force_qs;
rdp->qlen_last_fqs_check = rdp->qlen;
}
} else if (ULONG_CMP_LT(ACCESS_ONCE(rsp->jiffies_force_qs), jiffies))
force_quiescent_state(rsp, 1);
local_irq_restore(flags);
}
/*
* Queue an RCU-sched callback for invocation after a grace period.
*/
void call_rcu_sched(struct rcu_head *head, void (*func)(struct rcu_head *rcu))
{
__call_rcu(head, func, &rcu_sched_state, 0);
}
EXPORT_SYMBOL_GPL(call_rcu_sched);
/*
* Queue an RCU callback for invocation after a quicker grace period.
*/
void call_rcu_bh(struct rcu_head *head, void (*func)(struct rcu_head *rcu))
{
__call_rcu(head, func, &rcu_bh_state, 0);
}
EXPORT_SYMBOL_GPL(call_rcu_bh);
/**
* synchronize_sched - wait until an rcu-sched grace period has elapsed.
*
* Control will return to the caller some time after a full rcu-sched
* grace period has elapsed, in other words after all currently executing
* rcu-sched read-side critical sections have completed. These read-side
* critical sections are delimited by rcu_read_lock_sched() and
* rcu_read_unlock_sched(), and may be nested. Note that preempt_disable(),
* local_irq_disable(), and so on may be used in place of
* rcu_read_lock_sched().
*
* This means that all preempt_disable code sequences, including NMI and
* hardware-interrupt handlers, in progress on entry will have completed
* before this primitive returns. However, this does not guarantee that
* softirq handlers will have completed, since in some kernels, these
* handlers can run in process context, and can block.
*
* This primitive provides the guarantees made by the (now removed)
* synchronize_kernel() API. In contrast, synchronize_rcu() only
* guarantees that rcu_read_lock() sections will have completed.
* In "classic RCU", these two guarantees happen to be one and
* the same, but can differ in realtime RCU implementations.
*/
void synchronize_sched(void)
{
rcu_lockdep_assert(!lock_is_held(&rcu_bh_lock_map) &&
!lock_is_held(&rcu_lock_map) &&
!lock_is_held(&rcu_sched_lock_map),
"Illegal synchronize_sched() in RCU-sched read-side critical section");
if (rcu_blocking_is_gp())
return;
if (rcu_expedited)
synchronize_sched_expedited();
else
wait_rcu_gp(call_rcu_sched);
}
EXPORT_SYMBOL_GPL(synchronize_sched);
/**
* synchronize_rcu_bh - wait until an rcu_bh grace period has elapsed.
*
* Control will return to the caller some time after a full rcu_bh grace
* period has elapsed, in other words after all currently executing rcu_bh
* read-side critical sections have completed. RCU read-side critical
* sections are delimited by rcu_read_lock_bh() and rcu_read_unlock_bh(),
* and may be nested.
*/
void synchronize_rcu_bh(void)
{
rcu_lockdep_assert(!lock_is_held(&rcu_bh_lock_map) &&
!lock_is_held(&rcu_lock_map) &&
!lock_is_held(&rcu_sched_lock_map),
"Illegal synchronize_rcu_bh() in RCU-bh read-side critical section");
if (rcu_blocking_is_gp())
return;
if (rcu_expedited)
synchronize_rcu_bh_expedited();
else
wait_rcu_gp(call_rcu_bh);
}
EXPORT_SYMBOL_GPL(synchronize_rcu_bh);
static atomic_t sync_sched_expedited_started = ATOMIC_INIT(0);
static atomic_t sync_sched_expedited_done = ATOMIC_INIT(0);
static int synchronize_sched_expedited_cpu_stop(void *data)
{
/*
* There must be a full memory barrier on each affected CPU
* between the time that try_stop_cpus() is called and the
* time that it returns.
*
* In the current initial implementation of cpu_stop, the
* above condition is already met when the control reaches
* this point and the following smp_mb() is not strictly
* necessary. Do smp_mb() anyway for documentation and
* robustness against future implementation changes.
*/
smp_mb(); /* See above comment block. */
return 0;
}
/**
* synchronize_sched_expedited - Brute-force RCU-sched grace period
*
* Wait for an RCU-sched grace period to elapse, but use a "big hammer"
* approach to force the grace period to end quickly. This consumes
* significant time on all CPUs and is unfriendly to real-time workloads,
* so is thus not recommended for any sort of common-case code. In fact,
* if you are using synchronize_sched_expedited() in a loop, please
* restructure your code to batch your updates, and then use a single
* synchronize_sched() instead.
*
* Note that it is illegal to call this function while holding any lock
* that is acquired by a CPU-hotplug notifier. And yes, it is also illegal
* to call this function from a CPU-hotplug notifier. Failing to observe
* these restriction will result in deadlock.
*
* This implementation can be thought of as an application of ticket
* locking to RCU, with sync_sched_expedited_started and
* sync_sched_expedited_done taking on the roles of the halves
* of the ticket-lock word. Each task atomically increments
* sync_sched_expedited_started upon entry, snapshotting the old value,
* then attempts to stop all the CPUs. If this succeeds, then each
* CPU will have executed a context switch, resulting in an RCU-sched
* grace period. We are then done, so we use atomic_cmpxchg() to
* update sync_sched_expedited_done to match our snapshot -- but
* only if someone else has not already advanced past our snapshot.
*
* On the other hand, if try_stop_cpus() fails, we check the value
* of sync_sched_expedited_done. If it has advanced past our
* initial snapshot, then someone else must have forced a grace period
* some time after we took our snapshot. In this case, our work is
* done for us, and we can simply return. Otherwise, we try again,
* but keep our initial snapshot for purposes of checking for someone
* doing our work for us.
*
* If we fail too many times in a row, we fall back to synchronize_sched().
*/
void synchronize_sched_expedited(void)
{
int firstsnap, s, snap, trycount = 0;
/* Note that atomic_inc_return() implies full memory barrier. */
firstsnap = snap = atomic_inc_return(&sync_sched_expedited_started);
get_online_cpus();
WARN_ON_ONCE(cpu_is_offline(raw_smp_processor_id()));
/*
* Each pass through the following loop attempts to force a
* context switch on each CPU.
*/
while (try_stop_cpus(cpu_online_mask,
synchronize_sched_expedited_cpu_stop,
NULL) == -EAGAIN) {
put_online_cpus();
/* No joy, try again later. Or just synchronize_sched(). */
if (trycount++ < 10)
udelay(trycount * num_online_cpus());
else {
synchronize_sched();
return;
}
/* Check to see if someone else did our work for us. */
s = atomic_read(&sync_sched_expedited_done);
if (UINT_CMP_GE((unsigned)s, (unsigned)firstsnap)) {
smp_mb(); /* ensure test happens before caller kfree */
return;
}
/*
* Refetching sync_sched_expedited_started allows later
* callers to piggyback on our grace period. We subtract
* 1 to get the same token that the last incrementer got.
* We retry after they started, so our grace period works
* for them, and they started after our first try, so their
* grace period works for us.
*/
get_online_cpus();
snap = atomic_read(&sync_sched_expedited_started);
smp_mb(); /* ensure read is before try_stop_cpus(). */
}
/*
* Everyone up to our most recent fetch is covered by our grace
* period. Update the counter, but only if our work is still
* relevant -- which it won't be if someone who started later
* than we did beat us to the punch.
*/
do {
s = atomic_read(&sync_sched_expedited_done);
if (UINT_CMP_GE((unsigned)s, (unsigned)snap)) {
smp_mb(); /* ensure test happens before caller kfree */
break;
}
} while (atomic_cmpxchg(&sync_sched_expedited_done, s, snap) != s);
put_online_cpus();
}
EXPORT_SYMBOL_GPL(synchronize_sched_expedited);
/*
* Check to see if there is any immediate RCU-related work to be done
* by the current CPU, for the specified type of RCU, returning 1 if so.
* The checks are in order of increasing expense: checks that can be
* carried out against CPU-local state are performed first. However,
* we must check for CPU stalls first, else we might not get a chance.
*/
static int __rcu_pending(struct rcu_state *rsp, struct rcu_data *rdp)
{
struct rcu_node *rnp = rdp->mynode;
rdp->n_rcu_pending++;
/* Check for CPU stalls, if enabled. */
check_cpu_stall(rsp, rdp);
/* Is the RCU core waiting for a quiescent state from this CPU? */
if (rcu_scheduler_fully_active &&
rdp->qs_pending && !rdp->passed_quiesce) {
/*
* If force_quiescent_state() coming soon and this CPU
* needs a quiescent state, and this is either RCU-sched
* or RCU-bh, force a local reschedule.
*/
rdp->n_rp_qs_pending++;
if (!rdp->preemptible &&
ULONG_CMP_LT(ACCESS_ONCE(rsp->jiffies_force_qs) - 1,
jiffies))
set_need_resched();
} else if (rdp->qs_pending && rdp->passed_quiesce) {
rdp->n_rp_report_qs++;
return 1;
}
/* Does this CPU have callbacks ready to invoke? */
if (cpu_has_callbacks_ready_to_invoke(rdp)) {
rdp->n_rp_cb_ready++;
return 1;
}
/* Has RCU gone idle with this CPU needing another grace period? */
if (cpu_needs_another_gp(rsp, rdp)) {
rdp->n_rp_cpu_needs_gp++;
return 1;
}
/* Has another RCU grace period completed? */
if (ACCESS_ONCE(rnp->completed) != rdp->completed) { /* outside lock */
rdp->n_rp_gp_completed++;
return 1;
}
/* Has a new RCU grace period started? */
if (ACCESS_ONCE(rnp->gpnum) != rdp->gpnum) { /* outside lock */
rdp->n_rp_gp_started++;
return 1;
}
/* Has an RCU GP gone long enough to send resched IPIs &c? */
if (rcu_gp_in_progress(rsp) &&
ULONG_CMP_LT(ACCESS_ONCE(rsp->jiffies_force_qs), jiffies)) {
rdp->n_rp_need_fqs++;
return 1;
}
/* nothing to do */
rdp->n_rp_need_nothing++;
return 0;
}
/*
* Check to see if there is any immediate RCU-related work to be done
* by the current CPU, returning 1 if so. This function is part of the
* RCU implementation; it is -not- an exported member of the RCU API.
*/
static int rcu_pending(int cpu)
{
return __rcu_pending(&rcu_sched_state, &per_cpu(rcu_sched_data, cpu)) ||
__rcu_pending(&rcu_bh_state, &per_cpu(rcu_bh_data, cpu)) ||
rcu_preempt_pending(cpu);
}
/*
* Check to see if any future RCU-related work will need to be done
* by the current CPU, even if none need be done immediately, returning
* 1 if so.
*/
static int rcu_cpu_has_callbacks(int cpu)
{
/* RCU callbacks either ready or pending? */
return per_cpu(rcu_sched_data, cpu).nxtlist ||
per_cpu(rcu_bh_data, cpu).nxtlist ||
rcu_preempt_cpu_has_callbacks(cpu);
}
/*
* RCU callback function for _rcu_barrier(). If we are last, wake
* up the task executing _rcu_barrier().
*/
static void rcu_barrier_callback(struct rcu_head *notused)
{
if (atomic_dec_and_test(&rcu_barrier_cpu_count))
complete(&rcu_barrier_completion);
}
/*
* Called with preemption disabled, and from cross-cpu IRQ context.
*/
static void rcu_barrier_func(void *type)
{
int cpu = smp_processor_id();
struct rcu_head *head = &per_cpu(rcu_barrier_head, cpu);
void (*call_rcu_func)(struct rcu_head *head,
void (*func)(struct rcu_head *head));
atomic_inc(&rcu_barrier_cpu_count);
call_rcu_func = type;
call_rcu_func(head, rcu_barrier_callback);
}
/*
* Orchestrate the specified type of RCU barrier, waiting for all
* RCU callbacks of the specified type to complete.
*/
static void _rcu_barrier(struct rcu_state *rsp,
void (*call_rcu_func)(struct rcu_head *head,
void (*func)(struct rcu_head *head)))
{
int cpu;
unsigned long flags;
struct rcu_data *rdp;
struct rcu_head rh;
init_rcu_head_on_stack(&rh);
/* Take mutex to serialize concurrent rcu_barrier() requests. */
mutex_lock(&rcu_barrier_mutex);
smp_mb(); /* Prevent any prior operations from leaking in. */
/*
* Initialize the count to one rather than to zero in order to
* avoid a too-soon return to zero in case of a short grace period
* (or preemption of this task). Also flag this task as doing
* an rcu_barrier(). This will prevent anyone else from adopting
* orphaned callbacks, which could cause otherwise failure if a
* CPU went offline and quickly came back online. To see this,
* consider the following sequence of events:
*
* 1. We cause CPU 0 to post an rcu_barrier_callback() callback.
* 2. CPU 1 goes offline, orphaning its callbacks.
* 3. CPU 0 adopts CPU 1's orphaned callbacks.
* 4. CPU 1 comes back online.
* 5. We cause CPU 1 to post an rcu_barrier_callback() callback.
* 6. Both rcu_barrier_callback() callbacks are invoked, awakening
* us -- but before CPU 1's orphaned callbacks are invoked!!!
*/
init_completion(&rcu_barrier_completion);
atomic_set(&rcu_barrier_cpu_count, 1);
raw_spin_lock_irqsave(&rsp->onofflock, flags);
rsp->rcu_barrier_in_progress = current;
raw_spin_unlock_irqrestore(&rsp->onofflock, flags);
/*
* Force every CPU with callbacks to register a new callback
* that will tell us when all the preceding callbacks have
* been invoked. If an offline CPU has callbacks, wait for
* it to either come back online or to finish orphaning those
* callbacks.
*/
for_each_possible_cpu(cpu) {
preempt_disable();
rdp = per_cpu_ptr(rsp->rda, cpu);
if (cpu_is_offline(cpu)) {
preempt_enable();
while (cpu_is_offline(cpu) && ACCESS_ONCE(rdp->qlen))
schedule_timeout_interruptible(1);
} else if (ACCESS_ONCE(rdp->qlen)) {
smp_call_function_single(cpu, rcu_barrier_func,
(void *)call_rcu_func, 1);
preempt_enable();
} else {
preempt_enable();
}
}
/*
* Now that all online CPUs have rcu_barrier_callback() callbacks
* posted, we can adopt all of the orphaned callbacks and place
* an rcu_barrier_callback() callback after them. When that is done,
* we are guaranteed to have an rcu_barrier_callback() callback
* following every callback that could possibly have been
* registered before _rcu_barrier() was called.
*/
raw_spin_lock_irqsave(&rsp->onofflock, flags);
rcu_adopt_orphan_cbs(rsp);
rsp->rcu_barrier_in_progress = NULL;
raw_spin_unlock_irqrestore(&rsp->onofflock, flags);
atomic_inc(&rcu_barrier_cpu_count);
smp_mb__after_atomic_inc(); /* Ensure atomic_inc() before callback. */
call_rcu_func(&rh, rcu_barrier_callback);
/*
* Now that we have an rcu_barrier_callback() callback on each
* CPU, and thus each counted, remove the initial count.
*/
if (atomic_dec_and_test(&rcu_barrier_cpu_count))
complete(&rcu_barrier_completion);
/* Wait for all rcu_barrier_callback() callbacks to be invoked. */
wait_for_completion(&rcu_barrier_completion);
/* Other rcu_barrier() invocations can now safely proceed. */
mutex_unlock(&rcu_barrier_mutex);
destroy_rcu_head_on_stack(&rh);
}
/**
* rcu_barrier_bh - Wait until all in-flight call_rcu_bh() callbacks complete.
*/
void rcu_barrier_bh(void)
{
_rcu_barrier(&rcu_bh_state, call_rcu_bh);
}
EXPORT_SYMBOL_GPL(rcu_barrier_bh);
/**
* rcu_barrier_sched - Wait for in-flight call_rcu_sched() callbacks.
*/
void rcu_barrier_sched(void)
{
_rcu_barrier(&rcu_sched_state, call_rcu_sched);
}
EXPORT_SYMBOL_GPL(rcu_barrier_sched);
/*
* Do boot-time initialization of a CPU's per-CPU RCU data.
*/
static void __init
rcu_boot_init_percpu_data(int cpu, struct rcu_state *rsp)
{
unsigned long flags;
int i;
struct rcu_data *rdp = per_cpu_ptr(rsp->rda, cpu);
struct rcu_node *rnp = rcu_get_root(rsp);
/* Set up local state, ensuring consistent view of global state. */
raw_spin_lock_irqsave(&rnp->lock, flags);
rdp->grpmask = 1UL << (cpu - rdp->mynode->grplo);
rdp->nxtlist = NULL;
for (i = 0; i < RCU_NEXT_SIZE; i++)
rdp->nxttail[i] = &rdp->nxtlist;
rdp->qlen_lazy = 0;
rdp->qlen = 0;
rdp->dynticks = &per_cpu(rcu_dynticks, cpu);
WARN_ON_ONCE(rdp->dynticks->dynticks_nesting != DYNTICK_TASK_EXIT_IDLE);
WARN_ON_ONCE(atomic_read(&rdp->dynticks->dynticks) != 1);
rdp->cpu = cpu;
rdp->rsp = rsp;
raw_spin_unlock_irqrestore(&rnp->lock, flags);
}
/*
* Initialize a CPU's per-CPU RCU data. Note that only one online or
* offline event can be happening at a given time. Note also that we
* can accept some slop in the rsp->completed access due to the fact
* that this CPU cannot possibly have any RCU callbacks in flight yet.
*/
static void __cpuinit
rcu_init_percpu_data(int cpu, struct rcu_state *rsp, int preemptible)
{
unsigned long flags;
unsigned long mask;
struct rcu_data *rdp = per_cpu_ptr(rsp->rda, cpu);
struct rcu_node *rnp = rcu_get_root(rsp);
/* Set up local state, ensuring consistent view of global state. */
raw_spin_lock_irqsave(&rnp->lock, flags);
rdp->beenonline = 1; /* We have now been online. */
rdp->preemptible = preemptible;
rdp->qlen_last_fqs_check = 0;
rdp->n_force_qs_snap = rsp->n_force_qs;
rdp->blimit = blimit;
rdp->dynticks->dynticks_nesting = DYNTICK_TASK_EXIT_IDLE;
atomic_set(&rdp->dynticks->dynticks,
(atomic_read(&rdp->dynticks->dynticks) & ~0x1) + 1);
rcu_prepare_for_idle_init(cpu);
raw_spin_unlock(&rnp->lock); /* irqs remain disabled. */
/*
* A new grace period might start here. If so, we won't be part
* of it, but that is OK, as we are currently in a quiescent state.
*/
/* Exclude any attempts to start a new GP on large systems. */
raw_spin_lock(&rsp->onofflock); /* irqs already disabled. */
/* Add CPU to rcu_node bitmasks. */
rnp = rdp->mynode;
mask = rdp->grpmask;
do {
/* Exclude any attempts to start a new GP on small systems. */
raw_spin_lock(&rnp->lock); /* irqs already disabled. */
rnp->qsmaskinit |= mask;
mask = rnp->grpmask;
if (rnp == rdp->mynode) {
/*
* If there is a grace period in progress, we will
* set up to wait for it next time we run the
* RCU core code.
*/
rdp->gpnum = rnp->completed;
rdp->completed = rnp->completed;
rdp->passed_quiesce = 0;
rdp->qs_pending = 0;
rdp->passed_quiesce_gpnum = rnp->gpnum - 1;
trace_rcu_grace_period(rsp->name, rdp->gpnum, "cpuonl");
}
raw_spin_unlock(&rnp->lock); /* irqs already disabled. */
rnp = rnp->parent;
} while (rnp != NULL && !(rnp->qsmaskinit & mask));
raw_spin_unlock_irqrestore(&rsp->onofflock, flags);
}
static void __cpuinit rcu_prepare_cpu(int cpu)
{
rcu_init_percpu_data(cpu, &rcu_sched_state, 0);
rcu_init_percpu_data(cpu, &rcu_bh_state, 0);
rcu_preempt_init_percpu_data(cpu);
}
/*
* Handle CPU online/offline notification events.
*/
static int __cpuinit rcu_cpu_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
long cpu = (long)hcpu;
struct rcu_data *rdp = per_cpu_ptr(rcu_state->rda, cpu);
struct rcu_node *rnp = rdp->mynode;
trace_rcu_utilization("Start CPU hotplug");
switch (action) {
case CPU_UP_PREPARE:
case CPU_UP_PREPARE_FROZEN:
rcu_prepare_cpu(cpu);
rcu_prepare_kthreads(cpu);
break;
case CPU_ONLINE:
case CPU_DOWN_FAILED:
rcu_boost_kthread_setaffinity(rnp, -1);
break;
case CPU_DOWN_PREPARE:
rcu_boost_kthread_setaffinity(rnp, cpu);
break;
case CPU_DYING:
case CPU_DYING_FROZEN:
/*
* The whole machine is "stopped" except this CPU, so we can
* touch any data without introducing corruption. We send the
* dying CPU's callbacks to an arbitrarily chosen online CPU.
*/
rcu_cleanup_dying_cpu(&rcu_bh_state);
rcu_cleanup_dying_cpu(&rcu_sched_state);
rcu_preempt_cleanup_dying_cpu();
rcu_cleanup_after_idle(cpu);
break;
case CPU_DEAD:
case CPU_DEAD_FROZEN:
case CPU_UP_CANCELED:
case CPU_UP_CANCELED_FROZEN:
rcu_cleanup_dead_cpu(cpu, &rcu_bh_state);
rcu_cleanup_dead_cpu(cpu, &rcu_sched_state);
rcu_preempt_cleanup_dead_cpu(cpu);
break;
default:
break;
}
trace_rcu_utilization("End CPU hotplug");
return NOTIFY_OK;
}
/*
* This function is invoked towards the end of the scheduler's initialization
* process. Before this is called, the idle task might contain
* RCU read-side critical sections (during which time, this idle
* task is booting the system). After this function is called, the
* idle tasks are prohibited from containing RCU read-side critical
* sections. This function also enables RCU lockdep checking.
*/
void rcu_scheduler_starting(void)
{
WARN_ON(num_online_cpus() != 1);
WARN_ON(nr_context_switches() > 0);
rcu_scheduler_active = 1;
}
/*
* Compute the per-level fanout, either using the exact fanout specified
* or balancing the tree, depending on CONFIG_RCU_FANOUT_EXACT.
*/
#ifdef CONFIG_RCU_FANOUT_EXACT
static void __init rcu_init_levelspread(struct rcu_state *rsp)
{
int i;
for (i = NUM_RCU_LVLS - 1; i > 0; i--)
rsp->levelspread[i] = CONFIG_RCU_FANOUT;
rsp->levelspread[0] = RCU_FANOUT_LEAF;
}
#else /* #ifdef CONFIG_RCU_FANOUT_EXACT */
static void __init rcu_init_levelspread(struct rcu_state *rsp)
{
int ccur;
int cprv;
int i;
cprv = NR_CPUS;
for (i = NUM_RCU_LVLS - 1; i >= 0; i--) {
ccur = rsp->levelcnt[i];
rsp->levelspread[i] = (cprv + ccur - 1) / ccur;
cprv = ccur;
}
}
#endif /* #else #ifdef CONFIG_RCU_FANOUT_EXACT */
/*
* Helper function for rcu_init() that initializes one rcu_state structure.
*/
static void __init rcu_init_one(struct rcu_state *rsp,
struct rcu_data __percpu *rda)
{
static char *buf[] = { "rcu_node_level_0",
"rcu_node_level_1",
"rcu_node_level_2",
"rcu_node_level_3" }; /* Match MAX_RCU_LVLS */
int cpustride = 1;
int i;
int j;
struct rcu_node *rnp;
BUILD_BUG_ON(MAX_RCU_LVLS > ARRAY_SIZE(buf)); /* Fix buf[] init! */
/* Initialize the level-tracking arrays. */
for (i = 1; i < NUM_RCU_LVLS; i++)
rsp->level[i] = rsp->level[i - 1] + rsp->levelcnt[i - 1];
rcu_init_levelspread(rsp);
/* Initialize the elements themselves, starting from the leaves. */
for (i = NUM_RCU_LVLS - 1; i >= 0; i--) {
cpustride *= rsp->levelspread[i];
rnp = rsp->level[i];
for (j = 0; j < rsp->levelcnt[i]; j++, rnp++) {
raw_spin_lock_init(&rnp->lock);
lockdep_set_class_and_name(&rnp->lock,
&rcu_node_class[i], buf[i]);
rnp->gpnum = 0;
rnp->qsmask = 0;
rnp->qsmaskinit = 0;
rnp->grplo = j * cpustride;
rnp->grphi = (j + 1) * cpustride - 1;
if (rnp->grphi >= NR_CPUS)
rnp->grphi = NR_CPUS - 1;
if (i == 0) {
rnp->grpnum = 0;
rnp->grpmask = 0;
rnp->parent = NULL;
} else {
rnp->grpnum = j % rsp->levelspread[i - 1];
rnp->grpmask = 1UL << rnp->grpnum;
rnp->parent = rsp->level[i - 1] +
j / rsp->levelspread[i - 1];
}
rnp->level = i;
INIT_LIST_HEAD(&rnp->blkd_tasks);
}
}
rsp->rda = rda;
rnp = rsp->level[NUM_RCU_LVLS - 1];
for_each_possible_cpu(i) {
while (i > rnp->grphi)
rnp++;
per_cpu_ptr(rsp->rda, i)->mynode = rnp;
rcu_boot_init_percpu_data(i, rsp);
}
}
void __init rcu_init(void)
{
int cpu;
rcu_bootup_announce();
rcu_init_one(&rcu_sched_state, &rcu_sched_data);
rcu_init_one(&rcu_bh_state, &rcu_bh_data);
__rcu_init_preempt();
open_softirq(RCU_SOFTIRQ, rcu_process_callbacks);
/*
* We don't need protection against CPU-hotplug here because
* this is called early in boot, before either interrupts
* or the scheduler are operational.
*/
cpu_notifier(rcu_cpu_notify, 0);
for_each_online_cpu(cpu)
rcu_cpu_notify(NULL, CPU_UP_PREPARE, (void *)(long)cpu);
check_cpu_stall_init();
}
#include "rcutree_plugin.h"
| gpl-2.0 |
geoffret/litmus-rt | drivers/usb/host/ohci-platform.c | 357 | 10162 | /*
* Generic platform ohci driver
*
* Copyright 2007 Michael Buesch <m@bues.ch>
* Copyright 2011-2012 Hauke Mehrtens <hauke@hauke-m.de>
* Copyright 2014 Hans de Goede <hdegoede@redhat.com>
*
* Derived from the OCHI-SSB driver
* Derived from the OHCI-PCI driver
* Copyright 1999 Roman Weissgaerber
* Copyright 2000-2002 David Brownell
* Copyright 1999 Linus Torvalds
* Copyright 1999 Gregory P. Smith
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/usb/ohci_pdriver.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include "ohci.h"
#define DRIVER_DESC "OHCI generic platform driver"
#define OHCI_MAX_CLKS 3
#define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv)
struct ohci_platform_priv {
struct clk *clks[OHCI_MAX_CLKS];
struct reset_control *rst;
struct phy **phys;
int num_phys;
};
static const char hcd_name[] = "ohci-platform";
static int ohci_platform_power_on(struct platform_device *dev)
{
struct usb_hcd *hcd = platform_get_drvdata(dev);
struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
int clk, ret, phy_num;
for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) {
ret = clk_prepare_enable(priv->clks[clk]);
if (ret)
goto err_disable_clks;
}
for (phy_num = 0; phy_num < priv->num_phys; phy_num++) {
if (priv->phys[phy_num]) {
ret = phy_init(priv->phys[phy_num]);
if (ret)
goto err_exit_phy;
ret = phy_power_on(priv->phys[phy_num]);
if (ret) {
phy_exit(priv->phys[phy_num]);
goto err_exit_phy;
}
}
}
return 0;
err_exit_phy:
while (--phy_num >= 0) {
if (priv->phys[phy_num]) {
phy_power_off(priv->phys[phy_num]);
phy_exit(priv->phys[phy_num]);
}
}
err_disable_clks:
while (--clk >= 0)
clk_disable_unprepare(priv->clks[clk]);
return ret;
}
static void ohci_platform_power_off(struct platform_device *dev)
{
struct usb_hcd *hcd = platform_get_drvdata(dev);
struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
int clk, phy_num;
for (phy_num = 0; phy_num < priv->num_phys; phy_num++) {
if (priv->phys[phy_num]) {
phy_power_off(priv->phys[phy_num]);
phy_exit(priv->phys[phy_num]);
}
}
for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--)
if (priv->clks[clk])
clk_disable_unprepare(priv->clks[clk]);
}
static struct hc_driver __read_mostly ohci_platform_hc_driver;
static const struct ohci_driver_overrides platform_overrides __initconst = {
.product_desc = "Generic Platform OHCI controller",
.extra_priv_size = sizeof(struct ohci_platform_priv),
};
static struct usb_ohci_pdata ohci_platform_defaults = {
.power_on = ohci_platform_power_on,
.power_suspend = ohci_platform_power_off,
.power_off = ohci_platform_power_off,
};
static int ohci_platform_probe(struct platform_device *dev)
{
struct usb_hcd *hcd;
struct resource *res_mem;
struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
struct ohci_platform_priv *priv;
struct ohci_hcd *ohci;
const char *phy_name;
int err, irq, phy_num, clk = 0;
if (usb_disabled())
return -ENODEV;
/*
* Use reasonable defaults so platforms don't have to provide these
* with DT probing on ARM.
*/
if (!pdata)
pdata = &ohci_platform_defaults;
err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
if (err)
return err;
irq = platform_get_irq(dev, 0);
if (irq < 0) {
dev_err(&dev->dev, "no irq provided");
return irq;
}
hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev,
dev_name(&dev->dev));
if (!hcd)
return -ENOMEM;
platform_set_drvdata(dev, hcd);
dev->dev.platform_data = pdata;
priv = hcd_to_ohci_priv(hcd);
ohci = hcd_to_ohci(hcd);
if (pdata == &ohci_platform_defaults && dev->dev.of_node) {
if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
ohci->flags |= OHCI_QUIRK_BE_MMIO;
if (of_property_read_bool(dev->dev.of_node, "big-endian-desc"))
ohci->flags |= OHCI_QUIRK_BE_DESC;
if (of_property_read_bool(dev->dev.of_node, "big-endian"))
ohci->flags |= OHCI_QUIRK_BE_MMIO | OHCI_QUIRK_BE_DESC;
if (of_property_read_bool(dev->dev.of_node, "no-big-frame-no"))
ohci->flags |= OHCI_QUIRK_FRAME_NO;
of_property_read_u32(dev->dev.of_node, "num-ports",
&ohci->num_ports);
priv->num_phys = of_count_phandle_with_args(dev->dev.of_node,
"phys", "#phy-cells");
priv->num_phys = priv->num_phys > 0 ? priv->num_phys : 1;
priv->phys = devm_kcalloc(&dev->dev, priv->num_phys,
sizeof(struct phy *), GFP_KERNEL);
if (!priv->phys)
return -ENOMEM;
for (phy_num = 0; phy_num < priv->num_phys; phy_num++) {
err = of_property_read_string_index(
dev->dev.of_node,
"phy-names", phy_num,
&phy_name);
if (err < 0) {
if (priv->num_phys > 1) {
dev_err(&dev->dev, "phy-names not provided");
goto err_put_hcd;
} else
phy_name = "usb";
}
priv->phys[phy_num] = devm_phy_get(&dev->dev,
phy_name);
if (IS_ERR(priv->phys[phy_num])) {
err = PTR_ERR(priv->phys[phy_num]);
if ((priv->num_phys > 1) ||
(err == -EPROBE_DEFER))
goto err_put_hcd;
priv->phys[phy_num] = NULL;
}
}
for (clk = 0; clk < OHCI_MAX_CLKS; clk++) {
priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
if (IS_ERR(priv->clks[clk])) {
err = PTR_ERR(priv->clks[clk]);
if (err == -EPROBE_DEFER)
goto err_put_clks;
priv->clks[clk] = NULL;
break;
}
}
}
priv->rst = devm_reset_control_get_optional(&dev->dev, NULL);
if (IS_ERR(priv->rst)) {
err = PTR_ERR(priv->rst);
if (err == -EPROBE_DEFER)
goto err_put_clks;
priv->rst = NULL;
} else {
err = reset_control_deassert(priv->rst);
if (err)
goto err_put_clks;
}
if (pdata->big_endian_desc)
ohci->flags |= OHCI_QUIRK_BE_DESC;
if (pdata->big_endian_mmio)
ohci->flags |= OHCI_QUIRK_BE_MMIO;
if (pdata->no_big_frame_no)
ohci->flags |= OHCI_QUIRK_FRAME_NO;
if (pdata->num_ports)
ohci->num_ports = pdata->num_ports;
#ifndef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
if (ohci->flags & OHCI_QUIRK_BE_MMIO) {
dev_err(&dev->dev,
"Error: CONFIG_USB_OHCI_BIG_ENDIAN_MMIO not set\n");
err = -EINVAL;
goto err_reset;
}
#endif
#ifndef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
if (ohci->flags & OHCI_QUIRK_BE_DESC) {
dev_err(&dev->dev,
"Error: CONFIG_USB_OHCI_BIG_ENDIAN_DESC not set\n");
err = -EINVAL;
goto err_reset;
}
#endif
if (pdata->power_on) {
err = pdata->power_on(dev);
if (err < 0)
goto err_reset;
}
res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
if (IS_ERR(hcd->regs)) {
err = PTR_ERR(hcd->regs);
goto err_power;
}
hcd->rsrc_start = res_mem->start;
hcd->rsrc_len = resource_size(res_mem);
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (err)
goto err_power;
device_wakeup_enable(hcd->self.controller);
platform_set_drvdata(dev, hcd);
return err;
err_power:
if (pdata->power_off)
pdata->power_off(dev);
err_reset:
if (priv->rst)
reset_control_assert(priv->rst);
err_put_clks:
while (--clk >= 0)
clk_put(priv->clks[clk]);
err_put_hcd:
if (pdata == &ohci_platform_defaults)
dev->dev.platform_data = NULL;
usb_put_hcd(hcd);
return err;
}
static int ohci_platform_remove(struct platform_device *dev)
{
struct usb_hcd *hcd = platform_get_drvdata(dev);
struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
int clk;
usb_remove_hcd(hcd);
if (pdata->power_off)
pdata->power_off(dev);
if (priv->rst)
reset_control_assert(priv->rst);
for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++)
clk_put(priv->clks[clk]);
usb_put_hcd(hcd);
if (pdata == &ohci_platform_defaults)
dev->dev.platform_data = NULL;
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int ohci_platform_suspend(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct usb_ohci_pdata *pdata = dev->platform_data;
struct platform_device *pdev =
container_of(dev, struct platform_device, dev);
bool do_wakeup = device_may_wakeup(dev);
int ret;
ret = ohci_suspend(hcd, do_wakeup);
if (ret)
return ret;
if (pdata->power_suspend)
pdata->power_suspend(pdev);
return ret;
}
static int ohci_platform_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct usb_ohci_pdata *pdata = dev_get_platdata(dev);
struct platform_device *pdev =
container_of(dev, struct platform_device, dev);
if (pdata->power_on) {
int err = pdata->power_on(pdev);
if (err < 0)
return err;
}
ohci_resume(hcd, false);
return 0;
}
#endif /* CONFIG_PM_SLEEP */
static const struct of_device_id ohci_platform_ids[] = {
{ .compatible = "generic-ohci", },
{ .compatible = "cavium,octeon-6335-ohci", },
{ }
};
MODULE_DEVICE_TABLE(of, ohci_platform_ids);
static const struct platform_device_id ohci_platform_table[] = {
{ "ohci-platform", 0 },
{ }
};
MODULE_DEVICE_TABLE(platform, ohci_platform_table);
static SIMPLE_DEV_PM_OPS(ohci_platform_pm_ops, ohci_platform_suspend,
ohci_platform_resume);
static struct platform_driver ohci_platform_driver = {
.id_table = ohci_platform_table,
.probe = ohci_platform_probe,
.remove = ohci_platform_remove,
.shutdown = usb_hcd_platform_shutdown,
.driver = {
.name = "ohci-platform",
.pm = &ohci_platform_pm_ops,
.of_match_table = ohci_platform_ids,
}
};
static int __init ohci_platform_init(void)
{
if (usb_disabled())
return -ENODEV;
pr_info("%s: " DRIVER_DESC "\n", hcd_name);
ohci_init_driver(&ohci_platform_hc_driver, &platform_overrides);
return platform_driver_register(&ohci_platform_driver);
}
module_init(ohci_platform_init);
static void __exit ohci_platform_cleanup(void)
{
platform_driver_unregister(&ohci_platform_driver);
}
module_exit(ohci_platform_cleanup);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_AUTHOR("Hauke Mehrtens");
MODULE_AUTHOR("Alan Stern");
MODULE_LICENSE("GPL");
| gpl-2.0 |
giorgio130/KK_kernel | drivers/tc/tc.c | 613 | 5200 | /*
* TURBOchannel bus services.
*
* Copyright (c) Harald Koerfgen, 1998
* Copyright (c) 2001, 2003, 2005, 2006 Maciej W. Rozycki
* Copyright (c) 2005 James Simmons
*
* This file is subject to the terms and conditions of the GNU
* General Public License. See the file "COPYING" in the main
* directory of this archive for more details.
*/
#include <linux/compiler.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/tc.h>
#include <linux/types.h>
#include <asm/io.h>
static struct tc_bus tc_bus = {
.name = "TURBOchannel",
};
/*
* Probing for TURBOchannel modules.
*/
static void __init tc_bus_add_devices(struct tc_bus *tbus)
{
resource_size_t slotsize = tbus->info.slot_size << 20;
resource_size_t extslotsize = tbus->ext_slot_size;
resource_size_t slotaddr;
resource_size_t extslotaddr;
resource_size_t devsize;
void __iomem *module;
struct tc_dev *tdev;
int i, slot, err;
u8 pattern[4];
long offset;
for (slot = 0; slot < tbus->num_tcslots; slot++) {
slotaddr = tbus->slot_base + slot * slotsize;
extslotaddr = tbus->ext_slot_base + slot * extslotsize;
module = ioremap_nocache(slotaddr, slotsize);
BUG_ON(!module);
offset = TC_OLDCARD;
err = 0;
err |= tc_preadb(pattern + 0, module + offset + TC_PATTERN0);
err |= tc_preadb(pattern + 1, module + offset + TC_PATTERN1);
err |= tc_preadb(pattern + 2, module + offset + TC_PATTERN2);
err |= tc_preadb(pattern + 3, module + offset + TC_PATTERN3);
if (err)
goto out_err;
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
pattern[2] != 0xaa || pattern[3] != 0xff) {
offset = TC_NEWCARD;
err = 0;
err |= tc_preadb(pattern + 0,
module + offset + TC_PATTERN0);
err |= tc_preadb(pattern + 1,
module + offset + TC_PATTERN1);
err |= tc_preadb(pattern + 2,
module + offset + TC_PATTERN2);
err |= tc_preadb(pattern + 3,
module + offset + TC_PATTERN3);
if (err)
goto out_err;
}
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
pattern[2] != 0xaa || pattern[3] != 0xff)
goto out_err;
/* Found a board, allocate it an entry in the list */
tdev = kzalloc(sizeof(*tdev), GFP_KERNEL);
if (!tdev) {
printk(KERN_ERR "tc%x: unable to allocate tc_dev\n",
slot);
goto out_err;
}
dev_set_name(&tdev->dev, "tc%x", slot);
tdev->bus = tbus;
tdev->dev.parent = &tbus->dev;
tdev->dev.bus = &tc_bus_type;
tdev->slot = slot;
for (i = 0; i < 8; i++) {
tdev->firmware[i] =
readb(module + offset + TC_FIRM_VER + 4 * i);
tdev->vendor[i] =
readb(module + offset + TC_VENDOR + 4 * i);
tdev->name[i] =
readb(module + offset + TC_MODULE + 4 * i);
}
tdev->firmware[8] = 0;
tdev->vendor[8] = 0;
tdev->name[8] = 0;
pr_info("%s: %s %s %s\n", dev_name(&tdev->dev), tdev->vendor,
tdev->name, tdev->firmware);
devsize = readb(module + offset + TC_SLOT_SIZE);
devsize <<= 22;
if (devsize <= slotsize) {
tdev->resource.start = slotaddr;
tdev->resource.end = slotaddr + devsize - 1;
} else if (devsize <= extslotsize) {
tdev->resource.start = extslotaddr;
tdev->resource.end = extslotaddr + devsize - 1;
} else {
printk(KERN_ERR "%s: Cannot provide slot space "
"(%dMiB required, up to %dMiB supported)\n",
dev_name(&tdev->dev), devsize >> 20,
max(slotsize, extslotsize) >> 20);
kfree(tdev);
goto out_err;
}
tdev->resource.name = tdev->name;
tdev->resource.flags = IORESOURCE_MEM;
tc_device_get_irq(tdev);
device_register(&tdev->dev);
list_add_tail(&tdev->node, &tbus->devices);
out_err:
iounmap(module);
}
}
/*
* The main entry.
*/
static int __init tc_init(void)
{
/* Initialize the TURBOchannel bus */
if (tc_bus_get_info(&tc_bus))
return 0;
INIT_LIST_HEAD(&tc_bus.devices);
dev_set_name(&tc_bus.dev, "tc");
device_register(&tc_bus.dev);
if (tc_bus.info.slot_size) {
unsigned int tc_clock = tc_get_speed(&tc_bus) / 100000;
pr_info("tc: TURBOchannel rev. %d at %d.%d MHz "
"(with%s parity)\n", tc_bus.info.revision,
tc_clock / 10, tc_clock % 10,
tc_bus.info.parity ? "" : "out");
tc_bus.resource[0].start = tc_bus.slot_base;
tc_bus.resource[0].end = tc_bus.slot_base +
(tc_bus.info.slot_size << 20) *
tc_bus.num_tcslots - 1;
tc_bus.resource[0].name = tc_bus.name;
tc_bus.resource[0].flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource,
&tc_bus.resource[0]) < 0) {
printk(KERN_ERR "tc: Cannot reserve resource\n");
return 0;
}
if (tc_bus.ext_slot_size) {
tc_bus.resource[1].start = tc_bus.ext_slot_base;
tc_bus.resource[1].end = tc_bus.ext_slot_base +
tc_bus.ext_slot_size *
tc_bus.num_tcslots - 1;
tc_bus.resource[1].name = tc_bus.name;
tc_bus.resource[1].flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource,
&tc_bus.resource[1]) < 0) {
printk(KERN_ERR
"tc: Cannot reserve resource\n");
release_resource(&tc_bus.resource[0]);
return 0;
}
}
tc_bus_add_devices(&tc_bus);
}
return 0;
}
subsys_initcall(tc_init);
| gpl-2.0 |
bergwolf/redpatch | drivers/input/serio/rpckbd.c | 613 | 3956 | /*
* Copyright (c) 2000-2001 Vojtech Pavlik
* Copyright (c) 2002 Russell King
*/
/*
* Acorn RiscPC PS/2 keyboard controller driver for Linux/ARM
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Should you need to contact me, the author, you can do so either by
* e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
* Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/serio.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <asm/hardware/iomd.h>
#include <asm/system.h>
MODULE_AUTHOR("Vojtech Pavlik, Russell King");
MODULE_DESCRIPTION("Acorn RiscPC PS/2 keyboard controller driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:kart");
static int rpckbd_write(struct serio *port, unsigned char val)
{
while (!(iomd_readb(IOMD_KCTRL) & (1 << 7)))
cpu_relax();
iomd_writeb(val, IOMD_KARTTX);
return 0;
}
static irqreturn_t rpckbd_rx(int irq, void *dev_id)
{
struct serio *port = dev_id;
unsigned int byte;
int handled = IRQ_NONE;
while (iomd_readb(IOMD_KCTRL) & (1 << 5)) {
byte = iomd_readb(IOMD_KARTRX);
serio_interrupt(port, byte, 0);
handled = IRQ_HANDLED;
}
return handled;
}
static irqreturn_t rpckbd_tx(int irq, void *dev_id)
{
return IRQ_HANDLED;
}
static int rpckbd_open(struct serio *port)
{
/* Reset the keyboard state machine. */
iomd_writeb(0, IOMD_KCTRL);
iomd_writeb(8, IOMD_KCTRL);
iomd_readb(IOMD_KARTRX);
if (request_irq(IRQ_KEYBOARDRX, rpckbd_rx, 0, "rpckbd", port) != 0) {
printk(KERN_ERR "rpckbd.c: Could not allocate keyboard receive IRQ\n");
return -EBUSY;
}
if (request_irq(IRQ_KEYBOARDTX, rpckbd_tx, 0, "rpckbd", port) != 0) {
printk(KERN_ERR "rpckbd.c: Could not allocate keyboard transmit IRQ\n");
free_irq(IRQ_KEYBOARDRX, NULL);
return -EBUSY;
}
return 0;
}
static void rpckbd_close(struct serio *port)
{
free_irq(IRQ_KEYBOARDRX, port);
free_irq(IRQ_KEYBOARDTX, port);
}
/*
* Allocate and initialize serio structure for subsequent registration
* with serio core.
*/
static int __devinit rpckbd_probe(struct platform_device *dev)
{
struct serio *serio;
serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
if (!serio)
return -ENOMEM;
serio->id.type = SERIO_8042;
serio->write = rpckbd_write;
serio->open = rpckbd_open;
serio->close = rpckbd_close;
serio->dev.parent = &dev->dev;
strlcpy(serio->name, "RiscPC PS/2 kbd port", sizeof(serio->name));
strlcpy(serio->phys, "rpckbd/serio0", sizeof(serio->phys));
platform_set_drvdata(dev, serio);
serio_register_port(serio);
return 0;
}
static int __devexit rpckbd_remove(struct platform_device *dev)
{
struct serio *serio = platform_get_drvdata(dev);
serio_unregister_port(serio);
return 0;
}
static struct platform_driver rpckbd_driver = {
.probe = rpckbd_probe,
.remove = __devexit_p(rpckbd_remove),
.driver = {
.name = "kart",
.owner = THIS_MODULE,
},
};
static int __init rpckbd_init(void)
{
return platform_driver_register(&rpckbd_driver);
}
static void __exit rpckbd_exit(void)
{
platform_driver_unregister(&rpckbd_driver);
}
module_init(rpckbd_init);
module_exit(rpckbd_exit);
| gpl-2.0 |
houst0nn/android_kernel_lge_galbi | fs/btrfs/relocation.c | 1125 | 106832 | /*
* Copyright (C) 2009 Oracle. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License v2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 021110-1307, USA.
*/
#include <linux/sched.h>
#include <linux/pagemap.h>
#include <linux/writeback.h>
#include <linux/blkdev.h>
#include <linux/rbtree.h>
#include <linux/slab.h>
#include "ctree.h"
#include "disk-io.h"
#include "transaction.h"
#include "volumes.h"
#include "locking.h"
#include "btrfs_inode.h"
#include "async-thread.h"
#include "free-space-cache.h"
#include "inode-map.h"
/*
* backref_node, mapping_node and tree_block start with this
*/
struct tree_entry {
struct rb_node rb_node;
u64 bytenr;
};
/*
* present a tree block in the backref cache
*/
struct backref_node {
struct rb_node rb_node;
u64 bytenr;
u64 new_bytenr;
/* objectid of tree block owner, can be not uptodate */
u64 owner;
/* link to pending, changed or detached list */
struct list_head list;
/* list of upper level blocks reference this block */
struct list_head upper;
/* list of child blocks in the cache */
struct list_head lower;
/* NULL if this node is not tree root */
struct btrfs_root *root;
/* extent buffer got by COW the block */
struct extent_buffer *eb;
/* level of tree block */
unsigned int level:8;
/* is the block in non-reference counted tree */
unsigned int cowonly:1;
/* 1 if no child node in the cache */
unsigned int lowest:1;
/* is the extent buffer locked */
unsigned int locked:1;
/* has the block been processed */
unsigned int processed:1;
/* have backrefs of this block been checked */
unsigned int checked:1;
/*
* 1 if corresponding block has been cowed but some upper
* level block pointers may not point to the new location
*/
unsigned int pending:1;
/*
* 1 if the backref node isn't connected to any other
* backref node.
*/
unsigned int detached:1;
};
/*
* present a block pointer in the backref cache
*/
struct backref_edge {
struct list_head list[2];
struct backref_node *node[2];
};
#define LOWER 0
#define UPPER 1
struct backref_cache {
/* red black tree of all backref nodes in the cache */
struct rb_root rb_root;
/* for passing backref nodes to btrfs_reloc_cow_block */
struct backref_node *path[BTRFS_MAX_LEVEL];
/*
* list of blocks that have been cowed but some block
* pointers in upper level blocks may not reflect the
* new location
*/
struct list_head pending[BTRFS_MAX_LEVEL];
/* list of backref nodes with no child node */
struct list_head leaves;
/* list of blocks that have been cowed in current transaction */
struct list_head changed;
/* list of detached backref node. */
struct list_head detached;
u64 last_trans;
int nr_nodes;
int nr_edges;
};
/*
* map address of tree root to tree
*/
struct mapping_node {
struct rb_node rb_node;
u64 bytenr;
void *data;
};
struct mapping_tree {
struct rb_root rb_root;
spinlock_t lock;
};
/*
* present a tree block to process
*/
struct tree_block {
struct rb_node rb_node;
u64 bytenr;
struct btrfs_key key;
unsigned int level:8;
unsigned int key_ready:1;
};
#define MAX_EXTENTS 128
struct file_extent_cluster {
u64 start;
u64 end;
u64 boundary[MAX_EXTENTS];
unsigned int nr;
};
struct reloc_control {
/* block group to relocate */
struct btrfs_block_group_cache *block_group;
/* extent tree */
struct btrfs_root *extent_root;
/* inode for moving data */
struct inode *data_inode;
struct btrfs_block_rsv *block_rsv;
struct backref_cache backref_cache;
struct file_extent_cluster cluster;
/* tree blocks have been processed */
struct extent_io_tree processed_blocks;
/* map start of tree root to corresponding reloc tree */
struct mapping_tree reloc_root_tree;
/* list of reloc trees */
struct list_head reloc_roots;
/* size of metadata reservation for merging reloc trees */
u64 merging_rsv_size;
/* size of relocated tree nodes */
u64 nodes_relocated;
u64 search_start;
u64 extents_found;
unsigned int stage:8;
unsigned int create_reloc_tree:1;
unsigned int merge_reloc_tree:1;
unsigned int found_file_extent:1;
unsigned int commit_transaction:1;
};
/* stages of data relocation */
#define MOVE_DATA_EXTENTS 0
#define UPDATE_DATA_PTRS 1
static void remove_backref_node(struct backref_cache *cache,
struct backref_node *node);
static void __mark_block_processed(struct reloc_control *rc,
struct backref_node *node);
static void mapping_tree_init(struct mapping_tree *tree)
{
tree->rb_root = RB_ROOT;
spin_lock_init(&tree->lock);
}
static void backref_cache_init(struct backref_cache *cache)
{
int i;
cache->rb_root = RB_ROOT;
for (i = 0; i < BTRFS_MAX_LEVEL; i++)
INIT_LIST_HEAD(&cache->pending[i]);
INIT_LIST_HEAD(&cache->changed);
INIT_LIST_HEAD(&cache->detached);
INIT_LIST_HEAD(&cache->leaves);
}
static void backref_cache_cleanup(struct backref_cache *cache)
{
struct backref_node *node;
int i;
while (!list_empty(&cache->detached)) {
node = list_entry(cache->detached.next,
struct backref_node, list);
remove_backref_node(cache, node);
}
while (!list_empty(&cache->leaves)) {
node = list_entry(cache->leaves.next,
struct backref_node, lower);
remove_backref_node(cache, node);
}
cache->last_trans = 0;
for (i = 0; i < BTRFS_MAX_LEVEL; i++)
BUG_ON(!list_empty(&cache->pending[i]));
BUG_ON(!list_empty(&cache->changed));
BUG_ON(!list_empty(&cache->detached));
BUG_ON(!RB_EMPTY_ROOT(&cache->rb_root));
BUG_ON(cache->nr_nodes);
BUG_ON(cache->nr_edges);
}
static struct backref_node *alloc_backref_node(struct backref_cache *cache)
{
struct backref_node *node;
node = kzalloc(sizeof(*node), GFP_NOFS);
if (node) {
INIT_LIST_HEAD(&node->list);
INIT_LIST_HEAD(&node->upper);
INIT_LIST_HEAD(&node->lower);
RB_CLEAR_NODE(&node->rb_node);
cache->nr_nodes++;
}
return node;
}
static void free_backref_node(struct backref_cache *cache,
struct backref_node *node)
{
if (node) {
cache->nr_nodes--;
kfree(node);
}
}
static struct backref_edge *alloc_backref_edge(struct backref_cache *cache)
{
struct backref_edge *edge;
edge = kzalloc(sizeof(*edge), GFP_NOFS);
if (edge)
cache->nr_edges++;
return edge;
}
static void free_backref_edge(struct backref_cache *cache,
struct backref_edge *edge)
{
if (edge) {
cache->nr_edges--;
kfree(edge);
}
}
static struct rb_node *tree_insert(struct rb_root *root, u64 bytenr,
struct rb_node *node)
{
struct rb_node **p = &root->rb_node;
struct rb_node *parent = NULL;
struct tree_entry *entry;
while (*p) {
parent = *p;
entry = rb_entry(parent, struct tree_entry, rb_node);
if (bytenr < entry->bytenr)
p = &(*p)->rb_left;
else if (bytenr > entry->bytenr)
p = &(*p)->rb_right;
else
return parent;
}
rb_link_node(node, parent, p);
rb_insert_color(node, root);
return NULL;
}
static struct rb_node *tree_search(struct rb_root *root, u64 bytenr)
{
struct rb_node *n = root->rb_node;
struct tree_entry *entry;
while (n) {
entry = rb_entry(n, struct tree_entry, rb_node);
if (bytenr < entry->bytenr)
n = n->rb_left;
else if (bytenr > entry->bytenr)
n = n->rb_right;
else
return n;
}
return NULL;
}
void backref_tree_panic(struct rb_node *rb_node, int errno,
u64 bytenr)
{
struct btrfs_fs_info *fs_info = NULL;
struct backref_node *bnode = rb_entry(rb_node, struct backref_node,
rb_node);
if (bnode->root)
fs_info = bnode->root->fs_info;
btrfs_panic(fs_info, errno, "Inconsistency in backref cache "
"found at offset %llu\n", (unsigned long long)bytenr);
}
/*
* walk up backref nodes until reach node presents tree root
*/
static struct backref_node *walk_up_backref(struct backref_node *node,
struct backref_edge *edges[],
int *index)
{
struct backref_edge *edge;
int idx = *index;
while (!list_empty(&node->upper)) {
edge = list_entry(node->upper.next,
struct backref_edge, list[LOWER]);
edges[idx++] = edge;
node = edge->node[UPPER];
}
BUG_ON(node->detached);
*index = idx;
return node;
}
/*
* walk down backref nodes to find start of next reference path
*/
static struct backref_node *walk_down_backref(struct backref_edge *edges[],
int *index)
{
struct backref_edge *edge;
struct backref_node *lower;
int idx = *index;
while (idx > 0) {
edge = edges[idx - 1];
lower = edge->node[LOWER];
if (list_is_last(&edge->list[LOWER], &lower->upper)) {
idx--;
continue;
}
edge = list_entry(edge->list[LOWER].next,
struct backref_edge, list[LOWER]);
edges[idx - 1] = edge;
*index = idx;
return edge->node[UPPER];
}
*index = 0;
return NULL;
}
static void unlock_node_buffer(struct backref_node *node)
{
if (node->locked) {
btrfs_tree_unlock(node->eb);
node->locked = 0;
}
}
static void drop_node_buffer(struct backref_node *node)
{
if (node->eb) {
unlock_node_buffer(node);
free_extent_buffer(node->eb);
node->eb = NULL;
}
}
static void drop_backref_node(struct backref_cache *tree,
struct backref_node *node)
{
BUG_ON(!list_empty(&node->upper));
drop_node_buffer(node);
list_del(&node->list);
list_del(&node->lower);
if (!RB_EMPTY_NODE(&node->rb_node))
rb_erase(&node->rb_node, &tree->rb_root);
free_backref_node(tree, node);
}
/*
* remove a backref node from the backref cache
*/
static void remove_backref_node(struct backref_cache *cache,
struct backref_node *node)
{
struct backref_node *upper;
struct backref_edge *edge;
if (!node)
return;
BUG_ON(!node->lowest && !node->detached);
while (!list_empty(&node->upper)) {
edge = list_entry(node->upper.next, struct backref_edge,
list[LOWER]);
upper = edge->node[UPPER];
list_del(&edge->list[LOWER]);
list_del(&edge->list[UPPER]);
free_backref_edge(cache, edge);
if (RB_EMPTY_NODE(&upper->rb_node)) {
BUG_ON(!list_empty(&node->upper));
drop_backref_node(cache, node);
node = upper;
node->lowest = 1;
continue;
}
/*
* add the node to leaf node list if no other
* child block cached.
*/
if (list_empty(&upper->lower)) {
list_add_tail(&upper->lower, &cache->leaves);
upper->lowest = 1;
}
}
drop_backref_node(cache, node);
}
static void update_backref_node(struct backref_cache *cache,
struct backref_node *node, u64 bytenr)
{
struct rb_node *rb_node;
rb_erase(&node->rb_node, &cache->rb_root);
node->bytenr = bytenr;
rb_node = tree_insert(&cache->rb_root, node->bytenr, &node->rb_node);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST, bytenr);
}
/*
* update backref cache after a transaction commit
*/
static int update_backref_cache(struct btrfs_trans_handle *trans,
struct backref_cache *cache)
{
struct backref_node *node;
int level = 0;
if (cache->last_trans == 0) {
cache->last_trans = trans->transid;
return 0;
}
if (cache->last_trans == trans->transid)
return 0;
/*
* detached nodes are used to avoid unnecessary backref
* lookup. transaction commit changes the extent tree.
* so the detached nodes are no longer useful.
*/
while (!list_empty(&cache->detached)) {
node = list_entry(cache->detached.next,
struct backref_node, list);
remove_backref_node(cache, node);
}
while (!list_empty(&cache->changed)) {
node = list_entry(cache->changed.next,
struct backref_node, list);
list_del_init(&node->list);
BUG_ON(node->pending);
update_backref_node(cache, node, node->new_bytenr);
}
/*
* some nodes can be left in the pending list if there were
* errors during processing the pending nodes.
*/
for (level = 0; level < BTRFS_MAX_LEVEL; level++) {
list_for_each_entry(node, &cache->pending[level], list) {
BUG_ON(!node->pending);
if (node->bytenr == node->new_bytenr)
continue;
update_backref_node(cache, node, node->new_bytenr);
}
}
cache->last_trans = 0;
return 1;
}
static int should_ignore_root(struct btrfs_root *root)
{
struct btrfs_root *reloc_root;
if (!root->ref_cows)
return 0;
reloc_root = root->reloc_root;
if (!reloc_root)
return 0;
if (btrfs_root_last_snapshot(&reloc_root->root_item) ==
root->fs_info->running_transaction->transid - 1)
return 0;
/*
* if there is reloc tree and it was created in previous
* transaction backref lookup can find the reloc tree,
* so backref node for the fs tree root is useless for
* relocation.
*/
return 1;
}
/*
* find reloc tree by address of tree root
*/
static struct btrfs_root *find_reloc_root(struct reloc_control *rc,
u64 bytenr)
{
struct rb_node *rb_node;
struct mapping_node *node;
struct btrfs_root *root = NULL;
spin_lock(&rc->reloc_root_tree.lock);
rb_node = tree_search(&rc->reloc_root_tree.rb_root, bytenr);
if (rb_node) {
node = rb_entry(rb_node, struct mapping_node, rb_node);
root = (struct btrfs_root *)node->data;
}
spin_unlock(&rc->reloc_root_tree.lock);
return root;
}
static int is_cowonly_root(u64 root_objectid)
{
if (root_objectid == BTRFS_ROOT_TREE_OBJECTID ||
root_objectid == BTRFS_EXTENT_TREE_OBJECTID ||
root_objectid == BTRFS_CHUNK_TREE_OBJECTID ||
root_objectid == BTRFS_DEV_TREE_OBJECTID ||
root_objectid == BTRFS_TREE_LOG_OBJECTID ||
root_objectid == BTRFS_CSUM_TREE_OBJECTID)
return 1;
return 0;
}
static struct btrfs_root *read_fs_root(struct btrfs_fs_info *fs_info,
u64 root_objectid)
{
struct btrfs_key key;
key.objectid = root_objectid;
key.type = BTRFS_ROOT_ITEM_KEY;
if (is_cowonly_root(root_objectid))
key.offset = 0;
else
key.offset = (u64)-1;
return btrfs_read_fs_root_no_name(fs_info, &key);
}
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
static noinline_for_stack
struct btrfs_root *find_tree_root(struct reloc_control *rc,
struct extent_buffer *leaf,
struct btrfs_extent_ref_v0 *ref0)
{
struct btrfs_root *root;
u64 root_objectid = btrfs_ref_root_v0(leaf, ref0);
u64 generation = btrfs_ref_generation_v0(leaf, ref0);
BUG_ON(root_objectid == BTRFS_TREE_RELOC_OBJECTID);
root = read_fs_root(rc->extent_root->fs_info, root_objectid);
BUG_ON(IS_ERR(root));
if (root->ref_cows &&
generation != btrfs_root_generation(&root->root_item))
return NULL;
return root;
}
#endif
static noinline_for_stack
int find_inline_backref(struct extent_buffer *leaf, int slot,
unsigned long *ptr, unsigned long *end)
{
struct btrfs_extent_item *ei;
struct btrfs_tree_block_info *bi;
u32 item_size;
item_size = btrfs_item_size_nr(leaf, slot);
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
if (item_size < sizeof(*ei)) {
WARN_ON(item_size != sizeof(struct btrfs_extent_item_v0));
return 1;
}
#endif
ei = btrfs_item_ptr(leaf, slot, struct btrfs_extent_item);
WARN_ON(!(btrfs_extent_flags(leaf, ei) &
BTRFS_EXTENT_FLAG_TREE_BLOCK));
if (item_size <= sizeof(*ei) + sizeof(*bi)) {
WARN_ON(item_size < sizeof(*ei) + sizeof(*bi));
return 1;
}
bi = (struct btrfs_tree_block_info *)(ei + 1);
*ptr = (unsigned long)(bi + 1);
*end = (unsigned long)ei + item_size;
return 0;
}
/*
* build backref tree for a given tree block. root of the backref tree
* corresponds the tree block, leaves of the backref tree correspond
* roots of b-trees that reference the tree block.
*
* the basic idea of this function is check backrefs of a given block
* to find upper level blocks that refernece the block, and then check
* bakcrefs of these upper level blocks recursively. the recursion stop
* when tree root is reached or backrefs for the block is cached.
*
* NOTE: if we find backrefs for a block are cached, we know backrefs
* for all upper level blocks that directly/indirectly reference the
* block are also cached.
*/
static noinline_for_stack
struct backref_node *build_backref_tree(struct reloc_control *rc,
struct btrfs_key *node_key,
int level, u64 bytenr)
{
struct backref_cache *cache = &rc->backref_cache;
struct btrfs_path *path1;
struct btrfs_path *path2;
struct extent_buffer *eb;
struct btrfs_root *root;
struct backref_node *cur;
struct backref_node *upper;
struct backref_node *lower;
struct backref_node *node = NULL;
struct backref_node *exist = NULL;
struct backref_edge *edge;
struct rb_node *rb_node;
struct btrfs_key key;
unsigned long end;
unsigned long ptr;
LIST_HEAD(list);
LIST_HEAD(useless);
int cowonly;
int ret;
int err = 0;
bool need_check = true;
path1 = btrfs_alloc_path();
path2 = btrfs_alloc_path();
if (!path1 || !path2) {
err = -ENOMEM;
goto out;
}
path1->reada = 1;
path2->reada = 2;
node = alloc_backref_node(cache);
if (!node) {
err = -ENOMEM;
goto out;
}
node->bytenr = bytenr;
node->level = level;
node->lowest = 1;
cur = node;
again:
end = 0;
ptr = 0;
key.objectid = cur->bytenr;
key.type = BTRFS_EXTENT_ITEM_KEY;
key.offset = (u64)-1;
path1->search_commit_root = 1;
path1->skip_locking = 1;
ret = btrfs_search_slot(NULL, rc->extent_root, &key, path1,
0, 0);
if (ret < 0) {
err = ret;
goto out;
}
BUG_ON(!ret || !path1->slots[0]);
path1->slots[0]--;
WARN_ON(cur->checked);
if (!list_empty(&cur->upper)) {
/*
* the backref was added previously when processing
* backref of type BTRFS_TREE_BLOCK_REF_KEY
*/
BUG_ON(!list_is_singular(&cur->upper));
edge = list_entry(cur->upper.next, struct backref_edge,
list[LOWER]);
BUG_ON(!list_empty(&edge->list[UPPER]));
exist = edge->node[UPPER];
/*
* add the upper level block to pending list if we need
* check its backrefs
*/
if (!exist->checked)
list_add_tail(&edge->list[UPPER], &list);
} else {
exist = NULL;
}
while (1) {
cond_resched();
eb = path1->nodes[0];
if (ptr >= end) {
if (path1->slots[0] >= btrfs_header_nritems(eb)) {
ret = btrfs_next_leaf(rc->extent_root, path1);
if (ret < 0) {
err = ret;
goto out;
}
if (ret > 0)
break;
eb = path1->nodes[0];
}
btrfs_item_key_to_cpu(eb, &key, path1->slots[0]);
if (key.objectid != cur->bytenr) {
WARN_ON(exist);
break;
}
if (key.type == BTRFS_EXTENT_ITEM_KEY) {
ret = find_inline_backref(eb, path1->slots[0],
&ptr, &end);
if (ret)
goto next;
}
}
if (ptr < end) {
/* update key for inline back ref */
struct btrfs_extent_inline_ref *iref;
iref = (struct btrfs_extent_inline_ref *)ptr;
key.type = btrfs_extent_inline_ref_type(eb, iref);
key.offset = btrfs_extent_inline_ref_offset(eb, iref);
WARN_ON(key.type != BTRFS_TREE_BLOCK_REF_KEY &&
key.type != BTRFS_SHARED_BLOCK_REF_KEY);
}
if (exist &&
((key.type == BTRFS_TREE_BLOCK_REF_KEY &&
exist->owner == key.offset) ||
(key.type == BTRFS_SHARED_BLOCK_REF_KEY &&
exist->bytenr == key.offset))) {
exist = NULL;
goto next;
}
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
if (key.type == BTRFS_SHARED_BLOCK_REF_KEY ||
key.type == BTRFS_EXTENT_REF_V0_KEY) {
if (key.type == BTRFS_EXTENT_REF_V0_KEY) {
struct btrfs_extent_ref_v0 *ref0;
ref0 = btrfs_item_ptr(eb, path1->slots[0],
struct btrfs_extent_ref_v0);
if (key.objectid == key.offset) {
root = find_tree_root(rc, eb, ref0);
if (root && !should_ignore_root(root))
cur->root = root;
else
list_add(&cur->list, &useless);
break;
}
if (is_cowonly_root(btrfs_ref_root_v0(eb,
ref0)))
cur->cowonly = 1;
}
#else
BUG_ON(key.type == BTRFS_EXTENT_REF_V0_KEY);
if (key.type == BTRFS_SHARED_BLOCK_REF_KEY) {
#endif
if (key.objectid == key.offset) {
/*
* only root blocks of reloc trees use
* backref of this type.
*/
root = find_reloc_root(rc, cur->bytenr);
BUG_ON(!root);
cur->root = root;
break;
}
edge = alloc_backref_edge(cache);
if (!edge) {
err = -ENOMEM;
goto out;
}
rb_node = tree_search(&cache->rb_root, key.offset);
if (!rb_node) {
upper = alloc_backref_node(cache);
if (!upper) {
free_backref_edge(cache, edge);
err = -ENOMEM;
goto out;
}
upper->bytenr = key.offset;
upper->level = cur->level + 1;
/*
* backrefs for the upper level block isn't
* cached, add the block to pending list
*/
list_add_tail(&edge->list[UPPER], &list);
} else {
upper = rb_entry(rb_node, struct backref_node,
rb_node);
BUG_ON(!upper->checked);
INIT_LIST_HEAD(&edge->list[UPPER]);
}
list_add_tail(&edge->list[LOWER], &cur->upper);
edge->node[LOWER] = cur;
edge->node[UPPER] = upper;
goto next;
} else if (key.type != BTRFS_TREE_BLOCK_REF_KEY) {
goto next;
}
/* key.type == BTRFS_TREE_BLOCK_REF_KEY */
root = read_fs_root(rc->extent_root->fs_info, key.offset);
if (IS_ERR(root)) {
err = PTR_ERR(root);
goto out;
}
if (!root->ref_cows)
cur->cowonly = 1;
if (btrfs_root_level(&root->root_item) == cur->level) {
/* tree root */
BUG_ON(btrfs_root_bytenr(&root->root_item) !=
cur->bytenr);
if (should_ignore_root(root))
list_add(&cur->list, &useless);
else
cur->root = root;
break;
}
level = cur->level + 1;
/*
* searching the tree to find upper level blocks
* reference the block.
*/
path2->search_commit_root = 1;
path2->skip_locking = 1;
path2->lowest_level = level;
ret = btrfs_search_slot(NULL, root, node_key, path2, 0, 0);
path2->lowest_level = 0;
if (ret < 0) {
err = ret;
goto out;
}
if (ret > 0 && path2->slots[level] > 0)
path2->slots[level]--;
eb = path2->nodes[level];
WARN_ON(btrfs_node_blockptr(eb, path2->slots[level]) !=
cur->bytenr);
lower = cur;
need_check = true;
for (; level < BTRFS_MAX_LEVEL; level++) {
if (!path2->nodes[level]) {
BUG_ON(btrfs_root_bytenr(&root->root_item) !=
lower->bytenr);
if (should_ignore_root(root))
list_add(&lower->list, &useless);
else
lower->root = root;
break;
}
edge = alloc_backref_edge(cache);
if (!edge) {
err = -ENOMEM;
goto out;
}
eb = path2->nodes[level];
rb_node = tree_search(&cache->rb_root, eb->start);
if (!rb_node) {
upper = alloc_backref_node(cache);
if (!upper) {
free_backref_edge(cache, edge);
err = -ENOMEM;
goto out;
}
upper->bytenr = eb->start;
upper->owner = btrfs_header_owner(eb);
upper->level = lower->level + 1;
if (!root->ref_cows)
upper->cowonly = 1;
/*
* if we know the block isn't shared
* we can void checking its backrefs.
*/
if (btrfs_block_can_be_shared(root, eb))
upper->checked = 0;
else
upper->checked = 1;
/*
* add the block to pending list if we
* need check its backrefs, we only do this once
* while walking up a tree as we will catch
* anything else later on.
*/
if (!upper->checked && need_check) {
need_check = false;
list_add_tail(&edge->list[UPPER],
&list);
} else
INIT_LIST_HEAD(&edge->list[UPPER]);
} else {
upper = rb_entry(rb_node, struct backref_node,
rb_node);
BUG_ON(!upper->checked);
INIT_LIST_HEAD(&edge->list[UPPER]);
if (!upper->owner)
upper->owner = btrfs_header_owner(eb);
}
list_add_tail(&edge->list[LOWER], &lower->upper);
edge->node[LOWER] = lower;
edge->node[UPPER] = upper;
if (rb_node)
break;
lower = upper;
upper = NULL;
}
btrfs_release_path(path2);
next:
if (ptr < end) {
ptr += btrfs_extent_inline_ref_size(key.type);
if (ptr >= end) {
WARN_ON(ptr > end);
ptr = 0;
end = 0;
}
}
if (ptr >= end)
path1->slots[0]++;
}
btrfs_release_path(path1);
cur->checked = 1;
WARN_ON(exist);
/* the pending list isn't empty, take the first block to process */
if (!list_empty(&list)) {
edge = list_entry(list.next, struct backref_edge, list[UPPER]);
list_del_init(&edge->list[UPPER]);
cur = edge->node[UPPER];
goto again;
}
/*
* everything goes well, connect backref nodes and insert backref nodes
* into the cache.
*/
BUG_ON(!node->checked);
cowonly = node->cowonly;
if (!cowonly) {
rb_node = tree_insert(&cache->rb_root, node->bytenr,
&node->rb_node);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST, node->bytenr);
list_add_tail(&node->lower, &cache->leaves);
}
list_for_each_entry(edge, &node->upper, list[LOWER])
list_add_tail(&edge->list[UPPER], &list);
while (!list_empty(&list)) {
edge = list_entry(list.next, struct backref_edge, list[UPPER]);
list_del_init(&edge->list[UPPER]);
upper = edge->node[UPPER];
if (upper->detached) {
list_del(&edge->list[LOWER]);
lower = edge->node[LOWER];
free_backref_edge(cache, edge);
if (list_empty(&lower->upper))
list_add(&lower->list, &useless);
continue;
}
if (!RB_EMPTY_NODE(&upper->rb_node)) {
if (upper->lowest) {
list_del_init(&upper->lower);
upper->lowest = 0;
}
list_add_tail(&edge->list[UPPER], &upper->lower);
continue;
}
BUG_ON(!upper->checked);
BUG_ON(cowonly != upper->cowonly);
if (!cowonly) {
rb_node = tree_insert(&cache->rb_root, upper->bytenr,
&upper->rb_node);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST,
upper->bytenr);
}
list_add_tail(&edge->list[UPPER], &upper->lower);
list_for_each_entry(edge, &upper->upper, list[LOWER])
list_add_tail(&edge->list[UPPER], &list);
}
/*
* process useless backref nodes. backref nodes for tree leaves
* are deleted from the cache. backref nodes for upper level
* tree blocks are left in the cache to avoid unnecessary backref
* lookup.
*/
while (!list_empty(&useless)) {
upper = list_entry(useless.next, struct backref_node, list);
list_del_init(&upper->list);
BUG_ON(!list_empty(&upper->upper));
if (upper == node)
node = NULL;
if (upper->lowest) {
list_del_init(&upper->lower);
upper->lowest = 0;
}
while (!list_empty(&upper->lower)) {
edge = list_entry(upper->lower.next,
struct backref_edge, list[UPPER]);
list_del(&edge->list[UPPER]);
list_del(&edge->list[LOWER]);
lower = edge->node[LOWER];
free_backref_edge(cache, edge);
if (list_empty(&lower->upper))
list_add(&lower->list, &useless);
}
__mark_block_processed(rc, upper);
if (upper->level > 0) {
list_add(&upper->list, &cache->detached);
upper->detached = 1;
} else {
rb_erase(&upper->rb_node, &cache->rb_root);
free_backref_node(cache, upper);
}
}
out:
btrfs_free_path(path1);
btrfs_free_path(path2);
if (err) {
while (!list_empty(&useless)) {
lower = list_entry(useless.next,
struct backref_node, upper);
list_del_init(&lower->upper);
}
upper = node;
INIT_LIST_HEAD(&list);
while (upper) {
if (RB_EMPTY_NODE(&upper->rb_node)) {
list_splice_tail(&upper->upper, &list);
free_backref_node(cache, upper);
}
if (list_empty(&list))
break;
edge = list_entry(list.next, struct backref_edge,
list[LOWER]);
list_del(&edge->list[LOWER]);
upper = edge->node[UPPER];
free_backref_edge(cache, edge);
}
return ERR_PTR(err);
}
BUG_ON(node && node->detached);
return node;
}
/*
* helper to add backref node for the newly created snapshot.
* the backref node is created by cloning backref node that
* corresponds to root of source tree
*/
static int clone_backref_node(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct btrfs_root *src,
struct btrfs_root *dest)
{
struct btrfs_root *reloc_root = src->reloc_root;
struct backref_cache *cache = &rc->backref_cache;
struct backref_node *node = NULL;
struct backref_node *new_node;
struct backref_edge *edge;
struct backref_edge *new_edge;
struct rb_node *rb_node;
if (cache->last_trans > 0)
update_backref_cache(trans, cache);
rb_node = tree_search(&cache->rb_root, src->commit_root->start);
if (rb_node) {
node = rb_entry(rb_node, struct backref_node, rb_node);
if (node->detached)
node = NULL;
else
BUG_ON(node->new_bytenr != reloc_root->node->start);
}
if (!node) {
rb_node = tree_search(&cache->rb_root,
reloc_root->commit_root->start);
if (rb_node) {
node = rb_entry(rb_node, struct backref_node,
rb_node);
BUG_ON(node->detached);
}
}
if (!node)
return 0;
new_node = alloc_backref_node(cache);
if (!new_node)
return -ENOMEM;
new_node->bytenr = dest->node->start;
new_node->level = node->level;
new_node->lowest = node->lowest;
new_node->checked = 1;
new_node->root = dest;
if (!node->lowest) {
list_for_each_entry(edge, &node->lower, list[UPPER]) {
new_edge = alloc_backref_edge(cache);
if (!new_edge)
goto fail;
new_edge->node[UPPER] = new_node;
new_edge->node[LOWER] = edge->node[LOWER];
list_add_tail(&new_edge->list[UPPER],
&new_node->lower);
}
} else {
list_add_tail(&new_node->lower, &cache->leaves);
}
rb_node = tree_insert(&cache->rb_root, new_node->bytenr,
&new_node->rb_node);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST, new_node->bytenr);
if (!new_node->lowest) {
list_for_each_entry(new_edge, &new_node->lower, list[UPPER]) {
list_add_tail(&new_edge->list[LOWER],
&new_edge->node[LOWER]->upper);
}
}
return 0;
fail:
while (!list_empty(&new_node->lower)) {
new_edge = list_entry(new_node->lower.next,
struct backref_edge, list[UPPER]);
list_del(&new_edge->list[UPPER]);
free_backref_edge(cache, new_edge);
}
free_backref_node(cache, new_node);
return -ENOMEM;
}
/*
* helper to add 'address of tree root -> reloc tree' mapping
*/
static int __must_check __add_reloc_root(struct btrfs_root *root)
{
struct rb_node *rb_node;
struct mapping_node *node;
struct reloc_control *rc = root->fs_info->reloc_ctl;
node = kmalloc(sizeof(*node), GFP_NOFS);
if (!node)
return -ENOMEM;
node->bytenr = root->node->start;
node->data = root;
spin_lock(&rc->reloc_root_tree.lock);
rb_node = tree_insert(&rc->reloc_root_tree.rb_root,
node->bytenr, &node->rb_node);
spin_unlock(&rc->reloc_root_tree.lock);
if (rb_node) {
kfree(node);
btrfs_panic(root->fs_info, -EEXIST, "Duplicate root found "
"for start=%llu while inserting into relocation "
"tree\n");
}
list_add_tail(&root->root_list, &rc->reloc_roots);
return 0;
}
/*
* helper to update/delete the 'address of tree root -> reloc tree'
* mapping
*/
static int __update_reloc_root(struct btrfs_root *root, int del)
{
struct rb_node *rb_node;
struct mapping_node *node = NULL;
struct reloc_control *rc = root->fs_info->reloc_ctl;
spin_lock(&rc->reloc_root_tree.lock);
rb_node = tree_search(&rc->reloc_root_tree.rb_root,
root->commit_root->start);
if (rb_node) {
node = rb_entry(rb_node, struct mapping_node, rb_node);
rb_erase(&node->rb_node, &rc->reloc_root_tree.rb_root);
}
spin_unlock(&rc->reloc_root_tree.lock);
BUG_ON((struct btrfs_root *)node->data != root);
if (!del) {
spin_lock(&rc->reloc_root_tree.lock);
node->bytenr = root->node->start;
rb_node = tree_insert(&rc->reloc_root_tree.rb_root,
node->bytenr, &node->rb_node);
spin_unlock(&rc->reloc_root_tree.lock);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST, node->bytenr);
} else {
spin_lock(&root->fs_info->trans_lock);
list_del_init(&root->root_list);
spin_unlock(&root->fs_info->trans_lock);
kfree(node);
}
return 0;
}
static struct btrfs_root *create_reloc_root(struct btrfs_trans_handle *trans,
struct btrfs_root *root, u64 objectid)
{
struct btrfs_root *reloc_root;
struct extent_buffer *eb;
struct btrfs_root_item *root_item;
struct btrfs_key root_key;
int ret;
root_item = kmalloc(sizeof(*root_item), GFP_NOFS);
BUG_ON(!root_item);
root_key.objectid = BTRFS_TREE_RELOC_OBJECTID;
root_key.type = BTRFS_ROOT_ITEM_KEY;
root_key.offset = objectid;
if (root->root_key.objectid == objectid) {
/* called by btrfs_init_reloc_root */
ret = btrfs_copy_root(trans, root, root->commit_root, &eb,
BTRFS_TREE_RELOC_OBJECTID);
BUG_ON(ret);
btrfs_set_root_last_snapshot(&root->root_item,
trans->transid - 1);
} else {
/*
* called by btrfs_reloc_post_snapshot_hook.
* the source tree is a reloc tree, all tree blocks
* modified after it was created have RELOC flag
* set in their headers. so it's OK to not update
* the 'last_snapshot'.
*/
ret = btrfs_copy_root(trans, root, root->node, &eb,
BTRFS_TREE_RELOC_OBJECTID);
BUG_ON(ret);
}
memcpy(root_item, &root->root_item, sizeof(*root_item));
btrfs_set_root_bytenr(root_item, eb->start);
btrfs_set_root_level(root_item, btrfs_header_level(eb));
btrfs_set_root_generation(root_item, trans->transid);
if (root->root_key.objectid == objectid) {
btrfs_set_root_refs(root_item, 0);
memset(&root_item->drop_progress, 0,
sizeof(struct btrfs_disk_key));
root_item->drop_level = 0;
}
btrfs_tree_unlock(eb);
free_extent_buffer(eb);
ret = btrfs_insert_root(trans, root->fs_info->tree_root,
&root_key, root_item);
BUG_ON(ret);
kfree(root_item);
reloc_root = btrfs_read_fs_root_no_radix(root->fs_info->tree_root,
&root_key);
BUG_ON(IS_ERR(reloc_root));
reloc_root->last_trans = trans->transid;
return reloc_root;
}
/*
* create reloc tree for a given fs tree. reloc tree is just a
* snapshot of the fs tree with special root objectid.
*/
int btrfs_init_reloc_root(struct btrfs_trans_handle *trans,
struct btrfs_root *root)
{
struct btrfs_root *reloc_root;
struct reloc_control *rc = root->fs_info->reloc_ctl;
int clear_rsv = 0;
int ret;
if (root->reloc_root) {
reloc_root = root->reloc_root;
reloc_root->last_trans = trans->transid;
return 0;
}
if (!rc || !rc->create_reloc_tree ||
root->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID)
return 0;
if (!trans->block_rsv) {
trans->block_rsv = rc->block_rsv;
clear_rsv = 1;
}
reloc_root = create_reloc_root(trans, root, root->root_key.objectid);
if (clear_rsv)
trans->block_rsv = NULL;
ret = __add_reloc_root(reloc_root);
BUG_ON(ret < 0);
root->reloc_root = reloc_root;
return 0;
}
/*
* update root item of reloc tree
*/
int btrfs_update_reloc_root(struct btrfs_trans_handle *trans,
struct btrfs_root *root)
{
struct btrfs_root *reloc_root;
struct btrfs_root_item *root_item;
int del = 0;
int ret;
if (!root->reloc_root)
goto out;
reloc_root = root->reloc_root;
root_item = &reloc_root->root_item;
if (root->fs_info->reloc_ctl->merge_reloc_tree &&
btrfs_root_refs(root_item) == 0) {
root->reloc_root = NULL;
del = 1;
}
__update_reloc_root(reloc_root, del);
if (reloc_root->commit_root != reloc_root->node) {
btrfs_set_root_node(root_item, reloc_root->node);
free_extent_buffer(reloc_root->commit_root);
reloc_root->commit_root = btrfs_root_node(reloc_root);
}
ret = btrfs_update_root(trans, root->fs_info->tree_root,
&reloc_root->root_key, root_item);
BUG_ON(ret);
out:
return 0;
}
/*
* helper to find first cached inode with inode number >= objectid
* in a subvolume
*/
static struct inode *find_next_inode(struct btrfs_root *root, u64 objectid)
{
struct rb_node *node;
struct rb_node *prev;
struct btrfs_inode *entry;
struct inode *inode;
spin_lock(&root->inode_lock);
again:
node = root->inode_tree.rb_node;
prev = NULL;
while (node) {
prev = node;
entry = rb_entry(node, struct btrfs_inode, rb_node);
if (objectid < btrfs_ino(&entry->vfs_inode))
node = node->rb_left;
else if (objectid > btrfs_ino(&entry->vfs_inode))
node = node->rb_right;
else
break;
}
if (!node) {
while (prev) {
entry = rb_entry(prev, struct btrfs_inode, rb_node);
if (objectid <= btrfs_ino(&entry->vfs_inode)) {
node = prev;
break;
}
prev = rb_next(prev);
}
}
while (node) {
entry = rb_entry(node, struct btrfs_inode, rb_node);
inode = igrab(&entry->vfs_inode);
if (inode) {
spin_unlock(&root->inode_lock);
return inode;
}
objectid = btrfs_ino(&entry->vfs_inode) + 1;
if (cond_resched_lock(&root->inode_lock))
goto again;
node = rb_next(node);
}
spin_unlock(&root->inode_lock);
return NULL;
}
static int in_block_group(u64 bytenr,
struct btrfs_block_group_cache *block_group)
{
if (bytenr >= block_group->key.objectid &&
bytenr < block_group->key.objectid + block_group->key.offset)
return 1;
return 0;
}
/*
* get new location of data
*/
static int get_new_location(struct inode *reloc_inode, u64 *new_bytenr,
u64 bytenr, u64 num_bytes)
{
struct btrfs_root *root = BTRFS_I(reloc_inode)->root;
struct btrfs_path *path;
struct btrfs_file_extent_item *fi;
struct extent_buffer *leaf;
int ret;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
bytenr -= BTRFS_I(reloc_inode)->index_cnt;
ret = btrfs_lookup_file_extent(NULL, root, path, btrfs_ino(reloc_inode),
bytenr, 0);
if (ret < 0)
goto out;
if (ret > 0) {
ret = -ENOENT;
goto out;
}
leaf = path->nodes[0];
fi = btrfs_item_ptr(leaf, path->slots[0],
struct btrfs_file_extent_item);
BUG_ON(btrfs_file_extent_offset(leaf, fi) ||
btrfs_file_extent_compression(leaf, fi) ||
btrfs_file_extent_encryption(leaf, fi) ||
btrfs_file_extent_other_encoding(leaf, fi));
if (num_bytes != btrfs_file_extent_disk_num_bytes(leaf, fi)) {
ret = 1;
goto out;
}
*new_bytenr = btrfs_file_extent_disk_bytenr(leaf, fi);
ret = 0;
out:
btrfs_free_path(path);
return ret;
}
/*
* update file extent items in the tree leaf to point to
* the new locations.
*/
static noinline_for_stack
int replace_file_extents(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct btrfs_root *root,
struct extent_buffer *leaf)
{
struct btrfs_key key;
struct btrfs_file_extent_item *fi;
struct inode *inode = NULL;
u64 parent;
u64 bytenr;
u64 new_bytenr = 0;
u64 num_bytes;
u64 end;
u32 nritems;
u32 i;
int ret;
int first = 1;
int dirty = 0;
if (rc->stage != UPDATE_DATA_PTRS)
return 0;
/* reloc trees always use full backref */
if (root->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID)
parent = leaf->start;
else
parent = 0;
nritems = btrfs_header_nritems(leaf);
for (i = 0; i < nritems; i++) {
cond_resched();
btrfs_item_key_to_cpu(leaf, &key, i);
if (key.type != BTRFS_EXTENT_DATA_KEY)
continue;
fi = btrfs_item_ptr(leaf, i, struct btrfs_file_extent_item);
if (btrfs_file_extent_type(leaf, fi) ==
BTRFS_FILE_EXTENT_INLINE)
continue;
bytenr = btrfs_file_extent_disk_bytenr(leaf, fi);
num_bytes = btrfs_file_extent_disk_num_bytes(leaf, fi);
if (bytenr == 0)
continue;
if (!in_block_group(bytenr, rc->block_group))
continue;
/*
* if we are modifying block in fs tree, wait for readpage
* to complete and drop the extent cache
*/
if (root->root_key.objectid != BTRFS_TREE_RELOC_OBJECTID) {
if (first) {
inode = find_next_inode(root, key.objectid);
first = 0;
} else if (inode && btrfs_ino(inode) < key.objectid) {
btrfs_add_delayed_iput(inode);
inode = find_next_inode(root, key.objectid);
}
if (inode && btrfs_ino(inode) == key.objectid) {
end = key.offset +
btrfs_file_extent_num_bytes(leaf, fi);
WARN_ON(!IS_ALIGNED(key.offset,
root->sectorsize));
WARN_ON(!IS_ALIGNED(end, root->sectorsize));
end--;
ret = try_lock_extent(&BTRFS_I(inode)->io_tree,
key.offset, end);
if (!ret)
continue;
btrfs_drop_extent_cache(inode, key.offset, end,
1);
unlock_extent(&BTRFS_I(inode)->io_tree,
key.offset, end);
}
}
ret = get_new_location(rc->data_inode, &new_bytenr,
bytenr, num_bytes);
if (ret > 0) {
WARN_ON(1);
continue;
}
BUG_ON(ret < 0);
btrfs_set_file_extent_disk_bytenr(leaf, fi, new_bytenr);
dirty = 1;
key.offset -= btrfs_file_extent_offset(leaf, fi);
ret = btrfs_inc_extent_ref(trans, root, new_bytenr,
num_bytes, parent,
btrfs_header_owner(leaf),
key.objectid, key.offset, 1);
BUG_ON(ret);
ret = btrfs_free_extent(trans, root, bytenr, num_bytes,
parent, btrfs_header_owner(leaf),
key.objectid, key.offset, 1);
BUG_ON(ret);
}
if (dirty)
btrfs_mark_buffer_dirty(leaf);
if (inode)
btrfs_add_delayed_iput(inode);
return 0;
}
static noinline_for_stack
int memcmp_node_keys(struct extent_buffer *eb, int slot,
struct btrfs_path *path, int level)
{
struct btrfs_disk_key key1;
struct btrfs_disk_key key2;
btrfs_node_key(eb, &key1, slot);
btrfs_node_key(path->nodes[level], &key2, path->slots[level]);
return memcmp(&key1, &key2, sizeof(key1));
}
/*
* try to replace tree blocks in fs tree with the new blocks
* in reloc tree. tree blocks haven't been modified since the
* reloc tree was create can be replaced.
*
* if a block was replaced, level of the block + 1 is returned.
* if no block got replaced, 0 is returned. if there are other
* errors, a negative error number is returned.
*/
static noinline_for_stack
int replace_path(struct btrfs_trans_handle *trans,
struct btrfs_root *dest, struct btrfs_root *src,
struct btrfs_path *path, struct btrfs_key *next_key,
int lowest_level, int max_level)
{
struct extent_buffer *eb;
struct extent_buffer *parent;
struct btrfs_key key;
u64 old_bytenr;
u64 new_bytenr;
u64 old_ptr_gen;
u64 new_ptr_gen;
u64 last_snapshot;
u32 blocksize;
int cow = 0;
int level;
int ret;
int slot;
BUG_ON(src->root_key.objectid != BTRFS_TREE_RELOC_OBJECTID);
BUG_ON(dest->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID);
last_snapshot = btrfs_root_last_snapshot(&src->root_item);
again:
slot = path->slots[lowest_level];
btrfs_node_key_to_cpu(path->nodes[lowest_level], &key, slot);
eb = btrfs_lock_root_node(dest);
btrfs_set_lock_blocking(eb);
level = btrfs_header_level(eb);
if (level < lowest_level) {
btrfs_tree_unlock(eb);
free_extent_buffer(eb);
return 0;
}
if (cow) {
ret = btrfs_cow_block(trans, dest, eb, NULL, 0, &eb);
BUG_ON(ret);
}
btrfs_set_lock_blocking(eb);
if (next_key) {
next_key->objectid = (u64)-1;
next_key->type = (u8)-1;
next_key->offset = (u64)-1;
}
parent = eb;
while (1) {
level = btrfs_header_level(parent);
BUG_ON(level < lowest_level);
ret = btrfs_bin_search(parent, &key, level, &slot);
if (ret && slot > 0)
slot--;
if (next_key && slot + 1 < btrfs_header_nritems(parent))
btrfs_node_key_to_cpu(parent, next_key, slot + 1);
old_bytenr = btrfs_node_blockptr(parent, slot);
blocksize = btrfs_level_size(dest, level - 1);
old_ptr_gen = btrfs_node_ptr_generation(parent, slot);
if (level <= max_level) {
eb = path->nodes[level];
new_bytenr = btrfs_node_blockptr(eb,
path->slots[level]);
new_ptr_gen = btrfs_node_ptr_generation(eb,
path->slots[level]);
} else {
new_bytenr = 0;
new_ptr_gen = 0;
}
if (new_bytenr > 0 && new_bytenr == old_bytenr) {
WARN_ON(1);
ret = level;
break;
}
if (new_bytenr == 0 || old_ptr_gen > last_snapshot ||
memcmp_node_keys(parent, slot, path, level)) {
if (level <= lowest_level) {
ret = 0;
break;
}
eb = read_tree_block(dest, old_bytenr, blocksize,
old_ptr_gen);
BUG_ON(!eb);
btrfs_tree_lock(eb);
if (cow) {
ret = btrfs_cow_block(trans, dest, eb, parent,
slot, &eb);
BUG_ON(ret);
}
btrfs_set_lock_blocking(eb);
btrfs_tree_unlock(parent);
free_extent_buffer(parent);
parent = eb;
continue;
}
if (!cow) {
btrfs_tree_unlock(parent);
free_extent_buffer(parent);
cow = 1;
goto again;
}
btrfs_node_key_to_cpu(path->nodes[level], &key,
path->slots[level]);
btrfs_release_path(path);
path->lowest_level = level;
ret = btrfs_search_slot(trans, src, &key, path, 0, 1);
path->lowest_level = 0;
BUG_ON(ret);
/*
* swap blocks in fs tree and reloc tree.
*/
btrfs_set_node_blockptr(parent, slot, new_bytenr);
btrfs_set_node_ptr_generation(parent, slot, new_ptr_gen);
btrfs_mark_buffer_dirty(parent);
btrfs_set_node_blockptr(path->nodes[level],
path->slots[level], old_bytenr);
btrfs_set_node_ptr_generation(path->nodes[level],
path->slots[level], old_ptr_gen);
btrfs_mark_buffer_dirty(path->nodes[level]);
ret = btrfs_inc_extent_ref(trans, src, old_bytenr, blocksize,
path->nodes[level]->start,
src->root_key.objectid, level - 1, 0,
1);
BUG_ON(ret);
ret = btrfs_inc_extent_ref(trans, dest, new_bytenr, blocksize,
0, dest->root_key.objectid, level - 1,
0, 1);
BUG_ON(ret);
ret = btrfs_free_extent(trans, src, new_bytenr, blocksize,
path->nodes[level]->start,
src->root_key.objectid, level - 1, 0,
1);
BUG_ON(ret);
ret = btrfs_free_extent(trans, dest, old_bytenr, blocksize,
0, dest->root_key.objectid, level - 1,
0, 1);
BUG_ON(ret);
btrfs_unlock_up_safe(path, 0);
ret = level;
break;
}
btrfs_tree_unlock(parent);
free_extent_buffer(parent);
return ret;
}
/*
* helper to find next relocated block in reloc tree
*/
static noinline_for_stack
int walk_up_reloc_tree(struct btrfs_root *root, struct btrfs_path *path,
int *level)
{
struct extent_buffer *eb;
int i;
u64 last_snapshot;
u32 nritems;
last_snapshot = btrfs_root_last_snapshot(&root->root_item);
for (i = 0; i < *level; i++) {
free_extent_buffer(path->nodes[i]);
path->nodes[i] = NULL;
}
for (i = *level; i < BTRFS_MAX_LEVEL && path->nodes[i]; i++) {
eb = path->nodes[i];
nritems = btrfs_header_nritems(eb);
while (path->slots[i] + 1 < nritems) {
path->slots[i]++;
if (btrfs_node_ptr_generation(eb, path->slots[i]) <=
last_snapshot)
continue;
*level = i;
return 0;
}
free_extent_buffer(path->nodes[i]);
path->nodes[i] = NULL;
}
return 1;
}
/*
* walk down reloc tree to find relocated block of lowest level
*/
static noinline_for_stack
int walk_down_reloc_tree(struct btrfs_root *root, struct btrfs_path *path,
int *level)
{
struct extent_buffer *eb = NULL;
int i;
u64 bytenr;
u64 ptr_gen = 0;
u64 last_snapshot;
u32 blocksize;
u32 nritems;
last_snapshot = btrfs_root_last_snapshot(&root->root_item);
for (i = *level; i > 0; i--) {
eb = path->nodes[i];
nritems = btrfs_header_nritems(eb);
while (path->slots[i] < nritems) {
ptr_gen = btrfs_node_ptr_generation(eb, path->slots[i]);
if (ptr_gen > last_snapshot)
break;
path->slots[i]++;
}
if (path->slots[i] >= nritems) {
if (i == *level)
break;
*level = i + 1;
return 0;
}
if (i == 1) {
*level = i;
return 0;
}
bytenr = btrfs_node_blockptr(eb, path->slots[i]);
blocksize = btrfs_level_size(root, i - 1);
eb = read_tree_block(root, bytenr, blocksize, ptr_gen);
BUG_ON(btrfs_header_level(eb) != i - 1);
path->nodes[i - 1] = eb;
path->slots[i - 1] = 0;
}
return 1;
}
/*
* invalidate extent cache for file extents whose key in range of
* [min_key, max_key)
*/
static int invalidate_extent_cache(struct btrfs_root *root,
struct btrfs_key *min_key,
struct btrfs_key *max_key)
{
struct inode *inode = NULL;
u64 objectid;
u64 start, end;
u64 ino;
objectid = min_key->objectid;
while (1) {
cond_resched();
iput(inode);
if (objectid > max_key->objectid)
break;
inode = find_next_inode(root, objectid);
if (!inode)
break;
ino = btrfs_ino(inode);
if (ino > max_key->objectid) {
iput(inode);
break;
}
objectid = ino + 1;
if (!S_ISREG(inode->i_mode))
continue;
if (unlikely(min_key->objectid == ino)) {
if (min_key->type > BTRFS_EXTENT_DATA_KEY)
continue;
if (min_key->type < BTRFS_EXTENT_DATA_KEY)
start = 0;
else {
start = min_key->offset;
WARN_ON(!IS_ALIGNED(start, root->sectorsize));
}
} else {
start = 0;
}
if (unlikely(max_key->objectid == ino)) {
if (max_key->type < BTRFS_EXTENT_DATA_KEY)
continue;
if (max_key->type > BTRFS_EXTENT_DATA_KEY) {
end = (u64)-1;
} else {
if (max_key->offset == 0)
continue;
end = max_key->offset;
WARN_ON(!IS_ALIGNED(end, root->sectorsize));
end--;
}
} else {
end = (u64)-1;
}
/* the lock_extent waits for readpage to complete */
lock_extent(&BTRFS_I(inode)->io_tree, start, end);
btrfs_drop_extent_cache(inode, start, end, 1);
unlock_extent(&BTRFS_I(inode)->io_tree, start, end);
}
return 0;
}
static int find_next_key(struct btrfs_path *path, int level,
struct btrfs_key *key)
{
while (level < BTRFS_MAX_LEVEL) {
if (!path->nodes[level])
break;
if (path->slots[level] + 1 <
btrfs_header_nritems(path->nodes[level])) {
btrfs_node_key_to_cpu(path->nodes[level], key,
path->slots[level] + 1);
return 0;
}
level++;
}
return 1;
}
/*
* merge the relocated tree blocks in reloc tree with corresponding
* fs tree.
*/
static noinline_for_stack int merge_reloc_root(struct reloc_control *rc,
struct btrfs_root *root)
{
LIST_HEAD(inode_list);
struct btrfs_key key;
struct btrfs_key next_key;
struct btrfs_trans_handle *trans;
struct btrfs_root *reloc_root;
struct btrfs_root_item *root_item;
struct btrfs_path *path;
struct extent_buffer *leaf;
unsigned long nr;
int level;
int max_level;
int replaced = 0;
int ret;
int err = 0;
u32 min_reserved;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
path->reada = 1;
reloc_root = root->reloc_root;
root_item = &reloc_root->root_item;
if (btrfs_disk_key_objectid(&root_item->drop_progress) == 0) {
level = btrfs_root_level(root_item);
extent_buffer_get(reloc_root->node);
path->nodes[level] = reloc_root->node;
path->slots[level] = 0;
} else {
btrfs_disk_key_to_cpu(&key, &root_item->drop_progress);
level = root_item->drop_level;
BUG_ON(level == 0);
path->lowest_level = level;
ret = btrfs_search_slot(NULL, reloc_root, &key, path, 0, 0);
path->lowest_level = 0;
if (ret < 0) {
btrfs_free_path(path);
return ret;
}
btrfs_node_key_to_cpu(path->nodes[level], &next_key,
path->slots[level]);
WARN_ON(memcmp(&key, &next_key, sizeof(key)));
btrfs_unlock_up_safe(path, 0);
}
min_reserved = root->nodesize * (BTRFS_MAX_LEVEL - 1) * 2;
memset(&next_key, 0, sizeof(next_key));
while (1) {
trans = btrfs_start_transaction(root, 0);
BUG_ON(IS_ERR(trans));
trans->block_rsv = rc->block_rsv;
ret = btrfs_block_rsv_refill(root, rc->block_rsv, min_reserved);
if (ret) {
BUG_ON(ret != -EAGAIN);
ret = btrfs_commit_transaction(trans, root);
BUG_ON(ret);
continue;
}
replaced = 0;
max_level = level;
ret = walk_down_reloc_tree(reloc_root, path, &level);
if (ret < 0) {
err = ret;
goto out;
}
if (ret > 0)
break;
if (!find_next_key(path, level, &key) &&
btrfs_comp_cpu_keys(&next_key, &key) >= 0) {
ret = 0;
} else {
ret = replace_path(trans, root, reloc_root, path,
&next_key, level, max_level);
}
if (ret < 0) {
err = ret;
goto out;
}
if (ret > 0) {
level = ret;
btrfs_node_key_to_cpu(path->nodes[level], &key,
path->slots[level]);
replaced = 1;
}
ret = walk_up_reloc_tree(reloc_root, path, &level);
if (ret > 0)
break;
BUG_ON(level == 0);
/*
* save the merging progress in the drop_progress.
* this is OK since root refs == 1 in this case.
*/
btrfs_node_key(path->nodes[level], &root_item->drop_progress,
path->slots[level]);
root_item->drop_level = level;
nr = trans->blocks_used;
btrfs_end_transaction_throttle(trans, root);
btrfs_btree_balance_dirty(root, nr);
if (replaced && rc->stage == UPDATE_DATA_PTRS)
invalidate_extent_cache(root, &key, &next_key);
}
/*
* handle the case only one block in the fs tree need to be
* relocated and the block is tree root.
*/
leaf = btrfs_lock_root_node(root);
ret = btrfs_cow_block(trans, root, leaf, NULL, 0, &leaf);
btrfs_tree_unlock(leaf);
free_extent_buffer(leaf);
if (ret < 0)
err = ret;
out:
btrfs_free_path(path);
if (err == 0) {
memset(&root_item->drop_progress, 0,
sizeof(root_item->drop_progress));
root_item->drop_level = 0;
btrfs_set_root_refs(root_item, 0);
btrfs_update_reloc_root(trans, root);
}
nr = trans->blocks_used;
btrfs_end_transaction_throttle(trans, root);
btrfs_btree_balance_dirty(root, nr);
if (replaced && rc->stage == UPDATE_DATA_PTRS)
invalidate_extent_cache(root, &key, &next_key);
return err;
}
static noinline_for_stack
int prepare_to_merge(struct reloc_control *rc, int err)
{
struct btrfs_root *root = rc->extent_root;
struct btrfs_root *reloc_root;
struct btrfs_trans_handle *trans;
LIST_HEAD(reloc_roots);
u64 num_bytes = 0;
int ret;
mutex_lock(&root->fs_info->reloc_mutex);
rc->merging_rsv_size += root->nodesize * (BTRFS_MAX_LEVEL - 1) * 2;
rc->merging_rsv_size += rc->nodes_relocated * 2;
mutex_unlock(&root->fs_info->reloc_mutex);
again:
if (!err) {
num_bytes = rc->merging_rsv_size;
ret = btrfs_block_rsv_add(root, rc->block_rsv, num_bytes);
if (ret)
err = ret;
}
trans = btrfs_join_transaction(rc->extent_root);
if (IS_ERR(trans)) {
if (!err)
btrfs_block_rsv_release(rc->extent_root,
rc->block_rsv, num_bytes);
return PTR_ERR(trans);
}
if (!err) {
if (num_bytes != rc->merging_rsv_size) {
btrfs_end_transaction(trans, rc->extent_root);
btrfs_block_rsv_release(rc->extent_root,
rc->block_rsv, num_bytes);
goto again;
}
}
rc->merge_reloc_tree = 1;
while (!list_empty(&rc->reloc_roots)) {
reloc_root = list_entry(rc->reloc_roots.next,
struct btrfs_root, root_list);
list_del_init(&reloc_root->root_list);
root = read_fs_root(reloc_root->fs_info,
reloc_root->root_key.offset);
BUG_ON(IS_ERR(root));
BUG_ON(root->reloc_root != reloc_root);
/*
* set reference count to 1, so btrfs_recover_relocation
* knows it should resumes merging
*/
if (!err)
btrfs_set_root_refs(&reloc_root->root_item, 1);
btrfs_update_reloc_root(trans, root);
list_add(&reloc_root->root_list, &reloc_roots);
}
list_splice(&reloc_roots, &rc->reloc_roots);
if (!err)
btrfs_commit_transaction(trans, rc->extent_root);
else
btrfs_end_transaction(trans, rc->extent_root);
return err;
}
static noinline_for_stack
int merge_reloc_roots(struct reloc_control *rc)
{
struct btrfs_root *root;
struct btrfs_root *reloc_root;
LIST_HEAD(reloc_roots);
int found = 0;
int ret;
again:
root = rc->extent_root;
/*
* this serializes us with btrfs_record_root_in_transaction,
* we have to make sure nobody is in the middle of
* adding their roots to the list while we are
* doing this splice
*/
mutex_lock(&root->fs_info->reloc_mutex);
list_splice_init(&rc->reloc_roots, &reloc_roots);
mutex_unlock(&root->fs_info->reloc_mutex);
while (!list_empty(&reloc_roots)) {
found = 1;
reloc_root = list_entry(reloc_roots.next,
struct btrfs_root, root_list);
if (btrfs_root_refs(&reloc_root->root_item) > 0) {
root = read_fs_root(reloc_root->fs_info,
reloc_root->root_key.offset);
BUG_ON(IS_ERR(root));
BUG_ON(root->reloc_root != reloc_root);
ret = merge_reloc_root(rc, root);
BUG_ON(ret);
} else {
list_del_init(&reloc_root->root_list);
}
ret = btrfs_drop_snapshot(reloc_root, rc->block_rsv, 0, 1);
BUG_ON(ret < 0);
}
if (found) {
found = 0;
goto again;
}
BUG_ON(!RB_EMPTY_ROOT(&rc->reloc_root_tree.rb_root));
return 0;
}
static void free_block_list(struct rb_root *blocks)
{
struct tree_block *block;
struct rb_node *rb_node;
while ((rb_node = rb_first(blocks))) {
block = rb_entry(rb_node, struct tree_block, rb_node);
rb_erase(rb_node, blocks);
kfree(block);
}
}
static int record_reloc_root_in_trans(struct btrfs_trans_handle *trans,
struct btrfs_root *reloc_root)
{
struct btrfs_root *root;
if (reloc_root->last_trans == trans->transid)
return 0;
root = read_fs_root(reloc_root->fs_info, reloc_root->root_key.offset);
BUG_ON(IS_ERR(root));
BUG_ON(root->reloc_root != reloc_root);
return btrfs_record_root_in_trans(trans, root);
}
static noinline_for_stack
struct btrfs_root *select_reloc_root(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct backref_node *node,
struct backref_edge *edges[], int *nr)
{
struct backref_node *next;
struct btrfs_root *root;
int index = 0;
next = node;
while (1) {
cond_resched();
next = walk_up_backref(next, edges, &index);
root = next->root;
BUG_ON(!root);
BUG_ON(!root->ref_cows);
if (root->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID) {
record_reloc_root_in_trans(trans, root);
break;
}
btrfs_record_root_in_trans(trans, root);
root = root->reloc_root;
if (next->new_bytenr != root->node->start) {
BUG_ON(next->new_bytenr);
BUG_ON(!list_empty(&next->list));
next->new_bytenr = root->node->start;
next->root = root;
list_add_tail(&next->list,
&rc->backref_cache.changed);
__mark_block_processed(rc, next);
break;
}
WARN_ON(1);
root = NULL;
next = walk_down_backref(edges, &index);
if (!next || next->level <= node->level)
break;
}
if (!root)
return NULL;
*nr = index;
next = node;
/* setup backref node path for btrfs_reloc_cow_block */
while (1) {
rc->backref_cache.path[next->level] = next;
if (--index < 0)
break;
next = edges[index]->node[UPPER];
}
return root;
}
/*
* select a tree root for relocation. return NULL if the block
* is reference counted. we should use do_relocation() in this
* case. return a tree root pointer if the block isn't reference
* counted. return -ENOENT if the block is root of reloc tree.
*/
static noinline_for_stack
struct btrfs_root *select_one_root(struct btrfs_trans_handle *trans,
struct backref_node *node)
{
struct backref_node *next;
struct btrfs_root *root;
struct btrfs_root *fs_root = NULL;
struct backref_edge *edges[BTRFS_MAX_LEVEL - 1];
int index = 0;
next = node;
while (1) {
cond_resched();
next = walk_up_backref(next, edges, &index);
root = next->root;
BUG_ON(!root);
/* no other choice for non-references counted tree */
if (!root->ref_cows)
return root;
if (root->root_key.objectid != BTRFS_TREE_RELOC_OBJECTID)
fs_root = root;
if (next != node)
return NULL;
next = walk_down_backref(edges, &index);
if (!next || next->level <= node->level)
break;
}
if (!fs_root)
return ERR_PTR(-ENOENT);
return fs_root;
}
static noinline_for_stack
u64 calcu_metadata_size(struct reloc_control *rc,
struct backref_node *node, int reserve)
{
struct backref_node *next = node;
struct backref_edge *edge;
struct backref_edge *edges[BTRFS_MAX_LEVEL - 1];
u64 num_bytes = 0;
int index = 0;
BUG_ON(reserve && node->processed);
while (next) {
cond_resched();
while (1) {
if (next->processed && (reserve || next != node))
break;
num_bytes += btrfs_level_size(rc->extent_root,
next->level);
if (list_empty(&next->upper))
break;
edge = list_entry(next->upper.next,
struct backref_edge, list[LOWER]);
edges[index++] = edge;
next = edge->node[UPPER];
}
next = walk_down_backref(edges, &index);
}
return num_bytes;
}
static int reserve_metadata_space(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct backref_node *node)
{
struct btrfs_root *root = rc->extent_root;
u64 num_bytes;
int ret;
num_bytes = calcu_metadata_size(rc, node, 1) * 2;
trans->block_rsv = rc->block_rsv;
ret = btrfs_block_rsv_add(root, rc->block_rsv, num_bytes);
if (ret) {
if (ret == -EAGAIN)
rc->commit_transaction = 1;
return ret;
}
return 0;
}
static void release_metadata_space(struct reloc_control *rc,
struct backref_node *node)
{
u64 num_bytes = calcu_metadata_size(rc, node, 0) * 2;
btrfs_block_rsv_release(rc->extent_root, rc->block_rsv, num_bytes);
}
/*
* relocate a block tree, and then update pointers in upper level
* blocks that reference the block to point to the new location.
*
* if called by link_to_upper, the block has already been relocated.
* in that case this function just updates pointers.
*/
static int do_relocation(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct backref_node *node,
struct btrfs_key *key,
struct btrfs_path *path, int lowest)
{
struct backref_node *upper;
struct backref_edge *edge;
struct backref_edge *edges[BTRFS_MAX_LEVEL - 1];
struct btrfs_root *root;
struct extent_buffer *eb;
u32 blocksize;
u64 bytenr;
u64 generation;
int nr;
int slot;
int ret;
int err = 0;
BUG_ON(lowest && node->eb);
path->lowest_level = node->level + 1;
rc->backref_cache.path[node->level] = node;
list_for_each_entry(edge, &node->upper, list[LOWER]) {
cond_resched();
upper = edge->node[UPPER];
root = select_reloc_root(trans, rc, upper, edges, &nr);
BUG_ON(!root);
if (upper->eb && !upper->locked) {
if (!lowest) {
ret = btrfs_bin_search(upper->eb, key,
upper->level, &slot);
BUG_ON(ret);
bytenr = btrfs_node_blockptr(upper->eb, slot);
if (node->eb->start == bytenr)
goto next;
}
drop_node_buffer(upper);
}
if (!upper->eb) {
ret = btrfs_search_slot(trans, root, key, path, 0, 1);
if (ret < 0) {
err = ret;
break;
}
BUG_ON(ret > 0);
if (!upper->eb) {
upper->eb = path->nodes[upper->level];
path->nodes[upper->level] = NULL;
} else {
BUG_ON(upper->eb != path->nodes[upper->level]);
}
upper->locked = 1;
path->locks[upper->level] = 0;
slot = path->slots[upper->level];
btrfs_release_path(path);
} else {
ret = btrfs_bin_search(upper->eb, key, upper->level,
&slot);
BUG_ON(ret);
}
bytenr = btrfs_node_blockptr(upper->eb, slot);
if (lowest) {
BUG_ON(bytenr != node->bytenr);
} else {
if (node->eb->start == bytenr)
goto next;
}
blocksize = btrfs_level_size(root, node->level);
generation = btrfs_node_ptr_generation(upper->eb, slot);
eb = read_tree_block(root, bytenr, blocksize, generation);
if (!eb) {
err = -EIO;
goto next;
}
btrfs_tree_lock(eb);
btrfs_set_lock_blocking(eb);
if (!node->eb) {
ret = btrfs_cow_block(trans, root, eb, upper->eb,
slot, &eb);
btrfs_tree_unlock(eb);
free_extent_buffer(eb);
if (ret < 0) {
err = ret;
goto next;
}
BUG_ON(node->eb != eb);
} else {
btrfs_set_node_blockptr(upper->eb, slot,
node->eb->start);
btrfs_set_node_ptr_generation(upper->eb, slot,
trans->transid);
btrfs_mark_buffer_dirty(upper->eb);
ret = btrfs_inc_extent_ref(trans, root,
node->eb->start, blocksize,
upper->eb->start,
btrfs_header_owner(upper->eb),
node->level, 0, 1);
BUG_ON(ret);
ret = btrfs_drop_subtree(trans, root, eb, upper->eb);
BUG_ON(ret);
}
next:
if (!upper->pending)
drop_node_buffer(upper);
else
unlock_node_buffer(upper);
if (err)
break;
}
if (!err && node->pending) {
drop_node_buffer(node);
list_move_tail(&node->list, &rc->backref_cache.changed);
node->pending = 0;
}
path->lowest_level = 0;
BUG_ON(err == -ENOSPC);
return err;
}
static int link_to_upper(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct backref_node *node,
struct btrfs_path *path)
{
struct btrfs_key key;
btrfs_node_key_to_cpu(node->eb, &key, 0);
return do_relocation(trans, rc, node, &key, path, 0);
}
static int finish_pending_nodes(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct btrfs_path *path, int err)
{
LIST_HEAD(list);
struct backref_cache *cache = &rc->backref_cache;
struct backref_node *node;
int level;
int ret;
for (level = 0; level < BTRFS_MAX_LEVEL; level++) {
while (!list_empty(&cache->pending[level])) {
node = list_entry(cache->pending[level].next,
struct backref_node, list);
list_move_tail(&node->list, &list);
BUG_ON(!node->pending);
if (!err) {
ret = link_to_upper(trans, rc, node, path);
if (ret < 0)
err = ret;
}
}
list_splice_init(&list, &cache->pending[level]);
}
return err;
}
static void mark_block_processed(struct reloc_control *rc,
u64 bytenr, u32 blocksize)
{
set_extent_bits(&rc->processed_blocks, bytenr, bytenr + blocksize - 1,
EXTENT_DIRTY, GFP_NOFS);
}
static void __mark_block_processed(struct reloc_control *rc,
struct backref_node *node)
{
u32 blocksize;
if (node->level == 0 ||
in_block_group(node->bytenr, rc->block_group)) {
blocksize = btrfs_level_size(rc->extent_root, node->level);
mark_block_processed(rc, node->bytenr, blocksize);
}
node->processed = 1;
}
/*
* mark a block and all blocks directly/indirectly reference the block
* as processed.
*/
static void update_processed_blocks(struct reloc_control *rc,
struct backref_node *node)
{
struct backref_node *next = node;
struct backref_edge *edge;
struct backref_edge *edges[BTRFS_MAX_LEVEL - 1];
int index = 0;
while (next) {
cond_resched();
while (1) {
if (next->processed)
break;
__mark_block_processed(rc, next);
if (list_empty(&next->upper))
break;
edge = list_entry(next->upper.next,
struct backref_edge, list[LOWER]);
edges[index++] = edge;
next = edge->node[UPPER];
}
next = walk_down_backref(edges, &index);
}
}
static int tree_block_processed(u64 bytenr, u32 blocksize,
struct reloc_control *rc)
{
if (test_range_bit(&rc->processed_blocks, bytenr,
bytenr + blocksize - 1, EXTENT_DIRTY, 1, NULL))
return 1;
return 0;
}
static int get_tree_block_key(struct reloc_control *rc,
struct tree_block *block)
{
struct extent_buffer *eb;
BUG_ON(block->key_ready);
eb = read_tree_block(rc->extent_root, block->bytenr,
block->key.objectid, block->key.offset);
BUG_ON(!eb);
WARN_ON(btrfs_header_level(eb) != block->level);
if (block->level == 0)
btrfs_item_key_to_cpu(eb, &block->key, 0);
else
btrfs_node_key_to_cpu(eb, &block->key, 0);
free_extent_buffer(eb);
block->key_ready = 1;
return 0;
}
static int reada_tree_block(struct reloc_control *rc,
struct tree_block *block)
{
BUG_ON(block->key_ready);
readahead_tree_block(rc->extent_root, block->bytenr,
block->key.objectid, block->key.offset);
return 0;
}
/*
* helper function to relocate a tree block
*/
static int relocate_tree_block(struct btrfs_trans_handle *trans,
struct reloc_control *rc,
struct backref_node *node,
struct btrfs_key *key,
struct btrfs_path *path)
{
struct btrfs_root *root;
int release = 0;
int ret = 0;
if (!node)
return 0;
BUG_ON(node->processed);
root = select_one_root(trans, node);
if (root == ERR_PTR(-ENOENT)) {
update_processed_blocks(rc, node);
goto out;
}
if (!root || root->ref_cows) {
ret = reserve_metadata_space(trans, rc, node);
if (ret)
goto out;
release = 1;
}
if (root) {
if (root->ref_cows) {
BUG_ON(node->new_bytenr);
BUG_ON(!list_empty(&node->list));
btrfs_record_root_in_trans(trans, root);
root = root->reloc_root;
node->new_bytenr = root->node->start;
node->root = root;
list_add_tail(&node->list, &rc->backref_cache.changed);
} else {
path->lowest_level = node->level;
ret = btrfs_search_slot(trans, root, key, path, 0, 1);
btrfs_release_path(path);
if (ret > 0)
ret = 0;
}
if (!ret)
update_processed_blocks(rc, node);
} else {
ret = do_relocation(trans, rc, node, key, path, 1);
}
out:
if (ret || node->level == 0 || node->cowonly) {
if (release)
release_metadata_space(rc, node);
remove_backref_node(&rc->backref_cache, node);
}
return ret;
}
/*
* relocate a list of blocks
*/
static noinline_for_stack
int relocate_tree_blocks(struct btrfs_trans_handle *trans,
struct reloc_control *rc, struct rb_root *blocks)
{
struct backref_node *node;
struct btrfs_path *path;
struct tree_block *block;
struct rb_node *rb_node;
int ret;
int err = 0;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
rb_node = rb_first(blocks);
while (rb_node) {
block = rb_entry(rb_node, struct tree_block, rb_node);
if (!block->key_ready)
reada_tree_block(rc, block);
rb_node = rb_next(rb_node);
}
rb_node = rb_first(blocks);
while (rb_node) {
block = rb_entry(rb_node, struct tree_block, rb_node);
if (!block->key_ready)
get_tree_block_key(rc, block);
rb_node = rb_next(rb_node);
}
rb_node = rb_first(blocks);
while (rb_node) {
block = rb_entry(rb_node, struct tree_block, rb_node);
node = build_backref_tree(rc, &block->key,
block->level, block->bytenr);
if (IS_ERR(node)) {
err = PTR_ERR(node);
goto out;
}
ret = relocate_tree_block(trans, rc, node, &block->key,
path);
if (ret < 0) {
if (ret != -EAGAIN || rb_node == rb_first(blocks))
err = ret;
goto out;
}
rb_node = rb_next(rb_node);
}
out:
free_block_list(blocks);
err = finish_pending_nodes(trans, rc, path, err);
btrfs_free_path(path);
return err;
}
static noinline_for_stack
int prealloc_file_extent_cluster(struct inode *inode,
struct file_extent_cluster *cluster)
{
u64 alloc_hint = 0;
u64 start;
u64 end;
u64 offset = BTRFS_I(inode)->index_cnt;
u64 num_bytes;
int nr = 0;
int ret = 0;
BUG_ON(cluster->start != cluster->boundary[0]);
mutex_lock(&inode->i_mutex);
ret = btrfs_check_data_free_space(inode, cluster->end +
1 - cluster->start);
if (ret)
goto out;
while (nr < cluster->nr) {
start = cluster->boundary[nr] - offset;
if (nr + 1 < cluster->nr)
end = cluster->boundary[nr + 1] - 1 - offset;
else
end = cluster->end - offset;
lock_extent(&BTRFS_I(inode)->io_tree, start, end);
num_bytes = end + 1 - start;
ret = btrfs_prealloc_file_range(inode, 0, start,
num_bytes, num_bytes,
end + 1, &alloc_hint);
unlock_extent(&BTRFS_I(inode)->io_tree, start, end);
if (ret)
break;
nr++;
}
btrfs_free_reserved_data_space(inode, cluster->end +
1 - cluster->start);
out:
mutex_unlock(&inode->i_mutex);
return ret;
}
static noinline_for_stack
int setup_extent_mapping(struct inode *inode, u64 start, u64 end,
u64 block_start)
{
struct btrfs_root *root = BTRFS_I(inode)->root;
struct extent_map_tree *em_tree = &BTRFS_I(inode)->extent_tree;
struct extent_map *em;
int ret = 0;
em = alloc_extent_map();
if (!em)
return -ENOMEM;
em->start = start;
em->len = end + 1 - start;
em->block_len = em->len;
em->block_start = block_start;
em->bdev = root->fs_info->fs_devices->latest_bdev;
set_bit(EXTENT_FLAG_PINNED, &em->flags);
lock_extent(&BTRFS_I(inode)->io_tree, start, end);
while (1) {
write_lock(&em_tree->lock);
ret = add_extent_mapping(em_tree, em);
write_unlock(&em_tree->lock);
if (ret != -EEXIST) {
free_extent_map(em);
break;
}
btrfs_drop_extent_cache(inode, start, end, 0);
}
unlock_extent(&BTRFS_I(inode)->io_tree, start, end);
return ret;
}
static int relocate_file_extent_cluster(struct inode *inode,
struct file_extent_cluster *cluster)
{
u64 page_start;
u64 page_end;
u64 offset = BTRFS_I(inode)->index_cnt;
unsigned long index;
unsigned long last_index;
struct page *page;
struct file_ra_state *ra;
gfp_t mask = btrfs_alloc_write_mask(inode->i_mapping);
int nr = 0;
int ret = 0;
if (!cluster->nr)
return 0;
ra = kzalloc(sizeof(*ra), GFP_NOFS);
if (!ra)
return -ENOMEM;
ret = prealloc_file_extent_cluster(inode, cluster);
if (ret)
goto out;
file_ra_state_init(ra, inode->i_mapping);
ret = setup_extent_mapping(inode, cluster->start - offset,
cluster->end - offset, cluster->start);
if (ret)
goto out;
index = (cluster->start - offset) >> PAGE_CACHE_SHIFT;
last_index = (cluster->end - offset) >> PAGE_CACHE_SHIFT;
while (index <= last_index) {
ret = btrfs_delalloc_reserve_metadata(inode, PAGE_CACHE_SIZE);
if (ret)
goto out;
page = find_lock_page(inode->i_mapping, index);
if (!page) {
page_cache_sync_readahead(inode->i_mapping,
ra, NULL, index,
last_index + 1 - index);
page = find_or_create_page(inode->i_mapping, index,
mask);
if (!page) {
btrfs_delalloc_release_metadata(inode,
PAGE_CACHE_SIZE);
ret = -ENOMEM;
goto out;
}
}
if (PageReadahead(page)) {
page_cache_async_readahead(inode->i_mapping,
ra, NULL, page, index,
last_index + 1 - index);
}
if (!PageUptodate(page)) {
btrfs_readpage(NULL, page);
lock_page(page);
if (!PageUptodate(page)) {
unlock_page(page);
page_cache_release(page);
btrfs_delalloc_release_metadata(inode,
PAGE_CACHE_SIZE);
ret = -EIO;
goto out;
}
}
page_start = (u64)page->index << PAGE_CACHE_SHIFT;
page_end = page_start + PAGE_CACHE_SIZE - 1;
lock_extent(&BTRFS_I(inode)->io_tree, page_start, page_end);
set_page_extent_mapped(page);
if (nr < cluster->nr &&
page_start + offset == cluster->boundary[nr]) {
set_extent_bits(&BTRFS_I(inode)->io_tree,
page_start, page_end,
EXTENT_BOUNDARY, GFP_NOFS);
nr++;
}
btrfs_set_extent_delalloc(inode, page_start, page_end, NULL);
set_page_dirty(page);
unlock_extent(&BTRFS_I(inode)->io_tree,
page_start, page_end);
unlock_page(page);
page_cache_release(page);
index++;
balance_dirty_pages_ratelimited(inode->i_mapping);
btrfs_throttle(BTRFS_I(inode)->root);
}
WARN_ON(nr != cluster->nr);
out:
kfree(ra);
return ret;
}
static noinline_for_stack
int relocate_data_extent(struct inode *inode, struct btrfs_key *extent_key,
struct file_extent_cluster *cluster)
{
int ret;
if (cluster->nr > 0 && extent_key->objectid != cluster->end + 1) {
ret = relocate_file_extent_cluster(inode, cluster);
if (ret)
return ret;
cluster->nr = 0;
}
if (!cluster->nr)
cluster->start = extent_key->objectid;
else
BUG_ON(cluster->nr >= MAX_EXTENTS);
cluster->end = extent_key->objectid + extent_key->offset - 1;
cluster->boundary[cluster->nr] = extent_key->objectid;
cluster->nr++;
if (cluster->nr >= MAX_EXTENTS) {
ret = relocate_file_extent_cluster(inode, cluster);
if (ret)
return ret;
cluster->nr = 0;
}
return 0;
}
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
static int get_ref_objectid_v0(struct reloc_control *rc,
struct btrfs_path *path,
struct btrfs_key *extent_key,
u64 *ref_objectid, int *path_change)
{
struct btrfs_key key;
struct extent_buffer *leaf;
struct btrfs_extent_ref_v0 *ref0;
int ret;
int slot;
leaf = path->nodes[0];
slot = path->slots[0];
while (1) {
if (slot >= btrfs_header_nritems(leaf)) {
ret = btrfs_next_leaf(rc->extent_root, path);
if (ret < 0)
return ret;
BUG_ON(ret > 0);
leaf = path->nodes[0];
slot = path->slots[0];
if (path_change)
*path_change = 1;
}
btrfs_item_key_to_cpu(leaf, &key, slot);
if (key.objectid != extent_key->objectid)
return -ENOENT;
if (key.type != BTRFS_EXTENT_REF_V0_KEY) {
slot++;
continue;
}
ref0 = btrfs_item_ptr(leaf, slot,
struct btrfs_extent_ref_v0);
*ref_objectid = btrfs_ref_objectid_v0(leaf, ref0);
break;
}
return 0;
}
#endif
/*
* helper to add a tree block to the list.
* the major work is getting the generation and level of the block
*/
static int add_tree_block(struct reloc_control *rc,
struct btrfs_key *extent_key,
struct btrfs_path *path,
struct rb_root *blocks)
{
struct extent_buffer *eb;
struct btrfs_extent_item *ei;
struct btrfs_tree_block_info *bi;
struct tree_block *block;
struct rb_node *rb_node;
u32 item_size;
int level = -1;
int generation;
eb = path->nodes[0];
item_size = btrfs_item_size_nr(eb, path->slots[0]);
if (item_size >= sizeof(*ei) + sizeof(*bi)) {
ei = btrfs_item_ptr(eb, path->slots[0],
struct btrfs_extent_item);
bi = (struct btrfs_tree_block_info *)(ei + 1);
generation = btrfs_extent_generation(eb, ei);
level = btrfs_tree_block_level(eb, bi);
} else {
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
u64 ref_owner;
int ret;
BUG_ON(item_size != sizeof(struct btrfs_extent_item_v0));
ret = get_ref_objectid_v0(rc, path, extent_key,
&ref_owner, NULL);
if (ret < 0)
return ret;
BUG_ON(ref_owner >= BTRFS_MAX_LEVEL);
level = (int)ref_owner;
/* FIXME: get real generation */
generation = 0;
#else
BUG();
#endif
}
btrfs_release_path(path);
BUG_ON(level == -1);
block = kmalloc(sizeof(*block), GFP_NOFS);
if (!block)
return -ENOMEM;
block->bytenr = extent_key->objectid;
block->key.objectid = extent_key->offset;
block->key.offset = generation;
block->level = level;
block->key_ready = 0;
rb_node = tree_insert(blocks, block->bytenr, &block->rb_node);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST, block->bytenr);
return 0;
}
/*
* helper to add tree blocks for backref of type BTRFS_SHARED_DATA_REF_KEY
*/
static int __add_tree_block(struct reloc_control *rc,
u64 bytenr, u32 blocksize,
struct rb_root *blocks)
{
struct btrfs_path *path;
struct btrfs_key key;
int ret;
if (tree_block_processed(bytenr, blocksize, rc))
return 0;
if (tree_search(blocks, bytenr))
return 0;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
key.objectid = bytenr;
key.type = BTRFS_EXTENT_ITEM_KEY;
key.offset = blocksize;
path->search_commit_root = 1;
path->skip_locking = 1;
ret = btrfs_search_slot(NULL, rc->extent_root, &key, path, 0, 0);
if (ret < 0)
goto out;
BUG_ON(ret);
btrfs_item_key_to_cpu(path->nodes[0], &key, path->slots[0]);
ret = add_tree_block(rc, &key, path, blocks);
out:
btrfs_free_path(path);
return ret;
}
/*
* helper to check if the block use full backrefs for pointers in it
*/
static int block_use_full_backref(struct reloc_control *rc,
struct extent_buffer *eb)
{
u64 flags;
int ret;
if (btrfs_header_flag(eb, BTRFS_HEADER_FLAG_RELOC) ||
btrfs_header_backref_rev(eb) < BTRFS_MIXED_BACKREF_REV)
return 1;
ret = btrfs_lookup_extent_info(NULL, rc->extent_root,
eb->start, eb->len, NULL, &flags);
BUG_ON(ret);
if (flags & BTRFS_BLOCK_FLAG_FULL_BACKREF)
ret = 1;
else
ret = 0;
return ret;
}
static int delete_block_group_cache(struct btrfs_fs_info *fs_info,
struct inode *inode, u64 ino)
{
struct btrfs_key key;
struct btrfs_path *path;
struct btrfs_root *root = fs_info->tree_root;
struct btrfs_trans_handle *trans;
unsigned long nr;
int ret = 0;
if (inode)
goto truncate;
key.objectid = ino;
key.type = BTRFS_INODE_ITEM_KEY;
key.offset = 0;
inode = btrfs_iget(fs_info->sb, &key, root, NULL);
if (IS_ERR_OR_NULL(inode) || is_bad_inode(inode)) {
if (inode && !IS_ERR(inode))
iput(inode);
return -ENOENT;
}
truncate:
path = btrfs_alloc_path();
if (!path) {
ret = -ENOMEM;
goto out;
}
trans = btrfs_join_transaction(root);
if (IS_ERR(trans)) {
btrfs_free_path(path);
ret = PTR_ERR(trans);
goto out;
}
ret = btrfs_truncate_free_space_cache(root, trans, path, inode);
btrfs_free_path(path);
nr = trans->blocks_used;
btrfs_end_transaction(trans, root);
btrfs_btree_balance_dirty(root, nr);
out:
iput(inode);
return ret;
}
/*
* helper to add tree blocks for backref of type BTRFS_EXTENT_DATA_REF_KEY
* this function scans fs tree to find blocks reference the data extent
*/
static int find_data_references(struct reloc_control *rc,
struct btrfs_key *extent_key,
struct extent_buffer *leaf,
struct btrfs_extent_data_ref *ref,
struct rb_root *blocks)
{
struct btrfs_path *path;
struct tree_block *block;
struct btrfs_root *root;
struct btrfs_file_extent_item *fi;
struct rb_node *rb_node;
struct btrfs_key key;
u64 ref_root;
u64 ref_objectid;
u64 ref_offset;
u32 ref_count;
u32 nritems;
int err = 0;
int added = 0;
int counted;
int ret;
ref_root = btrfs_extent_data_ref_root(leaf, ref);
ref_objectid = btrfs_extent_data_ref_objectid(leaf, ref);
ref_offset = btrfs_extent_data_ref_offset(leaf, ref);
ref_count = btrfs_extent_data_ref_count(leaf, ref);
/*
* This is an extent belonging to the free space cache, lets just delete
* it and redo the search.
*/
if (ref_root == BTRFS_ROOT_TREE_OBJECTID) {
ret = delete_block_group_cache(rc->extent_root->fs_info,
NULL, ref_objectid);
if (ret != -ENOENT)
return ret;
ret = 0;
}
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
path->reada = 1;
root = read_fs_root(rc->extent_root->fs_info, ref_root);
if (IS_ERR(root)) {
err = PTR_ERR(root);
goto out;
}
key.objectid = ref_objectid;
key.type = BTRFS_EXTENT_DATA_KEY;
if (ref_offset > ((u64)-1 << 32))
key.offset = 0;
else
key.offset = ref_offset;
path->search_commit_root = 1;
path->skip_locking = 1;
ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
if (ret < 0) {
err = ret;
goto out;
}
leaf = path->nodes[0];
nritems = btrfs_header_nritems(leaf);
/*
* the references in tree blocks that use full backrefs
* are not counted in
*/
if (block_use_full_backref(rc, leaf))
counted = 0;
else
counted = 1;
rb_node = tree_search(blocks, leaf->start);
if (rb_node) {
if (counted)
added = 1;
else
path->slots[0] = nritems;
}
while (ref_count > 0) {
while (path->slots[0] >= nritems) {
ret = btrfs_next_leaf(root, path);
if (ret < 0) {
err = ret;
goto out;
}
if (ret > 0) {
WARN_ON(1);
goto out;
}
leaf = path->nodes[0];
nritems = btrfs_header_nritems(leaf);
added = 0;
if (block_use_full_backref(rc, leaf))
counted = 0;
else
counted = 1;
rb_node = tree_search(blocks, leaf->start);
if (rb_node) {
if (counted)
added = 1;
else
path->slots[0] = nritems;
}
}
btrfs_item_key_to_cpu(leaf, &key, path->slots[0]);
if (key.objectid != ref_objectid ||
key.type != BTRFS_EXTENT_DATA_KEY) {
WARN_ON(1);
break;
}
fi = btrfs_item_ptr(leaf, path->slots[0],
struct btrfs_file_extent_item);
if (btrfs_file_extent_type(leaf, fi) ==
BTRFS_FILE_EXTENT_INLINE)
goto next;
if (btrfs_file_extent_disk_bytenr(leaf, fi) !=
extent_key->objectid)
goto next;
key.offset -= btrfs_file_extent_offset(leaf, fi);
if (key.offset != ref_offset)
goto next;
if (counted)
ref_count--;
if (added)
goto next;
if (!tree_block_processed(leaf->start, leaf->len, rc)) {
block = kmalloc(sizeof(*block), GFP_NOFS);
if (!block) {
err = -ENOMEM;
break;
}
block->bytenr = leaf->start;
btrfs_item_key_to_cpu(leaf, &block->key, 0);
block->level = 0;
block->key_ready = 1;
rb_node = tree_insert(blocks, block->bytenr,
&block->rb_node);
if (rb_node)
backref_tree_panic(rb_node, -EEXIST,
block->bytenr);
}
if (counted)
added = 1;
else
path->slots[0] = nritems;
next:
path->slots[0]++;
}
out:
btrfs_free_path(path);
return err;
}
/*
* hepler to find all tree blocks that reference a given data extent
*/
static noinline_for_stack
int add_data_references(struct reloc_control *rc,
struct btrfs_key *extent_key,
struct btrfs_path *path,
struct rb_root *blocks)
{
struct btrfs_key key;
struct extent_buffer *eb;
struct btrfs_extent_data_ref *dref;
struct btrfs_extent_inline_ref *iref;
unsigned long ptr;
unsigned long end;
u32 blocksize = btrfs_level_size(rc->extent_root, 0);
int ret;
int err = 0;
eb = path->nodes[0];
ptr = btrfs_item_ptr_offset(eb, path->slots[0]);
end = ptr + btrfs_item_size_nr(eb, path->slots[0]);
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
if (ptr + sizeof(struct btrfs_extent_item_v0) == end)
ptr = end;
else
#endif
ptr += sizeof(struct btrfs_extent_item);
while (ptr < end) {
iref = (struct btrfs_extent_inline_ref *)ptr;
key.type = btrfs_extent_inline_ref_type(eb, iref);
if (key.type == BTRFS_SHARED_DATA_REF_KEY) {
key.offset = btrfs_extent_inline_ref_offset(eb, iref);
ret = __add_tree_block(rc, key.offset, blocksize,
blocks);
} else if (key.type == BTRFS_EXTENT_DATA_REF_KEY) {
dref = (struct btrfs_extent_data_ref *)(&iref->offset);
ret = find_data_references(rc, extent_key,
eb, dref, blocks);
} else {
BUG();
}
ptr += btrfs_extent_inline_ref_size(key.type);
}
WARN_ON(ptr > end);
while (1) {
cond_resched();
eb = path->nodes[0];
if (path->slots[0] >= btrfs_header_nritems(eb)) {
ret = btrfs_next_leaf(rc->extent_root, path);
if (ret < 0) {
err = ret;
break;
}
if (ret > 0)
break;
eb = path->nodes[0];
}
btrfs_item_key_to_cpu(eb, &key, path->slots[0]);
if (key.objectid != extent_key->objectid)
break;
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
if (key.type == BTRFS_SHARED_DATA_REF_KEY ||
key.type == BTRFS_EXTENT_REF_V0_KEY) {
#else
BUG_ON(key.type == BTRFS_EXTENT_REF_V0_KEY);
if (key.type == BTRFS_SHARED_DATA_REF_KEY) {
#endif
ret = __add_tree_block(rc, key.offset, blocksize,
blocks);
} else if (key.type == BTRFS_EXTENT_DATA_REF_KEY) {
dref = btrfs_item_ptr(eb, path->slots[0],
struct btrfs_extent_data_ref);
ret = find_data_references(rc, extent_key,
eb, dref, blocks);
} else {
ret = 0;
}
if (ret) {
err = ret;
break;
}
path->slots[0]++;
}
btrfs_release_path(path);
if (err)
free_block_list(blocks);
return err;
}
/*
* hepler to find next unprocessed extent
*/
static noinline_for_stack
int find_next_extent(struct btrfs_trans_handle *trans,
struct reloc_control *rc, struct btrfs_path *path,
struct btrfs_key *extent_key)
{
struct btrfs_key key;
struct extent_buffer *leaf;
u64 start, end, last;
int ret;
last = rc->block_group->key.objectid + rc->block_group->key.offset;
while (1) {
cond_resched();
if (rc->search_start >= last) {
ret = 1;
break;
}
key.objectid = rc->search_start;
key.type = BTRFS_EXTENT_ITEM_KEY;
key.offset = 0;
path->search_commit_root = 1;
path->skip_locking = 1;
ret = btrfs_search_slot(NULL, rc->extent_root, &key, path,
0, 0);
if (ret < 0)
break;
next:
leaf = path->nodes[0];
if (path->slots[0] >= btrfs_header_nritems(leaf)) {
ret = btrfs_next_leaf(rc->extent_root, path);
if (ret != 0)
break;
leaf = path->nodes[0];
}
btrfs_item_key_to_cpu(leaf, &key, path->slots[0]);
if (key.objectid >= last) {
ret = 1;
break;
}
if (key.type != BTRFS_EXTENT_ITEM_KEY ||
key.objectid + key.offset <= rc->search_start) {
path->slots[0]++;
goto next;
}
ret = find_first_extent_bit(&rc->processed_blocks,
key.objectid, &start, &end,
EXTENT_DIRTY);
if (ret == 0 && start <= key.objectid) {
btrfs_release_path(path);
rc->search_start = end + 1;
} else {
rc->search_start = key.objectid + key.offset;
memcpy(extent_key, &key, sizeof(key));
return 0;
}
}
btrfs_release_path(path);
return ret;
}
static void set_reloc_control(struct reloc_control *rc)
{
struct btrfs_fs_info *fs_info = rc->extent_root->fs_info;
mutex_lock(&fs_info->reloc_mutex);
fs_info->reloc_ctl = rc;
mutex_unlock(&fs_info->reloc_mutex);
}
static void unset_reloc_control(struct reloc_control *rc)
{
struct btrfs_fs_info *fs_info = rc->extent_root->fs_info;
mutex_lock(&fs_info->reloc_mutex);
fs_info->reloc_ctl = NULL;
mutex_unlock(&fs_info->reloc_mutex);
}
static int check_extent_flags(u64 flags)
{
if ((flags & BTRFS_EXTENT_FLAG_DATA) &&
(flags & BTRFS_EXTENT_FLAG_TREE_BLOCK))
return 1;
if (!(flags & BTRFS_EXTENT_FLAG_DATA) &&
!(flags & BTRFS_EXTENT_FLAG_TREE_BLOCK))
return 1;
if ((flags & BTRFS_EXTENT_FLAG_DATA) &&
(flags & BTRFS_BLOCK_FLAG_FULL_BACKREF))
return 1;
return 0;
}
static noinline_for_stack
int prepare_to_relocate(struct reloc_control *rc)
{
struct btrfs_trans_handle *trans;
int ret;
rc->block_rsv = btrfs_alloc_block_rsv(rc->extent_root);
if (!rc->block_rsv)
return -ENOMEM;
/*
* reserve some space for creating reloc trees.
* btrfs_init_reloc_root will use them when there
* is no reservation in transaction handle.
*/
ret = btrfs_block_rsv_add(rc->extent_root, rc->block_rsv,
rc->extent_root->nodesize * 256);
if (ret)
return ret;
memset(&rc->cluster, 0, sizeof(rc->cluster));
rc->search_start = rc->block_group->key.objectid;
rc->extents_found = 0;
rc->nodes_relocated = 0;
rc->merging_rsv_size = 0;
rc->create_reloc_tree = 1;
set_reloc_control(rc);
trans = btrfs_join_transaction(rc->extent_root);
BUG_ON(IS_ERR(trans));
btrfs_commit_transaction(trans, rc->extent_root);
return 0;
}
static noinline_for_stack int relocate_block_group(struct reloc_control *rc)
{
struct rb_root blocks = RB_ROOT;
struct btrfs_key key;
struct btrfs_trans_handle *trans = NULL;
struct btrfs_path *path;
struct btrfs_extent_item *ei;
unsigned long nr;
u64 flags;
u32 item_size;
int ret;
int err = 0;
int progress = 0;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
path->reada = 1;
ret = prepare_to_relocate(rc);
if (ret) {
err = ret;
goto out_free;
}
while (1) {
progress++;
trans = btrfs_start_transaction(rc->extent_root, 0);
BUG_ON(IS_ERR(trans));
restart:
if (update_backref_cache(trans, &rc->backref_cache)) {
btrfs_end_transaction(trans, rc->extent_root);
continue;
}
ret = find_next_extent(trans, rc, path, &key);
if (ret < 0)
err = ret;
if (ret != 0)
break;
rc->extents_found++;
ei = btrfs_item_ptr(path->nodes[0], path->slots[0],
struct btrfs_extent_item);
item_size = btrfs_item_size_nr(path->nodes[0], path->slots[0]);
if (item_size >= sizeof(*ei)) {
flags = btrfs_extent_flags(path->nodes[0], ei);
ret = check_extent_flags(flags);
BUG_ON(ret);
} else {
#ifdef BTRFS_COMPAT_EXTENT_TREE_V0
u64 ref_owner;
int path_change = 0;
BUG_ON(item_size !=
sizeof(struct btrfs_extent_item_v0));
ret = get_ref_objectid_v0(rc, path, &key, &ref_owner,
&path_change);
if (ref_owner < BTRFS_FIRST_FREE_OBJECTID)
flags = BTRFS_EXTENT_FLAG_TREE_BLOCK;
else
flags = BTRFS_EXTENT_FLAG_DATA;
if (path_change) {
btrfs_release_path(path);
path->search_commit_root = 1;
path->skip_locking = 1;
ret = btrfs_search_slot(NULL, rc->extent_root,
&key, path, 0, 0);
if (ret < 0) {
err = ret;
break;
}
BUG_ON(ret > 0);
}
#else
BUG();
#endif
}
if (flags & BTRFS_EXTENT_FLAG_TREE_BLOCK) {
ret = add_tree_block(rc, &key, path, &blocks);
} else if (rc->stage == UPDATE_DATA_PTRS &&
(flags & BTRFS_EXTENT_FLAG_DATA)) {
ret = add_data_references(rc, &key, path, &blocks);
} else {
btrfs_release_path(path);
ret = 0;
}
if (ret < 0) {
err = ret;
break;
}
if (!RB_EMPTY_ROOT(&blocks)) {
ret = relocate_tree_blocks(trans, rc, &blocks);
if (ret < 0) {
if (ret != -EAGAIN) {
err = ret;
break;
}
rc->extents_found--;
rc->search_start = key.objectid;
}
}
ret = btrfs_block_rsv_check(rc->extent_root, rc->block_rsv, 5);
if (ret < 0) {
if (ret != -ENOSPC) {
err = ret;
WARN_ON(1);
break;
}
rc->commit_transaction = 1;
}
if (rc->commit_transaction) {
rc->commit_transaction = 0;
ret = btrfs_commit_transaction(trans, rc->extent_root);
BUG_ON(ret);
} else {
nr = trans->blocks_used;
btrfs_end_transaction_throttle(trans, rc->extent_root);
btrfs_btree_balance_dirty(rc->extent_root, nr);
}
trans = NULL;
if (rc->stage == MOVE_DATA_EXTENTS &&
(flags & BTRFS_EXTENT_FLAG_DATA)) {
rc->found_file_extent = 1;
ret = relocate_data_extent(rc->data_inode,
&key, &rc->cluster);
if (ret < 0) {
err = ret;
break;
}
}
}
if (trans && progress && err == -ENOSPC) {
ret = btrfs_force_chunk_alloc(trans, rc->extent_root,
rc->block_group->flags);
if (ret == 0) {
err = 0;
progress = 0;
goto restart;
}
}
btrfs_release_path(path);
clear_extent_bits(&rc->processed_blocks, 0, (u64)-1, EXTENT_DIRTY,
GFP_NOFS);
if (trans) {
nr = trans->blocks_used;
btrfs_end_transaction_throttle(trans, rc->extent_root);
btrfs_btree_balance_dirty(rc->extent_root, nr);
}
if (!err) {
ret = relocate_file_extent_cluster(rc->data_inode,
&rc->cluster);
if (ret < 0)
err = ret;
}
rc->create_reloc_tree = 0;
set_reloc_control(rc);
backref_cache_cleanup(&rc->backref_cache);
btrfs_block_rsv_release(rc->extent_root, rc->block_rsv, (u64)-1);
err = prepare_to_merge(rc, err);
merge_reloc_roots(rc);
rc->merge_reloc_tree = 0;
unset_reloc_control(rc);
btrfs_block_rsv_release(rc->extent_root, rc->block_rsv, (u64)-1);
/* get rid of pinned extents */
trans = btrfs_join_transaction(rc->extent_root);
if (IS_ERR(trans))
err = PTR_ERR(trans);
else
btrfs_commit_transaction(trans, rc->extent_root);
out_free:
btrfs_free_block_rsv(rc->extent_root, rc->block_rsv);
btrfs_free_path(path);
return err;
}
static int __insert_orphan_inode(struct btrfs_trans_handle *trans,
struct btrfs_root *root, u64 objectid)
{
struct btrfs_path *path;
struct btrfs_inode_item *item;
struct extent_buffer *leaf;
int ret;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
ret = btrfs_insert_empty_inode(trans, root, path, objectid);
if (ret)
goto out;
leaf = path->nodes[0];
item = btrfs_item_ptr(leaf, path->slots[0], struct btrfs_inode_item);
memset_extent_buffer(leaf, 0, (unsigned long)item, sizeof(*item));
btrfs_set_inode_generation(leaf, item, 1);
btrfs_set_inode_size(leaf, item, 0);
btrfs_set_inode_mode(leaf, item, S_IFREG | 0600);
btrfs_set_inode_flags(leaf, item, BTRFS_INODE_NOCOMPRESS |
BTRFS_INODE_PREALLOC);
btrfs_mark_buffer_dirty(leaf);
btrfs_release_path(path);
out:
btrfs_free_path(path);
return ret;
}
/*
* helper to create inode for data relocation.
* the inode is in data relocation tree and its link count is 0
*/
static noinline_for_stack
struct inode *create_reloc_inode(struct btrfs_fs_info *fs_info,
struct btrfs_block_group_cache *group)
{
struct inode *inode = NULL;
struct btrfs_trans_handle *trans;
struct btrfs_root *root;
struct btrfs_key key;
unsigned long nr;
u64 objectid = BTRFS_FIRST_FREE_OBJECTID;
int err = 0;
root = read_fs_root(fs_info, BTRFS_DATA_RELOC_TREE_OBJECTID);
if (IS_ERR(root))
return ERR_CAST(root);
trans = btrfs_start_transaction(root, 6);
if (IS_ERR(trans))
return ERR_CAST(trans);
err = btrfs_find_free_objectid(root, &objectid);
if (err)
goto out;
err = __insert_orphan_inode(trans, root, objectid);
BUG_ON(err);
key.objectid = objectid;
key.type = BTRFS_INODE_ITEM_KEY;
key.offset = 0;
inode = btrfs_iget(root->fs_info->sb, &key, root, NULL);
BUG_ON(IS_ERR(inode) || is_bad_inode(inode));
BTRFS_I(inode)->index_cnt = group->key.objectid;
err = btrfs_orphan_add(trans, inode);
out:
nr = trans->blocks_used;
btrfs_end_transaction(trans, root);
btrfs_btree_balance_dirty(root, nr);
if (err) {
if (inode)
iput(inode);
inode = ERR_PTR(err);
}
return inode;
}
static struct reloc_control *alloc_reloc_control(void)
{
struct reloc_control *rc;
rc = kzalloc(sizeof(*rc), GFP_NOFS);
if (!rc)
return NULL;
INIT_LIST_HEAD(&rc->reloc_roots);
backref_cache_init(&rc->backref_cache);
mapping_tree_init(&rc->reloc_root_tree);
extent_io_tree_init(&rc->processed_blocks, NULL);
return rc;
}
/*
* function to relocate all extents in a block group.
*/
int btrfs_relocate_block_group(struct btrfs_root *extent_root, u64 group_start)
{
struct btrfs_fs_info *fs_info = extent_root->fs_info;
struct reloc_control *rc;
struct inode *inode;
struct btrfs_path *path;
int ret;
int rw = 0;
int err = 0;
rc = alloc_reloc_control();
if (!rc)
return -ENOMEM;
rc->extent_root = extent_root;
rc->block_group = btrfs_lookup_block_group(fs_info, group_start);
BUG_ON(!rc->block_group);
if (!rc->block_group->ro) {
ret = btrfs_set_block_group_ro(extent_root, rc->block_group);
if (ret) {
err = ret;
goto out;
}
rw = 1;
}
path = btrfs_alloc_path();
if (!path) {
err = -ENOMEM;
goto out;
}
inode = lookup_free_space_inode(fs_info->tree_root, rc->block_group,
path);
btrfs_free_path(path);
if (!IS_ERR(inode))
ret = delete_block_group_cache(fs_info, inode, 0);
else
ret = PTR_ERR(inode);
if (ret && ret != -ENOENT) {
err = ret;
goto out;
}
rc->data_inode = create_reloc_inode(fs_info, rc->block_group);
if (IS_ERR(rc->data_inode)) {
err = PTR_ERR(rc->data_inode);
rc->data_inode = NULL;
goto out;
}
printk(KERN_INFO "btrfs: relocating block group %llu flags %llu\n",
(unsigned long long)rc->block_group->key.objectid,
(unsigned long long)rc->block_group->flags);
btrfs_start_delalloc_inodes(fs_info->tree_root, 0);
btrfs_wait_ordered_extents(fs_info->tree_root, 0, 0);
while (1) {
mutex_lock(&fs_info->cleaner_mutex);
btrfs_clean_old_snapshots(fs_info->tree_root);
ret = relocate_block_group(rc);
mutex_unlock(&fs_info->cleaner_mutex);
if (ret < 0) {
err = ret;
goto out;
}
if (rc->extents_found == 0)
break;
printk(KERN_INFO "btrfs: found %llu extents\n",
(unsigned long long)rc->extents_found);
if (rc->stage == MOVE_DATA_EXTENTS && rc->found_file_extent) {
btrfs_wait_ordered_range(rc->data_inode, 0, (u64)-1);
invalidate_mapping_pages(rc->data_inode->i_mapping,
0, -1);
rc->stage = UPDATE_DATA_PTRS;
}
}
filemap_write_and_wait_range(fs_info->btree_inode->i_mapping,
rc->block_group->key.objectid,
rc->block_group->key.objectid +
rc->block_group->key.offset - 1);
WARN_ON(rc->block_group->pinned > 0);
WARN_ON(rc->block_group->reserved > 0);
WARN_ON(btrfs_block_group_used(&rc->block_group->item) > 0);
out:
if (err && rw)
btrfs_set_block_group_rw(extent_root, rc->block_group);
iput(rc->data_inode);
btrfs_put_block_group(rc->block_group);
kfree(rc);
return err;
}
static noinline_for_stack int mark_garbage_root(struct btrfs_root *root)
{
struct btrfs_trans_handle *trans;
int ret, err;
trans = btrfs_start_transaction(root->fs_info->tree_root, 0);
if (IS_ERR(trans))
return PTR_ERR(trans);
memset(&root->root_item.drop_progress, 0,
sizeof(root->root_item.drop_progress));
root->root_item.drop_level = 0;
btrfs_set_root_refs(&root->root_item, 0);
ret = btrfs_update_root(trans, root->fs_info->tree_root,
&root->root_key, &root->root_item);
err = btrfs_end_transaction(trans, root->fs_info->tree_root);
if (err)
return err;
return ret;
}
/*
* recover relocation interrupted by system crash.
*
* this function resumes merging reloc trees with corresponding fs trees.
* this is important for keeping the sharing of tree blocks
*/
int btrfs_recover_relocation(struct btrfs_root *root)
{
LIST_HEAD(reloc_roots);
struct btrfs_key key;
struct btrfs_root *fs_root;
struct btrfs_root *reloc_root;
struct btrfs_path *path;
struct extent_buffer *leaf;
struct reloc_control *rc = NULL;
struct btrfs_trans_handle *trans;
int ret;
int err = 0;
path = btrfs_alloc_path();
if (!path)
return -ENOMEM;
path->reada = -1;
key.objectid = BTRFS_TREE_RELOC_OBJECTID;
key.type = BTRFS_ROOT_ITEM_KEY;
key.offset = (u64)-1;
while (1) {
ret = btrfs_search_slot(NULL, root->fs_info->tree_root, &key,
path, 0, 0);
if (ret < 0) {
err = ret;
goto out;
}
if (ret > 0) {
if (path->slots[0] == 0)
break;
path->slots[0]--;
}
leaf = path->nodes[0];
btrfs_item_key_to_cpu(leaf, &key, path->slots[0]);
btrfs_release_path(path);
if (key.objectid != BTRFS_TREE_RELOC_OBJECTID ||
key.type != BTRFS_ROOT_ITEM_KEY)
break;
reloc_root = btrfs_read_fs_root_no_radix(root, &key);
if (IS_ERR(reloc_root)) {
err = PTR_ERR(reloc_root);
goto out;
}
list_add(&reloc_root->root_list, &reloc_roots);
if (btrfs_root_refs(&reloc_root->root_item) > 0) {
fs_root = read_fs_root(root->fs_info,
reloc_root->root_key.offset);
if (IS_ERR(fs_root)) {
ret = PTR_ERR(fs_root);
if (ret != -ENOENT) {
err = ret;
goto out;
}
ret = mark_garbage_root(reloc_root);
if (ret < 0) {
err = ret;
goto out;
}
}
}
if (key.offset == 0)
break;
key.offset--;
}
btrfs_release_path(path);
if (list_empty(&reloc_roots))
goto out;
rc = alloc_reloc_control();
if (!rc) {
err = -ENOMEM;
goto out;
}
rc->extent_root = root->fs_info->extent_root;
set_reloc_control(rc);
trans = btrfs_join_transaction(rc->extent_root);
if (IS_ERR(trans)) {
unset_reloc_control(rc);
err = PTR_ERR(trans);
goto out_free;
}
rc->merge_reloc_tree = 1;
while (!list_empty(&reloc_roots)) {
reloc_root = list_entry(reloc_roots.next,
struct btrfs_root, root_list);
list_del(&reloc_root->root_list);
if (btrfs_root_refs(&reloc_root->root_item) == 0) {
list_add_tail(&reloc_root->root_list,
&rc->reloc_roots);
continue;
}
fs_root = read_fs_root(root->fs_info,
reloc_root->root_key.offset);
if (IS_ERR(fs_root)) {
err = PTR_ERR(fs_root);
goto out_free;
}
err = __add_reloc_root(reloc_root);
BUG_ON(err < 0); /* -ENOMEM or logic error */
fs_root->reloc_root = reloc_root;
}
err = btrfs_commit_transaction(trans, rc->extent_root);
if (err)
goto out_free;
merge_reloc_roots(rc);
unset_reloc_control(rc);
trans = btrfs_join_transaction(rc->extent_root);
if (IS_ERR(trans))
err = PTR_ERR(trans);
else
err = btrfs_commit_transaction(trans, rc->extent_root);
out_free:
kfree(rc);
out:
while (!list_empty(&reloc_roots)) {
reloc_root = list_entry(reloc_roots.next,
struct btrfs_root, root_list);
list_del(&reloc_root->root_list);
free_extent_buffer(reloc_root->node);
free_extent_buffer(reloc_root->commit_root);
kfree(reloc_root);
}
btrfs_free_path(path);
if (err == 0) {
/* cleanup orphan inode in data relocation tree */
fs_root = read_fs_root(root->fs_info,
BTRFS_DATA_RELOC_TREE_OBJECTID);
if (IS_ERR(fs_root))
err = PTR_ERR(fs_root);
else
err = btrfs_orphan_cleanup(fs_root);
}
return err;
}
/*
* helper to add ordered checksum for data relocation.
*
* cloning checksum properly handles the nodatasum extents.
* it also saves CPU time to re-calculate the checksum.
*/
int btrfs_reloc_clone_csums(struct inode *inode, u64 file_pos, u64 len)
{
struct btrfs_ordered_sum *sums;
struct btrfs_sector_sum *sector_sum;
struct btrfs_ordered_extent *ordered;
struct btrfs_root *root = BTRFS_I(inode)->root;
size_t offset;
int ret;
u64 disk_bytenr;
LIST_HEAD(list);
ordered = btrfs_lookup_ordered_extent(inode, file_pos);
BUG_ON(ordered->file_offset != file_pos || ordered->len != len);
disk_bytenr = file_pos + BTRFS_I(inode)->index_cnt;
ret = btrfs_lookup_csums_range(root->fs_info->csum_root, disk_bytenr,
disk_bytenr + len - 1, &list, 0);
if (ret)
goto out;
while (!list_empty(&list)) {
sums = list_entry(list.next, struct btrfs_ordered_sum, list);
list_del_init(&sums->list);
sector_sum = sums->sums;
sums->bytenr = ordered->start;
offset = 0;
while (offset < sums->len) {
sector_sum->bytenr += ordered->start - disk_bytenr;
sector_sum++;
offset += root->sectorsize;
}
btrfs_add_ordered_sum(inode, ordered, sums);
}
out:
btrfs_put_ordered_extent(ordered);
return ret;
}
void btrfs_reloc_cow_block(struct btrfs_trans_handle *trans,
struct btrfs_root *root, struct extent_buffer *buf,
struct extent_buffer *cow)
{
struct reloc_control *rc;
struct backref_node *node;
int first_cow = 0;
int level;
int ret;
rc = root->fs_info->reloc_ctl;
if (!rc)
return;
BUG_ON(rc->stage == UPDATE_DATA_PTRS &&
root->root_key.objectid == BTRFS_DATA_RELOC_TREE_OBJECTID);
level = btrfs_header_level(buf);
if (btrfs_header_generation(buf) <=
btrfs_root_last_snapshot(&root->root_item))
first_cow = 1;
if (root->root_key.objectid == BTRFS_TREE_RELOC_OBJECTID &&
rc->create_reloc_tree) {
WARN_ON(!first_cow && level == 0);
node = rc->backref_cache.path[level];
BUG_ON(node->bytenr != buf->start &&
node->new_bytenr != buf->start);
drop_node_buffer(node);
extent_buffer_get(cow);
node->eb = cow;
node->new_bytenr = cow->start;
if (!node->pending) {
list_move_tail(&node->list,
&rc->backref_cache.pending[level]);
node->pending = 1;
}
if (first_cow)
__mark_block_processed(rc, node);
if (first_cow && level > 0)
rc->nodes_relocated += buf->len;
}
if (level == 0 && first_cow && rc->stage == UPDATE_DATA_PTRS) {
ret = replace_file_extents(trans, rc, root, cow);
BUG_ON(ret);
}
}
/*
* called before creating snapshot. it calculates metadata reservation
* requried for relocating tree blocks in the snapshot
*/
void btrfs_reloc_pre_snapshot(struct btrfs_trans_handle *trans,
struct btrfs_pending_snapshot *pending,
u64 *bytes_to_reserve)
{
struct btrfs_root *root;
struct reloc_control *rc;
root = pending->root;
if (!root->reloc_root)
return;
rc = root->fs_info->reloc_ctl;
if (!rc->merge_reloc_tree)
return;
root = root->reloc_root;
BUG_ON(btrfs_root_refs(&root->root_item) == 0);
/*
* relocation is in the stage of merging trees. the space
* used by merging a reloc tree is twice the size of
* relocated tree nodes in the worst case. half for cowing
* the reloc tree, half for cowing the fs tree. the space
* used by cowing the reloc tree will be freed after the
* tree is dropped. if we create snapshot, cowing the fs
* tree may use more space than it frees. so we need
* reserve extra space.
*/
*bytes_to_reserve += rc->nodes_relocated;
}
/*
* called after snapshot is created. migrate block reservation
* and create reloc root for the newly created snapshot
*/
int btrfs_reloc_post_snapshot(struct btrfs_trans_handle *trans,
struct btrfs_pending_snapshot *pending)
{
struct btrfs_root *root = pending->root;
struct btrfs_root *reloc_root;
struct btrfs_root *new_root;
struct reloc_control *rc;
int ret;
if (!root->reloc_root)
return 0;
rc = root->fs_info->reloc_ctl;
rc->merging_rsv_size += rc->nodes_relocated;
if (rc->merge_reloc_tree) {
ret = btrfs_block_rsv_migrate(&pending->block_rsv,
rc->block_rsv,
rc->nodes_relocated);
if (ret)
return ret;
}
new_root = pending->snap;
reloc_root = create_reloc_root(trans, root->reloc_root,
new_root->root_key.objectid);
if (IS_ERR(reloc_root))
return PTR_ERR(reloc_root);
ret = __add_reloc_root(reloc_root);
BUG_ON(ret < 0);
new_root->reloc_root = reloc_root;
if (rc->create_reloc_tree)
ret = clone_backref_node(trans, rc, root, reloc_root);
return ret;
}
| gpl-2.0 |
gsstudios/Dorimanx-SG2-I9100-Kernel | tools/lib/traceevent/plugin_xen.c | 2149 | 3533 | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "event-parse.h"
#define __HYPERVISOR_set_trap_table 0
#define __HYPERVISOR_mmu_update 1
#define __HYPERVISOR_set_gdt 2
#define __HYPERVISOR_stack_switch 3
#define __HYPERVISOR_set_callbacks 4
#define __HYPERVISOR_fpu_taskswitch 5
#define __HYPERVISOR_sched_op_compat 6
#define __HYPERVISOR_dom0_op 7
#define __HYPERVISOR_set_debugreg 8
#define __HYPERVISOR_get_debugreg 9
#define __HYPERVISOR_update_descriptor 10
#define __HYPERVISOR_memory_op 12
#define __HYPERVISOR_multicall 13
#define __HYPERVISOR_update_va_mapping 14
#define __HYPERVISOR_set_timer_op 15
#define __HYPERVISOR_event_channel_op_compat 16
#define __HYPERVISOR_xen_version 17
#define __HYPERVISOR_console_io 18
#define __HYPERVISOR_physdev_op_compat 19
#define __HYPERVISOR_grant_table_op 20
#define __HYPERVISOR_vm_assist 21
#define __HYPERVISOR_update_va_mapping_otherdomain 22
#define __HYPERVISOR_iret 23 /* x86 only */
#define __HYPERVISOR_vcpu_op 24
#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
#define __HYPERVISOR_mmuext_op 26
#define __HYPERVISOR_acm_op 27
#define __HYPERVISOR_nmi_op 28
#define __HYPERVISOR_sched_op 29
#define __HYPERVISOR_callback_op 30
#define __HYPERVISOR_xenoprof_op 31
#define __HYPERVISOR_event_channel_op 32
#define __HYPERVISOR_physdev_op 33
#define __HYPERVISOR_hvm_op 34
#define __HYPERVISOR_tmem_op 38
/* Architecture-specific hypercall definitions. */
#define __HYPERVISOR_arch_0 48
#define __HYPERVISOR_arch_1 49
#define __HYPERVISOR_arch_2 50
#define __HYPERVISOR_arch_3 51
#define __HYPERVISOR_arch_4 52
#define __HYPERVISOR_arch_5 53
#define __HYPERVISOR_arch_6 54
#define __HYPERVISOR_arch_7 55
#define N(x) [__HYPERVISOR_##x] = "("#x")"
static const char *xen_hypercall_names[] = {
N(set_trap_table),
N(mmu_update),
N(set_gdt),
N(stack_switch),
N(set_callbacks),
N(fpu_taskswitch),
N(sched_op_compat),
N(dom0_op),
N(set_debugreg),
N(get_debugreg),
N(update_descriptor),
N(memory_op),
N(multicall),
N(update_va_mapping),
N(set_timer_op),
N(event_channel_op_compat),
N(xen_version),
N(console_io),
N(physdev_op_compat),
N(grant_table_op),
N(vm_assist),
N(update_va_mapping_otherdomain),
N(iret),
N(vcpu_op),
N(set_segment_base),
N(mmuext_op),
N(acm_op),
N(nmi_op),
N(sched_op),
N(callback_op),
N(xenoprof_op),
N(event_channel_op),
N(physdev_op),
N(hvm_op),
/* Architecture-specific hypercall definitions. */
N(arch_0),
N(arch_1),
N(arch_2),
N(arch_3),
N(arch_4),
N(arch_5),
N(arch_6),
N(arch_7),
};
#undef N
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
static const char *xen_hypercall_name(unsigned op)
{
if (op < ARRAY_SIZE(xen_hypercall_names) &&
xen_hypercall_names[op] != NULL)
return xen_hypercall_names[op];
return "";
}
unsigned long long process_xen_hypercall_name(struct trace_seq *s,
unsigned long long *args)
{
unsigned int op = args[0];
trace_seq_printf(s, "%s", xen_hypercall_name(op));
return 0;
}
int PEVENT_PLUGIN_LOADER(struct pevent *pevent)
{
pevent_register_print_function(pevent,
process_xen_hypercall_name,
PEVENT_FUNC_ARG_STRING,
"xen_hypercall_name",
PEVENT_FUNC_ARG_INT,
PEVENT_FUNC_ARG_VOID);
return 0;
}
void PEVENT_PLUGIN_UNLOADER(struct pevent *pevent)
{
pevent_unregister_print_function(pevent, process_xen_hypercall_name,
"xen_hypercall_name");
}
| gpl-2.0 |
OlegKyiashko/LGOGP-kernel | drivers/pci/hotplug/shpchp_core.c | 3429 | 10516 | /*
* Standard Hot Plug Controller Driver
*
* Copyright (C) 1995,2001 Compaq Computer Corporation
* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
* Copyright (C) 2001 IBM Corp.
* Copyright (C) 2003-2004 Intel Corporation
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include "shpchp.h"
/* Global variables */
bool shpchp_debug;
bool shpchp_poll_mode;
int shpchp_poll_time;
struct workqueue_struct *shpchp_wq;
struct workqueue_struct *shpchp_ordered_wq;
#define DRIVER_VERSION "0.4"
#define DRIVER_AUTHOR "Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>"
#define DRIVER_DESC "Standard Hot Plug PCI Controller Driver"
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
module_param(shpchp_debug, bool, 0644);
module_param(shpchp_poll_mode, bool, 0644);
module_param(shpchp_poll_time, int, 0644);
MODULE_PARM_DESC(shpchp_debug, "Debugging mode enabled or not");
MODULE_PARM_DESC(shpchp_poll_mode, "Using polling mechanism for hot-plug events or not");
MODULE_PARM_DESC(shpchp_poll_time, "Polling mechanism frequency, in seconds");
#define SHPC_MODULE_NAME "shpchp"
static int set_attention_status (struct hotplug_slot *slot, u8 value);
static int enable_slot (struct hotplug_slot *slot);
static int disable_slot (struct hotplug_slot *slot);
static int get_power_status (struct hotplug_slot *slot, u8 *value);
static int get_attention_status (struct hotplug_slot *slot, u8 *value);
static int get_latch_status (struct hotplug_slot *slot, u8 *value);
static int get_adapter_status (struct hotplug_slot *slot, u8 *value);
static struct hotplug_slot_ops shpchp_hotplug_slot_ops = {
.set_attention_status = set_attention_status,
.enable_slot = enable_slot,
.disable_slot = disable_slot,
.get_power_status = get_power_status,
.get_attention_status = get_attention_status,
.get_latch_status = get_latch_status,
.get_adapter_status = get_adapter_status,
};
/**
* release_slot - free up the memory used by a slot
* @hotplug_slot: slot to free
*/
static void release_slot(struct hotplug_slot *hotplug_slot)
{
struct slot *slot = hotplug_slot->private;
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
kfree(slot->hotplug_slot->info);
kfree(slot->hotplug_slot);
kfree(slot);
}
static int init_slots(struct controller *ctrl)
{
struct slot *slot;
struct hotplug_slot *hotplug_slot;
struct hotplug_slot_info *info;
char name[SLOT_NAME_SIZE];
int retval = -ENOMEM;
int i;
for (i = 0; i < ctrl->num_slots; i++) {
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
if (!slot)
goto error;
hotplug_slot = kzalloc(sizeof(*hotplug_slot), GFP_KERNEL);
if (!hotplug_slot)
goto error_slot;
slot->hotplug_slot = hotplug_slot;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
goto error_hpslot;
hotplug_slot->info = info;
slot->hp_slot = i;
slot->ctrl = ctrl;
slot->bus = ctrl->pci_dev->subordinate->number;
slot->device = ctrl->slot_device_offset + i;
slot->hpc_ops = ctrl->hpc_ops;
slot->number = ctrl->first_slot + (ctrl->slot_num_inc * i);
mutex_init(&slot->lock);
INIT_DELAYED_WORK(&slot->work, shpchp_queue_pushbutton_work);
/* register this slot with the hotplug pci core */
hotplug_slot->private = slot;
hotplug_slot->release = &release_slot;
snprintf(name, SLOT_NAME_SIZE, "%d", slot->number);
hotplug_slot->ops = &shpchp_hotplug_slot_ops;
ctrl_dbg(ctrl, "Registering domain:bus:dev=%04x:%02x:%02x "
"hp_slot=%x sun=%x slot_device_offset=%x\n",
pci_domain_nr(ctrl->pci_dev->subordinate),
slot->bus, slot->device, slot->hp_slot, slot->number,
ctrl->slot_device_offset);
retval = pci_hp_register(slot->hotplug_slot,
ctrl->pci_dev->subordinate, slot->device, name);
if (retval) {
ctrl_err(ctrl, "pci_hp_register failed with error %d\n",
retval);
goto error_info;
}
get_power_status(hotplug_slot, &info->power_status);
get_attention_status(hotplug_slot, &info->attention_status);
get_latch_status(hotplug_slot, &info->latch_status);
get_adapter_status(hotplug_slot, &info->adapter_status);
list_add(&slot->slot_list, &ctrl->slot_list);
}
return 0;
error_info:
kfree(info);
error_hpslot:
kfree(hotplug_slot);
error_slot:
kfree(slot);
error:
return retval;
}
void cleanup_slots(struct controller *ctrl)
{
struct list_head *tmp;
struct list_head *next;
struct slot *slot;
list_for_each_safe(tmp, next, &ctrl->slot_list) {
slot = list_entry(tmp, struct slot, slot_list);
list_del(&slot->slot_list);
cancel_delayed_work(&slot->work);
flush_workqueue(shpchp_wq);
flush_workqueue(shpchp_ordered_wq);
pci_hp_deregister(slot->hotplug_slot);
}
}
/*
* set_attention_status - Turns the Amber LED for a slot on, off or blink
*/
static int set_attention_status (struct hotplug_slot *hotplug_slot, u8 status)
{
struct slot *slot = get_slot(hotplug_slot);
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
hotplug_slot->info->attention_status = status;
slot->hpc_ops->set_attention_status(slot, status);
return 0;
}
static int enable_slot (struct hotplug_slot *hotplug_slot)
{
struct slot *slot = get_slot(hotplug_slot);
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
return shpchp_sysfs_enable_slot(slot);
}
static int disable_slot (struct hotplug_slot *hotplug_slot)
{
struct slot *slot = get_slot(hotplug_slot);
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
return shpchp_sysfs_disable_slot(slot);
}
static int get_power_status (struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
retval = slot->hpc_ops->get_power_status(slot, value);
if (retval < 0)
*value = hotplug_slot->info->power_status;
return 0;
}
static int get_attention_status (struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
retval = slot->hpc_ops->get_attention_status(slot, value);
if (retval < 0)
*value = hotplug_slot->info->attention_status;
return 0;
}
static int get_latch_status (struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
retval = slot->hpc_ops->get_latch_status(slot, value);
if (retval < 0)
*value = hotplug_slot->info->latch_status;
return 0;
}
static int get_adapter_status (struct hotplug_slot *hotplug_slot, u8 *value)
{
struct slot *slot = get_slot(hotplug_slot);
int retval;
ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n",
__func__, slot_name(slot));
retval = slot->hpc_ops->get_adapter_status(slot, value);
if (retval < 0)
*value = hotplug_slot->info->adapter_status;
return 0;
}
static int is_shpc_capable(struct pci_dev *dev)
{
if (dev->vendor == PCI_VENDOR_ID_AMD &&
dev->device == PCI_DEVICE_ID_AMD_GOLAM_7450)
return 1;
if (!pci_find_capability(dev, PCI_CAP_ID_SHPC))
return 0;
if (get_hp_hw_control_from_firmware(dev))
return 0;
return 1;
}
static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int rc;
struct controller *ctrl;
if (!is_shpc_capable(pdev))
return -ENODEV;
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
if (!ctrl) {
dev_err(&pdev->dev, "%s: Out of memory\n", __func__);
goto err_out_none;
}
INIT_LIST_HEAD(&ctrl->slot_list);
rc = shpc_init(ctrl, pdev);
if (rc) {
ctrl_dbg(ctrl, "Controller initialization failed\n");
goto err_out_free_ctrl;
}
pci_set_drvdata(pdev, ctrl);
/* Setup the slot information structures */
rc = init_slots(ctrl);
if (rc) {
ctrl_err(ctrl, "Slot initialization failed\n");
goto err_out_release_ctlr;
}
rc = shpchp_create_ctrl_files(ctrl);
if (rc)
goto err_cleanup_slots;
return 0;
err_cleanup_slots:
cleanup_slots(ctrl);
err_out_release_ctlr:
ctrl->hpc_ops->release_ctlr(ctrl);
err_out_free_ctrl:
kfree(ctrl);
err_out_none:
return -ENODEV;
}
static void shpc_remove(struct pci_dev *dev)
{
struct controller *ctrl = pci_get_drvdata(dev);
shpchp_remove_ctrl_files(ctrl);
ctrl->hpc_ops->release_ctlr(ctrl);
kfree(ctrl);
}
static struct pci_device_id shpcd_pci_tbl[] = {
{PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0)},
{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, shpcd_pci_tbl);
static struct pci_driver shpc_driver = {
.name = SHPC_MODULE_NAME,
.id_table = shpcd_pci_tbl,
.probe = shpc_probe,
.remove = shpc_remove,
};
static int __init shpcd_init(void)
{
int retval = 0;
shpchp_wq = alloc_ordered_workqueue("shpchp", 0);
if (!shpchp_wq)
return -ENOMEM;
shpchp_ordered_wq = alloc_ordered_workqueue("shpchp_ordered", 0);
if (!shpchp_ordered_wq) {
destroy_workqueue(shpchp_wq);
return -ENOMEM;
}
retval = pci_register_driver(&shpc_driver);
dbg("%s: pci_register_driver = %d\n", __func__, retval);
info(DRIVER_DESC " version: " DRIVER_VERSION "\n");
if (retval) {
destroy_workqueue(shpchp_ordered_wq);
destroy_workqueue(shpchp_wq);
}
return retval;
}
static void __exit shpcd_cleanup(void)
{
dbg("unload_shpchpd()\n");
pci_unregister_driver(&shpc_driver);
destroy_workqueue(shpchp_ordered_wq);
destroy_workqueue(shpchp_wq);
info(DRIVER_DESC " version: " DRIVER_VERSION " unloaded\n");
}
module_init(shpcd_init);
module_exit(shpcd_cleanup);
| gpl-2.0 |
dorimanx/Dorimanx-SG2-I9100-Kernel | drivers/mtd/maps/ichxrom.c | 3685 | 9893 | /*
* ichxrom.c
*
* Normal mappings of chips in physical memory
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/flashchip.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/list.h>
#define xstr(s) str(s)
#define str(s) #s
#define MOD_NAME xstr(KBUILD_BASENAME)
#define ADDRESS_NAME_LEN 18
#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
#define BIOS_CNTL 0x4e
#define FWH_DEC_EN1 0xE3
#define FWH_DEC_EN2 0xF0
#define FWH_SEL1 0xE8
#define FWH_SEL2 0xEE
struct ichxrom_window {
void __iomem* virt;
unsigned long phys;
unsigned long size;
struct list_head maps;
struct resource rsrc;
struct pci_dev *pdev;
};
struct ichxrom_map_info {
struct list_head list;
struct map_info map;
struct mtd_info *mtd;
struct resource rsrc;
char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
};
static struct ichxrom_window ichxrom_window = {
.maps = LIST_HEAD_INIT(ichxrom_window.maps),
};
static void ichxrom_cleanup(struct ichxrom_window *window)
{
struct ichxrom_map_info *map, *scratch;
u16 word;
/* Disable writes through the rom window */
pci_read_config_word(window->pdev, BIOS_CNTL, &word);
pci_write_config_word(window->pdev, BIOS_CNTL, word & ~1);
pci_dev_put(window->pdev);
/* Free all of the mtd devices */
list_for_each_entry_safe(map, scratch, &window->maps, list) {
if (map->rsrc.parent)
release_resource(&map->rsrc);
mtd_device_unregister(map->mtd);
map_destroy(map->mtd);
list_del(&map->list);
kfree(map);
}
if (window->rsrc.parent)
release_resource(&window->rsrc);
if (window->virt) {
iounmap(window->virt);
window->virt = NULL;
window->phys = 0;
window->size = 0;
window->pdev = NULL;
}
}
static int ichxrom_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
struct ichxrom_window *window = &ichxrom_window;
struct ichxrom_map_info *map = NULL;
unsigned long map_top;
u8 byte;
u16 word;
/* For now I just handle the ichx and I assume there
* are not a lot of resources up at the top of the address
* space. It is possible to handle other devices in the
* top 16MB but it is very painful. Also since
* you can only really attach a FWH to an ICHX there
* a number of simplifications you can make.
*
* Also you can page firmware hubs if an 8MB window isn't enough
* but don't currently handle that case either.
*/
window->pdev = pdev;
/* Find a region continuous to the end of the ROM window */
window->phys = 0;
pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
if (byte == 0xff) {
window->phys = 0xffc00000;
pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
if ((byte & 0x0f) == 0x0f) {
window->phys = 0xff400000;
}
else if ((byte & 0x0e) == 0x0e) {
window->phys = 0xff500000;
}
else if ((byte & 0x0c) == 0x0c) {
window->phys = 0xff600000;
}
else if ((byte & 0x08) == 0x08) {
window->phys = 0xff700000;
}
}
else if ((byte & 0xfe) == 0xfe) {
window->phys = 0xffc80000;
}
else if ((byte & 0xfc) == 0xfc) {
window->phys = 0xffd00000;
}
else if ((byte & 0xf8) == 0xf8) {
window->phys = 0xffd80000;
}
else if ((byte & 0xf0) == 0xf0) {
window->phys = 0xffe00000;
}
else if ((byte & 0xe0) == 0xe0) {
window->phys = 0xffe80000;
}
else if ((byte & 0xc0) == 0xc0) {
window->phys = 0xfff00000;
}
else if ((byte & 0x80) == 0x80) {
window->phys = 0xfff80000;
}
if (window->phys == 0) {
printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
goto out;
}
window->phys -= 0x400000UL;
window->size = (0xffffffffUL - window->phys) + 1UL;
/* Enable writes through the rom window */
pci_read_config_word(pdev, BIOS_CNTL, &word);
if (!(word & 1) && (word & (1<<1))) {
/* The BIOS will generate an error if I enable
* this device, so don't even try.
*/
printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
goto out;
}
pci_write_config_word(pdev, BIOS_CNTL, word | 1);
/*
* Try to reserve the window mem region. If this fails then
* it is likely due to the window being "reseved" by the BIOS.
*/
window->rsrc.name = MOD_NAME;
window->rsrc.start = window->phys;
window->rsrc.end = window->phys + window->size - 1;
window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
if (request_resource(&iomem_resource, &window->rsrc)) {
window->rsrc.parent = NULL;
printk(KERN_DEBUG MOD_NAME ": "
"%s(): Unable to register resource %pR - kernel bug?\n",
__func__, &window->rsrc);
}
/* Map the firmware hub into my address space. */
window->virt = ioremap_nocache(window->phys, window->size);
if (!window->virt) {
printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
window->phys, window->size);
goto out;
}
/* Get the first address to look for an rom chip at */
map_top = window->phys;
if ((window->phys & 0x3fffff) != 0) {
map_top = window->phys + 0x400000;
}
#if 1
/* The probe sequence run over the firmware hub lock
* registers sets them to 0x7 (no access).
* Probe at most the last 4M of the address space.
*/
if (map_top < 0xffc00000) {
map_top = 0xffc00000;
}
#endif
/* Loop through and look for rom chips */
while((map_top - 1) < 0xffffffffUL) {
struct cfi_private *cfi;
unsigned long offset;
int i;
if (!map) {
map = kmalloc(sizeof(*map), GFP_KERNEL);
}
if (!map) {
printk(KERN_ERR MOD_NAME ": kmalloc failed");
goto out;
}
memset(map, 0, sizeof(*map));
INIT_LIST_HEAD(&map->list);
map->map.name = map->map_name;
map->map.phys = map_top;
offset = map_top - window->phys;
map->map.virt = (void __iomem *)
(((unsigned long)(window->virt)) + offset);
map->map.size = 0xffffffffUL - map_top + 1UL;
/* Set the name of the map to the address I am trying */
sprintf(map->map_name, "%s @%08Lx",
MOD_NAME, (unsigned long long)map->map.phys);
/* Firmware hubs only use vpp when being programmed
* in a factory setting. So in-place programming
* needs to use a different method.
*/
for(map->map.bankwidth = 32; map->map.bankwidth;
map->map.bankwidth >>= 1)
{
char **probe_type;
/* Skip bankwidths that are not supported */
if (!map_bankwidth_supported(map->map.bankwidth))
continue;
/* Setup the map methods */
simple_map_init(&map->map);
/* Try all of the probe methods */
probe_type = rom_probe_types;
for(; *probe_type; probe_type++) {
map->mtd = do_map_probe(*probe_type, &map->map);
if (map->mtd)
goto found;
}
}
map_top += ROM_PROBE_STEP_SIZE;
continue;
found:
/* Trim the size if we are larger than the map */
if (map->mtd->size > map->map.size) {
printk(KERN_WARNING MOD_NAME
" rom(%llu) larger than window(%lu). fixing...\n",
(unsigned long long)map->mtd->size, map->map.size);
map->mtd->size = map->map.size;
}
if (window->rsrc.parent) {
/*
* Registering the MTD device in iomem may not be possible
* if there is a BIOS "reserved" and BUSY range. If this
* fails then continue anyway.
*/
map->rsrc.name = map->map_name;
map->rsrc.start = map->map.phys;
map->rsrc.end = map->map.phys + map->mtd->size - 1;
map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
if (request_resource(&window->rsrc, &map->rsrc)) {
printk(KERN_ERR MOD_NAME
": cannot reserve MTD resource\n");
map->rsrc.parent = NULL;
}
}
/* Make the whole region visible in the map */
map->map.virt = window->virt;
map->map.phys = window->phys;
cfi = map->map.fldrv_priv;
for(i = 0; i < cfi->numchips; i++) {
cfi->chips[i].start += offset;
}
/* Now that the mtd devices is complete claim and export it */
map->mtd->owner = THIS_MODULE;
if (mtd_device_register(map->mtd, NULL, 0)) {
map_destroy(map->mtd);
map->mtd = NULL;
goto out;
}
/* Calculate the new value of map_top */
map_top += map->mtd->size;
/* File away the map structure */
list_add(&map->list, &window->maps);
map = NULL;
}
out:
/* Free any left over map structures */
kfree(map);
/* See if I have any map structures */
if (list_empty(&window->maps)) {
ichxrom_cleanup(window);
return -ENODEV;
}
return 0;
}
static void ichxrom_remove_one(struct pci_dev *pdev)
{
struct ichxrom_window *window = &ichxrom_window;
ichxrom_cleanup(window);
}
static struct pci_device_id ichxrom_pci_tbl[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
PCI_ANY_ID, PCI_ANY_ID, },
{ 0, },
};
#if 0
MODULE_DEVICE_TABLE(pci, ichxrom_pci_tbl);
static struct pci_driver ichxrom_driver = {
.name = MOD_NAME,
.id_table = ichxrom_pci_tbl,
.probe = ichxrom_init_one,
.remove = ichxrom_remove_one,
};
#endif
static int __init init_ichxrom(void)
{
struct pci_dev *pdev;
struct pci_device_id *id;
pdev = NULL;
for (id = ichxrom_pci_tbl; id->vendor; id++) {
pdev = pci_get_device(id->vendor, id->device, NULL);
if (pdev) {
break;
}
}
if (pdev) {
return ichxrom_init_one(pdev, &ichxrom_pci_tbl[0]);
}
return -ENXIO;
#if 0
return pci_register_driver(&ichxrom_driver);
#endif
}
static void __exit cleanup_ichxrom(void)
{
ichxrom_remove_one(ichxrom_window.pdev);
}
module_init(init_ichxrom);
module_exit(cleanup_ichxrom);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");
MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ICHX southbridge");
| gpl-2.0 |
vamanea/goldfish-trustzone | drivers/staging/iio/dds/ad9852.c | 4965 | 5708 | /*
* Driver for ADI Direct Digital Synthesis ad9852
*
* Copyright (c) 2010 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include "../iio.h"
#include "../sysfs.h"
#define DRV_NAME "ad9852"
#define addr_phaad1 0x0
#define addr_phaad2 0x1
#define addr_fretu1 0x2
#define addr_fretu2 0x3
#define addr_delfre 0x4
#define addr_updclk 0x5
#define addr_ramclk 0x6
#define addr_contrl 0x7
#define addr_optskm 0x8
#define addr_optskr 0xa
#define addr_dacctl 0xb
#define COMPPD (1 << 4)
#define REFMULT2 (1 << 2)
#define BYPPLL (1 << 5)
#define PLLRANG (1 << 6)
#define IEUPCLK (1)
#define OSKEN (1 << 5)
#define read_bit (1 << 7)
/* Register format: 1 byte addr + value */
struct ad9852_config {
u8 phajst0[3];
u8 phajst1[3];
u8 fretun1[6];
u8 fretun2[6];
u8 dltafre[6];
u8 updtclk[5];
u8 ramprat[4];
u8 control[5];
u8 outpskm[3];
u8 outpskr[2];
u8 daccntl[3];
};
struct ad9852_state {
struct mutex lock;
struct spi_device *sdev;
};
static ssize_t ad9852_set_parameter(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t len)
{
struct spi_message msg;
struct spi_transfer xfer;
int ret;
struct ad9852_config *config = (struct ad9852_config *)buf;
struct iio_dev *idev = dev_get_drvdata(dev);
struct ad9852_state *st = iio_priv(idev);
xfer.len = 3;
xfer.tx_buf = &config->phajst0[0];
mutex_lock(&st->lock);
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 3;
xfer.tx_buf = &config->phajst1[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 6;
xfer.tx_buf = &config->fretun1[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 6;
xfer.tx_buf = &config->fretun2[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 6;
xfer.tx_buf = &config->dltafre[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 5;
xfer.tx_buf = &config->updtclk[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 4;
xfer.tx_buf = &config->ramprat[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 5;
xfer.tx_buf = &config->control[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 3;
xfer.tx_buf = &config->outpskm[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 2;
xfer.tx_buf = &config->outpskr[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
xfer.len = 3;
xfer.tx_buf = &config->daccntl[0];
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
error_ret:
mutex_unlock(&st->lock);
return ret ? ret : len;
}
static IIO_DEVICE_ATTR(dds, S_IWUSR, NULL, ad9852_set_parameter, 0);
static void ad9852_init(struct ad9852_state *st)
{
struct spi_message msg;
struct spi_transfer xfer;
int ret;
u8 config[5];
config[0] = addr_contrl;
config[1] = COMPPD;
config[2] = REFMULT2 | BYPPLL | PLLRANG;
config[3] = IEUPCLK;
config[4] = OSKEN;
mutex_lock(&st->lock);
xfer.len = 5;
xfer.tx_buf = &config;
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
ret = spi_sync(st->sdev, &msg);
if (ret)
goto error_ret;
error_ret:
mutex_unlock(&st->lock);
}
static struct attribute *ad9852_attributes[] = {
&iio_dev_attr_dds.dev_attr.attr,
NULL,
};
static const struct attribute_group ad9852_attribute_group = {
.attrs = ad9852_attributes,
};
static const struct iio_info ad9852_info = {
.attrs = &ad9852_attribute_group,
.driver_module = THIS_MODULE,
};
static int __devinit ad9852_probe(struct spi_device *spi)
{
struct ad9852_state *st;
struct iio_dev *idev;
int ret = 0;
idev = iio_allocate_device(sizeof(*st));
if (idev == NULL) {
ret = -ENOMEM;
goto error_ret;
}
st = iio_priv(idev);
spi_set_drvdata(spi, idev);
mutex_init(&st->lock);
st->sdev = spi;
idev->dev.parent = &spi->dev;
idev->info = &ad9852_info;
idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(idev);
if (ret)
goto error_free_dev;
spi->max_speed_hz = 2000000;
spi->mode = SPI_MODE_3;
spi->bits_per_word = 8;
spi_setup(spi);
ad9852_init(st);
return 0;
error_free_dev:
iio_free_device(idev);
error_ret:
return ret;
}
static int __devexit ad9852_remove(struct spi_device *spi)
{
iio_device_unregister(spi_get_drvdata(spi));
iio_free_device(spi_get_drvdata(spi));
return 0;
}
static struct spi_driver ad9852_driver = {
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
},
.probe = ad9852_probe,
.remove = __devexit_p(ad9852_remove),
};
module_spi_driver(ad9852_driver);
MODULE_AUTHOR("Cliff Cai");
MODULE_DESCRIPTION("Analog Devices ad9852 driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:" DRV_NAME);
| gpl-2.0 |
boa19861105/android_442_KitKat_kernel_htc_dlxpul | drivers/net/wireless/b43/tables_nphy.c | 4965 | 137771 | /*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
#include "b43.h"
#include "tables_nphy.h"
#include "phy_common.h"
#include "phy_n.h"
static const u8 b43_ntab_adjustpower0[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 b43_ntab_adjustpower1[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u16 b43_ntab_bdi[] = {
0x0070, 0x0126, 0x012C, 0x0246, 0x048D, 0x04D2,
};
static const u32 b43_ntab_channelest[] = {
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
};
static const u8 b43_ntab_estimatepowerlt0[] = {
0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49,
0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41,
0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39,
0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31,
0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29,
0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21,
0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
};
static const u8 b43_ntab_estimatepowerlt1[] = {
0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49,
0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41,
0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39,
0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31,
0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29,
0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21,
0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
};
static const u8 b43_ntab_framelookup[] = {
0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16,
0x0A, 0x0C, 0x1C, 0x1C, 0x0B, 0x0D, 0x1E, 0x1E,
0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1A, 0x1A,
0x0E, 0x10, 0x20, 0x28, 0x0F, 0x11, 0x22, 0x2A,
};
static const u32 b43_ntab_framestruct[] = {
0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
0x09804506, 0x00100030, 0x09804507, 0x00100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A0C, 0x00100004, 0x01000A0D, 0x00100024,
0x0980450E, 0x00100034, 0x0980450F, 0x00100034,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
0x1980C506, 0x00100030, 0x21810506, 0x00100030,
0x21810506, 0x00100030, 0x01800504, 0x00100030,
0x11808505, 0x00100030, 0x29814507, 0x01100030,
0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
0x21810506, 0x00100030, 0x21810506, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
0x1980C50E, 0x00100038, 0x2181050E, 0x00100038,
0x2181050E, 0x00100038, 0x0180050C, 0x00100038,
0x1180850D, 0x00100038, 0x2981450F, 0x01100038,
0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
0x2181050E, 0x00100038, 0x2181050E, 0x00100038,
0x2981450F, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
0x1980C506, 0x00100030, 0x1980C506, 0x00100030,
0x11808504, 0x00100030, 0x3981CA05, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x10008A04, 0x00100000, 0x3981CA05, 0x00100030,
0x1980C506, 0x00100030, 0x29814507, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028,
0x1980C50E, 0x00100038, 0x1980C50E, 0x00100038,
0x1180850C, 0x00100038, 0x3981CA0D, 0x00100038,
0x2981450F, 0x01100038, 0x00000000, 0x00000000,
0x10008A0C, 0x00100008, 0x3981CA0D, 0x00100038,
0x1980C50E, 0x00100038, 0x2981450F, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x02001405, 0x00100040,
0x0B004A06, 0x01900060, 0x13008A06, 0x01900060,
0x13008A06, 0x01900060, 0x43020A04, 0x00100060,
0x1B00CA05, 0x00100060, 0x23010A07, 0x01500060,
0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
0x13008A06, 0x01900060, 0x13008A06, 0x01900060,
0x23010A07, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x0200140D, 0x00100050,
0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070,
0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070,
0x1B00CA0D, 0x00100070, 0x23010A0F, 0x01500070,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070,
0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x0B004A06, 0x01900060, 0x0B004A06, 0x01900060,
0x5B02CA04, 0x00100060, 0x3B01D405, 0x00100060,
0x23010A07, 0x01500060, 0x00000000, 0x00000000,
0x5802D404, 0x00100000, 0x3B01D405, 0x00100060,
0x0B004A06, 0x01900060, 0x23010A07, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x5002940C, 0x00100010, 0x3201940D, 0x00100050,
0x0B004A0E, 0x01900070, 0x0B004A0E, 0x01900070,
0x5B02CA0C, 0x00100070, 0x3B01D40D, 0x00100070,
0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
0x5802D40C, 0x00100010, 0x3B01D40D, 0x00100070,
0x0B004A0E, 0x01900070, 0x23010A0F, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x000F4800, 0x62031405, 0x00100040,
0x53028A06, 0x01900060, 0x53028A07, 0x01900060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x000F4808, 0x6203140D, 0x00100048,
0x53028A0E, 0x01900068, 0x53028A0F, 0x01900068,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A0C, 0x00100004, 0x11008A0D, 0x00100024,
0x1980C50E, 0x00100034, 0x2181050E, 0x00100034,
0x2181050E, 0x00100034, 0x0180050C, 0x00100038,
0x1180850D, 0x00100038, 0x1181850D, 0x00100038,
0x2981450F, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
0x2181050E, 0x00100038, 0x2181050E, 0x00100038,
0x1181850D, 0x00100038, 0x2981450F, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
0x0180C506, 0x00100030, 0x0180C506, 0x00100030,
0x2180C50C, 0x00100030, 0x49820A0D, 0x0016A130,
0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x2000CA0C, 0x00100000, 0x49820A0D, 0x0016A130,
0x1980C50E, 0x00100030, 0x41824A0D, 0x0016A130,
0x2981450F, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100008, 0x0200140D, 0x00100048,
0x0B004A0E, 0x01900068, 0x13008A0E, 0x01900068,
0x13008A0E, 0x01900068, 0x43020A0C, 0x00100070,
0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070,
0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070,
0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x03004A06, 0x01900060, 0x03004A06, 0x01900060,
0x6B030A0C, 0x00100060, 0x4B02140D, 0x0016A160,
0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x6B03140C, 0x00100060, 0x4B02140D, 0x0016A160,
0x0B004A0E, 0x01900060, 0x4302540D, 0x0016A160,
0x23010A0F, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
0x53028A06, 0x01900060, 0x5B02CA06, 0x01900060,
0x5B02CA06, 0x01900060, 0x43020A04, 0x00100060,
0x1B00CA05, 0x00100060, 0x53028A07, 0x0190C060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x53028A0E, 0x01900070, 0x5B02CA0E, 0x01900070,
0x5B02CA0E, 0x01900070, 0x43020A0C, 0x00100070,
0x1B00CA0D, 0x00100070, 0x53028A0F, 0x0190C070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060,
0x53028A07, 0x0190C060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070,
0x53028A0F, 0x0190C070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_gainctl0[] = {
0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E,
0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42,
0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B,
0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34,
0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E,
0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38,
0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32,
0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44,
0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D,
0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36,
0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40,
0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39,
0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33,
0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D,
0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E,
0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38,
0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42,
0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B,
0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34,
0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44,
0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D,
0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36,
0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30,
0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B,
0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26,
0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22,
0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E,
0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B,
0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00,
};
static const u32 b43_ntab_gainctl1[] = {
0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E,
0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42,
0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B,
0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34,
0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E,
0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38,
0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32,
0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44,
0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D,
0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36,
0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40,
0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39,
0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33,
0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D,
0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E,
0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38,
0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42,
0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B,
0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34,
0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44,
0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D,
0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36,
0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30,
0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B,
0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26,
0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22,
0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E,
0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B,
0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00,
};
static const u32 b43_ntab_intlevel[] = {
0x00802070, 0x0671188D, 0x0A60192C, 0x0A300E46,
0x00C1188D, 0x080024D2, 0x00000070,
};
static const u32 b43_ntab_iqlt0[] = {
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
};
static const u32 b43_ntab_iqlt1[] = {
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
};
static const u16 b43_ntab_loftlt0[] = {
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103,
};
static const u16 b43_ntab_loftlt1[] = {
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103,
};
static const u8 b43_ntab_mcs[] = {
0x00, 0x08, 0x0A, 0x10, 0x12, 0x19, 0x1A, 0x1C,
0x40, 0x48, 0x4A, 0x50, 0x52, 0x59, 0x5A, 0x5C,
0x80, 0x88, 0x8A, 0x90, 0x92, 0x99, 0x9A, 0x9C,
0xC0, 0xC8, 0xCA, 0xD0, 0xD2, 0xD9, 0xDA, 0xDC,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x01, 0x02, 0x04, 0x08, 0x09, 0x0A, 0x0C,
0x10, 0x11, 0x12, 0x14, 0x18, 0x19, 0x1A, 0x1C,
0x20, 0x21, 0x22, 0x24, 0x40, 0x41, 0x42, 0x44,
0x48, 0x49, 0x4A, 0x4C, 0x50, 0x51, 0x52, 0x54,
0x58, 0x59, 0x5A, 0x5C, 0x60, 0x61, 0x62, 0x64,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u32 b43_ntab_noisevar10[] = {
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
};
static const u32 b43_ntab_noisevar11[] = {
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
};
static const u16 b43_ntab_pilot[] = {
0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08,
0xFF08, 0xFF08, 0x80D5, 0x80D5, 0x80D5, 0x80D5,
0x80D5, 0x80D5, 0x80D5, 0x80D5, 0xFF0A, 0xFF82,
0xFFA0, 0xFF28, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
0xFF82, 0xFFA0, 0xFF28, 0xFF0A, 0xFFFF, 0xFFFF,
0xFFFF, 0xFFFF, 0xF83F, 0xFA1F, 0xFA97, 0xFAB5,
0xF2BD, 0xF0BF, 0xFFFF, 0xFFFF, 0xF017, 0xF815,
0xF215, 0xF095, 0xF035, 0xF01D, 0xFFFF, 0xFFFF,
0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xFF08, 0xFF02,
0xFF80, 0xFF20, 0xF01F, 0xF817, 0xFA15, 0xF295,
0xF0B5, 0xF03D, 0xFFFF, 0xFFFF, 0xF82A, 0xFA0A,
0xFA82, 0xFAA0, 0xF2A8, 0xF0AA, 0xFFFF, 0xFFFF,
0xF002, 0xF800, 0xF200, 0xF080, 0xF020, 0xF008,
0xFFFF, 0xFFFF, 0xF00A, 0xF802, 0xFA00, 0xF280,
0xF0A0, 0xF028, 0xFFFF, 0xFFFF,
};
static const u32 b43_ntab_pilotlt[] = {
0x76540123, 0x62407351, 0x76543201, 0x76540213,
0x76540123, 0x76430521,
};
static const u32 b43_ntab_tdi20a0[] = {
0x00091226, 0x000A1429, 0x000B56AD, 0x000C58B0,
0x000D5AB3, 0x000E9CB6, 0x000F9EBA, 0x0000C13D,
0x00020301, 0x00030504, 0x00040708, 0x0005090B,
0x00064B8E, 0x00095291, 0x000A5494, 0x000B9718,
0x000C9927, 0x000D9B2A, 0x000EDD2E, 0x000FDF31,
0x000101B4, 0x000243B7, 0x000345BB, 0x000447BE,
0x00058982, 0x00068C05, 0x00099309, 0x000A950C,
0x000BD78F, 0x000CD992, 0x000DDB96, 0x000F1D99,
0x00005FA8, 0x0001422C, 0x0002842F, 0x00038632,
0x00048835, 0x0005CA38, 0x0006CCBC, 0x0009D3BF,
0x000B1603, 0x000C1806, 0x000D1A0A, 0x000E1C0D,
0x000F5E10, 0x00008093, 0x00018297, 0x0002C49A,
0x0003C680, 0x0004C880, 0x00060B00, 0x00070D00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi20a1[] = {
0x00014B26, 0x00028D29, 0x000393AD, 0x00049630,
0x0005D833, 0x0006DA36, 0x00099C3A, 0x000A9E3D,
0x000BC081, 0x000CC284, 0x000DC488, 0x000F068B,
0x0000488E, 0x00018B91, 0x0002D214, 0x0003D418,
0x0004D6A7, 0x000618AA, 0x00071AAE, 0x0009DCB1,
0x000B1EB4, 0x000C0137, 0x000D033B, 0x000E053E,
0x000F4702, 0x00008905, 0x00020C09, 0x0003128C,
0x0004148F, 0x00051712, 0x00065916, 0x00091B19,
0x000A1D28, 0x000B5F2C, 0x000C41AF, 0x000D43B2,
0x000E85B5, 0x000F87B8, 0x0000C9BC, 0x00024CBF,
0x00035303, 0x00045506, 0x0005978A, 0x0006998D,
0x00095B90, 0x000A5D93, 0x000B9F97, 0x000C821A,
0x000D8400, 0x000EC600, 0x000FC800, 0x00010A00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a0[] = {
0x0011A346, 0x00136CCF, 0x0014F5D9, 0x001641E2,
0x0017CB6B, 0x00195475, 0x001B2383, 0x001CAD0C,
0x001E7616, 0x0000821F, 0x00020BA8, 0x0003D4B2,
0x00056447, 0x00072DD0, 0x0008B6DA, 0x000A02E3,
0x000B8C6C, 0x000D15F6, 0x0011E484, 0x0013AE0D,
0x00153717, 0x00168320, 0x00180CA9, 0x00199633,
0x001B6548, 0x001CEED1, 0x001EB7DB, 0x0000C3E4,
0x00024D6D, 0x000416F7, 0x0005A585, 0x00076F0F,
0x0008F818, 0x000A4421, 0x000BCDAB, 0x000D9734,
0x00122649, 0x0013EFD2, 0x001578DC, 0x0016C4E5,
0x00184E6E, 0x001A17F8, 0x001BA686, 0x001D3010,
0x001EF999, 0x00010522, 0x00028EAC, 0x00045835,
0x0005E74A, 0x0007B0D3, 0x00093A5D, 0x000A85E6,
0x000C0F6F, 0x000DD8F9, 0x00126787, 0x00143111,
0x0015BA9A, 0x00170623, 0x00188FAD, 0x001A5936,
0x001BE84B, 0x001DB1D4, 0x001F3B5E, 0x000146E7,
0x00031070, 0x000499FA, 0x00062888, 0x0007F212,
0x00097B9B, 0x000AC7A4, 0x000C50AE, 0x000E1A37,
0x0012A94C, 0x001472D5, 0x0015FC5F, 0x00174868,
0x0018D171, 0x001A9AFB, 0x001C2989, 0x001DF313,
0x001F7C9C, 0x000188A5, 0x000351AF, 0x0004DB38,
0x0006AA4D, 0x000833D7, 0x0009BD60, 0x000B0969,
0x000C9273, 0x000E5BFC, 0x00132A8A, 0x0014B414,
0x00163D9D, 0x001789A6, 0x001912B0, 0x001ADC39,
0x001C6BCE, 0x001E34D8, 0x001FBE61, 0x0001CA6A,
0x00039374, 0x00051CFD, 0x0006EC0B, 0x00087515,
0x0009FE9E, 0x000B4AA7, 0x000CD3B1, 0x000E9D3A,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a1[] = {
0x001EDB36, 0x000129CA, 0x0002B353, 0x00047CDD,
0x0005C8E6, 0x000791EF, 0x00091BF9, 0x000AAA07,
0x000C3391, 0x000DFD1A, 0x00120923, 0x0013D22D,
0x00155C37, 0x0016EACB, 0x00187454, 0x001A3DDE,
0x001B89E7, 0x001D12F0, 0x001F1CFA, 0x00016B88,
0x00033492, 0x0004BE1B, 0x00060A24, 0x0007D32E,
0x00095D38, 0x000AEC4C, 0x000C7555, 0x000E3EDF,
0x00124AE8, 0x001413F1, 0x0015A37B, 0x00172C89,
0x0018B593, 0x001A419C, 0x001BCB25, 0x001D942F,
0x001F63B9, 0x0001AD4D, 0x00037657, 0x0004C260,
0x00068BE9, 0x000814F3, 0x0009A47C, 0x000B2D8A,
0x000CB694, 0x000E429D, 0x00128C26, 0x001455B0,
0x0015E4BA, 0x00176E4E, 0x0018F758, 0x001A8361,
0x001C0CEA, 0x001DD674, 0x001FA57D, 0x0001EE8B,
0x0003B795, 0x0005039E, 0x0006CD27, 0x000856B1,
0x0009E5C6, 0x000B6F4F, 0x000CF859, 0x000E8462,
0x00130DEB, 0x00149775, 0x00162603, 0x0017AF8C,
0x00193896, 0x001AC49F, 0x001C4E28, 0x001E17B2,
0x0000A6C7, 0x00023050, 0x0003F9DA, 0x00054563,
0x00070EEC, 0x00089876, 0x000A2704, 0x000BB08D,
0x000D3A17, 0x001185A0, 0x00134F29, 0x0014D8B3,
0x001667C8, 0x0017F151, 0x00197ADB, 0x001B0664,
0x001C8FED, 0x001E5977, 0x0000E805, 0x0002718F,
0x00043B18, 0x000586A1, 0x0007502B, 0x0008D9B4,
0x000A68C9, 0x000BF252, 0x000DBBDC, 0x0011C7E5,
0x001390EE, 0x00151A78, 0x0016A906, 0x00183290,
0x0019BC19, 0x001B4822, 0x001CD12C, 0x001E9AB5,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdtrn[] = {
0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6,
0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68,
0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52,
0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050,
0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6,
0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68,
0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52,
0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050,
0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246,
0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C,
0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61,
0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D,
0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246,
0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C,
0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61,
0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D,
0xFA58FA58, 0xF895043B, 0xFF4C09C0, 0xFBC6FFA8,
0xFB84F384, 0x0798F6F9, 0x05760122, 0x058409F6,
0x0B500000, 0x05B7F542, 0x08860432, 0x06DDFEE7,
0xFB84F384, 0xF9D90664, 0xF7E8025C, 0x00FFF7BD,
0x05A805A8, 0xF7BD00FF, 0x025CF7E8, 0x0664F9D9,
0xF384FB84, 0xFEE706DD, 0x04320886, 0xF54205B7,
0x00000B50, 0x09F60584, 0x01220576, 0xF6F90798,
0xF384FB84, 0xFFA8FBC6, 0x09C0FF4C, 0x043BF895,
0x02D402D4, 0x07DE0270, 0xFC96079C, 0xF90AFE94,
0xFE00FF2C, 0x02D4065D, 0x092A0096, 0x0014FBB8,
0xFD2CFD2C, 0x076AFB3C, 0x0096F752, 0xF991FD87,
0xFB2C0200, 0xFEB8F960, 0x08E0FC96, 0x049802A8,
0xFD2CFD2C, 0x02A80498, 0xFC9608E0, 0xF960FEB8,
0x0200FB2C, 0xFD87F991, 0xF7520096, 0xFB3C076A,
0xFD2CFD2C, 0xFBB80014, 0x0096092A, 0x065D02D4,
0xFF2CFE00, 0xFE94F90A, 0x079CFC96, 0x027007DE,
0x02D402D4, 0x027007DE, 0x079CFC96, 0xFE94F90A,
0xFF2CFE00, 0x065D02D4, 0x0096092A, 0xFBB80014,
0xFD2CFD2C, 0xFB3C076A, 0xF7520096, 0xFD87F991,
0x0200FB2C, 0xF960FEB8, 0xFC9608E0, 0x02A80498,
0xFD2CFD2C, 0x049802A8, 0x08E0FC96, 0xFEB8F960,
0xFB2C0200, 0xF991FD87, 0x0096F752, 0x076AFB3C,
0xFD2CFD2C, 0x0014FBB8, 0x092A0096, 0x02D4065D,
0xFE00FF2C, 0xF90AFE94, 0xFC96079C, 0x07DE0270,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D,
0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF,
0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8,
0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7,
0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3,
0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841,
0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608,
0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759,
0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D,
0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF,
0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8,
0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7,
0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3,
0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841,
0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608,
0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759,
0x061C061C, 0xFF30009D, 0xFFB21141, 0xFD87FB54,
0xF65DFE59, 0x02EEF99E, 0x0166F03C, 0xFFF809B6,
0x000008A4, 0x000AF42B, 0x00EFF577, 0xFA840BF2,
0xFC02FF51, 0x08260F67, 0xFFF0036F, 0x0842F9C3,
0x00000000, 0x063DF7BE, 0xFC910010, 0xF099F7DA,
0x00AF03FE, 0xF40E057C, 0x0A89FF11, 0x0BD5FFF6,
0xF75C0000, 0xF64A0008, 0x0FC4FE9A, 0x0662FD12,
0x01A709A3, 0x04AC0279, 0xEEBF004E, 0xFF6300D0,
0xF9E4F9E4, 0x00D0FF63, 0x004EEEBF, 0x027904AC,
0x09A301A7, 0xFD120662, 0xFE9A0FC4, 0x0008F64A,
0x0000F75C, 0xFFF60BD5, 0xFF110A89, 0x057CF40E,
0x03FE00AF, 0xF7DAF099, 0x0010FC91, 0xF7BE063D,
0x00000000, 0xF9C30842, 0x036FFFF0, 0x0F670826,
0xFF51FC02, 0x0BF2FA84, 0xF57700EF, 0xF42B000A,
0x08A40000, 0x09B6FFF8, 0xF03C0166, 0xF99E02EE,
0xFE59F65D, 0xFB54FD87, 0x1141FFB2, 0x009DFF30,
0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59,
0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766,
0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986,
0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB,
0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7,
0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A,
0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A,
0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705,
0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59,
0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766,
0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986,
0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB,
0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7,
0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A,
0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A,
0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705,
0xFA58FA58, 0xF8F0FE00, 0x0448073D, 0xFDC9FE46,
0xF9910258, 0x089D0407, 0xFD5CF71A, 0x02AFFDE0,
0x083E0496, 0xFF5A0740, 0xFF7AFD97, 0x00FE01F1,
0x0009082E, 0xFA94FF75, 0xFECDF8EA, 0xFFB0F693,
0xFD2CFA58, 0x0433FF16, 0xFBA405DD, 0xFA610341,
0x06A606CB, 0x0039FD2D, 0x0677FA97, 0x01FA05E0,
0xF896003E, 0x075A068B, 0x012CFC3E, 0xFA23F98D,
0xFC7CFD43, 0xFF90FC0D, 0x01C10982, 0x00C601D6,
0xFD2CFD2C, 0x01D600C6, 0x098201C1, 0xFC0DFF90,
0xFD43FC7C, 0xF98DFA23, 0xFC3E012C, 0x068B075A,
0x003EF896, 0x05E001FA, 0xFA970677, 0xFD2D0039,
0x06CB06A6, 0x0341FA61, 0x05DDFBA4, 0xFF160433,
0xFA58FD2C, 0xF693FFB0, 0xF8EAFECD, 0xFF75FA94,
0x082E0009, 0x01F100FE, 0xFD97FF7A, 0x0740FF5A,
0x0496083E, 0xFDE002AF, 0xF71AFD5C, 0x0407089D,
0x0258F991, 0xFE46FDC9, 0x073D0448, 0xFE00F8F0,
0xFD2CFD2C, 0xFCE00500, 0xFC09FDDC, 0xFE680157,
0x04C70571, 0xFC3AFF21, 0xFCD70228, 0x056D0277,
0x0200FE00, 0x0022F927, 0xFE3C032B, 0xFC44FF3C,
0x03E9FBDB, 0x04570313, 0x04C9FF5C, 0x000D03B8,
0xFA580000, 0xFBE900D2, 0xF9D0FE0B, 0x0125FDF9,
0x042501BF, 0x0328FA2B, 0xFFA902F0, 0xFA250157,
0x0200FE00, 0x03740438, 0xFF0405FD, 0x030CFE52,
0x0037FB39, 0xFF6904C5, 0x04F8FD23, 0xFD31FC1B,
0xFD2CFD2C, 0xFC1BFD31, 0xFD2304F8, 0x04C5FF69,
0xFB390037, 0xFE52030C, 0x05FDFF04, 0x04380374,
0xFE000200, 0x0157FA25, 0x02F0FFA9, 0xFA2B0328,
0x01BF0425, 0xFDF90125, 0xFE0BF9D0, 0x00D2FBE9,
0x0000FA58, 0x03B8000D, 0xFF5C04C9, 0x03130457,
0xFBDB03E9, 0xFF3CFC44, 0x032BFE3C, 0xF9270022,
0xFE000200, 0x0277056D, 0x0228FCD7, 0xFF21FC3A,
0x057104C7, 0x0157FE68, 0xFDDCFC09, 0x0500FCE0,
0xFD2CFD2C, 0x0500FCE0, 0xFDDCFC09, 0x0157FE68,
0x057104C7, 0xFF21FC3A, 0x0228FCD7, 0x0277056D,
0xFE000200, 0xF9270022, 0x032BFE3C, 0xFF3CFC44,
0xFBDB03E9, 0x03130457, 0xFF5C04C9, 0x03B8000D,
0x0000FA58, 0x00D2FBE9, 0xFE0BF9D0, 0xFDF90125,
0x01BF0425, 0xFA2B0328, 0x02F0FFA9, 0x0157FA25,
0xFE000200, 0x04380374, 0x05FDFF04, 0xFE52030C,
0xFB390037, 0x04C5FF69, 0xFD2304F8, 0xFC1BFD31,
0xFD2CFD2C, 0xFD31FC1B, 0x04F8FD23, 0xFF6904C5,
0x0037FB39, 0x030CFE52, 0xFF0405FD, 0x03740438,
0x0200FE00, 0xFA250157, 0xFFA902F0, 0x0328FA2B,
0x042501BF, 0x0125FDF9, 0xF9D0FE0B, 0xFBE900D2,
0xFA580000, 0x000D03B8, 0x04C9FF5C, 0x04570313,
0x03E9FBDB, 0xFC44FF3C, 0xFE3C032B, 0x0022F927,
0x0200FE00, 0x056D0277, 0xFCD70228, 0xFC3AFF21,
0x04C70571, 0xFE680157, 0xFC09FDDC, 0xFCE00500,
0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E,
0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C,
0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926,
0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942,
0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382,
0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4,
0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA,
0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE,
0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E,
0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C,
0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926,
0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942,
0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382,
0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4,
0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA,
0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE,
};
static const u32 b43_ntab_tmap[] = {
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0xF1111110, 0x11111111, 0x11F11111, 0x00000111,
0x11000000, 0x1111F111, 0x11111111, 0x111111F1,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x000AA888,
0x88880000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA2222220, 0x22222222, 0x22C22222, 0x00000222,
0x22000000, 0x2222A222, 0x22222222, 0x222222A2,
0xF1111110, 0x11111111, 0x11F11111, 0x00011111,
0x11110000, 0x1111F111, 0x11111111, 0x111111F1,
0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00088AAA,
0xAAAA0000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
0xAAA8AAA0, 0x8AAA8AAA, 0xAA8A8A8A, 0x000AAA88,
0x8AAA0000, 0xAAA8A888, 0x8AA88A8A, 0x8A88A888,
0x08080A00, 0x0A08080A, 0x080A0A08, 0x00080808,
0x080A0000, 0x080A0808, 0x080A0808, 0x0A0A0A08,
0xA0A0A0A0, 0x80A0A080, 0x8080A0A0, 0x00008080,
0x80A00000, 0x80A080A0, 0xA080A0A0, 0x8080A0A0,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x99999000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888,
0x22000000, 0x2222B222, 0x22222222, 0x222222B2,
0xB2222220, 0x22222222, 0x22D22222, 0x00000222,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x33000000, 0x3333B333, 0x33333333, 0x333333B3,
0xB3333330, 0x33333333, 0x33D33333, 0x00000333,
0x22000000, 0x2222A222, 0x22222222, 0x222222A2,
0xA2222220, 0x22222222, 0x22C22222, 0x00000222,
0x99B99B00, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
0x9B99BB99, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888,
0x22222200, 0x2222F222, 0x22222222, 0x222222F2,
0x22222222, 0x22222222, 0x22F22222, 0x00000222,
0x11000000, 0x1111F111, 0x11111111, 0x11111111,
0xF1111111, 0x11111111, 0x11F11111, 0x01111111,
0xBB9BB900, 0xB9B9BB99, 0xB99BBBBB, 0xBBBB9B9B,
0xB9BB99BB, 0xB99999B9, 0xB9B9B99B, 0x00000BBB,
0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
0xA8AA88AA, 0xA88888A8, 0xA8A8A88A, 0x0A888AAA,
0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00000AAA,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0xBBBBBB00, 0x999BBBBB, 0x9BB99B9B, 0xB9B9B9BB,
0xB9B99BBB, 0xB9B9B9BB, 0xB9BB9B99, 0x00000999,
0x8A000000, 0xAA88A888, 0xA88888AA, 0xA88A8A88,
0xA88AA88A, 0x88A8AAAA, 0xA8AA8AAA, 0x0888A88A,
0x0B0B0B00, 0x090B0B0B, 0x0B090B0B, 0x0909090B,
0x09090B0B, 0x09090B0B, 0x09090B09, 0x00000909,
0x0A000000, 0x0A080808, 0x080A080A, 0x080A0A08,
0x080A080A, 0x0808080A, 0x0A0A0A08, 0x0808080A,
0xB0B0B000, 0x9090B0B0, 0x90B09090, 0xB0B0B090,
0xB0B090B0, 0x90B0B0B0, 0xB0B09090, 0x00000090,
0x80000000, 0xA080A080, 0xA08080A0, 0xA0808080,
0xA080A080, 0x80A0A0A0, 0xA0A080A0, 0x00A0A0A0,
0x22000000, 0x2222F222, 0x22222222, 0x222222F2,
0xF2222220, 0x22222222, 0x22F22222, 0x00000222,
0x11000000, 0x1111F111, 0x11111111, 0x111111F1,
0xF1111110, 0x11111111, 0x11F11111, 0x00000111,
0x33000000, 0x3333F333, 0x33333333, 0x333333F3,
0xF3333330, 0x33333333, 0x33F33333, 0x00000333,
0x22000000, 0x2222F222, 0x22222222, 0x222222F2,
0xF2222220, 0x22222222, 0x22F22222, 0x00000222,
0x99000000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88888000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888,
0x88A88A00, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
/* static tables, PHY revision >= 3 */
static const u32 b43_ntab_framestruct_r3[] = {
0x08004a04, 0x00100000, 0x01000a05, 0x00100020,
0x09804506, 0x00100030, 0x09804507, 0x00100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a0c, 0x00100004, 0x01000a0d, 0x00100024,
0x0980450e, 0x00100034, 0x0980450f, 0x00100034,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a04, 0x00100000, 0x11008a05, 0x00100020,
0x1980c506, 0x00100030, 0x21810506, 0x00100030,
0x21810506, 0x00100030, 0x01800504, 0x00100030,
0x11808505, 0x00100030, 0x29814507, 0x01100030,
0x00000a04, 0x00100000, 0x11008a05, 0x00100020,
0x21810506, 0x00100030, 0x21810506, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028,
0x1980c50e, 0x00100038, 0x2181050e, 0x00100038,
0x2181050e, 0x00100038, 0x0180050c, 0x00100038,
0x1180850d, 0x00100038, 0x2981450f, 0x01100038,
0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028,
0x2181050e, 0x00100038, 0x2181050e, 0x00100038,
0x2981450f, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a04, 0x00100000, 0x01000a05, 0x00100020,
0x1980c506, 0x00100030, 0x1980c506, 0x00100030,
0x11808504, 0x00100030, 0x3981ca05, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x10008a04, 0x00100000, 0x3981ca05, 0x00100030,
0x1980c506, 0x00100030, 0x29814507, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a0c, 0x00100008, 0x01000a0d, 0x00100028,
0x1980c50e, 0x00100038, 0x1980c50e, 0x00100038,
0x1180850c, 0x00100038, 0x3981ca0d, 0x00100038,
0x2981450f, 0x01100038, 0x00000000, 0x00000000,
0x10008a0c, 0x00100008, 0x3981ca0d, 0x00100038,
0x1980c50e, 0x00100038, 0x2981450f, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x02001405, 0x00100040,
0x0b004a06, 0x01900060, 0x13008a06, 0x01900060,
0x13008a06, 0x01900060, 0x43020a04, 0x00100060,
0x1b00ca05, 0x00100060, 0x23010a07, 0x01500060,
0x40021404, 0x00100000, 0x1a00d405, 0x00100040,
0x13008a06, 0x01900060, 0x13008a06, 0x01900060,
0x23010a07, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x0200140d, 0x00100050,
0x0b004a0e, 0x01900070, 0x13008a0e, 0x01900070,
0x13008a0e, 0x01900070, 0x43020a0c, 0x00100070,
0x1b00ca0d, 0x00100070, 0x23010a0f, 0x01500070,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070,
0x23010a0f, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x0b004a06, 0x01900060, 0x0b004a06, 0x01900060,
0x5b02ca04, 0x00100060, 0x3b01d405, 0x00100060,
0x23010a07, 0x01500060, 0x00000000, 0x00000000,
0x5802d404, 0x00100000, 0x3b01d405, 0x00100060,
0x0b004a06, 0x01900060, 0x23010a07, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x5002940c, 0x00100010, 0x3201940d, 0x00100050,
0x0b004a0e, 0x01900070, 0x0b004a0e, 0x01900070,
0x5b02ca0c, 0x00100070, 0x3b01d40d, 0x00100070,
0x23010a0f, 0x01500070, 0x00000000, 0x00000000,
0x5802d40c, 0x00100010, 0x3b01d40d, 0x00100070,
0x0b004a0e, 0x01900070, 0x23010a0f, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x000f4800, 0x62031405, 0x00100040,
0x53028a06, 0x01900060, 0x53028a07, 0x01900060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x000f4808, 0x6203140d, 0x00100048,
0x53028a0e, 0x01900068, 0x53028a0f, 0x01900068,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a0c, 0x00100004, 0x11008a0d, 0x00100024,
0x1980c50e, 0x00100034, 0x2181050e, 0x00100034,
0x2181050e, 0x00100034, 0x0180050c, 0x00100038,
0x1180850d, 0x00100038, 0x1181850d, 0x00100038,
0x2981450f, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028,
0x2181050e, 0x00100038, 0x2181050e, 0x00100038,
0x1181850d, 0x00100038, 0x2981450f, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a04, 0x00100000, 0x01000a05, 0x00100020,
0x0180c506, 0x00100030, 0x0180c506, 0x00100030,
0x2180c50c, 0x00100030, 0x49820a0d, 0x0016a130,
0x41824a0d, 0x0016a130, 0x2981450f, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x2000ca0c, 0x00100000, 0x49820a0d, 0x0016a130,
0x1980c50e, 0x00100030, 0x41824a0d, 0x0016a130,
0x2981450f, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100008, 0x0200140d, 0x00100048,
0x0b004a0e, 0x01900068, 0x13008a0e, 0x01900068,
0x13008a0e, 0x01900068, 0x43020a0c, 0x00100070,
0x1b00ca0d, 0x00100070, 0x1b014a0d, 0x00100070,
0x23010a0f, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070,
0x1b014a0d, 0x00100070, 0x23010a0f, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x03004a06, 0x01900060, 0x03004a06, 0x01900060,
0x6b030a0c, 0x00100060, 0x4b02140d, 0x0016a160,
0x4302540d, 0x0016a160, 0x23010a0f, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x6b03140c, 0x00100060, 0x4b02140d, 0x0016a160,
0x0b004a0e, 0x01900060, 0x4302540d, 0x0016a160,
0x23010a0f, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1a00d405, 0x00100040,
0x53028a06, 0x01900060, 0x5b02ca06, 0x01900060,
0x5b02ca06, 0x01900060, 0x43020a04, 0x00100060,
0x1b00ca05, 0x00100060, 0x53028a07, 0x0190c060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x53028a0e, 0x01900070, 0x5b02ca0e, 0x01900070,
0x5b02ca0e, 0x01900070, 0x43020a0c, 0x00100070,
0x1b00ca0d, 0x00100070, 0x53028a0f, 0x0190c070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1a00d405, 0x00100040,
0x5b02ca06, 0x01900060, 0x5b02ca06, 0x01900060,
0x53028a07, 0x0190c060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x5b02ca0e, 0x01900070, 0x5b02ca0e, 0x01900070,
0x53028a0f, 0x0190c070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u16 b43_ntab_pilot_r3[] = {
0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08,
0xff08, 0xff08, 0x80d5, 0x80d5, 0x80d5, 0x80d5,
0x80d5, 0x80d5, 0x80d5, 0x80d5, 0xff0a, 0xff82,
0xffa0, 0xff28, 0xffff, 0xffff, 0xffff, 0xffff,
0xff82, 0xffa0, 0xff28, 0xff0a, 0xffff, 0xffff,
0xffff, 0xffff, 0xf83f, 0xfa1f, 0xfa97, 0xfab5,
0xf2bd, 0xf0bf, 0xffff, 0xffff, 0xf017, 0xf815,
0xf215, 0xf095, 0xf035, 0xf01d, 0xffff, 0xffff,
0xff08, 0xff02, 0xff80, 0xff20, 0xff08, 0xff02,
0xff80, 0xff20, 0xf01f, 0xf817, 0xfa15, 0xf295,
0xf0b5, 0xf03d, 0xffff, 0xffff, 0xf82a, 0xfa0a,
0xfa82, 0xfaa0, 0xf2a8, 0xf0aa, 0xffff, 0xffff,
0xf002, 0xf800, 0xf200, 0xf080, 0xf020, 0xf008,
0xffff, 0xffff, 0xf00a, 0xf802, 0xfa00, 0xf280,
0xf0a0, 0xf028, 0xffff, 0xffff,
};
static const u32 b43_ntab_tmap_r3[] = {
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0xf1111110, 0x11111111, 0x11f11111, 0x00000111,
0x11000000, 0x1111f111, 0x11111111, 0x111111f1,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888,
0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa2222220, 0x22222222, 0x22c22222, 0x00000222,
0x22000000, 0x2222a222, 0x22222222, 0x222222a2,
0xf1111110, 0x11111111, 0x11f11111, 0x00011111,
0x11110000, 0x1111f111, 0x11111111, 0x111111f1,
0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa,
0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a,
0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88,
0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888,
0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808,
0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08,
0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080,
0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9,
0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888,
0x22000000, 0x2222b222, 0x22222222, 0x222222b2,
0xb2222220, 0x22222222, 0x22d22222, 0x00000222,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x33000000, 0x3333b333, 0x33333333, 0x333333b3,
0xb3333330, 0x33333333, 0x33d33333, 0x00000333,
0x22000000, 0x2222a222, 0x22222222, 0x222222a2,
0xa2222220, 0x22222222, 0x22c22222, 0x00000222,
0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9,
0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888,
0x22222200, 0x2222f222, 0x22222222, 0x222222f2,
0x22222222, 0x22222222, 0x22f22222, 0x00000222,
0x11000000, 0x1111f111, 0x11111111, 0x11111111,
0xf1111111, 0x11111111, 0x11f11111, 0x01111111,
0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b,
0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb,
0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a,
0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa,
0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a,
0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb,
0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999,
0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88,
0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a,
0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b,
0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909,
0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08,
0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a,
0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090,
0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090,
0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080,
0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0,
0x22000000, 0x2222f222, 0x22222222, 0x222222f2,
0xf2222220, 0x22222222, 0x22f22222, 0x00000222,
0x11000000, 0x1111f111, 0x11111111, 0x111111f1,
0xf1111110, 0x11111111, 0x11f11111, 0x00000111,
0x33000000, 0x3333f333, 0x33333333, 0x333333f3,
0xf3333330, 0x33333333, 0x33f33333, 0x00000333,
0x22000000, 0x2222f222, 0x22222222, 0x222222f2,
0xf2222220, 0x22222222, 0x22f22222, 0x00000222,
0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9,
0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888,
0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_intlevel_r3[] = {
0x00802070, 0x0671188d, 0x0a60192c, 0x0a300e46,
0x00c1188d, 0x080024d2, 0x00000070,
};
static const u32 b43_ntab_tdtrn_r3[] = {
0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6,
0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68,
0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52,
0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050,
0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6,
0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68,
0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52,
0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050,
0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246,
0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c,
0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61,
0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d,
0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246,
0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c,
0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61,
0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d,
0xfa58fa58, 0xf895043b, 0xff4c09c0, 0xfbc6ffa8,
0xfb84f384, 0x0798f6f9, 0x05760122, 0x058409f6,
0x0b500000, 0x05b7f542, 0x08860432, 0x06ddfee7,
0xfb84f384, 0xf9d90664, 0xf7e8025c, 0x00fff7bd,
0x05a805a8, 0xf7bd00ff, 0x025cf7e8, 0x0664f9d9,
0xf384fb84, 0xfee706dd, 0x04320886, 0xf54205b7,
0x00000b50, 0x09f60584, 0x01220576, 0xf6f90798,
0xf384fb84, 0xffa8fbc6, 0x09c0ff4c, 0x043bf895,
0x02d402d4, 0x07de0270, 0xfc96079c, 0xf90afe94,
0xfe00ff2c, 0x02d4065d, 0x092a0096, 0x0014fbb8,
0xfd2cfd2c, 0x076afb3c, 0x0096f752, 0xf991fd87,
0xfb2c0200, 0xfeb8f960, 0x08e0fc96, 0x049802a8,
0xfd2cfd2c, 0x02a80498, 0xfc9608e0, 0xf960feb8,
0x0200fb2c, 0xfd87f991, 0xf7520096, 0xfb3c076a,
0xfd2cfd2c, 0xfbb80014, 0x0096092a, 0x065d02d4,
0xff2cfe00, 0xfe94f90a, 0x079cfc96, 0x027007de,
0x02d402d4, 0x027007de, 0x079cfc96, 0xfe94f90a,
0xff2cfe00, 0x065d02d4, 0x0096092a, 0xfbb80014,
0xfd2cfd2c, 0xfb3c076a, 0xf7520096, 0xfd87f991,
0x0200fb2c, 0xf960feb8, 0xfc9608e0, 0x02a80498,
0xfd2cfd2c, 0x049802a8, 0x08e0fc96, 0xfeb8f960,
0xfb2c0200, 0xf991fd87, 0x0096f752, 0x076afb3c,
0xfd2cfd2c, 0x0014fbb8, 0x092a0096, 0x02d4065d,
0xfe00ff2c, 0xf90afe94, 0xfc96079c, 0x07de0270,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d,
0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf,
0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8,
0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7,
0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3,
0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841,
0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608,
0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759,
0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d,
0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf,
0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8,
0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7,
0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3,
0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841,
0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608,
0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759,
0x061c061c, 0xff30009d, 0xffb21141, 0xfd87fb54,
0xf65dfe59, 0x02eef99e, 0x0166f03c, 0xfff809b6,
0x000008a4, 0x000af42b, 0x00eff577, 0xfa840bf2,
0xfc02ff51, 0x08260f67, 0xfff0036f, 0x0842f9c3,
0x00000000, 0x063df7be, 0xfc910010, 0xf099f7da,
0x00af03fe, 0xf40e057c, 0x0a89ff11, 0x0bd5fff6,
0xf75c0000, 0xf64a0008, 0x0fc4fe9a, 0x0662fd12,
0x01a709a3, 0x04ac0279, 0xeebf004e, 0xff6300d0,
0xf9e4f9e4, 0x00d0ff63, 0x004eeebf, 0x027904ac,
0x09a301a7, 0xfd120662, 0xfe9a0fc4, 0x0008f64a,
0x0000f75c, 0xfff60bd5, 0xff110a89, 0x057cf40e,
0x03fe00af, 0xf7daf099, 0x0010fc91, 0xf7be063d,
0x00000000, 0xf9c30842, 0x036ffff0, 0x0f670826,
0xff51fc02, 0x0bf2fa84, 0xf57700ef, 0xf42b000a,
0x08a40000, 0x09b6fff8, 0xf03c0166, 0xf99e02ee,
0xfe59f65d, 0xfb54fd87, 0x1141ffb2, 0x009dff30,
0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59,
0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766,
0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986,
0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb,
0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7,
0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a,
0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a,
0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705,
0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59,
0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766,
0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986,
0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb,
0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7,
0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a,
0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a,
0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705,
0xfa58fa58, 0xf8f0fe00, 0x0448073d, 0xfdc9fe46,
0xf9910258, 0x089d0407, 0xfd5cf71a, 0x02affde0,
0x083e0496, 0xff5a0740, 0xff7afd97, 0x00fe01f1,
0x0009082e, 0xfa94ff75, 0xfecdf8ea, 0xffb0f693,
0xfd2cfa58, 0x0433ff16, 0xfba405dd, 0xfa610341,
0x06a606cb, 0x0039fd2d, 0x0677fa97, 0x01fa05e0,
0xf896003e, 0x075a068b, 0x012cfc3e, 0xfa23f98d,
0xfc7cfd43, 0xff90fc0d, 0x01c10982, 0x00c601d6,
0xfd2cfd2c, 0x01d600c6, 0x098201c1, 0xfc0dff90,
0xfd43fc7c, 0xf98dfa23, 0xfc3e012c, 0x068b075a,
0x003ef896, 0x05e001fa, 0xfa970677, 0xfd2d0039,
0x06cb06a6, 0x0341fa61, 0x05ddfba4, 0xff160433,
0xfa58fd2c, 0xf693ffb0, 0xf8eafecd, 0xff75fa94,
0x082e0009, 0x01f100fe, 0xfd97ff7a, 0x0740ff5a,
0x0496083e, 0xfde002af, 0xf71afd5c, 0x0407089d,
0x0258f991, 0xfe46fdc9, 0x073d0448, 0xfe00f8f0,
0xfd2cfd2c, 0xfce00500, 0xfc09fddc, 0xfe680157,
0x04c70571, 0xfc3aff21, 0xfcd70228, 0x056d0277,
0x0200fe00, 0x0022f927, 0xfe3c032b, 0xfc44ff3c,
0x03e9fbdb, 0x04570313, 0x04c9ff5c, 0x000d03b8,
0xfa580000, 0xfbe900d2, 0xf9d0fe0b, 0x0125fdf9,
0x042501bf, 0x0328fa2b, 0xffa902f0, 0xfa250157,
0x0200fe00, 0x03740438, 0xff0405fd, 0x030cfe52,
0x0037fb39, 0xff6904c5, 0x04f8fd23, 0xfd31fc1b,
0xfd2cfd2c, 0xfc1bfd31, 0xfd2304f8, 0x04c5ff69,
0xfb390037, 0xfe52030c, 0x05fdff04, 0x04380374,
0xfe000200, 0x0157fa25, 0x02f0ffa9, 0xfa2b0328,
0x01bf0425, 0xfdf90125, 0xfe0bf9d0, 0x00d2fbe9,
0x0000fa58, 0x03b8000d, 0xff5c04c9, 0x03130457,
0xfbdb03e9, 0xff3cfc44, 0x032bfe3c, 0xf9270022,
0xfe000200, 0x0277056d, 0x0228fcd7, 0xff21fc3a,
0x057104c7, 0x0157fe68, 0xfddcfc09, 0x0500fce0,
0xfd2cfd2c, 0x0500fce0, 0xfddcfc09, 0x0157fe68,
0x057104c7, 0xff21fc3a, 0x0228fcd7, 0x0277056d,
0xfe000200, 0xf9270022, 0x032bfe3c, 0xff3cfc44,
0xfbdb03e9, 0x03130457, 0xff5c04c9, 0x03b8000d,
0x0000fa58, 0x00d2fbe9, 0xfe0bf9d0, 0xfdf90125,
0x01bf0425, 0xfa2b0328, 0x02f0ffa9, 0x0157fa25,
0xfe000200, 0x04380374, 0x05fdff04, 0xfe52030c,
0xfb390037, 0x04c5ff69, 0xfd2304f8, 0xfc1bfd31,
0xfd2cfd2c, 0xfd31fc1b, 0x04f8fd23, 0xff6904c5,
0x0037fb39, 0x030cfe52, 0xff0405fd, 0x03740438,
0x0200fe00, 0xfa250157, 0xffa902f0, 0x0328fa2b,
0x042501bf, 0x0125fdf9, 0xf9d0fe0b, 0xfbe900d2,
0xfa580000, 0x000d03b8, 0x04c9ff5c, 0x04570313,
0x03e9fbdb, 0xfc44ff3c, 0xfe3c032b, 0x0022f927,
0x0200fe00, 0x056d0277, 0xfcd70228, 0xfc3aff21,
0x04c70571, 0xfe680157, 0xfc09fddc, 0xfce00500,
0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e,
0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c,
0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926,
0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942,
0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382,
0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4,
0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da,
0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be,
0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e,
0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c,
0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926,
0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942,
0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382,
0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4,
0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da,
0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be,
};
static const u32 b43_ntab_noisevar0_r3[] = {
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
};
static const u32 b43_ntab_noisevar1_r3[] = {
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
};
static const u16 b43_ntab_mcs_r3[] = {
0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019,
0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090,
0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108,
0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c,
0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199,
0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8,
0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128,
0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a,
0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8,
0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8,
0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa,
0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca,
0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001,
0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014,
0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081,
0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094,
0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007,
};
static const u32 b43_ntab_tdi20a0_r3[] = {
0x00091226, 0x000a1429, 0x000b56ad, 0x000c58b0,
0x000d5ab3, 0x000e9cb6, 0x000f9eba, 0x0000c13d,
0x00020301, 0x00030504, 0x00040708, 0x0005090b,
0x00064b8e, 0x00095291, 0x000a5494, 0x000b9718,
0x000c9927, 0x000d9b2a, 0x000edd2e, 0x000fdf31,
0x000101b4, 0x000243b7, 0x000345bb, 0x000447be,
0x00058982, 0x00068c05, 0x00099309, 0x000a950c,
0x000bd78f, 0x000cd992, 0x000ddb96, 0x000f1d99,
0x00005fa8, 0x0001422c, 0x0002842f, 0x00038632,
0x00048835, 0x0005ca38, 0x0006ccbc, 0x0009d3bf,
0x000b1603, 0x000c1806, 0x000d1a0a, 0x000e1c0d,
0x000f5e10, 0x00008093, 0x00018297, 0x0002c49a,
0x0003c680, 0x0004c880, 0x00060b00, 0x00070d00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi20a1_r3[] = {
0x00014b26, 0x00028d29, 0x000393ad, 0x00049630,
0x0005d833, 0x0006da36, 0x00099c3a, 0x000a9e3d,
0x000bc081, 0x000cc284, 0x000dc488, 0x000f068b,
0x0000488e, 0x00018b91, 0x0002d214, 0x0003d418,
0x0004d6a7, 0x000618aa, 0x00071aae, 0x0009dcb1,
0x000b1eb4, 0x000c0137, 0x000d033b, 0x000e053e,
0x000f4702, 0x00008905, 0x00020c09, 0x0003128c,
0x0004148f, 0x00051712, 0x00065916, 0x00091b19,
0x000a1d28, 0x000b5f2c, 0x000c41af, 0x000d43b2,
0x000e85b5, 0x000f87b8, 0x0000c9bc, 0x00024cbf,
0x00035303, 0x00045506, 0x0005978a, 0x0006998d,
0x00095b90, 0x000a5d93, 0x000b9f97, 0x000c821a,
0x000d8400, 0x000ec600, 0x000fc800, 0x00010a00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a0_r3[] = {
0x0011a346, 0x00136ccf, 0x0014f5d9, 0x001641e2,
0x0017cb6b, 0x00195475, 0x001b2383, 0x001cad0c,
0x001e7616, 0x0000821f, 0x00020ba8, 0x0003d4b2,
0x00056447, 0x00072dd0, 0x0008b6da, 0x000a02e3,
0x000b8c6c, 0x000d15f6, 0x0011e484, 0x0013ae0d,
0x00153717, 0x00168320, 0x00180ca9, 0x00199633,
0x001b6548, 0x001ceed1, 0x001eb7db, 0x0000c3e4,
0x00024d6d, 0x000416f7, 0x0005a585, 0x00076f0f,
0x0008f818, 0x000a4421, 0x000bcdab, 0x000d9734,
0x00122649, 0x0013efd2, 0x001578dc, 0x0016c4e5,
0x00184e6e, 0x001a17f8, 0x001ba686, 0x001d3010,
0x001ef999, 0x00010522, 0x00028eac, 0x00045835,
0x0005e74a, 0x0007b0d3, 0x00093a5d, 0x000a85e6,
0x000c0f6f, 0x000dd8f9, 0x00126787, 0x00143111,
0x0015ba9a, 0x00170623, 0x00188fad, 0x001a5936,
0x001be84b, 0x001db1d4, 0x001f3b5e, 0x000146e7,
0x00031070, 0x000499fa, 0x00062888, 0x0007f212,
0x00097b9b, 0x000ac7a4, 0x000c50ae, 0x000e1a37,
0x0012a94c, 0x001472d5, 0x0015fc5f, 0x00174868,
0x0018d171, 0x001a9afb, 0x001c2989, 0x001df313,
0x001f7c9c, 0x000188a5, 0x000351af, 0x0004db38,
0x0006aa4d, 0x000833d7, 0x0009bd60, 0x000b0969,
0x000c9273, 0x000e5bfc, 0x00132a8a, 0x0014b414,
0x00163d9d, 0x001789a6, 0x001912b0, 0x001adc39,
0x001c6bce, 0x001e34d8, 0x001fbe61, 0x0001ca6a,
0x00039374, 0x00051cfd, 0x0006ec0b, 0x00087515,
0x0009fe9e, 0x000b4aa7, 0x000cd3b1, 0x000e9d3a,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a1_r3[] = {
0x001edb36, 0x000129ca, 0x0002b353, 0x00047cdd,
0x0005c8e6, 0x000791ef, 0x00091bf9, 0x000aaa07,
0x000c3391, 0x000dfd1a, 0x00120923, 0x0013d22d,
0x00155c37, 0x0016eacb, 0x00187454, 0x001a3dde,
0x001b89e7, 0x001d12f0, 0x001f1cfa, 0x00016b88,
0x00033492, 0x0004be1b, 0x00060a24, 0x0007d32e,
0x00095d38, 0x000aec4c, 0x000c7555, 0x000e3edf,
0x00124ae8, 0x001413f1, 0x0015a37b, 0x00172c89,
0x0018b593, 0x001a419c, 0x001bcb25, 0x001d942f,
0x001f63b9, 0x0001ad4d, 0x00037657, 0x0004c260,
0x00068be9, 0x000814f3, 0x0009a47c, 0x000b2d8a,
0x000cb694, 0x000e429d, 0x00128c26, 0x001455b0,
0x0015e4ba, 0x00176e4e, 0x0018f758, 0x001a8361,
0x001c0cea, 0x001dd674, 0x001fa57d, 0x0001ee8b,
0x0003b795, 0x0005039e, 0x0006cd27, 0x000856b1,
0x0009e5c6, 0x000b6f4f, 0x000cf859, 0x000e8462,
0x00130deb, 0x00149775, 0x00162603, 0x0017af8c,
0x00193896, 0x001ac49f, 0x001c4e28, 0x001e17b2,
0x0000a6c7, 0x00023050, 0x0003f9da, 0x00054563,
0x00070eec, 0x00089876, 0x000a2704, 0x000bb08d,
0x000d3a17, 0x001185a0, 0x00134f29, 0x0014d8b3,
0x001667c8, 0x0017f151, 0x00197adb, 0x001b0664,
0x001c8fed, 0x001e5977, 0x0000e805, 0x0002718f,
0x00043b18, 0x000586a1, 0x0007502b, 0x0008d9b4,
0x000a68c9, 0x000bf252, 0x000dbbdc, 0x0011c7e5,
0x001390ee, 0x00151a78, 0x0016a906, 0x00183290,
0x0019bc19, 0x001b4822, 0x001cd12c, 0x001e9ab5,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_pilotlt_r3[] = {
0x76540213, 0x62407351, 0x76543210, 0x76540213,
0x76540213, 0x76430521,
};
static const u32 b43_ntab_channelest_r3[] = {
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
};
static const u8 b43_ntab_framelookup_r3[] = {
0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16,
0x0a, 0x0c, 0x1c, 0x1c, 0x0b, 0x0d, 0x1e, 0x1e,
0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1a, 0x1a,
0x0e, 0x10, 0x20, 0x28, 0x0f, 0x11, 0x22, 0x2a,
};
static const u8 b43_ntab_estimatepowerlt0_r3[] = {
0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51,
0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c,
0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46,
0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f,
0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36,
0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b,
0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a,
0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd,
};
static const u8 b43_ntab_estimatepowerlt1_r3[] = {
0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51,
0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c,
0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46,
0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f,
0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36,
0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b,
0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a,
0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd,
};
static const u8 b43_ntab_adjustpower0_r3[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 b43_ntab_adjustpower1_r3[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u32 b43_ntab_gainctl0_r3[] = {
0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e,
0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037,
0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031,
0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040,
0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039,
0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033,
0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e,
0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037,
0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031,
0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c,
0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e,
0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037,
0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031,
0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c,
0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042,
0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b,
0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034,
0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f,
0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e,
0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037,
0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031,
0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c,
0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027,
0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023,
0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e,
0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037,
0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031,
0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c,
0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027,
0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023,
0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f,
0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c,
};
static const u32 b43_ntab_gainctl1_r3[] = {
0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e,
0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037,
0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031,
0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040,
0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039,
0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033,
0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e,
0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037,
0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031,
0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c,
0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e,
0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037,
0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031,
0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c,
0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042,
0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b,
0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034,
0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f,
0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e,
0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037,
0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031,
0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c,
0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027,
0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023,
0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e,
0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037,
0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031,
0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c,
0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027,
0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023,
0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f,
0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c,
};
static const u32 b43_ntab_iqlt0_r3[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_iqlt1_r3[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u16 b43_ntab_loftlt0_r3[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000,
};
static const u16 b43_ntab_loftlt1_r3[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000,
};
/* volatile tables, PHY revision >= 3 */
/* indexed by antswctl2g */
static const u16 b43_ntab_antswctl2g_r3[4][32] = {
{
0x0082, 0x0082, 0x0211, 0x0222, 0x0328,
0x0000, 0x0000, 0x0000, 0x0144, 0x0000,
0x0000, 0x0000, 0x0188, 0x0000, 0x0000,
0x0000, 0x0082, 0x0082, 0x0211, 0x0222,
0x0328, 0x0000, 0x0000, 0x0000, 0x0144,
0x0000, 0x0000, 0x0000, 0x0188, 0x0000,
0x0000, 0x0000,
},
{
0x0022, 0x0022, 0x0011, 0x0022, 0x0022,
0x0000, 0x0000, 0x0000, 0x0011, 0x0000,
0x0000, 0x0000, 0x0022, 0x0000, 0x0000,
0x0000, 0x0022, 0x0022, 0x0011, 0x0022,
0x0022, 0x0000, 0x0000, 0x0000, 0x0011,
0x0000, 0x0000, 0x0000, 0x0022, 0x0000,
0x0000, 0x0000,
},
{
0x0088, 0x0088, 0x0044, 0x0088, 0x0088,
0x0000, 0x0000, 0x0000, 0x0044, 0x0000,
0x0000, 0x0000, 0x0088, 0x0000, 0x0000,
0x0000, 0x0088, 0x0088, 0x0044, 0x0088,
0x0088, 0x0000, 0x0000, 0x0000, 0x0044,
0x0000, 0x0000, 0x0000, 0x0088, 0x0000,
0x0000, 0x0000,
},
{
0x0022, 0x0022, 0x0011, 0x0022, 0x0000,
0x0000, 0x0000, 0x0000, 0x0011, 0x0000,
0x0000, 0x0000, 0x0022, 0x0000, 0x0000,
0x03cc, 0x0022, 0x0022, 0x0011, 0x0022,
0x0000, 0x0000, 0x0000, 0x0000, 0x0011,
0x0000, 0x0000, 0x0000, 0x0022, 0x0000,
0x0000, 0x03cc,
}
};
/* TX gain tables */
static const u32 b43_ntab_tx_gain_rev0_1_2[] = {
0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44,
0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844,
0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644,
0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444,
0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44,
0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844,
0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44,
0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944,
0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744,
0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544,
0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44,
0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844,
0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44,
0x03902b42, 0x03902a44, 0x03902a42, 0x03902944,
0x03902942, 0x03902844, 0x03902842, 0x03902744,
0x03902742, 0x03902644, 0x03902642, 0x03902544,
0x03902542, 0x03802b44, 0x03802b42, 0x03802a44,
0x03802a42, 0x03802944, 0x03802942, 0x03802844,
0x03802842, 0x03802744, 0x03802742, 0x03802644,
0x03802642, 0x03802544, 0x03802542, 0x03802444,
0x03802442, 0x03802344, 0x03802342, 0x03802244,
0x03802242, 0x03802144, 0x03802142, 0x03802044,
0x03802042, 0x03801f44, 0x03801f42, 0x03801e44,
0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44,
0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44,
0x03801a42, 0x03801944, 0x03801942, 0x03801844,
0x03801842, 0x03801744, 0x03801742, 0x03801644,
0x03801642, 0x03801544, 0x03801542, 0x03801444,
0x03801442, 0x03801344, 0x03801342, 0x00002b00,
};
static const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037,
0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e,
0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037,
0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e,
0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037,
0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e,
0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037,
0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e,
0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037,
0x19410044, 0x19410042, 0x19410040, 0x1941003e,
0x1941003c, 0x1941003b, 0x19410039, 0x19410037,
0x18410044, 0x18410042, 0x18410040, 0x1841003e,
0x1841003c, 0x1841003b, 0x18410039, 0x18410037,
0x17410044, 0x17410042, 0x17410040, 0x1741003e,
0x1741003c, 0x1741003b, 0x17410039, 0x17410037,
0x16410044, 0x16410042, 0x16410040, 0x1641003e,
0x1641003c, 0x1641003b, 0x16410039, 0x16410037,
0x15410044, 0x15410042, 0x15410040, 0x1541003e,
0x1541003c, 0x1541003b, 0x15410039, 0x15410037,
0x14410044, 0x14410042, 0x14410040, 0x1441003e,
0x1441003c, 0x1441003b, 0x14410039, 0x14410037,
0x13410044, 0x13410042, 0x13410040, 0x1341003e,
0x1341003c, 0x1341003b, 0x13410039, 0x13410037,
0x12410044, 0x12410042, 0x12410040, 0x1241003e,
0x1241003c, 0x1241003b, 0x12410039, 0x12410037,
0x11410044, 0x11410042, 0x11410040, 0x1141003e,
0x1141003c, 0x1141003b, 0x11410039, 0x11410037,
0x10410044, 0x10410042, 0x10410040, 0x1041003e,
0x1041003c, 0x1041003b, 0x10410039, 0x10410037,
};
static const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037,
0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e,
0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037,
0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e,
0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037,
0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e,
0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037,
0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e,
0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037,
0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e,
0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037,
0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e,
0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037,
0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e,
0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037,
0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e,
0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037,
0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e,
0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037,
0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e,
0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037,
0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e,
0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037,
0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e,
0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037,
0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e,
0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037,
0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e,
0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037,
};
static const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037,
0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e,
0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037,
0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e,
0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037,
0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e,
0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037,
0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e,
0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037,
0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e,
0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037,
0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e,
0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037,
0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e,
0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037,
0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e,
0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037,
0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e,
0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037,
0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e,
0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038,
0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e,
0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037,
0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e,
0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037,
0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e,
0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037,
0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c,
0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034,
};
static const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a,
0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e,
0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a,
0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e,
0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037,
0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040,
0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a,
0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c,
0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038,
0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b,
0x09620039, 0x09620037, 0x09620035, 0x09620033,
0x08620044, 0x08620042, 0x08620040, 0x0862003e,
0x0862003c, 0x0862003b, 0x0862003a, 0x08620039,
0x07620043, 0x07620042, 0x07620040, 0x0762003f,
0x0762003d, 0x0762003b, 0x0762003a, 0x07620039,
0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b,
0x06620039, 0x06620037, 0x06620035, 0x06620033,
0x05620046, 0x05620044, 0x05620042, 0x05620040,
0x0562003e, 0x0562003c, 0x0562003b, 0x05620039,
0x04620044, 0x04620042, 0x04620040, 0x0462003e,
0x0462003c, 0x0462003b, 0x04620039, 0x04620038,
0x0362003c, 0x0362003b, 0x0362003a, 0x03620039,
0x03620038, 0x03620037, 0x03620035, 0x03620033,
0x0262004c, 0x0262004a, 0x02620048, 0x02620047,
0x02620046, 0x02620044, 0x02620043, 0x02620042,
0x0162004a, 0x01620048, 0x01620046, 0x01620044,
0x01620043, 0x01620042, 0x01620041, 0x01620040,
0x00620042, 0x00620040, 0x0062003e, 0x0062003c,
0x0062003b, 0x00620039, 0x00620037, 0x00620035,
};
static const u32 txpwrctrl_tx_gain_ipa[] = {
0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025,
0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029,
0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025,
0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029,
0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025,
0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029,
0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025,
0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029,
0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025,
0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029,
0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025,
0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029,
0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025,
0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029,
0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025,
0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029,
0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025,
0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029,
0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025,
0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029,
0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025,
0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029,
0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025,
0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029,
0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025,
0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029,
0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025,
0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029,
0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025,
};
static const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025,
0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029,
0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025,
0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029,
0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025,
0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029,
0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025,
0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029,
0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025,
0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029,
0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025,
0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029,
0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025,
0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029,
0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025,
0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029,
0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025,
0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029,
0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025,
0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029,
0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025,
0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029,
0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025,
0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029,
0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025,
0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029,
0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025,
0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029,
0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025,
};
static const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025,
0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029,
0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025,
0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029,
0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025,
0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029,
0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025,
0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029,
0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025,
0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029,
0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025,
0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029,
0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025,
0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029,
0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025,
0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029,
0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025,
0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029,
0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025,
0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029,
0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025,
0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029,
0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025,
0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029,
0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025,
0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029,
0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025,
0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029,
0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025,
};
static const u32 txpwrctrl_tx_gain_ipa_5g[] = {
0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022,
0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025,
0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027,
0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023,
0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027,
0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022,
0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025,
0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021,
0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026,
0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022,
0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026,
0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022,
0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026,
0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022,
0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026,
0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022,
0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026,
0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021,
0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026,
0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029,
0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024,
0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027,
0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023,
0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026,
0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022,
0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025,
0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027,
0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022,
0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f,
};
const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[] = {
-114, -108, -98, -91, -84, -78, -70, -62,
-54, -46, -39, -31, -23, -15, -8, 0
};
const u16 tbl_iqcal_gainparams[2][9][8] = {
{
{ 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 },
{ 0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69 },
{ 0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68 },
{ 0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67 },
{ 0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66 },
{ 0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65 },
{ 0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65 },
{ 0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65 },
{ 0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65 }
},
{
{ 0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 },
{ 0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 },
{ 0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79 },
{ 0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78 },
{ 0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78 },
{ 0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78 },
{ 0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78 },
{ 0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78 },
{ 0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78 }
}
};
const struct nphy_txiqcal_ladder ladder_lo[] = {
{ 3, 0 },
{ 4, 0 },
{ 6, 0 },
{ 9, 0 },
{ 13, 0 },
{ 18, 0 },
{ 25, 0 },
{ 25, 1 },
{ 25, 2 },
{ 25, 3 },
{ 25, 4 },
{ 25, 5 },
{ 25, 6 },
{ 25, 7 },
{ 35, 7 },
{ 50, 7 },
{ 71, 7 },
{ 100, 7 }
};
const struct nphy_txiqcal_ladder ladder_iq[] = {
{ 3, 0 },
{ 4, 0 },
{ 6, 0 },
{ 9, 0 },
{ 13, 0 },
{ 18, 0 },
{ 25, 0 },
{ 35, 0 },
{ 50, 0 },
{ 71, 0 },
{ 100, 0 },
{ 100, 1 },
{ 100, 2 },
{ 100, 3 },
{ 100, 4 },
{ 100, 5 },
{ 100, 6 },
{ 100, 7 }
};
const u16 loscale[] = {
256, 256, 271, 271,
287, 256, 256, 271,
271, 287, 287, 304,
304, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 341,
341, 362, 362, 383,
383, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 256,
256, 271, 271, 287,
287, 304, 304, 322,
322, 341, 341, 362,
362, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 256,
256, 271, 271, 287,
287, 304, 304, 322,
322, 341, 341, 362,
362, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 341,
341, 362, 362, 383,
383, 406, 406, 430,
430, 455, 455, 482,
482, 511, 511, 541,
541, 573, 573, 607,
607, 643, 643, 681,
681, 722, 722, 764,
764, 810, 810, 858,
858, 908, 908, 962,
962, 1019, 1019, 256
};
const u16 tbl_tx_iqlo_cal_loft_ladder_40[] = {
0x0200, 0x0300, 0x0400, 0x0700,
0x0900, 0x0c00, 0x1200, 0x1201,
0x1202, 0x1203, 0x1204, 0x1205,
0x1206, 0x1207, 0x1907, 0x2307,
0x3207, 0x4707
};
const u16 tbl_tx_iqlo_cal_loft_ladder_20[] = {
0x0300, 0x0500, 0x0700, 0x0900,
0x0d00, 0x1100, 0x1900, 0x1901,
0x1902, 0x1903, 0x1904, 0x1905,
0x1906, 0x1907, 0x2407, 0x3207,
0x4607, 0x6407
};
const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = {
0x0100, 0x0200, 0x0400, 0x0700,
0x0900, 0x0c00, 0x1200, 0x1900,
0x2300, 0x3200, 0x4700, 0x4701,
0x4702, 0x4703, 0x4704, 0x4705,
0x4706, 0x4707
};
const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = {
0x0200, 0x0300, 0x0600, 0x0900,
0x0d00, 0x1100, 0x1900, 0x2400,
0x3200, 0x4600, 0x6400, 0x6401,
0x6402, 0x6403, 0x6404, 0x6405,
0x6406, 0x6407
};
const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3] = { };
const u16 tbl_tx_iqlo_cal_startcoefs[B43_NTAB_TX_IQLO_CAL_STARTCOEFS] = { };
const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = {
0x8423, 0x8323, 0x8073, 0x8256,
0x8045, 0x8223, 0x9423, 0x9323,
0x9073, 0x9256, 0x9045, 0x9223
};
const u16 tbl_tx_iqlo_cal_cmds_recal[] = {
0x8101, 0x8253, 0x8053, 0x8234,
0x8034, 0x9101, 0x9253, 0x9053,
0x9234, 0x9034
};
const u16 tbl_tx_iqlo_cal_cmds_fullcal[] = {
0x8123, 0x8264, 0x8086, 0x8245,
0x8056, 0x9123, 0x9264, 0x9086,
0x9245, 0x9056
};
const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = {
0x8434, 0x8334, 0x8084, 0x8267,
0x8056, 0x8234, 0x9434, 0x9334,
0x9084, 0x9267, 0x9056, 0x9234
};
const s16 tbl_tx_filter_coef_rev4[7][15] = {
{ -377, 137, -407, 208, -1527,
956, 93, 186, 93, 230,
-44, 230, 201, -191, 201 },
{ -77, 20, -98, 49, -93,
60, 56, 111, 56, 26,
-5, 26, 34, -32, 34 },
{ -360, 164, -376, 164, -1533,
576, 308, -314, 308, 121,
-73, 121, 91, 124, 91 },
{ -295, 200, -363, 142, -1391,
826, 151, 301, 151, 151,
301, 151, 602, -752, 602 },
{ -92, 58, -96, 49, -104,
44, 17, 35, 17, 12,
25, 12, 13, 27, 13 },
{ -375, 136, -399, 209, -1479,
949, 130, 260, 130, 230,
-44, 230, 201, -191, 201 },
{ 0xed9, 0xc8, 0xe95, 0x8e, 0xa91,
0x33a, 0x97, 0x12d, 0x97, 0x97,
0x12d, 0x97, 0x25a, 0xd10, 0x25a }
};
/* addr0, addr1, bmask, shift */
const struct nphy_rf_control_override_rev2 tbl_rf_control_override_rev2[] = {
{ 0x78, 0x78, 0x0038, 3 }, /* for field == 0x0002 (fls == 2) */
{ 0x7A, 0x7D, 0x0001, 0 }, /* for field == 0x0004 (fls == 3) */
{ 0x7A, 0x7D, 0x0002, 1 }, /* for field == 0x0008 (fls == 4) */
{ 0x7A, 0x7D, 0x0004, 2 }, /* for field == 0x0010 (fls == 5) */
{ 0x7A, 0x7D, 0x0030, 4 }, /* for field == 0x0020 (fls == 6) */
{ 0x7A, 0x7D, 0x00C0, 6 }, /* for field == 0x0040 (fls == 7) */
{ 0x7A, 0x7D, 0x0100, 8 }, /* for field == 0x0080 (fls == 8) */
{ 0x7A, 0x7D, 0x0200, 9 }, /* for field == 0x0100 (fls == 9) */
{ 0x78, 0x78, 0x0004, 2 }, /* for field == 0x0200 (fls == 10) */
{ 0x7B, 0x7E, 0x01FF, 0 }, /* for field == 0x0400 (fls == 11) */
{ 0x7C, 0x7F, 0x01FF, 0 }, /* for field == 0x0800 (fls == 12) */
{ 0x78, 0x78, 0x0100, 8 }, /* for field == 0x1000 (fls == 13) */
{ 0x78, 0x78, 0x0200, 9 }, /* for field == 0x2000 (fls == 14) */
{ 0x78, 0x78, 0xF000, 12 } /* for field == 0x4000 (fls == 15) */
};
/* val_mask, val_shift, en_addr0, val_addr0, en_addr1, val_addr1 */
const struct nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = {
{ 0x8000, 15, 0xE5, 0xF9, 0xE6, 0xFB }, /* field == 0x0001 (fls 1) */
{ 0x0001, 0, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0002 (fls 2) */
{ 0x0002, 1, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0004 (fls 3) */
{ 0x0004, 2, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0008 (fls 4) */
{ 0x0010, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */
{ 0x0020, 5, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0020 (fls 6) */
{ 0x0040, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0040 (fls 7) */
{ 0x0080, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */
{ 0x0100, 8, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */
{ 0x0007, 0, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0200 (fls 10) */
{ 0x0070, 4, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0400 (fls 11) */
{ 0xE000, 13, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0800 (fls 12) */
{ 0xFFFF, 0, 0xE7, 0x7B, 0xEC, 0x7E }, /* field == 0x1000 (fls 13) */
{ 0xFFFF, 0, 0xE7, 0x7C, 0xEC, 0x7F }, /* field == 0x2000 (fls 14) */
{ 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */
};
struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = {
{ 10, 14, 19, 27 },
{ -5, 6, 10, 15 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x427E,
{ 0x413F, 0x413F, 0x413F, 0x413F },
0x007E, 0x0066, 0x1074,
0x18, 0x18, 0x18,
0x01D0, 0x5,
};
struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = {
{ /* 2GHz */
{ /* PHY rev 3 */
{ 7, 11, 16, 23 },
{ -5, 6, 10, 14 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x627E,
{ 0x613F, 0x613F, 0x613F, 0x613F },
0x107E, 0x0066, 0x0074,
0x18, 0x18, 0x18,
0x020D, 0x5,
},
{ /* PHY rev 4 */
{ 8, 12, 17, 25 },
{ -5, 6, 10, 14 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x527E,
{ 0x513F, 0x513F, 0x513F, 0x513F },
0x007E, 0x0066, 0x0074,
0x18, 0x18, 0x18,
0x01A1, 0x5,
},
{ /* PHY rev 5 */
{ 9, 13, 18, 26 },
{ -3, 7, 11, 16 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x427E, /* invalid for external LNA! */
{ 0x413F, 0x413F, 0x413F, 0x413F }, /* invalid for external LNA! */
0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */
0x18, 0x18, 0x18,
0x01D0, 0x9,
},
{ /* PHY rev 6+ */
{ 8, 13, 18, 25 },
{ -5, 6, 10, 14 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x527E, /* invalid for external LNA! */
{ 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */
0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */
0x18, 0x18, 0x18,
0x01D0, 0x5,
},
},
{ /* 5GHz */
{ /* PHY rev 3 */
{ 7, 11, 17, 23 },
{ -6, 2, 6, 10 },
{ 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 },
{ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 },
0x52DE,
{ 0x516F, 0x516F, 0x516F, 0x516F },
0x00DE, 0x00CA, 0x00CC,
0x1E, 0x1E, 0x1E,
0x01A1, 25,
},
{ /* PHY rev 4 */
{ 8, 12, 18, 23 },
{ -5, 2, 6, 10 },
{ 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD },
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 },
0x629E,
{ 0x614F, 0x614F, 0x614F, 0x614F },
0x029E, 0x1084, 0x0086,
0x24, 0x24, 0x24,
0x0107, 25,
},
{ /* PHY rev 5 */
{ 6, 10, 16, 21 },
{ -7, 0, 4, 8 },
{ 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD },
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 },
0x729E,
{ 0x714F, 0x714F, 0x714F, 0x714F },
0x029E, 0x2084, 0x2086,
0x24, 0x24, 0x24,
0x00A9, 25,
},
{ /* PHY rev 6+ */
{ 6, 10, 16, 21 },
{ -7, 0, 4, 8 },
{ 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD },
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 },
0x729E,
{ 0x714F, 0x714F, 0x714F, 0x714F },
0x029E, 0x2084, 0x2086,
0x24, 0x24, 0x24, /* low is invalid for radio rev 11! */
0x00F0, 25,
},
},
};
static inline void assert_ntab_array_sizes(void)
{
#undef check
#define check(table, size) \
BUILD_BUG_ON(ARRAY_SIZE(b43_ntab_##table) != B43_NTAB_##size##_SIZE)
check(adjustpower0, C0_ADJPLT);
check(adjustpower1, C1_ADJPLT);
check(bdi, BDI);
check(channelest, CHANEST);
check(estimatepowerlt0, C0_ESTPLT);
check(estimatepowerlt1, C1_ESTPLT);
check(framelookup, FRAMELT);
check(framestruct, FRAMESTRUCT);
check(gainctl0, C0_GAINCTL);
check(gainctl1, C1_GAINCTL);
check(intlevel, INTLEVEL);
check(iqlt0, C0_IQLT);
check(iqlt1, C1_IQLT);
check(loftlt0, C0_LOFEEDTH);
check(loftlt1, C1_LOFEEDTH);
check(mcs, MCS);
check(noisevar10, NOISEVAR10);
check(noisevar11, NOISEVAR11);
check(pilot, PILOT);
check(pilotlt, PILOTLT);
check(tdi20a0, TDI20A0);
check(tdi20a1, TDI20A1);
check(tdi40a0, TDI40A0);
check(tdi40a1, TDI40A1);
check(tdtrn, TDTRN);
check(tmap, TMAP);
#undef check
}
u32 b43_ntab_read(struct b43_wldev *dev, u32 offset)
{
u32 type, value;
type = offset & B43_NTAB_TYPEMASK;
offset &= ~B43_NTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
switch (type) {
case B43_NTAB_8BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO) & 0xFF;
break;
case B43_NTAB_16BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
break;
case B43_NTAB_32BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
value |= b43_phy_read(dev, B43_NPHY_TABLE_DATAHI) << 16;
break;
default:
B43_WARN_ON(1);
value = 0;
}
return value;
}
void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset,
unsigned int nr_elements, void *_data)
{
u32 type;
u8 *data = _data;
unsigned int i;
type = offset & B43_NTAB_TYPEMASK;
offset &= ~B43_NTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
for (i = 0; i < nr_elements; i++) {
/* Auto increment broken + caching issue on BCM43224? */
if (dev->dev->chip_id == 43224 && dev->dev->chip_rev == 1) {
b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset + i);
}
switch (type) {
case B43_NTAB_8BIT:
*data = b43_phy_read(dev, B43_NPHY_TABLE_DATALO) & 0xFF;
data++;
break;
case B43_NTAB_16BIT:
*((u16 *)data) = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
data += 2;
break;
case B43_NTAB_32BIT:
*((u32 *)data) =
b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
*((u32 *)data) |=
b43_phy_read(dev, B43_NPHY_TABLE_DATAHI) << 16;
data += 4;
break;
default:
B43_WARN_ON(1);
}
}
}
void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value)
{
u32 type;
type = offset & B43_NTAB_TYPEMASK;
offset &= 0xFFFF;
switch (type) {
case B43_NTAB_8BIT:
B43_WARN_ON(value & ~0xFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_16BIT:
B43_WARN_ON(value & ~0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_32BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value & 0xFFFF);
break;
default:
B43_WARN_ON(1);
}
return;
/* Some compiletime assertions... */
assert_ntab_array_sizes();
}
void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
unsigned int nr_elements, const void *_data)
{
u32 type, value;
const u8 *data = _data;
unsigned int i;
type = offset & B43_NTAB_TYPEMASK;
offset &= ~B43_NTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
for (i = 0; i < nr_elements; i++) {
/* Auto increment broken + caching issue on BCM43224? */
if ((offset >> 10) == 9 && dev->dev->chip_id == 43224 &&
dev->dev->chip_rev == 1) {
b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset + i);
}
switch (type) {
case B43_NTAB_8BIT:
value = *data;
data++;
B43_WARN_ON(value & ~0xFF);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_16BIT:
value = *((u16 *)data);
data += 2;
B43_WARN_ON(value & ~0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_32BIT:
value = *((u32 *)data);
data += 4;
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
value & 0xFFFF);
break;
default:
B43_WARN_ON(1);
}
}
}
#define ntab_upload(dev, offset, data) do { \
b43_ntab_write_bulk(dev, offset, offset##_SIZE, data); \
} while (0)
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
{
/* Static tables */
ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
/* Volatile tables */
ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
}
#define ntab_upload_r3(dev, offset, data) do { \
b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
} while (0)
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
{
struct ssb_sprom *sprom = dev->dev->bus_sprom;
/* Static tables */
ntab_upload_r3(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
ntab_upload_r3(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
ntab_upload_r3(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
ntab_upload_r3(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
ntab_upload_r3(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
ntab_upload_r3(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
ntab_upload_r3(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
ntab_upload_r3(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
ntab_upload_r3(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
ntab_upload_r3(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
ntab_upload_r3(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
ntab_upload_r3(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
ntab_upload_r3(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
ntab_upload_r3(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
ntab_upload_r3(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
ntab_upload_r3(dev, B43_NTAB_C0_ESTPLT_R3,
b43_ntab_estimatepowerlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_ESTPLT_R3,
b43_ntab_estimatepowerlt1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
/* Volatile tables */
if (sprom->fem.ghz2.antswlut < ARRAY_SIZE(b43_ntab_antswctl2g_r3))
ntab_upload_r3(dev, B43_NTAB_ANT_SW_CTL_R3,
b43_ntab_antswctl2g_r3[sprom->fem.ghz2.antswlut]);
else
B43_WARN_ON(1);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
{
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
if (dev->phy.rev >= 6) {
if (dev->dev->chip_id == 47162)
return txpwrctrl_tx_gain_ipa_rev5;
return txpwrctrl_tx_gain_ipa_rev6;
} else if (dev->phy.rev >= 5) {
return txpwrctrl_tx_gain_ipa_rev5;
} else {
return txpwrctrl_tx_gain_ipa;
}
} else {
return txpwrctrl_tx_gain_ipa_5g;
}
}
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev)
{
enum ieee80211_band band = b43_current_band(dev->wl);
struct ssb_sprom *sprom = dev->dev->bus_sprom;
if (dev->phy.rev < 3)
return b43_ntab_tx_gain_rev0_1_2;
/* rev 3+ */
if ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
return b43_nphy_get_ipa_gain_table(dev);
} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
if (dev->phy.rev == 3)
return b43_ntab_tx_gain_rev3_5ghz;
if (dev->phy.rev == 4)
return sprom->fem.ghz5.extpa_gain == 3 ?
b43_ntab_tx_gain_rev4_5ghz :
b43_ntab_tx_gain_rev4_5ghz; /* FIXME */
else
return b43_ntab_tx_gain_rev5plus_5ghz;
} else {
if (dev->phy.rev >= 5 && sprom->fem.ghz5.extpa_gain == 3)
return b43_ntab_tx_gain_rev3plus_2ghz; /* FIXME */
else
return b43_ntab_tx_gain_rev3plus_2ghz;
}
}
struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
struct b43_wldev *dev, bool ghz5, bool ext_lna)
{
struct nphy_gain_ctl_workaround_entry *e;
u8 phy_idx;
u8 tr_iso = ghz5 ? dev->dev->bus_sprom->fem.ghz5.tr_iso :
dev->dev->bus_sprom->fem.ghz2.tr_iso;
if (!ghz5 && dev->phy.rev >= 6 && dev->phy.radio_rev == 11)
return &nphy_gain_ctl_wa_phy6_radio11_ghz2;
B43_WARN_ON(dev->phy.rev < 3);
if (dev->phy.rev >= 6)
phy_idx = 3;
else if (dev->phy.rev == 5)
phy_idx = 2;
else if (dev->phy.rev == 4)
phy_idx = 1;
else
phy_idx = 0;
e = &nphy_gain_ctl_workaround[ghz5][phy_idx];
/* Some workarounds to the workarounds... */
if (ghz5 && dev->phy.rev >= 6) {
if (dev->phy.radio_rev == 11 &&
!b43_channel_type_is_40mhz(dev->phy.channel_type))
e->cliplo_gain = 0x2d;
} else if (!ghz5 && dev->phy.rev >= 5) {
if (ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
}
switch (tr_iso) {
case 0:
e->cliplo_gain = 0x0062;
case 1:
e->cliplo_gain = 0x0064;
case 2:
e->cliplo_gain = 0x006a;
case 3:
e->cliplo_gain = 0x106a;
case 4:
e->cliplo_gain = 0x106c;
case 5:
e->cliplo_gain = 0x1074;
case 6:
e->cliplo_gain = 0x107c;
case 7:
e->cliplo_gain = 0x207c;
default:
e->cliplo_gain = 0x106a;
}
} else if (ghz5 && dev->phy.rev == 4 && ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
e->rfseq_init[0] |= 0x1000;
e->rfseq_init[1] |= 0x1000;
e->rfseq_init[2] |= 0x1000;
e->rfseq_init[3] |= 0x1000;
e->init_gain |= 0x1000;
}
return e;
}
| gpl-2.0 |
ChaOSChriS/android_kernel_asus_flo | drivers/input/misc/gp2ap002a00f.c | 4965 | 6166 | /*
* Copyright (C) 2011 Sony Ericsson Mobile Communications Inc.
*
* Author: Courtney Cavin <courtney.cavin@sonyericsson.com>
* Prepared for up-stream by: Oskar Andero <oskar.andero@sonyericsson.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*/
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/input/gp2ap002a00f.h>
struct gp2a_data {
struct input_dev *input;
const struct gp2a_platform_data *pdata;
struct i2c_client *i2c_client;
};
enum gp2a_addr {
GP2A_ADDR_PROX = 0x0,
GP2A_ADDR_GAIN = 0x1,
GP2A_ADDR_HYS = 0x2,
GP2A_ADDR_CYCLE = 0x3,
GP2A_ADDR_OPMOD = 0x4,
GP2A_ADDR_CON = 0x6
};
enum gp2a_controls {
/* Software Shutdown control: 0 = shutdown, 1 = normal operation */
GP2A_CTRL_SSD = 0x01
};
static int gp2a_report(struct gp2a_data *dt)
{
int vo = gpio_get_value(dt->pdata->vout_gpio);
input_report_switch(dt->input, SW_FRONT_PROXIMITY, !vo);
input_sync(dt->input);
return 0;
}
static irqreturn_t gp2a_irq(int irq, void *handle)
{
struct gp2a_data *dt = handle;
gp2a_report(dt);
return IRQ_HANDLED;
}
static int gp2a_enable(struct gp2a_data *dt)
{
return i2c_smbus_write_byte_data(dt->i2c_client, GP2A_ADDR_OPMOD,
GP2A_CTRL_SSD);
}
static int gp2a_disable(struct gp2a_data *dt)
{
return i2c_smbus_write_byte_data(dt->i2c_client, GP2A_ADDR_OPMOD,
0x00);
}
static int gp2a_device_open(struct input_dev *dev)
{
struct gp2a_data *dt = input_get_drvdata(dev);
int error;
error = gp2a_enable(dt);
if (error < 0) {
dev_err(&dt->i2c_client->dev,
"unable to activate, err %d\n", error);
return error;
}
gp2a_report(dt);
return 0;
}
static void gp2a_device_close(struct input_dev *dev)
{
struct gp2a_data *dt = input_get_drvdata(dev);
int error;
error = gp2a_disable(dt);
if (error < 0)
dev_err(&dt->i2c_client->dev,
"unable to deactivate, err %d\n", error);
}
static int __devinit gp2a_initialize(struct gp2a_data *dt)
{
int error;
error = i2c_smbus_write_byte_data(dt->i2c_client, GP2A_ADDR_GAIN,
0x08);
if (error < 0)
return error;
error = i2c_smbus_write_byte_data(dt->i2c_client, GP2A_ADDR_HYS,
0xc2);
if (error < 0)
return error;
error = i2c_smbus_write_byte_data(dt->i2c_client, GP2A_ADDR_CYCLE,
0x04);
if (error < 0)
return error;
error = gp2a_disable(dt);
return error;
}
static int __devinit gp2a_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
const struct gp2a_platform_data *pdata = client->dev.platform_data;
struct gp2a_data *dt;
int error;
if (!pdata)
return -EINVAL;
if (pdata->hw_setup) {
error = pdata->hw_setup(client);
if (error < 0)
return error;
}
error = gpio_request_one(pdata->vout_gpio, GPIOF_IN, GP2A_I2C_NAME);
if (error)
goto err_hw_shutdown;
dt = kzalloc(sizeof(struct gp2a_data), GFP_KERNEL);
if (!dt) {
error = -ENOMEM;
goto err_free_gpio;
}
dt->pdata = pdata;
dt->i2c_client = client;
error = gp2a_initialize(dt);
if (error < 0)
goto err_free_mem;
dt->input = input_allocate_device();
if (!dt->input) {
error = -ENOMEM;
goto err_free_mem;
}
input_set_drvdata(dt->input, dt);
dt->input->open = gp2a_device_open;
dt->input->close = gp2a_device_close;
dt->input->name = GP2A_I2C_NAME;
dt->input->id.bustype = BUS_I2C;
dt->input->dev.parent = &client->dev;
input_set_capability(dt->input, EV_SW, SW_FRONT_PROXIMITY);
error = request_threaded_irq(client->irq, NULL, gp2a_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
GP2A_I2C_NAME, dt);
if (error) {
dev_err(&client->dev, "irq request failed\n");
goto err_free_input_dev;
}
error = input_register_device(dt->input);
if (error) {
dev_err(&client->dev, "device registration failed\n");
goto err_free_irq;
}
device_init_wakeup(&client->dev, pdata->wakeup);
i2c_set_clientdata(client, dt);
return 0;
err_free_irq:
free_irq(client->irq, dt);
err_free_input_dev:
input_free_device(dt->input);
err_free_mem:
kfree(dt);
err_free_gpio:
gpio_free(pdata->vout_gpio);
err_hw_shutdown:
if (pdata->hw_shutdown)
pdata->hw_shutdown(client);
return error;
}
static int __devexit gp2a_remove(struct i2c_client *client)
{
struct gp2a_data *dt = i2c_get_clientdata(client);
const struct gp2a_platform_data *pdata = dt->pdata;
device_init_wakeup(&client->dev, false);
free_irq(client->irq, dt);
input_unregister_device(dt->input);
kfree(dt);
gpio_free(pdata->vout_gpio);
if (pdata->hw_shutdown)
pdata->hw_shutdown(client);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int gp2a_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct gp2a_data *dt = i2c_get_clientdata(client);
int retval = 0;
if (device_may_wakeup(&client->dev)) {
enable_irq_wake(client->irq);
} else {
mutex_lock(&dt->input->mutex);
if (dt->input->users)
retval = gp2a_disable(dt);
mutex_unlock(&dt->input->mutex);
}
return retval;
}
static int gp2a_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct gp2a_data *dt = i2c_get_clientdata(client);
int retval = 0;
if (device_may_wakeup(&client->dev)) {
disable_irq_wake(client->irq);
} else {
mutex_lock(&dt->input->mutex);
if (dt->input->users)
retval = gp2a_enable(dt);
mutex_unlock(&dt->input->mutex);
}
return retval;
}
#endif
static SIMPLE_DEV_PM_OPS(gp2a_pm, gp2a_suspend, gp2a_resume);
static const struct i2c_device_id gp2a_i2c_id[] = {
{ GP2A_I2C_NAME, 0 },
{ }
};
static struct i2c_driver gp2a_i2c_driver = {
.driver = {
.name = GP2A_I2C_NAME,
.owner = THIS_MODULE,
.pm = &gp2a_pm,
},
.probe = gp2a_probe,
.remove = __devexit_p(gp2a_remove),
.id_table = gp2a_i2c_id,
};
module_i2c_driver(gp2a_i2c_driver);
MODULE_AUTHOR("Courtney Cavin <courtney.cavin@sonyericsson.com>");
MODULE_DESCRIPTION("Sharp GP2AP002A00F I2C Proximity/Opto sensor driver");
MODULE_LICENSE("GPL v2");
| gpl-2.0 |
fronti90/kernel_lge_geefhd | drivers/net/wireless/brcm80211/brcmsmac/channel.c | 4965 | 43552 | /*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/types.h>
#include <net/mac80211.h>
#include <defs.h>
#include "pub.h"
#include "phy/phy_hal.h"
#include "main.h"
#include "stf.h"
#include "channel.h"
/* QDB() macro takes a dB value and converts to a quarter dB value */
#define QDB(n) ((n) * BRCMS_TXPWR_DB_FACTOR)
#define LOCALE_CHAN_01_11 (1<<0)
#define LOCALE_CHAN_12_13 (1<<1)
#define LOCALE_CHAN_14 (1<<2)
#define LOCALE_SET_5G_LOW_JP1 (1<<3) /* 34-48, step 2 */
#define LOCALE_SET_5G_LOW_JP2 (1<<4) /* 34-46, step 4 */
#define LOCALE_SET_5G_LOW1 (1<<5) /* 36-48, step 4 */
#define LOCALE_SET_5G_LOW2 (1<<6) /* 52 */
#define LOCALE_SET_5G_LOW3 (1<<7) /* 56-64, step 4 */
#define LOCALE_SET_5G_MID1 (1<<8) /* 100-116, step 4 */
#define LOCALE_SET_5G_MID2 (1<<9) /* 120-124, step 4 */
#define LOCALE_SET_5G_MID3 (1<<10) /* 128 */
#define LOCALE_SET_5G_HIGH1 (1<<11) /* 132-140, step 4 */
#define LOCALE_SET_5G_HIGH2 (1<<12) /* 149-161, step 4 */
#define LOCALE_SET_5G_HIGH3 (1<<13) /* 165 */
#define LOCALE_CHAN_52_140_ALL (1<<14)
#define LOCALE_SET_5G_HIGH4 (1<<15) /* 184-216 */
#define LOCALE_CHAN_36_64 (LOCALE_SET_5G_LOW1 | \
LOCALE_SET_5G_LOW2 | \
LOCALE_SET_5G_LOW3)
#define LOCALE_CHAN_52_64 (LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
#define LOCALE_CHAN_100_124 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2)
#define LOCALE_CHAN_100_140 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2 | \
LOCALE_SET_5G_MID3 | LOCALE_SET_5G_HIGH1)
#define LOCALE_CHAN_149_165 (LOCALE_SET_5G_HIGH2 | LOCALE_SET_5G_HIGH3)
#define LOCALE_CHAN_184_216 LOCALE_SET_5G_HIGH4
#define LOCALE_CHAN_01_14 (LOCALE_CHAN_01_11 | \
LOCALE_CHAN_12_13 | \
LOCALE_CHAN_14)
#define LOCALE_RADAR_SET_NONE 0
#define LOCALE_RADAR_SET_1 1
#define LOCALE_RESTRICTED_NONE 0
#define LOCALE_RESTRICTED_SET_2G_SHORT 1
#define LOCALE_RESTRICTED_CHAN_165 2
#define LOCALE_CHAN_ALL_5G 3
#define LOCALE_RESTRICTED_JAPAN_LEGACY 4
#define LOCALE_RESTRICTED_11D_2G 5
#define LOCALE_RESTRICTED_11D_5G 6
#define LOCALE_RESTRICTED_LOW_HI 7
#define LOCALE_RESTRICTED_12_13_14 8
#define LOCALE_2G_IDX_i 0
#define LOCALE_5G_IDX_11 0
#define LOCALE_MIMO_IDX_bn 0
#define LOCALE_MIMO_IDX_11n 0
/* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
#define BRCMS_MAXPWR_TBL_SIZE 6
/* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
#define BRCMS_MAXPWR_MIMO_TBL_SIZE 14
/* power level in group of 2.4GHz band channels:
* maxpwr[0] - CCK channels [1]
* maxpwr[1] - CCK channels [2-10]
* maxpwr[2] - CCK channels [11-14]
* maxpwr[3] - OFDM channels [1]
* maxpwr[4] - OFDM channels [2-10]
* maxpwr[5] - OFDM channels [11-14]
*/
/* maxpwr mapping to 5GHz band channels:
* maxpwr[0] - channels [34-48]
* maxpwr[1] - channels [52-60]
* maxpwr[2] - channels [62-64]
* maxpwr[3] - channels [100-140]
* maxpwr[4] - channels [149-165]
*/
#define BAND_5G_PWR_LVLS 5 /* 5 power levels for 5G */
#define LC(id) LOCALE_MIMO_IDX_ ## id
#define LC_2G(id) LOCALE_2G_IDX_ ## id
#define LC_5G(id) LOCALE_5G_IDX_ ## id
#define LOCALES(band2, band5, mimo2, mimo5) \
{LC_2G(band2), LC_5G(band5), LC(mimo2), LC(mimo5)}
/* macro to get 2.4 GHz channel group index for tx power */
#define CHANNEL_POWER_IDX_2G_CCK(c) (((c) < 2) ? 0 : (((c) < 11) ? 1 : 2))
#define CHANNEL_POWER_IDX_2G_OFDM(c) (((c) < 2) ? 3 : (((c) < 11) ? 4 : 5))
/* macro to get 5 GHz channel group index for tx power */
#define CHANNEL_POWER_IDX_5G(c) (((c) < 52) ? 0 : \
(((c) < 62) ? 1 : \
(((c) < 100) ? 2 : \
(((c) < 149) ? 3 : 4))))
#define ISDFS_EU(fl) (((fl) & BRCMS_DFS_EU) == BRCMS_DFS_EU)
struct brcms_cm_band {
/* struct locale_info flags */
u8 locale_flags;
/* List of valid channels in the country */
struct brcms_chanvec valid_channels;
/* List of restricted use channels */
const struct brcms_chanvec *restricted_channels;
/* List of radar sensitive channels */
const struct brcms_chanvec *radar_channels;
u8 PAD[8];
};
/* locale per-channel tx power limits for MIMO frames
* maxpwr arrays are index by channel for 2.4 GHz limits, and
* by sub-band for 5 GHz limits using CHANNEL_POWER_IDX_5G(channel)
*/
struct locale_mimo_info {
/* tx 20 MHz power limits, qdBm units */
s8 maxpwr20[BRCMS_MAXPWR_MIMO_TBL_SIZE];
/* tx 40 MHz power limits, qdBm units */
s8 maxpwr40[BRCMS_MAXPWR_MIMO_TBL_SIZE];
u8 flags;
};
/* Country names and abbreviations with locale defined from ISO 3166 */
struct country_info {
const u8 locale_2G; /* 2.4G band locale */
const u8 locale_5G; /* 5G band locale */
const u8 locale_mimo_2G; /* 2.4G mimo info */
const u8 locale_mimo_5G; /* 5G mimo info */
};
struct brcms_cm_info {
struct brcms_pub *pub;
struct brcms_c_info *wlc;
char srom_ccode[BRCM_CNTRY_BUF_SZ]; /* Country Code in SROM */
uint srom_regrev; /* Regulatory Rev for the SROM ccode */
const struct country_info *country; /* current country def */
char ccode[BRCM_CNTRY_BUF_SZ]; /* current internal Country Code */
uint regrev; /* current Regulatory Revision */
char country_abbrev[BRCM_CNTRY_BUF_SZ]; /* current advertised ccode */
/* per-band state (one per phy/radio) */
struct brcms_cm_band bandstate[MAXBANDS];
/* quiet channels currently for radar sensitivity or 11h support */
/* channels on which we cannot transmit */
struct brcms_chanvec quiet_channels;
};
/* locale channel and power info. */
struct locale_info {
u32 valid_channels;
/* List of radar sensitive channels */
u8 radar_channels;
/* List of channels used only if APs are detected */
u8 restricted_channels;
/* Max tx pwr in qdBm for each sub-band */
s8 maxpwr[BRCMS_MAXPWR_TBL_SIZE];
/* Country IE advertised max tx pwr in dBm per sub-band */
s8 pub_maxpwr[BAND_5G_PWR_LVLS];
u8 flags;
};
/* Regulatory Matrix Spreadsheet (CLM) MIMO v3.7.9 */
/*
* Some common channel sets
*/
/* No channels */
static const struct brcms_chanvec chanvec_none = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* All 2.4 GHz HW channels */
static const struct brcms_chanvec chanvec_all_2G = {
{0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* All 5 GHz HW channels */
static const struct brcms_chanvec chanvec_all_5G = {
{0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x11, 0x11,
0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11,
0x11, 0x11, 0x20, 0x22, 0x22, 0x00, 0x00, 0x11,
0x11, 0x11, 0x11, 0x01}
};
/*
* Radar channel sets
*/
/* Channels 52 - 64, 100 - 140 */
static const struct brcms_chanvec radar_set1 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, /* 52 - 60 */
0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, /* 64, 100 - 124 */
0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 128 - 140 */
0x00, 0x00, 0x00, 0x00}
};
/*
* Restricted channel sets
*/
/* Channels 34, 38, 42, 46 */
static const struct brcms_chanvec restricted_set_japan_legacy = {
{0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* Channels 12, 13 */
static const struct brcms_chanvec restricted_set_2g_short = {
{0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* Channel 165 */
static const struct brcms_chanvec restricted_chan_165 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* Channels 36 - 48 & 149 - 165 */
static const struct brcms_chanvec restricted_low_hi = {
{0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x20, 0x22, 0x22, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* Channels 12 - 14 */
static const struct brcms_chanvec restricted_set_12_13_14 = {
{0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
/* global memory to provide working buffer for expanded locale */
static const struct brcms_chanvec *g_table_radar_set[] = {
&chanvec_none,
&radar_set1
};
static const struct brcms_chanvec *g_table_restricted_chan[] = {
&chanvec_none, /* restricted_set_none */
&restricted_set_2g_short,
&restricted_chan_165,
&chanvec_all_5G,
&restricted_set_japan_legacy,
&chanvec_all_2G, /* restricted_set_11d_2G */
&chanvec_all_5G, /* restricted_set_11d_5G */
&restricted_low_hi,
&restricted_set_12_13_14
};
static const struct brcms_chanvec locale_2g_01_11 = {
{0xfe, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_2g_12_13 = {
{0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_2g_14 = {
{0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_LOW_JP1 = {
{0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_LOW_JP2 = {
{0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_LOW1 = {
{0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_LOW2 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_LOW3 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_MID1 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_MID2 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_MID3 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_HIGH1 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_HIGH2 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x20, 0x22, 0x02, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_HIGH3 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_52_140_ALL = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11,
0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
0x11, 0x11, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00}
};
static const struct brcms_chanvec locale_5g_HIGH4 = {
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
0x11, 0x11, 0x11, 0x11}
};
static const struct brcms_chanvec *g_table_locale_base[] = {
&locale_2g_01_11,
&locale_2g_12_13,
&locale_2g_14,
&locale_5g_LOW_JP1,
&locale_5g_LOW_JP2,
&locale_5g_LOW1,
&locale_5g_LOW2,
&locale_5g_LOW3,
&locale_5g_MID1,
&locale_5g_MID2,
&locale_5g_MID3,
&locale_5g_HIGH1,
&locale_5g_HIGH2,
&locale_5g_HIGH3,
&locale_5g_52_140_ALL,
&locale_5g_HIGH4
};
static void brcms_c_locale_add_channels(struct brcms_chanvec *target,
const struct brcms_chanvec *channels)
{
u8 i;
for (i = 0; i < sizeof(struct brcms_chanvec); i++)
target->vec[i] |= channels->vec[i];
}
static void brcms_c_locale_get_channels(const struct locale_info *locale,
struct brcms_chanvec *channels)
{
u8 i;
memset(channels, 0, sizeof(struct brcms_chanvec));
for (i = 0; i < ARRAY_SIZE(g_table_locale_base); i++) {
if (locale->valid_channels & (1 << i))
brcms_c_locale_add_channels(channels,
g_table_locale_base[i]);
}
}
/*
* Locale Definitions - 2.4 GHz
*/
static const struct locale_info locale_i = { /* locale i. channel 1 - 13 */
LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13,
LOCALE_RADAR_SET_NONE,
LOCALE_RESTRICTED_SET_2G_SHORT,
{QDB(19), QDB(19), QDB(19),
QDB(19), QDB(19), QDB(19)},
{20, 20, 20, 0},
BRCMS_EIRP
};
/*
* Locale Definitions - 5 GHz
*/
static const struct locale_info locale_11 = {
/* locale 11. channel 36 - 48, 52 - 64, 100 - 140, 149 - 165 */
LOCALE_CHAN_36_64 | LOCALE_CHAN_100_140 | LOCALE_CHAN_149_165,
LOCALE_RADAR_SET_1,
LOCALE_RESTRICTED_NONE,
{QDB(21), QDB(21), QDB(21), QDB(21), QDB(21)},
{23, 23, 23, 30, 30},
BRCMS_EIRP | BRCMS_DFS_EU
};
static const struct locale_info *g_locale_2g_table[] = {
&locale_i
};
static const struct locale_info *g_locale_5g_table[] = {
&locale_11
};
/*
* MIMO Locale Definitions - 2.4 GHz
*/
static const struct locale_mimo_info locale_bn = {
{QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
QDB(13), QDB(13), QDB(13)},
{0, 0, QDB(13), QDB(13), QDB(13),
QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
QDB(13), 0, 0},
0
};
static const struct locale_mimo_info *g_mimo_2g_table[] = {
&locale_bn
};
/*
* MIMO Locale Definitions - 5 GHz
*/
static const struct locale_mimo_info locale_11n = {
{ /* 12.5 dBm */ 50, 50, 50, QDB(15), QDB(15)},
{QDB(14), QDB(15), QDB(15), QDB(15), QDB(15)},
0
};
static const struct locale_mimo_info *g_mimo_5g_table[] = {
&locale_11n
};
static const struct {
char abbrev[BRCM_CNTRY_BUF_SZ]; /* country abbreviation */
struct country_info country;
} cntry_locales[] = {
{
"X2", LOCALES(i, 11, bn, 11n)}, /* Worldwide RoW 2 */
};
#ifdef SUPPORT_40MHZ
/* 20MHz channel info for 40MHz pairing support */
struct chan20_info {
u8 sb;
u8 adj_sbs;
};
/* indicates adjacent channels that are allowed for a 40 Mhz channel and
* those that permitted by the HT
*/
struct chan20_info chan20_info[] = {
/* 11b/11g */
/* 0 */ {1, (CH_UPPER_SB | CH_EWA_VALID)},
/* 1 */ {2, (CH_UPPER_SB | CH_EWA_VALID)},
/* 2 */ {3, (CH_UPPER_SB | CH_EWA_VALID)},
/* 3 */ {4, (CH_UPPER_SB | CH_EWA_VALID)},
/* 4 */ {5, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
/* 5 */ {6, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
/* 6 */ {7, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
/* 7 */ {8, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
/* 8 */ {9, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
/* 9 */ {10, (CH_LOWER_SB | CH_EWA_VALID)},
/* 10 */ {11, (CH_LOWER_SB | CH_EWA_VALID)},
/* 11 */ {12, (CH_LOWER_SB)},
/* 12 */ {13, (CH_LOWER_SB)},
/* 13 */ {14, (CH_LOWER_SB)},
/* 11a japan high */
/* 14 */ {34, (CH_UPPER_SB)},
/* 15 */ {38, (CH_LOWER_SB)},
/* 16 */ {42, (CH_LOWER_SB)},
/* 17 */ {46, (CH_LOWER_SB)},
/* 11a usa low */
/* 18 */ {36, (CH_UPPER_SB | CH_EWA_VALID)},
/* 19 */ {40, (CH_LOWER_SB | CH_EWA_VALID)},
/* 20 */ {44, (CH_UPPER_SB | CH_EWA_VALID)},
/* 21 */ {48, (CH_LOWER_SB | CH_EWA_VALID)},
/* 22 */ {52, (CH_UPPER_SB | CH_EWA_VALID)},
/* 23 */ {56, (CH_LOWER_SB | CH_EWA_VALID)},
/* 24 */ {60, (CH_UPPER_SB | CH_EWA_VALID)},
/* 25 */ {64, (CH_LOWER_SB | CH_EWA_VALID)},
/* 11a Europe */
/* 26 */ {100, (CH_UPPER_SB | CH_EWA_VALID)},
/* 27 */ {104, (CH_LOWER_SB | CH_EWA_VALID)},
/* 28 */ {108, (CH_UPPER_SB | CH_EWA_VALID)},
/* 29 */ {112, (CH_LOWER_SB | CH_EWA_VALID)},
/* 30 */ {116, (CH_UPPER_SB | CH_EWA_VALID)},
/* 31 */ {120, (CH_LOWER_SB | CH_EWA_VALID)},
/* 32 */ {124, (CH_UPPER_SB | CH_EWA_VALID)},
/* 33 */ {128, (CH_LOWER_SB | CH_EWA_VALID)},
/* 34 */ {132, (CH_UPPER_SB | CH_EWA_VALID)},
/* 35 */ {136, (CH_LOWER_SB | CH_EWA_VALID)},
/* 36 */ {140, (CH_LOWER_SB)},
/* 11a usa high, ref5 only */
/* The 0x80 bit in pdiv means these are REF5, other entries are REF20 */
/* 37 */ {149, (CH_UPPER_SB | CH_EWA_VALID)},
/* 38 */ {153, (CH_LOWER_SB | CH_EWA_VALID)},
/* 39 */ {157, (CH_UPPER_SB | CH_EWA_VALID)},
/* 40 */ {161, (CH_LOWER_SB | CH_EWA_VALID)},
/* 41 */ {165, (CH_LOWER_SB)},
/* 11a japan */
/* 42 */ {184, (CH_UPPER_SB)},
/* 43 */ {188, (CH_LOWER_SB)},
/* 44 */ {192, (CH_UPPER_SB)},
/* 45 */ {196, (CH_LOWER_SB)},
/* 46 */ {200, (CH_UPPER_SB)},
/* 47 */ {204, (CH_LOWER_SB)},
/* 48 */ {208, (CH_UPPER_SB)},
/* 49 */ {212, (CH_LOWER_SB)},
/* 50 */ {216, (CH_LOWER_SB)}
};
#endif /* SUPPORT_40MHZ */
static const struct locale_info *brcms_c_get_locale_2g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_locale_2g_table))
return NULL; /* error condition */
return g_locale_2g_table[locale_idx];
}
static const struct locale_info *brcms_c_get_locale_5g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_locale_5g_table))
return NULL; /* error condition */
return g_locale_5g_table[locale_idx];
}
static const struct locale_mimo_info *brcms_c_get_mimo_2g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table))
return NULL;
return g_mimo_2g_table[locale_idx];
}
static const struct locale_mimo_info *brcms_c_get_mimo_5g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_mimo_5g_table))
return NULL;
return g_mimo_5g_table[locale_idx];
}
static int
brcms_c_country_aggregate_map(struct brcms_cm_info *wlc_cm, const char *ccode,
char *mapped_ccode, uint *mapped_regrev)
{
return false;
}
/* Lookup a country info structure from a null terminated country
* abbreviation and regrev directly with no translation.
*/
static const struct country_info *
brcms_c_country_lookup_direct(const char *ccode, uint regrev)
{
uint size, i;
/* Should just return 0 for single locale driver. */
/* Keep it this way in case we add more locales. (for now anyway) */
/*
* all other country def arrays are for regrev == 0, so if
* regrev is non-zero, fail
*/
if (regrev > 0)
return NULL;
/* find matched table entry from country code */
size = ARRAY_SIZE(cntry_locales);
for (i = 0; i < size; i++) {
if (strcmp(ccode, cntry_locales[i].abbrev) == 0)
return &cntry_locales[i].country;
}
return NULL;
}
static const struct country_info *
brcms_c_countrycode_map(struct brcms_cm_info *wlc_cm, const char *ccode,
char *mapped_ccode, uint *mapped_regrev)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
const struct country_info *country;
uint srom_regrev = wlc_cm->srom_regrev;
const char *srom_ccode = wlc_cm->srom_ccode;
int mapped;
/* check for currently supported ccode size */
if (strlen(ccode) > (BRCM_CNTRY_BUF_SZ - 1)) {
wiphy_err(wlc->wiphy, "wl%d: %s: ccode \"%s\" too long for "
"match\n", wlc->pub->unit, __func__, ccode);
return NULL;
}
/* default mapping is the given ccode and regrev 0 */
strncpy(mapped_ccode, ccode, BRCM_CNTRY_BUF_SZ);
*mapped_regrev = 0;
/* If the desired country code matches the srom country code,
* then the mapped country is the srom regulatory rev.
* Otherwise look for an aggregate mapping.
*/
if (!strcmp(srom_ccode, ccode)) {
*mapped_regrev = srom_regrev;
mapped = 0;
wiphy_err(wlc->wiphy, "srom_code == ccode %s\n", __func__);
} else {
mapped =
brcms_c_country_aggregate_map(wlc_cm, ccode, mapped_ccode,
mapped_regrev);
}
/* find the matching built-in country definition */
country = brcms_c_country_lookup_direct(mapped_ccode, *mapped_regrev);
/* if there is not an exact rev match, default to rev zero */
if (country == NULL && *mapped_regrev != 0) {
*mapped_regrev = 0;
country =
brcms_c_country_lookup_direct(mapped_ccode, *mapped_regrev);
}
return country;
}
/* Lookup a country info structure from a null terminated country code
* The lookup is case sensitive.
*/
static const struct country_info *
brcms_c_country_lookup(struct brcms_c_info *wlc, const char *ccode)
{
const struct country_info *country;
char mapped_ccode[BRCM_CNTRY_BUF_SZ];
uint mapped_regrev;
/*
* map the country code to a built-in country code, regrev, and
* country_info struct
*/
country = brcms_c_countrycode_map(wlc->cmi, ccode, mapped_ccode,
&mapped_regrev);
return country;
}
/*
* reset the quiet channels vector to the union
* of the restricted and radar channel sets
*/
static void brcms_c_quiet_channels_reset(struct brcms_cm_info *wlc_cm)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
uint i, j;
struct brcms_band *band;
const struct brcms_chanvec *chanvec;
memset(&wlc_cm->quiet_channels, 0, sizeof(struct brcms_chanvec));
band = wlc->band;
for (i = 0; i < wlc->pub->_nbands;
i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
/* initialize quiet channels for restricted channels */
chanvec = wlc_cm->bandstate[band->bandunit].restricted_channels;
for (j = 0; j < sizeof(struct brcms_chanvec); j++)
wlc_cm->quiet_channels.vec[j] |= chanvec->vec[j];
}
}
/* Is the channel valid for the current locale and current band? */
static bool brcms_c_valid_channel20(struct brcms_cm_info *wlc_cm, uint val)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
return ((val < MAXCHANNEL) &&
isset(wlc_cm->bandstate[wlc->band->bandunit].valid_channels.vec,
val));
}
/* Is the channel valid for the current locale and specified band? */
static bool brcms_c_valid_channel20_in_band(struct brcms_cm_info *wlc_cm,
uint bandunit, uint val)
{
return ((val < MAXCHANNEL)
&& isset(wlc_cm->bandstate[bandunit].valid_channels.vec, val));
}
/* Is the channel valid for the current locale? (but don't consider channels not
* available due to bandlocking)
*/
static bool brcms_c_valid_channel20_db(struct brcms_cm_info *wlc_cm, uint val)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
return brcms_c_valid_channel20(wlc->cmi, val) ||
(!wlc->bandlocked
&& brcms_c_valid_channel20_in_band(wlc->cmi,
OTHERBANDUNIT(wlc), val));
}
/* JP, J1 - J10 are Japan ccodes */
static bool brcms_c_japan_ccode(const char *ccode)
{
return (ccode[0] == 'J' &&
(ccode[1] == 'P' || (ccode[1] >= '1' && ccode[1] <= '9')));
}
/* Returns true if currently set country is Japan or variant */
static bool brcms_c_japan(struct brcms_c_info *wlc)
{
return brcms_c_japan_ccode(wlc->cmi->country_abbrev);
}
static void
brcms_c_channel_min_txpower_limits_with_local_constraint(
struct brcms_cm_info *wlc_cm, struct txpwr_limits *txpwr,
u8 local_constraint_qdbm)
{
int j;
/* CCK Rates */
for (j = 0; j < WL_TX_POWER_CCK_NUM; j++)
txpwr->cck[j] = min(txpwr->cck[j], local_constraint_qdbm);
/* 20 MHz Legacy OFDM SISO */
for (j = 0; j < WL_TX_POWER_OFDM_NUM; j++)
txpwr->ofdm[j] = min(txpwr->ofdm[j], local_constraint_qdbm);
/* 20 MHz Legacy OFDM CDD */
for (j = 0; j < BRCMS_NUM_RATES_OFDM; j++)
txpwr->ofdm_cdd[j] =
min(txpwr->ofdm_cdd[j], local_constraint_qdbm);
/* 40 MHz Legacy OFDM SISO */
for (j = 0; j < BRCMS_NUM_RATES_OFDM; j++)
txpwr->ofdm_40_siso[j] =
min(txpwr->ofdm_40_siso[j], local_constraint_qdbm);
/* 40 MHz Legacy OFDM CDD */
for (j = 0; j < BRCMS_NUM_RATES_OFDM; j++)
txpwr->ofdm_40_cdd[j] =
min(txpwr->ofdm_40_cdd[j], local_constraint_qdbm);
/* 20MHz MCS 0-7 SISO */
for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
txpwr->mcs_20_siso[j] =
min(txpwr->mcs_20_siso[j], local_constraint_qdbm);
/* 20MHz MCS 0-7 CDD */
for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
txpwr->mcs_20_cdd[j] =
min(txpwr->mcs_20_cdd[j], local_constraint_qdbm);
/* 20MHz MCS 0-7 STBC */
for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
txpwr->mcs_20_stbc[j] =
min(txpwr->mcs_20_stbc[j], local_constraint_qdbm);
/* 20MHz MCS 8-15 MIMO */
for (j = 0; j < BRCMS_NUM_RATES_MCS_2_STREAM; j++)
txpwr->mcs_20_mimo[j] =
min(txpwr->mcs_20_mimo[j], local_constraint_qdbm);
/* 40MHz MCS 0-7 SISO */
for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
txpwr->mcs_40_siso[j] =
min(txpwr->mcs_40_siso[j], local_constraint_qdbm);
/* 40MHz MCS 0-7 CDD */
for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
txpwr->mcs_40_cdd[j] =
min(txpwr->mcs_40_cdd[j], local_constraint_qdbm);
/* 40MHz MCS 0-7 STBC */
for (j = 0; j < BRCMS_NUM_RATES_MCS_1_STREAM; j++)
txpwr->mcs_40_stbc[j] =
min(txpwr->mcs_40_stbc[j], local_constraint_qdbm);
/* 40MHz MCS 8-15 MIMO */
for (j = 0; j < BRCMS_NUM_RATES_MCS_2_STREAM; j++)
txpwr->mcs_40_mimo[j] =
min(txpwr->mcs_40_mimo[j], local_constraint_qdbm);
/* 40MHz MCS 32 */
txpwr->mcs32 = min(txpwr->mcs32, local_constraint_qdbm);
}
/* Update the radio state (enable/disable) and tx power targets
* based on a new set of channel/regulatory information
*/
static void brcms_c_channels_commit(struct brcms_cm_info *wlc_cm)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
uint chan;
struct txpwr_limits txpwr;
/* search for the existence of any valid channel */
for (chan = 0; chan < MAXCHANNEL; chan++) {
if (brcms_c_valid_channel20_db(wlc->cmi, chan))
break;
}
if (chan == MAXCHANNEL)
chan = INVCHANNEL;
/*
* based on the channel search above, set or
* clear WL_RADIO_COUNTRY_DISABLE.
*/
if (chan == INVCHANNEL) {
/*
* country/locale with no valid channels, set
* the radio disable bit
*/
mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\" "
"nbands %d bandlocked %d\n", wlc->pub->unit,
__func__, wlc_cm->country_abbrev, wlc->pub->_nbands,
wlc->bandlocked);
} else if (mboolisset(wlc->pub->radio_disabled,
WL_RADIO_COUNTRY_DISABLE)) {
/*
* country/locale with valid channel, clear
* the radio disable bit
*/
mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
}
/*
* Now that the country abbreviation is set, if the radio supports 2G,
* then set channel 14 restrictions based on the new locale.
*/
if (wlc->pub->_nbands > 1 || wlc->band->bandtype == BRCM_BAND_2G)
wlc_phy_chanspec_ch14_widefilter_set(wlc->band->pi,
brcms_c_japan(wlc) ? true :
false);
if (wlc->pub->up && chan != INVCHANNEL) {
brcms_c_channel_reg_limits(wlc_cm, wlc->chanspec, &txpwr);
brcms_c_channel_min_txpower_limits_with_local_constraint(wlc_cm,
&txpwr, BRCMS_TXPWR_MAX);
wlc_phy_txpower_limit_set(wlc->band->pi, &txpwr, wlc->chanspec);
}
}
static int
brcms_c_channels_init(struct brcms_cm_info *wlc_cm,
const struct country_info *country)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
uint i, j;
struct brcms_band *band;
const struct locale_info *li;
struct brcms_chanvec sup_chan;
const struct locale_mimo_info *li_mimo;
band = wlc->band;
for (i = 0; i < wlc->pub->_nbands;
i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
li = (band->bandtype == BRCM_BAND_5G) ?
brcms_c_get_locale_5g(country->locale_5G) :
brcms_c_get_locale_2g(country->locale_2G);
wlc_cm->bandstate[band->bandunit].locale_flags = li->flags;
li_mimo = (band->bandtype == BRCM_BAND_5G) ?
brcms_c_get_mimo_5g(country->locale_mimo_5G) :
brcms_c_get_mimo_2g(country->locale_mimo_2G);
/* merge the mimo non-mimo locale flags */
wlc_cm->bandstate[band->bandunit].locale_flags |=
li_mimo->flags;
wlc_cm->bandstate[band->bandunit].restricted_channels =
g_table_restricted_chan[li->restricted_channels];
wlc_cm->bandstate[band->bandunit].radar_channels =
g_table_radar_set[li->radar_channels];
/*
* set the channel availability, masking out the channels
* that may not be supported on this phy.
*/
wlc_phy_chanspec_band_validch(band->pi, band->bandtype,
&sup_chan);
brcms_c_locale_get_channels(li,
&wlc_cm->bandstate[band->bandunit].
valid_channels);
for (j = 0; j < sizeof(struct brcms_chanvec); j++)
wlc_cm->bandstate[band->bandunit].valid_channels.
vec[j] &= sup_chan.vec[j];
}
brcms_c_quiet_channels_reset(wlc_cm);
brcms_c_channels_commit(wlc_cm);
return 0;
}
/*
* set the driver's current country and regulatory information
* using a country code as the source. Look up built in country
* information found with the country code.
*/
static void
brcms_c_set_country_common(struct brcms_cm_info *wlc_cm,
const char *country_abbrev,
const char *ccode, uint regrev,
const struct country_info *country)
{
const struct locale_info *locale;
struct brcms_c_info *wlc = wlc_cm->wlc;
char prev_country_abbrev[BRCM_CNTRY_BUF_SZ];
/* save current country state */
wlc_cm->country = country;
memset(&prev_country_abbrev, 0, BRCM_CNTRY_BUF_SZ);
strncpy(prev_country_abbrev, wlc_cm->country_abbrev,
BRCM_CNTRY_BUF_SZ - 1);
strncpy(wlc_cm->country_abbrev, country_abbrev, BRCM_CNTRY_BUF_SZ - 1);
strncpy(wlc_cm->ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
wlc_cm->regrev = regrev;
if ((wlc->pub->_n_enab & SUPPORT_11N) !=
wlc->protection->nmode_user)
brcms_c_set_nmode(wlc);
brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
brcms_c_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
/* set or restore gmode as required by regulatory */
locale = brcms_c_get_locale_2g(country->locale_2G);
if (locale && (locale->flags & BRCMS_NO_OFDM))
brcms_c_set_gmode(wlc, GMODE_LEGACY_B, false);
else
brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
brcms_c_channels_init(wlc_cm, country);
return;
}
static int
brcms_c_set_countrycode_rev(struct brcms_cm_info *wlc_cm,
const char *country_abbrev,
const char *ccode, int regrev)
{
const struct country_info *country;
char mapped_ccode[BRCM_CNTRY_BUF_SZ];
uint mapped_regrev;
/* if regrev is -1, lookup the mapped country code,
* otherwise use the ccode and regrev directly
*/
if (regrev == -1) {
/*
* map the country code to a built-in country
* code, regrev, and country_info
*/
country =
brcms_c_countrycode_map(wlc_cm, ccode, mapped_ccode,
&mapped_regrev);
} else {
/* find the matching built-in country definition */
country = brcms_c_country_lookup_direct(ccode, regrev);
strncpy(mapped_ccode, ccode, BRCM_CNTRY_BUF_SZ);
mapped_regrev = regrev;
}
if (country == NULL)
return -EINVAL;
/* set the driver state for the country */
brcms_c_set_country_common(wlc_cm, country_abbrev, mapped_ccode,
mapped_regrev, country);
return 0;
}
/*
* set the driver's current country and regulatory information using
* a country code as the source. Lookup built in country information
* found with the country code.
*/
static int
brcms_c_set_countrycode(struct brcms_cm_info *wlc_cm, const char *ccode)
{
char country_abbrev[BRCM_CNTRY_BUF_SZ];
strncpy(country_abbrev, ccode, BRCM_CNTRY_BUF_SZ);
return brcms_c_set_countrycode_rev(wlc_cm, country_abbrev, ccode, -1);
}
struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)
{
struct brcms_cm_info *wlc_cm;
char country_abbrev[BRCM_CNTRY_BUF_SZ];
const struct country_info *country;
struct brcms_pub *pub = wlc->pub;
char *ccode;
BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
wlc_cm = kzalloc(sizeof(struct brcms_cm_info), GFP_ATOMIC);
if (wlc_cm == NULL)
return NULL;
wlc_cm->pub = pub;
wlc_cm->wlc = wlc;
wlc->cmi = wlc_cm;
/* store the country code for passing up as a regulatory hint */
ccode = getvar(wlc->hw->sih, BRCMS_SROM_CCODE);
if (ccode)
strncpy(wlc->pub->srom_ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
/*
* internal country information which must match
* regulatory constraints in firmware
*/
memset(country_abbrev, 0, BRCM_CNTRY_BUF_SZ);
strncpy(country_abbrev, "X2", sizeof(country_abbrev) - 1);
country = brcms_c_country_lookup(wlc, country_abbrev);
/* save default country for exiting 11d regulatory mode */
strncpy(wlc->country_default, country_abbrev, BRCM_CNTRY_BUF_SZ - 1);
/* initialize autocountry_default to driver default */
strncpy(wlc->autocountry_default, "X2", BRCM_CNTRY_BUF_SZ - 1);
brcms_c_set_countrycode(wlc_cm, country_abbrev);
return wlc_cm;
}
void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm)
{
kfree(wlc_cm);
}
u8
brcms_c_channel_locale_flags_in_band(struct brcms_cm_info *wlc_cm,
uint bandunit)
{
return wlc_cm->bandstate[bandunit].locale_flags;
}
static bool
brcms_c_quiet_chanspec(struct brcms_cm_info *wlc_cm, u16 chspec)
{
return (wlc_cm->wlc->pub->_n_enab & SUPPORT_11N) &&
CHSPEC_IS40(chspec) ?
(isset(wlc_cm->quiet_channels.vec,
lower_20_sb(CHSPEC_CHANNEL(chspec))) ||
isset(wlc_cm->quiet_channels.vec,
upper_20_sb(CHSPEC_CHANNEL(chspec)))) :
isset(wlc_cm->quiet_channels.vec, CHSPEC_CHANNEL(chspec));
}
void
brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec,
u8 local_constraint_qdbm)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
struct txpwr_limits txpwr;
brcms_c_channel_reg_limits(wlc_cm, chanspec, &txpwr);
brcms_c_channel_min_txpower_limits_with_local_constraint(
wlc_cm, &txpwr, local_constraint_qdbm
);
brcms_b_set_chanspec(wlc->hw, chanspec,
(brcms_c_quiet_chanspec(wlc_cm, chanspec) != 0),
&txpwr);
}
void
brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
struct txpwr_limits *txpwr)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
uint i;
uint chan;
int maxpwr;
int delta;
const struct country_info *country;
struct brcms_band *band;
const struct locale_info *li;
int conducted_max = BRCMS_TXPWR_MAX;
int conducted_ofdm_max = BRCMS_TXPWR_MAX;
const struct locale_mimo_info *li_mimo;
int maxpwr20, maxpwr40;
int maxpwr_idx;
uint j;
memset(txpwr, 0, sizeof(struct txpwr_limits));
if (!brcms_c_valid_chanspec_db(wlc_cm, chanspec)) {
country = brcms_c_country_lookup(wlc, wlc->autocountry_default);
if (country == NULL)
return;
} else {
country = wlc_cm->country;
}
chan = CHSPEC_CHANNEL(chanspec);
band = wlc->bandstate[chspec_bandunit(chanspec)];
li = (band->bandtype == BRCM_BAND_5G) ?
brcms_c_get_locale_5g(country->locale_5G) :
brcms_c_get_locale_2g(country->locale_2G);
li_mimo = (band->bandtype == BRCM_BAND_5G) ?
brcms_c_get_mimo_5g(country->locale_mimo_5G) :
brcms_c_get_mimo_2g(country->locale_mimo_2G);
if (li->flags & BRCMS_EIRP) {
delta = band->antgain;
} else {
delta = 0;
if (band->antgain > QDB(6))
delta = band->antgain - QDB(6); /* Excess over 6 dB */
}
if (li == &locale_i) {
conducted_max = QDB(22);
conducted_ofdm_max = QDB(22);
}
/* CCK txpwr limits for 2.4G band */
if (band->bandtype == BRCM_BAND_2G) {
maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_CCK(chan)];
maxpwr = maxpwr - delta;
maxpwr = max(maxpwr, 0);
maxpwr = min(maxpwr, conducted_max);
for (i = 0; i < BRCMS_NUM_RATES_CCK; i++)
txpwr->cck[i] = (u8) maxpwr;
}
/* OFDM txpwr limits for 2.4G or 5G bands */
if (band->bandtype == BRCM_BAND_2G)
maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_OFDM(chan)];
else
maxpwr = li->maxpwr[CHANNEL_POWER_IDX_5G(chan)];
maxpwr = maxpwr - delta;
maxpwr = max(maxpwr, 0);
maxpwr = min(maxpwr, conducted_ofdm_max);
/* Keep OFDM lmit below CCK limit */
if (band->bandtype == BRCM_BAND_2G)
maxpwr = min_t(int, maxpwr, txpwr->cck[0]);
for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++)
txpwr->ofdm[i] = (u8) maxpwr;
for (i = 0; i < BRCMS_NUM_RATES_OFDM; i++) {
/*
* OFDM 40 MHz SISO has the same power as the corresponding
* MCS0-7 rate unless overriden by the locale specific code.
* We set this value to 0 as a flag (presumably 0 dBm isn't
* a possibility) and then copy the MCS0-7 value to the 40 MHz
* value if it wasn't explicitly set.
*/
txpwr->ofdm_40_siso[i] = 0;
txpwr->ofdm_cdd[i] = (u8) maxpwr;
txpwr->ofdm_40_cdd[i] = 0;
}
/* MIMO/HT specific limits */
if (li_mimo->flags & BRCMS_EIRP) {
delta = band->antgain;
} else {
delta = 0;
if (band->antgain > QDB(6))
delta = band->antgain - QDB(6); /* Excess over 6 dB */
}
if (band->bandtype == BRCM_BAND_2G)
maxpwr_idx = (chan - 1);
else
maxpwr_idx = CHANNEL_POWER_IDX_5G(chan);
maxpwr20 = li_mimo->maxpwr20[maxpwr_idx];
maxpwr40 = li_mimo->maxpwr40[maxpwr_idx];
maxpwr20 = maxpwr20 - delta;
maxpwr20 = max(maxpwr20, 0);
maxpwr40 = maxpwr40 - delta;
maxpwr40 = max(maxpwr40, 0);
/* Fill in the MCS 0-7 (SISO) rates */
for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
/*
* 20 MHz has the same power as the corresponding OFDM rate
* unless overriden by the locale specific code.
*/
txpwr->mcs_20_siso[i] = txpwr->ofdm[i];
txpwr->mcs_40_siso[i] = 0;
}
/* Fill in the MCS 0-7 CDD rates */
for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
txpwr->mcs_20_cdd[i] = (u8) maxpwr20;
txpwr->mcs_40_cdd[i] = (u8) maxpwr40;
}
/*
* These locales have SISO expressed in the
* table and override CDD later
*/
if (li_mimo == &locale_bn) {
if (li_mimo == &locale_bn) {
maxpwr20 = QDB(16);
maxpwr40 = 0;
if (chan >= 3 && chan <= 11)
maxpwr40 = QDB(16);
}
for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
txpwr->mcs_20_siso[i] = (u8) maxpwr20;
txpwr->mcs_40_siso[i] = (u8) maxpwr40;
}
}
/* Fill in the MCS 0-7 STBC rates */
for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
txpwr->mcs_20_stbc[i] = 0;
txpwr->mcs_40_stbc[i] = 0;
}
/* Fill in the MCS 8-15 SDM rates */
for (i = 0; i < BRCMS_NUM_RATES_MCS_2_STREAM; i++) {
txpwr->mcs_20_mimo[i] = (u8) maxpwr20;
txpwr->mcs_40_mimo[i] = (u8) maxpwr40;
}
/* Fill in MCS32 */
txpwr->mcs32 = (u8) maxpwr40;
for (i = 0, j = 0; i < BRCMS_NUM_RATES_OFDM; i++, j++) {
if (txpwr->ofdm_40_cdd[i] == 0)
txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
if (i == 0) {
i = i + 1;
if (txpwr->ofdm_40_cdd[i] == 0)
txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
}
}
/*
* Copy the 40 MHZ MCS 0-7 CDD value to the 40 MHZ MCS 0-7 SISO
* value if it wasn't provided explicitly.
*/
for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
if (txpwr->mcs_40_siso[i] == 0)
txpwr->mcs_40_siso[i] = txpwr->mcs_40_cdd[i];
}
for (i = 0, j = 0; i < BRCMS_NUM_RATES_OFDM; i++, j++) {
if (txpwr->ofdm_40_siso[i] == 0)
txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
if (i == 0) {
i = i + 1;
if (txpwr->ofdm_40_siso[i] == 0)
txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
}
}
/*
* Copy the 20 and 40 MHz MCS0-7 CDD values to the corresponding
* STBC values if they weren't provided explicitly.
*/
for (i = 0; i < BRCMS_NUM_RATES_MCS_1_STREAM; i++) {
if (txpwr->mcs_20_stbc[i] == 0)
txpwr->mcs_20_stbc[i] = txpwr->mcs_20_cdd[i];
if (txpwr->mcs_40_stbc[i] == 0)
txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i];
}
return;
}
/*
* Verify the chanspec is using a legal set of parameters, i.e. that the
* chanspec specified a band, bw, ctl_sb and channel and that the
* combination could be legal given any set of circumstances.
* RETURNS: true is the chanspec is malformed, false if it looks good.
*/
static bool brcms_c_chspec_malformed(u16 chanspec)
{
/* must be 2G or 5G band */
if (!CHSPEC_IS5G(chanspec) && !CHSPEC_IS2G(chanspec))
return true;
/* must be 20 or 40 bandwidth */
if (!CHSPEC_IS40(chanspec) && !CHSPEC_IS20(chanspec))
return true;
/* 20MHZ b/w must have no ctl sb, 40 must have a ctl sb */
if (CHSPEC_IS20(chanspec)) {
if (!CHSPEC_SB_NONE(chanspec))
return true;
} else if (!CHSPEC_SB_UPPER(chanspec) && !CHSPEC_SB_LOWER(chanspec)) {
return true;
}
return false;
}
/*
* Validate the chanspec for this locale, for 40MHZ we need to also
* check that the sidebands are valid 20MZH channels in this locale
* and they are also a legal HT combination
*/
static bool
brcms_c_valid_chanspec_ext(struct brcms_cm_info *wlc_cm, u16 chspec,
bool dualband)
{
struct brcms_c_info *wlc = wlc_cm->wlc;
u8 channel = CHSPEC_CHANNEL(chspec);
/* check the chanspec */
if (brcms_c_chspec_malformed(chspec)) {
wiphy_err(wlc->wiphy, "wl%d: malformed chanspec 0x%x\n",
wlc->pub->unit, chspec);
return false;
}
if (CHANNEL_BANDUNIT(wlc_cm->wlc, channel) !=
chspec_bandunit(chspec))
return false;
/* Check a 20Mhz channel */
if (CHSPEC_IS20(chspec)) {
if (dualband)
return brcms_c_valid_channel20_db(wlc_cm->wlc->cmi,
channel);
else
return brcms_c_valid_channel20(wlc_cm->wlc->cmi,
channel);
}
#ifdef SUPPORT_40MHZ
/*
* We know we are now checking a 40MHZ channel, so we should
* only be here for NPHYS
*/
if (BRCMS_ISNPHY(wlc->band) || BRCMS_ISSSLPNPHY(wlc->band)) {
u8 upper_sideband = 0, idx;
u8 num_ch20_entries =
sizeof(chan20_info) / sizeof(struct chan20_info);
if (!VALID_40CHANSPEC_IN_BAND(wlc, chspec_bandunit(chspec)))
return false;
if (dualband) {
if (!brcms_c_valid_channel20_db(wlc->cmi,
lower_20_sb(channel)) ||
!brcms_c_valid_channel20_db(wlc->cmi,
upper_20_sb(channel)))
return false;
} else {
if (!brcms_c_valid_channel20(wlc->cmi,
lower_20_sb(channel)) ||
!brcms_c_valid_channel20(wlc->cmi,
upper_20_sb(channel)))
return false;
}
/* find the lower sideband info in the sideband array */
for (idx = 0; idx < num_ch20_entries; idx++) {
if (chan20_info[idx].sb == lower_20_sb(channel))
upper_sideband = chan20_info[idx].adj_sbs;
}
/* check that the lower sideband allows an upper sideband */
if ((upper_sideband & (CH_UPPER_SB | CH_EWA_VALID)) ==
(CH_UPPER_SB | CH_EWA_VALID))
return true;
return false;
}
#endif /* 40 MHZ */
return false;
}
bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm, u16 chspec)
{
return brcms_c_valid_chanspec_ext(wlc_cm, chspec, true);
}
| gpl-2.0 |
Tk-Glitch/Glitch_Flo_AOSP | drivers/net/wireless/b43/tables_nphy.c | 4965 | 137771 | /*
Broadcom B43 wireless driver
IEEE 802.11n PHY data tables
Copyright (c) 2008 Michael Buesch <m@bues.ch>
Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
#include "b43.h"
#include "tables_nphy.h"
#include "phy_common.h"
#include "phy_n.h"
static const u8 b43_ntab_adjustpower0[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 b43_ntab_adjustpower1[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u16 b43_ntab_bdi[] = {
0x0070, 0x0126, 0x012C, 0x0246, 0x048D, 0x04D2,
};
static const u32 b43_ntab_channelest[] = {
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
};
static const u8 b43_ntab_estimatepowerlt0[] = {
0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49,
0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41,
0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39,
0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31,
0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29,
0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21,
0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
};
static const u8 b43_ntab_estimatepowerlt1[] = {
0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49,
0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41,
0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39,
0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31,
0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29,
0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21,
0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
};
static const u8 b43_ntab_framelookup[] = {
0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16,
0x0A, 0x0C, 0x1C, 0x1C, 0x0B, 0x0D, 0x1E, 0x1E,
0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1A, 0x1A,
0x0E, 0x10, 0x20, 0x28, 0x0F, 0x11, 0x22, 0x2A,
};
static const u32 b43_ntab_framestruct[] = {
0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
0x09804506, 0x00100030, 0x09804507, 0x00100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A0C, 0x00100004, 0x01000A0D, 0x00100024,
0x0980450E, 0x00100034, 0x0980450F, 0x00100034,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
0x1980C506, 0x00100030, 0x21810506, 0x00100030,
0x21810506, 0x00100030, 0x01800504, 0x00100030,
0x11808505, 0x00100030, 0x29814507, 0x01100030,
0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
0x21810506, 0x00100030, 0x21810506, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
0x1980C50E, 0x00100038, 0x2181050E, 0x00100038,
0x2181050E, 0x00100038, 0x0180050C, 0x00100038,
0x1180850D, 0x00100038, 0x2981450F, 0x01100038,
0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
0x2181050E, 0x00100038, 0x2181050E, 0x00100038,
0x2981450F, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
0x1980C506, 0x00100030, 0x1980C506, 0x00100030,
0x11808504, 0x00100030, 0x3981CA05, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x10008A04, 0x00100000, 0x3981CA05, 0x00100030,
0x1980C506, 0x00100030, 0x29814507, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028,
0x1980C50E, 0x00100038, 0x1980C50E, 0x00100038,
0x1180850C, 0x00100038, 0x3981CA0D, 0x00100038,
0x2981450F, 0x01100038, 0x00000000, 0x00000000,
0x10008A0C, 0x00100008, 0x3981CA0D, 0x00100038,
0x1980C50E, 0x00100038, 0x2981450F, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x02001405, 0x00100040,
0x0B004A06, 0x01900060, 0x13008A06, 0x01900060,
0x13008A06, 0x01900060, 0x43020A04, 0x00100060,
0x1B00CA05, 0x00100060, 0x23010A07, 0x01500060,
0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
0x13008A06, 0x01900060, 0x13008A06, 0x01900060,
0x23010A07, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x0200140D, 0x00100050,
0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070,
0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070,
0x1B00CA0D, 0x00100070, 0x23010A0F, 0x01500070,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070,
0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x0B004A06, 0x01900060, 0x0B004A06, 0x01900060,
0x5B02CA04, 0x00100060, 0x3B01D405, 0x00100060,
0x23010A07, 0x01500060, 0x00000000, 0x00000000,
0x5802D404, 0x00100000, 0x3B01D405, 0x00100060,
0x0B004A06, 0x01900060, 0x23010A07, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x5002940C, 0x00100010, 0x3201940D, 0x00100050,
0x0B004A0E, 0x01900070, 0x0B004A0E, 0x01900070,
0x5B02CA0C, 0x00100070, 0x3B01D40D, 0x00100070,
0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
0x5802D40C, 0x00100010, 0x3B01D40D, 0x00100070,
0x0B004A0E, 0x01900070, 0x23010A0F, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x000F4800, 0x62031405, 0x00100040,
0x53028A06, 0x01900060, 0x53028A07, 0x01900060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x000F4808, 0x6203140D, 0x00100048,
0x53028A0E, 0x01900068, 0x53028A0F, 0x01900068,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A0C, 0x00100004, 0x11008A0D, 0x00100024,
0x1980C50E, 0x00100034, 0x2181050E, 0x00100034,
0x2181050E, 0x00100034, 0x0180050C, 0x00100038,
0x1180850D, 0x00100038, 0x1181850D, 0x00100038,
0x2981450F, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
0x2181050E, 0x00100038, 0x2181050E, 0x00100038,
0x1181850D, 0x00100038, 0x2981450F, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
0x0180C506, 0x00100030, 0x0180C506, 0x00100030,
0x2180C50C, 0x00100030, 0x49820A0D, 0x0016A130,
0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x2000CA0C, 0x00100000, 0x49820A0D, 0x0016A130,
0x1980C50E, 0x00100030, 0x41824A0D, 0x0016A130,
0x2981450F, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100008, 0x0200140D, 0x00100048,
0x0B004A0E, 0x01900068, 0x13008A0E, 0x01900068,
0x13008A0E, 0x01900068, 0x43020A0C, 0x00100070,
0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070,
0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070,
0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x03004A06, 0x01900060, 0x03004A06, 0x01900060,
0x6B030A0C, 0x00100060, 0x4B02140D, 0x0016A160,
0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x6B03140C, 0x00100060, 0x4B02140D, 0x0016A160,
0x0B004A0E, 0x01900060, 0x4302540D, 0x0016A160,
0x23010A0F, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
0x53028A06, 0x01900060, 0x5B02CA06, 0x01900060,
0x5B02CA06, 0x01900060, 0x43020A04, 0x00100060,
0x1B00CA05, 0x00100060, 0x53028A07, 0x0190C060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x53028A0E, 0x01900070, 0x5B02CA0E, 0x01900070,
0x5B02CA0E, 0x01900070, 0x43020A0C, 0x00100070,
0x1B00CA0D, 0x00100070, 0x53028A0F, 0x0190C070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060,
0x53028A07, 0x0190C060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070,
0x53028A0F, 0x0190C070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_gainctl0[] = {
0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E,
0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42,
0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B,
0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34,
0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E,
0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38,
0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32,
0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44,
0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D,
0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36,
0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40,
0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39,
0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33,
0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D,
0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E,
0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38,
0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42,
0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B,
0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34,
0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44,
0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D,
0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36,
0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30,
0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B,
0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26,
0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22,
0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E,
0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B,
0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00,
};
static const u32 b43_ntab_gainctl1[] = {
0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E,
0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42,
0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B,
0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34,
0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E,
0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38,
0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32,
0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44,
0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D,
0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36,
0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40,
0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39,
0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33,
0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D,
0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E,
0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38,
0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42,
0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B,
0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34,
0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44,
0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D,
0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36,
0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30,
0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B,
0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26,
0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22,
0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E,
0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B,
0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00,
};
static const u32 b43_ntab_intlevel[] = {
0x00802070, 0x0671188D, 0x0A60192C, 0x0A300E46,
0x00C1188D, 0x080024D2, 0x00000070,
};
static const u32 b43_ntab_iqlt0[] = {
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
};
static const u32 b43_ntab_iqlt1[] = {
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
};
static const u16 b43_ntab_loftlt0[] = {
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103,
};
static const u16 b43_ntab_loftlt1[] = {
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
0x0002, 0x0103,
};
static const u8 b43_ntab_mcs[] = {
0x00, 0x08, 0x0A, 0x10, 0x12, 0x19, 0x1A, 0x1C,
0x40, 0x48, 0x4A, 0x50, 0x52, 0x59, 0x5A, 0x5C,
0x80, 0x88, 0x8A, 0x90, 0x92, 0x99, 0x9A, 0x9C,
0xC0, 0xC8, 0xCA, 0xD0, 0xD2, 0xD9, 0xDA, 0xDC,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x01, 0x02, 0x04, 0x08, 0x09, 0x0A, 0x0C,
0x10, 0x11, 0x12, 0x14, 0x18, 0x19, 0x1A, 0x1C,
0x20, 0x21, 0x22, 0x24, 0x40, 0x41, 0x42, 0x44,
0x48, 0x49, 0x4A, 0x4C, 0x50, 0x51, 0x52, 0x54,
0x58, 0x59, 0x5A, 0x5C, 0x60, 0x61, 0x62, 0x64,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u32 b43_ntab_noisevar10[] = {
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
};
static const u32 b43_ntab_noisevar11[] = {
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
};
static const u16 b43_ntab_pilot[] = {
0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08,
0xFF08, 0xFF08, 0x80D5, 0x80D5, 0x80D5, 0x80D5,
0x80D5, 0x80D5, 0x80D5, 0x80D5, 0xFF0A, 0xFF82,
0xFFA0, 0xFF28, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
0xFF82, 0xFFA0, 0xFF28, 0xFF0A, 0xFFFF, 0xFFFF,
0xFFFF, 0xFFFF, 0xF83F, 0xFA1F, 0xFA97, 0xFAB5,
0xF2BD, 0xF0BF, 0xFFFF, 0xFFFF, 0xF017, 0xF815,
0xF215, 0xF095, 0xF035, 0xF01D, 0xFFFF, 0xFFFF,
0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xFF08, 0xFF02,
0xFF80, 0xFF20, 0xF01F, 0xF817, 0xFA15, 0xF295,
0xF0B5, 0xF03D, 0xFFFF, 0xFFFF, 0xF82A, 0xFA0A,
0xFA82, 0xFAA0, 0xF2A8, 0xF0AA, 0xFFFF, 0xFFFF,
0xF002, 0xF800, 0xF200, 0xF080, 0xF020, 0xF008,
0xFFFF, 0xFFFF, 0xF00A, 0xF802, 0xFA00, 0xF280,
0xF0A0, 0xF028, 0xFFFF, 0xFFFF,
};
static const u32 b43_ntab_pilotlt[] = {
0x76540123, 0x62407351, 0x76543201, 0x76540213,
0x76540123, 0x76430521,
};
static const u32 b43_ntab_tdi20a0[] = {
0x00091226, 0x000A1429, 0x000B56AD, 0x000C58B0,
0x000D5AB3, 0x000E9CB6, 0x000F9EBA, 0x0000C13D,
0x00020301, 0x00030504, 0x00040708, 0x0005090B,
0x00064B8E, 0x00095291, 0x000A5494, 0x000B9718,
0x000C9927, 0x000D9B2A, 0x000EDD2E, 0x000FDF31,
0x000101B4, 0x000243B7, 0x000345BB, 0x000447BE,
0x00058982, 0x00068C05, 0x00099309, 0x000A950C,
0x000BD78F, 0x000CD992, 0x000DDB96, 0x000F1D99,
0x00005FA8, 0x0001422C, 0x0002842F, 0x00038632,
0x00048835, 0x0005CA38, 0x0006CCBC, 0x0009D3BF,
0x000B1603, 0x000C1806, 0x000D1A0A, 0x000E1C0D,
0x000F5E10, 0x00008093, 0x00018297, 0x0002C49A,
0x0003C680, 0x0004C880, 0x00060B00, 0x00070D00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi20a1[] = {
0x00014B26, 0x00028D29, 0x000393AD, 0x00049630,
0x0005D833, 0x0006DA36, 0x00099C3A, 0x000A9E3D,
0x000BC081, 0x000CC284, 0x000DC488, 0x000F068B,
0x0000488E, 0x00018B91, 0x0002D214, 0x0003D418,
0x0004D6A7, 0x000618AA, 0x00071AAE, 0x0009DCB1,
0x000B1EB4, 0x000C0137, 0x000D033B, 0x000E053E,
0x000F4702, 0x00008905, 0x00020C09, 0x0003128C,
0x0004148F, 0x00051712, 0x00065916, 0x00091B19,
0x000A1D28, 0x000B5F2C, 0x000C41AF, 0x000D43B2,
0x000E85B5, 0x000F87B8, 0x0000C9BC, 0x00024CBF,
0x00035303, 0x00045506, 0x0005978A, 0x0006998D,
0x00095B90, 0x000A5D93, 0x000B9F97, 0x000C821A,
0x000D8400, 0x000EC600, 0x000FC800, 0x00010A00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a0[] = {
0x0011A346, 0x00136CCF, 0x0014F5D9, 0x001641E2,
0x0017CB6B, 0x00195475, 0x001B2383, 0x001CAD0C,
0x001E7616, 0x0000821F, 0x00020BA8, 0x0003D4B2,
0x00056447, 0x00072DD0, 0x0008B6DA, 0x000A02E3,
0x000B8C6C, 0x000D15F6, 0x0011E484, 0x0013AE0D,
0x00153717, 0x00168320, 0x00180CA9, 0x00199633,
0x001B6548, 0x001CEED1, 0x001EB7DB, 0x0000C3E4,
0x00024D6D, 0x000416F7, 0x0005A585, 0x00076F0F,
0x0008F818, 0x000A4421, 0x000BCDAB, 0x000D9734,
0x00122649, 0x0013EFD2, 0x001578DC, 0x0016C4E5,
0x00184E6E, 0x001A17F8, 0x001BA686, 0x001D3010,
0x001EF999, 0x00010522, 0x00028EAC, 0x00045835,
0x0005E74A, 0x0007B0D3, 0x00093A5D, 0x000A85E6,
0x000C0F6F, 0x000DD8F9, 0x00126787, 0x00143111,
0x0015BA9A, 0x00170623, 0x00188FAD, 0x001A5936,
0x001BE84B, 0x001DB1D4, 0x001F3B5E, 0x000146E7,
0x00031070, 0x000499FA, 0x00062888, 0x0007F212,
0x00097B9B, 0x000AC7A4, 0x000C50AE, 0x000E1A37,
0x0012A94C, 0x001472D5, 0x0015FC5F, 0x00174868,
0x0018D171, 0x001A9AFB, 0x001C2989, 0x001DF313,
0x001F7C9C, 0x000188A5, 0x000351AF, 0x0004DB38,
0x0006AA4D, 0x000833D7, 0x0009BD60, 0x000B0969,
0x000C9273, 0x000E5BFC, 0x00132A8A, 0x0014B414,
0x00163D9D, 0x001789A6, 0x001912B0, 0x001ADC39,
0x001C6BCE, 0x001E34D8, 0x001FBE61, 0x0001CA6A,
0x00039374, 0x00051CFD, 0x0006EC0B, 0x00087515,
0x0009FE9E, 0x000B4AA7, 0x000CD3B1, 0x000E9D3A,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a1[] = {
0x001EDB36, 0x000129CA, 0x0002B353, 0x00047CDD,
0x0005C8E6, 0x000791EF, 0x00091BF9, 0x000AAA07,
0x000C3391, 0x000DFD1A, 0x00120923, 0x0013D22D,
0x00155C37, 0x0016EACB, 0x00187454, 0x001A3DDE,
0x001B89E7, 0x001D12F0, 0x001F1CFA, 0x00016B88,
0x00033492, 0x0004BE1B, 0x00060A24, 0x0007D32E,
0x00095D38, 0x000AEC4C, 0x000C7555, 0x000E3EDF,
0x00124AE8, 0x001413F1, 0x0015A37B, 0x00172C89,
0x0018B593, 0x001A419C, 0x001BCB25, 0x001D942F,
0x001F63B9, 0x0001AD4D, 0x00037657, 0x0004C260,
0x00068BE9, 0x000814F3, 0x0009A47C, 0x000B2D8A,
0x000CB694, 0x000E429D, 0x00128C26, 0x001455B0,
0x0015E4BA, 0x00176E4E, 0x0018F758, 0x001A8361,
0x001C0CEA, 0x001DD674, 0x001FA57D, 0x0001EE8B,
0x0003B795, 0x0005039E, 0x0006CD27, 0x000856B1,
0x0009E5C6, 0x000B6F4F, 0x000CF859, 0x000E8462,
0x00130DEB, 0x00149775, 0x00162603, 0x0017AF8C,
0x00193896, 0x001AC49F, 0x001C4E28, 0x001E17B2,
0x0000A6C7, 0x00023050, 0x0003F9DA, 0x00054563,
0x00070EEC, 0x00089876, 0x000A2704, 0x000BB08D,
0x000D3A17, 0x001185A0, 0x00134F29, 0x0014D8B3,
0x001667C8, 0x0017F151, 0x00197ADB, 0x001B0664,
0x001C8FED, 0x001E5977, 0x0000E805, 0x0002718F,
0x00043B18, 0x000586A1, 0x0007502B, 0x0008D9B4,
0x000A68C9, 0x000BF252, 0x000DBBDC, 0x0011C7E5,
0x001390EE, 0x00151A78, 0x0016A906, 0x00183290,
0x0019BC19, 0x001B4822, 0x001CD12C, 0x001E9AB5,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdtrn[] = {
0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6,
0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68,
0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52,
0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050,
0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6,
0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68,
0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52,
0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050,
0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246,
0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C,
0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61,
0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D,
0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246,
0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C,
0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61,
0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D,
0xFA58FA58, 0xF895043B, 0xFF4C09C0, 0xFBC6FFA8,
0xFB84F384, 0x0798F6F9, 0x05760122, 0x058409F6,
0x0B500000, 0x05B7F542, 0x08860432, 0x06DDFEE7,
0xFB84F384, 0xF9D90664, 0xF7E8025C, 0x00FFF7BD,
0x05A805A8, 0xF7BD00FF, 0x025CF7E8, 0x0664F9D9,
0xF384FB84, 0xFEE706DD, 0x04320886, 0xF54205B7,
0x00000B50, 0x09F60584, 0x01220576, 0xF6F90798,
0xF384FB84, 0xFFA8FBC6, 0x09C0FF4C, 0x043BF895,
0x02D402D4, 0x07DE0270, 0xFC96079C, 0xF90AFE94,
0xFE00FF2C, 0x02D4065D, 0x092A0096, 0x0014FBB8,
0xFD2CFD2C, 0x076AFB3C, 0x0096F752, 0xF991FD87,
0xFB2C0200, 0xFEB8F960, 0x08E0FC96, 0x049802A8,
0xFD2CFD2C, 0x02A80498, 0xFC9608E0, 0xF960FEB8,
0x0200FB2C, 0xFD87F991, 0xF7520096, 0xFB3C076A,
0xFD2CFD2C, 0xFBB80014, 0x0096092A, 0x065D02D4,
0xFF2CFE00, 0xFE94F90A, 0x079CFC96, 0x027007DE,
0x02D402D4, 0x027007DE, 0x079CFC96, 0xFE94F90A,
0xFF2CFE00, 0x065D02D4, 0x0096092A, 0xFBB80014,
0xFD2CFD2C, 0xFB3C076A, 0xF7520096, 0xFD87F991,
0x0200FB2C, 0xF960FEB8, 0xFC9608E0, 0x02A80498,
0xFD2CFD2C, 0x049802A8, 0x08E0FC96, 0xFEB8F960,
0xFB2C0200, 0xF991FD87, 0x0096F752, 0x076AFB3C,
0xFD2CFD2C, 0x0014FBB8, 0x092A0096, 0x02D4065D,
0xFE00FF2C, 0xF90AFE94, 0xFC96079C, 0x07DE0270,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D,
0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF,
0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8,
0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7,
0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3,
0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841,
0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608,
0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759,
0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D,
0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF,
0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8,
0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7,
0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3,
0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841,
0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608,
0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759,
0x061C061C, 0xFF30009D, 0xFFB21141, 0xFD87FB54,
0xF65DFE59, 0x02EEF99E, 0x0166F03C, 0xFFF809B6,
0x000008A4, 0x000AF42B, 0x00EFF577, 0xFA840BF2,
0xFC02FF51, 0x08260F67, 0xFFF0036F, 0x0842F9C3,
0x00000000, 0x063DF7BE, 0xFC910010, 0xF099F7DA,
0x00AF03FE, 0xF40E057C, 0x0A89FF11, 0x0BD5FFF6,
0xF75C0000, 0xF64A0008, 0x0FC4FE9A, 0x0662FD12,
0x01A709A3, 0x04AC0279, 0xEEBF004E, 0xFF6300D0,
0xF9E4F9E4, 0x00D0FF63, 0x004EEEBF, 0x027904AC,
0x09A301A7, 0xFD120662, 0xFE9A0FC4, 0x0008F64A,
0x0000F75C, 0xFFF60BD5, 0xFF110A89, 0x057CF40E,
0x03FE00AF, 0xF7DAF099, 0x0010FC91, 0xF7BE063D,
0x00000000, 0xF9C30842, 0x036FFFF0, 0x0F670826,
0xFF51FC02, 0x0BF2FA84, 0xF57700EF, 0xF42B000A,
0x08A40000, 0x09B6FFF8, 0xF03C0166, 0xF99E02EE,
0xFE59F65D, 0xFB54FD87, 0x1141FFB2, 0x009DFF30,
0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59,
0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766,
0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986,
0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB,
0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7,
0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A,
0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A,
0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705,
0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59,
0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766,
0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986,
0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB,
0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7,
0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A,
0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A,
0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705,
0xFA58FA58, 0xF8F0FE00, 0x0448073D, 0xFDC9FE46,
0xF9910258, 0x089D0407, 0xFD5CF71A, 0x02AFFDE0,
0x083E0496, 0xFF5A0740, 0xFF7AFD97, 0x00FE01F1,
0x0009082E, 0xFA94FF75, 0xFECDF8EA, 0xFFB0F693,
0xFD2CFA58, 0x0433FF16, 0xFBA405DD, 0xFA610341,
0x06A606CB, 0x0039FD2D, 0x0677FA97, 0x01FA05E0,
0xF896003E, 0x075A068B, 0x012CFC3E, 0xFA23F98D,
0xFC7CFD43, 0xFF90FC0D, 0x01C10982, 0x00C601D6,
0xFD2CFD2C, 0x01D600C6, 0x098201C1, 0xFC0DFF90,
0xFD43FC7C, 0xF98DFA23, 0xFC3E012C, 0x068B075A,
0x003EF896, 0x05E001FA, 0xFA970677, 0xFD2D0039,
0x06CB06A6, 0x0341FA61, 0x05DDFBA4, 0xFF160433,
0xFA58FD2C, 0xF693FFB0, 0xF8EAFECD, 0xFF75FA94,
0x082E0009, 0x01F100FE, 0xFD97FF7A, 0x0740FF5A,
0x0496083E, 0xFDE002AF, 0xF71AFD5C, 0x0407089D,
0x0258F991, 0xFE46FDC9, 0x073D0448, 0xFE00F8F0,
0xFD2CFD2C, 0xFCE00500, 0xFC09FDDC, 0xFE680157,
0x04C70571, 0xFC3AFF21, 0xFCD70228, 0x056D0277,
0x0200FE00, 0x0022F927, 0xFE3C032B, 0xFC44FF3C,
0x03E9FBDB, 0x04570313, 0x04C9FF5C, 0x000D03B8,
0xFA580000, 0xFBE900D2, 0xF9D0FE0B, 0x0125FDF9,
0x042501BF, 0x0328FA2B, 0xFFA902F0, 0xFA250157,
0x0200FE00, 0x03740438, 0xFF0405FD, 0x030CFE52,
0x0037FB39, 0xFF6904C5, 0x04F8FD23, 0xFD31FC1B,
0xFD2CFD2C, 0xFC1BFD31, 0xFD2304F8, 0x04C5FF69,
0xFB390037, 0xFE52030C, 0x05FDFF04, 0x04380374,
0xFE000200, 0x0157FA25, 0x02F0FFA9, 0xFA2B0328,
0x01BF0425, 0xFDF90125, 0xFE0BF9D0, 0x00D2FBE9,
0x0000FA58, 0x03B8000D, 0xFF5C04C9, 0x03130457,
0xFBDB03E9, 0xFF3CFC44, 0x032BFE3C, 0xF9270022,
0xFE000200, 0x0277056D, 0x0228FCD7, 0xFF21FC3A,
0x057104C7, 0x0157FE68, 0xFDDCFC09, 0x0500FCE0,
0xFD2CFD2C, 0x0500FCE0, 0xFDDCFC09, 0x0157FE68,
0x057104C7, 0xFF21FC3A, 0x0228FCD7, 0x0277056D,
0xFE000200, 0xF9270022, 0x032BFE3C, 0xFF3CFC44,
0xFBDB03E9, 0x03130457, 0xFF5C04C9, 0x03B8000D,
0x0000FA58, 0x00D2FBE9, 0xFE0BF9D0, 0xFDF90125,
0x01BF0425, 0xFA2B0328, 0x02F0FFA9, 0x0157FA25,
0xFE000200, 0x04380374, 0x05FDFF04, 0xFE52030C,
0xFB390037, 0x04C5FF69, 0xFD2304F8, 0xFC1BFD31,
0xFD2CFD2C, 0xFD31FC1B, 0x04F8FD23, 0xFF6904C5,
0x0037FB39, 0x030CFE52, 0xFF0405FD, 0x03740438,
0x0200FE00, 0xFA250157, 0xFFA902F0, 0x0328FA2B,
0x042501BF, 0x0125FDF9, 0xF9D0FE0B, 0xFBE900D2,
0xFA580000, 0x000D03B8, 0x04C9FF5C, 0x04570313,
0x03E9FBDB, 0xFC44FF3C, 0xFE3C032B, 0x0022F927,
0x0200FE00, 0x056D0277, 0xFCD70228, 0xFC3AFF21,
0x04C70571, 0xFE680157, 0xFC09FDDC, 0xFCE00500,
0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E,
0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C,
0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926,
0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942,
0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382,
0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4,
0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA,
0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE,
0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E,
0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C,
0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926,
0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942,
0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382,
0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4,
0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA,
0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE,
};
static const u32 b43_ntab_tmap[] = {
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0xF1111110, 0x11111111, 0x11F11111, 0x00000111,
0x11000000, 0x1111F111, 0x11111111, 0x111111F1,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x000AA888,
0x88880000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA2222220, 0x22222222, 0x22C22222, 0x00000222,
0x22000000, 0x2222A222, 0x22222222, 0x222222A2,
0xF1111110, 0x11111111, 0x11F11111, 0x00011111,
0x11110000, 0x1111F111, 0x11111111, 0x111111F1,
0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00088AAA,
0xAAAA0000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
0xAAA8AAA0, 0x8AAA8AAA, 0xAA8A8A8A, 0x000AAA88,
0x8AAA0000, 0xAAA8A888, 0x8AA88A8A, 0x8A88A888,
0x08080A00, 0x0A08080A, 0x080A0A08, 0x00080808,
0x080A0000, 0x080A0808, 0x080A0808, 0x0A0A0A08,
0xA0A0A0A0, 0x80A0A080, 0x8080A0A0, 0x00008080,
0x80A00000, 0x80A080A0, 0xA080A0A0, 0x8080A0A0,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x99999000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888,
0x22000000, 0x2222B222, 0x22222222, 0x222222B2,
0xB2222220, 0x22222222, 0x22D22222, 0x00000222,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x33000000, 0x3333B333, 0x33333333, 0x333333B3,
0xB3333330, 0x33333333, 0x33D33333, 0x00000333,
0x22000000, 0x2222A222, 0x22222222, 0x222222A2,
0xA2222220, 0x22222222, 0x22C22222, 0x00000222,
0x99B99B00, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
0x9B99BB99, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888,
0x22222200, 0x2222F222, 0x22222222, 0x222222F2,
0x22222222, 0x22222222, 0x22F22222, 0x00000222,
0x11000000, 0x1111F111, 0x11111111, 0x11111111,
0xF1111111, 0x11111111, 0x11F11111, 0x01111111,
0xBB9BB900, 0xB9B9BB99, 0xB99BBBBB, 0xBBBB9B9B,
0xB9BB99BB, 0xB99999B9, 0xB9B9B99B, 0x00000BBB,
0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
0xA8AA88AA, 0xA88888A8, 0xA8A8A88A, 0x0A888AAA,
0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00000AAA,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0xBBBBBB00, 0x999BBBBB, 0x9BB99B9B, 0xB9B9B9BB,
0xB9B99BBB, 0xB9B9B9BB, 0xB9BB9B99, 0x00000999,
0x8A000000, 0xAA88A888, 0xA88888AA, 0xA88A8A88,
0xA88AA88A, 0x88A8AAAA, 0xA8AA8AAA, 0x0888A88A,
0x0B0B0B00, 0x090B0B0B, 0x0B090B0B, 0x0909090B,
0x09090B0B, 0x09090B0B, 0x09090B09, 0x00000909,
0x0A000000, 0x0A080808, 0x080A080A, 0x080A0A08,
0x080A080A, 0x0808080A, 0x0A0A0A08, 0x0808080A,
0xB0B0B000, 0x9090B0B0, 0x90B09090, 0xB0B0B090,
0xB0B090B0, 0x90B0B0B0, 0xB0B09090, 0x00000090,
0x80000000, 0xA080A080, 0xA08080A0, 0xA0808080,
0xA080A080, 0x80A0A0A0, 0xA0A080A0, 0x00A0A0A0,
0x22000000, 0x2222F222, 0x22222222, 0x222222F2,
0xF2222220, 0x22222222, 0x22F22222, 0x00000222,
0x11000000, 0x1111F111, 0x11111111, 0x111111F1,
0xF1111110, 0x11111111, 0x11F11111, 0x00000111,
0x33000000, 0x3333F333, 0x33333333, 0x333333F3,
0xF3333330, 0x33333333, 0x33F33333, 0x00000333,
0x22000000, 0x2222F222, 0x22222222, 0x222222F2,
0xF2222220, 0x22222222, 0x22F22222, 0x00000222,
0x99000000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88888000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888,
0x88A88A00, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
/* static tables, PHY revision >= 3 */
static const u32 b43_ntab_framestruct_r3[] = {
0x08004a04, 0x00100000, 0x01000a05, 0x00100020,
0x09804506, 0x00100030, 0x09804507, 0x00100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a0c, 0x00100004, 0x01000a0d, 0x00100024,
0x0980450e, 0x00100034, 0x0980450f, 0x00100034,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a04, 0x00100000, 0x11008a05, 0x00100020,
0x1980c506, 0x00100030, 0x21810506, 0x00100030,
0x21810506, 0x00100030, 0x01800504, 0x00100030,
0x11808505, 0x00100030, 0x29814507, 0x01100030,
0x00000a04, 0x00100000, 0x11008a05, 0x00100020,
0x21810506, 0x00100030, 0x21810506, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028,
0x1980c50e, 0x00100038, 0x2181050e, 0x00100038,
0x2181050e, 0x00100038, 0x0180050c, 0x00100038,
0x1180850d, 0x00100038, 0x2981450f, 0x01100038,
0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028,
0x2181050e, 0x00100038, 0x2181050e, 0x00100038,
0x2981450f, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a04, 0x00100000, 0x01000a05, 0x00100020,
0x1980c506, 0x00100030, 0x1980c506, 0x00100030,
0x11808504, 0x00100030, 0x3981ca05, 0x00100030,
0x29814507, 0x01100030, 0x00000000, 0x00000000,
0x10008a04, 0x00100000, 0x3981ca05, 0x00100030,
0x1980c506, 0x00100030, 0x29814507, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a0c, 0x00100008, 0x01000a0d, 0x00100028,
0x1980c50e, 0x00100038, 0x1980c50e, 0x00100038,
0x1180850c, 0x00100038, 0x3981ca0d, 0x00100038,
0x2981450f, 0x01100038, 0x00000000, 0x00000000,
0x10008a0c, 0x00100008, 0x3981ca0d, 0x00100038,
0x1980c50e, 0x00100038, 0x2981450f, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x02001405, 0x00100040,
0x0b004a06, 0x01900060, 0x13008a06, 0x01900060,
0x13008a06, 0x01900060, 0x43020a04, 0x00100060,
0x1b00ca05, 0x00100060, 0x23010a07, 0x01500060,
0x40021404, 0x00100000, 0x1a00d405, 0x00100040,
0x13008a06, 0x01900060, 0x13008a06, 0x01900060,
0x23010a07, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x0200140d, 0x00100050,
0x0b004a0e, 0x01900070, 0x13008a0e, 0x01900070,
0x13008a0e, 0x01900070, 0x43020a0c, 0x00100070,
0x1b00ca0d, 0x00100070, 0x23010a0f, 0x01500070,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070,
0x23010a0f, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x0b004a06, 0x01900060, 0x0b004a06, 0x01900060,
0x5b02ca04, 0x00100060, 0x3b01d405, 0x00100060,
0x23010a07, 0x01500060, 0x00000000, 0x00000000,
0x5802d404, 0x00100000, 0x3b01d405, 0x00100060,
0x0b004a06, 0x01900060, 0x23010a07, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x5002940c, 0x00100010, 0x3201940d, 0x00100050,
0x0b004a0e, 0x01900070, 0x0b004a0e, 0x01900070,
0x5b02ca0c, 0x00100070, 0x3b01d40d, 0x00100070,
0x23010a0f, 0x01500070, 0x00000000, 0x00000000,
0x5802d40c, 0x00100010, 0x3b01d40d, 0x00100070,
0x0b004a0e, 0x01900070, 0x23010a0f, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x000f4800, 0x62031405, 0x00100040,
0x53028a06, 0x01900060, 0x53028a07, 0x01900060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x000f4808, 0x6203140d, 0x00100048,
0x53028a0e, 0x01900068, 0x53028a0f, 0x01900068,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a0c, 0x00100004, 0x11008a0d, 0x00100024,
0x1980c50e, 0x00100034, 0x2181050e, 0x00100034,
0x2181050e, 0x00100034, 0x0180050c, 0x00100038,
0x1180850d, 0x00100038, 0x1181850d, 0x00100038,
0x2981450f, 0x01100038, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028,
0x2181050e, 0x00100038, 0x2181050e, 0x00100038,
0x1181850d, 0x00100038, 0x2981450f, 0x01100038,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x08004a04, 0x00100000, 0x01000a05, 0x00100020,
0x0180c506, 0x00100030, 0x0180c506, 0x00100030,
0x2180c50c, 0x00100030, 0x49820a0d, 0x0016a130,
0x41824a0d, 0x0016a130, 0x2981450f, 0x01100030,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x2000ca0c, 0x00100000, 0x49820a0d, 0x0016a130,
0x1980c50e, 0x00100030, 0x41824a0d, 0x0016a130,
0x2981450f, 0x01100030, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100008, 0x0200140d, 0x00100048,
0x0b004a0e, 0x01900068, 0x13008a0e, 0x01900068,
0x13008a0e, 0x01900068, 0x43020a0c, 0x00100070,
0x1b00ca0d, 0x00100070, 0x1b014a0d, 0x00100070,
0x23010a0f, 0x01500070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070,
0x1b014a0d, 0x00100070, 0x23010a0f, 0x01500070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x50029404, 0x00100000, 0x32019405, 0x00100040,
0x03004a06, 0x01900060, 0x03004a06, 0x01900060,
0x6b030a0c, 0x00100060, 0x4b02140d, 0x0016a160,
0x4302540d, 0x0016a160, 0x23010a0f, 0x01500060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x6b03140c, 0x00100060, 0x4b02140d, 0x0016a160,
0x0b004a0e, 0x01900060, 0x4302540d, 0x0016a160,
0x23010a0f, 0x01500060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1a00d405, 0x00100040,
0x53028a06, 0x01900060, 0x5b02ca06, 0x01900060,
0x5b02ca06, 0x01900060, 0x43020a04, 0x00100060,
0x1b00ca05, 0x00100060, 0x53028a07, 0x0190c060,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x53028a0e, 0x01900070, 0x5b02ca0e, 0x01900070,
0x5b02ca0e, 0x01900070, 0x43020a0c, 0x00100070,
0x1b00ca0d, 0x00100070, 0x53028a0f, 0x0190c070,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x40021404, 0x00100000, 0x1a00d405, 0x00100040,
0x5b02ca06, 0x01900060, 0x5b02ca06, 0x01900060,
0x53028a07, 0x0190c060, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050,
0x5b02ca0e, 0x01900070, 0x5b02ca0e, 0x01900070,
0x53028a0f, 0x0190c070, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u16 b43_ntab_pilot_r3[] = {
0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08,
0xff08, 0xff08, 0x80d5, 0x80d5, 0x80d5, 0x80d5,
0x80d5, 0x80d5, 0x80d5, 0x80d5, 0xff0a, 0xff82,
0xffa0, 0xff28, 0xffff, 0xffff, 0xffff, 0xffff,
0xff82, 0xffa0, 0xff28, 0xff0a, 0xffff, 0xffff,
0xffff, 0xffff, 0xf83f, 0xfa1f, 0xfa97, 0xfab5,
0xf2bd, 0xf0bf, 0xffff, 0xffff, 0xf017, 0xf815,
0xf215, 0xf095, 0xf035, 0xf01d, 0xffff, 0xffff,
0xff08, 0xff02, 0xff80, 0xff20, 0xff08, 0xff02,
0xff80, 0xff20, 0xf01f, 0xf817, 0xfa15, 0xf295,
0xf0b5, 0xf03d, 0xffff, 0xffff, 0xf82a, 0xfa0a,
0xfa82, 0xfaa0, 0xf2a8, 0xf0aa, 0xffff, 0xffff,
0xf002, 0xf800, 0xf200, 0xf080, 0xf020, 0xf008,
0xffff, 0xffff, 0xf00a, 0xf802, 0xfa00, 0xf280,
0xf0a0, 0xf028, 0xffff, 0xffff,
};
static const u32 b43_ntab_tmap_r3[] = {
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0xf1111110, 0x11111111, 0x11f11111, 0x00000111,
0x11000000, 0x1111f111, 0x11111111, 0x111111f1,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888,
0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa2222220, 0x22222222, 0x22c22222, 0x00000222,
0x22000000, 0x2222a222, 0x22222222, 0x222222a2,
0xf1111110, 0x11111111, 0x11f11111, 0x00011111,
0x11110000, 0x1111f111, 0x11111111, 0x111111f1,
0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa,
0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a,
0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88,
0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888,
0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808,
0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08,
0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080,
0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9,
0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888,
0x22000000, 0x2222b222, 0x22222222, 0x222222b2,
0xb2222220, 0x22222222, 0x22d22222, 0x00000222,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x33000000, 0x3333b333, 0x33333333, 0x333333b3,
0xb3333330, 0x33333333, 0x33d33333, 0x00000333,
0x22000000, 0x2222a222, 0x22222222, 0x222222a2,
0xa2222220, 0x22222222, 0x22c22222, 0x00000222,
0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9,
0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888,
0x22222200, 0x2222f222, 0x22222222, 0x222222f2,
0x22222222, 0x22222222, 0x22f22222, 0x00000222,
0x11000000, 0x1111f111, 0x11111111, 0x11111111,
0xf1111111, 0x11111111, 0x11f11111, 0x01111111,
0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b,
0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb,
0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a,
0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa,
0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a,
0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb,
0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999,
0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88,
0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a,
0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b,
0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909,
0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08,
0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a,
0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090,
0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090,
0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080,
0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0,
0x22000000, 0x2222f222, 0x22222222, 0x222222f2,
0xf2222220, 0x22222222, 0x22f22222, 0x00000222,
0x11000000, 0x1111f111, 0x11111111, 0x111111f1,
0xf1111110, 0x11111111, 0x11f11111, 0x00000111,
0x33000000, 0x3333f333, 0x33333333, 0x333333f3,
0xf3333330, 0x33333333, 0x33f33333, 0x00000333,
0x22000000, 0x2222f222, 0x22222222, 0x222222f2,
0xf2222220, 0x22222222, 0x22f22222, 0x00000222,
0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9,
0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888,
0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x11000000, 0x1111a111, 0x11111111, 0x111111a1,
0xa1111110, 0x11111111, 0x11c11111, 0x00000111,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8,
0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_intlevel_r3[] = {
0x00802070, 0x0671188d, 0x0a60192c, 0x0a300e46,
0x00c1188d, 0x080024d2, 0x00000070,
};
static const u32 b43_ntab_tdtrn_r3[] = {
0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6,
0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68,
0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52,
0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050,
0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6,
0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68,
0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52,
0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050,
0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246,
0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c,
0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61,
0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d,
0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246,
0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c,
0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61,
0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d,
0xfa58fa58, 0xf895043b, 0xff4c09c0, 0xfbc6ffa8,
0xfb84f384, 0x0798f6f9, 0x05760122, 0x058409f6,
0x0b500000, 0x05b7f542, 0x08860432, 0x06ddfee7,
0xfb84f384, 0xf9d90664, 0xf7e8025c, 0x00fff7bd,
0x05a805a8, 0xf7bd00ff, 0x025cf7e8, 0x0664f9d9,
0xf384fb84, 0xfee706dd, 0x04320886, 0xf54205b7,
0x00000b50, 0x09f60584, 0x01220576, 0xf6f90798,
0xf384fb84, 0xffa8fbc6, 0x09c0ff4c, 0x043bf895,
0x02d402d4, 0x07de0270, 0xfc96079c, 0xf90afe94,
0xfe00ff2c, 0x02d4065d, 0x092a0096, 0x0014fbb8,
0xfd2cfd2c, 0x076afb3c, 0x0096f752, 0xf991fd87,
0xfb2c0200, 0xfeb8f960, 0x08e0fc96, 0x049802a8,
0xfd2cfd2c, 0x02a80498, 0xfc9608e0, 0xf960feb8,
0x0200fb2c, 0xfd87f991, 0xf7520096, 0xfb3c076a,
0xfd2cfd2c, 0xfbb80014, 0x0096092a, 0x065d02d4,
0xff2cfe00, 0xfe94f90a, 0x079cfc96, 0x027007de,
0x02d402d4, 0x027007de, 0x079cfc96, 0xfe94f90a,
0xff2cfe00, 0x065d02d4, 0x0096092a, 0xfbb80014,
0xfd2cfd2c, 0xfb3c076a, 0xf7520096, 0xfd87f991,
0x0200fb2c, 0xf960feb8, 0xfc9608e0, 0x02a80498,
0xfd2cfd2c, 0x049802a8, 0x08e0fc96, 0xfeb8f960,
0xfb2c0200, 0xf991fd87, 0x0096f752, 0x076afb3c,
0xfd2cfd2c, 0x0014fbb8, 0x092a0096, 0x02d4065d,
0xfe00ff2c, 0xf90afe94, 0xfc96079c, 0x07de0270,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d,
0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf,
0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8,
0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7,
0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3,
0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841,
0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608,
0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759,
0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d,
0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf,
0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8,
0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7,
0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3,
0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841,
0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608,
0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759,
0x061c061c, 0xff30009d, 0xffb21141, 0xfd87fb54,
0xf65dfe59, 0x02eef99e, 0x0166f03c, 0xfff809b6,
0x000008a4, 0x000af42b, 0x00eff577, 0xfa840bf2,
0xfc02ff51, 0x08260f67, 0xfff0036f, 0x0842f9c3,
0x00000000, 0x063df7be, 0xfc910010, 0xf099f7da,
0x00af03fe, 0xf40e057c, 0x0a89ff11, 0x0bd5fff6,
0xf75c0000, 0xf64a0008, 0x0fc4fe9a, 0x0662fd12,
0x01a709a3, 0x04ac0279, 0xeebf004e, 0xff6300d0,
0xf9e4f9e4, 0x00d0ff63, 0x004eeebf, 0x027904ac,
0x09a301a7, 0xfd120662, 0xfe9a0fc4, 0x0008f64a,
0x0000f75c, 0xfff60bd5, 0xff110a89, 0x057cf40e,
0x03fe00af, 0xf7daf099, 0x0010fc91, 0xf7be063d,
0x00000000, 0xf9c30842, 0x036ffff0, 0x0f670826,
0xff51fc02, 0x0bf2fa84, 0xf57700ef, 0xf42b000a,
0x08a40000, 0x09b6fff8, 0xf03c0166, 0xf99e02ee,
0xfe59f65d, 0xfb54fd87, 0x1141ffb2, 0x009dff30,
0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59,
0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766,
0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986,
0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb,
0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7,
0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a,
0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a,
0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705,
0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59,
0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766,
0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986,
0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb,
0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7,
0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a,
0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a,
0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705,
0xfa58fa58, 0xf8f0fe00, 0x0448073d, 0xfdc9fe46,
0xf9910258, 0x089d0407, 0xfd5cf71a, 0x02affde0,
0x083e0496, 0xff5a0740, 0xff7afd97, 0x00fe01f1,
0x0009082e, 0xfa94ff75, 0xfecdf8ea, 0xffb0f693,
0xfd2cfa58, 0x0433ff16, 0xfba405dd, 0xfa610341,
0x06a606cb, 0x0039fd2d, 0x0677fa97, 0x01fa05e0,
0xf896003e, 0x075a068b, 0x012cfc3e, 0xfa23f98d,
0xfc7cfd43, 0xff90fc0d, 0x01c10982, 0x00c601d6,
0xfd2cfd2c, 0x01d600c6, 0x098201c1, 0xfc0dff90,
0xfd43fc7c, 0xf98dfa23, 0xfc3e012c, 0x068b075a,
0x003ef896, 0x05e001fa, 0xfa970677, 0xfd2d0039,
0x06cb06a6, 0x0341fa61, 0x05ddfba4, 0xff160433,
0xfa58fd2c, 0xf693ffb0, 0xf8eafecd, 0xff75fa94,
0x082e0009, 0x01f100fe, 0xfd97ff7a, 0x0740ff5a,
0x0496083e, 0xfde002af, 0xf71afd5c, 0x0407089d,
0x0258f991, 0xfe46fdc9, 0x073d0448, 0xfe00f8f0,
0xfd2cfd2c, 0xfce00500, 0xfc09fddc, 0xfe680157,
0x04c70571, 0xfc3aff21, 0xfcd70228, 0x056d0277,
0x0200fe00, 0x0022f927, 0xfe3c032b, 0xfc44ff3c,
0x03e9fbdb, 0x04570313, 0x04c9ff5c, 0x000d03b8,
0xfa580000, 0xfbe900d2, 0xf9d0fe0b, 0x0125fdf9,
0x042501bf, 0x0328fa2b, 0xffa902f0, 0xfa250157,
0x0200fe00, 0x03740438, 0xff0405fd, 0x030cfe52,
0x0037fb39, 0xff6904c5, 0x04f8fd23, 0xfd31fc1b,
0xfd2cfd2c, 0xfc1bfd31, 0xfd2304f8, 0x04c5ff69,
0xfb390037, 0xfe52030c, 0x05fdff04, 0x04380374,
0xfe000200, 0x0157fa25, 0x02f0ffa9, 0xfa2b0328,
0x01bf0425, 0xfdf90125, 0xfe0bf9d0, 0x00d2fbe9,
0x0000fa58, 0x03b8000d, 0xff5c04c9, 0x03130457,
0xfbdb03e9, 0xff3cfc44, 0x032bfe3c, 0xf9270022,
0xfe000200, 0x0277056d, 0x0228fcd7, 0xff21fc3a,
0x057104c7, 0x0157fe68, 0xfddcfc09, 0x0500fce0,
0xfd2cfd2c, 0x0500fce0, 0xfddcfc09, 0x0157fe68,
0x057104c7, 0xff21fc3a, 0x0228fcd7, 0x0277056d,
0xfe000200, 0xf9270022, 0x032bfe3c, 0xff3cfc44,
0xfbdb03e9, 0x03130457, 0xff5c04c9, 0x03b8000d,
0x0000fa58, 0x00d2fbe9, 0xfe0bf9d0, 0xfdf90125,
0x01bf0425, 0xfa2b0328, 0x02f0ffa9, 0x0157fa25,
0xfe000200, 0x04380374, 0x05fdff04, 0xfe52030c,
0xfb390037, 0x04c5ff69, 0xfd2304f8, 0xfc1bfd31,
0xfd2cfd2c, 0xfd31fc1b, 0x04f8fd23, 0xff6904c5,
0x0037fb39, 0x030cfe52, 0xff0405fd, 0x03740438,
0x0200fe00, 0xfa250157, 0xffa902f0, 0x0328fa2b,
0x042501bf, 0x0125fdf9, 0xf9d0fe0b, 0xfbe900d2,
0xfa580000, 0x000d03b8, 0x04c9ff5c, 0x04570313,
0x03e9fbdb, 0xfc44ff3c, 0xfe3c032b, 0x0022f927,
0x0200fe00, 0x056d0277, 0xfcd70228, 0xfc3aff21,
0x04c70571, 0xfe680157, 0xfc09fddc, 0xfce00500,
0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e,
0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c,
0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926,
0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942,
0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382,
0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4,
0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da,
0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be,
0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e,
0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c,
0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926,
0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942,
0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382,
0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4,
0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da,
0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be,
};
static const u32 b43_ntab_noisevar0_r3[] = {
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
};
static const u32 b43_ntab_noisevar1_r3[] = {
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
0x02110211, 0x0000014d, 0x02110211, 0x0000014d,
};
static const u16 b43_ntab_mcs_r3[] = {
0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019,
0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090,
0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108,
0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c,
0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199,
0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8,
0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128,
0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a,
0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8,
0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8,
0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa,
0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca,
0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001,
0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014,
0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081,
0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094,
0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
0x0007, 0x0007,
};
static const u32 b43_ntab_tdi20a0_r3[] = {
0x00091226, 0x000a1429, 0x000b56ad, 0x000c58b0,
0x000d5ab3, 0x000e9cb6, 0x000f9eba, 0x0000c13d,
0x00020301, 0x00030504, 0x00040708, 0x0005090b,
0x00064b8e, 0x00095291, 0x000a5494, 0x000b9718,
0x000c9927, 0x000d9b2a, 0x000edd2e, 0x000fdf31,
0x000101b4, 0x000243b7, 0x000345bb, 0x000447be,
0x00058982, 0x00068c05, 0x00099309, 0x000a950c,
0x000bd78f, 0x000cd992, 0x000ddb96, 0x000f1d99,
0x00005fa8, 0x0001422c, 0x0002842f, 0x00038632,
0x00048835, 0x0005ca38, 0x0006ccbc, 0x0009d3bf,
0x000b1603, 0x000c1806, 0x000d1a0a, 0x000e1c0d,
0x000f5e10, 0x00008093, 0x00018297, 0x0002c49a,
0x0003c680, 0x0004c880, 0x00060b00, 0x00070d00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi20a1_r3[] = {
0x00014b26, 0x00028d29, 0x000393ad, 0x00049630,
0x0005d833, 0x0006da36, 0x00099c3a, 0x000a9e3d,
0x000bc081, 0x000cc284, 0x000dc488, 0x000f068b,
0x0000488e, 0x00018b91, 0x0002d214, 0x0003d418,
0x0004d6a7, 0x000618aa, 0x00071aae, 0x0009dcb1,
0x000b1eb4, 0x000c0137, 0x000d033b, 0x000e053e,
0x000f4702, 0x00008905, 0x00020c09, 0x0003128c,
0x0004148f, 0x00051712, 0x00065916, 0x00091b19,
0x000a1d28, 0x000b5f2c, 0x000c41af, 0x000d43b2,
0x000e85b5, 0x000f87b8, 0x0000c9bc, 0x00024cbf,
0x00035303, 0x00045506, 0x0005978a, 0x0006998d,
0x00095b90, 0x000a5d93, 0x000b9f97, 0x000c821a,
0x000d8400, 0x000ec600, 0x000fc800, 0x00010a00,
0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a0_r3[] = {
0x0011a346, 0x00136ccf, 0x0014f5d9, 0x001641e2,
0x0017cb6b, 0x00195475, 0x001b2383, 0x001cad0c,
0x001e7616, 0x0000821f, 0x00020ba8, 0x0003d4b2,
0x00056447, 0x00072dd0, 0x0008b6da, 0x000a02e3,
0x000b8c6c, 0x000d15f6, 0x0011e484, 0x0013ae0d,
0x00153717, 0x00168320, 0x00180ca9, 0x00199633,
0x001b6548, 0x001ceed1, 0x001eb7db, 0x0000c3e4,
0x00024d6d, 0x000416f7, 0x0005a585, 0x00076f0f,
0x0008f818, 0x000a4421, 0x000bcdab, 0x000d9734,
0x00122649, 0x0013efd2, 0x001578dc, 0x0016c4e5,
0x00184e6e, 0x001a17f8, 0x001ba686, 0x001d3010,
0x001ef999, 0x00010522, 0x00028eac, 0x00045835,
0x0005e74a, 0x0007b0d3, 0x00093a5d, 0x000a85e6,
0x000c0f6f, 0x000dd8f9, 0x00126787, 0x00143111,
0x0015ba9a, 0x00170623, 0x00188fad, 0x001a5936,
0x001be84b, 0x001db1d4, 0x001f3b5e, 0x000146e7,
0x00031070, 0x000499fa, 0x00062888, 0x0007f212,
0x00097b9b, 0x000ac7a4, 0x000c50ae, 0x000e1a37,
0x0012a94c, 0x001472d5, 0x0015fc5f, 0x00174868,
0x0018d171, 0x001a9afb, 0x001c2989, 0x001df313,
0x001f7c9c, 0x000188a5, 0x000351af, 0x0004db38,
0x0006aa4d, 0x000833d7, 0x0009bd60, 0x000b0969,
0x000c9273, 0x000e5bfc, 0x00132a8a, 0x0014b414,
0x00163d9d, 0x001789a6, 0x001912b0, 0x001adc39,
0x001c6bce, 0x001e34d8, 0x001fbe61, 0x0001ca6a,
0x00039374, 0x00051cfd, 0x0006ec0b, 0x00087515,
0x0009fe9e, 0x000b4aa7, 0x000cd3b1, 0x000e9d3a,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_tdi40a1_r3[] = {
0x001edb36, 0x000129ca, 0x0002b353, 0x00047cdd,
0x0005c8e6, 0x000791ef, 0x00091bf9, 0x000aaa07,
0x000c3391, 0x000dfd1a, 0x00120923, 0x0013d22d,
0x00155c37, 0x0016eacb, 0x00187454, 0x001a3dde,
0x001b89e7, 0x001d12f0, 0x001f1cfa, 0x00016b88,
0x00033492, 0x0004be1b, 0x00060a24, 0x0007d32e,
0x00095d38, 0x000aec4c, 0x000c7555, 0x000e3edf,
0x00124ae8, 0x001413f1, 0x0015a37b, 0x00172c89,
0x0018b593, 0x001a419c, 0x001bcb25, 0x001d942f,
0x001f63b9, 0x0001ad4d, 0x00037657, 0x0004c260,
0x00068be9, 0x000814f3, 0x0009a47c, 0x000b2d8a,
0x000cb694, 0x000e429d, 0x00128c26, 0x001455b0,
0x0015e4ba, 0x00176e4e, 0x0018f758, 0x001a8361,
0x001c0cea, 0x001dd674, 0x001fa57d, 0x0001ee8b,
0x0003b795, 0x0005039e, 0x0006cd27, 0x000856b1,
0x0009e5c6, 0x000b6f4f, 0x000cf859, 0x000e8462,
0x00130deb, 0x00149775, 0x00162603, 0x0017af8c,
0x00193896, 0x001ac49f, 0x001c4e28, 0x001e17b2,
0x0000a6c7, 0x00023050, 0x0003f9da, 0x00054563,
0x00070eec, 0x00089876, 0x000a2704, 0x000bb08d,
0x000d3a17, 0x001185a0, 0x00134f29, 0x0014d8b3,
0x001667c8, 0x0017f151, 0x00197adb, 0x001b0664,
0x001c8fed, 0x001e5977, 0x0000e805, 0x0002718f,
0x00043b18, 0x000586a1, 0x0007502b, 0x0008d9b4,
0x000a68c9, 0x000bf252, 0x000dbbdc, 0x0011c7e5,
0x001390ee, 0x00151a78, 0x0016a906, 0x00183290,
0x0019bc19, 0x001b4822, 0x001cd12c, 0x001e9ab5,
0x00000000, 0x00000000,
};
static const u32 b43_ntab_pilotlt_r3[] = {
0x76540213, 0x62407351, 0x76543210, 0x76540213,
0x76540213, 0x76430521,
};
static const u32 b43_ntab_channelest_r3[] = {
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x44444444, 0x44444444, 0x44444444, 0x44444444,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
0x10101010, 0x10101010, 0x10101010, 0x10101010,
};
static const u8 b43_ntab_framelookup_r3[] = {
0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16,
0x0a, 0x0c, 0x1c, 0x1c, 0x0b, 0x0d, 0x1e, 0x1e,
0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1a, 0x1a,
0x0e, 0x10, 0x20, 0x28, 0x0f, 0x11, 0x22, 0x2a,
};
static const u8 b43_ntab_estimatepowerlt0_r3[] = {
0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51,
0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c,
0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46,
0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f,
0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36,
0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b,
0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a,
0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd,
};
static const u8 b43_ntab_estimatepowerlt1_r3[] = {
0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51,
0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c,
0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46,
0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f,
0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36,
0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b,
0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a,
0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd,
};
static const u8 b43_ntab_adjustpower0_r3[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u8 b43_ntab_adjustpower1_r3[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const u32 b43_ntab_gainctl0_r3[] = {
0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e,
0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037,
0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031,
0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040,
0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039,
0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033,
0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e,
0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037,
0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031,
0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c,
0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e,
0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037,
0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031,
0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c,
0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042,
0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b,
0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034,
0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f,
0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e,
0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037,
0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031,
0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c,
0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027,
0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023,
0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e,
0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037,
0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031,
0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c,
0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027,
0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023,
0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f,
0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c,
};
static const u32 b43_ntab_gainctl1_r3[] = {
0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e,
0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037,
0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031,
0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040,
0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039,
0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033,
0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e,
0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037,
0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031,
0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c,
0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e,
0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037,
0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031,
0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c,
0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042,
0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b,
0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034,
0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f,
0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e,
0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037,
0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031,
0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c,
0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027,
0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023,
0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e,
0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037,
0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031,
0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c,
0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027,
0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023,
0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f,
0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c,
};
static const u32 b43_ntab_iqlt0_r3[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u32 b43_ntab_iqlt1_r3[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
static const u16 b43_ntab_loftlt0_r3[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000,
};
static const u16 b43_ntab_loftlt1_r3[] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000,
};
/* volatile tables, PHY revision >= 3 */
/* indexed by antswctl2g */
static const u16 b43_ntab_antswctl2g_r3[4][32] = {
{
0x0082, 0x0082, 0x0211, 0x0222, 0x0328,
0x0000, 0x0000, 0x0000, 0x0144, 0x0000,
0x0000, 0x0000, 0x0188, 0x0000, 0x0000,
0x0000, 0x0082, 0x0082, 0x0211, 0x0222,
0x0328, 0x0000, 0x0000, 0x0000, 0x0144,
0x0000, 0x0000, 0x0000, 0x0188, 0x0000,
0x0000, 0x0000,
},
{
0x0022, 0x0022, 0x0011, 0x0022, 0x0022,
0x0000, 0x0000, 0x0000, 0x0011, 0x0000,
0x0000, 0x0000, 0x0022, 0x0000, 0x0000,
0x0000, 0x0022, 0x0022, 0x0011, 0x0022,
0x0022, 0x0000, 0x0000, 0x0000, 0x0011,
0x0000, 0x0000, 0x0000, 0x0022, 0x0000,
0x0000, 0x0000,
},
{
0x0088, 0x0088, 0x0044, 0x0088, 0x0088,
0x0000, 0x0000, 0x0000, 0x0044, 0x0000,
0x0000, 0x0000, 0x0088, 0x0000, 0x0000,
0x0000, 0x0088, 0x0088, 0x0044, 0x0088,
0x0088, 0x0000, 0x0000, 0x0000, 0x0044,
0x0000, 0x0000, 0x0000, 0x0088, 0x0000,
0x0000, 0x0000,
},
{
0x0022, 0x0022, 0x0011, 0x0022, 0x0000,
0x0000, 0x0000, 0x0000, 0x0011, 0x0000,
0x0000, 0x0000, 0x0022, 0x0000, 0x0000,
0x03cc, 0x0022, 0x0022, 0x0011, 0x0022,
0x0000, 0x0000, 0x0000, 0x0000, 0x0011,
0x0000, 0x0000, 0x0000, 0x0022, 0x0000,
0x0000, 0x03cc,
}
};
/* TX gain tables */
static const u32 b43_ntab_tx_gain_rev0_1_2[] = {
0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44,
0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844,
0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644,
0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444,
0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44,
0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844,
0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44,
0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944,
0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744,
0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544,
0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44,
0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844,
0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44,
0x03902b42, 0x03902a44, 0x03902a42, 0x03902944,
0x03902942, 0x03902844, 0x03902842, 0x03902744,
0x03902742, 0x03902644, 0x03902642, 0x03902544,
0x03902542, 0x03802b44, 0x03802b42, 0x03802a44,
0x03802a42, 0x03802944, 0x03802942, 0x03802844,
0x03802842, 0x03802744, 0x03802742, 0x03802644,
0x03802642, 0x03802544, 0x03802542, 0x03802444,
0x03802442, 0x03802344, 0x03802342, 0x03802244,
0x03802242, 0x03802144, 0x03802142, 0x03802044,
0x03802042, 0x03801f44, 0x03801f42, 0x03801e44,
0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44,
0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44,
0x03801a42, 0x03801944, 0x03801942, 0x03801844,
0x03801842, 0x03801744, 0x03801742, 0x03801644,
0x03801642, 0x03801544, 0x03801542, 0x03801444,
0x03801442, 0x03801344, 0x03801342, 0x00002b00,
};
static const u32 b43_ntab_tx_gain_rev3plus_2ghz[] = {
0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037,
0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e,
0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037,
0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e,
0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037,
0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e,
0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037,
0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e,
0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037,
0x19410044, 0x19410042, 0x19410040, 0x1941003e,
0x1941003c, 0x1941003b, 0x19410039, 0x19410037,
0x18410044, 0x18410042, 0x18410040, 0x1841003e,
0x1841003c, 0x1841003b, 0x18410039, 0x18410037,
0x17410044, 0x17410042, 0x17410040, 0x1741003e,
0x1741003c, 0x1741003b, 0x17410039, 0x17410037,
0x16410044, 0x16410042, 0x16410040, 0x1641003e,
0x1641003c, 0x1641003b, 0x16410039, 0x16410037,
0x15410044, 0x15410042, 0x15410040, 0x1541003e,
0x1541003c, 0x1541003b, 0x15410039, 0x15410037,
0x14410044, 0x14410042, 0x14410040, 0x1441003e,
0x1441003c, 0x1441003b, 0x14410039, 0x14410037,
0x13410044, 0x13410042, 0x13410040, 0x1341003e,
0x1341003c, 0x1341003b, 0x13410039, 0x13410037,
0x12410044, 0x12410042, 0x12410040, 0x1241003e,
0x1241003c, 0x1241003b, 0x12410039, 0x12410037,
0x11410044, 0x11410042, 0x11410040, 0x1141003e,
0x1141003c, 0x1141003b, 0x11410039, 0x11410037,
0x10410044, 0x10410042, 0x10410040, 0x1041003e,
0x1041003c, 0x1041003b, 0x10410039, 0x10410037,
};
static const u32 b43_ntab_tx_gain_rev3_5ghz[] = {
0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037,
0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e,
0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037,
0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e,
0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037,
0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e,
0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037,
0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e,
0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037,
0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e,
0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037,
0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e,
0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037,
0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e,
0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037,
0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e,
0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037,
0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e,
0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037,
0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e,
0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037,
0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e,
0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037,
0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e,
0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037,
0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e,
0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037,
0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e,
0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037,
};
static const u32 b43_ntab_tx_gain_rev4_5ghz[] = {
0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037,
0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e,
0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037,
0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e,
0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037,
0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e,
0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037,
0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e,
0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037,
0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e,
0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037,
0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e,
0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037,
0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e,
0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037,
0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e,
0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037,
0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e,
0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037,
0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e,
0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038,
0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e,
0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037,
0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e,
0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037,
0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e,
0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037,
0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c,
0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034,
};
static const u32 b43_ntab_tx_gain_rev5plus_5ghz[] = {
0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a,
0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e,
0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a,
0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e,
0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037,
0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040,
0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a,
0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c,
0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038,
0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b,
0x09620039, 0x09620037, 0x09620035, 0x09620033,
0x08620044, 0x08620042, 0x08620040, 0x0862003e,
0x0862003c, 0x0862003b, 0x0862003a, 0x08620039,
0x07620043, 0x07620042, 0x07620040, 0x0762003f,
0x0762003d, 0x0762003b, 0x0762003a, 0x07620039,
0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b,
0x06620039, 0x06620037, 0x06620035, 0x06620033,
0x05620046, 0x05620044, 0x05620042, 0x05620040,
0x0562003e, 0x0562003c, 0x0562003b, 0x05620039,
0x04620044, 0x04620042, 0x04620040, 0x0462003e,
0x0462003c, 0x0462003b, 0x04620039, 0x04620038,
0x0362003c, 0x0362003b, 0x0362003a, 0x03620039,
0x03620038, 0x03620037, 0x03620035, 0x03620033,
0x0262004c, 0x0262004a, 0x02620048, 0x02620047,
0x02620046, 0x02620044, 0x02620043, 0x02620042,
0x0162004a, 0x01620048, 0x01620046, 0x01620044,
0x01620043, 0x01620042, 0x01620041, 0x01620040,
0x00620042, 0x00620040, 0x0062003e, 0x0062003c,
0x0062003b, 0x00620039, 0x00620037, 0x00620035,
};
static const u32 txpwrctrl_tx_gain_ipa[] = {
0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025,
0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029,
0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025,
0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029,
0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025,
0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029,
0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025,
0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029,
0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025,
0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029,
0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025,
0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029,
0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025,
0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029,
0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025,
0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029,
0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025,
0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029,
0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025,
0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029,
0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025,
0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029,
0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025,
0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029,
0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025,
0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029,
0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025,
0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029,
0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025,
};
static const u32 txpwrctrl_tx_gain_ipa_rev5[] = {
0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025,
0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029,
0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025,
0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029,
0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025,
0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029,
0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025,
0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029,
0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025,
0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029,
0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025,
0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029,
0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025,
0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029,
0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025,
0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029,
0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025,
0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029,
0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025,
0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029,
0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025,
0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029,
0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025,
0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029,
0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025,
0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029,
0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025,
0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029,
0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025,
};
static const u32 txpwrctrl_tx_gain_ipa_rev6[] = {
0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025,
0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029,
0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025,
0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029,
0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025,
0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029,
0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025,
0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029,
0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025,
0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029,
0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025,
0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029,
0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025,
0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029,
0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025,
0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029,
0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025,
0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029,
0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025,
0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029,
0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025,
0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029,
0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025,
0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029,
0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025,
0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029,
0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025,
0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029,
0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025,
};
static const u32 txpwrctrl_tx_gain_ipa_5g[] = {
0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022,
0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025,
0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027,
0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023,
0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027,
0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022,
0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025,
0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021,
0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026,
0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022,
0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026,
0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022,
0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026,
0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022,
0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026,
0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022,
0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026,
0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021,
0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026,
0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029,
0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024,
0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027,
0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023,
0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026,
0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022,
0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025,
0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027,
0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022,
0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f,
};
const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[] = {
-114, -108, -98, -91, -84, -78, -70, -62,
-54, -46, -39, -31, -23, -15, -8, 0
};
const u16 tbl_iqcal_gainparams[2][9][8] = {
{
{ 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 },
{ 0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69 },
{ 0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68 },
{ 0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67 },
{ 0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66 },
{ 0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65 },
{ 0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65 },
{ 0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65 },
{ 0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65 }
},
{
{ 0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 },
{ 0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 },
{ 0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79 },
{ 0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78 },
{ 0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78 },
{ 0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78 },
{ 0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78 },
{ 0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78 },
{ 0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78 }
}
};
const struct nphy_txiqcal_ladder ladder_lo[] = {
{ 3, 0 },
{ 4, 0 },
{ 6, 0 },
{ 9, 0 },
{ 13, 0 },
{ 18, 0 },
{ 25, 0 },
{ 25, 1 },
{ 25, 2 },
{ 25, 3 },
{ 25, 4 },
{ 25, 5 },
{ 25, 6 },
{ 25, 7 },
{ 35, 7 },
{ 50, 7 },
{ 71, 7 },
{ 100, 7 }
};
const struct nphy_txiqcal_ladder ladder_iq[] = {
{ 3, 0 },
{ 4, 0 },
{ 6, 0 },
{ 9, 0 },
{ 13, 0 },
{ 18, 0 },
{ 25, 0 },
{ 35, 0 },
{ 50, 0 },
{ 71, 0 },
{ 100, 0 },
{ 100, 1 },
{ 100, 2 },
{ 100, 3 },
{ 100, 4 },
{ 100, 5 },
{ 100, 6 },
{ 100, 7 }
};
const u16 loscale[] = {
256, 256, 271, 271,
287, 256, 256, 271,
271, 287, 287, 304,
304, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 341,
341, 362, 362, 383,
383, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 256,
256, 271, 271, 287,
287, 304, 304, 322,
322, 341, 341, 362,
362, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 256,
256, 271, 271, 287,
287, 304, 304, 322,
322, 341, 341, 362,
362, 256, 256, 271,
271, 287, 287, 304,
304, 322, 322, 341,
341, 362, 362, 383,
383, 406, 406, 430,
430, 455, 455, 482,
482, 511, 511, 541,
541, 573, 573, 607,
607, 643, 643, 681,
681, 722, 722, 764,
764, 810, 810, 858,
858, 908, 908, 962,
962, 1019, 1019, 256
};
const u16 tbl_tx_iqlo_cal_loft_ladder_40[] = {
0x0200, 0x0300, 0x0400, 0x0700,
0x0900, 0x0c00, 0x1200, 0x1201,
0x1202, 0x1203, 0x1204, 0x1205,
0x1206, 0x1207, 0x1907, 0x2307,
0x3207, 0x4707
};
const u16 tbl_tx_iqlo_cal_loft_ladder_20[] = {
0x0300, 0x0500, 0x0700, 0x0900,
0x0d00, 0x1100, 0x1900, 0x1901,
0x1902, 0x1903, 0x1904, 0x1905,
0x1906, 0x1907, 0x2407, 0x3207,
0x4607, 0x6407
};
const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = {
0x0100, 0x0200, 0x0400, 0x0700,
0x0900, 0x0c00, 0x1200, 0x1900,
0x2300, 0x3200, 0x4700, 0x4701,
0x4702, 0x4703, 0x4704, 0x4705,
0x4706, 0x4707
};
const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = {
0x0200, 0x0300, 0x0600, 0x0900,
0x0d00, 0x1100, 0x1900, 0x2400,
0x3200, 0x4600, 0x6400, 0x6401,
0x6402, 0x6403, 0x6404, 0x6405,
0x6406, 0x6407
};
const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3] = { };
const u16 tbl_tx_iqlo_cal_startcoefs[B43_NTAB_TX_IQLO_CAL_STARTCOEFS] = { };
const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = {
0x8423, 0x8323, 0x8073, 0x8256,
0x8045, 0x8223, 0x9423, 0x9323,
0x9073, 0x9256, 0x9045, 0x9223
};
const u16 tbl_tx_iqlo_cal_cmds_recal[] = {
0x8101, 0x8253, 0x8053, 0x8234,
0x8034, 0x9101, 0x9253, 0x9053,
0x9234, 0x9034
};
const u16 tbl_tx_iqlo_cal_cmds_fullcal[] = {
0x8123, 0x8264, 0x8086, 0x8245,
0x8056, 0x9123, 0x9264, 0x9086,
0x9245, 0x9056
};
const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = {
0x8434, 0x8334, 0x8084, 0x8267,
0x8056, 0x8234, 0x9434, 0x9334,
0x9084, 0x9267, 0x9056, 0x9234
};
const s16 tbl_tx_filter_coef_rev4[7][15] = {
{ -377, 137, -407, 208, -1527,
956, 93, 186, 93, 230,
-44, 230, 201, -191, 201 },
{ -77, 20, -98, 49, -93,
60, 56, 111, 56, 26,
-5, 26, 34, -32, 34 },
{ -360, 164, -376, 164, -1533,
576, 308, -314, 308, 121,
-73, 121, 91, 124, 91 },
{ -295, 200, -363, 142, -1391,
826, 151, 301, 151, 151,
301, 151, 602, -752, 602 },
{ -92, 58, -96, 49, -104,
44, 17, 35, 17, 12,
25, 12, 13, 27, 13 },
{ -375, 136, -399, 209, -1479,
949, 130, 260, 130, 230,
-44, 230, 201, -191, 201 },
{ 0xed9, 0xc8, 0xe95, 0x8e, 0xa91,
0x33a, 0x97, 0x12d, 0x97, 0x97,
0x12d, 0x97, 0x25a, 0xd10, 0x25a }
};
/* addr0, addr1, bmask, shift */
const struct nphy_rf_control_override_rev2 tbl_rf_control_override_rev2[] = {
{ 0x78, 0x78, 0x0038, 3 }, /* for field == 0x0002 (fls == 2) */
{ 0x7A, 0x7D, 0x0001, 0 }, /* for field == 0x0004 (fls == 3) */
{ 0x7A, 0x7D, 0x0002, 1 }, /* for field == 0x0008 (fls == 4) */
{ 0x7A, 0x7D, 0x0004, 2 }, /* for field == 0x0010 (fls == 5) */
{ 0x7A, 0x7D, 0x0030, 4 }, /* for field == 0x0020 (fls == 6) */
{ 0x7A, 0x7D, 0x00C0, 6 }, /* for field == 0x0040 (fls == 7) */
{ 0x7A, 0x7D, 0x0100, 8 }, /* for field == 0x0080 (fls == 8) */
{ 0x7A, 0x7D, 0x0200, 9 }, /* for field == 0x0100 (fls == 9) */
{ 0x78, 0x78, 0x0004, 2 }, /* for field == 0x0200 (fls == 10) */
{ 0x7B, 0x7E, 0x01FF, 0 }, /* for field == 0x0400 (fls == 11) */
{ 0x7C, 0x7F, 0x01FF, 0 }, /* for field == 0x0800 (fls == 12) */
{ 0x78, 0x78, 0x0100, 8 }, /* for field == 0x1000 (fls == 13) */
{ 0x78, 0x78, 0x0200, 9 }, /* for field == 0x2000 (fls == 14) */
{ 0x78, 0x78, 0xF000, 12 } /* for field == 0x4000 (fls == 15) */
};
/* val_mask, val_shift, en_addr0, val_addr0, en_addr1, val_addr1 */
const struct nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = {
{ 0x8000, 15, 0xE5, 0xF9, 0xE6, 0xFB }, /* field == 0x0001 (fls 1) */
{ 0x0001, 0, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0002 (fls 2) */
{ 0x0002, 1, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0004 (fls 3) */
{ 0x0004, 2, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0008 (fls 4) */
{ 0x0010, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */
{ 0x0020, 5, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0020 (fls 6) */
{ 0x0040, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0040 (fls 7) */
{ 0x0080, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */
{ 0x0100, 8, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */
{ 0x0007, 0, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0200 (fls 10) */
{ 0x0070, 4, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0400 (fls 11) */
{ 0xE000, 13, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0800 (fls 12) */
{ 0xFFFF, 0, 0xE7, 0x7B, 0xEC, 0x7E }, /* field == 0x1000 (fls 13) */
{ 0xFFFF, 0, 0xE7, 0x7C, 0xEC, 0x7F }, /* field == 0x2000 (fls 14) */
{ 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */
};
struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = {
{ 10, 14, 19, 27 },
{ -5, 6, 10, 15 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x427E,
{ 0x413F, 0x413F, 0x413F, 0x413F },
0x007E, 0x0066, 0x1074,
0x18, 0x18, 0x18,
0x01D0, 0x5,
};
struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = {
{ /* 2GHz */
{ /* PHY rev 3 */
{ 7, 11, 16, 23 },
{ -5, 6, 10, 14 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x627E,
{ 0x613F, 0x613F, 0x613F, 0x613F },
0x107E, 0x0066, 0x0074,
0x18, 0x18, 0x18,
0x020D, 0x5,
},
{ /* PHY rev 4 */
{ 8, 12, 17, 25 },
{ -5, 6, 10, 14 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x527E,
{ 0x513F, 0x513F, 0x513F, 0x513F },
0x007E, 0x0066, 0x0074,
0x18, 0x18, 0x18,
0x01A1, 0x5,
},
{ /* PHY rev 5 */
{ 9, 13, 18, 26 },
{ -3, 7, 11, 16 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x427E, /* invalid for external LNA! */
{ 0x413F, 0x413F, 0x413F, 0x413F }, /* invalid for external LNA! */
0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */
0x18, 0x18, 0x18,
0x01D0, 0x9,
},
{ /* PHY rev 6+ */
{ 8, 13, 18, 25 },
{ -5, 6, 10, 14 },
{ 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x527E, /* invalid for external LNA! */
{ 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */
0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */
0x18, 0x18, 0x18,
0x01D0, 0x5,
},
},
{ /* 5GHz */
{ /* PHY rev 3 */
{ 7, 11, 17, 23 },
{ -6, 2, 6, 10 },
{ 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 },
{ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 },
0x52DE,
{ 0x516F, 0x516F, 0x516F, 0x516F },
0x00DE, 0x00CA, 0x00CC,
0x1E, 0x1E, 0x1E,
0x01A1, 25,
},
{ /* PHY rev 4 */
{ 8, 12, 18, 23 },
{ -5, 2, 6, 10 },
{ 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD },
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 },
0x629E,
{ 0x614F, 0x614F, 0x614F, 0x614F },
0x029E, 0x1084, 0x0086,
0x24, 0x24, 0x24,
0x0107, 25,
},
{ /* PHY rev 5 */
{ 6, 10, 16, 21 },
{ -7, 0, 4, 8 },
{ 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD },
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 },
0x729E,
{ 0x714F, 0x714F, 0x714F, 0x714F },
0x029E, 0x2084, 0x2086,
0x24, 0x24, 0x24,
0x00A9, 25,
},
{ /* PHY rev 6+ */
{ 6, 10, 16, 21 },
{ -7, 0, 4, 8 },
{ 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD },
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 },
0x729E,
{ 0x714F, 0x714F, 0x714F, 0x714F },
0x029E, 0x2084, 0x2086,
0x24, 0x24, 0x24, /* low is invalid for radio rev 11! */
0x00F0, 25,
},
},
};
static inline void assert_ntab_array_sizes(void)
{
#undef check
#define check(table, size) \
BUILD_BUG_ON(ARRAY_SIZE(b43_ntab_##table) != B43_NTAB_##size##_SIZE)
check(adjustpower0, C0_ADJPLT);
check(adjustpower1, C1_ADJPLT);
check(bdi, BDI);
check(channelest, CHANEST);
check(estimatepowerlt0, C0_ESTPLT);
check(estimatepowerlt1, C1_ESTPLT);
check(framelookup, FRAMELT);
check(framestruct, FRAMESTRUCT);
check(gainctl0, C0_GAINCTL);
check(gainctl1, C1_GAINCTL);
check(intlevel, INTLEVEL);
check(iqlt0, C0_IQLT);
check(iqlt1, C1_IQLT);
check(loftlt0, C0_LOFEEDTH);
check(loftlt1, C1_LOFEEDTH);
check(mcs, MCS);
check(noisevar10, NOISEVAR10);
check(noisevar11, NOISEVAR11);
check(pilot, PILOT);
check(pilotlt, PILOTLT);
check(tdi20a0, TDI20A0);
check(tdi20a1, TDI20A1);
check(tdi40a0, TDI40A0);
check(tdi40a1, TDI40A1);
check(tdtrn, TDTRN);
check(tmap, TMAP);
#undef check
}
u32 b43_ntab_read(struct b43_wldev *dev, u32 offset)
{
u32 type, value;
type = offset & B43_NTAB_TYPEMASK;
offset &= ~B43_NTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
switch (type) {
case B43_NTAB_8BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO) & 0xFF;
break;
case B43_NTAB_16BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
break;
case B43_NTAB_32BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
value |= b43_phy_read(dev, B43_NPHY_TABLE_DATAHI) << 16;
break;
default:
B43_WARN_ON(1);
value = 0;
}
return value;
}
void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset,
unsigned int nr_elements, void *_data)
{
u32 type;
u8 *data = _data;
unsigned int i;
type = offset & B43_NTAB_TYPEMASK;
offset &= ~B43_NTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
for (i = 0; i < nr_elements; i++) {
/* Auto increment broken + caching issue on BCM43224? */
if (dev->dev->chip_id == 43224 && dev->dev->chip_rev == 1) {
b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset + i);
}
switch (type) {
case B43_NTAB_8BIT:
*data = b43_phy_read(dev, B43_NPHY_TABLE_DATALO) & 0xFF;
data++;
break;
case B43_NTAB_16BIT:
*((u16 *)data) = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
data += 2;
break;
case B43_NTAB_32BIT:
*((u32 *)data) =
b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
*((u32 *)data) |=
b43_phy_read(dev, B43_NPHY_TABLE_DATAHI) << 16;
data += 4;
break;
default:
B43_WARN_ON(1);
}
}
}
void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value)
{
u32 type;
type = offset & B43_NTAB_TYPEMASK;
offset &= 0xFFFF;
switch (type) {
case B43_NTAB_8BIT:
B43_WARN_ON(value & ~0xFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_16BIT:
B43_WARN_ON(value & ~0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_32BIT:
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value & 0xFFFF);
break;
default:
B43_WARN_ON(1);
}
return;
/* Some compiletime assertions... */
assert_ntab_array_sizes();
}
void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
unsigned int nr_elements, const void *_data)
{
u32 type, value;
const u8 *data = _data;
unsigned int i;
type = offset & B43_NTAB_TYPEMASK;
offset &= ~B43_NTAB_TYPEMASK;
B43_WARN_ON(offset > 0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
for (i = 0; i < nr_elements; i++) {
/* Auto increment broken + caching issue on BCM43224? */
if ((offset >> 10) == 9 && dev->dev->chip_id == 43224 &&
dev->dev->chip_rev == 1) {
b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset + i);
}
switch (type) {
case B43_NTAB_8BIT:
value = *data;
data++;
B43_WARN_ON(value & ~0xFF);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_16BIT:
value = *((u16 *)data);
data += 2;
B43_WARN_ON(value & ~0xFFFF);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
break;
case B43_NTAB_32BIT:
value = *((u32 *)data);
data += 4;
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
value & 0xFFFF);
break;
default:
B43_WARN_ON(1);
}
}
}
#define ntab_upload(dev, offset, data) do { \
b43_ntab_write_bulk(dev, offset, offset##_SIZE, data); \
} while (0)
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
{
/* Static tables */
ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
/* Volatile tables */
ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
}
#define ntab_upload_r3(dev, offset, data) do { \
b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
} while (0)
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
{
struct ssb_sprom *sprom = dev->dev->bus_sprom;
/* Static tables */
ntab_upload_r3(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
ntab_upload_r3(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
ntab_upload_r3(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
ntab_upload_r3(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
ntab_upload_r3(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
ntab_upload_r3(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
ntab_upload_r3(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
ntab_upload_r3(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
ntab_upload_r3(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
ntab_upload_r3(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
ntab_upload_r3(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
ntab_upload_r3(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
ntab_upload_r3(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
ntab_upload_r3(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
ntab_upload_r3(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
ntab_upload_r3(dev, B43_NTAB_C0_ESTPLT_R3,
b43_ntab_estimatepowerlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_ESTPLT_R3,
b43_ntab_estimatepowerlt1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
/* Volatile tables */
if (sprom->fem.ghz2.antswlut < ARRAY_SIZE(b43_ntab_antswctl2g_r3))
ntab_upload_r3(dev, B43_NTAB_ANT_SW_CTL_R3,
b43_ntab_antswctl2g_r3[sprom->fem.ghz2.antswlut]);
else
B43_WARN_ON(1);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
{
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
if (dev->phy.rev >= 6) {
if (dev->dev->chip_id == 47162)
return txpwrctrl_tx_gain_ipa_rev5;
return txpwrctrl_tx_gain_ipa_rev6;
} else if (dev->phy.rev >= 5) {
return txpwrctrl_tx_gain_ipa_rev5;
} else {
return txpwrctrl_tx_gain_ipa;
}
} else {
return txpwrctrl_tx_gain_ipa_5g;
}
}
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev)
{
enum ieee80211_band band = b43_current_band(dev->wl);
struct ssb_sprom *sprom = dev->dev->bus_sprom;
if (dev->phy.rev < 3)
return b43_ntab_tx_gain_rev0_1_2;
/* rev 3+ */
if ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
return b43_nphy_get_ipa_gain_table(dev);
} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
if (dev->phy.rev == 3)
return b43_ntab_tx_gain_rev3_5ghz;
if (dev->phy.rev == 4)
return sprom->fem.ghz5.extpa_gain == 3 ?
b43_ntab_tx_gain_rev4_5ghz :
b43_ntab_tx_gain_rev4_5ghz; /* FIXME */
else
return b43_ntab_tx_gain_rev5plus_5ghz;
} else {
if (dev->phy.rev >= 5 && sprom->fem.ghz5.extpa_gain == 3)
return b43_ntab_tx_gain_rev3plus_2ghz; /* FIXME */
else
return b43_ntab_tx_gain_rev3plus_2ghz;
}
}
struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
struct b43_wldev *dev, bool ghz5, bool ext_lna)
{
struct nphy_gain_ctl_workaround_entry *e;
u8 phy_idx;
u8 tr_iso = ghz5 ? dev->dev->bus_sprom->fem.ghz5.tr_iso :
dev->dev->bus_sprom->fem.ghz2.tr_iso;
if (!ghz5 && dev->phy.rev >= 6 && dev->phy.radio_rev == 11)
return &nphy_gain_ctl_wa_phy6_radio11_ghz2;
B43_WARN_ON(dev->phy.rev < 3);
if (dev->phy.rev >= 6)
phy_idx = 3;
else if (dev->phy.rev == 5)
phy_idx = 2;
else if (dev->phy.rev == 4)
phy_idx = 1;
else
phy_idx = 0;
e = &nphy_gain_ctl_workaround[ghz5][phy_idx];
/* Some workarounds to the workarounds... */
if (ghz5 && dev->phy.rev >= 6) {
if (dev->phy.radio_rev == 11 &&
!b43_channel_type_is_40mhz(dev->phy.channel_type))
e->cliplo_gain = 0x2d;
} else if (!ghz5 && dev->phy.rev >= 5) {
if (ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
}
switch (tr_iso) {
case 0:
e->cliplo_gain = 0x0062;
case 1:
e->cliplo_gain = 0x0064;
case 2:
e->cliplo_gain = 0x006a;
case 3:
e->cliplo_gain = 0x106a;
case 4:
e->cliplo_gain = 0x106c;
case 5:
e->cliplo_gain = 0x1074;
case 6:
e->cliplo_gain = 0x107c;
case 7:
e->cliplo_gain = 0x207c;
default:
e->cliplo_gain = 0x106a;
}
} else if (ghz5 && dev->phy.rev == 4 && ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
e->rfseq_init[0] |= 0x1000;
e->rfseq_init[1] |= 0x1000;
e->rfseq_init[2] |= 0x1000;
e->rfseq_init[3] |= 0x1000;
e->init_gain |= 0x1000;
}
return e;
}
| gpl-2.0 |
batlin1977/LG_L90_kernel | fs/isofs/compress.c | 9317 | 10395 | /* -*- linux-c -*- ------------------------------------------------------- *
*
* Copyright 2001 H. Peter Anvin - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
* USA; either version 2 of the License, or (at your option) any later
* version; incorporated herein by reference.
*
* ----------------------------------------------------------------------- */
/*
* linux/fs/isofs/compress.c
*
* Transparent decompression of files on an iso9660 filesystem
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/zlib.h>
#include "isofs.h"
#include "zisofs.h"
/* This should probably be global. */
static char zisofs_sink_page[PAGE_CACHE_SIZE];
/*
* This contains the zlib memory allocation and the mutex for the
* allocation; this avoids failures at block-decompression time.
*/
static void *zisofs_zlib_workspace;
static DEFINE_MUTEX(zisofs_zlib_lock);
/*
* Read data of @inode from @block_start to @block_end and uncompress
* to one zisofs block. Store the data in the @pages array with @pcount
* entries. Start storing at offset @poffset of the first page.
*/
static loff_t zisofs_uncompress_block(struct inode *inode, loff_t block_start,
loff_t block_end, int pcount,
struct page **pages, unsigned poffset,
int *errp)
{
unsigned int zisofs_block_shift = ISOFS_I(inode)->i_format_parm[1];
unsigned int bufsize = ISOFS_BUFFER_SIZE(inode);
unsigned int bufshift = ISOFS_BUFFER_BITS(inode);
unsigned int bufmask = bufsize - 1;
int i, block_size = block_end - block_start;
z_stream stream = { .total_out = 0,
.avail_in = 0,
.avail_out = 0, };
int zerr;
int needblocks = (block_size + (block_start & bufmask) + bufmask)
>> bufshift;
int haveblocks;
blkcnt_t blocknum;
struct buffer_head *bhs[needblocks + 1];
int curbh, curpage;
if (block_size > deflateBound(1UL << zisofs_block_shift)) {
*errp = -EIO;
return 0;
}
/* Empty block? */
if (block_size == 0) {
for ( i = 0 ; i < pcount ; i++ ) {
if (!pages[i])
continue;
memset(page_address(pages[i]), 0, PAGE_CACHE_SIZE);
flush_dcache_page(pages[i]);
SetPageUptodate(pages[i]);
}
return ((loff_t)pcount) << PAGE_CACHE_SHIFT;
}
/* Because zlib is not thread-safe, do all the I/O at the top. */
blocknum = block_start >> bufshift;
memset(bhs, 0, (needblocks + 1) * sizeof(struct buffer_head *));
haveblocks = isofs_get_blocks(inode, blocknum, bhs, needblocks);
ll_rw_block(READ, haveblocks, bhs);
curbh = 0;
curpage = 0;
/*
* First block is special since it may be fractional. We also wait for
* it before grabbing the zlib mutex; odds are that the subsequent
* blocks are going to come in in short order so we don't hold the zlib
* mutex longer than necessary.
*/
if (!bhs[0])
goto b_eio;
wait_on_buffer(bhs[0]);
if (!buffer_uptodate(bhs[0])) {
*errp = -EIO;
goto b_eio;
}
stream.workspace = zisofs_zlib_workspace;
mutex_lock(&zisofs_zlib_lock);
zerr = zlib_inflateInit(&stream);
if (zerr != Z_OK) {
if (zerr == Z_MEM_ERROR)
*errp = -ENOMEM;
else
*errp = -EIO;
printk(KERN_DEBUG "zisofs: zisofs_inflateInit returned %d\n",
zerr);
goto z_eio;
}
while (curpage < pcount && curbh < haveblocks &&
zerr != Z_STREAM_END) {
if (!stream.avail_out) {
if (pages[curpage]) {
stream.next_out = page_address(pages[curpage])
+ poffset;
stream.avail_out = PAGE_CACHE_SIZE - poffset;
poffset = 0;
} else {
stream.next_out = (void *)&zisofs_sink_page;
stream.avail_out = PAGE_CACHE_SIZE;
}
}
if (!stream.avail_in) {
wait_on_buffer(bhs[curbh]);
if (!buffer_uptodate(bhs[curbh])) {
*errp = -EIO;
break;
}
stream.next_in = bhs[curbh]->b_data +
(block_start & bufmask);
stream.avail_in = min_t(unsigned, bufsize -
(block_start & bufmask),
block_size);
block_size -= stream.avail_in;
block_start = 0;
}
while (stream.avail_out && stream.avail_in) {
zerr = zlib_inflate(&stream, Z_SYNC_FLUSH);
if (zerr == Z_BUF_ERROR && stream.avail_in == 0)
break;
if (zerr == Z_STREAM_END)
break;
if (zerr != Z_OK) {
/* EOF, error, or trying to read beyond end of input */
if (zerr == Z_MEM_ERROR)
*errp = -ENOMEM;
else {
printk(KERN_DEBUG
"zisofs: zisofs_inflate returned"
" %d, inode = %lu,"
" page idx = %d, bh idx = %d,"
" avail_in = %d,"
" avail_out = %d\n",
zerr, inode->i_ino, curpage,
curbh, stream.avail_in,
stream.avail_out);
*errp = -EIO;
}
goto inflate_out;
}
}
if (!stream.avail_out) {
/* This page completed */
if (pages[curpage]) {
flush_dcache_page(pages[curpage]);
SetPageUptodate(pages[curpage]);
}
curpage++;
}
if (!stream.avail_in)
curbh++;
}
inflate_out:
zlib_inflateEnd(&stream);
z_eio:
mutex_unlock(&zisofs_zlib_lock);
b_eio:
for (i = 0; i < haveblocks; i++)
brelse(bhs[i]);
return stream.total_out;
}
/*
* Uncompress data so that pages[full_page] is fully uptodate and possibly
* fills in other pages if we have data for them.
*/
static int zisofs_fill_pages(struct inode *inode, int full_page, int pcount,
struct page **pages)
{
loff_t start_off, end_off;
loff_t block_start, block_end;
unsigned int header_size = ISOFS_I(inode)->i_format_parm[0];
unsigned int zisofs_block_shift = ISOFS_I(inode)->i_format_parm[1];
unsigned int blockptr;
loff_t poffset = 0;
blkcnt_t cstart_block, cend_block;
struct buffer_head *bh;
unsigned int blkbits = ISOFS_BUFFER_BITS(inode);
unsigned int blksize = 1 << blkbits;
int err;
loff_t ret;
BUG_ON(!pages[full_page]);
/*
* We want to read at least 'full_page' page. Because we have to
* uncompress the whole compression block anyway, fill the surrounding
* pages with the data we have anyway...
*/
start_off = page_offset(pages[full_page]);
end_off = min_t(loff_t, start_off + PAGE_CACHE_SIZE, inode->i_size);
cstart_block = start_off >> zisofs_block_shift;
cend_block = (end_off + (1 << zisofs_block_shift) - 1)
>> zisofs_block_shift;
WARN_ON(start_off - (full_page << PAGE_CACHE_SHIFT) !=
((cstart_block << zisofs_block_shift) & PAGE_CACHE_MASK));
/* Find the pointer to this specific chunk */
/* Note: we're not using isonum_731() here because the data is known aligned */
/* Note: header_size is in 32-bit words (4 bytes) */
blockptr = (header_size + cstart_block) << 2;
bh = isofs_bread(inode, blockptr >> blkbits);
if (!bh)
return -EIO;
block_start = le32_to_cpu(*(__le32 *)
(bh->b_data + (blockptr & (blksize - 1))));
while (cstart_block < cend_block && pcount > 0) {
/* Load end of the compressed block in the file */
blockptr += 4;
/* Traversed to next block? */
if (!(blockptr & (blksize - 1))) {
brelse(bh);
bh = isofs_bread(inode, blockptr >> blkbits);
if (!bh)
return -EIO;
}
block_end = le32_to_cpu(*(__le32 *)
(bh->b_data + (blockptr & (blksize - 1))));
if (block_start > block_end) {
brelse(bh);
return -EIO;
}
err = 0;
ret = zisofs_uncompress_block(inode, block_start, block_end,
pcount, pages, poffset, &err);
poffset += ret;
pages += poffset >> PAGE_CACHE_SHIFT;
pcount -= poffset >> PAGE_CACHE_SHIFT;
full_page -= poffset >> PAGE_CACHE_SHIFT;
poffset &= ~PAGE_CACHE_MASK;
if (err) {
brelse(bh);
/*
* Did we finish reading the page we really wanted
* to read?
*/
if (full_page < 0)
return 0;
return err;
}
block_start = block_end;
cstart_block++;
}
if (poffset && *pages) {
memset(page_address(*pages) + poffset, 0,
PAGE_CACHE_SIZE - poffset);
flush_dcache_page(*pages);
SetPageUptodate(*pages);
}
return 0;
}
/*
* When decompressing, we typically obtain more than one page
* per reference. We inject the additional pages into the page
* cache as a form of readahead.
*/
static int zisofs_readpage(struct file *file, struct page *page)
{
struct inode *inode = file->f_path.dentry->d_inode;
struct address_space *mapping = inode->i_mapping;
int err;
int i, pcount, full_page;
unsigned int zisofs_block_shift = ISOFS_I(inode)->i_format_parm[1];
unsigned int zisofs_pages_per_cblock =
PAGE_CACHE_SHIFT <= zisofs_block_shift ?
(1 << (zisofs_block_shift - PAGE_CACHE_SHIFT)) : 0;
struct page *pages[max_t(unsigned, zisofs_pages_per_cblock, 1)];
pgoff_t index = page->index, end_index;
end_index = (inode->i_size + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT;
/*
* If this page is wholly outside i_size we just return zero;
* do_generic_file_read() will handle this for us
*/
if (index >= end_index) {
SetPageUptodate(page);
unlock_page(page);
return 0;
}
if (PAGE_CACHE_SHIFT <= zisofs_block_shift) {
/* We have already been given one page, this is the one
we must do. */
full_page = index & (zisofs_pages_per_cblock - 1);
pcount = min_t(int, zisofs_pages_per_cblock,
end_index - (index & ~(zisofs_pages_per_cblock - 1)));
index -= full_page;
} else {
full_page = 0;
pcount = 1;
}
pages[full_page] = page;
for (i = 0; i < pcount; i++, index++) {
if (i != full_page)
pages[i] = grab_cache_page_nowait(mapping, index);
if (pages[i]) {
ClearPageError(pages[i]);
kmap(pages[i]);
}
}
err = zisofs_fill_pages(inode, full_page, pcount, pages);
/* Release any residual pages, do not SetPageUptodate */
for (i = 0; i < pcount; i++) {
if (pages[i]) {
flush_dcache_page(pages[i]);
if (i == full_page && err)
SetPageError(pages[i]);
kunmap(pages[i]);
unlock_page(pages[i]);
if (i != full_page)
page_cache_release(pages[i]);
}
}
/* At this point, err contains 0 or -EIO depending on the "critical" page */
return err;
}
const struct address_space_operations zisofs_aops = {
.readpage = zisofs_readpage,
/* No sync_page operation supported? */
/* No bmap operation supported */
};
int __init zisofs_init(void)
{
zisofs_zlib_workspace = vmalloc(zlib_inflate_workspacesize());
if ( !zisofs_zlib_workspace )
return -ENOMEM;
return 0;
}
void zisofs_cleanup(void)
{
vfree(zisofs_zlib_workspace);
}
| gpl-2.0 |
su-haris/falcon_kernel | drivers/isdn/mISDN/fsm.c | 9573 | 4508 | /*
* finite state machine implementation
*
* Author Karsten Keil <kkeil@novell.com>
*
* Thanks to Jan den Ouden
* Fritz Elfert
* Copyright 2008 by Karsten Keil <kkeil@novell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/string.h>
#include "fsm.h"
#define FSM_TIMER_DEBUG 0
void
mISDN_FsmNew(struct Fsm *fsm,
struct FsmNode *fnlist, int fncount)
{
int i;
fsm->jumpmatrix = kzalloc(sizeof(FSMFNPTR) * fsm->state_count *
fsm->event_count, GFP_KERNEL);
for (i = 0; i < fncount; i++)
if ((fnlist[i].state >= fsm->state_count) ||
(fnlist[i].event >= fsm->event_count)) {
printk(KERN_ERR
"mISDN_FsmNew Error: %d st(%ld/%ld) ev(%ld/%ld)\n",
i, (long)fnlist[i].state, (long)fsm->state_count,
(long)fnlist[i].event, (long)fsm->event_count);
} else
fsm->jumpmatrix[fsm->state_count * fnlist[i].event +
fnlist[i].state] = (FSMFNPTR) fnlist[i].routine;
}
EXPORT_SYMBOL(mISDN_FsmNew);
void
mISDN_FsmFree(struct Fsm *fsm)
{
kfree((void *) fsm->jumpmatrix);
}
EXPORT_SYMBOL(mISDN_FsmFree);
int
mISDN_FsmEvent(struct FsmInst *fi, int event, void *arg)
{
FSMFNPTR r;
if ((fi->state >= fi->fsm->state_count) ||
(event >= fi->fsm->event_count)) {
printk(KERN_ERR
"mISDN_FsmEvent Error st(%ld/%ld) ev(%d/%ld)\n",
(long)fi->state, (long)fi->fsm->state_count, event,
(long)fi->fsm->event_count);
return 1;
}
r = fi->fsm->jumpmatrix[fi->fsm->state_count * event + fi->state];
if (r) {
if (fi->debug)
fi->printdebug(fi, "State %s Event %s",
fi->fsm->strState[fi->state],
fi->fsm->strEvent[event]);
r(fi, event, arg);
return 0;
} else {
if (fi->debug)
fi->printdebug(fi, "State %s Event %s no action",
fi->fsm->strState[fi->state],
fi->fsm->strEvent[event]);
return 1;
}
}
EXPORT_SYMBOL(mISDN_FsmEvent);
void
mISDN_FsmChangeState(struct FsmInst *fi, int newstate)
{
fi->state = newstate;
if (fi->debug)
fi->printdebug(fi, "ChangeState %s",
fi->fsm->strState[newstate]);
}
EXPORT_SYMBOL(mISDN_FsmChangeState);
static void
FsmExpireTimer(struct FsmTimer *ft)
{
#if FSM_TIMER_DEBUG
if (ft->fi->debug)
ft->fi->printdebug(ft->fi, "FsmExpireTimer %lx", (long) ft);
#endif
mISDN_FsmEvent(ft->fi, ft->event, ft->arg);
}
void
mISDN_FsmInitTimer(struct FsmInst *fi, struct FsmTimer *ft)
{
ft->fi = fi;
ft->tl.function = (void *) FsmExpireTimer;
ft->tl.data = (long) ft;
#if FSM_TIMER_DEBUG
if (ft->fi->debug)
ft->fi->printdebug(ft->fi, "mISDN_FsmInitTimer %lx", (long) ft);
#endif
init_timer(&ft->tl);
}
EXPORT_SYMBOL(mISDN_FsmInitTimer);
void
mISDN_FsmDelTimer(struct FsmTimer *ft, int where)
{
#if FSM_TIMER_DEBUG
if (ft->fi->debug)
ft->fi->printdebug(ft->fi, "mISDN_FsmDelTimer %lx %d",
(long) ft, where);
#endif
del_timer(&ft->tl);
}
EXPORT_SYMBOL(mISDN_FsmDelTimer);
int
mISDN_FsmAddTimer(struct FsmTimer *ft,
int millisec, int event, void *arg, int where)
{
#if FSM_TIMER_DEBUG
if (ft->fi->debug)
ft->fi->printdebug(ft->fi, "mISDN_FsmAddTimer %lx %d %d",
(long) ft, millisec, where);
#endif
if (timer_pending(&ft->tl)) {
if (ft->fi->debug) {
printk(KERN_WARNING
"mISDN_FsmAddTimer: timer already active!\n");
ft->fi->printdebug(ft->fi,
"mISDN_FsmAddTimer already active!");
}
return -1;
}
init_timer(&ft->tl);
ft->event = event;
ft->arg = arg;
ft->tl.expires = jiffies + (millisec * HZ) / 1000;
add_timer(&ft->tl);
return 0;
}
EXPORT_SYMBOL(mISDN_FsmAddTimer);
void
mISDN_FsmRestartTimer(struct FsmTimer *ft,
int millisec, int event, void *arg, int where)
{
#if FSM_TIMER_DEBUG
if (ft->fi->debug)
ft->fi->printdebug(ft->fi, "mISDN_FsmRestartTimer %lx %d %d",
(long) ft, millisec, where);
#endif
if (timer_pending(&ft->tl))
del_timer(&ft->tl);
init_timer(&ft->tl);
ft->event = event;
ft->arg = arg;
ft->tl.expires = jiffies + (millisec * HZ) / 1000;
add_timer(&ft->tl);
}
EXPORT_SYMBOL(mISDN_FsmRestartTimer);
| gpl-2.0 |
bauner/kernel_n7000_tw_jb | fs/adfs/dir_f.c | 12389 | 10602 | /*
* linux/fs/adfs/dir_f.c
*
* Copyright (C) 1997-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* E and F format directory handling
*/
#include <linux/buffer_head.h>
#include "adfs.h"
#include "dir_f.h"
static void adfs_f_free(struct adfs_dir *dir);
/*
* Read an (unaligned) value of length 1..4 bytes
*/
static inline unsigned int adfs_readval(unsigned char *p, int len)
{
unsigned int val = 0;
switch (len) {
case 4: val |= p[3] << 24;
case 3: val |= p[2] << 16;
case 2: val |= p[1] << 8;
default: val |= p[0];
}
return val;
}
static inline void adfs_writeval(unsigned char *p, int len, unsigned int val)
{
switch (len) {
case 4: p[3] = val >> 24;
case 3: p[2] = val >> 16;
case 2: p[1] = val >> 8;
default: p[0] = val;
}
}
static inline int adfs_readname(char *buf, char *ptr, int maxlen)
{
char *old_buf = buf;
while ((unsigned char)*ptr >= ' ' && maxlen--) {
if (*ptr == '/')
*buf++ = '.';
else
*buf++ = *ptr;
ptr++;
}
return buf - old_buf;
}
#define ror13(v) ((v >> 13) | (v << 19))
#define dir_u8(idx) \
({ int _buf = idx >> blocksize_bits; \
int _off = idx - (_buf << blocksize_bits);\
*(u8 *)(bh[_buf]->b_data + _off); \
})
#define dir_u32(idx) \
({ int _buf = idx >> blocksize_bits; \
int _off = idx - (_buf << blocksize_bits);\
*(__le32 *)(bh[_buf]->b_data + _off); \
})
#define bufoff(_bh,_idx) \
({ int _buf = _idx >> blocksize_bits; \
int _off = _idx - (_buf << blocksize_bits);\
(u8 *)(_bh[_buf]->b_data + _off); \
})
/*
* There are some algorithms that are nice in
* assembler, but a bitch in C... This is one
* of them.
*/
static u8
adfs_dir_checkbyte(const struct adfs_dir *dir)
{
struct buffer_head * const *bh = dir->bh;
const int blocksize_bits = dir->sb->s_blocksize_bits;
union { __le32 *ptr32; u8 *ptr8; } ptr, end;
u32 dircheck = 0;
int last = 5 - 26;
int i = 0;
/*
* Accumulate each word up to the last whole
* word of the last directory entry. This
* can spread across several buffer heads.
*/
do {
last += 26;
do {
dircheck = le32_to_cpu(dir_u32(i)) ^ ror13(dircheck);
i += sizeof(u32);
} while (i < (last & ~3));
} while (dir_u8(last) != 0);
/*
* Accumulate the last few bytes. These
* bytes will be within the same bh.
*/
if (i != last) {
ptr.ptr8 = bufoff(bh, i);
end.ptr8 = ptr.ptr8 + last - i;
do {
dircheck = *ptr.ptr8++ ^ ror13(dircheck);
} while (ptr.ptr8 < end.ptr8);
}
/*
* The directory tail is in the final bh
* Note that contary to the RISC OS PRMs,
* the first few bytes are NOT included
* in the check. All bytes are in the
* same bh.
*/
ptr.ptr8 = bufoff(bh, 2008);
end.ptr8 = ptr.ptr8 + 36;
do {
__le32 v = *ptr.ptr32++;
dircheck = le32_to_cpu(v) ^ ror13(dircheck);
} while (ptr.ptr32 < end.ptr32);
return (dircheck ^ (dircheck >> 8) ^ (dircheck >> 16) ^ (dircheck >> 24)) & 0xff;
}
/*
* Read and check that a directory is valid
*/
static int
adfs_dir_read(struct super_block *sb, unsigned long object_id,
unsigned int size, struct adfs_dir *dir)
{
const unsigned int blocksize_bits = sb->s_blocksize_bits;
int blk = 0;
/*
* Directories which are not a multiple of 2048 bytes
* are considered bad v2 [3.6]
*/
if (size & 2047)
goto bad_dir;
size >>= blocksize_bits;
dir->nr_buffers = 0;
dir->sb = sb;
for (blk = 0; blk < size; blk++) {
int phys;
phys = __adfs_block_map(sb, object_id, blk);
if (!phys) {
adfs_error(sb, "dir object %lX has a hole at offset %d",
object_id, blk);
goto release_buffers;
}
dir->bh[blk] = sb_bread(sb, phys);
if (!dir->bh[blk])
goto release_buffers;
}
memcpy(&dir->dirhead, bufoff(dir->bh, 0), sizeof(dir->dirhead));
memcpy(&dir->dirtail, bufoff(dir->bh, 2007), sizeof(dir->dirtail));
if (dir->dirhead.startmasseq != dir->dirtail.new.endmasseq ||
memcmp(&dir->dirhead.startname, &dir->dirtail.new.endname, 4))
goto bad_dir;
if (memcmp(&dir->dirhead.startname, "Nick", 4) &&
memcmp(&dir->dirhead.startname, "Hugo", 4))
goto bad_dir;
if (adfs_dir_checkbyte(dir) != dir->dirtail.new.dircheckbyte)
goto bad_dir;
dir->nr_buffers = blk;
return 0;
bad_dir:
adfs_error(sb, "corrupted directory fragment %lX",
object_id);
release_buffers:
for (blk -= 1; blk >= 0; blk -= 1)
brelse(dir->bh[blk]);
dir->sb = NULL;
return -EIO;
}
/*
* convert a disk-based directory entry to a Linux ADFS directory entry
*/
static inline void
adfs_dir2obj(struct adfs_dir *dir, struct object_info *obj,
struct adfs_direntry *de)
{
obj->name_len = adfs_readname(obj->name, de->dirobname, ADFS_F_NAME_LEN);
obj->file_id = adfs_readval(de->dirinddiscadd, 3);
obj->loadaddr = adfs_readval(de->dirload, 4);
obj->execaddr = adfs_readval(de->direxec, 4);
obj->size = adfs_readval(de->dirlen, 4);
obj->attr = de->newdiratts;
obj->filetype = -1;
/*
* object is a file and is filetyped and timestamped?
* RISC OS 12-bit filetype is stored in load_address[19:8]
*/
if ((0 == (obj->attr & ADFS_NDA_DIRECTORY)) &&
(0xfff00000 == (0xfff00000 & obj->loadaddr))) {
obj->filetype = (__u16) ((0x000fff00 & obj->loadaddr) >> 8);
/* optionally append the ,xyz hex filetype suffix */
if (ADFS_SB(dir->sb)->s_ftsuffix)
obj->name_len +=
append_filetype_suffix(
&obj->name[obj->name_len],
obj->filetype);
}
}
/*
* convert a Linux ADFS directory entry to a disk-based directory entry
*/
static inline void
adfs_obj2dir(struct adfs_direntry *de, struct object_info *obj)
{
adfs_writeval(de->dirinddiscadd, 3, obj->file_id);
adfs_writeval(de->dirload, 4, obj->loadaddr);
adfs_writeval(de->direxec, 4, obj->execaddr);
adfs_writeval(de->dirlen, 4, obj->size);
de->newdiratts = obj->attr;
}
/*
* get a directory entry. Note that the caller is responsible
* for holding the relevant locks.
*/
static int
__adfs_dir_get(struct adfs_dir *dir, int pos, struct object_info *obj)
{
struct super_block *sb = dir->sb;
struct adfs_direntry de;
int thissize, buffer, offset;
buffer = pos >> sb->s_blocksize_bits;
if (buffer > dir->nr_buffers)
return -EINVAL;
offset = pos & (sb->s_blocksize - 1);
thissize = sb->s_blocksize - offset;
if (thissize > 26)
thissize = 26;
memcpy(&de, dir->bh[buffer]->b_data + offset, thissize);
if (thissize != 26)
memcpy(((char *)&de) + thissize, dir->bh[buffer + 1]->b_data,
26 - thissize);
if (!de.dirobname[0])
return -ENOENT;
adfs_dir2obj(dir, obj, &de);
return 0;
}
static int
__adfs_dir_put(struct adfs_dir *dir, int pos, struct object_info *obj)
{
struct super_block *sb = dir->sb;
struct adfs_direntry de;
int thissize, buffer, offset;
buffer = pos >> sb->s_blocksize_bits;
if (buffer > dir->nr_buffers)
return -EINVAL;
offset = pos & (sb->s_blocksize - 1);
thissize = sb->s_blocksize - offset;
if (thissize > 26)
thissize = 26;
/*
* Get the entry in total
*/
memcpy(&de, dir->bh[buffer]->b_data + offset, thissize);
if (thissize != 26)
memcpy(((char *)&de) + thissize, dir->bh[buffer + 1]->b_data,
26 - thissize);
/*
* update it
*/
adfs_obj2dir(&de, obj);
/*
* Put the new entry back
*/
memcpy(dir->bh[buffer]->b_data + offset, &de, thissize);
if (thissize != 26)
memcpy(dir->bh[buffer + 1]->b_data, ((char *)&de) + thissize,
26 - thissize);
return 0;
}
/*
* the caller is responsible for holding the necessary
* locks.
*/
static int
adfs_dir_find_entry(struct adfs_dir *dir, unsigned long object_id)
{
int pos, ret;
ret = -ENOENT;
for (pos = 5; pos < ADFS_NUM_DIR_ENTRIES * 26 + 5; pos += 26) {
struct object_info obj;
if (!__adfs_dir_get(dir, pos, &obj))
break;
if (obj.file_id == object_id) {
ret = pos;
break;
}
}
return ret;
}
static int
adfs_f_read(struct super_block *sb, unsigned int id, unsigned int sz, struct adfs_dir *dir)
{
int ret;
if (sz != ADFS_NEWDIR_SIZE)
return -EIO;
ret = adfs_dir_read(sb, id, sz, dir);
if (ret)
adfs_error(sb, "unable to read directory");
else
dir->parent_id = adfs_readval(dir->dirtail.new.dirparent, 3);
return ret;
}
static int
adfs_f_setpos(struct adfs_dir *dir, unsigned int fpos)
{
if (fpos >= ADFS_NUM_DIR_ENTRIES)
return -ENOENT;
dir->pos = 5 + fpos * 26;
return 0;
}
static int
adfs_f_getnext(struct adfs_dir *dir, struct object_info *obj)
{
unsigned int ret;
ret = __adfs_dir_get(dir, dir->pos, obj);
if (ret == 0)
dir->pos += 26;
return ret;
}
static int
adfs_f_update(struct adfs_dir *dir, struct object_info *obj)
{
struct super_block *sb = dir->sb;
int ret, i;
ret = adfs_dir_find_entry(dir, obj->file_id);
if (ret < 0) {
adfs_error(dir->sb, "unable to locate entry to update");
goto out;
}
__adfs_dir_put(dir, ret, obj);
/*
* Increment directory sequence number
*/
dir->bh[0]->b_data[0] += 1;
dir->bh[dir->nr_buffers - 1]->b_data[sb->s_blocksize - 6] += 1;
ret = adfs_dir_checkbyte(dir);
/*
* Update directory check byte
*/
dir->bh[dir->nr_buffers - 1]->b_data[sb->s_blocksize - 1] = ret;
#if 1
{
const unsigned int blocksize_bits = sb->s_blocksize_bits;
memcpy(&dir->dirhead, bufoff(dir->bh, 0), sizeof(dir->dirhead));
memcpy(&dir->dirtail, bufoff(dir->bh, 2007), sizeof(dir->dirtail));
if (dir->dirhead.startmasseq != dir->dirtail.new.endmasseq ||
memcmp(&dir->dirhead.startname, &dir->dirtail.new.endname, 4))
goto bad_dir;
if (memcmp(&dir->dirhead.startname, "Nick", 4) &&
memcmp(&dir->dirhead.startname, "Hugo", 4))
goto bad_dir;
if (adfs_dir_checkbyte(dir) != dir->dirtail.new.dircheckbyte)
goto bad_dir;
}
#endif
for (i = dir->nr_buffers - 1; i >= 0; i--)
mark_buffer_dirty(dir->bh[i]);
ret = 0;
out:
return ret;
#if 1
bad_dir:
adfs_error(dir->sb, "whoops! I broke a directory!");
return -EIO;
#endif
}
static int
adfs_f_sync(struct adfs_dir *dir)
{
int err = 0;
int i;
for (i = dir->nr_buffers - 1; i >= 0; i--) {
struct buffer_head *bh = dir->bh[i];
sync_dirty_buffer(bh);
if (buffer_req(bh) && !buffer_uptodate(bh))
err = -EIO;
}
return err;
}
static void
adfs_f_free(struct adfs_dir *dir)
{
int i;
for (i = dir->nr_buffers - 1; i >= 0; i--) {
brelse(dir->bh[i]);
dir->bh[i] = NULL;
}
dir->nr_buffers = 0;
dir->sb = NULL;
}
struct adfs_dir_ops adfs_f_dir_ops = {
.read = adfs_f_read,
.setpos = adfs_f_setpos,
.getnext = adfs_f_getnext,
.update = adfs_f_update,
.sync = adfs_f_sync,
.free = adfs_f_free
};
| gpl-2.0 |
kgdhost/kernel-lge-e400-stock | net/dcb/dcbnl.c | 102 | 43524 | /*
* Copyright (c) 2008, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Author: Lucy Liu <lucy.liu@intel.com>
*/
#include <linux/netdevice.h>
#include <linux/netlink.h>
#include <linux/slab.h>
#include <net/netlink.h>
#include <net/rtnetlink.h>
#include <linux/dcbnl.h>
#include <net/dcbevent.h>
#include <linux/rtnetlink.h>
#include <net/sock.h>
/**
* Data Center Bridging (DCB) is a collection of Ethernet enhancements
* intended to allow network traffic with differing requirements
* (highly reliable, no drops vs. best effort vs. low latency) to operate
* and co-exist on Ethernet. Current DCB features are:
*
* Enhanced Transmission Selection (aka Priority Grouping [PG]) - provides a
* framework for assigning bandwidth guarantees to traffic classes.
*
* Priority-based Flow Control (PFC) - provides a flow control mechanism which
* can work independently for each 802.1p priority.
*
* Congestion Notification - provides a mechanism for end-to-end congestion
* control for protocols which do not have built-in congestion management.
*
* More information about the emerging standards for these Ethernet features
* can be found at: http://www.ieee802.org/1/pages/dcbridges.html
*
* This file implements an rtnetlink interface to allow configuration of DCB
* features for capable devices.
*/
MODULE_AUTHOR("Lucy Liu, <lucy.liu@intel.com>");
MODULE_DESCRIPTION("Data Center Bridging netlink interface");
MODULE_LICENSE("GPL");
/**************** DCB attribute policies *************************************/
/* DCB netlink attributes policy */
static const struct nla_policy dcbnl_rtnl_policy[DCB_ATTR_MAX + 1] = {
[DCB_ATTR_IFNAME] = {.type = NLA_NUL_STRING, .len = IFNAMSIZ - 1},
[DCB_ATTR_STATE] = {.type = NLA_U8},
[DCB_ATTR_PFC_CFG] = {.type = NLA_NESTED},
[DCB_ATTR_PG_CFG] = {.type = NLA_NESTED},
[DCB_ATTR_SET_ALL] = {.type = NLA_U8},
[DCB_ATTR_PERM_HWADDR] = {.type = NLA_FLAG},
[DCB_ATTR_CAP] = {.type = NLA_NESTED},
[DCB_ATTR_PFC_STATE] = {.type = NLA_U8},
[DCB_ATTR_BCN] = {.type = NLA_NESTED},
[DCB_ATTR_APP] = {.type = NLA_NESTED},
[DCB_ATTR_IEEE] = {.type = NLA_NESTED},
[DCB_ATTR_DCBX] = {.type = NLA_U8},
[DCB_ATTR_FEATCFG] = {.type = NLA_NESTED},
};
/* DCB priority flow control to User Priority nested attributes */
static const struct nla_policy dcbnl_pfc_up_nest[DCB_PFC_UP_ATTR_MAX + 1] = {
[DCB_PFC_UP_ATTR_0] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_1] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_2] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_3] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_4] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_5] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_6] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_7] = {.type = NLA_U8},
[DCB_PFC_UP_ATTR_ALL] = {.type = NLA_FLAG},
};
/* DCB priority grouping nested attributes */
static const struct nla_policy dcbnl_pg_nest[DCB_PG_ATTR_MAX + 1] = {
[DCB_PG_ATTR_TC_0] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_1] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_2] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_3] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_4] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_5] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_6] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_7] = {.type = NLA_NESTED},
[DCB_PG_ATTR_TC_ALL] = {.type = NLA_NESTED},
[DCB_PG_ATTR_BW_ID_0] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_1] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_2] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_3] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_4] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_5] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_6] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_7] = {.type = NLA_U8},
[DCB_PG_ATTR_BW_ID_ALL] = {.type = NLA_FLAG},
};
/* DCB traffic class nested attributes. */
static const struct nla_policy dcbnl_tc_param_nest[DCB_TC_ATTR_PARAM_MAX + 1] = {
[DCB_TC_ATTR_PARAM_PGID] = {.type = NLA_U8},
[DCB_TC_ATTR_PARAM_UP_MAPPING] = {.type = NLA_U8},
[DCB_TC_ATTR_PARAM_STRICT_PRIO] = {.type = NLA_U8},
[DCB_TC_ATTR_PARAM_BW_PCT] = {.type = NLA_U8},
[DCB_TC_ATTR_PARAM_ALL] = {.type = NLA_FLAG},
};
/* DCB capabilities nested attributes. */
static const struct nla_policy dcbnl_cap_nest[DCB_CAP_ATTR_MAX + 1] = {
[DCB_CAP_ATTR_ALL] = {.type = NLA_FLAG},
[DCB_CAP_ATTR_PG] = {.type = NLA_U8},
[DCB_CAP_ATTR_PFC] = {.type = NLA_U8},
[DCB_CAP_ATTR_UP2TC] = {.type = NLA_U8},
[DCB_CAP_ATTR_PG_TCS] = {.type = NLA_U8},
[DCB_CAP_ATTR_PFC_TCS] = {.type = NLA_U8},
[DCB_CAP_ATTR_GSP] = {.type = NLA_U8},
[DCB_CAP_ATTR_BCN] = {.type = NLA_U8},
[DCB_CAP_ATTR_DCBX] = {.type = NLA_U8},
};
/* DCB capabilities nested attributes. */
static const struct nla_policy dcbnl_numtcs_nest[DCB_NUMTCS_ATTR_MAX + 1] = {
[DCB_NUMTCS_ATTR_ALL] = {.type = NLA_FLAG},
[DCB_NUMTCS_ATTR_PG] = {.type = NLA_U8},
[DCB_NUMTCS_ATTR_PFC] = {.type = NLA_U8},
};
/* DCB BCN nested attributes. */
static const struct nla_policy dcbnl_bcn_nest[DCB_BCN_ATTR_MAX + 1] = {
[DCB_BCN_ATTR_RP_0] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_1] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_2] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_3] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_4] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_5] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_6] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_7] = {.type = NLA_U8},
[DCB_BCN_ATTR_RP_ALL] = {.type = NLA_FLAG},
[DCB_BCN_ATTR_BCNA_0] = {.type = NLA_U32},
[DCB_BCN_ATTR_BCNA_1] = {.type = NLA_U32},
[DCB_BCN_ATTR_ALPHA] = {.type = NLA_U32},
[DCB_BCN_ATTR_BETA] = {.type = NLA_U32},
[DCB_BCN_ATTR_GD] = {.type = NLA_U32},
[DCB_BCN_ATTR_GI] = {.type = NLA_U32},
[DCB_BCN_ATTR_TMAX] = {.type = NLA_U32},
[DCB_BCN_ATTR_TD] = {.type = NLA_U32},
[DCB_BCN_ATTR_RMIN] = {.type = NLA_U32},
[DCB_BCN_ATTR_W] = {.type = NLA_U32},
[DCB_BCN_ATTR_RD] = {.type = NLA_U32},
[DCB_BCN_ATTR_RU] = {.type = NLA_U32},
[DCB_BCN_ATTR_WRTT] = {.type = NLA_U32},
[DCB_BCN_ATTR_RI] = {.type = NLA_U32},
[DCB_BCN_ATTR_C] = {.type = NLA_U32},
[DCB_BCN_ATTR_ALL] = {.type = NLA_FLAG},
};
/* DCB APP nested attributes. */
static const struct nla_policy dcbnl_app_nest[DCB_APP_ATTR_MAX + 1] = {
[DCB_APP_ATTR_IDTYPE] = {.type = NLA_U8},
[DCB_APP_ATTR_ID] = {.type = NLA_U16},
[DCB_APP_ATTR_PRIORITY] = {.type = NLA_U8},
};
/* IEEE 802.1Qaz nested attributes. */
static const struct nla_policy dcbnl_ieee_policy[DCB_ATTR_IEEE_MAX + 1] = {
[DCB_ATTR_IEEE_ETS] = {.len = sizeof(struct ieee_ets)},
[DCB_ATTR_IEEE_PFC] = {.len = sizeof(struct ieee_pfc)},
[DCB_ATTR_IEEE_APP_TABLE] = {.type = NLA_NESTED},
};
static const struct nla_policy dcbnl_ieee_app[DCB_ATTR_IEEE_APP_MAX + 1] = {
[DCB_ATTR_IEEE_APP] = {.len = sizeof(struct dcb_app)},
};
/* DCB number of traffic classes nested attributes. */
static const struct nla_policy dcbnl_featcfg_nest[DCB_FEATCFG_ATTR_MAX + 1] = {
[DCB_FEATCFG_ATTR_ALL] = {.type = NLA_FLAG},
[DCB_FEATCFG_ATTR_PG] = {.type = NLA_U8},
[DCB_FEATCFG_ATTR_PFC] = {.type = NLA_U8},
[DCB_FEATCFG_ATTR_APP] = {.type = NLA_U8},
};
static LIST_HEAD(dcb_app_list);
static DEFINE_SPINLOCK(dcb_lock);
/* standard netlink reply call */
static int dcbnl_reply(u8 value, u8 event, u8 cmd, u8 attr, u32 pid,
u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct dcbmsg *dcb;
struct nlmsghdr *nlh;
int ret = -EINVAL;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
return ret;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, event, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = cmd;
dcb->dcb_pad = 0;
ret = nla_put_u8(dcbnl_skb, attr, value);
if (ret)
goto err;
/* end the message, assign the nlmsg_len. */
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
return -EINVAL;
return 0;
nlmsg_failure:
err:
kfree_skb(dcbnl_skb);
return ret;
}
static int dcbnl_getstate(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret = -EINVAL;
/* if (!tb[DCB_ATTR_STATE] || !netdev->dcbnl_ops->getstate) */
if (!netdev->dcbnl_ops->getstate)
return ret;
ret = dcbnl_reply(netdev->dcbnl_ops->getstate(netdev), RTM_GETDCB,
DCB_CMD_GSTATE, DCB_ATTR_STATE, pid, seq, flags);
return ret;
}
static int dcbnl_getpfccfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *data[DCB_PFC_UP_ATTR_MAX + 1], *nest;
u8 value;
int ret = -EINVAL;
int i;
int getall = 0;
if (!tb[DCB_ATTR_PFC_CFG] || !netdev->dcbnl_ops->getpfccfg)
return ret;
ret = nla_parse_nested(data, DCB_PFC_UP_ATTR_MAX,
tb[DCB_ATTR_PFC_CFG],
dcbnl_pfc_up_nest);
if (ret)
goto err_out;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
goto err_out;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_PFC_GCFG;
nest = nla_nest_start(dcbnl_skb, DCB_ATTR_PFC_CFG);
if (!nest)
goto err;
if (data[DCB_PFC_UP_ATTR_ALL])
getall = 1;
for (i = DCB_PFC_UP_ATTR_0; i <= DCB_PFC_UP_ATTR_7; i++) {
if (!getall && !data[i])
continue;
netdev->dcbnl_ops->getpfccfg(netdev, i - DCB_PFC_UP_ATTR_0,
&value);
ret = nla_put_u8(dcbnl_skb, i, value);
if (ret) {
nla_nest_cancel(dcbnl_skb, nest);
goto err;
}
}
nla_nest_end(dcbnl_skb, nest);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
goto err_out;
return 0;
nlmsg_failure:
err:
kfree_skb(dcbnl_skb);
err_out:
return -EINVAL;
}
static int dcbnl_getperm_hwaddr(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
u8 perm_addr[MAX_ADDR_LEN];
int ret = -EINVAL;
if (!netdev->dcbnl_ops->getpermhwaddr)
return ret;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
goto err_out;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_GPERM_HWADDR;
netdev->dcbnl_ops->getpermhwaddr(netdev, perm_addr);
ret = nla_put(dcbnl_skb, DCB_ATTR_PERM_HWADDR, sizeof(perm_addr),
perm_addr);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
goto err_out;
return 0;
nlmsg_failure:
kfree_skb(dcbnl_skb);
err_out:
return -EINVAL;
}
static int dcbnl_getcap(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *data[DCB_CAP_ATTR_MAX + 1], *nest;
u8 value;
int ret = -EINVAL;
int i;
int getall = 0;
if (!tb[DCB_ATTR_CAP] || !netdev->dcbnl_ops->getcap)
return ret;
ret = nla_parse_nested(data, DCB_CAP_ATTR_MAX, tb[DCB_ATTR_CAP],
dcbnl_cap_nest);
if (ret)
goto err_out;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
goto err_out;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_GCAP;
nest = nla_nest_start(dcbnl_skb, DCB_ATTR_CAP);
if (!nest)
goto err;
if (data[DCB_CAP_ATTR_ALL])
getall = 1;
for (i = DCB_CAP_ATTR_ALL+1; i <= DCB_CAP_ATTR_MAX; i++) {
if (!getall && !data[i])
continue;
if (!netdev->dcbnl_ops->getcap(netdev, i, &value)) {
ret = nla_put_u8(dcbnl_skb, i, value);
if (ret) {
nla_nest_cancel(dcbnl_skb, nest);
goto err;
}
}
}
nla_nest_end(dcbnl_skb, nest);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
goto err_out;
return 0;
nlmsg_failure:
err:
kfree_skb(dcbnl_skb);
err_out:
return -EINVAL;
}
static int dcbnl_getnumtcs(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *data[DCB_NUMTCS_ATTR_MAX + 1], *nest;
u8 value;
int ret = -EINVAL;
int i;
int getall = 0;
if (!tb[DCB_ATTR_NUMTCS] || !netdev->dcbnl_ops->getnumtcs)
return ret;
ret = nla_parse_nested(data, DCB_NUMTCS_ATTR_MAX, tb[DCB_ATTR_NUMTCS],
dcbnl_numtcs_nest);
if (ret) {
ret = -EINVAL;
goto err_out;
}
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb) {
ret = -EINVAL;
goto err_out;
}
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_GNUMTCS;
nest = nla_nest_start(dcbnl_skb, DCB_ATTR_NUMTCS);
if (!nest) {
ret = -EINVAL;
goto err;
}
if (data[DCB_NUMTCS_ATTR_ALL])
getall = 1;
for (i = DCB_NUMTCS_ATTR_ALL+1; i <= DCB_NUMTCS_ATTR_MAX; i++) {
if (!getall && !data[i])
continue;
ret = netdev->dcbnl_ops->getnumtcs(netdev, i, &value);
if (!ret) {
ret = nla_put_u8(dcbnl_skb, i, value);
if (ret) {
nla_nest_cancel(dcbnl_skb, nest);
ret = -EINVAL;
goto err;
}
} else {
goto err;
}
}
nla_nest_end(dcbnl_skb, nest);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret) {
ret = -EINVAL;
goto err_out;
}
return 0;
nlmsg_failure:
err:
kfree_skb(dcbnl_skb);
err_out:
return ret;
}
static int dcbnl_setnumtcs(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct nlattr *data[DCB_NUMTCS_ATTR_MAX + 1];
int ret = -EINVAL;
u8 value;
int i;
if (!tb[DCB_ATTR_NUMTCS] || !netdev->dcbnl_ops->setnumtcs)
return ret;
ret = nla_parse_nested(data, DCB_NUMTCS_ATTR_MAX, tb[DCB_ATTR_NUMTCS],
dcbnl_numtcs_nest);
if (ret) {
ret = -EINVAL;
goto err;
}
for (i = DCB_NUMTCS_ATTR_ALL+1; i <= DCB_NUMTCS_ATTR_MAX; i++) {
if (data[i] == NULL)
continue;
value = nla_get_u8(data[i]);
ret = netdev->dcbnl_ops->setnumtcs(netdev, i, value);
if (ret)
goto operr;
}
operr:
ret = dcbnl_reply(!!ret, RTM_SETDCB, DCB_CMD_SNUMTCS,
DCB_ATTR_NUMTCS, pid, seq, flags);
err:
return ret;
}
static int dcbnl_getpfcstate(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret = -EINVAL;
if (!netdev->dcbnl_ops->getpfcstate)
return ret;
ret = dcbnl_reply(netdev->dcbnl_ops->getpfcstate(netdev), RTM_GETDCB,
DCB_CMD_PFC_GSTATE, DCB_ATTR_PFC_STATE,
pid, seq, flags);
return ret;
}
static int dcbnl_setpfcstate(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret = -EINVAL;
u8 value;
if (!tb[DCB_ATTR_PFC_STATE] || !netdev->dcbnl_ops->setpfcstate)
return ret;
value = nla_get_u8(tb[DCB_ATTR_PFC_STATE]);
netdev->dcbnl_ops->setpfcstate(netdev, value);
ret = dcbnl_reply(0, RTM_SETDCB, DCB_CMD_PFC_SSTATE, DCB_ATTR_PFC_STATE,
pid, seq, flags);
return ret;
}
static int dcbnl_getapp(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *app_nest;
struct nlattr *app_tb[DCB_APP_ATTR_MAX + 1];
u16 id;
u8 up, idtype;
int ret = -EINVAL;
if (!tb[DCB_ATTR_APP])
goto out;
ret = nla_parse_nested(app_tb, DCB_APP_ATTR_MAX, tb[DCB_ATTR_APP],
dcbnl_app_nest);
if (ret)
goto out;
ret = -EINVAL;
/* all must be non-null */
if ((!app_tb[DCB_APP_ATTR_IDTYPE]) ||
(!app_tb[DCB_APP_ATTR_ID]))
goto out;
/* either by eth type or by socket number */
idtype = nla_get_u8(app_tb[DCB_APP_ATTR_IDTYPE]);
if ((idtype != DCB_APP_IDTYPE_ETHTYPE) &&
(idtype != DCB_APP_IDTYPE_PORTNUM))
goto out;
id = nla_get_u16(app_tb[DCB_APP_ATTR_ID]);
if (netdev->dcbnl_ops->getapp) {
up = netdev->dcbnl_ops->getapp(netdev, idtype, id);
} else {
struct dcb_app app = {
.selector = idtype,
.protocol = id,
};
up = dcb_getapp(netdev, &app);
}
/* send this back */
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
goto out;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_GAPP;
app_nest = nla_nest_start(dcbnl_skb, DCB_ATTR_APP);
if (!app_nest)
goto out_cancel;
ret = nla_put_u8(dcbnl_skb, DCB_APP_ATTR_IDTYPE, idtype);
if (ret)
goto out_cancel;
ret = nla_put_u16(dcbnl_skb, DCB_APP_ATTR_ID, id);
if (ret)
goto out_cancel;
ret = nla_put_u8(dcbnl_skb, DCB_APP_ATTR_PRIORITY, up);
if (ret)
goto out_cancel;
nla_nest_end(dcbnl_skb, app_nest);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
goto nlmsg_failure;
goto out;
out_cancel:
nla_nest_cancel(dcbnl_skb, app_nest);
nlmsg_failure:
kfree_skb(dcbnl_skb);
out:
return ret;
}
static int dcbnl_setapp(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int err, ret = -EINVAL;
u16 id;
u8 up, idtype;
struct nlattr *app_tb[DCB_APP_ATTR_MAX + 1];
if (!tb[DCB_ATTR_APP])
goto out;
ret = nla_parse_nested(app_tb, DCB_APP_ATTR_MAX, tb[DCB_ATTR_APP],
dcbnl_app_nest);
if (ret)
goto out;
ret = -EINVAL;
/* all must be non-null */
if ((!app_tb[DCB_APP_ATTR_IDTYPE]) ||
(!app_tb[DCB_APP_ATTR_ID]) ||
(!app_tb[DCB_APP_ATTR_PRIORITY]))
goto out;
/* either by eth type or by socket number */
idtype = nla_get_u8(app_tb[DCB_APP_ATTR_IDTYPE]);
if ((idtype != DCB_APP_IDTYPE_ETHTYPE) &&
(idtype != DCB_APP_IDTYPE_PORTNUM))
goto out;
id = nla_get_u16(app_tb[DCB_APP_ATTR_ID]);
up = nla_get_u8(app_tb[DCB_APP_ATTR_PRIORITY]);
if (netdev->dcbnl_ops->setapp) {
err = netdev->dcbnl_ops->setapp(netdev, idtype, id, up);
} else {
struct dcb_app app;
app.selector = idtype;
app.protocol = id;
app.priority = up;
err = dcb_setapp(netdev, &app);
}
ret = dcbnl_reply(err, RTM_SETDCB, DCB_CMD_SAPP, DCB_ATTR_APP,
pid, seq, flags);
out:
return ret;
}
static int __dcbnl_pg_getcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags, int dir)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *pg_nest, *param_nest, *data;
struct nlattr *pg_tb[DCB_PG_ATTR_MAX + 1];
struct nlattr *param_tb[DCB_TC_ATTR_PARAM_MAX + 1];
u8 prio, pgid, tc_pct, up_map;
int ret = -EINVAL;
int getall = 0;
int i;
if (!tb[DCB_ATTR_PG_CFG] ||
!netdev->dcbnl_ops->getpgtccfgtx ||
!netdev->dcbnl_ops->getpgtccfgrx ||
!netdev->dcbnl_ops->getpgbwgcfgtx ||
!netdev->dcbnl_ops->getpgbwgcfgrx)
return ret;
ret = nla_parse_nested(pg_tb, DCB_PG_ATTR_MAX,
tb[DCB_ATTR_PG_CFG], dcbnl_pg_nest);
if (ret)
goto err_out;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
goto err_out;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = (dir) ? DCB_CMD_PGRX_GCFG : DCB_CMD_PGTX_GCFG;
pg_nest = nla_nest_start(dcbnl_skb, DCB_ATTR_PG_CFG);
if (!pg_nest)
goto err;
if (pg_tb[DCB_PG_ATTR_TC_ALL])
getall = 1;
for (i = DCB_PG_ATTR_TC_0; i <= DCB_PG_ATTR_TC_7; i++) {
if (!getall && !pg_tb[i])
continue;
if (pg_tb[DCB_PG_ATTR_TC_ALL])
data = pg_tb[DCB_PG_ATTR_TC_ALL];
else
data = pg_tb[i];
ret = nla_parse_nested(param_tb, DCB_TC_ATTR_PARAM_MAX,
data, dcbnl_tc_param_nest);
if (ret)
goto err_pg;
param_nest = nla_nest_start(dcbnl_skb, i);
if (!param_nest)
goto err_pg;
pgid = DCB_ATTR_VALUE_UNDEFINED;
prio = DCB_ATTR_VALUE_UNDEFINED;
tc_pct = DCB_ATTR_VALUE_UNDEFINED;
up_map = DCB_ATTR_VALUE_UNDEFINED;
if (dir) {
/* Rx */
netdev->dcbnl_ops->getpgtccfgrx(netdev,
i - DCB_PG_ATTR_TC_0, &prio,
&pgid, &tc_pct, &up_map);
} else {
/* Tx */
netdev->dcbnl_ops->getpgtccfgtx(netdev,
i - DCB_PG_ATTR_TC_0, &prio,
&pgid, &tc_pct, &up_map);
}
if (param_tb[DCB_TC_ATTR_PARAM_PGID] ||
param_tb[DCB_TC_ATTR_PARAM_ALL]) {
ret = nla_put_u8(dcbnl_skb,
DCB_TC_ATTR_PARAM_PGID, pgid);
if (ret)
goto err_param;
}
if (param_tb[DCB_TC_ATTR_PARAM_UP_MAPPING] ||
param_tb[DCB_TC_ATTR_PARAM_ALL]) {
ret = nla_put_u8(dcbnl_skb,
DCB_TC_ATTR_PARAM_UP_MAPPING, up_map);
if (ret)
goto err_param;
}
if (param_tb[DCB_TC_ATTR_PARAM_STRICT_PRIO] ||
param_tb[DCB_TC_ATTR_PARAM_ALL]) {
ret = nla_put_u8(dcbnl_skb,
DCB_TC_ATTR_PARAM_STRICT_PRIO, prio);
if (ret)
goto err_param;
}
if (param_tb[DCB_TC_ATTR_PARAM_BW_PCT] ||
param_tb[DCB_TC_ATTR_PARAM_ALL]) {
ret = nla_put_u8(dcbnl_skb, DCB_TC_ATTR_PARAM_BW_PCT,
tc_pct);
if (ret)
goto err_param;
}
nla_nest_end(dcbnl_skb, param_nest);
}
if (pg_tb[DCB_PG_ATTR_BW_ID_ALL])
getall = 1;
else
getall = 0;
for (i = DCB_PG_ATTR_BW_ID_0; i <= DCB_PG_ATTR_BW_ID_7; i++) {
if (!getall && !pg_tb[i])
continue;
tc_pct = DCB_ATTR_VALUE_UNDEFINED;
if (dir) {
/* Rx */
netdev->dcbnl_ops->getpgbwgcfgrx(netdev,
i - DCB_PG_ATTR_BW_ID_0, &tc_pct);
} else {
/* Tx */
netdev->dcbnl_ops->getpgbwgcfgtx(netdev,
i - DCB_PG_ATTR_BW_ID_0, &tc_pct);
}
ret = nla_put_u8(dcbnl_skb, i, tc_pct);
if (ret)
goto err_pg;
}
nla_nest_end(dcbnl_skb, pg_nest);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
goto err_out;
return 0;
err_param:
nla_nest_cancel(dcbnl_skb, param_nest);
err_pg:
nla_nest_cancel(dcbnl_skb, pg_nest);
nlmsg_failure:
err:
kfree_skb(dcbnl_skb);
err_out:
ret = -EINVAL;
return ret;
}
static int dcbnl_pgtx_getcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
return __dcbnl_pg_getcfg(netdev, tb, pid, seq, flags, 0);
}
static int dcbnl_pgrx_getcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
return __dcbnl_pg_getcfg(netdev, tb, pid, seq, flags, 1);
}
static int dcbnl_setstate(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret = -EINVAL;
u8 value;
if (!tb[DCB_ATTR_STATE] || !netdev->dcbnl_ops->setstate)
return ret;
value = nla_get_u8(tb[DCB_ATTR_STATE]);
ret = dcbnl_reply(netdev->dcbnl_ops->setstate(netdev, value),
RTM_SETDCB, DCB_CMD_SSTATE, DCB_ATTR_STATE,
pid, seq, flags);
return ret;
}
static int dcbnl_setpfccfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct nlattr *data[DCB_PFC_UP_ATTR_MAX + 1];
int i;
int ret = -EINVAL;
u8 value;
if (!tb[DCB_ATTR_PFC_CFG] || !netdev->dcbnl_ops->setpfccfg)
return ret;
ret = nla_parse_nested(data, DCB_PFC_UP_ATTR_MAX,
tb[DCB_ATTR_PFC_CFG],
dcbnl_pfc_up_nest);
if (ret)
goto err;
for (i = DCB_PFC_UP_ATTR_0; i <= DCB_PFC_UP_ATTR_7; i++) {
if (data[i] == NULL)
continue;
value = nla_get_u8(data[i]);
netdev->dcbnl_ops->setpfccfg(netdev,
data[i]->nla_type - DCB_PFC_UP_ATTR_0, value);
}
ret = dcbnl_reply(0, RTM_SETDCB, DCB_CMD_PFC_SCFG, DCB_ATTR_PFC_CFG,
pid, seq, flags);
err:
return ret;
}
static int dcbnl_setall(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret = -EINVAL;
if (!tb[DCB_ATTR_SET_ALL] || !netdev->dcbnl_ops->setall)
return ret;
ret = dcbnl_reply(netdev->dcbnl_ops->setall(netdev), RTM_SETDCB,
DCB_CMD_SET_ALL, DCB_ATTR_SET_ALL, pid, seq, flags);
return ret;
}
static int __dcbnl_pg_setcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags, int dir)
{
struct nlattr *pg_tb[DCB_PG_ATTR_MAX + 1];
struct nlattr *param_tb[DCB_TC_ATTR_PARAM_MAX + 1];
int ret = -EINVAL;
int i;
u8 pgid;
u8 up_map;
u8 prio;
u8 tc_pct;
if (!tb[DCB_ATTR_PG_CFG] ||
!netdev->dcbnl_ops->setpgtccfgtx ||
!netdev->dcbnl_ops->setpgtccfgrx ||
!netdev->dcbnl_ops->setpgbwgcfgtx ||
!netdev->dcbnl_ops->setpgbwgcfgrx)
return ret;
ret = nla_parse_nested(pg_tb, DCB_PG_ATTR_MAX,
tb[DCB_ATTR_PG_CFG], dcbnl_pg_nest);
if (ret)
goto err;
for (i = DCB_PG_ATTR_TC_0; i <= DCB_PG_ATTR_TC_7; i++) {
if (!pg_tb[i])
continue;
ret = nla_parse_nested(param_tb, DCB_TC_ATTR_PARAM_MAX,
pg_tb[i], dcbnl_tc_param_nest);
if (ret)
goto err;
pgid = DCB_ATTR_VALUE_UNDEFINED;
prio = DCB_ATTR_VALUE_UNDEFINED;
tc_pct = DCB_ATTR_VALUE_UNDEFINED;
up_map = DCB_ATTR_VALUE_UNDEFINED;
if (param_tb[DCB_TC_ATTR_PARAM_STRICT_PRIO])
prio =
nla_get_u8(param_tb[DCB_TC_ATTR_PARAM_STRICT_PRIO]);
if (param_tb[DCB_TC_ATTR_PARAM_PGID])
pgid = nla_get_u8(param_tb[DCB_TC_ATTR_PARAM_PGID]);
if (param_tb[DCB_TC_ATTR_PARAM_BW_PCT])
tc_pct = nla_get_u8(param_tb[DCB_TC_ATTR_PARAM_BW_PCT]);
if (param_tb[DCB_TC_ATTR_PARAM_UP_MAPPING])
up_map =
nla_get_u8(param_tb[DCB_TC_ATTR_PARAM_UP_MAPPING]);
/* dir: Tx = 0, Rx = 1 */
if (dir) {
/* Rx */
netdev->dcbnl_ops->setpgtccfgrx(netdev,
i - DCB_PG_ATTR_TC_0,
prio, pgid, tc_pct, up_map);
} else {
/* Tx */
netdev->dcbnl_ops->setpgtccfgtx(netdev,
i - DCB_PG_ATTR_TC_0,
prio, pgid, tc_pct, up_map);
}
}
for (i = DCB_PG_ATTR_BW_ID_0; i <= DCB_PG_ATTR_BW_ID_7; i++) {
if (!pg_tb[i])
continue;
tc_pct = nla_get_u8(pg_tb[i]);
/* dir: Tx = 0, Rx = 1 */
if (dir) {
/* Rx */
netdev->dcbnl_ops->setpgbwgcfgrx(netdev,
i - DCB_PG_ATTR_BW_ID_0, tc_pct);
} else {
/* Tx */
netdev->dcbnl_ops->setpgbwgcfgtx(netdev,
i - DCB_PG_ATTR_BW_ID_0, tc_pct);
}
}
ret = dcbnl_reply(0, RTM_SETDCB,
(dir ? DCB_CMD_PGRX_SCFG : DCB_CMD_PGTX_SCFG),
DCB_ATTR_PG_CFG, pid, seq, flags);
err:
return ret;
}
static int dcbnl_pgtx_setcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
return __dcbnl_pg_setcfg(netdev, tb, pid, seq, flags, 0);
}
static int dcbnl_pgrx_setcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
return __dcbnl_pg_setcfg(netdev, tb, pid, seq, flags, 1);
}
static int dcbnl_bcn_getcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *bcn_nest;
struct nlattr *bcn_tb[DCB_BCN_ATTR_MAX + 1];
u8 value_byte;
u32 value_integer;
int ret = -EINVAL;
bool getall = false;
int i;
if (!tb[DCB_ATTR_BCN] || !netdev->dcbnl_ops->getbcnrp ||
!netdev->dcbnl_ops->getbcncfg)
return ret;
ret = nla_parse_nested(bcn_tb, DCB_BCN_ATTR_MAX,
tb[DCB_ATTR_BCN], dcbnl_bcn_nest);
if (ret)
goto err_out;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb)
goto err_out;
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_BCN_GCFG;
bcn_nest = nla_nest_start(dcbnl_skb, DCB_ATTR_BCN);
if (!bcn_nest)
goto err;
if (bcn_tb[DCB_BCN_ATTR_ALL])
getall = true;
for (i = DCB_BCN_ATTR_RP_0; i <= DCB_BCN_ATTR_RP_7; i++) {
if (!getall && !bcn_tb[i])
continue;
netdev->dcbnl_ops->getbcnrp(netdev, i - DCB_BCN_ATTR_RP_0,
&value_byte);
ret = nla_put_u8(dcbnl_skb, i, value_byte);
if (ret)
goto err_bcn;
}
for (i = DCB_BCN_ATTR_BCNA_0; i <= DCB_BCN_ATTR_RI; i++) {
if (!getall && !bcn_tb[i])
continue;
netdev->dcbnl_ops->getbcncfg(netdev, i,
&value_integer);
ret = nla_put_u32(dcbnl_skb, i, value_integer);
if (ret)
goto err_bcn;
}
nla_nest_end(dcbnl_skb, bcn_nest);
nlmsg_end(dcbnl_skb, nlh);
ret = rtnl_unicast(dcbnl_skb, &init_net, pid);
if (ret)
goto err_out;
return 0;
err_bcn:
nla_nest_cancel(dcbnl_skb, bcn_nest);
nlmsg_failure:
err:
kfree_skb(dcbnl_skb);
err_out:
ret = -EINVAL;
return ret;
}
static int dcbnl_bcn_setcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct nlattr *data[DCB_BCN_ATTR_MAX + 1];
int i;
int ret = -EINVAL;
u8 value_byte;
u32 value_int;
if (!tb[DCB_ATTR_BCN] || !netdev->dcbnl_ops->setbcncfg ||
!netdev->dcbnl_ops->setbcnrp)
return ret;
ret = nla_parse_nested(data, DCB_BCN_ATTR_MAX,
tb[DCB_ATTR_BCN],
dcbnl_pfc_up_nest);
if (ret)
goto err;
for (i = DCB_BCN_ATTR_RP_0; i <= DCB_BCN_ATTR_RP_7; i++) {
if (data[i] == NULL)
continue;
value_byte = nla_get_u8(data[i]);
netdev->dcbnl_ops->setbcnrp(netdev,
data[i]->nla_type - DCB_BCN_ATTR_RP_0, value_byte);
}
for (i = DCB_BCN_ATTR_BCNA_0; i <= DCB_BCN_ATTR_RI; i++) {
if (data[i] == NULL)
continue;
value_int = nla_get_u32(data[i]);
netdev->dcbnl_ops->setbcncfg(netdev,
i, value_int);
}
ret = dcbnl_reply(0, RTM_SETDCB, DCB_CMD_BCN_SCFG, DCB_ATTR_BCN,
pid, seq, flags);
err:
return ret;
}
/* Handle IEEE 802.1Qaz SET commands. If any requested operation can not
* be completed the entire msg is aborted and error value is returned.
* No attempt is made to reconcile the case where only part of the
* cmd can be completed.
*/
static int dcbnl_ieee_set(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
const struct dcbnl_rtnl_ops *ops = netdev->dcbnl_ops;
struct nlattr *ieee[DCB_ATTR_IEEE_MAX + 1];
int err = -EOPNOTSUPP;
if (!ops)
goto err;
err = nla_parse_nested(ieee, DCB_ATTR_IEEE_MAX,
tb[DCB_ATTR_IEEE], dcbnl_ieee_policy);
if (err)
goto err;
if (ieee[DCB_ATTR_IEEE_ETS] && ops->ieee_setets) {
struct ieee_ets *ets = nla_data(ieee[DCB_ATTR_IEEE_ETS]);
err = ops->ieee_setets(netdev, ets);
if (err)
goto err;
}
if (ieee[DCB_ATTR_IEEE_PFC] && ops->ieee_setpfc) {
struct ieee_pfc *pfc = nla_data(ieee[DCB_ATTR_IEEE_PFC]);
err = ops->ieee_setpfc(netdev, pfc);
if (err)
goto err;
}
if (ieee[DCB_ATTR_IEEE_APP_TABLE]) {
struct nlattr *attr;
int rem;
nla_for_each_nested(attr, ieee[DCB_ATTR_IEEE_APP_TABLE], rem) {
struct dcb_app *app_data;
if (nla_type(attr) != DCB_ATTR_IEEE_APP)
continue;
app_data = nla_data(attr);
if (ops->ieee_setapp)
err = ops->ieee_setapp(netdev, app_data);
else
err = dcb_setapp(netdev, app_data);
if (err)
goto err;
}
}
err:
dcbnl_reply(err, RTM_SETDCB, DCB_CMD_IEEE_SET, DCB_ATTR_IEEE,
pid, seq, flags);
return err;
}
/* Handle IEEE 802.1Qaz GET commands. */
static int dcbnl_ieee_get(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *ieee, *app;
struct dcb_app_type *itr;
const struct dcbnl_rtnl_ops *ops = netdev->dcbnl_ops;
int err;
if (!ops)
return -EOPNOTSUPP;
skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!skb)
return -ENOBUFS;
nlh = NLMSG_NEW(skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_IEEE_GET;
NLA_PUT_STRING(skb, DCB_ATTR_IFNAME, netdev->name);
ieee = nla_nest_start(skb, DCB_ATTR_IEEE);
if (!ieee)
goto nla_put_failure;
if (ops->ieee_getets) {
struct ieee_ets ets;
err = ops->ieee_getets(netdev, &ets);
if (!err)
NLA_PUT(skb, DCB_ATTR_IEEE_ETS, sizeof(ets), &ets);
}
if (ops->ieee_getpfc) {
struct ieee_pfc pfc;
err = ops->ieee_getpfc(netdev, &pfc);
if (!err)
NLA_PUT(skb, DCB_ATTR_IEEE_PFC, sizeof(pfc), &pfc);
}
app = nla_nest_start(skb, DCB_ATTR_IEEE_APP_TABLE);
if (!app)
goto nla_put_failure;
spin_lock(&dcb_lock);
list_for_each_entry(itr, &dcb_app_list, list) {
if (strncmp(itr->name, netdev->name, IFNAMSIZ) == 0) {
err = nla_put(skb, DCB_ATTR_IEEE_APP, sizeof(itr->app),
&itr->app);
if (err) {
spin_unlock(&dcb_lock);
goto nla_put_failure;
}
}
}
spin_unlock(&dcb_lock);
nla_nest_end(skb, app);
nla_nest_end(skb, ieee);
nlmsg_end(skb, nlh);
return rtnl_unicast(skb, &init_net, pid);
nla_put_failure:
nlmsg_cancel(skb, nlh);
nlmsg_failure:
kfree_skb(skb);
return -1;
}
/* DCBX configuration */
static int dcbnl_getdcbx(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret;
if (!netdev->dcbnl_ops->getdcbx)
return -EOPNOTSUPP;
ret = dcbnl_reply(netdev->dcbnl_ops->getdcbx(netdev), RTM_GETDCB,
DCB_CMD_GDCBX, DCB_ATTR_DCBX, pid, seq, flags);
return ret;
}
static int dcbnl_setdcbx(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
int ret;
u8 value;
if (!netdev->dcbnl_ops->setdcbx)
return -EOPNOTSUPP;
if (!tb[DCB_ATTR_DCBX])
return -EINVAL;
value = nla_get_u8(tb[DCB_ATTR_DCBX]);
ret = dcbnl_reply(netdev->dcbnl_ops->setdcbx(netdev, value),
RTM_SETDCB, DCB_CMD_SDCBX, DCB_ATTR_DCBX,
pid, seq, flags);
return ret;
}
static int dcbnl_getfeatcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct sk_buff *dcbnl_skb;
struct nlmsghdr *nlh;
struct dcbmsg *dcb;
struct nlattr *data[DCB_FEATCFG_ATTR_MAX + 1], *nest;
u8 value;
int ret, i;
int getall = 0;
if (!netdev->dcbnl_ops->getfeatcfg)
return -EOPNOTSUPP;
if (!tb[DCB_ATTR_FEATCFG])
return -EINVAL;
ret = nla_parse_nested(data, DCB_FEATCFG_ATTR_MAX, tb[DCB_ATTR_FEATCFG],
dcbnl_featcfg_nest);
if (ret)
goto err_out;
dcbnl_skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
if (!dcbnl_skb) {
ret = -ENOBUFS;
goto err_out;
}
nlh = NLMSG_NEW(dcbnl_skb, pid, seq, RTM_GETDCB, sizeof(*dcb), flags);
dcb = NLMSG_DATA(nlh);
dcb->dcb_family = AF_UNSPEC;
dcb->cmd = DCB_CMD_GFEATCFG;
nest = nla_nest_start(dcbnl_skb, DCB_ATTR_FEATCFG);
if (!nest) {
ret = -EMSGSIZE;
goto nla_put_failure;
}
if (data[DCB_FEATCFG_ATTR_ALL])
getall = 1;
for (i = DCB_FEATCFG_ATTR_ALL+1; i <= DCB_FEATCFG_ATTR_MAX; i++) {
if (!getall && !data[i])
continue;
ret = netdev->dcbnl_ops->getfeatcfg(netdev, i, &value);
if (!ret)
ret = nla_put_u8(dcbnl_skb, i, value);
if (ret) {
nla_nest_cancel(dcbnl_skb, nest);
goto nla_put_failure;
}
}
nla_nest_end(dcbnl_skb, nest);
nlmsg_end(dcbnl_skb, nlh);
return rtnl_unicast(dcbnl_skb, &init_net, pid);
nla_put_failure:
nlmsg_cancel(dcbnl_skb, nlh);
nlmsg_failure:
kfree_skb(dcbnl_skb);
err_out:
return ret;
}
static int dcbnl_setfeatcfg(struct net_device *netdev, struct nlattr **tb,
u32 pid, u32 seq, u16 flags)
{
struct nlattr *data[DCB_FEATCFG_ATTR_MAX + 1];
int ret, i;
u8 value;
if (!netdev->dcbnl_ops->setfeatcfg)
return -ENOTSUPP;
if (!tb[DCB_ATTR_FEATCFG])
return -EINVAL;
ret = nla_parse_nested(data, DCB_FEATCFG_ATTR_MAX, tb[DCB_ATTR_FEATCFG],
dcbnl_featcfg_nest);
if (ret)
goto err;
for (i = DCB_FEATCFG_ATTR_ALL+1; i <= DCB_FEATCFG_ATTR_MAX; i++) {
if (data[i] == NULL)
continue;
value = nla_get_u8(data[i]);
ret = netdev->dcbnl_ops->setfeatcfg(netdev, i, value);
if (ret)
goto err;
}
err:
dcbnl_reply(ret, RTM_SETDCB, DCB_CMD_SFEATCFG, DCB_ATTR_FEATCFG,
pid, seq, flags);
return ret;
}
static int dcb_doit(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg)
{
struct net *net = sock_net(skb->sk);
struct net_device *netdev;
struct dcbmsg *dcb = (struct dcbmsg *)NLMSG_DATA(nlh);
struct nlattr *tb[DCB_ATTR_MAX + 1];
u32 pid = skb ? NETLINK_CB(skb).pid : 0;
int ret = -EINVAL;
if (!net_eq(net, &init_net))
return -EINVAL;
ret = nlmsg_parse(nlh, sizeof(*dcb), tb, DCB_ATTR_MAX,
dcbnl_rtnl_policy);
if (ret < 0)
return ret;
if (!tb[DCB_ATTR_IFNAME])
return -EINVAL;
netdev = dev_get_by_name(&init_net, nla_data(tb[DCB_ATTR_IFNAME]));
if (!netdev)
return -EINVAL;
if (!netdev->dcbnl_ops)
goto errout;
switch (dcb->cmd) {
case DCB_CMD_GSTATE:
ret = dcbnl_getstate(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PFC_GCFG:
ret = dcbnl_getpfccfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_GPERM_HWADDR:
ret = dcbnl_getperm_hwaddr(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PGTX_GCFG:
ret = dcbnl_pgtx_getcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PGRX_GCFG:
ret = dcbnl_pgrx_getcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_BCN_GCFG:
ret = dcbnl_bcn_getcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_SSTATE:
ret = dcbnl_setstate(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PFC_SCFG:
ret = dcbnl_setpfccfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_SET_ALL:
ret = dcbnl_setall(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PGTX_SCFG:
ret = dcbnl_pgtx_setcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PGRX_SCFG:
ret = dcbnl_pgrx_setcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_GCAP:
ret = dcbnl_getcap(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_GNUMTCS:
ret = dcbnl_getnumtcs(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_SNUMTCS:
ret = dcbnl_setnumtcs(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PFC_GSTATE:
ret = dcbnl_getpfcstate(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_PFC_SSTATE:
ret = dcbnl_setpfcstate(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_BCN_SCFG:
ret = dcbnl_bcn_setcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_GAPP:
ret = dcbnl_getapp(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_SAPP:
ret = dcbnl_setapp(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_IEEE_SET:
ret = dcbnl_ieee_set(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_IEEE_GET:
ret = dcbnl_ieee_get(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_GDCBX:
ret = dcbnl_getdcbx(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_SDCBX:
ret = dcbnl_setdcbx(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_GFEATCFG:
ret = dcbnl_getfeatcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
case DCB_CMD_SFEATCFG:
ret = dcbnl_setfeatcfg(netdev, tb, pid, nlh->nlmsg_seq,
nlh->nlmsg_flags);
goto out;
default:
goto errout;
}
errout:
ret = -EINVAL;
out:
dev_put(netdev);
return ret;
}
/**
* dcb_getapp - retrieve the DCBX application user priority
*
* On success returns a non-zero 802.1p user priority bitmap
* otherwise returns 0 as the invalid user priority bitmap to
* indicate an error.
*/
u8 dcb_getapp(struct net_device *dev, struct dcb_app *app)
{
struct dcb_app_type *itr;
u8 prio = 0;
spin_lock(&dcb_lock);
list_for_each_entry(itr, &dcb_app_list, list) {
if (itr->app.selector == app->selector &&
itr->app.protocol == app->protocol &&
(strncmp(itr->name, dev->name, IFNAMSIZ) == 0)) {
prio = itr->app.priority;
break;
}
}
spin_unlock(&dcb_lock);
return prio;
}
EXPORT_SYMBOL(dcb_getapp);
/**
* ixgbe_dcbnl_setapp - add dcb application data to app list
*
* Priority 0 is the default priority this removes applications
* from the app list if the priority is set to zero.
*/
u8 dcb_setapp(struct net_device *dev, struct dcb_app *new)
{
struct dcb_app_type *itr;
struct dcb_app_type event;
memcpy(&event.name, dev->name, sizeof(event.name));
memcpy(&event.app, new, sizeof(event.app));
spin_lock(&dcb_lock);
/* Search for existing match and replace */
list_for_each_entry(itr, &dcb_app_list, list) {
if (itr->app.selector == new->selector &&
itr->app.protocol == new->protocol &&
(strncmp(itr->name, dev->name, IFNAMSIZ) == 0)) {
if (new->priority)
itr->app.priority = new->priority;
else {
list_del(&itr->list);
kfree(itr);
}
goto out;
}
}
/* App type does not exist add new application type */
if (new->priority) {
struct dcb_app_type *entry;
entry = kmalloc(sizeof(struct dcb_app_type), GFP_ATOMIC);
if (!entry) {
spin_unlock(&dcb_lock);
return -ENOMEM;
}
memcpy(&entry->app, new, sizeof(*new));
strncpy(entry->name, dev->name, IFNAMSIZ);
list_add(&entry->list, &dcb_app_list);
}
out:
spin_unlock(&dcb_lock);
call_dcbevent_notifiers(DCB_APP_EVENT, &event);
return 0;
}
EXPORT_SYMBOL(dcb_setapp);
static void dcb_flushapp(void)
{
struct dcb_app_type *app;
struct dcb_app_type *tmp;
spin_lock(&dcb_lock);
list_for_each_entry_safe(app, tmp, &dcb_app_list, list) {
list_del(&app->list);
kfree(app);
}
spin_unlock(&dcb_lock);
}
static int __init dcbnl_init(void)
{
INIT_LIST_HEAD(&dcb_app_list);
rtnl_register(PF_UNSPEC, RTM_GETDCB, dcb_doit, NULL);
rtnl_register(PF_UNSPEC, RTM_SETDCB, dcb_doit, NULL);
return 0;
}
module_init(dcbnl_init);
static void __exit dcbnl_exit(void)
{
rtnl_unregister(PF_UNSPEC, RTM_GETDCB);
rtnl_unregister(PF_UNSPEC, RTM_SETDCB);
dcb_flushapp();
}
module_exit(dcbnl_exit);
| gpl-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/software/BSPv05/HAL/src/alt_close.c | 102 | 4021 | /******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <unistd.h>
#include "sys/alt_errno.h"
#include "sys/alt_warning.h"
#include "priv/alt_file.h"
#include "os/alt_syscall.h"
#ifdef ALT_USE_DIRECT_DRIVERS
int ALT_CLOSE (int fildes)
{
/* Generate a link time warning, should this function ever be called. */
ALT_STUB_WARNING(close);
/* Indicate an error */
ALT_ERRNO = ENOSYS;
return -1;
}
#else /* !ALT_USE_DIRECT_DRIVERS */
/*
* close() is called by an application to release a file descriptor. If the
* associated file system/device has a close() callback function registered
* then this called. The file descriptor is then marked as free.
*
* ALT_CLOSE is mapped onto the close() system call in alt_syscall.h
*/
int ALT_CLOSE (int fildes)
{
alt_fd* fd;
int rval;
/*
* A common error case is that when the file descriptor was created, the call
* to open() failed resulting in a negative file descriptor. This is trapped
* below so that we don't try and process an invalid file descriptor.
*/
fd = (fildes < 0) ? NULL : &alt_fd_list[fildes];
if (fd)
{
/*
* If the associated file system/device has a close function, call it so
* that any necessary cleanup code can run.
*/
rval = (fd->dev->close) ? fd->dev->close(fd) : 0;
/* Free the file descriptor structure and return. */
alt_release_fd (fildes);
if (rval < 0)
{
ALT_ERRNO = -rval;
return -1;
}
return 0;
}
else
{
ALT_ERRNO = EBADFD;
return -1;
}
}
#endif /* ALT_USE_DIRECT_DRIVERS */
| gpl-2.0 |
noobies/f240l-kernel | drivers/staging/prima/CORE/HDD/src/wlan_hdd_main.c | 358 | 146421 | /*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*========================================================================
\file wlan_hdd_main.c
\brief WLAN Host Device Driver implementation
Copyright 2008 (c) Qualcomm, Incorporated. All Rights Reserved.
Qualcomm Confidential and Proprietary.
========================================================================*/
/**=========================================================================
EDIT HISTORY FOR FILE
This section contains comments describing changes made to the module.
Notice that changes are listed in reverse chronological order.
$Header:$ $DateTime: $ $Author: $
when who what, where, why
-------- --- --------------------------------------------------------
04/5/09 Shailender Created module.
02/24/10 Sudhir.S.Kohalli Added to support param for SoftAP module
06/03/10 js - Added support to hostapd driven deauth/disassoc/mic failure
==========================================================================*/
/*--------------------------------------------------------------------------
Include Files
------------------------------------------------------------------------*/
//#include <wlan_qct_driver.h>
#include <wlan_hdd_includes.h>
#ifdef ANI_BUS_TYPE_SDIO
#include <wlan_sal_misc.h>
#endif // ANI_BUS_TYPE_SDIO
#include <vos_api.h>
#include <vos_sched.h>
#include <vos_power.h>
#include <linux/etherdevice.h>
#include <linux/firmware.h>
#ifdef ANI_BUS_TYPE_SDIO
#include <linux/mmc/sdio_func.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
// added in 2.6.32, need to define locally if using an earlier kernel
#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev)
#endif
#endif // ANI_BUS_TYPE_SDIO
#ifdef ANI_BUS_TYPE_PLATFORM
#include <linux/wcnss_wlan.h>
#endif //ANI_BUS_TYPE_PLATFORM
#ifdef ANI_BUS_TYPE_PCI
#include "wcnss_wlan.h"
#endif /* ANI_BUS_TYPE_PCI */
#include <wlan_hdd_tx_rx.h>
#include <palTimer.h>
#include <wniApi.h>
#include <wlan_nlink_srv.h>
#include <wlan_btc_svc.h>
#include <wlan_hdd_cfg.h>
#include <wlan_ptt_sock_svc.h>
#include <wlan_hdd_wowl.h>
#include <wlan_hdd_misc.h>
#include <wlan_hdd_wext.h>
#ifdef WLAN_BTAMP_FEATURE
#include <bap_hdd_main.h>
#include <bapInternal.h>
#endif // WLAN_BTAMP_FEATURE
#ifdef CONFIG_CFG80211
#include <linux/wireless.h>
#include <net/cfg80211.h>
#include "wlan_hdd_cfg80211.h"
#include "wlan_hdd_p2p.h"
#endif
#include <linux/rtnetlink.h>
#ifdef ANI_MANF_DIAG
int wlan_hdd_ftm_start(hdd_context_t *pAdapter);
#endif
#ifdef WLAN_SOFTAP_FEATURE
#include "sapApi.h"
#include <linux/semaphore.h>
#include <mach/subsystem_restart.h>
#include <wlan_hdd_hostapd.h>
#include <wlan_hdd_softap_tx_rx.h>
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
#include "cfgApi.h"
#endif
#include "wlan_hdd_dev_pwr.h"
#ifdef WLAN_BTAMP_FEATURE
#include "bap_hdd_misc.h"
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
#include "wlan_qct_pal_trace.h"
#endif /* FEATURE_WLAN_INTEGRATED_SOC */
#include "qwlan_version.h"
#ifdef MODULE
#define WLAN_MODULE_NAME module_name(THIS_MODULE)
#else
#define WLAN_MODULE_NAME "wlan"
#endif
#ifdef TIMER_MANAGER
#define TIMER_MANAGER_STR " +TIMER_MANAGER"
#else
#define TIMER_MANAGER_STR ""
#endif
#ifdef MEMORY_DEBUG
#define MEMORY_DEBUG_STR " +MEMORY_DEBUG"
#else
#define MEMORY_DEBUG_STR ""
#endif
/* the Android framework expects this param even though we don't use it */
#define BUF_LEN 20
static char fwpath[BUF_LEN];
#ifndef MODULE
static int wlan_hdd_inited = 0;
#endif
/*
* The rate at which the driver sends RESTART event to supplicant
* once the function 'vos_wlanRestart()' is called
*
*/
#define WLAN_HDD_RESTART_RETRY_DELAY_MS 5000 /* 5 second */
#define WLAN_HDD_RESTART_RETRY_MAX_CNT 5 /* 5 retries */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,5))
static struct wake_lock wlan_wake_lock;
#endif
/* set when SSR is needed after unload */
static v_U8_t isSsrRequired;
//internal function declaration
static VOS_STATUS wlan_hdd_framework_restart(hdd_context_t *pHddCtx);
static void wlan_hdd_restart_init(hdd_context_t *pHddCtx);
static void wlan_hdd_restart_deinit(hdd_context_t *pHddCtx);
void wlan_hdd_restart_timer_cb(v_PVOID_t usrDataForCallback);
v_U16_t hdd_select_queue(struct net_device *dev,
struct sk_buff *skb);
#ifdef WLAN_FEATURE_PACKET_FILTERING
static void hdd_set_multicast_list(struct net_device *dev);
#endif
void hdd_wlan_initial_scan(hdd_adapter_t *pAdapter);
extern int hdd_setBand_helper(struct net_device *dev, tANI_U8* ptr);
static int hdd_netdev_notifier_call(struct notifier_block * nb,
unsigned long state,
void *ndev)
{
struct net_device *dev = ndev;
hdd_adapter_t *pAdapter = NULL;
#ifdef WLAN_BTAMP_FEATURE
VOS_STATUS status;
hdd_context_t *pHddCtx;
#endif
//Make sure that this callback corresponds to our device.
if((strncmp( dev->name, "wlan", 4 )) &&
(strncmp( dev->name, "p2p", 3))
)
return NOTIFY_DONE;
#ifdef CONFIG_CFG80211
if (!dev->ieee80211_ptr)
return NOTIFY_DONE;
#endif
pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
if(NULL == pAdapter)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: HDD Adaptor Null Pointer", __func__);
VOS_ASSERT(0);
return NOTIFY_DONE;
}
hddLog(VOS_TRACE_LEVEL_INFO,"%s: New Net Device State = %lu", __func__, state);
switch (state) {
case NETDEV_REGISTER:
break;
case NETDEV_UNREGISTER:
break;
case NETDEV_UP:
break;
case NETDEV_DOWN:
break;
case NETDEV_CHANGE:
if(TRUE == pAdapter->isLinkUpSvcNeeded)
complete(&pAdapter->linkup_event_var);
break;
case NETDEV_GOING_DOWN:
if( pAdapter->scan_info.mScanPending != FALSE )
{
int result;
INIT_COMPLETION(pAdapter->abortscan_event_var);
hdd_abort_mac_scan(pAdapter->pHddCtx);
result = wait_for_completion_interruptible_timeout(
&pAdapter->abortscan_event_var,
msecs_to_jiffies(WLAN_WAIT_TIME_ABORTSCAN));
if(!result)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_ERROR,
"%s: Timeout occured while waiting for abortscan" ,
__FUNCTION__);
}
}
else
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO,
"%s: Scan is not Pending from user" , __FUNCTION__);
}
#ifdef WLAN_BTAMP_FEATURE
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO,"%s: disabling AMP", __FUNCTION__);
pHddCtx = WLAN_HDD_GET_CTX( pAdapter );
status = WLANBAP_StopAmp();
if(VOS_STATUS_SUCCESS != status )
{
pHddCtx->isAmpAllowed = VOS_TRUE;
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: Failed to stop AMP", __func__);
}
else
{
//a state m/c implementation in PAL is TBD to avoid this delay
msleep(500);
if ( pHddCtx->isAmpAllowed )
{
WLANBAP_DeregisterFromHCI();
pHddCtx->isAmpAllowed = VOS_FALSE;
}
}
#endif //WLAN_BTAMP_FEATURE
break;
default:
break;
}
return NOTIFY_DONE;
}
struct notifier_block hdd_netdev_notifier = {
.notifier_call = hdd_netdev_notifier_call,
};
/*---------------------------------------------------------------------------
* Function definitions
*-------------------------------------------------------------------------*/
extern int isWDresetInProgress(void);
#ifdef CONFIG_HAS_EARLYSUSPEND
extern void register_wlan_suspend(void);
extern void unregister_wlan_suspend(void);
void hdd_unregister_mcast_bcast_filter(hdd_context_t *pHddCtx);
void hdd_register_mcast_bcast_filter(hdd_context_t *pHddCtx);
#endif
//variable to hold the insmod parameters
static int con_mode = 0;
#ifndef MODULE
/* current con_mode - used only for statically linked driver
* con_mode is changed by userspace to indicate a mode change which will
* result in calling the module exit and init functions. The module
* exit function will clean up based on the value of con_mode prior to it
* being changed by userspace. So curr_con_mode records the current con_mode
* for exit when con_mode becomes the next mode for init
*/
static int curr_con_mode = 0;
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
/**---------------------------------------------------------------------------
\brief hdd_wdi_trace_enable() - Configure initial WDI Trace enable
Called immediately after the cfg.ini is read in order to configure
the desired trace levels in the WDI.
\param - moduleId - module whose trace level is being configured
\param - bitmask - bitmask of log levels to be enabled
\return - void
--------------------------------------------------------------------------*/
static void hdd_wdi_trace_enable(wpt_moduleid moduleId, v_U32_t bitmask)
{
wpt_tracelevel level;
/* if the bitmask is the default value, then a bitmask was not
specified in cfg.ini, so leave the logging level alone (it
will remain at the "compiled in" default value) */
if (CFG_WDI_TRACE_ENABLE_DEFAULT == bitmask)
{
return;
}
/* a mask was specified. start by disabling all logging */
wpalTraceSetLevel(moduleId, eWLAN_PAL_TRACE_LEVEL_NONE, 0);
/* now cycle through the bitmask until all "set" bits are serviced */
level = eWLAN_PAL_TRACE_LEVEL_FATAL;
while (0 != bitmask)
{
if (bitmask & 1)
{
wpalTraceSetLevel(moduleId, level, 1);
}
level++;
bitmask >>= 1;
}
}
#endif /* FEATURE_WLAN_INTEGRATED_SOC */
int hdd_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
hdd_priv_data_t priv_data;
tANI_U8 *command = NULL;
int ret = 0;
if (NULL == pAdapter)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: HDD adapter context is Null", __FUNCTION__);
ret = -ENODEV;
goto exit;
}
if ((!ifr) || (!ifr->ifr_data))
{
ret = -EINVAL;
goto exit;
}
if (copy_from_user(&priv_data, ifr->ifr_data, sizeof(hdd_priv_data_t)))
{
ret = -EFAULT;
goto exit;
}
command = kmalloc(priv_data.total_len, GFP_KERNEL);
if (!command)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: failed to allocate memory\n", __FUNCTION__);
ret = -ENOMEM;
goto exit;
}
if (copy_from_user(command, priv_data.buf, priv_data.total_len))
{
ret = -EFAULT;
goto exit;
}
if ((SIOCDEVPRIVATE + 1) == cmd)
{
hdd_context_t *pHddCtx = (hdd_context_t*)pAdapter->pHddCtx;
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO,
"%s: Received %s cmd from Wi-Fi GUI***", __func__, command);
if (strncmp(command, "P2P_DEV_ADDR", 12) == 0 )
{
if (copy_to_user(priv_data.buf, pHddCtx->p2pDeviceAddress.bytes,
sizeof(tSirMacAddr)))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: failed to copy data to user buffer\n", __FUNCTION__);
ret = -EFAULT;
}
}
else if(strncmp(priv_data.buf, "SETBAND", 7) == 0)
{
tANI_U8 *ptr = (tANI_U8*)priv_data.buf ;
int ret = 0 ;
/* Change band request received */
/* First 8 bytes will have "SETBAND " and
* 9 byte will have band setting value */
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO,
"%s: SetBandCommand Info comm %s UL %d, TL %d", __FUNCTION__, priv_data.buf, priv_data.used_len, priv_data.total_len);
/* Change band request received */
ret = hdd_setBand_helper(dev, ptr);
}
else if ( strncasecmp(command, "COUNTRY", 7) == 0 )
{
char *country_code;
country_code = command + 8;
ret = (int)sme_ChangeCountryCode(pHddCtx->hHal, NULL, country_code,
pAdapter, pHddCtx->pvosContext);
if( 0 != ret )
{
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_FATAL,
"%s: SME Change Country code fail ret=%d\n",__func__, ret);
}
}
else {
hddLog( VOS_TRACE_LEVEL_WARN, "%s: Unsupported GUI command %s",
__func__, command);
}
}
exit:
if (command)
{
kfree(command);
}
return ret;
}
/**---------------------------------------------------------------------------
\brief hdd_open() - HDD Open function
This is called in response to ifconfig up
\param - dev Pointer to net_device structure
\return - 0 for success non-zero for failure
--------------------------------------------------------------------------*/
int hdd_open (struct net_device *dev)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
hdd_context_t *pHddCtx;
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
VOS_STATUS status;
v_BOOL_t in_standby = TRUE;
if (NULL == pAdapter)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: HDD adapter context is Null", __FUNCTION__);
return -ENODEV;
}
pHddCtx = (hdd_context_t*)pAdapter->pHddCtx;
if (NULL == pHddCtx)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: HDD context is Null", __FUNCTION__);
return -ENODEV;
}
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( (NULL != pAdapterNode) && (VOS_STATUS_SUCCESS == status) )
{
if( pAdapterNode->pAdapter->event_flags & DEVICE_IFACE_OPENED)
{
hddLog(VOS_TRACE_LEVEL_INFO, "%s: chip already out of "
"standby", __func__, pAdapter->device_mode);
in_standby = FALSE;
break;
}
else
{
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
}
if (TRUE == in_standby)
{
if (VOS_STATUS_SUCCESS != wlan_hdd_exit_lowpower(pHddCtx, pAdapter))
{
hddLog(VOS_TRACE_LEVEL_ERROR, "%s: Failed to bring "
"wlan out of power save", __func__);
return -EINVAL;
}
}
pAdapter->event_flags |= DEVICE_IFACE_OPENED;
if (hdd_connIsConnected(WLAN_HDD_GET_STATION_CTX_PTR(pAdapter)))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO,
"%s: Enabling Tx Queues", __FUNCTION__);
/* Enable TX queues only when we are connected */
netif_tx_start_all_queues(dev);
}
return 0;
}
int hdd_mon_open (struct net_device *dev)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
if(pAdapter == NULL) {
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: HDD adapter context is Null", __FUNCTION__);
return -1;
}
netif_start_queue(dev);
return 0;
}
/**---------------------------------------------------------------------------
\brief hdd_stop() - HDD stop function
This is called in response to ifconfig down
\param - dev Pointer to net_device structure
\return - 0 for success non-zero for failure
--------------------------------------------------------------------------*/
int hdd_stop (struct net_device *dev)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
hdd_context_t *pHddCtx;
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
VOS_STATUS status;
v_BOOL_t enter_standby = TRUE;
ENTER();
if (NULL == pAdapter)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: HDD adapter context is Null", __FUNCTION__);
return -ENODEV;
}
pHddCtx = (hdd_context_t*)pAdapter->pHddCtx;
if (NULL == pHddCtx)
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: HDD context is Null", __FUNCTION__);
return -ENODEV;
}
pAdapter->event_flags &= ~(DEVICE_IFACE_OPENED);
hddLog(VOS_TRACE_LEVEL_INFO, "%s: Disabling OS Tx queues", __func__);
netif_tx_disable(pAdapter->dev);
netif_carrier_off(pAdapter->dev);
/* SoftAP ifaces should never go in power save mode
making sure same here. */
if ( (WLAN_HDD_SOFTAP == pAdapter->device_mode )
|| (WLAN_HDD_MONITOR == pAdapter->device_mode )
#ifdef WLAN_FEATURE_P2P
|| (WLAN_HDD_P2P_GO == pAdapter->device_mode )
#endif
)
{
/* SoftAP mode, so return from here */
EXIT();
return 0;
}
/* Find if any iface is up then
if any iface is up then can't put device to sleep/ power save mode. */
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( (NULL != pAdapterNode) && (VOS_STATUS_SUCCESS == status) )
{
if ( pAdapterNode->pAdapter->event_flags & DEVICE_IFACE_OPENED)
{
hddLog(VOS_TRACE_LEVEL_INFO, "%s: Still other ifaces are up cannot "
"put device to sleep", __func__, pAdapter->device_mode);
enter_standby = FALSE;
break;
}
else
{
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
}
if (TRUE == enter_standby)
{
hddLog(VOS_TRACE_LEVEL_INFO, "%s: All Interfaces are Down "
"entering standby", __func__);
if (VOS_STATUS_SUCCESS != wlan_hdd_enter_lowpower(pHddCtx))
{
/*log and return success*/
hddLog(VOS_TRACE_LEVEL_ERROR, "%s: Failed to put "
"wlan in power save", __func__);
}
}
EXIT();
return 0;
}
/**---------------------------------------------------------------------------
\brief hdd_uninit() - HDD uninit function
This is called during the netdev unregister to uninitialize all data
associated with the device
\param - dev Pointer to net_device structure
\return - void
--------------------------------------------------------------------------*/
static void hdd_uninit (struct net_device *dev)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
ENTER();
do
{
if (NULL == pAdapter)
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: NULL pAdapter", __func__);
break;
}
if (WLAN_HDD_ADAPTER_MAGIC != pAdapter->magic)
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: Invalid magic", __func__);
break;
}
if (NULL == pAdapter->pHddCtx)
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: NULL pHddCtx", __func__);
break;
}
if (dev != pAdapter->dev)
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: Invalid device reference", __func__);
/* we haven't validated all cases so let this go for now */
}
hdd_deinit_adapter(pAdapter->pHddCtx, pAdapter);
/* after uninit our adapter structure will no longer be valid */
pAdapter->dev = NULL;
pAdapter->magic = 0;
} while (0);
EXIT();
}
/**---------------------------------------------------------------------------
\brief hdd_release_firmware() -
This function calls the release firmware API to free the firmware buffer.
\param - pFileName Pointer to the File Name.
pCtx - Pointer to the adapter .
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
VOS_STATUS hdd_release_firmware(char *pFileName,v_VOID_t *pCtx)
{
VOS_STATUS status = VOS_STATUS_SUCCESS;
hdd_context_t *pHddCtx = (hdd_context_t*)pCtx;
ENTER();
if (!strcmp(WLAN_FW_FILE, pFileName)) {
hddLog(VOS_TRACE_LEVEL_INFO_HIGH,"%s: Loaded firmware file is %s",__func__,pFileName);
if(pHddCtx->fw) {
release_firmware(pHddCtx->fw);
pHddCtx->fw = NULL;
}
else
status = VOS_STATUS_E_FAILURE;
}
else if (!strcmp(WLAN_NV_FILE,pFileName)) {
if(pHddCtx->nv) {
release_firmware(pHddCtx->nv);
pHddCtx->nv = NULL;
}
else
status = VOS_STATUS_E_FAILURE;
}
EXIT();
return status;
}
/**---------------------------------------------------------------------------
\brief hdd_request_firmware() -
This function reads the firmware file using the request firmware
API and returns the the firmware data and the firmware file size.
\param - pfileName - Pointer to the file name.
- pCtx - Pointer to the adapter .
- ppfw_data - Pointer to the pointer of the firmware data.
- pSize - Pointer to the file size.
\return - VOS_STATUS_SUCCESS for success, VOS_STATUS_E_FAILURE for failure
--------------------------------------------------------------------------*/
VOS_STATUS hdd_request_firmware(char *pfileName,v_VOID_t *pCtx,v_VOID_t **ppfw_data, v_SIZE_t *pSize)
{
int status;
VOS_STATUS retval = VOS_STATUS_SUCCESS;
hdd_context_t *pHddCtx = (hdd_context_t*)pCtx;
ENTER();
if( (!strcmp(WLAN_FW_FILE, pfileName)) ) {
status = request_firmware(&pHddCtx->fw, pfileName, pHddCtx->parent_dev);
if(status || !pHddCtx->fw || !pHddCtx->fw->data) {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Firmware %s download failed",
__func__, pfileName);
retval = VOS_STATUS_E_FAILURE;
}
else {
*ppfw_data = (v_VOID_t *)pHddCtx->fw->data;
*pSize = pHddCtx->fw->size;
hddLog(VOS_TRACE_LEVEL_INFO, "%s: Firmware size = %d",
__func__, *pSize);
}
}
else if(!strcmp(WLAN_NV_FILE, pfileName)) {
status = request_firmware(&pHddCtx->nv, pfileName, pHddCtx->parent_dev);
if(status || !pHddCtx->nv || !pHddCtx->nv->data) {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: nv %s download failed",
__func__, pfileName);
retval = VOS_STATUS_E_FAILURE;
}
else {
*ppfw_data = (v_VOID_t *)pHddCtx->nv->data;
*pSize = pHddCtx->nv->size;
hddLog(VOS_TRACE_LEVEL_INFO, "%s: nv file size = %d",
__func__, *pSize);
}
}
EXIT();
return retval;
}
/**---------------------------------------------------------------------------
\brief hdd_full_pwr_cbk() - HDD full power callbackfunction
This is the function invoked by SME to inform the result of a full power
request issued by HDD
\param - callbackcontext - Pointer to cookie
status - result of request
\return - None
--------------------------------------------------------------------------*/
void hdd_full_pwr_cbk(void *callbackContext, eHalStatus status)
{
hdd_context_t *pHddCtx = (hdd_context_t*)callbackContext;
hddLog(VOS_TRACE_LEVEL_INFO_HIGH,"HDD full Power callback status = %d", status);
if(&pHddCtx->full_pwr_comp_var)
{
complete(&pHddCtx->full_pwr_comp_var);
}
}
/**---------------------------------------------------------------------------
\brief hdd_req_bmps_cbk() - HDD Request BMPS callback function
This is the function invoked by SME to inform the result of BMPS
request issued by HDD
\param - callbackcontext - Pointer to cookie
status - result of request
\return - None
--------------------------------------------------------------------------*/
void hdd_req_bmps_cbk(void *callbackContext, eHalStatus status)
{
struct completion *completion_var = (struct completion*) callbackContext;
hddLog(VOS_TRACE_LEVEL_ERROR, "HDD BMPS request Callback, status = %d\n", status);
if(completion_var != NULL)
{
complete(completion_var);
}
}
/**---------------------------------------------------------------------------
\brief hdd_get_cfg_file_size() -
This function reads the configuration file using the request firmware
API and returns the configuration file size.
\param - pCtx - Pointer to the adapter .
- pFileName - Pointer to the file name.
- pBufSize - Pointer to the buffer size.
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
VOS_STATUS hdd_get_cfg_file_size(v_VOID_t *pCtx, char *pFileName, v_SIZE_t *pBufSize)
{
int status;
hdd_context_t *pHddCtx = (hdd_context_t*)pCtx;
ENTER();
status = request_firmware(&pHddCtx->fw, pFileName, pHddCtx->parent_dev);
if(status || !pHddCtx->fw || !pHddCtx->fw->data) {
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: CFG download failed",__func__);
status = VOS_STATUS_E_FAILURE;
}
else {
*pBufSize = pHddCtx->fw->size;
hddLog(VOS_TRACE_LEVEL_INFO, "%s: CFG size = %d", __func__, *pBufSize);
release_firmware(pHddCtx->fw);
pHddCtx->fw = NULL;
}
EXIT();
return VOS_STATUS_SUCCESS;
}
/**---------------------------------------------------------------------------
\brief hdd_read_cfg_file() -
This function reads the configuration file using the request firmware
API and returns the cfg data and the buffer size of the configuration file.
\param - pCtx - Pointer to the adapter .
- pFileName - Pointer to the file name.
- pBuffer - Pointer to the data buffer.
- pBufSize - Pointer to the buffer size.
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
VOS_STATUS hdd_read_cfg_file(v_VOID_t *pCtx, char *pFileName,
v_VOID_t *pBuffer, v_SIZE_t *pBufSize)
{
int status;
hdd_context_t *pHddCtx = (hdd_context_t*)pCtx;
ENTER();
status = request_firmware(&pHddCtx->fw, pFileName, pHddCtx->parent_dev);
if(status || !pHddCtx->fw || !pHddCtx->fw->data) {
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: CFG download failed",__func__);
return VOS_STATUS_E_FAILURE;
}
else {
if(*pBufSize != pHddCtx->fw->size) {
hddLog(VOS_TRACE_LEVEL_ERROR, "%s: Caller sets invalid CFG "
"file size", __func__);
release_firmware(pHddCtx->fw);
pHddCtx->fw = NULL;
return VOS_STATUS_E_FAILURE;
}
else {
if(pBuffer) {
vos_mem_copy(pBuffer,pHddCtx->fw->data,*pBufSize);
}
release_firmware(pHddCtx->fw);
pHddCtx->fw = NULL;
}
}
EXIT();
return VOS_STATUS_SUCCESS;
}
/**---------------------------------------------------------------------------
\brief hdd_set_mac_addr_cb() -
This function is the call back function for setting the station
mac adrress called by ccm module to indicate the
success/failure result.
\param - hHal - Pointer to the hal module.
- result - returns the result of the set mac address.
\return - void
--------------------------------------------------------------------------*/
#ifndef FEATURE_WLAN_INTEGRATED_SOC
static void hdd_set_mac_addr_cb( tHalHandle hHal, tANI_S32 result )
{
// ignore the STA_ID response for now.
VOS_ASSERT( CCM_IS_RESULT_SUCCESS( result ) );
}
#endif
/**---------------------------------------------------------------------------
\brief hdd_set_mac_address() -
This function sets the user specified mac address using
the command ifconfig wlanX hw ether <mac adress>.
\param - dev - Pointer to the net device.
- addr - Pointer to the sockaddr.
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
static int hdd_set_mac_address(struct net_device *dev, void *addr)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
struct sockaddr *psta_mac_addr = addr;
eHalStatus halStatus = eHAL_STATUS_SUCCESS;
ENTER();
memcpy(&pAdapter->macAddressCurrent, psta_mac_addr->sa_data, ETH_ALEN);
#ifdef HDD_SESSIONIZE
// set the MAC address though the STA ID CFG.
halStatus = ccmCfgSetStr( pAdapter->hHal, WNI_CFG_STA_ID,
(v_U8_t *)&pAdapter->macAddressCurrent,
sizeof( pAdapter->macAddressCurrent ),
hdd_set_mac_addr_cb, VOS_FALSE );
#endif
memcpy(dev->dev_addr, psta_mac_addr->sa_data, ETH_ALEN);
EXIT();
return halStatus;
}
tANI_U8* wlan_hdd_get_intf_addr(hdd_context_t* pHddCtx)
{
int i;
for ( i = 0; i < VOS_MAX_CONCURRENCY_PERSONA; i++)
{
if( 0 == (pHddCtx->cfg_ini->intfAddrMask >> i))
break;
}
if( VOS_MAX_CONCURRENCY_PERSONA == i)
return NULL;
pHddCtx->cfg_ini->intfAddrMask |= (1 << i);
return &pHddCtx->cfg_ini->intfMacAddr[i].bytes[0];
}
void wlan_hdd_release_intf_addr(hdd_context_t* pHddCtx, tANI_U8* releaseAddr)
{
int i;
for ( i = 0; i < VOS_MAX_CONCURRENCY_PERSONA; i++)
{
if ( !memcmp(releaseAddr, &pHddCtx->cfg_ini->intfMacAddr[i].bytes[0], 6) )
{
pHddCtx->cfg_ini->intfAddrMask &= ~(1 << i);
break;
}
}
return;
}
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
static struct net_device_ops wlan_drv_ops = {
.ndo_open = hdd_open,
.ndo_stop = hdd_stop,
.ndo_uninit = hdd_uninit,
.ndo_start_xmit = hdd_hard_start_xmit,
.ndo_tx_timeout = hdd_tx_timeout,
.ndo_get_stats = hdd_stats,
.ndo_do_ioctl = hdd_ioctl,
.ndo_set_mac_address = hdd_set_mac_address,
.ndo_select_queue = hdd_select_queue,
#ifdef WLAN_FEATURE_PACKET_FILTERING
#if (LINUX_VERSION_CODE > KERNEL_VERSION(3,1,0))
.ndo_set_rx_mode = hdd_set_multicast_list,
#else
.ndo_set_multicast_list = hdd_set_multicast_list,
#endif //LINUX_VERSION_CODE
#endif
};
#ifdef CONFIG_CFG80211
static struct net_device_ops wlan_mon_drv_ops = {
.ndo_open = hdd_mon_open,
.ndo_stop = hdd_stop,
.ndo_uninit = hdd_uninit,
.ndo_start_xmit = hdd_mon_hard_start_xmit,
.ndo_tx_timeout = hdd_tx_timeout,
.ndo_get_stats = hdd_stats,
.ndo_do_ioctl = hdd_ioctl,
.ndo_set_mac_address = hdd_set_mac_address,
};
#endif
#endif
void hdd_set_station_ops( struct net_device *pWlanDev )
{
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
pWlanDev->tx_queue_len = NET_DEV_TX_QUEUE_LEN,
pWlanDev->netdev_ops = &wlan_drv_ops;
#else
pWlanDev->open = hdd_open;
pWlanDev->stop = hdd_stop;
pWlanDev->uninit = hdd_uninit;
pWlanDev->hard_start_xmit = NULL;
pWlanDev->tx_timeout = hdd_tx_timeout;
pWlanDev->get_stats = hdd_stats;
pWlanDev->do_ioctl = hdd_ioctl;
pWlanDev->tx_queue_len = NET_DEV_TX_QUEUE_LEN;
pWlanDev->set_mac_address = hdd_set_mac_address;
#endif
}
hdd_adapter_t* hdd_alloc_station_adapter( hdd_context_t *pHddCtx, tSirMacAddr macAddr, char* name )
{
struct net_device *pWlanDev = NULL;
hdd_adapter_t *pAdapter = NULL;
#ifdef CONFIG_CFG80211
/*
* cfg80211 initialization and registration....
*/
pWlanDev = alloc_netdev_mq(sizeof( hdd_adapter_t ), name, ether_setup, NUM_TX_QUEUES);
#else
//Allocate the net_device and private data (station ctx)
pWlanDev = alloc_etherdev_mq(sizeof( hdd_adapter_t ), NUM_TX_QUEUES);
#endif
if(pWlanDev != NULL)
{
//Save the pointer to the net_device in the HDD adapter
pAdapter = (hdd_adapter_t*) netdev_priv( pWlanDev );
#ifndef CONFIG_CFG80211
//Init the net_device structure
ether_setup(pWlanDev);
#endif
vos_mem_zero( pAdapter, sizeof( hdd_adapter_t ) );
pAdapter->dev = pWlanDev;
pAdapter->pHddCtx = pHddCtx;
pAdapter->magic = WLAN_HDD_ADAPTER_MAGIC;
init_completion(&pAdapter->session_open_comp_var);
init_completion(&pAdapter->session_close_comp_var);
init_completion(&pAdapter->disconnect_comp_var);
init_completion(&pAdapter->linkup_event_var);
init_completion(&pAdapter->cancel_rem_on_chan_var);
init_completion(&pAdapter->rem_on_chan_ready_event);
init_completion(&pAdapter->abortscan_event_var);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38))
init_completion(&pAdapter->offchannel_tx_event);
#endif
#ifdef CONFIG_CFG80211
init_completion(&pAdapter->tx_action_cnf_event);
#endif
init_completion(&pHddCtx->mc_sus_event_var);
init_completion(&pHddCtx->tx_sus_event_var);
init_completion(&pAdapter->scan_info.scan_req_completion_event);
pAdapter->isLinkUpSvcNeeded = FALSE;
pAdapter->higherDtimTransition = eANI_BOOLEAN_TRUE;
//Init the net_device structure
strlcpy(pWlanDev->name, name, IFNAMSIZ);
vos_mem_copy(pWlanDev->dev_addr, (void *)macAddr, sizeof(tSirMacAddr));
vos_mem_copy( pAdapter->macAddressCurrent.bytes, macAddr, sizeof(tSirMacAddr));
pWlanDev->watchdog_timeo = HDD_TX_TIMEOUT;
pWlanDev->hard_header_len += LIBRA_HW_NEEDED_HEADROOM;
hdd_set_station_ops( pAdapter->dev );
pWlanDev->destructor = free_netdev;
#ifdef CONFIG_CFG80211
pWlanDev->ieee80211_ptr = &pAdapter->wdev ;
pAdapter->wdev.wiphy = pHddCtx->wiphy;
pAdapter->wdev.netdev = pWlanDev;
#endif
/* set pWlanDev's parent to underlying device */
SET_NETDEV_DEV(pWlanDev, pHddCtx->parent_dev);
}
return pAdapter;
}
VOS_STATUS hdd_register_interface( hdd_adapter_t *pAdapter, tANI_U8 rtnl_lock_held )
{
struct net_device *pWlanDev = pAdapter->dev;
//hdd_station_ctx_t *pHddStaCtx = &pAdapter->sessionCtx.station;
//hdd_context_t *pHddCtx = WLAN_HDD_GET_CTX( pAdapter );
//eHalStatus halStatus = eHAL_STATUS_SUCCESS;
if( rtnl_lock_held )
{
if (strchr(pWlanDev->name, '%')) {
if( dev_alloc_name(pWlanDev, pWlanDev->name) < 0 )
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s:Failed:dev_alloc_name",__func__);
return VOS_STATUS_E_FAILURE;
}
}
if (register_netdevice(pWlanDev))
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s:Failed:register_netdev",__func__);
return VOS_STATUS_E_FAILURE;
}
}
else
{
if(register_netdev(pWlanDev))
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: Failed:register_netdev",__func__);
return VOS_STATUS_E_FAILURE;
}
}
set_bit(NET_DEVICE_REGISTERED, &pAdapter->event_flags);
return VOS_STATUS_SUCCESS;
}
eHalStatus hdd_smeCloseSessionCallback(void *pContext)
{
if(pContext != NULL)
{
clear_bit(SME_SESSION_OPENED, &((hdd_adapter_t*)pContext)->event_flags);
/* need to make sure all of our scheduled work has completed.
* This callback is called from MC thread context, so it is safe to
* to call below flush workqueue API from here.
*/
flush_scheduled_work();
complete(&((hdd_adapter_t*)pContext)->session_close_comp_var);
}
return eHAL_STATUS_SUCCESS;
}
VOS_STATUS hdd_init_station_mode( hdd_adapter_t *pAdapter )
{
struct net_device *pWlanDev = pAdapter->dev;
hdd_station_ctx_t *pHddStaCtx = &pAdapter->sessionCtx.station;
hdd_context_t *pHddCtx = WLAN_HDD_GET_CTX( pAdapter );
eHalStatus halStatus = eHAL_STATUS_SUCCESS;
VOS_STATUS status = VOS_STATUS_E_FAILURE;
int rc = 0;
INIT_COMPLETION(pAdapter->session_open_comp_var);
//Open a SME session for future operation
halStatus = sme_OpenSession( pHddCtx->hHal, hdd_smeRoamCallback, pAdapter,
(tANI_U8 *)&pAdapter->macAddressCurrent, &pAdapter->sessionId );
if ( !HAL_STATUS_SUCCESS( halStatus ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"sme_OpenSession() failed with status code %08d [x%08lx]",
halStatus, halStatus );
status = VOS_STATUS_E_FAILURE;
goto error_sme_open;
}
//Block on a completion variable. Can't wait forever though.
rc = wait_for_completion_interruptible_timeout(
&pAdapter->session_open_comp_var,
msecs_to_jiffies(WLAN_WAIT_TIME_SESSIONOPENCLOSE));
if (!rc)
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"Session is not opened within timeout period code %08d", rc );
status = VOS_STATUS_E_FAILURE;
goto error_sme_open;
}
// Register wireless extensions
if( eHAL_STATUS_SUCCESS != (halStatus = hdd_register_wext(pWlanDev)))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"hdd_register_wext() failed with status code %08d [x%08lx]",
halStatus, halStatus );
status = VOS_STATUS_E_FAILURE;
goto error_register_wext;
}
//Safe to register the hard_start_xmit function again
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
wlan_drv_ops.ndo_start_xmit = hdd_hard_start_xmit;
#else
pWlanDev->hard_start_xmit = hdd_hard_start_xmit;
#endif
//Set the Connection State to Not Connected
pHddStaCtx->conn_info.connState = eConnectionState_NotConnected;
//Set the default operation channel
pHddStaCtx->conn_info.operationChannel = pHddCtx->cfg_ini->OperatingChannel;
/* Make the default Auth Type as OPEN*/
pHddStaCtx->conn_info.authType = eCSR_AUTH_TYPE_OPEN_SYSTEM;
if( VOS_STATUS_SUCCESS != ( status = hdd_init_tx_rx( pAdapter ) ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"hdd_init_tx_rx() failed with status code %08d [x%08lx]",
status, status );
goto error_init_txrx;
}
set_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags);
if( VOS_STATUS_SUCCESS != ( status = hdd_wmm_adapter_init( pAdapter ) ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"hdd_wmm_adapter_init() failed with status code %08d [x%08lx]",
status, status );
goto error_wmm_init;
}
set_bit(WMM_INIT_DONE, &pAdapter->event_flags);
return VOS_STATUS_SUCCESS;
error_wmm_init:
clear_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags);
hdd_deinit_tx_rx(pAdapter);
error_init_txrx:
hdd_UnregisterWext(pWlanDev);
error_register_wext:
if(test_bit(SME_SESSION_OPENED, &pAdapter->event_flags))
{
INIT_COMPLETION(pAdapter->session_close_comp_var);
if( eHAL_STATUS_SUCCESS == sme_CloseSession( pHddCtx->hHal,
pAdapter->sessionId,
hdd_smeCloseSessionCallback, pAdapter ) )
{
//Block on a completion variable. Can't wait forever though.
wait_for_completion_interruptible_timeout(
&pAdapter->session_close_comp_var,
msecs_to_jiffies(WLAN_WAIT_TIME_SESSIONOPENCLOSE));
}
}
error_sme_open:
return status;
}
#ifdef CONFIG_CFG80211
void hdd_cleanup_actionframe( hdd_context_t *pHddCtx, hdd_adapter_t *pAdapter )
{
hdd_cfg80211_state_t *cfgState;
cfgState = WLAN_HDD_GET_CFG_STATE_PTR( pAdapter );
if( NULL != cfgState->buf )
{
int rc;
INIT_COMPLETION(pAdapter->tx_action_cnf_event);
rc = wait_for_completion_interruptible_timeout(
&pAdapter->tx_action_cnf_event,
msecs_to_jiffies(ACTION_FRAME_TX_TIMEOUT));
if(!rc)
{
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_ERROR,
("ERROR: HDD Wait for Action Confirmation Failed!!\n"));
}
}
return;
}
#endif
void hdd_deinit_adapter( hdd_context_t *pHddCtx, hdd_adapter_t *pAdapter )
{
ENTER();
switch ( pAdapter->device_mode )
{
case WLAN_HDD_INFRA_STATION:
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_DEVICE:
{
if(test_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags))
{
hdd_deinit_tx_rx( pAdapter );
clear_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags);
}
if(test_bit(WMM_INIT_DONE, &pAdapter->event_flags))
{
hdd_wmm_adapter_close( pAdapter );
clear_bit(WMM_INIT_DONE, &pAdapter->event_flags);
}
#ifdef CONFIG_CFG80211
hdd_cleanup_actionframe(pHddCtx, pAdapter);
#endif
break;
}
case WLAN_HDD_SOFTAP:
case WLAN_HDD_P2P_GO:
#ifdef WLAN_SOFTAP_FEATURE
{
#ifdef CONFIG_CFG80211
hdd_cleanup_actionframe(pHddCtx, pAdapter);
#endif
hdd_unregister_hostapd(pAdapter);
hdd_set_conparam( 0 );
#ifdef CONFIG_CFG80211
wlan_hdd_set_monitor_tx_adapter( WLAN_HDD_GET_CTX(pAdapter), NULL );
#endif
break;
}
case WLAN_HDD_MONITOR:
{
#ifdef CONFIG_CFG80211
hdd_adapter_t* pAdapterforTx = pAdapter->sessionCtx.monitor.pAdapterForTx;
#endif
if(test_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags))
{
hdd_deinit_tx_rx( pAdapter );
clear_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags);
}
#ifdef CONFIG_CFG80211
if(NULL != pAdapterforTx)
{
hdd_cleanup_actionframe(pHddCtx, pAdapterforTx);
}
#endif
#endif //WLAN_SOFTAP_FEATURE
break;
}
default:
break;
}
EXIT();
}
void hdd_cleanup_adapter( hdd_context_t *pHddCtx, hdd_adapter_t *pAdapter, tANI_U8 rtnl_held )
{
struct net_device *pWlanDev = pAdapter->dev;
if(test_bit(NET_DEVICE_REGISTERED, &pAdapter->event_flags)) {
if( rtnl_held )
{
unregister_netdevice(pWlanDev);
}
else
{
unregister_netdev(pWlanDev);
}
// note that the pAdapter is no longer valid at this point
// since the memory has been reclaimed
}
}
VOS_STATUS hdd_enable_bmps_imps(hdd_context_t *pHddCtx)
{
VOS_STATUS status = VOS_STATUS_SUCCESS;
if(pHddCtx->cfg_ini->fIsBmpsEnabled)
{
sme_EnablePowerSave(pHddCtx->hHal, ePMC_BEACON_MODE_POWER_SAVE);
}
if(pHddCtx->cfg_ini->fIsAutoBmpsTimerEnabled)
{
sme_StartAutoBmpsTimer(pHddCtx->hHal);
}
if (pHddCtx->cfg_ini->fIsImpsEnabled)
{
sme_EnablePowerSave (pHddCtx->hHal, ePMC_IDLE_MODE_POWER_SAVE);
}
return status;
}
VOS_STATUS hdd_disable_bmps_imps(hdd_context_t *pHddCtx, tANI_U8 session_type)
{
hdd_adapter_t *pAdapter = NULL;
eHalStatus halStatus;
VOS_STATUS status = VOS_STATUS_E_INVAL;
v_BOOL_t disableBmps = FALSE;
v_BOOL_t disableImps = FALSE;
switch(session_type)
{
case WLAN_HDD_INFRA_STATION:
case WLAN_HDD_SOFTAP:
#ifdef WLAN_FEATURE_P2P
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_GO:
#endif
//Exit BMPS -> Is Sta/P2P Client is already connected
pAdapter = hdd_get_adapter(pHddCtx, WLAN_HDD_INFRA_STATION);
if((NULL != pAdapter)&&
hdd_connIsConnected( WLAN_HDD_GET_STATION_CTX_PTR(pAdapter)))
{
disableBmps = TRUE;
}
pAdapter = hdd_get_adapter(pHddCtx, WLAN_HDD_P2P_CLIENT);
if((NULL != pAdapter)&&
hdd_connIsConnected( WLAN_HDD_GET_STATION_CTX_PTR(pAdapter)))
{
disableBmps = TRUE;
}
//Exit both Bmps and Imps incase of Go/SAP Mode
if((WLAN_HDD_SOFTAP == session_type) ||
(WLAN_HDD_P2P_GO == session_type))
{
disableBmps = TRUE;
disableImps = TRUE;
}
if(TRUE == disableImps)
{
if (pHddCtx->cfg_ini->fIsImpsEnabled)
{
sme_DisablePowerSave (pHddCtx->hHal, ePMC_IDLE_MODE_POWER_SAVE);
}
}
if(TRUE == disableBmps)
{
if(pHddCtx->cfg_ini->fIsBmpsEnabled)
{
halStatus = sme_DisablePowerSave(pHddCtx->hHal, ePMC_BEACON_MODE_POWER_SAVE);
if(eHAL_STATUS_SUCCESS != halStatus)
{
status = VOS_STATUS_E_FAILURE;
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: Fail to Disable Power Save\n", __func__);
VOS_ASSERT(0);
return status;
}
}
if(pHddCtx->cfg_ini->fIsAutoBmpsTimerEnabled)
{
halStatus = sme_StopAutoBmpsTimer(pHddCtx->hHal);
if(eHAL_STATUS_SUCCESS != halStatus)
{
status = VOS_STATUS_E_FAILURE;
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: Fail to Stop Auto Bmps Timer\n", __func__);
VOS_ASSERT(0);
return status;
}
}
}
if((TRUE == disableBmps) ||
(TRUE == disableImps))
{
/* Now, get the chip into Full Power now */
INIT_COMPLETION(pHddCtx->full_pwr_comp_var);
halStatus = sme_RequestFullPower(pHddCtx->hHal, hdd_full_pwr_cbk,
pHddCtx, eSME_FULL_PWR_NEEDED_BY_HDD);
if(halStatus != eHAL_STATUS_SUCCESS)
{
if(halStatus == eHAL_STATUS_PMC_PENDING)
{
//Block on a completion variable. Can't wait forever though
wait_for_completion_interruptible_timeout(
&pHddCtx->full_pwr_comp_var, msecs_to_jiffies(1000));
}
else
{
status = VOS_STATUS_E_FAILURE;
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: Request for Full Power failed\n", __func__);
VOS_ASSERT(0);
return status;
}
}
status = VOS_STATUS_SUCCESS;
}
break;
}
return status;
}
hdd_adapter_t* hdd_open_adapter( hdd_context_t *pHddCtx, tANI_U8 session_type,
char *iface_name, tSirMacAddr macAddr,
tANI_U8 rtnl_held )
{
hdd_adapter_t *pAdapter = NULL;
hdd_adapter_list_node_t *pHddAdapterNode = NULL;
VOS_STATUS status = VOS_STATUS_E_FAILURE;
VOS_STATUS exitbmpsStatus;
hddLog(VOS_TRACE_LEVEL_INFO_HIGH, "%s iface =%s type = %d\n",__func__,iface_name,session_type);
//Disable BMPS incase of Concurrency
exitbmpsStatus = hdd_disable_bmps_imps(pHddCtx, session_type);
if(VOS_STATUS_E_FAILURE == exitbmpsStatus)
{
//Fail to Exit BMPS
VOS_ASSERT(0);
return NULL;
}
switch(session_type)
{
case WLAN_HDD_INFRA_STATION:
#ifdef WLAN_FEATURE_P2P
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_DEVICE:
#endif
{
pAdapter = hdd_alloc_station_adapter( pHddCtx, macAddr, iface_name );
if( NULL == pAdapter )
return NULL;
#ifdef CONFIG_CFG80211
pAdapter->wdev.iftype = (session_type == WLAN_HDD_P2P_CLIENT) ?
NL80211_IFTYPE_P2P_CLIENT:
NL80211_IFTYPE_STATION;
#endif
pAdapter->device_mode = session_type;
status = hdd_init_station_mode( pAdapter );
if( VOS_STATUS_SUCCESS != status )
goto err_free_netdev;
status = hdd_register_interface( pAdapter, rtnl_held );
if( VOS_STATUS_SUCCESS != status )
{
hdd_deinit_adapter(pHddCtx, pAdapter);
goto err_free_netdev;
}
//Stop the Interface TX queue.
netif_tx_disable(pAdapter->dev);
//netif_tx_disable(pWlanDev);
netif_carrier_off(pAdapter->dev);
break;
}
#ifdef WLAN_FEATURE_P2P
case WLAN_HDD_P2P_GO:
#endif
case WLAN_HDD_SOFTAP:
{
pAdapter = hdd_wlan_create_ap_dev( pHddCtx, macAddr, (tANI_U8 *)iface_name );
if( NULL == pAdapter )
return NULL;
#ifdef CONFIG_CFG80211
pAdapter->wdev.iftype = (session_type == WLAN_HDD_SOFTAP) ?
NL80211_IFTYPE_AP:
NL80211_IFTYPE_P2P_GO;
#endif
pAdapter->device_mode = session_type;
status = hdd_init_ap_mode(pAdapter);
if( VOS_STATUS_SUCCESS != status )
goto err_free_netdev;
status = hdd_register_hostapd( pAdapter, rtnl_held );
if( VOS_STATUS_SUCCESS != status )
{
hdd_deinit_adapter(pHddCtx, pAdapter);
goto err_free_netdev;
}
netif_tx_disable(pAdapter->dev);
netif_carrier_off(pAdapter->dev);
hdd_set_conparam( 1 );
break;
}
case WLAN_HDD_MONITOR:
{
#ifdef CONFIG_CFG80211
pAdapter = hdd_alloc_station_adapter( pHddCtx, macAddr, iface_name );
if( NULL == pAdapter )
return NULL;
pAdapter->wdev.iftype = NL80211_IFTYPE_MONITOR;
pAdapter->device_mode = session_type;
status = hdd_register_interface( pAdapter, rtnl_held );
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29)
pAdapter->dev->netdev_ops = &wlan_mon_drv_ops;
#else
pAdapter->dev->open = hdd_mon_open;
pAdapter->dev->hard_start_xmit = hdd_mon_hard_start_xmit;
#endif
hdd_init_tx_rx( pAdapter );
set_bit(INIT_TX_RX_SUCCESS, &pAdapter->event_flags);
//Set adapter to be used for data tx. It will use either GO or softap.
pAdapter->sessionCtx.monitor.pAdapterForTx =
hdd_get_adapter(pAdapter->pHddCtx, WLAN_HDD_SOFTAP);
#ifdef WLAN_FEATURE_P2P
if (NULL == pAdapter->sessionCtx.monitor.pAdapterForTx)
{
pAdapter->sessionCtx.monitor.pAdapterForTx =
hdd_get_adapter(pAdapter->pHddCtx, WLAN_HDD_P2P_GO);
}
#endif
/* This workqueue will be used to transmit management packet over
* monitor interface. */
INIT_WORK(&pAdapter->sessionCtx.monitor.pAdapterForTx->monTxWorkQueue,
hdd_mon_tx_work_queue);
#endif
}
break;
#ifdef ANI_MANF_DIAG
case WLAN_HDD_FTM:
{
pAdapter = hdd_alloc_station_adapter( pHddCtx, macAddr, iface_name );
if( NULL == pAdapter )
return NULL;
/* Assign NL80211_IFTYPE_STATION as interface type to resolve Kernel Warning
* message while loading driver in FTM mode. */
pAdapter->wdev.iftype = NL80211_IFTYPE_STATION;
pAdapter->device_mode = session_type;
status = hdd_register_interface( pAdapter, rtnl_held );
}
break;
#endif
default:
{
VOS_ASSERT(0);
return NULL;
}
}
if( VOS_STATUS_SUCCESS == status )
{
//Add it to the hdd's session list.
pHddAdapterNode = vos_mem_malloc( sizeof( hdd_adapter_list_node_t ) );
if( NULL == pHddAdapterNode )
{
status = VOS_STATUS_E_NOMEM;
}
else
{
pHddAdapterNode->pAdapter = pAdapter;
status = hdd_add_adapter_back ( pHddCtx,
pHddAdapterNode );
}
}
if( VOS_STATUS_SUCCESS != status )
{
if( NULL != pAdapter )
{
hdd_cleanup_adapter( pHddCtx, pAdapter, rtnl_held );
pAdapter = NULL;
}
if( NULL != pHddAdapterNode )
{
vos_mem_free( pHddAdapterNode );
}
goto resume_bmps;
}
if(VOS_STATUS_SUCCESS == status)
{
wlan_hdd_set_concurrency_mode(pHddCtx, session_type);
#ifdef FEATURE_WLAN_NON_INTEGRATED_SOC
/* If there are concurrent session enable SW frame translation
* for all registered STA
* This is not required in case of PRIMA as HW frame translation
* is disabled in PRIMA*/
if (vos_concurrent_sessions_running())
{
WLANTL_ConfigureSwFrameTXXlationForAll(pHddCtx->pvosContext, TRUE);
}
#endif
}
return pAdapter;
err_free_netdev:
free_netdev(pAdapter->dev);
wlan_hdd_release_intf_addr( pHddCtx,
pAdapter->macAddressCurrent.bytes );
resume_bmps:
//If bmps disabled enable it
if(VOS_STATUS_SUCCESS == exitbmpsStatus)
{
hdd_enable_bmps_imps(pHddCtx);
}
return NULL;
}
VOS_STATUS hdd_close_adapter( hdd_context_t *pHddCtx, hdd_adapter_t *pAdapter,
tANI_U8 rtnl_held )
{
hdd_adapter_list_node_t *pAdapterNode, *pCurrent, *pNext;
VOS_STATUS status;
status = hdd_get_front_adapter ( pHddCtx, &pCurrent );
if( VOS_STATUS_SUCCESS != status )
return status;
while ( pCurrent->pAdapter != pAdapter )
{
status = hdd_get_next_adapter ( pHddCtx, pCurrent, &pNext );
if( VOS_STATUS_SUCCESS != status )
break;
pCurrent = pNext;
}
pAdapterNode = pCurrent;
if( VOS_STATUS_SUCCESS == status )
{
wlan_hdd_clear_concurrency_mode(pHddCtx, pAdapter->device_mode);
hdd_cleanup_adapter( pHddCtx, pAdapterNode->pAdapter, rtnl_held );
hdd_remove_adapter( pHddCtx, pAdapterNode );
vos_mem_free( pAdapterNode );
#ifdef FEATURE_WLAN_NON_INTEGRATED_SOC
/* If there is no concurrent session disable SW frame translation
* for all registered STA */
/* This is not required in case of PRIMA as HW frame translation
* is disabled in PRIMA*/
if (!vos_concurrent_sessions_running())
{
WLANTL_ConfigureSwFrameTXXlationForAll(pHddCtx->pvosContext, FALSE);
}
#endif
/* If there is a single session of STA/P2P client, re-enable BMPS */
if ((!vos_concurrent_sessions_running()) &&
((pHddCtx->no_of_sessions[VOS_STA_MODE] >= 1) ||
(pHddCtx->no_of_sessions[VOS_P2P_CLIENT_MODE] >= 1)))
{
hdd_enable_bmps_imps(pHddCtx);
}
return VOS_STATUS_SUCCESS;
}
return VOS_STATUS_E_FAILURE;
}
VOS_STATUS hdd_close_all_adapters( hdd_context_t *pHddCtx )
{
hdd_adapter_list_node_t *pHddAdapterNode;
VOS_STATUS status;
ENTER();
do
{
status = hdd_remove_front_adapter( pHddCtx, &pHddAdapterNode );
if( pHddAdapterNode && VOS_STATUS_SUCCESS == status )
{
hdd_cleanup_adapter( pHddCtx, pHddAdapterNode->pAdapter, FALSE );
vos_mem_free( pHddAdapterNode );
}
}while( NULL != pHddAdapterNode && VOS_STATUS_E_EMPTY != status );
EXIT();
return VOS_STATUS_SUCCESS;
}
void wlan_hdd_reset_prob_rspies(hdd_adapter_t* pHostapdAdapter)
{
v_U8_t addIE[1] = {0};
if ( eHAL_STATUS_FAILURE == ccmCfgSetStr((WLAN_HDD_GET_CTX(pHostapdAdapter))->hHal,
WNI_CFG_PROBE_RSP_ADDNIE_DATA1,(tANI_U8*)addIE, 0, NULL,
eANI_BOOLEAN_FALSE) )
{
hddLog(LOGE,
"Could not pass on WNI_CFG_PROBE_RSP_ADDNIE_DATA1 to CCM\n");
}
if ( eHAL_STATUS_FAILURE == ccmCfgSetStr((WLAN_HDD_GET_CTX(pHostapdAdapter))->hHal,
WNI_CFG_PROBE_RSP_ADDNIE_DATA2, (tANI_U8*)addIE, 0, NULL,
eANI_BOOLEAN_FALSE) )
{
hddLog(LOGE,
"Could not pass on WNI_CFG_PROBE_RSP_ADDNIE_DATA2 to CCM\n");
}
if ( eHAL_STATUS_FAILURE == ccmCfgSetStr((WLAN_HDD_GET_CTX(pHostapdAdapter))->hHal,
WNI_CFG_PROBE_RSP_ADDNIE_DATA3, (tANI_U8*)addIE, 0, NULL,
eANI_BOOLEAN_FALSE) )
{
hddLog(LOGE,
"Could not pass on WNI_CFG_PROBE_RSP_ADDNIE_DATA3 to CCM\n");
}
}
VOS_STATUS hdd_stop_adapter( hdd_context_t *pHddCtx, hdd_adapter_t *pAdapter )
{
eHalStatus halStatus = eHAL_STATUS_SUCCESS;
hdd_wext_state_t *pWextState = WLAN_HDD_GET_WEXT_STATE_PTR(pAdapter);
union iwreq_data wrqu;
ENTER();
switch(pAdapter->device_mode)
{
case WLAN_HDD_INFRA_STATION:
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_DEVICE:
if( hdd_connIsConnected( WLAN_HDD_GET_STATION_CTX_PTR( pAdapter )) )
{
if (pWextState->roamProfile.BSSType == eCSR_BSS_TYPE_START_IBSS)
halStatus = sme_RoamDisconnect(pHddCtx->hHal,
pAdapter->sessionId,
eCSR_DISCONNECT_REASON_IBSS_LEAVE);
else
halStatus = sme_RoamDisconnect(pHddCtx->hHal,
pAdapter->sessionId,
eCSR_DISCONNECT_REASON_UNSPECIFIED);
//success implies disconnect command got queued up successfully
if(halStatus == eHAL_STATUS_SUCCESS)
{
wait_for_completion_interruptible_timeout(&pAdapter->disconnect_comp_var,
msecs_to_jiffies(WLAN_WAIT_TIME_DISCONNECT));
}
memset(&wrqu, '\0', sizeof(wrqu));
wrqu.ap_addr.sa_family = ARPHRD_ETHER;
memset(wrqu.ap_addr.sa_data,'\0',ETH_ALEN);
wireless_send_event(pAdapter->dev, SIOCGIWAP, &wrqu, NULL);
}
else
{
hdd_abort_mac_scan(pHddCtx);
}
if (test_bit(SME_SESSION_OPENED, &pAdapter->event_flags))
{
INIT_COMPLETION(pAdapter->session_close_comp_var);
if (eHAL_STATUS_SUCCESS ==
sme_CloseSession(pHddCtx->hHal, pAdapter->sessionId,
hdd_smeCloseSessionCallback, pAdapter))
{
//Block on a completion variable. Can't wait forever though.
wait_for_completion_interruptible_timeout(
&pAdapter->session_close_comp_var,
msecs_to_jiffies(WLAN_WAIT_TIME_SESSIONOPENCLOSE));
}
}
break;
case WLAN_HDD_SOFTAP:
case WLAN_HDD_P2P_GO:
//Any softap specific cleanup here...
mutex_lock(&pHddCtx->sap_lock);
if (test_bit(SOFTAP_BSS_STARTED, &pAdapter->event_flags))
{
VOS_STATUS status;
hdd_context_t *pHddCtx = WLAN_HDD_GET_CTX(pAdapter);
//Stop Bss.
status = WLANSAP_StopBss(pHddCtx->pvosContext);
if (VOS_IS_STATUS_SUCCESS(status))
{
hdd_hostapd_state_t *pHostapdState =
WLAN_HDD_GET_HOSTAP_STATE_PTR(pAdapter);
status = vos_wait_single_event(&pHostapdState->vosEvent, 10000);
if (!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(LOGE, "%s: failure waiting for WLANSAP_StopBss",
__FUNCTION__);
}
}
else
{
hddLog(LOGE, "%s: failure in WLANSAP_StopBss", __FUNCTION__);
}
clear_bit(SOFTAP_BSS_STARTED, &pAdapter->event_flags);
if (eHAL_STATUS_FAILURE ==
ccmCfgSetInt(pHddCtx->hHal, WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG,
0, NULL, eANI_BOOLEAN_FALSE))
{
hddLog(LOGE,
"%s: Failed to set WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG",
__FUNCTION__);
}
if ( eHAL_STATUS_FAILURE == ccmCfgSetInt((WLAN_HDD_GET_CTX(pAdapter))->hHal,
WNI_CFG_ASSOC_RSP_ADDNIE_FLAG, 0, NULL,
eANI_BOOLEAN_FALSE) )
{
hddLog(LOGE,
"Could not pass on WNI_CFG_ASSOC_RSP_ADDNIE_FLAG to CCM");
}
// Reset WNI_CFG_PROBE_RSP Flags
wlan_hdd_reset_prob_rspies(pAdapter);
kfree(pAdapter->sessionCtx.ap.beacon);
pAdapter->sessionCtx.ap.beacon = NULL;
}
mutex_unlock(&pHddCtx->sap_lock);
break;
case WLAN_HDD_MONITOR:
break;
default:
break;
}
EXIT();
return VOS_STATUS_SUCCESS;
}
VOS_STATUS hdd_stop_all_adapters( hdd_context_t *pHddCtx )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
VOS_STATUS status;
hdd_adapter_t *pAdapter;
ENTER();
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
netif_tx_disable(pAdapter->dev);
netif_carrier_off(pAdapter->dev);
hdd_stop_adapter( pHddCtx, pAdapter );
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
EXIT();
return VOS_STATUS_SUCCESS;
}
VOS_STATUS hdd_reset_all_adapters( hdd_context_t *pHddCtx )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
VOS_STATUS status;
hdd_adapter_t *pAdapter;
ENTER();
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
netif_tx_disable(pAdapter->dev);
netif_carrier_off(pAdapter->dev);
//Record whether STA is associated
pAdapter->sessionCtx.station.bSendDisconnect =
hdd_connIsConnected( WLAN_HDD_GET_STATION_CTX_PTR( pAdapter )) ?
VOS_TRUE : VOS_FALSE;
hdd_deinit_tx_rx(pAdapter);
hdd_wmm_adapter_close(pAdapter);
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
EXIT();
return VOS_STATUS_SUCCESS;
}
VOS_STATUS hdd_start_all_adapters( hdd_context_t *pHddCtx )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
VOS_STATUS status;
hdd_adapter_t *pAdapter;
v_MACADDR_t bcastMac = VOS_MAC_ADDR_BROADCAST_INITIALIZER;
ENTER();
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
switch(pAdapter->device_mode)
{
case WLAN_HDD_INFRA_STATION:
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_DEVICE:
hdd_init_station_mode(pAdapter);
/* Open the gates for HDD to receive Wext commands */
pAdapter->isLinkUpSvcNeeded = FALSE;
pAdapter->scan_info.mScanPending = FALSE;
pAdapter->scan_info.waitScanResult = FALSE;
//Trigger the initial scan
hdd_wlan_initial_scan(pAdapter);
//Indicate disconnect event to supplicant if associated previously
if(pAdapter->sessionCtx.station.bSendDisconnect)
{
union iwreq_data wrqu;
memset(&wrqu, '\0', sizeof(wrqu));
wrqu.ap_addr.sa_family = ARPHRD_ETHER;
memset(wrqu.ap_addr.sa_data,'\0',ETH_ALEN);
wireless_send_event(pAdapter->dev, SIOCGIWAP, &wrqu, NULL);
pAdapter->sessionCtx.station.bSendDisconnect = VOS_FALSE;
#ifdef CONFIG_CFG80211
/* indicate disconnected event to nl80211 */
cfg80211_disconnected(pAdapter->dev, WLAN_REASON_UNSPECIFIED,
NULL, 0, GFP_KERNEL);
#endif
}
break;
case WLAN_HDD_SOFTAP:
/* softAP can handle SSR */
break;
case WLAN_HDD_P2P_GO:
#ifdef CONFIG_CFG80211
hddLog(VOS_TRACE_LEVEL_ERROR, "%s [SSR] send restart supplicant",
__func__);
/* event supplicant to restart */
cfg80211_del_sta(pAdapter->dev,
(const u8 *)&bcastMac.bytes[0], GFP_KERNEL);
#endif
break;
case WLAN_HDD_MONITOR:
/* monitor interface start */
break;
default:
break;
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
EXIT();
return VOS_STATUS_SUCCESS;
}
VOS_STATUS hdd_reconnect_all_adapters( hdd_context_t *pHddCtx )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
hdd_adapter_t *pAdapter;
VOS_STATUS status;
v_U32_t roamId;
ENTER();
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if( (WLAN_HDD_INFRA_STATION == pAdapter->device_mode) ||
(WLAN_HDD_P2P_CLIENT == pAdapter->device_mode) )
{
hdd_station_ctx_t *pHddStaCtx = WLAN_HDD_GET_STATION_CTX_PTR(pAdapter);
hdd_wext_state_t *pWextState = WLAN_HDD_GET_WEXT_STATE_PTR(pAdapter);
pHddStaCtx->conn_info.connState = eConnectionState_NotConnected;
init_completion(&pAdapter->disconnect_comp_var);
sme_RoamDisconnect(pHddCtx->hHal, pAdapter->sessionId,
eCSR_DISCONNECT_REASON_UNSPECIFIED);
wait_for_completion_interruptible_timeout(
&pAdapter->disconnect_comp_var,
msecs_to_jiffies(WLAN_WAIT_TIME_DISCONNECT));
pWextState->roamProfile.csrPersona = pAdapter->device_mode;
pHddCtx->isAmpAllowed = VOS_FALSE;
sme_RoamConnect(pHddCtx->hHal,
pAdapter->sessionId, &(pWextState->roamProfile),
&roamId);
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
EXIT();
return VOS_STATUS_SUCCESS;
}
v_U8_t hdd_is_ssr_required( void)
{
return isSsrRequired;
}
void hdd_set_ssr_required( v_U8_t value)
{
isSsrRequired = value;
}
VOS_STATUS hdd_get_front_adapter( hdd_context_t *pHddCtx,
hdd_adapter_list_node_t** ppAdapterNode)
{
VOS_STATUS status;
spin_lock(&pHddCtx->hddAdapters.lock);
status = hdd_list_peek_front ( &pHddCtx->hddAdapters,
(hdd_list_node_t**) ppAdapterNode );
spin_unlock(&pHddCtx->hddAdapters.lock);
return status;
}
VOS_STATUS hdd_get_next_adapter( hdd_context_t *pHddCtx,
hdd_adapter_list_node_t* pAdapterNode,
hdd_adapter_list_node_t** pNextAdapterNode)
{
VOS_STATUS status;
spin_lock(&pHddCtx->hddAdapters.lock);
status = hdd_list_peek_next ( &pHddCtx->hddAdapters,
(hdd_list_node_t*) pAdapterNode,
(hdd_list_node_t**)pNextAdapterNode );
spin_unlock(&pHddCtx->hddAdapters.lock);
return status;
}
VOS_STATUS hdd_remove_adapter( hdd_context_t *pHddCtx,
hdd_adapter_list_node_t* pAdapterNode)
{
VOS_STATUS status;
spin_lock(&pHddCtx->hddAdapters.lock);
status = hdd_list_remove_node ( &pHddCtx->hddAdapters,
&pAdapterNode->node );
spin_unlock(&pHddCtx->hddAdapters.lock);
return status;
}
VOS_STATUS hdd_remove_front_adapter( hdd_context_t *pHddCtx,
hdd_adapter_list_node_t** ppAdapterNode)
{
VOS_STATUS status;
spin_lock(&pHddCtx->hddAdapters.lock);
status = hdd_list_remove_front( &pHddCtx->hddAdapters,
(hdd_list_node_t**) ppAdapterNode );
spin_unlock(&pHddCtx->hddAdapters.lock);
return status;
}
VOS_STATUS hdd_add_adapter_back( hdd_context_t *pHddCtx,
hdd_adapter_list_node_t* pAdapterNode)
{
VOS_STATUS status;
spin_lock(&pHddCtx->hddAdapters.lock);
status = hdd_list_insert_back ( &pHddCtx->hddAdapters,
(hdd_list_node_t*) pAdapterNode );
spin_unlock(&pHddCtx->hddAdapters.lock);
return status;
}
VOS_STATUS hdd_add_adapter_front( hdd_context_t *pHddCtx,
hdd_adapter_list_node_t* pAdapterNode)
{
VOS_STATUS status;
spin_lock(&pHddCtx->hddAdapters.lock);
status = hdd_list_insert_front ( &pHddCtx->hddAdapters,
(hdd_list_node_t*) pAdapterNode );
spin_unlock(&pHddCtx->hddAdapters.lock);
return status;
}
hdd_adapter_t * hdd_get_adapter_by_macaddr( hdd_context_t *pHddCtx,
tSirMacAddr macAddr )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
hdd_adapter_t *pAdapter;
VOS_STATUS status;
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if( pAdapter && vos_mem_compare( pAdapter->macAddressCurrent.bytes,
macAddr, sizeof(tSirMacAddr) ) )
{
return pAdapter;
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
return NULL;
}
hdd_adapter_t * hdd_get_adapter_by_name( hdd_context_t *pHddCtx, tANI_U8 *name )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
hdd_adapter_t *pAdapter;
VOS_STATUS status;
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if( pAdapter && !strncmp( pAdapter->dev->name, (const char *)name,
IFNAMSIZ ) )
{
return pAdapter;
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
return NULL;
}
hdd_adapter_t * hdd_get_adapter( hdd_context_t *pHddCtx, device_mode_t mode )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
hdd_adapter_t *pAdapter;
VOS_STATUS status;
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if( pAdapter && (mode == pAdapter->device_mode) )
{
return pAdapter;
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
return NULL;
}
//Remove this function later
hdd_adapter_t * hdd_get_mon_adapter( hdd_context_t *pHddCtx )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
hdd_adapter_t *pAdapter;
VOS_STATUS status;
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if( pAdapter && WLAN_HDD_MONITOR == pAdapter->device_mode )
{
return pAdapter;
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
return NULL;
}
#ifdef CONFIG_CFG80211
/**---------------------------------------------------------------------------
\brief hdd_set_monitor_tx_adapter() -
This API initializes the adapter to be used while transmitting on monitor
adapter.
\param - pHddCtx - Pointer to the HDD context.
pAdapter - Adapter that will used for TX. This can be NULL.
\return - None.
--------------------------------------------------------------------------*/
void wlan_hdd_set_monitor_tx_adapter( hdd_context_t *pHddCtx, hdd_adapter_t *pAdapter )
{
hdd_adapter_t *pMonAdapter;
pMonAdapter = hdd_get_adapter( pHddCtx, WLAN_HDD_MONITOR );
if( NULL != pMonAdapter )
{
pMonAdapter->sessionCtx.monitor.pAdapterForTx = pAdapter;
}
}
#endif
/**---------------------------------------------------------------------------
\brief hdd_select_queue() -
This API returns the operating channel of the requested device mode
\param - pHddCtx - Pointer to the HDD context.
- mode - Device mode for which operating channel is required
suported modes - WLAN_HDD_INFRA_STATION, WLAN_HDD_P2P_CLIENT
WLAN_HDD_SOFTAP, WLAN_HDD_P2P_GO.
\return - channel number. "0" id the requested device is not found OR it is not connected.
--------------------------------------------------------------------------*/
v_U8_t hdd_get_operating_channel( hdd_context_t *pHddCtx, device_mode_t mode )
{
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
VOS_STATUS status;
hdd_adapter_t *pAdapter;
v_U8_t operatingChannel = 0;
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if( mode == pAdapter->device_mode )
{
switch(pAdapter->device_mode)
{
case WLAN_HDD_INFRA_STATION:
case WLAN_HDD_P2P_CLIENT:
if( hdd_connIsConnected( WLAN_HDD_GET_STATION_CTX_PTR( pAdapter )) )
operatingChannel = (WLAN_HDD_GET_STATION_CTX_PTR(pAdapter))->conn_info.operationChannel;
break;
case WLAN_HDD_SOFTAP:
case WLAN_HDD_P2P_GO:
/*softap connection info */
if(test_bit(SOFTAP_BSS_STARTED, &pAdapter->event_flags))
operatingChannel = (WLAN_HDD_GET_AP_CTX_PTR(pAdapter))->operatingChannel;
break;
default:
break;
}
break; //Found the device of interest. break the loop
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
return operatingChannel;
}
#ifdef WLAN_FEATURE_PACKET_FILTERING
/**---------------------------------------------------------------------------
\brief hdd_set_multicast_list() -
This used to set the multicast address list.
\param - dev - Pointer to the WLAN device.
- skb - Pointer to OS packet (sk_buff).
\return - success/fail
--------------------------------------------------------------------------*/
static void hdd_set_multicast_list(struct net_device *dev)
{
hdd_adapter_t *pAdapter = WLAN_HDD_GET_PRIV_PTR(dev);
hdd_context_t *pHddCtx;
int mc_count;
int i = 0;
struct netdev_hw_addr *ha;
pHddCtx = (hdd_context_t*)pAdapter->pHddCtx;
if (NULL == pHddCtx)
{
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: HDD context is Null", __FUNCTION__);
return;
}
if (dev->flags & IFF_ALLMULTI)
{
hddLog(VOS_TRACE_LEVEL_INFO,
"%s: allow all multicast frames", __FUNCTION__);
pHddCtx->mc_addr_list.mc_cnt = 0;
}
else
{
mc_count = netdev_mc_count(dev);
hddLog(VOS_TRACE_LEVEL_INFO,
"%s: mc_count = %u", __FUNCTION__, mc_count);
if (mc_count > WLAN_HDD_MAX_MC_ADDR_LIST)
{
hddLog(VOS_TRACE_LEVEL_INFO,
"%s: No free filter available; allow all multicast frames", __FUNCTION__);
pHddCtx->mc_addr_list.mc_cnt = 0;
return;
}
pHddCtx->mc_addr_list.mc_cnt = mc_count;
netdev_for_each_mc_addr(ha, dev) {
if (i == mc_count)
break;
memset(&(pHddCtx->mc_addr_list.addr[i][0]), 0, ETH_ALEN);
memcpy(&(pHddCtx->mc_addr_list.addr[i][0]), ha->addr, ETH_ALEN);
hddLog(VOS_TRACE_LEVEL_INFO, "\n%s: mlist[%d] = %02x:%02x:%02x:%02x:%02x:%02x",
__func__, i,
pHddCtx->mc_addr_list.addr[i][0], pHddCtx->mc_addr_list.addr[i][1],
pHddCtx->mc_addr_list.addr[i][2], pHddCtx->mc_addr_list.addr[i][3],
pHddCtx->mc_addr_list.addr[i][4], pHddCtx->mc_addr_list.addr[i][5]);
i++;
}
}
return;
}
#endif
/**---------------------------------------------------------------------------
\brief hdd_select_queue() -
This function is registered with the Linux OS for network
core to decide which queue to use first.
\param - dev - Pointer to the WLAN device.
- skb - Pointer to OS packet (sk_buff).
\return - ac, Queue Index/access category corresponding to UP in IP header
--------------------------------------------------------------------------*/
v_U16_t hdd_select_queue(struct net_device *dev,
struct sk_buff *skb)
{
return hdd_wmm_select_queue(dev, skb);
}
/**---------------------------------------------------------------------------
\brief hdd_wlan_initial_scan() -
This function triggers the initial scan
\param - pAdapter - Pointer to the HDD adapter.
--------------------------------------------------------------------------*/
void hdd_wlan_initial_scan(hdd_adapter_t *pAdapter)
{
tCsrScanRequest scanReq;
tCsrChannelInfo channelInfo;
eHalStatus halStatus;
unsigned long scanId;
hdd_context_t *pHddCtx = WLAN_HDD_GET_CTX(pAdapter);
vos_mem_zero(&scanReq, sizeof(tCsrScanRequest));
vos_mem_set(&scanReq.bssid, sizeof(tCsrBssid), 0xff);
scanReq.BSSType = eCSR_BSS_TYPE_ANY;
if(sme_Is11dSupported(pHddCtx->hHal))
{
halStatus = sme_ScanGetBaseChannels( pHddCtx->hHal, &channelInfo );
if ( HAL_STATUS_SUCCESS( halStatus ) )
{
scanReq.ChannelInfo.ChannelList = vos_mem_malloc(channelInfo.numOfChannels);
if( !scanReq.ChannelInfo.ChannelList )
{
hddLog(VOS_TRACE_LEVEL_ERROR, "%s kmalloc failed", __func__);
vos_mem_free(channelInfo.ChannelList);
return;
}
vos_mem_copy(scanReq.ChannelInfo.ChannelList, channelInfo.ChannelList,
channelInfo.numOfChannels);
scanReq.ChannelInfo.numOfChannels = channelInfo.numOfChannels;
vos_mem_free(channelInfo.ChannelList);
}
scanReq.scanType = eSIR_PASSIVE_SCAN;
scanReq.requestType = eCSR_SCAN_REQUEST_11D_SCAN;
scanReq.maxChnTime = pHddCtx->cfg_ini->nPassiveMaxChnTime;
scanReq.minChnTime = pHddCtx->cfg_ini->nPassiveMinChnTime;
}
else
{
scanReq.scanType = eSIR_ACTIVE_SCAN;
scanReq.requestType = eCSR_SCAN_REQUEST_FULL_SCAN;
scanReq.maxChnTime = pHddCtx->cfg_ini->nActiveMaxChnTime;
scanReq.minChnTime = pHddCtx->cfg_ini->nActiveMinChnTime;
}
halStatus = sme_ScanRequest(pHddCtx->hHal, pAdapter->sessionId, &scanReq, &scanId, NULL, NULL);
if ( !HAL_STATUS_SUCCESS( halStatus ) )
{
hddLog(VOS_TRACE_LEVEL_ERROR, "%s: sme_ScanRequest failed status code %d",
__func__, halStatus );
}
if(sme_Is11dSupported(pHddCtx->hHal))
vos_mem_free(scanReq.ChannelInfo.ChannelList);
}
struct fullPowerContext
{
struct completion completion;
unsigned int magic;
};
#define POWER_CONTEXT_MAGIC 0x504F5752 //POWR
/**---------------------------------------------------------------------------
\brief hdd_full_power_callback() - HDD full power callback function
This is the function invoked by SME to inform the result of a full power
request issued by HDD
\param - callbackcontext - Pointer to cookie
\param - status - result of request
\return - None
--------------------------------------------------------------------------*/
static void hdd_full_power_callback(void *callbackContext, eHalStatus status)
{
struct fullPowerContext *pContext = callbackContext;
hddLog(VOS_TRACE_LEVEL_INFO,
"%s: context = %p, status = %d", pContext, status);
if (NULL == callbackContext)
{
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: Bad param, context [%p]",
__FUNCTION__, callbackContext);
return;
}
/* there is a race condition that exists between this callback function
and the caller since the caller could time out either before or
while this code is executing. we'll assume the timeout hasn't
occurred, but we'll verify that right before we save our work */
if (POWER_CONTEXT_MAGIC != pContext->magic)
{
/* the caller presumably timed out so there is nothing we can do */
hddLog(VOS_TRACE_LEVEL_WARN,
"%s: Invalid context, magic [%08x]",
__FUNCTION__, pContext->magic);
return;
}
/* the race is on. caller could have timed out immediately after
we verified the magic, but if so, caller will wait a short time
for us to notify the caller, so the context will stay valid */
complete(&pContext->completion);
}
/**---------------------------------------------------------------------------
\brief hdd_wlan_exit() - HDD WLAN exit function
This is the driver exit point (invoked during rmmod)
\param - pHddCtx - Pointer to the HDD Context
\return - None
--------------------------------------------------------------------------*/
void hdd_wlan_exit(hdd_context_t *pHddCtx)
{
eHalStatus halStatus;
v_CONTEXT_t pVosContext = pHddCtx->pvosContext;
VOS_STATUS vosStatus;
#ifdef ANI_BUS_TYPE_SDIO
struct sdio_func *sdio_func_dev = NULL;
#endif // ANI_BUS_TYPE_SDIO
#ifdef CONFIG_CFG80211
struct wiphy *wiphy = pHddCtx->wiphy;
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
hdd_adapter_t* pAdapter;
#endif
struct fullPowerContext powerContext;
long lrc;
ENTER();
// Unloading, restart logic is no more required.
wlan_hdd_restart_deinit(pHddCtx);
#ifdef CONFIG_CFG80211
#ifdef WLAN_SOFTAP_FEATURE
if (VOS_STA_SAP_MODE != hdd_get_conparam())
#endif
{
#ifdef ANI_MANF_DIAG
if (VOS_FTM_MODE != hdd_get_conparam())
#endif /* ANI_MANF_DIAG */
{
hdd_adapter_t* pAdapter = hdd_get_adapter(pHddCtx,
WLAN_HDD_INFRA_STATION);
if (pAdapter == NULL)
pAdapter = hdd_get_adapter(pHddCtx, WLAN_HDD_P2P_CLIENT);
if (pAdapter != NULL)
{
wlan_hdd_cfg80211_pre_voss_stop(pAdapter);
hdd_UnregisterWext(pAdapter->dev);
}
}
}
#endif
#ifdef ANI_MANF_DIAG
if (VOS_FTM_MODE == hdd_get_conparam())
{
wlan_hdd_ftm_close(pHddCtx);
goto free_hdd_ctx;
}
#endif
//Stop the Interface TX queue.
//netif_tx_disable(pWlanDev);
//netif_carrier_off(pWlanDev);
#ifdef CONFIG_HAS_EARLYSUSPEND
// unregister suspend/resume callbacks
if(pHddCtx->cfg_ini->nEnableSuspend)
{
unregister_wlan_suspend();
}
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
#ifdef WLAN_SOFTAP_FEATURE
if (VOS_STA_SAP_MODE == hdd_get_conparam())
{
pAdapter = hdd_get_adapter(pHddCtx,
WLAN_HDD_SOFTAP);
}
else
{
#endif
#ifdef ANI_MANF_DIAG
if (VOS_FTM_MODE != hdd_get_conparam())
#endif /* ANI_MANF_DIAG */
{
pAdapter = hdd_get_adapter(pHddCtx,
WLAN_HDD_INFRA_STATION);
}
#ifdef WLAN_SOFTAP_FEATURE
}
#endif
/* DeRegister with platform driver as client for Suspend/Resume */
vosStatus = hddDeregisterPmOps(pHddCtx);
if ( !VOS_IS_STATUS_SUCCESS( vosStatus ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: hddDeregisterPmOps failed",__func__);
VOS_ASSERT(0);
}
vosStatus = hddDevTmUnregisterNotifyCallback(pHddCtx);
if ( !VOS_IS_STATUS_SUCCESS( vosStatus ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: hddDevTmUnregisterNotifyCallback failed",__func__);
}
#endif //FEATURE_WLAN_INTEGRATED_SOC
// Cancel any outstanding scan requests. We are about to close all
// of our adapters, but an adapter structure is what SME passes back
// to our callback function. Hence if there are any outstanding scan
// requests then there is a race condition between when the adapter
// is closed and when the callback is invoked. We try to resolve that
// race condition here by canceling any outstanding scans before we
// close the adapters.
// Note that the scans may be cancelled in an asynchronous manner, so
// ideally there needs to be some kind of synchronization. Rather than
// introduce a new synchronization here, we will utilize the fact that
// we are about to Request Full Power, and since that is synchronized,
// the expectation is that by the time Request Full Power has completed,
// all scans will be cancelled.
hdd_abort_mac_scan( pHddCtx );
//Disable IMPS/BMPS as we do not want the device to enter any power
//save mode during shutdown
sme_DisablePowerSave(pHddCtx->hHal, ePMC_IDLE_MODE_POWER_SAVE);
sme_DisablePowerSave(pHddCtx->hHal, ePMC_BEACON_MODE_POWER_SAVE);
sme_DisablePowerSave(pHddCtx->hHal, ePMC_UAPSD_MODE_POWER_SAVE);
//Ensure that device is in full power as we will touch H/W during vos_Stop
init_completion(&powerContext.completion);
powerContext.magic = POWER_CONTEXT_MAGIC;
halStatus = sme_RequestFullPower(pHddCtx->hHal, hdd_full_power_callback,
&powerContext, eSME_FULL_PWR_NEEDED_BY_HDD);
if (eHAL_STATUS_SUCCESS != halStatus)
{
if (eHAL_STATUS_PMC_PENDING == halStatus)
{
/* request was sent -- wait for the response */
lrc = wait_for_completion_interruptible_timeout(
&powerContext.completion,
msecs_to_jiffies(WLAN_WAIT_TIME_POWER));
/* either we have a response or we timed out
either way, first invalidate our magic */
powerContext.magic = 0;
if (lrc <= 0)
{
hddLog(VOS_TRACE_LEVEL_ERROR, "%s: %s while requesting full power",
__FUNCTION__, (0 == lrc) ? "timeout" : "interrupt");
/* there is a race condition such that the callback
function could be executing at the same time we are. of
primary concern is if the callback function had already
verified the "magic" but hasn't yet set the completion
variable. Since the completion variable is on our
stack, we'll delay just a bit to make sure the data is
still valid if that is the case */
msleep(50);
}
}
else
{
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: Request for Full Power failed, status %d",
__FUNCTION__, halStatus);
VOS_ASSERT(0);
/* continue -- need to clean up as much as possible */
}
}
// Unregister the Net Device Notifier
unregister_netdevice_notifier(&hdd_netdev_notifier);
hdd_stop_all_adapters( pHddCtx );
#ifdef ANI_BUS_TYPE_SDIO
sdio_func_dev = libra_getsdio_funcdev();
if(sdio_func_dev == NULL)
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: sdio_func_dev is NULL!",__func__);
VOS_ASSERT(0);
return;
}
sd_claim_host(sdio_func_dev);
/* Disable SDIO IRQ since we are exiting */
libra_enable_sdio_irq(sdio_func_dev, 0);
sd_release_host(sdio_func_dev);
#endif // ANI_BUS_TYPE_SDIO
#ifdef WLAN_BTAMP_FEATURE
vosStatus = WLANBAP_Stop(pVosContext);
if (!VOS_IS_STATUS_SUCCESS(vosStatus))
{
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_ERROR,
"%s: Failed to stop BAP",__func__);
}
#endif //WLAN_BTAMP_FEATURE
//Stop all the modules
vosStatus = vos_stop( pVosContext );
if (!VOS_IS_STATUS_SUCCESS(vosStatus))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to stop VOSS",__func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
}
#ifdef ANI_BUS_TYPE_SDIO
vosStatus = WLANBAL_Stop( pVosContext );
hddLog(VOS_TRACE_LEVEL_ERROR,"WLAN BAL STOP\n");
if (!VOS_IS_STATUS_SUCCESS(vosStatus))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to stop BAL",__func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
}
msleep(50);
//Put the chip is standby before asserting deep sleep
vosStatus = WLANBAL_SuspendChip( pVosContext );
hddLog(VOS_TRACE_LEVEL_ERROR,"WLAN Suspend Chip\n");
if (!VOS_IS_STATUS_SUCCESS(vosStatus))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to suspend chip ",__func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
}
//Invoke SAL stop
vosStatus = WLANSAL_Stop( pVosContext );
if (!VOS_IS_STATUS_SUCCESS(vosStatus))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to stop SAL",__func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
}
#endif // ANI_BUS_TYPE_SDIO
//Assert Deep sleep signal now to put Libra HW in lowest power state
vosStatus = vos_chipAssertDeepSleep( NULL, NULL, NULL );
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
//Vote off any PMIC voltage supplies
vos_chipPowerDown(NULL, NULL, NULL);
vos_chipVoteOffXOBuffer(NULL, NULL, NULL);
//Clean up HDD Nlink Service
send_btc_nlink_msg(WLAN_MODULE_DOWN_IND, 0);
nl_srv_exit();
//This requires pMac access, Call this before vos_close().
#ifdef CONFIG_HAS_EARLYSUSPEND
hdd_unregister_mcast_bcast_filter(pHddCtx);
#endif
//Close the scheduler before calling vos_close to make sure no thread is
// scheduled after the each module close is called i.e after all the data
// structures are freed.
vosStatus = vos_sched_close( pVosContext );
if (!VOS_IS_STATUS_SUCCESS(vosStatus)) {
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to close VOSS Scheduler",__func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
}
#ifdef WLAN_FEATURE_HOLD_RX_WAKELOCK
/* Destroy the wake lock */
wake_lock_destroy(&pHddCtx->rx_wake_lock);
#endif
//Close VOSS
//This frees pMac(HAL) context. There should not be any call that requires pMac access after this.
vos_close(pVosContext);
#ifdef ANI_BUS_TYPE_SDIO
vosStatus = WLANBAL_Close(pVosContext);
if (!VOS_IS_STATUS_SUCCESS(vosStatus))
{
VOS_TRACE( VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to close BAL",__func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( vosStatus ) );
}
hddLog(VOS_TRACE_LEVEL_ERROR,"Returned WLAN BAL CLOSE\n\n\n\n");
#endif // ANI_BUS_TYPE_SDIO
//Close Watchdog
if(pHddCtx->cfg_ini->fIsLogpEnabled)
vos_watchdog_close(pVosContext);
/* Cancel the vote for XO Core ON.
* This is done here to ensure there is no race condition since MC, TX and WD threads have
* exited at this point
*/
hddLog(VOS_TRACE_LEVEL_WARN, "In module exit: Cancel the vote for XO Core ON"
" when WLAN is turned OFF\n");
if (vos_chipVoteXOCore(NULL, NULL, NULL, VOS_FALSE) != VOS_STATUS_SUCCESS)
{
hddLog(VOS_TRACE_LEVEL_ERROR, "Could not cancel the vote for XO Core ON."
" Not returning failure."
" Power consumed will be high\n");
}
hdd_close_all_adapters( pHddCtx );
//Free up dynamically allocated members inside HDD Adapter
kfree(pHddCtx->cfg_ini);
pHddCtx->cfg_ini= NULL;
/* free the power on lock from platform driver */
if (free_riva_power_on_lock("wlan"))
{
hddLog(VOS_TRACE_LEVEL_ERROR, "%s: failed to free power on lock",
__func__);
}
#ifdef ANI_MANF_DIAG
free_hdd_ctx:
#endif
#ifdef CONFIG_CFG80211
wiphy_unregister(wiphy) ;
wiphy_free(wiphy) ;
#else
vos_mem_free( pHddCtx );
#endif
if (hdd_is_ssr_required())
{
/* WDI timeout had happened during unload, so SSR is needed here */
subsystem_restart("riva");
msleep(5000);
}
hdd_set_ssr_required (VOS_FALSE);
}
/**---------------------------------------------------------------------------
\brief hdd_update_config_from_nv() - Function to update the contents of
the running configuration with parameters taken from NV storage
\param - pHddCtx - Pointer to the HDD global context
\return - VOS_STATUS_SUCCESS if successful
--------------------------------------------------------------------------*/
static VOS_STATUS hdd_update_config_from_nv(hdd_context_t* pHddCtx)
{
#ifndef FEATURE_WLAN_INTEGRATED_SOC
eHalStatus halStatus;
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
v_BOOL_t itemIsValid = VOS_FALSE;
VOS_STATUS status;
v_MACADDR_t macFromNV[VOS_MAX_CONCURRENCY_PERSONA];
v_U8_t macLoop;
/*If the NV is valid then get the macaddress from nv else get it from qcom_cfg.ini*/
status = vos_nv_getValidity(VNV_FIELD_IMAGE, &itemIsValid);
if(status != VOS_STATUS_SUCCESS)
{
hddLog(VOS_TRACE_LEVEL_ERROR," vos_nv_getValidity() failed\n ");
return VOS_STATUS_E_FAILURE;
}
if (itemIsValid == VOS_TRUE)
{
hddLog(VOS_TRACE_LEVEL_INFO_HIGH," Reading the Macaddress from NV\n ");
status = vos_nv_readMultiMacAddress((v_U8_t *)&macFromNV[0].bytes[0],
VOS_MAX_CONCURRENCY_PERSONA);
if(status != VOS_STATUS_SUCCESS)
{
/* Get MAC from NV fail, not update CFG info
* INI MAC value will be used for MAC setting */
hddLog(VOS_TRACE_LEVEL_ERROR," vos_nv_readMacAddress() failed\n ");
return VOS_STATUS_E_FAILURE;
}
/* If first MAC is not valid, treat all others are not valid
* Then all MACs will be got from ini file */
if(vos_is_macaddr_zero(&macFromNV[0]))
{
/* MAC address in NV file is not configured yet */
hddLog(VOS_TRACE_LEVEL_WARN, "Invalid MAC in NV file");
return VOS_STATUS_E_INVAL;
}
/* Get MAC address from NV, update CFG info */
for(macLoop = 0; macLoop < VOS_MAX_CONCURRENCY_PERSONA; macLoop++)
{
if(vos_is_macaddr_zero(&macFromNV[macLoop]))
{
printk(KERN_ERR "not valid MAC from NV for %d", macLoop);
/* This MAC is not valid, skip it
* This MAC will be got from ini file */
}
else
{
vos_mem_copy((v_U8_t *)&pHddCtx->cfg_ini->intfMacAddr[macLoop].bytes[0],
(v_U8_t *)&macFromNV[macLoop].bytes[0],
VOS_MAC_ADDR_SIZE);
}
}
}
else
{
hddLog(VOS_TRACE_LEVEL_ERROR, "NV ITEM, MAC Not valid");
return VOS_STATUS_E_FAILURE;
}
#endif /* FEATURE_WLAN_INTEGRATED_SOC */
#ifndef FEATURE_WLAN_INTEGRATED_SOC
#if 1 /* need to fix for concurrency */
// Set the MAC Address
// Currently this is used by HAL to add self sta. Remove this once self sta is added as part of session open.
halStatus = ccmCfgSetStr( pHddCtx->hHal, WNI_CFG_STA_ID,
(v_U8_t *)&pHddCtx->cfg_ini->intfMacAddr[0],
sizeof( pHddCtx->cfg_ini->intfMacAddr[0]),
hdd_set_mac_addr_cb, VOS_FALSE );
if (!HAL_STATUS_SUCCESS( halStatus ))
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: Failed to set MAC Address. "
"HALStatus is %08d [x%08x]",__func__, halStatus, halStatus );
return VOS_STATUS_E_FAILURE;
}
#endif
#endif
return VOS_STATUS_SUCCESS;
}
/**---------------------------------------------------------------------------
\brief hdd_post_voss_start_config() - HDD post voss start config helper
\param - pAdapter - Pointer to the HDD
\return - None
--------------------------------------------------------------------------*/
VOS_STATUS hdd_post_voss_start_config(hdd_context_t* pHddCtx)
{
eHalStatus halStatus;
v_U32_t listenInterval;
#ifdef FEATURE_WLAN_NON_INTEGRATED_SOC
/* In the non-integrated architecture we update the configuration from
the INI file and from NV after vOSS has been started
*/
// Apply the cfg.ini to cfg.dat
if (FALSE == hdd_update_config_dat(pHddCtx))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: config update failed",__func__ );
return VOS_STATUS_E_FAILURE;
}
// Apply the NV to cfg.dat
if (VOS_STATUS_SUCCESS != hdd_update_config_from_nv(pHddCtx))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: config update from NV failed", __func__ );
return VOS_STATUS_E_FAILURE;
}
#endif // FEATURE_WLAN_NON_INTEGRATED_SOC
// Send ready indication to the HDD. This will kick off the MAC
// into a 'running' state and should kick off an initial scan.
halStatus = sme_HDDReadyInd( pHddCtx->hHal );
if ( !HAL_STATUS_SUCCESS( halStatus ) )
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%S: sme_HDDReadyInd() failed with status "
"code %08d [x%08x]",__func__, halStatus, halStatus );
return VOS_STATUS_E_FAILURE;
}
// Set default LI into HDD context,
// otherwise under some race condition, HDD will set 0 LI value into RIVA,
// And RIVA will crash
wlan_cfgGetInt(pHddCtx->hHal, WNI_CFG_LISTEN_INTERVAL, &listenInterval);
pHddCtx->hdd_actual_LI_value = listenInterval;
return VOS_STATUS_SUCCESS;
}
#ifdef ANI_BUS_TYPE_SDIO
#ifndef ANI_MANF_DIAG
// Routine to initialize the PMU
void wlan_hdd_enable_deepsleep(v_VOID_t * pVosContext)
{
/*-------------- Need to fix this correctly while doing Deepsleep testing
tANI_U32 regValue = 0;
regValue = QWLAN_PMU_LDO_CTRL_REG_PMU_ANA_DEEP_SLEEP_EN_MASK |
QWLAN_PMU_LDO_CTRL_REG_PMU_ANA_1P23_LPM_AON_MASK_MASK |
QWLAN_PMU_LDO_CTRL_REG_PMU_ANA_1P23_LPM_SW_MASK_MASK |
QWLAN_PMU_LDO_CTRL_REG_PMU_ANA_2P3_LPM_MASK_MASK;
WLANBAL_WriteRegister(pVosContext, QWLAN_PMU_LDO_CTRL_REG_REG, regValue);
---------------------*/
return;
}
#endif
#endif
/* wake lock APIs for HDD */
void hdd_prevent_suspend(void)
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,5))
wake_lock(&wlan_wake_lock);
#else
wcnss_prevent_suspend();
#endif
}
void hdd_allow_suspend(void)
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,5))
wake_unlock(&wlan_wake_lock);
#else
wcnss_allow_suspend();
#endif
}
/**---------------------------------------------------------------------------
\brief hdd_exchange_version_and_caps() - HDD function to exchange version and capability
information between Host and Riva
This function gets reported version of FW
It also finds the version of Riva headers used to compile the host
It compares the above two and prints a warning if they are different
It gets the SW and HW version string
Finally, it exchanges capabilities between host and Riva i.e. host and riva exchange a msg
indicating the features they support through a bitmap
\param - pHddCtx - Pointer to HDD context
\return - void
--------------------------------------------------------------------------*/
void hdd_exchange_version_and_caps(hdd_context_t *pHddCtx)
{
tSirVersionType versionCompiled;
tSirVersionType versionReported;
tSirVersionString versionString;
tANI_U8 fwFeatCapsMsgSupported = 0;
VOS_STATUS vstatus;
/* retrieve and display WCNSS version information */
do {
vstatus = sme_GetWcnssWlanCompiledVersion(pHddCtx->hHal,
&versionCompiled);
if (!VOS_IS_STATUS_SUCCESS(vstatus))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: unable to retrieve WCNSS WLAN compiled version",
__FUNCTION__);
break;
}
vstatus = sme_GetWcnssWlanReportedVersion(pHddCtx->hHal,
&versionReported);
if (!VOS_IS_STATUS_SUCCESS(vstatus))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: unable to retrieve WCNSS WLAN reported version",
__FUNCTION__);
break;
}
if ((versionCompiled.major != versionReported.major) ||
(versionCompiled.minor != versionReported.minor) ||
(versionCompiled.version != versionReported.version) ||
(versionCompiled.revision != versionReported.revision))
{
pr_err("%s: WCNSS WLAN Version %u.%u.%u.%u, "
"Host expected %u.%u.%u.%u\n",
WLAN_MODULE_NAME,
(int)versionReported.major,
(int)versionReported.minor,
(int)versionReported.version,
(int)versionReported.revision,
(int)versionCompiled.major,
(int)versionCompiled.minor,
(int)versionCompiled.version,
(int)versionCompiled.revision);
}
else
{
pr_info("%s: WCNSS WLAN version %u.%u.%u.%u\n",
WLAN_MODULE_NAME,
(int)versionReported.major,
(int)versionReported.minor,
(int)versionReported.version,
(int)versionReported.revision);
}
vstatus = sme_GetWcnssSoftwareVersion(pHddCtx->hHal,
versionString,
sizeof(versionString));
if (!VOS_IS_STATUS_SUCCESS(vstatus))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: unable to retrieve WCNSS software version string",
__FUNCTION__);
break;
}
pr_info("%s: WCNSS software version %s\n",
WLAN_MODULE_NAME, versionString);
vstatus = sme_GetWcnssHardwareVersion(pHddCtx->hHal,
versionString,
sizeof(versionString));
if (!VOS_IS_STATUS_SUCCESS(vstatus))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: unable to retrieve WCNSS hardware version string",
__FUNCTION__);
break;
}
pr_info("%s: WCNSS hardware version %s\n",
WLAN_MODULE_NAME, versionString);
/* 1.Check if FW version is greater than 0.1.1.0. Only then send host-FW capability exchange message
2.Host-FW capability exchange message is only present on riva 1.1 so
send the message only if it the riva is 1.1
minor numbers for different riva branches:
0 -> (1.0)Mainline Build
1 -> (1.1)Mainline Build
2->(1.04) Stability Build
*/
if (((versionReported.major>0) || (versionReported.minor>1) ||
((versionReported.minor>=1) && (versionReported.version>=1)))
&& ((versionReported.major == 1) && (versionReported.minor >= 1)))
fwFeatCapsMsgSupported = 1;
if (fwFeatCapsMsgSupported)
sme_featureCapsExchange(pHddCtx->hHal);
} while (0);
}
/**---------------------------------------------------------------------------
\brief hdd_wlan_startup() - HDD init function
This is the driver startup code executed once a WLAN device has been detected
\param - dev - Pointer to the underlying device
\return - 0 for success -1 for failure
--------------------------------------------------------------------------*/
int hdd_wlan_startup(struct device *dev )
{
VOS_STATUS status;
hdd_adapter_t *pAdapter = NULL;
hdd_adapter_t *pP2pAdapter = NULL;
hdd_context_t *pHddCtx = NULL;
v_CONTEXT_t pVosContext= NULL;
#ifdef WLAN_BTAMP_FEATURE
VOS_STATUS vStatus = VOS_STATUS_SUCCESS;
WLANBAP_ConfigType btAmpConfig;
hdd_config_t *pConfig;
#endif
int ret;
#ifdef CONFIG_CFG80211
struct wiphy *wiphy;
#endif
#ifdef ANI_BUS_TYPE_SDIO
struct sdio_func *sdio_func_dev = dev_to_sdio_func(dev);
#endif //ANI_BUS_TYPE_SDIO
ENTER();
#ifdef CONFIG_CFG80211
/*
* cfg80211: wiphy allocation
*/
wiphy = wlan_hdd_cfg80211_init(sizeof(hdd_context_t)) ;
if(wiphy == NULL)
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: cfg80211 init failed", __func__);
return -1;
}
pHddCtx = wiphy_priv(wiphy);
#else
pHddCtx = vos_mem_malloc ( sizeof( hdd_context_t ) );
if(pHddCtx == NULL)
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: cfg80211 init failed", __func__);
return -1;
}
#endif
//Initialize the adapter context to zeros.
vos_mem_zero(pHddCtx, sizeof( hdd_context_t ));
#ifdef CONFIG_CFG80211
pHddCtx->wiphy = wiphy;
#endif
hdd_prevent_suspend();
pHddCtx->isLoadUnloadInProgress = TRUE;
vos_set_load_unload_in_progress(VOS_MODULE_ID_VOSS, TRUE);
/*Get vos context here bcoz vos_open requires it*/
pVosContext = vos_get_global_context(VOS_MODULE_ID_SYS, NULL);
//Save the Global VOSS context in adapter context for future.
pHddCtx->pvosContext = pVosContext;
//Save the adapter context in global context for future.
((VosContextType*)(pVosContext))->pHDDContext = (v_VOID_t*)pHddCtx;
#ifdef ANI_BUS_TYPE_SDIO
// Set the private data for the device to our adapter.
libra_sdio_setprivdata (sdio_func_dev, pHddCtx);
atomic_set(&pHddCtx->sdio_claim_count, 0);
#endif // ANI_BUS_TYPE_SDIO
pHddCtx->parent_dev = dev;
init_completion(&pHddCtx->full_pwr_comp_var);
init_completion(&pHddCtx->standby_comp_var);
init_completion(&pHddCtx->req_bmps_comp_var);
hdd_list_init( &pHddCtx->hddAdapters, MAX_NUMBER_OF_ADAPTERS );
// Load all config first as TL config is needed during vos_open
pHddCtx->cfg_ini = (hdd_config_t*) kmalloc(sizeof(hdd_config_t), GFP_KERNEL);
if(pHddCtx->cfg_ini == NULL)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: Failed kmalloc hdd_config_t",__func__);
goto err_free_hdd_context;
}
vos_mem_zero(pHddCtx->cfg_ini, sizeof( hdd_config_t ));
// Read and parse the qcom_cfg.ini file
status = hdd_parse_config_ini( pHddCtx );
if ( VOS_STATUS_SUCCESS != status )
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: error parsing %s",
__func__, WLAN_INI_FILE);
goto err_config;
}
#ifdef CONFIG_CFG80211
/*
* cfg80211: Initialization and registration ...
*/
if (0 < wlan_hdd_cfg80211_register(dev, wiphy, pHddCtx->cfg_ini))
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: wlan_hdd_cfg80211_register return failure", __func__);
goto err_wiphy_reg;
}
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
// Update WDI trace levels based upon the cfg.ini
hdd_wdi_trace_enable(eWLAN_MODULE_DAL,
pHddCtx->cfg_ini->wdiTraceEnableDAL);
hdd_wdi_trace_enable(eWLAN_MODULE_DAL_CTRL,
pHddCtx->cfg_ini->wdiTraceEnableCTL);
hdd_wdi_trace_enable(eWLAN_MODULE_DAL_DATA,
pHddCtx->cfg_ini->wdiTraceEnableDAT);
hdd_wdi_trace_enable(eWLAN_MODULE_PAL,
pHddCtx->cfg_ini->wdiTraceEnablePAL);
#endif /* FEATURE_WLAN_INTEGRATED_SOC */
#ifdef ANI_MANF_DIAG
if(VOS_FTM_MODE == hdd_get_conparam())
{
if ( VOS_STATUS_SUCCESS != wlan_hdd_ftm_open(pHddCtx) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: wlan_hdd_ftm_open Failed",__func__);
goto err_free_hdd_context;
}
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: FTM driver loaded success fully",__func__);
return VOS_STATUS_SUCCESS;
}
#endif
//Open watchdog module
if(pHddCtx->cfg_ini->fIsLogpEnabled)
{
status = vos_watchdog_open(pVosContext,
&((VosContextType*)pVosContext)->vosWatchdog, sizeof(VosWatchdogContext));
if(!VOS_IS_STATUS_SUCCESS( status ))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: vos_watchdog_open failed",__func__);
#ifdef CONFIG_CFG80211
goto err_wiphy_reg;
#else
goto err_config;
#endif
}
}
pHddCtx->isLogpInProgress = FALSE;
vos_set_logp_in_progress(VOS_MODULE_ID_VOSS, FALSE);
#ifdef ANI_BUS_TYPE_SDIO
status = WLANBAL_Open(pHddCtx->pvosContext);
if(!VOS_IS_STATUS_SUCCESS(status))
{
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_ERROR,
"%s: Failed to open BAL",__func__);
goto err_wdclose;
}
#endif // ANI_BUS_TYPE_SDIO
status = vos_chipVoteOnXOBuffer(NULL, NULL, NULL);
if(!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Failed to configure 19.2 MHz Clock", __func__);
#ifdef ANI_BUS_TYPE_SDIO
goto err_balclose;
#else
goto err_wdclose;
#endif
}
#ifdef ANI_BUS_TYPE_SDIO
status = WLANSAL_Start(pHddCtx->pvosContext);
if (!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Failed to start SAL",__func__);
goto err_clkvote;
}
/* Start BAL */
status = WLANBAL_Start(pHddCtx->pvosContext);
if (!VOS_IS_STATUS_SUCCESS(status))
{
VOS_TRACE(VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_ERROR,
"%s: Failed to start BAL",__func__);
goto err_salstop;
}
#endif // ANI_BUS_TYPE_SDIO
#ifdef MSM_PLATFORM_7x30
/* FIXME: Volans 2.0 configuration. Reconfigure 1.3v SW supply to 1.3v. It will be configured to
* 1.4v in vos_ChipPowerup() routine above
*/
#endif
status = vos_open( &pVosContext, 0);
if ( !VOS_IS_STATUS_SUCCESS( status ))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: vos_open failed",__func__);
goto err_balstop;
}
/* Save the hal context in Adapter */
pHddCtx->hHal = (tHalHandle)vos_get_context( VOS_MODULE_ID_SME, pVosContext );
if ( NULL == pHddCtx->hHal )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: HAL context is null",__func__);
goto err_vosclose;
}
#ifdef FEATURE_WLAN_INTEGRATED_SOC
/* Vos preStart is calling */
/* vos preStart which does cfg download should be called before set sme config which accesses/sets some cfgs */
status = vos_preStart( pHddCtx->pvosContext );
if ( !VOS_IS_STATUS_SUCCESS( status ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: vos_preStart failed",__func__);
goto err_vosclose;
}
#endif
// Set the SME configuration parameters...
status = hdd_set_sme_config( pHddCtx );
if ( VOS_STATUS_SUCCESS != status )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: Failed hdd_set_sme_config",__func__);
goto err_vosclose;
}
//Initialize the WMM module
status = hdd_wmm_init(pHddCtx);
if (!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: hdd_wmm_init failed", __FUNCTION__);
goto err_vosclose;
}
#ifdef FEATURE_WLAN_INTEGRATED_SOC
/* In the integrated architecture we update the configuration from
the INI file and from NV before vOSS has been started so that
the final contents are available to send down to the cCPU */
// Apply the cfg.ini to cfg.dat
if (FALSE == hdd_update_config_dat(pHddCtx))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: config update failed",__func__ );
goto err_vosclose;
}
// Apply the NV to cfg.dat
/* Prima Update MAC address only at here */
if (VOS_STATUS_SUCCESS != hdd_update_config_from_nv(pHddCtx))
{
#ifdef WLAN_AUTOGEN_MACADDR_FEATURE
/* There was not a valid set of MAC Addresses in NV. See if the
default addresses were modified by the cfg.ini settings. If so,
we'll use them, but if not, we'll autogenerate a set of MAC
addresses based upon the device serial number */
static const v_MACADDR_t default_address =
{{0x00, 0x0A, 0xF5, 0x89, 0x89, 0xFF}};
unsigned int serialno;
int i;
serialno = wcnss_get_serial_number();
if ((0 != serialno) &&
(0 == memcmp(&default_address, &pHddCtx->cfg_ini->intfMacAddr[0],
sizeof(default_address))))
{
/* cfg.ini has the default address, invoke autogen logic */
/* MAC address has 3 bytes of OUI so we have a maximum of 3
bytes of the serial number that can be used to generate
the other 3 bytes of the MAC address. Mask off all but
the lower 3 bytes (this will also make sure we don't
overflow in the next step) */
serialno &= 0x00FFFFFF;
/* we need a unique address for each session */
serialno *= VOS_MAX_CONCURRENCY_PERSONA;
/* autogen all addresses */
for (i = 0; i < VOS_MAX_CONCURRENCY_PERSONA; i++)
{
/* start with the entire default address */
pHddCtx->cfg_ini->intfMacAddr[i] = default_address;
/* then replace the lower 3 bytes */
pHddCtx->cfg_ini->intfMacAddr[i].bytes[3] = (serialno >> 16) & 0xFF;
pHddCtx->cfg_ini->intfMacAddr[i].bytes[4] = (serialno >> 8) & 0xFF;
pHddCtx->cfg_ini->intfMacAddr[i].bytes[5] = serialno & 0xFF;
serialno++;
}
pr_info("wlan: Invalid MAC addresses in NV, autogenerated "
MAC_ADDRESS_STR,
MAC_ADDR_ARRAY(pHddCtx->cfg_ini->intfMacAddr[0].bytes));
}
else
#endif //WLAN_AUTOGEN_MACADDR_FEATURE
{
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: Invalid MAC address in NV, using MAC from ini file "
MAC_ADDRESS_STR, __func__,
MAC_ADDR_ARRAY(pHddCtx->cfg_ini->intfMacAddr[0].bytes));
}
}
{
eHalStatus halStatus;
// Set the MAC Address
// Currently this is used by HAL to add self sta. Remove this once self sta is added as part of session open.
halStatus = cfgSetStr( pHddCtx->hHal, WNI_CFG_STA_ID,
(v_U8_t *)&pHddCtx->cfg_ini->intfMacAddr[0],
sizeof( pHddCtx->cfg_ini->intfMacAddr[0]) );
if (!HAL_STATUS_SUCCESS( halStatus ))
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: Failed to set MAC Address. "
"HALStatus is %08d [x%08x]",__func__, halStatus, halStatus );
return VOS_STATUS_E_FAILURE;
}
}
#endif // FEATURE_WLAN_INTEGRATED_SOC
/*Start VOSS which starts up the SME/MAC/HAL modules and everything else
Note: Firmware image will be read and downloaded inside vos_start API */
status = vos_start( pHddCtx->pvosContext );
if ( !VOS_IS_STATUS_SUCCESS( status ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: vos_start failed",__func__);
goto err_vosclose;
}
/* Exchange capability info between Host and FW and also get versioning info from FW */
hdd_exchange_version_and_caps(pHddCtx);
status = hdd_post_voss_start_config( pHddCtx );
if ( !VOS_IS_STATUS_SUCCESS( status ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: hdd_post_voss_start_config failed",
__func__);
goto err_vosstop;
}
#ifdef WLAN_SOFTAP_FEATURE
if (VOS_STA_SAP_MODE == hdd_get_conparam())
{
pAdapter = hdd_open_adapter( pHddCtx, WLAN_HDD_SOFTAP, "softap.%d",
wlan_hdd_get_intf_addr(pHddCtx), FALSE );
}
else
{
#endif
pAdapter = hdd_open_adapter( pHddCtx, WLAN_HDD_INFRA_STATION, "wlan%d",
wlan_hdd_get_intf_addr(pHddCtx), FALSE );
if (pAdapter != NULL)
{
#ifdef WLAN_FEATURE_P2P
if ( pHddCtx->cfg_ini->isP2pDeviceAddrAdministrated )
{
vos_mem_copy( pHddCtx->p2pDeviceAddress.bytes,
pHddCtx->cfg_ini->intfMacAddr[0].bytes,
sizeof(tSirMacAddr));
/* Generate the P2P Device Address. This consists of the device's
* primary MAC address with the locally administered bit set.
*/
pHddCtx->p2pDeviceAddress.bytes[0] |= 0x02;
}
else
{
tANI_U8* p2p_dev_addr = wlan_hdd_get_intf_addr(pHddCtx);
if (p2p_dev_addr != NULL)
{
vos_mem_copy(&pHddCtx->p2pDeviceAddress.bytes[0],
p2p_dev_addr, VOS_MAC_ADDR_SIZE);
}
else
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: Failed to allocate mac_address for p2p_device",
__FUNCTION__);
goto err_close_adapter;
}
}
pP2pAdapter = hdd_open_adapter( pHddCtx, WLAN_HDD_P2P_DEVICE, "p2p%d",
&pHddCtx->p2pDeviceAddress.bytes[0], FALSE );
if ( NULL == pP2pAdapter )
{
hddLog(VOS_TRACE_LEVEL_FATAL,
"%s: Failed to do hdd_open_adapter for P2P Device Interface",
__FUNCTION__);
goto err_close_adapter;
}
#endif
}
#ifdef WLAN_SOFTAP_FEATURE
}
#endif
if( pAdapter == NULL )
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: hdd_open_adapter failed",__func__);
#ifdef ANI_BUS_TYPE_SDIO
goto err_balstop;
#else
goto err_clkvote;
#endif
}
#ifdef WLAN_BTAMP_FEATURE
vStatus = WLANBAP_Open(pVosContext);
if(!VOS_IS_STATUS_SUCCESS(vStatus))
{
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_ERROR,
"%s: Failed to open BAP",__func__);
goto err_close_adapter;
}
vStatus = BSL_Init(pVosContext);
if(!VOS_IS_STATUS_SUCCESS(vStatus))
{
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_ERROR,
"%s: Failed to Init BSL",__func__);
goto err_bap_close;
}
vStatus = WLANBAP_Start(pVosContext);
if (!VOS_IS_STATUS_SUCCESS(vStatus))
{
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_ERROR,
"%s: Failed to start TL",__func__);
goto err_bap_close;
}
pConfig = pHddCtx->cfg_ini;
btAmpConfig.ucPreferredChannel = pConfig->preferredChannel;
status = WLANBAP_SetConfig(&btAmpConfig);
#endif //WLAN_BTAMP_FEATURE
#ifdef FEATURE_WLAN_SCAN_PNO
/*SME must send channel update configuration to RIVA*/
sme_UpdateChannelConfig(pHddCtx->hHal);
#endif
#ifdef FEATURE_WLAN_INTEGRATED_SOC
/* Register with platform driver as client for Suspend/Resume */
status = hddRegisterPmOps(pHddCtx);
if ( !VOS_IS_STATUS_SUCCESS( status ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: hddRegisterPmOps failed",__func__);
#ifdef WLAN_BTAMP_FEATURE
goto err_bap_stop;
#else
goto err_close_adapter;
#endif //WLAN_BTAMP_FEATURE
}
/* Register TM level change handler function to the platform */
status = hddDevTmRegisterNotifyCallback(pHddCtx);
if ( !VOS_IS_STATUS_SUCCESS( status ) )
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: hddDevTmRegisterNotifyCallback failed",__func__);
goto err_unregister_pmops;
}
#endif
/* register for riva power on lock to platform driver */
if (req_riva_power_on_lock("wlan"))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: req riva power on lock failed",
__func__);
goto err_unregister_pmops;
}
#ifdef CONFIG_HAS_EARLYSUSPEND
// Register suspend/resume callbacks
if(pHddCtx->cfg_ini->nEnableSuspend)
{
register_wlan_suspend();
}
#endif
// register net device notifier for device change notification
ret = register_netdevice_notifier(&hdd_netdev_notifier);
if(ret < 0)
{
hddLog(VOS_TRACE_LEVEL_ERROR,"%s: register_netdevice_notifier failed",__func__);
goto err_free_power_on_lock;
}
//Initialize the nlink service
if(nl_srv_init() != 0)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%S: nl_srv_init failed",__func__);
goto err_reg_netdev;
}
//Initialize the BTC service
if(btc_activate_service(pHddCtx) != 0)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: btc_activate_service failed",__func__);
goto err_nl_srv;
}
#ifdef PTT_SOCK_SVC_ENABLE
//Initialize the PTT service
if(ptt_sock_activate_svc(pHddCtx) != 0)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: ptt_sock_activate_svc failed",__func__);
goto err_nl_srv;
}
#endif
//Initialize the WoWL service
if(!hdd_init_wowl(pHddCtx))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: hdd_init_wowl failed",__func__);
goto err_nl_srv;
}
#ifdef CONFIG_HAS_EARLYSUSPEND
hdd_register_mcast_bcast_filter(pHddCtx);
#endif
#ifdef CONFIG_CFG80211
#ifdef WLAN_SOFTAP_FEATURE
if (VOS_STA_SAP_MODE != hdd_get_conparam())
#endif
{
wlan_hdd_cfg80211_post_voss_start(pP2pAdapter);
}
#endif
mutex_init(&pHddCtx->sap_lock);
pHddCtx->isLoadUnloadInProgress = FALSE;
#ifdef WLAN_FEATURE_HOLD_RX_WAKELOCK
/* Initialize the wake lcok */
wake_lock_init(&pHddCtx->rx_wake_lock,
WAKE_LOCK_SUSPEND,
"qcom_rx_wakelock");
#endif
vos_event_init(&pAdapter->scan_info.scan_finished_event);
pAdapter->scan_info.scan_pending_option = WEXT_SCAN_PENDING_GIVEUP;
vos_set_load_unload_in_progress(VOS_MODULE_ID_VOSS, FALSE);
hdd_allow_suspend();
// Initialize the restart logic
wlan_hdd_restart_init(pHddCtx);
goto success;
err_nl_srv:
nl_srv_exit();
err_reg_netdev:
unregister_netdevice_notifier(&hdd_netdev_notifier);
err_free_power_on_lock:
free_riva_power_on_lock("wlan");
err_unregister_pmops:
hddDevTmUnregisterNotifyCallback(pHddCtx);
hddDeregisterPmOps(pHddCtx);
#ifdef WLAN_BTAMP_FEATURE
err_bap_stop:
WLANBAP_Stop(pVosContext);
#endif
#ifdef WLAN_BTAMP_FEATURE
err_bap_close:
WLANBAP_Close(pVosContext);
#endif
err_close_adapter:
hdd_close_all_adapters( pHddCtx );
err_vosstop:
vos_stop(pVosContext);
err_vosclose:
status = vos_sched_close( pVosContext );
if (!VOS_IS_STATUS_SUCCESS(status)) {
VOS_TRACE( VOS_MODULE_ID_VOSS, VOS_TRACE_LEVEL_FATAL,
"%s: Failed to close VOSS Scheduler", __func__);
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( status ) );
}
vos_close(pVosContext );
err_balstop:
#ifdef ANI_BUS_TYPE_SDIO
#ifndef ANI_MANF_DIAG
wlan_hdd_enable_deepsleep(pHddCtx->pvosContext);
#endif
WLANBAL_Stop(pHddCtx->pvosContext);
WLANBAL_SuspendChip(pHddCtx->pvosContext);
#endif
#ifdef ANI_BUS_TYPE_SDIO
err_salstop:
WLANSAL_Stop(pHddCtx->pvosContext);
#endif
err_clkvote:
vos_chipVoteOffXOBuffer(NULL, NULL, NULL);
#ifdef ANI_BUS_TYPE_SDIO
err_balclose:
WLANBAL_Close(pHddCtx->pvosContext);
#endif // ANI_BUS_TYPE_SDIO
err_wdclose:
if(pHddCtx->cfg_ini->fIsLogpEnabled)
vos_watchdog_close(pVosContext);
#ifdef CONFIG_CFG80211
err_wiphy_reg:
wiphy_unregister(wiphy) ;
#endif
err_config:
kfree(pHddCtx->cfg_ini);
pHddCtx->cfg_ini= NULL;
err_free_hdd_context:
hdd_allow_suspend();
#ifdef CONFIG_CFG80211
wiphy_free(wiphy) ;
//kfree(wdev) ;
#else
vos_mem_free( pHddCtx );
#endif
VOS_BUG(1);
return -1;
success:
EXIT();
return 0;
}
/**---------------------------------------------------------------------------
\brief hdd_driver_init() - Core Driver Init Function
This is the driver entry point - called in different timeline depending
on whether the driver is statically or dynamically linked
\param - None
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
static int hdd_driver_init( void)
{
VOS_STATUS status;
v_CONTEXT_t pVosContext = NULL;
#ifdef ANI_BUS_TYPE_SDIO
struct sdio_func *sdio_func_dev = NULL;
unsigned int attempts = 0;
#endif // ANI_BUS_TYPE_SDIO
struct device *dev = NULL;
int ret_status = 0;
ENTER();
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,5))
wake_lock_init(&wlan_wake_lock, WAKE_LOCK_SUSPEND, "wlan");
#endif
pr_info("%s: loading driver v%s\n", WLAN_MODULE_NAME,
QWLAN_VERSIONSTR TIMER_MANAGER_STR MEMORY_DEBUG_STR);
//Power Up Libra WLAN card first if not already powered up
status = vos_chipPowerUp(NULL,NULL,NULL);
if (!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Libra WLAN not Powered Up. "
"exiting", __func__);
return -1;
}
#ifdef ANI_BUS_TYPE_SDIO
//SDIO Polling should be turned on for card detection. When using Android Wi-Fi GUI
//users need not trigger SDIO polling explicitly. However when loading drivers via
//command line (Adb shell), users must turn on SDIO polling prior to loading WLAN.
do {
sdio_func_dev = libra_getsdio_funcdev();
if (NULL == sdio_func_dev) {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Libra WLAN not detected yet.",__func__);
attempts++;
}
else {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Libra WLAN detecton succeeded",__func__);
dev = &sdio_func_dev->dev;
break;
}
if(attempts == 7)
break;
msleep(250);
}while (attempts < 7);
//Retry to detect the card again by Powering Down the chip and Power up the chip
//again. This retry is done to recover from CRC Error
if (NULL == sdio_func_dev) {
attempts = 0;
//Vote off any PMIC voltage supplies
vos_chipPowerDown(NULL, NULL, NULL);
msleep(1000);
//Power Up Libra WLAN card first if not already powered up
status = vos_chipPowerUp(NULL,NULL,NULL);
if (!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Retry Libra WLAN not Powered Up. "
"exiting", __func__);
return -1;
}
do {
sdio_func_dev = libra_getsdio_funcdev();
if (NULL == sdio_func_dev) {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Retry Libra WLAN not detected yet.",__func__);
attempts++;
}
else {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: Retry Libra WLAN detecton succeeded",__func__);
dev = &sdio_func_dev->dev;
break;
}
if(attempts == 2)
break;
msleep(1000);
}while (attempts < 3);
}
#endif // ANI_BUS_TYPE_SDIO
#ifdef ANI_BUS_TYPE_PCI
dev = wcnss_wlan_get_device();
#endif // ANI_BUS_TYPE_PCI
#ifdef ANI_BUS_TYPE_PLATFORM
dev = wcnss_wlan_get_device();
#endif // ANI_BUS_TYPE_PLATFORM
do {
if (NULL == dev) {
hddLog(VOS_TRACE_LEVEL_FATAL, "%s: WLAN device not found!!",__func__);
ret_status = -1;
break;
}
#ifdef MEMORY_DEBUG
vos_mem_init();
#endif
#ifdef TIMER_MANAGER
vos_timer_manager_init();
#endif
/* Preopen VOSS so that it is ready to start at least SAL */
status = vos_preOpen(&pVosContext);
if (!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: Failed to preOpen VOSS", __func__);
ret_status = -1;
break;
}
#ifdef ANI_BUS_TYPE_SDIO
/* Now Open SAL */
status = WLANSAL_Open(pVosContext, 0);
if(!VOS_IS_STATUS_SUCCESS(status))
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: Failed to open SAL", __func__);
/* If unable to open, cleanup and return failure */
vos_preClose( &pVosContext );
ret_status = -1;
break;
}
#endif // ANI_BUS_TYPE_SDIO
#ifndef MODULE
/* For statically linked driver, call hdd_set_conparam to update curr_con_mode
*/
hdd_set_conparam((v_UINT_t)con_mode);
#endif
// Call our main init function
if(hdd_wlan_startup(dev)) {
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: WLAN Driver Initialization failed",
__func__);
#ifdef ANI_BUS_TYPE_SDIO
WLANSAL_Close(pVosContext);
#endif // ANI_BUS_TYPE_SDIO
vos_preClose( &pVosContext );
ret_status = -1;
break;
}
/* Cancel the vote for XO Core ON
* This is done here for safety purposes in case we re-initialize without turning
* it OFF in any error scenario.
*/
hddLog(VOS_TRACE_LEVEL_ERROR, "In module init: Ensure Force XO Core is OFF"
" when WLAN is turned ON so Core toggles"
" unless we enter PS\n");
if (vos_chipVoteXOCore(NULL, NULL, NULL, VOS_FALSE) != VOS_STATUS_SUCCESS)
{
hddLog(VOS_TRACE_LEVEL_ERROR, "Could not cancel XO Core ON vote. Not returning failure."
" Power consumed will be high\n");
}
} while (0);
if (0 != ret_status)
{
//Assert Deep sleep signal now to put Libra HW in lowest power state
status = vos_chipAssertDeepSleep( NULL, NULL, NULL );
VOS_ASSERT( VOS_IS_STATUS_SUCCESS( status) );
//Vote off any PMIC voltage supplies
vos_chipPowerDown(NULL, NULL, NULL);
#ifdef TIMER_MANAGER
vos_timer_exit();
#endif
#ifdef MEMORY_DEBUG
vos_mem_exit();
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,5))
wake_lock_destroy(&wlan_wake_lock);
#endif
pr_err("%s: driver load failure\n", WLAN_MODULE_NAME);
}
else
{
//Send WLAN UP indication to Nlink Service
send_btc_nlink_msg(WLAN_MODULE_UP_IND, 0);
pr_info("%s: driver loaded\n", WLAN_MODULE_NAME);
}
EXIT();
return ret_status;
}
/**---------------------------------------------------------------------------
\brief hdd_module_init() - Init Function
This is the driver entry point (invoked when module is loaded using insmod)
\param - None
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
#ifdef MODULE
static int __init hdd_module_init ( void)
{
return hdd_driver_init();
}
#else /* #ifdef MODULE */
static int __init hdd_module_init ( void)
{
/* Driver initialization is delayed to fwpath_changed_handler */
return 0;
}
#endif /* #ifdef MODULE */
/**---------------------------------------------------------------------------
\brief hdd_driver_exit() - Exit function
This is the driver exit point (invoked when module is unloaded using rmmod
or con_mode was changed by userspace)
\param - None
\return - None
--------------------------------------------------------------------------*/
static void hdd_driver_exit(void)
{
hdd_context_t *pHddCtx = NULL;
v_CONTEXT_t pVosContext = NULL;
pr_info("%s: unloading driver v%s\n", WLAN_MODULE_NAME, QWLAN_VERSIONSTR);
//Get the global vos context
pVosContext = vos_get_global_context(VOS_MODULE_ID_SYS, NULL);
if(!pVosContext)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: Global VOS context is Null", __func__);
goto done;
}
//Get the HDD context.
pHddCtx = (hdd_context_t *)vos_get_context(VOS_MODULE_ID_HDD, pVosContext );
if(!pHddCtx)
{
hddLog(VOS_TRACE_LEVEL_FATAL,"%s: module exit called before probe",__func__);
}
else
{
/* module exit should never proceed if SSR is not completed */
while(isWDresetInProgress()){
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL, "%s:SSR in Progress; block rmmod for 1 second!!!",__func__);
msleep(1000);
}
pHddCtx->isLoadUnloadInProgress = TRUE;
vos_set_load_unload_in_progress(VOS_MODULE_ID_VOSS, TRUE);
//Do all the cleanup before deregistering the driver
hdd_wlan_exit(pHddCtx);
}
#ifdef ANI_BUS_TYPE_SDIO
WLANSAL_Close(pVosContext);
#endif // ANI_BUS_TYPE_SDIO
vos_preClose( &pVosContext );
#ifdef TIMER_MANAGER
vos_timer_exit();
#endif
#ifdef MEMORY_DEBUG
vos_mem_exit();
#endif
done:
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,5))
wake_lock_destroy(&wlan_wake_lock);
#endif
pr_info("%s: driver unloaded\n", WLAN_MODULE_NAME);
}
/**---------------------------------------------------------------------------
\brief hdd_module_exit() - Exit function
This is the driver exit point (invoked when module is unloaded using rmmod)
\param - None
\return - None
--------------------------------------------------------------------------*/
static void __exit hdd_module_exit(void)
{
hdd_driver_exit();
}
#ifdef MODULE
static int fwpath_changed_handler(const char *kmessage,
struct kernel_param *kp)
{
/* nothing to do when driver is DLKM */
return 0;
}
static int con_mode_handler(const char *kmessage,
struct kernel_param *kp)
{
return 0;
}
#else /* #ifdef MODULE */
/**---------------------------------------------------------------------------
\brief fwpath_changed_handler() - Handler Function
This is the driver entry point
- delayed driver initialization when driver is statically linked
- invoked when module parameter fwpath is modified from userpspace to signal
initializing the WLAN driver
\return - 0 for success, non zero for failure
--------------------------------------------------------------------------*/
static int fwpath_changed_handler(const char *kmessage,
struct kernel_param *kp)
{
int ret_status;
if (!wlan_hdd_inited) {
ret_status = hdd_driver_init();
wlan_hdd_inited = ret_status ? 0 : 1;
return ret_status;
}
hdd_driver_exit();
msleep(200);
ret_status = hdd_driver_init();
wlan_hdd_inited = ret_status ? 0 : 1;
return ret_status;
}
/**---------------------------------------------------------------------------
\brief con_mode_handler() -
Handler function for module param con_mode when it is changed by userspace
Dynamically linked - do nothing
Statically linked - exit and init driver, as in rmmod and insmod
\param -
\return -
--------------------------------------------------------------------------*/
static int con_mode_handler(const char *kmessage,
struct kernel_param *kp)
{
int ret = param_set_int(kmessage, kp);
if (ret)
return ret;
return fwpath_changed_handler(kmessage, kp);
}
#endif /* #ifdef MODULE */
/**---------------------------------------------------------------------------
\brief hdd_get_conparam() -
This is the driver exit point (invoked when module is unloaded using rmmod)
\param - None
\return - tVOS_CON_MODE
--------------------------------------------------------------------------*/
tVOS_CON_MODE hdd_get_conparam ( void )
{
#ifdef MODULE
return (tVOS_CON_MODE)con_mode;
#else
return (tVOS_CON_MODE)curr_con_mode;
#endif
}
void hdd_set_conparam ( v_UINT_t newParam )
{
con_mode = newParam;
#ifndef MODULE
curr_con_mode = con_mode;
#endif
}
/**---------------------------------------------------------------------------
\brief hdd_softap_sta_deauth() - function
This to take counter measure to handle deauth req from HDD
\param - pAdapter - Pointer to the HDD
\param - enable - boolean value
\return - None
--------------------------------------------------------------------------*/
void hdd_softap_sta_deauth(hdd_adapter_t *pAdapter, v_U8_t *pDestMacAddress)
{
v_U8_t STAId;
v_CONTEXT_t pVosContext = (WLAN_HDD_GET_CTX(pAdapter))->pvosContext;
#ifdef FEATURE_WLAN_NON_INTEGRATED_SOC
tHalHandle hHalHandle;
#endif
ENTER();
hddLog( LOGE, "hdd_softap_sta_deauth:(0x%x, false)", (WLAN_HDD_GET_CTX(pAdapter))->pvosContext);
//Ignore request to deauth bcmc station
if( pDestMacAddress[0] & 0x1 )
return;
WLANSAP_DeauthSta(pVosContext,pDestMacAddress);
/*Get the Station ID*/
#ifdef FEATURE_WLAN_NON_INTEGRATED_SOC
hHalHandle = (tHalHandle ) vos_get_context(VOS_MODULE_ID_HAL, pVosContext);
if (eHAL_STATUS_SUCCESS ==
halTable_FindStaidByAddr(hHalHandle, (tANI_U8 *)pDestMacAddress,
&STAId))
{
hdd_softap_DeregisterSTA(pAdapter, STAId);
}
#else
if (VOS_STATUS_SUCCESS ==
hdd_softap_GetStaId(pAdapter, (v_MACADDR_t *)pDestMacAddress,
&STAId))
{
hdd_softap_DeregisterSTA(pAdapter, STAId);
}
#endif
EXIT();
}
/**---------------------------------------------------------------------------
\brief hdd_softap_sta_disassoc() - function
This to take counter measure to handle deauth req from HDD
\param - pAdapter - Pointer to the HDD
\param - enable - boolean value
\return - None
--------------------------------------------------------------------------*/
void hdd_softap_sta_disassoc(hdd_adapter_t *pAdapter,v_U8_t *pDestMacAddress)
{
v_CONTEXT_t pVosContext = (WLAN_HDD_GET_CTX(pAdapter))->pvosContext;
ENTER();
hddLog( LOGE, "hdd_softap_sta_disassoc:(0x%x, false)", (WLAN_HDD_GET_CTX(pAdapter))->pvosContext);
//Ignore request to disassoc bcmc station
if( pDestMacAddress[0] & 0x1 )
return;
WLANSAP_DisassocSta(pVosContext,pDestMacAddress);
}
void hdd_softap_tkip_mic_fail_counter_measure(hdd_adapter_t *pAdapter,v_BOOL_t enable)
{
v_CONTEXT_t pVosContext = (WLAN_HDD_GET_CTX(pAdapter))->pvosContext;
ENTER();
hddLog( LOGE, "hdd_softap_tkip_mic_fail_counter_measure:(0x%x, false)", (WLAN_HDD_GET_CTX(pAdapter))->pvosContext);
WLANSAP_SetCounterMeasure(pVosContext, (v_BOOL_t)enable);
}
/**---------------------------------------------------------------------------
*
* \brief hdd_get__concurrency_mode() -
*
*
* \param - None
*
* \return - CONCURRENCY MODE
*
* --------------------------------------------------------------------------*/
tVOS_CONCURRENCY_MODE hdd_get_concurrency_mode ( void )
{
v_CONTEXT_t pVosContext = vos_get_global_context( VOS_MODULE_ID_HDD, NULL );
hdd_context_t *pHddCtx;
if (NULL != pVosContext)
{
pHddCtx = vos_get_context( VOS_MODULE_ID_HDD, pVosContext);
if (NULL != pHddCtx)
{
return (tVOS_CONCURRENCY_MODE)pHddCtx->concurrency_mode;
}
}
/* we are in an invalid state :( */
hddLog(LOGE, "%s: Invalid context", __FUNCTION__);
return VOS_STA;
}
/* Decide whether to allow/not the apps power collapse.
* Allow apps power collapse if we are in connected state.
* if not, allow only if we are in IMPS */
v_BOOL_t hdd_is_apps_power_collapse_allowed(hdd_context_t* pHddCtx)
{
tPmcState pmcState = pmcGetPmcState(pHddCtx->hHal);
hdd_config_t *pConfig = pHddCtx->cfg_ini;
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
hdd_adapter_t *pAdapter = NULL;
VOS_STATUS status;
#ifdef WLAN_SOFTAP_FEATURE
if (VOS_STA_SAP_MODE == hdd_get_conparam())
return TRUE;
#endif
/*loop through all adapters. TBD fix for Concurrency */
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
while ( NULL != pAdapterNode && VOS_STATUS_SUCCESS == status )
{
pAdapter = pAdapterNode->pAdapter;
if ( (WLAN_HDD_INFRA_STATION == pAdapter->device_mode)
|| (WLAN_HDD_P2P_CLIENT == pAdapter->device_mode) )
{
if ((pConfig->fIsImpsEnabled || pConfig->fIsBmpsEnabled)
&& (pmcState != IMPS && pmcState != BMPS
&& pmcState != STOPPED && pmcState != STANDBY))
{
return FALSE;
}
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
}
return TRUE;
}
void wlan_hdd_set_concurrency_mode(hdd_context_t *pHddCtx, tVOS_CON_MODE mode)
{
switch(mode)
{
case WLAN_HDD_INFRA_STATION:
#ifdef WLAN_FEATURE_P2P
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_GO:
#endif
case WLAN_HDD_SOFTAP:
pHddCtx->concurrency_mode |= (1 << mode);
pHddCtx->no_of_sessions[mode]++;
break;
default:
break;
}
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO, "%s: concurrency_mode = 0x%x NumberofSessions for mode %d = %d",
__func__,pHddCtx->concurrency_mode,mode,pHddCtx->no_of_sessions[mode]);
}
void wlan_hdd_clear_concurrency_mode(hdd_context_t *pHddCtx, tVOS_CON_MODE mode)
{
switch(mode)
{
case WLAN_HDD_INFRA_STATION:
#ifdef WLAN_FEATURE_P2P
case WLAN_HDD_P2P_CLIENT:
case WLAN_HDD_P2P_GO:
#endif
case WLAN_HDD_SOFTAP:
pHddCtx->no_of_sessions[mode]--;
if (!(pHddCtx->no_of_sessions[mode]))
pHddCtx->concurrency_mode &= (~(1 << mode));
break;
default:
break;
}
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_INFO, "%s: concurrency_mode = 0x%x NumberofSessions for mode %d = %d",
__func__,pHddCtx->concurrency_mode,mode,pHddCtx->no_of_sessions[mode]);
}
/**---------------------------------------------------------------------------
*
* \brief wlan_hdd_restart_init
*
* This function initalizes restart timer/flag. An internal function.
*
* \param - pHddCtx
*
* \return - None
*
* --------------------------------------------------------------------------*/
static void wlan_hdd_restart_init(hdd_context_t *pHddCtx)
{
/* Initialize */
pHddCtx->hdd_restart_retries = 0;
atomic_set(&pHddCtx->isRestartInProgress, 0);
vos_timer_init(&pHddCtx->hdd_restart_timer,
VOS_TIMER_TYPE_SW,
wlan_hdd_restart_timer_cb,
pHddCtx);
}
/**---------------------------------------------------------------------------
*
* \brief wlan_hdd_restart_deinit
*
* This function cleans up the resources used. An internal function.
*
* \param - pHddCtx
*
* \return - None
*
* --------------------------------------------------------------------------*/
static void wlan_hdd_restart_deinit(hdd_context_t* pHddCtx)
{
VOS_STATUS vos_status;
/* Block any further calls */
atomic_set(&pHddCtx->isRestartInProgress, 1);
/* Cleanup */
vos_status = vos_timer_stop( &pHddCtx->hdd_restart_timer );
if (!VOS_IS_STATUS_SUCCESS(vos_status))
hddLog(LOGE, FL("Failed to stop HDD restart timer\n"));
vos_status = vos_timer_destroy(&pHddCtx->hdd_restart_timer);
if (!VOS_IS_STATUS_SUCCESS(vos_status))
hddLog(LOGE, FL("Failed to destroy HDD restart timer\n"));
}
/**---------------------------------------------------------------------------
*
* \brief wlan_hdd_framework_restart
*
* This function uses a cfg80211 API to start a framework initiated WLAN
* driver module unload/load.
*
* Also this API keep retrying (WLAN_HDD_RESTART_RETRY_MAX_CNT).
*
*
* \param - pHddCtx
*
* \return - VOS_STATUS_SUCCESS: Success
* VOS_STATUS_E_EMPTY: Adapter is Empty
* VOS_STATUS_E_NOMEM: No memory
* --------------------------------------------------------------------------*/
static VOS_STATUS wlan_hdd_framework_restart(hdd_context_t *pHddCtx)
{
VOS_STATUS status = VOS_STATUS_SUCCESS;
hdd_adapter_list_node_t *pAdapterNode = NULL, *pNext = NULL;
int len = (sizeof (struct ieee80211_mgmt));
struct ieee80211_mgmt *mgmt = NULL;
/* Prepare the DEAUTH managment frame with reason code */
mgmt = kzalloc(len, GFP_KERNEL);
if(mgmt == NULL)
{
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"%s: memory allocatoin failed (%d bytes)", __func__, len);
return VOS_STATUS_E_NOMEM;
}
mgmt->u.deauth.reason_code = WLAN_REASON_DISASSOC_LOW_ACK;
/* Iterate over all adapters/devices */
status = hdd_get_front_adapter ( pHddCtx, &pAdapterNode );
do
{
if( (status == VOS_STATUS_SUCCESS) &&
pAdapterNode &&
pAdapterNode->pAdapter)
{
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_FATAL,
"restarting the driver(intf:\'%s\' mode:%d :try %d)",
pAdapterNode->pAdapter->dev->name,
pAdapterNode->pAdapter->device_mode,
pHddCtx->hdd_restart_retries + 1);
/*
* CFG80211 event to restart the driver
*
* 'cfg80211_send_unprot_deauth' sends a
* NL80211_CMD_UNPROT_DEAUTHENTICATE event to supplicant at any state
* of SME(Linux Kernel) state machine.
*
* Reason code WLAN_REASON_DISASSOC_LOW_ACK is currently used to restart
* the driver.
*
*/
cfg80211_send_unprot_deauth(pAdapterNode->pAdapter->dev, (u_int8_t*)mgmt, len );
}
status = hdd_get_next_adapter ( pHddCtx, pAdapterNode, &pNext );
pAdapterNode = pNext;
} while((NULL != pAdapterNode) && (VOS_STATUS_SUCCESS == status));
/* Free the allocated management frame */
kfree(mgmt);
/* Retry until we unload or reach max count */
if(++pHddCtx->hdd_restart_retries < WLAN_HDD_RESTART_RETRY_MAX_CNT)
vos_timer_start(&pHddCtx->hdd_restart_timer, WLAN_HDD_RESTART_RETRY_DELAY_MS);
return status;
}
/**---------------------------------------------------------------------------
*
* \brief wlan_hdd_restart_timer_cb
*
* Restart timer callback. An internal function.
*
* \param - User data:
*
* \return - None
*
* --------------------------------------------------------------------------*/
void wlan_hdd_restart_timer_cb(v_PVOID_t usrDataForCallback)
{
hdd_context_t *pHddCtx = usrDataForCallback;
wlan_hdd_framework_restart(pHddCtx);
return;
}
/**---------------------------------------------------------------------------
*
* \brief wlan_hdd_restart_driver
*
* This function sends an event to supplicant to restart the WLAN driver.
*
* This function is called from vos_wlanRestart.
*
* \param - pHddCtx
*
* \return - VOS_STATUS_SUCCESS: Success
* VOS_STATUS_E_EMPTY: Adapter is Empty
* VOS_STATUS_E_ALREADY: Request already in progress
* --------------------------------------------------------------------------*/
VOS_STATUS wlan_hdd_restart_driver(hdd_context_t *pHddCtx)
{
VOS_STATUS status = VOS_STATUS_SUCCESS;
/* A tight check to make sure reentrancy */
if(atomic_xchg(&pHddCtx->isRestartInProgress, 1))
{
VOS_TRACE(VOS_MODULE_ID_HDD, VOS_TRACE_LEVEL_WARN,
"%s: WLAN restart is already in progress", __func__);
return VOS_STATUS_E_ALREADY;
}
/* Restart API */
status = wlan_hdd_framework_restart(pHddCtx);
return status;
}
//Register the module init/exit functions
module_init(hdd_module_init);
module_exit(hdd_module_exit);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Qualcomm Atheros, Inc.");
MODULE_DESCRIPTION("WLAN HOST DEVICE DRIVER");
module_param_call(con_mode, con_mode_handler, param_get_int, &con_mode,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
module_param_call(fwpath, fwpath_changed_handler, param_get_string, fwpath,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
| gpl-2.0 |
DarrenRainey/linux-1 | arch/m68k/68360/config.c | 358 | 4364 | /*
* config.c - non-mmu 68360 platform initialization code
*
* Copyright (c) 2000 Michael Leslie <mleslie@lineo.com>
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne <jeff@uclinux.org>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <stdarg.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/setup.h>
#include <asm/pgtable.h>
#include <asm/machdep.h>
#include <asm/m68360.h>
#ifdef CONFIG_UCQUICC
#include <asm/bootstd.h>
#endif
extern void m360_cpm_reset(void);
// Mask to select if the PLL prescaler is enabled.
#define MCU_PREEN ((unsigned short)(0x0001 << 13))
#if defined(CONFIG_UCQUICC)
#define OSCILLATOR (unsigned long int)33000000
#endif
static irq_handler_t timer_interrupt;
unsigned long int system_clock;
extern QUICC *pquicc;
/* TODO DON"T Hard Code this */
/* calculate properly using the right PLL and prescaller */
// unsigned int system_clock = 33000000l;
extern unsigned long int system_clock; //In kernel setup.c
static irqreturn_t hw_tick(int irq, void *dummy)
{
/* Reset Timer1 */
/* TSTAT &= 0; */
pquicc->timer_ter1 = 0x0002; /* clear timer event */
return timer_interrupt(irq, dummy);
}
static struct irqaction m68360_timer_irq = {
.name = "timer",
.flags = IRQF_TIMER,
.handler = hw_tick,
};
void hw_timer_init(irq_handler_t handler)
{
unsigned char prescaler;
unsigned short tgcr_save;
#if 0
/* Restart mode, Enable int, 32KHz, Enable timer */
TCTL = TCTL_OM | TCTL_IRQEN | TCTL_CLKSOURCE_32KHZ | TCTL_TEN;
/* Set prescaler (Divide 32KHz by 32)*/
TPRER = 31;
/* Set compare register 32Khz / 32 / 10 = 100 */
TCMP = 10;
request_irq(IRQ_MACHSPEC | 1, timer_routine, 0, "timer", NULL);
#endif
/* General purpose quicc timers: MC68360UM p7-20 */
/* Set up timer 1 (in [1..4]) to do 100Hz */
tgcr_save = pquicc->timer_tgcr & 0xfff0;
pquicc->timer_tgcr = tgcr_save; /* stop and reset timer 1 */
/* pquicc->timer_tgcr |= 0x4444; */ /* halt timers when FREEZE (ie bdm freeze) */
prescaler = 8;
pquicc->timer_tmr1 = 0x001a | /* or=1, frr=1, iclk=01b */
(unsigned short)((prescaler - 1) << 8);
pquicc->timer_tcn1 = 0x0000; /* initial count */
/* calculate interval for 100Hz based on the _system_clock: */
pquicc->timer_trr1 = (system_clock/ prescaler) / HZ; /* reference count */
pquicc->timer_ter1 = 0x0003; /* clear timer events */
timer_interrupt = handler;
/* enable timer 1 interrupt in CIMR */
setup_irq(CPMVEC_TIMER1, &m68360_timer_irq);
/* Start timer 1: */
tgcr_save = (pquicc->timer_tgcr & 0xfff0) | 0x0001;
pquicc->timer_tgcr = tgcr_save;
}
void BSP_reset (void)
{
local_irq_disable();
asm volatile (
"moveal #_start, %a0;\n"
"moveb #0, 0xFFFFF300;\n"
"moveal 0(%a0), %sp;\n"
"moveal 4(%a0), %a0;\n"
"jmp (%a0);\n"
);
}
unsigned char *scc1_hwaddr;
static int errno;
#if defined (CONFIG_UCQUICC)
_bsc0(char *, getserialnum)
_bsc1(unsigned char *, gethwaddr, int, a)
_bsc1(char *, getbenv, char *, a)
#endif
void __init config_BSP(char *command, int len)
{
unsigned char *p;
m360_cpm_reset();
/* Calculate the real system clock value. */
{
unsigned int local_pllcr = (unsigned int)(pquicc->sim_pllcr);
if( local_pllcr & MCU_PREEN ) // If the prescaler is dividing by 128
{
int mf = (int)(pquicc->sim_pllcr & 0x0fff);
system_clock = (OSCILLATOR / 128) * (mf + 1);
}
else
{
int mf = (int)(pquicc->sim_pllcr & 0x0fff);
system_clock = (OSCILLATOR) * (mf + 1);
}
}
printk(KERN_INFO "\n68360 QUICC support (C) 2000 Lineo Inc.\n");
#if defined(CONFIG_UCQUICC) && 0
printk(KERN_INFO "uCquicc serial string [%s]\n",getserialnum());
p = scc1_hwaddr = gethwaddr(0);
printk(KERN_INFO "uCquicc hwaddr %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
p[0], p[1], p[2], p[3], p[4], p[5]);
p = getbenv("APPEND");
if (p)
strcpy(p,command);
else
command[0] = 0;
#else
scc1_hwaddr = "\00\01\02\03\04\05";
#endif
mach_reset = BSP_reset;
}
| gpl-2.0 |
delaemon/linux | drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c | 614 | 58698 | /*---------------------------------------------------------------------------
FT1000 driver for Flarion Flash OFDM NIC Device
Copyright (C) 2002 Flarion Technologies, All rights reserved.
Copyright (C) 2006 Patrik Ostrihon, All rights reserved.
Copyright (C) 2006 ProWeb Consulting, a.s, All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option) any
later version. This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License along with this program; if not, write to the
Free Software Foundation, Inc., 59 Temple Place -
Suite 330, Boston, MA 02111-1307, USA.
-------------------------------------------------------------------------*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include <linux/wait.h>
#include <linux/vmalloc.h>
#include <linux/firmware.h>
#include <linux/ethtool.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/cisreg.h>
#include <pcmcia/ds.h>
#include <linux/delay.h>
#include "ft1000.h"
static const struct firmware *fw_entry;
static void ft1000_hbchk(u_long data);
static struct timer_list poll_timer = {
.function = ft1000_hbchk
};
static u16 cmdbuffer[1024];
static u8 tempbuffer[1600];
static u8 ft1000_card_present;
static u8 flarion_ft1000_cnt;
static irqreturn_t ft1000_interrupt(int irq, void *dev_id);
static void ft1000_enable_interrupts(struct net_device *dev);
static void ft1000_disable_interrupts(struct net_device *dev);
/* new kernel */
MODULE_AUTHOR("");
MODULE_DESCRIPTION("Support for Flarion Flash OFDM NIC Device. Support for PCMCIA when used with ft1000_cs.");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("FT1000");
#define MAX_RCV_LOOP 100
/*---------------------------------------------------------------------------
Function: ft1000_read_fifo_len
Description: This function will read the ASIC Uplink FIFO status register
which will return the number of bytes remaining in the Uplink FIFO.
Sixteen bytes are subtracted to make sure that the ASIC does not
reach its threshold.
Input:
dev - network device structure
Output:
value - number of bytes available in the ASIC Uplink FIFO.
-------------------------------------------------------------------------*/
static inline u16 ft1000_read_fifo_len(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
if (info->AsicID == ELECTRABUZZ_ID)
return (ft1000_read_reg(dev, FT1000_REG_UFIFO_STAT) - 16);
else
return (ft1000_read_reg(dev, FT1000_REG_MAG_UFSR) - 16);
}
/*---------------------------------------------------------------------------
Function: ft1000_read_dpram
Description: This function will read the specific area of dpram
(Electrabuzz ASIC only)
Input:
dev - device structure
offset - index of dpram
Output:
value - value of dpram
-------------------------------------------------------------------------*/
u16 ft1000_read_dpram(struct net_device *dev, int offset)
{
struct ft1000_info *info = netdev_priv(dev);
unsigned long flags;
u16 data;
/* Provide mutual exclusive access while reading ASIC registers. */
spin_lock_irqsave(&info->dpram_lock, flags);
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, offset);
data = ft1000_read_reg(dev, FT1000_REG_DPRAM_DATA);
spin_unlock_irqrestore(&info->dpram_lock, flags);
return data;
}
/*---------------------------------------------------------------------------
Function: ft1000_write_dpram
Description: This function will write to a specific area of dpram
(Electrabuzz ASIC only)
Input:
dev - device structure
offset - index of dpram
value - value to write
Output:
none.
-------------------------------------------------------------------------*/
static inline void ft1000_write_dpram(struct net_device *dev,
int offset, u16 value)
{
struct ft1000_info *info = netdev_priv(dev);
unsigned long flags;
/* Provide mutual exclusive access while reading ASIC registers. */
spin_lock_irqsave(&info->dpram_lock, flags);
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, offset);
ft1000_write_reg(dev, FT1000_REG_DPRAM_DATA, value);
spin_unlock_irqrestore(&info->dpram_lock, flags);
}
/*---------------------------------------------------------------------------
Function: ft1000_read_dpram_mag_16
Description: This function will read the specific area of dpram
(Magnemite ASIC only)
Input:
dev - device structure
offset - index of dpram
Output:
value - value of dpram
-------------------------------------------------------------------------*/
u16 ft1000_read_dpram_mag_16(struct net_device *dev, int offset, int Index)
{
struct ft1000_info *info = netdev_priv(dev);
unsigned long flags;
u16 data;
/* Provide mutual exclusive access while reading ASIC registers. */
spin_lock_irqsave(&info->dpram_lock, flags);
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, offset);
/* check if we want to read upper or lower 32-bit word */
if (Index)
data = ft1000_read_reg(dev, FT1000_REG_MAG_DPDATAL);
else
data = ft1000_read_reg(dev, FT1000_REG_MAG_DPDATAH);
spin_unlock_irqrestore(&info->dpram_lock, flags);
return data;
}
/*---------------------------------------------------------------------------
Function: ft1000_write_dpram_mag_16
Description: This function will write to a specific area of dpram
(Magnemite ASIC only)
Input:
dev - device structure
offset - index of dpram
value - value to write
Output:
none.
-------------------------------------------------------------------------*/
static inline void ft1000_write_dpram_mag_16(struct net_device *dev,
int offset, u16 value, int Index)
{
struct ft1000_info *info = netdev_priv(dev);
unsigned long flags;
/* Provide mutual exclusive access while reading ASIC registers. */
spin_lock_irqsave(&info->dpram_lock, flags);
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, offset);
if (Index)
ft1000_write_reg(dev, FT1000_REG_MAG_DPDATAL, value);
else
ft1000_write_reg(dev, FT1000_REG_MAG_DPDATAH, value);
spin_unlock_irqrestore(&info->dpram_lock, flags);
}
/*---------------------------------------------------------------------------
Function: ft1000_read_dpram_mag_32
Description: This function will read the specific area of dpram
(Magnemite ASIC only)
Input:
dev - device structure
offset - index of dpram
Output:
value - value of dpram
-------------------------------------------------------------------------*/
u32 ft1000_read_dpram_mag_32(struct net_device *dev, int offset)
{
struct ft1000_info *info = netdev_priv(dev);
unsigned long flags;
u32 data;
/* Provide mutual exclusive access while reading ASIC registers. */
spin_lock_irqsave(&info->dpram_lock, flags);
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, offset);
data = inl(dev->base_addr + FT1000_REG_MAG_DPDATAL);
spin_unlock_irqrestore(&info->dpram_lock, flags);
return data;
}
/*---------------------------------------------------------------------------
Function: ft1000_write_dpram_mag_32
Description: This function will write to a specific area of dpram
(Magnemite ASIC only)
Input:
dev - device structure
offset - index of dpram
value - value to write
Output:
none.
-------------------------------------------------------------------------*/
void ft1000_write_dpram_mag_32(struct net_device *dev, int offset, u32 value)
{
struct ft1000_info *info = netdev_priv(dev);
unsigned long flags;
/* Provide mutual exclusive access while reading ASIC registers. */
spin_lock_irqsave(&info->dpram_lock, flags);
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, offset);
outl(value, dev->base_addr + FT1000_REG_MAG_DPDATAL);
spin_unlock_irqrestore(&info->dpram_lock, flags);
}
/*---------------------------------------------------------------------------
Function: ft1000_enable_interrupts
Description: This function will enable interrupts base on the current
interrupt mask.
Input:
dev - device structure
Output:
None.
-------------------------------------------------------------------------*/
static void ft1000_enable_interrupts(struct net_device *dev)
{
u16 tempword;
ft1000_write_reg(dev, FT1000_REG_SUP_IMASK, ISR_DEFAULT_MASK);
tempword = ft1000_read_reg(dev, FT1000_REG_SUP_IMASK);
pr_debug("current interrupt enable mask = 0x%x\n", tempword);
}
/*---------------------------------------------------------------------------
Function: ft1000_disable_interrupts
Description: This function will disable all interrupts.
Input:
dev - device structure
Output:
None.
-------------------------------------------------------------------------*/
static void ft1000_disable_interrupts(struct net_device *dev)
{
u16 tempword;
ft1000_write_reg(dev, FT1000_REG_SUP_IMASK, ISR_MASK_ALL);
tempword = ft1000_read_reg(dev, FT1000_REG_SUP_IMASK);
pr_debug("current interrupt enable mask = 0x%x\n", tempword);
}
/*---------------------------------------------------------------------------
Function: ft1000_read_dsp_timer
Description: This function reads the DSP timer and stores its value in the
DSP_TIME field of the ft1000_info struct passed as argument
Input:
dev - device structure
info - ft1000_info structure
Output:
None.
-------------------------------------------------------------------------*/
static void ft1000_read_dsp_timer(struct net_device *dev,
struct ft1000_info *info)
{
if (info->AsicID == ELECTRABUZZ_ID) {
info->DSP_TIME[0] = ft1000_read_dpram(dev, FT1000_DSP_TIMER0);
info->DSP_TIME[1] = ft1000_read_dpram(dev, FT1000_DSP_TIMER1);
info->DSP_TIME[2] = ft1000_read_dpram(dev, FT1000_DSP_TIMER2);
info->DSP_TIME[3] = ft1000_read_dpram(dev, FT1000_DSP_TIMER3);
} else {
info->DSP_TIME[0] =
ft1000_read_dpram_mag_16(dev, FT1000_MAG_DSP_TIMER0,
FT1000_MAG_DSP_TIMER0_INDX);
info->DSP_TIME[1] =
ft1000_read_dpram_mag_16(dev, FT1000_MAG_DSP_TIMER1,
FT1000_MAG_DSP_TIMER1_INDX);
info->DSP_TIME[2] =
ft1000_read_dpram_mag_16(dev, FT1000_MAG_DSP_TIMER2,
FT1000_MAG_DSP_TIMER2_INDX);
info->DSP_TIME[3] =
ft1000_read_dpram_mag_16(dev, FT1000_MAG_DSP_TIMER3,
FT1000_MAG_DSP_TIMER3_INDX);
}
}
/*---------------------------------------------------------------------------
Function: ft1000_reset_asic
Description: This function will call the Card Service function to reset the
ASIC.
Input:
dev - device structure
Output:
none
-------------------------------------------------------------------------*/
static void ft1000_reset_asic(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
struct ft1000_pcmcia *pcmcia = info->priv;
u16 tempword;
(*info->ft1000_reset) (pcmcia->link);
/*
* Let's use the register provided by the Magnemite ASIC to reset the
* ASIC and DSP.
*/
if (info->AsicID == MAGNEMITE_ID) {
ft1000_write_reg(dev, FT1000_REG_RESET,
DSP_RESET_BIT | ASIC_RESET_BIT);
}
mdelay(1);
if (info->AsicID == ELECTRABUZZ_ID) {
/* set watermark to -1 in order to not generate an interrupt */
ft1000_write_reg(dev, FT1000_REG_WATERMARK, 0xffff);
} else {
/* set watermark to -1 in order to not generate an interrupt */
ft1000_write_reg(dev, FT1000_REG_MAG_WATERMARK, 0xffff);
}
/* clear interrupts */
tempword = ft1000_read_reg(dev, FT1000_REG_SUP_ISR);
pr_debug("interrupt status register = 0x%x\n", tempword);
ft1000_write_reg(dev, FT1000_REG_SUP_ISR, tempword);
tempword = ft1000_read_reg(dev, FT1000_REG_SUP_ISR);
pr_debug("interrupt status register = 0x%x\n", tempword);
}
/*---------------------------------------------------------------------------
Function: ft1000_reset_card
Description: This function will reset the card
Input:
dev - device structure
Output:
status - false (card reset fail)
true (card reset successful)
-------------------------------------------------------------------------*/
static int ft1000_reset_card(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
u16 tempword;
int i;
unsigned long flags;
struct prov_record *ptr;
struct prov_record *tmp;
info->CardReady = 0;
info->ProgConStat = 0;
info->squeseqnum = 0;
ft1000_disable_interrupts(dev);
/* del_timer(&poll_timer); */
/* Make sure we free any memory reserve for provisioning */
list_for_each_entry_safe(ptr, tmp, &info->prov_list, list) {
pr_debug("deleting provisioning record\n");
list_del(&ptr->list);
kfree(ptr->pprov_data);
kfree(ptr);
}
if (info->AsicID == ELECTRABUZZ_ID) {
pr_debug("resetting DSP\n");
ft1000_write_reg(dev, FT1000_REG_RESET, DSP_RESET_BIT);
} else {
pr_debug("resetting ASIC and DSP\n");
ft1000_write_reg(dev, FT1000_REG_RESET,
DSP_RESET_BIT | ASIC_RESET_BIT);
}
/* Copy DSP session record into info block if this is not a coldstart */
if (ft1000_card_present == 1) {
spin_lock_irqsave(&info->dpram_lock, flags);
if (info->AsicID == ELECTRABUZZ_ID) {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_RX_BASE);
for (i = 0; i < MAX_DSP_SESS_REC; i++) {
info->DSPSess.Rec[i] =
ft1000_read_reg(dev,
FT1000_REG_DPRAM_DATA);
}
} else {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_MAG_RX_BASE);
for (i = 0; i < MAX_DSP_SESS_REC / 2; i++) {
info->DSPSess.MagRec[i] =
inl(dev->base_addr
+ FT1000_REG_MAG_DPDATA);
}
}
spin_unlock_irqrestore(&info->dpram_lock, flags);
}
pr_debug("resetting ASIC\n");
mdelay(10);
/* reset ASIC */
ft1000_reset_asic(dev);
pr_debug("downloading dsp image\n");
if (info->AsicID == MAGNEMITE_ID) {
/* Put dsp in reset and take ASIC out of reset */
pr_debug("Put DSP in reset and take ASIC out of reset\n");
ft1000_write_reg(dev, FT1000_REG_RESET, DSP_RESET_BIT);
/* Setting MAGNEMITE ASIC to big endian mode */
ft1000_write_reg(dev, FT1000_REG_SUP_CTRL, HOST_INTF_BE);
/* Download bootloader */
card_bootload(dev);
/* Take DSP out of reset */
ft1000_write_reg(dev, FT1000_REG_RESET, 0);
/* FLARION_DSP_ACTIVE; */
mdelay(10);
pr_debug("Take DSP out of reset\n");
/*
* Wait for 0xfefe indicating dsp ready before starting
* download
*/
for (i = 0; i < 50; i++) {
tempword = ft1000_read_dpram_mag_16(dev,
FT1000_MAG_DPRAM_FEFE,
FT1000_MAG_DPRAM_FEFE_INDX);
if (tempword == 0xfefe)
break;
mdelay(20);
}
if (i == 50) {
pr_debug("No FEFE detected from DSP\n");
return false;
}
} else {
/* Take DSP out of reset */
ft1000_write_reg(dev, FT1000_REG_RESET, ~DSP_RESET_BIT);
mdelay(10);
}
if (card_download(dev, fw_entry->data, fw_entry->size)) {
pr_debug("card download unsuccessful\n");
return false;
}
pr_debug("card download successful\n");
mdelay(10);
if (info->AsicID == ELECTRABUZZ_ID) {
/*
* Need to initialize the FIFO length counter to zero in order
* to sync up with the DSP
*/
info->fifo_cnt = 0;
ft1000_write_dpram(dev, FT1000_FIFO_LEN, info->fifo_cnt);
/* Initialize DSP heartbeat area to ho */
ft1000_write_dpram(dev, FT1000_HI_HO, ho);
tempword = ft1000_read_dpram(dev, FT1000_HI_HO);
pr_debug("hi_ho value = 0x%x\n", tempword);
} else {
/* Initialize DSP heartbeat area to ho */
ft1000_write_dpram_mag_16(dev, FT1000_MAG_HI_HO, ho_mag,
FT1000_MAG_HI_HO_INDX);
tempword =
ft1000_read_dpram_mag_16(dev, FT1000_MAG_HI_HO,
FT1000_MAG_HI_HO_INDX);
pr_debug("hi_ho value = 0x%x\n", tempword);
}
info->CardReady = 1;
ft1000_enable_interrupts(dev);
/* Schedule heartbeat process to run every 2 seconds */
/* poll_timer.expires = jiffies + (2*HZ); */
/* poll_timer.data = (u_long)dev; */
/* add_timer(&poll_timer); */
return true;
}
/*---------------------------------------------------------------------------
Function: ft1000_chkcard
Description: This function will check if the device is presently available on
the system.
Input:
dev - device structure
Output:
status - false (device is not present)
true (device is present)
-------------------------------------------------------------------------*/
static int ft1000_chkcard(struct net_device *dev)
{
u16 tempword;
/*
* Mask register is used to check for device presence since it is never
* set to zero.
*/
tempword = ft1000_read_reg(dev, FT1000_REG_SUP_IMASK);
if (tempword == 0) {
pr_debug("IMASK = 0 Card not detected\n");
return false;
}
/*
* The system will return the value of 0xffff for the version register
* if the device is not present.
*/
tempword = ft1000_read_reg(dev, FT1000_REG_ASIC_ID);
if (tempword == 0xffff) {
pr_debug("Version = 0xffff Card not detected\n");
return false;
}
return true;
}
/*---------------------------------------------------------------------------
Function: ft1000_hbchk
Description: This function will perform the heart beat check of the DSP as
well as the ASIC.
Input:
dev - device structure
Output:
none
-------------------------------------------------------------------------*/
static void ft1000_hbchk(u_long data)
{
struct net_device *dev = (struct net_device *)data;
struct ft1000_info *info;
u16 tempword;
info = netdev_priv(dev);
if (info->CardReady == 1) {
/* Perform dsp heartbeat check */
if (info->AsicID == ELECTRABUZZ_ID) {
tempword = ft1000_read_dpram(dev, FT1000_HI_HO);
} else {
tempword =
ntohs(ft1000_read_dpram_mag_16
(dev, FT1000_MAG_HI_HO,
FT1000_MAG_HI_HO_INDX));
}
pr_debug("hi_ho value = 0x%x\n", tempword);
/* Let's perform another check if ho is not detected */
if (tempword != ho) {
if (info->AsicID == ELECTRABUZZ_ID)
tempword = ft1000_read_dpram(dev, FT1000_HI_HO);
else
tempword = ntohs(ft1000_read_dpram_mag_16(dev,
FT1000_MAG_HI_HO,
FT1000_MAG_HI_HO_INDX));
}
if (tempword != ho) {
pr_info("heartbeat failed - no ho detected\n");
ft1000_read_dsp_timer(dev, info);
info->DrvErrNum = DSP_HB_INFO;
if (ft1000_reset_card(dev) == 0) {
pr_info("Hardware Failure Detected - PC Card disabled\n");
info->ProgConStat = 0xff;
return;
}
/* Schedule this module to run every 2 seconds */
poll_timer.expires = jiffies + (2*HZ);
poll_timer.data = (u_long)dev;
add_timer(&poll_timer);
return;
}
tempword = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
/* Let's check doorbell again if fail */
if (tempword & FT1000_DB_HB)
tempword = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
if (tempword & FT1000_DB_HB) {
pr_info("heartbeat doorbell not clear by firmware\n");
ft1000_read_dsp_timer(dev, info);
info->DrvErrNum = DSP_HB_INFO;
if (ft1000_reset_card(dev) == 0) {
pr_info("Hardware Failure Detected - PC Card disabled\n");
info->ProgConStat = 0xff;
return;
}
/* Schedule this module to run every 2 seconds */
poll_timer.expires = jiffies + (2*HZ);
poll_timer.data = (u_long)dev;
add_timer(&poll_timer);
return;
}
/*
* Set dedicated area to hi and ring appropriate doorbell
* according to hi/ho heartbeat protocol
*/
if (info->AsicID == ELECTRABUZZ_ID) {
ft1000_write_dpram(dev, FT1000_HI_HO, hi);
} else {
ft1000_write_dpram_mag_16(dev, FT1000_MAG_HI_HO, hi_mag,
FT1000_MAG_HI_HO_INDX);
}
if (info->AsicID == ELECTRABUZZ_ID) {
tempword = ft1000_read_dpram(dev, FT1000_HI_HO);
} else {
tempword =
ntohs(ft1000_read_dpram_mag_16
(dev, FT1000_MAG_HI_HO,
FT1000_MAG_HI_HO_INDX));
}
/* Let's write hi again if fail */
if (tempword != hi) {
if (info->AsicID == ELECTRABUZZ_ID)
ft1000_write_dpram(dev, FT1000_HI_HO, hi);
else
ft1000_write_dpram_mag_16(dev, FT1000_MAG_HI_HO,
hi_mag, FT1000_MAG_HI_HO_INDX);
if (info->AsicID == ELECTRABUZZ_ID)
tempword = ft1000_read_dpram(dev, FT1000_HI_HO);
else
tempword = ntohs(ft1000_read_dpram_mag_16(dev,
FT1000_MAG_HI_HO,
FT1000_MAG_HI_HO_INDX));
}
if (tempword != hi) {
pr_info("heartbeat failed - cannot write hi into DPRAM\n");
ft1000_read_dsp_timer(dev, info);
info->DrvErrNum = DSP_HB_INFO;
if (ft1000_reset_card(dev) == 0) {
pr_info("Hardware Failure Detected - PC Card disabled\n");
info->ProgConStat = 0xff;
return;
}
/* Schedule this module to run every 2 seconds */
poll_timer.expires = jiffies + (2*HZ);
poll_timer.data = (u_long)dev;
add_timer(&poll_timer);
return;
}
ft1000_write_reg(dev, FT1000_REG_DOORBELL, FT1000_DB_HB);
}
/* Schedule this module to run every 2 seconds */
poll_timer.expires = jiffies + (2 * HZ);
poll_timer.data = (u_long)dev;
add_timer(&poll_timer);
}
/*---------------------------------------------------------------------------
Function: ft1000_send_cmd
Description:
Input:
Output:
-------------------------------------------------------------------------*/
static void ft1000_send_cmd(struct net_device *dev, u16 *ptempbuffer, int size,
u16 qtype)
{
struct ft1000_info *info = netdev_priv(dev);
int i;
u16 tempword;
unsigned long flags;
size += sizeof(struct pseudo_hdr);
/* check for odd byte and increment to 16-bit word align value */
if ((size & 0x0001))
size++;
pr_debug("total length = %d\n", size);
pr_debug("length = %d\n", ntohs(*ptempbuffer));
/*
* put message into slow queue area
* All messages are in the form total_len + pseudo header + message body
*/
spin_lock_irqsave(&info->dpram_lock, flags);
/* Make sure SLOWQ doorbell is clear */
tempword = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
i = 0;
while (tempword & FT1000_DB_DPRAM_TX) {
mdelay(10);
i++;
if (i == 10) {
spin_unlock_irqrestore(&info->dpram_lock, flags);
return;
}
tempword = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
}
if (info->AsicID == ELECTRABUZZ_ID) {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_TX_BASE);
/* Write total length to dpram */
ft1000_write_reg(dev, FT1000_REG_DPRAM_DATA, size);
/* Write pseudo header and messgae body */
for (i = 0; i < (size >> 1); i++) {
pr_debug("data %d = 0x%x\n", i, *ptempbuffer);
tempword = htons(*ptempbuffer++);
ft1000_write_reg(dev, FT1000_REG_DPRAM_DATA, tempword);
}
} else {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_MAG_TX_BASE);
/* Write total length to dpram */
ft1000_write_reg(dev, FT1000_REG_MAG_DPDATAH, htons(size));
/* Write pseudo header and messgae body */
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_MAG_TX_BASE + 1);
for (i = 0; i < (size >> 2); i++) {
pr_debug("data = 0x%x\n", *ptempbuffer);
outw(*ptempbuffer++,
dev->base_addr + FT1000_REG_MAG_DPDATAL);
pr_debug("data = 0x%x\n", *ptempbuffer);
outw(*ptempbuffer++,
dev->base_addr + FT1000_REG_MAG_DPDATAH);
}
pr_debug("data = 0x%x\n", *ptempbuffer);
outw(*ptempbuffer++, dev->base_addr + FT1000_REG_MAG_DPDATAL);
pr_debug("data = 0x%x\n", *ptempbuffer);
outw(*ptempbuffer++, dev->base_addr + FT1000_REG_MAG_DPDATAH);
}
spin_unlock_irqrestore(&info->dpram_lock, flags);
/* ring doorbell to notify DSP that we have a message ready */
ft1000_write_reg(dev, FT1000_REG_DOORBELL, FT1000_DB_DPRAM_TX);
}
/*---------------------------------------------------------------------------
Function: ft1000_receive_cmd
Description: This function will read a message from the dpram area.
Input:
dev - network device structure
pbuffer - caller supply address to buffer
pnxtph - pointer to next pseudo header
Output:
Status = 0 (unsuccessful)
= 1 (successful)
-------------------------------------------------------------------------*/
static bool ft1000_receive_cmd(struct net_device *dev, u16 *pbuffer,
int maxsz, u16 *pnxtph)
{
struct ft1000_info *info = netdev_priv(dev);
u16 size;
u16 *ppseudohdr;
int i;
u16 tempword;
unsigned long flags;
if (info->AsicID == ELECTRABUZZ_ID) {
size = ft1000_read_dpram(dev, *pnxtph)
+ sizeof(struct pseudo_hdr);
} else {
size = ntohs(ft1000_read_dpram_mag_16(dev, FT1000_MAG_PH_LEN,
FT1000_MAG_PH_LEN_INDX))
+ sizeof(struct pseudo_hdr);
}
if (size > maxsz) {
pr_debug("Invalid command length = %d\n", size);
return false;
}
ppseudohdr = (u16 *)pbuffer;
spin_lock_irqsave(&info->dpram_lock, flags);
if (info->AsicID == ELECTRABUZZ_ID) {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_RX_BASE + 2);
for (i = 0; i <= (size >> 1); i++) {
tempword =
ft1000_read_reg(dev, FT1000_REG_DPRAM_DATA);
*pbuffer++ = ntohs(tempword);
}
} else {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_MAG_RX_BASE);
*pbuffer = inw(dev->base_addr + FT1000_REG_MAG_DPDATAH);
pr_debug("received data = 0x%x\n", *pbuffer);
pbuffer++;
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_MAG_RX_BASE + 1);
for (i = 0; i <= (size >> 2); i++) {
*pbuffer =
inw(dev->base_addr +
FT1000_REG_MAG_DPDATAL);
pbuffer++;
*pbuffer =
inw(dev->base_addr +
FT1000_REG_MAG_DPDATAH);
pbuffer++;
}
/* copy odd aligned word */
*pbuffer = inw(dev->base_addr + FT1000_REG_MAG_DPDATAL);
pr_debug("received data = 0x%x\n", *pbuffer);
pbuffer++;
*pbuffer = inw(dev->base_addr + FT1000_REG_MAG_DPDATAH);
pr_debug("received data = 0x%x\n", *pbuffer);
pbuffer++;
}
if (size & 0x0001) {
/* copy odd byte from fifo */
tempword = ft1000_read_reg(dev, FT1000_REG_DPRAM_DATA);
*pbuffer = ntohs(tempword);
}
spin_unlock_irqrestore(&info->dpram_lock, flags);
/*
* Check if pseudo header checksum is good
* Calculate pseudo header checksum
*/
tempword = *ppseudohdr++;
for (i = 1; i < 7; i++)
tempword ^= *ppseudohdr++;
if (tempword != *ppseudohdr) {
pr_debug("Pseudo header checksum mismatch\n");
/* Drop this message */
return false;
}
return true;
}
/*---------------------------------------------------------------------------
Function: ft1000_proc_drvmsg
Description: This function will process the various driver messages.
Input:
dev - device structure
pnxtph - pointer to next pseudo header
Output:
none
-------------------------------------------------------------------------*/
static void ft1000_proc_drvmsg(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
u16 msgtype;
u16 tempword;
struct media_msg *pmediamsg;
struct dsp_init_msg *pdspinitmsg;
struct drv_msg *pdrvmsg;
u16 len;
u16 i;
struct prov_record *ptr;
struct pseudo_hdr *ppseudo_hdr;
u16 *pmsg;
struct timeval tv;
union {
u8 byte[2];
u16 wrd;
} convert;
if (info->AsicID == ELECTRABUZZ_ID)
tempword = FT1000_DPRAM_RX_BASE+2;
else
tempword = FT1000_DPRAM_MAG_RX_BASE;
if (ft1000_receive_cmd(dev, &cmdbuffer[0], MAX_CMD_SQSIZE, &tempword)) {
/*
* Get the message type which is total_len + PSEUDO header
* + msgtype + message body
*/
pdrvmsg = (struct drv_msg *)&cmdbuffer[0];
msgtype = ntohs(pdrvmsg->type);
pr_debug("Command message type = 0x%x\n", msgtype);
switch (msgtype) {
case DSP_PROVISION:
pr_debug("Got a provisioning request message from DSP\n");
mdelay(25);
while (list_empty(&info->prov_list) == 0) {
pr_debug("Sending a provisioning message\n");
/* Make sure SLOWQ doorbell is clear */
tempword = ft1000_read_reg(dev,
FT1000_REG_DOORBELL);
i = 0;
while (tempword & FT1000_DB_DPRAM_TX) {
mdelay(5);
i++;
if (i == 10)
break;
}
ptr = list_entry(info->prov_list.next,
struct prov_record, list);
len = *(u16 *)ptr->pprov_data;
len = htons(len);
pmsg = (u16 *)ptr->pprov_data;
ppseudo_hdr = (struct pseudo_hdr *)pmsg;
/* Insert slow queue sequence number */
ppseudo_hdr->seq_num = info->squeseqnum++;
ppseudo_hdr->portsrc = 0;
/* Calculate new checksum */
ppseudo_hdr->checksum = *pmsg++;
pr_debug("checksum = 0x%x\n",
ppseudo_hdr->checksum);
for (i = 1; i < 7; i++) {
ppseudo_hdr->checksum ^= *pmsg++;
pr_debug("checksum = 0x%x\n",
ppseudo_hdr->checksum);
}
ft1000_send_cmd(dev, (u16 *)ptr->pprov_data,
len, SLOWQ_TYPE);
list_del(&ptr->list);
kfree(ptr->pprov_data);
kfree(ptr);
}
/*
* Indicate adapter is ready to take application
* messages after all provisioning messages are sent
*/
info->CardReady = 1;
break;
case MEDIA_STATE:
pmediamsg = (struct media_msg *)&cmdbuffer[0];
if (info->ProgConStat != 0xFF) {
if (pmediamsg->state) {
pr_debug("Media is up\n");
if (info->mediastate == 0) {
netif_carrier_on(dev);
netif_wake_queue(dev);
info->mediastate = 1;
do_gettimeofday(&tv);
info->ConTm = tv.tv_sec;
}
} else {
pr_debug("Media is down\n");
if (info->mediastate == 1) {
info->mediastate = 0;
netif_carrier_off(dev);
netif_stop_queue(dev);
info->ConTm = 0;
}
}
} else {
pr_debug("Media is down\n");
if (info->mediastate == 1) {
info->mediastate = 0;
netif_carrier_off(dev);
netif_stop_queue(dev);
info->ConTm = 0;
}
}
break;
case DSP_INIT_MSG:
pdspinitmsg = (struct dsp_init_msg *)&cmdbuffer[0];
memcpy(info->DspVer, pdspinitmsg->DspVer, DSPVERSZ);
pr_debug("DSPVER = 0x%2x 0x%2x 0x%2x 0x%2x\n",
info->DspVer[0], info->DspVer[1],
info->DspVer[2], info->DspVer[3]);
memcpy(info->HwSerNum, pdspinitmsg->HwSerNum,
HWSERNUMSZ);
memcpy(info->Sku, pdspinitmsg->Sku, SKUSZ);
memcpy(info->eui64, pdspinitmsg->eui64, EUISZ);
dev->dev_addr[0] = info->eui64[0];
dev->dev_addr[1] = info->eui64[1];
dev->dev_addr[2] = info->eui64[2];
dev->dev_addr[3] = info->eui64[5];
dev->dev_addr[4] = info->eui64[6];
dev->dev_addr[5] = info->eui64[7];
if (ntohs(pdspinitmsg->length) ==
(sizeof(struct dsp_init_msg) - 20)) {
memcpy(info->ProductMode,
pdspinitmsg->ProductMode, MODESZ);
memcpy(info->RfCalVer, pdspinitmsg->RfCalVer,
CALVERSZ);
memcpy(info->RfCalDate, pdspinitmsg->RfCalDate,
CALDATESZ);
pr_debug("RFCalVer = 0x%2x 0x%2x\n",
info->RfCalVer[0], info->RfCalVer[1]);
}
break;
case DSP_STORE_INFO:
pr_debug("Got DSP_STORE_INFO\n");
tempword = ntohs(pdrvmsg->length);
info->DSPInfoBlklen = tempword;
if (tempword < (MAX_DSP_SESS_REC - 4)) {
pmsg = (u16 *)&pdrvmsg->data[0];
for (i = 0; i < ((tempword + 1) / 2); i++) {
pr_debug("dsp info data = 0x%x\n",
*pmsg);
info->DSPInfoBlk[i + 10] = *pmsg++;
}
}
break;
case DSP_GET_INFO:
pr_debug("Got DSP_GET_INFO\n");
/*
* copy dsp info block to dsp
* allow any outstanding ioctl to finish
*/
mdelay(10);
tempword = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
if (tempword & FT1000_DB_DPRAM_TX) {
mdelay(10);
tempword = ft1000_read_reg(dev,
FT1000_REG_DOORBELL);
if (tempword & FT1000_DB_DPRAM_TX)
mdelay(10);
}
if ((tempword & FT1000_DB_DPRAM_TX) == 0) {
/*
* Put message into Slow Queue
* Form Pseudo header
*/
pmsg = (u16 *)info->DSPInfoBlk;
ppseudo_hdr = (struct pseudo_hdr *)pmsg;
ppseudo_hdr->length =
htons(info->DSPInfoBlklen + 4);
ppseudo_hdr->source = 0x10;
ppseudo_hdr->destination = 0x20;
ppseudo_hdr->portdest = 0;
ppseudo_hdr->portsrc = 0;
ppseudo_hdr->sh_str_id = 0;
ppseudo_hdr->control = 0;
ppseudo_hdr->rsvd1 = 0;
ppseudo_hdr->rsvd2 = 0;
ppseudo_hdr->qos_class = 0;
/* Insert slow queue sequence number */
ppseudo_hdr->seq_num = info->squeseqnum++;
/* Insert application id */
ppseudo_hdr->portsrc = 0;
/* Calculate new checksum */
ppseudo_hdr->checksum = *pmsg++;
for (i = 1; i < 7; i++)
ppseudo_hdr->checksum ^= *pmsg++;
info->DSPInfoBlk[8] = 0x7200;
info->DSPInfoBlk[9] =
htons(info->DSPInfoBlklen);
ft1000_send_cmd(dev, info->DSPInfoBlk,
(u16)(info->DSPInfoBlklen+4),
0);
}
break;
case GET_DRV_ERR_RPT_MSG:
pr_debug("Got GET_DRV_ERR_RPT_MSG\n");
/*
* copy driver error message to dsp
* allow any outstanding ioctl to finish
*/
mdelay(10);
tempword = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
if (tempword & FT1000_DB_DPRAM_TX) {
mdelay(10);
tempword = ft1000_read_reg(dev,
FT1000_REG_DOORBELL);
if (tempword & FT1000_DB_DPRAM_TX)
mdelay(10);
}
if ((tempword & FT1000_DB_DPRAM_TX) == 0) {
/*
* Put message into Slow Queue
* Form Pseudo header
*/
pmsg = (u16 *)&tempbuffer[0];
ppseudo_hdr = (struct pseudo_hdr *)pmsg;
ppseudo_hdr->length = htons(0x0012);
ppseudo_hdr->source = 0x10;
ppseudo_hdr->destination = 0x20;
ppseudo_hdr->portdest = 0;
ppseudo_hdr->portsrc = 0;
ppseudo_hdr->sh_str_id = 0;
ppseudo_hdr->control = 0;
ppseudo_hdr->rsvd1 = 0;
ppseudo_hdr->rsvd2 = 0;
ppseudo_hdr->qos_class = 0;
/* Insert slow queue sequence number */
ppseudo_hdr->seq_num = info->squeseqnum++;
/* Insert application id */
ppseudo_hdr->portsrc = 0;
/* Calculate new checksum */
ppseudo_hdr->checksum = *pmsg++;
for (i = 1; i < 7; i++)
ppseudo_hdr->checksum ^= *pmsg++;
pmsg = (u16 *)&tempbuffer[16];
*pmsg++ = htons(RSP_DRV_ERR_RPT_MSG);
*pmsg++ = htons(0x000e);
*pmsg++ = htons(info->DSP_TIME[0]);
*pmsg++ = htons(info->DSP_TIME[1]);
*pmsg++ = htons(info->DSP_TIME[2]);
*pmsg++ = htons(info->DSP_TIME[3]);
convert.byte[0] = info->DspVer[0];
convert.byte[1] = info->DspVer[1];
*pmsg++ = convert.wrd;
convert.byte[0] = info->DspVer[2];
convert.byte[1] = info->DspVer[3];
*pmsg++ = convert.wrd;
*pmsg++ = htons(info->DrvErrNum);
ft1000_send_cmd(dev, (u16 *)&tempbuffer[0],
(u16)(0x0012), 0);
info->DrvErrNum = 0;
}
break;
default:
break;
}
}
}
/*---------------------------------------------------------------------------
Function: ft1000_parse_dpram_msg
Description: This function will parse the message received from the DSP
via the DPRAM interface.
Input:
dev - device structure
Output:
status - FAILURE
SUCCESS
-------------------------------------------------------------------------*/
static int ft1000_parse_dpram_msg(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
u16 doorbell;
u16 portid;
u16 nxtph;
u16 total_len;
int i = 0;
unsigned long flags;
doorbell = ft1000_read_reg(dev, FT1000_REG_DOORBELL);
pr_debug("Doorbell = 0x%x\n", doorbell);
if (doorbell & FT1000_ASIC_RESET_REQ) {
/* Copy DSP session record from info block */
spin_lock_irqsave(&info->dpram_lock, flags);
if (info->AsicID == ELECTRABUZZ_ID) {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_RX_BASE);
for (i = 0; i < MAX_DSP_SESS_REC; i++) {
ft1000_write_reg(dev, FT1000_REG_DPRAM_DATA,
info->DSPSess.Rec[i]);
}
} else {
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR,
FT1000_DPRAM_MAG_RX_BASE);
for (i = 0; i < MAX_DSP_SESS_REC / 2; i++) {
outl(info->DSPSess.MagRec[i],
dev->base_addr + FT1000_REG_MAG_DPDATA);
}
}
spin_unlock_irqrestore(&info->dpram_lock, flags);
/* clear ASIC RESET request */
ft1000_write_reg(dev, FT1000_REG_DOORBELL,
FT1000_ASIC_RESET_REQ);
pr_debug("Got an ASIC RESET Request\n");
ft1000_write_reg(dev, FT1000_REG_DOORBELL,
FT1000_ASIC_RESET_DSP);
if (info->AsicID == MAGNEMITE_ID) {
/* Setting MAGNEMITE ASIC to big endian mode */
ft1000_write_reg(dev, FT1000_REG_SUP_CTRL,
HOST_INTF_BE);
}
}
if (doorbell & FT1000_DSP_ASIC_RESET) {
pr_debug("Got a dsp ASIC reset message\n");
ft1000_write_reg(dev, FT1000_REG_DOORBELL,
FT1000_DSP_ASIC_RESET);
udelay(200);
return SUCCESS;
}
if (doorbell & FT1000_DB_DPRAM_RX) {
pr_debug("Got a slow queue message\n");
nxtph = FT1000_DPRAM_RX_BASE + 2;
if (info->AsicID == ELECTRABUZZ_ID) {
total_len =
ft1000_read_dpram(dev, FT1000_DPRAM_RX_BASE);
} else {
total_len =
ntohs(ft1000_read_dpram_mag_16
(dev, FT1000_MAG_TOTAL_LEN,
FT1000_MAG_TOTAL_LEN_INDX));
}
pr_debug("total length = %d\n", total_len);
if ((total_len < MAX_CMD_SQSIZE)
&& (total_len > sizeof(struct pseudo_hdr))) {
total_len += nxtph;
/*
* ft1000_read_reg will return a value that needs to be
* byteswap in order to get DSP_QID_OFFSET.
*/
if (info->AsicID == ELECTRABUZZ_ID) {
portid = (ft1000_read_dpram(dev, DSP_QID_OFFSET
+ FT1000_DPRAM_RX_BASE + 2)
>> 8) & 0xff;
} else {
portid =
ft1000_read_dpram_mag_16
(dev, FT1000_MAG_PORT_ID,
FT1000_MAG_PORT_ID_INDX) & 0xff;
}
pr_debug("DSP_QID = 0x%x\n", portid);
if (portid == DRIVERID) {
/*
* We are assumming one driver message from the
* DSP at a time.
*/
ft1000_proc_drvmsg(dev);
}
}
ft1000_write_reg(dev, FT1000_REG_DOORBELL, FT1000_DB_DPRAM_RX);
}
if (doorbell & FT1000_DB_COND_RESET) {
/* Reset ASIC and DSP */
ft1000_read_dsp_timer(dev, info);
info->DrvErrNum = DSP_CONDRESET_INFO;
pr_debug("DSP conditional reset requested\n");
ft1000_reset_card(dev);
ft1000_write_reg(dev, FT1000_REG_DOORBELL,
FT1000_DB_COND_RESET);
}
/* let's clear any unexpected doorbells from DSP */
doorbell =
doorbell & ~(FT1000_DB_DPRAM_RX | FT1000_ASIC_RESET_REQ |
FT1000_DB_COND_RESET | 0xff00);
if (doorbell) {
pr_debug("Clearing unexpected doorbell = 0x%x\n", doorbell);
ft1000_write_reg(dev, FT1000_REG_DOORBELL, doorbell);
}
return SUCCESS;
}
/*---------------------------------------------------------------------------
Function: ft1000_flush_fifo
Description: This function will flush one packet from the downlink
FIFO.
Input:
dev - device structure
drv_err - driver error causing the flush fifo
Output:
None.
-------------------------------------------------------------------------*/
static void ft1000_flush_fifo(struct net_device *dev, u16 DrvErrNum)
{
struct ft1000_info *info = netdev_priv(dev);
struct ft1000_pcmcia *pcmcia = info->priv;
u16 i;
u32 templong;
u16 tempword;
if (pcmcia->PktIntfErr > MAX_PH_ERR) {
ft1000_read_dsp_timer(dev, info);
info->DrvErrNum = DrvErrNum;
ft1000_reset_card(dev);
return;
}
/* Flush corrupted pkt from FIFO */
i = 0;
do {
if (info->AsicID == ELECTRABUZZ_ID) {
tempword =
ft1000_read_reg(dev, FT1000_REG_DFIFO);
tempword =
ft1000_read_reg(dev, FT1000_REG_DFIFO_STAT);
} else {
templong =
inl(dev->base_addr + FT1000_REG_MAG_DFR);
tempword =
inw(dev->base_addr + FT1000_REG_MAG_DFSR);
}
i++;
/*
* This should never happen unless the ASIC is broken.
* We must reset to recover.
*/
if ((i > 2048) || (tempword == 0)) {
ft1000_read_dsp_timer(dev, info);
if (tempword == 0) {
/*
* Let's check if ASIC reads are still ok by
* reading the Mask register which is never zero
* at this point of the code.
*/
tempword =
inw(dev->base_addr +
FT1000_REG_SUP_IMASK);
if (tempword == 0) {
/*
* This indicates that we can not
* communicate with the ASIC
*/
info->DrvErrNum = FIFO_FLUSH_BADCNT;
} else {
/*
* Let's assume that we really flush
* the FIFO
*/
pcmcia->PktIntfErr++;
return;
}
} else {
info->DrvErrNum = FIFO_FLUSH_MAXLIMIT;
}
return;
}
tempword = inw(dev->base_addr + FT1000_REG_SUP_STAT);
} while ((tempword & 0x03) != 0x03);
if (info->AsicID == ELECTRABUZZ_ID) {
i++;
pr_debug("Flushing FIFO complete = %x\n", tempword);
/* Flush last word in FIFO. */
tempword = ft1000_read_reg(dev, FT1000_REG_DFIFO);
/* Update FIFO counter for DSP */
i = i * 2;
pr_debug("Flush Data byte count to dsp = %d\n", i);
info->fifo_cnt += i;
ft1000_write_dpram(dev, FT1000_FIFO_LEN,
info->fifo_cnt);
} else {
pr_debug("Flushing FIFO complete = %x\n", tempword);
/* Flush last word in FIFO */
templong = inl(dev->base_addr + FT1000_REG_MAG_DFR);
tempword = inw(dev->base_addr + FT1000_REG_SUP_STAT);
pr_debug("FT1000_REG_SUP_STAT = 0x%x\n", tempword);
tempword = inw(dev->base_addr + FT1000_REG_MAG_DFSR);
pr_debug("FT1000_REG_MAG_DFSR = 0x%x\n", tempword);
}
if (DrvErrNum)
pcmcia->PktIntfErr++;
}
/*---------------------------------------------------------------------------
Function: ft1000_copy_up_pkt
Description: This function will pull Flarion packets out of the Downlink
FIFO and convert it to an ethernet packet. The ethernet packet will
then be deliver to the TCP/IP stack.
Input:
dev - device structure
Output:
status - FAILURE
SUCCESS
-------------------------------------------------------------------------*/
static int ft1000_copy_up_pkt(struct net_device *dev)
{
u16 tempword;
struct ft1000_info *info = netdev_priv(dev);
u16 len;
struct sk_buff *skb;
u16 i;
u8 *pbuffer = NULL;
u8 *ptemp = NULL;
u16 chksum;
u32 *ptemplong;
u32 templong;
/* Read length */
if (info->AsicID == ELECTRABUZZ_ID) {
tempword = ft1000_read_reg(dev, FT1000_REG_DFIFO);
len = tempword;
} else {
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRL);
len = ntohs(tempword);
}
chksum = tempword;
pr_debug("Number of Bytes in FIFO = %d\n", len);
if (len > ENET_MAX_SIZE) {
pr_debug("size of ethernet packet invalid\n");
if (info->AsicID == MAGNEMITE_ID) {
/* Read High word to complete 32 bit access */
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRH);
}
ft1000_flush_fifo(dev, DSP_PKTLEN_INFO);
info->stats.rx_errors++;
return FAILURE;
}
skb = dev_alloc_skb(len + 12 + 2);
if (skb == NULL) {
/* Read High word to complete 32 bit access */
if (info->AsicID == MAGNEMITE_ID)
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRH);
ft1000_flush_fifo(dev, 0);
info->stats.rx_errors++;
return FAILURE;
}
pbuffer = (u8 *)skb_put(skb, len + 12);
/* Pseudo header */
if (info->AsicID == ELECTRABUZZ_ID) {
for (i = 1; i < 7; i++) {
tempword = ft1000_read_reg(dev, FT1000_REG_DFIFO);
chksum ^= tempword;
}
/* read checksum value */
tempword = ft1000_read_reg(dev, FT1000_REG_DFIFO);
} else {
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRH);
pr_debug("Pseudo = 0x%x\n", tempword);
chksum ^= tempword;
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRL);
pr_debug("Pseudo = 0x%x\n", tempword);
chksum ^= tempword;
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRH);
pr_debug("Pseudo = 0x%x\n", tempword);
chksum ^= tempword;
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRL);
pr_debug("Pseudo = 0x%x\n", tempword);
chksum ^= tempword;
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRH);
pr_debug("Pseudo = 0x%x\n", tempword);
chksum ^= tempword;
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRL);
pr_debug("Pseudo = 0x%x\n", tempword);
chksum ^= tempword;
/* read checksum value */
tempword = ft1000_read_reg(dev, FT1000_REG_MAG_DFRH);
pr_debug("Pseudo = 0x%x\n", tempword);
}
if (chksum != tempword) {
pr_debug("Packet checksum mismatch 0x%x 0x%x\n",
chksum, tempword);
ft1000_flush_fifo(dev, DSP_PKTPHCKSUM_INFO);
info->stats.rx_errors++;
kfree_skb(skb);
return FAILURE;
}
/* subtract the number of bytes read already */
ptemp = pbuffer;
/* fake MAC address */
*pbuffer++ = dev->dev_addr[0];
*pbuffer++ = dev->dev_addr[1];
*pbuffer++ = dev->dev_addr[2];
*pbuffer++ = dev->dev_addr[3];
*pbuffer++ = dev->dev_addr[4];
*pbuffer++ = dev->dev_addr[5];
*pbuffer++ = 0x00;
*pbuffer++ = 0x07;
*pbuffer++ = 0x35;
*pbuffer++ = 0xff;
*pbuffer++ = 0xff;
*pbuffer++ = 0xfe;
if (info->AsicID == ELECTRABUZZ_ID) {
for (i = 0; i < len / 2; i++) {
tempword = ft1000_read_reg(dev, FT1000_REG_DFIFO);
*pbuffer++ = (u8) (tempword >> 8);
*pbuffer++ = (u8)tempword;
if (ft1000_chkcard(dev) == false) {
kfree_skb(skb);
return FAILURE;
}
}
/* Need to read one more word if odd byte */
if (len & 0x0001) {
tempword = ft1000_read_reg(dev, FT1000_REG_DFIFO);
*pbuffer++ = (u8) (tempword >> 8);
}
} else {
ptemplong = (u32 *)pbuffer;
for (i = 0; i < len / 4; i++) {
templong = inl(dev->base_addr + FT1000_REG_MAG_DFR);
pr_debug("Data = 0x%8x\n", templong);
*ptemplong++ = templong;
}
/* Need to read one more word if odd align. */
if (len & 0x0003) {
templong = inl(dev->base_addr + FT1000_REG_MAG_DFR);
pr_debug("Data = 0x%8x\n", templong);
*ptemplong++ = templong;
}
}
pr_debug("Data passed to Protocol layer:\n");
for (i = 0; i < len + 12; i++)
pr_debug("Protocol Data: 0x%x\n", *ptemp++);
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
skb->ip_summed = CHECKSUM_UNNECESSARY;
netif_rx(skb);
info->stats.rx_packets++;
/* Add on 12 bytes for MAC address which was removed */
info->stats.rx_bytes += (len + 12);
if (info->AsicID == ELECTRABUZZ_ID) {
/* track how many bytes have been read from FIFO - round up to
* 16 bit word */
tempword = len + 16;
if (tempword & 0x01)
tempword++;
info->fifo_cnt += tempword;
ft1000_write_reg(dev, FT1000_REG_DPRAM_ADDR, FT1000_FIFO_LEN);
ft1000_write_reg(dev, FT1000_REG_DPRAM_DATA, info->fifo_cnt);
}
return SUCCESS;
}
/*---------------------------------------------------------------------------
Function: ft1000_copy_down_pkt
Description: This function will take an ethernet packet and convert it to
a Flarion packet prior to sending it to the ASIC Downlink
FIFO.
Input:
dev - device structure
packet - address of ethernet packet
len - length of IP packet
Output:
status - FAILURE
SUCCESS
-------------------------------------------------------------------------*/
static int ft1000_copy_down_pkt(struct net_device *dev, u16 *packet, u16 len)
{
struct ft1000_info *info = netdev_priv(dev);
struct ft1000_pcmcia *pcmcia = info->priv;
union {
struct pseudo_hdr blk;
u16 buff[sizeof(struct pseudo_hdr) >> 1];
u8 buffc[sizeof(struct pseudo_hdr)];
} pseudo;
int i;
u32 *plong;
/* Check if there is room on the FIFO */
if (len > ft1000_read_fifo_len(dev)) {
udelay(10);
if (len > ft1000_read_fifo_len(dev))
udelay(20);
if (len > ft1000_read_fifo_len(dev))
udelay(20);
if (len > ft1000_read_fifo_len(dev))
udelay(20);
if (len > ft1000_read_fifo_len(dev))
udelay(20);
if (len > ft1000_read_fifo_len(dev))
udelay(20);
if (len > ft1000_read_fifo_len(dev)) {
pr_debug("Transmit FIFO is full - pkt drop\n");
info->stats.tx_errors++;
return SUCCESS;
}
}
/* Create pseudo header and send pseudo/ip to hardware */
if (info->AsicID == ELECTRABUZZ_ID)
pseudo.blk.length = len;
else
pseudo.blk.length = ntohs(len);
pseudo.blk.source = DSPID; /* Need to swap to get in correct
order */
pseudo.blk.destination = HOSTID;
pseudo.blk.portdest = NETWORKID; /* Need to swap to get in
correct order */
pseudo.blk.portsrc = DSPAIRID;
pseudo.blk.sh_str_id = 0;
pseudo.blk.control = 0;
pseudo.blk.rsvd1 = 0;
pseudo.blk.seq_num = 0;
pseudo.blk.rsvd2 = pcmcia->packetseqnum++;
pseudo.blk.qos_class = 0;
/* Calculate pseudo header checksum */
pseudo.blk.checksum = pseudo.buff[0];
for (i = 1; i < 7; i++)
pseudo.blk.checksum ^= pseudo.buff[i];
/* Production Mode */
if (info->AsicID == ELECTRABUZZ_ID) {
/* copy first word to UFIFO_BEG reg */
ft1000_write_reg(dev, FT1000_REG_UFIFO_BEG, pseudo.buff[0]);
pr_debug("data 0 BEG = 0x%04x\n", pseudo.buff[0]);
/* copy subsequent words to UFIFO_MID reg */
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[1]);
pr_debug("data 1 MID = 0x%04x\n", pseudo.buff[1]);
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[2]);
pr_debug("data 2 MID = 0x%04x\n", pseudo.buff[2]);
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[3]);
pr_debug("data 3 MID = 0x%04x\n", pseudo.buff[3]);
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[4]);
pr_debug("data 4 MID = 0x%04x\n", pseudo.buff[4]);
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[5]);
pr_debug("data 5 MID = 0x%04x\n", pseudo.buff[5]);
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[6]);
pr_debug("data 6 MID = 0x%04x\n", pseudo.buff[6]);
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID, pseudo.buff[7]);
pr_debug("data 7 MID = 0x%04x\n", pseudo.buff[7]);
/* Write PPP type + IP Packet into Downlink FIFO */
for (i = 0; i < (len >> 1) - 1; i++) {
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID,
htons(*packet));
pr_debug("data %d MID = 0x%04x\n",
i + 8, htons(*packet));
packet++;
}
/* Check for odd byte */
if (len & 0x0001) {
ft1000_write_reg(dev, FT1000_REG_UFIFO_MID,
htons(*packet));
pr_debug("data MID = 0x%04x\n", htons(*packet));
packet++;
ft1000_write_reg(dev, FT1000_REG_UFIFO_END,
htons(*packet));
pr_debug("data %d MID = 0x%04x\n",
i + 8, htons(*packet));
} else {
ft1000_write_reg(dev, FT1000_REG_UFIFO_END,
htons(*packet));
pr_debug("data %d MID = 0x%04x\n",
i + 8, htons(*packet));
}
} else {
outl(*(u32 *)&pseudo.buff[0],
dev->base_addr + FT1000_REG_MAG_UFDR);
pr_debug("Pseudo = 0x%8x\n", *(u32 *)&pseudo.buff[0]);
outl(*(u32 *)&pseudo.buff[2],
dev->base_addr + FT1000_REG_MAG_UFDR);
pr_debug("Pseudo = 0x%8x\n", *(u32 *)&pseudo.buff[2]);
outl(*(u32 *)&pseudo.buff[4],
dev->base_addr + FT1000_REG_MAG_UFDR);
pr_debug("Pseudo = 0x%8x\n", *(u32 *)&pseudo.buff[4]);
outl(*(u32 *)&pseudo.buff[6],
dev->base_addr + FT1000_REG_MAG_UFDR);
pr_debug("Pseudo = 0x%8x\n", *(u32 *)&pseudo.buff[6]);
plong = (u32 *)packet;
/* Write PPP type + IP Packet into Downlink FIFO */
for (i = 0; i < (len >> 2); i++)
outl(*plong++, dev->base_addr + FT1000_REG_MAG_UFDR);
/* Check for odd alignment */
if (len & 0x0003) {
pr_debug("data = 0x%8x\n", *plong);
outl(*plong++, dev->base_addr + FT1000_REG_MAG_UFDR);
}
outl(1, dev->base_addr + FT1000_REG_MAG_UFER);
}
info->stats.tx_packets++;
/* Add 14 bytes for MAC address plus ethernet type */
info->stats.tx_bytes += (len + 14);
return SUCCESS;
}
static struct net_device_stats *ft1000_stats(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
return &info->stats;
}
static int ft1000_open(struct net_device *dev)
{
ft1000_reset_card(dev);
/* schedule ft1000_hbchk to perform periodic heartbeat checks on DSP
* and ASIC */
init_timer(&poll_timer);
poll_timer.expires = jiffies + (2 * HZ);
poll_timer.data = (u_long)dev;
add_timer(&poll_timer);
return 0;
}
static int ft1000_close(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
info->CardReady = 0;
del_timer(&poll_timer);
if (ft1000_card_present == 1) {
pr_debug("Media is down\n");
netif_stop_queue(dev);
ft1000_disable_interrupts(dev);
ft1000_write_reg(dev, FT1000_REG_RESET, DSP_RESET_BIT);
/* reset ASIC */
ft1000_reset_asic(dev);
}
return 0;
}
static int ft1000_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
u8 *pdata;
if (skb == NULL) {
pr_debug("skb == NULL!!!\n");
return 0;
}
pr_debug("length of packet = %d\n", skb->len);
pdata = (u8 *)skb->data;
if (info->mediastate == 0) {
/* Drop packet is mediastate is down */
pr_debug("mediastate is down\n");
return SUCCESS;
}
if ((skb->len < ENET_HEADER_SIZE) || (skb->len > ENET_MAX_SIZE)) {
/* Drop packet which has invalid size */
pr_debug("invalid ethernet length\n");
return SUCCESS;
}
ft1000_copy_down_pkt(dev, (u16 *) (pdata + ENET_HEADER_SIZE - 2),
skb->len - ENET_HEADER_SIZE + 2);
dev_kfree_skb(skb);
return 0;
}
static irqreturn_t ft1000_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct ft1000_info *info = netdev_priv(dev);
u16 tempword;
u16 inttype;
int cnt;
if (info->CardReady == 0) {
ft1000_disable_interrupts(dev);
return IRQ_HANDLED;
}
if (ft1000_chkcard(dev) == false) {
ft1000_disable_interrupts(dev);
return IRQ_HANDLED;
}
ft1000_disable_interrupts(dev);
/* Read interrupt type */
inttype = ft1000_read_reg(dev, FT1000_REG_SUP_ISR);
/* Make sure we process all interrupt before leaving the ISR due to the
* edge trigger interrupt type */
while (inttype) {
if (inttype & ISR_DOORBELL_PEND)
ft1000_parse_dpram_msg(dev);
if (inttype & ISR_RCV) {
pr_debug("Data in FIFO\n");
cnt = 0;
do {
/* Check if we have packets in the Downlink
* FIFO */
if (info->AsicID == ELECTRABUZZ_ID) {
tempword = ft1000_read_reg(dev,
FT1000_REG_DFIFO_STAT);
} else {
tempword = ft1000_read_reg(dev,
FT1000_REG_MAG_DFSR);
}
if (!(tempword & 0x1f))
break;
ft1000_copy_up_pkt(dev);
cnt++;
} while (cnt < MAX_RCV_LOOP);
}
/* clear interrupts */
tempword = ft1000_read_reg(dev, FT1000_REG_SUP_ISR);
pr_debug("interrupt status register = 0x%x\n", tempword);
ft1000_write_reg(dev, FT1000_REG_SUP_ISR, tempword);
/* Read interrupt type */
inttype = ft1000_read_reg(dev, FT1000_REG_SUP_ISR);
pr_debug("interrupt status register after clear = 0x%x\n",
inttype);
}
ft1000_enable_interrupts(dev);
return IRQ_HANDLED;
}
void stop_ft1000_card(struct net_device *dev)
{
struct ft1000_info *info = netdev_priv(dev);
struct prov_record *ptr;
struct prov_record *tmp;
/* int cnt; */
info->CardReady = 0;
ft1000_card_present = 0;
netif_stop_queue(dev);
ft1000_disable_interrupts(dev);
/* Make sure we free any memory reserve for provisioning */
list_for_each_entry_safe(ptr, tmp, &info->prov_list, list) {
list_del(&ptr->list);
kfree(ptr->pprov_data);
kfree(ptr);
}
kfree(info->priv);
if (info->registered) {
unregister_netdev(dev);
info->registered = 0;
}
free_irq(dev->irq, dev);
release_region(dev->base_addr, 256);
release_firmware(fw_entry);
flarion_ft1000_cnt--;
}
static void ft1000_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
struct ft1000_info *ft_info;
ft_info = netdev_priv(dev);
strlcpy(info->driver, "ft1000", sizeof(info->driver));
snprintf(info->bus_info, sizeof(info->bus_info), "PCMCIA 0x%lx",
dev->base_addr);
snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d.%d.%d",
ft_info->DspVer[0], ft_info->DspVer[1], ft_info->DspVer[2],
ft_info->DspVer[3]);
}
static u32 ft1000_get_link(struct net_device *dev)
{
struct ft1000_info *info;
info = netdev_priv(dev);
return info->mediastate;
}
static const struct ethtool_ops ops = {
.get_drvinfo = ft1000_get_drvinfo,
.get_link = ft1000_get_link
};
struct net_device *init_ft1000_card(struct pcmcia_device *link,
void *ft1000_reset)
{
struct ft1000_info *info;
struct ft1000_pcmcia *pcmcia;
struct net_device *dev;
static const struct net_device_ops ft1000ops = {
.ndo_open = &ft1000_open,
.ndo_stop = &ft1000_close,
.ndo_start_xmit = &ft1000_start_xmit,
.ndo_get_stats = &ft1000_stats,
};
pr_debug("irq = %d, port = 0x%04llx\n",
link->irq, (unsigned long long)link->resource[0]->start);
flarion_ft1000_cnt++;
if (flarion_ft1000_cnt > 1) {
flarion_ft1000_cnt--;
dev_info(&link->dev,
"This driver can not support more than one instance\n");
return NULL;
}
dev = alloc_etherdev(sizeof(struct ft1000_info));
if (!dev) {
dev_err(&link->dev, "Failed to allocate etherdev\n");
return NULL;
}
SET_NETDEV_DEV(dev, &link->dev);
info = netdev_priv(dev);
memset(info, 0, sizeof(struct ft1000_info));
pr_debug("address of dev = 0x%p\n", dev);
pr_debug("address of dev info = 0x%p\n", info);
pr_debug("device name = %s\n", dev->name);
memset(&info->stats, 0, sizeof(struct net_device_stats));
info->priv = kzalloc(sizeof(struct ft1000_pcmcia), GFP_KERNEL);
pcmcia = info->priv;
pcmcia->link = link;
spin_lock_init(&info->dpram_lock);
info->DrvErrNum = 0;
info->registered = 1;
info->ft1000_reset = ft1000_reset;
info->mediastate = 0;
info->fifo_cnt = 0;
info->CardReady = 0;
info->DSP_TIME[0] = 0;
info->DSP_TIME[1] = 0;
info->DSP_TIME[2] = 0;
info->DSP_TIME[3] = 0;
flarion_ft1000_cnt = 0;
INIT_LIST_HEAD(&info->prov_list);
info->squeseqnum = 0;
/* dev->hard_start_xmit = &ft1000_start_xmit; */
/* dev->get_stats = &ft1000_stats; */
/* dev->open = &ft1000_open; */
/* dev->stop = &ft1000_close; */
dev->netdev_ops = &ft1000ops;
pr_debug("device name = %s\n", dev->name);
dev->irq = link->irq;
dev->base_addr = link->resource[0]->start;
if (pcmcia_get_mac_from_cis(link, dev)) {
netdev_err(dev, "Could not read mac address\n");
goto err_dev;
}
if (request_irq(dev->irq, ft1000_interrupt, IRQF_SHARED, dev->name,
dev)) {
netdev_err(dev, "Could not request_irq\n");
goto err_dev;
}
if (request_region(dev->base_addr, 256, dev->name) == NULL) {
netdev_err(dev, "Could not request_region\n");
goto err_irq;
}
if (register_netdev(dev)) {
pr_debug("Could not register netdev\n");
goto err_reg;
}
info->AsicID = ft1000_read_reg(dev, FT1000_REG_ASIC_ID);
if (info->AsicID == ELECTRABUZZ_ID) {
pr_debug("ELECTRABUZZ ASIC\n");
if (request_firmware(&fw_entry, "ft1000.img",
&link->dev) != 0) {
pr_info("Could not open ft1000.img\n");
goto err_unreg;
}
} else {
pr_debug("MAGNEMITE ASIC\n");
if (request_firmware(&fw_entry, "ft2000.img",
&link->dev) != 0) {
pr_info("Could not open ft2000.img\n");
goto err_unreg;
}
}
ft1000_enable_interrupts(dev);
ft1000_card_present = 1;
dev->ethtool_ops = &ops;
pr_info("%s: addr 0x%04lx irq %d, MAC addr %pM\n",
dev->name, dev->base_addr, dev->irq, dev->dev_addr);
return dev;
err_unreg:
unregister_netdev(dev);
err_reg:
release_region(dev->base_addr, 256);
err_irq:
free_irq(dev->irq, dev);
err_dev:
free_netdev(dev);
return NULL;
}
| gpl-2.0 |
Umang88/Radon-Kenzo | arch/arm/mach-realview/realview_pbx.c | 1382 | 11358 | /*
* arch/arm/mach-realview/realview_pbx.c
*
* Copyright (C) 2009 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/amba/mmci.h>
#include <linux/amba/pl022.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/platform_data/clk-realview.h>
#include <linux/reboot.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/smp_twd.h>
#include <asm/pgtable.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/board-pbx.h>
#include <mach/irqs.h>
#include "core.h"
static struct map_desc realview_pbx_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
.pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_GIC_CPU_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_GIC_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_TIMER0_1_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_TIMER2_3_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
},
#ifdef CONFIG_PCI
{
.virtual = PCIX_UNIT_BASE,
.pfn = __phys_to_pfn(REALVIEW_PBX_PCI_BASE),
.length = REALVIEW_PBX_PCI_BASE_SIZE,
.type = MT_DEVICE,
},
#endif
#ifdef CONFIG_DEBUG_LL
{
.virtual = IO_ADDRESS(REALVIEW_PBX_UART0_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_UART0_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
},
#endif
};
static struct map_desc realview_local_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_TILE_SCU_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE),
.pfn = __phys_to_pfn(REALVIEW_PBX_TILE_L220_BASE),
.length = SZ_8K,
.type = MT_DEVICE,
}
};
static void __init realview_pbx_map_io(void)
{
iotable_init(realview_pbx_io_desc, ARRAY_SIZE(realview_pbx_io_desc));
if (core_tile_pbx11mp() || core_tile_pbxa9mp())
iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
}
static struct pl061_platform_data gpio0_plat_data = {
.gpio_base = 0,
};
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
};
static struct pl061_platform_data gpio2_plat_data = {
.gpio_base = 16,
};
static struct pl022_ssp_controller ssp0_plat_data = {
.bus_id = 0,
.enable_dma = 0,
.num_chipselect = 1,
};
/*
* RealView PBXCore AMBA devices
*/
#define GPIO2_IRQ { IRQ_PBX_GPIO2 }
#define GPIO3_IRQ { IRQ_PBX_GPIO3 }
#define AACI_IRQ { IRQ_PBX_AACI }
#define MMCI0_IRQ { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
#define KMI0_IRQ { IRQ_PBX_KMI0 }
#define KMI1_IRQ { IRQ_PBX_KMI1 }
#define PBX_SMC_IRQ { }
#define MPMC_IRQ { }
#define PBX_CLCD_IRQ { IRQ_PBX_CLCD }
#define DMAC_IRQ { IRQ_PBX_DMAC }
#define SCTL_IRQ { }
#define PBX_WATCHDOG_IRQ { IRQ_PBX_WATCHDOG }
#define PBX_GPIO0_IRQ { IRQ_PBX_GPIO0 }
#define GPIO1_IRQ { IRQ_PBX_GPIO1 }
#define PBX_RTC_IRQ { IRQ_PBX_RTC }
#define SCI_IRQ { IRQ_PBX_SCI }
#define PBX_UART0_IRQ { IRQ_PBX_UART0 }
#define PBX_UART1_IRQ { IRQ_PBX_UART1 }
#define PBX_UART2_IRQ { IRQ_PBX_UART2 }
#define PBX_UART3_IRQ { IRQ_PBX_UART3 }
#define PBX_SSP_IRQ { IRQ_PBX_SSP }
/* FPGA Primecells */
APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
APB_DEVICE(uart3, "fpga:uart3", PBX_UART3, NULL);
/* DevChip Primecells */
AHB_DEVICE(smc, "dev:smc", PBX_SMC, NULL);
AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
APB_DEVICE(wdog, "dev:wdog", PBX_WATCHDOG, NULL);
APB_DEVICE(gpio0, "dev:gpio0", PBX_GPIO0, &gpio0_plat_data);
APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
APB_DEVICE(rtc, "dev:rtc", PBX_RTC, NULL);
APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
APB_DEVICE(uart0, "dev:uart0", PBX_UART0, NULL);
APB_DEVICE(uart1, "dev:uart1", PBX_UART1, NULL);
APB_DEVICE(uart2, "dev:uart2", PBX_UART2, NULL);
APB_DEVICE(ssp0, "dev:ssp0", PBX_SSP, &ssp0_plat_data);
/* Primecells on the NEC ISSP chip */
AHB_DEVICE(clcd, "issp:clcd", PBX_CLCD, &clcd_plat_data);
AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
static struct amba_device *amba_devs[] __initdata = {
&dmac_device,
&uart0_device,
&uart1_device,
&uart2_device,
&uart3_device,
&smc_device,
&clcd_device,
&sctl_device,
&wdog_device,
&gpio0_device,
&gpio1_device,
&gpio2_device,
&rtc_device,
&sci0_device,
&ssp0_device,
&aaci_device,
&mmc0_device,
&kmi0_device,
&kmi1_device,
};
/*
* RealView PB-X platform devices
*/
static struct resource realview_pbx_flash_resources[] = {
[0] = {
.start = REALVIEW_PBX_FLASH0_BASE,
.end = REALVIEW_PBX_FLASH0_BASE + REALVIEW_PBX_FLASH0_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = REALVIEW_PBX_FLASH1_BASE,
.end = REALVIEW_PBX_FLASH1_BASE + REALVIEW_PBX_FLASH1_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct resource realview_pbx_smsc911x_resources[] = {
[0] = {
.start = REALVIEW_PBX_ETH_BASE,
.end = REALVIEW_PBX_ETH_BASE + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PBX_ETH,
.end = IRQ_PBX_ETH,
.flags = IORESOURCE_IRQ,
},
};
static struct resource realview_pbx_isp1761_resources[] = {
[0] = {
.start = REALVIEW_PBX_USB_BASE,
.end = REALVIEW_PBX_USB_BASE + SZ_128K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PBX_USB,
.end = IRQ_PBX_USB,
.flags = IORESOURCE_IRQ,
},
};
static struct resource pmu_resources[] = {
[0] = {
.start = IRQ_PBX_PMU_CPU0,
.end = IRQ_PBX_PMU_CPU0,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = IRQ_PBX_PMU_CPU1,
.end = IRQ_PBX_PMU_CPU1,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_PBX_PMU_CPU2,
.end = IRQ_PBX_PMU_CPU2,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_PBX_PMU_CPU3,
.end = IRQ_PBX_PMU_CPU3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pmu_device = {
.name = "arm-pmu",
.id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
static void __init gic_init_irq(void)
{
/* ARM PBX on-board GIC */
if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
__io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
} else {
gic_init(0, IRQ_PBX_GIC_START,
__io_address(REALVIEW_PBX_GIC_DIST_BASE),
__io_address(REALVIEW_PBX_GIC_CPU_BASE));
}
}
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
REALVIEW_PBX_TILE_TWD_BASE,
IRQ_LOCALTIMER);
static void __init realview_pbx_twd_init(void)
{
int err = twd_local_timer_register(&twd_local_timer);
if (err)
pr_err("twd_local_timer_register failed %d\n", err);
}
#else
#define realview_pbx_twd_init() do { } while(0)
#endif
static void __init realview_pbx_timer_init(void)
{
timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
timer1_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE) + 0x20;
timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
realview_timer_init(IRQ_PBX_TIMER0_1);
realview_pbx_twd_init();
}
static void realview_pbx_fixup(struct tag *tags, char **from,
struct meminfo *meminfo)
{
#ifdef CONFIG_SPARSEMEM
/*
* Memory configuration with SPARSEMEM enabled on RealView PBX (see
* asm/mach/memory.h for more information).
*/
meminfo->bank[0].start = 0;
meminfo->bank[0].size = SZ_256M;
meminfo->bank[1].start = 0x20000000;
meminfo->bank[1].size = SZ_512M;
meminfo->bank[2].start = 0x80000000;
meminfo->bank[2].size = SZ_256M;
meminfo->nr_banks = 3;
#else
realview_fixup(tags, from, meminfo);
#endif
}
static void realview_pbx_restart(enum reboot_mode mode, const char *cmd)
{
void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
/*
* To reset, we hit the on-board reset register
* in the system FPGA
*/
__raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
__raw_writel(0x00F0, reset_ctrl);
__raw_writel(0x00F4, reset_ctrl);
dsb();
}
static void __init realview_pbx_init(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
if (core_tile_pbxa9mp()) {
void __iomem *l2x0_base =
__io_address(REALVIEW_PBX_TILE_L220_BASE);
/* set RAM latencies to 1 cycle for eASIC */
writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
/* 16KB way size, 8-way associativity, parity disabled
* Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
platform_device_register(&pmu_device);
}
#endif
realview_flash_register(realview_pbx_flash_resources,
ARRAY_SIZE(realview_pbx_flash_resources));
realview_eth_register(NULL, realview_pbx_smsc911x_resources);
platform_device_register(&realview_i2c_device);
platform_device_register(&realview_cf_device);
realview_usb_register(realview_pbx_isp1761_resources);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
}
MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.atag_offset = 0x100,
.smp = smp_ops(realview_smp_ops),
.fixup = realview_pbx_fixup,
.map_io = realview_pbx_map_io,
.init_early = realview_init_early,
.init_irq = gic_init_irq,
.init_time = realview_pbx_timer_init,
.init_machine = realview_pbx_init,
#ifdef CONFIG_ZONE_DMA
.dma_zone_size = SZ_256M,
#endif
.restart = realview_pbx_restart,
MACHINE_END
| gpl-2.0 |
CyanogenMod/android_kernel_asus_moorefield | fs/xfs/xfs_error.c | 2150 | 4073 | /*
* Copyright (c) 2000-2001,2005 Silicon Graphics, Inc.
* All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "xfs.h"
#include "xfs_fs.h"
#include "xfs_types.h"
#include "xfs_log.h"
#include "xfs_trans.h"
#include "xfs_sb.h"
#include "xfs_ag.h"
#include "xfs_mount.h"
#include "xfs_bmap_btree.h"
#include "xfs_dinode.h"
#include "xfs_inode.h"
#include "xfs_utils.h"
#include "xfs_error.h"
#ifdef DEBUG
int xfs_etrap[XFS_ERROR_NTRAP] = {
0,
};
int
xfs_error_trap(int e)
{
int i;
if (!e)
return 0;
for (i = 0; i < XFS_ERROR_NTRAP; i++) {
if (xfs_etrap[i] == 0)
break;
if (e != xfs_etrap[i])
continue;
xfs_notice(NULL, "%s: error %d", __func__, e);
BUG();
break;
}
return e;
}
int xfs_etest[XFS_NUM_INJECT_ERROR];
int64_t xfs_etest_fsid[XFS_NUM_INJECT_ERROR];
char * xfs_etest_fsname[XFS_NUM_INJECT_ERROR];
int xfs_error_test_active;
int
xfs_error_test(int error_tag, int *fsidp, char *expression,
int line, char *file, unsigned long randfactor)
{
int i;
int64_t fsid;
if (prandom_u32() % randfactor)
return 0;
memcpy(&fsid, fsidp, sizeof(xfs_fsid_t));
for (i = 0; i < XFS_NUM_INJECT_ERROR; i++) {
if (xfs_etest[i] == error_tag && xfs_etest_fsid[i] == fsid) {
xfs_warn(NULL,
"Injecting error (%s) at file %s, line %d, on filesystem \"%s\"",
expression, file, line, xfs_etest_fsname[i]);
return 1;
}
}
return 0;
}
int
xfs_errortag_add(int error_tag, xfs_mount_t *mp)
{
int i;
int len;
int64_t fsid;
memcpy(&fsid, mp->m_fixedfsid, sizeof(xfs_fsid_t));
for (i = 0; i < XFS_NUM_INJECT_ERROR; i++) {
if (xfs_etest_fsid[i] == fsid && xfs_etest[i] == error_tag) {
xfs_warn(mp, "error tag #%d on", error_tag);
return 0;
}
}
for (i = 0; i < XFS_NUM_INJECT_ERROR; i++) {
if (xfs_etest[i] == 0) {
xfs_warn(mp, "Turned on XFS error tag #%d",
error_tag);
xfs_etest[i] = error_tag;
xfs_etest_fsid[i] = fsid;
len = strlen(mp->m_fsname);
xfs_etest_fsname[i] = kmem_alloc(len + 1, KM_SLEEP);
strcpy(xfs_etest_fsname[i], mp->m_fsname);
xfs_error_test_active++;
return 0;
}
}
xfs_warn(mp, "error tag overflow, too many turned on");
return 1;
}
int
xfs_errortag_clearall(xfs_mount_t *mp, int loud)
{
int64_t fsid;
int cleared = 0;
int i;
memcpy(&fsid, mp->m_fixedfsid, sizeof(xfs_fsid_t));
for (i = 0; i < XFS_NUM_INJECT_ERROR; i++) {
if ((fsid == 0LL || xfs_etest_fsid[i] == fsid) &&
xfs_etest[i] != 0) {
cleared = 1;
xfs_warn(mp, "Clearing XFS error tag #%d",
xfs_etest[i]);
xfs_etest[i] = 0;
xfs_etest_fsid[i] = 0LL;
kmem_free(xfs_etest_fsname[i]);
xfs_etest_fsname[i] = NULL;
xfs_error_test_active--;
}
}
if (loud || cleared)
xfs_warn(mp, "Cleared all XFS error tags for filesystem");
return 0;
}
#endif /* DEBUG */
void
xfs_error_report(
const char *tag,
int level,
struct xfs_mount *mp,
const char *filename,
int linenum,
inst_t *ra)
{
if (level <= xfs_error_level) {
xfs_alert_tag(mp, XFS_PTAG_ERROR_REPORT,
"Internal error %s at line %d of file %s. Caller 0x%p\n",
tag, linenum, filename, ra);
xfs_stack_trace();
}
}
void
xfs_corruption_error(
const char *tag,
int level,
struct xfs_mount *mp,
void *p,
const char *filename,
int linenum,
inst_t *ra)
{
if (level <= xfs_error_level)
xfs_hex_dump(p, 64);
xfs_error_report(tag, level, mp, filename, linenum, ra);
xfs_alert(mp, "Corruption detected. Unmount and run xfs_repair");
}
| gpl-2.0 |
shminer/LG-F460-Kernel | tools/perf/builtin-mem.c | 2150 | 5933 | #include "builtin.h"
#include "perf.h"
#include "util/parse-options.h"
#include "util/trace-event.h"
#include "util/tool.h"
#include "util/session.h"
#define MEM_OPERATION_LOAD "load"
#define MEM_OPERATION_STORE "store"
static const char *mem_operation = MEM_OPERATION_LOAD;
struct perf_mem {
struct perf_tool tool;
char const *input_name;
symbol_filter_t annotate_init;
bool hide_unresolved;
bool dump_raw;
const char *cpu_list;
DECLARE_BITMAP(cpu_bitmap, MAX_NR_CPUS);
};
static const char * const mem_usage[] = {
"perf mem [<options>] {record <command> |report}",
NULL
};
static int __cmd_record(int argc, const char **argv)
{
int rec_argc, i = 0, j;
const char **rec_argv;
char event[64];
int ret;
rec_argc = argc + 4;
rec_argv = calloc(rec_argc + 1, sizeof(char *));
if (!rec_argv)
return -1;
rec_argv[i++] = strdup("record");
if (!strcmp(mem_operation, MEM_OPERATION_LOAD))
rec_argv[i++] = strdup("-W");
rec_argv[i++] = strdup("-d");
rec_argv[i++] = strdup("-e");
if (strcmp(mem_operation, MEM_OPERATION_LOAD))
sprintf(event, "cpu/mem-stores/pp");
else
sprintf(event, "cpu/mem-loads/pp");
rec_argv[i++] = strdup(event);
for (j = 1; j < argc; j++, i++)
rec_argv[i] = argv[j];
ret = cmd_record(i, rec_argv, NULL);
free(rec_argv);
return ret;
}
static int
dump_raw_samples(struct perf_tool *tool,
union perf_event *event,
struct perf_sample *sample,
struct perf_evsel *evsel __maybe_unused,
struct machine *machine)
{
struct perf_mem *mem = container_of(tool, struct perf_mem, tool);
struct addr_location al;
const char *fmt;
if (perf_event__preprocess_sample(event, machine, &al, sample,
mem->annotate_init) < 0) {
fprintf(stderr, "problem processing %d event, skipping it.\n",
event->header.type);
return -1;
}
if (al.filtered || (mem->hide_unresolved && al.sym == NULL))
return 0;
if (al.map != NULL)
al.map->dso->hit = 1;
if (symbol_conf.field_sep) {
fmt = "%d%s%d%s0x%"PRIx64"%s0x%"PRIx64"%s%"PRIu64
"%s0x%"PRIx64"%s%s:%s\n";
} else {
fmt = "%5d%s%5d%s0x%016"PRIx64"%s0x016%"PRIx64
"%s%5"PRIu64"%s0x%06"PRIx64"%s%s:%s\n";
symbol_conf.field_sep = " ";
}
printf(fmt,
sample->pid,
symbol_conf.field_sep,
sample->tid,
symbol_conf.field_sep,
event->ip.ip,
symbol_conf.field_sep,
sample->addr,
symbol_conf.field_sep,
sample->weight,
symbol_conf.field_sep,
sample->data_src,
symbol_conf.field_sep,
al.map ? (al.map->dso ? al.map->dso->long_name : "???") : "???",
al.sym ? al.sym->name : "???");
return 0;
}
static int process_sample_event(struct perf_tool *tool,
union perf_event *event,
struct perf_sample *sample,
struct perf_evsel *evsel,
struct machine *machine)
{
return dump_raw_samples(tool, event, sample, evsel, machine);
}
static int report_raw_events(struct perf_mem *mem)
{
int err = -EINVAL;
int ret;
struct perf_session *session = perf_session__new(input_name, O_RDONLY,
0, false, &mem->tool);
if (session == NULL)
return -ENOMEM;
if (mem->cpu_list) {
ret = perf_session__cpu_bitmap(session, mem->cpu_list,
mem->cpu_bitmap);
if (ret)
goto out_delete;
}
if (symbol__init() < 0)
return -1;
printf("# PID, TID, IP, ADDR, LOCAL WEIGHT, DSRC, SYMBOL\n");
err = perf_session__process_events(session, &mem->tool);
if (err)
return err;
return 0;
out_delete:
perf_session__delete(session);
return err;
}
static int report_events(int argc, const char **argv, struct perf_mem *mem)
{
const char **rep_argv;
int ret, i = 0, j, rep_argc;
if (mem->dump_raw)
return report_raw_events(mem);
rep_argc = argc + 3;
rep_argv = calloc(rep_argc + 1, sizeof(char *));
if (!rep_argv)
return -1;
rep_argv[i++] = strdup("report");
rep_argv[i++] = strdup("--mem-mode");
rep_argv[i++] = strdup("-n"); /* display number of samples */
/*
* there is no weight (cost) associated with stores, so don't print
* the column
*/
if (strcmp(mem_operation, MEM_OPERATION_LOAD))
rep_argv[i++] = strdup("--sort=mem,sym,dso,symbol_daddr,"
"dso_daddr,tlb,locked");
for (j = 1; j < argc; j++, i++)
rep_argv[i] = argv[j];
ret = cmd_report(i, rep_argv, NULL);
free(rep_argv);
return ret;
}
int cmd_mem(int argc, const char **argv, const char *prefix __maybe_unused)
{
struct stat st;
struct perf_mem mem = {
.tool = {
.sample = process_sample_event,
.mmap = perf_event__process_mmap,
.comm = perf_event__process_comm,
.lost = perf_event__process_lost,
.fork = perf_event__process_fork,
.build_id = perf_event__process_build_id,
.ordered_samples = true,
},
.input_name = "perf.data",
};
const struct option mem_options[] = {
OPT_STRING('t', "type", &mem_operation,
"type", "memory operations(load/store)"),
OPT_BOOLEAN('D', "dump-raw-samples", &mem.dump_raw,
"dump raw samples in ASCII"),
OPT_BOOLEAN('U', "hide-unresolved", &mem.hide_unresolved,
"Only display entries resolved to a symbol"),
OPT_STRING('i', "input", &input_name, "file",
"input file name"),
OPT_STRING('C', "cpu", &mem.cpu_list, "cpu",
"list of cpus to profile"),
OPT_STRING('x', "field-separator", &symbol_conf.field_sep,
"separator",
"separator for columns, no spaces will be added"
" between columns '.' is reserved."),
OPT_END()
};
argc = parse_options(argc, argv, mem_options, mem_usage,
PARSE_OPT_STOP_AT_NON_OPTION);
if (!argc || !(strncmp(argv[0], "rec", 3) || mem_operation))
usage_with_options(mem_usage, mem_options);
if (!mem.input_name || !strlen(mem.input_name)) {
if (!fstat(STDIN_FILENO, &st) && S_ISFIFO(st.st_mode))
mem.input_name = "-";
else
mem.input_name = "perf.data";
}
if (!strncmp(argv[0], "rec", 3))
return __cmd_record(argc, argv);
else if (!strncmp(argv[0], "rep", 3))
return report_events(argc, argv, &mem);
else
usage_with_options(mem_usage, mem_options);
return 0;
}
| gpl-2.0 |
balika011/android_kernel_xiaomi_kenzo | drivers/gpu/drm/drm_sysfs.c | 2150 | 14980 |
/*
* drm_sysfs.c - Modifications to drm_sysfs_class.c to support
* extra sysfs attribute from DRM. Normal drm_sysfs_class
* does not allow adding attributes.
*
* Copyright (c) 2004 Jon Smirl <jonsmirl@gmail.com>
* Copyright (c) 2003-2004 Greg Kroah-Hartman <greg@kroah.com>
* Copyright (c) 2003-2004 IBM Corp.
*
* This file is released under the GPLv2
*
*/
#include <linux/device.h>
#include <linux/kdev_t.h>
#include <linux/gfp.h>
#include <linux/err.h>
#include <linux/export.h>
#include <drm/drm_sysfs.h>
#include <drm/drm_core.h>
#include <drm/drmP.h>
#define to_drm_minor(d) container_of(d, struct drm_minor, kdev)
#define to_drm_connector(d) container_of(d, struct drm_connector, kdev)
static struct device_type drm_sysfs_device_minor = {
.name = "drm_minor"
};
/**
* drm_class_suspend - DRM class suspend hook
* @dev: Linux device to suspend
* @state: power state to enter
*
* Just figures out what the actual struct drm_device associated with
* @dev is and calls its suspend hook, if present.
*/
static int drm_class_suspend(struct device *dev, pm_message_t state)
{
if (dev->type == &drm_sysfs_device_minor) {
struct drm_minor *drm_minor = to_drm_minor(dev);
struct drm_device *drm_dev = drm_minor->dev;
if (drm_minor->type == DRM_MINOR_LEGACY &&
!drm_core_check_feature(drm_dev, DRIVER_MODESET) &&
drm_dev->driver->suspend)
return drm_dev->driver->suspend(drm_dev, state);
}
return 0;
}
/**
* drm_class_resume - DRM class resume hook
* @dev: Linux device to resume
*
* Just figures out what the actual struct drm_device associated with
* @dev is and calls its resume hook, if present.
*/
static int drm_class_resume(struct device *dev)
{
if (dev->type == &drm_sysfs_device_minor) {
struct drm_minor *drm_minor = to_drm_minor(dev);
struct drm_device *drm_dev = drm_minor->dev;
if (drm_minor->type == DRM_MINOR_LEGACY &&
!drm_core_check_feature(drm_dev, DRIVER_MODESET) &&
drm_dev->driver->resume)
return drm_dev->driver->resume(drm_dev);
}
return 0;
}
static char *drm_devnode(struct device *dev, umode_t *mode)
{
return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev));
}
static CLASS_ATTR_STRING(version, S_IRUGO,
CORE_NAME " "
__stringify(CORE_MAJOR) "."
__stringify(CORE_MINOR) "."
__stringify(CORE_PATCHLEVEL) " "
CORE_DATE);
/**
* drm_sysfs_create - create a struct drm_sysfs_class structure
* @owner: pointer to the module that is to "own" this struct drm_sysfs_class
* @name: pointer to a string for the name of this class.
*
* This is used to create DRM class pointer that can then be used
* in calls to drm_sysfs_device_add().
*
* Note, the pointer created here is to be destroyed when finished by making a
* call to drm_sysfs_destroy().
*/
struct class *drm_sysfs_create(struct module *owner, char *name)
{
struct class *class;
int err;
class = class_create(owner, name);
if (IS_ERR(class)) {
err = PTR_ERR(class);
goto err_out;
}
class->suspend = drm_class_suspend;
class->resume = drm_class_resume;
err = class_create_file(class, &class_attr_version.attr);
if (err)
goto err_out_class;
class->devnode = drm_devnode;
return class;
err_out_class:
class_destroy(class);
err_out:
return ERR_PTR(err);
}
/**
* drm_sysfs_destroy - destroys DRM class
*
* Destroy the DRM device class.
*/
void drm_sysfs_destroy(void)
{
if ((drm_class == NULL) || (IS_ERR(drm_class)))
return;
class_remove_file(drm_class, &class_attr_version.attr);
class_destroy(drm_class);
drm_class = NULL;
}
/**
* drm_sysfs_device_release - do nothing
* @dev: Linux device
*
* Normally, this would free the DRM device associated with @dev, along
* with cleaning up any other stuff. But we do that in the DRM core, so
* this function can just return and hope that the core does its job.
*/
static void drm_sysfs_device_release(struct device *dev)
{
memset(dev, 0, sizeof(struct device));
return;
}
/*
* Connector properties
*/
static ssize_t status_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
enum drm_connector_status status;
int ret;
ret = mutex_lock_interruptible(&connector->dev->mode_config.mutex);
if (ret)
return ret;
status = connector->funcs->detect(connector, true);
mutex_unlock(&connector->dev->mode_config.mutex);
return snprintf(buf, PAGE_SIZE, "%s\n",
drm_get_connector_status_name(status));
}
static ssize_t dpms_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
struct drm_device *dev = connector->dev;
uint64_t dpms_status;
int ret;
ret = drm_object_property_get_value(&connector->base,
dev->mode_config.dpms_property,
&dpms_status);
if (ret)
return 0;
return snprintf(buf, PAGE_SIZE, "%s\n",
drm_get_dpms_name((int)dpms_status));
}
static ssize_t enabled_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
return snprintf(buf, PAGE_SIZE, "%s\n", connector->encoder ? "enabled" :
"disabled");
}
static ssize_t edid_show(struct file *filp, struct kobject *kobj,
struct bin_attribute *attr, char *buf, loff_t off,
size_t count)
{
struct device *connector_dev = container_of(kobj, struct device, kobj);
struct drm_connector *connector = to_drm_connector(connector_dev);
unsigned char *edid;
size_t size;
if (!connector->edid_blob_ptr)
return 0;
edid = connector->edid_blob_ptr->data;
size = connector->edid_blob_ptr->length;
if (!edid)
return 0;
if (off >= size)
return 0;
if (off + count > size)
count = size - off;
memcpy(buf, edid + off, count);
return count;
}
static ssize_t modes_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
struct drm_display_mode *mode;
int written = 0;
list_for_each_entry(mode, &connector->modes, head) {
written += snprintf(buf + written, PAGE_SIZE - written, "%s\n",
mode->name);
}
return written;
}
static ssize_t subconnector_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
struct drm_device *dev = connector->dev;
struct drm_property *prop = NULL;
uint64_t subconnector;
int is_tv = 0;
int ret;
switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_DVII:
prop = dev->mode_config.dvi_i_subconnector_property;
break;
case DRM_MODE_CONNECTOR_Composite:
case DRM_MODE_CONNECTOR_SVIDEO:
case DRM_MODE_CONNECTOR_Component:
case DRM_MODE_CONNECTOR_TV:
prop = dev->mode_config.tv_subconnector_property;
is_tv = 1;
break;
default:
DRM_ERROR("Wrong connector type for this property\n");
return 0;
}
if (!prop) {
DRM_ERROR("Unable to find subconnector property\n");
return 0;
}
ret = drm_object_property_get_value(&connector->base, prop, &subconnector);
if (ret)
return 0;
return snprintf(buf, PAGE_SIZE, "%s", is_tv ?
drm_get_tv_subconnector_name((int)subconnector) :
drm_get_dvi_i_subconnector_name((int)subconnector));
}
static ssize_t select_subconnector_show(struct device *device,
struct device_attribute *attr,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
struct drm_device *dev = connector->dev;
struct drm_property *prop = NULL;
uint64_t subconnector;
int is_tv = 0;
int ret;
switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_DVII:
prop = dev->mode_config.dvi_i_select_subconnector_property;
break;
case DRM_MODE_CONNECTOR_Composite:
case DRM_MODE_CONNECTOR_SVIDEO:
case DRM_MODE_CONNECTOR_Component:
case DRM_MODE_CONNECTOR_TV:
prop = dev->mode_config.tv_select_subconnector_property;
is_tv = 1;
break;
default:
DRM_ERROR("Wrong connector type for this property\n");
return 0;
}
if (!prop) {
DRM_ERROR("Unable to find select subconnector property\n");
return 0;
}
ret = drm_object_property_get_value(&connector->base, prop, &subconnector);
if (ret)
return 0;
return snprintf(buf, PAGE_SIZE, "%s", is_tv ?
drm_get_tv_select_name((int)subconnector) :
drm_get_dvi_i_select_name((int)subconnector));
}
static struct device_attribute connector_attrs[] = {
__ATTR_RO(status),
__ATTR_RO(enabled),
__ATTR_RO(dpms),
__ATTR_RO(modes),
};
/* These attributes are for both DVI-I connectors and all types of tv-out. */
static struct device_attribute connector_attrs_opt1[] = {
__ATTR_RO(subconnector),
__ATTR_RO(select_subconnector),
};
static struct bin_attribute edid_attr = {
.attr.name = "edid",
.attr.mode = 0444,
.size = 0,
.read = edid_show,
};
/**
* drm_sysfs_connector_add - add a connector to sysfs
* @connector: connector to add
*
* Create a connector device in sysfs, along with its associated connector
* properties (so far, connection status, dpms, mode list & edid) and
* generate a hotplug event so userspace knows there's a new connector
* available.
*
* Note:
* This routine should only be called *once* for each registered connector.
* A second call for an already registered connector will trigger the BUG_ON
* below.
*/
int drm_sysfs_connector_add(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
int attr_cnt = 0;
int opt_cnt = 0;
int i;
int ret;
/* We shouldn't get called more than once for the same connector */
BUG_ON(device_is_registered(&connector->kdev));
connector->kdev.parent = &dev->primary->kdev;
connector->kdev.class = drm_class;
connector->kdev.release = drm_sysfs_device_release;
DRM_DEBUG("adding \"%s\" to sysfs\n",
drm_get_connector_name(connector));
dev_set_name(&connector->kdev, "card%d-%s",
dev->primary->index, drm_get_connector_name(connector));
ret = device_register(&connector->kdev);
if (ret) {
DRM_ERROR("failed to register connector device: %d\n", ret);
goto out;
}
/* Standard attributes */
for (attr_cnt = 0; attr_cnt < ARRAY_SIZE(connector_attrs); attr_cnt++) {
ret = device_create_file(&connector->kdev, &connector_attrs[attr_cnt]);
if (ret)
goto err_out_files;
}
/* Optional attributes */
/*
* In the long run it maybe a good idea to make one set of
* optionals per connector type.
*/
switch (connector->connector_type) {
case DRM_MODE_CONNECTOR_DVII:
case DRM_MODE_CONNECTOR_Composite:
case DRM_MODE_CONNECTOR_SVIDEO:
case DRM_MODE_CONNECTOR_Component:
case DRM_MODE_CONNECTOR_TV:
for (opt_cnt = 0; opt_cnt < ARRAY_SIZE(connector_attrs_opt1); opt_cnt++) {
ret = device_create_file(&connector->kdev, &connector_attrs_opt1[opt_cnt]);
if (ret)
goto err_out_files;
}
break;
default:
break;
}
ret = sysfs_create_bin_file(&connector->kdev.kobj, &edid_attr);
if (ret)
goto err_out_files;
/* Let userspace know we have a new connector */
drm_sysfs_hotplug_event(dev);
return 0;
err_out_files:
for (i = 0; i < opt_cnt; i++)
device_remove_file(&connector->kdev, &connector_attrs_opt1[i]);
for (i = 0; i < attr_cnt; i++)
device_remove_file(&connector->kdev, &connector_attrs[i]);
device_unregister(&connector->kdev);
out:
return ret;
}
EXPORT_SYMBOL(drm_sysfs_connector_add);
/**
* drm_sysfs_connector_remove - remove an connector device from sysfs
* @connector: connector to remove
*
* Remove @connector and its associated attributes from sysfs. Note that
* the device model core will take care of sending the "remove" uevent
* at this time, so we don't need to do it.
*
* Note:
* This routine should only be called if the connector was previously
* successfully registered. If @connector hasn't been registered yet,
* you'll likely see a panic somewhere deep in sysfs code when called.
*/
void drm_sysfs_connector_remove(struct drm_connector *connector)
{
int i;
if (!connector->kdev.parent)
return;
DRM_DEBUG("removing \"%s\" from sysfs\n",
drm_get_connector_name(connector));
for (i = 0; i < ARRAY_SIZE(connector_attrs); i++)
device_remove_file(&connector->kdev, &connector_attrs[i]);
sysfs_remove_bin_file(&connector->kdev.kobj, &edid_attr);
device_unregister(&connector->kdev);
connector->kdev.parent = NULL;
}
EXPORT_SYMBOL(drm_sysfs_connector_remove);
/**
* drm_sysfs_hotplug_event - generate a DRM uevent
* @dev: DRM device
*
* Send a uevent for the DRM device specified by @dev. Currently we only
* set HOTPLUG=1 in the uevent environment, but this could be expanded to
* deal with other types of events.
*/
void drm_sysfs_hotplug_event(struct drm_device *dev)
{
char *event_string = "HOTPLUG=1";
char *envp[] = { event_string, NULL };
DRM_DEBUG("generating hotplug event\n");
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
}
EXPORT_SYMBOL(drm_sysfs_hotplug_event);
/**
* drm_sysfs_device_add - adds a class device to sysfs for a character driver
* @dev: DRM device to be added
* @head: DRM head in question
*
* Add a DRM device to the DRM's device model class. We use @dev's PCI device
* as the parent for the Linux device, and make sure it has a file containing
* the driver we're using (for userspace compatibility).
*/
int drm_sysfs_device_add(struct drm_minor *minor)
{
int err;
char *minor_str;
minor->kdev.parent = minor->dev->dev;
minor->kdev.class = drm_class;
minor->kdev.release = drm_sysfs_device_release;
minor->kdev.devt = minor->device;
minor->kdev.type = &drm_sysfs_device_minor;
if (minor->type == DRM_MINOR_CONTROL)
minor_str = "controlD%d";
else if (minor->type == DRM_MINOR_RENDER)
minor_str = "renderD%d";
else
minor_str = "card%d";
dev_set_name(&minor->kdev, minor_str, minor->index);
err = device_register(&minor->kdev);
if (err) {
DRM_ERROR("device add failed: %d\n", err);
goto err_out;
}
return 0;
err_out:
return err;
}
/**
* drm_sysfs_device_remove - remove DRM device
* @dev: DRM device to remove
*
* This call unregisters and cleans up a class device that was created with a
* call to drm_sysfs_device_add()
*/
void drm_sysfs_device_remove(struct drm_minor *minor)
{
if (minor->kdev.parent)
device_unregister(&minor->kdev);
minor->kdev.parent = NULL;
}
/**
* drm_class_device_register - Register a struct device in the drm class.
*
* @dev: pointer to struct device to register.
*
* @dev should have all relevant members pre-filled with the exception
* of the class member. In particular, the device_type member must
* be set.
*/
int drm_class_device_register(struct device *dev)
{
if (!drm_class || IS_ERR(drm_class))
return -ENOENT;
dev->class = drm_class;
return device_register(dev);
}
EXPORT_SYMBOL_GPL(drm_class_device_register);
void drm_class_device_unregister(struct device *dev)
{
return device_unregister(dev);
}
EXPORT_SYMBOL_GPL(drm_class_device_unregister);
| gpl-2.0 |
olegsvs/android_kernel_ark_benefit_m7 | tools/perf/builtin-mem.c | 2150 | 5933 | #include "builtin.h"
#include "perf.h"
#include "util/parse-options.h"
#include "util/trace-event.h"
#include "util/tool.h"
#include "util/session.h"
#define MEM_OPERATION_LOAD "load"
#define MEM_OPERATION_STORE "store"
static const char *mem_operation = MEM_OPERATION_LOAD;
struct perf_mem {
struct perf_tool tool;
char const *input_name;
symbol_filter_t annotate_init;
bool hide_unresolved;
bool dump_raw;
const char *cpu_list;
DECLARE_BITMAP(cpu_bitmap, MAX_NR_CPUS);
};
static const char * const mem_usage[] = {
"perf mem [<options>] {record <command> |report}",
NULL
};
static int __cmd_record(int argc, const char **argv)
{
int rec_argc, i = 0, j;
const char **rec_argv;
char event[64];
int ret;
rec_argc = argc + 4;
rec_argv = calloc(rec_argc + 1, sizeof(char *));
if (!rec_argv)
return -1;
rec_argv[i++] = strdup("record");
if (!strcmp(mem_operation, MEM_OPERATION_LOAD))
rec_argv[i++] = strdup("-W");
rec_argv[i++] = strdup("-d");
rec_argv[i++] = strdup("-e");
if (strcmp(mem_operation, MEM_OPERATION_LOAD))
sprintf(event, "cpu/mem-stores/pp");
else
sprintf(event, "cpu/mem-loads/pp");
rec_argv[i++] = strdup(event);
for (j = 1; j < argc; j++, i++)
rec_argv[i] = argv[j];
ret = cmd_record(i, rec_argv, NULL);
free(rec_argv);
return ret;
}
static int
dump_raw_samples(struct perf_tool *tool,
union perf_event *event,
struct perf_sample *sample,
struct perf_evsel *evsel __maybe_unused,
struct machine *machine)
{
struct perf_mem *mem = container_of(tool, struct perf_mem, tool);
struct addr_location al;
const char *fmt;
if (perf_event__preprocess_sample(event, machine, &al, sample,
mem->annotate_init) < 0) {
fprintf(stderr, "problem processing %d event, skipping it.\n",
event->header.type);
return -1;
}
if (al.filtered || (mem->hide_unresolved && al.sym == NULL))
return 0;
if (al.map != NULL)
al.map->dso->hit = 1;
if (symbol_conf.field_sep) {
fmt = "%d%s%d%s0x%"PRIx64"%s0x%"PRIx64"%s%"PRIu64
"%s0x%"PRIx64"%s%s:%s\n";
} else {
fmt = "%5d%s%5d%s0x%016"PRIx64"%s0x016%"PRIx64
"%s%5"PRIu64"%s0x%06"PRIx64"%s%s:%s\n";
symbol_conf.field_sep = " ";
}
printf(fmt,
sample->pid,
symbol_conf.field_sep,
sample->tid,
symbol_conf.field_sep,
event->ip.ip,
symbol_conf.field_sep,
sample->addr,
symbol_conf.field_sep,
sample->weight,
symbol_conf.field_sep,
sample->data_src,
symbol_conf.field_sep,
al.map ? (al.map->dso ? al.map->dso->long_name : "???") : "???",
al.sym ? al.sym->name : "???");
return 0;
}
static int process_sample_event(struct perf_tool *tool,
union perf_event *event,
struct perf_sample *sample,
struct perf_evsel *evsel,
struct machine *machine)
{
return dump_raw_samples(tool, event, sample, evsel, machine);
}
static int report_raw_events(struct perf_mem *mem)
{
int err = -EINVAL;
int ret;
struct perf_session *session = perf_session__new(input_name, O_RDONLY,
0, false, &mem->tool);
if (session == NULL)
return -ENOMEM;
if (mem->cpu_list) {
ret = perf_session__cpu_bitmap(session, mem->cpu_list,
mem->cpu_bitmap);
if (ret)
goto out_delete;
}
if (symbol__init() < 0)
return -1;
printf("# PID, TID, IP, ADDR, LOCAL WEIGHT, DSRC, SYMBOL\n");
err = perf_session__process_events(session, &mem->tool);
if (err)
return err;
return 0;
out_delete:
perf_session__delete(session);
return err;
}
static int report_events(int argc, const char **argv, struct perf_mem *mem)
{
const char **rep_argv;
int ret, i = 0, j, rep_argc;
if (mem->dump_raw)
return report_raw_events(mem);
rep_argc = argc + 3;
rep_argv = calloc(rep_argc + 1, sizeof(char *));
if (!rep_argv)
return -1;
rep_argv[i++] = strdup("report");
rep_argv[i++] = strdup("--mem-mode");
rep_argv[i++] = strdup("-n"); /* display number of samples */
/*
* there is no weight (cost) associated with stores, so don't print
* the column
*/
if (strcmp(mem_operation, MEM_OPERATION_LOAD))
rep_argv[i++] = strdup("--sort=mem,sym,dso,symbol_daddr,"
"dso_daddr,tlb,locked");
for (j = 1; j < argc; j++, i++)
rep_argv[i] = argv[j];
ret = cmd_report(i, rep_argv, NULL);
free(rep_argv);
return ret;
}
int cmd_mem(int argc, const char **argv, const char *prefix __maybe_unused)
{
struct stat st;
struct perf_mem mem = {
.tool = {
.sample = process_sample_event,
.mmap = perf_event__process_mmap,
.comm = perf_event__process_comm,
.lost = perf_event__process_lost,
.fork = perf_event__process_fork,
.build_id = perf_event__process_build_id,
.ordered_samples = true,
},
.input_name = "perf.data",
};
const struct option mem_options[] = {
OPT_STRING('t', "type", &mem_operation,
"type", "memory operations(load/store)"),
OPT_BOOLEAN('D', "dump-raw-samples", &mem.dump_raw,
"dump raw samples in ASCII"),
OPT_BOOLEAN('U', "hide-unresolved", &mem.hide_unresolved,
"Only display entries resolved to a symbol"),
OPT_STRING('i', "input", &input_name, "file",
"input file name"),
OPT_STRING('C', "cpu", &mem.cpu_list, "cpu",
"list of cpus to profile"),
OPT_STRING('x', "field-separator", &symbol_conf.field_sep,
"separator",
"separator for columns, no spaces will be added"
" between columns '.' is reserved."),
OPT_END()
};
argc = parse_options(argc, argv, mem_options, mem_usage,
PARSE_OPT_STOP_AT_NON_OPTION);
if (!argc || !(strncmp(argv[0], "rec", 3) || mem_operation))
usage_with_options(mem_usage, mem_options);
if (!mem.input_name || !strlen(mem.input_name)) {
if (!fstat(STDIN_FILENO, &st) && S_ISFIFO(st.st_mode))
mem.input_name = "-";
else
mem.input_name = "perf.data";
}
if (!strncmp(argv[0], "rec", 3))
return __cmd_record(argc, argv);
else if (!strncmp(argv[0], "rep", 3))
return report_events(argc, argv, &mem);
else
usage_with_options(mem_usage, mem_options);
return 0;
}
| gpl-2.0 |
Hacker432-Y550/android_kernel_huawei_msm8916 | drivers/pcmcia/electra_cf.c | 2406 | 8746 | /*
* Copyright (C) 2007 PA Semi, Inc
*
* Maintained by: Olof Johansson <olof@lixom.net>
*
* Based on drivers/pcmcia/omap_cf.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <pcmcia/ss.h>
static const char driver_name[] = "electra-cf";
struct electra_cf_socket {
struct pcmcia_socket socket;
struct timer_list timer;
unsigned present:1;
unsigned active:1;
struct platform_device *ofdev;
unsigned long mem_phys;
void __iomem * mem_base;
unsigned long mem_size;
void __iomem * io_virt;
unsigned int io_base;
unsigned int io_size;
u_int irq;
struct resource iomem;
void __iomem * gpio_base;
int gpio_detect;
int gpio_vsense;
int gpio_3v;
int gpio_5v;
};
#define POLL_INTERVAL (2 * HZ)
static int electra_cf_present(struct electra_cf_socket *cf)
{
unsigned int gpio;
gpio = in_le32(cf->gpio_base+0x40);
return !(gpio & (1 << cf->gpio_detect));
}
static int electra_cf_ss_init(struct pcmcia_socket *s)
{
return 0;
}
/* the timer is primarily to kick this socket's pccardd */
static void electra_cf_timer(unsigned long _cf)
{
struct electra_cf_socket *cf = (void *) _cf;
int present = electra_cf_present(cf);
if (present != cf->present) {
cf->present = present;
pcmcia_parse_events(&cf->socket, SS_DETECT);
}
if (cf->active)
mod_timer(&cf->timer, jiffies + POLL_INTERVAL);
}
static irqreturn_t electra_cf_irq(int irq, void *_cf)
{
electra_cf_timer((unsigned long)_cf);
return IRQ_HANDLED;
}
static int electra_cf_get_status(struct pcmcia_socket *s, u_int *sp)
{
struct electra_cf_socket *cf;
if (!sp)
return -EINVAL;
cf = container_of(s, struct electra_cf_socket, socket);
/* NOTE CF is always 3VCARD */
if (electra_cf_present(cf)) {
*sp = SS_READY | SS_DETECT | SS_POWERON | SS_3VCARD;
s->pci_irq = cf->irq;
} else
*sp = 0;
return 0;
}
static int electra_cf_set_socket(struct pcmcia_socket *sock,
struct socket_state_t *s)
{
unsigned int gpio;
unsigned int vcc;
struct electra_cf_socket *cf;
cf = container_of(sock, struct electra_cf_socket, socket);
/* "reset" means no power in our case */
vcc = (s->flags & SS_RESET) ? 0 : s->Vcc;
switch (vcc) {
case 0:
gpio = 0;
break;
case 33:
gpio = (1 << cf->gpio_3v);
break;
case 5:
gpio = (1 << cf->gpio_5v);
break;
default:
return -EINVAL;
}
gpio |= 1 << (cf->gpio_3v + 16); /* enwr */
gpio |= 1 << (cf->gpio_5v + 16); /* enwr */
out_le32(cf->gpio_base+0x90, gpio);
pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n",
driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask);
return 0;
}
static int electra_cf_set_io_map(struct pcmcia_socket *s,
struct pccard_io_map *io)
{
return 0;
}
static int electra_cf_set_mem_map(struct pcmcia_socket *s,
struct pccard_mem_map *map)
{
struct electra_cf_socket *cf;
if (map->card_start)
return -EINVAL;
cf = container_of(s, struct electra_cf_socket, socket);
map->static_start = cf->mem_phys;
map->flags &= MAP_ACTIVE|MAP_ATTRIB;
if (!(map->flags & MAP_ATTRIB))
map->static_start += 0x800;
return 0;
}
static struct pccard_operations electra_cf_ops = {
.init = electra_cf_ss_init,
.get_status = electra_cf_get_status,
.set_socket = electra_cf_set_socket,
.set_io_map = electra_cf_set_io_map,
.set_mem_map = electra_cf_set_mem_map,
};
static int electra_cf_probe(struct platform_device *ofdev)
{
struct device *device = &ofdev->dev;
struct device_node *np = ofdev->dev.of_node;
struct electra_cf_socket *cf;
struct resource mem, io;
int status;
const unsigned int *prop;
int err;
struct vm_struct *area;
err = of_address_to_resource(np, 0, &mem);
if (err)
return -EINVAL;
err = of_address_to_resource(np, 1, &io);
if (err)
return -EINVAL;
cf = kzalloc(sizeof *cf, GFP_KERNEL);
if (!cf)
return -ENOMEM;
setup_timer(&cf->timer, electra_cf_timer, (unsigned long)cf);
cf->irq = NO_IRQ;
cf->ofdev = ofdev;
cf->mem_phys = mem.start;
cf->mem_size = PAGE_ALIGN(resource_size(&mem));
cf->mem_base = ioremap(cf->mem_phys, cf->mem_size);
cf->io_size = PAGE_ALIGN(resource_size(&io));
area = __get_vm_area(cf->io_size, 0, PHB_IO_BASE, PHB_IO_END);
if (area == NULL)
return -ENOMEM;
cf->io_virt = (void __iomem *)(area->addr);
cf->gpio_base = ioremap(0xfc103000, 0x1000);
dev_set_drvdata(device, cf);
if (!cf->mem_base || !cf->io_virt || !cf->gpio_base ||
(__ioremap_at(io.start, cf->io_virt, cf->io_size,
_PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)) {
dev_err(device, "can't ioremap ranges\n");
status = -ENOMEM;
goto fail1;
}
cf->io_base = (unsigned long)cf->io_virt - VMALLOC_END;
cf->iomem.start = (unsigned long)cf->mem_base;
cf->iomem.end = (unsigned long)cf->mem_base + (mem.end - mem.start);
cf->iomem.flags = IORESOURCE_MEM;
cf->irq = irq_of_parse_and_map(np, 0);
status = request_irq(cf->irq, electra_cf_irq, IRQF_SHARED,
driver_name, cf);
if (status < 0) {
dev_err(device, "request_irq failed\n");
goto fail1;
}
cf->socket.pci_irq = cf->irq;
prop = of_get_property(np, "card-detect-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_detect = *prop;
prop = of_get_property(np, "card-vsense-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_vsense = *prop;
prop = of_get_property(np, "card-3v-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_3v = *prop;
prop = of_get_property(np, "card-5v-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_5v = *prop;
cf->socket.io_offset = cf->io_base;
/* reserve chip-select regions */
if (!request_mem_region(cf->mem_phys, cf->mem_size, driver_name)) {
status = -ENXIO;
dev_err(device, "Can't claim memory region\n");
goto fail1;
}
if (!request_region(cf->io_base, cf->io_size, driver_name)) {
status = -ENXIO;
dev_err(device, "Can't claim I/O region\n");
goto fail2;
}
cf->socket.owner = THIS_MODULE;
cf->socket.dev.parent = &ofdev->dev;
cf->socket.ops = &electra_cf_ops;
cf->socket.resource_ops = &pccard_static_ops;
cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP |
SS_CAP_MEM_ALIGN;
cf->socket.map_size = 0x800;
status = pcmcia_register_socket(&cf->socket);
if (status < 0) {
dev_err(device, "pcmcia_register_socket failed\n");
goto fail3;
}
dev_info(device, "at mem 0x%lx io 0x%llx irq %d\n",
cf->mem_phys, io.start, cf->irq);
cf->active = 1;
electra_cf_timer((unsigned long)cf);
return 0;
fail3:
release_region(cf->io_base, cf->io_size);
fail2:
release_mem_region(cf->mem_phys, cf->mem_size);
fail1:
if (cf->irq != NO_IRQ)
free_irq(cf->irq, cf);
if (cf->io_virt)
__iounmap_at(cf->io_virt, cf->io_size);
if (cf->mem_base)
iounmap(cf->mem_base);
if (cf->gpio_base)
iounmap(cf->gpio_base);
device_init_wakeup(&ofdev->dev, 0);
kfree(cf);
return status;
}
static int electra_cf_remove(struct platform_device *ofdev)
{
struct device *device = &ofdev->dev;
struct electra_cf_socket *cf;
cf = dev_get_drvdata(device);
cf->active = 0;
pcmcia_unregister_socket(&cf->socket);
free_irq(cf->irq, cf);
del_timer_sync(&cf->timer);
__iounmap_at(cf->io_virt, cf->io_size);
iounmap(cf->mem_base);
iounmap(cf->gpio_base);
release_mem_region(cf->mem_phys, cf->mem_size);
release_region(cf->io_base, cf->io_size);
kfree(cf);
return 0;
}
static const struct of_device_id electra_cf_match[] = {
{
.compatible = "electra-cf",
},
{},
};
MODULE_DEVICE_TABLE(of, electra_cf_match);
static struct platform_driver electra_cf_driver = {
.driver = {
.name = (char *)driver_name,
.owner = THIS_MODULE,
.of_match_table = electra_cf_match,
},
.probe = electra_cf_probe,
.remove = electra_cf_remove,
};
module_platform_driver(electra_cf_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
MODULE_DESCRIPTION("PA Semi Electra CF driver");
| gpl-2.0 |
CyanogenMod/android_kernel_bn_acclaim | arch/alpha/kernel/irq_alpha.c | 2918 | 6542 | /*
* Alpha specific irq code.
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <asm/machvec.h>
#include <asm/dma.h>
#include <asm/perf_event.h>
#include "proto.h"
#include "irq_impl.h"
/* Hack minimum IPL during interrupt processing for broken hardware. */
#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
int __min_ipl;
EXPORT_SYMBOL(__min_ipl);
#endif
/*
* Performance counter hook. A module can override this to
* do something useful.
*/
static void
dummy_perf(unsigned long vector, struct pt_regs *regs)
{
irq_err_count++;
printk(KERN_CRIT "Performance counter interrupt!\n");
}
void (*perf_irq)(unsigned long, struct pt_regs *) = dummy_perf;
EXPORT_SYMBOL(perf_irq);
/*
* The main interrupt entry point.
*/
asmlinkage void
do_entInt(unsigned long type, unsigned long vector,
unsigned long la_ptr, struct pt_regs *regs)
{
struct pt_regs *old_regs;
switch (type) {
case 0:
#ifdef CONFIG_SMP
handle_ipi(regs);
return;
#else
irq_err_count++;
printk(KERN_CRIT "Interprocessor interrupt? "
"You must be kidding!\n");
#endif
break;
case 1:
old_regs = set_irq_regs(regs);
#ifdef CONFIG_SMP
{
long cpu;
local_irq_disable();
smp_percpu_timer_interrupt(regs);
cpu = smp_processor_id();
if (cpu != boot_cpuid) {
kstat_incr_irqs_this_cpu(RTC_IRQ, irq_to_desc(RTC_IRQ));
} else {
handle_irq(RTC_IRQ);
}
}
#else
handle_irq(RTC_IRQ);
#endif
set_irq_regs(old_regs);
return;
case 2:
old_regs = set_irq_regs(regs);
alpha_mv.machine_check(vector, la_ptr);
set_irq_regs(old_regs);
return;
case 3:
old_regs = set_irq_regs(regs);
alpha_mv.device_interrupt(vector);
set_irq_regs(old_regs);
return;
case 4:
perf_irq(la_ptr, regs);
return;
default:
printk(KERN_CRIT "Hardware intr %ld %lx? Huh?\n",
type, vector);
}
printk(KERN_CRIT "PC = %016lx PS=%04lx\n", regs->pc, regs->ps);
}
void __init
common_init_isa_dma(void)
{
outb(0, DMA1_RESET_REG);
outb(0, DMA2_RESET_REG);
outb(0, DMA1_CLR_MASK_REG);
outb(0, DMA2_CLR_MASK_REG);
}
void __init
init_IRQ(void)
{
/* Just in case the platform init_irq() causes interrupts/mchecks
(as is the case with RAWHIDE, at least). */
wrent(entInt, 0);
alpha_mv.init_irq();
}
/*
* machine error checks
*/
#define MCHK_K_TPERR 0x0080
#define MCHK_K_TCPERR 0x0082
#define MCHK_K_HERR 0x0084
#define MCHK_K_ECC_C 0x0086
#define MCHK_K_ECC_NC 0x0088
#define MCHK_K_OS_BUGCHECK 0x008A
#define MCHK_K_PAL_BUGCHECK 0x0090
#ifndef CONFIG_SMP
struct mcheck_info __mcheck_info;
#endif
void
process_mcheck_info(unsigned long vector, unsigned long la_ptr,
const char *machine, int expected)
{
struct el_common *mchk_header;
const char *reason;
/*
* See if the machine check is due to a badaddr() and if so,
* ignore it.
*/
#ifdef CONFIG_VERBOSE_MCHECK
if (alpha_verbose_mcheck > 1) {
printk(KERN_CRIT "%s machine check %s\n", machine,
expected ? "expected." : "NOT expected!!!");
}
#endif
if (expected) {
int cpu = smp_processor_id();
mcheck_expected(cpu) = 0;
mcheck_taken(cpu) = 1;
return;
}
mchk_header = (struct el_common *)la_ptr;
printk(KERN_CRIT "%s machine check: vector=0x%lx pc=0x%lx code=0x%x\n",
machine, vector, get_irq_regs()->pc, mchk_header->code);
switch (mchk_header->code) {
/* Machine check reasons. Defined according to PALcode sources. */
case 0x80: reason = "tag parity error"; break;
case 0x82: reason = "tag control parity error"; break;
case 0x84: reason = "generic hard error"; break;
case 0x86: reason = "correctable ECC error"; break;
case 0x88: reason = "uncorrectable ECC error"; break;
case 0x8A: reason = "OS-specific PAL bugcheck"; break;
case 0x90: reason = "callsys in kernel mode"; break;
case 0x96: reason = "i-cache read retryable error"; break;
case 0x98: reason = "processor detected hard error"; break;
/* System specific (these are for Alcor, at least): */
case 0x202: reason = "system detected hard error"; break;
case 0x203: reason = "system detected uncorrectable ECC error"; break;
case 0x204: reason = "SIO SERR occurred on PCI bus"; break;
case 0x205: reason = "parity error detected by core logic"; break;
case 0x206: reason = "SIO IOCHK occurred on ISA bus"; break;
case 0x207: reason = "non-existent memory error"; break;
case 0x208: reason = "MCHK_K_DCSR"; break;
case 0x209: reason = "PCI SERR detected"; break;
case 0x20b: reason = "PCI data parity error detected"; break;
case 0x20d: reason = "PCI address parity error detected"; break;
case 0x20f: reason = "PCI master abort error"; break;
case 0x211: reason = "PCI target abort error"; break;
case 0x213: reason = "scatter/gather PTE invalid error"; break;
case 0x215: reason = "flash ROM write error"; break;
case 0x217: reason = "IOA timeout detected"; break;
case 0x219: reason = "IOCHK#, EISA add-in board parity or other catastrophic error"; break;
case 0x21b: reason = "EISA fail-safe timer timeout"; break;
case 0x21d: reason = "EISA bus time-out"; break;
case 0x21f: reason = "EISA software generated NMI"; break;
case 0x221: reason = "unexpected ev5 IRQ[3] interrupt"; break;
default: reason = "unknown"; break;
}
printk(KERN_CRIT "machine check type: %s%s\n",
reason, mchk_header->retry ? " (retryable)" : "");
dik_show_regs(get_irq_regs(), NULL);
#ifdef CONFIG_VERBOSE_MCHECK
if (alpha_verbose_mcheck > 1) {
/* Dump the logout area to give all info. */
unsigned long *ptr = (unsigned long *)la_ptr;
long i;
for (i = 0; i < mchk_header->size / sizeof(long); i += 2) {
printk(KERN_CRIT " +%8lx %016lx %016lx\n",
i*sizeof(long), ptr[i], ptr[i+1]);
}
}
#endif /* CONFIG_VERBOSE_MCHECK */
}
/*
* The special RTC interrupt type. The interrupt itself was
* processed by PALcode, and comes in via entInt vector 1.
*/
struct irqaction timer_irqaction = {
.handler = timer_interrupt,
.flags = IRQF_DISABLED,
.name = "timer",
};
void __init
init_rtc_irq(void)
{
irq_set_chip_and_handler_name(RTC_IRQ, &dummy_irq_chip,
handle_simple_irq, "RTC");
setup_irq(RTC_IRQ, &timer_irqaction);
}
/* Dummy irqactions. */
struct irqaction isa_cascade_irqaction = {
.handler = no_action,
.name = "isa-cascade"
};
struct irqaction timer_cascade_irqaction = {
.handler = no_action,
.name = "timer-cascade"
};
struct irqaction halt_switch_irqaction = {
.handler = no_action,
.name = "halt-switch"
};
| gpl-2.0 |
omerjerk/android_kernel_xiaomi_ferrari | drivers/net/sungem_phy.c | 2918 | 29308 | /*
* PHY drivers for the sungem ethernet driver.
*
* This file could be shared with other drivers.
*
* (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
*
* TODO:
* - Add support for PHYs that provide an IRQ line
* - Eventually moved the entire polling state machine in
* there (out of the eth driver), so that it can easily be
* skipped on PHYs that implement it in hardware.
* - On LXT971 & BCM5201, Apple uses some chip specific regs
* to read the link status. Figure out why and if it makes
* sense to do the same (magic aneg ?)
* - Apple has some additional power management code for some
* Broadcom PHYs that they "hide" from the OpenSource version
* of darwin, still need to reverse engineer that
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#endif
#include <linux/sungem_phy.h>
/* Link modes of the BCM5400 PHY */
static const int phy_BCM5400_link_table[8][3] = {
{ 0, 0, 0 }, /* No link */
{ 0, 0, 0 }, /* 10BT Half Duplex */
{ 1, 0, 0 }, /* 10BT Full Duplex */
{ 0, 1, 0 }, /* 100BT Half Duplex */
{ 0, 1, 0 }, /* 100BT Half Duplex */
{ 1, 1, 0 }, /* 100BT Full Duplex*/
{ 1, 0, 1 }, /* 1000BT */
{ 1, 0, 1 }, /* 1000BT */
};
static inline int __phy_read(struct mii_phy* phy, int id, int reg)
{
return phy->mdio_read(phy->dev, id, reg);
}
static inline void __phy_write(struct mii_phy* phy, int id, int reg, int val)
{
phy->mdio_write(phy->dev, id, reg, val);
}
static inline int phy_read(struct mii_phy* phy, int reg)
{
return phy->mdio_read(phy->dev, phy->mii_id, reg);
}
static inline void phy_write(struct mii_phy* phy, int reg, int val)
{
phy->mdio_write(phy->dev, phy->mii_id, reg, val);
}
static int reset_one_mii_phy(struct mii_phy* phy, int phy_id)
{
u16 val;
int limit = 10000;
val = __phy_read(phy, phy_id, MII_BMCR);
val &= ~(BMCR_ISOLATE | BMCR_PDOWN);
val |= BMCR_RESET;
__phy_write(phy, phy_id, MII_BMCR, val);
udelay(100);
while (--limit) {
val = __phy_read(phy, phy_id, MII_BMCR);
if ((val & BMCR_RESET) == 0)
break;
udelay(10);
}
if ((val & BMCR_ISOLATE) && limit > 0)
__phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
return limit <= 0;
}
static int bcm5201_init(struct mii_phy* phy)
{
u16 data;
data = phy_read(phy, MII_BCM5201_MULTIPHY);
data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
phy_write(phy, MII_BCM5201_MULTIPHY, data);
phy_write(phy, MII_BCM5201_INTERRUPT, 0);
return 0;
}
static int bcm5201_suspend(struct mii_phy* phy)
{
phy_write(phy, MII_BCM5201_INTERRUPT, 0);
phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
return 0;
}
static int bcm5221_init(struct mii_phy* phy)
{
u16 data;
data = phy_read(phy, MII_BCM5221_TEST);
phy_write(phy, MII_BCM5221_TEST,
data | MII_BCM5221_TEST_ENABLE_SHADOWS);
data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
data | MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR);
data = phy_read(phy, MII_BCM5221_TEST);
phy_write(phy, MII_BCM5221_TEST,
data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
return 0;
}
static int bcm5221_suspend(struct mii_phy* phy)
{
u16 data;
data = phy_read(phy, MII_BCM5221_TEST);
phy_write(phy, MII_BCM5221_TEST,
data | MII_BCM5221_TEST_ENABLE_SHADOWS);
data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
return 0;
}
static int bcm5241_init(struct mii_phy* phy)
{
u16 data;
data = phy_read(phy, MII_BCM5221_TEST);
phy_write(phy, MII_BCM5221_TEST,
data | MII_BCM5221_TEST_ENABLE_SHADOWS);
data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
data & ~MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
data = phy_read(phy, MII_BCM5221_TEST);
phy_write(phy, MII_BCM5221_TEST,
data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
return 0;
}
static int bcm5241_suspend(struct mii_phy* phy)
{
u16 data;
data = phy_read(phy, MII_BCM5221_TEST);
phy_write(phy, MII_BCM5221_TEST,
data | MII_BCM5221_TEST_ENABLE_SHADOWS);
data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
data | MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
return 0;
}
static int bcm5400_init(struct mii_phy* phy)
{
u16 data;
/* Configure for gigabit full duplex */
data = phy_read(phy, MII_BCM5400_AUXCONTROL);
data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
phy_write(phy, MII_BCM5400_AUXCONTROL, data);
data = phy_read(phy, MII_BCM5400_GB_CONTROL);
data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
phy_write(phy, MII_BCM5400_GB_CONTROL, data);
udelay(100);
/* Reset and configure cascaded 10/100 PHY */
(void)reset_one_mii_phy(phy, 0x1f);
data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
data |= MII_BCM5201_MULTIPHY_SERIALMODE;
__phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
data = phy_read(phy, MII_BCM5400_AUXCONTROL);
data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
phy_write(phy, MII_BCM5400_AUXCONTROL, data);
return 0;
}
static int bcm5400_suspend(struct mii_phy* phy)
{
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
phy_write(phy, MII_BMCR, BMCR_PDOWN);
#endif
return 0;
}
static int bcm5401_init(struct mii_phy* phy)
{
u16 data;
int rev;
rev = phy_read(phy, MII_PHYSID2) & 0x000f;
if (rev == 0 || rev == 3) {
/* Some revisions of 5401 appear to need this
* initialisation sequence to disable, according
* to OF, "tap power management"
*
* WARNING ! OF and Darwin don't agree on the
* register addresses. OF seem to interpret the
* register numbers below as decimal
*
* Note: This should (and does) match tg3_init_5401phy_dsp
* in the tg3.c driver. -DaveM
*/
phy_write(phy, 0x18, 0x0c20);
phy_write(phy, 0x17, 0x0012);
phy_write(phy, 0x15, 0x1804);
phy_write(phy, 0x17, 0x0013);
phy_write(phy, 0x15, 0x1204);
phy_write(phy, 0x17, 0x8006);
phy_write(phy, 0x15, 0x0132);
phy_write(phy, 0x17, 0x8006);
phy_write(phy, 0x15, 0x0232);
phy_write(phy, 0x17, 0x201f);
phy_write(phy, 0x15, 0x0a20);
}
/* Configure for gigabit full duplex */
data = phy_read(phy, MII_BCM5400_GB_CONTROL);
data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
phy_write(phy, MII_BCM5400_GB_CONTROL, data);
udelay(10);
/* Reset and configure cascaded 10/100 PHY */
(void)reset_one_mii_phy(phy, 0x1f);
data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
data |= MII_BCM5201_MULTIPHY_SERIALMODE;
__phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
return 0;
}
static int bcm5401_suspend(struct mii_phy* phy)
{
#if 0 /* Commented out in Darwin... someone has those dawn docs ? */
phy_write(phy, MII_BMCR, BMCR_PDOWN);
#endif
return 0;
}
static int bcm5411_init(struct mii_phy* phy)
{
u16 data;
/* Here's some more Apple black magic to setup
* some voltage stuffs.
*/
phy_write(phy, 0x1c, 0x8c23);
phy_write(phy, 0x1c, 0x8ca3);
phy_write(phy, 0x1c, 0x8c23);
/* Here, Apple seems to want to reset it, do
* it as well
*/
phy_write(phy, MII_BMCR, BMCR_RESET);
phy_write(phy, MII_BMCR, 0x1340);
data = phy_read(phy, MII_BCM5400_GB_CONTROL);
data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
phy_write(phy, MII_BCM5400_GB_CONTROL, data);
udelay(10);
/* Reset and configure cascaded 10/100 PHY */
(void)reset_one_mii_phy(phy, 0x1f);
return 0;
}
static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
{
u16 ctl, adv;
phy->autoneg = 1;
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = 0;
phy->advertising = advertise;
/* Setup standard advertise */
adv = phy_read(phy, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
phy_write(phy, MII_ADVERTISE, adv);
/* Start/Restart aneg */
ctl = phy_read(phy, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
{
u16 ctl;
phy->autoneg = 0;
phy->speed = speed;
phy->duplex = fd;
phy->pause = 0;
ctl = phy_read(phy, MII_BMCR);
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE);
/* First reset the PHY */
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
/* Select speed & duplex */
switch(speed) {
case SPEED_10:
break;
case SPEED_100:
ctl |= BMCR_SPEED100;
break;
case SPEED_1000:
default:
return -EINVAL;
}
if (fd == DUPLEX_FULL)
ctl |= BMCR_FULLDPLX;
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int genmii_poll_link(struct mii_phy *phy)
{
u16 status;
(void)phy_read(phy, MII_BMSR);
status = phy_read(phy, MII_BMSR);
if ((status & BMSR_LSTATUS) == 0)
return 0;
if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
return 0;
return 1;
}
static int genmii_read_link(struct mii_phy *phy)
{
u16 lpa;
if (phy->autoneg) {
lpa = phy_read(phy, MII_LPA);
if (lpa & (LPA_10FULL | LPA_100FULL))
phy->duplex = DUPLEX_FULL;
else
phy->duplex = DUPLEX_HALF;
if (lpa & (LPA_100FULL | LPA_100HALF))
phy->speed = SPEED_100;
else
phy->speed = SPEED_10;
phy->pause = 0;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
}
static int generic_suspend(struct mii_phy* phy)
{
phy_write(phy, MII_BMCR, BMCR_PDOWN);
return 0;
}
static int bcm5421_init(struct mii_phy* phy)
{
u16 data;
unsigned int id;
id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2));
/* Revision 0 of 5421 needs some fixups */
if (id == 0x002060e0) {
/* This is borrowed from MacOS
*/
phy_write(phy, 0x18, 0x1007);
data = phy_read(phy, 0x18);
phy_write(phy, 0x18, data | 0x0400);
phy_write(phy, 0x18, 0x0007);
data = phy_read(phy, 0x18);
phy_write(phy, 0x18, data | 0x0800);
phy_write(phy, 0x17, 0x000a);
data = phy_read(phy, 0x15);
phy_write(phy, 0x15, data | 0x0200);
}
/* Pick up some init code from OF for K2 version */
if ((id & 0xfffffff0) == 0x002062e0) {
phy_write(phy, 4, 0x01e1);
phy_write(phy, 9, 0x0300);
}
/* Check if we can enable automatic low power */
#ifdef CONFIG_PPC_PMAC
if (phy->platform_data) {
struct device_node *np = of_get_parent(phy->platform_data);
int can_low_power = 1;
if (np == NULL || of_get_property(np, "no-autolowpower", NULL))
can_low_power = 0;
if (can_low_power) {
/* Enable automatic low-power */
phy_write(phy, 0x1c, 0x9002);
phy_write(phy, 0x1c, 0xa821);
phy_write(phy, 0x1c, 0x941d);
}
}
#endif /* CONFIG_PPC_PMAC */
return 0;
}
static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
{
u16 ctl, adv;
phy->autoneg = 1;
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = 0;
phy->advertising = advertise;
/* Setup standard advertise */
adv = phy_read(phy, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
if (advertise & ADVERTISED_Pause)
adv |= ADVERTISE_PAUSE_CAP;
if (advertise & ADVERTISED_Asym_Pause)
adv |= ADVERTISE_PAUSE_ASYM;
phy_write(phy, MII_ADVERTISE, adv);
/* Setup 1000BT advertise */
adv = phy_read(phy, MII_1000BASETCONTROL);
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP|MII_1000BASETCONTROL_HALFDUPLEXCAP);
if (advertise & SUPPORTED_1000baseT_Half)
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
if (advertise & SUPPORTED_1000baseT_Full)
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
phy_write(phy, MII_1000BASETCONTROL, adv);
/* Start/Restart aneg */
ctl = phy_read(phy, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
{
u16 ctl;
phy->autoneg = 0;
phy->speed = speed;
phy->duplex = fd;
phy->pause = 0;
ctl = phy_read(phy, MII_BMCR);
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
/* First reset the PHY */
phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
/* Select speed & duplex */
switch(speed) {
case SPEED_10:
break;
case SPEED_100:
ctl |= BMCR_SPEED100;
break;
case SPEED_1000:
ctl |= BMCR_SPD2;
}
if (fd == DUPLEX_FULL)
ctl |= BMCR_FULLDPLX;
// XXX Should we set the sungem to GII now on 1000BT ?
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int bcm54xx_read_link(struct mii_phy *phy)
{
int link_mode;
u16 val;
if (phy->autoneg) {
val = phy_read(phy, MII_BCM5400_AUXSTATUS);
link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
phy->duplex = phy_BCM5400_link_table[link_mode][0] ?
DUPLEX_FULL : DUPLEX_HALF;
phy->speed = phy_BCM5400_link_table[link_mode][2] ?
SPEED_1000 :
(phy_BCM5400_link_table[link_mode][1] ?
SPEED_100 : SPEED_10);
val = phy_read(phy, MII_LPA);
phy->pause = (phy->duplex == DUPLEX_FULL) &&
((val & LPA_PAUSE) != 0);
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
}
static int marvell88e1111_init(struct mii_phy* phy)
{
u16 rev;
/* magic init sequence for rev 0 */
rev = phy_read(phy, MII_PHYSID2) & 0x000f;
if (rev == 0) {
phy_write(phy, 0x1d, 0x000a);
phy_write(phy, 0x1e, 0x0821);
phy_write(phy, 0x1d, 0x0006);
phy_write(phy, 0x1e, 0x8600);
phy_write(phy, 0x1d, 0x000b);
phy_write(phy, 0x1e, 0x0100);
phy_write(phy, 0x1d, 0x0004);
phy_write(phy, 0x1e, 0x4850);
}
return 0;
}
#define BCM5421_MODE_MASK (1 << 5)
static int bcm5421_poll_link(struct mii_phy* phy)
{
u32 phy_reg;
int mode;
/* find out in what mode we are */
phy_write(phy, MII_NCONFIG, 0x1000);
phy_reg = phy_read(phy, MII_NCONFIG);
mode = (phy_reg & BCM5421_MODE_MASK) >> 5;
if ( mode == BCM54XX_COPPER)
return genmii_poll_link(phy);
/* try to find out whether we have a link */
phy_write(phy, MII_NCONFIG, 0x2000);
phy_reg = phy_read(phy, MII_NCONFIG);
if (phy_reg & 0x0020)
return 0;
else
return 1;
}
static int bcm5421_read_link(struct mii_phy* phy)
{
u32 phy_reg;
int mode;
/* find out in what mode we are */
phy_write(phy, MII_NCONFIG, 0x1000);
phy_reg = phy_read(phy, MII_NCONFIG);
mode = (phy_reg & BCM5421_MODE_MASK ) >> 5;
if ( mode == BCM54XX_COPPER)
return bcm54xx_read_link(phy);
phy->speed = SPEED_1000;
/* find out whether we are running half- or full duplex */
phy_write(phy, MII_NCONFIG, 0x2000);
phy_reg = phy_read(phy, MII_NCONFIG);
if ( (phy_reg & 0x0080) >> 7)
phy->duplex |= DUPLEX_HALF;
else
phy->duplex |= DUPLEX_FULL;
return 0;
}
static int bcm5421_enable_fiber(struct mii_phy* phy, int autoneg)
{
/* enable fiber mode */
phy_write(phy, MII_NCONFIG, 0x9020);
/* LEDs active in both modes, autosense prio = fiber */
phy_write(phy, MII_NCONFIG, 0x945f);
if (!autoneg) {
/* switch off fibre autoneg */
phy_write(phy, MII_NCONFIG, 0xfc01);
phy_write(phy, 0x0b, 0x0004);
}
phy->autoneg = autoneg;
return 0;
}
#define BCM5461_FIBER_LINK (1 << 2)
#define BCM5461_MODE_MASK (3 << 1)
static int bcm5461_poll_link(struct mii_phy* phy)
{
u32 phy_reg;
int mode;
/* find out in what mode we are */
phy_write(phy, MII_NCONFIG, 0x7c00);
phy_reg = phy_read(phy, MII_NCONFIG);
mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
if ( mode == BCM54XX_COPPER)
return genmii_poll_link(phy);
/* find out whether we have a link */
phy_write(phy, MII_NCONFIG, 0x7000);
phy_reg = phy_read(phy, MII_NCONFIG);
if (phy_reg & BCM5461_FIBER_LINK)
return 1;
else
return 0;
}
#define BCM5461_FIBER_DUPLEX (1 << 3)
static int bcm5461_read_link(struct mii_phy* phy)
{
u32 phy_reg;
int mode;
/* find out in what mode we are */
phy_write(phy, MII_NCONFIG, 0x7c00);
phy_reg = phy_read(phy, MII_NCONFIG);
mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
if ( mode == BCM54XX_COPPER) {
return bcm54xx_read_link(phy);
}
phy->speed = SPEED_1000;
/* find out whether we are running half- or full duplex */
phy_write(phy, MII_NCONFIG, 0x7000);
phy_reg = phy_read(phy, MII_NCONFIG);
if (phy_reg & BCM5461_FIBER_DUPLEX)
phy->duplex |= DUPLEX_FULL;
else
phy->duplex |= DUPLEX_HALF;
return 0;
}
static int bcm5461_enable_fiber(struct mii_phy* phy, int autoneg)
{
/* select fiber mode, enable 1000 base-X registers */
phy_write(phy, MII_NCONFIG, 0xfc0b);
if (autoneg) {
/* enable fiber with no autonegotiation */
phy_write(phy, MII_ADVERTISE, 0x01e0);
phy_write(phy, MII_BMCR, 0x1140);
} else {
/* enable fiber with autonegotiation */
phy_write(phy, MII_BMCR, 0x0140);
}
phy->autoneg = autoneg;
return 0;
}
static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
{
u16 ctl, adv;
phy->autoneg = 1;
phy->speed = SPEED_10;
phy->duplex = DUPLEX_HALF;
phy->pause = 0;
phy->advertising = advertise;
/* Setup standard advertise */
adv = phy_read(phy, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
if (advertise & ADVERTISED_Pause)
adv |= ADVERTISE_PAUSE_CAP;
if (advertise & ADVERTISED_Asym_Pause)
adv |= ADVERTISE_PAUSE_ASYM;
phy_write(phy, MII_ADVERTISE, adv);
/* Setup 1000BT advertise & enable crossover detect
* XXX How do we advertise 1000BT ? Darwin source is
* confusing here, they read from specific control and
* write to control... Someone has specs for those
* beasts ?
*/
adv = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
adv |= MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX;
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
MII_1000BASETCONTROL_HALFDUPLEXCAP);
if (advertise & SUPPORTED_1000baseT_Half)
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
if (advertise & SUPPORTED_1000baseT_Full)
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
phy_write(phy, MII_1000BASETCONTROL, adv);
/* Start/Restart aneg */
ctl = phy_read(phy, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
{
u16 ctl, ctl2;
phy->autoneg = 0;
phy->speed = speed;
phy->duplex = fd;
phy->pause = 0;
ctl = phy_read(phy, MII_BMCR);
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
ctl |= BMCR_RESET;
/* Select speed & duplex */
switch(speed) {
case SPEED_10:
break;
case SPEED_100:
ctl |= BMCR_SPEED100;
break;
/* I'm not sure about the one below, again, Darwin source is
* quite confusing and I lack chip specs
*/
case SPEED_1000:
ctl |= BMCR_SPD2;
}
if (fd == DUPLEX_FULL)
ctl |= BMCR_FULLDPLX;
/* Disable crossover. Again, the way Apple does it is strange,
* though I don't assume they are wrong ;)
*/
ctl2 = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX |
MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX |
MII_1000BASETCONTROL_FULLDUPLEXCAP |
MII_1000BASETCONTROL_HALFDUPLEXCAP);
if (speed == SPEED_1000)
ctl2 |= (fd == DUPLEX_FULL) ?
MII_1000BASETCONTROL_FULLDUPLEXCAP :
MII_1000BASETCONTROL_HALFDUPLEXCAP;
phy_write(phy, MII_1000BASETCONTROL, ctl2);
// XXX Should we set the sungem to GII now on 1000BT ?
phy_write(phy, MII_BMCR, ctl);
return 0;
}
static int marvell_read_link(struct mii_phy *phy)
{
u16 status, pmask;
if (phy->autoneg) {
status = phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
return -EAGAIN;
if (status & MII_M1011_PHY_SPEC_STATUS_1000)
phy->speed = SPEED_1000;
else if (status & MII_M1011_PHY_SPEC_STATUS_100)
phy->speed = SPEED_100;
else
phy->speed = SPEED_10;
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
phy->duplex = DUPLEX_FULL;
else
phy->duplex = DUPLEX_HALF;
pmask = MII_M1011_PHY_SPEC_STATUS_TX_PAUSE |
MII_M1011_PHY_SPEC_STATUS_RX_PAUSE;
phy->pause = (status & pmask) == pmask;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
}
#define MII_BASIC_FEATURES \
(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | \
SUPPORTED_Pause)
/* On gigabit capable PHYs, we advertise Pause support but not asym pause
* support for now as I'm not sure it's supported and Darwin doesn't do
* it neither. --BenH.
*/
#define MII_GBIT_FEATURES \
(MII_BASIC_FEATURES | \
SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
/* Broadcom BCM 5201 */
static struct mii_phy_ops bcm5201_phy_ops = {
.init = bcm5201_init,
.suspend = bcm5201_suspend,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link,
};
static struct mii_phy_def bcm5201_phy_def = {
.phy_id = 0x00406210,
.phy_id_mask = 0xfffffff0,
.name = "BCM5201",
.features = MII_BASIC_FEATURES,
.magic_aneg = 1,
.ops = &bcm5201_phy_ops
};
/* Broadcom BCM 5221 */
static struct mii_phy_ops bcm5221_phy_ops = {
.suspend = bcm5221_suspend,
.init = bcm5221_init,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link,
};
static struct mii_phy_def bcm5221_phy_def = {
.phy_id = 0x004061e0,
.phy_id_mask = 0xfffffff0,
.name = "BCM5221",
.features = MII_BASIC_FEATURES,
.magic_aneg = 1,
.ops = &bcm5221_phy_ops
};
/* Broadcom BCM 5241 */
static struct mii_phy_ops bcm5241_phy_ops = {
.suspend = bcm5241_suspend,
.init = bcm5241_init,
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link,
};
static struct mii_phy_def bcm5241_phy_def = {
.phy_id = 0x0143bc30,
.phy_id_mask = 0xfffffff0,
.name = "BCM5241",
.features = MII_BASIC_FEATURES,
.magic_aneg = 1,
.ops = &bcm5241_phy_ops
};
/* Broadcom BCM 5400 */
static struct mii_phy_ops bcm5400_phy_ops = {
.init = bcm5400_init,
.suspend = bcm5400_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = genmii_poll_link,
.read_link = bcm54xx_read_link,
};
static struct mii_phy_def bcm5400_phy_def = {
.phy_id = 0x00206040,
.phy_id_mask = 0xfffffff0,
.name = "BCM5400",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5400_phy_ops
};
/* Broadcom BCM 5401 */
static struct mii_phy_ops bcm5401_phy_ops = {
.init = bcm5401_init,
.suspend = bcm5401_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = genmii_poll_link,
.read_link = bcm54xx_read_link,
};
static struct mii_phy_def bcm5401_phy_def = {
.phy_id = 0x00206050,
.phy_id_mask = 0xfffffff0,
.name = "BCM5401",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5401_phy_ops
};
/* Broadcom BCM 5411 */
static struct mii_phy_ops bcm5411_phy_ops = {
.init = bcm5411_init,
.suspend = generic_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = genmii_poll_link,
.read_link = bcm54xx_read_link,
};
static struct mii_phy_def bcm5411_phy_def = {
.phy_id = 0x00206070,
.phy_id_mask = 0xfffffff0,
.name = "BCM5411",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5411_phy_ops
};
/* Broadcom BCM 5421 */
static struct mii_phy_ops bcm5421_phy_ops = {
.init = bcm5421_init,
.suspend = generic_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = bcm5421_poll_link,
.read_link = bcm5421_read_link,
.enable_fiber = bcm5421_enable_fiber,
};
static struct mii_phy_def bcm5421_phy_def = {
.phy_id = 0x002060e0,
.phy_id_mask = 0xfffffff0,
.name = "BCM5421",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5421_phy_ops
};
/* Broadcom BCM 5421 built-in K2 */
static struct mii_phy_ops bcm5421k2_phy_ops = {
.init = bcm5421_init,
.suspend = generic_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = genmii_poll_link,
.read_link = bcm54xx_read_link,
};
static struct mii_phy_def bcm5421k2_phy_def = {
.phy_id = 0x002062e0,
.phy_id_mask = 0xfffffff0,
.name = "BCM5421-K2",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5421k2_phy_ops
};
static struct mii_phy_ops bcm5461_phy_ops = {
.init = bcm5421_init,
.suspend = generic_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = bcm5461_poll_link,
.read_link = bcm5461_read_link,
.enable_fiber = bcm5461_enable_fiber,
};
static struct mii_phy_def bcm5461_phy_def = {
.phy_id = 0x002060c0,
.phy_id_mask = 0xfffffff0,
.name = "BCM5461",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5461_phy_ops
};
/* Broadcom BCM 5462 built-in Vesta */
static struct mii_phy_ops bcm5462V_phy_ops = {
.init = bcm5421_init,
.suspend = generic_suspend,
.setup_aneg = bcm54xx_setup_aneg,
.setup_forced = bcm54xx_setup_forced,
.poll_link = genmii_poll_link,
.read_link = bcm54xx_read_link,
};
static struct mii_phy_def bcm5462V_phy_def = {
.phy_id = 0x002060d0,
.phy_id_mask = 0xfffffff0,
.name = "BCM5462-Vesta",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &bcm5462V_phy_ops
};
/* Marvell 88E1101 amd 88E1111 */
static struct mii_phy_ops marvell88e1101_phy_ops = {
.suspend = generic_suspend,
.setup_aneg = marvell_setup_aneg,
.setup_forced = marvell_setup_forced,
.poll_link = genmii_poll_link,
.read_link = marvell_read_link
};
static struct mii_phy_ops marvell88e1111_phy_ops = {
.init = marvell88e1111_init,
.suspend = generic_suspend,
.setup_aneg = marvell_setup_aneg,
.setup_forced = marvell_setup_forced,
.poll_link = genmii_poll_link,
.read_link = marvell_read_link
};
/* two revs in darwin for the 88e1101 ... I could use a datasheet
* to get the proper names...
*/
static struct mii_phy_def marvell88e1101v1_phy_def = {
.phy_id = 0x01410c20,
.phy_id_mask = 0xfffffff0,
.name = "Marvell 88E1101v1",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &marvell88e1101_phy_ops
};
static struct mii_phy_def marvell88e1101v2_phy_def = {
.phy_id = 0x01410c60,
.phy_id_mask = 0xfffffff0,
.name = "Marvell 88E1101v2",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &marvell88e1101_phy_ops
};
static struct mii_phy_def marvell88e1111_phy_def = {
.phy_id = 0x01410cc0,
.phy_id_mask = 0xfffffff0,
.name = "Marvell 88E1111",
.features = MII_GBIT_FEATURES,
.magic_aneg = 1,
.ops = &marvell88e1111_phy_ops
};
/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
.setup_aneg = genmii_setup_aneg,
.setup_forced = genmii_setup_forced,
.poll_link = genmii_poll_link,
.read_link = genmii_read_link
};
static struct mii_phy_def genmii_phy_def = {
.phy_id = 0x00000000,
.phy_id_mask = 0x00000000,
.name = "Generic MII",
.features = MII_BASIC_FEATURES,
.magic_aneg = 0,
.ops = &generic_phy_ops
};
static struct mii_phy_def* mii_phy_table[] = {
&bcm5201_phy_def,
&bcm5221_phy_def,
&bcm5241_phy_def,
&bcm5400_phy_def,
&bcm5401_phy_def,
&bcm5411_phy_def,
&bcm5421_phy_def,
&bcm5421k2_phy_def,
&bcm5461_phy_def,
&bcm5462V_phy_def,
&marvell88e1101v1_phy_def,
&marvell88e1101v2_phy_def,
&marvell88e1111_phy_def,
&genmii_phy_def,
NULL
};
int sungem_phy_probe(struct mii_phy *phy, int mii_id)
{
int rc;
u32 id;
struct mii_phy_def* def;
int i;
/* We do not reset the mii_phy structure as the driver
* may re-probe the PHY regulary
*/
phy->mii_id = mii_id;
/* Take PHY out of isloate mode and reset it. */
rc = reset_one_mii_phy(phy, mii_id);
if (rc)
goto fail;
/* Read ID and find matching entry */
id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2));
printk(KERN_DEBUG KBUILD_MODNAME ": " "PHY ID: %x, addr: %x\n",
id, mii_id);
for (i=0; (def = mii_phy_table[i]) != NULL; i++)
if ((id & def->phy_id_mask) == def->phy_id)
break;
/* Should never be NULL (we have a generic entry), but... */
if (def == NULL)
goto fail;
phy->def = def;
return 0;
fail:
phy->speed = 0;
phy->duplex = 0;
phy->pause = 0;
phy->advertising = 0;
return -ENODEV;
}
EXPORT_SYMBOL(sungem_phy_probe);
MODULE_LICENSE("GPL");
| gpl-2.0 |
sailesh341/lge-kernel-p880 | sound/soc/ep93xx/edb93xx.c | 2918 | 3672 | /*
* SoC audio for EDB93xx
*
* Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This driver support CS4271 codec being master or slave, working
* in control port mode, connected either via SPI or I2C.
* The data format accepted is I2S or left-justified.
* DAPM support not implemented.
*/
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include "ep93xx-pcm.h"
#define edb93xx_has_audio() (machine_is_edb9301() || \
machine_is_edb9302() || \
machine_is_edb9302a() || \
machine_is_edb9307a() || \
machine_is_edb9315a())
static int edb93xx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int err;
unsigned int mclk_rate;
unsigned int rate = params_rate(params);
/*
* According to CS4271 datasheet we use MCLK/LRCK=256 for
* rates below 50kHz and 128 for higher sample rates
*/
if (rate < 50000)
mclk_rate = rate * 64 * 4;
else
mclk_rate = rate * 64 * 2;
err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_IF |
SND_SOC_DAIFMT_CBS_CFS);
if (err)
return err;
err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_IF |
SND_SOC_DAIFMT_CBS_CFS);
if (err)
return err;
err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate,
SND_SOC_CLOCK_IN);
if (err)
return err;
return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate,
SND_SOC_CLOCK_OUT);
}
static struct snd_soc_ops edb93xx_ops = {
.hw_params = edb93xx_hw_params,
};
static struct snd_soc_dai_link edb93xx_dai = {
.name = "CS4271",
.stream_name = "CS4271 HiFi",
.platform_name = "ep93xx-pcm-audio",
.cpu_dai_name = "ep93xx-i2s",
.codec_name = "spi0.0",
.codec_dai_name = "cs4271-hifi",
.ops = &edb93xx_ops,
};
static struct snd_soc_card snd_soc_edb93xx = {
.name = "EDB93XX",
.dai_link = &edb93xx_dai,
.num_links = 1,
};
static struct platform_device *edb93xx_snd_device;
static int __init edb93xx_init(void)
{
int ret;
if (!edb93xx_has_audio())
return -ENODEV;
ret = ep93xx_i2s_acquire(EP93XX_SYSCON_DEVCFG_I2SONAC97,
EP93XX_SYSCON_I2SCLKDIV_ORIDE |
EP93XX_SYSCON_I2SCLKDIV_SPOL);
if (ret)
return ret;
edb93xx_snd_device = platform_device_alloc("soc-audio", -1);
if (!edb93xx_snd_device) {
ret = -ENOMEM;
goto free_i2s;
}
platform_set_drvdata(edb93xx_snd_device, &snd_soc_edb93xx);
ret = platform_device_add(edb93xx_snd_device);
if (ret)
goto device_put;
return 0;
device_put:
platform_device_put(edb93xx_snd_device);
free_i2s:
ep93xx_i2s_release();
return ret;
}
module_init(edb93xx_init);
static void __exit edb93xx_exit(void)
{
platform_device_unregister(edb93xx_snd_device);
ep93xx_i2s_release();
}
module_exit(edb93xx_exit);
MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
MODULE_DESCRIPTION("ALSA SoC EDB93xx");
MODULE_LICENSE("GPL");
| gpl-2.0 |
dsb9938/DNA_JB_KERNEL | arch/c6x/kernel/irq.c | 4454 | 3185 | /*
* Copyright (C) 2011 Texas Instruments Incorporated
*
* This borrows heavily from powerpc version, which is:
*
* Derived from arch/i386/kernel/irq.c
* Copyright (C) 1992 Linus Torvalds
* Adapted from arch/i386 by Gary Thomas
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
* Updated and modified by Cort Dougan <cort@fsmlabs.com>
* Copyright (C) 1996-2001 Cort Dougan
* Adapted for Power Macintosh by Paul Mackerras
* Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/slab.h>
#include <linux/seq_file.h>
#include <linux/radix-tree.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/megamod-pic.h>
#include <asm/special_insns.h>
unsigned long irq_err_count;
static DEFINE_RAW_SPINLOCK(core_irq_lock);
static void mask_core_irq(struct irq_data *data)
{
unsigned int prio = data->irq;
BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);
raw_spin_lock(&core_irq_lock);
and_creg(IER, ~(1 << prio));
raw_spin_unlock(&core_irq_lock);
}
static void unmask_core_irq(struct irq_data *data)
{
unsigned int prio = data->irq;
raw_spin_lock(&core_irq_lock);
or_creg(IER, 1 << prio);
raw_spin_unlock(&core_irq_lock);
}
static struct irq_chip core_chip = {
.name = "core",
.irq_mask = mask_core_irq,
.irq_unmask = unmask_core_irq,
};
asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
irq_enter();
BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);
generic_handle_irq(prio);
irq_exit();
set_irq_regs(old_regs);
}
static struct irq_domain *core_domain;
static int core_domain_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
if (hw < 4 || hw >= NR_PRIORITY_IRQS)
return -EINVAL;
irq_set_status_flags(virq, IRQ_LEVEL);
irq_set_chip_and_handler(virq, &core_chip, handle_level_irq);
return 0;
}
static const struct irq_domain_ops core_domain_ops = {
.map = core_domain_map,
.xlate = irq_domain_xlate_onecell,
};
void __init init_IRQ(void)
{
struct device_node *np;
/* Mask all priority IRQs */
and_creg(IER, ~0xfff0);
np = of_find_compatible_node(NULL, NULL, "ti,c64x+core-pic");
if (np != NULL) {
/* create the core host */
core_domain = irq_domain_add_legacy(np, NR_PRIORITY_IRQS,
0, 0, &core_domain_ops,
NULL);
if (core_domain)
irq_set_default_host(core_domain);
of_node_put(np);
}
printk(KERN_INFO "Core interrupt controller initialized\n");
/* now we're ready for other SoC controllers */
megamod_pic_init();
/* Clear all general IRQ flags */
set_creg(ICR, 0xfff0);
}
void ack_bad_irq(int irq)
{
printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
irq_err_count++;
}
int arch_show_interrupts(struct seq_file *p, int prec)
{
seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
return 0;
}
| gpl-2.0 |
Split-Screen/android_kernel_motorola_titan | arch/parisc/kernel/module.c | 5222 | 26003 | /* Kernel dynamically loadable module help for PARISC.
*
* The best reference for this stuff is probably the Processor-
* Specific ELF Supplement for PA-RISC:
* http://ftp.parisc-linux.org/docs/arch/elf-pa-hp.pdf
*
* Linux/PA-RISC Project (http://www.parisc-linux.org/)
* Copyright (C) 2003 Randolph Chung <tausq at debian . org>
* Copyright (C) 2008 Helge Deller <deller@gmx.de>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*
* Notes:
* - PLT stub handling
* On 32bit (and sometimes 64bit) and with big kernel modules like xfs or
* ipv6 the relocation types R_PARISC_PCREL17F and R_PARISC_PCREL22F may
* fail to reach their PLT stub if we only create one big stub array for
* all sections at the beginning of the core or init section.
* Instead we now insert individual PLT stub entries directly in front of
* of the code sections where the stubs are actually called.
* This reduces the distance between the PCREL location and the stub entry
* so that the relocations can be fulfilled.
* While calculating the final layout of the kernel module in memory, the
* kernel module loader calls arch_mod_section_prepend() to request the
* to be reserved amount of memory in front of each individual section.
*
* - SEGREL32 handling
* We are not doing SEGREL32 handling correctly. According to the ABI, we
* should do a value offset, like this:
* if (in_init(me, (void *)val))
* val -= (uint32_t)me->module_init;
* else
* val -= (uint32_t)me->module_core;
* However, SEGREL32 is used only for PARISC unwind entries, and we want
* those entries to have an absolute address, and not just an offset.
*
* The unwind table mechanism has the ability to specify an offset for
* the unwind table; however, because we split off the init functions into
* a different piece of memory, it is not possible to do this using a
* single offset. Instead, we use the above hack for now.
*/
#include <linux/moduleloader.h>
#include <linux/elf.h>
#include <linux/vmalloc.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <asm/pgtable.h>
#include <asm/unwind.h>
#if 0
#define DEBUGP printk
#else
#define DEBUGP(fmt...)
#endif
#define RELOC_REACHABLE(val, bits) \
(( ( !((val) & (1<<((bits)-1))) && ((val)>>(bits)) != 0 ) || \
( ((val) & (1<<((bits)-1))) && ((val)>>(bits)) != (((__typeof__(val))(~0))>>((bits)+2)))) ? \
0 : 1)
#define CHECK_RELOC(val, bits) \
if (!RELOC_REACHABLE(val, bits)) { \
printk(KERN_ERR "module %s relocation of symbol %s is out of range (0x%lx in %d bits)\n", \
me->name, strtab + sym->st_name, (unsigned long)val, bits); \
return -ENOEXEC; \
}
/* Maximum number of GOT entries. We use a long displacement ldd from
* the bottom of the table, which has a maximum signed displacement of
* 0x3fff; however, since we're only going forward, this becomes
* 0x1fff, and thus, since each GOT entry is 8 bytes long we can have
* at most 1023 entries.
* To overcome this 14bit displacement with some kernel modules, we'll
* use instead the unusal 16bit displacement method (see reassemble_16a)
* which gives us a maximum positive displacement of 0x7fff, and as such
* allows us to allocate up to 4095 GOT entries. */
#define MAX_GOTS 4095
/* three functions to determine where in the module core
* or init pieces the location is */
static inline int in_init(struct module *me, void *loc)
{
return (loc >= me->module_init &&
loc <= (me->module_init + me->init_size));
}
static inline int in_core(struct module *me, void *loc)
{
return (loc >= me->module_core &&
loc <= (me->module_core + me->core_size));
}
static inline int in_local(struct module *me, void *loc)
{
return in_init(me, loc) || in_core(me, loc);
}
#ifndef CONFIG_64BIT
struct got_entry {
Elf32_Addr addr;
};
struct stub_entry {
Elf32_Word insns[2]; /* each stub entry has two insns */
};
#else
struct got_entry {
Elf64_Addr addr;
};
struct stub_entry {
Elf64_Word insns[4]; /* each stub entry has four insns */
};
#endif
/* Field selection types defined by hppa */
#define rnd(x) (((x)+0x1000)&~0x1fff)
/* fsel: full 32 bits */
#define fsel(v,a) ((v)+(a))
/* lsel: select left 21 bits */
#define lsel(v,a) (((v)+(a))>>11)
/* rsel: select right 11 bits */
#define rsel(v,a) (((v)+(a))&0x7ff)
/* lrsel with rounding of addend to nearest 8k */
#define lrsel(v,a) (((v)+rnd(a))>>11)
/* rrsel with rounding of addend to nearest 8k */
#define rrsel(v,a) ((((v)+rnd(a))&0x7ff)+((a)-rnd(a)))
#define mask(x,sz) ((x) & ~((1<<(sz))-1))
/* The reassemble_* functions prepare an immediate value for
insertion into an opcode. pa-risc uses all sorts of weird bitfields
in the instruction to hold the value. */
static inline int sign_unext(int x, int len)
{
int len_ones;
len_ones = (1 << len) - 1;
return x & len_ones;
}
static inline int low_sign_unext(int x, int len)
{
int sign, temp;
sign = (x >> (len-1)) & 1;
temp = sign_unext(x, len-1);
return (temp << 1) | sign;
}
static inline int reassemble_14(int as14)
{
return (((as14 & 0x1fff) << 1) |
((as14 & 0x2000) >> 13));
}
static inline int reassemble_16a(int as16)
{
int s, t;
/* Unusual 16-bit encoding, for wide mode only. */
t = (as16 << 1) & 0xffff;
s = (as16 & 0x8000);
return (t ^ s ^ (s >> 1)) | (s >> 15);
}
static inline int reassemble_17(int as17)
{
return (((as17 & 0x10000) >> 16) |
((as17 & 0x0f800) << 5) |
((as17 & 0x00400) >> 8) |
((as17 & 0x003ff) << 3));
}
static inline int reassemble_21(int as21)
{
return (((as21 & 0x100000) >> 20) |
((as21 & 0x0ffe00) >> 8) |
((as21 & 0x000180) << 7) |
((as21 & 0x00007c) << 14) |
((as21 & 0x000003) << 12));
}
static inline int reassemble_22(int as22)
{
return (((as22 & 0x200000) >> 21) |
((as22 & 0x1f0000) << 5) |
((as22 & 0x00f800) << 5) |
((as22 & 0x000400) >> 8) |
((as22 & 0x0003ff) << 3));
}
void *module_alloc(unsigned long size)
{
if (size == 0)
return NULL;
/* using RWX means less protection for modules, but it's
* easier than trying to map the text, data, init_text and
* init_data correctly */
return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END,
GFP_KERNEL | __GFP_HIGHMEM,
PAGE_KERNEL_RWX, -1,
__builtin_return_address(0));
}
#ifndef CONFIG_64BIT
static inline unsigned long count_gots(const Elf_Rela *rela, unsigned long n)
{
return 0;
}
static inline unsigned long count_fdescs(const Elf_Rela *rela, unsigned long n)
{
return 0;
}
static inline unsigned long count_stubs(const Elf_Rela *rela, unsigned long n)
{
unsigned long cnt = 0;
for (; n > 0; n--, rela++)
{
switch (ELF32_R_TYPE(rela->r_info)) {
case R_PARISC_PCREL17F:
case R_PARISC_PCREL22F:
cnt++;
}
}
return cnt;
}
#else
static inline unsigned long count_gots(const Elf_Rela *rela, unsigned long n)
{
unsigned long cnt = 0;
for (; n > 0; n--, rela++)
{
switch (ELF64_R_TYPE(rela->r_info)) {
case R_PARISC_LTOFF21L:
case R_PARISC_LTOFF14R:
case R_PARISC_PCREL22F:
cnt++;
}
}
return cnt;
}
static inline unsigned long count_fdescs(const Elf_Rela *rela, unsigned long n)
{
unsigned long cnt = 0;
for (; n > 0; n--, rela++)
{
switch (ELF64_R_TYPE(rela->r_info)) {
case R_PARISC_FPTR64:
cnt++;
}
}
return cnt;
}
static inline unsigned long count_stubs(const Elf_Rela *rela, unsigned long n)
{
unsigned long cnt = 0;
for (; n > 0; n--, rela++)
{
switch (ELF64_R_TYPE(rela->r_info)) {
case R_PARISC_PCREL22F:
cnt++;
}
}
return cnt;
}
#endif
/* Free memory returned from module_alloc */
void module_free(struct module *mod, void *module_region)
{
kfree(mod->arch.section);
mod->arch.section = NULL;
vfree(module_region);
}
/* Additional bytes needed in front of individual sections */
unsigned int arch_mod_section_prepend(struct module *mod,
unsigned int section)
{
/* size needed for all stubs of this section (including
* one additional for correct alignment of the stubs) */
return (mod->arch.section[section].stub_entries + 1)
* sizeof(struct stub_entry);
}
#define CONST
int module_frob_arch_sections(CONST Elf_Ehdr *hdr,
CONST Elf_Shdr *sechdrs,
CONST char *secstrings,
struct module *me)
{
unsigned long gots = 0, fdescs = 0, len;
unsigned int i;
len = hdr->e_shnum * sizeof(me->arch.section[0]);
me->arch.section = kzalloc(len, GFP_KERNEL);
if (!me->arch.section)
return -ENOMEM;
for (i = 1; i < hdr->e_shnum; i++) {
const Elf_Rela *rels = (void *)sechdrs[i].sh_addr;
unsigned long nrels = sechdrs[i].sh_size / sizeof(*rels);
unsigned int count, s;
if (strncmp(secstrings + sechdrs[i].sh_name,
".PARISC.unwind", 14) == 0)
me->arch.unwind_section = i;
if (sechdrs[i].sh_type != SHT_RELA)
continue;
/* some of these are not relevant for 32-bit/64-bit
* we leave them here to make the code common. the
* compiler will do its thing and optimize out the
* stuff we don't need
*/
gots += count_gots(rels, nrels);
fdescs += count_fdescs(rels, nrels);
/* XXX: By sorting the relocs and finding duplicate entries
* we could reduce the number of necessary stubs and save
* some memory. */
count = count_stubs(rels, nrels);
if (!count)
continue;
/* so we need relocation stubs. reserve necessary memory. */
/* sh_info gives the section for which we need to add stubs. */
s = sechdrs[i].sh_info;
/* each code section should only have one relocation section */
WARN_ON(me->arch.section[s].stub_entries);
/* store number of stubs we need for this section */
me->arch.section[s].stub_entries += count;
}
/* align things a bit */
me->core_size = ALIGN(me->core_size, 16);
me->arch.got_offset = me->core_size;
me->core_size += gots * sizeof(struct got_entry);
me->core_size = ALIGN(me->core_size, 16);
me->arch.fdesc_offset = me->core_size;
me->core_size += fdescs * sizeof(Elf_Fdesc);
me->arch.got_max = gots;
me->arch.fdesc_max = fdescs;
return 0;
}
#ifdef CONFIG_64BIT
static Elf64_Word get_got(struct module *me, unsigned long value, long addend)
{
unsigned int i;
struct got_entry *got;
value += addend;
BUG_ON(value == 0);
got = me->module_core + me->arch.got_offset;
for (i = 0; got[i].addr; i++)
if (got[i].addr == value)
goto out;
BUG_ON(++me->arch.got_count > me->arch.got_max);
got[i].addr = value;
out:
DEBUGP("GOT ENTRY %d[%x] val %lx\n", i, i*sizeof(struct got_entry),
value);
return i * sizeof(struct got_entry);
}
#endif /* CONFIG_64BIT */
#ifdef CONFIG_64BIT
static Elf_Addr get_fdesc(struct module *me, unsigned long value)
{
Elf_Fdesc *fdesc = me->module_core + me->arch.fdesc_offset;
if (!value) {
printk(KERN_ERR "%s: zero OPD requested!\n", me->name);
return 0;
}
/* Look for existing fdesc entry. */
while (fdesc->addr) {
if (fdesc->addr == value)
return (Elf_Addr)fdesc;
fdesc++;
}
BUG_ON(++me->arch.fdesc_count > me->arch.fdesc_max);
/* Create new one */
fdesc->addr = value;
fdesc->gp = (Elf_Addr)me->module_core + me->arch.got_offset;
return (Elf_Addr)fdesc;
}
#endif /* CONFIG_64BIT */
enum elf_stub_type {
ELF_STUB_GOT,
ELF_STUB_MILLI,
ELF_STUB_DIRECT,
};
static Elf_Addr get_stub(struct module *me, unsigned long value, long addend,
enum elf_stub_type stub_type, Elf_Addr loc0, unsigned int targetsec)
{
struct stub_entry *stub;
int __maybe_unused d;
/* initialize stub_offset to point in front of the section */
if (!me->arch.section[targetsec].stub_offset) {
loc0 -= (me->arch.section[targetsec].stub_entries + 1) *
sizeof(struct stub_entry);
/* get correct alignment for the stubs */
loc0 = ALIGN(loc0, sizeof(struct stub_entry));
me->arch.section[targetsec].stub_offset = loc0;
}
/* get address of stub entry */
stub = (void *) me->arch.section[targetsec].stub_offset;
me->arch.section[targetsec].stub_offset += sizeof(struct stub_entry);
/* do not write outside available stub area */
BUG_ON(0 == me->arch.section[targetsec].stub_entries--);
#ifndef CONFIG_64BIT
/* for 32-bit the stub looks like this:
* ldil L'XXX,%r1
* be,n R'XXX(%sr4,%r1)
*/
//value = *(unsigned long *)((value + addend) & ~3); /* why? */
stub->insns[0] = 0x20200000; /* ldil L'XXX,%r1 */
stub->insns[1] = 0xe0202002; /* be,n R'XXX(%sr4,%r1) */
stub->insns[0] |= reassemble_21(lrsel(value, addend));
stub->insns[1] |= reassemble_17(rrsel(value, addend) / 4);
#else
/* for 64-bit we have three kinds of stubs:
* for normal function calls:
* ldd 0(%dp),%dp
* ldd 10(%dp), %r1
* bve (%r1)
* ldd 18(%dp), %dp
*
* for millicode:
* ldil 0, %r1
* ldo 0(%r1), %r1
* ldd 10(%r1), %r1
* bve,n (%r1)
*
* for direct branches (jumps between different section of the
* same module):
* ldil 0, %r1
* ldo 0(%r1), %r1
* bve,n (%r1)
*/
switch (stub_type) {
case ELF_STUB_GOT:
d = get_got(me, value, addend);
if (d <= 15) {
/* Format 5 */
stub->insns[0] = 0x0f6010db; /* ldd 0(%dp),%dp */
stub->insns[0] |= low_sign_unext(d, 5) << 16;
} else {
/* Format 3 */
stub->insns[0] = 0x537b0000; /* ldd 0(%dp),%dp */
stub->insns[0] |= reassemble_16a(d);
}
stub->insns[1] = 0x53610020; /* ldd 10(%dp),%r1 */
stub->insns[2] = 0xe820d000; /* bve (%r1) */
stub->insns[3] = 0x537b0030; /* ldd 18(%dp),%dp */
break;
case ELF_STUB_MILLI:
stub->insns[0] = 0x20200000; /* ldil 0,%r1 */
stub->insns[1] = 0x34210000; /* ldo 0(%r1), %r1 */
stub->insns[2] = 0x50210020; /* ldd 10(%r1),%r1 */
stub->insns[3] = 0xe820d002; /* bve,n (%r1) */
stub->insns[0] |= reassemble_21(lrsel(value, addend));
stub->insns[1] |= reassemble_14(rrsel(value, addend));
break;
case ELF_STUB_DIRECT:
stub->insns[0] = 0x20200000; /* ldil 0,%r1 */
stub->insns[1] = 0x34210000; /* ldo 0(%r1), %r1 */
stub->insns[2] = 0xe820d002; /* bve,n (%r1) */
stub->insns[0] |= reassemble_21(lrsel(value, addend));
stub->insns[1] |= reassemble_14(rrsel(value, addend));
break;
}
#endif
return (Elf_Addr)stub;
}
#ifndef CONFIG_64BIT
int apply_relocate_add(Elf_Shdr *sechdrs,
const char *strtab,
unsigned int symindex,
unsigned int relsec,
struct module *me)
{
int i;
Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
Elf32_Sym *sym;
Elf32_Word *loc;
Elf32_Addr val;
Elf32_Sword addend;
Elf32_Addr dot;
Elf_Addr loc0;
unsigned int targetsec = sechdrs[relsec].sh_info;
//unsigned long dp = (unsigned long)$global$;
register unsigned long dp asm ("r27");
DEBUGP("Applying relocate section %u to %u\n", relsec,
targetsec);
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
/* This is where to make the change */
loc = (void *)sechdrs[targetsec].sh_addr
+ rel[i].r_offset;
/* This is the start of the target section */
loc0 = sechdrs[targetsec].sh_addr;
/* This is the symbol it is referring to */
sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
+ ELF32_R_SYM(rel[i].r_info);
if (!sym->st_value) {
printk(KERN_WARNING "%s: Unknown symbol %s\n",
me->name, strtab + sym->st_name);
return -ENOENT;
}
//dot = (sechdrs[relsec].sh_addr + rel->r_offset) & ~0x03;
dot = (Elf32_Addr)loc & ~0x03;
val = sym->st_value;
addend = rel[i].r_addend;
#if 0
#define r(t) ELF32_R_TYPE(rel[i].r_info)==t ? #t :
DEBUGP("Symbol %s loc 0x%x val 0x%x addend 0x%x: %s\n",
strtab + sym->st_name,
(uint32_t)loc, val, addend,
r(R_PARISC_PLABEL32)
r(R_PARISC_DIR32)
r(R_PARISC_DIR21L)
r(R_PARISC_DIR14R)
r(R_PARISC_SEGREL32)
r(R_PARISC_DPREL21L)
r(R_PARISC_DPREL14R)
r(R_PARISC_PCREL17F)
r(R_PARISC_PCREL22F)
"UNKNOWN");
#undef r
#endif
switch (ELF32_R_TYPE(rel[i].r_info)) {
case R_PARISC_PLABEL32:
/* 32-bit function address */
/* no function descriptors... */
*loc = fsel(val, addend);
break;
case R_PARISC_DIR32:
/* direct 32-bit ref */
*loc = fsel(val, addend);
break;
case R_PARISC_DIR21L:
/* left 21 bits of effective address */
val = lrsel(val, addend);
*loc = mask(*loc, 21) | reassemble_21(val);
break;
case R_PARISC_DIR14R:
/* right 14 bits of effective address */
val = rrsel(val, addend);
*loc = mask(*loc, 14) | reassemble_14(val);
break;
case R_PARISC_SEGREL32:
/* 32-bit segment relative address */
/* See note about special handling of SEGREL32 at
* the beginning of this file.
*/
*loc = fsel(val, addend);
break;
case R_PARISC_DPREL21L:
/* left 21 bit of relative address */
val = lrsel(val - dp, addend);
*loc = mask(*loc, 21) | reassemble_21(val);
break;
case R_PARISC_DPREL14R:
/* right 14 bit of relative address */
val = rrsel(val - dp, addend);
*loc = mask(*loc, 14) | reassemble_14(val);
break;
case R_PARISC_PCREL17F:
/* 17-bit PC relative address */
/* calculate direct call offset */
val += addend;
val = (val - dot - 8)/4;
if (!RELOC_REACHABLE(val, 17)) {
/* direct distance too far, create
* stub entry instead */
val = get_stub(me, sym->st_value, addend,
ELF_STUB_DIRECT, loc0, targetsec);
val = (val - dot - 8)/4;
CHECK_RELOC(val, 17);
}
*loc = (*loc & ~0x1f1ffd) | reassemble_17(val);
break;
case R_PARISC_PCREL22F:
/* 22-bit PC relative address; only defined for pa20 */
/* calculate direct call offset */
val += addend;
val = (val - dot - 8)/4;
if (!RELOC_REACHABLE(val, 22)) {
/* direct distance too far, create
* stub entry instead */
val = get_stub(me, sym->st_value, addend,
ELF_STUB_DIRECT, loc0, targetsec);
val = (val - dot - 8)/4;
CHECK_RELOC(val, 22);
}
*loc = (*loc & ~0x3ff1ffd) | reassemble_22(val);
break;
default:
printk(KERN_ERR "module %s: Unknown relocation: %u\n",
me->name, ELF32_R_TYPE(rel[i].r_info));
return -ENOEXEC;
}
}
return 0;
}
#else
int apply_relocate_add(Elf_Shdr *sechdrs,
const char *strtab,
unsigned int symindex,
unsigned int relsec,
struct module *me)
{
int i;
Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
Elf64_Sym *sym;
Elf64_Word *loc;
Elf64_Xword *loc64;
Elf64_Addr val;
Elf64_Sxword addend;
Elf64_Addr dot;
Elf_Addr loc0;
unsigned int targetsec = sechdrs[relsec].sh_info;
DEBUGP("Applying relocate section %u to %u\n", relsec,
targetsec);
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
/* This is where to make the change */
loc = (void *)sechdrs[targetsec].sh_addr
+ rel[i].r_offset;
/* This is the start of the target section */
loc0 = sechdrs[targetsec].sh_addr;
/* This is the symbol it is referring to */
sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
+ ELF64_R_SYM(rel[i].r_info);
if (!sym->st_value) {
printk(KERN_WARNING "%s: Unknown symbol %s\n",
me->name, strtab + sym->st_name);
return -ENOENT;
}
//dot = (sechdrs[relsec].sh_addr + rel->r_offset) & ~0x03;
dot = (Elf64_Addr)loc & ~0x03;
loc64 = (Elf64_Xword *)loc;
val = sym->st_value;
addend = rel[i].r_addend;
#if 0
#define r(t) ELF64_R_TYPE(rel[i].r_info)==t ? #t :
printk("Symbol %s loc %p val 0x%Lx addend 0x%Lx: %s\n",
strtab + sym->st_name,
loc, val, addend,
r(R_PARISC_LTOFF14R)
r(R_PARISC_LTOFF21L)
r(R_PARISC_PCREL22F)
r(R_PARISC_DIR64)
r(R_PARISC_SEGREL32)
r(R_PARISC_FPTR64)
"UNKNOWN");
#undef r
#endif
switch (ELF64_R_TYPE(rel[i].r_info)) {
case R_PARISC_LTOFF21L:
/* LT-relative; left 21 bits */
val = get_got(me, val, addend);
DEBUGP("LTOFF21L Symbol %s loc %p val %lx\n",
strtab + sym->st_name,
loc, val);
val = lrsel(val, 0);
*loc = mask(*loc, 21) | reassemble_21(val);
break;
case R_PARISC_LTOFF14R:
/* L(ltoff(val+addend)) */
/* LT-relative; right 14 bits */
val = get_got(me, val, addend);
val = rrsel(val, 0);
DEBUGP("LTOFF14R Symbol %s loc %p val %lx\n",
strtab + sym->st_name,
loc, val);
*loc = mask(*loc, 14) | reassemble_14(val);
break;
case R_PARISC_PCREL22F:
/* PC-relative; 22 bits */
DEBUGP("PCREL22F Symbol %s loc %p val %lx\n",
strtab + sym->st_name,
loc, val);
val += addend;
/* can we reach it locally? */
if (in_local(me, (void *)val)) {
/* this is the case where the symbol is local
* to the module, but in a different section,
* so stub the jump in case it's more than 22
* bits away */
val = (val - dot - 8)/4;
if (!RELOC_REACHABLE(val, 22)) {
/* direct distance too far, create
* stub entry instead */
val = get_stub(me, sym->st_value,
addend, ELF_STUB_DIRECT,
loc0, targetsec);
} else {
/* Ok, we can reach it directly. */
val = sym->st_value;
val += addend;
}
} else {
val = sym->st_value;
if (strncmp(strtab + sym->st_name, "$$", 2)
== 0)
val = get_stub(me, val, addend, ELF_STUB_MILLI,
loc0, targetsec);
else
val = get_stub(me, val, addend, ELF_STUB_GOT,
loc0, targetsec);
}
DEBUGP("STUB FOR %s loc %lx, val %lx+%lx at %lx\n",
strtab + sym->st_name, loc, sym->st_value,
addend, val);
val = (val - dot - 8)/4;
CHECK_RELOC(val, 22);
*loc = (*loc & ~0x3ff1ffd) | reassemble_22(val);
break;
case R_PARISC_DIR64:
/* 64-bit effective address */
*loc64 = val + addend;
break;
case R_PARISC_SEGREL32:
/* 32-bit segment relative address */
/* See note about special handling of SEGREL32 at
* the beginning of this file.
*/
*loc = fsel(val, addend);
break;
case R_PARISC_FPTR64:
/* 64-bit function address */
if(in_local(me, (void *)(val + addend))) {
*loc64 = get_fdesc(me, val+addend);
DEBUGP("FDESC for %s at %p points to %lx\n",
strtab + sym->st_name, *loc64,
((Elf_Fdesc *)*loc64)->addr);
} else {
/* if the symbol is not local to this
* module then val+addend is a pointer
* to the function descriptor */
DEBUGP("Non local FPTR64 Symbol %s loc %p val %lx\n",
strtab + sym->st_name,
loc, val);
*loc64 = val + addend;
}
break;
default:
printk(KERN_ERR "module %s: Unknown relocation: %Lu\n",
me->name, ELF64_R_TYPE(rel[i].r_info));
return -ENOEXEC;
}
}
return 0;
}
#endif
static void
register_unwind_table(struct module *me,
const Elf_Shdr *sechdrs)
{
unsigned char *table, *end;
unsigned long gp;
if (!me->arch.unwind_section)
return;
table = (unsigned char *)sechdrs[me->arch.unwind_section].sh_addr;
end = table + sechdrs[me->arch.unwind_section].sh_size;
gp = (Elf_Addr)me->module_core + me->arch.got_offset;
DEBUGP("register_unwind_table(), sect = %d at 0x%p - 0x%p (gp=0x%lx)\n",
me->arch.unwind_section, table, end, gp);
me->arch.unwind = unwind_table_add(me->name, 0, gp, table, end);
}
static void
deregister_unwind_table(struct module *me)
{
if (me->arch.unwind)
unwind_table_remove(me->arch.unwind);
}
int module_finalize(const Elf_Ehdr *hdr,
const Elf_Shdr *sechdrs,
struct module *me)
{
int i;
unsigned long nsyms;
const char *strtab = NULL;
Elf_Sym *newptr, *oldptr;
Elf_Shdr *symhdr = NULL;
#ifdef DEBUG
Elf_Fdesc *entry;
u32 *addr;
entry = (Elf_Fdesc *)me->init;
printk("FINALIZE, ->init FPTR is %p, GP %lx ADDR %lx\n", entry,
entry->gp, entry->addr);
addr = (u32 *)entry->addr;
printk("INSNS: %x %x %x %x\n",
addr[0], addr[1], addr[2], addr[3]);
printk("got entries used %ld, gots max %ld\n"
"fdescs used %ld, fdescs max %ld\n",
me->arch.got_count, me->arch.got_max,
me->arch.fdesc_count, me->arch.fdesc_max);
#endif
register_unwind_table(me, sechdrs);
/* haven't filled in me->symtab yet, so have to find it
* ourselves */
for (i = 1; i < hdr->e_shnum; i++) {
if(sechdrs[i].sh_type == SHT_SYMTAB
&& (sechdrs[i].sh_flags & SHF_ALLOC)) {
int strindex = sechdrs[i].sh_link;
/* FIXME: AWFUL HACK
* The cast is to drop the const from
* the sechdrs pointer */
symhdr = (Elf_Shdr *)&sechdrs[i];
strtab = (char *)sechdrs[strindex].sh_addr;
break;
}
}
DEBUGP("module %s: strtab %p, symhdr %p\n",
me->name, strtab, symhdr);
if(me->arch.got_count > MAX_GOTS) {
printk(KERN_ERR "%s: Global Offset Table overflow (used %ld, allowed %d)\n",
me->name, me->arch.got_count, MAX_GOTS);
return -EINVAL;
}
kfree(me->arch.section);
me->arch.section = NULL;
/* no symbol table */
if(symhdr == NULL)
return 0;
oldptr = (void *)symhdr->sh_addr;
newptr = oldptr + 1; /* we start counting at 1 */
nsyms = symhdr->sh_size / sizeof(Elf_Sym);
DEBUGP("OLD num_symtab %lu\n", nsyms);
for (i = 1; i < nsyms; i++) {
oldptr++; /* note, count starts at 1 so preincrement */
if(strncmp(strtab + oldptr->st_name,
".L", 2) == 0)
continue;
if(newptr != oldptr)
*newptr++ = *oldptr;
else
newptr++;
}
nsyms = newptr - (Elf_Sym *)symhdr->sh_addr;
DEBUGP("NEW num_symtab %lu\n", nsyms);
symhdr->sh_size = nsyms * sizeof(Elf_Sym);
return 0;
}
void module_arch_cleanup(struct module *mod)
{
deregister_unwind_table(mod);
}
| gpl-2.0 |
dremaker/imx6ul_linux | arch/mips/cavium-octeon/executive/octeon-model.c | 7782 | 9566 | /***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#include <asm/octeon/octeon.h>
/**
* Given the chip processor ID from COP0, this function returns a
* string representing the chip model number. The string is of the
* form CNXXXXpX.X-FREQ-SUFFIX.
* - XXXX = The chip model number
* - X.X = Chip pass number
* - FREQ = Current frequency in Mhz
* - SUFFIX = NSP, EXP, SCP, SSP, or CP
*
* @chip_id: Chip ID
*
* Returns Model string
*/
const char *octeon_model_get_string(uint32_t chip_id)
{
static char buffer[32];
return octeon_model_get_string_buffer(chip_id, buffer);
}
/*
* Version of octeon_model_get_string() that takes buffer as argument,
* as running early in u-boot static/global variables don't work when
* running from flash.
*/
const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
{
const char *family;
const char *core_model;
char pass[4];
int clock_mhz;
const char *suffix;
union cvmx_l2d_fus3 fus3;
int num_cores;
union cvmx_mio_fus_dat2 fus_dat2;
union cvmx_mio_fus_dat3 fus_dat3;
char fuse_model[10];
uint32_t fuse_data = 0;
fus3.u64 = 0;
if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
/* Make sure the non existent devices look disabled */
switch ((chip_id >> 8) & 0xff) {
case 6: /* CN50XX */
case 2: /* CN30XX */
fus_dat3.s.nodfa_dte = 1;
fus_dat3.s.nozip = 1;
break;
case 4: /* CN57XX or CN56XX */
fus_dat3.s.nodfa_dte = 1;
break;
default:
break;
}
/* Make a guess at the suffix */
/* NSP = everything */
/* EXP = No crypto */
/* SCP = No DFA, No zip */
/* CP = No DFA, No crypto, No zip */
if (fus_dat3.s.nodfa_dte) {
if (fus_dat2.s.nocrypto)
suffix = "CP";
else
suffix = "SCP";
} else if (fus_dat2.s.nocrypto)
suffix = "EXP";
else
suffix = "NSP";
/*
* Assume pass number is encoded using <5:3><2:0>. Exceptions
* will be fixed later.
*/
sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
/*
* Use the number of cores to determine the last 2 digits of
* the model number. There are some exceptions that are fixed
* later.
*/
switch (num_cores) {
case 32:
core_model = "80";
break;
case 24:
core_model = "70";
break;
case 16:
core_model = "60";
break;
case 15:
core_model = "58";
break;
case 14:
core_model = "55";
break;
case 13:
core_model = "52";
break;
case 12:
core_model = "50";
break;
case 11:
core_model = "48";
break;
case 10:
core_model = "45";
break;
case 9:
core_model = "42";
break;
case 8:
core_model = "40";
break;
case 7:
core_model = "38";
break;
case 6:
core_model = "34";
break;
case 5:
core_model = "32";
break;
case 4:
core_model = "30";
break;
case 3:
core_model = "25";
break;
case 2:
core_model = "20";
break;
case 1:
core_model = "10";
break;
default:
core_model = "XX";
break;
}
/* Now figure out the family, the first two digits */
switch ((chip_id >> 8) & 0xff) {
case 0: /* CN38XX, CN37XX or CN36XX */
if (fus3.cn38xx.crip_512k) {
/*
* For some unknown reason, the 16 core one is
* called 37 instead of 36.
*/
if (num_cores >= 16)
family = "37";
else
family = "36";
} else
family = "38";
/*
* This series of chips didn't follow the standard
* pass numbering.
*/
switch (chip_id & 0xf) {
case 0:
strcpy(pass, "1.X");
break;
case 1:
strcpy(pass, "2.X");
break;
case 3:
strcpy(pass, "3.X");
break;
default:
strcpy(pass, "X.X");
break;
}
break;
case 1: /* CN31XX or CN3020 */
if ((chip_id & 0x10) || fus3.cn31xx.crip_128k)
family = "30";
else
family = "31";
/*
* This series of chips didn't follow the standard
* pass numbering.
*/
switch (chip_id & 0xf) {
case 0:
strcpy(pass, "1.0");
break;
case 2:
strcpy(pass, "1.1");
break;
default:
strcpy(pass, "X.X");
break;
}
break;
case 2: /* CN3010 or CN3005 */
family = "30";
/* A chip with half cache is an 05 */
if (fus3.cn30xx.crip_64k)
core_model = "05";
/*
* This series of chips didn't follow the standard
* pass numbering.
*/
switch (chip_id & 0xf) {
case 0:
strcpy(pass, "1.0");
break;
case 2:
strcpy(pass, "1.1");
break;
default:
strcpy(pass, "X.X");
break;
}
break;
case 3: /* CN58XX */
family = "58";
/* Special case. 4 core, half cache (CP with half cache) */
if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
core_model = "29";
/* Pass 1 uses different encodings for pass numbers */
if ((chip_id & 0xFF) < 0x8) {
switch (chip_id & 0x3) {
case 0:
strcpy(pass, "1.0");
break;
case 1:
strcpy(pass, "1.1");
break;
case 3:
strcpy(pass, "1.2");
break;
default:
strcpy(pass, "1.X");
break;
}
}
break;
case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
if (fus_dat2.cn56xx.raid_en) {
if (fus3.cn56xx.crip_1024k)
family = "55";
else
family = "57";
if (fus_dat2.cn56xx.nocrypto)
suffix = "SP";
else
suffix = "SSP";
} else {
if (fus_dat2.cn56xx.nocrypto)
suffix = "CP";
else {
suffix = "NSP";
if (fus_dat3.s.nozip)
suffix = "SCP";
if (fus_dat3.s.bar2_en)
suffix = "NSPB2";
}
if (fus3.cn56xx.crip_1024k)
family = "54";
else
family = "56";
}
break;
case 6: /* CN50XX */
family = "50";
break;
case 7: /* CN52XX */
if (fus3.cn52xx.crip_256k)
family = "51";
else
family = "52";
break;
case 0x93: /* CN61XX */
family = "61";
if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
suffix = "AP";
if (fus_dat2.cn61xx.nocrypto)
suffix = "CP";
else if (fus_dat2.cn61xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn61xx.nozip)
suffix = "SCP";
break;
case 0x90: /* CN63XX */
family = "63";
if (fus_dat3.s.l2c_crip == 2)
family = "62";
if (num_cores == 6) /* Other core counts match generic */
core_model = "35";
if (fus_dat2.cn63xx.nocrypto)
suffix = "CP";
else if (fus_dat2.cn63xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn63xx.nozip)
suffix = "SCP";
else
suffix = "AAP";
break;
case 0x92: /* CN66XX */
family = "66";
if (num_cores == 6) /* Other core counts match generic */
core_model = "35";
if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
suffix = "AP";
if (fus_dat2.cn66xx.nocrypto)
suffix = "CP";
else if (fus_dat2.cn66xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn66xx.nozip)
suffix = "SCP";
else
suffix = "AAP";
break;
case 0x91: /* CN68XX */
family = "68";
if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
suffix = "CP";
else if (fus_dat2.cn68xx.dorm_crypto)
suffix = "DAP";
else if (fus_dat3.cn68xx.nozip)
suffix = "SCP";
else if (fus_dat2.cn68xx.nocrypto)
suffix = "SP";
else
suffix = "AAP";
break;
default:
family = "XX";
core_model = "XX";
strcpy(pass, "X.X");
suffix = "XXX";
break;
}
clock_mhz = octeon_get_clock_rate() / 1000000;
if (family[0] != '3') {
int fuse_base = 384 / 8;
if (family[0] == '6')
fuse_base = 832 / 8;
/* Check for model in fuses, overrides normal decode */
/* This is _not_ valid for Octeon CN3XXX models */
fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
fuse_data = fuse_data << 8;
fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
fuse_data = fuse_data << 8;
fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
fuse_data = fuse_data << 8;
fuse_data |= cvmx_fuse_read_byte(fuse_base);
if (fuse_data & 0x7ffff) {
int model = fuse_data & 0x3fff;
int suffix = (fuse_data >> 14) & 0x1f;
if (suffix && model) {
/* Have both number and suffix in fuses, so both */
sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
core_model = "";
family = fuse_model;
} else if (suffix && !model) {
/* Only have suffix, so add suffix to 'normal' model number */
sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
core_model = fuse_model;
} else {
/* Don't have suffix, so just use model from fuses */
sprintf(fuse_model, "%d", model);
core_model = "";
family = fuse_model;
}
}
}
sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
return buffer;
}
| gpl-2.0 |
qubir/PhoenixA20_linux_sourcecode | net/netfilter/xt_time.c | 8806 | 7669 | /*
* xt_time
* Copyright © CC Computer Consultants GmbH, 2007
*
* based on ipt_time by Fabrice MARIE <fabrice@netfilter.org>
* This is a module which is used for time matching
* It is using some modified code from dietlibc (localtime() function)
* that you can find at http://www.fefe.de/dietlibc/
* This file is distributed under the terms of the GNU General Public
* License (GPL). Copies of the GPL can be obtained from gnu.org/gpl.
*/
#include <linux/ktime.h>
#include <linux/module.h>
#include <linux/skbuff.h>
#include <linux/types.h>
#include <linux/netfilter/x_tables.h>
#include <linux/netfilter/xt_time.h>
struct xtm {
u_int8_t month; /* (1-12) */
u_int8_t monthday; /* (1-31) */
u_int8_t weekday; /* (1-7) */
u_int8_t hour; /* (0-23) */
u_int8_t minute; /* (0-59) */
u_int8_t second; /* (0-59) */
unsigned int dse;
};
extern struct timezone sys_tz; /* ouch */
static const u_int16_t days_since_year[] = {
0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334,
};
static const u_int16_t days_since_leapyear[] = {
0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335,
};
/*
* Since time progresses forward, it is best to organize this array in reverse,
* to minimize lookup time.
*/
enum {
DSE_FIRST = 2039,
};
static const u_int16_t days_since_epoch[] = {
/* 2039 - 2030 */
25202, 24837, 24472, 24106, 23741, 23376, 23011, 22645, 22280, 21915,
/* 2029 - 2020 */
21550, 21184, 20819, 20454, 20089, 19723, 19358, 18993, 18628, 18262,
/* 2019 - 2010 */
17897, 17532, 17167, 16801, 16436, 16071, 15706, 15340, 14975, 14610,
/* 2009 - 2000 */
14245, 13879, 13514, 13149, 12784, 12418, 12053, 11688, 11323, 10957,
/* 1999 - 1990 */
10592, 10227, 9862, 9496, 9131, 8766, 8401, 8035, 7670, 7305,
/* 1989 - 1980 */
6940, 6574, 6209, 5844, 5479, 5113, 4748, 4383, 4018, 3652,
/* 1979 - 1970 */
3287, 2922, 2557, 2191, 1826, 1461, 1096, 730, 365, 0,
};
static inline bool is_leap(unsigned int y)
{
return y % 4 == 0 && (y % 100 != 0 || y % 400 == 0);
}
/*
* Each network packet has a (nano)seconds-since-the-epoch (SSTE) timestamp.
* Since we match against days and daytime, the SSTE value needs to be
* computed back into human-readable dates.
*
* This is done in three separate functions so that the most expensive
* calculations are done last, in case a "simple match" can be found earlier.
*/
static inline unsigned int localtime_1(struct xtm *r, time_t time)
{
unsigned int v, w;
/* Each day has 86400s, so finding the hour/minute is actually easy. */
v = time % 86400;
r->second = v % 60;
w = v / 60;
r->minute = w % 60;
r->hour = w / 60;
return v;
}
static inline void localtime_2(struct xtm *r, time_t time)
{
/*
* Here comes the rest (weekday, monthday). First, divide the SSTE
* by seconds-per-day to get the number of _days_ since the epoch.
*/
r->dse = time / 86400;
/*
* 1970-01-01 (w=0) was a Thursday (4).
* -1 and +1 map Sunday properly onto 7.
*/
r->weekday = (4 + r->dse - 1) % 7 + 1;
}
static void localtime_3(struct xtm *r, time_t time)
{
unsigned int year, i, w = r->dse;
/*
* In each year, a certain number of days-since-the-epoch have passed.
* Find the year that is closest to said days.
*
* Consider, for example, w=21612 (2029-03-04). Loop will abort on
* dse[i] <= w, which happens when dse[i] == 21550. This implies
* year == 2009. w will then be 62.
*/
for (i = 0, year = DSE_FIRST; days_since_epoch[i] > w;
++i, --year)
/* just loop */;
w -= days_since_epoch[i];
/*
* By now we have the current year, and the day of the year.
* r->yearday = w;
*
* On to finding the month (like above). In each month, a certain
* number of days-since-New Year have passed, and find the closest
* one.
*
* Consider w=62 (in a non-leap year). Loop will abort on
* dsy[i] < w, which happens when dsy[i] == 31+28 (i == 2).
* Concludes i == 2, i.e. 3rd month => March.
*
* (A different approach to use would be to subtract a monthlength
* from w repeatedly while counting.)
*/
if (is_leap(year)) {
/* use days_since_leapyear[] in a leap year */
for (i = ARRAY_SIZE(days_since_leapyear) - 1;
i > 0 && days_since_leapyear[i] > w; --i)
/* just loop */;
r->monthday = w - days_since_leapyear[i] + 1;
} else {
for (i = ARRAY_SIZE(days_since_year) - 1;
i > 0 && days_since_year[i] > w; --i)
/* just loop */;
r->monthday = w - days_since_year[i] + 1;
}
r->month = i + 1;
}
static bool
time_mt(const struct sk_buff *skb, struct xt_action_param *par)
{
const struct xt_time_info *info = par->matchinfo;
unsigned int packet_time;
struct xtm current_time;
s64 stamp;
/*
* We cannot use get_seconds() instead of __net_timestamp() here.
* Suppose you have two rules:
* 1. match before 13:00
* 2. match after 13:00
* If you match against processing time (get_seconds) it
* may happen that the same packet matches both rules if
* it arrived at the right moment before 13:00.
*/
if (skb->tstamp.tv64 == 0)
__net_timestamp((struct sk_buff *)skb);
stamp = ktime_to_ns(skb->tstamp);
stamp = div_s64(stamp, NSEC_PER_SEC);
if (info->flags & XT_TIME_LOCAL_TZ)
/* Adjust for local timezone */
stamp -= 60 * sys_tz.tz_minuteswest;
/*
* xt_time will match when _all_ of the following hold:
* - 'now' is in the global time range date_start..date_end
* - 'now' is in the monthday mask
* - 'now' is in the weekday mask
* - 'now' is in the daytime range time_start..time_end
* (and by default, libxt_time will set these so as to match)
*/
if (stamp < info->date_start || stamp > info->date_stop)
return false;
packet_time = localtime_1(¤t_time, stamp);
if (info->daytime_start < info->daytime_stop) {
if (packet_time < info->daytime_start ||
packet_time > info->daytime_stop)
return false;
} else {
if (packet_time < info->daytime_start &&
packet_time > info->daytime_stop)
return false;
}
localtime_2(¤t_time, stamp);
if (!(info->weekdays_match & (1 << current_time.weekday)))
return false;
/* Do not spend time computing monthday if all days match anyway */
if (info->monthdays_match != XT_TIME_ALL_MONTHDAYS) {
localtime_3(¤t_time, stamp);
if (!(info->monthdays_match & (1 << current_time.monthday)))
return false;
}
return true;
}
static int time_mt_check(const struct xt_mtchk_param *par)
{
const struct xt_time_info *info = par->matchinfo;
if (info->daytime_start > XT_TIME_MAX_DAYTIME ||
info->daytime_stop > XT_TIME_MAX_DAYTIME) {
pr_info("invalid argument - start or "
"stop time greater than 23:59:59\n");
return -EDOM;
}
return 0;
}
static struct xt_match xt_time_mt_reg __read_mostly = {
.name = "time",
.family = NFPROTO_UNSPEC,
.match = time_mt,
.checkentry = time_mt_check,
.matchsize = sizeof(struct xt_time_info),
.me = THIS_MODULE,
};
static int __init time_mt_init(void)
{
int minutes = sys_tz.tz_minuteswest;
if (minutes < 0) /* east of Greenwich */
printk(KERN_INFO KBUILD_MODNAME
": kernel timezone is +%02d%02d\n",
-minutes / 60, -minutes % 60);
else /* west of Greenwich */
printk(KERN_INFO KBUILD_MODNAME
": kernel timezone is -%02d%02d\n",
minutes / 60, minutes % 60);
return xt_register_match(&xt_time_mt_reg);
}
static void __exit time_mt_exit(void)
{
xt_unregister_match(&xt_time_mt_reg);
}
module_init(time_mt_init);
module_exit(time_mt_exit);
MODULE_AUTHOR("Jan Engelhardt <jengelh@medozas.de>");
MODULE_DESCRIPTION("Xtables: time-based matching");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ipt_time");
MODULE_ALIAS("ip6t_time");
| gpl-2.0 |
htc-mirror/endeavoru-2.6.39-86aa44d | Documentation/connector/cn_test.c | 9062 | 4694 | /*
* cn_test.c
*
* 2004+ Copyright (c) Evgeniy Polyakov <zbr@ioremap.net>
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define pr_fmt(fmt) "cn_test: " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/connector.h>
static struct cb_id cn_test_id = { CN_NETLINK_USERS + 3, 0x456 };
static char cn_test_name[] = "cn_test";
static struct sock *nls;
static struct timer_list cn_test_timer;
static void cn_test_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
{
pr_info("%s: %lu: idx=%x, val=%x, seq=%u, ack=%u, len=%d: %s.\n",
__func__, jiffies, msg->id.idx, msg->id.val,
msg->seq, msg->ack, msg->len,
msg->len ? (char *)msg->data : "");
}
/*
* Do not remove this function even if no one is using it as
* this is an example of how to get notifications about new
* connector user registration
*/
#if 0
static int cn_test_want_notify(void)
{
struct cn_ctl_msg *ctl;
struct cn_notify_req *req;
struct cn_msg *msg = NULL;
int size, size0;
struct sk_buff *skb;
struct nlmsghdr *nlh;
u32 group = 1;
size0 = sizeof(*msg) + sizeof(*ctl) + 3 * sizeof(*req);
size = NLMSG_SPACE(size0);
skb = alloc_skb(size, GFP_ATOMIC);
if (!skb) {
pr_err("failed to allocate new skb with size=%u\n", size);
return -ENOMEM;
}
nlh = NLMSG_PUT(skb, 0, 0x123, NLMSG_DONE, size - sizeof(*nlh));
msg = (struct cn_msg *)NLMSG_DATA(nlh);
memset(msg, 0, size0);
msg->id.idx = -1;
msg->id.val = -1;
msg->seq = 0x123;
msg->ack = 0x345;
msg->len = size0 - sizeof(*msg);
ctl = (struct cn_ctl_msg *)(msg + 1);
ctl->idx_notify_num = 1;
ctl->val_notify_num = 2;
ctl->group = group;
ctl->len = msg->len - sizeof(*ctl);
req = (struct cn_notify_req *)(ctl + 1);
/*
* Idx.
*/
req->first = cn_test_id.idx;
req->range = 10;
/*
* Val 0.
*/
req++;
req->first = cn_test_id.val;
req->range = 10;
/*
* Val 1.
*/
req++;
req->first = cn_test_id.val + 20;
req->range = 10;
NETLINK_CB(skb).dst_group = ctl->group;
//netlink_broadcast(nls, skb, 0, ctl->group, GFP_ATOMIC);
netlink_unicast(nls, skb, 0, 0);
pr_info("request was sent: group=0x%x\n", ctl->group);
return 0;
nlmsg_failure:
pr_err("failed to send %u.%u\n", msg->seq, msg->ack);
kfree_skb(skb);
return -EINVAL;
}
#endif
static u32 cn_test_timer_counter;
static void cn_test_timer_func(unsigned long __data)
{
struct cn_msg *m;
char data[32];
pr_debug("%s: timer fired with data %lu\n", __func__, __data);
m = kzalloc(sizeof(*m) + sizeof(data), GFP_ATOMIC);
if (m) {
memcpy(&m->id, &cn_test_id, sizeof(m->id));
m->seq = cn_test_timer_counter;
m->len = sizeof(data);
m->len =
scnprintf(data, sizeof(data), "counter = %u",
cn_test_timer_counter) + 1;
memcpy(m + 1, data, m->len);
cn_netlink_send(m, 0, GFP_ATOMIC);
kfree(m);
}
cn_test_timer_counter++;
mod_timer(&cn_test_timer, jiffies + msecs_to_jiffies(1000));
}
static int cn_test_init(void)
{
int err;
err = cn_add_callback(&cn_test_id, cn_test_name, cn_test_callback);
if (err)
goto err_out;
cn_test_id.val++;
err = cn_add_callback(&cn_test_id, cn_test_name, cn_test_callback);
if (err) {
cn_del_callback(&cn_test_id);
goto err_out;
}
setup_timer(&cn_test_timer, cn_test_timer_func, 0);
mod_timer(&cn_test_timer, jiffies + msecs_to_jiffies(1000));
pr_info("initialized with id={%u.%u}\n",
cn_test_id.idx, cn_test_id.val);
return 0;
err_out:
if (nls && nls->sk_socket)
sock_release(nls->sk_socket);
return err;
}
static void cn_test_fini(void)
{
del_timer_sync(&cn_test_timer);
cn_del_callback(&cn_test_id);
cn_test_id.val--;
cn_del_callback(&cn_test_id);
if (nls && nls->sk_socket)
sock_release(nls->sk_socket);
}
module_init(cn_test_init);
module_exit(cn_test_fini);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Evgeniy Polyakov <zbr@ioremap.net>");
MODULE_DESCRIPTION("Connector's test module");
| gpl-2.0 |
santod/NuK3rn3l_htc_m7_GPE-5.1 | Documentation/connector/cn_test.c | 9062 | 4694 | /*
* cn_test.c
*
* 2004+ Copyright (c) Evgeniy Polyakov <zbr@ioremap.net>
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define pr_fmt(fmt) "cn_test: " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/connector.h>
static struct cb_id cn_test_id = { CN_NETLINK_USERS + 3, 0x456 };
static char cn_test_name[] = "cn_test";
static struct sock *nls;
static struct timer_list cn_test_timer;
static void cn_test_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
{
pr_info("%s: %lu: idx=%x, val=%x, seq=%u, ack=%u, len=%d: %s.\n",
__func__, jiffies, msg->id.idx, msg->id.val,
msg->seq, msg->ack, msg->len,
msg->len ? (char *)msg->data : "");
}
/*
* Do not remove this function even if no one is using it as
* this is an example of how to get notifications about new
* connector user registration
*/
#if 0
static int cn_test_want_notify(void)
{
struct cn_ctl_msg *ctl;
struct cn_notify_req *req;
struct cn_msg *msg = NULL;
int size, size0;
struct sk_buff *skb;
struct nlmsghdr *nlh;
u32 group = 1;
size0 = sizeof(*msg) + sizeof(*ctl) + 3 * sizeof(*req);
size = NLMSG_SPACE(size0);
skb = alloc_skb(size, GFP_ATOMIC);
if (!skb) {
pr_err("failed to allocate new skb with size=%u\n", size);
return -ENOMEM;
}
nlh = NLMSG_PUT(skb, 0, 0x123, NLMSG_DONE, size - sizeof(*nlh));
msg = (struct cn_msg *)NLMSG_DATA(nlh);
memset(msg, 0, size0);
msg->id.idx = -1;
msg->id.val = -1;
msg->seq = 0x123;
msg->ack = 0x345;
msg->len = size0 - sizeof(*msg);
ctl = (struct cn_ctl_msg *)(msg + 1);
ctl->idx_notify_num = 1;
ctl->val_notify_num = 2;
ctl->group = group;
ctl->len = msg->len - sizeof(*ctl);
req = (struct cn_notify_req *)(ctl + 1);
/*
* Idx.
*/
req->first = cn_test_id.idx;
req->range = 10;
/*
* Val 0.
*/
req++;
req->first = cn_test_id.val;
req->range = 10;
/*
* Val 1.
*/
req++;
req->first = cn_test_id.val + 20;
req->range = 10;
NETLINK_CB(skb).dst_group = ctl->group;
//netlink_broadcast(nls, skb, 0, ctl->group, GFP_ATOMIC);
netlink_unicast(nls, skb, 0, 0);
pr_info("request was sent: group=0x%x\n", ctl->group);
return 0;
nlmsg_failure:
pr_err("failed to send %u.%u\n", msg->seq, msg->ack);
kfree_skb(skb);
return -EINVAL;
}
#endif
static u32 cn_test_timer_counter;
static void cn_test_timer_func(unsigned long __data)
{
struct cn_msg *m;
char data[32];
pr_debug("%s: timer fired with data %lu\n", __func__, __data);
m = kzalloc(sizeof(*m) + sizeof(data), GFP_ATOMIC);
if (m) {
memcpy(&m->id, &cn_test_id, sizeof(m->id));
m->seq = cn_test_timer_counter;
m->len = sizeof(data);
m->len =
scnprintf(data, sizeof(data), "counter = %u",
cn_test_timer_counter) + 1;
memcpy(m + 1, data, m->len);
cn_netlink_send(m, 0, GFP_ATOMIC);
kfree(m);
}
cn_test_timer_counter++;
mod_timer(&cn_test_timer, jiffies + msecs_to_jiffies(1000));
}
static int cn_test_init(void)
{
int err;
err = cn_add_callback(&cn_test_id, cn_test_name, cn_test_callback);
if (err)
goto err_out;
cn_test_id.val++;
err = cn_add_callback(&cn_test_id, cn_test_name, cn_test_callback);
if (err) {
cn_del_callback(&cn_test_id);
goto err_out;
}
setup_timer(&cn_test_timer, cn_test_timer_func, 0);
mod_timer(&cn_test_timer, jiffies + msecs_to_jiffies(1000));
pr_info("initialized with id={%u.%u}\n",
cn_test_id.idx, cn_test_id.val);
return 0;
err_out:
if (nls && nls->sk_socket)
sock_release(nls->sk_socket);
return err;
}
static void cn_test_fini(void)
{
del_timer_sync(&cn_test_timer);
cn_del_callback(&cn_test_id);
cn_test_id.val--;
cn_del_callback(&cn_test_id);
if (nls && nls->sk_socket)
sock_release(nls->sk_socket);
}
module_init(cn_test_init);
module_exit(cn_test_fini);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Evgeniy Polyakov <zbr@ioremap.net>");
MODULE_DESCRIPTION("Connector's test module");
| gpl-2.0 |
avinashphilip/am335x_linux | arch/x86/um/sys_call_table_32.c | 103 | 1253 | /*
* System call table for UML/i386, copied from arch/x86/kernel/syscall_*.c
* with some changes for UML.
*/
#include <linux/linkage.h>
#include <linux/sys.h>
#include <linux/cache.h>
#include <generated/user_constants.h>
#define __NO_STUBS
/*
* Below you can see, in terms of #define's, the differences between the x86-64
* and the UML syscall table.
*/
/* Not going to be implemented by UML, since we have no hardware. */
#define sys_iopl sys_ni_syscall
#define sys_ioperm sys_ni_syscall
#define sys_vm86old sys_ni_syscall
#define sys_vm86 sys_ni_syscall
#define old_mmap sys_old_mmap
#define ptregs_iopl sys_iopl
#define ptregs_vm86old sys_vm86old
#define ptregs_vm86 sys_vm86
#define __SYSCALL_I386(nr, sym, compat) extern asmlinkage void sym(void) ;
#include <asm/syscalls_32.h>
#undef __SYSCALL_I386
#define __SYSCALL_I386(nr, sym, compat) [ nr ] = sym,
typedef asmlinkage void (*sys_call_ptr_t)(void);
extern asmlinkage void sys_ni_syscall(void);
const sys_call_ptr_t sys_call_table[] __cacheline_aligned = {
/*
* Smells like a compiler bug -- it doesn't work
* when the & below is removed.
*/
[0 ... __NR_syscall_max] = &sys_ni_syscall,
#include <asm/syscalls_32.h>
};
int syscall_table_size = sizeof(sys_call_table);
| gpl-2.0 |
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