repo_name string | path string | copies string | size string | content string | license string |
|---|---|---|---|---|---|
ztemt/NX511J_5.1_kernel | samples/kfifo/inttype-example.c | 10729 | 3831 | /*
* Sample kfifo int type implementation
*
* Copyright (C) 2010 Stefani Seibold <stefani@seibold.net>
*
* Released under the GPL version 2 only.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/mutex.h>
#include <linux/kfifo.h>
/*
* This module shows how to create a int type fifo.
*/
/* fifo size in elements (ints) */
#define FIFO_SIZE 32
/* name of the proc entry */
#define PROC_FIFO "int-fifo"
/* lock for procfs read access */
static DEFINE_MUTEX(read_lock);
/* lock for procfs write access */
static DEFINE_MUTEX(write_lock);
/*
* define DYNAMIC in this example for a dynamically allocated fifo.
*
* Otherwise the fifo storage will be a part of the fifo structure.
*/
#if 0
#define DYNAMIC
#endif
#ifdef DYNAMIC
static DECLARE_KFIFO_PTR(test, int);
#else
static DEFINE_KFIFO(test, int, FIFO_SIZE);
#endif
static const int expected_result[FIFO_SIZE] = {
3, 4, 5, 6, 7, 8, 9, 0,
1, 20, 21, 22, 23, 24, 25, 26,
27, 28, 29, 30, 31, 32, 33, 34,
35, 36, 37, 38, 39, 40, 41, 42,
};
static int __init testfunc(void)
{
int buf[6];
int i, j;
unsigned int ret;
printk(KERN_INFO "int fifo test start\n");
/* put values into the fifo */
for (i = 0; i != 10; i++)
kfifo_put(&test, &i);
/* show the number of used elements */
printk(KERN_INFO "fifo len: %u\n", kfifo_len(&test));
/* get max of 2 elements from the fifo */
ret = kfifo_out(&test, buf, 2);
printk(KERN_INFO "ret: %d\n", ret);
/* and put it back to the end of the fifo */
ret = kfifo_in(&test, buf, ret);
printk(KERN_INFO "ret: %d\n", ret);
/* skip first element of the fifo */
printk(KERN_INFO "skip 1st element\n");
kfifo_skip(&test);
/* put values into the fifo until is full */
for (i = 20; kfifo_put(&test, &i); i++)
;
printk(KERN_INFO "queue len: %u\n", kfifo_len(&test));
/* show the first value without removing from the fifo */
if (kfifo_peek(&test, &i))
printk(KERN_INFO "%d\n", i);
/* check the correctness of all values in the fifo */
j = 0;
while (kfifo_get(&test, &i)) {
printk(KERN_INFO "item = %d\n", i);
if (i != expected_result[j++]) {
printk(KERN_WARNING "value mismatch: test failed\n");
return -EIO;
}
}
if (j != ARRAY_SIZE(expected_result)) {
printk(KERN_WARNING "size mismatch: test failed\n");
return -EIO;
}
printk(KERN_INFO "test passed\n");
return 0;
}
static ssize_t fifo_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
int ret;
unsigned int copied;
if (mutex_lock_interruptible(&write_lock))
return -ERESTARTSYS;
ret = kfifo_from_user(&test, buf, count, &copied);
mutex_unlock(&write_lock);
return ret ? ret : copied;
}
static ssize_t fifo_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
int ret;
unsigned int copied;
if (mutex_lock_interruptible(&read_lock))
return -ERESTARTSYS;
ret = kfifo_to_user(&test, buf, count, &copied);
mutex_unlock(&read_lock);
return ret ? ret : copied;
}
static const struct file_operations fifo_fops = {
.owner = THIS_MODULE,
.read = fifo_read,
.write = fifo_write,
.llseek = noop_llseek,
};
static int __init example_init(void)
{
#ifdef DYNAMIC
int ret;
ret = kfifo_alloc(&test, FIFO_SIZE, GFP_KERNEL);
if (ret) {
printk(KERN_ERR "error kfifo_alloc\n");
return ret;
}
#endif
if (testfunc() < 0) {
#ifdef DYNAMIC
kfifo_free(&test);
#endif
return -EIO;
}
if (proc_create(PROC_FIFO, 0, NULL, &fifo_fops) == NULL) {
#ifdef DYNAMIC
kfifo_free(&test);
#endif
return -ENOMEM;
}
return 0;
}
static void __exit example_exit(void)
{
remove_proc_entry(PROC_FIFO, NULL);
#ifdef DYNAMIC
kfifo_free(&test);
#endif
}
module_init(example_init);
module_exit(example_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Stefani Seibold <stefani@seibold.net>");
| gpl-2.0 |
RonGokhale/lge-kernel-pecan | arch/powerpc/kernel/setup_32.c | 490 | 8364 | /*
* Common prep/pmac/chrp boot and setup code.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/reboot.h>
#include <linux/delay.h>
#include <linux/initrd.h>
#include <linux/tty.h>
#include <linux/bootmem.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/console.h>
#include <linux/lmb.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/setup.h>
#include <asm/smp.h>
#include <asm/elf.h>
#include <asm/cputable.h>
#include <asm/bootx.h>
#include <asm/btext.h>
#include <asm/machdep.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/pmac_feature.h>
#include <asm/sections.h>
#include <asm/nvram.h>
#include <asm/xmon.h>
#include <asm/time.h>
#include <asm/serial.h>
#include <asm/udbg.h>
#include <asm/mmu_context.h>
#include <asm/swiotlb.h>
#include "setup.h"
#define DBG(fmt...)
extern void bootx_init(unsigned long r4, unsigned long phys);
int boot_cpuid;
EXPORT_SYMBOL_GPL(boot_cpuid);
int boot_cpuid_phys;
int smp_hw_index[NR_CPUS];
unsigned long ISA_DMA_THRESHOLD;
unsigned int DMA_MODE_READ;
unsigned int DMA_MODE_WRITE;
#ifdef CONFIG_VGA_CONSOLE
unsigned long vgacon_remap_base;
EXPORT_SYMBOL(vgacon_remap_base);
#endif
/*
* These are used in binfmt_elf.c to put aux entries on the stack
* for each elf executable being started.
*/
int dcache_bsize;
int icache_bsize;
int ucache_bsize;
/*
* We're called here very early in the boot. We determine the machine
* type and call the appropriate low-level setup functions.
* -- Cort <cort@fsmlabs.com>
*
* Note that the kernel may be running at an address which is different
* from the address that it was linked at, so we must use RELOC/PTRRELOC
* to access static data (including strings). -- paulus
*/
notrace unsigned long __init early_init(unsigned long dt_ptr)
{
unsigned long offset = reloc_offset();
struct cpu_spec *spec;
/* First zero the BSS -- use memset_io, some platforms don't have
* caches on yet */
memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
__bss_stop - __bss_start);
/*
* Identify the CPU type and fix up code sections
* that depend on which cpu we have.
*/
spec = identify_cpu(offset, mfspr(SPRN_PVR));
do_feature_fixups(spec->cpu_features,
PTRRELOC(&__start___ftr_fixup),
PTRRELOC(&__stop___ftr_fixup));
do_feature_fixups(spec->mmu_features,
PTRRELOC(&__start___mmu_ftr_fixup),
PTRRELOC(&__stop___mmu_ftr_fixup));
do_lwsync_fixups(spec->cpu_features,
PTRRELOC(&__start___lwsync_fixup),
PTRRELOC(&__stop___lwsync_fixup));
return KERNELBASE + offset;
}
/*
* Find out what kind of machine we're on and save any data we need
* from the early boot process (devtree is copied on pmac by prom_init()).
* This is called very early on the boot process, after a minimal
* MMU environment has been set up but before MMU_init is called.
*/
notrace void __init machine_init(unsigned long dt_ptr)
{
lockdep_init();
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
/* Do some early initialization based on the flat device tree */
early_init_devtree(__va(dt_ptr));
probe_machine();
setup_kdump_trampoline();
#ifdef CONFIG_6xx
if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
cpu_has_feature(CPU_FTR_CAN_NAP))
ppc_md.power_save = ppc6xx_idle;
#endif
#ifdef CONFIG_E500
if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
cpu_has_feature(CPU_FTR_CAN_NAP))
ppc_md.power_save = e500_idle;
#endif
if (ppc_md.progress)
ppc_md.progress("id mach(): done", 0x200);
}
#ifdef CONFIG_BOOKE_WDT
/* Checks wdt=x and wdt_period=xx command-line option */
notrace int __init early_parse_wdt(char *p)
{
if (p && strncmp(p, "0", 1) != 0)
booke_wdt_enabled = 1;
return 0;
}
early_param("wdt", early_parse_wdt);
int __init early_parse_wdt_period (char *p)
{
if (p)
booke_wdt_period = simple_strtoul(p, NULL, 0);
return 0;
}
early_param("wdt_period", early_parse_wdt_period);
#endif /* CONFIG_BOOKE_WDT */
/* Checks "l2cr=xxxx" command-line option */
int __init ppc_setup_l2cr(char *str)
{
if (cpu_has_feature(CPU_FTR_L2CR)) {
unsigned long val = simple_strtoul(str, NULL, 0);
printk(KERN_INFO "l2cr set to %lx\n", val);
_set_L2CR(0); /* force invalidate by disable cache */
_set_L2CR(val); /* and enable it */
}
return 1;
}
__setup("l2cr=", ppc_setup_l2cr);
/* Checks "l3cr=xxxx" command-line option */
int __init ppc_setup_l3cr(char *str)
{
if (cpu_has_feature(CPU_FTR_L3CR)) {
unsigned long val = simple_strtoul(str, NULL, 0);
printk(KERN_INFO "l3cr set to %lx\n", val);
_set_L3CR(val); /* and enable it */
}
return 1;
}
__setup("l3cr=", ppc_setup_l3cr);
#ifdef CONFIG_GENERIC_NVRAM
/* Generic nvram hooks used by drivers/char/gen_nvram.c */
unsigned char nvram_read_byte(int addr)
{
if (ppc_md.nvram_read_val)
return ppc_md.nvram_read_val(addr);
return 0xff;
}
EXPORT_SYMBOL(nvram_read_byte);
void nvram_write_byte(unsigned char val, int addr)
{
if (ppc_md.nvram_write_val)
ppc_md.nvram_write_val(addr, val);
}
EXPORT_SYMBOL(nvram_write_byte);
ssize_t nvram_get_size(void)
{
if (ppc_md.nvram_size)
return ppc_md.nvram_size();
return -1;
}
EXPORT_SYMBOL(nvram_get_size);
void nvram_sync(void)
{
if (ppc_md.nvram_sync)
ppc_md.nvram_sync();
}
EXPORT_SYMBOL(nvram_sync);
#endif /* CONFIG_NVRAM */
int __init ppc_init(void)
{
/* clear the progress line */
if (ppc_md.progress)
ppc_md.progress(" ", 0xffff);
/* call platform init */
if (ppc_md.init != NULL) {
ppc_md.init();
}
return 0;
}
arch_initcall(ppc_init);
#ifdef CONFIG_IRQSTACKS
static void __init irqstack_early_init(void)
{
unsigned int i;
/* interrupt stacks must be in lowmem, we get that for free on ppc32
* as the lmb is limited to lowmem by LMB_REAL_LIMIT */
for_each_possible_cpu(i) {
softirq_ctx[i] = (struct thread_info *)
__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
hardirq_ctx[i] = (struct thread_info *)
__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
}
}
#else
#define irqstack_early_init()
#endif
#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
static void __init exc_lvl_early_init(void)
{
unsigned int i;
/* interrupt stacks must be in lowmem, we get that for free on ppc32
* as the lmb is limited to lowmem by LMB_REAL_LIMIT */
for_each_possible_cpu(i) {
critirq_ctx[i] = (struct thread_info *)
__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
#ifdef CONFIG_BOOKE
dbgirq_ctx[i] = (struct thread_info *)
__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
mcheckirq_ctx[i] = (struct thread_info *)
__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
#endif
}
}
#else
#define exc_lvl_early_init()
#endif
/* Warning, IO base is not yet inited */
void __init setup_arch(char **cmdline_p)
{
*cmdline_p = cmd_line;
/* so udelay does something sensible, assume <= 1000 bogomips */
loops_per_jiffy = 500000000 / HZ;
unflatten_device_tree();
check_for_initrd();
if (ppc_md.init_early)
ppc_md.init_early();
find_legacy_serial_ports();
smp_setup_cpu_maps();
/* Register early console */
register_early_udbg_console();
xmon_setup();
/*
* Set cache line size based on type of cpu as a default.
* Systems with OF can look in the properties on the cpu node(s)
* for a possibly more accurate value.
*/
dcache_bsize = cur_cpu_spec->dcache_bsize;
icache_bsize = cur_cpu_spec->icache_bsize;
ucache_bsize = 0;
if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
ucache_bsize = icache_bsize = dcache_bsize;
/* reboot on panic */
panic_timeout = 180;
if (ppc_md.panic)
setup_panic();
init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long) _etext;
init_mm.end_data = (unsigned long) _edata;
init_mm.brk = klimit;
exc_lvl_early_init();
irqstack_early_init();
/* set up the bootmem stuff with available memory */
do_init_bootmem();
if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
if (ppc_md.setup_arch)
ppc_md.setup_arch();
if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
#ifdef CONFIG_SWIOTLB
if (ppc_swiotlb_enable)
swiotlb_init();
#endif
paging_init();
/* Initialize the MMU context management stuff */
mmu_context_init();
}
| gpl-2.0 |
shminer/LG-F460-Kernel | drivers/isdn/gigaset/ser-gigaset.c | 490 | 19241 | /* This is the serial hardware link layer (HLL) for the Gigaset 307x isdn
* DECT base (aka Sinus 45 isdn) using the RS232 DECT data module M101,
* written as a line discipline.
*
* =====================================================================
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* =====================================================================
*/
#include "gigaset.h"
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/completion.h>
/* Version Information */
#define DRIVER_AUTHOR "Tilman Schmidt"
#define DRIVER_DESC "Serial Driver for Gigaset 307x using Siemens M101"
#define GIGASET_MINORS 1
#define GIGASET_MINOR 0
#define GIGASET_MODULENAME "ser_gigaset"
#define GIGASET_DEVNAME "ttyGS"
/* length limit according to Siemens 3070usb-protokoll.doc ch. 2.1 */
#define IF_WRITEBUF 264
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS_LDISC(N_GIGASET_M101);
static int startmode = SM_ISDN;
module_param(startmode, int, S_IRUGO);
MODULE_PARM_DESC(startmode, "initial operation mode");
static int cidmode = 1;
module_param(cidmode, int, S_IRUGO);
MODULE_PARM_DESC(cidmode, "stay in CID mode when idle");
static struct gigaset_driver *driver;
struct ser_cardstate {
struct platform_device dev;
struct tty_struct *tty;
atomic_t refcnt;
struct completion dead_cmp;
};
static struct platform_driver device_driver = {
.driver = {
.name = GIGASET_MODULENAME,
},
};
static void flush_send_queue(struct cardstate *);
/* transmit data from current open skb
* result: number of bytes sent or error code < 0
*/
static int write_modem(struct cardstate *cs)
{
struct tty_struct *tty = cs->hw.ser->tty;
struct bc_state *bcs = &cs->bcs[0]; /* only one channel */
struct sk_buff *skb = bcs->tx_skb;
int sent = -EOPNOTSUPP;
if (!tty || !tty->driver || !skb)
return -EINVAL;
if (!skb->len) {
dev_kfree_skb_any(skb);
bcs->tx_skb = NULL;
return -EINVAL;
}
set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
if (tty->ops->write)
sent = tty->ops->write(tty, skb->data, skb->len);
gig_dbg(DEBUG_OUTPUT, "write_modem: sent %d", sent);
if (sent < 0) {
/* error */
flush_send_queue(cs);
return sent;
}
skb_pull(skb, sent);
if (!skb->len) {
/* skb sent completely */
gigaset_skb_sent(bcs, skb);
gig_dbg(DEBUG_INTR, "kfree skb (Adr: %lx)!",
(unsigned long) skb);
dev_kfree_skb_any(skb);
bcs->tx_skb = NULL;
}
return sent;
}
/*
* transmit first queued command buffer
* result: number of bytes sent or error code < 0
*/
static int send_cb(struct cardstate *cs)
{
struct tty_struct *tty = cs->hw.ser->tty;
struct cmdbuf_t *cb, *tcb;
unsigned long flags;
int sent = 0;
if (!tty || !tty->driver)
return -EFAULT;
cb = cs->cmdbuf;
if (!cb)
return 0; /* nothing to do */
if (cb->len) {
set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
sent = tty->ops->write(tty, cb->buf + cb->offset, cb->len);
if (sent < 0) {
/* error */
gig_dbg(DEBUG_OUTPUT, "send_cb: write error %d", sent);
flush_send_queue(cs);
return sent;
}
cb->offset += sent;
cb->len -= sent;
gig_dbg(DEBUG_OUTPUT, "send_cb: sent %d, left %u, queued %u",
sent, cb->len, cs->cmdbytes);
}
while (cb && !cb->len) {
spin_lock_irqsave(&cs->cmdlock, flags);
cs->cmdbytes -= cs->curlen;
tcb = cb;
cs->cmdbuf = cb = cb->next;
if (cb) {
cb->prev = NULL;
cs->curlen = cb->len;
} else {
cs->lastcmdbuf = NULL;
cs->curlen = 0;
}
spin_unlock_irqrestore(&cs->cmdlock, flags);
if (tcb->wake_tasklet)
tasklet_schedule(tcb->wake_tasklet);
kfree(tcb);
}
return sent;
}
/*
* send queue tasklet
* If there is already a skb opened, put data to the transfer buffer
* by calling "write_modem".
* Otherwise take a new skb out of the queue.
*/
static void gigaset_modem_fill(unsigned long data)
{
struct cardstate *cs = (struct cardstate *) data;
struct bc_state *bcs;
struct sk_buff *nextskb;
int sent = 0;
if (!cs) {
gig_dbg(DEBUG_OUTPUT, "%s: no cardstate", __func__);
return;
}
bcs = cs->bcs;
if (!bcs) {
gig_dbg(DEBUG_OUTPUT, "%s: no cardstate", __func__);
return;
}
if (!bcs->tx_skb) {
/* no skb is being sent; send command if any */
sent = send_cb(cs);
gig_dbg(DEBUG_OUTPUT, "%s: send_cb -> %d", __func__, sent);
if (sent)
/* something sent or error */
return;
/* no command to send; get skb */
nextskb = skb_dequeue(&bcs->squeue);
if (!nextskb)
/* no skb either, nothing to do */
return;
bcs->tx_skb = nextskb;
gig_dbg(DEBUG_INTR, "Dequeued skb (Adr: %lx)",
(unsigned long) bcs->tx_skb);
}
/* send skb */
gig_dbg(DEBUG_OUTPUT, "%s: tx_skb", __func__);
if (write_modem(cs) < 0)
gig_dbg(DEBUG_OUTPUT, "%s: write_modem failed", __func__);
}
/*
* throw away all data queued for sending
*/
static void flush_send_queue(struct cardstate *cs)
{
struct sk_buff *skb;
struct cmdbuf_t *cb;
unsigned long flags;
/* command queue */
spin_lock_irqsave(&cs->cmdlock, flags);
while ((cb = cs->cmdbuf) != NULL) {
cs->cmdbuf = cb->next;
if (cb->wake_tasklet)
tasklet_schedule(cb->wake_tasklet);
kfree(cb);
}
cs->cmdbuf = cs->lastcmdbuf = NULL;
cs->cmdbytes = cs->curlen = 0;
spin_unlock_irqrestore(&cs->cmdlock, flags);
/* data queue */
if (cs->bcs->tx_skb)
dev_kfree_skb_any(cs->bcs->tx_skb);
while ((skb = skb_dequeue(&cs->bcs->squeue)) != NULL)
dev_kfree_skb_any(skb);
}
/* Gigaset Driver Interface */
/* ======================== */
/*
* queue an AT command string for transmission to the Gigaset device
* parameters:
* cs controller state structure
* buf buffer containing the string to send
* len number of characters to send
* wake_tasklet tasklet to run when transmission is complete, or NULL
* return value:
* number of bytes queued, or error code < 0
*/
static int gigaset_write_cmd(struct cardstate *cs, struct cmdbuf_t *cb)
{
unsigned long flags;
gigaset_dbg_buffer(cs->mstate != MS_LOCKED ?
DEBUG_TRANSCMD : DEBUG_LOCKCMD,
"CMD Transmit", cb->len, cb->buf);
spin_lock_irqsave(&cs->cmdlock, flags);
cb->prev = cs->lastcmdbuf;
if (cs->lastcmdbuf)
cs->lastcmdbuf->next = cb;
else {
cs->cmdbuf = cb;
cs->curlen = cb->len;
}
cs->cmdbytes += cb->len;
cs->lastcmdbuf = cb;
spin_unlock_irqrestore(&cs->cmdlock, flags);
spin_lock_irqsave(&cs->lock, flags);
if (cs->connected)
tasklet_schedule(&cs->write_tasklet);
spin_unlock_irqrestore(&cs->lock, flags);
return cb->len;
}
/*
* tty_driver.write_room interface routine
* return number of characters the driver will accept to be written
* parameter:
* controller state structure
* return value:
* number of characters
*/
static int gigaset_write_room(struct cardstate *cs)
{
unsigned bytes;
bytes = cs->cmdbytes;
return bytes < IF_WRITEBUF ? IF_WRITEBUF - bytes : 0;
}
/*
* tty_driver.chars_in_buffer interface routine
* return number of characters waiting to be sent
* parameter:
* controller state structure
* return value:
* number of characters
*/
static int gigaset_chars_in_buffer(struct cardstate *cs)
{
return cs->cmdbytes;
}
/*
* implementation of ioctl(GIGASET_BRKCHARS)
* parameter:
* controller state structure
* return value:
* -EINVAL (unimplemented function)
*/
static int gigaset_brkchars(struct cardstate *cs, const unsigned char buf[6])
{
/* not implemented */
return -EINVAL;
}
/*
* Open B channel
* Called by "do_action" in ev-layer.c
*/
static int gigaset_init_bchannel(struct bc_state *bcs)
{
/* nothing to do for M10x */
gigaset_bchannel_up(bcs);
return 0;
}
/*
* Close B channel
* Called by "do_action" in ev-layer.c
*/
static int gigaset_close_bchannel(struct bc_state *bcs)
{
/* nothing to do for M10x */
gigaset_bchannel_down(bcs);
return 0;
}
/*
* Set up B channel structure
* This is called by "gigaset_initcs" in common.c
*/
static int gigaset_initbcshw(struct bc_state *bcs)
{
/* unused */
bcs->hw.ser = NULL;
return 0;
}
/*
* Free B channel structure
* Called by "gigaset_freebcs" in common.c
*/
static void gigaset_freebcshw(struct bc_state *bcs)
{
/* unused */
}
/*
* Reinitialize B channel structure
* This is called by "bcs_reinit" in common.c
*/
static void gigaset_reinitbcshw(struct bc_state *bcs)
{
/* nothing to do for M10x */
}
/*
* Free hardware specific device data
* This will be called by "gigaset_freecs" in common.c
*/
static void gigaset_freecshw(struct cardstate *cs)
{
tasklet_kill(&cs->write_tasklet);
if (!cs->hw.ser)
return;
dev_set_drvdata(&cs->hw.ser->dev.dev, NULL);
platform_device_unregister(&cs->hw.ser->dev);
kfree(cs->hw.ser);
cs->hw.ser = NULL;
}
static void gigaset_device_release(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
/* adapted from platform_device_release() in drivers/base/platform.c */
kfree(dev->platform_data);
kfree(pdev->resource);
}
/*
* Set up hardware specific device data
* This is called by "gigaset_initcs" in common.c
*/
static int gigaset_initcshw(struct cardstate *cs)
{
int rc;
struct ser_cardstate *scs;
scs = kzalloc(sizeof(struct ser_cardstate), GFP_KERNEL);
if (!scs) {
pr_err("out of memory\n");
return -ENOMEM;
}
cs->hw.ser = scs;
cs->hw.ser->dev.name = GIGASET_MODULENAME;
cs->hw.ser->dev.id = cs->minor_index;
cs->hw.ser->dev.dev.release = gigaset_device_release;
rc = platform_device_register(&cs->hw.ser->dev);
if (rc != 0) {
pr_err("error %d registering platform device\n", rc);
kfree(cs->hw.ser);
cs->hw.ser = NULL;
return rc;
}
dev_set_drvdata(&cs->hw.ser->dev.dev, cs);
tasklet_init(&cs->write_tasklet,
gigaset_modem_fill, (unsigned long) cs);
return 0;
}
/*
* set modem control lines
* Parameters:
* card state structure
* modem control line state ([TIOCM_DTR]|[TIOCM_RTS])
* Called by "gigaset_start" and "gigaset_enterconfigmode" in common.c
* and by "if_lock" and "if_termios" in interface.c
*/
static int gigaset_set_modem_ctrl(struct cardstate *cs, unsigned old_state,
unsigned new_state)
{
struct tty_struct *tty = cs->hw.ser->tty;
unsigned int set, clear;
if (!tty || !tty->driver || !tty->ops->tiocmset)
return -EINVAL;
set = new_state & ~old_state;
clear = old_state & ~new_state;
if (!set && !clear)
return 0;
gig_dbg(DEBUG_IF, "tiocmset set %x clear %x", set, clear);
return tty->ops->tiocmset(tty, set, clear);
}
static int gigaset_baud_rate(struct cardstate *cs, unsigned cflag)
{
return -EINVAL;
}
static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag)
{
return -EINVAL;
}
static const struct gigaset_ops ops = {
gigaset_write_cmd,
gigaset_write_room,
gigaset_chars_in_buffer,
gigaset_brkchars,
gigaset_init_bchannel,
gigaset_close_bchannel,
gigaset_initbcshw,
gigaset_freebcshw,
gigaset_reinitbcshw,
gigaset_initcshw,
gigaset_freecshw,
gigaset_set_modem_ctrl,
gigaset_baud_rate,
gigaset_set_line_ctrl,
gigaset_m10x_send_skb, /* asyncdata.c */
gigaset_m10x_input, /* asyncdata.c */
};
/* Line Discipline Interface */
/* ========================= */
/* helper functions for cardstate refcounting */
static struct cardstate *cs_get(struct tty_struct *tty)
{
struct cardstate *cs = tty->disc_data;
if (!cs || !cs->hw.ser) {
gig_dbg(DEBUG_ANY, "%s: no cardstate", __func__);
return NULL;
}
atomic_inc(&cs->hw.ser->refcnt);
return cs;
}
static void cs_put(struct cardstate *cs)
{
if (atomic_dec_and_test(&cs->hw.ser->refcnt))
complete(&cs->hw.ser->dead_cmp);
}
/*
* Called by the tty driver when the line discipline is pushed onto the tty.
* Called in process context.
*/
static int
gigaset_tty_open(struct tty_struct *tty)
{
struct cardstate *cs;
int rc;
gig_dbg(DEBUG_INIT, "Starting HLL for Gigaset M101");
pr_info(DRIVER_DESC "\n");
if (!driver) {
pr_err("%s: no driver structure\n", __func__);
return -ENODEV;
}
/* allocate memory for our device state and initialize it */
cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME);
if (!cs) {
rc = -ENODEV;
goto error;
}
cs->dev = &cs->hw.ser->dev.dev;
cs->hw.ser->tty = tty;
atomic_set(&cs->hw.ser->refcnt, 1);
init_completion(&cs->hw.ser->dead_cmp);
tty->disc_data = cs;
/* Set the amount of data we're willing to receive per call
* from the hardware driver to half of the input buffer size
* to leave some reserve.
* Note: We don't do flow control towards the hardware driver.
* If more data is received than will fit into the input buffer,
* it will be dropped and an error will be logged. This should
* never happen as the device is slow and the buffer size ample.
*/
tty->receive_room = RBUFSIZE/2;
/* OK.. Initialization of the datastructures and the HW is done.. Now
* startup system and notify the LL that we are ready to run
*/
if (startmode == SM_LOCKED)
cs->mstate = MS_LOCKED;
rc = gigaset_start(cs);
if (rc < 0) {
tasklet_kill(&cs->write_tasklet);
goto error;
}
gig_dbg(DEBUG_INIT, "Startup of HLL done");
return 0;
error:
gig_dbg(DEBUG_INIT, "Startup of HLL failed");
tty->disc_data = NULL;
gigaset_freecs(cs);
return rc;
}
/*
* Called by the tty driver when the line discipline is removed.
* Called from process context.
*/
static void
gigaset_tty_close(struct tty_struct *tty)
{
struct cardstate *cs = tty->disc_data;
gig_dbg(DEBUG_INIT, "Stopping HLL for Gigaset M101");
if (!cs) {
gig_dbg(DEBUG_INIT, "%s: no cardstate", __func__);
return;
}
/* prevent other callers from entering ldisc methods */
tty->disc_data = NULL;
if (!cs->hw.ser)
pr_err("%s: no hw cardstate\n", __func__);
else {
/* wait for running methods to finish */
if (!atomic_dec_and_test(&cs->hw.ser->refcnt))
wait_for_completion(&cs->hw.ser->dead_cmp);
}
/* stop operations */
gigaset_stop(cs);
tasklet_kill(&cs->write_tasklet);
flush_send_queue(cs);
cs->dev = NULL;
gigaset_freecs(cs);
gig_dbg(DEBUG_INIT, "Shutdown of HLL done");
}
/*
* Called by the tty driver when the tty line is hung up.
* Wait for I/O to driver to complete and unregister ISDN device.
* This is already done by the close routine, so just call that.
* Called from process context.
*/
static int gigaset_tty_hangup(struct tty_struct *tty)
{
gigaset_tty_close(tty);
return 0;
}
/*
* Read on the tty.
* Unused, received data goes only to the Gigaset driver.
*/
static ssize_t
gigaset_tty_read(struct tty_struct *tty, struct file *file,
unsigned char __user *buf, size_t count)
{
return -EAGAIN;
}
/*
* Write on the tty.
* Unused, transmit data comes only from the Gigaset driver.
*/
static ssize_t
gigaset_tty_write(struct tty_struct *tty, struct file *file,
const unsigned char *buf, size_t count)
{
return -EAGAIN;
}
/*
* Ioctl on the tty.
* Called in process context only.
* May be re-entered by multiple ioctl calling threads.
*/
static int
gigaset_tty_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg)
{
struct cardstate *cs = cs_get(tty);
int rc, val;
int __user *p = (int __user *)arg;
if (!cs)
return -ENXIO;
switch (cmd) {
case FIONREAD:
/* unused, always return zero */
val = 0;
rc = put_user(val, p);
break;
case TCFLSH:
/* flush our buffers and the serial port's buffer */
switch (arg) {
case TCIFLUSH:
/* no own input buffer to flush */
break;
case TCIOFLUSH:
case TCOFLUSH:
flush_send_queue(cs);
break;
}
/* Pass through */
default:
/* pass through to underlying serial device */
rc = n_tty_ioctl_helper(tty, file, cmd, arg);
break;
}
cs_put(cs);
return rc;
}
/*
* Called by the tty driver when a block of data has been received.
* Will not be re-entered while running but other ldisc functions
* may be called in parallel.
* Can be called from hard interrupt level as well as soft interrupt
* level or mainline.
* Parameters:
* tty tty structure
* buf buffer containing received characters
* cflags buffer containing error flags for received characters (ignored)
* count number of received characters
*/
static void
gigaset_tty_receive(struct tty_struct *tty, const unsigned char *buf,
char *cflags, int count)
{
struct cardstate *cs = cs_get(tty);
unsigned tail, head, n;
struct inbuf_t *inbuf;
if (!cs)
return;
inbuf = cs->inbuf;
if (!inbuf) {
dev_err(cs->dev, "%s: no inbuf\n", __func__);
cs_put(cs);
return;
}
tail = inbuf->tail;
head = inbuf->head;
gig_dbg(DEBUG_INTR, "buffer state: %u -> %u, receive %u bytes",
head, tail, count);
if (head <= tail) {
/* possible buffer wraparound */
n = min_t(unsigned, count, RBUFSIZE - tail);
memcpy(inbuf->data + tail, buf, n);
tail = (tail + n) % RBUFSIZE;
buf += n;
count -= n;
}
if (count > 0) {
/* tail < head and some data left */
n = head - tail - 1;
if (count > n) {
dev_err(cs->dev,
"inbuf overflow, discarding %d bytes\n",
count - n);
count = n;
}
memcpy(inbuf->data + tail, buf, count);
tail += count;
}
gig_dbg(DEBUG_INTR, "setting tail to %u", tail);
inbuf->tail = tail;
/* Everything was received .. Push data into handler */
gig_dbg(DEBUG_INTR, "%s-->BH", __func__);
gigaset_schedule_event(cs);
cs_put(cs);
}
/*
* Called by the tty driver when there's room for more data to send.
*/
static void
gigaset_tty_wakeup(struct tty_struct *tty)
{
struct cardstate *cs = cs_get(tty);
clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
if (!cs)
return;
tasklet_schedule(&cs->write_tasklet);
cs_put(cs);
}
static struct tty_ldisc_ops gigaset_ldisc = {
.owner = THIS_MODULE,
.magic = TTY_LDISC_MAGIC,
.name = "ser_gigaset",
.open = gigaset_tty_open,
.close = gigaset_tty_close,
.hangup = gigaset_tty_hangup,
.read = gigaset_tty_read,
.write = gigaset_tty_write,
.ioctl = gigaset_tty_ioctl,
.receive_buf = gigaset_tty_receive,
.write_wakeup = gigaset_tty_wakeup,
};
/* Initialization / Shutdown */
/* ========================= */
static int __init ser_gigaset_init(void)
{
int rc;
gig_dbg(DEBUG_INIT, "%s", __func__);
rc = platform_driver_register(&device_driver);
if (rc != 0) {
pr_err("error %d registering platform driver\n", rc);
return rc;
}
/* allocate memory for our driver state and initialize it */
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
GIGASET_MODULENAME, GIGASET_DEVNAME,
&ops, THIS_MODULE);
if (!driver)
goto error;
rc = tty_register_ldisc(N_GIGASET_M101, &gigaset_ldisc);
if (rc != 0) {
pr_err("error %d registering line discipline\n", rc);
goto error;
}
return 0;
error:
if (driver) {
gigaset_freedriver(driver);
driver = NULL;
}
platform_driver_unregister(&device_driver);
return rc;
}
static void __exit ser_gigaset_exit(void)
{
int rc;
gig_dbg(DEBUG_INIT, "%s", __func__);
if (driver) {
gigaset_freedriver(driver);
driver = NULL;
}
rc = tty_unregister_ldisc(N_GIGASET_M101);
if (rc != 0)
pr_err("error %d unregistering line discipline\n", rc);
platform_driver_unregister(&device_driver);
}
module_init(ser_gigaset_init);
module_exit(ser_gigaset_exit);
| gpl-2.0 |
Jewbie/Kernel-2.6.32 | drivers/video/geode/lxfb_core.c | 746 | 17741 | /*
* Geode LX framebuffer driver.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Built from gxfb (which is Copyright (C) 2006 Arcom Control Systems Ltd.)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/console.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/suspend.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/uaccess.h>
#include "lxfb.h"
static char *mode_option;
static int noclear, nopanel, nocrt;
static int vram;
static int vt_switch;
/* Most of these modes are sorted in ascending order, but
* since the first entry in this table is the "default" mode,
* we try to make it something sane - 640x480-60 is sane
*/
static struct fb_videomode geode_modedb[] __initdata = {
/* 640x480-60 */
{ NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x400-70 */
{ NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2,
FB_SYNC_HOR_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-70 */
{ NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 640x480-72 */
{ NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-75 */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-85 */
{ NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-90 */
{ NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 640x480-100 */
{ NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 640x480-60 */
{ NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 800x600-56 */
{ NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-60 */
{ NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-70 */
{ NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-72 */
{ NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-75 */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-85 */
{ NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-90 */
{ NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-100 */
{ NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-60 */
{ NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-60 */
{ NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-70 */
{ NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-72 */
{ NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-75 */
{ NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-85 */
{ NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-90 */
{ NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-100 */
{ NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-60 */
{ NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-60 */
{ NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-70 */
{ NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-72 */
{ NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-75 */
{ NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-85 */
{ NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-90 */
{ NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-100 */
{ NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-60 */
{ NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-60 */
{ NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-70 */
{ NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-72 */
{ NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-75 */
{ NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-85 */
{ NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-90 */
{ NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-100 */
{ NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-60 */
{ NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-60 */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-70 */
{ NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-72 */
{ NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-75 */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-85 */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-90 */
{ NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-100 */
{ NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-60 */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-60 */
{ NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-70 */
{ NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-72 */
{ NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-75 */
{ NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-85 */
{ NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3,
0, FB_VMODE_NONINTERLACED, 0 },
};
#ifdef CONFIG_OLPC
#include <asm/olpc.h>
static struct fb_videomode olpc_dcon_modedb[] __initdata = {
/* The only mode the DCON has is 1200x900 */
{ NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 }
};
static void __init get_modedb(struct fb_videomode **modedb, unsigned int *size)
{
if (olpc_has_dcon()) {
*modedb = (struct fb_videomode *) olpc_dcon_modedb;
*size = ARRAY_SIZE(olpc_dcon_modedb);
} else {
*modedb = (struct fb_videomode *) geode_modedb;
*size = ARRAY_SIZE(geode_modedb);
}
}
#else
static void __init get_modedb(struct fb_videomode **modedb, unsigned int *size)
{
*modedb = (struct fb_videomode *) geode_modedb;
*size = ARRAY_SIZE(geode_modedb);
}
#endif
static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (var->xres > 1920 || var->yres > 1440)
return -EINVAL;
if (var->bits_per_pixel == 32) {
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else
return -EINVAL;
var->transp.offset = 0; var->transp.length = 0;
/* Enough video memory? */
if ((lx_get_pitch(var->xres, var->bits_per_pixel) * var->yres)
> info->fix.smem_len)
return -EINVAL;
return 0;
}
static int lxfb_set_par(struct fb_info *info)
{
if (info->var.bits_per_pixel > 8)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = lx_get_pitch(info->var.xres,
info->var.bits_per_pixel);
lx_set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int lxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
lx_set_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int lxfb_blank(int blank_mode, struct fb_info *info)
{
return lx_blank_display(info, blank_mode);
}
static int __init lxfb_map_video_memory(struct fb_info *info,
struct pci_dev *dev)
{
struct lxfb_par *par = info->par;
int ret;
ret = pci_enable_device(dev);
if (ret)
return ret;
ret = pci_request_region(dev, 0, "lxfb-framebuffer");
if (ret)
return ret;
ret = pci_request_region(dev, 1, "lxfb-gp");
if (ret)
return ret;
ret = pci_request_region(dev, 2, "lxfb-vg");
if (ret)
return ret;
ret = pci_request_region(dev, 3, "lxfb-vp");
if (ret)
return ret;
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = vram ? vram : lx_framebuffer_size();
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
ret = -ENOMEM;
if (info->screen_base == NULL)
return ret;
par->gp_regs = pci_ioremap_bar(dev, 1);
if (par->gp_regs == NULL)
return ret;
par->dc_regs = pci_ioremap_bar(dev, 2);
if (par->dc_regs == NULL)
return ret;
par->vp_regs = pci_ioremap_bar(dev, 3);
if (par->vp_regs == NULL)
return ret;
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static struct fb_ops lxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = lxfb_check_var,
.fb_set_par = lxfb_set_par,
.fb_setcolreg = lxfb_setcolreg,
.fb_blank = lxfb_blank,
/* No HW acceleration for now. */
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static struct fb_info * __init lxfb_init_fbinfo(struct device *dev)
{
struct lxfb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct lxfb_par) + sizeof(u32) * 16,
dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "Geode LX");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &lxfb_ops;
info->flags = FBINFO_DEFAULT;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct lxfb_par);
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
framebuffer_release(info);
return NULL;
}
info->var.grayscale = 0;
return info;
}
#ifdef CONFIG_PM
static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct fb_info *info = pci_get_drvdata(pdev);
if (state.event == PM_EVENT_SUSPEND) {
acquire_console_sem();
lx_powerdown(info);
fb_set_suspend(info, 1);
release_console_sem();
}
/* there's no point in setting PCI states; we emulate PCI, so
* we don't end up getting power savings anyways */
return 0;
}
static int lxfb_resume(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
int ret;
acquire_console_sem();
ret = lx_powerup(info);
if (ret) {
printk(KERN_ERR "lxfb: power up failed!\n");
return ret;
}
fb_set_suspend(info, 0);
release_console_sem();
return 0;
}
#else
#define lxfb_suspend NULL
#define lxfb_resume NULL
#endif
static int __init lxfb_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct lxfb_par *par;
struct fb_info *info;
int ret;
struct fb_videomode *modedb_ptr;
unsigned int modedb_size;
info = lxfb_init_fbinfo(&pdev->dev);
if (info == NULL)
return -ENOMEM;
par = info->par;
ret = lxfb_map_video_memory(info, pdev);
if (ret < 0) {
dev_err(&pdev->dev,
"failed to map frame buffer or controller registers\n");
goto err;
}
/* Set up the desired outputs */
par->output = 0;
par->output |= (nopanel) ? 0 : OUTPUT_PANEL;
par->output |= (nocrt) ? 0 : OUTPUT_CRT;
/* Set up the mode database */
get_modedb(&modedb_ptr, &modedb_size);
ret = fb_find_mode(&info->var, info, mode_option,
modedb_ptr, modedb_size, NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the screen of garbage, unless noclear was specified,
* in which case we assume the user knows what he is doing */
if (!noclear)
memset_io(info->screen_base, 0, info->fix.smem_len);
/* Set the mode */
lxfb_check_var(&info->var, info);
lxfb_set_par(info);
pm_set_vt_switch(vt_switch);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
printk(KERN_INFO "fb%d: %s frame buffer device\n",
info->node, info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->gp_regs) {
iounmap(par->gp_regs);
pci_release_region(pdev, 1);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
}
if (par->vp_regs) {
iounmap(par->vp_regs);
pci_release_region(pdev, 3);
}
if (info) {
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
return ret;
}
static void lxfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct lxfb_par *par = info->par;
unregister_framebuffer(info);
iounmap(info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->gp_regs);
pci_release_region(pdev, 1);
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
iounmap(par->vp_regs);
pci_release_region(pdev, 3);
fb_dealloc_cmap(&info->cmap);
pci_set_drvdata(pdev, NULL);
framebuffer_release(info);
}
static struct pci_device_id lxfb_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_VIDEO) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, lxfb_id_table);
static struct pci_driver lxfb_driver = {
.name = "lxfb",
.id_table = lxfb_id_table,
.probe = lxfb_probe,
.remove = lxfb_remove,
.suspend = lxfb_suspend,
.resume = lxfb_resume,
};
#ifndef MODULE
static int __init lxfb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
if (!strcmp(opt, "noclear"))
noclear = 1;
else if (!strcmp(opt, "nopanel"))
nopanel = 1;
else if (!strcmp(opt, "nocrt"))
nocrt = 1;
else
mode_option = opt;
}
return 0;
}
#endif
static int __init lxfb_init(void)
{
#ifndef MODULE
char *option = NULL;
if (fb_get_options("lxfb", &option))
return -ENODEV;
lxfb_setup(option);
#endif
return pci_register_driver(&lxfb_driver);
}
static void __exit lxfb_cleanup(void)
{
pci_unregister_driver(&lxfb_driver);
}
module_init(lxfb_init);
module_exit(lxfb_cleanup);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "video memory size");
module_param(vt_switch, int, 0);
MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode LX");
MODULE_LICENSE("GPL");
| gpl-2.0 |
weboo/kernel-is01 | drivers/mtd/maps/alchemy-flash.c | 746 | 4191 | /*
* Flash memory access on AMD Alchemy evaluation boards
*
* (C) 2003, 2004 Pete Popov <ppopov@embeddedalley.com>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#ifdef CONFIG_MIPS_PB1000
#define BOARD_MAP_NAME "Pb1000 Flash"
#define BOARD_FLASH_SIZE 0x00800000 /* 8MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_PB1500
#define BOARD_MAP_NAME "Pb1500 Flash"
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_PB1100
#define BOARD_MAP_NAME "Pb1100 Flash"
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_PB1550
#define BOARD_MAP_NAME "Pb1550 Flash"
#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_PB1200
#define BOARD_MAP_NAME "Pb1200 Flash"
#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
#define BOARD_FLASH_WIDTH 2 /* 16-bits */
#endif
#ifdef CONFIG_MIPS_DB1000
#define BOARD_MAP_NAME "Db1000 Flash"
#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_DB1500
#define BOARD_MAP_NAME "Db1500 Flash"
#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_DB1100
#define BOARD_MAP_NAME "Db1100 Flash"
#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_DB1550
#define BOARD_MAP_NAME "Db1550 Flash"
#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#endif
#ifdef CONFIG_MIPS_DB1200
#define BOARD_MAP_NAME "Db1200 Flash"
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
#define BOARD_FLASH_WIDTH 2 /* 16-bits */
#endif
#ifdef CONFIG_MIPS_BOSPORUS
#define BOARD_MAP_NAME "Bosporus Flash"
#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
#define BOARD_FLASH_WIDTH 2 /* 16-bits */
#endif
#ifdef CONFIG_MIPS_MIRAGE
#define BOARD_MAP_NAME "Mirage Flash"
#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
#define BOARD_FLASH_WIDTH 4 /* 32-bits */
#define USE_LOCAL_ACCESSORS /* why? */
#endif
static struct map_info alchemy_map = {
.name = BOARD_MAP_NAME,
};
static struct mtd_partition alchemy_partitions[] = {
{
.name = "User FS",
.size = BOARD_FLASH_SIZE - 0x00400000,
.offset = 0x0000000
},{
.name = "YAMON",
.size = 0x0100000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE
},{
.name = "raw kernel",
.size = (0x300000 - 0x40000), /* last 256KB is yamon env */
.offset = MTDPART_OFS_APPEND,
}
};
static struct mtd_info *mymtd;
static int __init alchemy_mtd_init(void)
{
struct mtd_partition *parts;
int nb_parts = 0;
unsigned long window_addr;
unsigned long window_size;
/* Default flash buswidth */
alchemy_map.bankwidth = BOARD_FLASH_WIDTH;
window_addr = 0x20000000 - BOARD_FLASH_SIZE;
window_size = BOARD_FLASH_SIZE;
/*
* Static partition definition selection
*/
parts = alchemy_partitions;
nb_parts = ARRAY_SIZE(alchemy_partitions);
alchemy_map.size = window_size;
/*
* Now let's probe for the actual flash. Do it here since
* specific machine settings might have been set above.
*/
printk(KERN_NOTICE BOARD_MAP_NAME ": probing %d-bit flash bus\n",
alchemy_map.bankwidth*8);
alchemy_map.virt = ioremap(window_addr, window_size);
mymtd = do_map_probe("cfi_probe", &alchemy_map);
if (!mymtd) {
iounmap(alchemy_map.virt);
return -ENXIO;
}
mymtd->owner = THIS_MODULE;
add_mtd_partitions(mymtd, parts, nb_parts);
return 0;
}
static void __exit alchemy_mtd_cleanup(void)
{
if (mymtd) {
del_mtd_partitions(mymtd);
map_destroy(mymtd);
iounmap(alchemy_map.virt);
}
}
module_init(alchemy_mtd_init);
module_exit(alchemy_mtd_cleanup);
MODULE_AUTHOR("Embedded Alley Solutions, Inc");
MODULE_DESCRIPTION(BOARD_MAP_NAME " MTD driver");
MODULE_LICENSE("GPL");
| gpl-2.0 |
xiaowei942/Tiny210-kernel-2.6.35.7 | fs/ubifs/shrinker.c | 746 | 9508 | /*
* This file is part of UBIFS.
*
* Copyright (C) 2006-2008 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 51
* Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* Authors: Artem Bityutskiy (Битюцкий Артём)
* Adrian Hunter
*/
/*
* This file implements UBIFS shrinker which evicts clean znodes from the TNC
* tree when Linux VM needs more RAM.
*
* We do not implement any LRU lists to find oldest znodes to free because it
* would add additional overhead to the file system fast paths. So the shrinker
* just walks the TNC tree when searching for znodes to free.
*
* If the root of a TNC sub-tree is clean and old enough, then the children are
* also clean and old enough. So the shrinker walks the TNC in level order and
* dumps entire sub-trees.
*
* The age of znodes is just the time-stamp when they were last looked at.
* The current shrinker first tries to evict old znodes, then young ones.
*
* Since the shrinker is global, it has to protect against races with FS
* un-mounts, which is done by the 'ubifs_infos_lock' and 'c->umount_mutex'.
*/
#include "ubifs.h"
/* List of all UBIFS file-system instances */
LIST_HEAD(ubifs_infos);
/*
* We number each shrinker run and record the number on the ubifs_info structure
* so that we can easily work out which ubifs_info structures have already been
* done by the current run.
*/
static unsigned int shrinker_run_no;
/* Protects 'ubifs_infos' list */
DEFINE_SPINLOCK(ubifs_infos_lock);
/* Global clean znode counter (for all mounted UBIFS instances) */
atomic_long_t ubifs_clean_zn_cnt;
/**
* shrink_tnc - shrink TNC tree.
* @c: UBIFS file-system description object
* @nr: number of znodes to free
* @age: the age of znodes to free
* @contention: if any contention, this is set to %1
*
* This function traverses TNC tree and frees clean znodes. It does not free
* clean znodes which younger then @age. Returns number of freed znodes.
*/
static int shrink_tnc(struct ubifs_info *c, int nr, int age, int *contention)
{
int total_freed = 0;
struct ubifs_znode *znode, *zprev;
int time = get_seconds();
ubifs_assert(mutex_is_locked(&c->umount_mutex));
ubifs_assert(mutex_is_locked(&c->tnc_mutex));
if (!c->zroot.znode || atomic_long_read(&c->clean_zn_cnt) == 0)
return 0;
/*
* Traverse the TNC tree in levelorder manner, so that it is possible
* to destroy large sub-trees. Indeed, if a znode is old, then all its
* children are older or of the same age.
*
* Note, we are holding 'c->tnc_mutex', so we do not have to lock the
* 'c->space_lock' when _reading_ 'c->clean_zn_cnt', because it is
* changed only when the 'c->tnc_mutex' is held.
*/
zprev = NULL;
znode = ubifs_tnc_levelorder_next(c->zroot.znode, NULL);
while (znode && total_freed < nr &&
atomic_long_read(&c->clean_zn_cnt) > 0) {
int freed;
/*
* If the znode is clean, but it is in the 'c->cnext' list, this
* means that this znode has just been written to flash as a
* part of commit and was marked clean. They will be removed
* from the list at end commit. We cannot change the list,
* because it is not protected by any mutex (design decision to
* make commit really independent and parallel to main I/O). So
* we just skip these znodes.
*
* Note, the 'clean_zn_cnt' counters are not updated until
* after the commit, so the UBIFS shrinker does not report
* the znodes which are in the 'c->cnext' list as freeable.
*
* Also note, if the root of a sub-tree is not in 'c->cnext',
* then the whole sub-tree is not in 'c->cnext' as well, so it
* is safe to dump whole sub-tree.
*/
if (znode->cnext) {
/*
* Very soon these znodes will be removed from the list
* and become freeable.
*/
*contention = 1;
} else if (!ubifs_zn_dirty(znode) &&
abs(time - znode->time) >= age) {
if (znode->parent)
znode->parent->zbranch[znode->iip].znode = NULL;
else
c->zroot.znode = NULL;
freed = ubifs_destroy_tnc_subtree(znode);
atomic_long_sub(freed, &ubifs_clean_zn_cnt);
atomic_long_sub(freed, &c->clean_zn_cnt);
ubifs_assert(atomic_long_read(&c->clean_zn_cnt) >= 0);
total_freed += freed;
znode = zprev;
}
if (unlikely(!c->zroot.znode))
break;
zprev = znode;
znode = ubifs_tnc_levelorder_next(c->zroot.znode, znode);
cond_resched();
}
return total_freed;
}
/**
* shrink_tnc_trees - shrink UBIFS TNC trees.
* @nr: number of znodes to free
* @age: the age of znodes to free
* @contention: if any contention, this is set to %1
*
* This function walks the list of mounted UBIFS file-systems and frees clean
* znodes which are older than @age, until at least @nr znodes are freed.
* Returns the number of freed znodes.
*/
static int shrink_tnc_trees(int nr, int age, int *contention)
{
struct ubifs_info *c;
struct list_head *p;
unsigned int run_no;
int freed = 0;
spin_lock(&ubifs_infos_lock);
do {
run_no = ++shrinker_run_no;
} while (run_no == 0);
/* Iterate over all mounted UBIFS file-systems and try to shrink them */
p = ubifs_infos.next;
while (p != &ubifs_infos) {
c = list_entry(p, struct ubifs_info, infos_list);
/*
* We move the ones we do to the end of the list, so we stop
* when we see one we have already done.
*/
if (c->shrinker_run_no == run_no)
break;
if (!mutex_trylock(&c->umount_mutex)) {
/* Some un-mount is in progress, try next FS */
*contention = 1;
p = p->next;
continue;
}
/*
* We're holding 'c->umount_mutex', so the file-system won't go
* away.
*/
if (!mutex_trylock(&c->tnc_mutex)) {
mutex_unlock(&c->umount_mutex);
*contention = 1;
p = p->next;
continue;
}
spin_unlock(&ubifs_infos_lock);
/*
* OK, now we have TNC locked, the file-system cannot go away -
* it is safe to reap the cache.
*/
c->shrinker_run_no = run_no;
freed += shrink_tnc(c, nr, age, contention);
mutex_unlock(&c->tnc_mutex);
spin_lock(&ubifs_infos_lock);
/* Get the next list element before we move this one */
p = p->next;
/*
* Move this one to the end of the list to provide some
* fairness.
*/
list_move_tail(&c->infos_list, &ubifs_infos);
mutex_unlock(&c->umount_mutex);
if (freed >= nr)
break;
}
spin_unlock(&ubifs_infos_lock);
return freed;
}
/**
* kick_a_thread - kick a background thread to start commit.
*
* This function kicks a background thread to start background commit. Returns
* %-1 if a thread was kicked or there is another reason to assume the memory
* will soon be freed or become freeable. If there are no dirty znodes, returns
* %0.
*/
static int kick_a_thread(void)
{
int i;
struct ubifs_info *c;
/*
* Iterate over all mounted UBIFS file-systems and find out if there is
* already an ongoing commit operation there. If no, then iterate for
* the second time and initiate background commit.
*/
spin_lock(&ubifs_infos_lock);
for (i = 0; i < 2; i++) {
list_for_each_entry(c, &ubifs_infos, infos_list) {
long dirty_zn_cnt;
if (!mutex_trylock(&c->umount_mutex)) {
/*
* Some un-mount is in progress, it will
* certainly free memory, so just return.
*/
spin_unlock(&ubifs_infos_lock);
return -1;
}
dirty_zn_cnt = atomic_long_read(&c->dirty_zn_cnt);
if (!dirty_zn_cnt || c->cmt_state == COMMIT_BROKEN ||
c->ro_media) {
mutex_unlock(&c->umount_mutex);
continue;
}
if (c->cmt_state != COMMIT_RESTING) {
spin_unlock(&ubifs_infos_lock);
mutex_unlock(&c->umount_mutex);
return -1;
}
if (i == 1) {
list_move_tail(&c->infos_list, &ubifs_infos);
spin_unlock(&ubifs_infos_lock);
ubifs_request_bg_commit(c);
mutex_unlock(&c->umount_mutex);
return -1;
}
mutex_unlock(&c->umount_mutex);
}
}
spin_unlock(&ubifs_infos_lock);
return 0;
}
int ubifs_shrinker(struct shrinker *shrink, int nr, gfp_t gfp_mask)
{
int freed, contention = 0;
long clean_zn_cnt = atomic_long_read(&ubifs_clean_zn_cnt);
if (nr == 0)
return clean_zn_cnt;
if (!clean_zn_cnt) {
/*
* No clean znodes, nothing to reap. All we can do in this case
* is to kick background threads to start commit, which will
* probably make clean znodes which, in turn, will be freeable.
* And we return -1 which means will make VM call us again
* later.
*/
dbg_tnc("no clean znodes, kick a thread");
return kick_a_thread();
}
freed = shrink_tnc_trees(nr, OLD_ZNODE_AGE, &contention);
if (freed >= nr)
goto out;
dbg_tnc("not enough old znodes, try to free young ones");
freed += shrink_tnc_trees(nr - freed, YOUNG_ZNODE_AGE, &contention);
if (freed >= nr)
goto out;
dbg_tnc("not enough young znodes, free all");
freed += shrink_tnc_trees(nr - freed, 0, &contention);
if (!freed && contention) {
dbg_tnc("freed nothing, but contention");
return -1;
}
out:
dbg_tnc("%d znodes were freed, requested %d", freed, nr);
return freed;
}
| gpl-2.0 |
NaokiXie/android_kernel_samsung_wilcox | drivers/power/power_supply_core.c | 1258 | 9235 | /*
* Universal power supply monitor class
*
* Copyright © 2007 Anton Vorontsov <cbou@mail.ru>
* Copyright © 2004 Szabolcs Gyurko
* Copyright © 2003 Ian Molton <spyro@f2s.com>
*
* Modified: 2004, Oct Szabolcs Gyurko
*
* You may use this code as per GPL version 2
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/power_supply.h>
#include "power_supply.h"
/* exported for the APM Power driver, APM emulation */
struct class *power_supply_class;
EXPORT_SYMBOL_GPL(power_supply_class);
static struct device_type power_supply_dev_type;
/**
* power_supply_set_current_limit - set current limit
* @psy: the power supply to control
* @limit: current limit in uA from the power supply.
* 0 will disable the power supply.
*
* This function will set a maximum supply current from a source
* and it will disable the charger when limit is 0.
*/
int power_supply_set_current_limit(struct power_supply *psy, int limit)
{
const union power_supply_propval ret = {limit,};
if (psy->set_property)
return psy->set_property(psy, POWER_SUPPLY_PROP_CURRENT_MAX,
&ret);
return -ENXIO;
}
EXPORT_SYMBOL_GPL(power_supply_set_current_limit);
/**
* power_supply_set_online - set online state of the power supply
* @psy: the power supply to control
* @enable: sets online property of power supply
*/
int power_supply_set_online(struct power_supply *psy, bool enable)
{
const union power_supply_propval ret = {enable,};
if (psy->set_property)
return psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE,
&ret);
return -ENXIO;
}
EXPORT_SYMBOL_GPL(power_supply_set_online);
/**
* power_supply_set_scope - set scope of the power supply
* @psy: the power supply to control
* @scope: value to set the scope property to, should be from
* the SCOPE enum in power_supply.h
*/
int power_supply_set_scope(struct power_supply *psy, int scope)
{
const union power_supply_propval ret = {scope, };
if (psy->set_property)
return psy->set_property(psy, POWER_SUPPLY_PROP_SCOPE,
&ret);
return -ENXIO;
}
EXPORT_SYMBOL_GPL(power_supply_set_scope);
/**
* power_supply_set_supply_type - set type of the power supply
* @psy: the power supply to control
* @supply_type: sets type property of power supply
*/
int power_supply_set_supply_type(struct power_supply *psy,
enum power_supply_type supply_type)
{
const union power_supply_propval ret = {supply_type,};
if (psy->set_property)
return psy->set_property(psy, POWER_SUPPLY_PROP_TYPE,
&ret);
return -ENXIO;
}
EXPORT_SYMBOL_GPL(power_supply_set_supply_type);
/**
* power_supply_set_charge_type - set charge type of the power supply
* @psy: the power supply to control
* @enable: sets charge type property of power supply
*/
int power_supply_set_charge_type(struct power_supply *psy, int charge_type)
{
const union power_supply_propval ret = {charge_type,};
if (psy->set_property)
return psy->set_property(psy, POWER_SUPPLY_PROP_CHARGE_TYPE,
&ret);
return -ENXIO;
}
EXPORT_SYMBOL_GPL(power_supply_set_charge_type);
static int __power_supply_changed_work(struct device *dev, void *data)
{
struct power_supply *psy = (struct power_supply *)data;
struct power_supply *pst = dev_get_drvdata(dev);
int i;
for (i = 0; i < psy->num_supplicants; i++)
if (!strcmp(psy->supplied_to[i], pst->name)) {
if (pst->external_power_changed)
pst->external_power_changed(pst);
}
return 0;
}
static void power_supply_changed_work(struct work_struct *work)
{
unsigned long flags;
struct power_supply *psy = container_of(work, struct power_supply,
changed_work);
dev_dbg(psy->dev, "%s\n", __func__);
spin_lock_irqsave(&psy->changed_lock, flags);
if (psy->changed) {
psy->changed = false;
spin_unlock_irqrestore(&psy->changed_lock, flags);
class_for_each_device(power_supply_class, NULL, psy,
__power_supply_changed_work);
power_supply_update_leds(psy);
kobject_uevent(&psy->dev->kobj, KOBJ_CHANGE);
spin_lock_irqsave(&psy->changed_lock, flags);
}
if (!psy->changed)
wake_unlock(&psy->work_wake_lock);
spin_unlock_irqrestore(&psy->changed_lock, flags);
}
void power_supply_changed(struct power_supply *psy)
{
unsigned long flags;
dev_dbg(psy->dev, "%s\n", __func__);
spin_lock_irqsave(&psy->changed_lock, flags);
psy->changed = true;
wake_lock(&psy->work_wake_lock);
spin_unlock_irqrestore(&psy->changed_lock, flags);
schedule_work(&psy->changed_work);
}
EXPORT_SYMBOL_GPL(power_supply_changed);
static int __power_supply_am_i_supplied(struct device *dev, void *data)
{
union power_supply_propval ret = {0,};
struct power_supply *psy = (struct power_supply *)data;
struct power_supply *epsy = dev_get_drvdata(dev);
int i;
for (i = 0; i < epsy->num_supplicants; i++) {
if (!strcmp(epsy->supplied_to[i], psy->name)) {
if (epsy->get_property(epsy,
POWER_SUPPLY_PROP_ONLINE, &ret))
continue;
if (ret.intval)
return ret.intval;
}
}
return 0;
}
int power_supply_am_i_supplied(struct power_supply *psy)
{
int error;
error = class_for_each_device(power_supply_class, NULL, psy,
__power_supply_am_i_supplied);
dev_dbg(psy->dev, "%s %d\n", __func__, error);
return error;
}
EXPORT_SYMBOL_GPL(power_supply_am_i_supplied);
static int __power_supply_is_system_supplied(struct device *dev, void *data)
{
union power_supply_propval ret = {0,};
struct power_supply *psy = dev_get_drvdata(dev);
unsigned int *count = data;
(*count)++;
if (psy->type != POWER_SUPPLY_TYPE_BATTERY) {
if (psy->get_property(psy, POWER_SUPPLY_PROP_ONLINE, &ret))
return 0;
if (ret.intval)
return ret.intval;
}
return 0;
}
int power_supply_is_system_supplied(void)
{
int error;
unsigned int count = 0;
error = class_for_each_device(power_supply_class, NULL, &count,
__power_supply_is_system_supplied);
/*
* If no power class device was found at all, most probably we are
* running on a desktop system, so assume we are on mains power.
*/
if (count == 0)
return 1;
return error;
}
EXPORT_SYMBOL_GPL(power_supply_is_system_supplied);
int power_supply_set_battery_charged(struct power_supply *psy)
{
if (psy->type == POWER_SUPPLY_TYPE_BATTERY && psy->set_charged) {
psy->set_charged(psy);
return 0;
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(power_supply_set_battery_charged);
static int power_supply_match_device_by_name(struct device *dev, void *data)
{
const char *name = data;
struct power_supply *psy = dev_get_drvdata(dev);
return strcmp(psy->name, name) == 0;
}
struct power_supply *power_supply_get_by_name(char *name)
{
struct device *dev = class_find_device(power_supply_class, NULL, name,
power_supply_match_device_by_name);
return dev ? dev_get_drvdata(dev) : NULL;
}
EXPORT_SYMBOL_GPL(power_supply_get_by_name);
int power_supply_powers(struct power_supply *psy, struct device *dev)
{
return sysfs_create_link(&psy->dev->kobj, &dev->kobj, "powers");
}
EXPORT_SYMBOL_GPL(power_supply_powers);
static void power_supply_dev_release(struct device *dev)
{
pr_debug("device: '%s': %s\n", dev_name(dev), __func__);
kfree(dev);
}
int power_supply_register(struct device *parent, struct power_supply *psy)
{
struct device *dev;
int rc;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
device_initialize(dev);
dev->class = power_supply_class;
dev->type = &power_supply_dev_type;
dev->parent = parent;
dev->release = power_supply_dev_release;
dev_set_drvdata(dev, psy);
psy->dev = dev;
INIT_WORK(&psy->changed_work, power_supply_changed_work);
rc = kobject_set_name(&dev->kobj, "%s", psy->name);
if (rc)
goto kobject_set_name_failed;
rc = device_add(dev);
if (rc)
goto device_add_failed;
spin_lock_init(&psy->changed_lock);
wake_lock_init(&psy->work_wake_lock, WAKE_LOCK_SUSPEND, "power-supply");
rc = power_supply_create_triggers(psy);
if (rc)
goto create_triggers_failed;
power_supply_changed(psy);
goto success;
create_triggers_failed:
wake_lock_destroy(&psy->work_wake_lock);
device_del(dev);
kobject_set_name_failed:
device_add_failed:
put_device(dev);
success:
return rc;
}
EXPORT_SYMBOL_GPL(power_supply_register);
void power_supply_unregister(struct power_supply *psy)
{
cancel_work_sync(&psy->changed_work);
sysfs_remove_link(&psy->dev->kobj, "powers");
power_supply_remove_triggers(psy);
wake_lock_destroy(&psy->work_wake_lock);
device_unregister(psy->dev);
}
EXPORT_SYMBOL_GPL(power_supply_unregister);
static int __init power_supply_class_init(void)
{
power_supply_class = class_create(THIS_MODULE, "power_supply");
if (IS_ERR(power_supply_class))
return PTR_ERR(power_supply_class);
power_supply_class->dev_uevent = power_supply_uevent;
power_supply_init_attrs(&power_supply_dev_type);
return 0;
}
static void __exit power_supply_class_exit(void)
{
class_destroy(power_supply_class);
}
subsys_initcall(power_supply_class_init);
module_exit(power_supply_class_exit);
MODULE_DESCRIPTION("Universal power supply monitor class");
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>, "
"Szabolcs Gyurko, "
"Anton Vorontsov <cbou@mail.ru>");
MODULE_LICENSE("GPL");
| gpl-2.0 |
TimmyTossPot/rk30-kernel | drivers/gpio/tps65910-gpio.c | 2282 | 2552 | /*
* tps65910-gpio.c -- TI TPS6591x
*
* Copyright 2010 Texas Instruments Inc.
*
* Author: Graeme Gregory <gg@slimlogic.co.uk>
* Author: Jorge Eduardo Candelaria jedu@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/mfd/tps65910.h>
static int tps65910_gpio_get(struct gpio_chip *gc, unsigned offset)
{
struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
uint8_t val;
tps65910->read(tps65910, TPS65910_GPIO0 + offset, 1, &val);
if (val & GPIO_STS_MASK)
return 1;
return 0;
}
static void tps65910_gpio_set(struct gpio_chip *gc, unsigned offset,
int value)
{
struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
if (value)
tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
GPIO_SET_MASK);
else
tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
GPIO_SET_MASK);
}
static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
/* Set the initial value */
tps65910_gpio_set(gc, 0, value);
return tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
GPIO_CFG_MASK);
}
static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
{
struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
return tps65910_clear_bits(tps65910, TPS65910_GPIO0 + offset,
GPIO_CFG_MASK);
}
void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
{
int ret;
if (!gpio_base)
return;
tps65910->gpio.owner = THIS_MODULE;
tps65910->gpio.label = tps65910->i2c_client->name;
tps65910->gpio.dev = tps65910->dev;
tps65910->gpio.base = gpio_base;
switch(tps65910_chip_id(tps65910)) {
case TPS65910:
tps65910->gpio.ngpio = 6;
break;
case TPS65911:
tps65910->gpio.ngpio = 9;
break;
default:
return;
}
tps65910->gpio.can_sleep = 1;
tps65910->gpio.direction_input = tps65910_gpio_input;
tps65910->gpio.direction_output = tps65910_gpio_output;
tps65910->gpio.set = tps65910_gpio_set;
tps65910->gpio.get = tps65910_gpio_get;
ret = gpiochip_add(&tps65910->gpio);
if (ret)
dev_warn(tps65910->dev, "GPIO registration failed: %d\n", ret);
}
| gpl-2.0 |
laufersteppenwolf/lge-kernel-p880 | arch/arm/mach-omap2/dpll44xx.c | 2538 | 1800 | /*
* OMAP4-specific DPLL control functions
*
* Copyright (C) 2011 Texas Instruments, Inc.
* Rajendra Nayak
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include "clock.h"
#include "cm-regbits-44xx.h"
/* Supported only on OMAP4 */
int omap4_dpllmx_gatectrl_read(struct clk *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
return -EINVAL;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = __raw_readl(clk->clksel_reg);
v &= mask;
v >>= __ffs(mask);
return v;
}
void omap4_dpllmx_allow_gatectrl(struct clk *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
return;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = __raw_readl(clk->clksel_reg);
/* Clear the bit to allow gatectrl */
v &= ~mask;
__raw_writel(v, clk->clksel_reg);
}
void omap4_dpllmx_deny_gatectrl(struct clk *clk)
{
u32 v;
u32 mask;
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
return;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = __raw_readl(clk->clksel_reg);
/* Set the bit to deny gatectrl */
v |= mask;
__raw_writel(v, clk->clksel_reg);
}
const struct clkops clkops_omap4_dpllmx_ops = {
.allow_idle = omap4_dpllmx_allow_gatectrl,
.deny_idle = omap4_dpllmx_deny_gatectrl,
};
| gpl-2.0 |
CoolDevelopment/VSMC-i9105p | drivers/scsi/megaraid/megaraid_sas_fp.c | 2538 | 14531 | /*
* Linux MegaRAID driver for SAS based RAID controllers
*
* Copyright (c) 2009-2011 LSI Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* FILE: megaraid_sas_fp.c
*
* Authors: LSI Corporation
* Sumant Patro
* Varad Talamacki
* Manoj Jose
*
* Send feedback to: <megaraidlinux@lsi.com>
*
* Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
* ATTN: Linuxraid
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/moduleparam.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/uio.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#include <linux/compat.h>
#include <linux/blkdev.h>
#include <linux/poll.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include "megaraid_sas_fusion.h"
#include <asm/div64.h>
#define ABS_DIFF(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
#define MR_LD_STATE_OPTIMAL 3
#define FALSE 0
#define TRUE 1
/* Prototypes */
void
mr_update_load_balance_params(struct MR_FW_RAID_MAP_ALL *map,
struct LD_LOAD_BALANCE_INFO *lbInfo);
u32 mega_mod64(u64 dividend, u32 divisor)
{
u64 d;
u32 remainder;
if (!divisor)
printk(KERN_ERR "megasas : DIVISOR is zero, in div fn\n");
d = dividend;
remainder = do_div(d, divisor);
return remainder;
}
/**
* @param dividend : Dividend
* @param divisor : Divisor
*
* @return quotient
**/
u64 mega_div64_32(uint64_t dividend, uint32_t divisor)
{
u32 remainder;
u64 d;
if (!divisor)
printk(KERN_ERR "megasas : DIVISOR is zero in mod fn\n");
d = dividend;
remainder = do_div(d, divisor);
return d;
}
struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_FW_RAID_MAP_ALL *map)
{
return &map->raidMap.ldSpanMap[ld].ldRaid;
}
static struct MR_SPAN_BLOCK_INFO *MR_LdSpanInfoGet(u32 ld,
struct MR_FW_RAID_MAP_ALL
*map)
{
return &map->raidMap.ldSpanMap[ld].spanBlock[0];
}
static u8 MR_LdDataArmGet(u32 ld, u32 armIdx, struct MR_FW_RAID_MAP_ALL *map)
{
return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx];
}
static u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_FW_RAID_MAP_ALL *map)
{
return map->raidMap.arMapInfo[ar].pd[arm];
}
static u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_FW_RAID_MAP_ALL *map)
{
return map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef;
}
static u16 MR_PdDevHandleGet(u32 pd, struct MR_FW_RAID_MAP_ALL *map)
{
return map->raidMap.devHndlInfo[pd].curDevHdl;
}
u16 MR_GetLDTgtId(u32 ld, struct MR_FW_RAID_MAP_ALL *map)
{
return map->raidMap.ldSpanMap[ld].ldRaid.targetId;
}
u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_FW_RAID_MAP_ALL *map)
{
return map->raidMap.ldTgtIdToLd[ldTgtId];
}
static struct MR_LD_SPAN *MR_LdSpanPtrGet(u32 ld, u32 span,
struct MR_FW_RAID_MAP_ALL *map)
{
return &map->raidMap.ldSpanMap[ld].spanBlock[span].span;
}
/*
* This function will validate Map info data provided by FW
*/
u8 MR_ValidateMapInfo(struct MR_FW_RAID_MAP_ALL *map,
struct LD_LOAD_BALANCE_INFO *lbInfo)
{
struct MR_FW_RAID_MAP *pFwRaidMap = &map->raidMap;
if (pFwRaidMap->totalSize !=
(sizeof(struct MR_FW_RAID_MAP) -sizeof(struct MR_LD_SPAN_MAP) +
(sizeof(struct MR_LD_SPAN_MAP) *pFwRaidMap->ldCount))) {
printk(KERN_ERR "megasas: map info structure size 0x%x is not matching with ld count\n",
(unsigned int)((sizeof(struct MR_FW_RAID_MAP) -
sizeof(struct MR_LD_SPAN_MAP)) +
(sizeof(struct MR_LD_SPAN_MAP) *
pFwRaidMap->ldCount)));
printk(KERN_ERR "megasas: span map %x, pFwRaidMap->totalSize "
": %x\n", (unsigned int)sizeof(struct MR_LD_SPAN_MAP),
pFwRaidMap->totalSize);
return 0;
}
mr_update_load_balance_params(map, lbInfo);
return 1;
}
u32 MR_GetSpanBlock(u32 ld, u64 row, u64 *span_blk,
struct MR_FW_RAID_MAP_ALL *map, int *div_error)
{
struct MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map);
struct MR_QUAD_ELEMENT *quad;
struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
u32 span, j;
for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) {
for (j = 0; j < pSpanBlock->block_span_info.noElements; j++) {
quad = &pSpanBlock->block_span_info.quad[j];
if (quad->diff == 0) {
*div_error = 1;
return span;
}
if (quad->logStart <= row && row <= quad->logEnd &&
(mega_mod64(row-quad->logStart, quad->diff)) == 0) {
if (span_blk != NULL) {
u64 blk, debugBlk;
blk =
mega_div64_32(
(row-quad->logStart),
quad->diff);
debugBlk = blk;
blk = (blk + quad->offsetInSpan) <<
raid->stripeShift;
*span_blk = blk;
}
return span;
}
}
}
return span;
}
/*
******************************************************************************
*
* This routine calculates the arm, span and block for the specified stripe and
* reference in stripe.
*
* Inputs :
*
* ld - Logical drive number
* stripRow - Stripe number
* stripRef - Reference in stripe
*
* Outputs :
*
* span - Span number
* block - Absolute Block number in the physical disk
*/
u8 MR_GetPhyParams(u32 ld, u64 stripRow, u16 stripRef, u64 *pdBlock,
u16 *pDevHandle, struct RAID_CONTEXT *pRAID_Context,
struct MR_FW_RAID_MAP_ALL *map)
{
struct MR_LD_RAID *raid = MR_LdRaidGet(ld, map);
u32 pd, arRef;
u8 physArm, span;
u64 row;
u8 retval = TRUE;
int error_code = 0;
row = mega_div64_32(stripRow, raid->rowDataSize);
if (raid->level == 6) {
/* logical arm within row */
u32 logArm = mega_mod64(stripRow, raid->rowDataSize);
u32 rowMod, armQ, arm;
if (raid->rowSize == 0)
return FALSE;
/* get logical row mod */
rowMod = mega_mod64(row, raid->rowSize);
armQ = raid->rowSize-1-rowMod; /* index of Q drive */
arm = armQ+1+logArm; /* data always logically follows Q */
if (arm >= raid->rowSize) /* handle wrap condition */
arm -= raid->rowSize;
physArm = (u8)arm;
} else {
if (raid->modFactor == 0)
return FALSE;
physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow,
raid->modFactor),
map);
}
if (raid->spanDepth == 1) {
span = 0;
*pdBlock = row << raid->stripeShift;
} else {
span = (u8)MR_GetSpanBlock(ld, row, pdBlock, map, &error_code);
if (error_code == 1)
return FALSE;
}
/* Get the array on which this span is present */
arRef = MR_LdSpanArrayGet(ld, span, map);
pd = MR_ArPdGet(arRef, physArm, map); /* Get the pd */
if (pd != MR_PD_INVALID)
/* Get dev handle from Pd. */
*pDevHandle = MR_PdDevHandleGet(pd, map);
else {
*pDevHandle = MR_PD_INVALID; /* set dev handle as invalid. */
if (raid->level >= 5)
pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE;
else if (raid->level == 1) {
/* Get alternate Pd. */
pd = MR_ArPdGet(arRef, physArm + 1, map);
if (pd != MR_PD_INVALID)
/* Get dev handle from Pd */
*pDevHandle = MR_PdDevHandleGet(pd, map);
}
retval = FALSE;
}
*pdBlock += stripRef + MR_LdSpanPtrGet(ld, span, map)->startBlk;
pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) |
physArm;
return retval;
}
/*
******************************************************************************
*
* MR_BuildRaidContext function
*
* This function will initiate command processing. The start/end row and strip
* information is calculated then the lock is acquired.
* This function will return 0 if region lock was acquired OR return num strips
*/
u8
MR_BuildRaidContext(struct IO_REQUEST_INFO *io_info,
struct RAID_CONTEXT *pRAID_Context,
struct MR_FW_RAID_MAP_ALL *map)
{
struct MR_LD_RAID *raid;
u32 ld, stripSize, stripe_mask;
u64 endLba, endStrip, endRow, start_row, start_strip;
u64 regStart;
u32 regSize;
u8 num_strips, numRows;
u16 ref_in_start_stripe, ref_in_end_stripe;
u64 ldStartBlock;
u32 numBlocks, ldTgtId;
u8 isRead;
u8 retval = 0;
ldStartBlock = io_info->ldStartBlock;
numBlocks = io_info->numBlocks;
ldTgtId = io_info->ldTgtId;
isRead = io_info->isRead;
ld = MR_TargetIdToLdGet(ldTgtId, map);
raid = MR_LdRaidGet(ld, map);
stripSize = 1 << raid->stripeShift;
stripe_mask = stripSize-1;
/*
* calculate starting row and stripe, and number of strips and rows
*/
start_strip = ldStartBlock >> raid->stripeShift;
ref_in_start_stripe = (u16)(ldStartBlock & stripe_mask);
endLba = ldStartBlock + numBlocks - 1;
ref_in_end_stripe = (u16)(endLba & stripe_mask);
endStrip = endLba >> raid->stripeShift;
num_strips = (u8)(endStrip - start_strip + 1); /* End strip */
if (raid->rowDataSize == 0)
return FALSE;
start_row = mega_div64_32(start_strip, raid->rowDataSize);
endRow = mega_div64_32(endStrip, raid->rowDataSize);
numRows = (u8)(endRow - start_row + 1);
/*
* calculate region info.
*/
/* assume region is at the start of the first row */
regStart = start_row << raid->stripeShift;
/* assume this IO needs the full row - we'll adjust if not true */
regSize = stripSize;
/* If IO spans more than 1 strip, fp is not possible
FP is not possible for writes on non-0 raid levels
FP is not possible if LD is not capable */
if (num_strips > 1 || (!isRead && raid->level != 0) ||
!raid->capability.fpCapable) {
io_info->fpOkForIo = FALSE;
} else {
io_info->fpOkForIo = TRUE;
}
if (numRows == 1) {
/* single-strip IOs can always lock only the data needed */
if (num_strips == 1) {
regStart += ref_in_start_stripe;
regSize = numBlocks;
}
/* multi-strip IOs always need to full stripe locked */
} else {
if (start_strip == (start_row + 1) * raid->rowDataSize - 1) {
/* If the start strip is the last in the start row */
regStart += ref_in_start_stripe;
regSize = stripSize - ref_in_start_stripe;
/* initialize count to sectors from startref to end
of strip */
}
if (numRows > 2)
/* Add complete rows in the middle of the transfer */
regSize += (numRows-2) << raid->stripeShift;
/* if IO ends within first strip of last row */
if (endStrip == endRow*raid->rowDataSize)
regSize += ref_in_end_stripe+1;
else
regSize += stripSize;
}
pRAID_Context->timeoutValue = map->raidMap.fpPdIoTimeoutSec;
pRAID_Context->regLockFlags = (isRead) ? REGION_TYPE_SHARED_READ :
raid->regTypeReqOnWrite;
pRAID_Context->VirtualDiskTgtId = raid->targetId;
pRAID_Context->regLockRowLBA = regStart;
pRAID_Context->regLockLength = regSize;
pRAID_Context->configSeqNum = raid->seqNum;
/*Get Phy Params only if FP capable, or else leave it to MR firmware
to do the calculation.*/
if (io_info->fpOkForIo) {
retval = MR_GetPhyParams(ld, start_strip, ref_in_start_stripe,
&io_info->pdBlock,
&io_info->devHandle, pRAID_Context,
map);
/* If IO on an invalid Pd, then FP i snot possible */
if (io_info->devHandle == MR_PD_INVALID)
io_info->fpOkForIo = FALSE;
return retval;
} else if (isRead) {
uint stripIdx;
for (stripIdx = 0; stripIdx < num_strips; stripIdx++) {
if (!MR_GetPhyParams(ld, start_strip + stripIdx,
ref_in_start_stripe,
&io_info->pdBlock,
&io_info->devHandle,
pRAID_Context, map))
return TRUE;
}
}
return TRUE;
}
void
mr_update_load_balance_params(struct MR_FW_RAID_MAP_ALL *map,
struct LD_LOAD_BALANCE_INFO *lbInfo)
{
int ldCount;
u16 ld;
struct MR_LD_RAID *raid;
for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES; ldCount++) {
ld = MR_TargetIdToLdGet(ldCount, map);
if (ld >= MAX_LOGICAL_DRIVES) {
lbInfo[ldCount].loadBalanceFlag = 0;
continue;
}
raid = MR_LdRaidGet(ld, map);
/* Two drive Optimal RAID 1 */
if ((raid->level == 1) && (raid->rowSize == 2) &&
(raid->spanDepth == 1) && raid->ldState ==
MR_LD_STATE_OPTIMAL) {
u32 pd, arRef;
lbInfo[ldCount].loadBalanceFlag = 1;
/* Get the array on which this span is present */
arRef = MR_LdSpanArrayGet(ld, 0, map);
/* Get the Pd */
pd = MR_ArPdGet(arRef, 0, map);
/* Get dev handle from Pd */
lbInfo[ldCount].raid1DevHandle[0] =
MR_PdDevHandleGet(pd, map);
/* Get the Pd */
pd = MR_ArPdGet(arRef, 1, map);
/* Get the dev handle from Pd */
lbInfo[ldCount].raid1DevHandle[1] =
MR_PdDevHandleGet(pd, map);
} else
lbInfo[ldCount].loadBalanceFlag = 0;
}
}
u8 megasas_get_best_arm(struct LD_LOAD_BALANCE_INFO *lbInfo, u8 arm, u64 block,
u32 count)
{
u16 pend0, pend1;
u64 diff0, diff1;
u8 bestArm;
/* get the pending cmds for the data and mirror arms */
pend0 = atomic_read(&lbInfo->scsi_pending_cmds[0]);
pend1 = atomic_read(&lbInfo->scsi_pending_cmds[1]);
/* Determine the disk whose head is nearer to the req. block */
diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[0]);
diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[1]);
bestArm = (diff0 <= diff1 ? 0 : 1);
if ((bestArm == arm && pend0 > pend1 + 16) ||
(bestArm != arm && pend1 > pend0 + 16))
bestArm ^= 1;
/* Update the last accessed block on the correct pd */
lbInfo->last_accessed_block[bestArm] = block + count - 1;
return bestArm;
}
u16 get_updated_dev_handle(struct LD_LOAD_BALANCE_INFO *lbInfo,
struct IO_REQUEST_INFO *io_info)
{
u8 arm, old_arm;
u16 devHandle;
old_arm = lbInfo->raid1DevHandle[0] == io_info->devHandle ? 0 : 1;
/* get best new arm */
arm = megasas_get_best_arm(lbInfo, old_arm, io_info->ldStartBlock,
io_info->numBlocks);
devHandle = lbInfo->raid1DevHandle[arm];
atomic_inc(&lbInfo->scsi_pending_cmds[arm]);
return devHandle;
}
| gpl-2.0 |
Red680812/X920D | arch/x86/kernel/tsc.c | 4074 | 26706 | #include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/timer.h>
#include <linux/acpi_pmtmr.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/clocksource.h>
#include <linux/percpu.h>
#include <linux/timex.h>
#include <asm/hpet.h>
#include <asm/timer.h>
#include <asm/vgtod.h>
#include <asm/time.h>
#include <asm/delay.h>
#include <asm/hypervisor.h>
#include <asm/nmi.h>
#include <asm/x86_init.h>
unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
EXPORT_SYMBOL(cpu_khz);
unsigned int __read_mostly tsc_khz;
EXPORT_SYMBOL(tsc_khz);
/*
* TSC can be unstable due to cpufreq or due to unsynced TSCs
*/
static int __read_mostly tsc_unstable;
/* native_sched_clock() is called before tsc_init(), so
we must start with the TSC soft disabled to prevent
erroneous rdtsc usage on !cpu_has_tsc processors */
static int __read_mostly tsc_disabled = -1;
int tsc_clocksource_reliable;
/*
* Scheduler clock - returns current time in nanosec units.
*/
u64 native_sched_clock(void)
{
u64 this_offset;
/*
* Fall back to jiffies if there's no TSC available:
* ( But note that we still use it if the TSC is marked
* unstable. We do this because unlike Time Of Day,
* the scheduler clock tolerates small errors and it's
* very important for it to be as fast as the platform
* can achieve it. )
*/
if (unlikely(tsc_disabled)) {
/* No locking but a rare wrong value is not a big deal: */
return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
}
/* read the Time Stamp Counter: */
rdtscll(this_offset);
/* return the value in ns */
return __cycles_2_ns(this_offset);
}
/* We need to define a real function for sched_clock, to override the
weak default version */
#ifdef CONFIG_PARAVIRT
unsigned long long sched_clock(void)
{
return paravirt_sched_clock();
}
#else
unsigned long long
sched_clock(void) __attribute__((alias("native_sched_clock")));
#endif
int check_tsc_unstable(void)
{
return tsc_unstable;
}
EXPORT_SYMBOL_GPL(check_tsc_unstable);
#ifdef CONFIG_X86_TSC
int __init notsc_setup(char *str)
{
printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
"cannot disable TSC completely.\n");
tsc_disabled = 1;
return 1;
}
#else
/*
* disable flag for tsc. Takes effect by clearing the TSC cpu flag
* in cpu/common.c
*/
int __init notsc_setup(char *str)
{
setup_clear_cpu_cap(X86_FEATURE_TSC);
return 1;
}
#endif
__setup("notsc", notsc_setup);
static int no_sched_irq_time;
static int __init tsc_setup(char *str)
{
if (!strcmp(str, "reliable"))
tsc_clocksource_reliable = 1;
if (!strncmp(str, "noirqtime", 9))
no_sched_irq_time = 1;
return 1;
}
__setup("tsc=", tsc_setup);
#define MAX_RETRIES 5
#define SMI_TRESHOLD 50000
/*
* Read TSC and the reference counters. Take care of SMI disturbance
*/
static u64 tsc_read_refs(u64 *p, int hpet)
{
u64 t1, t2;
int i;
for (i = 0; i < MAX_RETRIES; i++) {
t1 = get_cycles();
if (hpet)
*p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
else
*p = acpi_pm_read_early();
t2 = get_cycles();
if ((t2 - t1) < SMI_TRESHOLD)
return t2;
}
return ULLONG_MAX;
}
/*
* Calculate the TSC frequency from HPET reference
*/
static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
{
u64 tmp;
if (hpet2 < hpet1)
hpet2 += 0x100000000ULL;
hpet2 -= hpet1;
tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
do_div(tmp, 1000000);
do_div(deltatsc, tmp);
return (unsigned long) deltatsc;
}
/*
* Calculate the TSC frequency from PMTimer reference
*/
static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
{
u64 tmp;
if (!pm1 && !pm2)
return ULONG_MAX;
if (pm2 < pm1)
pm2 += (u64)ACPI_PM_OVRRUN;
pm2 -= pm1;
tmp = pm2 * 1000000000LL;
do_div(tmp, PMTMR_TICKS_PER_SEC);
do_div(deltatsc, tmp);
return (unsigned long) deltatsc;
}
#define CAL_MS 10
#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
#define CAL_PIT_LOOPS 1000
#define CAL2_MS 50
#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
#define CAL2_PIT_LOOPS 5000
/*
* Try to calibrate the TSC against the Programmable
* Interrupt Timer and return the frequency of the TSC
* in kHz.
*
* Return ULONG_MAX on failure to calibrate.
*/
static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
{
u64 tsc, t1, t2, delta;
unsigned long tscmin, tscmax;
int pitcnt;
/* Set the Gate high, disable speaker */
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
/*
* Setup CTC channel 2* for mode 0, (interrupt on terminal
* count mode), binary count. Set the latch register to 50ms
* (LSB then MSB) to begin countdown.
*/
outb(0xb0, 0x43);
outb(latch & 0xff, 0x42);
outb(latch >> 8, 0x42);
tsc = t1 = t2 = get_cycles();
pitcnt = 0;
tscmax = 0;
tscmin = ULONG_MAX;
while ((inb(0x61) & 0x20) == 0) {
t2 = get_cycles();
delta = t2 - tsc;
tsc = t2;
if ((unsigned long) delta < tscmin)
tscmin = (unsigned int) delta;
if ((unsigned long) delta > tscmax)
tscmax = (unsigned int) delta;
pitcnt++;
}
/*
* Sanity checks:
*
* If we were not able to read the PIT more than loopmin
* times, then we have been hit by a massive SMI
*
* If the maximum is 10 times larger than the minimum,
* then we got hit by an SMI as well.
*/
if (pitcnt < loopmin || tscmax > 10 * tscmin)
return ULONG_MAX;
/* Calculate the PIT value */
delta = t2 - t1;
do_div(delta, ms);
return delta;
}
/*
* This reads the current MSB of the PIT counter, and
* checks if we are running on sufficiently fast and
* non-virtualized hardware.
*
* Our expectations are:
*
* - the PIT is running at roughly 1.19MHz
*
* - each IO is going to take about 1us on real hardware,
* but we allow it to be much faster (by a factor of 10) or
* _slightly_ slower (ie we allow up to a 2us read+counter
* update - anything else implies a unacceptably slow CPU
* or PIT for the fast calibration to work.
*
* - with 256 PIT ticks to read the value, we have 214us to
* see the same MSB (and overhead like doing a single TSC
* read per MSB value etc).
*
* - We're doing 2 reads per loop (LSB, MSB), and we expect
* them each to take about a microsecond on real hardware.
* So we expect a count value of around 100. But we'll be
* generous, and accept anything over 50.
*
* - if the PIT is stuck, and we see *many* more reads, we
* return early (and the next caller of pit_expect_msb()
* then consider it a failure when they don't see the
* next expected value).
*
* These expectations mean that we know that we have seen the
* transition from one expected value to another with a fairly
* high accuracy, and we didn't miss any events. We can thus
* use the TSC value at the transitions to calculate a pretty
* good value for the TSC frequencty.
*/
static inline int pit_verify_msb(unsigned char val)
{
/* Ignore LSB */
inb(0x42);
return inb(0x42) == val;
}
static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
{
int count;
u64 tsc = 0, prev_tsc = 0;
for (count = 0; count < 50000; count++) {
if (!pit_verify_msb(val))
break;
prev_tsc = tsc;
tsc = get_cycles();
}
*deltap = get_cycles() - prev_tsc;
*tscp = tsc;
/*
* We require _some_ success, but the quality control
* will be based on the error terms on the TSC values.
*/
return count > 5;
}
/*
* How many MSB values do we want to see? We aim for
* a maximum error rate of 500ppm (in practice the
* real error is much smaller), but refuse to spend
* more than 50ms on it.
*/
#define MAX_QUICK_PIT_MS 50
#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
static unsigned long quick_pit_calibrate(void)
{
int i;
u64 tsc, delta;
unsigned long d1, d2;
/* Set the Gate high, disable speaker */
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
/*
* Counter 2, mode 0 (one-shot), binary count
*
* NOTE! Mode 2 decrements by two (and then the
* output is flipped each time, giving the same
* final output frequency as a decrement-by-one),
* so mode 0 is much better when looking at the
* individual counts.
*/
outb(0xb0, 0x43);
/* Start at 0xffff */
outb(0xff, 0x42);
outb(0xff, 0x42);
/*
* The PIT starts counting at the next edge, so we
* need to delay for a microsecond. The easiest way
* to do that is to just read back the 16-bit counter
* once from the PIT.
*/
pit_verify_msb(0);
if (pit_expect_msb(0xff, &tsc, &d1)) {
for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
if (!pit_expect_msb(0xff-i, &delta, &d2))
break;
/*
* Iterate until the error is less than 500 ppm
*/
delta -= tsc;
if (d1+d2 >= delta >> 11)
continue;
/*
* Check the PIT one more time to verify that
* all TSC reads were stable wrt the PIT.
*
* This also guarantees serialization of the
* last cycle read ('d2') in pit_expect_msb.
*/
if (!pit_verify_msb(0xfe - i))
break;
goto success;
}
}
printk("Fast TSC calibration failed\n");
return 0;
success:
/*
* Ok, if we get here, then we've seen the
* MSB of the PIT decrement 'i' times, and the
* error has shrunk to less than 500 ppm.
*
* As a result, we can depend on there not being
* any odd delays anywhere, and the TSC reads are
* reliable (within the error).
*
* kHz = ticks / time-in-seconds / 1000;
* kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
* kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
*/
delta *= PIT_TICK_RATE;
do_div(delta, i*256*1000);
printk("Fast TSC calibration using PIT\n");
return delta;
}
/**
* native_calibrate_tsc - calibrate the tsc on boot
*/
unsigned long native_calibrate_tsc(void)
{
u64 tsc1, tsc2, delta, ref1, ref2;
unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
unsigned long flags, latch, ms, fast_calibrate;
int hpet = is_hpet_enabled(), i, loopmin;
local_irq_save(flags);
fast_calibrate = quick_pit_calibrate();
local_irq_restore(flags);
if (fast_calibrate)
return fast_calibrate;
/*
* Run 5 calibration loops to get the lowest frequency value
* (the best estimate). We use two different calibration modes
* here:
*
* 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
* load a timeout of 50ms. We read the time right after we
* started the timer and wait until the PIT count down reaches
* zero. In each wait loop iteration we read the TSC and check
* the delta to the previous read. We keep track of the min
* and max values of that delta. The delta is mostly defined
* by the IO time of the PIT access, so we can detect when a
* SMI/SMM disturbance happened between the two reads. If the
* maximum time is significantly larger than the minimum time,
* then we discard the result and have another try.
*
* 2) Reference counter. If available we use the HPET or the
* PMTIMER as a reference to check the sanity of that value.
* We use separate TSC readouts and check inside of the
* reference read for a SMI/SMM disturbance. We dicard
* disturbed values here as well. We do that around the PIT
* calibration delay loop as we have to wait for a certain
* amount of time anyway.
*/
/* Preset PIT loop values */
latch = CAL_LATCH;
ms = CAL_MS;
loopmin = CAL_PIT_LOOPS;
for (i = 0; i < 3; i++) {
unsigned long tsc_pit_khz;
/*
* Read the start value and the reference count of
* hpet/pmtimer when available. Then do the PIT
* calibration, which will take at least 50ms, and
* read the end value.
*/
local_irq_save(flags);
tsc1 = tsc_read_refs(&ref1, hpet);
tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
tsc2 = tsc_read_refs(&ref2, hpet);
local_irq_restore(flags);
/* Pick the lowest PIT TSC calibration so far */
tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
/* hpet or pmtimer available ? */
if (ref1 == ref2)
continue;
/* Check, whether the sampling was disturbed by an SMI */
if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
continue;
tsc2 = (tsc2 - tsc1) * 1000000LL;
if (hpet)
tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
else
tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
/* Check the reference deviation */
delta = ((u64) tsc_pit_min) * 100;
do_div(delta, tsc_ref_min);
/*
* If both calibration results are inside a 10% window
* then we can be sure, that the calibration
* succeeded. We break out of the loop right away. We
* use the reference value, as it is more precise.
*/
if (delta >= 90 && delta <= 110) {
printk(KERN_INFO
"TSC: PIT calibration matches %s. %d loops\n",
hpet ? "HPET" : "PMTIMER", i + 1);
return tsc_ref_min;
}
/*
* Check whether PIT failed more than once. This
* happens in virtualized environments. We need to
* give the virtual PC a slightly longer timeframe for
* the HPET/PMTIMER to make the result precise.
*/
if (i == 1 && tsc_pit_min == ULONG_MAX) {
latch = CAL2_LATCH;
ms = CAL2_MS;
loopmin = CAL2_PIT_LOOPS;
}
}
/*
* Now check the results.
*/
if (tsc_pit_min == ULONG_MAX) {
/* PIT gave no useful value */
printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
/* We don't have an alternative source, disable TSC */
if (!hpet && !ref1 && !ref2) {
printk("TSC: No reference (HPET/PMTIMER) available\n");
return 0;
}
/* The alternative source failed as well, disable TSC */
if (tsc_ref_min == ULONG_MAX) {
printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
"failed.\n");
return 0;
}
/* Use the alternative source */
printk(KERN_INFO "TSC: using %s reference calibration\n",
hpet ? "HPET" : "PMTIMER");
return tsc_ref_min;
}
/* We don't have an alternative source, use the PIT calibration value */
if (!hpet && !ref1 && !ref2) {
printk(KERN_INFO "TSC: Using PIT calibration value\n");
return tsc_pit_min;
}
/* The alternative source failed, use the PIT calibration value */
if (tsc_ref_min == ULONG_MAX) {
printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
"Using PIT calibration\n");
return tsc_pit_min;
}
/*
* The calibration values differ too much. In doubt, we use
* the PIT value as we know that there are PMTIMERs around
* running at double speed. At least we let the user know:
*/
printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
printk(KERN_INFO "TSC: Using PIT calibration value\n");
return tsc_pit_min;
}
int recalibrate_cpu_khz(void)
{
#ifndef CONFIG_SMP
unsigned long cpu_khz_old = cpu_khz;
if (cpu_has_tsc) {
tsc_khz = x86_platform.calibrate_tsc();
cpu_khz = tsc_khz;
cpu_data(0).loops_per_jiffy =
cpufreq_scale(cpu_data(0).loops_per_jiffy,
cpu_khz_old, cpu_khz);
return 0;
} else
return -ENODEV;
#else
return -ENODEV;
#endif
}
EXPORT_SYMBOL(recalibrate_cpu_khz);
/* Accelerators for sched_clock()
* convert from cycles(64bits) => nanoseconds (64bits)
* basic equation:
* ns = cycles / (freq / ns_per_sec)
* ns = cycles * (ns_per_sec / freq)
* ns = cycles * (10^9 / (cpu_khz * 10^3))
* ns = cycles * (10^6 / cpu_khz)
*
* Then we use scaling math (suggested by george@mvista.com) to get:
* ns = cycles * (10^6 * SC / cpu_khz) / SC
* ns = cycles * cyc2ns_scale / SC
*
* And since SC is a constant power of two, we can convert the div
* into a shift.
*
* We can use khz divisor instead of mhz to keep a better precision, since
* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
* (mathieu.desnoyers@polymtl.ca)
*
* -johnstul@us.ibm.com "math is hard, lets go shopping!"
*/
DEFINE_PER_CPU(unsigned long, cyc2ns);
DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
{
unsigned long long tsc_now, ns_now, *offset;
unsigned long flags, *scale;
local_irq_save(flags);
sched_clock_idle_sleep_event();
scale = &per_cpu(cyc2ns, cpu);
offset = &per_cpu(cyc2ns_offset, cpu);
rdtscll(tsc_now);
ns_now = __cycles_2_ns(tsc_now);
if (cpu_khz) {
*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
*offset = ns_now - mult_frac(tsc_now, *scale,
(1UL << CYC2NS_SCALE_FACTOR));
}
sched_clock_idle_wakeup_event(0);
local_irq_restore(flags);
}
static unsigned long long cyc2ns_suspend;
void tsc_save_sched_clock_state(void)
{
if (!sched_clock_stable)
return;
cyc2ns_suspend = sched_clock();
}
/*
* Even on processors with invariant TSC, TSC gets reset in some the
* ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
* arbitrary value (still sync'd across cpu's) during resume from such sleep
* states. To cope up with this, recompute the cyc2ns_offset for each cpu so
* that sched_clock() continues from the point where it was left off during
* suspend.
*/
void tsc_restore_sched_clock_state(void)
{
unsigned long long offset;
unsigned long flags;
int cpu;
if (!sched_clock_stable)
return;
local_irq_save(flags);
__this_cpu_write(cyc2ns_offset, 0);
offset = cyc2ns_suspend - sched_clock();
for_each_possible_cpu(cpu)
per_cpu(cyc2ns_offset, cpu) = offset;
local_irq_restore(flags);
}
#ifdef CONFIG_CPU_FREQ
/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
* changes.
*
* RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
* not that important because current Opteron setups do not support
* scaling on SMP anyroads.
*
* Should fix up last_tsc too. Currently gettimeofday in the
* first tick after the change will be slightly wrong.
*/
static unsigned int ref_freq;
static unsigned long loops_per_jiffy_ref;
static unsigned long tsc_khz_ref;
static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
void *data)
{
struct cpufreq_freqs *freq = data;
unsigned long *lpj;
if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
return 0;
lpj = &boot_cpu_data.loops_per_jiffy;
#ifdef CONFIG_SMP
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
lpj = &cpu_data(freq->cpu).loops_per_jiffy;
#endif
if (!ref_freq) {
ref_freq = freq->old;
loops_per_jiffy_ref = *lpj;
tsc_khz_ref = tsc_khz;
}
if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
(val == CPUFREQ_RESUMECHANGE)) {
*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
mark_tsc_unstable("cpufreq changes");
}
set_cyc2ns_scale(tsc_khz, freq->cpu);
return 0;
}
static struct notifier_block time_cpufreq_notifier_block = {
.notifier_call = time_cpufreq_notifier
};
static int __init cpufreq_tsc(void)
{
if (!cpu_has_tsc)
return 0;
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
return 0;
cpufreq_register_notifier(&time_cpufreq_notifier_block,
CPUFREQ_TRANSITION_NOTIFIER);
return 0;
}
core_initcall(cpufreq_tsc);
#endif /* CONFIG_CPU_FREQ */
/* clocksource code */
static struct clocksource clocksource_tsc;
/*
* We compare the TSC to the cycle_last value in the clocksource
* structure to avoid a nasty time-warp. This can be observed in a
* very small window right after one CPU updated cycle_last under
* xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
* is smaller than the cycle_last reference value due to a TSC which
* is slighty behind. This delta is nowhere else observable, but in
* that case it results in a forward time jump in the range of hours
* due to the unsigned delta calculation of the time keeping core
* code, which is necessary to support wrapping clocksources like pm
* timer.
*/
static cycle_t read_tsc(struct clocksource *cs)
{
cycle_t ret = (cycle_t)get_cycles();
return ret >= clocksource_tsc.cycle_last ?
ret : clocksource_tsc.cycle_last;
}
static void resume_tsc(struct clocksource *cs)
{
clocksource_tsc.cycle_last = 0;
}
static struct clocksource clocksource_tsc = {
.name = "tsc",
.rating = 300,
.read = read_tsc,
.resume = resume_tsc,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
CLOCK_SOURCE_MUST_VERIFY,
#ifdef CONFIG_X86_64
.archdata = { .vclock_mode = VCLOCK_TSC },
#endif
};
void mark_tsc_unstable(char *reason)
{
if (!tsc_unstable) {
tsc_unstable = 1;
sched_clock_stable = 0;
disable_sched_clock_irqtime();
printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
/* Change only the rating, when not registered */
if (clocksource_tsc.mult)
clocksource_mark_unstable(&clocksource_tsc);
else {
clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
clocksource_tsc.rating = 0;
}
}
}
EXPORT_SYMBOL_GPL(mark_tsc_unstable);
static void __init check_system_tsc_reliable(void)
{
#ifdef CONFIG_MGEODE_LX
/* RTSC counts during suspend */
#define RTSC_SUSP 0x100
unsigned long res_low, res_high;
rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
/* Geode_LX - the OLPC CPU has a very reliable TSC */
if (res_low & RTSC_SUSP)
tsc_clocksource_reliable = 1;
#endif
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
tsc_clocksource_reliable = 1;
}
/*
* Make an educated guess if the TSC is trustworthy and synchronized
* over all CPUs.
*/
__cpuinit int unsynchronized_tsc(void)
{
if (!cpu_has_tsc || tsc_unstable)
return 1;
#ifdef CONFIG_SMP
if (apic_is_clustered_box())
return 1;
#endif
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
return 0;
if (tsc_clocksource_reliable)
return 0;
/*
* Intel systems are normally all synchronized.
* Exceptions must mark TSC as unstable:
*/
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
/* assume multi socket systems are not synchronized: */
if (num_possible_cpus() > 1)
return 1;
}
return 0;
}
static void tsc_refine_calibration_work(struct work_struct *work);
static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
/**
* tsc_refine_calibration_work - Further refine tsc freq calibration
* @work - ignored.
*
* This functions uses delayed work over a period of a
* second to further refine the TSC freq value. Since this is
* timer based, instead of loop based, we don't block the boot
* process while this longer calibration is done.
*
* If there are any calibration anomalies (too many SMIs, etc),
* or the refined calibration is off by 1% of the fast early
* calibration, we throw out the new calibration and use the
* early calibration.
*/
static void tsc_refine_calibration_work(struct work_struct *work)
{
static u64 tsc_start = -1, ref_start;
static int hpet;
u64 tsc_stop, ref_stop, delta;
unsigned long freq;
/* Don't bother refining TSC on unstable systems */
if (check_tsc_unstable())
goto out;
/*
* Since the work is started early in boot, we may be
* delayed the first time we expire. So set the workqueue
* again once we know timers are working.
*/
if (tsc_start == -1) {
/*
* Only set hpet once, to avoid mixing hardware
* if the hpet becomes enabled later.
*/
hpet = is_hpet_enabled();
schedule_delayed_work(&tsc_irqwork, HZ);
tsc_start = tsc_read_refs(&ref_start, hpet);
return;
}
tsc_stop = tsc_read_refs(&ref_stop, hpet);
/* hpet or pmtimer available ? */
if (ref_start == ref_stop)
goto out;
/* Check, whether the sampling was disturbed by an SMI */
if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
goto out;
delta = tsc_stop - tsc_start;
delta *= 1000000LL;
if (hpet)
freq = calc_hpet_ref(delta, ref_start, ref_stop);
else
freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
/* Make sure we're within 1% */
if (abs(tsc_khz - freq) > tsc_khz/100)
goto out;
tsc_khz = freq;
printk(KERN_INFO "Refined TSC clocksource calibration: "
"%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
(unsigned long)tsc_khz % 1000);
out:
clocksource_register_khz(&clocksource_tsc, tsc_khz);
}
static int __init init_tsc_clocksource(void)
{
if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
return 0;
if (tsc_clocksource_reliable)
clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
/* lower the rating if we already know its unstable: */
if (check_tsc_unstable()) {
clocksource_tsc.rating = 0;
clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
}
/*
* Trust the results of the earlier calibration on systems
* exporting a reliable TSC.
*/
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
clocksource_register_khz(&clocksource_tsc, tsc_khz);
return 0;
}
schedule_delayed_work(&tsc_irqwork, 0);
return 0;
}
/*
* We use device_initcall here, to ensure we run after the hpet
* is fully initialized, which may occur at fs_initcall time.
*/
device_initcall(init_tsc_clocksource);
void __init tsc_init(void)
{
u64 lpj;
int cpu;
x86_init.timers.tsc_pre_init();
if (!cpu_has_tsc)
return;
tsc_khz = x86_platform.calibrate_tsc();
cpu_khz = tsc_khz;
if (!tsc_khz) {
mark_tsc_unstable("could not calculate TSC khz");
return;
}
printk("Detected %lu.%03lu MHz processor.\n",
(unsigned long)cpu_khz / 1000,
(unsigned long)cpu_khz % 1000);
/*
* Secondary CPUs do not run through tsc_init(), so set up
* all the scale factors for all CPUs, assuming the same
* speed as the bootup CPU. (cpufreq notifiers will fix this
* up if their speed diverges)
*/
for_each_possible_cpu(cpu)
set_cyc2ns_scale(cpu_khz, cpu);
if (tsc_disabled > 0)
return;
/* now allow native_sched_clock() to use rdtsc */
tsc_disabled = 0;
if (!no_sched_irq_time)
enable_sched_clock_irqtime();
lpj = ((u64)tsc_khz * 1000);
do_div(lpj, HZ);
lpj_fine = lpj;
use_tsc_delay();
if (unsynchronized_tsc())
mark_tsc_unstable("TSCs unsynchronized");
check_system_tsc_reliable();
}
#ifdef CONFIG_SMP
/*
* If we have a constant TSC and are using the TSC for the delay loop,
* we can skip clock calibration if another cpu in the same socket has already
* been calibrated. This assumes that CONSTANT_TSC applies to all
* cpus in the socket - this should be a safe assumption.
*/
unsigned long __cpuinit calibrate_delay_is_known(void)
{
int i, cpu = smp_processor_id();
if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
return 0;
for_each_online_cpu(i)
if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
return cpu_data(i).loops_per_jiffy;
return 0;
}
#endif
| gpl-2.0 |
jeremytrimble/adi-linux | drivers/net/fddi/skfp/pmf.c | 4586 | 40418 | /******************************************************************************
*
* (C)Copyright 1998,1999 SysKonnect,
* a business unit of Schneider & Koch & Co. Datensysteme GmbH.
*
* See the file "skfddi.c" for further information.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* The information in this file is provided "AS IS" without warranty.
*
******************************************************************************/
/*
Parameter Management Frame processing for SMT 7.2
*/
#include "h/types.h"
#include "h/fddi.h"
#include "h/smc.h"
#include "h/smt_p.h"
#define KERNEL
#include "h/smtstate.h"
#ifndef SLIM_SMT
#ifndef lint
static const char ID_sccs[] = "@(#)pmf.c 1.37 97/08/04 (C) SK " ;
#endif
static int smt_authorize(struct s_smc *smc, struct smt_header *sm);
static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm);
static const struct s_p_tab* smt_get_ptab(u_short para);
static int smt_mib_phys(struct s_smc *smc);
static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
int local, int set);
void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
int index, int local);
static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
int set, int local);
static int port_to_mib(struct s_smc *smc, int p);
#define MOFFSS(e) offsetof(struct fddi_mib, e)
#define MOFFMS(e) offsetof(struct fddi_mib_m, e)
#define MOFFAS(e) offsetof(struct fddi_mib_a, e)
#define MOFFPS(e) offsetof(struct fddi_mib_p, e)
#define AC_G 0x01 /* Get */
#define AC_GR 0x02 /* Get/Set */
#define AC_S 0x04 /* Set */
#define AC_NA 0x08
#define AC_GROUP 0x10 /* Group */
#define MS2BCLK(x) ((x)*12500L)
/*
F LFag (byte)
B byte
S u_short 16 bit
C Counter 32 bit
L Long 32 bit
T Timer_2 32 bit
P TimeStamp ;
A LongAddress (6 byte)
E Enum 16 bit
R ResId 16 Bit
*/
static const struct s_p_tab {
u_short p_num ; /* parameter code */
u_char p_access ; /* access rights */
u_short p_offset ; /* offset in mib */
char p_swap[3] ; /* format string */
} p_tab[] = {
/* StationIdGrp */
{ SMT_P100A,AC_GROUP } ,
{ SMT_P100B,AC_G, MOFFSS(fddiSMTStationId), "8" } ,
{ SMT_P100D,AC_G, MOFFSS(fddiSMTOpVersionId), "S" } ,
{ SMT_P100E,AC_G, MOFFSS(fddiSMTHiVersionId), "S" } ,
{ SMT_P100F,AC_G, MOFFSS(fddiSMTLoVersionId), "S" } ,
{ SMT_P1010,AC_G, MOFFSS(fddiSMTManufacturerData), "D" } ,
{ SMT_P1011,AC_GR, MOFFSS(fddiSMTUserData), "D" } ,
{ SMT_P1012,AC_G, MOFFSS(fddiSMTMIBVersionId), "S" } ,
/* StationConfigGrp */
{ SMT_P1014,AC_GROUP } ,
{ SMT_P1015,AC_G, MOFFSS(fddiSMTMac_Ct), "B" } ,
{ SMT_P1016,AC_G, MOFFSS(fddiSMTNonMaster_Ct), "B" } ,
{ SMT_P1017,AC_G, MOFFSS(fddiSMTMaster_Ct), "B" } ,
{ SMT_P1018,AC_G, MOFFSS(fddiSMTAvailablePaths), "B" } ,
{ SMT_P1019,AC_G, MOFFSS(fddiSMTConfigCapabilities),"S" } ,
{ SMT_P101A,AC_GR, MOFFSS(fddiSMTConfigPolicy), "wS" } ,
{ SMT_P101B,AC_GR, MOFFSS(fddiSMTConnectionPolicy),"wS" } ,
{ SMT_P101D,AC_GR, MOFFSS(fddiSMTTT_Notify), "wS" } ,
{ SMT_P101E,AC_GR, MOFFSS(fddiSMTStatRptPolicy), "bB" } ,
{ SMT_P101F,AC_GR, MOFFSS(fddiSMTTrace_MaxExpiration),"lL" } ,
{ SMT_P1020,AC_G, MOFFSS(fddiSMTPORTIndexes), "II" } ,
{ SMT_P1021,AC_G, MOFFSS(fddiSMTMACIndexes), "I" } ,
{ SMT_P1022,AC_G, MOFFSS(fddiSMTBypassPresent), "F" } ,
/* StatusGrp */
{ SMT_P1028,AC_GROUP } ,
{ SMT_P1029,AC_G, MOFFSS(fddiSMTECMState), "E" } ,
{ SMT_P102A,AC_G, MOFFSS(fddiSMTCF_State), "E" } ,
{ SMT_P102C,AC_G, MOFFSS(fddiSMTRemoteDisconnectFlag),"F" } ,
{ SMT_P102D,AC_G, MOFFSS(fddiSMTStationStatus), "E" } ,
{ SMT_P102E,AC_G, MOFFSS(fddiSMTPeerWrapFlag), "F" } ,
/* MIBOperationGrp */
{ SMT_P1032,AC_GROUP } ,
{ SMT_P1033,AC_G, MOFFSS(fddiSMTTimeStamp),"P" } ,
{ SMT_P1034,AC_G, MOFFSS(fddiSMTTransitionTimeStamp),"P" } ,
/* NOTE : SMT_P1035 is already swapped ! SMT_P_SETCOUNT */
{ SMT_P1035,AC_G, MOFFSS(fddiSMTSetCount),"4P" } ,
{ SMT_P1036,AC_G, MOFFSS(fddiSMTLastSetStationId),"8" } ,
{ SMT_P103C,AC_S, 0, "wS" } ,
/*
* PRIVATE EXTENSIONS
* only accessible locally to get/set passwd
*/
{ SMT_P10F0,AC_GR, MOFFSS(fddiPRPMFPasswd), "8" } ,
{ SMT_P10F1,AC_GR, MOFFSS(fddiPRPMFStation), "8" } ,
#ifdef ESS
{ SMT_P10F2,AC_GR, MOFFSS(fddiESSPayload), "lL" } ,
{ SMT_P10F3,AC_GR, MOFFSS(fddiESSOverhead), "lL" } ,
{ SMT_P10F4,AC_GR, MOFFSS(fddiESSMaxTNeg), "lL" } ,
{ SMT_P10F5,AC_GR, MOFFSS(fddiESSMinSegmentSize), "lL" } ,
{ SMT_P10F6,AC_GR, MOFFSS(fddiESSCategory), "lL" } ,
{ SMT_P10F7,AC_GR, MOFFSS(fddiESSSynchTxMode), "wS" } ,
#endif
#ifdef SBA
{ SMT_P10F8,AC_GR, MOFFSS(fddiSBACommand), "bF" } ,
{ SMT_P10F9,AC_GR, MOFFSS(fddiSBAAvailable), "bF" } ,
#endif
/* MAC Attributes */
{ SMT_P200A,AC_GROUP } ,
{ SMT_P200B,AC_G, MOFFMS(fddiMACFrameStatusFunctions),"S" } ,
{ SMT_P200D,AC_G, MOFFMS(fddiMACT_MaxCapabilitiy),"T" } ,
{ SMT_P200E,AC_G, MOFFMS(fddiMACTVXCapabilitiy),"T" } ,
/* ConfigGrp */
{ SMT_P2014,AC_GROUP } ,
{ SMT_P2016,AC_G, MOFFMS(fddiMACAvailablePaths), "B" } ,
{ SMT_P2017,AC_G, MOFFMS(fddiMACCurrentPath), "S" } ,
{ SMT_P2018,AC_G, MOFFMS(fddiMACUpstreamNbr), "A" } ,
{ SMT_P2019,AC_G, MOFFMS(fddiMACDownstreamNbr), "A" } ,
{ SMT_P201A,AC_G, MOFFMS(fddiMACOldUpstreamNbr), "A" } ,
{ SMT_P201B,AC_G, MOFFMS(fddiMACOldDownstreamNbr),"A" } ,
{ SMT_P201D,AC_G, MOFFMS(fddiMACDupAddressTest), "E" } ,
{ SMT_P2020,AC_GR, MOFFMS(fddiMACRequestedPaths), "wS" } ,
{ SMT_P2021,AC_G, MOFFMS(fddiMACDownstreamPORTType),"E" } ,
{ SMT_P2022,AC_G, MOFFMS(fddiMACIndex), "S" } ,
/* AddressGrp */
{ SMT_P2028,AC_GROUP } ,
{ SMT_P2029,AC_G, MOFFMS(fddiMACSMTAddress), "A" } ,
/* OperationGrp */
{ SMT_P2032,AC_GROUP } ,
{ SMT_P2033,AC_G, MOFFMS(fddiMACT_Req), "T" } ,
{ SMT_P2034,AC_G, MOFFMS(fddiMACT_Neg), "T" } ,
{ SMT_P2035,AC_G, MOFFMS(fddiMACT_Max), "T" } ,
{ SMT_P2036,AC_G, MOFFMS(fddiMACTvxValue), "T" } ,
{ SMT_P2038,AC_G, MOFFMS(fddiMACT_Pri0), "T" } ,
{ SMT_P2039,AC_G, MOFFMS(fddiMACT_Pri1), "T" } ,
{ SMT_P203A,AC_G, MOFFMS(fddiMACT_Pri2), "T" } ,
{ SMT_P203B,AC_G, MOFFMS(fddiMACT_Pri3), "T" } ,
{ SMT_P203C,AC_G, MOFFMS(fddiMACT_Pri4), "T" } ,
{ SMT_P203D,AC_G, MOFFMS(fddiMACT_Pri5), "T" } ,
{ SMT_P203E,AC_G, MOFFMS(fddiMACT_Pri6), "T" } ,
/* CountersGrp */
{ SMT_P2046,AC_GROUP } ,
{ SMT_P2047,AC_G, MOFFMS(fddiMACFrame_Ct), "C" } ,
{ SMT_P2048,AC_G, MOFFMS(fddiMACCopied_Ct), "C" } ,
{ SMT_P2049,AC_G, MOFFMS(fddiMACTransmit_Ct), "C" } ,
{ SMT_P204A,AC_G, MOFFMS(fddiMACToken_Ct), "C" } ,
{ SMT_P2051,AC_G, MOFFMS(fddiMACError_Ct), "C" } ,
{ SMT_P2052,AC_G, MOFFMS(fddiMACLost_Ct), "C" } ,
{ SMT_P2053,AC_G, MOFFMS(fddiMACTvxExpired_Ct), "C" } ,
{ SMT_P2054,AC_G, MOFFMS(fddiMACNotCopied_Ct), "C" } ,
{ SMT_P2056,AC_G, MOFFMS(fddiMACRingOp_Ct), "C" } ,
/* FrameErrorConditionGrp */
{ SMT_P205A,AC_GROUP } ,
{ SMT_P205F,AC_GR, MOFFMS(fddiMACFrameErrorThreshold),"wS" } ,
{ SMT_P2060,AC_G, MOFFMS(fddiMACFrameErrorRatio), "S" } ,
/* NotCopiedConditionGrp */
{ SMT_P2064,AC_GROUP } ,
{ SMT_P2067,AC_GR, MOFFMS(fddiMACNotCopiedThreshold),"wS" } ,
{ SMT_P2069,AC_G, MOFFMS(fddiMACNotCopiedRatio), "S" } ,
/* StatusGrp */
{ SMT_P206E,AC_GROUP } ,
{ SMT_P206F,AC_G, MOFFMS(fddiMACRMTState), "S" } ,
{ SMT_P2070,AC_G, MOFFMS(fddiMACDA_Flag), "F" } ,
{ SMT_P2071,AC_G, MOFFMS(fddiMACUNDA_Flag), "F" } ,
{ SMT_P2072,AC_G, MOFFMS(fddiMACFrameErrorFlag), "F" } ,
{ SMT_P2073,AC_G, MOFFMS(fddiMACNotCopiedFlag), "F" } ,
{ SMT_P2074,AC_G, MOFFMS(fddiMACMA_UnitdataAvailable),"F" } ,
{ SMT_P2075,AC_G, MOFFMS(fddiMACHardwarePresent), "F" } ,
{ SMT_P2076,AC_GR, MOFFMS(fddiMACMA_UnitdataEnable),"bF" } ,
/*
* PRIVATE EXTENSIONS
* only accessible locally to get/set TMIN
*/
{ SMT_P20F0,AC_NA } ,
{ SMT_P20F1,AC_GR, MOFFMS(fddiMACT_Min), "lT" } ,
/* Path Attributes */
/*
* DON't swap 320B,320F,3210: they are already swapped in swap_para()
*/
{ SMT_P320A,AC_GROUP } ,
{ SMT_P320B,AC_G, MOFFAS(fddiPATHIndex), "r" } ,
{ SMT_P320F,AC_GR, MOFFAS(fddiPATHSbaPayload), "l4" } ,
{ SMT_P3210,AC_GR, MOFFAS(fddiPATHSbaOverhead), "l4" } ,
/* fddiPATHConfiguration */
{ SMT_P3212,AC_G, 0, "" } ,
{ SMT_P3213,AC_GR, MOFFAS(fddiPATHT_Rmode), "lT" } ,
{ SMT_P3214,AC_GR, MOFFAS(fddiPATHSbaAvailable), "lL" } ,
{ SMT_P3215,AC_GR, MOFFAS(fddiPATHTVXLowerBound), "lT" } ,
{ SMT_P3216,AC_GR, MOFFAS(fddiPATHT_MaxLowerBound),"lT" } ,
{ SMT_P3217,AC_GR, MOFFAS(fddiPATHMaxT_Req), "lT" } ,
/* Port Attributes */
/* ConfigGrp */
{ SMT_P400A,AC_GROUP } ,
{ SMT_P400C,AC_G, MOFFPS(fddiPORTMy_Type), "E" } ,
{ SMT_P400D,AC_G, MOFFPS(fddiPORTNeighborType), "E" } ,
{ SMT_P400E,AC_GR, MOFFPS(fddiPORTConnectionPolicies),"bB" } ,
{ SMT_P400F,AC_G, MOFFPS(fddiPORTMacIndicated), "2" } ,
{ SMT_P4010,AC_G, MOFFPS(fddiPORTCurrentPath), "E" } ,
{ SMT_P4011,AC_GR, MOFFPS(fddiPORTRequestedPaths), "l4" } ,
{ SMT_P4012,AC_G, MOFFPS(fddiPORTMACPlacement), "S" } ,
{ SMT_P4013,AC_G, MOFFPS(fddiPORTAvailablePaths), "B" } ,
{ SMT_P4016,AC_G, MOFFPS(fddiPORTPMDClass), "E" } ,
{ SMT_P4017,AC_G, MOFFPS(fddiPORTConnectionCapabilities), "B"} ,
{ SMT_P401D,AC_G, MOFFPS(fddiPORTIndex), "R" } ,
/* OperationGrp */
{ SMT_P401E,AC_GROUP } ,
{ SMT_P401F,AC_GR, MOFFPS(fddiPORTMaint_LS), "wE" } ,
{ SMT_P4021,AC_G, MOFFPS(fddiPORTBS_Flag), "F" } ,
{ SMT_P4022,AC_G, MOFFPS(fddiPORTPC_LS), "E" } ,
/* ErrorCtrsGrp */
{ SMT_P4028,AC_GROUP } ,
{ SMT_P4029,AC_G, MOFFPS(fddiPORTEBError_Ct), "C" } ,
{ SMT_P402A,AC_G, MOFFPS(fddiPORTLCTFail_Ct), "C" } ,
/* LerGrp */
{ SMT_P4032,AC_GROUP } ,
{ SMT_P4033,AC_G, MOFFPS(fddiPORTLer_Estimate), "F" } ,
{ SMT_P4034,AC_G, MOFFPS(fddiPORTLem_Reject_Ct), "C" } ,
{ SMT_P4035,AC_G, MOFFPS(fddiPORTLem_Ct), "C" } ,
{ SMT_P403A,AC_GR, MOFFPS(fddiPORTLer_Cutoff), "bB" } ,
{ SMT_P403B,AC_GR, MOFFPS(fddiPORTLer_Alarm), "bB" } ,
/* StatusGrp */
{ SMT_P403C,AC_GROUP } ,
{ SMT_P403D,AC_G, MOFFPS(fddiPORTConnectState), "E" } ,
{ SMT_P403E,AC_G, MOFFPS(fddiPORTPCMStateX), "E" } ,
{ SMT_P403F,AC_G, MOFFPS(fddiPORTPC_Withhold), "E" } ,
{ SMT_P4040,AC_G, MOFFPS(fddiPORTLerFlag), "F" } ,
{ SMT_P4041,AC_G, MOFFPS(fddiPORTHardwarePresent),"F" } ,
{ SMT_P4046,AC_S, 0, "wS" } ,
{ 0, AC_GROUP } ,
{ 0 }
} ;
void smt_pmf_received_pack(struct s_smc *smc, SMbuf *mb, int local)
{
struct smt_header *sm ;
SMbuf *reply ;
sm = smtod(mb,struct smt_header *) ;
DB_SMT("SMT: processing PMF frame at %x len %d\n",sm,mb->sm_len) ;
#ifdef DEBUG
dump_smt(smc,sm,"PMF Received") ;
#endif
/*
* Start the watchdog: It may be a long, long packet and
* maybe the watchdog occurs ...
*/
smt_start_watchdog(smc) ;
if (sm->smt_class == SMT_PMF_GET ||
sm->smt_class == SMT_PMF_SET) {
reply = smt_build_pmf_response(smc,sm,
sm->smt_class == SMT_PMF_SET,local) ;
if (reply) {
sm = smtod(reply,struct smt_header *) ;
#ifdef DEBUG
dump_smt(smc,sm,"PMF Reply") ;
#endif
smt_send_frame(smc,reply,FC_SMT_INFO,local) ;
}
}
}
static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
int set, int local)
{
SMbuf *mb ;
struct smt_header *smt ;
struct smt_para *pa ;
struct smt_p_reason *res ;
const struct s_p_tab *pt ;
int len ;
int index ;
int idx_end ;
int error ;
int range ;
SK_LOC_DECL(struct s_pcon,pcon) ;
SK_LOC_DECL(struct s_pcon,set_pcon) ;
/*
* build SMT header
*/
if (!(mb = smt_get_mbuf(smc)))
return mb;
smt = smtod(mb, struct smt_header *) ;
smt->smt_dest = req->smt_source ; /* DA == source of request */
smt->smt_class = req->smt_class ; /* same class (GET/SET) */
smt->smt_type = SMT_REPLY ;
smt->smt_version = SMT_VID_2 ;
smt->smt_tid = req->smt_tid ; /* same TID */
smt->smt_pad = 0 ;
smt->smt_len = 0 ;
/*
* setup parameter status
*/
pcon.pc_len = SMT_MAX_INFO_LEN ; /* max para length */
pcon.pc_err = 0 ; /* no error */
pcon.pc_badset = 0 ; /* no bad set count */
pcon.pc_p = (void *) (smt + 1) ; /* paras start here */
/*
* check authoriziation and set count
*/
error = 0 ;
if (set) {
if (!local && smt_authorize(smc,req))
error = SMT_RDF_AUTHOR ;
else if (smt_check_set_count(smc,req))
pcon.pc_badset = SMT_RDF_BADSET ;
}
/*
* add reason code and all mandatory parameters
*/
res = (struct smt_p_reason *) pcon.pc_p ;
smt_add_para(smc,&pcon,(u_short) SMT_P_REASON,0,0) ;
smt_add_para(smc,&pcon,(u_short) SMT_P1033,0,0) ;
/* update 1035 and 1036 later if set */
set_pcon = pcon ;
smt_add_para(smc,&pcon,(u_short) SMT_P1035,0,0) ;
smt_add_para(smc,&pcon,(u_short) SMT_P1036,0,0) ;
pcon.pc_err = error ;
len = req->smt_len ;
pa = (struct smt_para *) (req + 1) ;
/*
* process list of paras
*/
while (!pcon.pc_err && len > 0 ) {
if (((u_short)len < pa->p_len + PARA_LEN) || (pa->p_len & 3)) {
pcon.pc_err = SMT_RDF_LENGTH ;
break ;
}
if (((range = (pa->p_type & 0xf000)) == 0x2000) ||
range == 0x3000 || range == 0x4000) {
/*
* get index for PART,MAC ad PATH group
*/
index = *((u_char *)pa + PARA_LEN + 3) ;/* index */
idx_end = index ;
if (!set && (pa->p_len != 4)) {
pcon.pc_err = SMT_RDF_LENGTH ;
break ;
}
if (!index && !set) {
switch (range) {
case 0x2000 :
index = INDEX_MAC ;
idx_end = index - 1 + NUMMACS ;
break ;
case 0x3000 :
index = INDEX_PATH ;
idx_end = index - 1 + NUMPATHS ;
break ;
case 0x4000 :
index = INDEX_PORT ;
idx_end = index - 1 + NUMPHYS ;
#ifndef CONCENTRATOR
if (smc->s.sas == SMT_SAS)
idx_end = INDEX_PORT ;
#endif
break ;
}
}
}
else {
/*
* smt group has no index
*/
if (!set && (pa->p_len != 0)) {
pcon.pc_err = SMT_RDF_LENGTH ;
break ;
}
index = 0 ;
idx_end = 0 ;
}
while (index <= idx_end) {
/*
* if group
* add all paras of group
*/
pt = smt_get_ptab(pa->p_type) ;
if (pt && pt->p_access == AC_GROUP && !set) {
pt++ ;
while (pt->p_access == AC_G ||
pt->p_access == AC_GR) {
smt_add_para(smc,&pcon,pt->p_num,
index,local);
pt++ ;
}
}
/*
* ignore
* AUTHORIZATION in get/set
* SET COUNT in set
*/
else if (pa->p_type != SMT_P_AUTHOR &&
(!set || (pa->p_type != SMT_P1035))) {
int st ;
if (pcon.pc_badset) {
smt_add_para(smc,&pcon,pa->p_type,
index,local) ;
}
else if (set) {
st = smt_set_para(smc,pa,index,local,1);
/*
* return para even if error
*/
smt_add_para(smc,&pcon,pa->p_type,
index,local) ;
pcon.pc_err = st ;
}
else {
if (pt && pt->p_access == AC_S) {
pcon.pc_err =
SMT_RDF_ILLEGAL ;
}
smt_add_para(smc,&pcon,pa->p_type,
index,local) ;
}
}
if (pcon.pc_err)
break ;
index++ ;
}
len -= pa->p_len + PARA_LEN ;
pa = (struct smt_para *) ((char *)pa + pa->p_len + PARA_LEN) ;
}
smt->smt_len = SMT_MAX_INFO_LEN - pcon.pc_len ;
mb->sm_len = smt->smt_len + sizeof(struct smt_header) ;
/* update reason code */
res->rdf_reason = pcon.pc_badset ? pcon.pc_badset :
pcon.pc_err ? pcon.pc_err : SMT_RDF_SUCCESS ;
if (set && (res->rdf_reason == SMT_RDF_SUCCESS)) {
/*
* increment set count
* set time stamp
* store station id of last set
*/
smc->mib.fddiSMTSetCount.count++ ;
smt_set_timestamp(smc,smc->mib.fddiSMTSetCount.timestamp) ;
smc->mib.fddiSMTLastSetStationId = req->smt_sid ;
smt_add_para(smc,&set_pcon,(u_short) SMT_P1035,0,0) ;
smt_add_para(smc,&set_pcon,(u_short) SMT_P1036,0,0) ;
}
return mb;
}
static int smt_authorize(struct s_smc *smc, struct smt_header *sm)
{
struct smt_para *pa ;
int i ;
char *p ;
/*
* check source station id if not zero
*/
p = (char *) &smc->mib.fddiPRPMFStation ;
for (i = 0 ; i < 8 && !p[i] ; i++)
;
if (i != 8) {
if (memcmp((char *) &sm->smt_sid,
(char *) &smc->mib.fddiPRPMFStation,8))
return 1;
}
/*
* check authoriziation parameter if passwd not zero
*/
p = (char *) smc->mib.fddiPRPMFPasswd ;
for (i = 0 ; i < 8 && !p[i] ; i++)
;
if (i != 8) {
pa = (struct smt_para *) sm_to_para(smc,sm,SMT_P_AUTHOR) ;
if (!pa)
return 1;
if (pa->p_len != 8)
return 1;
if (memcmp((char *)(pa+1),(char *)smc->mib.fddiPRPMFPasswd,8))
return 1;
}
return 0;
}
static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm)
{
struct smt_para *pa ;
struct smt_p_setcount *sc ;
pa = (struct smt_para *) sm_to_para(smc,sm,SMT_P1035) ;
if (pa) {
sc = (struct smt_p_setcount *) pa ;
if ((smc->mib.fddiSMTSetCount.count != sc->count) ||
memcmp((char *) smc->mib.fddiSMTSetCount.timestamp,
(char *)sc->timestamp,8))
return 1;
}
return 0;
}
void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
int index, int local)
{
struct smt_para *pa ;
const struct s_p_tab *pt ;
struct fddi_mib_m *mib_m = NULL;
struct fddi_mib_p *mib_p = NULL;
int len ;
int plen ;
char *from ;
char *to ;
const char *swap ;
char c ;
int range ;
char *mib_addr ;
int mac ;
int path ;
int port ;
int sp_len ;
/*
* skip if error
*/
if (pcon->pc_err)
return ;
/*
* actions don't have a value
*/
pt = smt_get_ptab(para) ;
if (pt && pt->p_access == AC_S)
return ;
to = (char *) (pcon->pc_p) ; /* destination pointer */
len = pcon->pc_len ; /* free space */
plen = len ; /* remember start length */
pa = (struct smt_para *) to ; /* type/length pointer */
to += PARA_LEN ; /* skip smt_para */
len -= PARA_LEN ;
/*
* set index if required
*/
if (((range = (para & 0xf000)) == 0x2000) ||
range == 0x3000 || range == 0x4000) {
if (len < 4)
goto wrong_error ;
to[0] = 0 ;
to[1] = 0 ;
to[2] = 0 ;
to[3] = index ;
len -= 4 ;
to += 4 ;
}
mac = index - INDEX_MAC ;
path = index - INDEX_PATH ;
port = index - INDEX_PORT ;
/*
* get pointer to mib
*/
switch (range) {
case 0x1000 :
default :
mib_addr = (char *) (&smc->mib) ;
break ;
case 0x2000 :
if (mac < 0 || mac >= NUMMACS) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
mib_addr = (char *) (&smc->mib.m[mac]) ;
mib_m = (struct fddi_mib_m *) mib_addr ;
break ;
case 0x3000 :
if (path < 0 || path >= NUMPATHS) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
mib_addr = (char *) (&smc->mib.a[path]) ;
break ;
case 0x4000 :
if (port < 0 || port >= smt_mib_phys(smc)) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
mib_addr = (char *) (&smc->mib.p[port_to_mib(smc,port)]) ;
mib_p = (struct fddi_mib_p *) mib_addr ;
break ;
}
/*
* check special paras
*/
swap = NULL;
switch (para) {
case SMT_P10F0 :
case SMT_P10F1 :
#ifdef ESS
case SMT_P10F2 :
case SMT_P10F3 :
case SMT_P10F4 :
case SMT_P10F5 :
case SMT_P10F6 :
case SMT_P10F7 :
#endif
#ifdef SBA
case SMT_P10F8 :
case SMT_P10F9 :
#endif
case SMT_P20F1 :
if (!local) {
pcon->pc_err = SMT_RDF_NOPARAM ;
return ;
}
break ;
case SMT_P2034 :
case SMT_P2046 :
case SMT_P2047 :
case SMT_P204A :
case SMT_P2051 :
case SMT_P2052 :
mac_update_counter(smc) ;
break ;
case SMT_P4022:
mib_p->fddiPORTPC_LS = LS2MIB(
sm_pm_get_ls(smc,port_to_mib(smc,port))) ;
break ;
case SMT_P_REASON :
*(u32 *)to = 0 ;
sp_len = 4 ;
goto sp_done ;
case SMT_P1033 : /* time stamp */
smt_set_timestamp(smc,smc->mib.fddiSMTTimeStamp) ;
break ;
case SMT_P1020: /* port indexes */
#if NUMPHYS == 12
swap = "IIIIIIIIIIII" ;
#else
#if NUMPHYS == 2
if (smc->s.sas == SMT_SAS)
swap = "I" ;
else
swap = "II" ;
#else
#if NUMPHYS == 24
swap = "IIIIIIIIIIIIIIIIIIIIIIII" ;
#else
????
#endif
#endif
#endif
break ;
case SMT_P3212 :
{
sp_len = cem_build_path(smc,to,path) ;
goto sp_done ;
}
case SMT_P1048 : /* peer wrap condition */
{
struct smt_p_1048 *sp ;
sp = (struct smt_p_1048 *) to ;
sp->p1048_flag = smc->mib.fddiSMTPeerWrapFlag ;
sp->p1048_cf_state = smc->mib.fddiSMTCF_State ;
sp_len = sizeof(struct smt_p_1048) ;
goto sp_done ;
}
case SMT_P208C :
{
struct smt_p_208c *sp ;
sp = (struct smt_p_208c *) to ;
sp->p208c_flag =
smc->mib.m[MAC0].fddiMACDuplicateAddressCond ;
sp->p208c_dupcondition =
(mib_m->fddiMACDA_Flag ? SMT_ST_MY_DUPA : 0) |
(mib_m->fddiMACUNDA_Flag ? SMT_ST_UNA_DUPA : 0);
sp->p208c_fddilong =
mib_m->fddiMACSMTAddress ;
sp->p208c_fddiunalong =
mib_m->fddiMACUpstreamNbr ;
sp->p208c_pad = 0 ;
sp_len = sizeof(struct smt_p_208c) ;
goto sp_done ;
}
case SMT_P208D : /* frame error condition */
{
struct smt_p_208d *sp ;
sp = (struct smt_p_208d *) to ;
sp->p208d_flag =
mib_m->fddiMACFrameErrorFlag ;
sp->p208d_frame_ct =
mib_m->fddiMACFrame_Ct ;
sp->p208d_error_ct =
mib_m->fddiMACError_Ct ;
sp->p208d_lost_ct =
mib_m->fddiMACLost_Ct ;
sp->p208d_ratio =
mib_m->fddiMACFrameErrorRatio ;
sp_len = sizeof(struct smt_p_208d) ;
goto sp_done ;
}
case SMT_P208E : /* not copied condition */
{
struct smt_p_208e *sp ;
sp = (struct smt_p_208e *) to ;
sp->p208e_flag =
mib_m->fddiMACNotCopiedFlag ;
sp->p208e_not_copied =
mib_m->fddiMACNotCopied_Ct ;
sp->p208e_copied =
mib_m->fddiMACCopied_Ct ;
sp->p208e_not_copied_ratio =
mib_m->fddiMACNotCopiedRatio ;
sp_len = sizeof(struct smt_p_208e) ;
goto sp_done ;
}
case SMT_P208F : /* neighbor change event */
{
struct smt_p_208f *sp ;
sp = (struct smt_p_208f *) to ;
sp->p208f_multiple =
mib_m->fddiMACMultiple_N ;
sp->p208f_nacondition =
mib_m->fddiMACDuplicateAddressCond ;
sp->p208f_old_una =
mib_m->fddiMACOldUpstreamNbr ;
sp->p208f_new_una =
mib_m->fddiMACUpstreamNbr ;
sp->p208f_old_dna =
mib_m->fddiMACOldDownstreamNbr ;
sp->p208f_new_dna =
mib_m->fddiMACDownstreamNbr ;
sp->p208f_curren_path =
mib_m->fddiMACCurrentPath ;
sp->p208f_smt_address =
mib_m->fddiMACSMTAddress ;
sp_len = sizeof(struct smt_p_208f) ;
goto sp_done ;
}
case SMT_P2090 :
{
struct smt_p_2090 *sp ;
sp = (struct smt_p_2090 *) to ;
sp->p2090_multiple =
mib_m->fddiMACMultiple_P ;
sp->p2090_availablepaths =
mib_m->fddiMACAvailablePaths ;
sp->p2090_currentpath =
mib_m->fddiMACCurrentPath ;
sp->p2090_requestedpaths =
mib_m->fddiMACRequestedPaths ;
sp_len = sizeof(struct smt_p_2090) ;
goto sp_done ;
}
case SMT_P4050 :
{
struct smt_p_4050 *sp ;
sp = (struct smt_p_4050 *) to ;
sp->p4050_flag =
mib_p->fddiPORTLerFlag ;
sp->p4050_pad = 0 ;
sp->p4050_cutoff =
mib_p->fddiPORTLer_Cutoff ;
sp->p4050_alarm =
mib_p->fddiPORTLer_Alarm ;
sp->p4050_estimate =
mib_p->fddiPORTLer_Estimate ;
sp->p4050_reject_ct =
mib_p->fddiPORTLem_Reject_Ct ;
sp->p4050_ct =
mib_p->fddiPORTLem_Ct ;
sp_len = sizeof(struct smt_p_4050) ;
goto sp_done ;
}
case SMT_P4051 :
{
struct smt_p_4051 *sp ;
sp = (struct smt_p_4051 *) to ;
sp->p4051_multiple =
mib_p->fddiPORTMultiple_U ;
sp->p4051_porttype =
mib_p->fddiPORTMy_Type ;
sp->p4051_connectstate =
mib_p->fddiPORTConnectState ;
sp->p4051_pc_neighbor =
mib_p->fddiPORTNeighborType ;
sp->p4051_pc_withhold =
mib_p->fddiPORTPC_Withhold ;
sp_len = sizeof(struct smt_p_4051) ;
goto sp_done ;
}
case SMT_P4052 :
{
struct smt_p_4052 *sp ;
sp = (struct smt_p_4052 *) to ;
sp->p4052_flag =
mib_p->fddiPORTEB_Condition ;
sp->p4052_eberrorcount =
mib_p->fddiPORTEBError_Ct ;
sp_len = sizeof(struct smt_p_4052) ;
goto sp_done ;
}
case SMT_P4053 :
{
struct smt_p_4053 *sp ;
sp = (struct smt_p_4053 *) to ;
sp->p4053_multiple =
mib_p->fddiPORTMultiple_P ;
sp->p4053_availablepaths =
mib_p->fddiPORTAvailablePaths ;
sp->p4053_currentpath =
mib_p->fddiPORTCurrentPath ;
memcpy( (char *) &sp->p4053_requestedpaths,
(char *) mib_p->fddiPORTRequestedPaths,4) ;
sp->p4053_mytype =
mib_p->fddiPORTMy_Type ;
sp->p4053_neighbortype =
mib_p->fddiPORTNeighborType ;
sp_len = sizeof(struct smt_p_4053) ;
goto sp_done ;
}
default :
break ;
}
/*
* in table ?
*/
if (!pt) {
pcon->pc_err = (para & 0xff00) ? SMT_RDF_NOPARAM :
SMT_RDF_ILLEGAL ;
return ;
}
/*
* check access rights
*/
switch (pt->p_access) {
case AC_G :
case AC_GR :
break ;
default :
pcon->pc_err = SMT_RDF_ILLEGAL ;
return ;
}
from = mib_addr + pt->p_offset ;
if (!swap)
swap = pt->p_swap ; /* pointer to swap string */
/*
* copy values
*/
while ((c = *swap++)) {
switch(c) {
case 'b' :
case 'w' :
case 'l' :
break ;
case 'S' :
case 'E' :
case 'R' :
case 'r' :
if (len < 4)
goto len_error ;
to[0] = 0 ;
to[1] = 0 ;
#ifdef LITTLE_ENDIAN
if (c == 'r') {
to[2] = *from++ ;
to[3] = *from++ ;
}
else {
to[3] = *from++ ;
to[2] = *from++ ;
}
#else
to[2] = *from++ ;
to[3] = *from++ ;
#endif
to += 4 ;
len -= 4 ;
break ;
case 'I' : /* for SET of port indexes */
if (len < 2)
goto len_error ;
#ifdef LITTLE_ENDIAN
to[1] = *from++ ;
to[0] = *from++ ;
#else
to[0] = *from++ ;
to[1] = *from++ ;
#endif
to += 2 ;
len -= 2 ;
break ;
case 'F' :
case 'B' :
if (len < 4)
goto len_error ;
len -= 4 ;
to[0] = 0 ;
to[1] = 0 ;
to[2] = 0 ;
to[3] = *from++ ;
to += 4 ;
break ;
case 'C' :
case 'T' :
case 'L' :
if (len < 4)
goto len_error ;
#ifdef LITTLE_ENDIAN
to[3] = *from++ ;
to[2] = *from++ ;
to[1] = *from++ ;
to[0] = *from++ ;
#else
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
#endif
len -= 4 ;
to += 4 ;
break ;
case '2' : /* PortMacIndicated */
if (len < 4)
goto len_error ;
to[0] = 0 ;
to[1] = 0 ;
to[2] = *from++ ;
to[3] = *from++ ;
len -= 4 ;
to += 4 ;
break ;
case '4' :
if (len < 4)
goto len_error ;
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
len -= 4 ;
to += 4 ;
break ;
case 'A' :
if (len < 8)
goto len_error ;
to[0] = 0 ;
to[1] = 0 ;
memcpy((char *) to+2,(char *) from,6) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case '8' :
if (len < 8)
goto len_error ;
memcpy((char *) to,(char *) from,8) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case 'D' :
if (len < 32)
goto len_error ;
memcpy((char *) to,(char *) from,32) ;
to += 32 ;
from += 32 ;
len -= 32 ;
break ;
case 'P' : /* timestamp is NOT swapped */
if (len < 8)
goto len_error ;
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
to[4] = *from++ ;
to[5] = *from++ ;
to[6] = *from++ ;
to[7] = *from++ ;
to += 8 ;
len -= 8 ;
break ;
default :
SMT_PANIC(smc,SMT_E0119, SMT_E0119_MSG) ;
break ;
}
}
done:
/*
* make it even (in case of 'I' encoding)
* note: len is DECREMENTED
*/
if (len & 3) {
to[0] = 0 ;
to[1] = 0 ;
to += 4 - (len & 3 ) ;
len = len & ~ 3 ;
}
/* set type and length */
pa->p_type = para ;
pa->p_len = plen - len - PARA_LEN ;
/* return values */
pcon->pc_p = (void *) to ;
pcon->pc_len = len ;
return ;
sp_done:
len -= sp_len ;
to += sp_len ;
goto done ;
len_error:
/* parameter does not fit in frame */
pcon->pc_err = SMT_RDF_TOOLONG ;
return ;
wrong_error:
pcon->pc_err = SMT_RDF_LENGTH ;
}
/*
* set parameter
*/
static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
int local, int set)
{
#define IFSET(x) if (set) (x)
const struct s_p_tab *pt ;
int len ;
char *from ;
char *to ;
const char *swap ;
char c ;
char *mib_addr ;
struct fddi_mib *mib ;
struct fddi_mib_m *mib_m = NULL;
struct fddi_mib_a *mib_a = NULL;
struct fddi_mib_p *mib_p = NULL;
int mac ;
int path ;
int port ;
SK_LOC_DECL(u_char,byte_val) ;
SK_LOC_DECL(u_short,word_val) ;
SK_LOC_DECL(u_long,long_val) ;
mac = index - INDEX_MAC ;
path = index - INDEX_PATH ;
port = index - INDEX_PORT ;
len = pa->p_len ;
from = (char *) (pa + 1 ) ;
mib = &smc->mib ;
switch (pa->p_type & 0xf000) {
case 0x1000 :
default :
mib_addr = (char *) mib ;
break ;
case 0x2000 :
if (mac < 0 || mac >= NUMMACS) {
return SMT_RDF_NOPARAM;
}
mib_m = &smc->mib.m[mac] ;
mib_addr = (char *) mib_m ;
from += 4 ; /* skip index */
len -= 4 ;
break ;
case 0x3000 :
if (path < 0 || path >= NUMPATHS) {
return SMT_RDF_NOPARAM;
}
mib_a = &smc->mib.a[path] ;
mib_addr = (char *) mib_a ;
from += 4 ; /* skip index */
len -= 4 ;
break ;
case 0x4000 :
if (port < 0 || port >= smt_mib_phys(smc)) {
return SMT_RDF_NOPARAM;
}
mib_p = &smc->mib.p[port_to_mib(smc,port)] ;
mib_addr = (char *) mib_p ;
from += 4 ; /* skip index */
len -= 4 ;
break ;
}
switch (pa->p_type) {
case SMT_P10F0 :
case SMT_P10F1 :
#ifdef ESS
case SMT_P10F2 :
case SMT_P10F3 :
case SMT_P10F4 :
case SMT_P10F5 :
case SMT_P10F6 :
case SMT_P10F7 :
#endif
#ifdef SBA
case SMT_P10F8 :
case SMT_P10F9 :
#endif
case SMT_P20F1 :
if (!local)
return SMT_RDF_NOPARAM;
break ;
}
pt = smt_get_ptab(pa->p_type) ;
if (!pt)
return (pa->p_type & 0xff00) ? SMT_RDF_NOPARAM :
SMT_RDF_ILLEGAL;
switch (pt->p_access) {
case AC_GR :
case AC_S :
break ;
default :
return SMT_RDF_ILLEGAL;
}
to = mib_addr + pt->p_offset ;
swap = pt->p_swap ; /* pointer to swap string */
while (swap && (c = *swap++)) {
switch(c) {
case 'b' :
to = (char *) &byte_val ;
break ;
case 'w' :
to = (char *) &word_val ;
break ;
case 'l' :
to = (char *) &long_val ;
break ;
case 'S' :
case 'E' :
case 'R' :
case 'r' :
if (len < 4) {
goto len_error ;
}
if (from[0] | from[1])
goto val_error ;
#ifdef LITTLE_ENDIAN
if (c == 'r') {
to[0] = from[2] ;
to[1] = from[3] ;
}
else {
to[1] = from[2] ;
to[0] = from[3] ;
}
#else
to[0] = from[2] ;
to[1] = from[3] ;
#endif
from += 4 ;
to += 2 ;
len -= 4 ;
break ;
case 'F' :
case 'B' :
if (len < 4) {
goto len_error ;
}
if (from[0] | from[1] | from[2])
goto val_error ;
to[0] = from[3] ;
len -= 4 ;
from += 4 ;
to += 4 ;
break ;
case 'C' :
case 'T' :
case 'L' :
if (len < 4) {
goto len_error ;
}
#ifdef LITTLE_ENDIAN
to[3] = *from++ ;
to[2] = *from++ ;
to[1] = *from++ ;
to[0] = *from++ ;
#else
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
#endif
len -= 4 ;
to += 4 ;
break ;
case 'A' :
if (len < 8)
goto len_error ;
if (set)
memcpy(to,from+2,6) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case '4' :
if (len < 4)
goto len_error ;
if (set)
memcpy(to,from,4) ;
to += 4 ;
from += 4 ;
len -= 4 ;
break ;
case '8' :
if (len < 8)
goto len_error ;
if (set)
memcpy(to,from,8) ;
to += 8 ;
from += 8 ;
len -= 8 ;
break ;
case 'D' :
if (len < 32)
goto len_error ;
if (set)
memcpy(to,from,32) ;
to += 32 ;
from += 32 ;
len -= 32 ;
break ;
case 'P' : /* timestamp is NOT swapped */
if (set) {
to[0] = *from++ ;
to[1] = *from++ ;
to[2] = *from++ ;
to[3] = *from++ ;
to[4] = *from++ ;
to[5] = *from++ ;
to[6] = *from++ ;
to[7] = *from++ ;
}
to += 8 ;
len -= 8 ;
break ;
default :
SMT_PANIC(smc,SMT_E0120, SMT_E0120_MSG) ;
return SMT_RDF_ILLEGAL;
}
}
/*
* actions and internal updates
*/
switch (pa->p_type) {
case SMT_P101A: /* fddiSMTConfigPolicy */
if (word_val & ~1)
goto val_error ;
IFSET(mib->fddiSMTConfigPolicy = word_val) ;
break ;
case SMT_P101B : /* fddiSMTConnectionPolicy */
if (!(word_val & POLICY_MM))
goto val_error ;
IFSET(mib->fddiSMTConnectionPolicy = word_val) ;
break ;
case SMT_P101D : /* fddiSMTTT_Notify */
if (word_val < 2 || word_val > 30)
goto val_error ;
IFSET(mib->fddiSMTTT_Notify = word_val) ;
break ;
case SMT_P101E : /* fddiSMTStatRptPolicy */
if (byte_val & ~1)
goto val_error ;
IFSET(mib->fddiSMTStatRptPolicy = byte_val) ;
break ;
case SMT_P101F : /* fddiSMTTrace_MaxExpiration */
/*
* note: lower limit trace_max = 6.001773... s
* NO upper limit
*/
if (long_val < (long)0x478bf51L)
goto val_error ;
IFSET(mib->fddiSMTTrace_MaxExpiration = long_val) ;
break ;
#ifdef ESS
case SMT_P10F2 : /* fddiESSPayload */
if (long_val > 1562)
goto val_error ;
if (set && smc->mib.fddiESSPayload != long_val) {
smc->ess.raf_act_timer_poll = TRUE ;
smc->mib.fddiESSPayload = long_val ;
}
break ;
case SMT_P10F3 : /* fddiESSOverhead */
if (long_val < 50 || long_val > 5000)
goto val_error ;
if (set && smc->mib.fddiESSPayload &&
smc->mib.fddiESSOverhead != long_val) {
smc->ess.raf_act_timer_poll = TRUE ;
smc->mib.fddiESSOverhead = long_val ;
}
break ;
case SMT_P10F4 : /* fddiESSMaxTNeg */
if (long_val > -MS2BCLK(5) || long_val < -MS2BCLK(165))
goto val_error ;
IFSET(mib->fddiESSMaxTNeg = long_val) ;
break ;
case SMT_P10F5 : /* fddiESSMinSegmentSize */
if (long_val < 1 || long_val > 4478)
goto val_error ;
IFSET(mib->fddiESSMinSegmentSize = long_val) ;
break ;
case SMT_P10F6 : /* fddiESSCategory */
if ((long_val & 0xffff) != 1)
goto val_error ;
IFSET(mib->fddiESSCategory = long_val) ;
break ;
case SMT_P10F7 : /* fddiESSSyncTxMode */
if (word_val > 1)
goto val_error ;
IFSET(mib->fddiESSSynchTxMode = word_val) ;
break ;
#endif
#ifdef SBA
case SMT_P10F8 : /* fddiSBACommand */
if (byte_val != SB_STOP && byte_val != SB_START)
goto val_error ;
IFSET(mib->fddiSBACommand = byte_val) ;
break ;
case SMT_P10F9 : /* fddiSBAAvailable */
if (byte_val > 100)
goto val_error ;
IFSET(mib->fddiSBAAvailable = byte_val) ;
break ;
#endif
case SMT_P2020 : /* fddiMACRequestedPaths */
if ((word_val & (MIB_P_PATH_PRIM_PREFER |
MIB_P_PATH_PRIM_ALTER)) == 0 )
goto val_error ;
IFSET(mib_m->fddiMACRequestedPaths = word_val) ;
break ;
case SMT_P205F : /* fddiMACFrameErrorThreshold */
/* 0 .. ffff acceptable */
IFSET(mib_m->fddiMACFrameErrorThreshold = word_val) ;
break ;
case SMT_P2067 : /* fddiMACNotCopiedThreshold */
/* 0 .. ffff acceptable */
IFSET(mib_m->fddiMACNotCopiedThreshold = word_val) ;
break ;
case SMT_P2076: /* fddiMACMA_UnitdataEnable */
if (byte_val & ~1)
goto val_error ;
if (set) {
mib_m->fddiMACMA_UnitdataEnable = byte_val ;
queue_event(smc,EVENT_RMT,RM_ENABLE_FLAG) ;
}
break ;
case SMT_P20F1 : /* fddiMACT_Min */
IFSET(mib_m->fddiMACT_Min = long_val) ;
break ;
case SMT_P320F :
if (long_val > 1562)
goto val_error ;
IFSET(mib_a->fddiPATHSbaPayload = long_val) ;
#ifdef ESS
if (set)
ess_para_change(smc) ;
#endif
break ;
case SMT_P3210 :
if (long_val > 5000)
goto val_error ;
if (long_val != 0 && mib_a->fddiPATHSbaPayload == 0)
goto val_error ;
IFSET(mib_a->fddiPATHSbaOverhead = long_val) ;
#ifdef ESS
if (set)
ess_para_change(smc) ;
#endif
break ;
case SMT_P3213: /* fddiPATHT_Rmode */
/* no limit :
* 0 .. 343.597 => 0 .. 2e32 * 80nS
*/
if (set) {
mib_a->fddiPATHT_Rmode = long_val ;
rtm_set_timer(smc) ;
}
break ;
case SMT_P3214 : /* fddiPATHSbaAvailable */
if (long_val > 0x00BEBC20L)
goto val_error ;
#ifdef SBA
if (set && mib->fddiSBACommand == SB_STOP)
goto val_error ;
#endif
IFSET(mib_a->fddiPATHSbaAvailable = long_val) ;
break ;
case SMT_P3215 : /* fddiPATHTVXLowerBound */
IFSET(mib_a->fddiPATHTVXLowerBound = long_val) ;
goto change_mac_para ;
case SMT_P3216 : /* fddiPATHT_MaxLowerBound */
IFSET(mib_a->fddiPATHT_MaxLowerBound = long_val) ;
goto change_mac_para ;
case SMT_P3217 : /* fddiPATHMaxT_Req */
IFSET(mib_a->fddiPATHMaxT_Req = long_val) ;
change_mac_para:
if (set && smt_set_mac_opvalues(smc)) {
RS_SET(smc,RS_EVENT) ;
smc->sm.please_reconnect = 1 ;
queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
}
break ;
case SMT_P400E : /* fddiPORTConnectionPolicies */
if (byte_val > 1)
goto val_error ;
IFSET(mib_p->fddiPORTConnectionPolicies = byte_val) ;
break ;
case SMT_P4011 : /* fddiPORTRequestedPaths */
/* all 3*8 bits allowed */
IFSET(memcpy((char *)mib_p->fddiPORTRequestedPaths,
(char *)&long_val,4)) ;
break ;
case SMT_P401F: /* fddiPORTMaint_LS */
if (word_val > 4)
goto val_error ;
IFSET(mib_p->fddiPORTMaint_LS = word_val) ;
break ;
case SMT_P403A : /* fddiPORTLer_Cutoff */
if (byte_val < 4 || byte_val > 15)
goto val_error ;
IFSET(mib_p->fddiPORTLer_Cutoff = byte_val) ;
break ;
case SMT_P403B : /* fddiPORTLer_Alarm */
if (byte_val < 4 || byte_val > 15)
goto val_error ;
IFSET(mib_p->fddiPORTLer_Alarm = byte_val) ;
break ;
/*
* Actions
*/
case SMT_P103C : /* fddiSMTStationAction */
if (smt_action(smc,SMT_STATION_ACTION, (int) word_val, 0))
goto val_error ;
break ;
case SMT_P4046: /* fddiPORTAction */
if (smt_action(smc,SMT_PORT_ACTION, (int) word_val,
port_to_mib(smc,port)))
goto val_error ;
break ;
default :
break ;
}
return 0;
val_error:
/* parameter value in frame is out of range */
return SMT_RDF_RANGE;
len_error:
/* parameter value in frame is too short */
return SMT_RDF_LENGTH;
#if 0
no_author_error:
/* parameter not setable, because the SBA is not active
* Please note: we give the return code 'not authorizeed
* because SBA denied is not a valid return code in the
* PMF protocol.
*/
return SMT_RDF_AUTHOR;
#endif
}
static const struct s_p_tab *smt_get_ptab(u_short para)
{
const struct s_p_tab *pt ;
for (pt = p_tab ; pt->p_num && pt->p_num != para ; pt++)
;
return pt->p_num ? pt : NULL;
}
static int smt_mib_phys(struct s_smc *smc)
{
#ifdef CONCENTRATOR
SK_UNUSED(smc) ;
return NUMPHYS;
#else
if (smc->s.sas == SMT_SAS)
return 1;
return NUMPHYS;
#endif
}
static int port_to_mib(struct s_smc *smc, int p)
{
#ifdef CONCENTRATOR
SK_UNUSED(smc) ;
return p;
#else
if (smc->s.sas == SMT_SAS)
return PS;
return p;
#endif
}
#ifdef DEBUG
#ifndef BOOT
void dump_smt(struct s_smc *smc, struct smt_header *sm, char *text)
{
int len ;
struct smt_para *pa ;
char *c ;
int n ;
int nn ;
#ifdef LITTLE_ENDIAN
int smtlen ;
#endif
SK_UNUSED(smc) ;
#ifdef DEBUG_BRD
if (smc->debug.d_smtf < 2)
#else
if (debug.d_smtf < 2)
#endif
return ;
#ifdef LITTLE_ENDIAN
smtlen = sm->smt_len + sizeof(struct smt_header) ;
#endif
printf("SMT Frame [%s]:\nDA ",text) ;
dump_hex((char *) &sm->smt_dest,6) ;
printf("\tSA ") ;
dump_hex((char *) &sm->smt_source,6) ;
printf(" Class %x Type %x Version %x\n",
sm->smt_class,sm->smt_type,sm->smt_version) ;
printf("TID %lx\t\tSID ",sm->smt_tid) ;
dump_hex((char *) &sm->smt_sid,8) ;
printf(" LEN %x\n",sm->smt_len) ;
len = sm->smt_len ;
pa = (struct smt_para *) (sm + 1) ;
while (len > 0 ) {
int plen ;
#ifdef UNIX
printf("TYPE %x LEN %x VALUE\t",pa->p_type,pa->p_len) ;
#else
printf("TYPE %04x LEN %2x VALUE\t",pa->p_type,pa->p_len) ;
#endif
n = pa->p_len ;
if ( (n < 0 ) || (n > (int)(len - PARA_LEN))) {
n = len - PARA_LEN ;
printf(" BAD LENGTH\n") ;
break ;
}
#ifdef LITTLE_ENDIAN
smt_swap_para(sm,smtlen,0) ;
#endif
if (n < 24) {
dump_hex((char *)(pa+1),(int) n) ;
printf("\n") ;
}
else {
int first = 0 ;
c = (char *)(pa+1) ;
dump_hex(c,16) ;
printf("\n") ;
n -= 16 ;
c += 16 ;
while (n > 0) {
nn = (n > 16) ? 16 : n ;
if (n > 64) {
if (first == 0)
printf("\t\t\t...\n") ;
first = 1 ;
}
else {
printf("\t\t\t") ;
dump_hex(c,nn) ;
printf("\n") ;
}
n -= nn ;
c += 16 ;
}
}
#ifdef LITTLE_ENDIAN
smt_swap_para(sm,smtlen,1) ;
#endif
plen = (pa->p_len + PARA_LEN + 3) & ~3 ;
len -= plen ;
pa = (struct smt_para *)((char *)pa + plen) ;
}
printf("-------------------------------------------------\n\n") ;
}
void dump_hex(char *p, int len)
{
int n = 0 ;
while (len--) {
n++ ;
#ifdef UNIX
printf("%x%s",*p++ & 0xff,len ? ( (n & 7) ? " " : "-") : "") ;
#else
printf("%02x%s",*p++ & 0xff,len ? ( (n & 7) ? " " : "-") : "") ;
#endif
}
}
#endif /* no BOOT */
#endif /* DEBUG */
#endif /* no SLIM_SMT */
| gpl-2.0 |
devttys1/linux-fslc | drivers/ide/ht6560b.c | 4842 | 10680 | /*
* Copyright (C) 1995-2000 Linus Torvalds & author (see below)
*/
/*
* HT-6560B EIDE-controller support
* To activate controller support use kernel parameter "ide0=ht6560b".
* Use hdparm utility to enable PIO mode support.
*
* Author: Mikko Ala-Fossi <maf@iki.fi>
* Jan Evert van Grootheest <j.e.van.grootheest@caiway.nl>
*
*/
#define DRV_NAME "ht6560b"
#define HT6560B_VERSION "v0.08"
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <asm/io.h>
/* #define DEBUG */ /* remove comments for DEBUG messages */
/*
* The special i/o-port that HT-6560B uses to configuration:
* bit0 (0x01): "1" selects secondary interface
* bit2 (0x04): "1" enables FIFO function
* bit5 (0x20): "1" enables prefetched data read function (???)
*
* The special i/o-port that HT-6560A uses to configuration:
* bit0 (0x01): "1" selects secondary interface
* bit1 (0x02): "1" enables prefetched data read function
* bit2 (0x04): "0" enables multi-master system (?)
* bit3 (0x08): "1" 3 cycle time, "0" 2 cycle time (?)
*/
#define HT_CONFIG_PORT 0x3e6
static inline u8 HT_CONFIG(ide_drive_t *drive)
{
return ((unsigned long)ide_get_drivedata(drive) & 0xff00) >> 8;
}
/*
* FIFO + PREFETCH (both a/b-model)
*/
#define HT_CONFIG_DEFAULT 0x1c /* no prefetch */
/* #define HT_CONFIG_DEFAULT 0x3c */ /* with prefetch */
#define HT_SECONDARY_IF 0x01
#define HT_PREFETCH_MODE 0x20
/*
* ht6560b Timing values:
*
* I reviewed some assembler source listings of htide drivers and found
* out how they setup those cycle time interfacing values, as they at Holtek
* call them. IDESETUP.COM that is supplied with the drivers figures out
* optimal values and fetches those values to drivers. I found out that
* they use Select register to fetch timings to the ide board right after
* interface switching. After that it was quite easy to add code to
* ht6560b.c.
*
* IDESETUP.COM gave me values 0x24, 0x45, 0xaa, 0xff that worked fine
* for hda and hdc. But hdb needed higher values to work, so I guess
* that sometimes it is necessary to give higher value than IDESETUP
* gives. [see cmd640.c for an extreme example of this. -ml]
*
* Perhaps I should explain something about these timing values:
* The higher nibble of value is the Recovery Time (rt) and the lower nibble
* of the value is the Active Time (at). Minimum value 2 is the fastest and
* the maximum value 15 is the slowest. Default values should be 15 for both.
* So 0x24 means 2 for rt and 4 for at. Each of the drives should have
* both values, and IDESETUP gives automatically rt=15 st=15 for CDROMs or
* similar. If value is too small there will be all sorts of failures.
*
* Timing byte consists of
* High nibble: Recovery Cycle Time (rt)
* The valid values range from 2 to 15. The default is 15.
*
* Low nibble: Active Cycle Time (at)
* The valid values range from 2 to 15. The default is 15.
*
* You can obtain optimized timing values by running Holtek IDESETUP.COM
* for DOS. DOS drivers get their timing values from command line, where
* the first value is the Recovery Time and the second value is the
* Active Time for each drive. Smaller value gives higher speed.
* In case of failures you should probably fall back to a higher value.
*/
static inline u8 HT_TIMING(ide_drive_t *drive)
{
return (unsigned long)ide_get_drivedata(drive) & 0x00ff;
}
#define HT_TIMING_DEFAULT 0xff
/*
* This routine handles interface switching for the peculiar hardware design
* on the F.G.I./Holtek HT-6560B VLB IDE interface.
* The HT-6560B can only enable one IDE port at a time, and requires a
* silly sequence (below) whenever we switch between primary and secondary.
*/
/*
* This routine is invoked from ide.c to prepare for access to a given drive.
*/
static void ht6560b_dev_select(ide_drive_t *drive)
{
ide_hwif_t *hwif = drive->hwif;
unsigned long flags;
static u8 current_select = 0;
static u8 current_timing = 0;
u8 select, timing;
local_irq_save(flags);
select = HT_CONFIG(drive);
timing = HT_TIMING(drive);
/*
* Need to enforce prefetch sometimes because otherwise
* it'll hang (hard).
*/
if (drive->media != ide_disk ||
(drive->dev_flags & IDE_DFLAG_PRESENT) == 0)
select |= HT_PREFETCH_MODE;
if (select != current_select || timing != current_timing) {
current_select = select;
current_timing = timing;
(void)inb(HT_CONFIG_PORT);
(void)inb(HT_CONFIG_PORT);
(void)inb(HT_CONFIG_PORT);
(void)inb(HT_CONFIG_PORT);
outb(select, HT_CONFIG_PORT);
/*
* Set timing for this drive:
*/
outb(timing, hwif->io_ports.device_addr);
(void)inb(hwif->io_ports.status_addr);
#ifdef DEBUG
printk("ht6560b: %s: select=%#x timing=%#x\n",
drive->name, select, timing);
#endif
}
local_irq_restore(flags);
outb(drive->select | ATA_DEVICE_OBS, hwif->io_ports.device_addr);
}
/*
* Autodetection and initialization of ht6560b
*/
static int __init try_to_init_ht6560b(void)
{
u8 orig_value;
int i;
/* Autodetect ht6560b */
if ((orig_value = inb(HT_CONFIG_PORT)) == 0xff)
return 0;
for (i=3;i>0;i--) {
outb(0x00, HT_CONFIG_PORT);
if (!( (~inb(HT_CONFIG_PORT)) & 0x3f )) {
outb(orig_value, HT_CONFIG_PORT);
return 0;
}
}
outb(0x00, HT_CONFIG_PORT);
if ((~inb(HT_CONFIG_PORT))& 0x3f) {
outb(orig_value, HT_CONFIG_PORT);
return 0;
}
/*
* Ht6560b autodetected
*/
outb(HT_CONFIG_DEFAULT, HT_CONFIG_PORT);
outb(HT_TIMING_DEFAULT, 0x1f6); /* Select register */
(void)inb(0x1f7); /* Status register */
printk("ht6560b " HT6560B_VERSION
": chipset detected and initialized"
#ifdef DEBUG
" with debug enabled"
#endif
"\n"
);
return 1;
}
static u8 ht_pio2timings(ide_drive_t *drive, const u8 pio)
{
int active_time, recovery_time;
int active_cycles, recovery_cycles;
int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
if (pio) {
unsigned int cycle_time;
struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
cycle_time = ide_pio_cycle_time(drive, pio);
/*
* Just like opti621.c we try to calculate the
* actual cycle time for recovery and activity
* according system bus speed.
*/
active_time = t->active;
recovery_time = cycle_time - active_time - t->setup;
/*
* Cycle times should be Vesa bus cycles
*/
active_cycles = (active_time * bus_speed + 999) / 1000;
recovery_cycles = (recovery_time * bus_speed + 999) / 1000;
/*
* Upper and lower limits
*/
if (active_cycles < 2) active_cycles = 2;
if (recovery_cycles < 2) recovery_cycles = 2;
if (active_cycles > 15) active_cycles = 15;
if (recovery_cycles > 15) recovery_cycles = 0; /* 0==16 */
#ifdef DEBUG
printk("ht6560b: drive %s setting pio=%d recovery=%d (%dns) active=%d (%dns)\n", drive->name, pio, recovery_cycles, recovery_time, active_cycles, active_time);
#endif
return (u8)((recovery_cycles << 4) | active_cycles);
} else {
#ifdef DEBUG
printk("ht6560b: drive %s setting pio=0\n", drive->name);
#endif
return HT_TIMING_DEFAULT; /* default setting */
}
}
static DEFINE_SPINLOCK(ht6560b_lock);
/*
* Enable/Disable so called prefetch mode
*/
static void ht_set_prefetch(ide_drive_t *drive, u8 state)
{
unsigned long flags, config;
int t = HT_PREFETCH_MODE << 8;
spin_lock_irqsave(&ht6560b_lock, flags);
config = (unsigned long)ide_get_drivedata(drive);
/*
* Prefetch mode and unmask irq seems to conflict
*/
if (state) {
config |= t; /* enable prefetch mode */
drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
drive->dev_flags &= ~IDE_DFLAG_UNMASK;
} else {
config &= ~t; /* disable prefetch mode */
drive->dev_flags &= ~IDE_DFLAG_NO_UNMASK;
}
ide_set_drivedata(drive, (void *)config);
spin_unlock_irqrestore(&ht6560b_lock, flags);
#ifdef DEBUG
printk("ht6560b: drive %s prefetch mode %sabled\n", drive->name, (state ? "en" : "dis"));
#endif
}
static void ht6560b_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
unsigned long flags, config;
const u8 pio = drive->pio_mode - XFER_PIO_0;
u8 timing;
switch (pio) {
case 8: /* set prefetch off */
case 9: /* set prefetch on */
ht_set_prefetch(drive, pio & 1);
return;
}
timing = ht_pio2timings(drive, pio);
spin_lock_irqsave(&ht6560b_lock, flags);
config = (unsigned long)ide_get_drivedata(drive);
config &= 0xff00;
config |= timing;
ide_set_drivedata(drive, (void *)config);
spin_unlock_irqrestore(&ht6560b_lock, flags);
#ifdef DEBUG
printk("ht6560b: drive %s tuned to pio mode %#x timing=%#x\n", drive->name, pio, timing);
#endif
}
static void __init ht6560b_init_dev(ide_drive_t *drive)
{
ide_hwif_t *hwif = drive->hwif;
/* Setting default configurations for drives. */
int t = (HT_CONFIG_DEFAULT << 8) | HT_TIMING_DEFAULT;
if (hwif->channel)
t |= (HT_SECONDARY_IF << 8);
ide_set_drivedata(drive, (void *)t);
}
static bool probe_ht6560b;
module_param_named(probe, probe_ht6560b, bool, 0);
MODULE_PARM_DESC(probe, "probe for HT6560B chipset");
static const struct ide_tp_ops ht6560b_tp_ops = {
.exec_command = ide_exec_command,
.read_status = ide_read_status,
.read_altstatus = ide_read_altstatus,
.write_devctl = ide_write_devctl,
.dev_select = ht6560b_dev_select,
.tf_load = ide_tf_load,
.tf_read = ide_tf_read,
.input_data = ide_input_data,
.output_data = ide_output_data,
};
static const struct ide_port_ops ht6560b_port_ops = {
.init_dev = ht6560b_init_dev,
.set_pio_mode = ht6560b_set_pio_mode,
};
static const struct ide_port_info ht6560b_port_info __initconst = {
.name = DRV_NAME,
.chipset = ide_ht6560b,
.tp_ops = &ht6560b_tp_ops,
.port_ops = &ht6560b_port_ops,
.host_flags = IDE_HFLAG_SERIALIZE | /* is this needed? */
IDE_HFLAG_NO_DMA |
IDE_HFLAG_ABUSE_PREFETCH,
.pio_mask = ATA_PIO4,
};
static int __init ht6560b_init(void)
{
if (probe_ht6560b == 0)
return -ENODEV;
if (!request_region(HT_CONFIG_PORT, 1, DRV_NAME)) {
printk(KERN_NOTICE "%s: HT_CONFIG_PORT not found\n",
__func__);
return -ENODEV;
}
if (!try_to_init_ht6560b()) {
printk(KERN_NOTICE "%s: HBA not found\n", __func__);
goto release_region;
}
return ide_legacy_device_add(&ht6560b_port_info, 0);
release_region:
release_region(HT_CONFIG_PORT, 1);
return -ENODEV;
}
module_init(ht6560b_init);
MODULE_AUTHOR("See Local File");
MODULE_DESCRIPTION("HT-6560B EIDE-controller support");
MODULE_LICENSE("GPL");
| gpl-2.0 |
anders3408/kernel_oppo_find5-old | arch/arm/mach-s5pc100/common.c | 4842 | 5229 | /*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Common Codes for S5PC100
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <asm/irq.h>
#include <asm/proc-fns.h>
#include <asm/system_misc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/map.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/adc-core.h>
#include <plat/ata-core.h>
#include <plat/fb-core.h>
#include <plat/iic-core.h>
#include <plat/onenand-core.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>
#include "common.h"
static const char name_s5pc100[] = "S5PC100";
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = S5PC100_CPU_ID,
.idmask = S5PC100_CPU_MASK,
.map_io = s5pc100_map_io,
.init_clocks = s5pc100_init_clocks,
.init_uarts = s5pc100_init_uarts,
.init = s5pc100_init,
.name = name_s5pc100,
},
};
/* Initial IO mappings */
static struct map_desc s5pc100_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_CHIPID,
.pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_TIMER,
.pfn = __phys_to_pfn(S5PC100_PA_TIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_WATCHDOG,
.pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(S5PC100_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO,
.pfn = __phys_to_pfn(S5PC100_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S5PC100_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S5PC100_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC2,
.pfn = __phys_to_pfn(S5PC100_PA_VIC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC100_VA_OTHERS,
.pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
.length = SZ_4K,
.type = MT_DEVICE,
}
};
/*
* s5pc100_map_io
*
* register the standard CPU IO areas
*/
void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
{
/* initialize the io descriptors we need for initialization */
iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
if (mach_desc)
iotable_init(mach_desc, size);
/* detect cpu id and rev. */
s5p_init_cpu(S5P_VA_CHIPID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}
void __init s5pc100_map_io(void)
{
/* initialise device information early */
s5pc100_default_sdhci0();
s5pc100_default_sdhci1();
s5pc100_default_sdhci2();
s3c_adc_setname("s3c64xx-adc");
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_onenand_setname("s5pc100-onenand");
s3c_fb_setname("s5pc100-fb");
s3c_cfcon_setname("s5pc100-pata");
}
void __init s5pc100_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5pc100_register_clocks();
s5pc100_setup_clocks();
}
void __init s5pc100_init_irq(void)
{
u32 vic[] = {~0, ~0, ~0};
/* VIC0, VIC1, and VIC2 are fully populated. */
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
static struct bus_type s5pc100_subsys = {
.name = "s5pc100-core",
.dev_name = "s5pc100-core",
};
static struct device s5pc100_dev = {
.bus = &s5pc100_subsys,
};
static int __init s5pc100_core_init(void)
{
return subsys_system_register(&s5pc100_subsys, NULL);
}
core_initcall(s5pc100_core_init);
int __init s5pc100_init(void)
{
printk(KERN_INFO "S5PC100: Initializing architecture\n");
return device_register(&s5pc100_dev);
}
/* uart registration process */
void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}
void s5pc100_restart(char mode, const char *cmd)
{
if (mode != 's')
arch_wdt_reset();
soft_restart(0);
}
| gpl-2.0 |
vwmofo/android_kernel_htc_msm8960 | drivers/mtd/mtdsuper.c | 5098 | 5583 | /* MTD-based superblock management
*
* Copyright © 2001-2007 Red Hat, Inc. All Rights Reserved.
* Copyright © 2001-2010 David Woodhouse <dwmw2@infradead.org>
*
* Written by: David Howells <dhowells@redhat.com>
* David Woodhouse <dwmw2@infradead.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/mtd/super.h>
#include <linux/namei.h>
#include <linux/export.h>
#include <linux/ctype.h>
#include <linux/slab.h>
/*
* compare superblocks to see if they're equivalent
* - they are if the underlying MTD device is the same
*/
static int get_sb_mtd_compare(struct super_block *sb, void *_mtd)
{
struct mtd_info *mtd = _mtd;
if (sb->s_mtd == mtd) {
pr_debug("MTDSB: Match on device %d (\"%s\")\n",
mtd->index, mtd->name);
return 1;
}
pr_debug("MTDSB: No match, device %d (\"%s\"), device %d (\"%s\")\n",
sb->s_mtd->index, sb->s_mtd->name, mtd->index, mtd->name);
return 0;
}
/*
* mark the superblock by the MTD device it is using
* - set the device number to be the correct MTD block device for pesuperstence
* of NFS exports
*/
static int get_sb_mtd_set(struct super_block *sb, void *_mtd)
{
struct mtd_info *mtd = _mtd;
sb->s_mtd = mtd;
sb->s_dev = MKDEV(MTD_BLOCK_MAJOR, mtd->index);
sb->s_bdi = mtd->backing_dev_info;
return 0;
}
/*
* get a superblock on an MTD-backed filesystem
*/
static struct dentry *mount_mtd_aux(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
struct mtd_info *mtd,
int (*fill_super)(struct super_block *, void *, int))
{
struct super_block *sb;
int ret;
sb = sget(fs_type, get_sb_mtd_compare, get_sb_mtd_set, mtd);
if (IS_ERR(sb))
goto out_error;
if (sb->s_root)
goto already_mounted;
/* fresh new superblock */
pr_debug("MTDSB: New superblock for device %d (\"%s\")\n",
mtd->index, mtd->name);
sb->s_flags = flags;
ret = fill_super(sb, data, flags & MS_SILENT ? 1 : 0);
if (ret < 0) {
deactivate_locked_super(sb);
return ERR_PTR(ret);
}
/* go */
sb->s_flags |= MS_ACTIVE;
return dget(sb->s_root);
/* new mountpoint for an already mounted superblock */
already_mounted:
pr_debug("MTDSB: Device %d (\"%s\") is already mounted\n",
mtd->index, mtd->name);
put_mtd_device(mtd);
return dget(sb->s_root);
out_error:
put_mtd_device(mtd);
return ERR_CAST(sb);
}
/*
* get a superblock on an MTD-backed filesystem by MTD device number
*/
static struct dentry *mount_mtd_nr(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data, int mtdnr,
int (*fill_super)(struct super_block *, void *, int))
{
struct mtd_info *mtd;
mtd = get_mtd_device(NULL, mtdnr);
if (IS_ERR(mtd)) {
pr_debug("MTDSB: Device #%u doesn't appear to exist\n", mtdnr);
return ERR_CAST(mtd);
}
return mount_mtd_aux(fs_type, flags, dev_name, data, mtd, fill_super);
}
/*
* set up an MTD-based superblock
*/
struct dentry *mount_mtd(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
int (*fill_super)(struct super_block *, void *, int))
{
#ifdef CONFIG_BLOCK
struct block_device *bdev;
int ret, major;
#endif
int mtdnr;
if (!dev_name)
return ERR_PTR(-EINVAL);
pr_debug("MTDSB: dev_name \"%s\"\n", dev_name);
/* the preferred way of mounting in future; especially when
* CONFIG_BLOCK=n - we specify the underlying MTD device by number or
* by name, so that we don't require block device support to be present
* in the kernel. */
if (dev_name[0] == 'm' && dev_name[1] == 't' && dev_name[2] == 'd') {
if (dev_name[3] == ':') {
struct mtd_info *mtd;
/* mount by MTD device name */
pr_debug("MTDSB: mtd:%%s, name \"%s\"\n",
dev_name + 4);
mtd = get_mtd_device_nm(dev_name + 4);
if (!IS_ERR(mtd))
return mount_mtd_aux(
fs_type, flags,
dev_name, data, mtd,
fill_super);
printk(KERN_NOTICE "MTD:"
" MTD device with name \"%s\" not found.\n",
dev_name + 4);
} else if (isdigit(dev_name[3])) {
/* mount by MTD device number name */
char *endptr;
mtdnr = simple_strtoul(dev_name + 3, &endptr, 0);
if (!*endptr) {
/* It was a valid number */
pr_debug("MTDSB: mtd%%d, mtdnr %d\n",
mtdnr);
return mount_mtd_nr(fs_type, flags,
dev_name, data,
mtdnr, fill_super);
}
}
}
#ifdef CONFIG_BLOCK
/* try the old way - the hack where we allowed users to mount
* /dev/mtdblock$(n) but didn't actually _use_ the blockdev
*/
bdev = lookup_bdev(dev_name);
if (IS_ERR(bdev)) {
ret = PTR_ERR(bdev);
pr_debug("MTDSB: lookup_bdev() returned %d\n", ret);
return ERR_PTR(ret);
}
pr_debug("MTDSB: lookup_bdev() returned 0\n");
ret = -EINVAL;
major = MAJOR(bdev->bd_dev);
mtdnr = MINOR(bdev->bd_dev);
bdput(bdev);
if (major != MTD_BLOCK_MAJOR)
goto not_an_MTD_device;
return mount_mtd_nr(fs_type, flags, dev_name, data, mtdnr, fill_super);
not_an_MTD_device:
#endif /* CONFIG_BLOCK */
if (!(flags & MS_SILENT))
printk(KERN_NOTICE
"MTD: Attempt to mount non-MTD device \"%s\"\n",
dev_name);
return ERR_PTR(-EINVAL);
}
EXPORT_SYMBOL_GPL(mount_mtd);
/*
* destroy an MTD-based superblock
*/
void kill_mtd_super(struct super_block *sb)
{
generic_shutdown_super(sb);
put_mtd_device(sb->s_mtd);
sb->s_mtd = NULL;
}
EXPORT_SYMBOL_GPL(kill_mtd_super);
| gpl-2.0 |
SlimRoms/kernel_xiaomi_armani | drivers/scsi/bfa/bfa_fcs_fcpim.c | 5610 | 21866 | /*
* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
* All rights reserved
* www.brocade.com
*
* Linux driver for Brocade Fibre Channel Host Bus Adapter.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License (GPL) Version 2 as
* published by the Free Software Foundation
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
/*
* fcpim.c - FCP initiator mode i-t nexus state machine
*/
#include "bfad_drv.h"
#include "bfa_fcs.h"
#include "bfa_fcbuild.h"
#include "bfad_im.h"
BFA_TRC_FILE(FCS, FCPIM);
/*
* forward declarations
*/
static void bfa_fcs_itnim_timeout(void *arg);
static void bfa_fcs_itnim_free(struct bfa_fcs_itnim_s *itnim);
static void bfa_fcs_itnim_send_prli(void *itnim_cbarg,
struct bfa_fcxp_s *fcxp_alloced);
static void bfa_fcs_itnim_prli_response(void *fcsarg,
struct bfa_fcxp_s *fcxp, void *cbarg,
bfa_status_t req_status, u32 rsp_len,
u32 resid_len, struct fchs_s *rsp_fchs);
static void bfa_fcs_itnim_aen_post(struct bfa_fcs_itnim_s *itnim,
enum bfa_itnim_aen_event event);
/*
* fcs_itnim_sm FCS itnim state machine events
*/
enum bfa_fcs_itnim_event {
BFA_FCS_ITNIM_SM_ONLINE = 1, /* rport online event */
BFA_FCS_ITNIM_SM_OFFLINE = 2, /* rport offline */
BFA_FCS_ITNIM_SM_FRMSENT = 3, /* prli frame is sent */
BFA_FCS_ITNIM_SM_RSP_OK = 4, /* good response */
BFA_FCS_ITNIM_SM_RSP_ERROR = 5, /* error response */
BFA_FCS_ITNIM_SM_TIMEOUT = 6, /* delay timeout */
BFA_FCS_ITNIM_SM_HCB_OFFLINE = 7, /* BFA online callback */
BFA_FCS_ITNIM_SM_HCB_ONLINE = 8, /* BFA offline callback */
BFA_FCS_ITNIM_SM_INITIATOR = 9, /* rport is initiator */
BFA_FCS_ITNIM_SM_DELETE = 10, /* delete event from rport */
BFA_FCS_ITNIM_SM_PRLO = 11, /* delete event from rport */
BFA_FCS_ITNIM_SM_RSP_NOT_SUPP = 12, /* cmd not supported rsp */
};
static void bfa_fcs_itnim_sm_offline(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_prli_send(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_prli(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_prli_retry(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_hcb_online(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_online(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_hcb_offline(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static void bfa_fcs_itnim_sm_initiator(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event);
static struct bfa_sm_table_s itnim_sm_table[] = {
{BFA_SM(bfa_fcs_itnim_sm_offline), BFA_ITNIM_OFFLINE},
{BFA_SM(bfa_fcs_itnim_sm_prli_send), BFA_ITNIM_PRLI_SEND},
{BFA_SM(bfa_fcs_itnim_sm_prli), BFA_ITNIM_PRLI_SENT},
{BFA_SM(bfa_fcs_itnim_sm_prli_retry), BFA_ITNIM_PRLI_RETRY},
{BFA_SM(bfa_fcs_itnim_sm_hcb_online), BFA_ITNIM_HCB_ONLINE},
{BFA_SM(bfa_fcs_itnim_sm_online), BFA_ITNIM_ONLINE},
{BFA_SM(bfa_fcs_itnim_sm_hcb_offline), BFA_ITNIM_HCB_OFFLINE},
{BFA_SM(bfa_fcs_itnim_sm_initiator), BFA_ITNIM_INITIATIOR},
};
/*
* fcs_itnim_sm FCS itnim state machine
*/
static void
bfa_fcs_itnim_sm_offline(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_ONLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_prli_send);
itnim->prli_retries = 0;
bfa_fcs_itnim_send_prli(itnim, NULL);
break;
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_INITIATOR:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_initiator);
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_sm_prli_send(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_FRMSENT:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_prli);
break;
case BFA_FCS_ITNIM_SM_INITIATOR:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_initiator);
bfa_fcxp_walloc_cancel(itnim->fcs->bfa, &itnim->fcxp_wqe);
break;
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcxp_walloc_cancel(itnim->fcs->bfa, &itnim->fcxp_wqe);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcxp_walloc_cancel(itnim->fcs->bfa, &itnim->fcxp_wqe);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_sm_prli(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_RSP_OK:
if (itnim->rport->scsi_function == BFA_RPORT_INITIATOR) {
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_initiator);
} else {
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_hcb_online);
bfa_itnim_online(itnim->bfa_itnim, itnim->seq_rec);
}
break;
case BFA_FCS_ITNIM_SM_RSP_ERROR:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_prli_retry);
bfa_timer_start(itnim->fcs->bfa, &itnim->timer,
bfa_fcs_itnim_timeout, itnim,
BFA_FCS_RETRY_TIMEOUT);
break;
case BFA_FCS_ITNIM_SM_RSP_NOT_SUPP:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
break;
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcxp_discard(itnim->fcxp);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_INITIATOR:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_initiator);
bfa_fcxp_discard(itnim->fcxp);
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcxp_discard(itnim->fcxp);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_sm_prli_retry(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_TIMEOUT:
if (itnim->prli_retries < BFA_FCS_RPORT_MAX_RETRIES) {
itnim->prli_retries++;
bfa_trc(itnim->fcs, itnim->prli_retries);
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_prli_send);
bfa_fcs_itnim_send_prli(itnim, NULL);
} else {
/* invoke target offline */
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_LOGO_IMP);
}
break;
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_timer_stop(&itnim->timer);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_INITIATOR:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_initiator);
bfa_timer_stop(&itnim->timer);
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_timer_stop(&itnim->timer);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_sm_hcb_online(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
struct bfad_s *bfad = (struct bfad_s *)itnim->fcs->bfad;
char lpwwn_buf[BFA_STRING_32];
char rpwwn_buf[BFA_STRING_32];
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_HCB_ONLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_online);
bfa_fcb_itnim_online(itnim->itnim_drv);
wwn2str(lpwwn_buf, bfa_fcs_lport_get_pwwn(itnim->rport->port));
wwn2str(rpwwn_buf, itnim->rport->pwwn);
BFA_LOG(KERN_INFO, bfad, bfa_log_level,
"Target (WWN = %s) is online for initiator (WWN = %s)\n",
rpwwn_buf, lpwwn_buf);
bfa_fcs_itnim_aen_post(itnim, BFA_ITNIM_AEN_ONLINE);
break;
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_itnim_offline(itnim->bfa_itnim);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_sm_online(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
struct bfad_s *bfad = (struct bfad_s *)itnim->fcs->bfad;
char lpwwn_buf[BFA_STRING_32];
char rpwwn_buf[BFA_STRING_32];
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_hcb_offline);
bfa_fcb_itnim_offline(itnim->itnim_drv);
bfa_itnim_offline(itnim->bfa_itnim);
wwn2str(lpwwn_buf, bfa_fcs_lport_get_pwwn(itnim->rport->port));
wwn2str(rpwwn_buf, itnim->rport->pwwn);
if (bfa_fcs_lport_is_online(itnim->rport->port) == BFA_TRUE) {
BFA_LOG(KERN_ERR, bfad, bfa_log_level,
"Target (WWN = %s) connectivity lost for "
"initiator (WWN = %s)\n", rpwwn_buf, lpwwn_buf);
bfa_fcs_itnim_aen_post(itnim, BFA_ITNIM_AEN_DISCONNECT);
} else {
BFA_LOG(KERN_INFO, bfad, bfa_log_level,
"Target (WWN = %s) offlined by initiator (WWN = %s)\n",
rpwwn_buf, lpwwn_buf);
bfa_fcs_itnim_aen_post(itnim, BFA_ITNIM_AEN_OFFLINE);
}
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_sm_hcb_offline(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_HCB_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
/*
* This state is set when a discovered rport is also in intiator mode.
* This ITN is marked as no_op and is not active and will not be truned into
* online state.
*/
static void
bfa_fcs_itnim_sm_initiator(struct bfa_fcs_itnim_s *itnim,
enum bfa_fcs_itnim_event event)
{
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_trc(itnim->fcs, event);
switch (event) {
case BFA_FCS_ITNIM_SM_OFFLINE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_FC4_OFFLINE);
break;
case BFA_FCS_ITNIM_SM_RSP_ERROR:
case BFA_FCS_ITNIM_SM_ONLINE:
case BFA_FCS_ITNIM_SM_INITIATOR:
break;
case BFA_FCS_ITNIM_SM_DELETE:
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
bfa_fcs_itnim_free(itnim);
break;
default:
bfa_sm_fault(itnim->fcs, event);
}
}
static void
bfa_fcs_itnim_aen_post(struct bfa_fcs_itnim_s *itnim,
enum bfa_itnim_aen_event event)
{
struct bfa_fcs_rport_s *rport = itnim->rport;
struct bfad_s *bfad = (struct bfad_s *)itnim->fcs->bfad;
struct bfa_aen_entry_s *aen_entry;
/* Don't post events for well known addresses */
if (BFA_FCS_PID_IS_WKA(rport->pid))
return;
bfad_get_aen_entry(bfad, aen_entry);
if (!aen_entry)
return;
aen_entry->aen_data.itnim.vf_id = rport->port->fabric->vf_id;
aen_entry->aen_data.itnim.ppwwn = bfa_fcs_lport_get_pwwn(
bfa_fcs_get_base_port(itnim->fcs));
aen_entry->aen_data.itnim.lpwwn = bfa_fcs_lport_get_pwwn(rport->port);
aen_entry->aen_data.itnim.rpwwn = rport->pwwn;
/* Send the AEN notification */
bfad_im_post_vendor_event(aen_entry, bfad, ++rport->fcs->fcs_aen_seq,
BFA_AEN_CAT_ITNIM, event);
}
static void
bfa_fcs_itnim_send_prli(void *itnim_cbarg, struct bfa_fcxp_s *fcxp_alloced)
{
struct bfa_fcs_itnim_s *itnim = itnim_cbarg;
struct bfa_fcs_rport_s *rport = itnim->rport;
struct bfa_fcs_lport_s *port = rport->port;
struct fchs_s fchs;
struct bfa_fcxp_s *fcxp;
int len;
bfa_trc(itnim->fcs, itnim->rport->pwwn);
fcxp = fcxp_alloced ? fcxp_alloced : bfa_fcs_fcxp_alloc(port->fcs);
if (!fcxp) {
itnim->stats.fcxp_alloc_wait++;
bfa_fcs_fcxp_alloc_wait(port->fcs->bfa, &itnim->fcxp_wqe,
bfa_fcs_itnim_send_prli, itnim);
return;
}
itnim->fcxp = fcxp;
len = fc_prli_build(&fchs, bfa_fcxp_get_reqbuf(fcxp),
itnim->rport->pid, bfa_fcs_lport_get_fcid(port), 0);
bfa_fcxp_send(fcxp, rport->bfa_rport, port->fabric->vf_id, port->lp_tag,
BFA_FALSE, FC_CLASS_3, len, &fchs,
bfa_fcs_itnim_prli_response, (void *)itnim,
FC_MAX_PDUSZ, FC_ELS_TOV);
itnim->stats.prli_sent++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_FRMSENT);
}
static void
bfa_fcs_itnim_prli_response(void *fcsarg, struct bfa_fcxp_s *fcxp, void *cbarg,
bfa_status_t req_status, u32 rsp_len,
u32 resid_len, struct fchs_s *rsp_fchs)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) cbarg;
struct fc_els_cmd_s *els_cmd;
struct fc_prli_s *prli_resp;
struct fc_ls_rjt_s *ls_rjt;
struct fc_prli_params_s *sparams;
bfa_trc(itnim->fcs, req_status);
/*
* Sanity Checks
*/
if (req_status != BFA_STATUS_OK) {
itnim->stats.prli_rsp_err++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_RSP_ERROR);
return;
}
els_cmd = (struct fc_els_cmd_s *) BFA_FCXP_RSP_PLD(fcxp);
if (els_cmd->els_code == FC_ELS_ACC) {
prli_resp = (struct fc_prli_s *) els_cmd;
if (fc_prli_rsp_parse(prli_resp, rsp_len) != FC_PARSE_OK) {
bfa_trc(itnim->fcs, rsp_len);
/*
* Check if this r-port is also in Initiator mode.
* If so, we need to set this ITN as a no-op.
*/
if (prli_resp->parampage.servparams.initiator) {
bfa_trc(itnim->fcs, prli_resp->parampage.type);
itnim->rport->scsi_function =
BFA_RPORT_INITIATOR;
itnim->stats.prli_rsp_acc++;
itnim->stats.initiator++;
bfa_sm_send_event(itnim,
BFA_FCS_ITNIM_SM_RSP_OK);
return;
}
itnim->stats.prli_rsp_parse_err++;
return;
}
itnim->rport->scsi_function = BFA_RPORT_TARGET;
sparams = &prli_resp->parampage.servparams;
itnim->seq_rec = sparams->retry;
itnim->rec_support = sparams->rec_support;
itnim->task_retry_id = sparams->task_retry_id;
itnim->conf_comp = sparams->confirm;
itnim->stats.prli_rsp_acc++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_RSP_OK);
} else {
ls_rjt = (struct fc_ls_rjt_s *) BFA_FCXP_RSP_PLD(fcxp);
bfa_trc(itnim->fcs, ls_rjt->reason_code);
bfa_trc(itnim->fcs, ls_rjt->reason_code_expl);
itnim->stats.prli_rsp_rjt++;
if (ls_rjt->reason_code == FC_LS_RJT_RSN_CMD_NOT_SUPP) {
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_RSP_NOT_SUPP);
return;
}
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_RSP_ERROR);
}
}
static void
bfa_fcs_itnim_timeout(void *arg)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) arg;
itnim->stats.timeout++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_TIMEOUT);
}
static void
bfa_fcs_itnim_free(struct bfa_fcs_itnim_s *itnim)
{
bfa_itnim_delete(itnim->bfa_itnim);
bfa_fcb_itnim_free(itnim->fcs->bfad, itnim->itnim_drv);
}
/*
* itnim_public FCS ITNIM public interfaces
*/
/*
* Called by rport when a new rport is created.
*
* @param[in] rport - remote port.
*/
struct bfa_fcs_itnim_s *
bfa_fcs_itnim_create(struct bfa_fcs_rport_s *rport)
{
struct bfa_fcs_lport_s *port = rport->port;
struct bfa_fcs_itnim_s *itnim;
struct bfad_itnim_s *itnim_drv;
struct bfa_itnim_s *bfa_itnim;
/*
* call bfad to allocate the itnim
*/
bfa_fcb_itnim_alloc(port->fcs->bfad, &itnim, &itnim_drv);
if (itnim == NULL) {
bfa_trc(port->fcs, rport->pwwn);
return NULL;
}
/*
* Initialize itnim
*/
itnim->rport = rport;
itnim->fcs = rport->fcs;
itnim->itnim_drv = itnim_drv;
/*
* call BFA to create the itnim
*/
bfa_itnim =
bfa_itnim_create(port->fcs->bfa, rport->bfa_rport, itnim);
if (bfa_itnim == NULL) {
bfa_trc(port->fcs, rport->pwwn);
bfa_fcb_itnim_free(port->fcs->bfad, itnim_drv);
WARN_ON(1);
return NULL;
}
itnim->bfa_itnim = bfa_itnim;
itnim->seq_rec = BFA_FALSE;
itnim->rec_support = BFA_FALSE;
itnim->conf_comp = BFA_FALSE;
itnim->task_retry_id = BFA_FALSE;
/*
* Set State machine
*/
bfa_sm_set_state(itnim, bfa_fcs_itnim_sm_offline);
return itnim;
}
/*
* Called by rport to delete the instance of FCPIM.
*
* @param[in] rport - remote port.
*/
void
bfa_fcs_itnim_delete(struct bfa_fcs_itnim_s *itnim)
{
bfa_trc(itnim->fcs, itnim->rport->pid);
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_DELETE);
}
/*
* Notification from rport that PLOGI is complete to initiate FC-4 session.
*/
void
bfa_fcs_itnim_rport_online(struct bfa_fcs_itnim_s *itnim)
{
itnim->stats.onlines++;
if (!BFA_FCS_PID_IS_WKA(itnim->rport->pid)) {
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_ONLINE);
} else {
/*
* For well known addresses, we set the itnim to initiator
* state
*/
itnim->stats.initiator++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_INITIATOR);
}
}
/*
* Called by rport to handle a remote device offline.
*/
void
bfa_fcs_itnim_rport_offline(struct bfa_fcs_itnim_s *itnim)
{
itnim->stats.offlines++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_OFFLINE);
}
/*
* Called by rport when remote port is known to be an initiator from
* PRLI received.
*/
void
bfa_fcs_itnim_is_initiator(struct bfa_fcs_itnim_s *itnim)
{
bfa_trc(itnim->fcs, itnim->rport->pid);
itnim->stats.initiator++;
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_INITIATOR);
}
/*
* Called by rport to check if the itnim is online.
*/
bfa_status_t
bfa_fcs_itnim_get_online_state(struct bfa_fcs_itnim_s *itnim)
{
bfa_trc(itnim->fcs, itnim->rport->pid);
switch (bfa_sm_to_state(itnim_sm_table, itnim->sm)) {
case BFA_ITNIM_ONLINE:
case BFA_ITNIM_INITIATIOR:
return BFA_STATUS_OK;
default:
return BFA_STATUS_NO_FCPIM_NEXUS;
}
}
/*
* BFA completion callback for bfa_itnim_online().
*/
void
bfa_cb_itnim_online(void *cbarg)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) cbarg;
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_HCB_ONLINE);
}
/*
* BFA completion callback for bfa_itnim_offline().
*/
void
bfa_cb_itnim_offline(void *cb_arg)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) cb_arg;
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_sm_send_event(itnim, BFA_FCS_ITNIM_SM_HCB_OFFLINE);
}
/*
* Mark the beginning of PATH TOV handling. IO completion callbacks
* are still pending.
*/
void
bfa_cb_itnim_tov_begin(void *cb_arg)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) cb_arg;
bfa_trc(itnim->fcs, itnim->rport->pwwn);
}
/*
* Mark the end of PATH TOV handling. All pending IOs are already cleaned up.
*/
void
bfa_cb_itnim_tov(void *cb_arg)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) cb_arg;
struct bfad_itnim_s *itnim_drv = itnim->itnim_drv;
bfa_trc(itnim->fcs, itnim->rport->pwwn);
itnim_drv->state = ITNIM_STATE_TIMEOUT;
}
/*
* BFA notification to FCS/driver for second level error recovery.
*
* Atleast one I/O request has timedout and target is unresponsive to
* repeated abort requests. Second level error recovery should be initiated
* by starting implicit logout and recovery procedures.
*/
void
bfa_cb_itnim_sler(void *cb_arg)
{
struct bfa_fcs_itnim_s *itnim = (struct bfa_fcs_itnim_s *) cb_arg;
itnim->stats.sler++;
bfa_trc(itnim->fcs, itnim->rport->pwwn);
bfa_sm_send_event(itnim->rport, RPSM_EVENT_LOGO_IMP);
}
struct bfa_fcs_itnim_s *
bfa_fcs_itnim_lookup(struct bfa_fcs_lport_s *port, wwn_t rpwwn)
{
struct bfa_fcs_rport_s *rport;
rport = bfa_fcs_rport_lookup(port, rpwwn);
if (!rport)
return NULL;
WARN_ON(rport->itnim == NULL);
return rport->itnim;
}
bfa_status_t
bfa_fcs_itnim_attr_get(struct bfa_fcs_lport_s *port, wwn_t rpwwn,
struct bfa_itnim_attr_s *attr)
{
struct bfa_fcs_itnim_s *itnim = NULL;
itnim = bfa_fcs_itnim_lookup(port, rpwwn);
if (itnim == NULL)
return BFA_STATUS_NO_FCPIM_NEXUS;
attr->state = bfa_sm_to_state(itnim_sm_table, itnim->sm);
attr->retry = itnim->seq_rec;
attr->rec_support = itnim->rec_support;
attr->conf_comp = itnim->conf_comp;
attr->task_retry_id = itnim->task_retry_id;
return BFA_STATUS_OK;
}
bfa_status_t
bfa_fcs_itnim_stats_get(struct bfa_fcs_lport_s *port, wwn_t rpwwn,
struct bfa_itnim_stats_s *stats)
{
struct bfa_fcs_itnim_s *itnim = NULL;
WARN_ON(port == NULL);
itnim = bfa_fcs_itnim_lookup(port, rpwwn);
if (itnim == NULL)
return BFA_STATUS_NO_FCPIM_NEXUS;
memcpy(stats, &itnim->stats, sizeof(struct bfa_itnim_stats_s));
return BFA_STATUS_OK;
}
bfa_status_t
bfa_fcs_itnim_stats_clear(struct bfa_fcs_lport_s *port, wwn_t rpwwn)
{
struct bfa_fcs_itnim_s *itnim = NULL;
WARN_ON(port == NULL);
itnim = bfa_fcs_itnim_lookup(port, rpwwn);
if (itnim == NULL)
return BFA_STATUS_NO_FCPIM_NEXUS;
memset(&itnim->stats, 0, sizeof(struct bfa_itnim_stats_s));
return BFA_STATUS_OK;
}
void
bfa_fcs_fcpim_uf_recv(struct bfa_fcs_itnim_s *itnim,
struct fchs_s *fchs, u16 len)
{
struct fc_els_cmd_s *els_cmd;
bfa_trc(itnim->fcs, fchs->type);
if (fchs->type != FC_TYPE_ELS)
return;
els_cmd = (struct fc_els_cmd_s *) (fchs + 1);
bfa_trc(itnim->fcs, els_cmd->els_code);
switch (els_cmd->els_code) {
case FC_ELS_PRLO:
bfa_fcs_rport_prlo(itnim->rport, fchs->ox_id);
break;
default:
WARN_ON(1);
}
}
| gpl-2.0 |
googyanas/Googy-Max4-CM-Kernel | drivers/usb/host/fhci-dbg.c | 9194 | 3699 | /*
* Freescale QUICC Engine USB Host Controller Driver
*
* Copyright (c) Freescale Semicondutor, Inc. 2006.
* Shlomi Gridish <gridish@freescale.com>
* Jerry Huang <Chang-Ming.Huang@freescale.com>
* Copyright (c) Logic Product Development, Inc. 2007
* Peter Barada <peterb@logicpd.com>
* Copyright (c) MontaVista Software, Inc. 2008.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include "fhci.h"
void fhci_dbg_isr(struct fhci_hcd *fhci, int usb_er)
{
int i;
if (usb_er == -1) {
fhci->usb_irq_stat[12]++;
return;
}
for (i = 0; i < 12; ++i) {
if (usb_er & (1 << i))
fhci->usb_irq_stat[i]++;
}
}
static int fhci_dfs_regs_show(struct seq_file *s, void *v)
{
struct fhci_hcd *fhci = s->private;
struct fhci_regs __iomem *regs = fhci->regs;
seq_printf(s,
"mode: 0x%x\n" "addr: 0x%x\n"
"command: 0x%x\n" "ep0: 0x%x\n"
"event: 0x%x\n" "mask: 0x%x\n"
"status: 0x%x\n" "SOF timer: %d\n"
"frame number: %d\n"
"lines status: 0x%x\n",
in_8(®s->usb_mod), in_8(®s->usb_addr),
in_8(®s->usb_comm), in_be16(®s->usb_ep[0]),
in_be16(®s->usb_event), in_be16(®s->usb_mask),
in_8(®s->usb_status), in_be16(®s->usb_sof_tmr),
in_be16(®s->usb_frame_num),
fhci_ioports_check_bus_state(fhci));
return 0;
}
static int fhci_dfs_irq_stat_show(struct seq_file *s, void *v)
{
struct fhci_hcd *fhci = s->private;
int *usb_irq_stat = fhci->usb_irq_stat;
seq_printf(s,
"RXB: %d\n" "TXB: %d\n" "BSY: %d\n"
"SOF: %d\n" "TXE0: %d\n" "TXE1: %d\n"
"TXE2: %d\n" "TXE3: %d\n" "IDLE: %d\n"
"RESET: %d\n" "SFT: %d\n" "MSF: %d\n"
"IDLE_ONLY: %d\n",
usb_irq_stat[0], usb_irq_stat[1], usb_irq_stat[2],
usb_irq_stat[3], usb_irq_stat[4], usb_irq_stat[5],
usb_irq_stat[6], usb_irq_stat[7], usb_irq_stat[8],
usb_irq_stat[9], usb_irq_stat[10], usb_irq_stat[11],
usb_irq_stat[12]);
return 0;
}
static int fhci_dfs_regs_open(struct inode *inode, struct file *file)
{
return single_open(file, fhci_dfs_regs_show, inode->i_private);
}
static int fhci_dfs_irq_stat_open(struct inode *inode, struct file *file)
{
return single_open(file, fhci_dfs_irq_stat_show, inode->i_private);
}
static const struct file_operations fhci_dfs_regs_fops = {
.open = fhci_dfs_regs_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations fhci_dfs_irq_stat_fops = {
.open = fhci_dfs_irq_stat_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
void fhci_dfs_create(struct fhci_hcd *fhci)
{
struct device *dev = fhci_to_hcd(fhci)->self.controller;
fhci->dfs_root = debugfs_create_dir(dev_name(dev), usb_debug_root);
if (!fhci->dfs_root) {
WARN_ON(1);
return;
}
fhci->dfs_regs = debugfs_create_file("regs", S_IFREG | S_IRUGO,
fhci->dfs_root, fhci, &fhci_dfs_regs_fops);
fhci->dfs_irq_stat = debugfs_create_file("irq_stat",
S_IFREG | S_IRUGO, fhci->dfs_root, fhci,
&fhci_dfs_irq_stat_fops);
WARN_ON(!fhci->dfs_regs || !fhci->dfs_irq_stat);
}
void fhci_dfs_destroy(struct fhci_hcd *fhci)
{
if (!fhci->dfs_root)
return;
if (fhci->dfs_irq_stat)
debugfs_remove(fhci->dfs_irq_stat);
if (fhci->dfs_regs)
debugfs_remove(fhci->dfs_regs);
debugfs_remove(fhci->dfs_root);
}
| gpl-2.0 |
TeamBliss-Devices/android_kernel_samsung_v2wifixx | fs/configfs/file.c | 12266 | 9648 | /* -*- mode: c; c-basic-offset: 8; -*-
* vim: noexpandtab sw=8 ts=8 sts=0:
*
* file.c - operations for regular (text) files.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this program; if not, write to the
* Free Software Foundation, Inc., 59 Temple Place - Suite 330,
* Boston, MA 021110-1307, USA.
*
* Based on sysfs:
* sysfs is Copyright (C) 2001, 2002, 2003 Patrick Mochel
*
* configfs Copyright (C) 2005 Oracle. All rights reserved.
*/
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <asm/uaccess.h>
#include <linux/configfs.h>
#include "configfs_internal.h"
/*
* A simple attribute can only be 4096 characters. Why 4k? Because the
* original code limited it to PAGE_SIZE. That's a bad idea, though,
* because an attribute of 16k on ia64 won't work on x86. So we limit to
* 4k, our minimum common page size.
*/
#define SIMPLE_ATTR_SIZE 4096
struct configfs_buffer {
size_t count;
loff_t pos;
char * page;
struct configfs_item_operations * ops;
struct mutex mutex;
int needs_read_fill;
};
/**
* fill_read_buffer - allocate and fill buffer from item.
* @dentry: dentry pointer.
* @buffer: data buffer for file.
*
* Allocate @buffer->page, if it hasn't been already, then call the
* config_item's show() method to fill the buffer with this attribute's
* data.
* This is called only once, on the file's first read.
*/
static int fill_read_buffer(struct dentry * dentry, struct configfs_buffer * buffer)
{
struct configfs_attribute * attr = to_attr(dentry);
struct config_item * item = to_item(dentry->d_parent);
struct configfs_item_operations * ops = buffer->ops;
int ret = 0;
ssize_t count;
if (!buffer->page)
buffer->page = (char *) get_zeroed_page(GFP_KERNEL);
if (!buffer->page)
return -ENOMEM;
count = ops->show_attribute(item,attr,buffer->page);
buffer->needs_read_fill = 0;
BUG_ON(count > (ssize_t)SIMPLE_ATTR_SIZE);
if (count >= 0)
buffer->count = count;
else
ret = count;
return ret;
}
/**
* configfs_read_file - read an attribute.
* @file: file pointer.
* @buf: buffer to fill.
* @count: number of bytes to read.
* @ppos: starting offset in file.
*
* Userspace wants to read an attribute file. The attribute descriptor
* is in the file's ->d_fsdata. The target item is in the directory's
* ->d_fsdata.
*
* We call fill_read_buffer() to allocate and fill the buffer from the
* item's show() method exactly once (if the read is happening from
* the beginning of the file). That should fill the entire buffer with
* all the data the item has to offer for that attribute.
* We then call flush_read_buffer() to copy the buffer to userspace
* in the increments specified.
*/
static ssize_t
configfs_read_file(struct file *file, char __user *buf, size_t count, loff_t *ppos)
{
struct configfs_buffer * buffer = file->private_data;
ssize_t retval = 0;
mutex_lock(&buffer->mutex);
if (buffer->needs_read_fill) {
if ((retval = fill_read_buffer(file->f_path.dentry,buffer)))
goto out;
}
pr_debug("%s: count = %zd, ppos = %lld, buf = %s\n",
__func__, count, *ppos, buffer->page);
retval = simple_read_from_buffer(buf, count, ppos, buffer->page,
buffer->count);
out:
mutex_unlock(&buffer->mutex);
return retval;
}
/**
* fill_write_buffer - copy buffer from userspace.
* @buffer: data buffer for file.
* @buf: data from user.
* @count: number of bytes in @userbuf.
*
* Allocate @buffer->page if it hasn't been already, then
* copy the user-supplied buffer into it.
*/
static int
fill_write_buffer(struct configfs_buffer * buffer, const char __user * buf, size_t count)
{
int error;
if (!buffer->page)
buffer->page = (char *)__get_free_pages(GFP_KERNEL, 0);
if (!buffer->page)
return -ENOMEM;
if (count >= SIMPLE_ATTR_SIZE)
count = SIMPLE_ATTR_SIZE - 1;
error = copy_from_user(buffer->page,buf,count);
buffer->needs_read_fill = 1;
/* if buf is assumed to contain a string, terminate it by \0,
* so e.g. sscanf() can scan the string easily */
buffer->page[count] = 0;
return error ? -EFAULT : count;
}
/**
* flush_write_buffer - push buffer to config_item.
* @dentry: dentry to the attribute
* @buffer: data buffer for file.
* @count: number of bytes
*
* Get the correct pointers for the config_item and the attribute we're
* dealing with, then call the store() method for the attribute,
* passing the buffer that we acquired in fill_write_buffer().
*/
static int
flush_write_buffer(struct dentry * dentry, struct configfs_buffer * buffer, size_t count)
{
struct configfs_attribute * attr = to_attr(dentry);
struct config_item * item = to_item(dentry->d_parent);
struct configfs_item_operations * ops = buffer->ops;
return ops->store_attribute(item,attr,buffer->page,count);
}
/**
* configfs_write_file - write an attribute.
* @file: file pointer
* @buf: data to write
* @count: number of bytes
* @ppos: starting offset
*
* Similar to configfs_read_file(), though working in the opposite direction.
* We allocate and fill the data from the user in fill_write_buffer(),
* then push it to the config_item in flush_write_buffer().
* There is no easy way for us to know if userspace is only doing a partial
* write, so we don't support them. We expect the entire buffer to come
* on the first write.
* Hint: if you're writing a value, first read the file, modify only the
* the value you're changing, then write entire buffer back.
*/
static ssize_t
configfs_write_file(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
{
struct configfs_buffer * buffer = file->private_data;
ssize_t len;
mutex_lock(&buffer->mutex);
len = fill_write_buffer(buffer, buf, count);
if (len > 0)
len = flush_write_buffer(file->f_path.dentry, buffer, count);
if (len > 0)
*ppos += len;
mutex_unlock(&buffer->mutex);
return len;
}
static int check_perm(struct inode * inode, struct file * file)
{
struct config_item *item = configfs_get_config_item(file->f_path.dentry->d_parent);
struct configfs_attribute * attr = to_attr(file->f_path.dentry);
struct configfs_buffer * buffer;
struct configfs_item_operations * ops = NULL;
int error = 0;
if (!item || !attr)
goto Einval;
/* Grab the module reference for this attribute if we have one */
if (!try_module_get(attr->ca_owner)) {
error = -ENODEV;
goto Done;
}
if (item->ci_type)
ops = item->ci_type->ct_item_ops;
else
goto Eaccess;
/* File needs write support.
* The inode's perms must say it's ok,
* and we must have a store method.
*/
if (file->f_mode & FMODE_WRITE) {
if (!(inode->i_mode & S_IWUGO) || !ops->store_attribute)
goto Eaccess;
}
/* File needs read support.
* The inode's perms must say it's ok, and we there
* must be a show method for it.
*/
if (file->f_mode & FMODE_READ) {
if (!(inode->i_mode & S_IRUGO) || !ops->show_attribute)
goto Eaccess;
}
/* No error? Great, allocate a buffer for the file, and store it
* it in file->private_data for easy access.
*/
buffer = kzalloc(sizeof(struct configfs_buffer),GFP_KERNEL);
if (!buffer) {
error = -ENOMEM;
goto Enomem;
}
mutex_init(&buffer->mutex);
buffer->needs_read_fill = 1;
buffer->ops = ops;
file->private_data = buffer;
goto Done;
Einval:
error = -EINVAL;
goto Done;
Eaccess:
error = -EACCES;
Enomem:
module_put(attr->ca_owner);
Done:
if (error && item)
config_item_put(item);
return error;
}
static int configfs_open_file(struct inode * inode, struct file * filp)
{
return check_perm(inode,filp);
}
static int configfs_release(struct inode * inode, struct file * filp)
{
struct config_item * item = to_item(filp->f_path.dentry->d_parent);
struct configfs_attribute * attr = to_attr(filp->f_path.dentry);
struct module * owner = attr->ca_owner;
struct configfs_buffer * buffer = filp->private_data;
if (item)
config_item_put(item);
/* After this point, attr should not be accessed. */
module_put(owner);
if (buffer) {
if (buffer->page)
free_page((unsigned long)buffer->page);
mutex_destroy(&buffer->mutex);
kfree(buffer);
}
return 0;
}
const struct file_operations configfs_file_operations = {
.read = configfs_read_file,
.write = configfs_write_file,
.llseek = generic_file_llseek,
.open = configfs_open_file,
.release = configfs_release,
};
int configfs_add_file(struct dentry * dir, const struct configfs_attribute * attr, int type)
{
struct configfs_dirent * parent_sd = dir->d_fsdata;
umode_t mode = (attr->ca_mode & S_IALLUGO) | S_IFREG;
int error = 0;
mutex_lock_nested(&dir->d_inode->i_mutex, I_MUTEX_NORMAL);
error = configfs_make_dirent(parent_sd, NULL, (void *) attr, mode, type);
mutex_unlock(&dir->d_inode->i_mutex);
return error;
}
/**
* configfs_create_file - create an attribute file for an item.
* @item: item we're creating for.
* @attr: atrribute descriptor.
*/
int configfs_create_file(struct config_item * item, const struct configfs_attribute * attr)
{
BUG_ON(!item || !item->ci_dentry || !attr);
return configfs_add_file(item->ci_dentry, attr,
CONFIGFS_ITEM_ATTR);
}
| gpl-2.0 |
byzvulture/Z5S_NX503A_KitKat_kernel | drivers/video/aty/radeon_i2c.c | 12778 | 4019 | #include "radeonfb.h"
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <asm/io.h>
#include <video/radeon.h>
#include "../edid.h"
static void radeon_gpio_setscl(void* data, int state)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN);
if (!state)
val |= VGA_DDC_CLK_OUT_EN;
OUTREG(chan->ddc_reg, val);
(void)INREG(chan->ddc_reg);
}
static void radeon_gpio_setsda(void* data, int state)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN);
if (!state)
val |= VGA_DDC_DATA_OUT_EN;
OUTREG(chan->ddc_reg, val);
(void)INREG(chan->ddc_reg);
}
static int radeon_gpio_getscl(void* data)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg);
return (val & VGA_DDC_CLK_INPUT) ? 1 : 0;
}
static int radeon_gpio_getsda(void* data)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg);
return (val & VGA_DDC_DATA_INPUT) ? 1 : 0;
}
static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan, const char *name)
{
int rc;
snprintf(chan->adapter.name, sizeof(chan->adapter.name),
"radeonfb %s", name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->rinfo->pdev->dev;
chan->algo.setsda = radeon_gpio_setsda;
chan->algo.setscl = radeon_gpio_setscl;
chan->algo.getsda = radeon_gpio_getsda;
chan->algo.getscl = radeon_gpio_getscl;
chan->algo.udelay = 10;
chan->algo.timeout = 20;
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
radeon_gpio_setsda(chan, 1);
radeon_gpio_setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->rinfo->pdev->dev, "I2C bus %s registered.\n", name);
else
dev_warn(&chan->rinfo->pdev->dev, "Failed to register I2C bus %s.\n", name);
return rc;
}
void radeon_create_i2c_busses(struct radeonfb_info *rinfo)
{
rinfo->i2c[0].rinfo = rinfo;
rinfo->i2c[0].ddc_reg = GPIO_MONID;
#ifndef CONFIG_PPC
rinfo->i2c[0].adapter.class = I2C_CLASS_HWMON;
#endif
radeon_setup_i2c_bus(&rinfo->i2c[0], "monid");
rinfo->i2c[1].rinfo = rinfo;
rinfo->i2c[1].ddc_reg = GPIO_DVI_DDC;
radeon_setup_i2c_bus(&rinfo->i2c[1], "dvi");
rinfo->i2c[2].rinfo = rinfo;
rinfo->i2c[2].ddc_reg = GPIO_VGA_DDC;
radeon_setup_i2c_bus(&rinfo->i2c[2], "vga");
rinfo->i2c[3].rinfo = rinfo;
rinfo->i2c[3].ddc_reg = GPIO_CRT2_DDC;
radeon_setup_i2c_bus(&rinfo->i2c[3], "crt2");
}
void radeon_delete_i2c_busses(struct radeonfb_info *rinfo)
{
if (rinfo->i2c[0].rinfo)
i2c_del_adapter(&rinfo->i2c[0].adapter);
rinfo->i2c[0].rinfo = NULL;
if (rinfo->i2c[1].rinfo)
i2c_del_adapter(&rinfo->i2c[1].adapter);
rinfo->i2c[1].rinfo = NULL;
if (rinfo->i2c[2].rinfo)
i2c_del_adapter(&rinfo->i2c[2].adapter);
rinfo->i2c[2].rinfo = NULL;
if (rinfo->i2c[3].rinfo)
i2c_del_adapter(&rinfo->i2c[3].adapter);
rinfo->i2c[3].rinfo = NULL;
}
int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn,
u8 **out_edid)
{
u8 *edid;
edid = fb_ddc_read(&rinfo->i2c[conn-1].adapter);
if (out_edid)
*out_edid = edid;
if (!edid) {
pr_debug("radeonfb: I2C (port %d) ... not found\n", conn);
return MT_NONE;
}
if (edid[0x14] & 0x80) {
/* Fix detection using BIOS tables */
if (rinfo->is_mobility /*&& conn == ddc_dvi*/ &&
(INREG(LVDS_GEN_CNTL) & LVDS_ON)) {
pr_debug("radeonfb: I2C (port %d) ... found LVDS panel\n", conn);
return MT_LCD;
} else {
pr_debug("radeonfb: I2C (port %d) ... found TMDS panel\n", conn);
return MT_DFP;
}
}
pr_debug("radeonfb: I2C (port %d) ... found CRT display\n", conn);
return MT_CRT;
}
| gpl-2.0 |
muntahar/GT-S5660-KERNEL | sound/isa/gus/gus_mem.c | 14058 | 9900 | /*
* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
* GUS's memory allocation routines / bottom layer
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/slab.h>
#include <linux/string.h>
#include <sound/core.h>
#include <sound/gus.h>
#include <sound/info.h>
#ifdef CONFIG_SND_DEBUG
static void snd_gf1_mem_info_read(struct snd_info_entry *entry,
struct snd_info_buffer *buffer);
#endif
void snd_gf1_mem_lock(struct snd_gf1_mem * alloc, int xup)
{
if (!xup) {
mutex_lock(&alloc->memory_mutex);
} else {
mutex_unlock(&alloc->memory_mutex);
}
}
static struct snd_gf1_mem_block *snd_gf1_mem_xalloc(struct snd_gf1_mem * alloc,
struct snd_gf1_mem_block * block)
{
struct snd_gf1_mem_block *pblock, *nblock;
nblock = kmalloc(sizeof(struct snd_gf1_mem_block), GFP_KERNEL);
if (nblock == NULL)
return NULL;
*nblock = *block;
pblock = alloc->first;
while (pblock) {
if (pblock->ptr > nblock->ptr) {
nblock->prev = pblock->prev;
nblock->next = pblock;
pblock->prev = nblock;
if (pblock == alloc->first)
alloc->first = nblock;
else
nblock->prev->next = nblock;
mutex_unlock(&alloc->memory_mutex);
return NULL;
}
pblock = pblock->next;
}
nblock->next = NULL;
if (alloc->last == NULL) {
nblock->prev = NULL;
alloc->first = alloc->last = nblock;
} else {
nblock->prev = alloc->last;
alloc->last->next = nblock;
alloc->last = nblock;
}
return nblock;
}
int snd_gf1_mem_xfree(struct snd_gf1_mem * alloc, struct snd_gf1_mem_block * block)
{
if (block->share) { /* ok.. shared block */
block->share--;
mutex_unlock(&alloc->memory_mutex);
return 0;
}
if (alloc->first == block) {
alloc->first = block->next;
if (block->next)
block->next->prev = NULL;
} else {
block->prev->next = block->next;
if (block->next)
block->next->prev = block->prev;
}
if (alloc->last == block) {
alloc->last = block->prev;
if (block->prev)
block->prev->next = NULL;
} else {
block->next->prev = block->prev;
if (block->prev)
block->prev->next = block->next;
}
kfree(block->name);
kfree(block);
return 0;
}
static struct snd_gf1_mem_block *snd_gf1_mem_look(struct snd_gf1_mem * alloc,
unsigned int address)
{
struct snd_gf1_mem_block *block;
for (block = alloc->first; block; block = block->next) {
if (block->ptr == address) {
return block;
}
}
return NULL;
}
static struct snd_gf1_mem_block *snd_gf1_mem_share(struct snd_gf1_mem * alloc,
unsigned int *share_id)
{
struct snd_gf1_mem_block *block;
if (!share_id[0] && !share_id[1] &&
!share_id[2] && !share_id[3])
return NULL;
for (block = alloc->first; block; block = block->next)
if (!memcmp(share_id, block->share_id,
sizeof(block->share_id)))
return block;
return NULL;
}
static int snd_gf1_mem_find(struct snd_gf1_mem * alloc,
struct snd_gf1_mem_block * block,
unsigned int size, int w_16, int align)
{
struct snd_gf1_bank_info *info = w_16 ? alloc->banks_16 : alloc->banks_8;
unsigned int idx, boundary;
int size1;
struct snd_gf1_mem_block *pblock;
unsigned int ptr1, ptr2;
if (w_16 && align < 2)
align = 2;
block->flags = w_16 ? SNDRV_GF1_MEM_BLOCK_16BIT : 0;
block->owner = SNDRV_GF1_MEM_OWNER_DRIVER;
block->share = 0;
block->share_id[0] = block->share_id[1] =
block->share_id[2] = block->share_id[3] = 0;
block->name = NULL;
block->prev = block->next = NULL;
for (pblock = alloc->first, idx = 0; pblock; pblock = pblock->next) {
while (pblock->ptr >= (boundary = info[idx].address + info[idx].size))
idx++;
while (pblock->ptr + pblock->size >= (boundary = info[idx].address + info[idx].size))
idx++;
ptr2 = boundary;
if (pblock->next) {
if (pblock->ptr + pblock->size == pblock->next->ptr)
continue;
if (pblock->next->ptr < boundary)
ptr2 = pblock->next->ptr;
}
ptr1 = ALIGN(pblock->ptr + pblock->size, align);
if (ptr1 >= ptr2)
continue;
size1 = ptr2 - ptr1;
if ((int)size <= size1) {
block->ptr = ptr1;
block->size = size;
return 0;
}
}
while (++idx < 4) {
if (size <= info[idx].size) {
/* I assume that bank address is already aligned.. */
block->ptr = info[idx].address;
block->size = size;
return 0;
}
}
return -ENOMEM;
}
struct snd_gf1_mem_block *snd_gf1_mem_alloc(struct snd_gf1_mem * alloc, int owner,
char *name, int size, int w_16, int align,
unsigned int *share_id)
{
struct snd_gf1_mem_block block, *nblock;
snd_gf1_mem_lock(alloc, 0);
if (share_id != NULL) {
nblock = snd_gf1_mem_share(alloc, share_id);
if (nblock != NULL) {
if (size != (int)nblock->size) {
/* TODO: remove in the future */
snd_printk(KERN_ERR "snd_gf1_mem_alloc - share: sizes differ\n");
goto __std;
}
nblock->share++;
snd_gf1_mem_lock(alloc, 1);
return NULL;
}
}
__std:
if (snd_gf1_mem_find(alloc, &block, size, w_16, align) < 0) {
snd_gf1_mem_lock(alloc, 1);
return NULL;
}
if (share_id != NULL)
memcpy(&block.share_id, share_id, sizeof(block.share_id));
block.owner = owner;
block.name = kstrdup(name, GFP_KERNEL);
nblock = snd_gf1_mem_xalloc(alloc, &block);
snd_gf1_mem_lock(alloc, 1);
return nblock;
}
int snd_gf1_mem_free(struct snd_gf1_mem * alloc, unsigned int address)
{
int result;
struct snd_gf1_mem_block *block;
snd_gf1_mem_lock(alloc, 0);
if ((block = snd_gf1_mem_look(alloc, address)) != NULL) {
result = snd_gf1_mem_xfree(alloc, block);
snd_gf1_mem_lock(alloc, 1);
return result;
}
snd_gf1_mem_lock(alloc, 1);
return -EINVAL;
}
int snd_gf1_mem_init(struct snd_gus_card * gus)
{
struct snd_gf1_mem *alloc;
struct snd_gf1_mem_block block;
#ifdef CONFIG_SND_DEBUG
struct snd_info_entry *entry;
#endif
alloc = &gus->gf1.mem_alloc;
mutex_init(&alloc->memory_mutex);
alloc->first = alloc->last = NULL;
if (!gus->gf1.memory)
return 0;
memset(&block, 0, sizeof(block));
block.owner = SNDRV_GF1_MEM_OWNER_DRIVER;
if (gus->gf1.enh_mode) {
block.ptr = 0;
block.size = 1024;
block.name = kstrdup("InterWave LFOs", GFP_KERNEL);
if (snd_gf1_mem_xalloc(alloc, &block) == NULL)
return -ENOMEM;
}
block.ptr = gus->gf1.default_voice_address;
block.size = 4;
block.name = kstrdup("Voice default (NULL's)", GFP_KERNEL);
if (snd_gf1_mem_xalloc(alloc, &block) == NULL)
return -ENOMEM;
#ifdef CONFIG_SND_DEBUG
if (! snd_card_proc_new(gus->card, "gusmem", &entry))
snd_info_set_text_ops(entry, gus, snd_gf1_mem_info_read);
#endif
return 0;
}
int snd_gf1_mem_done(struct snd_gus_card * gus)
{
struct snd_gf1_mem *alloc;
struct snd_gf1_mem_block *block, *nblock;
alloc = &gus->gf1.mem_alloc;
block = alloc->first;
while (block) {
nblock = block->next;
snd_gf1_mem_xfree(alloc, block);
block = nblock;
}
return 0;
}
#ifdef CONFIG_SND_DEBUG
static void snd_gf1_mem_info_read(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
struct snd_gus_card *gus;
struct snd_gf1_mem *alloc;
struct snd_gf1_mem_block *block;
unsigned int total, used;
int i;
gus = entry->private_data;
alloc = &gus->gf1.mem_alloc;
mutex_lock(&alloc->memory_mutex);
snd_iprintf(buffer, "8-bit banks : \n ");
for (i = 0; i < 4; i++)
snd_iprintf(buffer, "0x%06x (%04ik)%s", alloc->banks_8[i].address, alloc->banks_8[i].size >> 10, i + 1 < 4 ? "," : "");
snd_iprintf(buffer, "\n"
"16-bit banks : \n ");
for (i = total = 0; i < 4; i++) {
snd_iprintf(buffer, "0x%06x (%04ik)%s", alloc->banks_16[i].address, alloc->banks_16[i].size >> 10, i + 1 < 4 ? "," : "");
total += alloc->banks_16[i].size;
}
snd_iprintf(buffer, "\n");
used = 0;
for (block = alloc->first, i = 0; block; block = block->next, i++) {
used += block->size;
snd_iprintf(buffer, "Block %i at 0x%lx onboard 0x%x size %i (0x%x):\n", i, (long) block, block->ptr, block->size, block->size);
if (block->share ||
block->share_id[0] || block->share_id[1] ||
block->share_id[2] || block->share_id[3])
snd_iprintf(buffer, " Share : %i [id0 0x%x] [id1 0x%x] [id2 0x%x] [id3 0x%x]\n",
block->share,
block->share_id[0], block->share_id[1],
block->share_id[2], block->share_id[3]);
snd_iprintf(buffer, " Flags :%s\n",
block->flags & SNDRV_GF1_MEM_BLOCK_16BIT ? " 16-bit" : "");
snd_iprintf(buffer, " Owner : ");
switch (block->owner) {
case SNDRV_GF1_MEM_OWNER_DRIVER:
snd_iprintf(buffer, "driver - %s\n", block->name);
break;
case SNDRV_GF1_MEM_OWNER_WAVE_SIMPLE:
snd_iprintf(buffer, "SIMPLE wave\n");
break;
case SNDRV_GF1_MEM_OWNER_WAVE_GF1:
snd_iprintf(buffer, "GF1 wave\n");
break;
case SNDRV_GF1_MEM_OWNER_WAVE_IWFFFF:
snd_iprintf(buffer, "IWFFFF wave\n");
break;
default:
snd_iprintf(buffer, "unknown\n");
}
}
snd_iprintf(buffer, " Total: memory = %i, used = %i, free = %i\n",
total, used, total - used);
mutex_unlock(&alloc->memory_mutex);
#if 0
ultra_iprintf(buffer, " Verify: free = %i, max 8-bit block = %i, max 16-bit block = %i\n",
ultra_memory_free_size(card, &card->gf1.mem_alloc),
ultra_memory_free_block(card, &card->gf1.mem_alloc, 0),
ultra_memory_free_block(card, &card->gf1.mem_alloc, 1));
#endif
}
#endif
| gpl-2.0 |
ngvincent/android-kernel-oppo-find5 | drivers/uwb/i1480/dfu/mac.c | 14058 | 14012 | /*
* Intel Wireless UWB Link 1480
* MAC Firmware upload implementation
*
* Copyright (C) 2005-2006 Intel Corporation
* Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*
* Implementation of the code for parsing the firmware file (extract
* the headers and binary code chunks) in the fw_*() functions. The
* code to upload pre and mac firmwares is the same, so it uses a
* common entry point in __mac_fw_upload(), which uses the i1480
* function pointers to push the firmware to the device.
*/
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/uwb.h>
#include "i1480-dfu.h"
/*
* Descriptor for a continuous segment of MAC fw data
*/
struct fw_hdr {
unsigned long address;
size_t length;
const u32 *bin;
struct fw_hdr *next;
};
/* Free a chain of firmware headers */
static
void fw_hdrs_free(struct fw_hdr *hdr)
{
struct fw_hdr *next;
while (hdr) {
next = hdr->next;
kfree(hdr);
hdr = next;
}
}
/* Fill a firmware header descriptor from a memory buffer */
static
int fw_hdr_load(struct i1480 *i1480, struct fw_hdr *hdr, unsigned hdr_cnt,
const char *_data, const u32 *data_itr, const u32 *data_top)
{
size_t hdr_offset = (const char *) data_itr - _data;
size_t remaining_size = (void *) data_top - (void *) data_itr;
if (data_itr + 2 > data_top) {
dev_err(i1480->dev, "fw hdr #%u/%zu: EOF reached in header at "
"offset %zu, limit %zu\n",
hdr_cnt, hdr_offset,
(const char *) data_itr + 2 - _data,
(const char *) data_top - _data);
return -EINVAL;
}
hdr->next = NULL;
hdr->address = le32_to_cpu(*data_itr++);
hdr->length = le32_to_cpu(*data_itr++);
hdr->bin = data_itr;
if (hdr->length > remaining_size) {
dev_err(i1480->dev, "fw hdr #%u/%zu: EOF reached in data; "
"chunk too long (%zu bytes), only %zu left\n",
hdr_cnt, hdr_offset, hdr->length, remaining_size);
return -EINVAL;
}
return 0;
}
/**
* Get a buffer where the firmware is supposed to be and create a
* chain of headers linking them together.
*
* @phdr: where to place the pointer to the first header (headers link
* to the next via the @hdr->next ptr); need to free the whole
* chain when done.
*
* @_data: Pointer to the data buffer.
*
* @_data_size: Size of the data buffer (bytes); data size has to be a
* multiple of 4. Function will fail if not.
*
* Goes over the whole binary blob; reads the first chunk and creates
* a fw hdr from it (which points to where the data is in @_data and
* the length of the chunk); then goes on to the next chunk until
* done. Each header is linked to the next.
*/
static
int fw_hdrs_load(struct i1480 *i1480, struct fw_hdr **phdr,
const char *_data, size_t data_size)
{
int result;
unsigned hdr_cnt = 0;
u32 *data = (u32 *) _data, *data_itr, *data_top;
struct fw_hdr *hdr, **prev_hdr = phdr;
result = -EINVAL;
/* Check size is ok and pointer is aligned */
if (data_size % sizeof(u32) != 0)
goto error;
if ((unsigned long) _data % sizeof(u16) != 0)
goto error;
*phdr = NULL;
data_itr = data;
data_top = (u32 *) (_data + data_size);
while (data_itr < data_top) {
result = -ENOMEM;
hdr = kmalloc(sizeof(*hdr), GFP_KERNEL);
if (hdr == NULL) {
dev_err(i1480->dev, "Cannot allocate fw header "
"for chunk #%u\n", hdr_cnt);
goto error_alloc;
}
result = fw_hdr_load(i1480, hdr, hdr_cnt,
_data, data_itr, data_top);
if (result < 0)
goto error_load;
data_itr += 2 + hdr->length;
*prev_hdr = hdr;
prev_hdr = &hdr->next;
hdr_cnt++;
};
*prev_hdr = NULL;
return 0;
error_load:
kfree(hdr);
error_alloc:
fw_hdrs_free(*phdr);
error:
return result;
}
/**
* Compares a chunk of fw with one in the devices's memory
*
* @i1480: Device instance
* @hdr: Pointer to the firmware chunk
* @returns: 0 if equal, < 0 errno on error. If > 0, it is the offset
* where the difference was found (plus one).
*
* Kind of dirty and simplistic, but does the trick in both the PCI
* and USB version. We do a quick[er] memcmp(), and if it fails, we do
* a byte-by-byte to find the offset.
*/
static
ssize_t i1480_fw_cmp(struct i1480 *i1480, struct fw_hdr *hdr)
{
ssize_t result = 0;
u32 src_itr = 0, cnt;
size_t size = hdr->length*sizeof(hdr->bin[0]);
size_t chunk_size;
u8 *bin = (u8 *) hdr->bin;
while (size > 0) {
chunk_size = size < i1480->buf_size ? size : i1480->buf_size;
result = i1480->read(i1480, hdr->address + src_itr, chunk_size);
if (result < 0) {
dev_err(i1480->dev, "error reading for verification: "
"%zd\n", result);
goto error;
}
if (memcmp(i1480->cmd_buf, bin + src_itr, result)) {
u8 *buf = i1480->cmd_buf;
for (cnt = 0; cnt < result; cnt++)
if (bin[src_itr + cnt] != buf[cnt]) {
dev_err(i1480->dev, "byte failed at "
"src_itr %u cnt %u [0x%02x "
"vs 0x%02x]\n", src_itr, cnt,
bin[src_itr + cnt], buf[cnt]);
result = src_itr + cnt + 1;
goto cmp_failed;
}
}
src_itr += result;
size -= result;
}
result = 0;
error:
cmp_failed:
return result;
}
/**
* Writes firmware headers to the device.
*
* @prd: PRD instance
* @hdr: Processed firmware
* @returns: 0 if ok, < 0 errno on error.
*/
static
int mac_fw_hdrs_push(struct i1480 *i1480, struct fw_hdr *hdr,
const char *fw_name, const char *fw_tag)
{
struct device *dev = i1480->dev;
ssize_t result = 0;
struct fw_hdr *hdr_itr;
int verif_retry_count;
/* Now, header by header, push them to the hw */
for (hdr_itr = hdr; hdr_itr != NULL; hdr_itr = hdr_itr->next) {
verif_retry_count = 0;
retry:
dev_dbg(dev, "fw chunk (%zu @ 0x%08lx)\n",
hdr_itr->length * sizeof(hdr_itr->bin[0]),
hdr_itr->address);
result = i1480->write(i1480, hdr_itr->address, hdr_itr->bin,
hdr_itr->length*sizeof(hdr_itr->bin[0]));
if (result < 0) {
dev_err(dev, "%s fw '%s': write failed (%zuB @ 0x%lx):"
" %zd\n", fw_tag, fw_name,
hdr_itr->length * sizeof(hdr_itr->bin[0]),
hdr_itr->address, result);
break;
}
result = i1480_fw_cmp(i1480, hdr_itr);
if (result < 0) {
dev_err(dev, "%s fw '%s': verification read "
"failed (%zuB @ 0x%lx): %zd\n",
fw_tag, fw_name,
hdr_itr->length * sizeof(hdr_itr->bin[0]),
hdr_itr->address, result);
break;
}
if (result > 0) { /* Offset where it failed + 1 */
result--;
dev_err(dev, "%s fw '%s': WARNING: verification "
"failed at 0x%lx: retrying\n",
fw_tag, fw_name, hdr_itr->address + result);
if (++verif_retry_count < 3)
goto retry; /* write this block again! */
dev_err(dev, "%s fw '%s': verification failed at 0x%lx: "
"tried %d times\n", fw_tag, fw_name,
hdr_itr->address + result, verif_retry_count);
result = -EINVAL;
break;
}
}
return result;
}
/** Puts the device in firmware upload mode.*/
static
int mac_fw_upload_enable(struct i1480 *i1480)
{
int result;
u32 reg = 0x800000c0;
u32 *buffer = (u32 *)i1480->cmd_buf;
if (i1480->hw_rev > 1)
reg = 0x8000d0d4;
result = i1480->read(i1480, reg, sizeof(u32));
if (result < 0)
goto error_cmd;
*buffer &= ~i1480_FW_UPLOAD_MODE_MASK;
result = i1480->write(i1480, reg, buffer, sizeof(u32));
if (result < 0)
goto error_cmd;
return 0;
error_cmd:
dev_err(i1480->dev, "can't enable fw upload mode: %d\n", result);
return result;
}
/** Gets the device out of firmware upload mode. */
static
int mac_fw_upload_disable(struct i1480 *i1480)
{
int result;
u32 reg = 0x800000c0;
u32 *buffer = (u32 *)i1480->cmd_buf;
if (i1480->hw_rev > 1)
reg = 0x8000d0d4;
result = i1480->read(i1480, reg, sizeof(u32));
if (result < 0)
goto error_cmd;
*buffer |= i1480_FW_UPLOAD_MODE_MASK;
result = i1480->write(i1480, reg, buffer, sizeof(u32));
if (result < 0)
goto error_cmd;
return 0;
error_cmd:
dev_err(i1480->dev, "can't disable fw upload mode: %d\n", result);
return result;
}
/**
* Generic function for uploading a MAC firmware.
*
* @i1480: Device instance
* @fw_name: Name of firmware file to upload.
* @fw_tag: Name of the firmware type (for messages)
* [eg: MAC, PRE]
* @do_wait: Wait for device to emit initialization done message (0
* for PRE fws, 1 for MAC fws).
* @returns: 0 if ok, < 0 errno on error.
*/
static
int __mac_fw_upload(struct i1480 *i1480, const char *fw_name,
const char *fw_tag)
{
int result;
const struct firmware *fw;
struct fw_hdr *fw_hdrs;
result = request_firmware(&fw, fw_name, i1480->dev);
if (result < 0) /* Up to caller to complain on -ENOENT */
goto out;
result = fw_hdrs_load(i1480, &fw_hdrs, fw->data, fw->size);
if (result < 0) {
dev_err(i1480->dev, "%s fw '%s': failed to parse firmware "
"file: %d\n", fw_tag, fw_name, result);
goto out_release;
}
result = mac_fw_upload_enable(i1480);
if (result < 0)
goto out_hdrs_release;
result = mac_fw_hdrs_push(i1480, fw_hdrs, fw_name, fw_tag);
mac_fw_upload_disable(i1480);
out_hdrs_release:
if (result >= 0)
dev_info(i1480->dev, "%s fw '%s': uploaded\n", fw_tag, fw_name);
else
dev_err(i1480->dev, "%s fw '%s': failed to upload (%d), "
"power cycle device\n", fw_tag, fw_name, result);
fw_hdrs_free(fw_hdrs);
out_release:
release_firmware(fw);
out:
return result;
}
/**
* Upload a pre-PHY firmware
*
*/
int i1480_pre_fw_upload(struct i1480 *i1480)
{
int result;
result = __mac_fw_upload(i1480, i1480->pre_fw_name, "PRE");
if (result == 0)
msleep(400);
return result;
}
/**
* Reset a the MAC and PHY
*
* @i1480: Device's instance
* @returns: 0 if ok, < 0 errno code on error
*
* We put the command on kmalloc'ed memory as some arches cannot do
* USB from the stack. The reply event is copied from an stage buffer,
* so it can be in the stack. See WUSB1.0[8.6.2.4] for more details.
*
* We issue the reset to make sure the UWB controller reinits the PHY;
* this way we can now if the PHY init went ok.
*/
static
int i1480_cmd_reset(struct i1480 *i1480)
{
int result;
struct uwb_rccb *cmd = (void *) i1480->cmd_buf;
struct i1480_evt_reset {
struct uwb_rceb rceb;
u8 bResultCode;
} __attribute__((packed)) *reply = (void *) i1480->evt_buf;
result = -ENOMEM;
cmd->bCommandType = UWB_RC_CET_GENERAL;
cmd->wCommand = cpu_to_le16(UWB_RC_CMD_RESET);
reply->rceb.bEventType = UWB_RC_CET_GENERAL;
reply->rceb.wEvent = UWB_RC_CMD_RESET;
result = i1480_cmd(i1480, "RESET", sizeof(*cmd), sizeof(*reply));
if (result < 0)
goto out;
if (reply->bResultCode != UWB_RC_RES_SUCCESS) {
dev_err(i1480->dev, "RESET: command execution failed: %u\n",
reply->bResultCode);
result = -EIO;
}
out:
return result;
}
/* Wait for the MAC FW to start running */
static
int i1480_fw_is_running_q(struct i1480 *i1480)
{
int cnt = 0;
int result;
u32 *val = (u32 *) i1480->cmd_buf;
for (cnt = 0; cnt < 10; cnt++) {
msleep(100);
result = i1480->read(i1480, 0x80080000, 4);
if (result < 0) {
dev_err(i1480->dev, "Can't read 0x8008000: %d\n", result);
goto out;
}
if (*val == 0x55555555UL) /* fw running? cool */
goto out;
}
dev_err(i1480->dev, "Timed out waiting for fw to start\n");
result = -ETIMEDOUT;
out:
return result;
}
/**
* Upload MAC firmware, wait for it to start
*
* @i1480: Device instance
* @fw_name: Name of the file that contains the firmware
*
* This has to be called after the pre fw has been uploaded (if
* there is any).
*/
int i1480_mac_fw_upload(struct i1480 *i1480)
{
int result = 0, deprecated_name = 0;
struct i1480_rceb *rcebe = (void *) i1480->evt_buf;
result = __mac_fw_upload(i1480, i1480->mac_fw_name, "MAC");
if (result == -ENOENT) {
result = __mac_fw_upload(i1480, i1480->mac_fw_name_deprecate,
"MAC");
deprecated_name = 1;
}
if (result < 0)
return result;
if (deprecated_name == 1)
dev_warn(i1480->dev,
"WARNING: firmware file name %s is deprecated, "
"please rename to %s\n",
i1480->mac_fw_name_deprecate, i1480->mac_fw_name);
result = i1480_fw_is_running_q(i1480);
if (result < 0)
goto error_fw_not_running;
result = i1480->rc_setup ? i1480->rc_setup(i1480) : 0;
if (result < 0) {
dev_err(i1480->dev, "Cannot setup after MAC fw upload: %d\n",
result);
goto error_setup;
}
result = i1480->wait_init_done(i1480); /* wait init'on */
if (result < 0) {
dev_err(i1480->dev, "MAC fw '%s': Initialization timed out "
"(%d)\n", i1480->mac_fw_name, result);
goto error_init_timeout;
}
/* verify we got the right initialization done event */
if (i1480->evt_result != sizeof(*rcebe)) {
dev_err(i1480->dev, "MAC fw '%s': initialization event returns "
"wrong size (%zu bytes vs %zu needed)\n",
i1480->mac_fw_name, i1480->evt_result, sizeof(*rcebe));
goto error_size;
}
result = -EIO;
if (i1480_rceb_check(i1480, &rcebe->rceb, NULL, 0, i1480_CET_VS1,
i1480_EVT_RM_INIT_DONE) < 0) {
dev_err(i1480->dev, "wrong initialization event 0x%02x/%04x/%02x "
"received; expected 0x%02x/%04x/00\n",
rcebe->rceb.bEventType, le16_to_cpu(rcebe->rceb.wEvent),
rcebe->rceb.bEventContext, i1480_CET_VS1,
i1480_EVT_RM_INIT_DONE);
goto error_init_timeout;
}
result = i1480_cmd_reset(i1480);
if (result < 0)
dev_err(i1480->dev, "MAC fw '%s': MBOA reset failed (%d)\n",
i1480->mac_fw_name, result);
error_fw_not_running:
error_init_timeout:
error_size:
error_setup:
return result;
}
| gpl-2.0 |
hpzhong/linux-stable | drivers/char/tpm/tpm-interface.c | 747 | 26064 | /*
* Copyright (C) 2004 IBM Corporation
* Copyright (C) 2014 Intel Corporation
*
* Authors:
* Leendert van Doorn <leendert@watson.ibm.com>
* Dave Safford <safford@watson.ibm.com>
* Reiner Sailer <sailer@watson.ibm.com>
* Kylene Hall <kjhall@us.ibm.com>
*
* Maintained by: <tpmdd-devel@lists.sourceforge.net>
*
* Device driver for TCG/TCPA TPM (trusted platform module).
* Specifications at www.trustedcomputinggroup.org
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation, version 2 of the
* License.
*
* Note, the TPM chip is not interrupt driven (only polling)
* and can have very long timeouts (minutes!). Hence the unusual
* calls to msleep.
*
*/
#include <linux/poll.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <linux/freezer.h>
#include "tpm.h"
#include "tpm_eventlog.h"
#define TPM_MAX_ORDINAL 243
#define TSC_MAX_ORDINAL 12
#define TPM_PROTECTED_COMMAND 0x00
#define TPM_CONNECTION_COMMAND 0x40
/*
* Bug workaround - some TPM's don't flush the most
* recently changed pcr on suspend, so force the flush
* with an extend to the selected _unused_ non-volatile pcr.
*/
static int tpm_suspend_pcr;
module_param_named(suspend_pcr, tpm_suspend_pcr, uint, 0644);
MODULE_PARM_DESC(suspend_pcr,
"PCR to use for dummy writes to faciltate flush on suspend.");
/*
* Array with one entry per ordinal defining the maximum amount
* of time the chip could take to return the result. The ordinal
* designation of short, medium or long is defined in a table in
* TCG Specification TPM Main Part 2 TPM Structures Section 17. The
* values of the SHORT, MEDIUM, and LONG durations are retrieved
* from the chip during initialization with a call to tpm_get_timeouts.
*/
static const u8 tpm_ordinal_duration[TPM_MAX_ORDINAL] = {
TPM_UNDEFINED, /* 0 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 5 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 10 */
TPM_SHORT,
TPM_MEDIUM,
TPM_LONG,
TPM_LONG,
TPM_MEDIUM, /* 15 */
TPM_SHORT,
TPM_SHORT,
TPM_MEDIUM,
TPM_LONG,
TPM_SHORT, /* 20 */
TPM_SHORT,
TPM_MEDIUM,
TPM_MEDIUM,
TPM_MEDIUM,
TPM_SHORT, /* 25 */
TPM_SHORT,
TPM_MEDIUM,
TPM_SHORT,
TPM_SHORT,
TPM_MEDIUM, /* 30 */
TPM_LONG,
TPM_MEDIUM,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT, /* 35 */
TPM_MEDIUM,
TPM_MEDIUM,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_MEDIUM, /* 40 */
TPM_LONG,
TPM_MEDIUM,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT, /* 45 */
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_LONG,
TPM_MEDIUM, /* 50 */
TPM_MEDIUM,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 55 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_MEDIUM, /* 60 */
TPM_MEDIUM,
TPM_MEDIUM,
TPM_SHORT,
TPM_SHORT,
TPM_MEDIUM, /* 65 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 70 */
TPM_SHORT,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 75 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_LONG, /* 80 */
TPM_UNDEFINED,
TPM_MEDIUM,
TPM_LONG,
TPM_SHORT,
TPM_UNDEFINED, /* 85 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 90 */
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_UNDEFINED, /* 95 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_MEDIUM, /* 100 */
TPM_SHORT,
TPM_SHORT,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 105 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 110 */
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT, /* 115 */
TPM_SHORT,
TPM_SHORT,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_LONG, /* 120 */
TPM_LONG,
TPM_MEDIUM,
TPM_UNDEFINED,
TPM_SHORT,
TPM_SHORT, /* 125 */
TPM_SHORT,
TPM_LONG,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT, /* 130 */
TPM_MEDIUM,
TPM_UNDEFINED,
TPM_SHORT,
TPM_MEDIUM,
TPM_UNDEFINED, /* 135 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 140 */
TPM_SHORT,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 145 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 150 */
TPM_MEDIUM,
TPM_MEDIUM,
TPM_SHORT,
TPM_SHORT,
TPM_UNDEFINED, /* 155 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 160 */
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 165 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_LONG, /* 170 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 175 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_MEDIUM, /* 180 */
TPM_SHORT,
TPM_MEDIUM,
TPM_MEDIUM,
TPM_MEDIUM,
TPM_MEDIUM, /* 185 */
TPM_SHORT,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 190 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 195 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 200 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT,
TPM_SHORT, /* 205 */
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_MEDIUM, /* 210 */
TPM_UNDEFINED,
TPM_MEDIUM,
TPM_MEDIUM,
TPM_MEDIUM,
TPM_UNDEFINED, /* 215 */
TPM_MEDIUM,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT,
TPM_SHORT, /* 220 */
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_SHORT,
TPM_UNDEFINED, /* 225 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 230 */
TPM_LONG,
TPM_MEDIUM,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED, /* 235 */
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_UNDEFINED,
TPM_SHORT, /* 240 */
TPM_UNDEFINED,
TPM_MEDIUM,
};
/*
* Returns max number of jiffies to wait
*/
unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip,
u32 ordinal)
{
int duration_idx = TPM_UNDEFINED;
int duration = 0;
u8 category = (ordinal >> 24) & 0xFF;
if ((category == TPM_PROTECTED_COMMAND && ordinal < TPM_MAX_ORDINAL) ||
(category == TPM_CONNECTION_COMMAND && ordinal < TSC_MAX_ORDINAL))
duration_idx = tpm_ordinal_duration[ordinal];
if (duration_idx != TPM_UNDEFINED)
duration = chip->vendor.duration[duration_idx];
if (duration <= 0)
return 2 * 60 * HZ;
else
return duration;
}
EXPORT_SYMBOL_GPL(tpm_calc_ordinal_duration);
/*
* Internal kernel interface to transmit TPM commands
*/
ssize_t tpm_transmit(struct tpm_chip *chip, const char *buf,
size_t bufsiz)
{
ssize_t rc;
u32 count, ordinal;
unsigned long stop;
if (bufsiz > TPM_BUFSIZE)
bufsiz = TPM_BUFSIZE;
count = be32_to_cpu(*((__be32 *) (buf + 2)));
ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
if (count == 0)
return -ENODATA;
if (count > bufsiz) {
dev_err(chip->pdev,
"invalid count value %x %zx\n", count, bufsiz);
return -E2BIG;
}
mutex_lock(&chip->tpm_mutex);
rc = chip->ops->send(chip, (u8 *) buf, count);
if (rc < 0) {
dev_err(chip->pdev,
"tpm_transmit: tpm_send: error %zd\n", rc);
goto out;
}
if (chip->vendor.irq)
goto out_recv;
if (chip->flags & TPM_CHIP_FLAG_TPM2)
stop = jiffies + tpm2_calc_ordinal_duration(chip, ordinal);
else
stop = jiffies + tpm_calc_ordinal_duration(chip, ordinal);
do {
u8 status = chip->ops->status(chip);
if ((status & chip->ops->req_complete_mask) ==
chip->ops->req_complete_val)
goto out_recv;
if (chip->ops->req_canceled(chip, status)) {
dev_err(chip->pdev, "Operation Canceled\n");
rc = -ECANCELED;
goto out;
}
msleep(TPM_TIMEOUT); /* CHECK */
rmb();
} while (time_before(jiffies, stop));
chip->ops->cancel(chip);
dev_err(chip->pdev, "Operation Timed out\n");
rc = -ETIME;
goto out;
out_recv:
rc = chip->ops->recv(chip, (u8 *) buf, bufsiz);
if (rc < 0)
dev_err(chip->pdev,
"tpm_transmit: tpm_recv: error %zd\n", rc);
out:
mutex_unlock(&chip->tpm_mutex);
return rc;
}
#define TPM_DIGEST_SIZE 20
#define TPM_RET_CODE_IDX 6
ssize_t tpm_transmit_cmd(struct tpm_chip *chip, void *cmd,
int len, const char *desc)
{
struct tpm_output_header *header;
int err;
len = tpm_transmit(chip, (u8 *) cmd, len);
if (len < 0)
return len;
else if (len < TPM_HEADER_SIZE)
return -EFAULT;
header = cmd;
err = be32_to_cpu(header->return_code);
if (err != 0 && desc)
dev_err(chip->pdev, "A TPM error (%d) occurred %s\n", err,
desc);
return err;
}
#define TPM_INTERNAL_RESULT_SIZE 200
#define TPM_ORD_GET_CAP cpu_to_be32(101)
#define TPM_ORD_GET_RANDOM cpu_to_be32(70)
static const struct tpm_input_header tpm_getcap_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(22),
.ordinal = TPM_ORD_GET_CAP
};
ssize_t tpm_getcap(struct device *dev, __be32 subcap_id, cap_t *cap,
const char *desc)
{
struct tpm_cmd_t tpm_cmd;
int rc;
struct tpm_chip *chip = dev_get_drvdata(dev);
tpm_cmd.header.in = tpm_getcap_header;
if (subcap_id == CAP_VERSION_1_1 || subcap_id == CAP_VERSION_1_2) {
tpm_cmd.params.getcap_in.cap = subcap_id;
/*subcap field not necessary */
tpm_cmd.params.getcap_in.subcap_size = cpu_to_be32(0);
tpm_cmd.header.in.length -= cpu_to_be32(sizeof(__be32));
} else {
if (subcap_id == TPM_CAP_FLAG_PERM ||
subcap_id == TPM_CAP_FLAG_VOL)
tpm_cmd.params.getcap_in.cap = TPM_CAP_FLAG;
else
tpm_cmd.params.getcap_in.cap = TPM_CAP_PROP;
tpm_cmd.params.getcap_in.subcap_size = cpu_to_be32(4);
tpm_cmd.params.getcap_in.subcap = subcap_id;
}
rc = tpm_transmit_cmd(chip, &tpm_cmd, TPM_INTERNAL_RESULT_SIZE, desc);
if (!rc)
*cap = tpm_cmd.params.getcap_out.cap;
return rc;
}
void tpm_gen_interrupt(struct tpm_chip *chip)
{
struct tpm_cmd_t tpm_cmd;
ssize_t rc;
tpm_cmd.header.in = tpm_getcap_header;
tpm_cmd.params.getcap_in.cap = TPM_CAP_PROP;
tpm_cmd.params.getcap_in.subcap_size = cpu_to_be32(4);
tpm_cmd.params.getcap_in.subcap = TPM_CAP_PROP_TIS_TIMEOUT;
rc = tpm_transmit_cmd(chip, &tpm_cmd, TPM_INTERNAL_RESULT_SIZE,
"attempting to determine the timeouts");
}
EXPORT_SYMBOL_GPL(tpm_gen_interrupt);
#define TPM_ORD_STARTUP cpu_to_be32(153)
#define TPM_ST_CLEAR cpu_to_be16(1)
#define TPM_ST_STATE cpu_to_be16(2)
#define TPM_ST_DEACTIVATED cpu_to_be16(3)
static const struct tpm_input_header tpm_startup_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(12),
.ordinal = TPM_ORD_STARTUP
};
static int tpm_startup(struct tpm_chip *chip, __be16 startup_type)
{
struct tpm_cmd_t start_cmd;
start_cmd.header.in = tpm_startup_header;
start_cmd.params.startup_in.startup_type = startup_type;
return tpm_transmit_cmd(chip, &start_cmd, TPM_INTERNAL_RESULT_SIZE,
"attempting to start the TPM");
}
int tpm_get_timeouts(struct tpm_chip *chip)
{
struct tpm_cmd_t tpm_cmd;
unsigned long new_timeout[4];
unsigned long old_timeout[4];
struct duration_t *duration_cap;
ssize_t rc;
tpm_cmd.header.in = tpm_getcap_header;
tpm_cmd.params.getcap_in.cap = TPM_CAP_PROP;
tpm_cmd.params.getcap_in.subcap_size = cpu_to_be32(4);
tpm_cmd.params.getcap_in.subcap = TPM_CAP_PROP_TIS_TIMEOUT;
rc = tpm_transmit_cmd(chip, &tpm_cmd, TPM_INTERNAL_RESULT_SIZE, NULL);
if (rc == TPM_ERR_INVALID_POSTINIT) {
/* The TPM is not started, we are the first to talk to it.
Execute a startup command. */
dev_info(chip->pdev, "Issuing TPM_STARTUP");
if (tpm_startup(chip, TPM_ST_CLEAR))
return rc;
tpm_cmd.header.in = tpm_getcap_header;
tpm_cmd.params.getcap_in.cap = TPM_CAP_PROP;
tpm_cmd.params.getcap_in.subcap_size = cpu_to_be32(4);
tpm_cmd.params.getcap_in.subcap = TPM_CAP_PROP_TIS_TIMEOUT;
rc = tpm_transmit_cmd(chip, &tpm_cmd, TPM_INTERNAL_RESULT_SIZE,
NULL);
}
if (rc) {
dev_err(chip->pdev,
"A TPM error (%zd) occurred attempting to determine the timeouts\n",
rc);
goto duration;
}
if (be32_to_cpu(tpm_cmd.header.out.return_code) != 0 ||
be32_to_cpu(tpm_cmd.header.out.length)
!= sizeof(tpm_cmd.header.out) + sizeof(u32) + 4 * sizeof(u32))
return -EINVAL;
old_timeout[0] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.a);
old_timeout[1] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.b);
old_timeout[2] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.c);
old_timeout[3] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.d);
memcpy(new_timeout, old_timeout, sizeof(new_timeout));
/*
* Provide ability for vendor overrides of timeout values in case
* of misreporting.
*/
if (chip->ops->update_timeouts != NULL)
chip->vendor.timeout_adjusted =
chip->ops->update_timeouts(chip, new_timeout);
if (!chip->vendor.timeout_adjusted) {
/* Don't overwrite default if value is 0 */
if (new_timeout[0] != 0 && new_timeout[0] < 1000) {
int i;
/* timeouts in msec rather usec */
for (i = 0; i != ARRAY_SIZE(new_timeout); i++)
new_timeout[i] *= 1000;
chip->vendor.timeout_adjusted = true;
}
}
/* Report adjusted timeouts */
if (chip->vendor.timeout_adjusted) {
dev_info(chip->pdev,
HW_ERR "Adjusting reported timeouts: A %lu->%luus B %lu->%luus C %lu->%luus D %lu->%luus\n",
old_timeout[0], new_timeout[0],
old_timeout[1], new_timeout[1],
old_timeout[2], new_timeout[2],
old_timeout[3], new_timeout[3]);
}
chip->vendor.timeout_a = usecs_to_jiffies(new_timeout[0]);
chip->vendor.timeout_b = usecs_to_jiffies(new_timeout[1]);
chip->vendor.timeout_c = usecs_to_jiffies(new_timeout[2]);
chip->vendor.timeout_d = usecs_to_jiffies(new_timeout[3]);
duration:
tpm_cmd.header.in = tpm_getcap_header;
tpm_cmd.params.getcap_in.cap = TPM_CAP_PROP;
tpm_cmd.params.getcap_in.subcap_size = cpu_to_be32(4);
tpm_cmd.params.getcap_in.subcap = TPM_CAP_PROP_TIS_DURATION;
rc = tpm_transmit_cmd(chip, &tpm_cmd, TPM_INTERNAL_RESULT_SIZE,
"attempting to determine the durations");
if (rc)
return rc;
if (be32_to_cpu(tpm_cmd.header.out.return_code) != 0 ||
be32_to_cpu(tpm_cmd.header.out.length)
!= sizeof(tpm_cmd.header.out) + sizeof(u32) + 3 * sizeof(u32))
return -EINVAL;
duration_cap = &tpm_cmd.params.getcap_out.cap.duration;
chip->vendor.duration[TPM_SHORT] =
usecs_to_jiffies(be32_to_cpu(duration_cap->tpm_short));
chip->vendor.duration[TPM_MEDIUM] =
usecs_to_jiffies(be32_to_cpu(duration_cap->tpm_medium));
chip->vendor.duration[TPM_LONG] =
usecs_to_jiffies(be32_to_cpu(duration_cap->tpm_long));
/* The Broadcom BCM0102 chipset in a Dell Latitude D820 gets the above
* value wrong and apparently reports msecs rather than usecs. So we
* fix up the resulting too-small TPM_SHORT value to make things work.
* We also scale the TPM_MEDIUM and -_LONG values by 1000.
*/
if (chip->vendor.duration[TPM_SHORT] < (HZ / 100)) {
chip->vendor.duration[TPM_SHORT] = HZ;
chip->vendor.duration[TPM_MEDIUM] *= 1000;
chip->vendor.duration[TPM_LONG] *= 1000;
chip->vendor.duration_adjusted = true;
dev_info(chip->pdev, "Adjusting TPM timeout parameters.");
}
return 0;
}
EXPORT_SYMBOL_GPL(tpm_get_timeouts);
#define TPM_ORD_CONTINUE_SELFTEST 83
#define CONTINUE_SELFTEST_RESULT_SIZE 10
static struct tpm_input_header continue_selftest_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(10),
.ordinal = cpu_to_be32(TPM_ORD_CONTINUE_SELFTEST),
};
/**
* tpm_continue_selftest -- run TPM's selftest
* @chip: TPM chip to use
*
* Returns 0 on success, < 0 in case of fatal error or a value > 0 representing
* a TPM error code.
*/
static int tpm_continue_selftest(struct tpm_chip *chip)
{
int rc;
struct tpm_cmd_t cmd;
cmd.header.in = continue_selftest_header;
rc = tpm_transmit_cmd(chip, &cmd, CONTINUE_SELFTEST_RESULT_SIZE,
"continue selftest");
return rc;
}
#define TPM_ORDINAL_PCRREAD cpu_to_be32(21)
#define READ_PCR_RESULT_SIZE 30
static struct tpm_input_header pcrread_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(14),
.ordinal = TPM_ORDINAL_PCRREAD
};
int tpm_pcr_read_dev(struct tpm_chip *chip, int pcr_idx, u8 *res_buf)
{
int rc;
struct tpm_cmd_t cmd;
cmd.header.in = pcrread_header;
cmd.params.pcrread_in.pcr_idx = cpu_to_be32(pcr_idx);
rc = tpm_transmit_cmd(chip, &cmd, READ_PCR_RESULT_SIZE,
"attempting to read a pcr value");
if (rc == 0)
memcpy(res_buf, cmd.params.pcrread_out.pcr_result,
TPM_DIGEST_SIZE);
return rc;
}
/**
* tpm_pcr_read - read a pcr value
* @chip_num: tpm idx # or ANY
* @pcr_idx: pcr idx to retrieve
* @res_buf: TPM_PCR value
* size of res_buf is 20 bytes (or NULL if you don't care)
*
* The TPM driver should be built-in, but for whatever reason it
* isn't, protect against the chip disappearing, by incrementing
* the module usage count.
*/
int tpm_pcr_read(u32 chip_num, int pcr_idx, u8 *res_buf)
{
struct tpm_chip *chip;
int rc;
chip = tpm_chip_find_get(chip_num);
if (chip == NULL)
return -ENODEV;
if (chip->flags & TPM_CHIP_FLAG_TPM2)
rc = tpm2_pcr_read(chip, pcr_idx, res_buf);
else
rc = tpm_pcr_read_dev(chip, pcr_idx, res_buf);
tpm_chip_put(chip);
return rc;
}
EXPORT_SYMBOL_GPL(tpm_pcr_read);
/**
* tpm_pcr_extend - extend pcr value with hash
* @chip_num: tpm idx # or AN&
* @pcr_idx: pcr idx to extend
* @hash: hash value used to extend pcr value
*
* The TPM driver should be built-in, but for whatever reason it
* isn't, protect against the chip disappearing, by incrementing
* the module usage count.
*/
#define TPM_ORD_PCR_EXTEND cpu_to_be32(20)
#define EXTEND_PCR_RESULT_SIZE 34
static struct tpm_input_header pcrextend_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(34),
.ordinal = TPM_ORD_PCR_EXTEND
};
int tpm_pcr_extend(u32 chip_num, int pcr_idx, const u8 *hash)
{
struct tpm_cmd_t cmd;
int rc;
struct tpm_chip *chip;
chip = tpm_chip_find_get(chip_num);
if (chip == NULL)
return -ENODEV;
if (chip->flags & TPM_CHIP_FLAG_TPM2) {
rc = tpm2_pcr_extend(chip, pcr_idx, hash);
tpm_chip_put(chip);
return rc;
}
cmd.header.in = pcrextend_header;
cmd.params.pcrextend_in.pcr_idx = cpu_to_be32(pcr_idx);
memcpy(cmd.params.pcrextend_in.hash, hash, TPM_DIGEST_SIZE);
rc = tpm_transmit_cmd(chip, &cmd, EXTEND_PCR_RESULT_SIZE,
"attempting extend a PCR value");
tpm_chip_put(chip);
return rc;
}
EXPORT_SYMBOL_GPL(tpm_pcr_extend);
/**
* tpm_do_selftest - have the TPM continue its selftest and wait until it
* can receive further commands
* @chip: TPM chip to use
*
* Returns 0 on success, < 0 in case of fatal error or a value > 0 representing
* a TPM error code.
*/
int tpm_do_selftest(struct tpm_chip *chip)
{
int rc;
unsigned int loops;
unsigned int delay_msec = 100;
unsigned long duration;
struct tpm_cmd_t cmd;
duration = tpm_calc_ordinal_duration(chip, TPM_ORD_CONTINUE_SELFTEST);
loops = jiffies_to_msecs(duration) / delay_msec;
rc = tpm_continue_selftest(chip);
/* This may fail if there was no TPM driver during a suspend/resume
* cycle; some may return 10 (BAD_ORDINAL), others 28 (FAILEDSELFTEST)
*/
if (rc)
return rc;
do {
/* Attempt to read a PCR value */
cmd.header.in = pcrread_header;
cmd.params.pcrread_in.pcr_idx = cpu_to_be32(0);
rc = tpm_transmit(chip, (u8 *) &cmd, READ_PCR_RESULT_SIZE);
/* Some buggy TPMs will not respond to tpm_tis_ready() for
* around 300ms while the self test is ongoing, keep trying
* until the self test duration expires. */
if (rc == -ETIME) {
dev_info(chip->pdev, HW_ERR "TPM command timed out during continue self test");
msleep(delay_msec);
continue;
}
if (rc < TPM_HEADER_SIZE)
return -EFAULT;
rc = be32_to_cpu(cmd.header.out.return_code);
if (rc == TPM_ERR_DISABLED || rc == TPM_ERR_DEACTIVATED) {
dev_info(chip->pdev,
"TPM is disabled/deactivated (0x%X)\n", rc);
/* TPM is disabled and/or deactivated; driver can
* proceed and TPM does handle commands for
* suspend/resume correctly
*/
return 0;
}
if (rc != TPM_WARN_DOING_SELFTEST)
return rc;
msleep(delay_msec);
} while (--loops > 0);
return rc;
}
EXPORT_SYMBOL_GPL(tpm_do_selftest);
int tpm_send(u32 chip_num, void *cmd, size_t buflen)
{
struct tpm_chip *chip;
int rc;
chip = tpm_chip_find_get(chip_num);
if (chip == NULL)
return -ENODEV;
rc = tpm_transmit_cmd(chip, cmd, buflen, "attempting tpm_cmd");
tpm_chip_put(chip);
return rc;
}
EXPORT_SYMBOL_GPL(tpm_send);
static bool wait_for_tpm_stat_cond(struct tpm_chip *chip, u8 mask,
bool check_cancel, bool *canceled)
{
u8 status = chip->ops->status(chip);
*canceled = false;
if ((status & mask) == mask)
return true;
if (check_cancel && chip->ops->req_canceled(chip, status)) {
*canceled = true;
return true;
}
return false;
}
int wait_for_tpm_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout,
wait_queue_head_t *queue, bool check_cancel)
{
unsigned long stop;
long rc;
u8 status;
bool canceled = false;
/* check current status */
status = chip->ops->status(chip);
if ((status & mask) == mask)
return 0;
stop = jiffies + timeout;
if (chip->vendor.irq) {
again:
timeout = stop - jiffies;
if ((long)timeout <= 0)
return -ETIME;
rc = wait_event_interruptible_timeout(*queue,
wait_for_tpm_stat_cond(chip, mask, check_cancel,
&canceled),
timeout);
if (rc > 0) {
if (canceled)
return -ECANCELED;
return 0;
}
if (rc == -ERESTARTSYS && freezing(current)) {
clear_thread_flag(TIF_SIGPENDING);
goto again;
}
} else {
do {
msleep(TPM_TIMEOUT);
status = chip->ops->status(chip);
if ((status & mask) == mask)
return 0;
} while (time_before(jiffies, stop));
}
return -ETIME;
}
EXPORT_SYMBOL_GPL(wait_for_tpm_stat);
#define TPM_ORD_SAVESTATE cpu_to_be32(152)
#define SAVESTATE_RESULT_SIZE 10
static struct tpm_input_header savestate_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(10),
.ordinal = TPM_ORD_SAVESTATE
};
/*
* We are about to suspend. Save the TPM state
* so that it can be restored.
*/
int tpm_pm_suspend(struct device *dev)
{
struct tpm_chip *chip = dev_get_drvdata(dev);
struct tpm_cmd_t cmd;
int rc, try;
u8 dummy_hash[TPM_DIGEST_SIZE] = { 0 };
if (chip == NULL)
return -ENODEV;
if (chip->flags & TPM_CHIP_FLAG_TPM2) {
tpm2_shutdown(chip, TPM2_SU_STATE);
return 0;
}
/* for buggy tpm, flush pcrs with extend to selected dummy */
if (tpm_suspend_pcr) {
cmd.header.in = pcrextend_header;
cmd.params.pcrextend_in.pcr_idx = cpu_to_be32(tpm_suspend_pcr);
memcpy(cmd.params.pcrextend_in.hash, dummy_hash,
TPM_DIGEST_SIZE);
rc = tpm_transmit_cmd(chip, &cmd, EXTEND_PCR_RESULT_SIZE,
"extending dummy pcr before suspend");
}
/* now do the actual savestate */
for (try = 0; try < TPM_RETRY; try++) {
cmd.header.in = savestate_header;
rc = tpm_transmit_cmd(chip, &cmd, SAVESTATE_RESULT_SIZE, NULL);
/*
* If the TPM indicates that it is too busy to respond to
* this command then retry before giving up. It can take
* several seconds for this TPM to be ready.
*
* This can happen if the TPM has already been sent the
* SaveState command before the driver has loaded. TCG 1.2
* specification states that any communication after SaveState
* may cause the TPM to invalidate previously saved state.
*/
if (rc != TPM_WARN_RETRY)
break;
msleep(TPM_TIMEOUT_RETRY);
}
if (rc)
dev_err(chip->pdev,
"Error (%d) sending savestate before suspend\n", rc);
else if (try > 0)
dev_warn(chip->pdev, "TPM savestate took %dms\n",
try * TPM_TIMEOUT_RETRY);
return rc;
}
EXPORT_SYMBOL_GPL(tpm_pm_suspend);
/*
* Resume from a power safe. The BIOS already restored
* the TPM state.
*/
int tpm_pm_resume(struct device *dev)
{
struct tpm_chip *chip = dev_get_drvdata(dev);
if (chip == NULL)
return -ENODEV;
return 0;
}
EXPORT_SYMBOL_GPL(tpm_pm_resume);
#define TPM_GETRANDOM_RESULT_SIZE 18
static struct tpm_input_header tpm_getrandom_header = {
.tag = TPM_TAG_RQU_COMMAND,
.length = cpu_to_be32(14),
.ordinal = TPM_ORD_GET_RANDOM
};
/**
* tpm_get_random() - Get random bytes from the tpm's RNG
* @chip_num: A specific chip number for the request or TPM_ANY_NUM
* @out: destination buffer for the random bytes
* @max: the max number of bytes to write to @out
*
* Returns < 0 on error and the number of bytes read on success
*/
int tpm_get_random(u32 chip_num, u8 *out, size_t max)
{
struct tpm_chip *chip;
struct tpm_cmd_t tpm_cmd;
u32 recd, num_bytes = min_t(u32, max, TPM_MAX_RNG_DATA);
int err, total = 0, retries = 5;
u8 *dest = out;
if (!out || !num_bytes || max > TPM_MAX_RNG_DATA)
return -EINVAL;
chip = tpm_chip_find_get(chip_num);
if (chip == NULL)
return -ENODEV;
if (chip->flags & TPM_CHIP_FLAG_TPM2) {
err = tpm2_get_random(chip, out, max);
tpm_chip_put(chip);
return err;
}
do {
tpm_cmd.header.in = tpm_getrandom_header;
tpm_cmd.params.getrandom_in.num_bytes = cpu_to_be32(num_bytes);
err = tpm_transmit_cmd(chip, &tpm_cmd,
TPM_GETRANDOM_RESULT_SIZE + num_bytes,
"attempting get random");
if (err)
break;
recd = be32_to_cpu(tpm_cmd.params.getrandom_out.rng_data_len);
memcpy(dest, tpm_cmd.params.getrandom_out.rng_data, recd);
dest += recd;
total += recd;
num_bytes -= recd;
} while (retries-- && total < max);
tpm_chip_put(chip);
return total ? total : -EIO;
}
EXPORT_SYMBOL_GPL(tpm_get_random);
static int __init tpm_init(void)
{
int rc;
tpm_class = class_create(THIS_MODULE, "tpm");
if (IS_ERR(tpm_class)) {
pr_err("couldn't create tpm class\n");
return PTR_ERR(tpm_class);
}
rc = alloc_chrdev_region(&tpm_devt, 0, TPM_NUM_DEVICES, "tpm");
if (rc < 0) {
pr_err("tpm: failed to allocate char dev region\n");
class_destroy(tpm_class);
return rc;
}
return 0;
}
static void __exit tpm_exit(void)
{
class_destroy(tpm_class);
unregister_chrdev_region(tpm_devt, TPM_NUM_DEVICES);
}
subsys_initcall(tpm_init);
module_exit(tpm_exit);
MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
MODULE_DESCRIPTION("TPM Driver");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| gpl-2.0 |
xcaliburinhand/I9000-Reoriented-for-I897-Ginger | drivers/staging/dream/qdsp5/adsp_6220.c | 1515 | 10147 | /* arch/arm/mach-msm/qdsp5/adsp_6220.h
*
* Copyright (c) 2008 QUALCOMM Incorporated.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include "adsp.h"
/* Firmware modules */
typedef enum {
QDSP_MODULE_KERNEL,
QDSP_MODULE_AFETASK,
QDSP_MODULE_AUDPLAY0TASK,
QDSP_MODULE_AUDPLAY1TASK,
QDSP_MODULE_AUDPPTASK,
QDSP_MODULE_VIDEOTASK,
QDSP_MODULE_VIDEO_AAC_VOC,
QDSP_MODULE_PCM_DEC,
QDSP_MODULE_AUDIO_DEC_MP3,
QDSP_MODULE_AUDIO_DEC_AAC,
QDSP_MODULE_AUDIO_DEC_WMA,
QDSP_MODULE_HOSTPCM,
QDSP_MODULE_DTMF,
QDSP_MODULE_AUDRECTASK,
QDSP_MODULE_AUDPREPROCTASK,
QDSP_MODULE_SBC_ENC,
QDSP_MODULE_VOC,
QDSP_MODULE_VOC_PCM,
QDSP_MODULE_VOCENCTASK,
QDSP_MODULE_VOCDECTASK,
QDSP_MODULE_VOICEPROCTASK,
QDSP_MODULE_VIDEOENCTASK,
QDSP_MODULE_VFETASK,
QDSP_MODULE_WAV_ENC,
QDSP_MODULE_AACLC_ENC,
QDSP_MODULE_VIDEO_AMR,
QDSP_MODULE_VOC_AMR,
QDSP_MODULE_VOC_EVRC,
QDSP_MODULE_VOC_13K,
QDSP_MODULE_VOC_FGV,
QDSP_MODULE_DIAGTASK,
QDSP_MODULE_JPEGTASK,
QDSP_MODULE_LPMTASK,
QDSP_MODULE_QCAMTASK,
QDSP_MODULE_MODMATHTASK,
QDSP_MODULE_AUDPLAY2TASK,
QDSP_MODULE_AUDPLAY3TASK,
QDSP_MODULE_AUDPLAY4TASK,
QDSP_MODULE_GRAPHICSTASK,
QDSP_MODULE_MIDI,
QDSP_MODULE_GAUDIO,
QDSP_MODULE_VDEC_LP_MODE,
QDSP_MODULE_MAX,
} qdsp_module_type;
#define QDSP_RTOS_MAX_TASK_ID 19U
/* Table of modules indexed by task ID for the GAUDIO image */
static qdsp_module_type qdsp_gaudio_task_to_module_table[] = {
QDSP_MODULE_KERNEL,
QDSP_MODULE_AFETASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_AUDPPTASK,
QDSP_MODULE_AUDPLAY0TASK,
QDSP_MODULE_AUDPLAY1TASK,
QDSP_MODULE_AUDPLAY2TASK,
QDSP_MODULE_AUDPLAY3TASK,
QDSP_MODULE_AUDPLAY4TASK,
QDSP_MODULE_MAX,
QDSP_MODULE_AUDRECTASK,
QDSP_MODULE_AUDPREPROCTASK,
QDSP_MODULE_MAX,
QDSP_MODULE_GRAPHICSTASK,
QDSP_MODULE_MAX
};
/* Queue offset table indexed by queue ID for the GAUDIO image */
static uint32_t qdsp_gaudio_queue_offset_table[] = {
QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
0x3f0, /* QDSP_mpuAfeQueue */
0x420, /* QDSP_mpuGraphicsCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecPktQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
0x3f4, /* QDSP_uPAudPPCmd1Queue */
0x3f8, /* QDSP_uPAudPPCmd2Queue */
0x3fc, /* QDSP_uPAudPPCmd3Queue */
0x40c, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
0x410, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
0x414, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
0x418, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
0x41c, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
0x400, /* QDSP_uPAudPreProcCmdQueue */
0x408, /* QDSP_uPAudRecBitStreamQueue */
0x404, /* QDSP_uPAudRecCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
QDSP_RTOS_NO_QUEUE /* QDSP_vfeCommandTableQueue */
};
/* Table of modules indexed by task ID for the COMBO image */
static qdsp_module_type qdsp_combo_task_to_module_table[] = {
QDSP_MODULE_KERNEL,
QDSP_MODULE_AFETASK,
QDSP_MODULE_VOCDECTASK,
QDSP_MODULE_VOCENCTASK,
QDSP_MODULE_VIDEOTASK,
QDSP_MODULE_VIDEOENCTASK,
QDSP_MODULE_VOICEPROCTASK,
QDSP_MODULE_VFETASK,
QDSP_MODULE_JPEGTASK,
QDSP_MODULE_AUDPPTASK,
QDSP_MODULE_AUDPLAY0TASK,
QDSP_MODULE_AUDPLAY1TASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_LPMTASK,
QDSP_MODULE_AUDRECTASK,
QDSP_MODULE_AUDPREPROCTASK,
QDSP_MODULE_MODMATHTASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX
};
/* Queue offset table indexed by queue ID for the COMBO image */
static uint32_t qdsp_combo_queue_offset_table[] = {
0x6f2, /* QDSP_lpmCommandQueue */
0x69e, /* QDSP_mpuAfeQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
0x6b2, /* QDSP_mpuModmathCmdQueue */
0x6c6, /* QDSP_mpuVDecCmdQueue */
0x6ca, /* QDSP_mpuVDecPktQueue */
0x6c2, /* QDSP_mpuVEncCmdQueue */
0x6a6, /* QDSP_rxMpuDecCmdQueue */
0x6aa, /* QDSP_rxMpuDecPktQueue */
0x6ae, /* QDSP_txMpuEncQueue */
0x6ce, /* QDSP_uPAudPPCmd1Queue */
0x6d2, /* QDSP_uPAudPPCmd2Queue */
0x6d6, /* QDSP_uPAudPPCmd3Queue */
0x6e6, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
0x6da, /* QDSP_uPAudPreProcCmdQueue */
0x6e2, /* QDSP_uPAudRecBitStreamQueue */
0x6de, /* QDSP_uPAudRecCmdQueue */
0x6ee, /* QDSP_uPJpegActionCmdQueue */
0x6ea, /* QDSP_uPJpegCfgCmdQueue */
0x6a2, /* QDSP_uPVocProcQueue */
0x6b6, /* QDSP_vfeCommandQueue */
0x6be, /* QDSP_vfeCommandScaleQueue */
0x6ba /* QDSP_vfeCommandTableQueue */
};
/* Table of modules indexed by task ID for the QTV_LP image */
static qdsp_module_type qdsp_qtv_lp_task_to_module_table[] = {
QDSP_MODULE_KERNEL,
QDSP_MODULE_AFETASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_VIDEOTASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_AUDPPTASK,
QDSP_MODULE_AUDPLAY0TASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_AUDRECTASK,
QDSP_MODULE_AUDPREPROCTASK,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX,
QDSP_MODULE_MAX
};
/* Queue offset table indexed by queue ID for the QTV_LP image */
static uint32_t qdsp_qtv_lp_queue_offset_table[] = {
QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
0x430, /* QDSP_mpuAfeQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
0x434, /* QDSP_mpuVDecCmdQueue */
0x438, /* QDSP_mpuVDecPktQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
0x440, /* QDSP_uPAudPPCmd1Queue */
0x444, /* QDSP_uPAudPPCmd2Queue */
0x448, /* QDSP_uPAudPPCmd3Queue */
0x454, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
0x43c, /* QDSP_uPAudPreProcCmdQueue */
0x450, /* QDSP_uPAudRecBitStreamQueue */
0x44c, /* QDSP_uPAudRecCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
QDSP_RTOS_NO_QUEUE /* QDSP_vfeCommandTableQueue */
};
/* Tables to convert tasks to modules */
static qdsp_module_type *qdsp_task_to_module[] = {
qdsp_combo_task_to_module_table,
qdsp_gaudio_task_to_module_table,
qdsp_qtv_lp_task_to_module_table,
};
/* Tables to retrieve queue offsets */
static uint32_t *qdsp_queue_offset_table[] = {
qdsp_combo_queue_offset_table,
qdsp_gaudio_queue_offset_table,
qdsp_qtv_lp_queue_offset_table,
};
#define QDSP_MODULE(n) \
{ .name = #n, .pdev_name = "adsp_" #n, .id = QDSP_MODULE_##n }
static struct adsp_module_info module_info[] = {
QDSP_MODULE(AUDPLAY0TASK),
QDSP_MODULE(AUDPPTASK),
QDSP_MODULE(AUDPREPROCTASK),
QDSP_MODULE(AUDRECTASK),
QDSP_MODULE(VFETASK),
QDSP_MODULE(QCAMTASK),
QDSP_MODULE(LPMTASK),
QDSP_MODULE(JPEGTASK),
QDSP_MODULE(VIDEOTASK),
QDSP_MODULE(VDEC_LP_MODE),
};
int adsp_init_info(struct adsp_info *info)
{
info->send_irq = 0x00c00200;
info->read_ctrl = 0x00400038;
info->write_ctrl = 0x00400034;
info->max_msg16_size = 193;
info->max_msg32_size = 8;
info->max_task_id = 16;
info->max_module_id = QDSP_MODULE_MAX - 1;
info->max_queue_id = QDSP_QUEUE_MAX;
info->max_image_id = 2;
info->queue_offset = qdsp_queue_offset_table;
info->task_to_module = qdsp_task_to_module;
info->module_count = ARRAY_SIZE(module_info);
info->module = module_info;
return 0;
}
| gpl-2.0 |
delafer/YP-GI1CW | arch/avr32/kernel/setup.c | 1771 | 14915 | /*
* Copyright (C) 2004-2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/initrd.h>
#include <linux/sched.h>
#include <linux/console.h>
#include <linux/ioport.h>
#include <linux/bootmem.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/pfn.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/kernel.h>
#include <asm/sections.h>
#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/setup.h>
#include <asm/sysreg.h>
#include <mach/board.h>
#include <mach/init.h>
extern int root_mountflags;
/*
* Initialize loops_per_jiffy as 5000000 (500MIPS).
* Better make it too large than too small...
*/
struct avr32_cpuinfo boot_cpu_data = {
.loops_per_jiffy = 5000000
};
EXPORT_SYMBOL(boot_cpu_data);
static char __initdata command_line[COMMAND_LINE_SIZE];
/*
* Standard memory resources
*/
static struct resource __initdata kernel_data = {
.name = "Kernel data",
.start = 0,
.end = 0,
.flags = IORESOURCE_MEM,
};
static struct resource __initdata kernel_code = {
.name = "Kernel code",
.start = 0,
.end = 0,
.flags = IORESOURCE_MEM,
.sibling = &kernel_data,
};
/*
* Available system RAM and reserved regions as singly linked
* lists. These lists are traversed using the sibling pointer in
* struct resource and are kept sorted at all times.
*/
static struct resource *__initdata system_ram;
static struct resource *__initdata reserved = &kernel_code;
/*
* We need to allocate these before the bootmem allocator is up and
* running, so we need this "cache". 32 entries are probably enough
* for all but the most insanely complex systems.
*/
static struct resource __initdata res_cache[32];
static unsigned int __initdata res_cache_next_free;
static void __init resource_init(void)
{
struct resource *mem, *res;
struct resource *new;
kernel_code.start = __pa(init_mm.start_code);
for (mem = system_ram; mem; mem = mem->sibling) {
new = alloc_bootmem_low(sizeof(struct resource));
memcpy(new, mem, sizeof(struct resource));
new->sibling = NULL;
if (request_resource(&iomem_resource, new))
printk(KERN_WARNING "Bad RAM resource %08x-%08x\n",
mem->start, mem->end);
}
for (res = reserved; res; res = res->sibling) {
new = alloc_bootmem_low(sizeof(struct resource));
memcpy(new, res, sizeof(struct resource));
new->sibling = NULL;
if (insert_resource(&iomem_resource, new))
printk(KERN_WARNING
"Bad reserved resource %s (%08x-%08x)\n",
res->name, res->start, res->end);
}
}
static void __init
add_physical_memory(resource_size_t start, resource_size_t end)
{
struct resource *new, *next, **pprev;
for (pprev = &system_ram, next = system_ram; next;
pprev = &next->sibling, next = next->sibling) {
if (end < next->start)
break;
if (start <= next->end) {
printk(KERN_WARNING
"Warning: Physical memory map is broken\n");
printk(KERN_WARNING
"Warning: %08x-%08x overlaps %08x-%08x\n",
start, end, next->start, next->end);
return;
}
}
if (res_cache_next_free >= ARRAY_SIZE(res_cache)) {
printk(KERN_WARNING
"Warning: Failed to add physical memory %08x-%08x\n",
start, end);
return;
}
new = &res_cache[res_cache_next_free++];
new->start = start;
new->end = end;
new->name = "System RAM";
new->flags = IORESOURCE_MEM;
*pprev = new;
}
static int __init
add_reserved_region(resource_size_t start, resource_size_t end,
const char *name)
{
struct resource *new, *next, **pprev;
if (end < start)
return -EINVAL;
if (res_cache_next_free >= ARRAY_SIZE(res_cache))
return -ENOMEM;
for (pprev = &reserved, next = reserved; next;
pprev = &next->sibling, next = next->sibling) {
if (end < next->start)
break;
if (start <= next->end)
return -EBUSY;
}
new = &res_cache[res_cache_next_free++];
new->start = start;
new->end = end;
new->name = name;
new->sibling = next;
new->flags = IORESOURCE_MEM;
*pprev = new;
return 0;
}
static unsigned long __init
find_free_region(const struct resource *mem, resource_size_t size,
resource_size_t align)
{
struct resource *res;
unsigned long target;
target = ALIGN(mem->start, align);
for (res = reserved; res; res = res->sibling) {
if ((target + size) <= res->start)
break;
if (target <= res->end)
target = ALIGN(res->end + 1, align);
}
if ((target + size) > (mem->end + 1))
return mem->end + 1;
return target;
}
static int __init
alloc_reserved_region(resource_size_t *start, resource_size_t size,
resource_size_t align, const char *name)
{
struct resource *mem;
resource_size_t target;
int ret;
for (mem = system_ram; mem; mem = mem->sibling) {
target = find_free_region(mem, size, align);
if (target <= mem->end) {
ret = add_reserved_region(target, target + size - 1,
name);
if (!ret)
*start = target;
return ret;
}
}
return -ENOMEM;
}
/*
* Early framebuffer allocation. Works as follows:
* - If fbmem_size is zero, nothing will be allocated or reserved.
* - If fbmem_start is zero when setup_bootmem() is called,
* a block of fbmem_size bytes will be reserved before bootmem
* initialization. It will be aligned to the largest page size
* that fbmem_size is a multiple of.
* - If fbmem_start is nonzero, an area of size fbmem_size will be
* reserved at the physical address fbmem_start if possible. If
* it collides with other reserved memory, a different block of
* same size will be allocated, just as if fbmem_start was zero.
*
* Board-specific code may use these variables to set up platform data
* for the framebuffer driver if fbmem_size is nonzero.
*/
resource_size_t __initdata fbmem_start;
resource_size_t __initdata fbmem_size;
/*
* "fbmem=xxx[kKmM]" allocates the specified amount of boot memory for
* use as framebuffer.
*
* "fbmem=xxx[kKmM]@yyy[kKmM]" defines a memory region of size xxx and
* starting at yyy to be reserved for use as framebuffer.
*
* The kernel won't verify that the memory region starting at yyy
* actually contains usable RAM.
*/
static int __init early_parse_fbmem(char *p)
{
int ret;
unsigned long align;
fbmem_size = memparse(p, &p);
if (*p == '@') {
fbmem_start = memparse(p + 1, &p);
ret = add_reserved_region(fbmem_start,
fbmem_start + fbmem_size - 1,
"Framebuffer");
if (ret) {
printk(KERN_WARNING
"Failed to reserve framebuffer memory\n");
fbmem_start = 0;
}
}
if (!fbmem_start) {
if ((fbmem_size & 0x000fffffUL) == 0)
align = 0x100000; /* 1 MiB */
else if ((fbmem_size & 0x0000ffffUL) == 0)
align = 0x10000; /* 64 KiB */
else
align = 0x1000; /* 4 KiB */
ret = alloc_reserved_region(&fbmem_start, fbmem_size,
align, "Framebuffer");
if (ret) {
printk(KERN_WARNING
"Failed to allocate framebuffer memory\n");
fbmem_size = 0;
} else {
memset(__va(fbmem_start), 0, fbmem_size);
}
}
return 0;
}
early_param("fbmem", early_parse_fbmem);
/*
* Pick out the memory size. We look for mem=size@start,
* where start and size are "size[KkMmGg]"
*/
static int __init early_mem(char *p)
{
resource_size_t size, start;
start = system_ram->start;
size = memparse(p, &p);
if (*p == '@')
start = memparse(p + 1, &p);
system_ram->start = start;
system_ram->end = system_ram->start + size - 1;
return 0;
}
early_param("mem", early_mem);
static int __init parse_tag_core(struct tag *tag)
{
if (tag->hdr.size > 2) {
if ((tag->u.core.flags & 1) == 0)
root_mountflags &= ~MS_RDONLY;
ROOT_DEV = new_decode_dev(tag->u.core.rootdev);
}
return 0;
}
__tagtable(ATAG_CORE, parse_tag_core);
static int __init parse_tag_mem(struct tag *tag)
{
unsigned long start, end;
/*
* Ignore zero-sized entries. If we're running standalone, the
* SDRAM code may emit such entries if something goes
* wrong...
*/
if (tag->u.mem_range.size == 0)
return 0;
start = tag->u.mem_range.addr;
end = tag->u.mem_range.addr + tag->u.mem_range.size - 1;
add_physical_memory(start, end);
return 0;
}
__tagtable(ATAG_MEM, parse_tag_mem);
static int __init parse_tag_rdimg(struct tag *tag)
{
#ifdef CONFIG_BLK_DEV_INITRD
struct tag_mem_range *mem = &tag->u.mem_range;
int ret;
if (initrd_start) {
printk(KERN_WARNING
"Warning: Only the first initrd image will be used\n");
return 0;
}
ret = add_reserved_region(mem->addr, mem->addr + mem->size - 1,
"initrd");
if (ret) {
printk(KERN_WARNING
"Warning: Failed to reserve initrd memory\n");
return ret;
}
initrd_start = (unsigned long)__va(mem->addr);
initrd_end = initrd_start + mem->size;
#else
printk(KERN_WARNING "RAM disk image present, but "
"no initrd support in kernel, ignoring\n");
#endif
return 0;
}
__tagtable(ATAG_RDIMG, parse_tag_rdimg);
static int __init parse_tag_rsvd_mem(struct tag *tag)
{
struct tag_mem_range *mem = &tag->u.mem_range;
return add_reserved_region(mem->addr, mem->addr + mem->size - 1,
"Reserved");
}
__tagtable(ATAG_RSVD_MEM, parse_tag_rsvd_mem);
static int __init parse_tag_cmdline(struct tag *tag)
{
strlcpy(boot_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE);
return 0;
}
__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
static int __init parse_tag_clock(struct tag *tag)
{
/*
* We'll figure out the clocks by peeking at the system
* manager regs directly.
*/
return 0;
}
__tagtable(ATAG_CLOCK, parse_tag_clock);
/*
* Scan the tag table for this tag, and call its parse function. The
* tag table is built by the linker from all the __tagtable
* declarations.
*/
static int __init parse_tag(struct tag *tag)
{
extern struct tagtable __tagtable_begin, __tagtable_end;
struct tagtable *t;
for (t = &__tagtable_begin; t < &__tagtable_end; t++)
if (tag->hdr.tag == t->tag) {
t->parse(tag);
break;
}
return t < &__tagtable_end;
}
/*
* Parse all tags in the list we got from the boot loader
*/
static void __init parse_tags(struct tag *t)
{
for (; t->hdr.tag != ATAG_NONE; t = tag_next(t))
if (!parse_tag(t))
printk(KERN_WARNING
"Ignoring unrecognised tag 0x%08x\n",
t->hdr.tag);
}
/*
* Find a free memory region large enough for storing the
* bootmem bitmap.
*/
static unsigned long __init
find_bootmap_pfn(const struct resource *mem)
{
unsigned long bootmap_pages, bootmap_len;
unsigned long node_pages = PFN_UP(mem->end - mem->start + 1);
unsigned long bootmap_start;
bootmap_pages = bootmem_bootmap_pages(node_pages);
bootmap_len = bootmap_pages << PAGE_SHIFT;
/*
* Find a large enough region without reserved pages for
* storing the bootmem bitmap. We can take advantage of the
* fact that all lists have been sorted.
*
* We have to check that we don't collide with any reserved
* regions, which includes the kernel image and any RAMDISK
* images.
*/
bootmap_start = find_free_region(mem, bootmap_len, PAGE_SIZE);
return bootmap_start >> PAGE_SHIFT;
}
#define MAX_LOWMEM HIGHMEM_START
#define MAX_LOWMEM_PFN PFN_DOWN(MAX_LOWMEM)
static void __init setup_bootmem(void)
{
unsigned bootmap_size;
unsigned long first_pfn, bootmap_pfn, pages;
unsigned long max_pfn, max_low_pfn;
unsigned node = 0;
struct resource *res;
printk(KERN_INFO "Physical memory:\n");
for (res = system_ram; res; res = res->sibling)
printk(" %08x-%08x\n", res->start, res->end);
printk(KERN_INFO "Reserved memory:\n");
for (res = reserved; res; res = res->sibling)
printk(" %08x-%08x: %s\n",
res->start, res->end, res->name);
nodes_clear(node_online_map);
if (system_ram->sibling)
printk(KERN_WARNING "Only using first memory bank\n");
for (res = system_ram; res; res = NULL) {
first_pfn = PFN_UP(res->start);
max_low_pfn = max_pfn = PFN_DOWN(res->end + 1);
bootmap_pfn = find_bootmap_pfn(res);
if (bootmap_pfn > max_pfn)
panic("No space for bootmem bitmap!\n");
if (max_low_pfn > MAX_LOWMEM_PFN) {
max_low_pfn = MAX_LOWMEM_PFN;
#ifndef CONFIG_HIGHMEM
/*
* Lowmem is memory that can be addressed
* directly through P1/P2
*/
printk(KERN_WARNING
"Node %u: Only %ld MiB of memory will be used.\n",
node, MAX_LOWMEM >> 20);
printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
#else
#error HIGHMEM is not supported by AVR32 yet
#endif
}
/* Initialize the boot-time allocator with low memory only. */
bootmap_size = init_bootmem_node(NODE_DATA(node), bootmap_pfn,
first_pfn, max_low_pfn);
/*
* Register fully available RAM pages with the bootmem
* allocator.
*/
pages = max_low_pfn - first_pfn;
free_bootmem_node (NODE_DATA(node), PFN_PHYS(first_pfn),
PFN_PHYS(pages));
/* Reserve space for the bootmem bitmap... */
reserve_bootmem_node(NODE_DATA(node),
PFN_PHYS(bootmap_pfn),
bootmap_size,
BOOTMEM_DEFAULT);
/* ...and any other reserved regions. */
for (res = reserved; res; res = res->sibling) {
if (res->start > PFN_PHYS(max_pfn))
break;
/*
* resource_init will complain about partial
* overlaps, so we'll just ignore such
* resources for now.
*/
if (res->start >= PFN_PHYS(first_pfn)
&& res->end < PFN_PHYS(max_pfn))
reserve_bootmem_node(
NODE_DATA(node), res->start,
res->end - res->start + 1,
BOOTMEM_DEFAULT);
}
node_set_online(node);
}
}
void __init setup_arch (char **cmdline_p)
{
struct clk *cpu_clk;
init_mm.start_code = (unsigned long)_text;
init_mm.end_code = (unsigned long)_etext;
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)_end;
/*
* Include .init section to make allocations easier. It will
* be removed before the resource is actually requested.
*/
kernel_code.start = __pa(__init_begin);
kernel_code.end = __pa(init_mm.end_code - 1);
kernel_data.start = __pa(init_mm.end_code);
kernel_data.end = __pa(init_mm.brk - 1);
parse_tags(bootloader_tags);
setup_processor();
setup_platform();
setup_board();
cpu_clk = clk_get(NULL, "cpu");
if (IS_ERR(cpu_clk)) {
printk(KERN_WARNING "Warning: Unable to get CPU clock\n");
} else {
unsigned long cpu_hz = clk_get_rate(cpu_clk);
/*
* Well, duh, but it's probably a good idea to
* increment the use count.
*/
clk_enable(cpu_clk);
boot_cpu_data.clk = cpu_clk;
boot_cpu_data.loops_per_jiffy = cpu_hz * 4;
printk("CPU: Running at %lu.%03lu MHz\n",
((cpu_hz + 500) / 1000) / 1000,
((cpu_hz + 500) / 1000) % 1000);
}
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
setup_bootmem();
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
paging_init();
resource_init();
}
| gpl-2.0 |
premaca/android_kernel_redmi2 | sound/soc/atmel/atmel-pcm-dma.c | 2027 | 6707 | /*
* atmel-pcm-dma.c -- ALSA PCM DMA support for the Atmel SoC.
*
* Copyright (C) 2012 Atmel
*
* Author: Bo Shen <voice.shen@atmel.com>
*
* Based on atmel-pcm by:
* Sedji Gaouaou <sedji.gaouaou@atmel.com>
* Copyright 2008 Atmel
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/atmel-ssc.h>
#include <linux/platform_data/dma-atmel.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "atmel-pcm.h"
/*--------------------------------------------------------------------------*\
* Hardware definition
\*--------------------------------------------------------------------------*/
static const struct snd_pcm_hardware atmel_pcm_dma_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_PAUSE,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.period_bytes_min = 256, /* lighting DMA overhead */
.period_bytes_max = 2 * 0xffff, /* if 2 bytes format */
.periods_min = 8,
.periods_max = 1024, /* no limit */
.buffer_bytes_max = ATMEL_SSC_DMABUF_SIZE,
};
/**
* atmel_pcm_dma_irq: SSC interrupt handler for DMAENGINE enabled SSC
*
* We use DMAENGINE to send/receive data to/from SSC so this ISR is only to
* check if any overrun occured.
*/
static void atmel_pcm_dma_irq(u32 ssc_sr,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct atmel_pcm_dma_params *prtd;
prtd = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
if (ssc_sr & prtd->mask->ssc_error) {
if (snd_pcm_running(substream))
pr_warn("atmel-pcm: buffer %s on %s (SSC_SR=%#x)\n",
substream->stream == SNDRV_PCM_STREAM_PLAYBACK
? "underrun" : "overrun", prtd->name,
ssc_sr);
/* stop RX and capture: will be enabled again at restart */
ssc_writex(prtd->ssc->regs, SSC_CR, prtd->mask->ssc_disable);
snd_pcm_stream_lock(substream);
snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
snd_pcm_stream_unlock(substream);
/* now drain RHR and read status to remove xrun condition */
ssc_readx(prtd->ssc->regs, SSC_RHR);
ssc_readx(prtd->ssc->regs, SSC_SR);
}
}
/*--------------------------------------------------------------------------*\
* DMAENGINE operations
\*--------------------------------------------------------------------------*/
static bool filter(struct dma_chan *chan, void *slave)
{
struct at_dma_slave *sl = slave;
if (sl->dma_dev == chan->device->dev) {
chan->private = sl;
return true;
} else {
return false;
}
}
static int atmel_pcm_configure_dma(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct atmel_pcm_dma_params *prtd)
{
struct ssc_device *ssc;
struct dma_chan *dma_chan;
struct dma_slave_config slave_config;
int ret;
ssc = prtd->ssc;
ret = snd_hwparams_to_dma_slave_config(substream, params,
&slave_config);
if (ret) {
pr_err("atmel-pcm: hwparams to dma slave configure failed\n");
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config.dst_addr = (dma_addr_t)ssc->phybase + SSC_THR;
slave_config.dst_maxburst = 1;
} else {
slave_config.src_addr = (dma_addr_t)ssc->phybase + SSC_RHR;
slave_config.src_maxburst = 1;
}
dma_chan = snd_dmaengine_pcm_get_chan(substream);
if (dmaengine_slave_config(dma_chan, &slave_config)) {
pr_err("atmel-pcm: failed to configure dma channel\n");
ret = -EBUSY;
return ret;
}
return 0;
}
static int atmel_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct atmel_pcm_dma_params *prtd;
struct ssc_device *ssc;
struct at_dma_slave *sdata = NULL;
int ret;
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
prtd = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
ssc = prtd->ssc;
if (ssc->pdev)
sdata = ssc->pdev->dev.platform_data;
ret = snd_dmaengine_pcm_open_request_chan(substream, filter, sdata);
if (ret) {
pr_err("atmel-pcm: dmaengine pcm open failed\n");
return -EINVAL;
}
ret = atmel_pcm_configure_dma(substream, params, prtd);
if (ret) {
pr_err("atmel-pcm: failed to configure dmai\n");
goto err;
}
prtd->dma_intr_handler = atmel_pcm_dma_irq;
return 0;
err:
snd_dmaengine_pcm_close_release_chan(substream);
return ret;
}
static int atmel_pcm_dma_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct atmel_pcm_dma_params *prtd;
prtd = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
ssc_writex(prtd->ssc->regs, SSC_IER, prtd->mask->ssc_error);
ssc_writex(prtd->ssc->regs, SSC_CR, prtd->mask->ssc_enable);
return 0;
}
static int atmel_pcm_open(struct snd_pcm_substream *substream)
{
snd_soc_set_runtime_hwparams(substream, &atmel_pcm_dma_hardware);
return 0;
}
static struct snd_pcm_ops atmel_pcm_ops = {
.open = atmel_pcm_open,
.close = snd_dmaengine_pcm_close_release_chan,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = atmel_pcm_hw_params,
.prepare = atmel_pcm_dma_prepare,
.trigger = snd_dmaengine_pcm_trigger,
.pointer = snd_dmaengine_pcm_pointer_no_residue,
.mmap = atmel_pcm_mmap,
};
static struct snd_soc_platform_driver atmel_soc_platform = {
.ops = &atmel_pcm_ops,
.pcm_new = atmel_pcm_new,
.pcm_free = atmel_pcm_free,
};
int atmel_pcm_dma_platform_register(struct device *dev)
{
return snd_soc_register_platform(dev, &atmel_soc_platform);
}
EXPORT_SYMBOL(atmel_pcm_dma_platform_register);
void atmel_pcm_dma_platform_unregister(struct device *dev)
{
snd_soc_unregister_platform(dev);
}
EXPORT_SYMBOL(atmel_pcm_dma_platform_unregister);
MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
MODULE_DESCRIPTION("Atmel DMA based PCM module");
MODULE_LICENSE("GPL");
| gpl-2.0 |
adegroote/linux | usr/gen_init_cpio.c | 2283 | 13029 | #include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <string.h>
#include <unistd.h>
#include <time.h>
#include <fcntl.h>
#include <errno.h>
#include <ctype.h>
#include <limits.h>
/*
* Original work by Jeff Garzik
*
* External file lists, symlink, pipe and fifo support by Thayne Harbaugh
* Hard link support by Luciano Rocha
*/
#define xstr(s) #s
#define str(s) xstr(s)
static unsigned int offset;
static unsigned int ino = 721;
static time_t default_mtime;
struct file_handler {
const char *type;
int (*handler)(const char *line);
};
static void push_string(const char *name)
{
unsigned int name_len = strlen(name) + 1;
fputs(name, stdout);
putchar(0);
offset += name_len;
}
static void push_pad (void)
{
while (offset & 3) {
putchar(0);
offset++;
}
}
static void push_rest(const char *name)
{
unsigned int name_len = strlen(name) + 1;
unsigned int tmp_ofs;
fputs(name, stdout);
putchar(0);
offset += name_len;
tmp_ofs = name_len + 110;
while (tmp_ofs & 3) {
putchar(0);
offset++;
tmp_ofs++;
}
}
static void push_hdr(const char *s)
{
fputs(s, stdout);
offset += 110;
}
static void cpio_trailer(void)
{
char s[256];
const char name[] = "TRAILER!!!";
sprintf(s, "%s%08X%08X%08lX%08lX%08X%08lX"
"%08X%08X%08X%08X%08X%08X%08X",
"070701", /* magic */
0, /* ino */
0, /* mode */
(long) 0, /* uid */
(long) 0, /* gid */
1, /* nlink */
(long) 0, /* mtime */
0, /* filesize */
0, /* major */
0, /* minor */
0, /* rmajor */
0, /* rminor */
(unsigned)strlen(name)+1, /* namesize */
0); /* chksum */
push_hdr(s);
push_rest(name);
while (offset % 512) {
putchar(0);
offset++;
}
}
static int cpio_mkslink(const char *name, const char *target,
unsigned int mode, uid_t uid, gid_t gid)
{
char s[256];
if (name[0] == '/')
name++;
sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
"%08X%08X%08X%08X%08X%08X%08X",
"070701", /* magic */
ino++, /* ino */
S_IFLNK | mode, /* mode */
(long) uid, /* uid */
(long) gid, /* gid */
1, /* nlink */
(long) default_mtime, /* mtime */
(unsigned)strlen(target)+1, /* filesize */
3, /* major */
1, /* minor */
0, /* rmajor */
0, /* rminor */
(unsigned)strlen(name) + 1,/* namesize */
0); /* chksum */
push_hdr(s);
push_string(name);
push_pad();
push_string(target);
push_pad();
return 0;
}
static int cpio_mkslink_line(const char *line)
{
char name[PATH_MAX + 1];
char target[PATH_MAX + 1];
unsigned int mode;
int uid;
int gid;
int rc = -1;
if (5 != sscanf(line, "%" str(PATH_MAX) "s %" str(PATH_MAX) "s %o %d %d", name, target, &mode, &uid, &gid)) {
fprintf(stderr, "Unrecognized dir format '%s'", line);
goto fail;
}
rc = cpio_mkslink(name, target, mode, uid, gid);
fail:
return rc;
}
static int cpio_mkgeneric(const char *name, unsigned int mode,
uid_t uid, gid_t gid)
{
char s[256];
if (name[0] == '/')
name++;
sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
"%08X%08X%08X%08X%08X%08X%08X",
"070701", /* magic */
ino++, /* ino */
mode, /* mode */
(long) uid, /* uid */
(long) gid, /* gid */
2, /* nlink */
(long) default_mtime, /* mtime */
0, /* filesize */
3, /* major */
1, /* minor */
0, /* rmajor */
0, /* rminor */
(unsigned)strlen(name) + 1,/* namesize */
0); /* chksum */
push_hdr(s);
push_rest(name);
return 0;
}
enum generic_types {
GT_DIR,
GT_PIPE,
GT_SOCK
};
struct generic_type {
const char *type;
mode_t mode;
};
static struct generic_type generic_type_table[] = {
[GT_DIR] = {
.type = "dir",
.mode = S_IFDIR
},
[GT_PIPE] = {
.type = "pipe",
.mode = S_IFIFO
},
[GT_SOCK] = {
.type = "sock",
.mode = S_IFSOCK
}
};
static int cpio_mkgeneric_line(const char *line, enum generic_types gt)
{
char name[PATH_MAX + 1];
unsigned int mode;
int uid;
int gid;
int rc = -1;
if (4 != sscanf(line, "%" str(PATH_MAX) "s %o %d %d", name, &mode, &uid, &gid)) {
fprintf(stderr, "Unrecognized %s format '%s'",
line, generic_type_table[gt].type);
goto fail;
}
mode |= generic_type_table[gt].mode;
rc = cpio_mkgeneric(name, mode, uid, gid);
fail:
return rc;
}
static int cpio_mkdir_line(const char *line)
{
return cpio_mkgeneric_line(line, GT_DIR);
}
static int cpio_mkpipe_line(const char *line)
{
return cpio_mkgeneric_line(line, GT_PIPE);
}
static int cpio_mksock_line(const char *line)
{
return cpio_mkgeneric_line(line, GT_SOCK);
}
static int cpio_mknod(const char *name, unsigned int mode,
uid_t uid, gid_t gid, char dev_type,
unsigned int maj, unsigned int min)
{
char s[256];
if (dev_type == 'b')
mode |= S_IFBLK;
else
mode |= S_IFCHR;
if (name[0] == '/')
name++;
sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
"%08X%08X%08X%08X%08X%08X%08X",
"070701", /* magic */
ino++, /* ino */
mode, /* mode */
(long) uid, /* uid */
(long) gid, /* gid */
1, /* nlink */
(long) default_mtime, /* mtime */
0, /* filesize */
3, /* major */
1, /* minor */
maj, /* rmajor */
min, /* rminor */
(unsigned)strlen(name) + 1,/* namesize */
0); /* chksum */
push_hdr(s);
push_rest(name);
return 0;
}
static int cpio_mknod_line(const char *line)
{
char name[PATH_MAX + 1];
unsigned int mode;
int uid;
int gid;
char dev_type;
unsigned int maj;
unsigned int min;
int rc = -1;
if (7 != sscanf(line, "%" str(PATH_MAX) "s %o %d %d %c %u %u",
name, &mode, &uid, &gid, &dev_type, &maj, &min)) {
fprintf(stderr, "Unrecognized nod format '%s'", line);
goto fail;
}
rc = cpio_mknod(name, mode, uid, gid, dev_type, maj, min);
fail:
return rc;
}
static int cpio_mkfile(const char *name, const char *location,
unsigned int mode, uid_t uid, gid_t gid,
unsigned int nlinks)
{
char s[256];
char *filebuf = NULL;
struct stat buf;
long size;
int file = -1;
int retval;
int rc = -1;
int namesize;
unsigned int i;
mode |= S_IFREG;
file = open (location, O_RDONLY);
if (file < 0) {
fprintf (stderr, "File %s could not be opened for reading\n", location);
goto error;
}
retval = fstat(file, &buf);
if (retval) {
fprintf(stderr, "File %s could not be stat()'ed\n", location);
goto error;
}
filebuf = malloc(buf.st_size);
if (!filebuf) {
fprintf (stderr, "out of memory\n");
goto error;
}
retval = read (file, filebuf, buf.st_size);
if (retval < 0) {
fprintf (stderr, "Can not read %s file\n", location);
goto error;
}
size = 0;
for (i = 1; i <= nlinks; i++) {
/* data goes on last link */
if (i == nlinks) size = buf.st_size;
if (name[0] == '/')
name++;
namesize = strlen(name) + 1;
sprintf(s,"%s%08X%08X%08lX%08lX%08X%08lX"
"%08lX%08X%08X%08X%08X%08X%08X",
"070701", /* magic */
ino, /* ino */
mode, /* mode */
(long) uid, /* uid */
(long) gid, /* gid */
nlinks, /* nlink */
(long) buf.st_mtime, /* mtime */
size, /* filesize */
3, /* major */
1, /* minor */
0, /* rmajor */
0, /* rminor */
namesize, /* namesize */
0); /* chksum */
push_hdr(s);
push_string(name);
push_pad();
if (size) {
if (fwrite(filebuf, size, 1, stdout) != 1) {
fprintf(stderr, "writing filebuf failed\n");
goto error;
}
offset += size;
push_pad();
}
name += namesize;
}
ino++;
rc = 0;
error:
if (filebuf) free(filebuf);
if (file >= 0) close(file);
return rc;
}
static char *cpio_replace_env(char *new_location)
{
char expanded[PATH_MAX + 1];
char *start, *end, *var;
while ((start = strstr(new_location, "${")) &&
(end = strchr(start + 2, '}'))) {
*start = *end = 0;
var = getenv(start + 2);
snprintf(expanded, sizeof expanded, "%s%s%s",
new_location, var ? var : "", end + 1);
strcpy(new_location, expanded);
}
return new_location;
}
static int cpio_mkfile_line(const char *line)
{
char name[PATH_MAX + 1];
char *dname = NULL; /* malloc'ed buffer for hard links */
char location[PATH_MAX + 1];
unsigned int mode;
int uid;
int gid;
int nlinks = 1;
int end = 0, dname_len = 0;
int rc = -1;
if (5 > sscanf(line, "%" str(PATH_MAX) "s %" str(PATH_MAX)
"s %o %d %d %n",
name, location, &mode, &uid, &gid, &end)) {
fprintf(stderr, "Unrecognized file format '%s'", line);
goto fail;
}
if (end && isgraph(line[end])) {
int len;
int nend;
dname = malloc(strlen(line));
if (!dname) {
fprintf (stderr, "out of memory (%d)\n", dname_len);
goto fail;
}
dname_len = strlen(name) + 1;
memcpy(dname, name, dname_len);
do {
nend = 0;
if (sscanf(line + end, "%" str(PATH_MAX) "s %n",
name, &nend) < 1)
break;
len = strlen(name) + 1;
memcpy(dname + dname_len, name, len);
dname_len += len;
nlinks++;
end += nend;
} while (isgraph(line[end]));
} else {
dname = name;
}
rc = cpio_mkfile(dname, cpio_replace_env(location),
mode, uid, gid, nlinks);
fail:
if (dname_len) free(dname);
return rc;
}
static void usage(const char *prog)
{
fprintf(stderr, "Usage:\n"
"\t%s [-t <timestamp>] <cpio_list>\n"
"\n"
"<cpio_list> is a file containing newline separated entries that\n"
"describe the files to be included in the initramfs archive:\n"
"\n"
"# a comment\n"
"file <name> <location> <mode> <uid> <gid> [<hard links>]\n"
"dir <name> <mode> <uid> <gid>\n"
"nod <name> <mode> <uid> <gid> <dev_type> <maj> <min>\n"
"slink <name> <target> <mode> <uid> <gid>\n"
"pipe <name> <mode> <uid> <gid>\n"
"sock <name> <mode> <uid> <gid>\n"
"\n"
"<name> name of the file/dir/nod/etc in the archive\n"
"<location> location of the file in the current filesystem\n"
" expands shell variables quoted with ${}\n"
"<target> link target\n"
"<mode> mode/permissions of the file\n"
"<uid> user id (0=root)\n"
"<gid> group id (0=root)\n"
"<dev_type> device type (b=block, c=character)\n"
"<maj> major number of nod\n"
"<min> minor number of nod\n"
"<hard links> space separated list of other links to file\n"
"\n"
"example:\n"
"# A simple initramfs\n"
"dir /dev 0755 0 0\n"
"nod /dev/console 0600 0 0 c 5 1\n"
"dir /root 0700 0 0\n"
"dir /sbin 0755 0 0\n"
"file /sbin/kinit /usr/src/klibc/kinit/kinit 0755 0 0\n"
"\n"
"<timestamp> is time in seconds since Epoch that will be used\n"
"as mtime for symlinks, special files and directories. The default\n"
"is to use the current time for these entries.\n",
prog);
}
struct file_handler file_handler_table[] = {
{
.type = "file",
.handler = cpio_mkfile_line,
}, {
.type = "nod",
.handler = cpio_mknod_line,
}, {
.type = "dir",
.handler = cpio_mkdir_line,
}, {
.type = "slink",
.handler = cpio_mkslink_line,
}, {
.type = "pipe",
.handler = cpio_mkpipe_line,
}, {
.type = "sock",
.handler = cpio_mksock_line,
}, {
.type = NULL,
.handler = NULL,
}
};
#define LINE_SIZE (2 * PATH_MAX + 50)
int main (int argc, char *argv[])
{
FILE *cpio_list;
char line[LINE_SIZE];
char *args, *type;
int ec = 0;
int line_nr = 0;
const char *filename;
default_mtime = time(NULL);
while (1) {
int opt = getopt(argc, argv, "t:h");
char *invalid;
if (opt == -1)
break;
switch (opt) {
case 't':
default_mtime = strtol(optarg, &invalid, 10);
if (!*optarg || *invalid) {
fprintf(stderr, "Invalid timestamp: %s\n",
optarg);
usage(argv[0]);
exit(1);
}
break;
case 'h':
case '?':
usage(argv[0]);
exit(opt == 'h' ? 0 : 1);
}
}
if (argc - optind != 1) {
usage(argv[0]);
exit(1);
}
filename = argv[optind];
if (!strcmp(filename, "-"))
cpio_list = stdin;
else if (!(cpio_list = fopen(filename, "r"))) {
fprintf(stderr, "ERROR: unable to open '%s': %s\n\n",
filename, strerror(errno));
usage(argv[0]);
exit(1);
}
while (fgets(line, LINE_SIZE, cpio_list)) {
int type_idx;
size_t slen = strlen(line);
line_nr++;
if ('#' == *line) {
/* comment - skip to next line */
continue;
}
if (! (type = strtok(line, " \t"))) {
fprintf(stderr,
"ERROR: incorrect format, could not locate file type line %d: '%s'\n",
line_nr, line);
ec = -1;
break;
}
if ('\n' == *type) {
/* a blank line */
continue;
}
if (slen == strlen(type)) {
/* must be an empty line */
continue;
}
if (! (args = strtok(NULL, "\n"))) {
fprintf(stderr,
"ERROR: incorrect format, newline required line %d: '%s'\n",
line_nr, line);
ec = -1;
}
for (type_idx = 0; file_handler_table[type_idx].type; type_idx++) {
int rc;
if (! strcmp(line, file_handler_table[type_idx].type)) {
if ((rc = file_handler_table[type_idx].handler(args))) {
ec = rc;
fprintf(stderr, " line %d\n", line_nr);
}
break;
}
}
if (NULL == file_handler_table[type_idx].type) {
fprintf(stderr, "unknown file type line %d: '%s'\n",
line_nr, line);
}
}
if (ec == 0)
cpio_trailer();
exit(ec);
}
| gpl-2.0 |
shakalaca/ASUS_ZenFone_ZE601KL | kernel/net/netfilter/nf_nat_proto_common.c | 2539 | 3110 | /* (C) 1999-2001 Paul `Rusty' Russell
* (C) 2002-2006 Netfilter Core Team <coreteam@netfilter.org>
* (C) 2008 Patrick McHardy <kaber@trash.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/types.h>
#include <linux/random.h>
#include <linux/netfilter.h>
#include <linux/export.h>
#include <net/netfilter/nf_nat.h>
#include <net/netfilter/nf_nat_core.h>
#include <net/netfilter/nf_nat_l3proto.h>
#include <net/netfilter/nf_nat_l4proto.h>
bool nf_nat_l4proto_in_range(const struct nf_conntrack_tuple *tuple,
enum nf_nat_manip_type maniptype,
const union nf_conntrack_man_proto *min,
const union nf_conntrack_man_proto *max)
{
__be16 port;
if (maniptype == NF_NAT_MANIP_SRC)
port = tuple->src.u.all;
else
port = tuple->dst.u.all;
return ntohs(port) >= ntohs(min->all) &&
ntohs(port) <= ntohs(max->all);
}
EXPORT_SYMBOL_GPL(nf_nat_l4proto_in_range);
void nf_nat_l4proto_unique_tuple(const struct nf_nat_l3proto *l3proto,
struct nf_conntrack_tuple *tuple,
const struct nf_nat_range *range,
enum nf_nat_manip_type maniptype,
const struct nf_conn *ct,
u16 *rover)
{
unsigned int range_size, min, i;
__be16 *portptr;
u_int16_t off;
if (maniptype == NF_NAT_MANIP_SRC)
portptr = &tuple->src.u.all;
else
portptr = &tuple->dst.u.all;
/* If no range specified... */
if (!(range->flags & NF_NAT_RANGE_PROTO_SPECIFIED)) {
/* If it's dst rewrite, can't change port */
if (maniptype == NF_NAT_MANIP_DST)
return;
if (ntohs(*portptr) < 1024) {
/* Loose convention: >> 512 is credential passing */
if (ntohs(*portptr) < 512) {
min = 1;
range_size = 511 - min + 1;
} else {
min = 600;
range_size = 1023 - min + 1;
}
} else {
min = 1024;
range_size = 65535 - 1024 + 1;
}
} else {
min = ntohs(range->min_proto.all);
range_size = ntohs(range->max_proto.all) - min + 1;
}
if (range->flags & NF_NAT_RANGE_PROTO_RANDOM)
off = l3proto->secure_port(tuple, maniptype == NF_NAT_MANIP_SRC
? tuple->dst.u.all
: tuple->src.u.all);
else
off = *rover;
for (i = 0; ; ++off) {
*portptr = htons(min + off % range_size);
if (++i != range_size && nf_nat_used_tuple(tuple, ct))
continue;
if (!(range->flags & NF_NAT_RANGE_PROTO_RANDOM))
*rover = off;
return;
}
return;
}
EXPORT_SYMBOL_GPL(nf_nat_l4proto_unique_tuple);
#if defined(CONFIG_NF_CT_NETLINK) || defined(CONFIG_NF_CT_NETLINK_MODULE)
int nf_nat_l4proto_nlattr_to_range(struct nlattr *tb[],
struct nf_nat_range *range)
{
if (tb[CTA_PROTONAT_PORT_MIN]) {
range->min_proto.all = nla_get_be16(tb[CTA_PROTONAT_PORT_MIN]);
range->max_proto.all = range->min_proto.all;
range->flags |= NF_NAT_RANGE_PROTO_SPECIFIED;
}
if (tb[CTA_PROTONAT_PORT_MAX]) {
range->max_proto.all = nla_get_be16(tb[CTA_PROTONAT_PORT_MAX]);
range->flags |= NF_NAT_RANGE_PROTO_SPECIFIED;
}
return 0;
}
EXPORT_SYMBOL_GPL(nf_nat_l4proto_nlattr_to_range);
#endif
| gpl-2.0 |
ptmr3/N7100_Kernel | drivers/staging/easycap/easycap_settings.c | 2539 | 18284 | /******************************************************************************
* *
* easycap_settings.c *
* *
******************************************************************************/
/*
*
* Copyright (C) 2010 R.M. Thomas <rmthomas@sciolus.org>
*
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* The software is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/*****************************************************************************/
#include "easycap.h"
/*---------------------------------------------------------------------------*/
/*
* THE LEAST SIGNIFICANT BIT OF easycap_standard.mask HAS MEANING:
* 0 => 25 fps
* 1 => 30 fps
*
* THE MOST SIGNIFICANT BIT OF easycap_standard.mask HAS MEANING:
* 0 => full framerate
* 1 => 20% framerate
*/
/*---------------------------------------------------------------------------*/
const struct easycap_standard easycap_standard[] = {
{
.mask = 0x00FF & PAL_BGHIN ,
.v4l2_standard = {
.index = PAL_BGHIN,
.id = (V4L2_STD_PAL_B |
V4L2_STD_PAL_G | V4L2_STD_PAL_H |
V4L2_STD_PAL_I | V4L2_STD_PAL_N),
.name = "PAL_BGHIN",
.frameperiod = {1, 25},
.framelines = 625,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & NTSC_N_443 ,
.v4l2_standard = {
.index = NTSC_N_443,
.id = V4L2_STD_UNKNOWN,
.name = "NTSC_N_443",
.frameperiod = {1, 25},
.framelines = 480,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & PAL_Nc ,
.v4l2_standard = {
.index = PAL_Nc,
.id = V4L2_STD_PAL_Nc,
.name = "PAL_Nc",
.frameperiod = {1, 25},
.framelines = 625,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & NTSC_N ,
.v4l2_standard = {
.index = NTSC_N,
.id = V4L2_STD_UNKNOWN,
.name = "NTSC_N",
.frameperiod = {1, 25},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & SECAM ,
.v4l2_standard = {
.index = SECAM,
.id = V4L2_STD_SECAM,
.name = "SECAM",
.frameperiod = {1, 25},
.framelines = 625,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & NTSC_M ,
.v4l2_standard = {
.index = NTSC_M,
.id = V4L2_STD_NTSC_M,
.name = "NTSC_M",
.frameperiod = {1, 30},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & NTSC_M_JP ,
.v4l2_standard = {
.index = NTSC_M_JP,
.id = V4L2_STD_NTSC_M_JP,
.name = "NTSC_M_JP",
.frameperiod = {1, 30},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & PAL_60 ,
.v4l2_standard = {
.index = PAL_60,
.id = V4L2_STD_PAL_60,
.name = "PAL_60",
.frameperiod = {1, 30},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & NTSC_443 ,
.v4l2_standard = {
.index = NTSC_443,
.id = V4L2_STD_NTSC_443,
.name = "NTSC_443",
.frameperiod = {1, 30},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x00FF & PAL_M ,
.v4l2_standard = {
.index = PAL_M,
.id = V4L2_STD_PAL_M,
.name = "PAL_M",
.frameperiod = {1, 30},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & PAL_BGHIN_SLOW),
.v4l2_standard = {
.index = PAL_BGHIN_SLOW,
.id = (V4L2_STD_PAL_B | V4L2_STD_PAL_G |
V4L2_STD_PAL_H |
V4L2_STD_PAL_I | V4L2_STD_PAL_N |
(((v4l2_std_id)0x01) << 32)),
.name = "PAL_BGHIN_SLOW",
.frameperiod = {1, 5},
.framelines = 625,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & NTSC_N_443_SLOW),
.v4l2_standard = {
.index = NTSC_N_443_SLOW,
.id = (V4L2_STD_UNKNOWN | (((v4l2_std_id)0x11) << 32)),
.name = "NTSC_N_443_SLOW",
.frameperiod = {1, 5},
.framelines = 480,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & PAL_Nc_SLOW),
.v4l2_standard = {
.index = PAL_Nc_SLOW,
.id = (V4L2_STD_PAL_Nc | (((v4l2_std_id)0x01) << 32)),
.name = "PAL_Nc_SLOW",
.frameperiod = {1, 5},
.framelines = 625,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & NTSC_N_SLOW),
.v4l2_standard = {
.index = NTSC_N_SLOW,
.id = (V4L2_STD_UNKNOWN | (((v4l2_std_id)0x21) << 32)),
.name = "NTSC_N_SLOW",
.frameperiod = {1, 5},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & SECAM_SLOW),
.v4l2_standard = {
.index = SECAM_SLOW,
.id = (V4L2_STD_SECAM | (((v4l2_std_id)0x01) << 32)),
.name = "SECAM_SLOW",
.frameperiod = {1, 5},
.framelines = 625,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & NTSC_M_SLOW),
.v4l2_standard = {
.index = NTSC_M_SLOW,
.id = (V4L2_STD_NTSC_M | (((v4l2_std_id)0x01) << 32)),
.name = "NTSC_M_SLOW",
.frameperiod = {1, 6},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & NTSC_M_JP_SLOW),
.v4l2_standard = {
.index = NTSC_M_JP_SLOW,
.id = (V4L2_STD_NTSC_M_JP |
(((v4l2_std_id)0x01) << 32)),
.name = "NTSC_M_JP_SLOW",
.frameperiod = {1, 6},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & PAL_60_SLOW),
.v4l2_standard = {
.index = PAL_60_SLOW,
.id = (V4L2_STD_PAL_60 | (((v4l2_std_id)0x01) << 32)),
.name = "PAL_60_SLOW",
.frameperiod = {1, 6},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & NTSC_443_SLOW),
.v4l2_standard = {
.index = NTSC_443_SLOW,
.id = (V4L2_STD_NTSC_443 | (((v4l2_std_id)0x01) << 32)),
.name = "NTSC_443_SLOW",
.frameperiod = {1, 6},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0x8000 | (0x00FF & PAL_M_SLOW),
.v4l2_standard = {
.index = PAL_M_SLOW,
.id = (V4L2_STD_PAL_M | (((v4l2_std_id)0x01) << 32)),
.name = "PAL_M_SLOW",
.frameperiod = {1, 6},
.framelines = 525,
.reserved = {0, 0, 0, 0}
}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.mask = 0xFFFF
}
};
/*---------------------------------------------------------------------------*/
/*
* THE 16-BIT easycap_format.mask HAS MEANING:
* (least significant) BIT 0: 0 => PAL, 25 FPS; 1 => NTSC, 30 FPS
* BITS 2-4: RESERVED FOR DIFFERENTIATING STANDARDS
* BITS 5-7: NUMBER OF BYTES PER PIXEL
* BIT 8: 0 => NATIVE BYTE ORDER; 1 => SWAPPED
* BITS 9-10: RESERVED FOR OTHER BYTE PERMUTATIONS
* BIT 11: 0 => UNDECIMATED; 1 => DECIMATED
* BIT 12: 0 => OFFER FRAMES; 1 => OFFER FIELDS
* BIT 13: 0 => FULL FRAMERATE; 1 => REDUCED
* (most significant) BITS 14-15: RESERVED FOR OTHER FIELD/FRAME OPTIONS
* IT FOLLOWS THAT:
* bytesperpixel IS ((0x00E0 & easycap_format.mask) >> 5)
* byteswaporder IS true IF (0 != (0x0100 & easycap_format.mask))
*
* decimatepixel IS true IF (0 != (0x0800 & easycap_format.mask))
*
* offerfields IS true IF (0 != (0x1000 & easycap_format.mask))
*/
/*---------------------------------------------------------------------------*/
struct easycap_format easycap_format[1 + SETTINGS_MANY];
int fillin_formats(void)
{
const char *name1, *name2, *name3, *name4;
struct v4l2_format *fmt;
int i, j, k, m, n;
u32 width, height, pixelformat, bytesperline, sizeimage;
u16 mask1, mask2, mask3, mask4;
enum v4l2_field field;
enum v4l2_colorspace colorspace;
for (i = 0, n = 0; i < STANDARD_MANY; i++) {
mask1 = 0x0000;
switch (i) {
case PAL_BGHIN: {
mask1 = 0x1F & PAL_BGHIN;
name1 = "PAL_BGHIN";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case SECAM: {
mask1 = 0x1F & SECAM;
name1 = "SECAM";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case PAL_Nc: {
mask1 = 0x1F & PAL_Nc;
name1 = "PAL_Nc";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case PAL_60: {
mask1 = 0x1F & PAL_60;
name1 = "PAL_60";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case PAL_M: {
mask1 = 0x1F & PAL_M;
name1 = "PAL_M";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case NTSC_M: {
mask1 = 0x1F & NTSC_M;
name1 = "NTSC_M";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_443: {
mask1 = 0x1F & NTSC_443;
name1 = "NTSC_443";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_M_JP: {
mask1 = 0x1F & NTSC_M_JP;
name1 = "NTSC_M_JP";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_N: {
mask1 = 0x1F & NTSC_M;
name1 = "NTSC_N";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_N_443: {
mask1 = 0x1F & NTSC_N_443;
name1 = "NTSC_N_443";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case PAL_BGHIN_SLOW: {
mask1 = 0x001F & PAL_BGHIN_SLOW;
mask1 |= 0x0200;
name1 = "PAL_BGHIN_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case SECAM_SLOW: {
mask1 = 0x001F & SECAM_SLOW;
mask1 |= 0x0200;
name1 = "SECAM_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case PAL_Nc_SLOW: {
mask1 = 0x001F & PAL_Nc_SLOW;
mask1 |= 0x0200;
name1 = "PAL_Nc_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case PAL_60_SLOW: {
mask1 = 0x001F & PAL_60_SLOW;
mask1 |= 0x0200;
name1 = "PAL_60_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case PAL_M_SLOW: {
mask1 = 0x001F & PAL_M_SLOW;
mask1 |= 0x0200;
name1 = "PAL_M_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_BG;
break;
}
case NTSC_M_SLOW: {
mask1 = 0x001F & NTSC_M_SLOW;
mask1 |= 0x0200;
name1 = "NTSC_M_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_443_SLOW: {
mask1 = 0x001F & NTSC_443_SLOW;
mask1 |= 0x0200;
name1 = "NTSC_443_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_M_JP_SLOW: {
mask1 = 0x001F & NTSC_M_JP_SLOW;
mask1 |= 0x0200;
name1 = "NTSC_M_JP_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_N_SLOW: {
mask1 = 0x001F & NTSC_N_SLOW;
mask1 |= 0x0200;
name1 = "NTSC_N_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
case NTSC_N_443_SLOW: {
mask1 = 0x001F & NTSC_N_443_SLOW;
mask1 |= 0x0200;
name1 = "NTSC_N_443_SLOW";
colorspace = V4L2_COLORSPACE_470_SYSTEM_M;
break;
}
default:
return -1;
}
for (j = 0; j < RESOLUTION_MANY; j++) {
mask2 = 0x0000;
switch (j) {
case AT_720x576: {
if (0x1 & mask1)
continue;
name2 = "_AT_720x576";
width = 720;
height = 576;
break;
}
case AT_704x576: {
if (0x1 & mask1)
continue;
name2 = "_AT_704x576";
width = 704;
height = 576;
break;
}
case AT_640x480: {
name2 = "_AT_640x480";
width = 640;
height = 480;
break;
}
case AT_720x480: {
if (!(0x1 & mask1))
continue;
name2 = "_AT_720x480";
width = 720;
height = 480;
break;
}
case AT_360x288: {
if (0x1 & mask1)
continue;
name2 = "_AT_360x288";
width = 360;
height = 288;
mask2 = 0x0800;
break;
}
case AT_320x240: {
name2 = "_AT_320x240";
width = 320;
height = 240;
mask2 = 0x0800;
break;
}
case AT_360x240: {
if (!(0x1 & mask1))
continue;
name2 = "_AT_360x240";
width = 360;
height = 240;
mask2 = 0x0800;
break;
}
default:
return -2;
}
for (k = 0; k < PIXELFORMAT_MANY; k++) {
mask3 = 0x0000;
switch (k) {
case FMT_UYVY: {
name3 = __stringify(FMT_UYVY);
pixelformat = V4L2_PIX_FMT_UYVY;
mask3 |= (0x02 << 5);
break;
}
case FMT_YUY2: {
name3 = __stringify(FMT_YUY2);
pixelformat = V4L2_PIX_FMT_YUYV;
mask3 |= (0x02 << 5);
mask3 |= 0x0100;
break;
}
case FMT_RGB24: {
name3 = __stringify(FMT_RGB24);
pixelformat = V4L2_PIX_FMT_RGB24;
mask3 |= (0x03 << 5);
break;
}
case FMT_RGB32: {
name3 = __stringify(FMT_RGB32);
pixelformat = V4L2_PIX_FMT_RGB32;
mask3 |= (0x04 << 5);
break;
}
case FMT_BGR24: {
name3 = __stringify(FMT_BGR24);
pixelformat = V4L2_PIX_FMT_BGR24;
mask3 |= (0x03 << 5);
mask3 |= 0x0100;
break;
}
case FMT_BGR32: {
name3 = __stringify(FMT_BGR32);
pixelformat = V4L2_PIX_FMT_BGR32;
mask3 |= (0x04 << 5);
mask3 |= 0x0100;
break;
}
default:
return -3;
}
bytesperline = width * ((mask3 & 0x00F0) >> 4);
sizeimage = bytesperline * height;
for (m = 0; m < INTERLACE_MANY; m++) {
mask4 = 0x0000;
switch (m) {
case FIELD_NONE: {
name4 = "-n";
field = V4L2_FIELD_NONE;
break;
}
case FIELD_INTERLACED: {
name4 = "-i";
mask4 |= 0x1000;
field = V4L2_FIELD_INTERLACED;
break;
}
default:
return -4;
}
if (SETTINGS_MANY <= n)
return -5;
strcpy(easycap_format[n].name, name1);
strcat(easycap_format[n].name, name2);
strcat(easycap_format[n].name, "_");
strcat(easycap_format[n].name, name3);
strcat(easycap_format[n].name, name4);
easycap_format[n].mask =
mask1 | mask2 | mask3 | mask4;
fmt = &easycap_format[n].v4l2_format;
fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
fmt->fmt.pix.width = width;
fmt->fmt.pix.height = height;
fmt->fmt.pix.pixelformat = pixelformat;
fmt->fmt.pix.field = field;
fmt->fmt.pix.bytesperline = bytesperline;
fmt->fmt.pix.sizeimage = sizeimage;
fmt->fmt.pix.colorspace = colorspace;
fmt->fmt.pix.priv = 0;
n++;
}
}
}
}
if ((1 + SETTINGS_MANY) <= n)
return -6;
easycap_format[n].mask = 0xFFFF;
return n;
}
/*---------------------------------------------------------------------------*/
struct v4l2_queryctrl easycap_control[] = {
{
.id = V4L2_CID_BRIGHTNESS,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Brightness",
.minimum = 0,
.maximum = 255,
.step = 1,
.default_value = SAA_0A_DEFAULT,
.flags = 0,
.reserved = {0, 0}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.id = V4L2_CID_CONTRAST,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Contrast",
.minimum = 0,
.maximum = 255,
.step = 1,
.default_value = SAA_0B_DEFAULT + 128,
.flags = 0,
.reserved = {0, 0}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.id = V4L2_CID_SATURATION,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Saturation",
.minimum = 0,
.maximum = 255,
.step = 1,
.default_value = SAA_0C_DEFAULT + 128,
.flags = 0,
.reserved = {0, 0}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.id = V4L2_CID_HUE,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Hue",
.minimum = 0,
.maximum = 255,
.step = 1,
.default_value = SAA_0D_DEFAULT + 128,
.flags = 0,
.reserved = {0, 0}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.id = V4L2_CID_AUDIO_VOLUME,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Volume",
.minimum = 0,
.maximum = 31,
.step = 1,
.default_value = 16,
.flags = 0,
.reserved = {0, 0}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.id = V4L2_CID_AUDIO_MUTE,
.type = V4L2_CTRL_TYPE_BOOLEAN,
.name = "Mute",
.default_value = true,
.flags = 0,
.reserved = {0, 0}
},
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
{
.id = 0xFFFFFFFF
}
};
/*****************************************************************************/
| gpl-2.0 |
Team-Exhibit/android_kernel_samsung_u8500 | drivers/i2c/busses/i2c-pxa-pci.c | 2539 | 3875 | /*
* The CE4100's I2C device is more or less the same one as found on PXA.
* It does not support slave mode, the register slightly moved. This PCI
* device provides three bars, every contains a single I2C controller.
*/
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#define CE4100_PCI_I2C_DEVS 3
struct ce4100_devices {
struct platform_device *pdev[CE4100_PCI_I2C_DEVS];
};
static struct platform_device *add_i2c_device(struct pci_dev *dev, int bar)
{
struct platform_device *pdev;
struct i2c_pxa_platform_data pdata;
struct resource res[2];
struct device_node *child;
static int devnum;
int ret;
memset(&pdata, 0, sizeof(struct i2c_pxa_platform_data));
memset(&res, 0, sizeof(res));
res[0].flags = IORESOURCE_MEM;
res[0].start = pci_resource_start(dev, bar);
res[0].end = pci_resource_end(dev, bar);
res[1].flags = IORESOURCE_IRQ;
res[1].start = dev->irq;
res[1].end = dev->irq;
for_each_child_of_node(dev->dev.of_node, child) {
const void *prop;
struct resource r;
int ret;
ret = of_address_to_resource(child, 0, &r);
if (ret < 0)
continue;
if (r.start != res[0].start)
continue;
if (r.end != res[0].end)
continue;
if (r.flags != res[0].flags)
continue;
prop = of_get_property(child, "fast-mode", NULL);
if (prop)
pdata.fast_mode = 1;
break;
}
if (!child) {
dev_err(&dev->dev, "failed to match a DT node for bar %d.\n",
bar);
ret = -EINVAL;
goto out;
}
pdev = platform_device_alloc("ce4100-i2c", devnum);
if (!pdev) {
of_node_put(child);
ret = -ENOMEM;
goto out;
}
pdev->dev.parent = &dev->dev;
pdev->dev.of_node = child;
ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
if (ret)
goto err;
ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
if (ret)
goto err;
ret = platform_device_add(pdev);
if (ret)
goto err;
devnum++;
return pdev;
err:
platform_device_put(pdev);
out:
return ERR_PTR(ret);
}
static int __devinit ce4100_i2c_probe(struct pci_dev *dev,
const struct pci_device_id *ent)
{
int ret;
int i;
struct ce4100_devices *sds;
ret = pci_enable_device_mem(dev);
if (ret)
return ret;
if (!dev->dev.of_node) {
dev_err(&dev->dev, "Missing device tree node.\n");
return -EINVAL;
}
sds = kzalloc(sizeof(*sds), GFP_KERNEL);
if (!sds)
goto err_mem;
for (i = 0; i < ARRAY_SIZE(sds->pdev); i++) {
sds->pdev[i] = add_i2c_device(dev, i);
if (IS_ERR(sds->pdev[i])) {
while (--i >= 0)
platform_device_unregister(sds->pdev[i]);
goto err_dev_add;
}
}
pci_set_drvdata(dev, sds);
return 0;
err_dev_add:
pci_set_drvdata(dev, NULL);
kfree(sds);
err_mem:
pci_disable_device(dev);
return ret;
}
static void __devexit ce4100_i2c_remove(struct pci_dev *dev)
{
struct ce4100_devices *sds;
unsigned int i;
sds = pci_get_drvdata(dev);
pci_set_drvdata(dev, NULL);
for (i = 0; i < ARRAY_SIZE(sds->pdev); i++)
platform_device_unregister(sds->pdev[i]);
pci_disable_device(dev);
kfree(sds);
}
static struct pci_device_id ce4100_i2c_devices[] __devinitdata = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2e68)},
{ },
};
MODULE_DEVICE_TABLE(pci, ce4100_i2c_devices);
static struct pci_driver ce4100_i2c_driver = {
.name = "ce4100_i2c",
.id_table = ce4100_i2c_devices,
.probe = ce4100_i2c_probe,
.remove = __devexit_p(ce4100_i2c_remove),
};
static int __init ce4100_i2c_init(void)
{
return pci_register_driver(&ce4100_i2c_driver);
}
module_init(ce4100_i2c_init);
static void __exit ce4100_i2c_exit(void)
{
pci_unregister_driver(&ce4100_i2c_driver);
}
module_exit(ce4100_i2c_exit);
MODULE_DESCRIPTION("CE4100 PCI-I2C glue code for PXA's driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
| gpl-2.0 |
KronicKernel/falcon | arch/arm/mach-imx/mach-mx53_loco.c | 4843 | 9393 | /*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx53.h"
#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define LOCO_LED IMX_GPIO_NR(7, 7)
#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14)
static iomux_v3_cfg_t mx53_loco_pads[] = {
/* FEC */
MX53_PAD_FEC_MDC__FEC_MDC,
MX53_PAD_FEC_MDIO__FEC_MDIO,
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
MX53_PAD_FEC_RX_ER__FEC_RX_ER,
MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
MX53_PAD_FEC_RXD1__FEC_RDATA_1,
MX53_PAD_FEC_RXD0__FEC_RDATA_0,
MX53_PAD_FEC_TX_EN__FEC_TX_EN,
MX53_PAD_FEC_TXD1__FEC_TDATA_1,
MX53_PAD_FEC_TXD0__FEC_TDATA_0,
/* FEC_nRST */
MX53_PAD_PATA_DA_0__GPIO7_6,
/* FEC_nINT */
MX53_PAD_PATA_DATA4__GPIO2_4,
/* AUDMUX5 */
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */
/* I2C2 */
MX53_PAD_KEY_COL3__I2C2_SCL,
MX53_PAD_KEY_ROW3__I2C2_SDA,
/* SD1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1_CD */
MX53_PAD_EIM_DA13__GPIO3_13,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
/* SD3_CD */
MX53_PAD_EIM_DA11__GPIO3_11,
/* SD3_WP */
MX53_PAD_EIM_DA12__GPIO3_12,
/* VGA */
MX53_PAD_EIM_OE__IPU_DI1_PIN7,
MX53_PAD_EIM_RW__IPU_DI1_PIN8,
/* DISPLB */
MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
/* DISP0_POWER_EN */
MX53_PAD_EIM_D24__GPIO3_24,
/* DISP0 DET INT */
MX53_PAD_EIM_D31__GPIO3_31,
/* LVDS */
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
/* UART1 */
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
/* CSI0 */
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
/* DISPLAY */
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
/* Audio CLK*/
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
/* PWM */
MX53_PAD_GPIO_1__PWM2_PWMO,
/* SPDIF */
MX53_PAD_GPIO_7__SPDIF_PLOCK,
MX53_PAD_GPIO_17__SPDIF_OUT1,
/* GPIO */
MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
MX53_PAD_PATA_DA_2__GPIO7_8,
MX53_PAD_PATA_DATA5__GPIO2_5,
MX53_PAD_PATA_DATA6__GPIO2_6,
MX53_PAD_PATA_DATA14__GPIO2_14,
MX53_PAD_PATA_DATA15__GPIO2_15,
MX53_PAD_PATA_INTRQ__GPIO7_2,
MX53_PAD_EIM_WAIT__GPIO5_0,
MX53_PAD_NANDF_WP_B__GPIO6_9,
MX53_PAD_NANDF_RB0__GPIO6_10,
MX53_PAD_NANDF_CS1__GPIO6_14,
MX53_PAD_NANDF_CS2__GPIO6_15,
MX53_PAD_NANDF_CS3__GPIO6_16,
MX53_PAD_GPIO_5__GPIO1_5,
MX53_PAD_GPIO_16__GPIO7_11,
MX53_PAD_GPIO_8__GPIO1_8,
};
#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
{ \
.gpio = gpio_num, \
.type = EV_KEY, \
.code = ev_code, \
.active_low = act_low, \
.desc = "btn " descr, \
.wakeup = wake, \
}
static struct gpio_keys_button loco_buttons[] = {
GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
};
static const struct gpio_keys_platform_data loco_button_data __initconst = {
.buttons = loco_buttons,
.nbuttons = ARRAY_SIZE(loco_buttons),
};
static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
.cd_gpio = LOCO_SD1_CD,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_NONE,
};
static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
.cd_gpio = LOCO_SD3_CD,
.wp_gpio = LOCO_SD3_WP,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_GPIO,
};
static inline void mx53_loco_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
gpio_direction_output(LOCO_FEC_PHY_RST, 0);
msleep(1);
gpio_set_value(LOCO_FEC_PHY_RST, 1);
}
static const struct fec_platform_data mx53_loco_fec_data __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
.bitrate = 100000,
};
static const struct gpio_led mx53loco_leds[] __initconst = {
{
.name = "green",
.default_trigger = "heartbeat",
.gpio = LOCO_LED,
},
};
static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
.leds = mx53loco_leds,
.num_leds = ARRAY_SIZE(mx53loco_leds),
};
void __init imx53_qsb_common_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
ARRAY_SIZE(mx53_loco_pads));
}
static struct i2c_board_info mx53loco_i2c_devices[] = {
{
I2C_BOARD_INFO("mma8450", 0x1C),
},
};
static void __init mx53_loco_board_init(void)
{
int ret;
imx53_soc_init();
imx53_qsb_common_init();
imx53_add_imx_uart(0, NULL);
mx53_loco_fec_reset();
imx53_add_fec(&mx53_loco_fec_data);
imx53_add_imx2_wdt(0, NULL);
ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
if (ret)
pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
i2c_register_board_info(0, mx53loco_i2c_devices,
ARRAY_SIZE(mx53loco_i2c_devices));
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
imx_add_gpio_keys(&loco_button_data);
gpio_led_register_device(-1, &mx53loco_leds_data);
imx53_add_ahci_imx();
}
static void __init mx53_loco_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 0, 0);
}
static struct sys_timer mx53_loco_timer = {
.init = mx53_loco_timer_init,
};
MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.timer = &mx53_loco_timer,
.init_machine = mx53_loco_board_init,
.restart = mxc_restart,
MACHINE_END
| gpl-2.0 |
Haxynox/kernel_samsung_n7100-old | drivers/media/dvb/dvb-usb/vp7045-fe.c | 5099 | 5077 | /* DVB frontend part of the Linux driver for TwinhanDTV Alpha/MagicBoxII USB2.0
* DVB-T receiver.
*
* Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
*
* Thanks to Twinhan who kindly provided hardware and information.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation, version 2.
*
* see Documentation/dvb/README.dvb-usb for more information
*
*/
#include "vp7045.h"
/* It is a Zarlink MT352 within a Samsung Tuner (DNOS404ZH102A) - 040929 - AAT
*
* Programming is hidden inside the firmware, so set_frontend is very easy.
* Even though there is a Firmware command that one can use to access the demod
* via its registers. This is used for status information.
*/
struct vp7045_fe_state {
struct dvb_frontend fe;
struct dvb_usb_device *d;
};
static int vp7045_fe_read_status(struct dvb_frontend* fe, fe_status_t *status)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
u8 s0 = vp7045_read_reg(state->d,0x00),
s1 = vp7045_read_reg(state->d,0x01),
s3 = vp7045_read_reg(state->d,0x03);
*status = 0;
if (s0 & (1 << 4))
*status |= FE_HAS_CARRIER;
if (s0 & (1 << 1))
*status |= FE_HAS_VITERBI;
if (s0 & (1 << 5))
*status |= FE_HAS_LOCK;
if (s1 & (1 << 1))
*status |= FE_HAS_SYNC;
if (s3 & (1 << 6))
*status |= FE_HAS_SIGNAL;
if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
(FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
*status &= ~FE_HAS_LOCK;
return 0;
}
static int vp7045_fe_read_ber(struct dvb_frontend* fe, u32 *ber)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
*ber = (vp7045_read_reg(state->d, 0x0D) << 16) |
(vp7045_read_reg(state->d, 0x0E) << 8) |
vp7045_read_reg(state->d, 0x0F);
return 0;
}
static int vp7045_fe_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
*unc = (vp7045_read_reg(state->d, 0x10) << 8) |
vp7045_read_reg(state->d, 0x11);
return 0;
}
static int vp7045_fe_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
u16 signal = (vp7045_read_reg(state->d, 0x14) << 8) |
vp7045_read_reg(state->d, 0x15);
*strength = ~signal;
return 0;
}
static int vp7045_fe_read_snr(struct dvb_frontend* fe, u16 *snr)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
u8 _snr = vp7045_read_reg(state->d, 0x09);
*snr = (_snr << 8) | _snr;
return 0;
}
static int vp7045_fe_init(struct dvb_frontend* fe)
{
return 0;
}
static int vp7045_fe_sleep(struct dvb_frontend* fe)
{
return 0;
}
static int vp7045_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 800;
return 0;
}
static int vp7045_fe_set_frontend(struct dvb_frontend* fe,
struct dvb_frontend_parameters *fep)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
u8 buf[5];
u32 freq = fep->frequency / 1000;
buf[0] = (freq >> 16) & 0xff;
buf[1] = (freq >> 8) & 0xff;
buf[2] = freq & 0xff;
buf[3] = 0;
switch (fep->u.ofdm.bandwidth) {
case BANDWIDTH_8_MHZ: buf[4] = 8; break;
case BANDWIDTH_7_MHZ: buf[4] = 7; break;
case BANDWIDTH_6_MHZ: buf[4] = 6; break;
case BANDWIDTH_AUTO: return -EOPNOTSUPP;
default:
return -EINVAL;
}
vp7045_usb_op(state->d,LOCK_TUNER_COMMAND,buf,5,NULL,0,200);
return 0;
}
static int vp7045_fe_get_frontend(struct dvb_frontend* fe,
struct dvb_frontend_parameters *fep)
{
return 0;
}
static void vp7045_fe_release(struct dvb_frontend* fe)
{
struct vp7045_fe_state *state = fe->demodulator_priv;
kfree(state);
}
static struct dvb_frontend_ops vp7045_fe_ops;
struct dvb_frontend * vp7045_fe_attach(struct dvb_usb_device *d)
{
struct vp7045_fe_state *s = kzalloc(sizeof(struct vp7045_fe_state), GFP_KERNEL);
if (s == NULL)
goto error;
s->d = d;
memcpy(&s->fe.ops, &vp7045_fe_ops, sizeof(struct dvb_frontend_ops));
s->fe.demodulator_priv = s;
return &s->fe;
error:
return NULL;
}
static struct dvb_frontend_ops vp7045_fe_ops = {
.info = {
.name = "Twinhan VP7045/46 USB DVB-T",
.type = FE_OFDM,
.frequency_min = 44250000,
.frequency_max = 867250000,
.frequency_stepsize = 1000,
.caps = FE_CAN_INVERSION_AUTO |
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_RECOVER |
FE_CAN_HIERARCHY_AUTO,
},
.release = vp7045_fe_release,
.init = vp7045_fe_init,
.sleep = vp7045_fe_sleep,
.set_frontend = vp7045_fe_set_frontend,
.get_frontend = vp7045_fe_get_frontend,
.get_tune_settings = vp7045_fe_get_tune_settings,
.read_status = vp7045_fe_read_status,
.read_ber = vp7045_fe_read_ber,
.read_signal_strength = vp7045_fe_read_signal_strength,
.read_snr = vp7045_fe_read_snr,
.read_ucblocks = vp7045_fe_read_unc_blocks,
};
| gpl-2.0 |
myfluxi/android_kernel_oneplus_msm8974 | drivers/hid/hid-cypress.c | 6123 | 3943 | /*
* HID driver for some cypress "special" devices
*
* Copyright (c) 1999 Andreas Gal
* Copyright (c) 2000-2005 Vojtech Pavlik <vojtech@suse.cz>
* Copyright (c) 2005 Michael Haboustak <mike-@cinci.rr.com> for Concept2, Inc
* Copyright (c) 2006-2007 Jiri Kosina
* Copyright (c) 2007 Paul Walmsley
* Copyright (c) 2008 Jiri Slaby
*/
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <linux/device.h>
#include <linux/hid.h>
#include <linux/input.h>
#include <linux/module.h>
#include "hid-ids.h"
#define CP_RDESC_SWAPPED_MIN_MAX 0x01
#define CP_2WHEEL_MOUSE_HACK 0x02
#define CP_2WHEEL_MOUSE_HACK_ON 0x04
/*
* Some USB barcode readers from cypress have usage min and usage max in
* the wrong order
*/
static __u8 *cp_report_fixup(struct hid_device *hdev, __u8 *rdesc,
unsigned int *rsize)
{
unsigned long quirks = (unsigned long)hid_get_drvdata(hdev);
unsigned int i;
if (!(quirks & CP_RDESC_SWAPPED_MIN_MAX))
return rdesc;
for (i = 0; i < *rsize - 4; i++)
if (rdesc[i] == 0x29 && rdesc[i + 2] == 0x19) {
__u8 tmp;
rdesc[i] = 0x19;
rdesc[i + 2] = 0x29;
tmp = rdesc[i + 3];
rdesc[i + 3] = rdesc[i + 1];
rdesc[i + 1] = tmp;
}
return rdesc;
}
static int cp_input_mapped(struct hid_device *hdev, struct hid_input *hi,
struct hid_field *field, struct hid_usage *usage,
unsigned long **bit, int *max)
{
unsigned long quirks = (unsigned long)hid_get_drvdata(hdev);
if (!(quirks & CP_2WHEEL_MOUSE_HACK))
return 0;
if (usage->type == EV_REL && usage->code == REL_WHEEL)
set_bit(REL_HWHEEL, *bit);
if (usage->hid == 0x00090005)
return -1;
return 0;
}
static int cp_event(struct hid_device *hdev, struct hid_field *field,
struct hid_usage *usage, __s32 value)
{
unsigned long quirks = (unsigned long)hid_get_drvdata(hdev);
if (!(hdev->claimed & HID_CLAIMED_INPUT) || !field->hidinput ||
!usage->type || !(quirks & CP_2WHEEL_MOUSE_HACK))
return 0;
if (usage->hid == 0x00090005) {
if (value)
quirks |= CP_2WHEEL_MOUSE_HACK_ON;
else
quirks &= ~CP_2WHEEL_MOUSE_HACK_ON;
hid_set_drvdata(hdev, (void *)quirks);
return 1;
}
if (usage->code == REL_WHEEL && (quirks & CP_2WHEEL_MOUSE_HACK_ON)) {
struct input_dev *input = field->hidinput->input;
input_event(input, usage->type, REL_HWHEEL, value);
return 1;
}
return 0;
}
static int cp_probe(struct hid_device *hdev, const struct hid_device_id *id)
{
unsigned long quirks = id->driver_data;
int ret;
hid_set_drvdata(hdev, (void *)quirks);
ret = hid_parse(hdev);
if (ret) {
hid_err(hdev, "parse failed\n");
goto err_free;
}
ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT);
if (ret) {
hid_err(hdev, "hw start failed\n");
goto err_free;
}
return 0;
err_free:
return ret;
}
static const struct hid_device_id cp_devices[] = {
{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_1),
.driver_data = CP_RDESC_SWAPPED_MIN_MAX },
{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_2),
.driver_data = CP_RDESC_SWAPPED_MIN_MAX },
{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_BARCODE_3),
.driver_data = CP_RDESC_SWAPPED_MIN_MAX },
{ HID_USB_DEVICE(USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_MOUSE),
.driver_data = CP_2WHEEL_MOUSE_HACK },
{ }
};
MODULE_DEVICE_TABLE(hid, cp_devices);
static struct hid_driver cp_driver = {
.name = "cypress",
.id_table = cp_devices,
.report_fixup = cp_report_fixup,
.input_mapped = cp_input_mapped,
.event = cp_event,
.probe = cp_probe,
};
static int __init cp_init(void)
{
return hid_register_driver(&cp_driver);
}
static void __exit cp_exit(void)
{
hid_unregister_driver(&cp_driver);
}
module_init(cp_init);
module_exit(cp_exit);
MODULE_LICENSE("GPL");
| gpl-2.0 |
markyzq/kernel-next | arch/alpha/boot/main.c | 7915 | 4373 | /*
* arch/alpha/boot/main.c
*
* Copyright (C) 1994, 1995 Linus Torvalds
*
* This file is the bootloader for the Linux/AXP kernel
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <generated/utsrelease.h>
#include <linux/mm.h>
#include <asm/console.h>
#include <asm/hwrpb.h>
#include <asm/pgtable.h>
#include <stdarg.h>
#include "ksize.h"
extern int vsprintf(char *, const char *, va_list);
extern unsigned long switch_to_osf_pal(unsigned long nr,
struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa,
unsigned long *vptb);
struct hwrpb_struct *hwrpb = INIT_HWRPB;
static struct pcb_struct pcb_va[1];
/*
* Find a physical address of a virtual object..
*
* This is easy using the virtual page table address.
*/
static inline void *
find_pa(unsigned long *vptb, void *ptr)
{
unsigned long address = (unsigned long) ptr;
unsigned long result;
result = vptb[address >> 13];
result >>= 32;
result <<= 13;
result |= address & 0x1fff;
return (void *) result;
}
/*
* This function moves into OSF/1 pal-code, and has a temporary
* PCB for that. The kernel proper should replace this PCB with
* the real one as soon as possible.
*
* The page table muckery in here depends on the fact that the boot
* code has the L1 page table identity-map itself in the second PTE
* in the L1 page table. Thus the L1-page is virtually addressable
* itself (through three levels) at virtual address 0x200802000.
*/
#define VPTB ((unsigned long *) 0x200000000)
#define L1 ((unsigned long *) 0x200802000)
void
pal_init(void)
{
unsigned long i, rev;
struct percpu_struct * percpu;
struct pcb_struct * pcb_pa;
/* Create the dummy PCB. */
pcb_va->ksp = 0;
pcb_va->usp = 0;
pcb_va->ptbr = L1[1] >> 32;
pcb_va->asn = 0;
pcb_va->pcc = 0;
pcb_va->unique = 0;
pcb_va->flags = 1;
pcb_va->res1 = 0;
pcb_va->res2 = 0;
pcb_pa = find_pa(VPTB, pcb_va);
/*
* a0 = 2 (OSF)
* a1 = return address, but we give the asm the vaddr of the PCB
* a2 = physical addr of PCB
* a3 = new virtual page table pointer
* a4 = KSP (but the asm sets it)
*/
srm_printk("Switching to OSF PAL-code .. ");
i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
if (i) {
srm_printk("failed, code %ld\n", i);
__halt();
}
percpu = (struct percpu_struct *)
(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
rev = percpu->pal_revision = percpu->palcode_avail[2];
srm_printk("Ok (rev %lx)\n", rev);
tbia(); /* do it directly in case we are SMP */
}
static inline long openboot(void)
{
char bootdev[256];
long result;
result = callback_getenv(ENV_BOOTED_DEV, bootdev, 255);
if (result < 0)
return result;
return callback_open(bootdev, result & 255);
}
static inline long close(long dev)
{
return callback_close(dev);
}
static inline long load(long dev, unsigned long addr, unsigned long count)
{
char bootfile[256];
extern char _end;
long result, boot_size = &_end - (char *) BOOT_ADDR;
result = callback_getenv(ENV_BOOTED_FILE, bootfile, 255);
if (result < 0)
return result;
result &= 255;
bootfile[result] = '\0';
if (result)
srm_printk("Boot file specification (%s) not implemented\n",
bootfile);
return callback_read(dev, count, (void *)addr, boot_size/512 + 1);
}
/*
* Start the kernel.
*/
static void runkernel(void)
{
__asm__ __volatile__(
"bis %1,%1,$30\n\t"
"bis %0,%0,$26\n\t"
"ret ($26)"
: /* no outputs: it doesn't even return */
: "r" (START_ADDR),
"r" (PAGE_SIZE + INIT_STACK));
}
void start_kernel(void)
{
long i;
long dev;
int nbytes;
char envval[256];
srm_printk("Linux/AXP bootloader for Linux " UTS_RELEASE "\n");
if (INIT_HWRPB->pagesize != 8192) {
srm_printk("Expected 8kB pages, got %ldkB\n", INIT_HWRPB->pagesize >> 10);
return;
}
pal_init();
dev = openboot();
if (dev < 0) {
srm_printk("Unable to open boot device: %016lx\n", dev);
return;
}
dev &= 0xffffffff;
srm_printk("Loading vmlinux ...");
i = load(dev, START_ADDR, KERNEL_SIZE);
close(dev);
if (i != KERNEL_SIZE) {
srm_printk("Failed (%lx)\n", i);
return;
}
nbytes = callback_getenv(ENV_BOOTED_OSFLAGS, envval, sizeof(envval));
if (nbytes < 0) {
nbytes = 0;
}
envval[nbytes] = '\0';
strcpy((char*)ZERO_PGE, envval);
srm_printk(" Ok\nNow booting the kernel\n");
runkernel();
for (i = 0 ; i < 0x100000000 ; i++)
/* nothing */;
__halt();
}
| gpl-2.0 |
loiz/android_kernel_samsung_hllte | drivers/scsi/arm/cumana_2.c | 8171 | 14691 | /*
* linux/drivers/acorn/scsi/cumana_2.c
*
* Copyright (C) 1997-2005 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 30-08-1997 RMK 0.0.0 Created, READONLY version.
* 22-01-1998 RMK 0.0.1 Updated to 2.1.80.
* 15-04-1998 RMK 0.0.1 Only do PIO if FAS216 will allow it.
* 02-05-1998 RMK 0.0.2 Updated & added DMA support.
* 27-06-1998 RMK Changed asm/delay.h to linux/delay.h
* 18-08-1998 RMK 0.0.3 Fixed synchronous transfer depth.
* 02-04-2000 RMK 0.0.4 Updated for new error handling code.
*/
#include <linux/module.h>
#include <linux/blkdev.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/proc_fs.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <asm/dma.h>
#include <asm/ecard.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include "../scsi.h"
#include <scsi/scsi_host.h>
#include "fas216.h"
#include "scsi.h"
#include <scsi/scsicam.h>
#define CUMANASCSI2_STATUS (0x0000)
#define STATUS_INT (1 << 0)
#define STATUS_DRQ (1 << 1)
#define STATUS_LATCHED (1 << 3)
#define CUMANASCSI2_ALATCH (0x0014)
#define ALATCH_ENA_INT (3)
#define ALATCH_DIS_INT (2)
#define ALATCH_ENA_TERM (5)
#define ALATCH_DIS_TERM (4)
#define ALATCH_ENA_BIT32 (11)
#define ALATCH_DIS_BIT32 (10)
#define ALATCH_ENA_DMA (13)
#define ALATCH_DIS_DMA (12)
#define ALATCH_DMA_OUT (15)
#define ALATCH_DMA_IN (14)
#define CUMANASCSI2_PSEUDODMA (0x0200)
#define CUMANASCSI2_FAS216_OFFSET (0x0300)
#define CUMANASCSI2_FAS216_SHIFT 2
/*
* Version
*/
#define VERSION "1.00 (13/11/2002 2.5.47)"
/*
* Use term=0,1,0,0,0 to turn terminators on/off
*/
static int term[MAX_ECARDS] = { 1, 1, 1, 1, 1, 1, 1, 1 };
#define NR_SG 256
struct cumanascsi2_info {
FAS216_Info info;
struct expansion_card *ec;
void __iomem *base;
unsigned int terms; /* Terminator state */
struct scatterlist sg[NR_SG]; /* Scatter DMA list */
};
#define CSTATUS_IRQ (1 << 0)
#define CSTATUS_DRQ (1 << 1)
/* Prototype: void cumanascsi_2_irqenable(ec, irqnr)
* Purpose : Enable interrupts on Cumana SCSI 2 card
* Params : ec - expansion card structure
* : irqnr - interrupt number
*/
static void
cumanascsi_2_irqenable(struct expansion_card *ec, int irqnr)
{
struct cumanascsi2_info *info = ec->irq_data;
writeb(ALATCH_ENA_INT, info->base + CUMANASCSI2_ALATCH);
}
/* Prototype: void cumanascsi_2_irqdisable(ec, irqnr)
* Purpose : Disable interrupts on Cumana SCSI 2 card
* Params : ec - expansion card structure
* : irqnr - interrupt number
*/
static void
cumanascsi_2_irqdisable(struct expansion_card *ec, int irqnr)
{
struct cumanascsi2_info *info = ec->irq_data;
writeb(ALATCH_DIS_INT, info->base + CUMANASCSI2_ALATCH);
}
static const expansioncard_ops_t cumanascsi_2_ops = {
.irqenable = cumanascsi_2_irqenable,
.irqdisable = cumanascsi_2_irqdisable,
};
/* Prototype: void cumanascsi_2_terminator_ctl(host, on_off)
* Purpose : Turn the Cumana SCSI 2 terminators on or off
* Params : host - card to turn on/off
* : on_off - !0 to turn on, 0 to turn off
*/
static void
cumanascsi_2_terminator_ctl(struct Scsi_Host *host, int on_off)
{
struct cumanascsi2_info *info = (struct cumanascsi2_info *)host->hostdata;
if (on_off) {
info->terms = 1;
writeb(ALATCH_ENA_TERM, info->base + CUMANASCSI2_ALATCH);
} else {
info->terms = 0;
writeb(ALATCH_DIS_TERM, info->base + CUMANASCSI2_ALATCH);
}
}
/* Prototype: void cumanascsi_2_intr(irq, *dev_id, *regs)
* Purpose : handle interrupts from Cumana SCSI 2 card
* Params : irq - interrupt number
* dev_id - user-defined (Scsi_Host structure)
*/
static irqreturn_t
cumanascsi_2_intr(int irq, void *dev_id)
{
struct cumanascsi2_info *info = dev_id;
return fas216_intr(&info->info);
}
/* Prototype: fasdmatype_t cumanascsi_2_dma_setup(host, SCpnt, direction, min_type)
* Purpose : initialises DMA/PIO
* Params : host - host
* SCpnt - command
* direction - DMA on to/off of card
* min_type - minimum DMA support that we must have for this transfer
* Returns : type of transfer to be performed
*/
static fasdmatype_t
cumanascsi_2_dma_setup(struct Scsi_Host *host, struct scsi_pointer *SCp,
fasdmadir_t direction, fasdmatype_t min_type)
{
struct cumanascsi2_info *info = (struct cumanascsi2_info *)host->hostdata;
struct device *dev = scsi_get_device(host);
int dmach = info->info.scsi.dma;
writeb(ALATCH_DIS_DMA, info->base + CUMANASCSI2_ALATCH);
if (dmach != NO_DMA &&
(min_type == fasdma_real_all || SCp->this_residual >= 512)) {
int bufs, map_dir, dma_dir, alatch_dir;
bufs = copy_SCp_to_sg(&info->sg[0], SCp, NR_SG);
if (direction == DMA_OUT)
map_dir = DMA_TO_DEVICE,
dma_dir = DMA_MODE_WRITE,
alatch_dir = ALATCH_DMA_OUT;
else
map_dir = DMA_FROM_DEVICE,
dma_dir = DMA_MODE_READ,
alatch_dir = ALATCH_DMA_IN;
dma_map_sg(dev, info->sg, bufs, map_dir);
disable_dma(dmach);
set_dma_sg(dmach, info->sg, bufs);
writeb(alatch_dir, info->base + CUMANASCSI2_ALATCH);
set_dma_mode(dmach, dma_dir);
enable_dma(dmach);
writeb(ALATCH_ENA_DMA, info->base + CUMANASCSI2_ALATCH);
writeb(ALATCH_DIS_BIT32, info->base + CUMANASCSI2_ALATCH);
return fasdma_real_all;
}
/*
* If we're not doing DMA,
* we'll do pseudo DMA
*/
return fasdma_pio;
}
/*
* Prototype: void cumanascsi_2_dma_pseudo(host, SCpnt, direction, transfer)
* Purpose : handles pseudo DMA
* Params : host - host
* SCpnt - command
* direction - DMA on to/off of card
* transfer - minimum number of bytes we expect to transfer
*/
static void
cumanascsi_2_dma_pseudo(struct Scsi_Host *host, struct scsi_pointer *SCp,
fasdmadir_t direction, int transfer)
{
struct cumanascsi2_info *info = (struct cumanascsi2_info *)host->hostdata;
unsigned int length;
unsigned char *addr;
length = SCp->this_residual;
addr = SCp->ptr;
if (direction == DMA_OUT)
#if 0
while (length > 1) {
unsigned long word;
unsigned int status = readb(info->base + CUMANASCSI2_STATUS);
if (status & STATUS_INT)
goto end;
if (!(status & STATUS_DRQ))
continue;
word = *addr | *(addr + 1) << 8;
writew(word, info->base + CUMANASCSI2_PSEUDODMA);
addr += 2;
length -= 2;
}
#else
printk ("PSEUDO_OUT???\n");
#endif
else {
if (transfer && (transfer & 255)) {
while (length >= 256) {
unsigned int status = readb(info->base + CUMANASCSI2_STATUS);
if (status & STATUS_INT)
return;
if (!(status & STATUS_DRQ))
continue;
readsw(info->base + CUMANASCSI2_PSEUDODMA,
addr, 256 >> 1);
addr += 256;
length -= 256;
}
}
while (length > 0) {
unsigned long word;
unsigned int status = readb(info->base + CUMANASCSI2_STATUS);
if (status & STATUS_INT)
return;
if (!(status & STATUS_DRQ))
continue;
word = readw(info->base + CUMANASCSI2_PSEUDODMA);
*addr++ = word;
if (--length > 0) {
*addr++ = word >> 8;
length --;
}
}
}
}
/* Prototype: int cumanascsi_2_dma_stop(host, SCpnt)
* Purpose : stops DMA/PIO
* Params : host - host
* SCpnt - command
*/
static void
cumanascsi_2_dma_stop(struct Scsi_Host *host, struct scsi_pointer *SCp)
{
struct cumanascsi2_info *info = (struct cumanascsi2_info *)host->hostdata;
if (info->info.scsi.dma != NO_DMA) {
writeb(ALATCH_DIS_DMA, info->base + CUMANASCSI2_ALATCH);
disable_dma(info->info.scsi.dma);
}
}
/* Prototype: const char *cumanascsi_2_info(struct Scsi_Host * host)
* Purpose : returns a descriptive string about this interface,
* Params : host - driver host structure to return info for.
* Returns : pointer to a static buffer containing null terminated string.
*/
const char *cumanascsi_2_info(struct Scsi_Host *host)
{
struct cumanascsi2_info *info = (struct cumanascsi2_info *)host->hostdata;
static char string[150];
sprintf(string, "%s (%s) in slot %d v%s terminators o%s",
host->hostt->name, info->info.scsi.type, info->ec->slot_no,
VERSION, info->terms ? "n" : "ff");
return string;
}
/* Prototype: int cumanascsi_2_set_proc_info(struct Scsi_Host *host, char *buffer, int length)
* Purpose : Set a driver specific function
* Params : host - host to setup
* : buffer - buffer containing string describing operation
* : length - length of string
* Returns : -EINVAL, or 0
*/
static int
cumanascsi_2_set_proc_info(struct Scsi_Host *host, char *buffer, int length)
{
int ret = length;
if (length >= 11 && strncmp(buffer, "CUMANASCSI2", 11) == 0) {
buffer += 11;
length -= 11;
if (length >= 5 && strncmp(buffer, "term=", 5) == 0) {
if (buffer[5] == '1')
cumanascsi_2_terminator_ctl(host, 1);
else if (buffer[5] == '0')
cumanascsi_2_terminator_ctl(host, 0);
else
ret = -EINVAL;
} else
ret = -EINVAL;
} else
ret = -EINVAL;
return ret;
}
/* Prototype: int cumanascsi_2_proc_info(char *buffer, char **start, off_t offset,
* int length, int host_no, int inout)
* Purpose : Return information about the driver to a user process accessing
* the /proc filesystem.
* Params : buffer - a buffer to write information to
* start - a pointer into this buffer set by this routine to the start
* of the required information.
* offset - offset into information that we have read up to.
* length - length of buffer
* host_no - host number to return information for
* inout - 0 for reading, 1 for writing.
* Returns : length of data written to buffer.
*/
int cumanascsi_2_proc_info (struct Scsi_Host *host, char *buffer, char **start, off_t offset,
int length, int inout)
{
struct cumanascsi2_info *info;
char *p = buffer;
int pos;
if (inout == 1)
return cumanascsi_2_set_proc_info(host, buffer, length);
info = (struct cumanascsi2_info *)host->hostdata;
p += sprintf(p, "Cumana SCSI II driver v%s\n", VERSION);
p += fas216_print_host(&info->info, p);
p += sprintf(p, "Term : o%s\n",
info->terms ? "n" : "ff");
p += fas216_print_stats(&info->info, p);
p += fas216_print_devices(&info->info, p);
*start = buffer + offset;
pos = p - buffer - offset;
if (pos > length)
pos = length;
return pos;
}
static struct scsi_host_template cumanascsi2_template = {
.module = THIS_MODULE,
.proc_info = cumanascsi_2_proc_info,
.name = "Cumana SCSI II",
.info = cumanascsi_2_info,
.queuecommand = fas216_queue_command,
.eh_host_reset_handler = fas216_eh_host_reset,
.eh_bus_reset_handler = fas216_eh_bus_reset,
.eh_device_reset_handler = fas216_eh_device_reset,
.eh_abort_handler = fas216_eh_abort,
.can_queue = 1,
.this_id = 7,
.sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS,
.dma_boundary = IOMD_DMA_BOUNDARY,
.cmd_per_lun = 1,
.use_clustering = DISABLE_CLUSTERING,
.proc_name = "cumanascsi2",
};
static int __devinit
cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id)
{
struct Scsi_Host *host;
struct cumanascsi2_info *info;
void __iomem *base;
int ret;
ret = ecard_request_resources(ec);
if (ret)
goto out;
base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
if (!base) {
ret = -ENOMEM;
goto out_region;
}
host = scsi_host_alloc(&cumanascsi2_template,
sizeof(struct cumanascsi2_info));
if (!host) {
ret = -ENOMEM;
goto out_region;
}
ecard_set_drvdata(ec, host);
info = (struct cumanascsi2_info *)host->hostdata;
info->ec = ec;
info->base = base;
cumanascsi_2_terminator_ctl(host, term[ec->slot_no]);
info->info.scsi.io_base = base + CUMANASCSI2_FAS216_OFFSET;
info->info.scsi.io_shift = CUMANASCSI2_FAS216_SHIFT;
info->info.scsi.irq = ec->irq;
info->info.scsi.dma = ec->dma;
info->info.ifcfg.clockrate = 40; /* MHz */
info->info.ifcfg.select_timeout = 255;
info->info.ifcfg.asyncperiod = 200; /* ns */
info->info.ifcfg.sync_max_depth = 7;
info->info.ifcfg.cntl3 = CNTL3_BS8 | CNTL3_FASTSCSI | CNTL3_FASTCLK;
info->info.ifcfg.disconnect_ok = 1;
info->info.ifcfg.wide_max_size = 0;
info->info.ifcfg.capabilities = FASCAP_PSEUDODMA;
info->info.dma.setup = cumanascsi_2_dma_setup;
info->info.dma.pseudo = cumanascsi_2_dma_pseudo;
info->info.dma.stop = cumanascsi_2_dma_stop;
ec->irqaddr = info->base + CUMANASCSI2_STATUS;
ec->irqmask = STATUS_INT;
ecard_setirq(ec, &cumanascsi_2_ops, info);
ret = fas216_init(host);
if (ret)
goto out_free;
ret = request_irq(ec->irq, cumanascsi_2_intr,
IRQF_DISABLED, "cumanascsi2", info);
if (ret) {
printk("scsi%d: IRQ%d not free: %d\n",
host->host_no, ec->irq, ret);
goto out_release;
}
if (info->info.scsi.dma != NO_DMA) {
if (request_dma(info->info.scsi.dma, "cumanascsi2")) {
printk("scsi%d: DMA%d not free, using PIO\n",
host->host_no, info->info.scsi.dma);
info->info.scsi.dma = NO_DMA;
} else {
set_dma_speed(info->info.scsi.dma, 180);
info->info.ifcfg.capabilities |= FASCAP_DMA;
}
}
ret = fas216_add(host, &ec->dev);
if (ret == 0)
goto out;
if (info->info.scsi.dma != NO_DMA)
free_dma(info->info.scsi.dma);
free_irq(ec->irq, host);
out_release:
fas216_release(host);
out_free:
scsi_host_put(host);
out_region:
ecard_release_resources(ec);
out:
return ret;
}
static void __devexit cumanascsi2_remove(struct expansion_card *ec)
{
struct Scsi_Host *host = ecard_get_drvdata(ec);
struct cumanascsi2_info *info = (struct cumanascsi2_info *)host->hostdata;
ecard_set_drvdata(ec, NULL);
fas216_remove(host);
if (info->info.scsi.dma != NO_DMA)
free_dma(info->info.scsi.dma);
free_irq(ec->irq, info);
fas216_release(host);
scsi_host_put(host);
ecard_release_resources(ec);
}
static const struct ecard_id cumanascsi2_cids[] = {
{ MANU_CUMANA, PROD_CUMANA_SCSI_2 },
{ 0xffff, 0xffff },
};
static struct ecard_driver cumanascsi2_driver = {
.probe = cumanascsi2_probe,
.remove = __devexit_p(cumanascsi2_remove),
.id_table = cumanascsi2_cids,
.drv = {
.name = "cumanascsi2",
},
};
static int __init cumanascsi2_init(void)
{
return ecard_register_driver(&cumanascsi2_driver);
}
static void __exit cumanascsi2_exit(void)
{
ecard_remove_driver(&cumanascsi2_driver);
}
module_init(cumanascsi2_init);
module_exit(cumanascsi2_exit);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("Cumana SCSI-2 driver for Acorn machines");
module_param_array(term, int, NULL, 0);
MODULE_PARM_DESC(term, "SCSI bus termination");
MODULE_LICENSE("GPL");
| gpl-2.0 |
sebirdman/m7_kernel_dev | drivers/isdn/hardware/eicon/message.c | 8171 | 446143 | /*
*
Copyright (c) Eicon Networks, 2002.
*
This source file is supplied for the use with
Eicon Networks range of DIVA Server Adapters.
*
Eicon File Revision : 2.1
*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
*
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY OF ANY KIND WHATSOEVER INCLUDING ANY
implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
*
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include "platform.h"
#include "di_defs.h"
#include "pc.h"
#include "capi20.h"
#include "divacapi.h"
#include "mdm_msg.h"
#include "divasync.h"
#define FILE_ "MESSAGE.C"
#define dprintf
/*------------------------------------------------------------------*/
/* This is options supported for all adapters that are server by */
/* XDI driver. Allo it is not necessary to ask it from every adapter*/
/* and it is not necessary to save it separate for every adapter */
/* Macrose defined here have only local meaning */
/*------------------------------------------------------------------*/
static dword diva_xdi_extended_features = 0;
#define DIVA_CAPI_USE_CMA 0x00000001
#define DIVA_CAPI_XDI_PROVIDES_SDRAM_BAR 0x00000002
#define DIVA_CAPI_XDI_PROVIDES_NO_CANCEL 0x00000004
#define DIVA_CAPI_XDI_PROVIDES_RX_DMA 0x00000008
/*
CAPI can request to process all return codes self only if:
protocol code supports this && xdi supports this
*/
#define DIVA_CAPI_SUPPORTS_NO_CANCEL(__a__) (((__a__)->manufacturer_features & MANUFACTURER_FEATURE_XONOFF_FLOW_CONTROL) && ((__a__)->manufacturer_features & MANUFACTURER_FEATURE_OK_FC_LABEL) && (diva_xdi_extended_features & DIVA_CAPI_XDI_PROVIDES_NO_CANCEL))
/*------------------------------------------------------------------*/
/* local function prototypes */
/*------------------------------------------------------------------*/
static void group_optimization(DIVA_CAPI_ADAPTER *a, PLCI *plci);
static void set_group_ind_mask(PLCI *plci);
static void clear_group_ind_mask_bit(PLCI *plci, word b);
static byte test_group_ind_mask_bit(PLCI *plci, word b);
void AutomaticLaw(DIVA_CAPI_ADAPTER *);
word CapiRelease(word);
word CapiRegister(word);
word api_put(APPL *, CAPI_MSG *);
static word api_parse(byte *, word, byte *, API_PARSE *);
static void api_save_msg(API_PARSE *in, byte *format, API_SAVE *out);
static void api_load_msg(API_SAVE *in, API_PARSE *out);
word api_remove_start(void);
void api_remove_complete(void);
static void plci_remove(PLCI *);
static void diva_get_extended_adapter_features(DIVA_CAPI_ADAPTER *a);
static void diva_ask_for_xdi_sdram_bar(DIVA_CAPI_ADAPTER *, IDI_SYNC_REQ *);
void callback(ENTITY *);
static void control_rc(PLCI *, byte, byte, byte, byte, byte);
static void data_rc(PLCI *, byte);
static void data_ack(PLCI *, byte);
static void sig_ind(PLCI *);
static void SendInfo(PLCI *, dword, byte **, byte);
static void SendSetupInfo(APPL *, PLCI *, dword, byte **, byte);
static void SendSSExtInd(APPL *, PLCI *plci, dword Id, byte **parms);
static void VSwitchReqInd(PLCI *plci, dword Id, byte **parms);
static void nl_ind(PLCI *);
static byte connect_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte connect_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte connect_a_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte disconnect_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte disconnect_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte listen_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte info_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte info_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte alert_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte facility_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte facility_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte connect_b3_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte connect_b3_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte connect_b3_a_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte disconnect_b3_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte disconnect_b3_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte data_b3_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte data_b3_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte reset_b3_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte reset_b3_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte connect_b3_t90_a_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte select_b_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte manufacturer_req(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static byte manufacturer_res(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
static word get_plci(DIVA_CAPI_ADAPTER *);
static void add_p(PLCI *, byte, byte *);
static void add_s(PLCI *plci, byte code, API_PARSE *p);
static void add_ss(PLCI *plci, byte code, API_PARSE *p);
static void add_ie(PLCI *plci, byte code, byte *p, word p_length);
static void add_d(PLCI *, word, byte *);
static void add_ai(PLCI *, API_PARSE *);
static word add_b1(PLCI *, API_PARSE *, word, word);
static word add_b23(PLCI *, API_PARSE *);
static word add_modem_b23(PLCI *plci, API_PARSE *bp_parms);
static void sig_req(PLCI *, byte, byte);
static void nl_req_ncci(PLCI *, byte, byte);
static void send_req(PLCI *);
static void send_data(PLCI *);
static word plci_remove_check(PLCI *);
static void listen_check(DIVA_CAPI_ADAPTER *);
static byte AddInfo(byte **, byte **, byte *, byte *);
static byte getChannel(API_PARSE *);
static void IndParse(PLCI *, word *, byte **, byte);
static byte ie_compare(byte *, byte *);
static word find_cip(DIVA_CAPI_ADAPTER *, byte *, byte *);
static word CPN_filter_ok(byte *cpn, DIVA_CAPI_ADAPTER *, word);
/*
XON protocol helpers
*/
static void channel_flow_control_remove(PLCI *plci);
static void channel_x_off(PLCI *plci, byte ch, byte flag);
static void channel_x_on(PLCI *plci, byte ch);
static void channel_request_xon(PLCI *plci, byte ch);
static void channel_xmit_xon(PLCI *plci);
static int channel_can_xon(PLCI *plci, byte ch);
static void channel_xmit_extended_xon(PLCI *plci);
static byte SendMultiIE(PLCI *plci, dword Id, byte **parms, byte ie_type, dword info_mask, byte setupParse);
static word AdvCodecSupport(DIVA_CAPI_ADAPTER *, PLCI *, APPL *, byte);
static void CodecIdCheck(DIVA_CAPI_ADAPTER *, PLCI *);
static void SetVoiceChannel(PLCI *, byte *, DIVA_CAPI_ADAPTER *);
static void VoiceChannelOff(PLCI *plci);
static void adv_voice_write_coefs(PLCI *plci, word write_command);
static void adv_voice_clear_config(PLCI *plci);
static word get_b1_facilities(PLCI *plci, byte b1_resource);
static byte add_b1_facilities(PLCI *plci, byte b1_resource, word b1_facilities);
static void adjust_b1_facilities(PLCI *plci, byte new_b1_resource, word new_b1_facilities);
static word adjust_b_process(dword Id, PLCI *plci, byte Rc);
static void adjust_b1_resource(dword Id, PLCI *plci, API_SAVE *bp_msg, word b1_facilities, word internal_command);
static void adjust_b_restore(dword Id, PLCI *plci, byte Rc);
static void reset_b3_command(dword Id, PLCI *plci, byte Rc);
static void select_b_command(dword Id, PLCI *plci, byte Rc);
static void fax_connect_ack_command(dword Id, PLCI *plci, byte Rc);
static void fax_edata_ack_command(dword Id, PLCI *plci, byte Rc);
static void fax_connect_info_command(dword Id, PLCI *plci, byte Rc);
static void fax_adjust_b23_command(dword Id, PLCI *plci, byte Rc);
static void fax_disconnect_command(dword Id, PLCI *plci, byte Rc);
static void hold_save_command(dword Id, PLCI *plci, byte Rc);
static void retrieve_restore_command(dword Id, PLCI *plci, byte Rc);
static void init_b1_config(PLCI *plci);
static void clear_b1_config(PLCI *plci);
static void dtmf_command(dword Id, PLCI *plci, byte Rc);
static byte dtmf_request(dword Id, word Number, DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl, API_PARSE *msg);
static void dtmf_confirmation(dword Id, PLCI *plci);
static void dtmf_indication(dword Id, PLCI *plci, byte *msg, word length);
static void dtmf_parameter_write(PLCI *plci);
static void mixer_set_bchannel_id_esc(PLCI *plci, byte bchannel_id);
static void mixer_set_bchannel_id(PLCI *plci, byte *chi);
static void mixer_clear_config(PLCI *plci);
static void mixer_notify_update(PLCI *plci, byte others);
static void mixer_command(dword Id, PLCI *plci, byte Rc);
static byte mixer_request(dword Id, word Number, DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl, API_PARSE *msg);
static void mixer_indication_coefs_set(dword Id, PLCI *plci);
static void mixer_indication_xconnect_from(dword Id, PLCI *plci, byte *msg, word length);
static void mixer_indication_xconnect_to(dword Id, PLCI *plci, byte *msg, word length);
static void mixer_remove(PLCI *plci);
static void ec_command(dword Id, PLCI *plci, byte Rc);
static byte ec_request(dword Id, word Number, DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl, API_PARSE *msg);
static void ec_indication(dword Id, PLCI *plci, byte *msg, word length);
static void rtp_connect_b3_req_command(dword Id, PLCI *plci, byte Rc);
static void rtp_connect_b3_res_command(dword Id, PLCI *plci, byte Rc);
static int diva_get_dma_descriptor(PLCI *plci, dword *dma_magic);
static void diva_free_dma_descriptor(PLCI *plci, int nr);
/*------------------------------------------------------------------*/
/* external function prototypes */
/*------------------------------------------------------------------*/
extern byte MapController(byte);
extern byte UnMapController(byte);
#define MapId(Id)(((Id) & 0xffffff00L) | MapController((byte)(Id)))
#define UnMapId(Id)(((Id) & 0xffffff00L) | UnMapController((byte)(Id)))
void sendf(APPL *, word, dword, word, byte *, ...);
void *TransmitBufferSet(APPL *appl, dword ref);
void *TransmitBufferGet(APPL *appl, void *p);
void TransmitBufferFree(APPL *appl, void *p);
void *ReceiveBufferGet(APPL *appl, int Num);
int fax_head_line_time(char *buffer);
/*------------------------------------------------------------------*/
/* Global data definitions */
/*------------------------------------------------------------------*/
extern byte max_adapter;
extern byte max_appl;
extern DIVA_CAPI_ADAPTER *adapter;
extern APPL *application;
static byte remove_started = false;
static PLCI dummy_plci;
static struct _ftable {
word command;
byte *format;
byte (*function)(dword, word, DIVA_CAPI_ADAPTER *, PLCI *, APPL *, API_PARSE *);
} ftable[] = {
{_DATA_B3_R, "dwww", data_b3_req},
{_DATA_B3_I | RESPONSE, "w", data_b3_res},
{_INFO_R, "ss", info_req},
{_INFO_I | RESPONSE, "", info_res},
{_CONNECT_R, "wsssssssss", connect_req},
{_CONNECT_I | RESPONSE, "wsssss", connect_res},
{_CONNECT_ACTIVE_I | RESPONSE, "", connect_a_res},
{_DISCONNECT_R, "s", disconnect_req},
{_DISCONNECT_I | RESPONSE, "", disconnect_res},
{_LISTEN_R, "dddss", listen_req},
{_ALERT_R, "s", alert_req},
{_FACILITY_R, "ws", facility_req},
{_FACILITY_I | RESPONSE, "ws", facility_res},
{_CONNECT_B3_R, "s", connect_b3_req},
{_CONNECT_B3_I | RESPONSE, "ws", connect_b3_res},
{_CONNECT_B3_ACTIVE_I | RESPONSE, "", connect_b3_a_res},
{_DISCONNECT_B3_R, "s", disconnect_b3_req},
{_DISCONNECT_B3_I | RESPONSE, "", disconnect_b3_res},
{_RESET_B3_R, "s", reset_b3_req},
{_RESET_B3_I | RESPONSE, "", reset_b3_res},
{_CONNECT_B3_T90_ACTIVE_I | RESPONSE, "ws", connect_b3_t90_a_res},
{_CONNECT_B3_T90_ACTIVE_I | RESPONSE, "", connect_b3_t90_a_res},
{_SELECT_B_REQ, "s", select_b_req},
{_MANUFACTURER_R, "dws", manufacturer_req},
{_MANUFACTURER_I | RESPONSE, "dws", manufacturer_res},
{_MANUFACTURER_I | RESPONSE, "", manufacturer_res}
};
static byte *cip_bc[29][2] = {
{ "", "" }, /* 0 */
{ "\x03\x80\x90\xa3", "\x03\x80\x90\xa2" }, /* 1 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 2 */
{ "\x02\x89\x90", "\x02\x89\x90" }, /* 3 */
{ "\x03\x90\x90\xa3", "\x03\x90\x90\xa2" }, /* 4 */
{ "\x03\x91\x90\xa5", "\x03\x91\x90\xa5" }, /* 5 */
{ "\x02\x98\x90", "\x02\x98\x90" }, /* 6 */
{ "\x04\x88\xc0\xc6\xe6", "\x04\x88\xc0\xc6\xe6" }, /* 7 */
{ "\x04\x88\x90\x21\x8f", "\x04\x88\x90\x21\x8f" }, /* 8 */
{ "\x03\x91\x90\xa5", "\x03\x91\x90\xa5" }, /* 9 */
{ "", "" }, /* 10 */
{ "", "" }, /* 11 */
{ "", "" }, /* 12 */
{ "", "" }, /* 13 */
{ "", "" }, /* 14 */
{ "", "" }, /* 15 */
{ "\x03\x80\x90\xa3", "\x03\x80\x90\xa2" }, /* 16 */
{ "\x03\x90\x90\xa3", "\x03\x90\x90\xa2" }, /* 17 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 18 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 19 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 20 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 21 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 22 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 23 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 24 */
{ "\x02\x88\x90", "\x02\x88\x90" }, /* 25 */
{ "\x03\x91\x90\xa5", "\x03\x91\x90\xa5" }, /* 26 */
{ "\x03\x91\x90\xa5", "\x03\x91\x90\xa5" }, /* 27 */
{ "\x02\x88\x90", "\x02\x88\x90" } /* 28 */
};
static byte *cip_hlc[29] = {
"", /* 0 */
"", /* 1 */
"", /* 2 */
"", /* 3 */
"", /* 4 */
"", /* 5 */
"", /* 6 */
"", /* 7 */
"", /* 8 */
"", /* 9 */
"", /* 10 */
"", /* 11 */
"", /* 12 */
"", /* 13 */
"", /* 14 */
"", /* 15 */
"\x02\x91\x81", /* 16 */
"\x02\x91\x84", /* 17 */
"\x02\x91\xa1", /* 18 */
"\x02\x91\xa4", /* 19 */
"\x02\x91\xa8", /* 20 */
"\x02\x91\xb1", /* 21 */
"\x02\x91\xb2", /* 22 */
"\x02\x91\xb5", /* 23 */
"\x02\x91\xb8", /* 24 */
"\x02\x91\xc1", /* 25 */
"\x02\x91\x81", /* 26 */
"\x03\x91\xe0\x01", /* 27 */
"\x03\x91\xe0\x02" /* 28 */
};
/*------------------------------------------------------------------*/
#define V120_HEADER_LENGTH 1
#define V120_HEADER_EXTEND_BIT 0x80
#define V120_HEADER_BREAK_BIT 0x40
#define V120_HEADER_C1_BIT 0x04
#define V120_HEADER_C2_BIT 0x08
#define V120_HEADER_FLUSH_COND (V120_HEADER_BREAK_BIT | V120_HEADER_C1_BIT | V120_HEADER_C2_BIT)
static byte v120_default_header[] =
{
0x83 /* Ext, BR , res, res, C2 , C1 , B , F */
};
static byte v120_break_header[] =
{
0xc3 | V120_HEADER_BREAK_BIT /* Ext, BR , res, res, C2 , C1 , B , F */
};
/*------------------------------------------------------------------*/
/* API_PUT function */
/*------------------------------------------------------------------*/
word api_put(APPL *appl, CAPI_MSG *msg)
{
word i, j, k, l, n;
word ret;
byte c;
byte controller;
DIVA_CAPI_ADAPTER *a;
PLCI *plci;
NCCI *ncci_ptr;
word ncci;
CAPI_MSG *m;
API_PARSE msg_parms[MAX_MSG_PARMS + 1];
if (msg->header.length < sizeof(msg->header) ||
msg->header.length > MAX_MSG_SIZE) {
dbug(1, dprintf("bad len"));
return _BAD_MSG;
}
controller = (byte)((msg->header.controller & 0x7f) - 1);
/* controller starts with 0 up to (max_adapter - 1) */
if (controller >= max_adapter)
{
dbug(1, dprintf("invalid ctrl"));
return _BAD_MSG;
}
a = &adapter[controller];
plci = NULL;
if ((msg->header.plci != 0) && (msg->header.plci <= a->max_plci) && !a->adapter_disabled)
{
dbug(1, dprintf("plci=%x", msg->header.plci));
plci = &a->plci[msg->header.plci - 1];
ncci = GET_WORD(&msg->header.ncci);
if (plci->Id
&& (plci->appl
|| (plci->State == INC_CON_PENDING)
|| (plci->State == INC_CON_ALERT)
|| (msg->header.command == (_DISCONNECT_I | RESPONSE)))
&& ((ncci == 0)
|| (msg->header.command == (_DISCONNECT_B3_I | RESPONSE))
|| ((ncci < MAX_NCCI + 1) && (a->ncci_plci[ncci] == plci->Id))))
{
i = plci->msg_in_read_pos;
j = plci->msg_in_write_pos;
if (j >= i)
{
if (j + msg->header.length + MSG_IN_OVERHEAD <= MSG_IN_QUEUE_SIZE)
i += MSG_IN_QUEUE_SIZE - j;
else
j = 0;
}
else
{
n = (((CAPI_MSG *)(plci->msg_in_queue))->header.length + MSG_IN_OVERHEAD + 3) & 0xfffc;
if (i > MSG_IN_QUEUE_SIZE - n)
i = MSG_IN_QUEUE_SIZE - n + 1;
i -= j;
}
if (i <= ((msg->header.length + MSG_IN_OVERHEAD + 3) & 0xfffc))
{
dbug(0, dprintf("Q-FULL1(msg) - len=%d write=%d read=%d wrap=%d free=%d",
msg->header.length, plci->msg_in_write_pos,
plci->msg_in_read_pos, plci->msg_in_wrap_pos, i));
return _QUEUE_FULL;
}
c = false;
if ((((byte *) msg) < ((byte *)(plci->msg_in_queue)))
|| (((byte *) msg) >= ((byte *)(plci->msg_in_queue)) + sizeof(plci->msg_in_queue)))
{
if (plci->msg_in_write_pos != plci->msg_in_read_pos)
c = true;
}
if (msg->header.command == _DATA_B3_R)
{
if (msg->header.length < 20)
{
dbug(1, dprintf("DATA_B3 REQ wrong length %d", msg->header.length));
return _BAD_MSG;
}
ncci_ptr = &(a->ncci[ncci]);
n = ncci_ptr->data_pending;
l = ncci_ptr->data_ack_pending;
k = plci->msg_in_read_pos;
while (k != plci->msg_in_write_pos)
{
if (k == plci->msg_in_wrap_pos)
k = 0;
if ((((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[k]))->header.command == _DATA_B3_R)
&& (((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[k]))->header.ncci == ncci))
{
n++;
if (((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[k]))->info.data_b3_req.Flags & 0x0004)
l++;
}
k += (((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[k]))->header.length +
MSG_IN_OVERHEAD + 3) & 0xfffc;
}
if ((n >= MAX_DATA_B3) || (l >= MAX_DATA_ACK))
{
dbug(0, dprintf("Q-FULL2(data) - pending=%d/%d ack_pending=%d/%d",
ncci_ptr->data_pending, n, ncci_ptr->data_ack_pending, l));
return _QUEUE_FULL;
}
if (plci->req_in || plci->internal_command)
{
if ((((byte *) msg) >= ((byte *)(plci->msg_in_queue)))
&& (((byte *) msg) < ((byte *)(plci->msg_in_queue)) + sizeof(plci->msg_in_queue)))
{
dbug(0, dprintf("Q-FULL3(requeue)"));
return _QUEUE_FULL;
}
c = true;
}
}
else
{
if (plci->req_in || plci->internal_command)
c = true;
else
{
plci->command = msg->header.command;
plci->number = msg->header.number;
}
}
if (c)
{
dbug(1, dprintf("enqueue msg(0x%04x,0x%x,0x%x) - len=%d write=%d read=%d wrap=%d free=%d",
msg->header.command, plci->req_in, plci->internal_command,
msg->header.length, plci->msg_in_write_pos,
plci->msg_in_read_pos, plci->msg_in_wrap_pos, i));
if (j == 0)
plci->msg_in_wrap_pos = plci->msg_in_write_pos;
m = (CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[j]);
for (i = 0; i < msg->header.length; i++)
((byte *)(plci->msg_in_queue))[j++] = ((byte *) msg)[i];
if (m->header.command == _DATA_B3_R)
{
m->info.data_b3_req.Data = (dword)(long)(TransmitBufferSet(appl, m->info.data_b3_req.Data));
}
j = (j + 3) & 0xfffc;
*((APPL **)(&((byte *)(plci->msg_in_queue))[j])) = appl;
plci->msg_in_write_pos = j + MSG_IN_OVERHEAD;
return 0;
}
}
else
{
plci = NULL;
}
}
dbug(1, dprintf("com=%x", msg->header.command));
for (j = 0; j < MAX_MSG_PARMS + 1; j++) msg_parms[j].length = 0;
for (i = 0, ret = _BAD_MSG; i < ARRAY_SIZE(ftable); i++) {
if (ftable[i].command == msg->header.command) {
/* break loop if the message is correct, otherwise continue scan */
/* (for example: CONNECT_B3_T90_ACT_RES has two specifications) */
if (!api_parse(msg->info.b, (word)(msg->header.length - 12), ftable[i].format, msg_parms)) {
ret = 0;
break;
}
for (j = 0; j < MAX_MSG_PARMS + 1; j++) msg_parms[j].length = 0;
}
}
if (ret) {
dbug(1, dprintf("BAD_MSG"));
if (plci) plci->command = 0;
return ret;
}
c = ftable[i].function(GET_DWORD(&msg->header.controller),
msg->header.number,
a,
plci,
appl,
msg_parms);
channel_xmit_extended_xon(plci);
if (c == 1) send_req(plci);
if (c == 2 && plci) plci->req_in = plci->req_in_start = plci->req_out = 0;
if (plci && !plci->req_in) plci->command = 0;
return 0;
}
/*------------------------------------------------------------------*/
/* api_parse function, check the format of api messages */
/*------------------------------------------------------------------*/
static word api_parse(byte *msg, word length, byte *format, API_PARSE *parms)
{
word i;
word p;
for (i = 0, p = 0; format[i]; i++) {
if (parms)
{
parms[i].info = &msg[p];
}
switch (format[i]) {
case 'b':
p += 1;
break;
case 'w':
p += 2;
break;
case 'd':
p += 4;
break;
case 's':
if (msg[p] == 0xff) {
parms[i].info += 2;
parms[i].length = msg[p + 1] + (msg[p + 2] << 8);
p += (parms[i].length + 3);
}
else {
parms[i].length = msg[p];
p += (parms[i].length + 1);
}
break;
}
if (p > length) return true;
}
if (parms) parms[i].info = NULL;
return false;
}
static void api_save_msg(API_PARSE *in, byte *format, API_SAVE *out)
{
word i, j, n = 0;
byte *p;
p = out->info;
for (i = 0; format[i] != '\0'; i++)
{
out->parms[i].info = p;
out->parms[i].length = in[i].length;
switch (format[i])
{
case 'b':
n = 1;
break;
case 'w':
n = 2;
break;
case 'd':
n = 4;
break;
case 's':
n = in[i].length + 1;
break;
}
for (j = 0; j < n; j++)
*(p++) = in[i].info[j];
}
out->parms[i].info = NULL;
out->parms[i].length = 0;
}
static void api_load_msg(API_SAVE *in, API_PARSE *out)
{
word i;
i = 0;
do
{
out[i].info = in->parms[i].info;
out[i].length = in->parms[i].length;
} while (in->parms[i++].info);
}
/*------------------------------------------------------------------*/
/* CAPI remove function */
/*------------------------------------------------------------------*/
word api_remove_start(void)
{
word i;
word j;
if (!remove_started) {
remove_started = true;
for (i = 0; i < max_adapter; i++) {
if (adapter[i].request) {
for (j = 0; j < adapter[i].max_plci; j++) {
if (adapter[i].plci[j].Sig.Id) plci_remove(&adapter[i].plci[j]);
}
}
}
return 1;
}
else {
for (i = 0; i < max_adapter; i++) {
if (adapter[i].request) {
for (j = 0; j < adapter[i].max_plci; j++) {
if (adapter[i].plci[j].Sig.Id) return 1;
}
}
}
}
api_remove_complete();
return 0;
}
/*------------------------------------------------------------------*/
/* internal command queue */
/*------------------------------------------------------------------*/
static void init_internal_command_queue(PLCI *plci)
{
word i;
dbug(1, dprintf("%s,%d: init_internal_command_queue",
(char *)(FILE_), __LINE__));
plci->internal_command = 0;
for (i = 0; i < MAX_INTERNAL_COMMAND_LEVELS; i++)
plci->internal_command_queue[i] = NULL;
}
static void start_internal_command(dword Id, PLCI *plci, t_std_internal_command command_function)
{
word i;
dbug(1, dprintf("[%06lx] %s,%d: start_internal_command",
UnMapId(Id), (char *)(FILE_), __LINE__));
if (plci->internal_command == 0)
{
plci->internal_command_queue[0] = command_function;
(*command_function)(Id, plci, OK);
}
else
{
i = 1;
while (plci->internal_command_queue[i] != NULL)
i++;
plci->internal_command_queue[i] = command_function;
}
}
static void next_internal_command(dword Id, PLCI *plci)
{
word i;
dbug(1, dprintf("[%06lx] %s,%d: next_internal_command",
UnMapId(Id), (char *)(FILE_), __LINE__));
plci->internal_command = 0;
plci->internal_command_queue[0] = NULL;
while (plci->internal_command_queue[1] != NULL)
{
for (i = 0; i < MAX_INTERNAL_COMMAND_LEVELS - 1; i++)
plci->internal_command_queue[i] = plci->internal_command_queue[i + 1];
plci->internal_command_queue[MAX_INTERNAL_COMMAND_LEVELS - 1] = NULL;
(*(plci->internal_command_queue[0]))(Id, plci, OK);
if (plci->internal_command != 0)
return;
plci->internal_command_queue[0] = NULL;
}
}
/*------------------------------------------------------------------*/
/* NCCI allocate/remove function */
/*------------------------------------------------------------------*/
static dword ncci_mapping_bug = 0;
static word get_ncci(PLCI *plci, byte ch, word force_ncci)
{
DIVA_CAPI_ADAPTER *a;
word ncci, i, j, k;
a = plci->adapter;
if (!ch || a->ch_ncci[ch])
{
ncci_mapping_bug++;
dbug(1, dprintf("NCCI mapping exists %ld %02x %02x %02x-%02x",
ncci_mapping_bug, ch, force_ncci, a->ncci_ch[a->ch_ncci[ch]], a->ch_ncci[ch]));
ncci = ch;
}
else
{
if (force_ncci)
ncci = force_ncci;
else
{
if ((ch < MAX_NCCI + 1) && !a->ncci_ch[ch])
ncci = ch;
else
{
ncci = 1;
while ((ncci < MAX_NCCI + 1) && a->ncci_ch[ncci])
ncci++;
if (ncci == MAX_NCCI + 1)
{
ncci_mapping_bug++;
i = 1;
do
{
j = 1;
while ((j < MAX_NCCI + 1) && (a->ncci_ch[j] != i))
j++;
k = j;
if (j < MAX_NCCI + 1)
{
do
{
j++;
} while ((j < MAX_NCCI + 1) && (a->ncci_ch[j] != i));
}
} while ((i < MAX_NL_CHANNEL + 1) && (j < MAX_NCCI + 1));
if (i < MAX_NL_CHANNEL + 1)
{
dbug(1, dprintf("NCCI mapping overflow %ld %02x %02x %02x-%02x-%02x",
ncci_mapping_bug, ch, force_ncci, i, k, j));
}
else
{
dbug(1, dprintf("NCCI mapping overflow %ld %02x %02x",
ncci_mapping_bug, ch, force_ncci));
}
ncci = ch;
}
}
a->ncci_plci[ncci] = plci->Id;
a->ncci_state[ncci] = IDLE;
if (!plci->ncci_ring_list)
plci->ncci_ring_list = ncci;
else
a->ncci_next[ncci] = a->ncci_next[plci->ncci_ring_list];
a->ncci_next[plci->ncci_ring_list] = (byte) ncci;
}
a->ncci_ch[ncci] = ch;
a->ch_ncci[ch] = (byte) ncci;
dbug(1, dprintf("NCCI mapping established %ld %02x %02x %02x-%02x",
ncci_mapping_bug, ch, force_ncci, ch, ncci));
}
return (ncci);
}
static void ncci_free_receive_buffers(PLCI *plci, word ncci)
{
DIVA_CAPI_ADAPTER *a;
APPL *appl;
word i, ncci_code;
dword Id;
a = plci->adapter;
Id = (((dword) ncci) << 16) | (((word)(plci->Id)) << 8) | a->Id;
if (ncci)
{
if (a->ncci_plci[ncci] == plci->Id)
{
if (!plci->appl)
{
ncci_mapping_bug++;
dbug(1, dprintf("NCCI mapping appl expected %ld %08lx",
ncci_mapping_bug, Id));
}
else
{
appl = plci->appl;
ncci_code = ncci | (((word) a->Id) << 8);
for (i = 0; i < appl->MaxBuffer; i++)
{
if ((appl->DataNCCI[i] == ncci_code)
&& (((byte)(appl->DataFlags[i] >> 8)) == plci->Id))
{
appl->DataNCCI[i] = 0;
}
}
}
}
}
else
{
for (ncci = 1; ncci < MAX_NCCI + 1; ncci++)
{
if (a->ncci_plci[ncci] == plci->Id)
{
if (!plci->appl)
{
ncci_mapping_bug++;
dbug(1, dprintf("NCCI mapping no appl %ld %08lx",
ncci_mapping_bug, Id));
}
else
{
appl = plci->appl;
ncci_code = ncci | (((word) a->Id) << 8);
for (i = 0; i < appl->MaxBuffer; i++)
{
if ((appl->DataNCCI[i] == ncci_code)
&& (((byte)(appl->DataFlags[i] >> 8)) == plci->Id))
{
appl->DataNCCI[i] = 0;
}
}
}
}
}
}
}
static void cleanup_ncci_data(PLCI *plci, word ncci)
{
NCCI *ncci_ptr;
if (ncci && (plci->adapter->ncci_plci[ncci] == plci->Id))
{
ncci_ptr = &(plci->adapter->ncci[ncci]);
if (plci->appl)
{
while (ncci_ptr->data_pending != 0)
{
if (!plci->data_sent || (ncci_ptr->DBuffer[ncci_ptr->data_out].P != plci->data_sent_ptr))
TransmitBufferFree(plci->appl, ncci_ptr->DBuffer[ncci_ptr->data_out].P);
(ncci_ptr->data_out)++;
if (ncci_ptr->data_out == MAX_DATA_B3)
ncci_ptr->data_out = 0;
(ncci_ptr->data_pending)--;
}
}
ncci_ptr->data_out = 0;
ncci_ptr->data_pending = 0;
ncci_ptr->data_ack_out = 0;
ncci_ptr->data_ack_pending = 0;
}
}
static void ncci_remove(PLCI *plci, word ncci, byte preserve_ncci)
{
DIVA_CAPI_ADAPTER *a;
dword Id;
word i;
a = plci->adapter;
Id = (((dword) ncci) << 16) | (((word)(plci->Id)) << 8) | a->Id;
if (!preserve_ncci)
ncci_free_receive_buffers(plci, ncci);
if (ncci)
{
if (a->ncci_plci[ncci] != plci->Id)
{
ncci_mapping_bug++;
dbug(1, dprintf("NCCI mapping doesn't exist %ld %08lx %02x",
ncci_mapping_bug, Id, preserve_ncci));
}
else
{
cleanup_ncci_data(plci, ncci);
dbug(1, dprintf("NCCI mapping released %ld %08lx %02x %02x-%02x",
ncci_mapping_bug, Id, preserve_ncci, a->ncci_ch[ncci], ncci));
a->ch_ncci[a->ncci_ch[ncci]] = 0;
if (!preserve_ncci)
{
a->ncci_ch[ncci] = 0;
a->ncci_plci[ncci] = 0;
a->ncci_state[ncci] = IDLE;
i = plci->ncci_ring_list;
while ((i != 0) && (a->ncci_next[i] != plci->ncci_ring_list) && (a->ncci_next[i] != ncci))
i = a->ncci_next[i];
if ((i != 0) && (a->ncci_next[i] == ncci))
{
if (i == ncci)
plci->ncci_ring_list = 0;
else if (plci->ncci_ring_list == ncci)
plci->ncci_ring_list = i;
a->ncci_next[i] = a->ncci_next[ncci];
}
a->ncci_next[ncci] = 0;
}
}
}
else
{
for (ncci = 1; ncci < MAX_NCCI + 1; ncci++)
{
if (a->ncci_plci[ncci] == plci->Id)
{
cleanup_ncci_data(plci, ncci);
dbug(1, dprintf("NCCI mapping released %ld %08lx %02x %02x-%02x",
ncci_mapping_bug, Id, preserve_ncci, a->ncci_ch[ncci], ncci));
a->ch_ncci[a->ncci_ch[ncci]] = 0;
if (!preserve_ncci)
{
a->ncci_ch[ncci] = 0;
a->ncci_plci[ncci] = 0;
a->ncci_state[ncci] = IDLE;
a->ncci_next[ncci] = 0;
}
}
}
if (!preserve_ncci)
plci->ncci_ring_list = 0;
}
}
/*------------------------------------------------------------------*/
/* PLCI remove function */
/*------------------------------------------------------------------*/
static void plci_free_msg_in_queue(PLCI *plci)
{
word i;
if (plci->appl)
{
i = plci->msg_in_read_pos;
while (i != plci->msg_in_write_pos)
{
if (i == plci->msg_in_wrap_pos)
i = 0;
if (((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[i]))->header.command == _DATA_B3_R)
{
TransmitBufferFree(plci->appl,
(byte *)(long)(((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[i]))->info.data_b3_req.Data));
}
i += (((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[i]))->header.length +
MSG_IN_OVERHEAD + 3) & 0xfffc;
}
}
plci->msg_in_write_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_read_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_wrap_pos = MSG_IN_QUEUE_SIZE;
}
static void plci_remove(PLCI *plci)
{
if (!plci) {
dbug(1, dprintf("plci_remove(no plci)"));
return;
}
init_internal_command_queue(plci);
dbug(1, dprintf("plci_remove(%x,tel=%x)", plci->Id, plci->tel));
if (plci_remove_check(plci))
{
return;
}
if (plci->Sig.Id == 0xff)
{
dbug(1, dprintf("D-channel X.25 plci->NL.Id:%0x", plci->NL.Id));
if (plci->NL.Id && !plci->nl_remove_id)
{
nl_req_ncci(plci, REMOVE, 0);
send_req(plci);
}
}
else
{
if (!plci->sig_remove_id
&& (plci->Sig.Id
|| (plci->req_in != plci->req_out)
|| (plci->nl_req || plci->sig_req)))
{
sig_req(plci, HANGUP, 0);
send_req(plci);
}
}
ncci_remove(plci, 0, false);
plci_free_msg_in_queue(plci);
plci->channels = 0;
plci->appl = NULL;
if ((plci->State == INC_CON_PENDING) || (plci->State == INC_CON_ALERT))
plci->State = OUTG_DIS_PENDING;
}
/*------------------------------------------------------------------*/
/* Application Group function helpers */
/*------------------------------------------------------------------*/
static void set_group_ind_mask(PLCI *plci)
{
word i;
for (i = 0; i < C_IND_MASK_DWORDS; i++)
plci->group_optimization_mask_table[i] = 0xffffffffL;
}
static void clear_group_ind_mask_bit(PLCI *plci, word b)
{
plci->group_optimization_mask_table[b >> 5] &= ~(1L << (b & 0x1f));
}
static byte test_group_ind_mask_bit(PLCI *plci, word b)
{
return ((plci->group_optimization_mask_table[b >> 5] & (1L << (b & 0x1f))) != 0);
}
/*------------------------------------------------------------------*/
/* c_ind_mask operations for arbitrary MAX_APPL */
/*------------------------------------------------------------------*/
static void clear_c_ind_mask(PLCI *plci)
{
word i;
for (i = 0; i < C_IND_MASK_DWORDS; i++)
plci->c_ind_mask_table[i] = 0;
}
static byte c_ind_mask_empty(PLCI *plci)
{
word i;
i = 0;
while ((i < C_IND_MASK_DWORDS) && (plci->c_ind_mask_table[i] == 0))
i++;
return (i == C_IND_MASK_DWORDS);
}
static void set_c_ind_mask_bit(PLCI *plci, word b)
{
plci->c_ind_mask_table[b >> 5] |= (1L << (b & 0x1f));
}
static void clear_c_ind_mask_bit(PLCI *plci, word b)
{
plci->c_ind_mask_table[b >> 5] &= ~(1L << (b & 0x1f));
}
static byte test_c_ind_mask_bit(PLCI *plci, word b)
{
return ((plci->c_ind_mask_table[b >> 5] & (1L << (b & 0x1f))) != 0);
}
static void dump_c_ind_mask(PLCI *plci)
{
static char hex_digit_table[0x10] =
{'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'};
word i, j, k;
dword d;
char *p;
char buf[40];
for (i = 0; i < C_IND_MASK_DWORDS; i += 4)
{
p = buf + 36;
*p = '\0';
for (j = 0; j < 4; j++)
{
if (i + j < C_IND_MASK_DWORDS)
{
d = plci->c_ind_mask_table[i + j];
for (k = 0; k < 8; k++)
{
*(--p) = hex_digit_table[d & 0xf];
d >>= 4;
}
}
else if (i != 0)
{
for (k = 0; k < 8; k++)
*(--p) = ' ';
}
*(--p) = ' ';
}
dbug(1, dprintf("c_ind_mask =%s", (char *) p));
}
}
#define dump_plcis(a)
/*------------------------------------------------------------------*/
/* translation function for each message */
/*------------------------------------------------------------------*/
static byte connect_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word ch;
word i;
word Info;
byte LinkLayer;
API_PARSE *ai;
API_PARSE *bp;
API_PARSE ai_parms[5];
word channel = 0;
dword ch_mask;
byte m;
static byte esc_chi[35] = {0x02, 0x18, 0x01};
static byte lli[2] = {0x01, 0x00};
byte noCh = 0;
word dir = 0;
byte *p_chi = "";
for (i = 0; i < 5; i++) ai_parms[i].length = 0;
dbug(1, dprintf("connect_req(%d)", parms->length));
Info = _WRONG_IDENTIFIER;
if (a)
{
if (a->adapter_disabled)
{
dbug(1, dprintf("adapter disabled"));
Id = ((word)1 << 8) | a->Id;
sendf(appl, _CONNECT_R | CONFIRM, Id, Number, "w", 0);
sendf(appl, _DISCONNECT_I, Id, 0, "w", _L1_ERROR);
return false;
}
Info = _OUT_OF_PLCI;
if ((i = get_plci(a)))
{
Info = 0;
plci = &a->plci[i - 1];
plci->appl = appl;
plci->call_dir = CALL_DIR_OUT | CALL_DIR_ORIGINATE;
/* check 'external controller' bit for codec support */
if (Id & EXT_CONTROLLER)
{
if (AdvCodecSupport(a, plci, appl, 0))
{
plci->Id = 0;
sendf(appl, _CONNECT_R | CONFIRM, Id, Number, "w", _WRONG_IDENTIFIER);
return 2;
}
}
ai = &parms[9];
bp = &parms[5];
ch = 0;
if (bp->length)LinkLayer = bp->info[3];
else LinkLayer = 0;
if (ai->length)
{
ch = 0xffff;
if (!api_parse(&ai->info[1], (word)ai->length, "ssss", ai_parms))
{
ch = 0;
if (ai_parms[0].length)
{
ch = GET_WORD(ai_parms[0].info + 1);
if (ch > 4) ch = 0; /* safety -> ignore ChannelID */
if (ch == 4) /* explizit CHI in message */
{
/* check length of B-CH struct */
if ((ai_parms[0].info)[3] >= 1)
{
if ((ai_parms[0].info)[4] == CHI)
{
p_chi = &((ai_parms[0].info)[5]);
}
else
{
p_chi = &((ai_parms[0].info)[3]);
}
if (p_chi[0] > 35) /* check length of channel ID */
{
Info = _WRONG_MESSAGE_FORMAT;
}
}
else Info = _WRONG_MESSAGE_FORMAT;
}
if (ch == 3 && ai_parms[0].length >= 7 && ai_parms[0].length <= 36)
{
dir = GET_WORD(ai_parms[0].info + 3);
ch_mask = 0;
m = 0x3f;
for (i = 0; i + 5 <= ai_parms[0].length; i++)
{
if (ai_parms[0].info[i + 5] != 0)
{
if ((ai_parms[0].info[i + 5] | m) != 0xff)
Info = _WRONG_MESSAGE_FORMAT;
else
{
if (ch_mask == 0)
channel = i;
ch_mask |= 1L << i;
}
}
m = 0;
}
if (ch_mask == 0)
Info = _WRONG_MESSAGE_FORMAT;
if (!Info)
{
if ((ai_parms[0].length == 36) || (ch_mask != ((dword)(1L << channel))))
{
esc_chi[0] = (byte)(ai_parms[0].length - 2);
for (i = 0; i + 5 <= ai_parms[0].length; i++)
esc_chi[i + 3] = ai_parms[0].info[i + 5];
}
else
esc_chi[0] = 2;
esc_chi[2] = (byte)channel;
plci->b_channel = (byte)channel; /* not correct for ETSI ch 17..31 */
add_p(plci, LLI, lli);
add_p(plci, ESC, esc_chi);
plci->State = LOCAL_CONNECT;
if (!dir) plci->call_dir |= CALL_DIR_FORCE_OUTG_NL; /* dir 0=DTE, 1=DCE */
}
}
}
}
else Info = _WRONG_MESSAGE_FORMAT;
}
dbug(1, dprintf("ch=%x,dir=%x,p_ch=%d", ch, dir, channel));
plci->command = _CONNECT_R;
plci->number = Number;
/* x.31 or D-ch free SAPI in LinkLayer? */
if (ch == 1 && LinkLayer != 3 && LinkLayer != 12) noCh = true;
if ((ch == 0 || ch == 2 || noCh || ch == 3 || ch == 4) && !Info)
{
/* B-channel used for B3 connections (ch==0), or no B channel */
/* is used (ch==2) or perm. connection (3) is used do a CALL */
if (noCh) Info = add_b1(plci, &parms[5], 2, 0); /* no resource */
else Info = add_b1(plci, &parms[5], ch, 0);
add_s(plci, OAD, &parms[2]);
add_s(plci, OSA, &parms[4]);
add_s(plci, BC, &parms[6]);
add_s(plci, LLC, &parms[7]);
add_s(plci, HLC, &parms[8]);
if (a->Info_Mask[appl->Id - 1] & 0x200)
{
/* early B3 connect (CIP mask bit 9) no release after a disc */
add_p(plci, LLI, "\x01\x01");
}
if (GET_WORD(parms[0].info) < 29) {
add_p(plci, BC, cip_bc[GET_WORD(parms[0].info)][a->u_law]);
add_p(plci, HLC, cip_hlc[GET_WORD(parms[0].info)]);
}
add_p(plci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(plci, ASSIGN, DSIG_ID);
}
else if (ch == 1) {
/* D-Channel used for B3 connections */
plci->Sig.Id = 0xff;
Info = 0;
}
if (!Info && ch != 2 && !noCh) {
Info = add_b23(plci, &parms[5]);
if (!Info) {
if (!(plci->tel && !plci->adv_nl))nl_req_ncci(plci, ASSIGN, 0);
}
}
if (!Info)
{
if (ch == 0 || ch == 2 || ch == 3 || noCh || ch == 4)
{
if (plci->spoofed_msg == SPOOFING_REQUIRED)
{
api_save_msg(parms, "wsssssssss", &plci->saved_msg);
plci->spoofed_msg = CALL_REQ;
plci->internal_command = BLOCK_PLCI;
plci->command = 0;
dbug(1, dprintf("Spoof"));
send_req(plci);
return false;
}
if (ch == 4)add_p(plci, CHI, p_chi);
add_s(plci, CPN, &parms[1]);
add_s(plci, DSA, &parms[3]);
if (noCh) add_p(plci, ESC, "\x02\x18\xfd"); /* D-channel, no B-L3 */
add_ai(plci, &parms[9]);
if (!dir)sig_req(plci, CALL_REQ, 0);
else
{
plci->command = PERM_LIST_REQ;
plci->appl = appl;
sig_req(plci, LISTEN_REQ, 0);
send_req(plci);
return false;
}
}
send_req(plci);
return false;
}
plci->Id = 0;
}
}
sendf(appl,
_CONNECT_R | CONFIRM,
Id,
Number,
"w", Info);
return 2;
}
static byte connect_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word i, Info;
word Reject;
static byte cau_t[] = {0, 0, 0x90, 0x91, 0xac, 0x9d, 0x86, 0xd8, 0x9b};
static byte esc_t[] = {0x03, 0x08, 0x00, 0x00};
API_PARSE *ai;
API_PARSE ai_parms[5];
word ch = 0;
if (!plci) {
dbug(1, dprintf("connect_res(no plci)"));
return 0; /* no plci, no send */
}
dbug(1, dprintf("connect_res(State=0x%x)", plci->State));
for (i = 0; i < 5; i++) ai_parms[i].length = 0;
ai = &parms[5];
dbug(1, dprintf("ai->length=%d", ai->length));
if (ai->length)
{
if (!api_parse(&ai->info[1], (word)ai->length, "ssss", ai_parms))
{
dbug(1, dprintf("ai_parms[0].length=%d/0x%x", ai_parms[0].length, GET_WORD(ai_parms[0].info + 1)));
ch = 0;
if (ai_parms[0].length)
{
ch = GET_WORD(ai_parms[0].info + 1);
dbug(1, dprintf("BCH-I=0x%x", ch));
}
}
}
if (plci->State == INC_CON_CONNECTED_ALERT)
{
dbug(1, dprintf("Connected Alert Call_Res"));
if (a->Info_Mask[appl->Id - 1] & 0x200)
{
/* early B3 connect (CIP mask bit 9) no release after a disc */
add_p(plci, LLI, "\x01\x01");
}
add_s(plci, CONN_NR, &parms[2]);
add_s(plci, LLC, &parms[4]);
add_ai(plci, &parms[5]);
plci->State = INC_CON_ACCEPT;
sig_req(plci, CALL_RES, 0);
return 1;
}
else if (plci->State == INC_CON_PENDING || plci->State == INC_CON_ALERT) {
clear_c_ind_mask_bit(plci, (word)(appl->Id - 1));
dump_c_ind_mask(plci);
Reject = GET_WORD(parms[0].info);
dbug(1, dprintf("Reject=0x%x", Reject));
if (Reject)
{
if (c_ind_mask_empty(plci))
{
if ((Reject & 0xff00) == 0x3400)
{
esc_t[2] = ((byte)(Reject & 0x00ff)) | 0x80;
add_p(plci, ESC, esc_t);
add_ai(plci, &parms[5]);
sig_req(plci, REJECT, 0);
}
else if (Reject == 1 || Reject > 9)
{
add_ai(plci, &parms[5]);
sig_req(plci, HANGUP, 0);
}
else
{
esc_t[2] = cau_t[(Reject&0x000f)];
add_p(plci, ESC, esc_t);
add_ai(plci, &parms[5]);
sig_req(plci, REJECT, 0);
}
plci->appl = appl;
}
else
{
sendf(appl, _DISCONNECT_I, Id, 0, "w", _OTHER_APPL_CONNECTED);
}
}
else {
plci->appl = appl;
if (Id & EXT_CONTROLLER) {
if (AdvCodecSupport(a, plci, appl, 0)) {
dbug(1, dprintf("connect_res(error from AdvCodecSupport)"));
sig_req(plci, HANGUP, 0);
return 1;
}
if (plci->tel == ADV_VOICE && a->AdvCodecPLCI)
{
Info = add_b23(plci, &parms[1]);
if (Info)
{
dbug(1, dprintf("connect_res(error from add_b23)"));
sig_req(plci, HANGUP, 0);
return 1;
}
if (plci->adv_nl)
{
nl_req_ncci(plci, ASSIGN, 0);
}
}
}
else
{
plci->tel = 0;
if (ch != 2)
{
Info = add_b23(plci, &parms[1]);
if (Info)
{
dbug(1, dprintf("connect_res(error from add_b23 2)"));
sig_req(plci, HANGUP, 0);
return 1;
}
}
nl_req_ncci(plci, ASSIGN, 0);
}
if (plci->spoofed_msg == SPOOFING_REQUIRED)
{
api_save_msg(parms, "wsssss", &plci->saved_msg);
plci->spoofed_msg = CALL_RES;
plci->internal_command = BLOCK_PLCI;
plci->command = 0;
dbug(1, dprintf("Spoof"));
}
else
{
add_b1(plci, &parms[1], ch, plci->B1_facilities);
if (a->Info_Mask[appl->Id - 1] & 0x200)
{
/* early B3 connect (CIP mask bit 9) no release after a disc */
add_p(plci, LLI, "\x01\x01");
}
add_s(plci, CONN_NR, &parms[2]);
add_s(plci, LLC, &parms[4]);
add_ai(plci, &parms[5]);
plci->State = INC_CON_ACCEPT;
sig_req(plci, CALL_RES, 0);
}
for (i = 0; i < max_appl; i++) {
if (test_c_ind_mask_bit(plci, i)) {
sendf(&application[i], _DISCONNECT_I, Id, 0, "w", _OTHER_APPL_CONNECTED);
}
}
}
}
return 1;
}
static byte connect_a_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
dbug(1, dprintf("connect_a_res"));
return false;
}
static byte disconnect_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info;
word i;
dbug(1, dprintf("disconnect_req"));
Info = _WRONG_IDENTIFIER;
if (plci)
{
if (plci->State == INC_CON_PENDING || plci->State == INC_CON_ALERT)
{
clear_c_ind_mask_bit(plci, (word)(appl->Id - 1));
plci->appl = appl;
for (i = 0; i < max_appl; i++)
{
if (test_c_ind_mask_bit(plci, i))
sendf(&application[i], _DISCONNECT_I, Id, 0, "w", 0);
}
plci->State = OUTG_DIS_PENDING;
}
if (plci->Sig.Id && plci->appl)
{
Info = 0;
if (plci->Sig.Id != 0xff)
{
if (plci->State != INC_DIS_PENDING)
{
add_ai(plci, &msg[0]);
sig_req(plci, HANGUP, 0);
plci->State = OUTG_DIS_PENDING;
return 1;
}
}
else
{
if (plci->NL.Id && !plci->nl_remove_id)
{
mixer_remove(plci);
nl_req_ncci(plci, REMOVE, 0);
sendf(appl, _DISCONNECT_R | CONFIRM, Id, Number, "w", 0);
sendf(appl, _DISCONNECT_I, Id, 0, "w", 0);
plci->State = INC_DIS_PENDING;
}
return 1;
}
}
}
if (!appl) return false;
sendf(appl, _DISCONNECT_R | CONFIRM, Id, Number, "w", Info);
return false;
}
static byte disconnect_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
dbug(1, dprintf("disconnect_res"));
if (plci)
{
/* clear ind mask bit, just in case of collsion of */
/* DISCONNECT_IND and CONNECT_RES */
clear_c_ind_mask_bit(plci, (word)(appl->Id - 1));
ncci_free_receive_buffers(plci, 0);
if (plci_remove_check(plci))
{
return 0;
}
if (plci->State == INC_DIS_PENDING
|| plci->State == SUSPENDING) {
if (c_ind_mask_empty(plci)) {
if (plci->State != SUSPENDING) plci->State = IDLE;
dbug(1, dprintf("chs=%d", plci->channels));
if (!plci->channels) {
plci_remove(plci);
}
}
}
}
return 0;
}
static byte listen_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word Info;
byte i;
dbug(1, dprintf("listen_req(Appl=0x%x)", appl->Id));
Info = _WRONG_IDENTIFIER;
if (a) {
Info = 0;
a->Info_Mask[appl->Id - 1] = GET_DWORD(parms[0].info);
a->CIP_Mask[appl->Id - 1] = GET_DWORD(parms[1].info);
dbug(1, dprintf("CIP_MASK=0x%lx", GET_DWORD(parms[1].info)));
if (a->Info_Mask[appl->Id - 1] & 0x200) { /* early B3 connect provides */
a->Info_Mask[appl->Id - 1] |= 0x10; /* call progression infos */
}
/* check if external controller listen and switch listen on or off*/
if (Id&EXT_CONTROLLER && GET_DWORD(parms[1].info)) {
if (a->profile.Global_Options & ON_BOARD_CODEC) {
dummy_plci.State = IDLE;
a->codec_listen[appl->Id - 1] = &dummy_plci;
a->TelOAD[0] = (byte)(parms[3].length);
for (i = 1; parms[3].length >= i && i < 22; i++) {
a->TelOAD[i] = parms[3].info[i];
}
a->TelOAD[i] = 0;
a->TelOSA[0] = (byte)(parms[4].length);
for (i = 1; parms[4].length >= i && i < 22; i++) {
a->TelOSA[i] = parms[4].info[i];
}
a->TelOSA[i] = 0;
}
else Info = 0x2002; /* wrong controller, codec not supported */
}
else{ /* clear listen */
a->codec_listen[appl->Id - 1] = (PLCI *)0;
}
}
sendf(appl,
_LISTEN_R | CONFIRM,
Id,
Number,
"w", Info);
if (a) listen_check(a);
return false;
}
static byte info_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
word i;
API_PARSE *ai;
PLCI *rc_plci = NULL;
API_PARSE ai_parms[5];
word Info = 0;
dbug(1, dprintf("info_req"));
for (i = 0; i < 5; i++) ai_parms[i].length = 0;
ai = &msg[1];
if (ai->length)
{
if (api_parse(&ai->info[1], (word)ai->length, "ssss", ai_parms))
{
dbug(1, dprintf("AddInfo wrong"));
Info = _WRONG_MESSAGE_FORMAT;
}
}
if (!a) Info = _WRONG_STATE;
if (!Info && plci)
{ /* no fac, with CPN, or KEY */
rc_plci = plci;
if (!ai_parms[3].length && plci->State && (msg[0].length || ai_parms[1].length))
{
/* overlap sending option */
dbug(1, dprintf("OvlSnd"));
add_s(plci, CPN, &msg[0]);
add_s(plci, KEY, &ai_parms[1]);
sig_req(plci, INFO_REQ, 0);
send_req(plci);
return false;
}
if (plci->State && ai_parms[2].length)
{
/* User_Info option */
dbug(1, dprintf("UUI"));
add_s(plci, UUI, &ai_parms[2]);
sig_req(plci, USER_DATA, 0);
}
else if (plci->State && ai_parms[3].length)
{
/* Facility option */
dbug(1, dprintf("FAC"));
add_s(plci, CPN, &msg[0]);
add_ai(plci, &msg[1]);
sig_req(plci, FACILITY_REQ, 0);
}
else
{
Info = _WRONG_STATE;
}
}
else if ((ai_parms[1].length || ai_parms[2].length || ai_parms[3].length) && !Info)
{
/* NCR_Facility option -> send UUI and Keypad too */
dbug(1, dprintf("NCR_FAC"));
if ((i = get_plci(a)))
{
rc_plci = &a->plci[i - 1];
appl->NullCREnable = true;
rc_plci->internal_command = C_NCR_FAC_REQ;
rc_plci->appl = appl;
add_p(rc_plci, CAI, "\x01\x80");
add_p(rc_plci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rc_plci, ASSIGN, DSIG_ID);
send_req(rc_plci);
}
else
{
Info = _OUT_OF_PLCI;
}
if (!Info)
{
add_s(rc_plci, CPN, &msg[0]);
add_ai(rc_plci, &msg[1]);
sig_req(rc_plci, NCR_FACILITY, 0);
send_req(rc_plci);
return false;
/* for application controlled supplementary services */
}
}
if (!rc_plci)
{
Info = _WRONG_MESSAGE_FORMAT;
}
if (!Info)
{
send_req(rc_plci);
}
else
{ /* appl is not assigned to a PLCI or error condition */
dbug(1, dprintf("localInfoCon"));
sendf(appl,
_INFO_R | CONFIRM,
Id,
Number,
"w", Info);
}
return false;
}
static byte info_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
dbug(1, dprintf("info_res"));
return false;
}
static byte alert_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info;
byte ret;
dbug(1, dprintf("alert_req"));
Info = _WRONG_IDENTIFIER;
ret = false;
if (plci) {
Info = _ALERT_IGNORED;
if (plci->State != INC_CON_ALERT) {
Info = _WRONG_STATE;
if (plci->State == INC_CON_PENDING) {
Info = 0;
plci->State = INC_CON_ALERT;
add_ai(plci, &msg[0]);
sig_req(plci, CALL_ALERT, 0);
ret = 1;
}
}
}
sendf(appl,
_ALERT_R | CONFIRM,
Id,
Number,
"w", Info);
return ret;
}
static byte facility_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info = 0;
word i = 0;
word selector;
word SSreq;
long relatedPLCIvalue;
DIVA_CAPI_ADAPTER *relatedadapter;
byte *SSparms = "";
byte RCparms[] = "\x05\x00\x00\x02\x00\x00";
byte SSstruct[] = "\x09\x00\x00\x06\x00\x00\x00\x00\x00\x00";
API_PARSE *parms;
API_PARSE ss_parms[11];
PLCI *rplci;
byte cai[15];
dword d;
API_PARSE dummy;
dbug(1, dprintf("facility_req"));
for (i = 0; i < 9; i++) ss_parms[i].length = 0;
parms = &msg[1];
if (!a)
{
dbug(1, dprintf("wrong Ctrl"));
Info = _WRONG_IDENTIFIER;
}
selector = GET_WORD(msg[0].info);
if (!Info)
{
switch (selector)
{
case SELECTOR_HANDSET:
Info = AdvCodecSupport(a, plci, appl, HOOK_SUPPORT);
break;
case SELECTOR_SU_SERV:
if (!msg[1].length)
{
Info = _WRONG_MESSAGE_FORMAT;
break;
}
SSreq = GET_WORD(&(msg[1].info[1]));
PUT_WORD(&RCparms[1], SSreq);
SSparms = RCparms;
switch (SSreq)
{
case S_GET_SUPPORTED_SERVICES:
if ((i = get_plci(a)))
{
rplci = &a->plci[i - 1];
rplci->appl = appl;
add_p(rplci, CAI, "\x01\x80");
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
}
else
{
PUT_DWORD(&SSstruct[6], MASK_TERMINAL_PORTABILITY);
SSparms = (byte *)SSstruct;
break;
}
rplci->internal_command = GETSERV_REQ_PEND;
rplci->number = Number;
rplci->appl = appl;
sig_req(rplci, S_SUPPORTED, 0);
send_req(rplci);
return false;
break;
case S_LISTEN:
if (parms->length == 7)
{
if (api_parse(&parms->info[1], (word)parms->length, "wbd", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
}
else
{
Info = _WRONG_MESSAGE_FORMAT;
break;
}
a->Notification_Mask[appl->Id - 1] = GET_DWORD(ss_parms[2].info);
if (a->Notification_Mask[appl->Id - 1] & SMASK_MWI) /* MWI active? */
{
if ((i = get_plci(a)))
{
rplci = &a->plci[i - 1];
rplci->appl = appl;
add_p(rplci, CAI, "\x01\x80");
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
}
else
{
break;
}
rplci->internal_command = GET_MWI_STATE;
rplci->number = Number;
sig_req(rplci, MWI_POLL, 0);
send_req(rplci);
}
break;
case S_HOLD:
api_parse(&parms->info[1], (word)parms->length, "ws", ss_parms);
if (plci && plci->State && plci->SuppState == IDLE)
{
plci->SuppState = HOLD_REQUEST;
plci->command = C_HOLD_REQ;
add_s(plci, CAI, &ss_parms[1]);
sig_req(plci, CALL_HOLD, 0);
send_req(plci);
return false;
}
else Info = 0x3010; /* wrong state */
break;
case S_RETRIEVE:
if (plci && plci->State && plci->SuppState == CALL_HELD)
{
if (Id & EXT_CONTROLLER)
{
if (AdvCodecSupport(a, plci, appl, 0))
{
Info = 0x3010; /* wrong state */
break;
}
}
else plci->tel = 0;
plci->SuppState = RETRIEVE_REQUEST;
plci->command = C_RETRIEVE_REQ;
if (plci->spoofed_msg == SPOOFING_REQUIRED)
{
plci->spoofed_msg = CALL_RETRIEVE;
plci->internal_command = BLOCK_PLCI;
plci->command = 0;
dbug(1, dprintf("Spoof"));
return false;
}
else
{
sig_req(plci, CALL_RETRIEVE, 0);
send_req(plci);
return false;
}
}
else Info = 0x3010; /* wrong state */
break;
case S_SUSPEND:
if (parms->length)
{
if (api_parse(&parms->info[1], (word)parms->length, "wbs", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
}
if (plci && plci->State)
{
add_s(plci, CAI, &ss_parms[2]);
plci->command = SUSPEND_REQ;
sig_req(plci, SUSPEND, 0);
plci->State = SUSPENDING;
send_req(plci);
}
else Info = 0x3010; /* wrong state */
break;
case S_RESUME:
if (!(i = get_plci(a)))
{
Info = _OUT_OF_PLCI;
break;
}
rplci = &a->plci[i - 1];
rplci->appl = appl;
rplci->number = Number;
rplci->tel = 0;
rplci->call_dir = CALL_DIR_OUT | CALL_DIR_ORIGINATE;
/* check 'external controller' bit for codec support */
if (Id & EXT_CONTROLLER)
{
if (AdvCodecSupport(a, rplci, appl, 0))
{
rplci->Id = 0;
Info = 0x300A;
break;
}
}
if (parms->length)
{
if (api_parse(&parms->info[1], (word)parms->length, "wbs", ss_parms))
{
dbug(1, dprintf("format wrong"));
rplci->Id = 0;
Info = _WRONG_MESSAGE_FORMAT;
break;
}
}
dummy.length = 0;
dummy.info = "\x00";
add_b1(rplci, &dummy, 0, 0);
if (a->Info_Mask[appl->Id - 1] & 0x200)
{
/* early B3 connect (CIP mask bit 9) no release after a disc */
add_p(rplci, LLI, "\x01\x01");
}
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
add_s(rplci, CAI, &ss_parms[2]);
rplci->command = RESUME_REQ;
sig_req(rplci, RESUME, 0);
rplci->State = RESUMING;
send_req(rplci);
break;
case S_CONF_BEGIN: /* Request */
case S_CONF_DROP:
case S_CONF_ISOLATE:
case S_CONF_REATTACH:
if (api_parse(&parms->info[1], (word)parms->length, "wbd", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (plci && plci->State && ((plci->SuppState == IDLE) || (plci->SuppState == CALL_HELD)))
{
d = GET_DWORD(ss_parms[2].info);
if (d >= 0x80)
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
plci->ptyState = (byte)SSreq;
plci->command = 0;
cai[0] = 2;
switch (SSreq)
{
case S_CONF_BEGIN:
cai[1] = CONF_BEGIN;
plci->internal_command = CONF_BEGIN_REQ_PEND;
break;
case S_CONF_DROP:
cai[1] = CONF_DROP;
plci->internal_command = CONF_DROP_REQ_PEND;
break;
case S_CONF_ISOLATE:
cai[1] = CONF_ISOLATE;
plci->internal_command = CONF_ISOLATE_REQ_PEND;
break;
case S_CONF_REATTACH:
cai[1] = CONF_REATTACH;
plci->internal_command = CONF_REATTACH_REQ_PEND;
break;
}
cai[2] = (byte)d; /* Conference Size resp. PartyId */
add_p(plci, CAI, cai);
sig_req(plci, S_SERVICE, 0);
send_req(plci);
return false;
}
else Info = 0x3010; /* wrong state */
break;
case S_ECT:
case S_3PTY_BEGIN:
case S_3PTY_END:
case S_CONF_ADD:
if (parms->length == 7)
{
if (api_parse(&parms->info[1], (word)parms->length, "wbd", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
}
else if (parms->length == 8) /* workaround for the T-View-S */
{
if (api_parse(&parms->info[1], (word)parms->length, "wbdb", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
}
else
{
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (!msg[1].length)
{
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (!plci)
{
Info = _WRONG_IDENTIFIER;
break;
}
relatedPLCIvalue = GET_DWORD(ss_parms[2].info);
relatedPLCIvalue &= 0x0000FFFF;
dbug(1, dprintf("PTY/ECT/addCONF,relPLCI=%lx", relatedPLCIvalue));
/* controller starts with 0 up to (max_adapter - 1) */
if (((relatedPLCIvalue & 0x7f) == 0)
|| (MapController((byte)(relatedPLCIvalue & 0x7f)) == 0)
|| (MapController((byte)(relatedPLCIvalue & 0x7f)) > max_adapter))
{
if (SSreq == S_3PTY_END)
{
dbug(1, dprintf("wrong Controller use 2nd PLCI=PLCI"));
rplci = plci;
}
else
{
Info = 0x3010; /* wrong state */
break;
}
}
else
{
relatedadapter = &adapter[MapController((byte)(relatedPLCIvalue & 0x7f)) - 1];
relatedPLCIvalue >>= 8;
/* find PLCI PTR*/
for (i = 0, rplci = NULL; i < relatedadapter->max_plci; i++)
{
if (relatedadapter->plci[i].Id == (byte)relatedPLCIvalue)
{
rplci = &relatedadapter->plci[i];
}
}
if (!rplci || !relatedPLCIvalue)
{
if (SSreq == S_3PTY_END)
{
dbug(1, dprintf("use 2nd PLCI=PLCI"));
rplci = plci;
}
else
{
Info = 0x3010; /* wrong state */
break;
}
}
}
/*
dbug(1, dprintf("rplci:%x", rplci));
dbug(1, dprintf("plci:%x", plci));
dbug(1, dprintf("rplci->ptyState:%x", rplci->ptyState));
dbug(1, dprintf("plci->ptyState:%x", plci->ptyState));
dbug(1, dprintf("SSreq:%x", SSreq));
dbug(1, dprintf("rplci->internal_command:%x", rplci->internal_command));
dbug(1, dprintf("rplci->appl:%x", rplci->appl));
dbug(1, dprintf("rplci->Id:%x", rplci->Id));
*/
/* send PTY/ECT req, cannot check all states because of US stuff */
if (!rplci->internal_command && rplci->appl)
{
plci->command = 0;
rplci->relatedPTYPLCI = plci;
plci->relatedPTYPLCI = rplci;
rplci->ptyState = (byte)SSreq;
if (SSreq == S_ECT)
{
rplci->internal_command = ECT_REQ_PEND;
cai[1] = ECT_EXECUTE;
rplci->vswitchstate = 0;
rplci->vsprot = 0;
rplci->vsprotdialect = 0;
plci->vswitchstate = 0;
plci->vsprot = 0;
plci->vsprotdialect = 0;
}
else if (SSreq == S_CONF_ADD)
{
rplci->internal_command = CONF_ADD_REQ_PEND;
cai[1] = CONF_ADD;
}
else
{
rplci->internal_command = PTY_REQ_PEND;
cai[1] = (byte)(SSreq - 3);
}
rplci->number = Number;
if (plci != rplci) /* explicit invocation */
{
cai[0] = 2;
cai[2] = plci->Sig.Id;
dbug(1, dprintf("explicit invocation"));
}
else
{
dbug(1, dprintf("implicit invocation"));
cai[0] = 1;
}
add_p(rplci, CAI, cai);
sig_req(rplci, S_SERVICE, 0);
send_req(rplci);
return false;
}
else
{
dbug(0, dprintf("Wrong line"));
Info = 0x3010; /* wrong state */
break;
}
break;
case S_CALL_DEFLECTION:
if (api_parse(&parms->info[1], (word)parms->length, "wbwss", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (!plci)
{
Info = _WRONG_IDENTIFIER;
break;
}
/* reuse unused screening indicator */
ss_parms[3].info[3] = (byte)GET_WORD(&(ss_parms[2].info[0]));
plci->command = 0;
plci->internal_command = CD_REQ_PEND;
appl->CDEnable = true;
cai[0] = 1;
cai[1] = CALL_DEFLECTION;
add_p(plci, CAI, cai);
add_p(plci, CPN, ss_parms[3].info);
sig_req(plci, S_SERVICE, 0);
send_req(plci);
return false;
break;
case S_CALL_FORWARDING_START:
if (api_parse(&parms->info[1], (word)parms->length, "wbdwwsss", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if ((i = get_plci(a)))
{
rplci = &a->plci[i - 1];
rplci->appl = appl;
add_p(rplci, CAI, "\x01\x80");
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
}
else
{
Info = _OUT_OF_PLCI;
break;
}
/* reuse unused screening indicator */
rplci->internal_command = CF_START_PEND;
rplci->appl = appl;
rplci->number = Number;
appl->S_Handle = GET_DWORD(&(ss_parms[2].info[0]));
cai[0] = 2;
cai[1] = 0x70 | (byte)GET_WORD(&(ss_parms[3].info[0])); /* Function */
cai[2] = (byte)GET_WORD(&(ss_parms[4].info[0])); /* Basic Service */
add_p(rplci, CAI, cai);
add_p(rplci, OAD, ss_parms[5].info);
add_p(rplci, CPN, ss_parms[6].info);
sig_req(rplci, S_SERVICE, 0);
send_req(rplci);
return false;
break;
case S_INTERROGATE_DIVERSION:
case S_INTERROGATE_NUMBERS:
case S_CALL_FORWARDING_STOP:
case S_CCBS_REQUEST:
case S_CCBS_DEACTIVATE:
case S_CCBS_INTERROGATE:
switch (SSreq)
{
case S_INTERROGATE_NUMBERS:
if (api_parse(&parms->info[1], (word)parms->length, "wbd", ss_parms))
{
dbug(0, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
}
break;
case S_CCBS_REQUEST:
case S_CCBS_DEACTIVATE:
if (api_parse(&parms->info[1], (word)parms->length, "wbdw", ss_parms))
{
dbug(0, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
}
break;
case S_CCBS_INTERROGATE:
if (api_parse(&parms->info[1], (word)parms->length, "wbdws", ss_parms))
{
dbug(0, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
}
break;
default:
if (api_parse(&parms->info[1], (word)parms->length, "wbdwws", ss_parms))
{
dbug(0, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
break;
}
if (Info) break;
if ((i = get_plci(a)))
{
rplci = &a->plci[i - 1];
switch (SSreq)
{
case S_INTERROGATE_DIVERSION: /* use cai with S_SERVICE below */
cai[1] = 0x60 | (byte)GET_WORD(&(ss_parms[3].info[0])); /* Function */
rplci->internal_command = INTERR_DIVERSION_REQ_PEND; /* move to rplci if assigned */
break;
case S_INTERROGATE_NUMBERS: /* use cai with S_SERVICE below */
cai[1] = DIVERSION_INTERROGATE_NUM; /* Function */
rplci->internal_command = INTERR_NUMBERS_REQ_PEND; /* move to rplci if assigned */
break;
case S_CALL_FORWARDING_STOP:
rplci->internal_command = CF_STOP_PEND;
cai[1] = 0x80 | (byte)GET_WORD(&(ss_parms[3].info[0])); /* Function */
break;
case S_CCBS_REQUEST:
cai[1] = CCBS_REQUEST;
rplci->internal_command = CCBS_REQUEST_REQ_PEND;
break;
case S_CCBS_DEACTIVATE:
cai[1] = CCBS_DEACTIVATE;
rplci->internal_command = CCBS_DEACTIVATE_REQ_PEND;
break;
case S_CCBS_INTERROGATE:
cai[1] = CCBS_INTERROGATE;
rplci->internal_command = CCBS_INTERROGATE_REQ_PEND;
break;
default:
cai[1] = 0;
break;
}
rplci->appl = appl;
rplci->number = Number;
add_p(rplci, CAI, "\x01\x80");
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
}
else
{
Info = _OUT_OF_PLCI;
break;
}
appl->S_Handle = GET_DWORD(&(ss_parms[2].info[0]));
switch (SSreq)
{
case S_INTERROGATE_NUMBERS:
cai[0] = 1;
add_p(rplci, CAI, cai);
break;
case S_CCBS_REQUEST:
case S_CCBS_DEACTIVATE:
cai[0] = 3;
PUT_WORD(&cai[2], GET_WORD(&(ss_parms[3].info[0])));
add_p(rplci, CAI, cai);
break;
case S_CCBS_INTERROGATE:
cai[0] = 3;
PUT_WORD(&cai[2], GET_WORD(&(ss_parms[3].info[0])));
add_p(rplci, CAI, cai);
add_p(rplci, OAD, ss_parms[4].info);
break;
default:
cai[0] = 2;
cai[2] = (byte)GET_WORD(&(ss_parms[4].info[0])); /* Basic Service */
add_p(rplci, CAI, cai);
add_p(rplci, OAD, ss_parms[5].info);
break;
}
sig_req(rplci, S_SERVICE, 0);
send_req(rplci);
return false;
break;
case S_MWI_ACTIVATE:
if (api_parse(&parms->info[1], (word)parms->length, "wbwdwwwssss", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (!plci)
{
if ((i = get_plci(a)))
{
rplci = &a->plci[i - 1];
rplci->appl = appl;
rplci->cr_enquiry = true;
add_p(rplci, CAI, "\x01\x80");
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
}
else
{
Info = _OUT_OF_PLCI;
break;
}
}
else
{
rplci = plci;
rplci->cr_enquiry = false;
}
rplci->command = 0;
rplci->internal_command = MWI_ACTIVATE_REQ_PEND;
rplci->appl = appl;
rplci->number = Number;
cai[0] = 13;
cai[1] = ACTIVATION_MWI; /* Function */
PUT_WORD(&cai[2], GET_WORD(&(ss_parms[2].info[0]))); /* Basic Service */
PUT_DWORD(&cai[4], GET_DWORD(&(ss_parms[3].info[0]))); /* Number of Messages */
PUT_WORD(&cai[8], GET_WORD(&(ss_parms[4].info[0]))); /* Message Status */
PUT_WORD(&cai[10], GET_WORD(&(ss_parms[5].info[0]))); /* Message Reference */
PUT_WORD(&cai[12], GET_WORD(&(ss_parms[6].info[0]))); /* Invocation Mode */
add_p(rplci, CAI, cai);
add_p(rplci, CPN, ss_parms[7].info); /* Receiving User Number */
add_p(rplci, OAD, ss_parms[8].info); /* Controlling User Number */
add_p(rplci, OSA, ss_parms[9].info); /* Controlling User Provided Number */
add_p(rplci, UID, ss_parms[10].info); /* Time */
sig_req(rplci, S_SERVICE, 0);
send_req(rplci);
return false;
case S_MWI_DEACTIVATE:
if (api_parse(&parms->info[1], (word)parms->length, "wbwwss", ss_parms))
{
dbug(1, dprintf("format wrong"));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (!plci)
{
if ((i = get_plci(a)))
{
rplci = &a->plci[i - 1];
rplci->appl = appl;
rplci->cr_enquiry = true;
add_p(rplci, CAI, "\x01\x80");
add_p(rplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(rplci, ASSIGN, DSIG_ID);
send_req(rplci);
}
else
{
Info = _OUT_OF_PLCI;
break;
}
}
else
{
rplci = plci;
rplci->cr_enquiry = false;
}
rplci->command = 0;
rplci->internal_command = MWI_DEACTIVATE_REQ_PEND;
rplci->appl = appl;
rplci->number = Number;
cai[0] = 5;
cai[1] = DEACTIVATION_MWI; /* Function */
PUT_WORD(&cai[2], GET_WORD(&(ss_parms[2].info[0]))); /* Basic Service */
PUT_WORD(&cai[4], GET_WORD(&(ss_parms[3].info[0]))); /* Invocation Mode */
add_p(rplci, CAI, cai);
add_p(rplci, CPN, ss_parms[4].info); /* Receiving User Number */
add_p(rplci, OAD, ss_parms[5].info); /* Controlling User Number */
sig_req(rplci, S_SERVICE, 0);
send_req(rplci);
return false;
default:
Info = 0x300E; /* not supported */
break;
}
break; /* case SELECTOR_SU_SERV: end */
case SELECTOR_DTMF:
return (dtmf_request(Id, Number, a, plci, appl, msg));
case SELECTOR_LINE_INTERCONNECT:
return (mixer_request(Id, Number, a, plci, appl, msg));
case PRIV_SELECTOR_ECHO_CANCELLER:
appl->appl_flags |= APPL_FLAG_PRIV_EC_SPEC;
return (ec_request(Id, Number, a, plci, appl, msg));
case SELECTOR_ECHO_CANCELLER:
appl->appl_flags &= ~APPL_FLAG_PRIV_EC_SPEC;
return (ec_request(Id, Number, a, plci, appl, msg));
case SELECTOR_V42BIS:
default:
Info = _FACILITY_NOT_SUPPORTED;
break;
} /* end of switch (selector) */
}
dbug(1, dprintf("SendFacRc"));
sendf(appl,
_FACILITY_R | CONFIRM,
Id,
Number,
"wws", Info, selector, SSparms);
return false;
}
static byte facility_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
dbug(1, dprintf("facility_res"));
return false;
}
static byte connect_b3_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word Info = 0;
byte req;
byte len;
word w;
word fax_control_bits, fax_feature_bits, fax_info_change;
API_PARSE *ncpi;
byte pvc[2];
API_PARSE fax_parms[9];
word i;
dbug(1, dprintf("connect_b3_req"));
if (plci)
{
if ((plci->State == IDLE) || (plci->State == OUTG_DIS_PENDING)
|| (plci->State == INC_DIS_PENDING) || (plci->SuppState != IDLE))
{
Info = _WRONG_STATE;
}
else
{
/* local reply if assign unsuccessful
or B3 protocol allows only one layer 3 connection
and already connected
or B2 protocol not any LAPD
and connect_b3_req contradicts originate/answer direction */
if (!plci->NL.Id
|| (((plci->B3_prot != B3_T90NL) && (plci->B3_prot != B3_ISO8208) && (plci->B3_prot != B3_X25_DCE))
&& ((plci->channels != 0)
|| (((plci->B2_prot != B2_SDLC) && (plci->B2_prot != B2_LAPD) && (plci->B2_prot != B2_LAPD_FREE_SAPI_SEL))
&& ((plci->call_dir & CALL_DIR_ANSWER) && !(plci->call_dir & CALL_DIR_FORCE_OUTG_NL))))))
{
dbug(1, dprintf("B3 already connected=%d or no NL.Id=0x%x, dir=%d sstate=0x%x",
plci->channels, plci->NL.Id, plci->call_dir, plci->SuppState));
Info = _WRONG_STATE;
sendf(appl,
_CONNECT_B3_R | CONFIRM,
Id,
Number,
"w", Info);
return false;
}
plci->requested_options_conn = 0;
req = N_CONNECT;
ncpi = &parms[0];
if (plci->B3_prot == 2 || plci->B3_prot == 3)
{
if (ncpi->length > 2)
{
/* check for PVC */
if (ncpi->info[2] || ncpi->info[3])
{
pvc[0] = ncpi->info[3];
pvc[1] = ncpi->info[2];
add_d(plci, 2, pvc);
req = N_RESET;
}
else
{
if (ncpi->info[1] & 1) req = N_CONNECT | N_D_BIT;
add_d(plci, (word)(ncpi->length - 3), &ncpi->info[4]);
}
}
}
else if (plci->B3_prot == 5)
{
if (plci->NL.Id && !plci->nl_remove_id)
{
fax_control_bits = GET_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->control_bits_low);
fax_feature_bits = GET_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->feature_bits_low);
if (!(fax_control_bits & T30_CONTROL_BIT_MORE_DOCUMENTS)
|| (fax_feature_bits & T30_FEATURE_BIT_MORE_DOCUMENTS))
{
len = offsetof(T30_INFO, universal_6);
fax_info_change = false;
if (ncpi->length >= 4)
{
w = GET_WORD(&ncpi->info[3]);
if ((w & 0x0001) != ((word)(((T30_INFO *)(plci->fax_connect_info_buffer))->resolution & 0x0001)))
{
((T30_INFO *)(plci->fax_connect_info_buffer))->resolution =
(byte)((((T30_INFO *)(plci->fax_connect_info_buffer))->resolution & ~T30_RESOLUTION_R8_0770_OR_200) |
((w & 0x0001) ? T30_RESOLUTION_R8_0770_OR_200 : 0));
fax_info_change = true;
}
fax_control_bits &= ~(T30_CONTROL_BIT_REQUEST_POLLING | T30_CONTROL_BIT_MORE_DOCUMENTS);
if (w & 0x0002) /* Fax-polling request */
fax_control_bits |= T30_CONTROL_BIT_REQUEST_POLLING;
if ((w & 0x0004) /* Request to send / poll another document */
&& (a->manufacturer_features & MANUFACTURER_FEATURE_FAX_MORE_DOCUMENTS))
{
fax_control_bits |= T30_CONTROL_BIT_MORE_DOCUMENTS;
}
if (ncpi->length >= 6)
{
w = GET_WORD(&ncpi->info[5]);
if (((byte) w) != ((T30_INFO *)(plci->fax_connect_info_buffer))->data_format)
{
((T30_INFO *)(plci->fax_connect_info_buffer))->data_format = (byte) w;
fax_info_change = true;
}
if ((a->man_profile.private_options & (1L << PRIVATE_FAX_SUB_SEP_PWD))
&& (GET_WORD(&ncpi->info[5]) & 0x8000)) /* Private SEP/SUB/PWD enable */
{
plci->requested_options_conn |= (1L << PRIVATE_FAX_SUB_SEP_PWD);
}
if ((a->man_profile.private_options & (1L << PRIVATE_FAX_NONSTANDARD))
&& (GET_WORD(&ncpi->info[5]) & 0x4000)) /* Private non-standard facilities enable */
{
plci->requested_options_conn |= (1L << PRIVATE_FAX_NONSTANDARD);
}
fax_control_bits &= ~(T30_CONTROL_BIT_ACCEPT_SUBADDRESS | T30_CONTROL_BIT_ACCEPT_SEL_POLLING |
T30_CONTROL_BIT_ACCEPT_PASSWORD);
if ((plci->requested_options_conn | plci->requested_options | a->requested_options_table[appl->Id - 1])
& ((1L << PRIVATE_FAX_SUB_SEP_PWD) | (1L << PRIVATE_FAX_NONSTANDARD)))
{
if (api_parse(&ncpi->info[1], ncpi->length, "wwwwsss", fax_parms))
Info = _WRONG_MESSAGE_FORMAT;
else
{
if ((plci->requested_options_conn | plci->requested_options | a->requested_options_table[appl->Id - 1])
& (1L << PRIVATE_FAX_SUB_SEP_PWD))
{
fax_control_bits |= T30_CONTROL_BIT_ACCEPT_SUBADDRESS | T30_CONTROL_BIT_ACCEPT_PASSWORD;
if (fax_control_bits & T30_CONTROL_BIT_ACCEPT_POLLING)
fax_control_bits |= T30_CONTROL_BIT_ACCEPT_SEL_POLLING;
}
w = fax_parms[4].length;
if (w > 20)
w = 20;
((T30_INFO *)(plci->fax_connect_info_buffer))->station_id_len = (byte) w;
for (i = 0; i < w; i++)
((T30_INFO *)(plci->fax_connect_info_buffer))->station_id[i] = fax_parms[4].info[1 + i];
((T30_INFO *)(plci->fax_connect_info_buffer))->head_line_len = 0;
len = offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH;
w = fax_parms[5].length;
if (w > 20)
w = 20;
plci->fax_connect_info_buffer[len++] = (byte) w;
for (i = 0; i < w; i++)
plci->fax_connect_info_buffer[len++] = fax_parms[5].info[1 + i];
w = fax_parms[6].length;
if (w > 20)
w = 20;
plci->fax_connect_info_buffer[len++] = (byte) w;
for (i = 0; i < w; i++)
plci->fax_connect_info_buffer[len++] = fax_parms[6].info[1 + i];
if ((plci->requested_options_conn | plci->requested_options | a->requested_options_table[appl->Id - 1])
& (1L << PRIVATE_FAX_NONSTANDARD))
{
if (api_parse(&ncpi->info[1], ncpi->length, "wwwwssss", fax_parms))
{
dbug(1, dprintf("non-standard facilities info missing or wrong format"));
plci->fax_connect_info_buffer[len++] = 0;
}
else
{
if ((fax_parms[7].length >= 3) && (fax_parms[7].info[1] >= 2))
plci->nsf_control_bits = GET_WORD(&fax_parms[7].info[2]);
plci->fax_connect_info_buffer[len++] = (byte)(fax_parms[7].length);
for (i = 0; i < fax_parms[7].length; i++)
plci->fax_connect_info_buffer[len++] = fax_parms[7].info[1 + i];
}
}
}
}
else
{
len = offsetof(T30_INFO, universal_6);
}
fax_info_change = true;
}
if (fax_control_bits != GET_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->control_bits_low))
{
PUT_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->control_bits_low, fax_control_bits);
fax_info_change = true;
}
}
if (Info == GOOD)
{
plci->fax_connect_info_length = len;
if (fax_info_change)
{
if (fax_feature_bits & T30_FEATURE_BIT_MORE_DOCUMENTS)
{
start_internal_command(Id, plci, fax_connect_info_command);
return false;
}
else
{
start_internal_command(Id, plci, fax_adjust_b23_command);
return false;
}
}
}
}
else Info = _WRONG_STATE;
}
else Info = _WRONG_STATE;
}
else if (plci->B3_prot == B3_RTP)
{
plci->internal_req_buffer[0] = ncpi->length + 1;
plci->internal_req_buffer[1] = UDATA_REQUEST_RTP_RECONFIGURE;
for (w = 0; w < ncpi->length; w++)
plci->internal_req_buffer[2 + w] = ncpi->info[1 + w];
start_internal_command(Id, plci, rtp_connect_b3_req_command);
return false;
}
if (!Info)
{
nl_req_ncci(plci, req, 0);
return 1;
}
}
}
else Info = _WRONG_IDENTIFIER;
sendf(appl,
_CONNECT_B3_R | CONFIRM,
Id,
Number,
"w", Info);
return false;
}
static byte connect_b3_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word ncci;
API_PARSE *ncpi;
byte req;
word w;
API_PARSE fax_parms[9];
word i;
byte len;
dbug(1, dprintf("connect_b3_res"));
ncci = (word)(Id >> 16);
if (plci && ncci) {
if (a->ncci_state[ncci] == INC_CON_PENDING) {
if (GET_WORD(&parms[0].info[0]) != 0)
{
a->ncci_state[ncci] = OUTG_REJ_PENDING;
channel_request_xon(plci, a->ncci_ch[ncci]);
channel_xmit_xon(plci);
cleanup_ncci_data(plci, ncci);
nl_req_ncci(plci, N_DISC, (byte)ncci);
return 1;
}
a->ncci_state[ncci] = INC_ACT_PENDING;
req = N_CONNECT_ACK;
ncpi = &parms[1];
if ((plci->B3_prot == 4) || (plci->B3_prot == 5) || (plci->B3_prot == 7))
{
if ((plci->requested_options_conn | plci->requested_options | a->requested_options_table[plci->appl->Id - 1])
& (1L << PRIVATE_FAX_NONSTANDARD))
{
if (((plci->B3_prot == 4) || (plci->B3_prot == 5))
&& (plci->nsf_control_bits & T30_NSF_CONTROL_BIT_ENABLE_NSF)
&& (plci->nsf_control_bits & T30_NSF_CONTROL_BIT_NEGOTIATE_RESP))
{
len = offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH;
if (plci->fax_connect_info_length < len)
{
((T30_INFO *)(plci->fax_connect_info_buffer))->station_id_len = 0;
((T30_INFO *)(plci->fax_connect_info_buffer))->head_line_len = 0;
}
if (api_parse(&ncpi->info[1], ncpi->length, "wwwwssss", fax_parms))
{
dbug(1, dprintf("non-standard facilities info missing or wrong format"));
}
else
{
if (plci->fax_connect_info_length <= len)
plci->fax_connect_info_buffer[len] = 0;
len += 1 + plci->fax_connect_info_buffer[len];
if (plci->fax_connect_info_length <= len)
plci->fax_connect_info_buffer[len] = 0;
len += 1 + plci->fax_connect_info_buffer[len];
if ((fax_parms[7].length >= 3) && (fax_parms[7].info[1] >= 2))
plci->nsf_control_bits = GET_WORD(&fax_parms[7].info[2]);
plci->fax_connect_info_buffer[len++] = (byte)(fax_parms[7].length);
for (i = 0; i < fax_parms[7].length; i++)
plci->fax_connect_info_buffer[len++] = fax_parms[7].info[1 + i];
}
plci->fax_connect_info_length = len;
((T30_INFO *)(plci->fax_connect_info_buffer))->code = 0;
start_internal_command(Id, plci, fax_connect_ack_command);
return false;
}
}
nl_req_ncci(plci, req, (byte)ncci);
if ((plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
if (plci->B3_prot == 4)
sendf(appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
else
sendf(appl, _CONNECT_B3_ACTIVE_I, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
}
else if (plci->B3_prot == B3_RTP)
{
plci->internal_req_buffer[0] = ncpi->length + 1;
plci->internal_req_buffer[1] = UDATA_REQUEST_RTP_RECONFIGURE;
for (w = 0; w < ncpi->length; w++)
plci->internal_req_buffer[2 + w] = ncpi->info[1+w];
start_internal_command(Id, plci, rtp_connect_b3_res_command);
return false;
}
else
{
if (ncpi->length > 2) {
if (ncpi->info[1] & 1) req = N_CONNECT_ACK | N_D_BIT;
add_d(plci, (word)(ncpi->length - 3), &ncpi->info[4]);
}
nl_req_ncci(plci, req, (byte)ncci);
sendf(appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
if (plci->adjust_b_restore)
{
plci->adjust_b_restore = false;
start_internal_command(Id, plci, adjust_b_restore);
}
}
return 1;
}
}
return false;
}
static byte connect_b3_a_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word ncci;
ncci = (word)(Id >> 16);
dbug(1, dprintf("connect_b3_a_res(ncci=0x%x)", ncci));
if (plci && ncci && (plci->State != IDLE) && (plci->State != INC_DIS_PENDING)
&& (plci->State != OUTG_DIS_PENDING))
{
if (a->ncci_state[ncci] == INC_ACT_PENDING) {
a->ncci_state[ncci] = CONNECTED;
if (plci->State != INC_CON_CONNECTED_ALERT) plci->State = CONNECTED;
channel_request_xon(plci, a->ncci_ch[ncci]);
channel_xmit_xon(plci);
}
}
return false;
}
static byte disconnect_b3_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word Info;
word ncci;
API_PARSE *ncpi;
dbug(1, dprintf("disconnect_b3_req"));
Info = _WRONG_IDENTIFIER;
ncci = (word)(Id >> 16);
if (plci && ncci)
{
Info = _WRONG_STATE;
if ((a->ncci_state[ncci] == CONNECTED)
|| (a->ncci_state[ncci] == OUTG_CON_PENDING)
|| (a->ncci_state[ncci] == INC_CON_PENDING)
|| (a->ncci_state[ncci] == INC_ACT_PENDING))
{
a->ncci_state[ncci] = OUTG_DIS_PENDING;
channel_request_xon(plci, a->ncci_ch[ncci]);
channel_xmit_xon(plci);
if (a->ncci[ncci].data_pending
&& ((plci->B3_prot == B3_TRANSPARENT)
|| (plci->B3_prot == B3_T30)
|| (plci->B3_prot == B3_T30_WITH_EXTENSIONS)))
{
plci->send_disc = (byte)ncci;
plci->command = 0;
return false;
}
else
{
cleanup_ncci_data(plci, ncci);
if (plci->B3_prot == 2 || plci->B3_prot == 3)
{
ncpi = &parms[0];
if (ncpi->length > 3)
{
add_d(plci, (word)(ncpi->length - 3), (byte *)&(ncpi->info[4]));
}
}
nl_req_ncci(plci, N_DISC, (byte)ncci);
}
return 1;
}
}
sendf(appl,
_DISCONNECT_B3_R | CONFIRM,
Id,
Number,
"w", Info);
return false;
}
static byte disconnect_b3_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word ncci;
word i;
ncci = (word)(Id >> 16);
dbug(1, dprintf("disconnect_b3_res(ncci=0x%x", ncci));
if (plci && ncci) {
plci->requested_options_conn = 0;
plci->fax_connect_info_length = 0;
plci->ncpi_state = 0x00;
if (((plci->B3_prot != B3_T90NL) && (plci->B3_prot != B3_ISO8208) && (plci->B3_prot != B3_X25_DCE))
&& ((plci->B2_prot != B2_LAPD) && (plci->B2_prot != B2_LAPD_FREE_SAPI_SEL)))
{
plci->call_dir |= CALL_DIR_FORCE_OUTG_NL;
}
for (i = 0; i < MAX_CHANNELS_PER_PLCI && plci->inc_dis_ncci_table[i] != (byte)ncci; i++);
if (i < MAX_CHANNELS_PER_PLCI) {
if (plci->channels)plci->channels--;
for (; i < MAX_CHANNELS_PER_PLCI - 1; i++) plci->inc_dis_ncci_table[i] = plci->inc_dis_ncci_table[i + 1];
plci->inc_dis_ncci_table[MAX_CHANNELS_PER_PLCI - 1] = 0;
ncci_free_receive_buffers(plci, ncci);
if ((plci->State == IDLE || plci->State == SUSPENDING) && !plci->channels) {
if (plci->State == SUSPENDING) {
sendf(plci->appl,
_FACILITY_I,
Id & 0xffffL,
0,
"ws", (word)3, "\x03\x04\x00\x00");
sendf(plci->appl, _DISCONNECT_I, Id & 0xffffL, 0, "w", 0);
}
plci_remove(plci);
plci->State = IDLE;
}
}
else
{
if ((a->manufacturer_features & MANUFACTURER_FEATURE_FAX_PAPER_FORMATS)
&& ((plci->B3_prot == 4) || (plci->B3_prot == 5))
&& (a->ncci_state[ncci] == INC_DIS_PENDING))
{
ncci_free_receive_buffers(plci, ncci);
nl_req_ncci(plci, N_EDATA, (byte)ncci);
plci->adapter->ncci_state[ncci] = IDLE;
start_internal_command(Id, plci, fax_disconnect_command);
return 1;
}
}
}
return false;
}
static byte data_b3_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
NCCI *ncci_ptr;
DATA_B3_DESC *data;
word Info;
word ncci;
word i;
dbug(1, dprintf("data_b3_req"));
Info = _WRONG_IDENTIFIER;
ncci = (word)(Id >> 16);
dbug(1, dprintf("ncci=0x%x, plci=0x%x", ncci, plci));
if (plci && ncci)
{
Info = _WRONG_STATE;
if ((a->ncci_state[ncci] == CONNECTED)
|| (a->ncci_state[ncci] == INC_ACT_PENDING))
{
/* queue data */
ncci_ptr = &(a->ncci[ncci]);
i = ncci_ptr->data_out + ncci_ptr->data_pending;
if (i >= MAX_DATA_B3)
i -= MAX_DATA_B3;
data = &(ncci_ptr->DBuffer[i]);
data->Number = Number;
if ((((byte *)(parms[0].info)) >= ((byte *)(plci->msg_in_queue)))
&& (((byte *)(parms[0].info)) < ((byte *)(plci->msg_in_queue)) + sizeof(plci->msg_in_queue)))
{
data->P = (byte *)(long)(*((dword *)(parms[0].info)));
}
else
data->P = TransmitBufferSet(appl, *(dword *)parms[0].info);
data->Length = GET_WORD(parms[1].info);
data->Handle = GET_WORD(parms[2].info);
data->Flags = GET_WORD(parms[3].info);
(ncci_ptr->data_pending)++;
/* check for delivery confirmation */
if (data->Flags & 0x0004)
{
i = ncci_ptr->data_ack_out + ncci_ptr->data_ack_pending;
if (i >= MAX_DATA_ACK)
i -= MAX_DATA_ACK;
ncci_ptr->DataAck[i].Number = data->Number;
ncci_ptr->DataAck[i].Handle = data->Handle;
(ncci_ptr->data_ack_pending)++;
}
send_data(plci);
return false;
}
}
if (appl)
{
if (plci)
{
if ((((byte *)(parms[0].info)) >= ((byte *)(plci->msg_in_queue)))
&& (((byte *)(parms[0].info)) < ((byte *)(plci->msg_in_queue)) + sizeof(plci->msg_in_queue)))
{
TransmitBufferFree(appl, (byte *)(long)(*((dword *)(parms[0].info))));
}
}
sendf(appl,
_DATA_B3_R | CONFIRM,
Id,
Number,
"ww", GET_WORD(parms[2].info), Info);
}
return false;
}
static byte data_b3_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word n;
word ncci;
word NCCIcode;
dbug(1, dprintf("data_b3_res"));
ncci = (word)(Id >> 16);
if (plci && ncci) {
n = GET_WORD(parms[0].info);
dbug(1, dprintf("free(%d)", n));
NCCIcode = ncci | (((word) a->Id) << 8);
if (n < appl->MaxBuffer &&
appl->DataNCCI[n] == NCCIcode &&
(byte)(appl->DataFlags[n] >> 8) == plci->Id) {
dbug(1, dprintf("found"));
appl->DataNCCI[n] = 0;
if (channel_can_xon(plci, a->ncci_ch[ncci])) {
channel_request_xon(plci, a->ncci_ch[ncci]);
}
channel_xmit_xon(plci);
if (appl->DataFlags[n] & 4) {
nl_req_ncci(plci, N_DATA_ACK, (byte)ncci);
return 1;
}
}
}
return false;
}
static byte reset_b3_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word Info;
word ncci;
dbug(1, dprintf("reset_b3_req"));
Info = _WRONG_IDENTIFIER;
ncci = (word)(Id >> 16);
if (plci && ncci)
{
Info = _WRONG_STATE;
switch (plci->B3_prot)
{
case B3_ISO8208:
case B3_X25_DCE:
if (a->ncci_state[ncci] == CONNECTED)
{
nl_req_ncci(plci, N_RESET, (byte)ncci);
send_req(plci);
Info = GOOD;
}
break;
case B3_TRANSPARENT:
if (a->ncci_state[ncci] == CONNECTED)
{
start_internal_command(Id, plci, reset_b3_command);
Info = GOOD;
}
break;
}
}
/* reset_b3 must result in a reset_b3_con & reset_b3_Ind */
sendf(appl,
_RESET_B3_R | CONFIRM,
Id,
Number,
"w", Info);
return false;
}
static byte reset_b3_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word ncci;
dbug(1, dprintf("reset_b3_res"));
ncci = (word)(Id >> 16);
if (plci && ncci) {
switch (plci->B3_prot)
{
case B3_ISO8208:
case B3_X25_DCE:
if (a->ncci_state[ncci] == INC_RES_PENDING)
{
a->ncci_state[ncci] = CONNECTED;
nl_req_ncci(plci, N_RESET_ACK, (byte)ncci);
return true;
}
break;
}
}
return false;
}
static byte connect_b3_t90_a_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word ncci;
API_PARSE *ncpi;
byte req;
dbug(1, dprintf("connect_b3_t90_a_res"));
ncci = (word)(Id >> 16);
if (plci && ncci) {
if (a->ncci_state[ncci] == INC_ACT_PENDING) {
a->ncci_state[ncci] = CONNECTED;
}
else if (a->ncci_state[ncci] == INC_CON_PENDING) {
a->ncci_state[ncci] = CONNECTED;
req = N_CONNECT_ACK;
/* parms[0]==0 for CAPI original message definition! */
if (parms[0].info) {
ncpi = &parms[1];
if (ncpi->length > 2) {
if (ncpi->info[1] & 1) req = N_CONNECT_ACK | N_D_BIT;
add_d(plci, (word)(ncpi->length - 3), &ncpi->info[4]);
}
}
nl_req_ncci(plci, req, (byte)ncci);
return 1;
}
}
return false;
}
static byte select_b_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info = 0;
word i;
byte tel;
API_PARSE bp_parms[7];
if (!plci || !msg)
{
Info = _WRONG_IDENTIFIER;
}
else
{
dbug(1, dprintf("select_b_req[%d],PLCI=0x%x,Tel=0x%x,NL=0x%x,appl=0x%x,sstate=0x%x",
msg->length, plci->Id, plci->tel, plci->NL.Id, plci->appl, plci->SuppState));
dbug(1, dprintf("PlciState=0x%x", plci->State));
for (i = 0; i < 7; i++) bp_parms[i].length = 0;
/* check if no channel is open, no B3 connected only */
if ((plci->State == IDLE) || (plci->State == OUTG_DIS_PENDING) || (plci->State == INC_DIS_PENDING)
|| (plci->SuppState != IDLE) || plci->channels || plci->nl_remove_id)
{
Info = _WRONG_STATE;
}
/* check message format and fill bp_parms pointer */
else if (msg->length && api_parse(&msg->info[1], (word)msg->length, "wwwsss", bp_parms))
{
Info = _WRONG_MESSAGE_FORMAT;
}
else
{
if ((plci->State == INC_CON_PENDING) || (plci->State == INC_CON_ALERT)) /* send alert tone inband to the network, */
{ /* e.g. Qsig or RBS or Cornet-N or xess PRI */
if (Id & EXT_CONTROLLER)
{
sendf(appl, _SELECT_B_REQ | CONFIRM, Id, Number, "w", 0x2002); /* wrong controller */
return 0;
}
plci->State = INC_CON_CONNECTED_ALERT;
plci->appl = appl;
clear_c_ind_mask_bit(plci, (word)(appl->Id - 1));
dump_c_ind_mask(plci);
for (i = 0; i < max_appl; i++) /* disconnect the other appls */
{ /* its quasi a connect */
if (test_c_ind_mask_bit(plci, i))
sendf(&application[i], _DISCONNECT_I, Id, 0, "w", _OTHER_APPL_CONNECTED);
}
}
api_save_msg(msg, "s", &plci->saved_msg);
tel = plci->tel;
if (Id & EXT_CONTROLLER)
{
if (tel) /* external controller in use by this PLCI */
{
if (a->AdvSignalAppl && a->AdvSignalAppl != appl)
{
dbug(1, dprintf("Ext_Ctrl in use 1"));
Info = _WRONG_STATE;
}
}
else /* external controller NOT in use by this PLCI ? */
{
if (a->AdvSignalPLCI)
{
dbug(1, dprintf("Ext_Ctrl in use 2"));
Info = _WRONG_STATE;
}
else /* activate the codec */
{
dbug(1, dprintf("Ext_Ctrl start"));
if (AdvCodecSupport(a, plci, appl, 0))
{
dbug(1, dprintf("Error in codec procedures"));
Info = _WRONG_STATE;
}
else if (plci->spoofed_msg == SPOOFING_REQUIRED) /* wait until codec is active */
{
plci->spoofed_msg = AWAITING_SELECT_B;
plci->internal_command = BLOCK_PLCI; /* lock other commands */
plci->command = 0;
dbug(1, dprintf("continue if codec loaded"));
return false;
}
}
}
}
else /* external controller bit is OFF */
{
if (tel) /* external controller in use, need to switch off */
{
if (a->AdvSignalAppl == appl)
{
CodecIdCheck(a, plci);
plci->tel = 0;
plci->adv_nl = 0;
dbug(1, dprintf("Ext_Ctrl disable"));
}
else
{
dbug(1, dprintf("Ext_Ctrl not requested"));
}
}
}
if (!Info)
{
if (plci->call_dir & CALL_DIR_OUT)
plci->call_dir = CALL_DIR_OUT | CALL_DIR_ORIGINATE;
else if (plci->call_dir & CALL_DIR_IN)
plci->call_dir = CALL_DIR_IN | CALL_DIR_ANSWER;
start_internal_command(Id, plci, select_b_command);
return false;
}
}
}
sendf(appl, _SELECT_B_REQ | CONFIRM, Id, Number, "w", Info);
return false;
}
static byte manufacturer_req(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *parms)
{
word command;
word i;
word ncci;
API_PARSE *m;
API_PARSE m_parms[5];
word codec;
byte req;
byte ch;
byte dir;
static byte chi[2] = {0x01, 0x00};
static byte lli[2] = {0x01, 0x00};
static byte codec_cai[2] = {0x01, 0x01};
static byte null_msg = {0};
static API_PARSE null_parms = { 0, &null_msg };
PLCI *v_plci;
word Info = 0;
dbug(1, dprintf("manufacturer_req"));
for (i = 0; i < 5; i++) m_parms[i].length = 0;
if (GET_DWORD(parms[0].info) != _DI_MANU_ID) {
Info = _WRONG_MESSAGE_FORMAT;
}
command = GET_WORD(parms[1].info);
m = &parms[2];
if (!Info)
{
switch (command) {
case _DI_ASSIGN_PLCI:
if (api_parse(&m->info[1], (word)m->length, "wbbs", m_parms)) {
Info = _WRONG_MESSAGE_FORMAT;
break;
}
codec = GET_WORD(m_parms[0].info);
ch = m_parms[1].info[0];
dir = m_parms[2].info[0];
if ((i = get_plci(a))) {
plci = &a->plci[i - 1];
plci->appl = appl;
plci->command = _MANUFACTURER_R;
plci->m_command = command;
plci->number = Number;
plci->State = LOCAL_CONNECT;
Id = (((word)plci->Id << 8) | plci->adapter->Id | 0x80);
dbug(1, dprintf("ManCMD,plci=0x%x", Id));
if ((ch == 1 || ch == 2) && (dir <= 2)) {
chi[1] = (byte)(0x80 | ch);
lli[1] = 0;
plci->call_dir = CALL_DIR_OUT | CALL_DIR_ORIGINATE;
switch (codec)
{
case 0:
Info = add_b1(plci, &m_parms[3], 0, 0);
break;
case 1:
add_p(plci, CAI, codec_cai);
break;
/* manual 'swich on' to the codec support without signalling */
/* first 'assign plci' with this function, then use */
case 2:
if (AdvCodecSupport(a, plci, appl, 0)) {
Info = _RESOURCE_ERROR;
}
else {
Info = add_b1(plci, &null_parms, 0, B1_FACILITY_LOCAL);
lli[1] = 0x10; /* local call codec stream */
}
break;
}
plci->State = LOCAL_CONNECT;
plci->manufacturer = true;
plci->command = _MANUFACTURER_R;
plci->m_command = command;
plci->number = Number;
if (!Info)
{
add_p(plci, LLI, lli);
add_p(plci, CHI, chi);
add_p(plci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(plci, ASSIGN, DSIG_ID);
if (!codec)
{
Info = add_b23(plci, &m_parms[3]);
if (!Info)
{
nl_req_ncci(plci, ASSIGN, 0);
send_req(plci);
}
}
if (!Info)
{
dbug(1, dprintf("dir=0x%x,spoof=0x%x", dir, plci->spoofed_msg));
if (plci->spoofed_msg == SPOOFING_REQUIRED)
{
api_save_msg(m_parms, "wbbs", &plci->saved_msg);
plci->spoofed_msg = AWAITING_MANUF_CON;
plci->internal_command = BLOCK_PLCI; /* reject other req meanwhile */
plci->command = 0;
send_req(plci);
return false;
}
if (dir == 1) {
sig_req(plci, CALL_REQ, 0);
}
else if (!dir) {
sig_req(plci, LISTEN_REQ, 0);
}
send_req(plci);
}
else
{
sendf(appl,
_MANUFACTURER_R | CONFIRM,
Id,
Number,
"dww", _DI_MANU_ID, command, Info);
return 2;
}
}
}
}
else Info = _OUT_OF_PLCI;
break;
case _DI_IDI_CTRL:
if (!plci)
{
Info = _WRONG_IDENTIFIER;
break;
}
if (api_parse(&m->info[1], (word)m->length, "bs", m_parms)) {
Info = _WRONG_MESSAGE_FORMAT;
break;
}
req = m_parms[0].info[0];
plci->command = _MANUFACTURER_R;
plci->m_command = command;
plci->number = Number;
if (req == CALL_REQ)
{
plci->b_channel = getChannel(&m_parms[1]);
mixer_set_bchannel_id_esc(plci, plci->b_channel);
if (plci->spoofed_msg == SPOOFING_REQUIRED)
{
plci->spoofed_msg = CALL_REQ | AWAITING_MANUF_CON;
plci->internal_command = BLOCK_PLCI; /* reject other req meanwhile */
plci->command = 0;
break;
}
}
else if (req == LAW_REQ)
{
plci->cr_enquiry = true;
}
add_ss(plci, FTY, &m_parms[1]);
sig_req(plci, req, 0);
send_req(plci);
if (req == HANGUP)
{
if (plci->NL.Id && !plci->nl_remove_id)
{
if (plci->channels)
{
for (ncci = 1; ncci < MAX_NCCI + 1; ncci++)
{
if ((a->ncci_plci[ncci] == plci->Id) && (a->ncci_state[ncci] == CONNECTED))
{
a->ncci_state[ncci] = OUTG_DIS_PENDING;
cleanup_ncci_data(plci, ncci);
nl_req_ncci(plci, N_DISC, (byte)ncci);
}
}
}
mixer_remove(plci);
nl_req_ncci(plci, REMOVE, 0);
send_req(plci);
}
}
break;
case _DI_SIG_CTRL:
/* signalling control for loop activation B-channel */
if (!plci)
{
Info = _WRONG_IDENTIFIER;
break;
}
if (m->length) {
plci->command = _MANUFACTURER_R;
plci->number = Number;
add_ss(plci, FTY, m);
sig_req(plci, SIG_CTRL, 0);
send_req(plci);
}
else Info = _WRONG_MESSAGE_FORMAT;
break;
case _DI_RXT_CTRL:
/* activation control for receiver/transmitter B-channel */
if (!plci)
{
Info = _WRONG_IDENTIFIER;
break;
}
if (m->length) {
plci->command = _MANUFACTURER_R;
plci->number = Number;
add_ss(plci, FTY, m);
sig_req(plci, DSP_CTRL, 0);
send_req(plci);
}
else Info = _WRONG_MESSAGE_FORMAT;
break;
case _DI_ADV_CODEC:
case _DI_DSP_CTRL:
/* TEL_CTRL commands to support non standard adjustments: */
/* Ring on/off, Handset micro volume, external micro vol. */
/* handset+external speaker volume, receiver+transm. gain,*/
/* handsfree on (hookinfo off), set mixer command */
if (command == _DI_ADV_CODEC)
{
if (!a->AdvCodecPLCI) {
Info = _WRONG_STATE;
break;
}
v_plci = a->AdvCodecPLCI;
}
else
{
if (plci
&& (m->length >= 3)
&& (m->info[1] == 0x1c)
&& (m->info[2] >= 1))
{
if (m->info[3] == DSP_CTRL_OLD_SET_MIXER_COEFFICIENTS)
{
if ((plci->tel != ADV_VOICE) || (plci != a->AdvSignalPLCI))
{
Info = _WRONG_STATE;
break;
}
a->adv_voice_coef_length = m->info[2] - 1;
if (a->adv_voice_coef_length > m->length - 3)
a->adv_voice_coef_length = (byte)(m->length - 3);
if (a->adv_voice_coef_length > ADV_VOICE_COEF_BUFFER_SIZE)
a->adv_voice_coef_length = ADV_VOICE_COEF_BUFFER_SIZE;
for (i = 0; i < a->adv_voice_coef_length; i++)
a->adv_voice_coef_buffer[i] = m->info[4 + i];
if (plci->B1_facilities & B1_FACILITY_VOICE)
adv_voice_write_coefs(plci, ADV_VOICE_WRITE_UPDATE);
break;
}
else if (m->info[3] == DSP_CTRL_SET_DTMF_PARAMETERS)
{
if (!(a->manufacturer_features & MANUFACTURER_FEATURE_DTMF_PARAMETERS))
{
Info = _FACILITY_NOT_SUPPORTED;
break;
}
plci->dtmf_parameter_length = m->info[2] - 1;
if (plci->dtmf_parameter_length > m->length - 3)
plci->dtmf_parameter_length = (byte)(m->length - 3);
if (plci->dtmf_parameter_length > DTMF_PARAMETER_BUFFER_SIZE)
plci->dtmf_parameter_length = DTMF_PARAMETER_BUFFER_SIZE;
for (i = 0; i < plci->dtmf_parameter_length; i++)
plci->dtmf_parameter_buffer[i] = m->info[4 + i];
if (plci->B1_facilities & B1_FACILITY_DTMFR)
dtmf_parameter_write(plci);
break;
}
}
v_plci = plci;
}
if (!v_plci)
{
Info = _WRONG_IDENTIFIER;
break;
}
if (m->length) {
add_ss(v_plci, FTY, m);
sig_req(v_plci, TEL_CTRL, 0);
send_req(v_plci);
}
else Info = _WRONG_MESSAGE_FORMAT;
break;
case _DI_OPTIONS_REQUEST:
if (api_parse(&m->info[1], (word)m->length, "d", m_parms)) {
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (GET_DWORD(m_parms[0].info) & ~a->man_profile.private_options)
{
Info = _FACILITY_NOT_SUPPORTED;
break;
}
a->requested_options_table[appl->Id - 1] = GET_DWORD(m_parms[0].info);
break;
default:
Info = _WRONG_MESSAGE_FORMAT;
break;
}
}
sendf(appl,
_MANUFACTURER_R | CONFIRM,
Id,
Number,
"dww", _DI_MANU_ID, command, Info);
return false;
}
static byte manufacturer_res(dword Id, word Number, DIVA_CAPI_ADAPTER *a,
PLCI *plci, APPL *appl, API_PARSE *msg)
{
word indication;
API_PARSE m_parms[3];
API_PARSE *ncpi;
API_PARSE fax_parms[9];
word i;
byte len;
dbug(1, dprintf("manufacturer_res"));
if ((msg[0].length == 0)
|| (msg[1].length == 0)
|| (GET_DWORD(msg[0].info) != _DI_MANU_ID))
{
return false;
}
indication = GET_WORD(msg[1].info);
switch (indication)
{
case _DI_NEGOTIATE_B3:
if (!plci)
break;
if (((plci->B3_prot != 4) && (plci->B3_prot != 5))
|| !(plci->ncpi_state & NCPI_NEGOTIATE_B3_SENT))
{
dbug(1, dprintf("wrong state for NEGOTIATE_B3 parameters"));
break;
}
if (api_parse(&msg[2].info[1], msg[2].length, "ws", m_parms))
{
dbug(1, dprintf("wrong format in NEGOTIATE_B3 parameters"));
break;
}
ncpi = &m_parms[1];
len = offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH;
if (plci->fax_connect_info_length < len)
{
((T30_INFO *)(plci->fax_connect_info_buffer))->station_id_len = 0;
((T30_INFO *)(plci->fax_connect_info_buffer))->head_line_len = 0;
}
if (api_parse(&ncpi->info[1], ncpi->length, "wwwwssss", fax_parms))
{
dbug(1, dprintf("non-standard facilities info missing or wrong format"));
}
else
{
if (plci->fax_connect_info_length <= len)
plci->fax_connect_info_buffer[len] = 0;
len += 1 + plci->fax_connect_info_buffer[len];
if (plci->fax_connect_info_length <= len)
plci->fax_connect_info_buffer[len] = 0;
len += 1 + plci->fax_connect_info_buffer[len];
if ((fax_parms[7].length >= 3) && (fax_parms[7].info[1] >= 2))
plci->nsf_control_bits = GET_WORD(&fax_parms[7].info[2]);
plci->fax_connect_info_buffer[len++] = (byte)(fax_parms[7].length);
for (i = 0; i < fax_parms[7].length; i++)
plci->fax_connect_info_buffer[len++] = fax_parms[7].info[1 + i];
}
plci->fax_connect_info_length = len;
plci->fax_edata_ack_length = plci->fax_connect_info_length;
start_internal_command(Id, plci, fax_edata_ack_command);
break;
}
return false;
}
/*------------------------------------------------------------------*/
/* IDI callback function */
/*------------------------------------------------------------------*/
void callback(ENTITY *e)
{
DIVA_CAPI_ADAPTER *a;
APPL *appl;
PLCI *plci;
CAPI_MSG *m;
word i, j;
byte rc;
byte ch;
byte req;
byte global_req;
int no_cancel_rc;
dbug(1, dprintf("%x:CB(%x:Req=%x,Rc=%x,Ind=%x)",
(e->user[0] + 1) & 0x7fff, e->Id, e->Req, e->Rc, e->Ind));
a = &(adapter[(byte)e->user[0]]);
plci = &(a->plci[e->user[1]]);
no_cancel_rc = DIVA_CAPI_SUPPORTS_NO_CANCEL(a);
/*
If new protocol code and new XDI is used then CAPI should work
fully in accordance with IDI cpec an look on callback field instead
of Rc field for return codes.
*/
if (((e->complete == 0xff) && no_cancel_rc) ||
(e->Rc && !no_cancel_rc)) {
rc = e->Rc;
ch = e->RcCh;
req = e->Req;
e->Rc = 0;
if (e->user[0] & 0x8000)
{
/*
If REMOVE request was sent then we have to wait until
return code with Id set to zero arrives.
All other return codes should be ignored.
*/
if (req == REMOVE)
{
if (e->Id)
{
dbug(1, dprintf("cancel RC in REMOVE state"));
return;
}
channel_flow_control_remove(plci);
for (i = 0; i < 256; i++)
{
if (a->FlowControlIdTable[i] == plci->nl_remove_id)
a->FlowControlIdTable[i] = 0;
}
plci->nl_remove_id = 0;
if (plci->rx_dma_descriptor > 0) {
diva_free_dma_descriptor(plci, plci->rx_dma_descriptor - 1);
plci->rx_dma_descriptor = 0;
}
}
if (rc == OK_FC)
{
a->FlowControlIdTable[ch] = e->Id;
a->FlowControlSkipTable[ch] = 0;
a->ch_flow_control[ch] |= N_OK_FC_PENDING;
a->ch_flow_plci[ch] = plci->Id;
plci->nl_req = 0;
}
else
{
/*
Cancel return codes self, if feature was requested
*/
if (no_cancel_rc && (a->FlowControlIdTable[ch] == e->Id) && e->Id) {
a->FlowControlIdTable[ch] = 0;
if ((rc == OK) && a->FlowControlSkipTable[ch]) {
dbug(3, dprintf("XDI CAPI: RC cancelled Id:0x02, Ch:%02x", e->Id, ch));
return;
}
}
if (a->ch_flow_control[ch] & N_OK_FC_PENDING)
{
a->ch_flow_control[ch] &= ~N_OK_FC_PENDING;
if (ch == e->ReqCh)
plci->nl_req = 0;
}
else
plci->nl_req = 0;
}
if (plci->nl_req)
control_rc(plci, 0, rc, ch, 0, true);
else
{
if (req == N_XON)
{
channel_x_on(plci, ch);
if (plci->internal_command)
control_rc(plci, req, rc, ch, 0, true);
}
else
{
if (plci->nl_global_req)
{
global_req = plci->nl_global_req;
plci->nl_global_req = 0;
if (rc != ASSIGN_OK) {
e->Id = 0;
if (plci->rx_dma_descriptor > 0) {
diva_free_dma_descriptor(plci, plci->rx_dma_descriptor - 1);
plci->rx_dma_descriptor = 0;
}
}
channel_xmit_xon(plci);
control_rc(plci, 0, rc, ch, global_req, true);
}
else if (plci->data_sent)
{
channel_xmit_xon(plci);
plci->data_sent = false;
plci->NL.XNum = 1;
data_rc(plci, ch);
if (plci->internal_command)
control_rc(plci, req, rc, ch, 0, true);
}
else
{
channel_xmit_xon(plci);
control_rc(plci, req, rc, ch, 0, true);
}
}
}
}
else
{
/*
If REMOVE request was sent then we have to wait until
return code with Id set to zero arrives.
All other return codes should be ignored.
*/
if (req == REMOVE)
{
if (e->Id)
{
dbug(1, dprintf("cancel RC in REMOVE state"));
return;
}
plci->sig_remove_id = 0;
}
plci->sig_req = 0;
if (plci->sig_global_req)
{
global_req = plci->sig_global_req;
plci->sig_global_req = 0;
if (rc != ASSIGN_OK)
e->Id = 0;
channel_xmit_xon(plci);
control_rc(plci, 0, rc, ch, global_req, false);
}
else
{
channel_xmit_xon(plci);
control_rc(plci, req, rc, ch, 0, false);
}
}
/*
Again: in accordance with IDI spec Rc and Ind can't be delivered in the
same callback. Also if new XDI and protocol code used then jump
direct to finish.
*/
if (no_cancel_rc) {
channel_xmit_xon(plci);
goto capi_callback_suffix;
}
}
channel_xmit_xon(plci);
if (e->Ind) {
if (e->user[0] & 0x8000) {
byte Ind = e->Ind & 0x0f;
byte Ch = e->IndCh;
if (((Ind == N_DISC) || (Ind == N_DISC_ACK)) &&
(a->ch_flow_plci[Ch] == plci->Id)) {
if (a->ch_flow_control[Ch] & N_RX_FLOW_CONTROL_MASK) {
dbug(3, dprintf("XDI CAPI: I: pending N-XON Ch:%02x", Ch));
}
a->ch_flow_control[Ch] &= ~N_RX_FLOW_CONTROL_MASK;
}
nl_ind(plci);
if ((e->RNR != 1) &&
(a->ch_flow_plci[Ch] == plci->Id) &&
(a->ch_flow_control[Ch] & N_RX_FLOW_CONTROL_MASK)) {
a->ch_flow_control[Ch] &= ~N_RX_FLOW_CONTROL_MASK;
dbug(3, dprintf("XDI CAPI: I: remove faked N-XON Ch:%02x", Ch));
}
} else {
sig_ind(plci);
}
e->Ind = 0;
}
capi_callback_suffix:
while (!plci->req_in
&& !plci->internal_command
&& (plci->msg_in_write_pos != plci->msg_in_read_pos))
{
j = (plci->msg_in_read_pos == plci->msg_in_wrap_pos) ? 0 : plci->msg_in_read_pos;
i = (((CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[j]))->header.length + 3) & 0xfffc;
m = (CAPI_MSG *)(&((byte *)(plci->msg_in_queue))[j]);
appl = *((APPL **)(&((byte *)(plci->msg_in_queue))[j + i]));
dbug(1, dprintf("dequeue msg(0x%04x) - write=%d read=%d wrap=%d",
m->header.command, plci->msg_in_write_pos, plci->msg_in_read_pos, plci->msg_in_wrap_pos));
if (plci->msg_in_read_pos == plci->msg_in_wrap_pos)
{
plci->msg_in_wrap_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_read_pos = i + MSG_IN_OVERHEAD;
}
else
{
plci->msg_in_read_pos = j + i + MSG_IN_OVERHEAD;
}
if (plci->msg_in_read_pos == plci->msg_in_write_pos)
{
plci->msg_in_write_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_read_pos = MSG_IN_QUEUE_SIZE;
}
else if (plci->msg_in_read_pos == plci->msg_in_wrap_pos)
{
plci->msg_in_read_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_wrap_pos = MSG_IN_QUEUE_SIZE;
}
i = api_put(appl, m);
if (i != 0)
{
if (m->header.command == _DATA_B3_R)
TransmitBufferFree(appl, (byte *)(long)(m->info.data_b3_req.Data));
dbug(1, dprintf("Error 0x%04x from msg(0x%04x)", i, m->header.command));
break;
}
if (plci->li_notify_update)
{
plci->li_notify_update = false;
mixer_notify_update(plci, false);
}
}
send_data(plci);
send_req(plci);
}
static void control_rc(PLCI *plci, byte req, byte rc, byte ch, byte global_req,
byte nl_rc)
{
dword Id;
dword rId;
word Number;
word Info = 0;
word i;
word ncci;
DIVA_CAPI_ADAPTER *a;
APPL *appl;
PLCI *rplci;
byte SSparms[] = "\x05\x00\x00\x02\x00\x00";
byte SSstruct[] = "\x09\x00\x00\x06\x00\x00\x00\x00\x00\x00";
if (!plci) {
dbug(0, dprintf("A: control_rc, no plci %02x:%02x:%02x:%02x:%02x", req, rc, ch, global_req, nl_rc));
return;
}
dbug(1, dprintf("req0_in/out=%d/%d", plci->req_in, plci->req_out));
if (plci->req_in != plci->req_out)
{
if (nl_rc || (global_req != ASSIGN) || (rc == ASSIGN_OK))
{
dbug(1, dprintf("req_1return"));
return;
}
/* cancel outstanding request on the PLCI after SIG ASSIGN failure */
}
plci->req_in = plci->req_in_start = plci->req_out = 0;
dbug(1, dprintf("control_rc"));
appl = plci->appl;
a = plci->adapter;
ncci = a->ch_ncci[ch];
if (appl)
{
Id = (((dword)(ncci ? ncci : ch)) << 16) | ((word)plci->Id << 8) | a->Id;
if (plci->tel && plci->SuppState != CALL_HELD) Id |= EXT_CONTROLLER;
Number = plci->number;
dbug(1, dprintf("Contr_RC-Id=%08lx,plci=%x,tel=%x, entity=0x%x, command=0x%x, int_command=0x%x", Id, plci->Id, plci->tel, plci->Sig.Id, plci->command, plci->internal_command));
dbug(1, dprintf("channels=0x%x", plci->channels));
if (plci_remove_check(plci))
return;
if (req == REMOVE && rc == ASSIGN_OK)
{
sig_req(plci, HANGUP, 0);
sig_req(plci, REMOVE, 0);
send_req(plci);
}
if (plci->command)
{
switch (plci->command)
{
case C_HOLD_REQ:
dbug(1, dprintf("HoldRC=0x%x", rc));
SSparms[1] = (byte)S_HOLD;
if (rc != OK)
{
plci->SuppState = IDLE;
Info = 0x2001;
}
sendf(appl, _FACILITY_R | CONFIRM, Id, Number, "wws", Info, 3, SSparms);
break;
case C_RETRIEVE_REQ:
dbug(1, dprintf("RetrieveRC=0x%x", rc));
SSparms[1] = (byte)S_RETRIEVE;
if (rc != OK)
{
plci->SuppState = CALL_HELD;
Info = 0x2001;
}
sendf(appl, _FACILITY_R | CONFIRM, Id, Number, "wws", Info, 3, SSparms);
break;
case _INFO_R:
dbug(1, dprintf("InfoRC=0x%x", rc));
if (rc != OK) Info = _WRONG_STATE;
sendf(appl, _INFO_R | CONFIRM, Id, Number, "w", Info);
break;
case _CONNECT_R:
dbug(1, dprintf("Connect_R=0x%x/0x%x/0x%x/0x%x", req, rc, global_req, nl_rc));
if (plci->State == INC_DIS_PENDING)
break;
if (plci->Sig.Id != 0xff)
{
if (((global_req == ASSIGN) && (rc != ASSIGN_OK))
|| (!nl_rc && (req == CALL_REQ) && (rc != OK)))
{
dbug(1, dprintf("No more IDs/Call_Req failed"));
sendf(appl, _CONNECT_R | CONFIRM, Id & 0xffL, Number, "w", _OUT_OF_PLCI);
plci_remove(plci);
plci->State = IDLE;
break;
}
if (plci->State != LOCAL_CONNECT) plci->State = OUTG_CON_PENDING;
sendf(appl, _CONNECT_R | CONFIRM, Id, Number, "w", 0);
}
else /* D-ch activation */
{
if (rc != ASSIGN_OK)
{
dbug(1, dprintf("No more IDs/X.25 Call_Req failed"));
sendf(appl, _CONNECT_R | CONFIRM, Id & 0xffL, Number, "w", _OUT_OF_PLCI);
plci_remove(plci);
plci->State = IDLE;
break;
}
sendf(appl, _CONNECT_R | CONFIRM, Id, Number, "w", 0);
sendf(plci->appl, _CONNECT_ACTIVE_I, Id, 0, "sss", "", "", "");
plci->State = INC_ACT_PENDING;
}
break;
case _CONNECT_I | RESPONSE:
if (plci->State != INC_DIS_PENDING)
plci->State = INC_CON_ACCEPT;
break;
case _DISCONNECT_R:
if (plci->State == INC_DIS_PENDING)
break;
if (plci->Sig.Id != 0xff)
{
plci->State = OUTG_DIS_PENDING;
sendf(appl, _DISCONNECT_R | CONFIRM, Id, Number, "w", 0);
}
break;
case SUSPEND_REQ:
break;
case RESUME_REQ:
break;
case _CONNECT_B3_R:
if (rc != OK)
{
sendf(appl, _CONNECT_B3_R | CONFIRM, Id, Number, "w", _WRONG_IDENTIFIER);
break;
}
ncci = get_ncci(plci, ch, 0);
Id = (Id & 0xffff) | (((dword) ncci) << 16);
plci->channels++;
if (req == N_RESET)
{
a->ncci_state[ncci] = INC_ACT_PENDING;
sendf(appl, _CONNECT_B3_R | CONFIRM, Id, Number, "w", 0);
sendf(appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
}
else
{
a->ncci_state[ncci] = OUTG_CON_PENDING;
sendf(appl, _CONNECT_B3_R | CONFIRM, Id, Number, "w", 0);
}
break;
case _CONNECT_B3_I | RESPONSE:
break;
case _RESET_B3_R:
/* sendf(appl, _RESET_B3_R | CONFIRM, Id, Number, "w", 0);*/
break;
case _DISCONNECT_B3_R:
sendf(appl, _DISCONNECT_B3_R | CONFIRM, Id, Number, "w", 0);
break;
case _MANUFACTURER_R:
break;
case PERM_LIST_REQ:
if (rc != OK)
{
Info = _WRONG_IDENTIFIER;
sendf(plci->appl, _CONNECT_R | CONFIRM, Id, Number, "w", Info);
plci_remove(plci);
}
else
sendf(plci->appl, _CONNECT_R | CONFIRM, Id, Number, "w", Info);
break;
default:
break;
}
plci->command = 0;
}
else if (plci->internal_command)
{
switch (plci->internal_command)
{
case BLOCK_PLCI:
return;
case GET_MWI_STATE:
if (rc == OK) /* command supported, wait for indication */
{
return;
}
plci_remove(plci);
break;
/* Get Supported Services */
case GETSERV_REQ_PEND:
if (rc == OK) /* command supported, wait for indication */
{
break;
}
PUT_DWORD(&SSstruct[6], MASK_TERMINAL_PORTABILITY);
sendf(appl, _FACILITY_R | CONFIRM, Id, Number, "wws", 0, 3, SSstruct);
plci_remove(plci);
break;
case INTERR_DIVERSION_REQ_PEND: /* Interrogate Parameters */
case INTERR_NUMBERS_REQ_PEND:
case CF_START_PEND: /* Call Forwarding Start pending */
case CF_STOP_PEND: /* Call Forwarding Stop pending */
case CCBS_REQUEST_REQ_PEND:
case CCBS_DEACTIVATE_REQ_PEND:
case CCBS_INTERROGATE_REQ_PEND:
switch (plci->internal_command)
{
case INTERR_DIVERSION_REQ_PEND:
SSparms[1] = S_INTERROGATE_DIVERSION;
break;
case INTERR_NUMBERS_REQ_PEND:
SSparms[1] = S_INTERROGATE_NUMBERS;
break;
case CF_START_PEND:
SSparms[1] = S_CALL_FORWARDING_START;
break;
case CF_STOP_PEND:
SSparms[1] = S_CALL_FORWARDING_STOP;
break;
case CCBS_REQUEST_REQ_PEND:
SSparms[1] = S_CCBS_REQUEST;
break;
case CCBS_DEACTIVATE_REQ_PEND:
SSparms[1] = S_CCBS_DEACTIVATE;
break;
case CCBS_INTERROGATE_REQ_PEND:
SSparms[1] = S_CCBS_INTERROGATE;
break;
}
if (global_req == ASSIGN)
{
dbug(1, dprintf("AssignDiversion_RC=0x%x/0x%x", req, rc));
return;
}
if (!plci->appl) break;
if (rc == ISDN_GUARD_REJ)
{
Info = _CAPI_GUARD_ERROR;
}
else if (rc != OK)
{
Info = _SUPPLEMENTARY_SERVICE_NOT_SUPPORTED;
}
sendf(plci->appl, _FACILITY_R | CONFIRM, Id & 0x7,
plci->number, "wws", Info, (word)3, SSparms);
if (Info) plci_remove(plci);
break;
/* 3pty conference pending */
case PTY_REQ_PEND:
if (!plci->relatedPTYPLCI) break;
rplci = plci->relatedPTYPLCI;
SSparms[1] = plci->ptyState;
rId = ((word)rplci->Id << 8) | rplci->adapter->Id;
if (rplci->tel) rId |= EXT_CONTROLLER;
if (rc != OK)
{
Info = 0x300E; /* not supported */
plci->relatedPTYPLCI = NULL;
plci->ptyState = 0;
}
sendf(rplci->appl,
_FACILITY_R | CONFIRM,
rId,
plci->number,
"wws", Info, (word)3, SSparms);
break;
/* Explicit Call Transfer pending */
case ECT_REQ_PEND:
dbug(1, dprintf("ECT_RC=0x%x/0x%x", req, rc));
if (!plci->relatedPTYPLCI) break;
rplci = plci->relatedPTYPLCI;
SSparms[1] = S_ECT;
rId = ((word)rplci->Id << 8) | rplci->adapter->Id;
if (rplci->tel) rId |= EXT_CONTROLLER;
if (rc != OK)
{
Info = 0x300E; /* not supported */
plci->relatedPTYPLCI = NULL;
plci->ptyState = 0;
}
sendf(rplci->appl,
_FACILITY_R | CONFIRM,
rId,
plci->number,
"wws", Info, (word)3, SSparms);
break;
case _MANUFACTURER_R:
dbug(1, dprintf("_Manufacturer_R=0x%x/0x%x", req, rc));
if ((global_req == ASSIGN) && (rc != ASSIGN_OK))
{
dbug(1, dprintf("No more IDs"));
sendf(appl, _MANUFACTURER_R | CONFIRM, Id, Number, "dww", _DI_MANU_ID, _MANUFACTURER_R, _OUT_OF_PLCI);
plci_remove(plci); /* after codec init, internal codec commands pending */
}
break;
case _CONNECT_R:
dbug(1, dprintf("_Connect_R=0x%x/0x%x", req, rc));
if ((global_req == ASSIGN) && (rc != ASSIGN_OK))
{
dbug(1, dprintf("No more IDs"));
sendf(appl, _CONNECT_R | CONFIRM, Id & 0xffL, Number, "w", _OUT_OF_PLCI);
plci_remove(plci); /* after codec init, internal codec commands pending */
}
break;
case PERM_COD_HOOK: /* finished with Hook_Ind */
return;
case PERM_COD_CALL:
dbug(1, dprintf("***Codec Connect_Pending A, Rc = 0x%x", rc));
plci->internal_command = PERM_COD_CONN_PEND;
return;
case PERM_COD_ASSIGN:
dbug(1, dprintf("***Codec Assign A, Rc = 0x%x", rc));
if (rc != ASSIGN_OK) break;
sig_req(plci, CALL_REQ, 0);
send_req(plci);
plci->internal_command = PERM_COD_CALL;
return;
/* Null Call Reference Request pending */
case C_NCR_FAC_REQ:
dbug(1, dprintf("NCR_FAC=0x%x/0x%x", req, rc));
if (global_req == ASSIGN)
{
if (rc == ASSIGN_OK)
{
return;
}
else
{
sendf(appl, _INFO_R | CONFIRM, Id & 0xf, Number, "w", _WRONG_STATE);
appl->NullCREnable = false;
plci_remove(plci);
}
}
else if (req == NCR_FACILITY)
{
if (rc == OK)
{
sendf(appl, _INFO_R | CONFIRM, Id & 0xf, Number, "w", 0);
}
else
{
sendf(appl, _INFO_R | CONFIRM, Id & 0xf, Number, "w", _WRONG_STATE);
appl->NullCREnable = false;
}
plci_remove(plci);
}
break;
case HOOK_ON_REQ:
if (plci->channels)
{
if (a->ncci_state[ncci] == CONNECTED)
{
a->ncci_state[ncci] = OUTG_DIS_PENDING;
cleanup_ncci_data(plci, ncci);
nl_req_ncci(plci, N_DISC, (byte)ncci);
}
break;
}
break;
case HOOK_OFF_REQ:
if (plci->State == INC_DIS_PENDING)
break;
sig_req(plci, CALL_REQ, 0);
send_req(plci);
plci->State = OUTG_CON_PENDING;
break;
case MWI_ACTIVATE_REQ_PEND:
case MWI_DEACTIVATE_REQ_PEND:
if (global_req == ASSIGN && rc == ASSIGN_OK)
{
dbug(1, dprintf("MWI_REQ assigned"));
return;
}
else if (rc != OK)
{
if (rc == WRONG_IE)
{
Info = 0x2007; /* Illegal message parameter coding */
dbug(1, dprintf("MWI_REQ invalid parameter"));
}
else
{
Info = 0x300B; /* not supported */
dbug(1, dprintf("MWI_REQ not supported"));
}
/* 0x3010: Request not allowed in this state */
PUT_WORD(&SSparms[4], 0x300E); /* SS not supported */
}
if (plci->internal_command == MWI_ACTIVATE_REQ_PEND)
{
PUT_WORD(&SSparms[1], S_MWI_ACTIVATE);
}
else PUT_WORD(&SSparms[1], S_MWI_DEACTIVATE);
if (plci->cr_enquiry)
{
sendf(plci->appl,
_FACILITY_R | CONFIRM,
Id & 0xf,
plci->number,
"wws", Info, (word)3, SSparms);
if (rc != OK) plci_remove(plci);
}
else
{
sendf(plci->appl,
_FACILITY_R | CONFIRM,
Id,
plci->number,
"wws", Info, (word)3, SSparms);
}
break;
case CONF_BEGIN_REQ_PEND:
case CONF_ADD_REQ_PEND:
case CONF_SPLIT_REQ_PEND:
case CONF_DROP_REQ_PEND:
case CONF_ISOLATE_REQ_PEND:
case CONF_REATTACH_REQ_PEND:
dbug(1, dprintf("CONF_RC=0x%x/0x%x", req, rc));
if ((plci->internal_command == CONF_ADD_REQ_PEND) && (!plci->relatedPTYPLCI)) break;
rplci = plci;
rId = Id;
switch (plci->internal_command)
{
case CONF_BEGIN_REQ_PEND:
SSparms[1] = S_CONF_BEGIN;
break;
case CONF_ADD_REQ_PEND:
SSparms[1] = S_CONF_ADD;
rplci = plci->relatedPTYPLCI;
rId = ((word)rplci->Id << 8) | rplci->adapter->Id;
break;
case CONF_SPLIT_REQ_PEND:
SSparms[1] = S_CONF_SPLIT;
break;
case CONF_DROP_REQ_PEND:
SSparms[1] = S_CONF_DROP;
break;
case CONF_ISOLATE_REQ_PEND:
SSparms[1] = S_CONF_ISOLATE;
break;
case CONF_REATTACH_REQ_PEND:
SSparms[1] = S_CONF_REATTACH;
break;
}
if (rc != OK)
{
Info = 0x300E; /* not supported */
plci->relatedPTYPLCI = NULL;
plci->ptyState = 0;
}
sendf(rplci->appl,
_FACILITY_R | CONFIRM,
rId,
plci->number,
"wws", Info, (word)3, SSparms);
break;
case VSWITCH_REQ_PEND:
if (rc != OK)
{
if (plci->relatedPTYPLCI)
{
plci->relatedPTYPLCI->vswitchstate = 0;
plci->relatedPTYPLCI->vsprot = 0;
plci->relatedPTYPLCI->vsprotdialect = 0;
}
plci->vswitchstate = 0;
plci->vsprot = 0;
plci->vsprotdialect = 0;
}
else
{
if (plci->relatedPTYPLCI &&
plci->vswitchstate == 1 &&
plci->relatedPTYPLCI->vswitchstate == 3) /* join complete */
plci->vswitchstate = 3;
}
break;
/* Call Deflection Request pending (SSCT) */
case CD_REQ_PEND:
SSparms[1] = S_CALL_DEFLECTION;
if (rc != OK)
{
Info = 0x300E; /* not supported */
plci->appl->CDEnable = 0;
}
sendf(plci->appl, _FACILITY_R | CONFIRM, Id,
plci->number, "wws", Info, (word)3, SSparms);
break;
case RTP_CONNECT_B3_REQ_COMMAND_2:
if (rc == OK)
{
ncci = get_ncci(plci, ch, 0);
Id = (Id & 0xffff) | (((dword) ncci) << 16);
plci->channels++;
a->ncci_state[ncci] = OUTG_CON_PENDING;
}
default:
if (plci->internal_command_queue[0])
{
(*(plci->internal_command_queue[0]))(Id, plci, rc);
if (plci->internal_command)
return;
}
break;
}
next_internal_command(Id, plci);
}
}
else /* appl==0 */
{
Id = ((word)plci->Id << 8) | plci->adapter->Id;
if (plci->tel) Id |= EXT_CONTROLLER;
switch (plci->internal_command)
{
case BLOCK_PLCI:
return;
case START_L1_SIG_ASSIGN_PEND:
case REM_L1_SIG_ASSIGN_PEND:
if (global_req == ASSIGN)
{
break;
}
else
{
dbug(1, dprintf("***L1 Req rem PLCI"));
plci->internal_command = 0;
sig_req(plci, REMOVE, 0);
send_req(plci);
}
break;
/* Call Deflection Request pending, just no appl ptr assigned */
case CD_REQ_PEND:
SSparms[1] = S_CALL_DEFLECTION;
if (rc != OK)
{
Info = 0x300E; /* not supported */
}
for (i = 0; i < max_appl; i++)
{
if (application[i].CDEnable)
{
if (!application[i].Id) application[i].CDEnable = 0;
else
{
sendf(&application[i], _FACILITY_R | CONFIRM, Id,
plci->number, "wws", Info, (word)3, SSparms);
if (Info) application[i].CDEnable = 0;
}
}
}
plci->internal_command = 0;
break;
case PERM_COD_HOOK: /* finished with Hook_Ind */
return;
case PERM_COD_CALL:
plci->internal_command = PERM_COD_CONN_PEND;
dbug(1, dprintf("***Codec Connect_Pending, Rc = 0x%x", rc));
return;
case PERM_COD_ASSIGN:
dbug(1, dprintf("***Codec Assign, Rc = 0x%x", rc));
plci->internal_command = 0;
if (rc != ASSIGN_OK) break;
plci->internal_command = PERM_COD_CALL;
sig_req(plci, CALL_REQ, 0);
send_req(plci);
return;
case LISTEN_SIG_ASSIGN_PEND:
if (rc == ASSIGN_OK)
{
plci->internal_command = 0;
dbug(1, dprintf("ListenCheck, new SIG_ID = 0x%x", plci->Sig.Id));
add_p(plci, ESC, "\x02\x18\x00"); /* support call waiting */
sig_req(plci, INDICATE_REQ, 0);
send_req(plci);
}
else
{
dbug(1, dprintf("ListenCheck failed (assignRc=0x%x)", rc));
a->listen_active--;
plci_remove(plci);
plci->State = IDLE;
}
break;
case USELAW_REQ:
if (global_req == ASSIGN)
{
if (rc == ASSIGN_OK)
{
sig_req(plci, LAW_REQ, 0);
send_req(plci);
dbug(1, dprintf("Auto-Law assigned"));
}
else
{
dbug(1, dprintf("Auto-Law assign failed"));
a->automatic_law = 3;
plci->internal_command = 0;
a->automatic_lawPLCI = NULL;
}
break;
}
else if (req == LAW_REQ && rc == OK)
{
dbug(1, dprintf("Auto-Law initiated"));
a->automatic_law = 2;
plci->internal_command = 0;
}
else
{
dbug(1, dprintf("Auto-Law not supported"));
a->automatic_law = 3;
plci->internal_command = 0;
sig_req(plci, REMOVE, 0);
send_req(plci);
a->automatic_lawPLCI = NULL;
}
break;
}
plci_remove_check(plci);
}
}
static void data_rc(PLCI *plci, byte ch)
{
dword Id;
DIVA_CAPI_ADAPTER *a;
NCCI *ncci_ptr;
DATA_B3_DESC *data;
word ncci;
if (plci->appl)
{
TransmitBufferFree(plci->appl, plci->data_sent_ptr);
a = plci->adapter;
ncci = a->ch_ncci[ch];
if (ncci && (a->ncci_plci[ncci] == plci->Id))
{
ncci_ptr = &(a->ncci[ncci]);
dbug(1, dprintf("data_out=%d, data_pending=%d", ncci_ptr->data_out, ncci_ptr->data_pending));
if (ncci_ptr->data_pending)
{
data = &(ncci_ptr->DBuffer[ncci_ptr->data_out]);
if (!(data->Flags & 4) && a->ncci_state[ncci])
{
Id = (((dword)ncci) << 16) | ((word)plci->Id << 8) | a->Id;
if (plci->tel) Id |= EXT_CONTROLLER;
sendf(plci->appl, _DATA_B3_R | CONFIRM, Id, data->Number,
"ww", data->Handle, 0);
}
(ncci_ptr->data_out)++;
if (ncci_ptr->data_out == MAX_DATA_B3)
ncci_ptr->data_out = 0;
(ncci_ptr->data_pending)--;
}
}
}
}
static void data_ack(PLCI *plci, byte ch)
{
dword Id;
DIVA_CAPI_ADAPTER *a;
NCCI *ncci_ptr;
word ncci;
a = plci->adapter;
ncci = a->ch_ncci[ch];
ncci_ptr = &(a->ncci[ncci]);
if (ncci_ptr->data_ack_pending)
{
if (a->ncci_state[ncci] && (a->ncci_plci[ncci] == plci->Id))
{
Id = (((dword)ncci) << 16) | ((word)plci->Id << 8) | a->Id;
if (plci->tel) Id |= EXT_CONTROLLER;
sendf(plci->appl, _DATA_B3_R | CONFIRM, Id, ncci_ptr->DataAck[ncci_ptr->data_ack_out].Number,
"ww", ncci_ptr->DataAck[ncci_ptr->data_ack_out].Handle, 0);
}
(ncci_ptr->data_ack_out)++;
if (ncci_ptr->data_ack_out == MAX_DATA_ACK)
ncci_ptr->data_ack_out = 0;
(ncci_ptr->data_ack_pending)--;
}
}
static void sig_ind(PLCI *plci)
{
dword x_Id;
dword Id;
dword rId;
word i;
word cip;
dword cip_mask;
byte *ie;
DIVA_CAPI_ADAPTER *a;
API_PARSE saved_parms[MAX_MSG_PARMS + 1];
#define MAXPARMSIDS 31
byte *parms[MAXPARMSIDS];
byte *add_i[4];
byte *multi_fac_parms[MAX_MULTI_IE];
byte *multi_pi_parms[MAX_MULTI_IE];
byte *multi_ssext_parms[MAX_MULTI_IE];
byte *multi_CiPN_parms[MAX_MULTI_IE];
byte *multi_vswitch_parms[MAX_MULTI_IE];
byte ai_len;
byte *esc_chi = "";
byte *esc_law = "";
byte *pty_cai = "";
byte *esc_cr = "";
byte *esc_profile = "";
byte facility[256];
PLCI *tplci = NULL;
byte chi[] = "\x02\x18\x01";
byte voice_cai[] = "\x06\x14\x00\x00\x00\x00\x08";
byte resume_cau[] = "\x05\x05\x00\x02\x00\x00";
/* ESC_MSGTYPE must be the last but one message, a new IE has to be */
/* included before the ESC_MSGTYPE and MAXPARMSIDS has to be incremented */
/* SMSG is situated at the end because its 0 (for compatibility reasons */
/* (see Info_Mask Bit 4, first IE. then the message type) */
word parms_id[] =
{MAXPARMSIDS, CPN, 0xff, DSA, OSA, BC, LLC, HLC, ESC_CAUSE, DSP, DT, CHA,
UUI, CONG_RR, CONG_RNR, ESC_CHI, KEY, CHI, CAU, ESC_LAW,
RDN, RDX, CONN_NR, RIN, NI, CAI, ESC_CR,
CST, ESC_PROFILE, 0xff, ESC_MSGTYPE, SMSG};
/* 14 FTY repl by ESC_CHI */
/* 18 PI repl by ESC_LAW */
/* removed OAD changed to 0xff for future use, OAD is multiIE now */
word multi_fac_id[] = {1, FTY};
word multi_pi_id[] = {1, PI};
word multi_CiPN_id[] = {1, OAD};
word multi_ssext_id[] = {1, ESC_SSEXT};
word multi_vswitch_id[] = {1, ESC_VSWITCH};
byte *cau;
word ncci;
byte SS_Ind[] = "\x05\x02\x00\x02\x00\x00"; /* Hold_Ind struct*/
byte CF_Ind[] = "\x09\x02\x00\x06\x00\x00\x00\x00\x00\x00";
byte Interr_Err_Ind[] = "\x0a\x02\x00\x07\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
byte CONF_Ind[] = "\x09\x16\x00\x06\x00\x00\0x00\0x00\0x00\0x00";
byte force_mt_info = false;
byte dir;
dword d;
word w;
a = plci->adapter;
Id = ((word)plci->Id << 8) | a->Id;
PUT_WORD(&SS_Ind[4], 0x0000);
if (plci->sig_remove_id)
{
plci->Sig.RNR = 2; /* discard */
dbug(1, dprintf("SIG discard while remove pending"));
return;
}
if (plci->tel && plci->SuppState != CALL_HELD) Id |= EXT_CONTROLLER;
dbug(1, dprintf("SigInd-Id=%08lx,plci=%x,tel=%x,state=0x%x,channels=%d,Discflowcl=%d",
Id, plci->Id, plci->tel, plci->State, plci->channels, plci->hangup_flow_ctrl_timer));
if (plci->Sig.Ind == CALL_HOLD_ACK && plci->channels)
{
plci->Sig.RNR = 1;
return;
}
if (plci->Sig.Ind == HANGUP && plci->channels)
{
plci->Sig.RNR = 1;
plci->hangup_flow_ctrl_timer++;
/* recover the network layer after timeout */
if (plci->hangup_flow_ctrl_timer == 100)
{
dbug(1, dprintf("Exceptional disc"));
plci->Sig.RNR = 0;
plci->hangup_flow_ctrl_timer = 0;
for (ncci = 1; ncci < MAX_NCCI + 1; ncci++)
{
if (a->ncci_plci[ncci] == plci->Id)
{
cleanup_ncci_data(plci, ncci);
if (plci->channels)plci->channels--;
if (plci->appl)
sendf(plci->appl, _DISCONNECT_B3_I, (((dword) ncci) << 16) | Id, 0, "ws", 0, "");
}
}
if (plci->appl)
sendf(plci->appl, _DISCONNECT_I, Id, 0, "w", 0);
plci_remove(plci);
plci->State = IDLE;
}
return;
}
/* do first parse the info with no OAD in, because OAD will be converted */
/* first the multiple facility IE, then mult. progress ind. */
/* then the parameters for the info_ind + conn_ind */
IndParse(plci, multi_fac_id, multi_fac_parms, MAX_MULTI_IE);
IndParse(plci, multi_pi_id, multi_pi_parms, MAX_MULTI_IE);
IndParse(plci, multi_ssext_id, multi_ssext_parms, MAX_MULTI_IE);
IndParse(plci, multi_vswitch_id, multi_vswitch_parms, MAX_MULTI_IE);
IndParse(plci, parms_id, parms, 0);
IndParse(plci, multi_CiPN_id, multi_CiPN_parms, MAX_MULTI_IE);
esc_chi = parms[14];
esc_law = parms[18];
pty_cai = parms[24];
esc_cr = parms[25];
esc_profile = parms[27];
if (esc_cr[0] && plci)
{
if (plci->cr_enquiry && plci->appl)
{
plci->cr_enquiry = false;
/* d = MANU_ID */
/* w = m_command */
/* b = total length */
/* b = indication type */
/* b = length of all IEs */
/* b = IE1 */
/* S = IE1 length + cont. */
/* b = IE2 */
/* S = IE2 length + cont. */
sendf(plci->appl,
_MANUFACTURER_I,
Id,
0,
"dwbbbbSbS", _DI_MANU_ID, plci->m_command,
2 + 1 + 1 + esc_cr[0] + 1 + 1 + esc_law[0], plci->Sig.Ind, 1 + 1 + esc_cr[0] + 1 + 1 + esc_law[0], ESC, esc_cr, ESC, esc_law);
}
}
/* create the additional info structure */
add_i[1] = parms[15]; /* KEY of additional info */
add_i[2] = parms[11]; /* UUI of additional info */
ai_len = AddInfo(add_i, multi_fac_parms, esc_chi, facility);
/* the ESC_LAW indicates if u-Law or a-Law is actually used by the card */
/* indication returns by the card if requested by the function */
/* AutomaticLaw() after driver init */
if (a->automatic_law < 4)
{
if (esc_law[0]) {
if (esc_law[2]) {
dbug(0, dprintf("u-Law selected"));
a->u_law = 1;
}
else {
dbug(0, dprintf("a-Law selected"));
a->u_law = 0;
}
a->automatic_law = 4;
if (plci == a->automatic_lawPLCI) {
plci->internal_command = 0;
sig_req(plci, REMOVE, 0);
send_req(plci);
a->automatic_lawPLCI = NULL;
}
}
if (esc_profile[0])
{
dbug(1, dprintf("[%06x] CardProfile: %lx %lx %lx %lx %lx",
UnMapController(a->Id), GET_DWORD(&esc_profile[6]),
GET_DWORD(&esc_profile[10]), GET_DWORD(&esc_profile[14]),
GET_DWORD(&esc_profile[18]), GET_DWORD(&esc_profile[46])));
a->profile.Global_Options &= 0x000000ffL;
a->profile.B1_Protocols &= 0x000003ffL;
a->profile.B2_Protocols &= 0x00001fdfL;
a->profile.B3_Protocols &= 0x000000b7L;
a->profile.Global_Options &= GET_DWORD(&esc_profile[6]) |
GL_BCHANNEL_OPERATION_SUPPORTED;
a->profile.B1_Protocols &= GET_DWORD(&esc_profile[10]);
a->profile.B2_Protocols &= GET_DWORD(&esc_profile[14]);
a->profile.B3_Protocols &= GET_DWORD(&esc_profile[18]);
a->manufacturer_features = GET_DWORD(&esc_profile[46]);
a->man_profile.private_options = 0;
if (a->manufacturer_features & MANUFACTURER_FEATURE_ECHO_CANCELLER)
{
a->man_profile.private_options |= 1L << PRIVATE_ECHO_CANCELLER;
a->profile.Global_Options |= GL_ECHO_CANCELLER_SUPPORTED;
}
if (a->manufacturer_features & MANUFACTURER_FEATURE_RTP)
a->man_profile.private_options |= 1L << PRIVATE_RTP;
a->man_profile.rtp_primary_payloads = GET_DWORD(&esc_profile[50]);
a->man_profile.rtp_additional_payloads = GET_DWORD(&esc_profile[54]);
if (a->manufacturer_features & MANUFACTURER_FEATURE_T38)
a->man_profile.private_options |= 1L << PRIVATE_T38;
if (a->manufacturer_features & MANUFACTURER_FEATURE_FAX_SUB_SEP_PWD)
a->man_profile.private_options |= 1L << PRIVATE_FAX_SUB_SEP_PWD;
if (a->manufacturer_features & MANUFACTURER_FEATURE_V18)
a->man_profile.private_options |= 1L << PRIVATE_V18;
if (a->manufacturer_features & MANUFACTURER_FEATURE_DTMF_TONE)
a->man_profile.private_options |= 1L << PRIVATE_DTMF_TONE;
if (a->manufacturer_features & MANUFACTURER_FEATURE_PIAFS)
a->man_profile.private_options |= 1L << PRIVATE_PIAFS;
if (a->manufacturer_features & MANUFACTURER_FEATURE_FAX_PAPER_FORMATS)
a->man_profile.private_options |= 1L << PRIVATE_FAX_PAPER_FORMATS;
if (a->manufacturer_features & MANUFACTURER_FEATURE_VOWN)
a->man_profile.private_options |= 1L << PRIVATE_VOWN;
if (a->manufacturer_features & MANUFACTURER_FEATURE_FAX_NONSTANDARD)
a->man_profile.private_options |= 1L << PRIVATE_FAX_NONSTANDARD;
}
else
{
a->profile.Global_Options &= 0x0000007fL;
a->profile.B1_Protocols &= 0x000003dfL;
a->profile.B2_Protocols &= 0x00001adfL;
a->profile.B3_Protocols &= 0x000000b7L;
a->manufacturer_features &= MANUFACTURER_FEATURE_HARDDTMF;
}
if (a->manufacturer_features & (MANUFACTURER_FEATURE_HARDDTMF |
MANUFACTURER_FEATURE_SOFTDTMF_SEND | MANUFACTURER_FEATURE_SOFTDTMF_RECEIVE))
{
a->profile.Global_Options |= GL_DTMF_SUPPORTED;
}
a->manufacturer_features &= ~MANUFACTURER_FEATURE_OOB_CHANNEL;
dbug(1, dprintf("[%06x] Profile: %lx %lx %lx %lx %lx",
UnMapController(a->Id), a->profile.Global_Options,
a->profile.B1_Protocols, a->profile.B2_Protocols,
a->profile.B3_Protocols, a->manufacturer_features));
}
/* codec plci for the handset/hook state support is just an internal id */
if (plci != a->AdvCodecPLCI)
{
force_mt_info = SendMultiIE(plci, Id, multi_fac_parms, FTY, 0x20, 0);
force_mt_info |= SendMultiIE(plci, Id, multi_pi_parms, PI, 0x210, 0);
SendSSExtInd(NULL, plci, Id, multi_ssext_parms);
SendInfo(plci, Id, parms, force_mt_info);
VSwitchReqInd(plci, Id, multi_vswitch_parms);
}
/* switch the codec to the b-channel */
if (esc_chi[0] && plci && !plci->SuppState) {
plci->b_channel = esc_chi[esc_chi[0]]&0x1f;
mixer_set_bchannel_id_esc(plci, plci->b_channel);
dbug(1, dprintf("storeChannel=0x%x", plci->b_channel));
if (plci->tel == ADV_VOICE && plci->appl) {
SetVoiceChannel(a->AdvCodecPLCI, esc_chi, a);
}
}
if (plci->appl) plci->appl->Number++;
switch (plci->Sig.Ind) {
/* Response to Get_Supported_Services request */
case S_SUPPORTED:
dbug(1, dprintf("S_Supported"));
if (!plci->appl) break;
if (pty_cai[0] == 4)
{
PUT_DWORD(&CF_Ind[6], GET_DWORD(&pty_cai[1]));
}
else
{
PUT_DWORD(&CF_Ind[6], MASK_TERMINAL_PORTABILITY | MASK_HOLD_RETRIEVE);
}
PUT_WORD(&CF_Ind[1], 0);
PUT_WORD(&CF_Ind[4], 0);
sendf(plci->appl, _FACILITY_R | CONFIRM, Id & 0x7, plci->number, "wws", 0, 3, CF_Ind);
plci_remove(plci);
break;
/* Supplementary Service rejected */
case S_SERVICE_REJ:
dbug(1, dprintf("S_Reject=0x%x", pty_cai[5]));
if (!pty_cai[0]) break;
switch (pty_cai[5])
{
case ECT_EXECUTE:
case THREE_PTY_END:
case THREE_PTY_BEGIN:
if (!plci->relatedPTYPLCI) break;
tplci = plci->relatedPTYPLCI;
rId = ((word)tplci->Id << 8) | tplci->adapter->Id;
if (tplci->tel) rId |= EXT_CONTROLLER;
if (pty_cai[5] == ECT_EXECUTE)
{
PUT_WORD(&SS_Ind[1], S_ECT);
plci->vswitchstate = 0;
plci->relatedPTYPLCI->vswitchstate = 0;
}
else
{
PUT_WORD(&SS_Ind[1], pty_cai[5] + 3);
}
if (pty_cai[2] != 0xff)
{
PUT_WORD(&SS_Ind[4], 0x3600 | (word)pty_cai[2]);
}
else
{
PUT_WORD(&SS_Ind[4], 0x300E);
}
plci->relatedPTYPLCI = NULL;
plci->ptyState = 0;
sendf(tplci->appl, _FACILITY_I, rId, 0, "ws", 3, SS_Ind);
break;
case CALL_DEFLECTION:
if (pty_cai[2] != 0xff)
{
PUT_WORD(&SS_Ind[4], 0x3600 | (word)pty_cai[2]);
}
else
{
PUT_WORD(&SS_Ind[4], 0x300E);
}
PUT_WORD(&SS_Ind[1], pty_cai[5]);
for (i = 0; i < max_appl; i++)
{
if (application[i].CDEnable)
{
if (application[i].Id) sendf(&application[i], _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
application[i].CDEnable = false;
}
}
break;
case DEACTIVATION_DIVERSION:
case ACTIVATION_DIVERSION:
case DIVERSION_INTERROGATE_CFU:
case DIVERSION_INTERROGATE_CFB:
case DIVERSION_INTERROGATE_CFNR:
case DIVERSION_INTERROGATE_NUM:
case CCBS_REQUEST:
case CCBS_DEACTIVATE:
case CCBS_INTERROGATE:
if (!plci->appl) break;
if (pty_cai[2] != 0xff)
{
PUT_WORD(&Interr_Err_Ind[4], 0x3600 | (word)pty_cai[2]);
}
else
{
PUT_WORD(&Interr_Err_Ind[4], 0x300E);
}
switch (pty_cai[5])
{
case DEACTIVATION_DIVERSION:
dbug(1, dprintf("Deact_Div"));
Interr_Err_Ind[0] = 0x9;
Interr_Err_Ind[3] = 0x6;
PUT_WORD(&Interr_Err_Ind[1], S_CALL_FORWARDING_STOP);
break;
case ACTIVATION_DIVERSION:
dbug(1, dprintf("Act_Div"));
Interr_Err_Ind[0] = 0x9;
Interr_Err_Ind[3] = 0x6;
PUT_WORD(&Interr_Err_Ind[1], S_CALL_FORWARDING_START);
break;
case DIVERSION_INTERROGATE_CFU:
case DIVERSION_INTERROGATE_CFB:
case DIVERSION_INTERROGATE_CFNR:
dbug(1, dprintf("Interr_Div"));
Interr_Err_Ind[0] = 0xa;
Interr_Err_Ind[3] = 0x7;
PUT_WORD(&Interr_Err_Ind[1], S_INTERROGATE_DIVERSION);
break;
case DIVERSION_INTERROGATE_NUM:
dbug(1, dprintf("Interr_Num"));
Interr_Err_Ind[0] = 0xa;
Interr_Err_Ind[3] = 0x7;
PUT_WORD(&Interr_Err_Ind[1], S_INTERROGATE_NUMBERS);
break;
case CCBS_REQUEST:
dbug(1, dprintf("CCBS Request"));
Interr_Err_Ind[0] = 0xd;
Interr_Err_Ind[3] = 0xa;
PUT_WORD(&Interr_Err_Ind[1], S_CCBS_REQUEST);
break;
case CCBS_DEACTIVATE:
dbug(1, dprintf("CCBS Deactivate"));
Interr_Err_Ind[0] = 0x9;
Interr_Err_Ind[3] = 0x6;
PUT_WORD(&Interr_Err_Ind[1], S_CCBS_DEACTIVATE);
break;
case CCBS_INTERROGATE:
dbug(1, dprintf("CCBS Interrogate"));
Interr_Err_Ind[0] = 0xb;
Interr_Err_Ind[3] = 0x8;
PUT_WORD(&Interr_Err_Ind[1], S_CCBS_INTERROGATE);
break;
}
PUT_DWORD(&Interr_Err_Ind[6], plci->appl->S_Handle);
sendf(plci->appl, _FACILITY_I, Id & 0x7, 0, "ws", 3, Interr_Err_Ind);
plci_remove(plci);
break;
case ACTIVATION_MWI:
case DEACTIVATION_MWI:
if (pty_cai[5] == ACTIVATION_MWI)
{
PUT_WORD(&SS_Ind[1], S_MWI_ACTIVATE);
}
else PUT_WORD(&SS_Ind[1], S_MWI_DEACTIVATE);
if (pty_cai[2] != 0xff)
{
PUT_WORD(&SS_Ind[4], 0x3600 | (word)pty_cai[2]);
}
else
{
PUT_WORD(&SS_Ind[4], 0x300E);
}
if (plci->cr_enquiry)
{
sendf(plci->appl, _FACILITY_I, Id & 0xf, 0, "ws", 3, SS_Ind);
plci_remove(plci);
}
else
{
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
}
break;
case CONF_ADD: /* ERROR */
case CONF_BEGIN:
case CONF_DROP:
case CONF_ISOLATE:
case CONF_REATTACH:
CONF_Ind[0] = 9;
CONF_Ind[3] = 6;
switch (pty_cai[5])
{
case CONF_BEGIN:
PUT_WORD(&CONF_Ind[1], S_CONF_BEGIN);
plci->ptyState = 0;
break;
case CONF_DROP:
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
PUT_WORD(&CONF_Ind[1], S_CONF_DROP);
plci->ptyState = CONNECTED;
break;
case CONF_ISOLATE:
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
PUT_WORD(&CONF_Ind[1], S_CONF_ISOLATE);
plci->ptyState = CONNECTED;
break;
case CONF_REATTACH:
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
PUT_WORD(&CONF_Ind[1], S_CONF_REATTACH);
plci->ptyState = CONNECTED;
break;
case CONF_ADD:
PUT_WORD(&CONF_Ind[1], S_CONF_ADD);
plci->relatedPTYPLCI = NULL;
tplci = plci->relatedPTYPLCI;
if (tplci) tplci->ptyState = CONNECTED;
plci->ptyState = CONNECTED;
break;
}
if (pty_cai[2] != 0xff)
{
PUT_WORD(&CONF_Ind[4], 0x3600 | (word)pty_cai[2]);
}
else
{
PUT_WORD(&CONF_Ind[4], 0x3303); /* Time-out: network did not respond
within the required time */
}
PUT_DWORD(&CONF_Ind[6], 0x0);
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, CONF_Ind);
break;
}
break;
/* Supplementary Service indicates success */
case S_SERVICE:
dbug(1, dprintf("Service_Ind"));
PUT_WORD(&CF_Ind[4], 0);
switch (pty_cai[5])
{
case THREE_PTY_END:
case THREE_PTY_BEGIN:
case ECT_EXECUTE:
if (!plci->relatedPTYPLCI) break;
tplci = plci->relatedPTYPLCI;
rId = ((word)tplci->Id << 8) | tplci->adapter->Id;
if (tplci->tel) rId |= EXT_CONTROLLER;
if (pty_cai[5] == ECT_EXECUTE)
{
PUT_WORD(&SS_Ind[1], S_ECT);
if (plci->vswitchstate != 3)
{
plci->ptyState = IDLE;
plci->relatedPTYPLCI = NULL;
plci->ptyState = 0;
}
dbug(1, dprintf("ECT OK"));
sendf(tplci->appl, _FACILITY_I, rId, 0, "ws", 3, SS_Ind);
}
else
{
switch (plci->ptyState)
{
case S_3PTY_BEGIN:
plci->ptyState = CONNECTED;
dbug(1, dprintf("3PTY ON"));
break;
case S_3PTY_END:
plci->ptyState = IDLE;
plci->relatedPTYPLCI = NULL;
plci->ptyState = 0;
dbug(1, dprintf("3PTY OFF"));
break;
}
PUT_WORD(&SS_Ind[1], pty_cai[5] + 3);
sendf(tplci->appl, _FACILITY_I, rId, 0, "ws", 3, SS_Ind);
}
break;
case CALL_DEFLECTION:
PUT_WORD(&SS_Ind[1], pty_cai[5]);
for (i = 0; i < max_appl; i++)
{
if (application[i].CDEnable)
{
if (application[i].Id) sendf(&application[i], _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
application[i].CDEnable = false;
}
}
break;
case DEACTIVATION_DIVERSION:
case ACTIVATION_DIVERSION:
if (!plci->appl) break;
PUT_WORD(&CF_Ind[1], pty_cai[5] + 2);
PUT_DWORD(&CF_Ind[6], plci->appl->S_Handle);
sendf(plci->appl, _FACILITY_I, Id & 0x7, 0, "ws", 3, CF_Ind);
plci_remove(plci);
break;
case DIVERSION_INTERROGATE_CFU:
case DIVERSION_INTERROGATE_CFB:
case DIVERSION_INTERROGATE_CFNR:
case DIVERSION_INTERROGATE_NUM:
case CCBS_REQUEST:
case CCBS_DEACTIVATE:
case CCBS_INTERROGATE:
if (!plci->appl) break;
switch (pty_cai[5])
{
case DIVERSION_INTERROGATE_CFU:
case DIVERSION_INTERROGATE_CFB:
case DIVERSION_INTERROGATE_CFNR:
dbug(1, dprintf("Interr_Div"));
PUT_WORD(&pty_cai[1], S_INTERROGATE_DIVERSION);
pty_cai[3] = pty_cai[0] - 3; /* Supplementary Service-specific parameter len */
break;
case DIVERSION_INTERROGATE_NUM:
dbug(1, dprintf("Interr_Num"));
PUT_WORD(&pty_cai[1], S_INTERROGATE_NUMBERS);
pty_cai[3] = pty_cai[0] - 3; /* Supplementary Service-specific parameter len */
break;
case CCBS_REQUEST:
dbug(1, dprintf("CCBS Request"));
PUT_WORD(&pty_cai[1], S_CCBS_REQUEST);
pty_cai[3] = pty_cai[0] - 3; /* Supplementary Service-specific parameter len */
break;
case CCBS_DEACTIVATE:
dbug(1, dprintf("CCBS Deactivate"));
PUT_WORD(&pty_cai[1], S_CCBS_DEACTIVATE);
pty_cai[3] = pty_cai[0] - 3; /* Supplementary Service-specific parameter len */
break;
case CCBS_INTERROGATE:
dbug(1, dprintf("CCBS Interrogate"));
PUT_WORD(&pty_cai[1], S_CCBS_INTERROGATE);
pty_cai[3] = pty_cai[0] - 3; /* Supplementary Service-specific parameter len */
break;
}
PUT_WORD(&pty_cai[4], 0); /* Supplementary Service Reason */
PUT_DWORD(&pty_cai[6], plci->appl->S_Handle);
sendf(plci->appl, _FACILITY_I, Id & 0x7, 0, "wS", 3, pty_cai);
plci_remove(plci);
break;
case ACTIVATION_MWI:
case DEACTIVATION_MWI:
if (pty_cai[5] == ACTIVATION_MWI)
{
PUT_WORD(&SS_Ind[1], S_MWI_ACTIVATE);
}
else PUT_WORD(&SS_Ind[1], S_MWI_DEACTIVATE);
if (plci->cr_enquiry)
{
sendf(plci->appl, _FACILITY_I, Id & 0xf, 0, "ws", 3, SS_Ind);
plci_remove(plci);
}
else
{
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
}
break;
case MWI_INDICATION:
if (pty_cai[0] >= 0x12)
{
PUT_WORD(&pty_cai[3], S_MWI_INDICATE);
pty_cai[2] = pty_cai[0] - 2; /* len Parameter */
pty_cai[5] = pty_cai[0] - 5; /* Supplementary Service-specific parameter len */
if (plci->appl && (a->Notification_Mask[plci->appl->Id - 1] & SMASK_MWI))
{
if (plci->internal_command == GET_MWI_STATE) /* result on Message Waiting Listen */
{
sendf(plci->appl, _FACILITY_I, Id & 0xf, 0, "wS", 3, &pty_cai[2]);
plci_remove(plci);
return;
}
else sendf(plci->appl, _FACILITY_I, Id, 0, "wS", 3, &pty_cai[2]);
pty_cai[0] = 0;
}
else
{
for (i = 0; i < max_appl; i++)
{
if (a->Notification_Mask[i]&SMASK_MWI)
{
sendf(&application[i], _FACILITY_I, Id & 0x7, 0, "wS", 3, &pty_cai[2]);
pty_cai[0] = 0;
}
}
}
if (!pty_cai[0])
{ /* acknowledge */
facility[2] = 0; /* returncode */
}
else facility[2] = 0xff;
}
else
{
/* reject */
facility[2] = 0xff; /* returncode */
}
facility[0] = 2;
facility[1] = MWI_RESPONSE; /* Function */
add_p(plci, CAI, facility);
add_p(plci, ESC, multi_ssext_parms[0]); /* remembered parameter -> only one possible */
sig_req(plci, S_SERVICE, 0);
send_req(plci);
plci->command = 0;
next_internal_command(Id, plci);
break;
case CONF_ADD: /* OK */
case CONF_BEGIN:
case CONF_DROP:
case CONF_ISOLATE:
case CONF_REATTACH:
case CONF_PARTYDISC:
CONF_Ind[0] = 9;
CONF_Ind[3] = 6;
switch (pty_cai[5])
{
case CONF_BEGIN:
PUT_WORD(&CONF_Ind[1], S_CONF_BEGIN);
if (pty_cai[0] == 6)
{
d = pty_cai[6];
PUT_DWORD(&CONF_Ind[6], d); /* PartyID */
}
else
{
PUT_DWORD(&CONF_Ind[6], 0x0);
}
break;
case CONF_ISOLATE:
PUT_WORD(&CONF_Ind[1], S_CONF_ISOLATE);
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
break;
case CONF_REATTACH:
PUT_WORD(&CONF_Ind[1], S_CONF_REATTACH);
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
break;
case CONF_DROP:
PUT_WORD(&CONF_Ind[1], S_CONF_DROP);
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
break;
case CONF_ADD:
PUT_WORD(&CONF_Ind[1], S_CONF_ADD);
d = pty_cai[6];
PUT_DWORD(&CONF_Ind[6], d); /* PartyID */
tplci = plci->relatedPTYPLCI;
if (tplci) tplci->ptyState = CONNECTED;
break;
case CONF_PARTYDISC:
CONF_Ind[0] = 7;
CONF_Ind[3] = 4;
PUT_WORD(&CONF_Ind[1], S_CONF_PARTYDISC);
d = pty_cai[6];
PUT_DWORD(&CONF_Ind[4], d); /* PartyID */
break;
}
plci->ptyState = CONNECTED;
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, CONF_Ind);
break;
case CCBS_INFO_RETAIN:
case CCBS_ERASECALLLINKAGEID:
case CCBS_STOP_ALERTING:
CONF_Ind[0] = 5;
CONF_Ind[3] = 2;
switch (pty_cai[5])
{
case CCBS_INFO_RETAIN:
PUT_WORD(&CONF_Ind[1], S_CCBS_INFO_RETAIN);
break;
case CCBS_STOP_ALERTING:
PUT_WORD(&CONF_Ind[1], S_CCBS_STOP_ALERTING);
break;
case CCBS_ERASECALLLINKAGEID:
PUT_WORD(&CONF_Ind[1], S_CCBS_ERASECALLLINKAGEID);
CONF_Ind[0] = 7;
CONF_Ind[3] = 4;
CONF_Ind[6] = 0;
CONF_Ind[7] = 0;
break;
}
w = pty_cai[6];
PUT_WORD(&CONF_Ind[4], w); /* PartyID */
if (plci->appl && (a->Notification_Mask[plci->appl->Id - 1] & SMASK_CCBS))
{
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, CONF_Ind);
}
else
{
for (i = 0; i < max_appl; i++)
if (a->Notification_Mask[i] & SMASK_CCBS)
sendf(&application[i], _FACILITY_I, Id & 0x7, 0, "ws", 3, CONF_Ind);
}
break;
}
break;
case CALL_HOLD_REJ:
cau = parms[7];
if (cau)
{
i = _L3_CAUSE | cau[2];
if (cau[2] == 0) i = 0x3603;
}
else
{
i = 0x3603;
}
PUT_WORD(&SS_Ind[1], S_HOLD);
PUT_WORD(&SS_Ind[4], i);
if (plci->SuppState == HOLD_REQUEST)
{
plci->SuppState = IDLE;
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
}
break;
case CALL_HOLD_ACK:
if (plci->SuppState == HOLD_REQUEST)
{
plci->SuppState = CALL_HELD;
CodecIdCheck(a, plci);
start_internal_command(Id, plci, hold_save_command);
}
break;
case CALL_RETRIEVE_REJ:
cau = parms[7];
if (cau)
{
i = _L3_CAUSE | cau[2];
if (cau[2] == 0) i = 0x3603;
}
else
{
i = 0x3603;
}
PUT_WORD(&SS_Ind[1], S_RETRIEVE);
PUT_WORD(&SS_Ind[4], i);
if (plci->SuppState == RETRIEVE_REQUEST)
{
plci->SuppState = CALL_HELD;
CodecIdCheck(a, plci);
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
}
break;
case CALL_RETRIEVE_ACK:
PUT_WORD(&SS_Ind[1], S_RETRIEVE);
if (plci->SuppState == RETRIEVE_REQUEST)
{
plci->SuppState = IDLE;
plci->call_dir |= CALL_DIR_FORCE_OUTG_NL;
plci->b_channel = esc_chi[esc_chi[0]]&0x1f;
if (plci->tel)
{
mixer_set_bchannel_id_esc(plci, plci->b_channel);
dbug(1, dprintf("RetrChannel=0x%x", plci->b_channel));
SetVoiceChannel(a->AdvCodecPLCI, esc_chi, a);
if (plci->B2_prot == B2_TRANSPARENT && plci->B3_prot == B3_TRANSPARENT)
{
dbug(1, dprintf("Get B-ch"));
start_internal_command(Id, plci, retrieve_restore_command);
}
else
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", 3, SS_Ind);
}
else
start_internal_command(Id, plci, retrieve_restore_command);
}
break;
case INDICATE_IND:
if (plci->State != LISTENING) {
sig_req(plci, HANGUP, 0);
send_req(plci);
break;
}
cip = find_cip(a, parms[4], parms[6]);
cip_mask = 1L << cip;
dbug(1, dprintf("cip=%d,cip_mask=%lx", cip, cip_mask));
clear_c_ind_mask(plci);
if (!remove_started && !a->adapter_disabled)
{
set_c_ind_mask_bit(plci, MAX_APPL);
group_optimization(a, plci);
for (i = 0; i < max_appl; i++) {
if (application[i].Id
&& (a->CIP_Mask[i] & 1 || a->CIP_Mask[i] & cip_mask)
&& CPN_filter_ok(parms[0], a, i)
&& test_group_ind_mask_bit(plci, i)) {
dbug(1, dprintf("storedcip_mask[%d]=0x%lx", i, a->CIP_Mask[i]));
set_c_ind_mask_bit(plci, i);
dump_c_ind_mask(plci);
plci->State = INC_CON_PENDING;
plci->call_dir = (plci->call_dir & ~(CALL_DIR_OUT | CALL_DIR_ORIGINATE)) |
CALL_DIR_IN | CALL_DIR_ANSWER;
if (esc_chi[0]) {
plci->b_channel = esc_chi[esc_chi[0]] & 0x1f;
mixer_set_bchannel_id_esc(plci, plci->b_channel);
}
/* if a listen on the ext controller is done, check if hook states */
/* are supported or if just a on board codec must be activated */
if (a->codec_listen[i] && !a->AdvSignalPLCI) {
if (a->profile.Global_Options & HANDSET)
plci->tel = ADV_VOICE;
else if (a->profile.Global_Options & ON_BOARD_CODEC)
plci->tel = CODEC;
if (plci->tel) Id |= EXT_CONTROLLER;
a->codec_listen[i] = plci;
}
sendf(&application[i], _CONNECT_I, Id, 0,
"wSSSSSSSbSSSSS", cip, /* CIP */
parms[0], /* CalledPartyNumber */
multi_CiPN_parms[0], /* CallingPartyNumber */
parms[2], /* CalledPartySubad */
parms[3], /* CallingPartySubad */
parms[4], /* BearerCapability */
parms[5], /* LowLC */
parms[6], /* HighLC */
ai_len, /* nested struct add_i */
add_i[0], /* B channel info */
add_i[1], /* keypad facility */
add_i[2], /* user user data */
add_i[3], /* nested facility */
multi_CiPN_parms[1] /* second CiPN(SCR) */
);
SendSSExtInd(&application[i],
plci,
Id,
multi_ssext_parms);
SendSetupInfo(&application[i],
plci,
Id,
parms,
SendMultiIE(plci, Id, multi_pi_parms, PI, 0x210, true));
}
}
clear_c_ind_mask_bit(plci, MAX_APPL);
dump_c_ind_mask(plci);
}
if (c_ind_mask_empty(plci)) {
sig_req(plci, HANGUP, 0);
send_req(plci);
plci->State = IDLE;
}
plci->notifiedcall = 0;
a->listen_active--;
listen_check(a);
break;
case CALL_PEND_NOTIFY:
plci->notifiedcall = 1;
listen_check(a);
break;
case CALL_IND:
case CALL_CON:
if (plci->State == ADVANCED_VOICE_SIG || plci->State == ADVANCED_VOICE_NOSIG)
{
if (plci->internal_command == PERM_COD_CONN_PEND)
{
if (plci->State == ADVANCED_VOICE_NOSIG)
{
dbug(1, dprintf("***Codec OK"));
if (a->AdvSignalPLCI)
{
tplci = a->AdvSignalPLCI;
if (tplci->spoofed_msg)
{
dbug(1, dprintf("***Spoofed Msg(0x%x)", tplci->spoofed_msg));
tplci->command = 0;
tplci->internal_command = 0;
x_Id = ((word)tplci->Id << 8) | tplci->adapter->Id | 0x80;
switch (tplci->spoofed_msg)
{
case CALL_RES:
tplci->command = _CONNECT_I | RESPONSE;
api_load_msg(&tplci->saved_msg, saved_parms);
add_b1(tplci, &saved_parms[1], 0, tplci->B1_facilities);
if (tplci->adapter->Info_Mask[tplci->appl->Id - 1] & 0x200)
{
/* early B3 connect (CIP mask bit 9) no release after a disc */
add_p(tplci, LLI, "\x01\x01");
}
add_s(tplci, CONN_NR, &saved_parms[2]);
add_s(tplci, LLC, &saved_parms[4]);
add_ai(tplci, &saved_parms[5]);
tplci->State = INC_CON_ACCEPT;
sig_req(tplci, CALL_RES, 0);
send_req(tplci);
break;
case AWAITING_SELECT_B:
dbug(1, dprintf("Select_B continue"));
start_internal_command(x_Id, tplci, select_b_command);
break;
case AWAITING_MANUF_CON: /* Get_Plci per Manufacturer_Req to ext controller */
if (!tplci->Sig.Id)
{
dbug(1, dprintf("No SigID!"));
sendf(tplci->appl, _MANUFACTURER_R | CONFIRM, x_Id, tplci->number, "dww", _DI_MANU_ID, _MANUFACTURER_R, _OUT_OF_PLCI);
plci_remove(tplci);
break;
}
tplci->command = _MANUFACTURER_R;
api_load_msg(&tplci->saved_msg, saved_parms);
dir = saved_parms[2].info[0];
if (dir == 1) {
sig_req(tplci, CALL_REQ, 0);
}
else if (!dir) {
sig_req(tplci, LISTEN_REQ, 0);
}
send_req(tplci);
sendf(tplci->appl, _MANUFACTURER_R | CONFIRM, x_Id, tplci->number, "dww", _DI_MANU_ID, _MANUFACTURER_R, 0);
break;
case (CALL_REQ | AWAITING_MANUF_CON):
sig_req(tplci, CALL_REQ, 0);
send_req(tplci);
break;
case CALL_REQ:
if (!tplci->Sig.Id)
{
dbug(1, dprintf("No SigID!"));
sendf(tplci->appl, _CONNECT_R | CONFIRM, tplci->adapter->Id, 0, "w", _OUT_OF_PLCI);
plci_remove(tplci);
break;
}
tplci->command = _CONNECT_R;
api_load_msg(&tplci->saved_msg, saved_parms);
add_s(tplci, CPN, &saved_parms[1]);
add_s(tplci, DSA, &saved_parms[3]);
add_ai(tplci, &saved_parms[9]);
sig_req(tplci, CALL_REQ, 0);
send_req(tplci);
break;
case CALL_RETRIEVE:
tplci->command = C_RETRIEVE_REQ;
sig_req(tplci, CALL_RETRIEVE, 0);
send_req(tplci);
break;
}
tplci->spoofed_msg = 0;
if (tplci->internal_command == 0)
next_internal_command(x_Id, tplci);
}
}
next_internal_command(Id, plci);
break;
}
dbug(1, dprintf("***Codec Hook Init Req"));
plci->internal_command = PERM_COD_HOOK;
add_p(plci, FTY, "\x01\x09"); /* Get Hook State*/
sig_req(plci, TEL_CTRL, 0);
send_req(plci);
}
}
else if (plci->command != _MANUFACTURER_R /* old style permanent connect */
&& plci->State != INC_ACT_PENDING)
{
mixer_set_bchannel_id_esc(plci, plci->b_channel);
if (plci->tel == ADV_VOICE && plci->SuppState == IDLE) /* with permanent codec switch on immediately */
{
chi[2] = plci->b_channel;
SetVoiceChannel(a->AdvCodecPLCI, chi, a);
}
sendf(plci->appl, _CONNECT_ACTIVE_I, Id, 0, "Sss", parms[21], "", "");
plci->State = INC_ACT_PENDING;
}
break;
case TEL_CTRL:
ie = multi_fac_parms[0]; /* inspect the facility hook indications */
if (plci->State == ADVANCED_VOICE_SIG && ie[0]) {
switch (ie[1] & 0x91) {
case 0x80: /* hook off */
case 0x81:
if (plci->internal_command == PERM_COD_HOOK)
{
dbug(1, dprintf("init:hook_off"));
plci->hook_state = ie[1];
next_internal_command(Id, plci);
break;
}
else /* ignore doubled hook indications */
{
if (((plci->hook_state) & 0xf0) == 0x80)
{
dbug(1, dprintf("ignore hook"));
break;
}
plci->hook_state = ie[1]&0x91;
}
/* check for incoming call pending */
/* and signal '+'.Appl must decide */
/* with connect_res if call must */
/* accepted or not */
for (i = 0, tplci = NULL; i < max_appl; i++) {
if (a->codec_listen[i]
&& (a->codec_listen[i]->State == INC_CON_PENDING
|| a->codec_listen[i]->State == INC_CON_ALERT)) {
tplci = a->codec_listen[i];
tplci->appl = &application[i];
}
}
/* no incoming call, do outgoing call */
/* and signal '+' if outg. setup */
if (!a->AdvSignalPLCI && !tplci) {
if ((i = get_plci(a))) {
a->AdvSignalPLCI = &a->plci[i - 1];
tplci = a->AdvSignalPLCI;
tplci->tel = ADV_VOICE;
PUT_WORD(&voice_cai[5], a->AdvSignalAppl->MaxDataLength);
if (a->Info_Mask[a->AdvSignalAppl->Id - 1] & 0x200) {
/* early B3 connect (CIP mask bit 9) no release after a disc */
add_p(tplci, LLI, "\x01\x01");
}
add_p(tplci, CAI, voice_cai);
add_p(tplci, OAD, a->TelOAD);
add_p(tplci, OSA, a->TelOSA);
add_p(tplci, SHIFT | 6, NULL);
add_p(tplci, SIN, "\x02\x01\x00");
add_p(tplci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(tplci, ASSIGN, DSIG_ID);
a->AdvSignalPLCI->internal_command = HOOK_OFF_REQ;
a->AdvSignalPLCI->command = 0;
tplci->appl = a->AdvSignalAppl;
tplci->call_dir = CALL_DIR_OUT | CALL_DIR_ORIGINATE;
send_req(tplci);
}
}
if (!tplci) break;
Id = ((word)tplci->Id << 8) | a->Id;
Id |= EXT_CONTROLLER;
sendf(tplci->appl,
_FACILITY_I,
Id,
0,
"ws", (word)0, "\x01+");
break;
case 0x90: /* hook on */
case 0x91:
if (plci->internal_command == PERM_COD_HOOK)
{
dbug(1, dprintf("init:hook_on"));
plci->hook_state = ie[1] & 0x91;
next_internal_command(Id, plci);
break;
}
else /* ignore doubled hook indications */
{
if (((plci->hook_state) & 0xf0) == 0x90) break;
plci->hook_state = ie[1] & 0x91;
}
/* hangup the adv. voice call and signal '-' to the appl */
if (a->AdvSignalPLCI) {
Id = ((word)a->AdvSignalPLCI->Id << 8) | a->Id;
if (plci->tel) Id |= EXT_CONTROLLER;
sendf(a->AdvSignalAppl,
_FACILITY_I,
Id,
0,
"ws", (word)0, "\x01-");
a->AdvSignalPLCI->internal_command = HOOK_ON_REQ;
a->AdvSignalPLCI->command = 0;
sig_req(a->AdvSignalPLCI, HANGUP, 0);
send_req(a->AdvSignalPLCI);
}
break;
}
}
break;
case RESUME:
clear_c_ind_mask_bit(plci, (word)(plci->appl->Id - 1));
PUT_WORD(&resume_cau[4], GOOD);
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", (word)3, resume_cau);
break;
case SUSPEND:
clear_c_ind_mask(plci);
if (plci->NL.Id && !plci->nl_remove_id) {
mixer_remove(plci);
nl_req_ncci(plci, REMOVE, 0);
}
if (!plci->sig_remove_id) {
plci->internal_command = 0;
sig_req(plci, REMOVE, 0);
}
send_req(plci);
if (!plci->channels) {
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", (word)3, "\x05\x04\x00\x02\x00\x00");
sendf(plci->appl, _DISCONNECT_I, Id, 0, "w", 0);
}
break;
case SUSPEND_REJ:
break;
case HANGUP:
plci->hangup_flow_ctrl_timer = 0;
if (plci->manufacturer && plci->State == LOCAL_CONNECT) break;
cau = parms[7];
if (cau) {
i = _L3_CAUSE | cau[2];
if (cau[2] == 0) i = 0;
else if (cau[2] == 8) i = _L1_ERROR;
else if (cau[2] == 9 || cau[2] == 10) i = _L2_ERROR;
else if (cau[2] == 5) i = _CAPI_GUARD_ERROR;
}
else {
i = _L3_ERROR;
}
if (plci->State == INC_CON_PENDING || plci->State == INC_CON_ALERT)
{
for (i = 0; i < max_appl; i++)
{
if (test_c_ind_mask_bit(plci, i))
sendf(&application[i], _DISCONNECT_I, Id, 0, "w", 0);
}
}
else
{
clear_c_ind_mask(plci);
}
if (!plci->appl)
{
if (plci->State == LISTENING)
{
plci->notifiedcall = 0;
a->listen_active--;
}
plci->State = INC_DIS_PENDING;
if (c_ind_mask_empty(plci))
{
plci->State = IDLE;
if (plci->NL.Id && !plci->nl_remove_id)
{
mixer_remove(plci);
nl_req_ncci(plci, REMOVE, 0);
}
if (!plci->sig_remove_id)
{
plci->internal_command = 0;
sig_req(plci, REMOVE, 0);
}
send_req(plci);
}
}
else
{
/* collision of DISCONNECT or CONNECT_RES with HANGUP can */
/* result in a second HANGUP! Don't generate another */
/* DISCONNECT */
if (plci->State != IDLE && plci->State != INC_DIS_PENDING)
{
if (plci->State == RESUMING)
{
PUT_WORD(&resume_cau[4], i);
sendf(plci->appl, _FACILITY_I, Id, 0, "ws", (word)3, resume_cau);
}
plci->State = INC_DIS_PENDING;
sendf(plci->appl, _DISCONNECT_I, Id, 0, "w", i);
}
}
break;
case SSEXT_IND:
SendSSExtInd(NULL, plci, Id, multi_ssext_parms);
break;
case VSWITCH_REQ:
VSwitchReqInd(plci, Id, multi_vswitch_parms);
break;
case VSWITCH_IND:
if (plci->relatedPTYPLCI &&
plci->vswitchstate == 3 &&
plci->relatedPTYPLCI->vswitchstate == 3 &&
parms[MAXPARMSIDS - 1][0])
{
add_p(plci->relatedPTYPLCI, SMSG, parms[MAXPARMSIDS - 1]);
sig_req(plci->relatedPTYPLCI, VSWITCH_REQ, 0);
send_req(plci->relatedPTYPLCI);
}
else VSwitchReqInd(plci, Id, multi_vswitch_parms);
break;
}
}
static void SendSetupInfo(APPL *appl, PLCI *plci, dword Id, byte **parms, byte Info_Sent_Flag)
{
word i;
byte *ie;
word Info_Number;
byte *Info_Element;
word Info_Mask = 0;
dbug(1, dprintf("SetupInfo"));
for (i = 0; i < MAXPARMSIDS; i++) {
ie = parms[i];
Info_Number = 0;
Info_Element = ie;
if (ie[0]) {
switch (i) {
case 0:
dbug(1, dprintf("CPN "));
Info_Number = 0x0070;
Info_Mask = 0x80;
Info_Sent_Flag = true;
break;
case 8: /* display */
dbug(1, dprintf("display(%d)", i));
Info_Number = 0x0028;
Info_Mask = 0x04;
Info_Sent_Flag = true;
break;
case 16: /* Channel Id */
dbug(1, dprintf("CHI"));
Info_Number = 0x0018;
Info_Mask = 0x100;
Info_Sent_Flag = true;
mixer_set_bchannel_id(plci, Info_Element);
break;
case 19: /* Redirected Number */
dbug(1, dprintf("RDN"));
Info_Number = 0x0074;
Info_Mask = 0x400;
Info_Sent_Flag = true;
break;
case 20: /* Redirected Number extended */
dbug(1, dprintf("RDX"));
Info_Number = 0x0073;
Info_Mask = 0x400;
Info_Sent_Flag = true;
break;
case 22: /* Redirecing Number */
dbug(1, dprintf("RIN"));
Info_Number = 0x0076;
Info_Mask = 0x400;
Info_Sent_Flag = true;
break;
default:
Info_Number = 0;
break;
}
}
if (i == MAXPARMSIDS - 2) { /* to indicate the message type "Setup" */
Info_Number = 0x8000 | 5;
Info_Mask = 0x10;
Info_Element = "";
}
if (Info_Sent_Flag && Info_Number) {
if (plci->adapter->Info_Mask[appl->Id - 1] & Info_Mask) {
sendf(appl, _INFO_I, Id, 0, "wS", Info_Number, Info_Element);
}
}
}
}
static void SendInfo(PLCI *plci, dword Id, byte **parms, byte iesent)
{
word i;
word j;
word k;
byte *ie;
word Info_Number;
byte *Info_Element;
word Info_Mask = 0;
static byte charges[5] = {4, 0, 0, 0, 0};
static byte cause[] = {0x02, 0x80, 0x00};
APPL *appl;
dbug(1, dprintf("InfoParse "));
if (
!plci->appl
&& !plci->State
&& plci->Sig.Ind != NCR_FACILITY
)
{
dbug(1, dprintf("NoParse "));
return;
}
cause[2] = 0;
for (i = 0; i < MAXPARMSIDS; i++) {
ie = parms[i];
Info_Number = 0;
Info_Element = ie;
if (ie[0]) {
switch (i) {
case 0:
dbug(1, dprintf("CPN "));
Info_Number = 0x0070;
Info_Mask = 0x80;
break;
case 7: /* ESC_CAU */
dbug(1, dprintf("cau(0x%x)", ie[2]));
Info_Number = 0x0008;
Info_Mask = 0x00;
cause[2] = ie[2];
Info_Element = NULL;
break;
case 8: /* display */
dbug(1, dprintf("display(%d)", i));
Info_Number = 0x0028;
Info_Mask = 0x04;
break;
case 9: /* Date display */
dbug(1, dprintf("date(%d)", i));
Info_Number = 0x0029;
Info_Mask = 0x02;
break;
case 10: /* charges */
for (j = 0; j < 4; j++) charges[1 + j] = 0;
for (j = 0; j < ie[0] && !(ie[1 + j] & 0x80); j++);
for (k = 1, j++; j < ie[0] && k <= 4; j++, k++) charges[k] = ie[1 + j];
Info_Number = 0x4000;
Info_Mask = 0x40;
Info_Element = charges;
break;
case 11: /* user user info */
dbug(1, dprintf("uui"));
Info_Number = 0x007E;
Info_Mask = 0x08;
break;
case 12: /* congestion receiver ready */
dbug(1, dprintf("clRDY"));
Info_Number = 0x00B0;
Info_Mask = 0x08;
Info_Element = "";
break;
case 13: /* congestion receiver not ready */
dbug(1, dprintf("clNRDY"));
Info_Number = 0x00BF;
Info_Mask = 0x08;
Info_Element = "";
break;
case 15: /* Keypad Facility */
dbug(1, dprintf("KEY"));
Info_Number = 0x002C;
Info_Mask = 0x20;
break;
case 16: /* Channel Id */
dbug(1, dprintf("CHI"));
Info_Number = 0x0018;
Info_Mask = 0x100;
mixer_set_bchannel_id(plci, Info_Element);
break;
case 17: /* if no 1tr6 cause, send full cause, else esc_cause */
dbug(1, dprintf("q9cau(0x%x)", ie[2]));
if (!cause[2] || cause[2] < 0x80) break; /* eg. layer 1 error */
Info_Number = 0x0008;
Info_Mask = 0x01;
if (cause[2] != ie[2]) Info_Element = cause;
break;
case 19: /* Redirected Number */
dbug(1, dprintf("RDN"));
Info_Number = 0x0074;
Info_Mask = 0x400;
break;
case 22: /* Redirecing Number */
dbug(1, dprintf("RIN"));
Info_Number = 0x0076;
Info_Mask = 0x400;
break;
case 23: /* Notification Indicator */
dbug(1, dprintf("NI"));
Info_Number = (word)NI;
Info_Mask = 0x210;
break;
case 26: /* Call State */
dbug(1, dprintf("CST"));
Info_Number = (word)CST;
Info_Mask = 0x01; /* do with cause i.e. for now */
break;
case MAXPARMSIDS - 2: /* Escape Message Type, must be the last indication */
dbug(1, dprintf("ESC/MT[0x%x]", ie[3]));
Info_Number = 0x8000 | ie[3];
if (iesent) Info_Mask = 0xffff;
else Info_Mask = 0x10;
Info_Element = "";
break;
default:
Info_Number = 0;
Info_Mask = 0;
Info_Element = "";
break;
}
}
if (plci->Sig.Ind == NCR_FACILITY) /* check controller broadcast */
{
for (j = 0; j < max_appl; j++)
{
appl = &application[j];
if (Info_Number
&& appl->Id
&& plci->adapter->Info_Mask[appl->Id - 1] & Info_Mask)
{
dbug(1, dprintf("NCR_Ind"));
iesent = true;
sendf(&application[j], _INFO_I, Id & 0x0f, 0, "wS", Info_Number, Info_Element);
}
}
}
else if (!plci->appl)
{ /* overlap receiving broadcast */
if (Info_Number == CPN
|| Info_Number == KEY
|| Info_Number == NI
|| Info_Number == DSP
|| Info_Number == UUI)
{
for (j = 0; j < max_appl; j++)
{
if (test_c_ind_mask_bit(plci, j))
{
dbug(1, dprintf("Ovl_Ind"));
iesent = true;
sendf(&application[j], _INFO_I, Id, 0, "wS", Info_Number, Info_Element);
}
}
}
} /* all other signalling states */
else if (Info_Number
&& plci->adapter->Info_Mask[plci->appl->Id - 1] & Info_Mask)
{
dbug(1, dprintf("Std_Ind"));
iesent = true;
sendf(plci->appl, _INFO_I, Id, 0, "wS", Info_Number, Info_Element);
}
}
}
static byte SendMultiIE(PLCI *plci, dword Id, byte **parms, byte ie_type,
dword info_mask, byte setupParse)
{
word i;
word j;
byte *ie;
word Info_Number;
byte *Info_Element;
APPL *appl;
word Info_Mask = 0;
byte iesent = 0;
if (
!plci->appl
&& !plci->State
&& plci->Sig.Ind != NCR_FACILITY
&& !setupParse
)
{
dbug(1, dprintf("NoM-IEParse "));
return 0;
}
dbug(1, dprintf("M-IEParse "));
for (i = 0; i < MAX_MULTI_IE; i++)
{
ie = parms[i];
Info_Number = 0;
Info_Element = ie;
if (ie[0])
{
dbug(1, dprintf("[Ind0x%x]:IE=0x%x", plci->Sig.Ind, ie_type));
Info_Number = (word)ie_type;
Info_Mask = (word)info_mask;
}
if (plci->Sig.Ind == NCR_FACILITY) /* check controller broadcast */
{
for (j = 0; j < max_appl; j++)
{
appl = &application[j];
if (Info_Number
&& appl->Id
&& plci->adapter->Info_Mask[appl->Id - 1] & Info_Mask)
{
iesent = true;
dbug(1, dprintf("Mlt_NCR_Ind"));
sendf(&application[j], _INFO_I, Id & 0x0f, 0, "wS", Info_Number, Info_Element);
}
}
}
else if (!plci->appl && Info_Number)
{ /* overlap receiving broadcast */
for (j = 0; j < max_appl; j++)
{
if (test_c_ind_mask_bit(plci, j))
{
iesent = true;
dbug(1, dprintf("Mlt_Ovl_Ind"));
sendf(&application[j] , _INFO_I, Id, 0, "wS", Info_Number, Info_Element);
}
}
} /* all other signalling states */
else if (Info_Number
&& plci->adapter->Info_Mask[plci->appl->Id - 1] & Info_Mask)
{
iesent = true;
dbug(1, dprintf("Mlt_Std_Ind"));
sendf(plci->appl, _INFO_I, Id, 0, "wS", Info_Number, Info_Element);
}
}
return iesent;
}
static void SendSSExtInd(APPL *appl, PLCI *plci, dword Id, byte **parms)
{
word i;
/* Format of multi_ssext_parms[i][]:
0 byte length
1 byte SSEXTIE
2 byte SSEXT_REQ/SSEXT_IND
3 byte length
4 word SSExtCommand
6... Params
*/
if (
plci
&& plci->State
&& plci->Sig.Ind != NCR_FACILITY
)
for (i = 0; i < MAX_MULTI_IE; i++)
{
if (parms[i][0] < 6) continue;
if (parms[i][2] == SSEXT_REQ) continue;
if (appl)
{
parms[i][0] = 0; /* kill it */
sendf(appl, _MANUFACTURER_I,
Id,
0,
"dwS",
_DI_MANU_ID,
_DI_SSEXT_CTRL,
&parms[i][3]);
}
else if (plci->appl)
{
parms[i][0] = 0; /* kill it */
sendf(plci->appl, _MANUFACTURER_I,
Id,
0,
"dwS",
_DI_MANU_ID,
_DI_SSEXT_CTRL,
&parms[i][3]);
}
}
};
static void nl_ind(PLCI *plci)
{
byte ch;
word ncci;
dword Id;
DIVA_CAPI_ADAPTER *a;
word NCCIcode;
APPL *APPLptr;
word count;
word Num;
word i, ncpi_state;
byte len, ncci_state;
word msg;
word info = 0;
word fax_feature_bits;
byte fax_send_edata_ack;
static byte v120_header_buffer[2 + 3];
static word fax_info[] = {
0, /* T30_SUCCESS */
_FAX_NO_CONNECTION, /* T30_ERR_NO_DIS_RECEIVED */
_FAX_PROTOCOL_ERROR, /* T30_ERR_TIMEOUT_NO_RESPONSE */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_RESPONSE */
_FAX_PROTOCOL_ERROR, /* T30_ERR_TOO_MANY_REPEATS */
_FAX_PROTOCOL_ERROR, /* T30_ERR_UNEXPECTED_MESSAGE */
_FAX_REMOTE_ABORT, /* T30_ERR_UNEXPECTED_DCN */
_FAX_LOCAL_ABORT, /* T30_ERR_DTC_UNSUPPORTED */
_FAX_TRAINING_ERROR, /* T30_ERR_ALL_RATES_FAILED */
_FAX_TRAINING_ERROR, /* T30_ERR_TOO_MANY_TRAINS */
_FAX_PARAMETER_ERROR, /* T30_ERR_RECEIVE_CORRUPTED */
_FAX_REMOTE_ABORT, /* T30_ERR_UNEXPECTED_DISC */
_FAX_LOCAL_ABORT, /* T30_ERR_APPLICATION_DISC */
_FAX_REMOTE_REJECT, /* T30_ERR_INCOMPATIBLE_DIS */
_FAX_LOCAL_ABORT, /* T30_ERR_INCOMPATIBLE_DCS */
_FAX_PROTOCOL_ERROR, /* T30_ERR_TIMEOUT_NO_COMMAND */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_COMMAND */
_FAX_PROTOCOL_ERROR, /* T30_ERR_TIMEOUT_COMMAND_TOO_LONG */
_FAX_PROTOCOL_ERROR, /* T30_ERR_TIMEOUT_RESPONSE_TOO_LONG */
_FAX_NO_CONNECTION, /* T30_ERR_NOT_IDENTIFIED */
_FAX_PROTOCOL_ERROR, /* T30_ERR_SUPERVISORY_TIMEOUT */
_FAX_PARAMETER_ERROR, /* T30_ERR_TOO_LONG_SCAN_LINE */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_PAGE_AFTER_MPS */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_PAGE_AFTER_CFR */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_DCS_AFTER_FTT */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_DCS_AFTER_EOM */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_DCS_AFTER_MPS */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_DCN_AFTER_MCF */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_DCN_AFTER_RTN */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_CFR */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_MCF_AFTER_EOP */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_MCF_AFTER_EOM */
_FAX_PROTOCOL_ERROR, /* T30_ERR_RETRY_NO_MCF_AFTER_MPS */
0x331d, /* T30_ERR_SUB_SEP_UNSUPPORTED */
0x331e, /* T30_ERR_PWD_UNSUPPORTED */
0x331f, /* T30_ERR_SUB_SEP_PWD_UNSUPPORTED */
_FAX_PROTOCOL_ERROR, /* T30_ERR_INVALID_COMMAND_FRAME */
_FAX_PARAMETER_ERROR, /* T30_ERR_UNSUPPORTED_PAGE_CODING */
_FAX_PARAMETER_ERROR, /* T30_ERR_INVALID_PAGE_CODING */
_FAX_REMOTE_REJECT, /* T30_ERR_INCOMPATIBLE_PAGE_CONFIG */
_FAX_LOCAL_ABORT, /* T30_ERR_TIMEOUT_FROM_APPLICATION */
_FAX_PROTOCOL_ERROR, /* T30_ERR_V34FAX_NO_REACTION_ON_MARK */
_FAX_PROTOCOL_ERROR, /* T30_ERR_V34FAX_TRAINING_TIMEOUT */
_FAX_PROTOCOL_ERROR, /* T30_ERR_V34FAX_UNEXPECTED_V21 */
_FAX_PROTOCOL_ERROR, /* T30_ERR_V34FAX_PRIMARY_CTS_ON */
_FAX_LOCAL_ABORT, /* T30_ERR_V34FAX_TURNAROUND_POLLING */
_FAX_LOCAL_ABORT /* T30_ERR_V34FAX_V8_INCOMPATIBILITY */
};
byte dtmf_code_buffer[CAPIDTMF_RECV_DIGIT_BUFFER_SIZE + 1];
static word rtp_info[] = {
GOOD, /* RTP_SUCCESS */
0x3600 /* RTP_ERR_SSRC_OR_PAYLOAD_CHANGE */
};
static dword udata_forwarding_table[0x100 / sizeof(dword)] =
{
0x0020301e, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000
};
ch = plci->NL.IndCh;
a = plci->adapter;
ncci = a->ch_ncci[ch];
Id = (((dword)(ncci ? ncci : ch)) << 16) | (((word) plci->Id) << 8) | a->Id;
if (plci->tel) Id |= EXT_CONTROLLER;
APPLptr = plci->appl;
dbug(1, dprintf("NL_IND-Id(NL:0x%x)=0x%08lx,plci=%x,tel=%x,state=0x%x,ch=0x%x,chs=%d,Ind=%x",
plci->NL.Id, Id, plci->Id, plci->tel, plci->State, ch, plci->channels, plci->NL.Ind & 0x0f));
/* in the case if no connect_active_Ind was sent to the appl we wait for */
if (plci->nl_remove_id)
{
plci->NL.RNR = 2; /* discard */
dbug(1, dprintf("NL discard while remove pending"));
return;
}
if ((plci->NL.Ind & 0x0f) == N_CONNECT)
{
if (plci->State == INC_DIS_PENDING
|| plci->State == OUTG_DIS_PENDING
|| plci->State == IDLE)
{
plci->NL.RNR = 2; /* discard */
dbug(1, dprintf("discard n_connect"));
return;
}
if (plci->State < INC_ACT_PENDING)
{
plci->NL.RNR = 1; /* flow control */
channel_x_off(plci, ch, N_XON_CONNECT_IND);
return;
}
}
if (!APPLptr) /* no application or invalid data */
{ /* while reloading the DSP */
dbug(1, dprintf("discard1"));
plci->NL.RNR = 2;
return;
}
if (((plci->NL.Ind & 0x0f) == N_UDATA)
&& (((plci->B2_prot != B2_SDLC) && ((plci->B1_resource == 17) || (plci->B1_resource == 18)))
|| (plci->B2_prot == 7)
|| (plci->B3_prot == 7)))
{
plci->ncpi_buffer[0] = 0;
ncpi_state = plci->ncpi_state;
if (plci->NL.complete == 1)
{
byte *data = &plci->NL.RBuffer->P[0];
if ((plci->NL.RBuffer->length >= 12)
&& ((*data == DSP_UDATA_INDICATION_DCD_ON)
|| (*data == DSP_UDATA_INDICATION_CTS_ON)))
{
word conn_opt, ncpi_opt = 0x00;
/* HexDump ("MDM N_UDATA:", plci->NL.RBuffer->length, data); */
if (*data == DSP_UDATA_INDICATION_DCD_ON)
plci->ncpi_state |= NCPI_MDM_DCD_ON_RECEIVED;
if (*data == DSP_UDATA_INDICATION_CTS_ON)
plci->ncpi_state |= NCPI_MDM_CTS_ON_RECEIVED;
data++; /* indication code */
data += 2; /* timestamp */
if ((*data == DSP_CONNECTED_NORM_V18) || (*data == DSP_CONNECTED_NORM_VOWN))
ncpi_state &= ~(NCPI_MDM_DCD_ON_RECEIVED | NCPI_MDM_CTS_ON_RECEIVED);
data++; /* connected norm */
conn_opt = GET_WORD(data);
data += 2; /* connected options */
PUT_WORD(&(plci->ncpi_buffer[1]), (word)(GET_DWORD(data) & 0x0000FFFF));
if (conn_opt & DSP_CONNECTED_OPTION_MASK_V42)
{
ncpi_opt |= MDM_NCPI_ECM_V42;
}
else if (conn_opt & DSP_CONNECTED_OPTION_MASK_MNP)
{
ncpi_opt |= MDM_NCPI_ECM_MNP;
}
else
{
ncpi_opt |= MDM_NCPI_TRANSPARENT;
}
if (conn_opt & DSP_CONNECTED_OPTION_MASK_COMPRESSION)
{
ncpi_opt |= MDM_NCPI_COMPRESSED;
}
PUT_WORD(&(plci->ncpi_buffer[3]), ncpi_opt);
plci->ncpi_buffer[0] = 4;
plci->ncpi_state |= NCPI_VALID_CONNECT_B3_IND | NCPI_VALID_CONNECT_B3_ACT | NCPI_VALID_DISC_B3_IND;
}
}
if (plci->B3_prot == 7)
{
if (((a->ncci_state[ncci] == INC_ACT_PENDING) || (a->ncci_state[ncci] == OUTG_CON_PENDING))
&& (plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
a->ncci_state[ncci] = INC_ACT_PENDING;
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
}
if (!((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[plci->appl->Id - 1])
& ((1L << PRIVATE_V18) | (1L << PRIVATE_VOWN)))
|| !(ncpi_state & NCPI_MDM_DCD_ON_RECEIVED)
|| !(ncpi_state & NCPI_MDM_CTS_ON_RECEIVED))
{
plci->NL.RNR = 2;
return;
}
}
if (plci->NL.complete == 2)
{
if (((plci->NL.Ind & 0x0f) == N_UDATA)
&& !(udata_forwarding_table[plci->RData[0].P[0] >> 5] & (1L << (plci->RData[0].P[0] & 0x1f))))
{
switch (plci->RData[0].P[0])
{
case DTMF_UDATA_INDICATION_FAX_CALLING_TONE:
if (plci->dtmf_rec_active & DTMF_LISTEN_ACTIVE_FLAG)
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0, "ws", SELECTOR_DTMF, "\x01X");
break;
case DTMF_UDATA_INDICATION_ANSWER_TONE:
if (plci->dtmf_rec_active & DTMF_LISTEN_ACTIVE_FLAG)
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0, "ws", SELECTOR_DTMF, "\x01Y");
break;
case DTMF_UDATA_INDICATION_DIGITS_RECEIVED:
dtmf_indication(Id, plci, plci->RData[0].P, plci->RData[0].PLength);
break;
case DTMF_UDATA_INDICATION_DIGITS_SENT:
dtmf_confirmation(Id, plci);
break;
case UDATA_INDICATION_MIXER_TAP_DATA:
capidtmf_recv_process_block(&(plci->capidtmf_state), plci->RData[0].P + 1, (word)(plci->RData[0].PLength - 1));
i = capidtmf_indication(&(plci->capidtmf_state), dtmf_code_buffer + 1);
if (i != 0)
{
dtmf_code_buffer[0] = DTMF_UDATA_INDICATION_DIGITS_RECEIVED;
dtmf_indication(Id, plci, dtmf_code_buffer, (word)(i + 1));
}
break;
case UDATA_INDICATION_MIXER_COEFS_SET:
mixer_indication_coefs_set(Id, plci);
break;
case UDATA_INDICATION_XCONNECT_FROM:
mixer_indication_xconnect_from(Id, plci, plci->RData[0].P, plci->RData[0].PLength);
break;
case UDATA_INDICATION_XCONNECT_TO:
mixer_indication_xconnect_to(Id, plci, plci->RData[0].P, plci->RData[0].PLength);
break;
case LEC_UDATA_INDICATION_DISABLE_DETECT:
ec_indication(Id, plci, plci->RData[0].P, plci->RData[0].PLength);
break;
default:
break;
}
}
else
{
if ((plci->RData[0].PLength != 0)
&& ((plci->B2_prot == B2_V120_ASYNC)
|| (plci->B2_prot == B2_V120_ASYNC_V42BIS)
|| (plci->B2_prot == B2_V120_BIT_TRANSPARENT)))
{
sendf(plci->appl, _DATA_B3_I, Id, 0,
"dwww",
plci->RData[1].P,
(plci->NL.RNum < 2) ? 0 : plci->RData[1].PLength,
plci->RNum,
plci->RFlags);
}
else
{
sendf(plci->appl, _DATA_B3_I, Id, 0,
"dwww",
plci->RData[0].P,
plci->RData[0].PLength,
plci->RNum,
plci->RFlags);
}
}
return;
}
fax_feature_bits = 0;
if ((plci->NL.Ind & 0x0f) == N_CONNECT ||
(plci->NL.Ind & 0x0f) == N_CONNECT_ACK ||
(plci->NL.Ind & 0x0f) == N_DISC ||
(plci->NL.Ind & 0x0f) == N_EDATA ||
(plci->NL.Ind & 0x0f) == N_DISC_ACK)
{
info = 0;
plci->ncpi_buffer[0] = 0;
switch (plci->B3_prot) {
case 0: /*XPARENT*/
case 1: /*T.90 NL*/
break; /* no network control protocol info - jfr */
case 2: /*ISO8202*/
case 3: /*X25 DCE*/
for (i = 0; i < plci->NL.RLength; i++) plci->ncpi_buffer[4 + i] = plci->NL.RBuffer->P[i];
plci->ncpi_buffer[0] = (byte)(i + 3);
plci->ncpi_buffer[1] = (byte)(plci->NL.Ind & N_D_BIT ? 1 : 0);
plci->ncpi_buffer[2] = 0;
plci->ncpi_buffer[3] = 0;
break;
case 4: /*T.30 - FAX*/
case 5: /*T.30 - FAX*/
if (plci->NL.RLength >= sizeof(T30_INFO))
{
dbug(1, dprintf("FaxStatus %04x", ((T30_INFO *)plci->NL.RBuffer->P)->code));
len = 9;
PUT_WORD(&(plci->ncpi_buffer[1]), ((T30_INFO *)plci->NL.RBuffer->P)->rate_div_2400 * 2400);
fax_feature_bits = GET_WORD(&((T30_INFO *)plci->NL.RBuffer->P)->feature_bits_low);
i = (((T30_INFO *)plci->NL.RBuffer->P)->resolution & T30_RESOLUTION_R8_0770_OR_200) ? 0x0001 : 0x0000;
if (plci->B3_prot == 5)
{
if (!(fax_feature_bits & T30_FEATURE_BIT_ECM))
i |= 0x8000; /* This is not an ECM connection */
if (fax_feature_bits & T30_FEATURE_BIT_T6_CODING)
i |= 0x4000; /* This is a connection with MMR compression */
if (fax_feature_bits & T30_FEATURE_BIT_2D_CODING)
i |= 0x2000; /* This is a connection with MR compression */
if (fax_feature_bits & T30_FEATURE_BIT_MORE_DOCUMENTS)
i |= 0x0004; /* More documents */
if (fax_feature_bits & T30_FEATURE_BIT_POLLING)
i |= 0x0002; /* Fax-polling indication */
}
dbug(1, dprintf("FAX Options %04x %04x", fax_feature_bits, i));
PUT_WORD(&(plci->ncpi_buffer[3]), i);
PUT_WORD(&(plci->ncpi_buffer[5]), ((T30_INFO *)plci->NL.RBuffer->P)->data_format);
plci->ncpi_buffer[7] = ((T30_INFO *)plci->NL.RBuffer->P)->pages_low;
plci->ncpi_buffer[8] = ((T30_INFO *)plci->NL.RBuffer->P)->pages_high;
plci->ncpi_buffer[len] = 0;
if (((T30_INFO *)plci->NL.RBuffer->P)->station_id_len)
{
plci->ncpi_buffer[len] = 20;
for (i = 0; i < T30_MAX_STATION_ID_LENGTH; i++)
plci->ncpi_buffer[++len] = ((T30_INFO *)plci->NL.RBuffer->P)->station_id[i];
}
if (((plci->NL.Ind & 0x0f) == N_DISC) || ((plci->NL.Ind & 0x0f) == N_DISC_ACK))
{
if (((T30_INFO *)plci->NL.RBuffer->P)->code < ARRAY_SIZE(fax_info))
info = fax_info[((T30_INFO *)plci->NL.RBuffer->P)->code];
else
info = _FAX_PROTOCOL_ERROR;
}
if ((plci->requested_options_conn | plci->requested_options | a->requested_options_table[plci->appl->Id - 1])
& ((1L << PRIVATE_FAX_SUB_SEP_PWD) | (1L << PRIVATE_FAX_NONSTANDARD)))
{
i = offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + ((T30_INFO *)plci->NL.RBuffer->P)->head_line_len;
while (i < plci->NL.RBuffer->length)
plci->ncpi_buffer[++len] = plci->NL.RBuffer->P[i++];
}
plci->ncpi_buffer[0] = len;
fax_feature_bits = GET_WORD(&((T30_INFO *)plci->NL.RBuffer->P)->feature_bits_low);
PUT_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->feature_bits_low, fax_feature_bits);
plci->ncpi_state |= NCPI_VALID_CONNECT_B3_IND;
if (((plci->NL.Ind & 0x0f) == N_CONNECT_ACK)
|| (((plci->NL.Ind & 0x0f) == N_CONNECT)
&& (fax_feature_bits & T30_FEATURE_BIT_POLLING))
|| (((plci->NL.Ind & 0x0f) == N_EDATA)
&& ((((T30_INFO *)plci->NL.RBuffer->P)->code == EDATA_T30_TRAIN_OK)
|| (((T30_INFO *)plci->NL.RBuffer->P)->code == EDATA_T30_DIS)
|| (((T30_INFO *)plci->NL.RBuffer->P)->code == EDATA_T30_DTC))))
{
plci->ncpi_state |= NCPI_VALID_CONNECT_B3_ACT;
}
if (((plci->NL.Ind & 0x0f) == N_DISC)
|| ((plci->NL.Ind & 0x0f) == N_DISC_ACK)
|| (((plci->NL.Ind & 0x0f) == N_EDATA)
&& (((T30_INFO *)plci->NL.RBuffer->P)->code == EDATA_T30_EOP_CAPI)))
{
plci->ncpi_state |= NCPI_VALID_CONNECT_B3_ACT | NCPI_VALID_DISC_B3_IND;
}
}
break;
case B3_RTP:
if (((plci->NL.Ind & 0x0f) == N_DISC) || ((plci->NL.Ind & 0x0f) == N_DISC_ACK))
{
if (plci->NL.RLength != 0)
{
info = rtp_info[plci->NL.RBuffer->P[0]];
plci->ncpi_buffer[0] = plci->NL.RLength - 1;
for (i = 1; i < plci->NL.RLength; i++)
plci->ncpi_buffer[i] = plci->NL.RBuffer->P[i];
}
}
break;
}
plci->NL.RNR = 2;
}
switch (plci->NL.Ind & 0x0f) {
case N_EDATA:
if ((plci->B3_prot == 4) || (plci->B3_prot == 5))
{
dbug(1, dprintf("EDATA ncci=0x%x state=%d code=%02x", ncci, a->ncci_state[ncci],
((T30_INFO *)plci->NL.RBuffer->P)->code));
fax_send_edata_ack = (((T30_INFO *)(plci->fax_connect_info_buffer))->operating_mode == T30_OPERATING_MODE_CAPI_NEG);
if ((plci->nsf_control_bits & T30_NSF_CONTROL_BIT_ENABLE_NSF)
&& (plci->nsf_control_bits & (T30_NSF_CONTROL_BIT_NEGOTIATE_IND | T30_NSF_CONTROL_BIT_NEGOTIATE_RESP))
&& (((T30_INFO *)plci->NL.RBuffer->P)->code == EDATA_T30_DIS)
&& (a->ncci_state[ncci] == OUTG_CON_PENDING)
&& (plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_NEGOTIATE_B3_SENT))
{
((T30_INFO *)(plci->fax_connect_info_buffer))->code = ((T30_INFO *)plci->NL.RBuffer->P)->code;
sendf(plci->appl, _MANUFACTURER_I, Id, 0, "dwbS", _DI_MANU_ID, _DI_NEGOTIATE_B3,
(byte)(plci->ncpi_buffer[0] + 1), plci->ncpi_buffer);
plci->ncpi_state |= NCPI_NEGOTIATE_B3_SENT;
if (plci->nsf_control_bits & T30_NSF_CONTROL_BIT_NEGOTIATE_RESP)
fax_send_edata_ack = false;
}
if (a->manufacturer_features & MANUFACTURER_FEATURE_FAX_PAPER_FORMATS)
{
switch (((T30_INFO *)plci->NL.RBuffer->P)->code)
{
case EDATA_T30_DIS:
if ((a->ncci_state[ncci] == OUTG_CON_PENDING)
&& !(GET_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->control_bits_low) & T30_CONTROL_BIT_REQUEST_POLLING)
&& (plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
a->ncci_state[ncci] = INC_ACT_PENDING;
if (plci->B3_prot == 4)
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
else
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
break;
case EDATA_T30_TRAIN_OK:
if ((a->ncci_state[ncci] == INC_ACT_PENDING)
&& (plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
if (plci->B3_prot == 4)
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
else
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
break;
case EDATA_T30_EOP_CAPI:
if (a->ncci_state[ncci] == CONNECTED)
{
sendf(plci->appl, _DISCONNECT_B3_I, Id, 0, "wS", GOOD, plci->ncpi_buffer);
a->ncci_state[ncci] = INC_DIS_PENDING;
plci->ncpi_state = 0;
fax_send_edata_ack = false;
}
break;
}
}
else
{
switch (((T30_INFO *)plci->NL.RBuffer->P)->code)
{
case EDATA_T30_TRAIN_OK:
if ((a->ncci_state[ncci] == INC_ACT_PENDING)
&& (plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
if (plci->B3_prot == 4)
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
else
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
break;
}
}
if (fax_send_edata_ack)
{
((T30_INFO *)(plci->fax_connect_info_buffer))->code = ((T30_INFO *)plci->NL.RBuffer->P)->code;
plci->fax_edata_ack_length = 1;
start_internal_command(Id, plci, fax_edata_ack_command);
}
}
else
{
dbug(1, dprintf("EDATA ncci=0x%x state=%d", ncci, a->ncci_state[ncci]));
}
break;
case N_CONNECT:
if (!a->ch_ncci[ch])
{
ncci = get_ncci(plci, ch, 0);
Id = (Id & 0xffff) | (((dword) ncci) << 16);
}
dbug(1, dprintf("N_CONNECT: ch=%d state=%d plci=%lx plci_Id=%lx plci_State=%d",
ch, a->ncci_state[ncci], a->ncci_plci[ncci], plci->Id, plci->State));
msg = _CONNECT_B3_I;
if (a->ncci_state[ncci] == IDLE)
plci->channels++;
else if (plci->B3_prot == 1)
msg = _CONNECT_B3_T90_ACTIVE_I;
a->ncci_state[ncci] = INC_CON_PENDING;
if (plci->B3_prot == 4)
sendf(plci->appl, msg, Id, 0, "s", "");
else
sendf(plci->appl, msg, Id, 0, "S", plci->ncpi_buffer);
break;
case N_CONNECT_ACK:
dbug(1, dprintf("N_connect_Ack"));
if (plci->internal_command_queue[0]
&& ((plci->adjust_b_state == ADJUST_B_CONNECT_2)
|| (plci->adjust_b_state == ADJUST_B_CONNECT_3)
|| (plci->adjust_b_state == ADJUST_B_CONNECT_4)))
{
(*(plci->internal_command_queue[0]))(Id, plci, 0);
if (!plci->internal_command)
next_internal_command(Id, plci);
break;
}
msg = _CONNECT_B3_ACTIVE_I;
if (plci->B3_prot == 1)
{
if (a->ncci_state[ncci] != OUTG_CON_PENDING)
msg = _CONNECT_B3_T90_ACTIVE_I;
a->ncci_state[ncci] = INC_ACT_PENDING;
sendf(plci->appl, msg, Id, 0, "S", plci->ncpi_buffer);
}
else if ((plci->B3_prot == 4) || (plci->B3_prot == 5) || (plci->B3_prot == 7))
{
if ((a->ncci_state[ncci] == OUTG_CON_PENDING)
&& (plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
a->ncci_state[ncci] = INC_ACT_PENDING;
if (plci->B3_prot == 4)
sendf(plci->appl, msg, Id, 0, "s", "");
else
sendf(plci->appl, msg, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
}
else
{
a->ncci_state[ncci] = INC_ACT_PENDING;
sendf(plci->appl, msg, Id, 0, "S", plci->ncpi_buffer);
}
if (plci->adjust_b_restore)
{
plci->adjust_b_restore = false;
start_internal_command(Id, plci, adjust_b_restore);
}
break;
case N_DISC:
case N_DISC_ACK:
if (plci->internal_command_queue[0]
&& ((plci->internal_command == FAX_DISCONNECT_COMMAND_1)
|| (plci->internal_command == FAX_DISCONNECT_COMMAND_2)
|| (plci->internal_command == FAX_DISCONNECT_COMMAND_3)))
{
(*(plci->internal_command_queue[0]))(Id, plci, 0);
if (!plci->internal_command)
next_internal_command(Id, plci);
}
ncci_state = a->ncci_state[ncci];
ncci_remove(plci, ncci, false);
/* with N_DISC or N_DISC_ACK the IDI frees the respective */
/* channel, so we cannot store the state in ncci_state! The */
/* information which channel we received a N_DISC is thus */
/* stored in the inc_dis_ncci_table buffer. */
for (i = 0; plci->inc_dis_ncci_table[i]; i++);
plci->inc_dis_ncci_table[i] = (byte) ncci;
/* need a connect_b3_ind before a disconnect_b3_ind with FAX */
if (!plci->channels
&& (plci->B1_resource == 16)
&& (plci->State <= CONNECTED))
{
len = 9;
i = ((T30_INFO *)plci->fax_connect_info_buffer)->rate_div_2400 * 2400;
PUT_WORD(&plci->ncpi_buffer[1], i);
PUT_WORD(&plci->ncpi_buffer[3], 0);
i = ((T30_INFO *)plci->fax_connect_info_buffer)->data_format;
PUT_WORD(&plci->ncpi_buffer[5], i);
PUT_WORD(&plci->ncpi_buffer[7], 0);
plci->ncpi_buffer[len] = 0;
plci->ncpi_buffer[0] = len;
if (plci->B3_prot == 4)
sendf(plci->appl, _CONNECT_B3_I, Id, 0, "s", "");
else
{
if ((plci->requested_options_conn | plci->requested_options | a->requested_options_table[plci->appl->Id - 1])
& ((1L << PRIVATE_FAX_SUB_SEP_PWD) | (1L << PRIVATE_FAX_NONSTANDARD)))
{
plci->ncpi_buffer[++len] = 0;
plci->ncpi_buffer[++len] = 0;
plci->ncpi_buffer[++len] = 0;
plci->ncpi_buffer[0] = len;
}
sendf(plci->appl, _CONNECT_B3_I, Id, 0, "S", plci->ncpi_buffer);
}
sendf(plci->appl, _DISCONNECT_B3_I, Id, 0, "wS", info, plci->ncpi_buffer);
plci->ncpi_state = 0;
sig_req(plci, HANGUP, 0);
send_req(plci);
plci->State = OUTG_DIS_PENDING;
/* disc here */
}
else if ((a->manufacturer_features & MANUFACTURER_FEATURE_FAX_PAPER_FORMATS)
&& ((plci->B3_prot == 4) || (plci->B3_prot == 5))
&& ((ncci_state == INC_DIS_PENDING) || (ncci_state == IDLE)))
{
if (ncci_state == IDLE)
{
if (plci->channels)
plci->channels--;
if ((plci->State == IDLE || plci->State == SUSPENDING) && !plci->channels) {
if (plci->State == SUSPENDING) {
sendf(plci->appl,
_FACILITY_I,
Id & 0xffffL,
0,
"ws", (word)3, "\x03\x04\x00\x00");
sendf(plci->appl, _DISCONNECT_I, Id & 0xffffL, 0, "w", 0);
}
plci_remove(plci);
plci->State = IDLE;
}
}
}
else if (plci->channels)
{
sendf(plci->appl, _DISCONNECT_B3_I, Id, 0, "wS", info, plci->ncpi_buffer);
plci->ncpi_state = 0;
if ((ncci_state == OUTG_REJ_PENDING)
&& ((plci->B3_prot != B3_T90NL) && (plci->B3_prot != B3_ISO8208) && (plci->B3_prot != B3_X25_DCE)))
{
sig_req(plci, HANGUP, 0);
send_req(plci);
plci->State = OUTG_DIS_PENDING;
}
}
break;
case N_RESET:
a->ncci_state[ncci] = INC_RES_PENDING;
sendf(plci->appl, _RESET_B3_I, Id, 0, "S", plci->ncpi_buffer);
break;
case N_RESET_ACK:
a->ncci_state[ncci] = CONNECTED;
sendf(plci->appl, _RESET_B3_I, Id, 0, "S", plci->ncpi_buffer);
break;
case N_UDATA:
if (!(udata_forwarding_table[plci->NL.RBuffer->P[0] >> 5] & (1L << (plci->NL.RBuffer->P[0] & 0x1f))))
{
plci->RData[0].P = plci->internal_ind_buffer + (-((int)(long)(plci->internal_ind_buffer)) & 3);
plci->RData[0].PLength = INTERNAL_IND_BUFFER_SIZE;
plci->NL.R = plci->RData;
plci->NL.RNum = 1;
return;
}
case N_BDATA:
case N_DATA:
if (((a->ncci_state[ncci] != CONNECTED) && (plci->B2_prot == 1)) /* transparent */
|| (a->ncci_state[ncci] == IDLE)
|| (a->ncci_state[ncci] == INC_DIS_PENDING))
{
plci->NL.RNR = 2;
break;
}
if ((a->ncci_state[ncci] != CONNECTED)
&& (a->ncci_state[ncci] != OUTG_DIS_PENDING)
&& (a->ncci_state[ncci] != OUTG_REJ_PENDING))
{
dbug(1, dprintf("flow control"));
plci->NL.RNR = 1; /* flow control */
channel_x_off(plci, ch, 0);
break;
}
NCCIcode = ncci | (((word)a->Id) << 8);
/* count all buffers within the Application pool */
/* belonging to the same NCCI. If this is below the */
/* number of buffers available per NCCI we accept */
/* this packet, otherwise we reject it */
count = 0;
Num = 0xffff;
for (i = 0; i < APPLptr->MaxBuffer; i++) {
if (NCCIcode == APPLptr->DataNCCI[i]) count++;
if (!APPLptr->DataNCCI[i] && Num == 0xffff) Num = i;
}
if (count >= APPLptr->MaxNCCIData || Num == 0xffff)
{
dbug(3, dprintf("Flow-Control"));
plci->NL.RNR = 1;
if (++(APPLptr->NCCIDataFlowCtrlTimer) >=
(word)((a->manufacturer_features & MANUFACTURER_FEATURE_OOB_CHANNEL) ? 40 : 2000))
{
plci->NL.RNR = 2;
dbug(3, dprintf("DiscardData"));
} else {
channel_x_off(plci, ch, 0);
}
break;
}
else
{
APPLptr->NCCIDataFlowCtrlTimer = 0;
}
plci->RData[0].P = ReceiveBufferGet(APPLptr, Num);
if (!plci->RData[0].P) {
plci->NL.RNR = 1;
channel_x_off(plci, ch, 0);
break;
}
APPLptr->DataNCCI[Num] = NCCIcode;
APPLptr->DataFlags[Num] = (plci->Id << 8) | (plci->NL.Ind >> 4);
dbug(3, dprintf("Buffer(%d), Max = %d", Num, APPLptr->MaxBuffer));
plci->RNum = Num;
plci->RFlags = plci->NL.Ind >> 4;
plci->RData[0].PLength = APPLptr->MaxDataLength;
plci->NL.R = plci->RData;
if ((plci->NL.RLength != 0)
&& ((plci->B2_prot == B2_V120_ASYNC)
|| (plci->B2_prot == B2_V120_ASYNC_V42BIS)
|| (plci->B2_prot == B2_V120_BIT_TRANSPARENT)))
{
plci->RData[1].P = plci->RData[0].P;
plci->RData[1].PLength = plci->RData[0].PLength;
plci->RData[0].P = v120_header_buffer + (-((unsigned long)v120_header_buffer) & 3);
if ((plci->NL.RBuffer->P[0] & V120_HEADER_EXTEND_BIT) || (plci->NL.RLength == 1))
plci->RData[0].PLength = 1;
else
plci->RData[0].PLength = 2;
if (plci->NL.RBuffer->P[0] & V120_HEADER_BREAK_BIT)
plci->RFlags |= 0x0010;
if (plci->NL.RBuffer->P[0] & (V120_HEADER_C1_BIT | V120_HEADER_C2_BIT))
plci->RFlags |= 0x8000;
plci->NL.RNum = 2;
}
else
{
if ((plci->NL.Ind & 0x0f) == N_UDATA)
plci->RFlags |= 0x0010;
else if ((plci->B3_prot == B3_RTP) && ((plci->NL.Ind & 0x0f) == N_BDATA))
plci->RFlags |= 0x0001;
plci->NL.RNum = 1;
}
break;
case N_DATA_ACK:
data_ack(plci, ch);
break;
default:
plci->NL.RNR = 2;
break;
}
}
/*------------------------------------------------------------------*/
/* find a free PLCI */
/*------------------------------------------------------------------*/
static word get_plci(DIVA_CAPI_ADAPTER *a)
{
word i, j;
PLCI *plci;
dump_plcis(a);
for (i = 0; i < a->max_plci && a->plci[i].Id; i++);
if (i == a->max_plci) {
dbug(1, dprintf("get_plci: out of PLCIs"));
return 0;
}
plci = &a->plci[i];
plci->Id = (byte)(i + 1);
plci->Sig.Id = 0;
plci->NL.Id = 0;
plci->sig_req = 0;
plci->nl_req = 0;
plci->appl = NULL;
plci->relatedPTYPLCI = NULL;
plci->State = IDLE;
plci->SuppState = IDLE;
plci->channels = 0;
plci->tel = 0;
plci->B1_resource = 0;
plci->B2_prot = 0;
plci->B3_prot = 0;
plci->command = 0;
plci->m_command = 0;
init_internal_command_queue(plci);
plci->number = 0;
plci->req_in_start = 0;
plci->req_in = 0;
plci->req_out = 0;
plci->msg_in_write_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_read_pos = MSG_IN_QUEUE_SIZE;
plci->msg_in_wrap_pos = MSG_IN_QUEUE_SIZE;
plci->data_sent = false;
plci->send_disc = 0;
plci->sig_global_req = 0;
plci->sig_remove_id = 0;
plci->nl_global_req = 0;
plci->nl_remove_id = 0;
plci->adv_nl = 0;
plci->manufacturer = false;
plci->call_dir = CALL_DIR_OUT | CALL_DIR_ORIGINATE;
plci->spoofed_msg = 0;
plci->ptyState = 0;
plci->cr_enquiry = false;
plci->hangup_flow_ctrl_timer = 0;
plci->ncci_ring_list = 0;
for (j = 0; j < MAX_CHANNELS_PER_PLCI; j++) plci->inc_dis_ncci_table[j] = 0;
clear_c_ind_mask(plci);
set_group_ind_mask(plci);
plci->fax_connect_info_length = 0;
plci->nsf_control_bits = 0;
plci->ncpi_state = 0x00;
plci->ncpi_buffer[0] = 0;
plci->requested_options_conn = 0;
plci->requested_options = 0;
plci->notifiedcall = 0;
plci->vswitchstate = 0;
plci->vsprot = 0;
plci->vsprotdialect = 0;
init_b1_config(plci);
dbug(1, dprintf("get_plci(%x)", plci->Id));
return i + 1;
}
/*------------------------------------------------------------------*/
/* put a parameter in the parameter buffer */
/*------------------------------------------------------------------*/
static void add_p(PLCI *plci, byte code, byte *p)
{
word p_length;
p_length = 0;
if (p) p_length = p[0];
add_ie(plci, code, p, p_length);
}
/*------------------------------------------------------------------*/
/* put a structure in the parameter buffer */
/*------------------------------------------------------------------*/
static void add_s(PLCI *plci, byte code, API_PARSE *p)
{
if (p) add_ie(plci, code, p->info, (word)p->length);
}
/*------------------------------------------------------------------*/
/* put multiple structures in the parameter buffer */
/*------------------------------------------------------------------*/
static void add_ss(PLCI *plci, byte code, API_PARSE *p)
{
byte i;
if (p) {
dbug(1, dprintf("add_ss(%x,len=%d)", code, p->length));
for (i = 2; i < (byte)p->length; i += p->info[i] + 2) {
dbug(1, dprintf("add_ss_ie(%x,len=%d)", p->info[i - 1], p->info[i]));
add_ie(plci, p->info[i - 1], (byte *)&(p->info[i]), (word)p->info[i]);
}
}
}
/*------------------------------------------------------------------*/
/* return the channel number sent by the application in a esc_chi */
/*------------------------------------------------------------------*/
static byte getChannel(API_PARSE *p)
{
byte i;
if (p) {
for (i = 2; i < (byte)p->length; i += p->info[i] + 2) {
if (p->info[i] == 2) {
if (p->info[i - 1] == ESC && p->info[i + 1] == CHI) return (p->info[i + 2]);
}
}
}
return 0;
}
/*------------------------------------------------------------------*/
/* put an information element in the parameter buffer */
/*------------------------------------------------------------------*/
static void add_ie(PLCI *plci, byte code, byte *p, word p_length)
{
word i;
if (!(code & 0x80) && !p_length) return;
if (plci->req_in == plci->req_in_start) {
plci->req_in += 2;
}
else {
plci->req_in--;
}
plci->RBuffer[plci->req_in++] = code;
if (p) {
plci->RBuffer[plci->req_in++] = (byte)p_length;
for (i = 0; i < p_length; i++) plci->RBuffer[plci->req_in++] = p[1 + i];
}
plci->RBuffer[plci->req_in++] = 0;
}
/*------------------------------------------------------------------*/
/* put a unstructured data into the buffer */
/*------------------------------------------------------------------*/
static void add_d(PLCI *plci, word length, byte *p)
{
word i;
if (plci->req_in == plci->req_in_start) {
plci->req_in += 2;
}
else {
plci->req_in--;
}
for (i = 0; i < length; i++) plci->RBuffer[plci->req_in++] = p[i];
}
/*------------------------------------------------------------------*/
/* put parameters from the Additional Info parameter in the */
/* parameter buffer */
/*------------------------------------------------------------------*/
static void add_ai(PLCI *plci, API_PARSE *ai)
{
word i;
API_PARSE ai_parms[5];
for (i = 0; i < 5; i++) ai_parms[i].length = 0;
if (!ai->length)
return;
if (api_parse(&ai->info[1], (word)ai->length, "ssss", ai_parms))
return;
add_s(plci, KEY, &ai_parms[1]);
add_s(plci, UUI, &ai_parms[2]);
add_ss(plci, FTY, &ai_parms[3]);
}
/*------------------------------------------------------------------*/
/* put parameter for b1 protocol in the parameter buffer */
/*------------------------------------------------------------------*/
static word add_b1(PLCI *plci, API_PARSE *bp, word b_channel_info,
word b1_facilities)
{
API_PARSE bp_parms[8];
API_PARSE mdm_cfg[9];
API_PARSE global_config[2];
byte cai[256];
byte resource[] = {5, 9, 13, 12, 16, 39, 9, 17, 17, 18};
byte voice_cai[] = "\x06\x14\x00\x00\x00\x00\x08";
word i;
API_PARSE mdm_cfg_v18[4];
word j, n, w;
dword d;
for (i = 0; i < 8; i++) bp_parms[i].length = 0;
for (i = 0; i < 2; i++) global_config[i].length = 0;
dbug(1, dprintf("add_b1"));
api_save_msg(bp, "s", &plci->B_protocol);
if (b_channel_info == 2) {
plci->B1_resource = 0;
adjust_b1_facilities(plci, plci->B1_resource, b1_facilities);
add_p(plci, CAI, "\x01\x00");
dbug(1, dprintf("Cai=1,0 (no resource)"));
return 0;
}
if (plci->tel == CODEC_PERMANENT) return 0;
else if (plci->tel == CODEC) {
plci->B1_resource = 1;
adjust_b1_facilities(plci, plci->B1_resource, b1_facilities);
add_p(plci, CAI, "\x01\x01");
dbug(1, dprintf("Cai=1,1 (Codec)"));
return 0;
}
else if (plci->tel == ADV_VOICE) {
plci->B1_resource = add_b1_facilities(plci, 9, (word)(b1_facilities | B1_FACILITY_VOICE));
adjust_b1_facilities(plci, plci->B1_resource, (word)(b1_facilities | B1_FACILITY_VOICE));
voice_cai[1] = plci->B1_resource;
PUT_WORD(&voice_cai[5], plci->appl->MaxDataLength);
add_p(plci, CAI, voice_cai);
dbug(1, dprintf("Cai=1,0x%x (AdvVoice)", voice_cai[1]));
return 0;
}
plci->call_dir &= ~(CALL_DIR_ORIGINATE | CALL_DIR_ANSWER);
if (plci->call_dir & CALL_DIR_OUT)
plci->call_dir |= CALL_DIR_ORIGINATE;
else if (plci->call_dir & CALL_DIR_IN)
plci->call_dir |= CALL_DIR_ANSWER;
if (!bp->length) {
plci->B1_resource = 0x5;
adjust_b1_facilities(plci, plci->B1_resource, b1_facilities);
add_p(plci, CAI, "\x01\x05");
return 0;
}
dbug(1, dprintf("b_prot_len=%d", (word)bp->length));
if (bp->length > 256) return _WRONG_MESSAGE_FORMAT;
if (api_parse(&bp->info[1], (word)bp->length, "wwwsssb", bp_parms))
{
bp_parms[6].length = 0;
if (api_parse(&bp->info[1], (word)bp->length, "wwwsss", bp_parms))
{
dbug(1, dprintf("b-form.!"));
return _WRONG_MESSAGE_FORMAT;
}
}
else if (api_parse(&bp->info[1], (word)bp->length, "wwwssss", bp_parms))
{
dbug(1, dprintf("b-form.!"));
return _WRONG_MESSAGE_FORMAT;
}
if (bp_parms[6].length)
{
if (api_parse(&bp_parms[6].info[1], (word)bp_parms[6].length, "w", global_config))
{
return _WRONG_MESSAGE_FORMAT;
}
switch (GET_WORD(global_config[0].info))
{
case 1:
plci->call_dir = (plci->call_dir & ~CALL_DIR_ANSWER) | CALL_DIR_ORIGINATE;
break;
case 2:
plci->call_dir = (plci->call_dir & ~CALL_DIR_ORIGINATE) | CALL_DIR_ANSWER;
break;
}
}
dbug(1, dprintf("call_dir=%04x", plci->call_dir));
if ((GET_WORD(bp_parms[0].info) == B1_RTP)
&& (plci->adapter->man_profile.private_options & (1L << PRIVATE_RTP)))
{
plci->B1_resource = add_b1_facilities(plci, 31, (word)(b1_facilities & ~B1_FACILITY_VOICE));
adjust_b1_facilities(plci, plci->B1_resource, (word)(b1_facilities & ~B1_FACILITY_VOICE));
cai[1] = plci->B1_resource;
cai[2] = 0;
cai[3] = 0;
cai[4] = 0;
PUT_WORD(&cai[5], plci->appl->MaxDataLength);
for (i = 0; i < bp_parms[3].length; i++)
cai[7 + i] = bp_parms[3].info[1 + i];
cai[0] = 6 + bp_parms[3].length;
add_p(plci, CAI, cai);
return 0;
}
if ((GET_WORD(bp_parms[0].info) == B1_PIAFS)
&& (plci->adapter->man_profile.private_options & (1L << PRIVATE_PIAFS)))
{
plci->B1_resource = add_b1_facilities(plci, 35/* PIAFS HARDWARE FACILITY */, (word)(b1_facilities & ~B1_FACILITY_VOICE));
adjust_b1_facilities(plci, plci->B1_resource, (word)(b1_facilities & ~B1_FACILITY_VOICE));
cai[1] = plci->B1_resource;
cai[2] = 0;
cai[3] = 0;
cai[4] = 0;
PUT_WORD(&cai[5], plci->appl->MaxDataLength);
cai[0] = 6;
add_p(plci, CAI, cai);
return 0;
}
if ((GET_WORD(bp_parms[0].info) >= 32)
|| (!((1L << GET_WORD(bp_parms[0].info)) & plci->adapter->profile.B1_Protocols)
&& ((GET_WORD(bp_parms[0].info) != 3)
|| !((1L << B1_HDLC) & plci->adapter->profile.B1_Protocols)
|| ((bp_parms[3].length != 0) && (GET_WORD(&bp_parms[3].info[1]) != 0) && (GET_WORD(&bp_parms[3].info[1]) != 56000)))))
{
return _B1_NOT_SUPPORTED;
}
plci->B1_resource = add_b1_facilities(plci, resource[GET_WORD(bp_parms[0].info)],
(word)(b1_facilities & ~B1_FACILITY_VOICE));
adjust_b1_facilities(plci, plci->B1_resource, (word)(b1_facilities & ~B1_FACILITY_VOICE));
cai[0] = 6;
cai[1] = plci->B1_resource;
for (i = 2; i < sizeof(cai); i++) cai[i] = 0;
if ((GET_WORD(bp_parms[0].info) == B1_MODEM_ALL_NEGOTIATE)
|| (GET_WORD(bp_parms[0].info) == B1_MODEM_ASYNC)
|| (GET_WORD(bp_parms[0].info) == B1_MODEM_SYNC_HDLC))
{ /* B1 - modem */
for (i = 0; i < 7; i++) mdm_cfg[i].length = 0;
if (bp_parms[3].length)
{
if (api_parse(&bp_parms[3].info[1], (word)bp_parms[3].length, "wwwwww", mdm_cfg))
{
return (_WRONG_MESSAGE_FORMAT);
}
cai[2] = 0; /* Bit rate for adaptation */
dbug(1, dprintf("MDM Max Bit Rate:<%d>", GET_WORD(mdm_cfg[0].info)));
PUT_WORD(&cai[13], 0); /* Min Tx speed */
PUT_WORD(&cai[15], GET_WORD(mdm_cfg[0].info)); /* Max Tx speed */
PUT_WORD(&cai[17], 0); /* Min Rx speed */
PUT_WORD(&cai[19], GET_WORD(mdm_cfg[0].info)); /* Max Rx speed */
cai[3] = 0; /* Async framing parameters */
switch (GET_WORD(mdm_cfg[2].info))
{ /* Parity */
case 1: /* odd parity */
cai[3] |= (DSP_CAI_ASYNC_PARITY_ENABLE | DSP_CAI_ASYNC_PARITY_ODD);
dbug(1, dprintf("MDM: odd parity"));
break;
case 2: /* even parity */
cai[3] |= (DSP_CAI_ASYNC_PARITY_ENABLE | DSP_CAI_ASYNC_PARITY_EVEN);
dbug(1, dprintf("MDM: even parity"));
break;
default:
dbug(1, dprintf("MDM: no parity"));
break;
}
switch (GET_WORD(mdm_cfg[3].info))
{ /* stop bits */
case 1: /* 2 stop bits */
cai[3] |= DSP_CAI_ASYNC_TWO_STOP_BITS;
dbug(1, dprintf("MDM: 2 stop bits"));
break;
default:
dbug(1, dprintf("MDM: 1 stop bit"));
break;
}
switch (GET_WORD(mdm_cfg[1].info))
{ /* char length */
case 5:
cai[3] |= DSP_CAI_ASYNC_CHAR_LENGTH_5;
dbug(1, dprintf("MDM: 5 bits"));
break;
case 6:
cai[3] |= DSP_CAI_ASYNC_CHAR_LENGTH_6;
dbug(1, dprintf("MDM: 6 bits"));
break;
case 7:
cai[3] |= DSP_CAI_ASYNC_CHAR_LENGTH_7;
dbug(1, dprintf("MDM: 7 bits"));
break;
default:
dbug(1, dprintf("MDM: 8 bits"));
break;
}
cai[7] = 0; /* Line taking options */
cai[8] = 0; /* Modulation negotiation options */
cai[9] = 0; /* Modulation options */
if (((plci->call_dir & CALL_DIR_ORIGINATE) != 0) ^ ((plci->call_dir & CALL_DIR_OUT) != 0))
{
cai[9] |= DSP_CAI_MODEM_REVERSE_DIRECTION;
dbug(1, dprintf("MDM: Reverse direction"));
}
if (GET_WORD(mdm_cfg[4].info) & MDM_CAPI_DISABLE_RETRAIN)
{
cai[9] |= DSP_CAI_MODEM_DISABLE_RETRAIN;
dbug(1, dprintf("MDM: Disable retrain"));
}
if (GET_WORD(mdm_cfg[4].info) & MDM_CAPI_DISABLE_RING_TONE)
{
cai[7] |= DSP_CAI_MODEM_DISABLE_CALLING_TONE | DSP_CAI_MODEM_DISABLE_ANSWER_TONE;
dbug(1, dprintf("MDM: Disable ring tone"));
}
if (GET_WORD(mdm_cfg[4].info) & MDM_CAPI_GUARD_1800)
{
cai[8] |= DSP_CAI_MODEM_GUARD_TONE_1800HZ;
dbug(1, dprintf("MDM: 1800 guard tone"));
}
else if (GET_WORD(mdm_cfg[4].info) & MDM_CAPI_GUARD_550)
{
cai[8] |= DSP_CAI_MODEM_GUARD_TONE_550HZ;
dbug(1, dprintf("MDM: 550 guard tone"));
}
if ((GET_WORD(mdm_cfg[5].info) & 0x00ff) == MDM_CAPI_NEG_V100)
{
cai[8] |= DSP_CAI_MODEM_NEGOTIATE_V100;
dbug(1, dprintf("MDM: V100"));
}
else if ((GET_WORD(mdm_cfg[5].info) & 0x00ff) == MDM_CAPI_NEG_MOD_CLASS)
{
cai[8] |= DSP_CAI_MODEM_NEGOTIATE_IN_CLASS;
dbug(1, dprintf("MDM: IN CLASS"));
}
else if ((GET_WORD(mdm_cfg[5].info) & 0x00ff) == MDM_CAPI_NEG_DISABLED)
{
cai[8] |= DSP_CAI_MODEM_NEGOTIATE_DISABLED;
dbug(1, dprintf("MDM: DISABLED"));
}
cai[0] = 20;
if ((plci->adapter->man_profile.private_options & (1L << PRIVATE_V18))
&& (GET_WORD(mdm_cfg[5].info) & 0x8000)) /* Private V.18 enable */
{
plci->requested_options |= 1L << PRIVATE_V18;
}
if (GET_WORD(mdm_cfg[5].info) & 0x4000) /* Private VOWN enable */
plci->requested_options |= 1L << PRIVATE_VOWN;
if ((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[plci->appl->Id - 1])
& ((1L << PRIVATE_V18) | (1L << PRIVATE_VOWN)))
{
if (!api_parse(&bp_parms[3].info[1], (word)bp_parms[3].length, "wwwwwws", mdm_cfg))
{
i = 27;
if (mdm_cfg[6].length >= 4)
{
d = GET_DWORD(&mdm_cfg[6].info[1]);
cai[7] |= (byte) d; /* line taking options */
cai[9] |= (byte)(d >> 8); /* modulation options */
cai[++i] = (byte)(d >> 16); /* vown modulation options */
cai[++i] = (byte)(d >> 24);
if (mdm_cfg[6].length >= 8)
{
d = GET_DWORD(&mdm_cfg[6].info[5]);
cai[10] |= (byte) d; /* disabled modulations mask */
cai[11] |= (byte)(d >> 8);
if (mdm_cfg[6].length >= 12)
{
d = GET_DWORD(&mdm_cfg[6].info[9]);
cai[12] = (byte) d; /* enabled modulations mask */
cai[++i] = (byte)(d >> 8); /* vown enabled modulations */
cai[++i] = (byte)(d >> 16);
cai[++i] = (byte)(d >> 24);
cai[++i] = 0;
if (mdm_cfg[6].length >= 14)
{
w = GET_WORD(&mdm_cfg[6].info[13]);
if (w != 0)
PUT_WORD(&cai[13], w); /* min tx speed */
if (mdm_cfg[6].length >= 16)
{
w = GET_WORD(&mdm_cfg[6].info[15]);
if (w != 0)
PUT_WORD(&cai[15], w); /* max tx speed */
if (mdm_cfg[6].length >= 18)
{
w = GET_WORD(&mdm_cfg[6].info[17]);
if (w != 0)
PUT_WORD(&cai[17], w); /* min rx speed */
if (mdm_cfg[6].length >= 20)
{
w = GET_WORD(&mdm_cfg[6].info[19]);
if (w != 0)
PUT_WORD(&cai[19], w); /* max rx speed */
if (mdm_cfg[6].length >= 22)
{
w = GET_WORD(&mdm_cfg[6].info[21]);
cai[23] = (byte)(-((short) w)); /* transmit level */
if (mdm_cfg[6].length >= 24)
{
w = GET_WORD(&mdm_cfg[6].info[23]);
cai[22] |= (byte) w; /* info options mask */
cai[21] |= (byte)(w >> 8); /* disabled symbol rates */
}
}
}
}
}
}
}
}
}
cai[27] = i - 27;
i++;
if (!api_parse(&bp_parms[3].info[1], (word)bp_parms[3].length, "wwwwwwss", mdm_cfg))
{
if (!api_parse(&mdm_cfg[7].info[1], (word)mdm_cfg[7].length, "sss", mdm_cfg_v18))
{
for (n = 0; n < 3; n++)
{
cai[i] = (byte)(mdm_cfg_v18[n].length);
for (j = 1; j < ((word)(cai[i] + 1)); j++)
cai[i + j] = mdm_cfg_v18[n].info[j];
i += cai[i] + 1;
}
}
}
cai[0] = (byte)(i - 1);
}
}
}
}
if (GET_WORD(bp_parms[0].info) == 2 || /* V.110 async */
GET_WORD(bp_parms[0].info) == 3) /* V.110 sync */
{
if (bp_parms[3].length) {
dbug(1, dprintf("V.110,%d", GET_WORD(&bp_parms[3].info[1])));
switch (GET_WORD(&bp_parms[3].info[1])) { /* Rate */
case 0:
case 56000:
if (GET_WORD(bp_parms[0].info) == 3) { /* V.110 sync 56k */
dbug(1, dprintf("56k sync HSCX"));
cai[1] = 8;
cai[2] = 0;
cai[3] = 0;
}
else if (GET_WORD(bp_parms[0].info) == 2) {
dbug(1, dprintf("56k async DSP"));
cai[2] = 9;
}
break;
case 50: cai[2] = 1; break;
case 75: cai[2] = 1; break;
case 110: cai[2] = 1; break;
case 150: cai[2] = 1; break;
case 200: cai[2] = 1; break;
case 300: cai[2] = 1; break;
case 600: cai[2] = 1; break;
case 1200: cai[2] = 2; break;
case 2400: cai[2] = 3; break;
case 4800: cai[2] = 4; break;
case 7200: cai[2] = 10; break;
case 9600: cai[2] = 5; break;
case 12000: cai[2] = 13; break;
case 24000: cai[2] = 0; break;
case 14400: cai[2] = 11; break;
case 19200: cai[2] = 6; break;
case 28800: cai[2] = 12; break;
case 38400: cai[2] = 7; break;
case 48000: cai[2] = 8; break;
case 76: cai[2] = 15; break; /* 75/1200 */
case 1201: cai[2] = 14; break; /* 1200/75 */
case 56001: cai[2] = 9; break; /* V.110 56000 */
default:
return _B1_PARM_NOT_SUPPORTED;
}
cai[3] = 0;
if (cai[1] == 13) /* v.110 async */
{
if (bp_parms[3].length >= 8)
{
switch (GET_WORD(&bp_parms[3].info[3]))
{ /* char length */
case 5:
cai[3] |= DSP_CAI_ASYNC_CHAR_LENGTH_5;
break;
case 6:
cai[3] |= DSP_CAI_ASYNC_CHAR_LENGTH_6;
break;
case 7:
cai[3] |= DSP_CAI_ASYNC_CHAR_LENGTH_7;
break;
}
switch (GET_WORD(&bp_parms[3].info[5]))
{ /* Parity */
case 1: /* odd parity */
cai[3] |= (DSP_CAI_ASYNC_PARITY_ENABLE | DSP_CAI_ASYNC_PARITY_ODD);
break;
case 2: /* even parity */
cai[3] |= (DSP_CAI_ASYNC_PARITY_ENABLE | DSP_CAI_ASYNC_PARITY_EVEN);
break;
}
switch (GET_WORD(&bp_parms[3].info[7]))
{ /* stop bits */
case 1: /* 2 stop bits */
cai[3] |= DSP_CAI_ASYNC_TWO_STOP_BITS;
break;
}
}
}
}
else if (cai[1] == 8 || GET_WORD(bp_parms[0].info) == 3) {
dbug(1, dprintf("V.110 default 56k sync"));
cai[1] = 8;
cai[2] = 0;
cai[3] = 0;
}
else {
dbug(1, dprintf("V.110 default 9600 async"));
cai[2] = 5;
}
}
PUT_WORD(&cai[5], plci->appl->MaxDataLength);
dbug(1, dprintf("CAI[%d]=%x,%x,%x,%x,%x,%x", cai[0], cai[1], cai[2], cai[3], cai[4], cai[5], cai[6]));
/* HexDump ("CAI", sizeof(cai), &cai[0]); */
add_p(plci, CAI, cai);
return 0;
}
/*------------------------------------------------------------------*/
/* put parameter for b2 and B3 protocol in the parameter buffer */
/*------------------------------------------------------------------*/
static word add_b23(PLCI *plci, API_PARSE *bp)
{
word i, fax_control_bits;
byte pos, len;
byte SAPI = 0x40; /* default SAPI 16 for x.31 */
API_PARSE bp_parms[8];
API_PARSE *b1_config;
API_PARSE *b2_config;
API_PARSE b2_config_parms[8];
API_PARSE *b3_config;
API_PARSE b3_config_parms[6];
API_PARSE global_config[2];
static byte llc[3] = {2,0,0};
static byte dlc[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
static byte nlc[256];
static byte lli[12] = {1,1};
const byte llc2_out[] = {1,2,4,6,2,0,0,0, X75_V42BIS,V120_L2,V120_V42BIS,V120_L2,6};
const byte llc2_in[] = {1,3,4,6,3,0,0,0, X75_V42BIS,V120_L2,V120_V42BIS,V120_L2,6};
const byte llc3[] = {4,3,2,2,6,6,0};
const byte header[] = {0,2,3,3,0,0,0};
for (i = 0; i < 8; i++) bp_parms[i].length = 0;
for (i = 0; i < 6; i++) b2_config_parms[i].length = 0;
for (i = 0; i < 5; i++) b3_config_parms[i].length = 0;
lli[0] = 1;
lli[1] = 1;
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_XONOFF_FLOW_CONTROL)
lli[1] |= 2;
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_OOB_CHANNEL)
lli[1] |= 4;
if ((lli[1] & 0x02) && (diva_xdi_extended_features & DIVA_CAPI_USE_CMA)) {
lli[1] |= 0x10;
if (plci->rx_dma_descriptor <= 0) {
plci->rx_dma_descriptor = diva_get_dma_descriptor(plci, &plci->rx_dma_magic);
if (plci->rx_dma_descriptor >= 0)
plci->rx_dma_descriptor++;
}
if (plci->rx_dma_descriptor > 0) {
lli[0] = 6;
lli[1] |= 0x40;
lli[2] = (byte)(plci->rx_dma_descriptor - 1);
lli[3] = (byte)plci->rx_dma_magic;
lli[4] = (byte)(plci->rx_dma_magic >> 8);
lli[5] = (byte)(plci->rx_dma_magic >> 16);
lli[6] = (byte)(plci->rx_dma_magic >> 24);
}
}
if (DIVA_CAPI_SUPPORTS_NO_CANCEL(plci->adapter)) {
lli[1] |= 0x20;
}
dbug(1, dprintf("add_b23"));
api_save_msg(bp, "s", &plci->B_protocol);
if (!bp->length && plci->tel)
{
plci->adv_nl = true;
dbug(1, dprintf("Default adv.Nl"));
add_p(plci, LLI, lli);
plci->B2_prot = 1 /*XPARENT*/;
plci->B3_prot = 0 /*XPARENT*/;
llc[1] = 2;
llc[2] = 4;
add_p(plci, LLC, llc);
dlc[0] = 2;
PUT_WORD(&dlc[1], plci->appl->MaxDataLength);
add_p(plci, DLC, dlc);
return 0;
}
if (!bp->length) /*default*/
{
dbug(1, dprintf("ret default"));
add_p(plci, LLI, lli);
plci->B2_prot = 0 /*X.75 */;
plci->B3_prot = 0 /*XPARENT*/;
llc[1] = 1;
llc[2] = 4;
add_p(plci, LLC, llc);
dlc[0] = 2;
PUT_WORD(&dlc[1], plci->appl->MaxDataLength);
add_p(plci, DLC, dlc);
return 0;
}
dbug(1, dprintf("b_prot_len=%d", (word)bp->length));
if ((word)bp->length > 256) return _WRONG_MESSAGE_FORMAT;
if (api_parse(&bp->info[1], (word)bp->length, "wwwsssb", bp_parms))
{
bp_parms[6].length = 0;
if (api_parse(&bp->info[1], (word)bp->length, "wwwsss", bp_parms))
{
dbug(1, dprintf("b-form.!"));
return _WRONG_MESSAGE_FORMAT;
}
}
else if (api_parse(&bp->info[1], (word)bp->length, "wwwssss", bp_parms))
{
dbug(1, dprintf("b-form.!"));
return _WRONG_MESSAGE_FORMAT;
}
if (plci->tel == ADV_VOICE) /* transparent B on advanced voice */
{
if (GET_WORD(bp_parms[1].info) != 1
|| GET_WORD(bp_parms[2].info) != 0) return _B2_NOT_SUPPORTED;
plci->adv_nl = true;
}
else if (plci->tel) return _B2_NOT_SUPPORTED;
if ((GET_WORD(bp_parms[1].info) == B2_RTP)
&& (GET_WORD(bp_parms[2].info) == B3_RTP)
&& (plci->adapter->man_profile.private_options & (1L << PRIVATE_RTP)))
{
add_p(plci, LLI, lli);
plci->B2_prot = (byte) GET_WORD(bp_parms[1].info);
plci->B3_prot = (byte) GET_WORD(bp_parms[2].info);
llc[1] = (plci->call_dir & (CALL_DIR_ORIGINATE | CALL_DIR_FORCE_OUTG_NL)) ? 14 : 13;
llc[2] = 4;
add_p(plci, LLC, llc);
dlc[0] = 2;
PUT_WORD(&dlc[1], plci->appl->MaxDataLength);
dlc[3] = 3; /* Addr A */
dlc[4] = 1; /* Addr B */
dlc[5] = 7; /* modulo mode */
dlc[6] = 7; /* window size */
dlc[7] = 0; /* XID len Lo */
dlc[8] = 0; /* XID len Hi */
for (i = 0; i < bp_parms[4].length; i++)
dlc[9 + i] = bp_parms[4].info[1 + i];
dlc[0] = (byte)(8 + bp_parms[4].length);
add_p(plci, DLC, dlc);
for (i = 0; i < bp_parms[5].length; i++)
nlc[1 + i] = bp_parms[5].info[1 + i];
nlc[0] = (byte)(bp_parms[5].length);
add_p(plci, NLC, nlc);
return 0;
}
if ((GET_WORD(bp_parms[1].info) >= 32)
|| (!((1L << GET_WORD(bp_parms[1].info)) & plci->adapter->profile.B2_Protocols)
&& ((GET_WORD(bp_parms[1].info) != B2_PIAFS)
|| !(plci->adapter->man_profile.private_options & (1L << PRIVATE_PIAFS)))))
{
return _B2_NOT_SUPPORTED;
}
if ((GET_WORD(bp_parms[2].info) >= 32)
|| !((1L << GET_WORD(bp_parms[2].info)) & plci->adapter->profile.B3_Protocols))
{
return _B3_NOT_SUPPORTED;
}
if ((GET_WORD(bp_parms[1].info) != B2_SDLC)
&& ((GET_WORD(bp_parms[0].info) == B1_MODEM_ALL_NEGOTIATE)
|| (GET_WORD(bp_parms[0].info) == B1_MODEM_ASYNC)
|| (GET_WORD(bp_parms[0].info) == B1_MODEM_SYNC_HDLC)))
{
return (add_modem_b23(plci, bp_parms));
}
add_p(plci, LLI, lli);
plci->B2_prot = (byte)GET_WORD(bp_parms[1].info);
plci->B3_prot = (byte)GET_WORD(bp_parms[2].info);
if (plci->B2_prot == 12) SAPI = 0; /* default SAPI D-channel */
if (bp_parms[6].length)
{
if (api_parse(&bp_parms[6].info[1], (word)bp_parms[6].length, "w", global_config))
{
return _WRONG_MESSAGE_FORMAT;
}
switch (GET_WORD(global_config[0].info))
{
case 1:
plci->call_dir = (plci->call_dir & ~CALL_DIR_ANSWER) | CALL_DIR_ORIGINATE;
break;
case 2:
plci->call_dir = (plci->call_dir & ~CALL_DIR_ORIGINATE) | CALL_DIR_ANSWER;
break;
}
}
dbug(1, dprintf("call_dir=%04x", plci->call_dir));
if (plci->B2_prot == B2_PIAFS)
llc[1] = PIAFS_CRC;
else
/* IMPLEMENT_PIAFS */
{
llc[1] = (plci->call_dir & (CALL_DIR_ORIGINATE | CALL_DIR_FORCE_OUTG_NL)) ?
llc2_out[GET_WORD(bp_parms[1].info)] : llc2_in[GET_WORD(bp_parms[1].info)];
}
llc[2] = llc3[GET_WORD(bp_parms[2].info)];
add_p(plci, LLC, llc);
dlc[0] = 2;
PUT_WORD(&dlc[1], plci->appl->MaxDataLength +
header[GET_WORD(bp_parms[2].info)]);
b1_config = &bp_parms[3];
nlc[0] = 0;
if (plci->B3_prot == 4
|| plci->B3_prot == 5)
{
for (i = 0; i < sizeof(T30_INFO); i++) nlc[i] = 0;
nlc[0] = sizeof(T30_INFO);
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_FAX_PAPER_FORMATS)
((T30_INFO *)&nlc[1])->operating_mode = T30_OPERATING_MODE_CAPI;
((T30_INFO *)&nlc[1])->rate_div_2400 = 0xff;
if (b1_config->length >= 2)
{
((T30_INFO *)&nlc[1])->rate_div_2400 = (byte)(GET_WORD(&b1_config->info[1]) / 2400);
}
}
b2_config = &bp_parms[4];
if (llc[1] == PIAFS_CRC)
{
if (plci->B3_prot != B3_TRANSPARENT)
{
return _B_STACK_NOT_SUPPORTED;
}
if (b2_config->length && api_parse(&b2_config->info[1], (word)b2_config->length, "bwww", b2_config_parms)) {
return _WRONG_MESSAGE_FORMAT;
}
PUT_WORD(&dlc[1], plci->appl->MaxDataLength);
dlc[3] = 0; /* Addr A */
dlc[4] = 0; /* Addr B */
dlc[5] = 0; /* modulo mode */
dlc[6] = 0; /* window size */
if (b2_config->length >= 7) {
dlc[7] = 7;
dlc[8] = 0;
dlc[9] = b2_config_parms[0].info[0]; /* PIAFS protocol Speed configuration */
dlc[10] = b2_config_parms[1].info[0]; /* V.42bis P0 */
dlc[11] = b2_config_parms[1].info[1]; /* V.42bis P0 */
dlc[12] = b2_config_parms[2].info[0]; /* V.42bis P1 */
dlc[13] = b2_config_parms[2].info[1]; /* V.42bis P1 */
dlc[14] = b2_config_parms[3].info[0]; /* V.42bis P2 */
dlc[15] = b2_config_parms[3].info[1]; /* V.42bis P2 */
dlc[0] = 15;
if (b2_config->length >= 8) { /* PIAFS control abilities */
dlc[7] = 10;
dlc[16] = 2; /* Length of PIAFS extension */
dlc[17] = PIAFS_UDATA_ABILITIES; /* control (UDATA) ability */
dlc[18] = b2_config_parms[4].info[0]; /* value */
dlc[0] = 18;
}
}
else /* default values, 64K, variable, no compression */
{
dlc[7] = 7;
dlc[8] = 0;
dlc[9] = 0x03; /* PIAFS protocol Speed configuration */
dlc[10] = 0x03; /* V.42bis P0 */
dlc[11] = 0; /* V.42bis P0 */
dlc[12] = 0; /* V.42bis P1 */
dlc[13] = 0; /* V.42bis P1 */
dlc[14] = 0; /* V.42bis P2 */
dlc[15] = 0; /* V.42bis P2 */
dlc[0] = 15;
}
add_p(plci, DLC, dlc);
}
else
if ((llc[1] == V120_L2) || (llc[1] == V120_V42BIS))
{
if (plci->B3_prot != B3_TRANSPARENT)
return _B_STACK_NOT_SUPPORTED;
dlc[0] = 6;
PUT_WORD(&dlc[1], GET_WORD(&dlc[1]) + 2);
dlc[3] = 0x08;
dlc[4] = 0x01;
dlc[5] = 127;
dlc[6] = 7;
if (b2_config->length != 0)
{
if ((llc[1] == V120_V42BIS) && api_parse(&b2_config->info[1], (word)b2_config->length, "bbbbwww", b2_config_parms)) {
return _WRONG_MESSAGE_FORMAT;
}
dlc[3] = (byte)((b2_config->info[2] << 3) | ((b2_config->info[1] >> 5) & 0x04));
dlc[4] = (byte)((b2_config->info[1] << 1) | 0x01);
if (b2_config->info[3] != 128)
{
dbug(1, dprintf("1D-dlc= %x %x %x %x %x", dlc[0], dlc[1], dlc[2], dlc[3], dlc[4]));
return _B2_PARM_NOT_SUPPORTED;
}
dlc[5] = (byte)(b2_config->info[3] - 1);
dlc[6] = b2_config->info[4];
if (llc[1] == V120_V42BIS) {
if (b2_config->length >= 10) {
dlc[7] = 6;
dlc[8] = 0;
dlc[9] = b2_config_parms[4].info[0];
dlc[10] = b2_config_parms[4].info[1];
dlc[11] = b2_config_parms[5].info[0];
dlc[12] = b2_config_parms[5].info[1];
dlc[13] = b2_config_parms[6].info[0];
dlc[14] = b2_config_parms[6].info[1];
dlc[0] = 14;
dbug(1, dprintf("b2_config_parms[4].info[0] [1]: %x %x", b2_config_parms[4].info[0], b2_config_parms[4].info[1]));
dbug(1, dprintf("b2_config_parms[5].info[0] [1]: %x %x", b2_config_parms[5].info[0], b2_config_parms[5].info[1]));
dbug(1, dprintf("b2_config_parms[6].info[0] [1]: %x %x", b2_config_parms[6].info[0], b2_config_parms[6].info[1]));
}
else {
dlc[6] = 14;
}
}
}
}
else
{
if (b2_config->length)
{
dbug(1, dprintf("B2-Config"));
if (llc[1] == X75_V42BIS) {
if (api_parse(&b2_config->info[1], (word)b2_config->length, "bbbbwww", b2_config_parms))
{
return _WRONG_MESSAGE_FORMAT;
}
}
else {
if (api_parse(&b2_config->info[1], (word)b2_config->length, "bbbbs", b2_config_parms))
{
return _WRONG_MESSAGE_FORMAT;
}
}
/* if B2 Protocol is LAPD, b2_config structure is different */
if (llc[1] == 6)
{
dlc[0] = 4;
if (b2_config->length >= 1) dlc[2] = b2_config->info[1]; /* TEI */
else dlc[2] = 0x01;
if ((b2_config->length >= 2) && (plci->B2_prot == 12))
{
SAPI = b2_config->info[2]; /* SAPI */
}
dlc[1] = SAPI;
if ((b2_config->length >= 3) && (b2_config->info[3] == 128))
{
dlc[3] = 127; /* Mode */
}
else
{
dlc[3] = 7; /* Mode */
}
if (b2_config->length >= 4) dlc[4] = b2_config->info[4]; /* Window */
else dlc[4] = 1;
dbug(1, dprintf("D-dlc[%d]=%x,%x,%x,%x", dlc[0], dlc[1], dlc[2], dlc[3], dlc[4]));
if (b2_config->length > 5) return _B2_PARM_NOT_SUPPORTED;
}
else
{
dlc[0] = (byte)(b2_config_parms[4].length + 6);
dlc[3] = b2_config->info[1];
dlc[4] = b2_config->info[2];
if (b2_config->info[3] != 8 && b2_config->info[3] != 128) {
dbug(1, dprintf("1D-dlc= %x %x %x %x %x", dlc[0], dlc[1], dlc[2], dlc[3], dlc[4]));
return _B2_PARM_NOT_SUPPORTED;
}
dlc[5] = (byte)(b2_config->info[3] - 1);
dlc[6] = b2_config->info[4];
if (dlc[6] > dlc[5]) {
dbug(1, dprintf("2D-dlc= %x %x %x %x %x %x %x", dlc[0], dlc[1], dlc[2], dlc[3], dlc[4], dlc[5], dlc[6]));
return _B2_PARM_NOT_SUPPORTED;
}
if (llc[1] == X75_V42BIS) {
if (b2_config->length >= 10) {
dlc[7] = 6;
dlc[8] = 0;
dlc[9] = b2_config_parms[4].info[0];
dlc[10] = b2_config_parms[4].info[1];
dlc[11] = b2_config_parms[5].info[0];
dlc[12] = b2_config_parms[5].info[1];
dlc[13] = b2_config_parms[6].info[0];
dlc[14] = b2_config_parms[6].info[1];
dlc[0] = 14;
dbug(1, dprintf("b2_config_parms[4].info[0] [1]: %x %x", b2_config_parms[4].info[0], b2_config_parms[4].info[1]));
dbug(1, dprintf("b2_config_parms[5].info[0] [1]: %x %x", b2_config_parms[5].info[0], b2_config_parms[5].info[1]));
dbug(1, dprintf("b2_config_parms[6].info[0] [1]: %x %x", b2_config_parms[6].info[0], b2_config_parms[6].info[1]));
}
else {
dlc[6] = 14;
}
}
else {
PUT_WORD(&dlc[7], (word)b2_config_parms[4].length);
for (i = 0; i < b2_config_parms[4].length; i++)
dlc[11 + i] = b2_config_parms[4].info[1 + i];
}
}
}
}
add_p(plci, DLC, dlc);
b3_config = &bp_parms[5];
if (b3_config->length)
{
if (plci->B3_prot == 4
|| plci->B3_prot == 5)
{
if (api_parse(&b3_config->info[1], (word)b3_config->length, "wwss", b3_config_parms))
{
return _WRONG_MESSAGE_FORMAT;
}
i = GET_WORD((byte *)(b3_config_parms[0].info));
((T30_INFO *)&nlc[1])->resolution = (byte)(((i & 0x0001) ||
((plci->B3_prot == 4) && (((byte)(GET_WORD((byte *)b3_config_parms[1].info))) != 5))) ? T30_RESOLUTION_R8_0770_OR_200 : 0);
((T30_INFO *)&nlc[1])->data_format = (byte)(GET_WORD((byte *)b3_config_parms[1].info));
fax_control_bits = T30_CONTROL_BIT_ALL_FEATURES;
if ((((T30_INFO *)&nlc[1])->rate_div_2400 != 0) && (((T30_INFO *)&nlc[1])->rate_div_2400 <= 6))
fax_control_bits &= ~T30_CONTROL_BIT_ENABLE_V34FAX;
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_FAX_PAPER_FORMATS)
{
if ((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[plci->appl->Id - 1])
& (1L << PRIVATE_FAX_PAPER_FORMATS))
{
((T30_INFO *)&nlc[1])->resolution |= T30_RESOLUTION_R8_1540 |
T30_RESOLUTION_R16_1540_OR_400 | T30_RESOLUTION_300_300 |
T30_RESOLUTION_INCH_BASED | T30_RESOLUTION_METRIC_BASED;
}
((T30_INFO *)&nlc[1])->recording_properties =
T30_RECORDING_WIDTH_ISO_A3 |
(T30_RECORDING_LENGTH_UNLIMITED << 2) |
(T30_MIN_SCANLINE_TIME_00_00_00 << 4);
}
if (plci->B3_prot == 5)
{
if (i & 0x0002) /* Accept incoming fax-polling requests */
fax_control_bits |= T30_CONTROL_BIT_ACCEPT_POLLING;
if (i & 0x2000) /* Do not use MR compression */
fax_control_bits &= ~T30_CONTROL_BIT_ENABLE_2D_CODING;
if (i & 0x4000) /* Do not use MMR compression */
fax_control_bits &= ~T30_CONTROL_BIT_ENABLE_T6_CODING;
if (i & 0x8000) /* Do not use ECM */
fax_control_bits &= ~T30_CONTROL_BIT_ENABLE_ECM;
if (plci->fax_connect_info_length != 0)
{
((T30_INFO *)&nlc[1])->resolution = ((T30_INFO *)plci->fax_connect_info_buffer)->resolution;
((T30_INFO *)&nlc[1])->data_format = ((T30_INFO *)plci->fax_connect_info_buffer)->data_format;
((T30_INFO *)&nlc[1])->recording_properties = ((T30_INFO *)plci->fax_connect_info_buffer)->recording_properties;
fax_control_bits |= GET_WORD(&((T30_INFO *)plci->fax_connect_info_buffer)->control_bits_low) &
(T30_CONTROL_BIT_REQUEST_POLLING | T30_CONTROL_BIT_MORE_DOCUMENTS);
}
}
/* copy station id to NLC */
for (i = 0; i < T30_MAX_STATION_ID_LENGTH; i++)
{
if (i < b3_config_parms[2].length)
{
((T30_INFO *)&nlc[1])->station_id[i] = ((byte *)b3_config_parms[2].info)[1 + i];
}
else
{
((T30_INFO *)&nlc[1])->station_id[i] = ' ';
}
}
((T30_INFO *)&nlc[1])->station_id_len = T30_MAX_STATION_ID_LENGTH;
/* copy head line to NLC */
if (b3_config_parms[3].length)
{
pos = (byte)(fax_head_line_time(&(((T30_INFO *)&nlc[1])->station_id[T30_MAX_STATION_ID_LENGTH])));
if (pos != 0)
{
if (CAPI_MAX_DATE_TIME_LENGTH + 2 + b3_config_parms[3].length > CAPI_MAX_HEAD_LINE_SPACE)
pos = 0;
else
{
nlc[1 + offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + pos++] = ' ';
nlc[1 + offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + pos++] = ' ';
len = (byte)b3_config_parms[2].length;
if (len > 20)
len = 20;
if (CAPI_MAX_DATE_TIME_LENGTH + 2 + len + 2 + b3_config_parms[3].length <= CAPI_MAX_HEAD_LINE_SPACE)
{
for (i = 0; i < len; i++)
nlc[1 + offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + pos++] = ((byte *)b3_config_parms[2].info)[1 + i];
nlc[1 + offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + pos++] = ' ';
nlc[1 + offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + pos++] = ' ';
}
}
}
len = (byte)b3_config_parms[3].length;
if (len > CAPI_MAX_HEAD_LINE_SPACE - pos)
len = (byte)(CAPI_MAX_HEAD_LINE_SPACE - pos);
((T30_INFO *)&nlc[1])->head_line_len = (byte)(pos + len);
nlc[0] += (byte)(pos + len);
for (i = 0; i < len; i++)
nlc[1 + offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH + pos++] = ((byte *)b3_config_parms[3].info)[1 + i];
} else
((T30_INFO *)&nlc[1])->head_line_len = 0;
plci->nsf_control_bits = 0;
if (plci->B3_prot == 5)
{
if ((plci->adapter->man_profile.private_options & (1L << PRIVATE_FAX_SUB_SEP_PWD))
&& (GET_WORD((byte *)b3_config_parms[1].info) & 0x8000)) /* Private SUB/SEP/PWD enable */
{
plci->requested_options |= 1L << PRIVATE_FAX_SUB_SEP_PWD;
}
if ((plci->adapter->man_profile.private_options & (1L << PRIVATE_FAX_NONSTANDARD))
&& (GET_WORD((byte *)b3_config_parms[1].info) & 0x4000)) /* Private non-standard facilities enable */
{
plci->requested_options |= 1L << PRIVATE_FAX_NONSTANDARD;
}
if ((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[plci->appl->Id - 1])
& ((1L << PRIVATE_FAX_SUB_SEP_PWD) | (1L << PRIVATE_FAX_NONSTANDARD)))
{
if ((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[plci->appl->Id - 1])
& (1L << PRIVATE_FAX_SUB_SEP_PWD))
{
fax_control_bits |= T30_CONTROL_BIT_ACCEPT_SUBADDRESS | T30_CONTROL_BIT_ACCEPT_PASSWORD;
if (fax_control_bits & T30_CONTROL_BIT_ACCEPT_POLLING)
fax_control_bits |= T30_CONTROL_BIT_ACCEPT_SEL_POLLING;
}
len = nlc[0];
pos = offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH;
if (pos < plci->fax_connect_info_length)
{
for (i = 1 + plci->fax_connect_info_buffer[pos]; i != 0; i--)
nlc[++len] = plci->fax_connect_info_buffer[pos++];
}
else
nlc[++len] = 0;
if (pos < plci->fax_connect_info_length)
{
for (i = 1 + plci->fax_connect_info_buffer[pos]; i != 0; i--)
nlc[++len] = plci->fax_connect_info_buffer[pos++];
}
else
nlc[++len] = 0;
if ((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[plci->appl->Id - 1])
& (1L << PRIVATE_FAX_NONSTANDARD))
{
if ((pos < plci->fax_connect_info_length) && (plci->fax_connect_info_buffer[pos] != 0))
{
if ((plci->fax_connect_info_buffer[pos] >= 3) && (plci->fax_connect_info_buffer[pos + 1] >= 2))
plci->nsf_control_bits = GET_WORD(&plci->fax_connect_info_buffer[pos + 2]);
for (i = 1 + plci->fax_connect_info_buffer[pos]; i != 0; i--)
nlc[++len] = plci->fax_connect_info_buffer[pos++];
}
else
{
if (api_parse(&b3_config->info[1], (word)b3_config->length, "wwsss", b3_config_parms))
{
dbug(1, dprintf("non-standard facilities info missing or wrong format"));
nlc[++len] = 0;
}
else
{
if ((b3_config_parms[4].length >= 3) && (b3_config_parms[4].info[1] >= 2))
plci->nsf_control_bits = GET_WORD(&b3_config_parms[4].info[2]);
nlc[++len] = (byte)(b3_config_parms[4].length);
for (i = 0; i < b3_config_parms[4].length; i++)
nlc[++len] = b3_config_parms[4].info[1 + i];
}
}
}
nlc[0] = len;
if ((plci->nsf_control_bits & T30_NSF_CONTROL_BIT_ENABLE_NSF)
&& (plci->nsf_control_bits & T30_NSF_CONTROL_BIT_NEGOTIATE_RESP))
{
((T30_INFO *)&nlc[1])->operating_mode = T30_OPERATING_MODE_CAPI_NEG;
}
}
}
PUT_WORD(&(((T30_INFO *)&nlc[1])->control_bits_low), fax_control_bits);
len = offsetof(T30_INFO, station_id) + T30_MAX_STATION_ID_LENGTH;
for (i = 0; i < len; i++)
plci->fax_connect_info_buffer[i] = nlc[1 + i];
((T30_INFO *) plci->fax_connect_info_buffer)->head_line_len = 0;
i += ((T30_INFO *)&nlc[1])->head_line_len;
while (i < nlc[0])
plci->fax_connect_info_buffer[len++] = nlc[++i];
plci->fax_connect_info_length = len;
}
else
{
nlc[0] = 14;
if (b3_config->length != 16)
return _B3_PARM_NOT_SUPPORTED;
for (i = 0; i < 12; i++) nlc[1 + i] = b3_config->info[1 + i];
if (GET_WORD(&b3_config->info[13]) != 8 && GET_WORD(&b3_config->info[13]) != 128)
return _B3_PARM_NOT_SUPPORTED;
nlc[13] = b3_config->info[13];
if (GET_WORD(&b3_config->info[15]) >= nlc[13])
return _B3_PARM_NOT_SUPPORTED;
nlc[14] = b3_config->info[15];
}
}
else
{
if (plci->B3_prot == 4
|| plci->B3_prot == 5 /*T.30 - FAX*/) return _B3_PARM_NOT_SUPPORTED;
}
add_p(plci, NLC, nlc);
return 0;
}
/*----------------------------------------------------------------*/
/* make the same as add_b23, but only for the modem related */
/* L2 and L3 B-Chan protocol. */
/* */
/* Enabled L2 and L3 Configurations: */
/* If L1 == Modem all negotiation */
/* only L2 == Modem with full negotiation is allowed */
/* If L1 == Modem async or sync */
/* only L2 == Transparent is allowed */
/* L3 == Modem or L3 == Transparent are allowed */
/* B2 Configuration for modem: */
/* word : enable/disable compression, bitoptions */
/* B3 Configuration for modem: */
/* empty */
/*----------------------------------------------------------------*/
static word add_modem_b23(PLCI *plci, API_PARSE *bp_parms)
{
static byte lli[12] = {1,1};
static byte llc[3] = {2,0,0};
static byte dlc[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
API_PARSE mdm_config[2];
word i;
word b2_config = 0;
for (i = 0; i < 2; i++) mdm_config[i].length = 0;
for (i = 0; i < sizeof(dlc); i++) dlc[i] = 0;
if (((GET_WORD(bp_parms[0].info) == B1_MODEM_ALL_NEGOTIATE)
&& (GET_WORD(bp_parms[1].info) != B2_MODEM_EC_COMPRESSION))
|| ((GET_WORD(bp_parms[0].info) != B1_MODEM_ALL_NEGOTIATE)
&& (GET_WORD(bp_parms[1].info) != B2_TRANSPARENT)))
{
return (_B_STACK_NOT_SUPPORTED);
}
if ((GET_WORD(bp_parms[2].info) != B3_MODEM)
&& (GET_WORD(bp_parms[2].info) != B3_TRANSPARENT))
{
return (_B_STACK_NOT_SUPPORTED);
}
plci->B2_prot = (byte) GET_WORD(bp_parms[1].info);
plci->B3_prot = (byte) GET_WORD(bp_parms[2].info);
if ((GET_WORD(bp_parms[1].info) == B2_MODEM_EC_COMPRESSION) && bp_parms[4].length)
{
if (api_parse(&bp_parms[4].info[1],
(word)bp_parms[4].length, "w",
mdm_config))
{
return (_WRONG_MESSAGE_FORMAT);
}
b2_config = GET_WORD(mdm_config[0].info);
}
/* OK, L2 is modem */
lli[0] = 1;
lli[1] = 1;
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_XONOFF_FLOW_CONTROL)
lli[1] |= 2;
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_OOB_CHANNEL)
lli[1] |= 4;
if ((lli[1] & 0x02) && (diva_xdi_extended_features & DIVA_CAPI_USE_CMA)) {
lli[1] |= 0x10;
if (plci->rx_dma_descriptor <= 0) {
plci->rx_dma_descriptor = diva_get_dma_descriptor(plci, &plci->rx_dma_magic);
if (plci->rx_dma_descriptor >= 0)
plci->rx_dma_descriptor++;
}
if (plci->rx_dma_descriptor > 0) {
lli[1] |= 0x40;
lli[0] = 6;
lli[2] = (byte)(plci->rx_dma_descriptor - 1);
lli[3] = (byte)plci->rx_dma_magic;
lli[4] = (byte)(plci->rx_dma_magic >> 8);
lli[5] = (byte)(plci->rx_dma_magic >> 16);
lli[6] = (byte)(plci->rx_dma_magic >> 24);
}
}
if (DIVA_CAPI_SUPPORTS_NO_CANCEL(plci->adapter)) {
lli[1] |= 0x20;
}
llc[1] = (plci->call_dir & (CALL_DIR_ORIGINATE | CALL_DIR_FORCE_OUTG_NL)) ?
/*V42*/ 10 : /*V42_IN*/ 9;
llc[2] = 4; /* pass L3 always transparent */
add_p(plci, LLI, lli);
add_p(plci, LLC, llc);
i = 1;
PUT_WORD(&dlc[i], plci->appl->MaxDataLength);
i += 2;
if (GET_WORD(bp_parms[1].info) == B2_MODEM_EC_COMPRESSION)
{
if (bp_parms[4].length)
{
dbug(1, dprintf("MDM b2_config=%02x", b2_config));
dlc[i++] = 3; /* Addr A */
dlc[i++] = 1; /* Addr B */
dlc[i++] = 7; /* modulo mode */
dlc[i++] = 7; /* window size */
dlc[i++] = 0; /* XID len Lo */
dlc[i++] = 0; /* XID len Hi */
if (b2_config & MDM_B2_DISABLE_V42bis)
{
dlc[i] |= DLC_MODEMPROT_DISABLE_V42_V42BIS;
}
if (b2_config & MDM_B2_DISABLE_MNP)
{
dlc[i] |= DLC_MODEMPROT_DISABLE_MNP_MNP5;
}
if (b2_config & MDM_B2_DISABLE_TRANS)
{
dlc[i] |= DLC_MODEMPROT_REQUIRE_PROTOCOL;
}
if (b2_config & MDM_B2_DISABLE_V42)
{
dlc[i] |= DLC_MODEMPROT_DISABLE_V42_DETECT;
}
if (b2_config & MDM_B2_DISABLE_COMP)
{
dlc[i] |= DLC_MODEMPROT_DISABLE_COMPRESSION;
}
i++;
}
}
else
{
dlc[i++] = 3; /* Addr A */
dlc[i++] = 1; /* Addr B */
dlc[i++] = 7; /* modulo mode */
dlc[i++] = 7; /* window size */
dlc[i++] = 0; /* XID len Lo */
dlc[i++] = 0; /* XID len Hi */
dlc[i++] = DLC_MODEMPROT_DISABLE_V42_V42BIS |
DLC_MODEMPROT_DISABLE_MNP_MNP5 |
DLC_MODEMPROT_DISABLE_V42_DETECT |
DLC_MODEMPROT_DISABLE_COMPRESSION;
}
dlc[0] = (byte)(i - 1);
/* HexDump ("DLC", sizeof(dlc), &dlc[0]); */
add_p(plci, DLC, dlc);
return (0);
}
/*------------------------------------------------------------------*/
/* send a request for the signaling entity */
/*------------------------------------------------------------------*/
static void sig_req(PLCI *plci, byte req, byte Id)
{
if (!plci) return;
if (plci->adapter->adapter_disabled) return;
dbug(1, dprintf("sig_req(%x)", req));
if (req == REMOVE)
plci->sig_remove_id = plci->Sig.Id;
if (plci->req_in == plci->req_in_start) {
plci->req_in += 2;
plci->RBuffer[plci->req_in++] = 0;
}
PUT_WORD(&plci->RBuffer[plci->req_in_start], plci->req_in-plci->req_in_start - 2);
plci->RBuffer[plci->req_in++] = Id; /* sig/nl flag */
plci->RBuffer[plci->req_in++] = req; /* request */
plci->RBuffer[plci->req_in++] = 0; /* channel */
plci->req_in_start = plci->req_in;
}
/*------------------------------------------------------------------*/
/* send a request for the network layer entity */
/*------------------------------------------------------------------*/
static void nl_req_ncci(PLCI *plci, byte req, byte ncci)
{
if (!plci) return;
if (plci->adapter->adapter_disabled) return;
dbug(1, dprintf("nl_req %02x %02x %02x", plci->Id, req, ncci));
if (req == REMOVE)
{
plci->nl_remove_id = plci->NL.Id;
ncci_remove(plci, 0, (byte)(ncci != 0));
ncci = 0;
}
if (plci->req_in == plci->req_in_start) {
plci->req_in += 2;
plci->RBuffer[plci->req_in++] = 0;
}
PUT_WORD(&plci->RBuffer[plci->req_in_start], plci->req_in-plci->req_in_start - 2);
plci->RBuffer[plci->req_in++] = 1; /* sig/nl flag */
plci->RBuffer[plci->req_in++] = req; /* request */
plci->RBuffer[plci->req_in++] = plci->adapter->ncci_ch[ncci]; /* channel */
plci->req_in_start = plci->req_in;
}
static void send_req(PLCI *plci)
{
ENTITY *e;
word l;
/* word i; */
if (!plci) return;
if (plci->adapter->adapter_disabled) return;
channel_xmit_xon(plci);
/* if nothing to do, return */
if (plci->req_in == plci->req_out) return;
dbug(1, dprintf("send_req(in=%d,out=%d)", plci->req_in, plci->req_out));
if (plci->nl_req || plci->sig_req) return;
l = GET_WORD(&plci->RBuffer[plci->req_out]);
plci->req_out += 2;
plci->XData[0].P = &plci->RBuffer[plci->req_out];
plci->req_out += l;
if (plci->RBuffer[plci->req_out] == 1)
{
e = &plci->NL;
plci->req_out++;
e->Req = plci->nl_req = plci->RBuffer[plci->req_out++];
e->ReqCh = plci->RBuffer[plci->req_out++];
if (!(e->Id & 0x1f))
{
e->Id = NL_ID;
plci->RBuffer[plci->req_out - 4] = CAI;
plci->RBuffer[plci->req_out - 3] = 1;
plci->RBuffer[plci->req_out - 2] = (plci->Sig.Id == 0xff) ? 0 : plci->Sig.Id;
plci->RBuffer[plci->req_out - 1] = 0;
l += 3;
plci->nl_global_req = plci->nl_req;
}
dbug(1, dprintf("%x:NLREQ(%x:%x:%x)", plci->adapter->Id, e->Id, e->Req, e->ReqCh));
}
else
{
e = &plci->Sig;
if (plci->RBuffer[plci->req_out])
e->Id = plci->RBuffer[plci->req_out];
plci->req_out++;
e->Req = plci->sig_req = plci->RBuffer[plci->req_out++];
e->ReqCh = plci->RBuffer[plci->req_out++];
if (!(e->Id & 0x1f))
plci->sig_global_req = plci->sig_req;
dbug(1, dprintf("%x:SIGREQ(%x:%x:%x)", plci->adapter->Id, e->Id, e->Req, e->ReqCh));
}
plci->XData[0].PLength = l;
e->X = plci->XData;
plci->adapter->request(e);
dbug(1, dprintf("send_ok"));
}
static void send_data(PLCI *plci)
{
DIVA_CAPI_ADAPTER *a;
DATA_B3_DESC *data;
NCCI *ncci_ptr;
word ncci;
if (!plci->nl_req && plci->ncci_ring_list)
{
a = plci->adapter;
ncci = plci->ncci_ring_list;
do
{
ncci = a->ncci_next[ncci];
ncci_ptr = &(a->ncci[ncci]);
if (!(a->ncci_ch[ncci]
&& (a->ch_flow_control[a->ncci_ch[ncci]] & N_OK_FC_PENDING)))
{
if (ncci_ptr->data_pending)
{
if ((a->ncci_state[ncci] == CONNECTED)
|| (a->ncci_state[ncci] == INC_ACT_PENDING)
|| (plci->send_disc == ncci))
{
data = &(ncci_ptr->DBuffer[ncci_ptr->data_out]);
if ((plci->B2_prot == B2_V120_ASYNC)
|| (plci->B2_prot == B2_V120_ASYNC_V42BIS)
|| (plci->B2_prot == B2_V120_BIT_TRANSPARENT))
{
plci->NData[1].P = TransmitBufferGet(plci->appl, data->P);
plci->NData[1].PLength = data->Length;
if (data->Flags & 0x10)
plci->NData[0].P = v120_break_header;
else
plci->NData[0].P = v120_default_header;
plci->NData[0].PLength = 1;
plci->NL.XNum = 2;
plci->NL.Req = plci->nl_req = (byte)((data->Flags & 0x07) << 4 | N_DATA);
}
else
{
plci->NData[0].P = TransmitBufferGet(plci->appl, data->P);
plci->NData[0].PLength = data->Length;
if (data->Flags & 0x10)
plci->NL.Req = plci->nl_req = (byte)N_UDATA;
else if ((plci->B3_prot == B3_RTP) && (data->Flags & 0x01))
plci->NL.Req = plci->nl_req = (byte)N_BDATA;
else
plci->NL.Req = plci->nl_req = (byte)((data->Flags & 0x07) << 4 | N_DATA);
}
plci->NL.X = plci->NData;
plci->NL.ReqCh = a->ncci_ch[ncci];
dbug(1, dprintf("%x:DREQ(%x:%x)", a->Id, plci->NL.Id, plci->NL.Req));
plci->data_sent = true;
plci->data_sent_ptr = data->P;
a->request(&plci->NL);
}
else {
cleanup_ncci_data(plci, ncci);
}
}
else if (plci->send_disc == ncci)
{
/* dprintf("N_DISC"); */
plci->NData[0].PLength = 0;
plci->NL.ReqCh = a->ncci_ch[ncci];
plci->NL.Req = plci->nl_req = N_DISC;
a->request(&plci->NL);
plci->command = _DISCONNECT_B3_R;
plci->send_disc = 0;
}
}
} while (!plci->nl_req && (ncci != plci->ncci_ring_list));
plci->ncci_ring_list = ncci;
}
}
static void listen_check(DIVA_CAPI_ADAPTER *a)
{
word i, j;
PLCI *plci;
byte activnotifiedcalls = 0;
dbug(1, dprintf("listen_check(%d,%d)", a->listen_active, a->max_listen));
if (!remove_started && !a->adapter_disabled)
{
for (i = 0; i < a->max_plci; i++)
{
plci = &(a->plci[i]);
if (plci->notifiedcall) activnotifiedcalls++;
}
dbug(1, dprintf("listen_check(%d)", activnotifiedcalls));
for (i = a->listen_active; i < ((word)(a->max_listen + activnotifiedcalls)); i++) {
if ((j = get_plci(a))) {
a->listen_active++;
plci = &a->plci[j - 1];
plci->State = LISTENING;
add_p(plci, OAD, "\x01\xfd");
add_p(plci, KEY, "\x04\x43\x41\x32\x30");
add_p(plci, CAI, "\x01\xc0");
add_p(plci, UID, "\x06\x43\x61\x70\x69\x32\x30");
add_p(plci, LLI, "\x01\xc4"); /* support Dummy CR FAC + MWI + SpoofNotify */
add_p(plci, SHIFT | 6, NULL);
add_p(plci, SIN, "\x02\x00\x00");
plci->internal_command = LISTEN_SIG_ASSIGN_PEND; /* do indicate_req if OK */
sig_req(plci, ASSIGN, DSIG_ID);
send_req(plci);
}
}
}
}
/*------------------------------------------------------------------*/
/* functions for all parameters sent in INDs */
/*------------------------------------------------------------------*/
static void IndParse(PLCI *plci, word *parms_id, byte **parms, byte multiIEsize)
{
word ploc; /* points to current location within packet */
byte w;
byte wlen;
byte codeset, lock;
byte *in;
word i;
word code;
word mIEindex = 0;
ploc = 0;
codeset = 0;
lock = 0;
in = plci->Sig.RBuffer->P;
for (i = 0; i < parms_id[0]; i++) /* multiIE parms_id contains just the 1st */
{ /* element but parms array is larger */
parms[i] = (byte *)"";
}
for (i = 0; i < multiIEsize; i++)
{
parms[i] = (byte *)"";
}
while (ploc < plci->Sig.RBuffer->length - 1) {
/* read information element id and length */
w = in[ploc];
if (w & 0x80) {
/* w &=0xf0; removed, cannot detect congestion levels */
/* upper 4 bit masked with w==SHIFT now */
wlen = 0;
}
else {
wlen = (byte)(in[ploc + 1] + 1);
}
/* check if length valid (not exceeding end of packet) */
if ((ploc + wlen) > 270) return;
if (lock & 0x80) lock &= 0x7f;
else codeset = lock;
if ((w & 0xf0) == SHIFT) {
codeset = in[ploc];
if (!(codeset & 0x08)) lock = (byte)(codeset & 7);
codeset &= 7;
lock |= 0x80;
}
else {
if (w == ESC && wlen >= 3) code = in[ploc + 2] | 0x800;
else code = w;
code |= (codeset << 8);
for (i = 1; i < parms_id[0] + 1 && parms_id[i] != code; i++);
if (i < parms_id[0] + 1) {
if (!multiIEsize) { /* with multiIEs use next field index, */
mIEindex = i - 1; /* with normal IEs use same index like parms_id */
}
parms[mIEindex] = &in[ploc + 1];
dbug(1, dprintf("mIE[%d]=0x%x", *parms[mIEindex], in[ploc]));
if (parms_id[i] == OAD
|| parms_id[i] == CONN_NR
|| parms_id[i] == CAD) {
if (in[ploc + 2] & 0x80) {
in[ploc + 0] = (byte)(in[ploc + 1] + 1);
in[ploc + 1] = (byte)(in[ploc + 2] & 0x7f);
in[ploc + 2] = 0x80;
parms[mIEindex] = &in[ploc];
}
}
mIEindex++; /* effects multiIEs only */
}
}
ploc += (wlen + 1);
}
return;
}
/*------------------------------------------------------------------*/
/* try to match a cip from received BC and HLC */
/*------------------------------------------------------------------*/
static byte ie_compare(byte *ie1, byte *ie2)
{
word i;
if (!ie1 || !ie2) return false;
if (!ie1[0]) return false;
for (i = 0; i < (word)(ie1[0] + 1); i++) if (ie1[i] != ie2[i]) return false;
return true;
}
static word find_cip(DIVA_CAPI_ADAPTER *a, byte *bc, byte *hlc)
{
word i;
word j;
for (i = 9; i && !ie_compare(bc, cip_bc[i][a->u_law]); i--);
for (j = 16; j < 29 &&
(!ie_compare(bc, cip_bc[j][a->u_law]) || !ie_compare(hlc, cip_hlc[j])); j++);
if (j == 29) return i;
return j;
}
static byte AddInfo(byte **add_i,
byte **fty_i,
byte *esc_chi,
byte *facility)
{
byte i;
byte j;
byte k;
byte flen;
byte len = 0;
/* facility is a nested structure */
/* FTY can be more than once */
if (esc_chi[0] && !(esc_chi[esc_chi[0]] & 0x7f))
{
add_i[0] = (byte *)"\x02\x02\x00"; /* use neither b nor d channel */
}
else
{
add_i[0] = (byte *)"";
}
if (!fty_i[0][0])
{
add_i[3] = (byte *)"";
}
else
{ /* facility array found */
for (i = 0, j = 1; i < MAX_MULTI_IE && fty_i[i][0]; i++)
{
dbug(1, dprintf("AddIFac[%d]", fty_i[i][0]));
len += fty_i[i][0];
len += 2;
flen = fty_i[i][0];
facility[j++] = 0x1c; /* copy fac IE */
for (k = 0; k <= flen; k++, j++)
{
facility[j] = fty_i[i][k];
/* dbug(1, dprintf("%x ",facility[j])); */
}
}
facility[0] = len;
add_i[3] = facility;
}
/* dbug(1, dprintf("FacArrLen=%d ",len)); */
len = add_i[0][0] + add_i[1][0] + add_i[2][0] + add_i[3][0];
len += 4; /* calculate length of all */
return (len);
}
/*------------------------------------------------------------------*/
/* voice and codec features */
/*------------------------------------------------------------------*/
static void SetVoiceChannel(PLCI *plci, byte *chi, DIVA_CAPI_ADAPTER *a)
{
byte voice_chi[] = "\x02\x18\x01";
byte channel;
channel = chi[chi[0]] & 0x3;
dbug(1, dprintf("ExtDevON(Ch=0x%x)", channel));
voice_chi[2] = (channel) ? channel : 1;
add_p(plci, FTY, "\x02\x01\x07"); /* B On, default on 1 */
add_p(plci, ESC, voice_chi); /* Channel */
sig_req(plci, TEL_CTRL, 0);
send_req(plci);
if (a->AdvSignalPLCI)
{
adv_voice_write_coefs(a->AdvSignalPLCI, ADV_VOICE_WRITE_ACTIVATION);
}
}
static void VoiceChannelOff(PLCI *plci)
{
dbug(1, dprintf("ExtDevOFF"));
add_p(plci, FTY, "\x02\x01\x08"); /* B Off */
sig_req(plci, TEL_CTRL, 0);
send_req(plci);
if (plci->adapter->AdvSignalPLCI)
{
adv_voice_clear_config(plci->adapter->AdvSignalPLCI);
}
}
static word AdvCodecSupport(DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl,
byte hook_listen)
{
word j;
PLCI *splci;
/* check if hardware supports handset with hook states (adv.codec) */
/* or if just a on board codec is supported */
/* the advanced codec plci is just for internal use */
/* diva Pro with on-board codec: */
if (a->profile.Global_Options & HANDSET)
{
/* new call, but hook states are already signalled */
if (a->AdvCodecFLAG)
{
if (a->AdvSignalAppl != appl || a->AdvSignalPLCI)
{
dbug(1, dprintf("AdvSigPlci=0x%x", a->AdvSignalPLCI));
return 0x2001; /* codec in use by another application */
}
if (plci != NULL)
{
a->AdvSignalPLCI = plci;
plci->tel = ADV_VOICE;
}
return 0; /* adv codec still used */
}
if ((j = get_plci(a)))
{
splci = &a->plci[j - 1];
splci->tel = CODEC_PERMANENT;
/* hook_listen indicates if a facility_req with handset/hook support */
/* was sent. Otherwise if just a call on an external device was made */
/* the codec will be used but the hook info will be discarded (just */
/* the external controller is in use */
if (hook_listen) splci->State = ADVANCED_VOICE_SIG;
else
{
splci->State = ADVANCED_VOICE_NOSIG;
if (plci)
{
plci->spoofed_msg = SPOOFING_REQUIRED;
}
/* indicate D-ch connect if */
} /* codec is connected OK */
if (plci != NULL)
{
a->AdvSignalPLCI = plci;
plci->tel = ADV_VOICE;
}
a->AdvSignalAppl = appl;
a->AdvCodecFLAG = true;
a->AdvCodecPLCI = splci;
add_p(splci, CAI, "\x01\x15");
add_p(splci, LLI, "\x01\x00");
add_p(splci, ESC, "\x02\x18\x00");
add_p(splci, UID, "\x06\x43\x61\x70\x69\x32\x30");
splci->internal_command = PERM_COD_ASSIGN;
dbug(1, dprintf("Codec Assign"));
sig_req(splci, ASSIGN, DSIG_ID);
send_req(splci);
}
else
{
return 0x2001; /* wrong state, no more plcis */
}
}
else if (a->profile.Global_Options & ON_BOARD_CODEC)
{
if (hook_listen) return 0x300B; /* Facility not supported */
/* no hook with SCOM */
if (plci != NULL) plci->tel = CODEC;
dbug(1, dprintf("S/SCOM codec"));
/* first time we use the scom-s codec we must shut down the internal */
/* handset application of the card. This can be done by an assign with */
/* a cai with the 0x80 bit set. Assign return code is 'out of resource'*/
if (!a->scom_appl_disable) {
if ((j = get_plci(a))) {
splci = &a->plci[j - 1];
add_p(splci, CAI, "\x01\x80");
add_p(splci, UID, "\x06\x43\x61\x70\x69\x32\x30");
sig_req(splci, ASSIGN, 0xC0); /* 0xc0 is the TEL_ID */
send_req(splci);
a->scom_appl_disable = true;
}
else{
return 0x2001; /* wrong state, no more plcis */
}
}
}
else return 0x300B; /* Facility not supported */
return 0;
}
static void CodecIdCheck(DIVA_CAPI_ADAPTER *a, PLCI *plci)
{
dbug(1, dprintf("CodecIdCheck"));
if (a->AdvSignalPLCI == plci)
{
dbug(1, dprintf("PLCI owns codec"));
VoiceChannelOff(a->AdvCodecPLCI);
if (a->AdvCodecPLCI->State == ADVANCED_VOICE_NOSIG)
{
dbug(1, dprintf("remove temp codec PLCI"));
plci_remove(a->AdvCodecPLCI);
a->AdvCodecFLAG = 0;
a->AdvCodecPLCI = NULL;
a->AdvSignalAppl = NULL;
}
a->AdvSignalPLCI = NULL;
}
}
/* -------------------------------------------------------------------
Ask for physical address of card on PCI bus
------------------------------------------------------------------- */
static void diva_ask_for_xdi_sdram_bar(DIVA_CAPI_ADAPTER *a,
IDI_SYNC_REQ *preq) {
a->sdram_bar = 0;
if (diva_xdi_extended_features & DIVA_CAPI_XDI_PROVIDES_SDRAM_BAR) {
ENTITY *e = (ENTITY *)preq;
e->user[0] = a->Id - 1;
preq->xdi_sdram_bar.info.bar = 0;
preq->xdi_sdram_bar.Req = 0;
preq->xdi_sdram_bar.Rc = IDI_SYNC_REQ_XDI_GET_ADAPTER_SDRAM_BAR;
(*(a->request))(e);
a->sdram_bar = preq->xdi_sdram_bar.info.bar;
dbug(3, dprintf("A(%d) SDRAM BAR = %08x", a->Id, a->sdram_bar));
}
}
/* -------------------------------------------------------------------
Ask XDI about extended features
------------------------------------------------------------------- */
static void diva_get_extended_adapter_features(DIVA_CAPI_ADAPTER *a) {
IDI_SYNC_REQ *preq;
char buffer[((sizeof(preq->xdi_extended_features) + 4) > sizeof(ENTITY)) ? (sizeof(preq->xdi_extended_features) + 4) : sizeof(ENTITY)];
char features[4];
preq = (IDI_SYNC_REQ *)&buffer[0];
if (!diva_xdi_extended_features) {
ENTITY *e = (ENTITY *)preq;
diva_xdi_extended_features |= 0x80000000;
e->user[0] = a->Id - 1;
preq->xdi_extended_features.Req = 0;
preq->xdi_extended_features.Rc = IDI_SYNC_REQ_XDI_GET_EXTENDED_FEATURES;
preq->xdi_extended_features.info.buffer_length_in_bytes = sizeof(features);
preq->xdi_extended_features.info.features = &features[0];
(*(a->request))(e);
if (features[0] & DIVA_XDI_EXTENDED_FEATURES_VALID) {
/*
Check features located in the byte '0'
*/
if (features[0] & DIVA_XDI_EXTENDED_FEATURE_CMA) {
diva_xdi_extended_features |= DIVA_CAPI_USE_CMA;
}
if (features[0] & DIVA_XDI_EXTENDED_FEATURE_RX_DMA) {
diva_xdi_extended_features |= DIVA_CAPI_XDI_PROVIDES_RX_DMA;
dbug(1, dprintf("XDI provides RxDMA"));
}
if (features[0] & DIVA_XDI_EXTENDED_FEATURE_SDRAM_BAR) {
diva_xdi_extended_features |= DIVA_CAPI_XDI_PROVIDES_SDRAM_BAR;
}
if (features[0] & DIVA_XDI_EXTENDED_FEATURE_NO_CANCEL_RC) {
diva_xdi_extended_features |= DIVA_CAPI_XDI_PROVIDES_NO_CANCEL;
dbug(3, dprintf("XDI provides NO_CANCEL_RC feature"));
}
}
}
diva_ask_for_xdi_sdram_bar(a, preq);
}
/*------------------------------------------------------------------*/
/* automatic law */
/*------------------------------------------------------------------*/
/* called from OS specific part after init time to get the Law */
/* a-law (Euro) and u-law (us,japan) use different BCs in the Setup message */
void AutomaticLaw(DIVA_CAPI_ADAPTER *a)
{
word j;
PLCI *splci;
if (a->automatic_law) {
return;
}
if ((j = get_plci(a))) {
diva_get_extended_adapter_features(a);
splci = &a->plci[j - 1];
a->automatic_lawPLCI = splci;
a->automatic_law = 1;
add_p(splci, CAI, "\x01\x80");
add_p(splci, UID, "\x06\x43\x61\x70\x69\x32\x30");
splci->internal_command = USELAW_REQ;
splci->command = 0;
splci->number = 0;
sig_req(splci, ASSIGN, DSIG_ID);
send_req(splci);
}
}
/* called from OS specific part if an application sends an Capi20Release */
word CapiRelease(word Id)
{
word i, j, appls_found;
PLCI *plci;
APPL *this;
DIVA_CAPI_ADAPTER *a;
if (!Id)
{
dbug(0, dprintf("A: CapiRelease(Id==0)"));
return (_WRONG_APPL_ID);
}
this = &application[Id - 1]; /* get application pointer */
for (i = 0, appls_found = 0; i < max_appl; i++)
{
if (application[i].Id) /* an application has been found */
{
appls_found++;
}
}
for (i = 0; i < max_adapter; i++) /* scan all adapters... */
{
a = &adapter[i];
if (a->request)
{
a->Info_Mask[Id - 1] = 0;
a->CIP_Mask[Id - 1] = 0;
a->Notification_Mask[Id - 1] = 0;
a->codec_listen[Id - 1] = NULL;
a->requested_options_table[Id - 1] = 0;
for (j = 0; j < a->max_plci; j++) /* and all PLCIs connected */
{ /* with this application */
plci = &a->plci[j];
if (plci->Id) /* if plci owns no application */
{ /* it may be not jet connected */
if (plci->State == INC_CON_PENDING
|| plci->State == INC_CON_ALERT)
{
if (test_c_ind_mask_bit(plci, (word)(Id - 1)))
{
clear_c_ind_mask_bit(plci, (word)(Id - 1));
if (c_ind_mask_empty(plci))
{
sig_req(plci, HANGUP, 0);
send_req(plci);
plci->State = OUTG_DIS_PENDING;
}
}
}
if (test_c_ind_mask_bit(plci, (word)(Id - 1)))
{
clear_c_ind_mask_bit(plci, (word)(Id - 1));
if (c_ind_mask_empty(plci))
{
if (!plci->appl)
{
plci_remove(plci);
plci->State = IDLE;
}
}
}
if (plci->appl == this)
{
plci->appl = NULL;
plci_remove(plci);
plci->State = IDLE;
}
}
}
listen_check(a);
if (a->flag_dynamic_l1_down)
{
if (appls_found == 1) /* last application does a capi release */
{
if ((j = get_plci(a)))
{
plci = &a->plci[j - 1];
plci->command = 0;
add_p(plci, OAD, "\x01\xfd");
add_p(plci, CAI, "\x01\x80");
add_p(plci, UID, "\x06\x43\x61\x70\x69\x32\x30");
add_p(plci, SHIFT | 6, NULL);
add_p(plci, SIN, "\x02\x00\x00");
plci->internal_command = REM_L1_SIG_ASSIGN_PEND;
sig_req(plci, ASSIGN, DSIG_ID);
add_p(plci, FTY, "\x02\xff\x06"); /* l1 down */
sig_req(plci, SIG_CTRL, 0);
send_req(plci);
}
}
}
if (a->AdvSignalAppl == this)
{
this->NullCREnable = false;
if (a->AdvCodecPLCI)
{
plci_remove(a->AdvCodecPLCI);
a->AdvCodecPLCI->tel = 0;
a->AdvCodecPLCI->adv_nl = 0;
}
a->AdvSignalAppl = NULL;
a->AdvSignalPLCI = NULL;
a->AdvCodecFLAG = 0;
a->AdvCodecPLCI = NULL;
}
}
}
this->Id = 0;
return GOOD;
}
static word plci_remove_check(PLCI *plci)
{
if (!plci) return true;
if (!plci->NL.Id && c_ind_mask_empty(plci))
{
if (plci->Sig.Id == 0xff)
plci->Sig.Id = 0;
if (!plci->Sig.Id)
{
dbug(1, dprintf("plci_remove_complete(%x)", plci->Id));
dbug(1, dprintf("tel=0x%x,Sig=0x%x", plci->tel, plci->Sig.Id));
if (plci->Id)
{
CodecIdCheck(plci->adapter, plci);
clear_b1_config(plci);
ncci_remove(plci, 0, false);
plci_free_msg_in_queue(plci);
channel_flow_control_remove(plci);
plci->Id = 0;
plci->State = IDLE;
plci->channels = 0;
plci->appl = NULL;
plci->notifiedcall = 0;
}
listen_check(plci->adapter);
return true;
}
}
return false;
}
/*------------------------------------------------------------------*/
static byte plci_nl_busy(PLCI *plci)
{
/* only applicable for non-multiplexed protocols */
return (plci->nl_req
|| (plci->ncci_ring_list
&& plci->adapter->ncci_ch[plci->ncci_ring_list]
&& (plci->adapter->ch_flow_control[plci->adapter->ncci_ch[plci->ncci_ring_list]] & N_OK_FC_PENDING)));
}
/*------------------------------------------------------------------*/
/* DTMF facilities */
/*------------------------------------------------------------------*/
static struct
{
byte send_mask;
byte listen_mask;
byte character;
byte code;
} dtmf_digit_map[] =
{
{ 0x01, 0x01, 0x23, DTMF_DIGIT_TONE_CODE_HASHMARK },
{ 0x01, 0x01, 0x2a, DTMF_DIGIT_TONE_CODE_STAR },
{ 0x01, 0x01, 0x30, DTMF_DIGIT_TONE_CODE_0 },
{ 0x01, 0x01, 0x31, DTMF_DIGIT_TONE_CODE_1 },
{ 0x01, 0x01, 0x32, DTMF_DIGIT_TONE_CODE_2 },
{ 0x01, 0x01, 0x33, DTMF_DIGIT_TONE_CODE_3 },
{ 0x01, 0x01, 0x34, DTMF_DIGIT_TONE_CODE_4 },
{ 0x01, 0x01, 0x35, DTMF_DIGIT_TONE_CODE_5 },
{ 0x01, 0x01, 0x36, DTMF_DIGIT_TONE_CODE_6 },
{ 0x01, 0x01, 0x37, DTMF_DIGIT_TONE_CODE_7 },
{ 0x01, 0x01, 0x38, DTMF_DIGIT_TONE_CODE_8 },
{ 0x01, 0x01, 0x39, DTMF_DIGIT_TONE_CODE_9 },
{ 0x01, 0x01, 0x41, DTMF_DIGIT_TONE_CODE_A },
{ 0x01, 0x01, 0x42, DTMF_DIGIT_TONE_CODE_B },
{ 0x01, 0x01, 0x43, DTMF_DIGIT_TONE_CODE_C },
{ 0x01, 0x01, 0x44, DTMF_DIGIT_TONE_CODE_D },
{ 0x01, 0x00, 0x61, DTMF_DIGIT_TONE_CODE_A },
{ 0x01, 0x00, 0x62, DTMF_DIGIT_TONE_CODE_B },
{ 0x01, 0x00, 0x63, DTMF_DIGIT_TONE_CODE_C },
{ 0x01, 0x00, 0x64, DTMF_DIGIT_TONE_CODE_D },
{ 0x04, 0x04, 0x80, DTMF_SIGNAL_NO_TONE },
{ 0x00, 0x04, 0x81, DTMF_SIGNAL_UNIDENTIFIED_TONE },
{ 0x04, 0x04, 0x82, DTMF_SIGNAL_DIAL_TONE },
{ 0x04, 0x04, 0x83, DTMF_SIGNAL_PABX_INTERNAL_DIAL_TONE },
{ 0x04, 0x04, 0x84, DTMF_SIGNAL_SPECIAL_DIAL_TONE },
{ 0x04, 0x04, 0x85, DTMF_SIGNAL_SECOND_DIAL_TONE },
{ 0x04, 0x04, 0x86, DTMF_SIGNAL_RINGING_TONE },
{ 0x04, 0x04, 0x87, DTMF_SIGNAL_SPECIAL_RINGING_TONE },
{ 0x04, 0x04, 0x88, DTMF_SIGNAL_BUSY_TONE },
{ 0x04, 0x04, 0x89, DTMF_SIGNAL_CONGESTION_TONE },
{ 0x04, 0x04, 0x8a, DTMF_SIGNAL_SPECIAL_INFORMATION_TONE },
{ 0x04, 0x04, 0x8b, DTMF_SIGNAL_COMFORT_TONE },
{ 0x04, 0x04, 0x8c, DTMF_SIGNAL_HOLD_TONE },
{ 0x04, 0x04, 0x8d, DTMF_SIGNAL_RECORD_TONE },
{ 0x04, 0x04, 0x8e, DTMF_SIGNAL_CALLER_WAITING_TONE },
{ 0x04, 0x04, 0x8f, DTMF_SIGNAL_CALL_WAITING_TONE },
{ 0x04, 0x04, 0x90, DTMF_SIGNAL_PAY_TONE },
{ 0x04, 0x04, 0x91, DTMF_SIGNAL_POSITIVE_INDICATION_TONE },
{ 0x04, 0x04, 0x92, DTMF_SIGNAL_NEGATIVE_INDICATION_TONE },
{ 0x04, 0x04, 0x93, DTMF_SIGNAL_WARNING_TONE },
{ 0x04, 0x04, 0x94, DTMF_SIGNAL_INTRUSION_TONE },
{ 0x04, 0x04, 0x95, DTMF_SIGNAL_CALLING_CARD_SERVICE_TONE },
{ 0x04, 0x04, 0x96, DTMF_SIGNAL_PAYPHONE_RECOGNITION_TONE },
{ 0x04, 0x04, 0x97, DTMF_SIGNAL_CPE_ALERTING_SIGNAL },
{ 0x04, 0x04, 0x98, DTMF_SIGNAL_OFF_HOOK_WARNING_TONE },
{ 0x04, 0x04, 0xbf, DTMF_SIGNAL_INTERCEPT_TONE },
{ 0x04, 0x04, 0xc0, DTMF_SIGNAL_MODEM_CALLING_TONE },
{ 0x04, 0x04, 0xc1, DTMF_SIGNAL_FAX_CALLING_TONE },
{ 0x04, 0x04, 0xc2, DTMF_SIGNAL_ANSWER_TONE },
{ 0x04, 0x04, 0xc3, DTMF_SIGNAL_REVERSED_ANSWER_TONE },
{ 0x04, 0x04, 0xc4, DTMF_SIGNAL_ANSAM_TONE },
{ 0x04, 0x04, 0xc5, DTMF_SIGNAL_REVERSED_ANSAM_TONE },
{ 0x04, 0x04, 0xc6, DTMF_SIGNAL_BELL103_ANSWER_TONE },
{ 0x04, 0x04, 0xc7, DTMF_SIGNAL_FAX_FLAGS },
{ 0x04, 0x04, 0xc8, DTMF_SIGNAL_G2_FAX_GROUP_ID },
{ 0x00, 0x04, 0xc9, DTMF_SIGNAL_HUMAN_SPEECH },
{ 0x04, 0x04, 0xca, DTMF_SIGNAL_ANSWERING_MACHINE_390 },
{ 0x02, 0x02, 0xf1, DTMF_MF_DIGIT_TONE_CODE_1 },
{ 0x02, 0x02, 0xf2, DTMF_MF_DIGIT_TONE_CODE_2 },
{ 0x02, 0x02, 0xf3, DTMF_MF_DIGIT_TONE_CODE_3 },
{ 0x02, 0x02, 0xf4, DTMF_MF_DIGIT_TONE_CODE_4 },
{ 0x02, 0x02, 0xf5, DTMF_MF_DIGIT_TONE_CODE_5 },
{ 0x02, 0x02, 0xf6, DTMF_MF_DIGIT_TONE_CODE_6 },
{ 0x02, 0x02, 0xf7, DTMF_MF_DIGIT_TONE_CODE_7 },
{ 0x02, 0x02, 0xf8, DTMF_MF_DIGIT_TONE_CODE_8 },
{ 0x02, 0x02, 0xf9, DTMF_MF_DIGIT_TONE_CODE_9 },
{ 0x02, 0x02, 0xfa, DTMF_MF_DIGIT_TONE_CODE_0 },
{ 0x02, 0x02, 0xfb, DTMF_MF_DIGIT_TONE_CODE_K1 },
{ 0x02, 0x02, 0xfc, DTMF_MF_DIGIT_TONE_CODE_K2 },
{ 0x02, 0x02, 0xfd, DTMF_MF_DIGIT_TONE_CODE_KP },
{ 0x02, 0x02, 0xfe, DTMF_MF_DIGIT_TONE_CODE_S1 },
{ 0x02, 0x02, 0xff, DTMF_MF_DIGIT_TONE_CODE_ST },
};
#define DTMF_DIGIT_MAP_ENTRIES ARRAY_SIZE(dtmf_digit_map)
static void dtmf_enable_receiver(PLCI *plci, byte enable_mask)
{
word min_digit_duration, min_gap_duration;
dbug(1, dprintf("[%06lx] %s,%d: dtmf_enable_receiver %02x",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, enable_mask));
if (enable_mask != 0)
{
min_digit_duration = (plci->dtmf_rec_pulse_ms == 0) ? 40 : plci->dtmf_rec_pulse_ms;
min_gap_duration = (plci->dtmf_rec_pause_ms == 0) ? 40 : plci->dtmf_rec_pause_ms;
plci->internal_req_buffer[0] = DTMF_UDATA_REQUEST_ENABLE_RECEIVER;
PUT_WORD(&plci->internal_req_buffer[1], min_digit_duration);
PUT_WORD(&plci->internal_req_buffer[3], min_gap_duration);
plci->NData[0].PLength = 5;
PUT_WORD(&plci->internal_req_buffer[5], INTERNAL_IND_BUFFER_SIZE);
plci->NData[0].PLength += 2;
capidtmf_recv_enable(&(plci->capidtmf_state), min_digit_duration, min_gap_duration);
}
else
{
plci->internal_req_buffer[0] = DTMF_UDATA_REQUEST_DISABLE_RECEIVER;
plci->NData[0].PLength = 1;
capidtmf_recv_disable(&(plci->capidtmf_state));
}
plci->NData[0].P = plci->internal_req_buffer;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_UDATA;
plci->adapter->request(&plci->NL);
}
static void dtmf_send_digits(PLCI *plci, byte *digit_buffer, word digit_count)
{
word w, i;
dbug(1, dprintf("[%06lx] %s,%d: dtmf_send_digits %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, digit_count));
plci->internal_req_buffer[0] = DTMF_UDATA_REQUEST_SEND_DIGITS;
w = (plci->dtmf_send_pulse_ms == 0) ? 40 : plci->dtmf_send_pulse_ms;
PUT_WORD(&plci->internal_req_buffer[1], w);
w = (plci->dtmf_send_pause_ms == 0) ? 40 : plci->dtmf_send_pause_ms;
PUT_WORD(&plci->internal_req_buffer[3], w);
for (i = 0; i < digit_count; i++)
{
w = 0;
while ((w < DTMF_DIGIT_MAP_ENTRIES)
&& (digit_buffer[i] != dtmf_digit_map[w].character))
{
w++;
}
plci->internal_req_buffer[5 + i] = (w < DTMF_DIGIT_MAP_ENTRIES) ?
dtmf_digit_map[w].code : DTMF_DIGIT_TONE_CODE_STAR;
}
plci->NData[0].PLength = 5 + digit_count;
plci->NData[0].P = plci->internal_req_buffer;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_UDATA;
plci->adapter->request(&plci->NL);
}
static void dtmf_rec_clear_config(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_rec_clear_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->dtmf_rec_active = 0;
plci->dtmf_rec_pulse_ms = 0;
plci->dtmf_rec_pause_ms = 0;
capidtmf_init(&(plci->capidtmf_state), plci->adapter->u_law);
}
static void dtmf_send_clear_config(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_send_clear_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->dtmf_send_requests = 0;
plci->dtmf_send_pulse_ms = 0;
plci->dtmf_send_pause_ms = 0;
}
static void dtmf_prepare_switch(dword Id, PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_prepare_switch",
UnMapId(Id), (char *)(FILE_), __LINE__));
while (plci->dtmf_send_requests != 0)
dtmf_confirmation(Id, plci);
}
static word dtmf_save_config(dword Id, PLCI *plci, byte Rc)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_save_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
return (GOOD);
}
static word dtmf_restore_config(dword Id, PLCI *plci, byte Rc)
{
word Info;
dbug(1, dprintf("[%06lx] %s,%d: dtmf_restore_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
Info = GOOD;
if (plci->B1_facilities & B1_FACILITY_DTMFR)
{
switch (plci->adjust_b_state)
{
case ADJUST_B_RESTORE_DTMF_1:
plci->internal_command = plci->adjust_b_command;
if (plci_nl_busy(plci))
{
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_1;
break;
}
dtmf_enable_receiver(plci, plci->dtmf_rec_active);
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_2;
break;
case ADJUST_B_RESTORE_DTMF_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Reenable DTMF receiver failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
break;
}
}
return (Info);
}
static void dtmf_command(dword Id, PLCI *plci, byte Rc)
{
word internal_command, Info;
byte mask;
byte result[4];
dbug(1, dprintf("[%06lx] %s,%d: dtmf_command %02x %04x %04x %d %d %d %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command,
plci->dtmf_cmd, plci->dtmf_rec_pulse_ms, plci->dtmf_rec_pause_ms,
plci->dtmf_send_pulse_ms, plci->dtmf_send_pause_ms));
Info = GOOD;
result[0] = 2;
PUT_WORD(&result[1], DTMF_SUCCESS);
internal_command = plci->internal_command;
plci->internal_command = 0;
mask = 0x01;
switch (plci->dtmf_cmd)
{
case DTMF_LISTEN_TONE_START:
mask <<= 1;
case DTMF_LISTEN_MF_START:
mask <<= 1;
case DTMF_LISTEN_START:
switch (internal_command)
{
default:
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities |
B1_FACILITY_DTMFR), DTMF_COMMAND_1);
case DTMF_COMMAND_1:
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Load DTMF failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (plci->internal_command)
return;
case DTMF_COMMAND_2:
if (plci_nl_busy(plci))
{
plci->internal_command = DTMF_COMMAND_2;
return;
}
plci->internal_command = DTMF_COMMAND_3;
dtmf_enable_receiver(plci, (byte)(plci->dtmf_rec_active | mask));
return;
case DTMF_COMMAND_3:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Enable DTMF receiver failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
plci->tone_last_indication_code = DTMF_SIGNAL_NO_TONE;
plci->dtmf_rec_active |= mask;
break;
}
break;
case DTMF_LISTEN_TONE_STOP:
mask <<= 1;
case DTMF_LISTEN_MF_STOP:
mask <<= 1;
case DTMF_LISTEN_STOP:
switch (internal_command)
{
default:
plci->dtmf_rec_active &= ~mask;
if (plci->dtmf_rec_active)
break;
/*
case DTMF_COMMAND_1:
if (plci->dtmf_rec_active)
{
if (plci_nl_busy (plci))
{
plci->internal_command = DTMF_COMMAND_1;
return;
}
plci->dtmf_rec_active &= ~mask;
plci->internal_command = DTMF_COMMAND_2;
dtmf_enable_receiver (plci, false);
return;
}
Rc = OK;
case DTMF_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug (1, dprintf("[%06lx] %s,%d: Disable DTMF receiver failed %02x",
UnMapId (Id), (char far *)(FILE_), __LINE__, Rc));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
*/
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities &
~(B1_FACILITY_DTMFX | B1_FACILITY_DTMFR)), DTMF_COMMAND_3);
case DTMF_COMMAND_3:
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Unload DTMF failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (plci->internal_command)
return;
break;
}
break;
case DTMF_SEND_TONE:
mask <<= 1;
case DTMF_SEND_MF:
mask <<= 1;
case DTMF_DIGITS_SEND:
switch (internal_command)
{
default:
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities |
((plci->dtmf_parameter_length != 0) ? B1_FACILITY_DTMFX | B1_FACILITY_DTMFR : B1_FACILITY_DTMFX)),
DTMF_COMMAND_1);
case DTMF_COMMAND_1:
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Load DTMF failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (plci->internal_command)
return;
case DTMF_COMMAND_2:
if (plci_nl_busy(plci))
{
plci->internal_command = DTMF_COMMAND_2;
return;
}
plci->dtmf_msg_number_queue[(plci->dtmf_send_requests)++] = plci->number;
plci->internal_command = DTMF_COMMAND_3;
dtmf_send_digits(plci, &plci->saved_msg.parms[3].info[1], plci->saved_msg.parms[3].length);
return;
case DTMF_COMMAND_3:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Send DTMF digits failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
if (plci->dtmf_send_requests != 0)
(plci->dtmf_send_requests)--;
Info = _FACILITY_NOT_SUPPORTED;
break;
}
return;
}
break;
}
sendf(plci->appl, _FACILITY_R | CONFIRM, Id & 0xffffL, plci->number,
"wws", Info, SELECTOR_DTMF, result);
}
static byte dtmf_request(dword Id, word Number, DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info;
word i, j;
byte mask;
API_PARSE dtmf_parms[5];
byte result[40];
dbug(1, dprintf("[%06lx] %s,%d: dtmf_request",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = GOOD;
result[0] = 2;
PUT_WORD(&result[1], DTMF_SUCCESS);
if (!(a->profile.Global_Options & GL_DTMF_SUPPORTED))
{
dbug(1, dprintf("[%06lx] %s,%d: Facility not supported",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
}
else if (api_parse(&msg[1].info[1], msg[1].length, "w", dtmf_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
}
else if ((GET_WORD(dtmf_parms[0].info) == DTMF_GET_SUPPORTED_DETECT_CODES)
|| (GET_WORD(dtmf_parms[0].info) == DTMF_GET_SUPPORTED_SEND_CODES))
{
if (!((a->requested_options_table[appl->Id - 1])
& (1L << PRIVATE_DTMF_TONE)))
{
dbug(1, dprintf("[%06lx] %s,%d: DTMF unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, GET_WORD(dtmf_parms[0].info)));
PUT_WORD(&result[1], DTMF_UNKNOWN_REQUEST);
}
else
{
for (i = 0; i < 32; i++)
result[4 + i] = 0;
if (GET_WORD(dtmf_parms[0].info) == DTMF_GET_SUPPORTED_DETECT_CODES)
{
for (i = 0; i < DTMF_DIGIT_MAP_ENTRIES; i++)
{
if (dtmf_digit_map[i].listen_mask != 0)
result[4 + (dtmf_digit_map[i].character >> 3)] |= (1 << (dtmf_digit_map[i].character & 0x7));
}
}
else
{
for (i = 0; i < DTMF_DIGIT_MAP_ENTRIES; i++)
{
if (dtmf_digit_map[i].send_mask != 0)
result[4 + (dtmf_digit_map[i].character >> 3)] |= (1 << (dtmf_digit_map[i].character & 0x7));
}
}
result[0] = 3 + 32;
result[3] = 32;
}
}
else if (plci == NULL)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong PLCI",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_IDENTIFIER;
}
else
{
if (!plci->State
|| !plci->NL.Id || plci->nl_remove_id)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong state",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_STATE;
}
else
{
plci->command = 0;
plci->dtmf_cmd = GET_WORD(dtmf_parms[0].info);
mask = 0x01;
switch (plci->dtmf_cmd)
{
case DTMF_LISTEN_TONE_START:
case DTMF_LISTEN_TONE_STOP:
mask <<= 1;
case DTMF_LISTEN_MF_START:
case DTMF_LISTEN_MF_STOP:
mask <<= 1;
if (!((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[appl->Id - 1])
& (1L << PRIVATE_DTMF_TONE)))
{
dbug(1, dprintf("[%06lx] %s,%d: DTMF unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, GET_WORD(dtmf_parms[0].info)));
PUT_WORD(&result[1], DTMF_UNKNOWN_REQUEST);
break;
}
case DTMF_LISTEN_START:
case DTMF_LISTEN_STOP:
if (!(a->manufacturer_features & MANUFACTURER_FEATURE_HARDDTMF)
&& !(a->manufacturer_features & MANUFACTURER_FEATURE_SOFTDTMF_RECEIVE))
{
dbug(1, dprintf("[%06lx] %s,%d: Facility not supported",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (mask & DTMF_LISTEN_ACTIVE_FLAG)
{
if (api_parse(&msg[1].info[1], msg[1].length, "wwws", dtmf_parms))
{
plci->dtmf_rec_pulse_ms = 0;
plci->dtmf_rec_pause_ms = 0;
}
else
{
plci->dtmf_rec_pulse_ms = GET_WORD(dtmf_parms[1].info);
plci->dtmf_rec_pause_ms = GET_WORD(dtmf_parms[2].info);
}
}
start_internal_command(Id, plci, dtmf_command);
return (false);
case DTMF_SEND_TONE:
mask <<= 1;
case DTMF_SEND_MF:
mask <<= 1;
if (!((plci->requested_options_conn | plci->requested_options | plci->adapter->requested_options_table[appl->Id - 1])
& (1L << PRIVATE_DTMF_TONE)))
{
dbug(1, dprintf("[%06lx] %s,%d: DTMF unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, GET_WORD(dtmf_parms[0].info)));
PUT_WORD(&result[1], DTMF_UNKNOWN_REQUEST);
break;
}
case DTMF_DIGITS_SEND:
if (api_parse(&msg[1].info[1], msg[1].length, "wwws", dtmf_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
if (mask & DTMF_LISTEN_ACTIVE_FLAG)
{
plci->dtmf_send_pulse_ms = GET_WORD(dtmf_parms[1].info);
plci->dtmf_send_pause_ms = GET_WORD(dtmf_parms[2].info);
}
i = 0;
j = 0;
while ((i < dtmf_parms[3].length) && (j < DTMF_DIGIT_MAP_ENTRIES))
{
j = 0;
while ((j < DTMF_DIGIT_MAP_ENTRIES)
&& ((dtmf_parms[3].info[i + 1] != dtmf_digit_map[j].character)
|| ((dtmf_digit_map[j].send_mask & mask) == 0)))
{
j++;
}
i++;
}
if (j == DTMF_DIGIT_MAP_ENTRIES)
{
dbug(1, dprintf("[%06lx] %s,%d: Incorrect DTMF digit %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, dtmf_parms[3].info[i]));
PUT_WORD(&result[1], DTMF_INCORRECT_DIGIT);
break;
}
if (plci->dtmf_send_requests >= ARRAY_SIZE(plci->dtmf_msg_number_queue))
{
dbug(1, dprintf("[%06lx] %s,%d: DTMF request overrun",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_STATE;
break;
}
api_save_msg(dtmf_parms, "wwws", &plci->saved_msg);
start_internal_command(Id, plci, dtmf_command);
return (false);
default:
dbug(1, dprintf("[%06lx] %s,%d: DTMF unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, plci->dtmf_cmd));
PUT_WORD(&result[1], DTMF_UNKNOWN_REQUEST);
}
}
}
sendf(appl, _FACILITY_R | CONFIRM, Id & 0xffffL, Number,
"wws", Info, SELECTOR_DTMF, result);
return (false);
}
static void dtmf_confirmation(dword Id, PLCI *plci)
{
word i;
byte result[4];
dbug(1, dprintf("[%06lx] %s,%d: dtmf_confirmation",
UnMapId(Id), (char *)(FILE_), __LINE__));
result[0] = 2;
PUT_WORD(&result[1], DTMF_SUCCESS);
if (plci->dtmf_send_requests != 0)
{
sendf(plci->appl, _FACILITY_R | CONFIRM, Id & 0xffffL, plci->dtmf_msg_number_queue[0],
"wws", GOOD, SELECTOR_DTMF, result);
(plci->dtmf_send_requests)--;
for (i = 0; i < plci->dtmf_send_requests; i++)
plci->dtmf_msg_number_queue[i] = plci->dtmf_msg_number_queue[i + 1];
}
}
static void dtmf_indication(dword Id, PLCI *plci, byte *msg, word length)
{
word i, j, n;
dbug(1, dprintf("[%06lx] %s,%d: dtmf_indication",
UnMapId(Id), (char *)(FILE_), __LINE__));
n = 0;
for (i = 1; i < length; i++)
{
j = 0;
while ((j < DTMF_DIGIT_MAP_ENTRIES)
&& ((msg[i] != dtmf_digit_map[j].code)
|| ((dtmf_digit_map[j].listen_mask & plci->dtmf_rec_active) == 0)))
{
j++;
}
if (j < DTMF_DIGIT_MAP_ENTRIES)
{
if ((dtmf_digit_map[j].listen_mask & DTMF_TONE_LISTEN_ACTIVE_FLAG)
&& (plci->tone_last_indication_code == DTMF_SIGNAL_NO_TONE)
&& (dtmf_digit_map[j].character != DTMF_SIGNAL_UNIDENTIFIED_TONE))
{
if (n + 1 == i)
{
for (i = length; i > n + 1; i--)
msg[i] = msg[i - 1];
length++;
i++;
}
msg[++n] = DTMF_SIGNAL_UNIDENTIFIED_TONE;
}
plci->tone_last_indication_code = dtmf_digit_map[j].character;
msg[++n] = dtmf_digit_map[j].character;
}
}
if (n != 0)
{
msg[0] = (byte) n;
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0, "wS", SELECTOR_DTMF, msg);
}
}
/*------------------------------------------------------------------*/
/* DTMF parameters */
/*------------------------------------------------------------------*/
static void dtmf_parameter_write(PLCI *plci)
{
word i;
byte parameter_buffer[DTMF_PARAMETER_BUFFER_SIZE + 2];
dbug(1, dprintf("[%06lx] %s,%d: dtmf_parameter_write",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
parameter_buffer[0] = plci->dtmf_parameter_length + 1;
parameter_buffer[1] = DSP_CTRL_SET_DTMF_PARAMETERS;
for (i = 0; i < plci->dtmf_parameter_length; i++)
parameter_buffer[2 + i] = plci->dtmf_parameter_buffer[i];
add_p(plci, FTY, parameter_buffer);
sig_req(plci, TEL_CTRL, 0);
send_req(plci);
}
static void dtmf_parameter_clear_config(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_parameter_clear_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->dtmf_parameter_length = 0;
}
static void dtmf_parameter_prepare_switch(dword Id, PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_parameter_prepare_switch",
UnMapId(Id), (char *)(FILE_), __LINE__));
}
static word dtmf_parameter_save_config(dword Id, PLCI *plci, byte Rc)
{
dbug(1, dprintf("[%06lx] %s,%d: dtmf_parameter_save_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
return (GOOD);
}
static word dtmf_parameter_restore_config(dword Id, PLCI *plci, byte Rc)
{
word Info;
dbug(1, dprintf("[%06lx] %s,%d: dtmf_parameter_restore_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
Info = GOOD;
if ((plci->B1_facilities & B1_FACILITY_DTMFR)
&& (plci->dtmf_parameter_length != 0))
{
switch (plci->adjust_b_state)
{
case ADJUST_B_RESTORE_DTMF_PARAMETER_1:
plci->internal_command = plci->adjust_b_command;
if (plci->sig_req)
{
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_PARAMETER_1;
break;
}
dtmf_parameter_write(plci);
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_PARAMETER_2;
break;
case ADJUST_B_RESTORE_DTMF_PARAMETER_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Restore DTMF parameters failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
break;
}
}
return (Info);
}
/*------------------------------------------------------------------*/
/* Line interconnect facilities */
/*------------------------------------------------------------------*/
LI_CONFIG *li_config_table;
word li_total_channels;
/*------------------------------------------------------------------*/
/* translate a CHI information element to a channel number */
/* returns 0xff - any channel */
/* 0xfe - chi wrong coding */
/* 0xfd - D-channel */
/* 0x00 - no channel */
/* else channel number / PRI: timeslot */
/* if channels is provided we accept more than one channel. */
/*------------------------------------------------------------------*/
static byte chi_to_channel(byte *chi, dword *pchannelmap)
{
int p;
int i;
dword map;
byte excl;
byte ofs;
byte ch;
if (pchannelmap) *pchannelmap = 0;
if (!chi[0]) return 0xff;
excl = 0;
if (chi[1] & 0x20) {
if (chi[0] == 1 && chi[1] == 0xac) return 0xfd; /* exclusive d-channel */
for (i = 1; i < chi[0] && !(chi[i] & 0x80); i++);
if (i == chi[0] || !(chi[i] & 0x80)) return 0xfe;
if ((chi[1] | 0xc8) != 0xe9) return 0xfe;
if (chi[1] & 0x08) excl = 0x40;
/* int. id present */
if (chi[1] & 0x40) {
p = i + 1;
for (i = p; i < chi[0] && !(chi[i] & 0x80); i++);
if (i == chi[0] || !(chi[i] & 0x80)) return 0xfe;
}
/* coding standard, Number/Map, Channel Type */
p = i + 1;
for (i = p; i < chi[0] && !(chi[i] & 0x80); i++);
if (i == chi[0] || !(chi[i] & 0x80)) return 0xfe;
if ((chi[p] | 0xd0) != 0xd3) return 0xfe;
/* Number/Map */
if (chi[p] & 0x10) {
/* map */
if ((chi[0] - p) == 4) ofs = 0;
else if ((chi[0] - p) == 3) ofs = 1;
else return 0xfe;
ch = 0;
map = 0;
for (i = 0; i < 4 && p < chi[0]; i++) {
p++;
ch += 8;
map <<= 8;
if (chi[p]) {
for (ch = 0; !(chi[p] & (1 << ch)); ch++);
map |= chi[p];
}
}
ch += ofs;
map <<= ofs;
}
else {
/* number */
p = i + 1;
ch = chi[p] & 0x3f;
if (pchannelmap) {
if ((byte)(chi[0] - p) > 30) return 0xfe;
map = 0;
for (i = p; i <= chi[0]; i++) {
if ((chi[i] & 0x7f) > 31) return 0xfe;
map |= (1L << (chi[i] & 0x7f));
}
}
else {
if (p != chi[0]) return 0xfe;
if (ch > 31) return 0xfe;
map = (1L << ch);
}
if (chi[p] & 0x40) return 0xfe;
}
if (pchannelmap) *pchannelmap = map;
else if (map != ((dword)(1L << ch))) return 0xfe;
return (byte)(excl | ch);
}
else { /* not PRI */
for (i = 1; i < chi[0] && !(chi[i] & 0x80); i++);
if (i != chi[0] || !(chi[i] & 0x80)) return 0xfe;
if (chi[1] & 0x08) excl = 0x40;
switch (chi[1] | 0x98) {
case 0x98: return 0;
case 0x99:
if (pchannelmap) *pchannelmap = 2;
return excl | 1;
case 0x9a:
if (pchannelmap) *pchannelmap = 4;
return excl | 2;
case 0x9b: return 0xff;
case 0x9c: return 0xfd; /* d-ch */
default: return 0xfe;
}
}
}
static void mixer_set_bchannel_id_esc(PLCI *plci, byte bchannel_id)
{
DIVA_CAPI_ADAPTER *a;
PLCI *splci;
byte old_id;
a = plci->adapter;
old_id = plci->li_bchannel_id;
if (a->li_pri)
{
if ((old_id != 0) && (li_config_table[a->li_base + (old_id - 1)].plci == plci))
li_config_table[a->li_base + (old_id - 1)].plci = NULL;
plci->li_bchannel_id = (bchannel_id & 0x1f) + 1;
if (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == NULL)
li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci = plci;
}
else
{
if (((bchannel_id & 0x03) == 1) || ((bchannel_id & 0x03) == 2))
{
if ((old_id != 0) && (li_config_table[a->li_base + (old_id - 1)].plci == plci))
li_config_table[a->li_base + (old_id - 1)].plci = NULL;
plci->li_bchannel_id = bchannel_id & 0x03;
if ((a->AdvSignalPLCI != NULL) && (a->AdvSignalPLCI != plci) && (a->AdvSignalPLCI->tel == ADV_VOICE))
{
splci = a->AdvSignalPLCI;
if (li_config_table[a->li_base + (2 - plci->li_bchannel_id)].plci == NULL)
{
if ((splci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (splci->li_bchannel_id - 1)].plci == splci))
{
li_config_table[a->li_base + (splci->li_bchannel_id - 1)].plci = NULL;
}
splci->li_bchannel_id = 3 - plci->li_bchannel_id;
li_config_table[a->li_base + (2 - plci->li_bchannel_id)].plci = splci;
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_set_bchannel_id_esc %d",
(dword)((splci->Id << 8) | UnMapController(splci->adapter->Id)),
(char *)(FILE_), __LINE__, splci->li_bchannel_id));
}
}
if (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == NULL)
li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci = plci;
}
}
if ((old_id == 0) && (plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
mixer_clear_config(plci);
}
dbug(1, dprintf("[%06lx] %s,%d: mixer_set_bchannel_id_esc %d %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, bchannel_id, plci->li_bchannel_id));
}
static void mixer_set_bchannel_id(PLCI *plci, byte *chi)
{
DIVA_CAPI_ADAPTER *a;
PLCI *splci;
byte ch, old_id;
a = plci->adapter;
old_id = plci->li_bchannel_id;
ch = chi_to_channel(chi, NULL);
if (!(ch & 0x80))
{
if (a->li_pri)
{
if ((old_id != 0) && (li_config_table[a->li_base + (old_id - 1)].plci == plci))
li_config_table[a->li_base + (old_id - 1)].plci = NULL;
plci->li_bchannel_id = (ch & 0x1f) + 1;
if (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == NULL)
li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci = plci;
}
else
{
if (((ch & 0x1f) == 1) || ((ch & 0x1f) == 2))
{
if ((old_id != 0) && (li_config_table[a->li_base + (old_id - 1)].plci == plci))
li_config_table[a->li_base + (old_id - 1)].plci = NULL;
plci->li_bchannel_id = ch & 0x1f;
if ((a->AdvSignalPLCI != NULL) && (a->AdvSignalPLCI != plci) && (a->AdvSignalPLCI->tel == ADV_VOICE))
{
splci = a->AdvSignalPLCI;
if (li_config_table[a->li_base + (2 - plci->li_bchannel_id)].plci == NULL)
{
if ((splci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (splci->li_bchannel_id - 1)].plci == splci))
{
li_config_table[a->li_base + (splci->li_bchannel_id - 1)].plci = NULL;
}
splci->li_bchannel_id = 3 - plci->li_bchannel_id;
li_config_table[a->li_base + (2 - plci->li_bchannel_id)].plci = splci;
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_set_bchannel_id %d",
(dword)((splci->Id << 8) | UnMapController(splci->adapter->Id)),
(char *)(FILE_), __LINE__, splci->li_bchannel_id));
}
}
if (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == NULL)
li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci = plci;
}
}
}
if ((old_id == 0) && (plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
mixer_clear_config(plci);
}
dbug(1, dprintf("[%06lx] %s,%d: mixer_set_bchannel_id %02x %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, ch, plci->li_bchannel_id));
}
#define MIXER_MAX_DUMP_CHANNELS 34
static void mixer_calculate_coefs(DIVA_CAPI_ADAPTER *a)
{
static char hex_digit_table[0x10] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'};
word n, i, j;
char *p;
char hex_line[2 * MIXER_MAX_DUMP_CHANNELS + MIXER_MAX_DUMP_CHANNELS / 8 + 4];
dbug(1, dprintf("[%06lx] %s,%d: mixer_calculate_coefs",
(dword)(UnMapController(a->Id)), (char *)(FILE_), __LINE__));
for (i = 0; i < li_total_channels; i++)
{
li_config_table[i].channel &= LI_CHANNEL_ADDRESSES_SET;
if (li_config_table[i].chflags != 0)
li_config_table[i].channel |= LI_CHANNEL_INVOLVED;
else
{
for (j = 0; j < li_total_channels; j++)
{
if (((li_config_table[i].flag_table[j]) != 0)
|| ((li_config_table[j].flag_table[i]) != 0))
{
li_config_table[i].channel |= LI_CHANNEL_INVOLVED;
}
if (((li_config_table[i].flag_table[j] & LI_FLAG_CONFERENCE) != 0)
|| ((li_config_table[j].flag_table[i] & LI_FLAG_CONFERENCE) != 0))
{
li_config_table[i].channel |= LI_CHANNEL_CONFERENCE;
}
}
}
}
for (i = 0; i < li_total_channels; i++)
{
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].coef_table[j] &= ~(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC);
if (li_config_table[i].flag_table[j] & LI_FLAG_CONFERENCE)
li_config_table[i].coef_table[j] |= LI_COEF_CH_CH;
}
}
for (n = 0; n < li_total_channels; n++)
{
if (li_config_table[n].channel & LI_CHANNEL_CONFERENCE)
{
for (i = 0; i < li_total_channels; i++)
{
if (li_config_table[i].channel & LI_CHANNEL_CONFERENCE)
{
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].coef_table[j] |=
li_config_table[i].coef_table[n] & li_config_table[n].coef_table[j];
}
}
}
}
}
for (i = 0; i < li_total_channels; i++)
{
if (li_config_table[i].channel & LI_CHANNEL_INVOLVED)
{
li_config_table[i].coef_table[i] &= ~LI_COEF_CH_CH;
for (j = 0; j < li_total_channels; j++)
{
if (li_config_table[i].coef_table[j] & LI_COEF_CH_CH)
li_config_table[i].flag_table[j] |= LI_FLAG_CONFERENCE;
}
if (li_config_table[i].flag_table[i] & LI_FLAG_CONFERENCE)
li_config_table[i].coef_table[i] |= LI_COEF_CH_CH;
}
}
for (i = 0; i < li_total_channels; i++)
{
if (li_config_table[i].channel & LI_CHANNEL_INVOLVED)
{
for (j = 0; j < li_total_channels; j++)
{
if (li_config_table[i].flag_table[j] & LI_FLAG_INTERCONNECT)
li_config_table[i].coef_table[j] |= LI_COEF_CH_CH;
if (li_config_table[i].flag_table[j] & LI_FLAG_MONITOR)
li_config_table[i].coef_table[j] |= LI_COEF_CH_PC;
if (li_config_table[i].flag_table[j] & LI_FLAG_MIX)
li_config_table[i].coef_table[j] |= LI_COEF_PC_CH;
if (li_config_table[i].flag_table[j] & LI_FLAG_PCCONNECT)
li_config_table[i].coef_table[j] |= LI_COEF_PC_PC;
}
if (li_config_table[i].chflags & LI_CHFLAG_MONITOR)
{
for (j = 0; j < li_total_channels; j++)
{
if (li_config_table[i].flag_table[j] & LI_FLAG_INTERCONNECT)
{
li_config_table[i].coef_table[j] |= LI_COEF_CH_PC;
if (li_config_table[j].chflags & LI_CHFLAG_MIX)
li_config_table[i].coef_table[j] |= LI_COEF_PC_CH | LI_COEF_PC_PC;
}
}
}
if (li_config_table[i].chflags & LI_CHFLAG_MIX)
{
for (j = 0; j < li_total_channels; j++)
{
if (li_config_table[j].flag_table[i] & LI_FLAG_INTERCONNECT)
li_config_table[j].coef_table[i] |= LI_COEF_PC_CH;
}
}
if (li_config_table[i].chflags & LI_CHFLAG_LOOP)
{
for (j = 0; j < li_total_channels; j++)
{
if (li_config_table[i].flag_table[j] & LI_FLAG_INTERCONNECT)
{
for (n = 0; n < li_total_channels; n++)
{
if (li_config_table[n].flag_table[i] & LI_FLAG_INTERCONNECT)
{
li_config_table[n].coef_table[j] |= LI_COEF_CH_CH;
if (li_config_table[j].chflags & LI_CHFLAG_MIX)
{
li_config_table[n].coef_table[j] |= LI_COEF_PC_CH;
if (li_config_table[n].chflags & LI_CHFLAG_MONITOR)
li_config_table[n].coef_table[j] |= LI_COEF_CH_PC | LI_COEF_PC_PC;
}
else if (li_config_table[n].chflags & LI_CHFLAG_MONITOR)
li_config_table[n].coef_table[j] |= LI_COEF_CH_PC;
}
}
}
}
}
}
}
for (i = 0; i < li_total_channels; i++)
{
if (li_config_table[i].channel & LI_CHANNEL_INVOLVED)
{
if (li_config_table[i].chflags & (LI_CHFLAG_MONITOR | LI_CHFLAG_MIX | LI_CHFLAG_LOOP))
li_config_table[i].channel |= LI_CHANNEL_ACTIVE;
if (li_config_table[i].chflags & LI_CHFLAG_MONITOR)
li_config_table[i].channel |= LI_CHANNEL_RX_DATA;
if (li_config_table[i].chflags & LI_CHFLAG_MIX)
li_config_table[i].channel |= LI_CHANNEL_TX_DATA;
for (j = 0; j < li_total_channels; j++)
{
if ((li_config_table[i].flag_table[j] &
(LI_FLAG_INTERCONNECT | LI_FLAG_PCCONNECT | LI_FLAG_CONFERENCE | LI_FLAG_MONITOR))
|| (li_config_table[j].flag_table[i] &
(LI_FLAG_INTERCONNECT | LI_FLAG_PCCONNECT | LI_FLAG_CONFERENCE | LI_FLAG_ANNOUNCEMENT | LI_FLAG_MIX)))
{
li_config_table[i].channel |= LI_CHANNEL_ACTIVE;
}
if (li_config_table[i].flag_table[j] & (LI_FLAG_PCCONNECT | LI_FLAG_MONITOR))
li_config_table[i].channel |= LI_CHANNEL_RX_DATA;
if (li_config_table[j].flag_table[i] & (LI_FLAG_PCCONNECT | LI_FLAG_ANNOUNCEMENT | LI_FLAG_MIX))
li_config_table[i].channel |= LI_CHANNEL_TX_DATA;
}
if (!(li_config_table[i].channel & LI_CHANNEL_ACTIVE))
{
li_config_table[i].coef_table[i] |= LI_COEF_PC_CH | LI_COEF_CH_PC;
li_config_table[i].channel |= LI_CHANNEL_TX_DATA | LI_CHANNEL_RX_DATA;
}
}
}
for (i = 0; i < li_total_channels; i++)
{
if (li_config_table[i].channel & LI_CHANNEL_INVOLVED)
{
j = 0;
while ((j < li_total_channels) && !(li_config_table[i].flag_table[j] & LI_FLAG_ANNOUNCEMENT))
j++;
if (j < li_total_channels)
{
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].coef_table[j] &= ~(LI_COEF_CH_CH | LI_COEF_PC_CH);
if (li_config_table[i].flag_table[j] & LI_FLAG_ANNOUNCEMENT)
li_config_table[i].coef_table[j] |= LI_COEF_PC_CH;
}
}
}
}
n = li_total_channels;
if (n > MIXER_MAX_DUMP_CHANNELS)
n = MIXER_MAX_DUMP_CHANNELS;
p = hex_line;
for (j = 0; j < n; j++)
{
if ((j & 0x7) == 0)
*(p++) = ' ';
*(p++) = hex_digit_table[li_config_table[j].curchnl >> 4];
*(p++) = hex_digit_table[li_config_table[j].curchnl & 0xf];
}
*p = '\0';
dbug(1, dprintf("[%06lx] CURRENT %s",
(dword)(UnMapController(a->Id)), (char *)hex_line));
p = hex_line;
for (j = 0; j < n; j++)
{
if ((j & 0x7) == 0)
*(p++) = ' ';
*(p++) = hex_digit_table[li_config_table[j].channel >> 4];
*(p++) = hex_digit_table[li_config_table[j].channel & 0xf];
}
*p = '\0';
dbug(1, dprintf("[%06lx] CHANNEL %s",
(dword)(UnMapController(a->Id)), (char *)hex_line));
p = hex_line;
for (j = 0; j < n; j++)
{
if ((j & 0x7) == 0)
*(p++) = ' ';
*(p++) = hex_digit_table[li_config_table[j].chflags >> 4];
*(p++) = hex_digit_table[li_config_table[j].chflags & 0xf];
}
*p = '\0';
dbug(1, dprintf("[%06lx] CHFLAG %s",
(dword)(UnMapController(a->Id)), (char *)hex_line));
for (i = 0; i < n; i++)
{
p = hex_line;
for (j = 0; j < n; j++)
{
if ((j & 0x7) == 0)
*(p++) = ' ';
*(p++) = hex_digit_table[li_config_table[i].flag_table[j] >> 4];
*(p++) = hex_digit_table[li_config_table[i].flag_table[j] & 0xf];
}
*p = '\0';
dbug(1, dprintf("[%06lx] FLAG[%02x]%s",
(dword)(UnMapController(a->Id)), i, (char *)hex_line));
}
for (i = 0; i < n; i++)
{
p = hex_line;
for (j = 0; j < n; j++)
{
if ((j & 0x7) == 0)
*(p++) = ' ';
*(p++) = hex_digit_table[li_config_table[i].coef_table[j] >> 4];
*(p++) = hex_digit_table[li_config_table[i].coef_table[j] & 0xf];
}
*p = '\0';
dbug(1, dprintf("[%06lx] COEF[%02x]%s",
(dword)(UnMapController(a->Id)), i, (char *)hex_line));
}
}
static struct
{
byte mask;
byte line_flags;
} mixer_write_prog_pri[] =
{
{ LI_COEF_CH_CH, 0 },
{ LI_COEF_CH_PC, MIXER_COEF_LINE_TO_PC_FLAG },
{ LI_COEF_PC_CH, MIXER_COEF_LINE_FROM_PC_FLAG },
{ LI_COEF_PC_PC, MIXER_COEF_LINE_TO_PC_FLAG | MIXER_COEF_LINE_FROM_PC_FLAG }
};
static struct
{
byte from_ch;
byte to_ch;
byte mask;
byte xconnect_override;
} mixer_write_prog_bri[] =
{
{ 0, 0, LI_COEF_CH_CH, 0x01 }, /* B to B */
{ 1, 0, LI_COEF_CH_CH, 0x01 }, /* Alt B to B */
{ 0, 0, LI_COEF_PC_CH, 0x80 }, /* PC to B */
{ 1, 0, LI_COEF_PC_CH, 0x01 }, /* Alt PC to B */
{ 2, 0, LI_COEF_CH_CH, 0x00 }, /* IC to B */
{ 3, 0, LI_COEF_CH_CH, 0x00 }, /* Alt IC to B */
{ 0, 0, LI_COEF_CH_PC, 0x80 }, /* B to PC */
{ 1, 0, LI_COEF_CH_PC, 0x01 }, /* Alt B to PC */
{ 0, 0, LI_COEF_PC_PC, 0x01 }, /* PC to PC */
{ 1, 0, LI_COEF_PC_PC, 0x01 }, /* Alt PC to PC */
{ 2, 0, LI_COEF_CH_PC, 0x00 }, /* IC to PC */
{ 3, 0, LI_COEF_CH_PC, 0x00 }, /* Alt IC to PC */
{ 0, 2, LI_COEF_CH_CH, 0x00 }, /* B to IC */
{ 1, 2, LI_COEF_CH_CH, 0x00 }, /* Alt B to IC */
{ 0, 2, LI_COEF_PC_CH, 0x00 }, /* PC to IC */
{ 1, 2, LI_COEF_PC_CH, 0x00 }, /* Alt PC to IC */
{ 2, 2, LI_COEF_CH_CH, 0x00 }, /* IC to IC */
{ 3, 2, LI_COEF_CH_CH, 0x00 }, /* Alt IC to IC */
{ 1, 1, LI_COEF_CH_CH, 0x01 }, /* Alt B to Alt B */
{ 0, 1, LI_COEF_CH_CH, 0x01 }, /* B to Alt B */
{ 1, 1, LI_COEF_PC_CH, 0x80 }, /* Alt PC to Alt B */
{ 0, 1, LI_COEF_PC_CH, 0x01 }, /* PC to Alt B */
{ 3, 1, LI_COEF_CH_CH, 0x00 }, /* Alt IC to Alt B */
{ 2, 1, LI_COEF_CH_CH, 0x00 }, /* IC to Alt B */
{ 1, 1, LI_COEF_CH_PC, 0x80 }, /* Alt B to Alt PC */
{ 0, 1, LI_COEF_CH_PC, 0x01 }, /* B to Alt PC */
{ 1, 1, LI_COEF_PC_PC, 0x01 }, /* Alt PC to Alt PC */
{ 0, 1, LI_COEF_PC_PC, 0x01 }, /* PC to Alt PC */
{ 3, 1, LI_COEF_CH_PC, 0x00 }, /* Alt IC to Alt PC */
{ 2, 1, LI_COEF_CH_PC, 0x00 }, /* IC to Alt PC */
{ 1, 3, LI_COEF_CH_CH, 0x00 }, /* Alt B to Alt IC */
{ 0, 3, LI_COEF_CH_CH, 0x00 }, /* B to Alt IC */
{ 1, 3, LI_COEF_PC_CH, 0x00 }, /* Alt PC to Alt IC */
{ 0, 3, LI_COEF_PC_CH, 0x00 }, /* PC to Alt IC */
{ 3, 3, LI_COEF_CH_CH, 0x00 }, /* Alt IC to Alt IC */
{ 2, 3, LI_COEF_CH_CH, 0x00 } /* IC to Alt IC */
};
static byte mixer_swapped_index_bri[] =
{
18, /* B to B */
19, /* Alt B to B */
20, /* PC to B */
21, /* Alt PC to B */
22, /* IC to B */
23, /* Alt IC to B */
24, /* B to PC */
25, /* Alt B to PC */
26, /* PC to PC */
27, /* Alt PC to PC */
28, /* IC to PC */
29, /* Alt IC to PC */
30, /* B to IC */
31, /* Alt B to IC */
32, /* PC to IC */
33, /* Alt PC to IC */
34, /* IC to IC */
35, /* Alt IC to IC */
0, /* Alt B to Alt B */
1, /* B to Alt B */
2, /* Alt PC to Alt B */
3, /* PC to Alt B */
4, /* Alt IC to Alt B */
5, /* IC to Alt B */
6, /* Alt B to Alt PC */
7, /* B to Alt PC */
8, /* Alt PC to Alt PC */
9, /* PC to Alt PC */
10, /* Alt IC to Alt PC */
11, /* IC to Alt PC */
12, /* Alt B to Alt IC */
13, /* B to Alt IC */
14, /* Alt PC to Alt IC */
15, /* PC to Alt IC */
16, /* Alt IC to Alt IC */
17 /* IC to Alt IC */
};
static struct
{
byte mask;
byte from_pc;
byte to_pc;
} xconnect_write_prog[] =
{
{ LI_COEF_CH_CH, false, false },
{ LI_COEF_CH_PC, false, true },
{ LI_COEF_PC_CH, true, false },
{ LI_COEF_PC_PC, true, true }
};
static void xconnect_query_addresses(PLCI *plci)
{
DIVA_CAPI_ADAPTER *a;
word w, ch;
byte *p;
dbug(1, dprintf("[%06lx] %s,%d: xconnect_query_addresses",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
a = plci->adapter;
if (a->li_pri && ((plci->li_bchannel_id == 0)
|| (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci != plci)))
{
dbug(1, dprintf("[%06x] %s,%d: Channel id wiped out",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
return;
}
p = plci->internal_req_buffer;
ch = (a->li_pri) ? plci->li_bchannel_id - 1 : 0;
*(p++) = UDATA_REQUEST_XCONNECT_FROM;
w = ch;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
w = ch | XCONNECT_CHANNEL_PORT_PC;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
plci->NData[0].P = plci->internal_req_buffer;
plci->NData[0].PLength = p - plci->internal_req_buffer;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_UDATA;
plci->adapter->request(&plci->NL);
}
static void xconnect_write_coefs(PLCI *plci, word internal_command)
{
dbug(1, dprintf("[%06lx] %s,%d: xconnect_write_coefs %04x",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, internal_command));
plci->li_write_command = internal_command;
plci->li_write_channel = 0;
}
static byte xconnect_write_coefs_process(dword Id, PLCI *plci, byte Rc)
{
DIVA_CAPI_ADAPTER *a;
word w, n, i, j, r, s, to_ch;
dword d;
byte *p;
struct xconnect_transfer_address_s *transfer_address;
byte ch_map[MIXER_CHANNELS_BRI];
dbug(1, dprintf("[%06x] %s,%d: xconnect_write_coefs_process %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->li_write_channel));
a = plci->adapter;
if ((plci->li_bchannel_id == 0)
|| (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci != plci))
{
dbug(1, dprintf("[%06x] %s,%d: Channel id wiped out",
UnMapId(Id), (char *)(FILE_), __LINE__));
return (true);
}
i = a->li_base + (plci->li_bchannel_id - 1);
j = plci->li_write_channel;
p = plci->internal_req_buffer;
if (j != 0)
{
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: LI write coefs failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
return (false);
}
}
if (li_config_table[i].adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
{
r = 0;
s = 0;
if (j < li_total_channels)
{
if (li_config_table[i].channel & LI_CHANNEL_ADDRESSES_SET)
{
s = ((li_config_table[i].send_b.card_address.low | li_config_table[i].send_b.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_CH_PC | LI_COEF_PC_PC)) &
((li_config_table[i].send_pc.card_address.low | li_config_table[i].send_pc.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_CH_CH | LI_COEF_PC_CH));
}
r = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
while ((j < li_total_channels)
&& ((r == 0)
|| (!(li_config_table[j].channel & LI_CHANNEL_ADDRESSES_SET))
|| (!li_config_table[j].adapter->li_pri
&& (j >= li_config_table[j].adapter->li_base + MIXER_BCHANNELS_BRI))
|| (((li_config_table[j].send_b.card_address.low != li_config_table[i].send_b.card_address.low)
|| (li_config_table[j].send_b.card_address.high != li_config_table[i].send_b.card_address.high))
&& (!(a->manufacturer_features & MANUFACTURER_FEATURE_DMACONNECT)
|| !(li_config_table[j].adapter->manufacturer_features & MANUFACTURER_FEATURE_DMACONNECT)))
|| ((li_config_table[j].adapter->li_base != a->li_base)
&& !(r & s &
((li_config_table[j].send_b.card_address.low | li_config_table[j].send_b.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_PC_CH | LI_COEF_PC_PC)) &
((li_config_table[j].send_pc.card_address.low | li_config_table[j].send_pc.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_CH_CH | LI_COEF_CH_PC))))))
{
j++;
if (j < li_total_channels)
r = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
}
}
if (j < li_total_channels)
{
plci->internal_command = plci->li_write_command;
if (plci_nl_busy(plci))
return (true);
to_ch = (a->li_pri) ? plci->li_bchannel_id - 1 : 0;
*(p++) = UDATA_REQUEST_XCONNECT_TO;
do
{
if (li_config_table[j].adapter->li_base != a->li_base)
{
r &= s &
((li_config_table[j].send_b.card_address.low | li_config_table[j].send_b.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_PC_CH | LI_COEF_PC_PC)) &
((li_config_table[j].send_pc.card_address.low | li_config_table[j].send_pc.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_CH_CH | LI_COEF_CH_PC));
}
n = 0;
do
{
if (r & xconnect_write_prog[n].mask)
{
if (xconnect_write_prog[n].from_pc)
transfer_address = &(li_config_table[j].send_pc);
else
transfer_address = &(li_config_table[j].send_b);
d = transfer_address->card_address.low;
*(p++) = (byte) d;
*(p++) = (byte)(d >> 8);
*(p++) = (byte)(d >> 16);
*(p++) = (byte)(d >> 24);
d = transfer_address->card_address.high;
*(p++) = (byte) d;
*(p++) = (byte)(d >> 8);
*(p++) = (byte)(d >> 16);
*(p++) = (byte)(d >> 24);
d = transfer_address->offset;
*(p++) = (byte) d;
*(p++) = (byte)(d >> 8);
*(p++) = (byte)(d >> 16);
*(p++) = (byte)(d >> 24);
w = xconnect_write_prog[n].to_pc ? to_ch | XCONNECT_CHANNEL_PORT_PC : to_ch;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
w = ((li_config_table[i].coef_table[j] & xconnect_write_prog[n].mask) == 0) ? 0x01 :
(li_config_table[i].adapter->u_law ?
(li_config_table[j].adapter->u_law ? 0x80 : 0x86) :
(li_config_table[j].adapter->u_law ? 0x7a : 0x80));
*(p++) = (byte) w;
*(p++) = (byte) 0;
li_config_table[i].coef_table[j] ^= xconnect_write_prog[n].mask << 4;
}
n++;
} while ((n < ARRAY_SIZE(xconnect_write_prog))
&& ((p - plci->internal_req_buffer) + 16 < INTERNAL_REQ_BUFFER_SIZE));
if (n == ARRAY_SIZE(xconnect_write_prog))
{
do
{
j++;
if (j < li_total_channels)
r = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
} while ((j < li_total_channels)
&& ((r == 0)
|| (!(li_config_table[j].channel & LI_CHANNEL_ADDRESSES_SET))
|| (!li_config_table[j].adapter->li_pri
&& (j >= li_config_table[j].adapter->li_base + MIXER_BCHANNELS_BRI))
|| (((li_config_table[j].send_b.card_address.low != li_config_table[i].send_b.card_address.low)
|| (li_config_table[j].send_b.card_address.high != li_config_table[i].send_b.card_address.high))
&& (!(a->manufacturer_features & MANUFACTURER_FEATURE_DMACONNECT)
|| !(li_config_table[j].adapter->manufacturer_features & MANUFACTURER_FEATURE_DMACONNECT)))
|| ((li_config_table[j].adapter->li_base != a->li_base)
&& !(r & s &
((li_config_table[j].send_b.card_address.low | li_config_table[j].send_b.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_PC_CH | LI_COEF_PC_PC)) &
((li_config_table[j].send_pc.card_address.low | li_config_table[j].send_pc.card_address.high) ?
(LI_COEF_CH_CH | LI_COEF_CH_PC | LI_COEF_PC_CH | LI_COEF_PC_PC) : (LI_COEF_CH_CH | LI_COEF_CH_PC))))));
}
} while ((j < li_total_channels)
&& ((p - plci->internal_req_buffer) + 16 < INTERNAL_REQ_BUFFER_SIZE));
}
else if (j == li_total_channels)
{
plci->internal_command = plci->li_write_command;
if (plci_nl_busy(plci))
return (true);
if (a->li_pri)
{
*(p++) = UDATA_REQUEST_SET_MIXER_COEFS_PRI_SYNC;
w = 0;
if (li_config_table[i].channel & LI_CHANNEL_TX_DATA)
w |= MIXER_FEATURE_ENABLE_TX_DATA;
if (li_config_table[i].channel & LI_CHANNEL_RX_DATA)
w |= MIXER_FEATURE_ENABLE_RX_DATA;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
}
else
{
*(p++) = UDATA_REQUEST_SET_MIXER_COEFS_BRI;
w = 0;
if ((plci->tel == ADV_VOICE) && (plci == a->AdvSignalPLCI)
&& (ADV_VOICE_NEW_COEF_BASE + sizeof(word) <= a->adv_voice_coef_length))
{
w = GET_WORD(a->adv_voice_coef_buffer + ADV_VOICE_NEW_COEF_BASE);
}
if (li_config_table[i].channel & LI_CHANNEL_TX_DATA)
w |= MIXER_FEATURE_ENABLE_TX_DATA;
if (li_config_table[i].channel & LI_CHANNEL_RX_DATA)
w |= MIXER_FEATURE_ENABLE_RX_DATA;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
for (j = 0; j < sizeof(ch_map); j += 2)
{
if (plci->li_bchannel_id == 2)
{
ch_map[j] = (byte)(j + 1);
ch_map[j + 1] = (byte) j;
}
else
{
ch_map[j] = (byte) j;
ch_map[j + 1] = (byte)(j + 1);
}
}
for (n = 0; n < ARRAY_SIZE(mixer_write_prog_bri); n++)
{
i = a->li_base + ch_map[mixer_write_prog_bri[n].to_ch];
j = a->li_base + ch_map[mixer_write_prog_bri[n].from_ch];
if (li_config_table[i].channel & li_config_table[j].channel & LI_CHANNEL_INVOLVED)
{
*p = (mixer_write_prog_bri[n].xconnect_override != 0) ?
mixer_write_prog_bri[n].xconnect_override :
((li_config_table[i].coef_table[j] & mixer_write_prog_bri[n].mask) ? 0x80 : 0x01);
if ((i >= a->li_base + MIXER_BCHANNELS_BRI) || (j >= a->li_base + MIXER_BCHANNELS_BRI))
{
w = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
li_config_table[i].coef_table[j] ^= (w & mixer_write_prog_bri[n].mask) << 4;
}
}
else
{
*p = 0x00;
if ((a->AdvSignalPLCI != NULL) && (a->AdvSignalPLCI->tel == ADV_VOICE))
{
w = (plci == a->AdvSignalPLCI) ? n : mixer_swapped_index_bri[n];
if (ADV_VOICE_NEW_COEF_BASE + sizeof(word) + w < a->adv_voice_coef_length)
*p = a->adv_voice_coef_buffer[ADV_VOICE_NEW_COEF_BASE + sizeof(word) + w];
}
}
p++;
}
}
j = li_total_channels + 1;
}
}
else
{
if (j <= li_total_channels)
{
plci->internal_command = plci->li_write_command;
if (plci_nl_busy(plci))
return (true);
if (j < a->li_base)
j = a->li_base;
if (a->li_pri)
{
*(p++) = UDATA_REQUEST_SET_MIXER_COEFS_PRI_SYNC;
w = 0;
if (li_config_table[i].channel & LI_CHANNEL_TX_DATA)
w |= MIXER_FEATURE_ENABLE_TX_DATA;
if (li_config_table[i].channel & LI_CHANNEL_RX_DATA)
w |= MIXER_FEATURE_ENABLE_RX_DATA;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
for (n = 0; n < ARRAY_SIZE(mixer_write_prog_pri); n++)
{
*(p++) = (byte)((plci->li_bchannel_id - 1) | mixer_write_prog_pri[n].line_flags);
for (j = a->li_base; j < a->li_base + MIXER_CHANNELS_PRI; j++)
{
w = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
if (w & mixer_write_prog_pri[n].mask)
{
*(p++) = (li_config_table[i].coef_table[j] & mixer_write_prog_pri[n].mask) ? 0x80 : 0x01;
li_config_table[i].coef_table[j] ^= mixer_write_prog_pri[n].mask << 4;
}
else
*(p++) = 0x00;
}
*(p++) = (byte)((plci->li_bchannel_id - 1) | MIXER_COEF_LINE_ROW_FLAG | mixer_write_prog_pri[n].line_flags);
for (j = a->li_base; j < a->li_base + MIXER_CHANNELS_PRI; j++)
{
w = ((li_config_table[j].coef_table[i] & 0xf) ^ (li_config_table[j].coef_table[i] >> 4));
if (w & mixer_write_prog_pri[n].mask)
{
*(p++) = (li_config_table[j].coef_table[i] & mixer_write_prog_pri[n].mask) ? 0x80 : 0x01;
li_config_table[j].coef_table[i] ^= mixer_write_prog_pri[n].mask << 4;
}
else
*(p++) = 0x00;
}
}
}
else
{
*(p++) = UDATA_REQUEST_SET_MIXER_COEFS_BRI;
w = 0;
if ((plci->tel == ADV_VOICE) && (plci == a->AdvSignalPLCI)
&& (ADV_VOICE_NEW_COEF_BASE + sizeof(word) <= a->adv_voice_coef_length))
{
w = GET_WORD(a->adv_voice_coef_buffer + ADV_VOICE_NEW_COEF_BASE);
}
if (li_config_table[i].channel & LI_CHANNEL_TX_DATA)
w |= MIXER_FEATURE_ENABLE_TX_DATA;
if (li_config_table[i].channel & LI_CHANNEL_RX_DATA)
w |= MIXER_FEATURE_ENABLE_RX_DATA;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
for (j = 0; j < sizeof(ch_map); j += 2)
{
if (plci->li_bchannel_id == 2)
{
ch_map[j] = (byte)(j + 1);
ch_map[j + 1] = (byte) j;
}
else
{
ch_map[j] = (byte) j;
ch_map[j + 1] = (byte)(j + 1);
}
}
for (n = 0; n < ARRAY_SIZE(mixer_write_prog_bri); n++)
{
i = a->li_base + ch_map[mixer_write_prog_bri[n].to_ch];
j = a->li_base + ch_map[mixer_write_prog_bri[n].from_ch];
if (li_config_table[i].channel & li_config_table[j].channel & LI_CHANNEL_INVOLVED)
{
*p = ((li_config_table[i].coef_table[j] & mixer_write_prog_bri[n].mask) ? 0x80 : 0x01);
w = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
li_config_table[i].coef_table[j] ^= (w & mixer_write_prog_bri[n].mask) << 4;
}
else
{
*p = 0x00;
if ((a->AdvSignalPLCI != NULL) && (a->AdvSignalPLCI->tel == ADV_VOICE))
{
w = (plci == a->AdvSignalPLCI) ? n : mixer_swapped_index_bri[n];
if (ADV_VOICE_NEW_COEF_BASE + sizeof(word) + w < a->adv_voice_coef_length)
*p = a->adv_voice_coef_buffer[ADV_VOICE_NEW_COEF_BASE + sizeof(word) + w];
}
}
p++;
}
}
j = li_total_channels + 1;
}
}
plci->li_write_channel = j;
if (p != plci->internal_req_buffer)
{
plci->NData[0].P = plci->internal_req_buffer;
plci->NData[0].PLength = p - plci->internal_req_buffer;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_UDATA;
plci->adapter->request(&plci->NL);
}
return (true);
}
static void mixer_notify_update(PLCI *plci, byte others)
{
DIVA_CAPI_ADAPTER *a;
word i, w;
PLCI *notify_plci;
byte msg[sizeof(CAPI_MSG_HEADER) + 6];
dbug(1, dprintf("[%06lx] %s,%d: mixer_notify_update %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, others));
a = plci->adapter;
if (a->profile.Global_Options & GL_LINE_INTERCONNECT_SUPPORTED)
{
if (others)
plci->li_notify_update = true;
i = 0;
do
{
notify_plci = NULL;
if (others)
{
while ((i < li_total_channels) && (li_config_table[i].plci == NULL))
i++;
if (i < li_total_channels)
notify_plci = li_config_table[i++].plci;
}
else
{
if ((plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
notify_plci = plci;
}
}
if ((notify_plci != NULL)
&& !notify_plci->li_notify_update
&& (notify_plci->appl != NULL)
&& (notify_plci->State)
&& notify_plci->NL.Id && !notify_plci->nl_remove_id)
{
notify_plci->li_notify_update = true;
((CAPI_MSG *) msg)->header.length = 18;
((CAPI_MSG *) msg)->header.appl_id = notify_plci->appl->Id;
((CAPI_MSG *) msg)->header.command = _FACILITY_R;
((CAPI_MSG *) msg)->header.number = 0;
((CAPI_MSG *) msg)->header.controller = notify_plci->adapter->Id;
((CAPI_MSG *) msg)->header.plci = notify_plci->Id;
((CAPI_MSG *) msg)->header.ncci = 0;
((CAPI_MSG *) msg)->info.facility_req.Selector = SELECTOR_LINE_INTERCONNECT;
((CAPI_MSG *) msg)->info.facility_req.structs[0] = 3;
PUT_WORD(&(((CAPI_MSG *) msg)->info.facility_req.structs[1]), LI_REQ_SILENT_UPDATE);
((CAPI_MSG *) msg)->info.facility_req.structs[3] = 0;
w = api_put(notify_plci->appl, (CAPI_MSG *) msg);
if (w != _QUEUE_FULL)
{
if (w != 0)
{
dbug(1, dprintf("[%06lx] %s,%d: Interconnect notify failed %06x %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__,
(dword)((notify_plci->Id << 8) | UnMapController(notify_plci->adapter->Id)), w));
}
notify_plci->li_notify_update = false;
}
}
} while (others && (notify_plci != NULL));
if (others)
plci->li_notify_update = false;
}
}
static void mixer_clear_config(PLCI *plci)
{
DIVA_CAPI_ADAPTER *a;
word i, j;
dbug(1, dprintf("[%06lx] %s,%d: mixer_clear_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->li_notify_update = false;
plci->li_plci_b_write_pos = 0;
plci->li_plci_b_read_pos = 0;
plci->li_plci_b_req_pos = 0;
a = plci->adapter;
if ((plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
i = a->li_base + (plci->li_bchannel_id - 1);
li_config_table[i].curchnl = 0;
li_config_table[i].channel = 0;
li_config_table[i].chflags = 0;
for (j = 0; j < li_total_channels; j++)
{
li_config_table[j].flag_table[i] = 0;
li_config_table[i].flag_table[j] = 0;
li_config_table[i].coef_table[j] = 0;
li_config_table[j].coef_table[i] = 0;
}
if (!a->li_pri)
{
li_config_table[i].coef_table[i] |= LI_COEF_CH_PC_SET | LI_COEF_PC_CH_SET;
if ((plci->tel == ADV_VOICE) && (plci == a->AdvSignalPLCI))
{
i = a->li_base + MIXER_IC_CHANNEL_BASE + (plci->li_bchannel_id - 1);
li_config_table[i].curchnl = 0;
li_config_table[i].channel = 0;
li_config_table[i].chflags = 0;
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].flag_table[j] = 0;
li_config_table[j].flag_table[i] = 0;
li_config_table[i].coef_table[j] = 0;
li_config_table[j].coef_table[i] = 0;
}
if (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC)
{
i = a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id);
li_config_table[i].curchnl = 0;
li_config_table[i].channel = 0;
li_config_table[i].chflags = 0;
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].flag_table[j] = 0;
li_config_table[j].flag_table[i] = 0;
li_config_table[i].coef_table[j] = 0;
li_config_table[j].coef_table[i] = 0;
}
}
}
}
}
}
static void mixer_prepare_switch(dword Id, PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: mixer_prepare_switch",
UnMapId(Id), (char *)(FILE_), __LINE__));
do
{
mixer_indication_coefs_set(Id, plci);
} while (plci->li_plci_b_read_pos != plci->li_plci_b_req_pos);
}
static word mixer_save_config(dword Id, PLCI *plci, byte Rc)
{
DIVA_CAPI_ADAPTER *a;
word i, j;
dbug(1, dprintf("[%06lx] %s,%d: mixer_save_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
a = plci->adapter;
if ((plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
i = a->li_base + (plci->li_bchannel_id - 1);
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].coef_table[j] &= 0xf;
li_config_table[j].coef_table[i] &= 0xf;
}
if (!a->li_pri)
li_config_table[i].coef_table[i] |= LI_COEF_CH_PC_SET | LI_COEF_PC_CH_SET;
}
return (GOOD);
}
static word mixer_restore_config(dword Id, PLCI *plci, byte Rc)
{
DIVA_CAPI_ADAPTER *a;
word Info;
dbug(1, dprintf("[%06lx] %s,%d: mixer_restore_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
Info = GOOD;
a = plci->adapter;
if ((plci->B1_facilities & B1_FACILITY_MIXER)
&& (plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
switch (plci->adjust_b_state)
{
case ADJUST_B_RESTORE_MIXER_1:
if (a->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
{
plci->internal_command = plci->adjust_b_command;
if (plci_nl_busy(plci))
{
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_1;
break;
}
xconnect_query_addresses(plci);
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_2;
break;
}
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_5;
Rc = OK;
case ADJUST_B_RESTORE_MIXER_2:
case ADJUST_B_RESTORE_MIXER_3:
case ADJUST_B_RESTORE_MIXER_4:
if ((Rc != OK) && (Rc != OK_FC) && (Rc != 0))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B query addresses failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
if (Rc == OK)
{
if (plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_2)
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_3;
else if (plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_4)
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_5;
}
else if (Rc == 0)
{
if (plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_2)
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_4;
else if (plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_3)
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_5;
}
if (plci->adjust_b_state != ADJUST_B_RESTORE_MIXER_5)
{
plci->internal_command = plci->adjust_b_command;
break;
}
case ADJUST_B_RESTORE_MIXER_5:
xconnect_write_coefs(plci, plci->adjust_b_command);
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_6;
Rc = OK;
case ADJUST_B_RESTORE_MIXER_6:
if (!xconnect_write_coefs_process(Id, plci, Rc))
{
dbug(1, dprintf("[%06lx] %s,%d: Write mixer coefs failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (plci->internal_command)
break;
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_7;
case ADJUST_B_RESTORE_MIXER_7:
break;
}
}
return (Info);
}
static void mixer_command(dword Id, PLCI *plci, byte Rc)
{
DIVA_CAPI_ADAPTER *a;
word i, internal_command;
dbug(1, dprintf("[%06lx] %s,%d: mixer_command %02x %04x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command,
plci->li_cmd));
a = plci->adapter;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (plci->li_cmd)
{
case LI_REQ_CONNECT:
case LI_REQ_DISCONNECT:
case LI_REQ_SILENT_UPDATE:
switch (internal_command)
{
default:
if (plci->li_channel_bits & LI_CHANNEL_INVOLVED)
{
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities |
B1_FACILITY_MIXER), MIXER_COMMAND_1);
}
case MIXER_COMMAND_1:
if (plci->li_channel_bits & LI_CHANNEL_INVOLVED)
{
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Load mixer failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
}
plci->li_plci_b_req_pos = plci->li_plci_b_write_pos;
if ((plci->li_channel_bits & LI_CHANNEL_INVOLVED)
|| ((get_b1_facilities(plci, plci->B1_resource) & B1_FACILITY_MIXER)
&& (add_b1_facilities(plci, plci->B1_resource, (word)(plci->B1_facilities &
~B1_FACILITY_MIXER)) == plci->B1_resource)))
{
xconnect_write_coefs(plci, MIXER_COMMAND_2);
}
else
{
do
{
mixer_indication_coefs_set(Id, plci);
} while (plci->li_plci_b_read_pos != plci->li_plci_b_req_pos);
}
case MIXER_COMMAND_2:
if ((plci->li_channel_bits & LI_CHANNEL_INVOLVED)
|| ((get_b1_facilities(plci, plci->B1_resource) & B1_FACILITY_MIXER)
&& (add_b1_facilities(plci, plci->B1_resource, (word)(plci->B1_facilities &
~B1_FACILITY_MIXER)) == plci->B1_resource)))
{
if (!xconnect_write_coefs_process(Id, plci, Rc))
{
dbug(1, dprintf("[%06lx] %s,%d: Write mixer coefs failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
if (plci->li_plci_b_write_pos != plci->li_plci_b_req_pos)
{
do
{
plci->li_plci_b_write_pos = (plci->li_plci_b_write_pos == 0) ?
LI_PLCI_B_QUEUE_ENTRIES - 1 : plci->li_plci_b_write_pos - 1;
i = (plci->li_plci_b_write_pos == 0) ?
LI_PLCI_B_QUEUE_ENTRIES - 1 : plci->li_plci_b_write_pos - 1;
} while ((plci->li_plci_b_write_pos != plci->li_plci_b_req_pos)
&& !(plci->li_plci_b_queue[i] & LI_PLCI_B_LAST_FLAG));
}
break;
}
if (plci->internal_command)
return;
}
if (!(plci->li_channel_bits & LI_CHANNEL_INVOLVED))
{
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities &
~B1_FACILITY_MIXER), MIXER_COMMAND_3);
}
case MIXER_COMMAND_3:
if (!(plci->li_channel_bits & LI_CHANNEL_INVOLVED))
{
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Unload mixer failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
}
break;
}
break;
}
if ((plci->li_bchannel_id == 0)
|| (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci != plci))
{
dbug(1, dprintf("[%06x] %s,%d: Channel id wiped out %d",
UnMapId(Id), (char *)(FILE_), __LINE__, (int)(plci->li_bchannel_id)));
}
else
{
i = a->li_base + (plci->li_bchannel_id - 1);
li_config_table[i].curchnl = plci->li_channel_bits;
if (!a->li_pri && (plci->tel == ADV_VOICE) && (plci == a->AdvSignalPLCI))
{
i = a->li_base + MIXER_IC_CHANNEL_BASE + (plci->li_bchannel_id - 1);
li_config_table[i].curchnl = plci->li_channel_bits;
if (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC)
{
i = a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id);
li_config_table[i].curchnl = plci->li_channel_bits;
}
}
}
}
static void li_update_connect(dword Id, DIVA_CAPI_ADAPTER *a, PLCI *plci,
dword plci_b_id, byte connect, dword li_flags)
{
word i, ch_a, ch_a_v, ch_a_s, ch_b, ch_b_v, ch_b_s;
PLCI *plci_b;
DIVA_CAPI_ADAPTER *a_b;
a_b = &(adapter[MapController((byte)(plci_b_id & 0x7f)) - 1]);
plci_b = &(a_b->plci[((plci_b_id >> 8) & 0xff) - 1]);
ch_a = a->li_base + (plci->li_bchannel_id - 1);
if (!a->li_pri && (plci->tel == ADV_VOICE)
&& (plci == a->AdvSignalPLCI) && (Id & EXT_CONTROLLER))
{
ch_a_v = ch_a + MIXER_IC_CHANNEL_BASE;
ch_a_s = (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC) ?
a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id) : ch_a_v;
}
else
{
ch_a_v = ch_a;
ch_a_s = ch_a;
}
ch_b = a_b->li_base + (plci_b->li_bchannel_id - 1);
if (!a_b->li_pri && (plci_b->tel == ADV_VOICE)
&& (plci_b == a_b->AdvSignalPLCI) && (plci_b_id & EXT_CONTROLLER))
{
ch_b_v = ch_b + MIXER_IC_CHANNEL_BASE;
ch_b_s = (a_b->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC) ?
a_b->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci_b->li_bchannel_id) : ch_b_v;
}
else
{
ch_b_v = ch_b;
ch_b_s = ch_b;
}
if (connect)
{
li_config_table[ch_a].flag_table[ch_a_v] &= ~LI_FLAG_MONITOR;
li_config_table[ch_a].flag_table[ch_a_s] &= ~LI_FLAG_MONITOR;
li_config_table[ch_a_v].flag_table[ch_a] &= ~(LI_FLAG_ANNOUNCEMENT | LI_FLAG_MIX);
li_config_table[ch_a_s].flag_table[ch_a] &= ~(LI_FLAG_ANNOUNCEMENT | LI_FLAG_MIX);
}
li_config_table[ch_a].flag_table[ch_b_v] &= ~LI_FLAG_MONITOR;
li_config_table[ch_a].flag_table[ch_b_s] &= ~LI_FLAG_MONITOR;
li_config_table[ch_b_v].flag_table[ch_a] &= ~(LI_FLAG_ANNOUNCEMENT | LI_FLAG_MIX);
li_config_table[ch_b_s].flag_table[ch_a] &= ~(LI_FLAG_ANNOUNCEMENT | LI_FLAG_MIX);
if (ch_a_v == ch_b_v)
{
li_config_table[ch_a_v].flag_table[ch_b_v] &= ~LI_FLAG_CONFERENCE;
li_config_table[ch_a_s].flag_table[ch_b_s] &= ~LI_FLAG_CONFERENCE;
}
else
{
if (li_config_table[ch_a_v].flag_table[ch_b_v] & LI_FLAG_CONFERENCE)
{
for (i = 0; i < li_total_channels; i++)
{
if (i != ch_a_v)
li_config_table[ch_a_v].flag_table[i] &= ~LI_FLAG_CONFERENCE;
}
}
if (li_config_table[ch_a_s].flag_table[ch_b_v] & LI_FLAG_CONFERENCE)
{
for (i = 0; i < li_total_channels; i++)
{
if (i != ch_a_s)
li_config_table[ch_a_s].flag_table[i] &= ~LI_FLAG_CONFERENCE;
}
}
if (li_config_table[ch_b_v].flag_table[ch_a_v] & LI_FLAG_CONFERENCE)
{
for (i = 0; i < li_total_channels; i++)
{
if (i != ch_a_v)
li_config_table[i].flag_table[ch_a_v] &= ~LI_FLAG_CONFERENCE;
}
}
if (li_config_table[ch_b_v].flag_table[ch_a_s] & LI_FLAG_CONFERENCE)
{
for (i = 0; i < li_total_channels; i++)
{
if (i != ch_a_s)
li_config_table[i].flag_table[ch_a_s] &= ~LI_FLAG_CONFERENCE;
}
}
}
if (li_flags & LI_FLAG_CONFERENCE_A_B)
{
li_config_table[ch_b_v].flag_table[ch_a_v] |= LI_FLAG_CONFERENCE;
li_config_table[ch_b_s].flag_table[ch_a_v] |= LI_FLAG_CONFERENCE;
li_config_table[ch_b_v].flag_table[ch_a_s] |= LI_FLAG_CONFERENCE;
li_config_table[ch_b_s].flag_table[ch_a_s] |= LI_FLAG_CONFERENCE;
}
if (li_flags & LI_FLAG_CONFERENCE_B_A)
{
li_config_table[ch_a_v].flag_table[ch_b_v] |= LI_FLAG_CONFERENCE;
li_config_table[ch_a_v].flag_table[ch_b_s] |= LI_FLAG_CONFERENCE;
li_config_table[ch_a_s].flag_table[ch_b_v] |= LI_FLAG_CONFERENCE;
li_config_table[ch_a_s].flag_table[ch_b_s] |= LI_FLAG_CONFERENCE;
}
if (li_flags & LI_FLAG_MONITOR_A)
{
li_config_table[ch_a].flag_table[ch_a_v] |= LI_FLAG_MONITOR;
li_config_table[ch_a].flag_table[ch_a_s] |= LI_FLAG_MONITOR;
}
if (li_flags & LI_FLAG_MONITOR_B)
{
li_config_table[ch_a].flag_table[ch_b_v] |= LI_FLAG_MONITOR;
li_config_table[ch_a].flag_table[ch_b_s] |= LI_FLAG_MONITOR;
}
if (li_flags & LI_FLAG_ANNOUNCEMENT_A)
{
li_config_table[ch_a_v].flag_table[ch_a] |= LI_FLAG_ANNOUNCEMENT;
li_config_table[ch_a_s].flag_table[ch_a] |= LI_FLAG_ANNOUNCEMENT;
}
if (li_flags & LI_FLAG_ANNOUNCEMENT_B)
{
li_config_table[ch_b_v].flag_table[ch_a] |= LI_FLAG_ANNOUNCEMENT;
li_config_table[ch_b_s].flag_table[ch_a] |= LI_FLAG_ANNOUNCEMENT;
}
if (li_flags & LI_FLAG_MIX_A)
{
li_config_table[ch_a_v].flag_table[ch_a] |= LI_FLAG_MIX;
li_config_table[ch_a_s].flag_table[ch_a] |= LI_FLAG_MIX;
}
if (li_flags & LI_FLAG_MIX_B)
{
li_config_table[ch_b_v].flag_table[ch_a] |= LI_FLAG_MIX;
li_config_table[ch_b_s].flag_table[ch_a] |= LI_FLAG_MIX;
}
if (ch_a_v != ch_a_s)
{
li_config_table[ch_a_v].flag_table[ch_a_s] |= LI_FLAG_CONFERENCE;
li_config_table[ch_a_s].flag_table[ch_a_v] |= LI_FLAG_CONFERENCE;
}
if (ch_b_v != ch_b_s)
{
li_config_table[ch_b_v].flag_table[ch_b_s] |= LI_FLAG_CONFERENCE;
li_config_table[ch_b_s].flag_table[ch_b_v] |= LI_FLAG_CONFERENCE;
}
}
static void li2_update_connect(dword Id, DIVA_CAPI_ADAPTER *a, PLCI *plci,
dword plci_b_id, byte connect, dword li_flags)
{
word ch_a, ch_a_v, ch_a_s, ch_b, ch_b_v, ch_b_s;
PLCI *plci_b;
DIVA_CAPI_ADAPTER *a_b;
a_b = &(adapter[MapController((byte)(plci_b_id & 0x7f)) - 1]);
plci_b = &(a_b->plci[((plci_b_id >> 8) & 0xff) - 1]);
ch_a = a->li_base + (plci->li_bchannel_id - 1);
if (!a->li_pri && (plci->tel == ADV_VOICE)
&& (plci == a->AdvSignalPLCI) && (Id & EXT_CONTROLLER))
{
ch_a_v = ch_a + MIXER_IC_CHANNEL_BASE;
ch_a_s = (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC) ?
a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id) : ch_a_v;
}
else
{
ch_a_v = ch_a;
ch_a_s = ch_a;
}
ch_b = a_b->li_base + (plci_b->li_bchannel_id - 1);
if (!a_b->li_pri && (plci_b->tel == ADV_VOICE)
&& (plci_b == a_b->AdvSignalPLCI) && (plci_b_id & EXT_CONTROLLER))
{
ch_b_v = ch_b + MIXER_IC_CHANNEL_BASE;
ch_b_s = (a_b->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC) ?
a_b->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci_b->li_bchannel_id) : ch_b_v;
}
else
{
ch_b_v = ch_b;
ch_b_s = ch_b;
}
if (connect)
{
li_config_table[ch_b].flag_table[ch_b_v] &= ~LI_FLAG_MONITOR;
li_config_table[ch_b].flag_table[ch_b_s] &= ~LI_FLAG_MONITOR;
li_config_table[ch_b_v].flag_table[ch_b] &= ~LI_FLAG_MIX;
li_config_table[ch_b_s].flag_table[ch_b] &= ~LI_FLAG_MIX;
li_config_table[ch_b].flag_table[ch_b] &= ~LI_FLAG_PCCONNECT;
li_config_table[ch_b].chflags &= ~(LI_CHFLAG_MONITOR | LI_CHFLAG_MIX | LI_CHFLAG_LOOP);
}
li_config_table[ch_b_v].flag_table[ch_a_v] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_b_s].flag_table[ch_a_v] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_b_v].flag_table[ch_a_s] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_b_s].flag_table[ch_a_s] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_a_v].flag_table[ch_b_v] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_a_v].flag_table[ch_b_s] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_a_s].flag_table[ch_b_v] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
li_config_table[ch_a_s].flag_table[ch_b_s] &= ~(LI_FLAG_INTERCONNECT | LI_FLAG_CONFERENCE);
if (li_flags & LI2_FLAG_INTERCONNECT_A_B)
{
li_config_table[ch_b_v].flag_table[ch_a_v] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_b_s].flag_table[ch_a_v] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_b_v].flag_table[ch_a_s] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_b_s].flag_table[ch_a_s] |= LI_FLAG_INTERCONNECT;
}
if (li_flags & LI2_FLAG_INTERCONNECT_B_A)
{
li_config_table[ch_a_v].flag_table[ch_b_v] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_a_v].flag_table[ch_b_s] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_a_s].flag_table[ch_b_v] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_a_s].flag_table[ch_b_s] |= LI_FLAG_INTERCONNECT;
}
if (li_flags & LI2_FLAG_MONITOR_B)
{
li_config_table[ch_b].flag_table[ch_b_v] |= LI_FLAG_MONITOR;
li_config_table[ch_b].flag_table[ch_b_s] |= LI_FLAG_MONITOR;
}
if (li_flags & LI2_FLAG_MIX_B)
{
li_config_table[ch_b_v].flag_table[ch_b] |= LI_FLAG_MIX;
li_config_table[ch_b_s].flag_table[ch_b] |= LI_FLAG_MIX;
}
if (li_flags & LI2_FLAG_MONITOR_X)
li_config_table[ch_b].chflags |= LI_CHFLAG_MONITOR;
if (li_flags & LI2_FLAG_MIX_X)
li_config_table[ch_b].chflags |= LI_CHFLAG_MIX;
if (li_flags & LI2_FLAG_LOOP_B)
{
li_config_table[ch_b_v].flag_table[ch_b_v] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_b_s].flag_table[ch_b_v] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_b_v].flag_table[ch_b_s] |= LI_FLAG_INTERCONNECT;
li_config_table[ch_b_s].flag_table[ch_b_s] |= LI_FLAG_INTERCONNECT;
}
if (li_flags & LI2_FLAG_LOOP_PC)
li_config_table[ch_b].flag_table[ch_b] |= LI_FLAG_PCCONNECT;
if (li_flags & LI2_FLAG_LOOP_X)
li_config_table[ch_b].chflags |= LI_CHFLAG_LOOP;
if (li_flags & LI2_FLAG_PCCONNECT_A_B)
li_config_table[ch_b_s].flag_table[ch_a_s] |= LI_FLAG_PCCONNECT;
if (li_flags & LI2_FLAG_PCCONNECT_B_A)
li_config_table[ch_a_s].flag_table[ch_b_s] |= LI_FLAG_PCCONNECT;
if (ch_a_v != ch_a_s)
{
li_config_table[ch_a_v].flag_table[ch_a_s] |= LI_FLAG_CONFERENCE;
li_config_table[ch_a_s].flag_table[ch_a_v] |= LI_FLAG_CONFERENCE;
}
if (ch_b_v != ch_b_s)
{
li_config_table[ch_b_v].flag_table[ch_b_s] |= LI_FLAG_CONFERENCE;
li_config_table[ch_b_s].flag_table[ch_b_v] |= LI_FLAG_CONFERENCE;
}
}
static word li_check_main_plci(dword Id, PLCI *plci)
{
if (plci == NULL)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong PLCI",
UnMapId(Id), (char *)(FILE_), __LINE__));
return (_WRONG_IDENTIFIER);
}
if (!plci->State
|| !plci->NL.Id || plci->nl_remove_id
|| (plci->li_bchannel_id == 0))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong state",
UnMapId(Id), (char *)(FILE_), __LINE__));
return (_WRONG_STATE);
}
li_config_table[plci->adapter->li_base + (plci->li_bchannel_id - 1)].plci = plci;
return (GOOD);
}
static PLCI *li_check_plci_b(dword Id, PLCI *plci,
dword plci_b_id, word plci_b_write_pos, byte *p_result)
{
byte ctlr_b;
PLCI *plci_b;
if (((plci->li_plci_b_read_pos > plci_b_write_pos) ? plci->li_plci_b_read_pos :
LI_PLCI_B_QUEUE_ENTRIES + plci->li_plci_b_read_pos) - plci_b_write_pos - 1 < 2)
{
dbug(1, dprintf("[%06lx] %s,%d: LI request overrun",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(p_result, _REQUEST_NOT_ALLOWED_IN_THIS_STATE);
return (NULL);
}
ctlr_b = 0;
if ((plci_b_id & 0x7f) != 0)
{
ctlr_b = MapController((byte)(plci_b_id & 0x7f));
if ((ctlr_b > max_adapter) || ((ctlr_b != 0) && (adapter[ctlr_b - 1].request == NULL)))
ctlr_b = 0;
}
if ((ctlr_b == 0)
|| (((plci_b_id >> 8) & 0xff) == 0)
|| (((plci_b_id >> 8) & 0xff) > adapter[ctlr_b - 1].max_plci))
{
dbug(1, dprintf("[%06lx] %s,%d: LI invalid second PLCI %08lx",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b_id));
PUT_WORD(p_result, _WRONG_IDENTIFIER);
return (NULL);
}
plci_b = &(adapter[ctlr_b - 1].plci[((plci_b_id >> 8) & 0xff) - 1]);
if (!plci_b->State
|| !plci_b->NL.Id || plci_b->nl_remove_id
|| (plci_b->li_bchannel_id == 0))
{
dbug(1, dprintf("[%06lx] %s,%d: LI peer in wrong state %08lx",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b_id));
PUT_WORD(p_result, _REQUEST_NOT_ALLOWED_IN_THIS_STATE);
return (NULL);
}
li_config_table[plci_b->adapter->li_base + (plci_b->li_bchannel_id - 1)].plci = plci_b;
if (((byte)(plci_b_id & ~EXT_CONTROLLER)) !=
((byte)(UnMapController(plci->adapter->Id) & ~EXT_CONTROLLER))
&& (!(plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
|| !(plci_b->adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)))
{
dbug(1, dprintf("[%06lx] %s,%d: LI not on same ctrl %08lx",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b_id));
PUT_WORD(p_result, _WRONG_IDENTIFIER);
return (NULL);
}
if (!(get_b1_facilities(plci_b, add_b1_facilities(plci_b, plci_b->B1_resource,
(word)(plci_b->B1_facilities | B1_FACILITY_MIXER))) & B1_FACILITY_MIXER))
{
dbug(1, dprintf("[%06lx] %s,%d: Interconnect peer cannot mix %d",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b->B1_resource));
PUT_WORD(p_result, _REQUEST_NOT_ALLOWED_IN_THIS_STATE);
return (NULL);
}
return (plci_b);
}
static PLCI *li2_check_plci_b(dword Id, PLCI *plci,
dword plci_b_id, word plci_b_write_pos, byte *p_result)
{
byte ctlr_b;
PLCI *plci_b;
if (((plci->li_plci_b_read_pos > plci_b_write_pos) ? plci->li_plci_b_read_pos :
LI_PLCI_B_QUEUE_ENTRIES + plci->li_plci_b_read_pos) - plci_b_write_pos - 1 < 2)
{
dbug(1, dprintf("[%06lx] %s,%d: LI request overrun",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(p_result, _WRONG_STATE);
return (NULL);
}
ctlr_b = 0;
if ((plci_b_id & 0x7f) != 0)
{
ctlr_b = MapController((byte)(plci_b_id & 0x7f));
if ((ctlr_b > max_adapter) || ((ctlr_b != 0) && (adapter[ctlr_b - 1].request == NULL)))
ctlr_b = 0;
}
if ((ctlr_b == 0)
|| (((plci_b_id >> 8) & 0xff) == 0)
|| (((plci_b_id >> 8) & 0xff) > adapter[ctlr_b - 1].max_plci))
{
dbug(1, dprintf("[%06lx] %s,%d: LI invalid second PLCI %08lx",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b_id));
PUT_WORD(p_result, _WRONG_IDENTIFIER);
return (NULL);
}
plci_b = &(adapter[ctlr_b - 1].plci[((plci_b_id >> 8) & 0xff) - 1]);
if (!plci_b->State
|| !plci_b->NL.Id || plci_b->nl_remove_id
|| (plci_b->li_bchannel_id == 0)
|| (li_config_table[plci_b->adapter->li_base + (plci_b->li_bchannel_id - 1)].plci != plci_b))
{
dbug(1, dprintf("[%06lx] %s,%d: LI peer in wrong state %08lx",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b_id));
PUT_WORD(p_result, _WRONG_STATE);
return (NULL);
}
if (((byte)(plci_b_id & ~EXT_CONTROLLER)) !=
((byte)(UnMapController(plci->adapter->Id) & ~EXT_CONTROLLER))
&& (!(plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
|| !(plci_b->adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)))
{
dbug(1, dprintf("[%06lx] %s,%d: LI not on same ctrl %08lx",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b_id));
PUT_WORD(p_result, _WRONG_IDENTIFIER);
return (NULL);
}
if (!(get_b1_facilities(plci_b, add_b1_facilities(plci_b, plci_b->B1_resource,
(word)(plci_b->B1_facilities | B1_FACILITY_MIXER))) & B1_FACILITY_MIXER))
{
dbug(1, dprintf("[%06lx] %s,%d: Interconnect peer cannot mix %d",
UnMapId(Id), (char *)(FILE_), __LINE__, plci_b->B1_resource));
PUT_WORD(p_result, _WRONG_STATE);
return (NULL);
}
return (plci_b);
}
static byte mixer_request(dword Id, word Number, DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info;
word i;
dword d, li_flags, plci_b_id;
PLCI *plci_b;
API_PARSE li_parms[3];
API_PARSE li_req_parms[3];
API_PARSE li_participant_struct[2];
API_PARSE li_participant_parms[3];
word participant_parms_pos;
byte result_buffer[32];
byte *result;
word result_pos;
word plci_b_write_pos;
dbug(1, dprintf("[%06lx] %s,%d: mixer_request",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = GOOD;
result = result_buffer;
result_buffer[0] = 0;
if (!(a->profile.Global_Options & GL_LINE_INTERCONNECT_SUPPORTED))
{
dbug(1, dprintf("[%06lx] %s,%d: Facility not supported",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
}
else if (api_parse(&msg[1].info[1], msg[1].length, "ws", li_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
}
else
{
result_buffer[0] = 3;
PUT_WORD(&result_buffer[1], GET_WORD(li_parms[0].info));
result_buffer[3] = 0;
switch (GET_WORD(li_parms[0].info))
{
case LI_GET_SUPPORTED_SERVICES:
if (appl->appl_flags & APPL_FLAG_OLD_LI_SPEC)
{
result_buffer[0] = 17;
result_buffer[3] = 14;
PUT_WORD(&result_buffer[4], GOOD);
d = 0;
if (a->manufacturer_features & MANUFACTURER_FEATURE_MIXER_CH_CH)
d |= LI_CONFERENCING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_MIXER_CH_PC)
d |= LI_MONITORING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_MIXER_PC_CH)
d |= LI_ANNOUNCEMENTS_SUPPORTED | LI_MIXING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
d |= LI_CROSS_CONTROLLER_SUPPORTED;
PUT_DWORD(&result_buffer[6], d);
if (a->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
{
d = 0;
for (i = 0; i < li_total_channels; i++)
{
if ((li_config_table[i].adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
&& (li_config_table[i].adapter->li_pri
|| (i < li_config_table[i].adapter->li_base + MIXER_BCHANNELS_BRI)))
{
d++;
}
}
}
else
{
d = a->li_pri ? a->li_channels : MIXER_BCHANNELS_BRI;
}
PUT_DWORD(&result_buffer[10], d / 2);
PUT_DWORD(&result_buffer[14], d);
}
else
{
result_buffer[0] = 25;
result_buffer[3] = 22;
PUT_WORD(&result_buffer[4], GOOD);
d = LI2_ASYMMETRIC_SUPPORTED | LI2_B_LOOPING_SUPPORTED | LI2_X_LOOPING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_MIXER_CH_PC)
d |= LI2_MONITORING_SUPPORTED | LI2_REMOTE_MONITORING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_MIXER_PC_CH)
d |= LI2_MIXING_SUPPORTED | LI2_REMOTE_MIXING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_MIXER_PC_PC)
d |= LI2_PC_LOOPING_SUPPORTED;
if (a->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
d |= LI2_CROSS_CONTROLLER_SUPPORTED;
PUT_DWORD(&result_buffer[6], d);
d = a->li_pri ? a->li_channels : MIXER_BCHANNELS_BRI;
PUT_DWORD(&result_buffer[10], d / 2);
PUT_DWORD(&result_buffer[14], d - 1);
if (a->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
{
d = 0;
for (i = 0; i < li_total_channels; i++)
{
if ((li_config_table[i].adapter->manufacturer_features & MANUFACTURER_FEATURE_XCONNECT)
&& (li_config_table[i].adapter->li_pri
|| (i < li_config_table[i].adapter->li_base + MIXER_BCHANNELS_BRI)))
{
d++;
}
}
}
PUT_DWORD(&result_buffer[18], d / 2);
PUT_DWORD(&result_buffer[22], d - 1);
}
break;
case LI_REQ_CONNECT:
if (li_parms[1].length == 8)
{
appl->appl_flags |= APPL_FLAG_OLD_LI_SPEC;
if (api_parse(&li_parms[1].info[1], li_parms[1].length, "dd", li_req_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
plci_b_id = GET_DWORD(li_req_parms[0].info) & 0xffff;
li_flags = GET_DWORD(li_req_parms[1].info);
Info = li_check_main_plci(Id, plci);
result_buffer[0] = 9;
result_buffer[3] = 6;
PUT_DWORD(&result_buffer[4], plci_b_id);
PUT_WORD(&result_buffer[8], GOOD);
if (Info != GOOD)
break;
result = plci->saved_msg.info;
for (i = 0; i <= result_buffer[0]; i++)
result[i] = result_buffer[i];
plci_b_write_pos = plci->li_plci_b_write_pos;
plci_b = li_check_plci_b(Id, plci, plci_b_id, plci_b_write_pos, &result[8]);
if (plci_b == NULL)
break;
li_update_connect(Id, a, plci, plci_b_id, true, li_flags);
plci->li_plci_b_queue[plci_b_write_pos] = plci_b_id | LI_PLCI_B_LAST_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
plci->li_plci_b_write_pos = plci_b_write_pos;
}
else
{
appl->appl_flags &= ~APPL_FLAG_OLD_LI_SPEC;
if (api_parse(&li_parms[1].info[1], li_parms[1].length, "ds", li_req_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
li_flags = GET_DWORD(li_req_parms[0].info) & ~(LI2_FLAG_INTERCONNECT_A_B | LI2_FLAG_INTERCONNECT_B_A);
Info = li_check_main_plci(Id, plci);
result_buffer[0] = 7;
result_buffer[3] = 4;
PUT_WORD(&result_buffer[4], Info);
result_buffer[6] = 0;
if (Info != GOOD)
break;
result = plci->saved_msg.info;
for (i = 0; i <= result_buffer[0]; i++)
result[i] = result_buffer[i];
plci_b_write_pos = plci->li_plci_b_write_pos;
participant_parms_pos = 0;
result_pos = 7;
li2_update_connect(Id, a, plci, UnMapId(Id), true, li_flags);
while (participant_parms_pos < li_req_parms[1].length)
{
result[result_pos] = 6;
result_pos += 7;
PUT_DWORD(&result[result_pos - 6], 0);
PUT_WORD(&result[result_pos - 2], GOOD);
if (api_parse(&li_req_parms[1].info[1 + participant_parms_pos],
(word)(li_parms[1].length - participant_parms_pos), "s", li_participant_struct))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(&result[result_pos - 2], _WRONG_MESSAGE_FORMAT);
break;
}
if (api_parse(&li_participant_struct[0].info[1],
li_participant_struct[0].length, "dd", li_participant_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(&result[result_pos - 2], _WRONG_MESSAGE_FORMAT);
break;
}
plci_b_id = GET_DWORD(li_participant_parms[0].info) & 0xffff;
li_flags = GET_DWORD(li_participant_parms[1].info);
PUT_DWORD(&result[result_pos - 6], plci_b_id);
if (sizeof(result) - result_pos < 7)
{
dbug(1, dprintf("[%06lx] %s,%d: LI result overrun",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(&result[result_pos - 2], _WRONG_STATE);
break;
}
plci_b = li2_check_plci_b(Id, plci, plci_b_id, plci_b_write_pos, &result[result_pos - 2]);
if (plci_b != NULL)
{
li2_update_connect(Id, a, plci, plci_b_id, true, li_flags);
plci->li_plci_b_queue[plci_b_write_pos] = plci_b_id |
((li_flags & (LI2_FLAG_INTERCONNECT_A_B | LI2_FLAG_INTERCONNECT_B_A |
LI2_FLAG_PCCONNECT_A_B | LI2_FLAG_PCCONNECT_B_A)) ? 0 : LI_PLCI_B_DISC_FLAG);
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
}
participant_parms_pos = (word)((&li_participant_struct[0].info[1 + li_participant_struct[0].length]) -
(&li_req_parms[1].info[1]));
}
result[0] = (byte)(result_pos - 1);
result[3] = (byte)(result_pos - 4);
result[6] = (byte)(result_pos - 7);
i = (plci_b_write_pos == 0) ? LI_PLCI_B_QUEUE_ENTRIES - 1 : plci_b_write_pos - 1;
if ((plci_b_write_pos == plci->li_plci_b_read_pos)
|| (plci->li_plci_b_queue[i] & LI_PLCI_B_LAST_FLAG))
{
plci->li_plci_b_queue[plci_b_write_pos] = LI_PLCI_B_SKIP_FLAG | LI_PLCI_B_LAST_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
}
else
plci->li_plci_b_queue[i] |= LI_PLCI_B_LAST_FLAG;
plci->li_plci_b_write_pos = plci_b_write_pos;
}
mixer_calculate_coefs(a);
plci->li_channel_bits = li_config_table[a->li_base + (plci->li_bchannel_id - 1)].channel;
mixer_notify_update(plci, true);
sendf(appl, _FACILITY_R | CONFIRM, Id & 0xffffL, Number,
"wwS", Info, SELECTOR_LINE_INTERCONNECT, result);
plci->command = 0;
plci->li_cmd = GET_WORD(li_parms[0].info);
start_internal_command(Id, plci, mixer_command);
return (false);
case LI_REQ_DISCONNECT:
if (li_parms[1].length == 4)
{
appl->appl_flags |= APPL_FLAG_OLD_LI_SPEC;
if (api_parse(&li_parms[1].info[1], li_parms[1].length, "d", li_req_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
plci_b_id = GET_DWORD(li_req_parms[0].info) & 0xffff;
Info = li_check_main_plci(Id, plci);
result_buffer[0] = 9;
result_buffer[3] = 6;
PUT_DWORD(&result_buffer[4], GET_DWORD(li_req_parms[0].info));
PUT_WORD(&result_buffer[8], GOOD);
if (Info != GOOD)
break;
result = plci->saved_msg.info;
for (i = 0; i <= result_buffer[0]; i++)
result[i] = result_buffer[i];
plci_b_write_pos = plci->li_plci_b_write_pos;
plci_b = li_check_plci_b(Id, plci, plci_b_id, plci_b_write_pos, &result[8]);
if (plci_b == NULL)
break;
li_update_connect(Id, a, plci, plci_b_id, false, 0);
plci->li_plci_b_queue[plci_b_write_pos] = plci_b_id | LI_PLCI_B_DISC_FLAG | LI_PLCI_B_LAST_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
plci->li_plci_b_write_pos = plci_b_write_pos;
}
else
{
appl->appl_flags &= ~APPL_FLAG_OLD_LI_SPEC;
if (api_parse(&li_parms[1].info[1], li_parms[1].length, "s", li_req_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
break;
}
Info = li_check_main_plci(Id, plci);
result_buffer[0] = 7;
result_buffer[3] = 4;
PUT_WORD(&result_buffer[4], Info);
result_buffer[6] = 0;
if (Info != GOOD)
break;
result = plci->saved_msg.info;
for (i = 0; i <= result_buffer[0]; i++)
result[i] = result_buffer[i];
plci_b_write_pos = plci->li_plci_b_write_pos;
participant_parms_pos = 0;
result_pos = 7;
while (participant_parms_pos < li_req_parms[0].length)
{
result[result_pos] = 6;
result_pos += 7;
PUT_DWORD(&result[result_pos - 6], 0);
PUT_WORD(&result[result_pos - 2], GOOD);
if (api_parse(&li_req_parms[0].info[1 + participant_parms_pos],
(word)(li_parms[1].length - participant_parms_pos), "s", li_participant_struct))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(&result[result_pos - 2], _WRONG_MESSAGE_FORMAT);
break;
}
if (api_parse(&li_participant_struct[0].info[1],
li_participant_struct[0].length, "d", li_participant_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(&result[result_pos - 2], _WRONG_MESSAGE_FORMAT);
break;
}
plci_b_id = GET_DWORD(li_participant_parms[0].info) & 0xffff;
PUT_DWORD(&result[result_pos - 6], plci_b_id);
if (sizeof(result) - result_pos < 7)
{
dbug(1, dprintf("[%06lx] %s,%d: LI result overrun",
UnMapId(Id), (char *)(FILE_), __LINE__));
PUT_WORD(&result[result_pos - 2], _WRONG_STATE);
break;
}
plci_b = li2_check_plci_b(Id, plci, plci_b_id, plci_b_write_pos, &result[result_pos - 2]);
if (plci_b != NULL)
{
li2_update_connect(Id, a, plci, plci_b_id, false, 0);
plci->li_plci_b_queue[plci_b_write_pos] = plci_b_id | LI_PLCI_B_DISC_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
}
participant_parms_pos = (word)((&li_participant_struct[0].info[1 + li_participant_struct[0].length]) -
(&li_req_parms[0].info[1]));
}
result[0] = (byte)(result_pos - 1);
result[3] = (byte)(result_pos - 4);
result[6] = (byte)(result_pos - 7);
i = (plci_b_write_pos == 0) ? LI_PLCI_B_QUEUE_ENTRIES - 1 : plci_b_write_pos - 1;
if ((plci_b_write_pos == plci->li_plci_b_read_pos)
|| (plci->li_plci_b_queue[i] & LI_PLCI_B_LAST_FLAG))
{
plci->li_plci_b_queue[plci_b_write_pos] = LI_PLCI_B_SKIP_FLAG | LI_PLCI_B_LAST_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
}
else
plci->li_plci_b_queue[i] |= LI_PLCI_B_LAST_FLAG;
plci->li_plci_b_write_pos = plci_b_write_pos;
}
mixer_calculate_coefs(a);
plci->li_channel_bits = li_config_table[a->li_base + (plci->li_bchannel_id - 1)].channel;
mixer_notify_update(plci, true);
sendf(appl, _FACILITY_R | CONFIRM, Id & 0xffffL, Number,
"wwS", Info, SELECTOR_LINE_INTERCONNECT, result);
plci->command = 0;
plci->li_cmd = GET_WORD(li_parms[0].info);
start_internal_command(Id, plci, mixer_command);
return (false);
case LI_REQ_SILENT_UPDATE:
if (!plci || !plci->State
|| !plci->NL.Id || plci->nl_remove_id
|| (plci->li_bchannel_id == 0)
|| (li_config_table[plci->adapter->li_base + (plci->li_bchannel_id - 1)].plci != plci))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong state",
UnMapId(Id), (char *)(FILE_), __LINE__));
return (false);
}
plci_b_write_pos = plci->li_plci_b_write_pos;
if (((plci->li_plci_b_read_pos > plci_b_write_pos) ? plci->li_plci_b_read_pos :
LI_PLCI_B_QUEUE_ENTRIES + plci->li_plci_b_read_pos) - plci_b_write_pos - 1 < 2)
{
dbug(1, dprintf("[%06lx] %s,%d: LI request overrun",
UnMapId(Id), (char *)(FILE_), __LINE__));
return (false);
}
i = (plci_b_write_pos == 0) ? LI_PLCI_B_QUEUE_ENTRIES - 1 : plci_b_write_pos - 1;
if ((plci_b_write_pos == plci->li_plci_b_read_pos)
|| (plci->li_plci_b_queue[i] & LI_PLCI_B_LAST_FLAG))
{
plci->li_plci_b_queue[plci_b_write_pos] = LI_PLCI_B_SKIP_FLAG | LI_PLCI_B_LAST_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
}
else
plci->li_plci_b_queue[i] |= LI_PLCI_B_LAST_FLAG;
plci->li_plci_b_write_pos = plci_b_write_pos;
plci->li_channel_bits = li_config_table[a->li_base + (plci->li_bchannel_id - 1)].channel;
plci->command = 0;
plci->li_cmd = GET_WORD(li_parms[0].info);
start_internal_command(Id, plci, mixer_command);
return (false);
default:
dbug(1, dprintf("[%06lx] %s,%d: LI unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, GET_WORD(li_parms[0].info)));
Info = _FACILITY_NOT_SUPPORTED;
}
}
sendf(appl, _FACILITY_R | CONFIRM, Id & 0xffffL, Number,
"wwS", Info, SELECTOR_LINE_INTERCONNECT, result);
return (false);
}
static void mixer_indication_coefs_set(dword Id, PLCI *plci)
{
dword d;
byte result[12];
dbug(1, dprintf("[%06lx] %s,%d: mixer_indication_coefs_set",
UnMapId(Id), (char *)(FILE_), __LINE__));
if (plci->li_plci_b_read_pos != plci->li_plci_b_req_pos)
{
do
{
d = plci->li_plci_b_queue[plci->li_plci_b_read_pos];
if (!(d & LI_PLCI_B_SKIP_FLAG))
{
if (plci->appl->appl_flags & APPL_FLAG_OLD_LI_SPEC)
{
if (d & LI_PLCI_B_DISC_FLAG)
{
result[0] = 5;
PUT_WORD(&result[1], LI_IND_DISCONNECT);
result[3] = 2;
PUT_WORD(&result[4], _LI_USER_INITIATED);
}
else
{
result[0] = 7;
PUT_WORD(&result[1], LI_IND_CONNECT_ACTIVE);
result[3] = 4;
PUT_DWORD(&result[4], d & ~LI_PLCI_B_FLAG_MASK);
}
}
else
{
if (d & LI_PLCI_B_DISC_FLAG)
{
result[0] = 9;
PUT_WORD(&result[1], LI_IND_DISCONNECT);
result[3] = 6;
PUT_DWORD(&result[4], d & ~LI_PLCI_B_FLAG_MASK);
PUT_WORD(&result[8], _LI_USER_INITIATED);
}
else
{
result[0] = 7;
PUT_WORD(&result[1], LI_IND_CONNECT_ACTIVE);
result[3] = 4;
PUT_DWORD(&result[4], d & ~LI_PLCI_B_FLAG_MASK);
}
}
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0,
"ws", SELECTOR_LINE_INTERCONNECT, result);
}
plci->li_plci_b_read_pos = (plci->li_plci_b_read_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ?
0 : plci->li_plci_b_read_pos + 1;
} while (!(d & LI_PLCI_B_LAST_FLAG) && (plci->li_plci_b_read_pos != plci->li_plci_b_req_pos));
}
}
static void mixer_indication_xconnect_from(dword Id, PLCI *plci, byte *msg, word length)
{
word i, j, ch;
struct xconnect_transfer_address_s s, *p;
DIVA_CAPI_ADAPTER *a;
dbug(1, dprintf("[%06lx] %s,%d: mixer_indication_xconnect_from %d",
UnMapId(Id), (char *)(FILE_), __LINE__, (int)length));
a = plci->adapter;
i = 1;
for (i = 1; i < length; i += 16)
{
s.card_address.low = msg[i] | (msg[i + 1] << 8) | (((dword)(msg[i + 2])) << 16) | (((dword)(msg[i + 3])) << 24);
s.card_address.high = msg[i + 4] | (msg[i + 5] << 8) | (((dword)(msg[i + 6])) << 16) | (((dword)(msg[i + 7])) << 24);
s.offset = msg[i + 8] | (msg[i + 9] << 8) | (((dword)(msg[i + 10])) << 16) | (((dword)(msg[i + 11])) << 24);
ch = msg[i + 12] | (msg[i + 13] << 8);
j = ch & XCONNECT_CHANNEL_NUMBER_MASK;
if (!a->li_pri && (plci->li_bchannel_id == 2))
j = 1 - j;
j += a->li_base;
if (ch & XCONNECT_CHANNEL_PORT_PC)
p = &(li_config_table[j].send_pc);
else
p = &(li_config_table[j].send_b);
p->card_address.low = s.card_address.low;
p->card_address.high = s.card_address.high;
p->offset = s.offset;
li_config_table[j].channel |= LI_CHANNEL_ADDRESSES_SET;
}
if (plci->internal_command_queue[0]
&& ((plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_2)
|| (plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_3)
|| (plci->adjust_b_state == ADJUST_B_RESTORE_MIXER_4)))
{
(*(plci->internal_command_queue[0]))(Id, plci, 0);
if (!plci->internal_command)
next_internal_command(Id, plci);
}
mixer_notify_update(plci, true);
}
static void mixer_indication_xconnect_to(dword Id, PLCI *plci, byte *msg, word length)
{
dbug(1, dprintf("[%06lx] %s,%d: mixer_indication_xconnect_to %d",
UnMapId(Id), (char *)(FILE_), __LINE__, (int) length));
}
static byte mixer_notify_source_removed(PLCI *plci, dword plci_b_id)
{
word plci_b_write_pos;
plci_b_write_pos = plci->li_plci_b_write_pos;
if (((plci->li_plci_b_read_pos > plci_b_write_pos) ? plci->li_plci_b_read_pos :
LI_PLCI_B_QUEUE_ENTRIES + plci->li_plci_b_read_pos) - plci_b_write_pos - 1 < 1)
{
dbug(1, dprintf("[%06lx] %s,%d: LI request overrun",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
return (false);
}
plci->li_plci_b_queue[plci_b_write_pos] = plci_b_id | LI_PLCI_B_DISC_FLAG;
plci_b_write_pos = (plci_b_write_pos == LI_PLCI_B_QUEUE_ENTRIES - 1) ? 0 : plci_b_write_pos + 1;
plci->li_plci_b_write_pos = plci_b_write_pos;
return (true);
}
static void mixer_remove(PLCI *plci)
{
DIVA_CAPI_ADAPTER *a;
PLCI *notify_plci;
dword plci_b_id;
word i, j;
dbug(1, dprintf("[%06lx] %s,%d: mixer_remove",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
a = plci->adapter;
plci_b_id = (plci->Id << 8) | UnMapController(plci->adapter->Id);
if (a->profile.Global_Options & GL_LINE_INTERCONNECT_SUPPORTED)
{
if ((plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
i = a->li_base + (plci->li_bchannel_id - 1);
if ((li_config_table[i].curchnl | li_config_table[i].channel) & LI_CHANNEL_INVOLVED)
{
for (j = 0; j < li_total_channels; j++)
{
if ((li_config_table[i].flag_table[j] & LI_FLAG_INTERCONNECT)
|| (li_config_table[j].flag_table[i] & LI_FLAG_INTERCONNECT))
{
notify_plci = li_config_table[j].plci;
if ((notify_plci != NULL)
&& (notify_plci != plci)
&& (notify_plci->appl != NULL)
&& !(notify_plci->appl->appl_flags & APPL_FLAG_OLD_LI_SPEC)
&& (notify_plci->State)
&& notify_plci->NL.Id && !notify_plci->nl_remove_id)
{
mixer_notify_source_removed(notify_plci, plci_b_id);
}
}
}
mixer_clear_config(plci);
mixer_calculate_coefs(a);
mixer_notify_update(plci, true);
}
li_config_table[i].plci = NULL;
plci->li_bchannel_id = 0;
}
}
}
/*------------------------------------------------------------------*/
/* Echo canceller facilities */
/*------------------------------------------------------------------*/
static void ec_write_parameters(PLCI *plci)
{
word w;
byte parameter_buffer[6];
dbug(1, dprintf("[%06lx] %s,%d: ec_write_parameters",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
parameter_buffer[0] = 5;
parameter_buffer[1] = DSP_CTRL_SET_LEC_PARAMETERS;
PUT_WORD(¶meter_buffer[2], plci->ec_idi_options);
plci->ec_idi_options &= ~LEC_RESET_COEFFICIENTS;
w = (plci->ec_tail_length == 0) ? 128 : plci->ec_tail_length;
PUT_WORD(¶meter_buffer[4], w);
add_p(plci, FTY, parameter_buffer);
sig_req(plci, TEL_CTRL, 0);
send_req(plci);
}
static void ec_clear_config(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: ec_clear_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->ec_idi_options = LEC_ENABLE_ECHO_CANCELLER |
LEC_MANUAL_DISABLE | LEC_ENABLE_NONLINEAR_PROCESSING;
plci->ec_tail_length = 0;
}
static void ec_prepare_switch(dword Id, PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: ec_prepare_switch",
UnMapId(Id), (char *)(FILE_), __LINE__));
}
static word ec_save_config(dword Id, PLCI *plci, byte Rc)
{
dbug(1, dprintf("[%06lx] %s,%d: ec_save_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
return (GOOD);
}
static word ec_restore_config(dword Id, PLCI *plci, byte Rc)
{
word Info;
dbug(1, dprintf("[%06lx] %s,%d: ec_restore_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
Info = GOOD;
if (plci->B1_facilities & B1_FACILITY_EC)
{
switch (plci->adjust_b_state)
{
case ADJUST_B_RESTORE_EC_1:
plci->internal_command = plci->adjust_b_command;
if (plci->sig_req)
{
plci->adjust_b_state = ADJUST_B_RESTORE_EC_1;
break;
}
ec_write_parameters(plci);
plci->adjust_b_state = ADJUST_B_RESTORE_EC_2;
break;
case ADJUST_B_RESTORE_EC_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Restore EC failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
break;
}
}
return (Info);
}
static void ec_command(dword Id, PLCI *plci, byte Rc)
{
word internal_command, Info;
byte result[8];
dbug(1, dprintf("[%06lx] %s,%d: ec_command %02x %04x %04x %04x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command,
plci->ec_cmd, plci->ec_idi_options, plci->ec_tail_length));
Info = GOOD;
if (plci->appl->appl_flags & APPL_FLAG_PRIV_EC_SPEC)
{
result[0] = 2;
PUT_WORD(&result[1], EC_SUCCESS);
}
else
{
result[0] = 5;
PUT_WORD(&result[1], plci->ec_cmd);
result[3] = 2;
PUT_WORD(&result[4], GOOD);
}
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (plci->ec_cmd)
{
case EC_ENABLE_OPERATION:
case EC_FREEZE_COEFFICIENTS:
case EC_RESUME_COEFFICIENT_UPDATE:
case EC_RESET_COEFFICIENTS:
switch (internal_command)
{
default:
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities |
B1_FACILITY_EC), EC_COMMAND_1);
case EC_COMMAND_1:
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Load EC failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (plci->internal_command)
return;
case EC_COMMAND_2:
if (plci->sig_req)
{
plci->internal_command = EC_COMMAND_2;
return;
}
plci->internal_command = EC_COMMAND_3;
ec_write_parameters(plci);
return;
case EC_COMMAND_3:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Enable EC failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
break;
}
break;
case EC_DISABLE_OPERATION:
switch (internal_command)
{
default:
case EC_COMMAND_1:
if (plci->B1_facilities & B1_FACILITY_EC)
{
if (plci->sig_req)
{
plci->internal_command = EC_COMMAND_1;
return;
}
plci->internal_command = EC_COMMAND_2;
ec_write_parameters(plci);
return;
}
Rc = OK;
case EC_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Disable EC failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
adjust_b1_resource(Id, plci, NULL, (word)(plci->B1_facilities &
~B1_FACILITY_EC), EC_COMMAND_3);
case EC_COMMAND_3:
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Unload EC failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
break;
}
if (plci->internal_command)
return;
break;
}
break;
}
sendf(plci->appl, _FACILITY_R | CONFIRM, Id & 0xffffL, plci->number,
"wws", Info, (plci->appl->appl_flags & APPL_FLAG_PRIV_EC_SPEC) ?
PRIV_SELECTOR_ECHO_CANCELLER : SELECTOR_ECHO_CANCELLER, result);
}
static byte ec_request(dword Id, word Number, DIVA_CAPI_ADAPTER *a, PLCI *plci, APPL *appl, API_PARSE *msg)
{
word Info;
word opt;
API_PARSE ec_parms[3];
byte result[16];
dbug(1, dprintf("[%06lx] %s,%d: ec_request",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = GOOD;
result[0] = 0;
if (!(a->man_profile.private_options & (1L << PRIVATE_ECHO_CANCELLER)))
{
dbug(1, dprintf("[%06lx] %s,%d: Facility not supported",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _FACILITY_NOT_SUPPORTED;
}
else
{
if (appl->appl_flags & APPL_FLAG_PRIV_EC_SPEC)
{
if (api_parse(&msg[1].info[1], msg[1].length, "w", ec_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
}
else
{
if (plci == NULL)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong PLCI",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_IDENTIFIER;
}
else if (!plci->State || !plci->NL.Id || plci->nl_remove_id)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong state",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_STATE;
}
else
{
plci->command = 0;
plci->ec_cmd = GET_WORD(ec_parms[0].info);
plci->ec_idi_options &= ~(LEC_MANUAL_DISABLE | LEC_RESET_COEFFICIENTS);
result[0] = 2;
PUT_WORD(&result[1], EC_SUCCESS);
if (msg[1].length >= 4)
{
opt = GET_WORD(&ec_parms[0].info[2]);
plci->ec_idi_options &= ~(LEC_ENABLE_NONLINEAR_PROCESSING |
LEC_ENABLE_2100HZ_DETECTOR | LEC_REQUIRE_2100HZ_REVERSALS);
if (!(opt & EC_DISABLE_NON_LINEAR_PROCESSING))
plci->ec_idi_options |= LEC_ENABLE_NONLINEAR_PROCESSING;
if (opt & EC_DETECT_DISABLE_TONE)
plci->ec_idi_options |= LEC_ENABLE_2100HZ_DETECTOR;
if (!(opt & EC_DO_NOT_REQUIRE_REVERSALS))
plci->ec_idi_options |= LEC_REQUIRE_2100HZ_REVERSALS;
if (msg[1].length >= 6)
{
plci->ec_tail_length = GET_WORD(&ec_parms[0].info[4]);
}
}
switch (plci->ec_cmd)
{
case EC_ENABLE_OPERATION:
plci->ec_idi_options &= ~LEC_FREEZE_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
case EC_DISABLE_OPERATION:
plci->ec_idi_options = LEC_ENABLE_ECHO_CANCELLER |
LEC_MANUAL_DISABLE | LEC_ENABLE_NONLINEAR_PROCESSING |
LEC_RESET_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
case EC_FREEZE_COEFFICIENTS:
plci->ec_idi_options |= LEC_FREEZE_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
case EC_RESUME_COEFFICIENT_UPDATE:
plci->ec_idi_options &= ~LEC_FREEZE_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
case EC_RESET_COEFFICIENTS:
plci->ec_idi_options |= LEC_RESET_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
default:
dbug(1, dprintf("[%06lx] %s,%d: EC unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, plci->ec_cmd));
PUT_WORD(&result[1], EC_UNSUPPORTED_OPERATION);
}
}
}
}
else
{
if (api_parse(&msg[1].info[1], msg[1].length, "ws", ec_parms))
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong message format",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_MESSAGE_FORMAT;
}
else
{
if (GET_WORD(ec_parms[0].info) == EC_GET_SUPPORTED_SERVICES)
{
result[0] = 11;
PUT_WORD(&result[1], EC_GET_SUPPORTED_SERVICES);
result[3] = 8;
PUT_WORD(&result[4], GOOD);
PUT_WORD(&result[6], 0x0007);
PUT_WORD(&result[8], LEC_MAX_SUPPORTED_TAIL_LENGTH);
PUT_WORD(&result[10], 0);
}
else if (plci == NULL)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong PLCI",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_IDENTIFIER;
}
else if (!plci->State || !plci->NL.Id || plci->nl_remove_id)
{
dbug(1, dprintf("[%06lx] %s,%d: Wrong state",
UnMapId(Id), (char *)(FILE_), __LINE__));
Info = _WRONG_STATE;
}
else
{
plci->command = 0;
plci->ec_cmd = GET_WORD(ec_parms[0].info);
plci->ec_idi_options &= ~(LEC_MANUAL_DISABLE | LEC_RESET_COEFFICIENTS);
result[0] = 5;
PUT_WORD(&result[1], plci->ec_cmd);
result[3] = 2;
PUT_WORD(&result[4], GOOD);
plci->ec_idi_options &= ~(LEC_ENABLE_NONLINEAR_PROCESSING |
LEC_ENABLE_2100HZ_DETECTOR | LEC_REQUIRE_2100HZ_REVERSALS);
plci->ec_tail_length = 0;
if (ec_parms[1].length >= 2)
{
opt = GET_WORD(&ec_parms[1].info[1]);
if (opt & EC_ENABLE_NON_LINEAR_PROCESSING)
plci->ec_idi_options |= LEC_ENABLE_NONLINEAR_PROCESSING;
if (opt & EC_DETECT_DISABLE_TONE)
plci->ec_idi_options |= LEC_ENABLE_2100HZ_DETECTOR;
if (!(opt & EC_DO_NOT_REQUIRE_REVERSALS))
plci->ec_idi_options |= LEC_REQUIRE_2100HZ_REVERSALS;
if (ec_parms[1].length >= 4)
{
plci->ec_tail_length = GET_WORD(&ec_parms[1].info[3]);
}
}
switch (plci->ec_cmd)
{
case EC_ENABLE_OPERATION:
plci->ec_idi_options &= ~LEC_FREEZE_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
case EC_DISABLE_OPERATION:
plci->ec_idi_options = LEC_ENABLE_ECHO_CANCELLER |
LEC_MANUAL_DISABLE | LEC_ENABLE_NONLINEAR_PROCESSING |
LEC_RESET_COEFFICIENTS;
start_internal_command(Id, plci, ec_command);
return (false);
default:
dbug(1, dprintf("[%06lx] %s,%d: EC unknown request %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, plci->ec_cmd));
PUT_WORD(&result[4], _FACILITY_SPECIFIC_FUNCTION_NOT_SUPP);
}
}
}
}
}
sendf(appl, _FACILITY_R | CONFIRM, Id & 0xffffL, Number,
"wws", Info, (appl->appl_flags & APPL_FLAG_PRIV_EC_SPEC) ?
PRIV_SELECTOR_ECHO_CANCELLER : SELECTOR_ECHO_CANCELLER, result);
return (false);
}
static void ec_indication(dword Id, PLCI *plci, byte *msg, word length)
{
byte result[8];
dbug(1, dprintf("[%06lx] %s,%d: ec_indication",
UnMapId(Id), (char *)(FILE_), __LINE__));
if (!(plci->ec_idi_options & LEC_MANUAL_DISABLE))
{
if (plci->appl->appl_flags & APPL_FLAG_PRIV_EC_SPEC)
{
result[0] = 2;
PUT_WORD(&result[1], 0);
switch (msg[1])
{
case LEC_DISABLE_TYPE_CONTIGNUOUS_2100HZ:
PUT_WORD(&result[1], EC_BYPASS_DUE_TO_CONTINUOUS_2100HZ);
break;
case LEC_DISABLE_TYPE_REVERSED_2100HZ:
PUT_WORD(&result[1], EC_BYPASS_DUE_TO_REVERSED_2100HZ);
break;
case LEC_DISABLE_RELEASED:
PUT_WORD(&result[1], EC_BYPASS_RELEASED);
break;
}
}
else
{
result[0] = 5;
PUT_WORD(&result[1], EC_BYPASS_INDICATION);
result[3] = 2;
PUT_WORD(&result[4], 0);
switch (msg[1])
{
case LEC_DISABLE_TYPE_CONTIGNUOUS_2100HZ:
PUT_WORD(&result[4], EC_BYPASS_DUE_TO_CONTINUOUS_2100HZ);
break;
case LEC_DISABLE_TYPE_REVERSED_2100HZ:
PUT_WORD(&result[4], EC_BYPASS_DUE_TO_REVERSED_2100HZ);
break;
case LEC_DISABLE_RELEASED:
PUT_WORD(&result[4], EC_BYPASS_RELEASED);
break;
}
}
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0, "ws", (plci->appl->appl_flags & APPL_FLAG_PRIV_EC_SPEC) ?
PRIV_SELECTOR_ECHO_CANCELLER : SELECTOR_ECHO_CANCELLER, result);
}
}
/*------------------------------------------------------------------*/
/* Advanced voice */
/*------------------------------------------------------------------*/
static void adv_voice_write_coefs(PLCI *plci, word write_command)
{
DIVA_CAPI_ADAPTER *a;
word i;
byte *p;
word w, n, j, k;
byte ch_map[MIXER_CHANNELS_BRI];
byte coef_buffer[ADV_VOICE_COEF_BUFFER_SIZE + 2];
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_write_coefs %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, write_command));
a = plci->adapter;
p = coef_buffer + 1;
*(p++) = DSP_CTRL_OLD_SET_MIXER_COEFFICIENTS;
i = 0;
while (i + sizeof(word) <= a->adv_voice_coef_length)
{
PUT_WORD(p, GET_WORD(a->adv_voice_coef_buffer + i));
p += 2;
i += 2;
}
while (i < ADV_VOICE_OLD_COEF_COUNT * sizeof(word))
{
PUT_WORD(p, 0x8000);
p += 2;
i += 2;
}
if (!a->li_pri && (plci->li_bchannel_id == 0))
{
if ((li_config_table[a->li_base].plci == NULL) && (li_config_table[a->li_base + 1].plci != NULL))
{
plci->li_bchannel_id = 1;
li_config_table[a->li_base].plci = plci;
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_set_bchannel_id %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, plci->li_bchannel_id));
}
else if ((li_config_table[a->li_base].plci != NULL) && (li_config_table[a->li_base + 1].plci == NULL))
{
plci->li_bchannel_id = 2;
li_config_table[a->li_base + 1].plci = plci;
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_set_bchannel_id %d",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, plci->li_bchannel_id));
}
}
if (!a->li_pri && (plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
i = a->li_base + (plci->li_bchannel_id - 1);
switch (write_command)
{
case ADV_VOICE_WRITE_ACTIVATION:
j = a->li_base + MIXER_IC_CHANNEL_BASE + (plci->li_bchannel_id - 1);
k = a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id);
if (!(plci->B1_facilities & B1_FACILITY_MIXER))
{
li_config_table[j].flag_table[i] |= LI_FLAG_CONFERENCE | LI_FLAG_MIX;
li_config_table[i].flag_table[j] |= LI_FLAG_CONFERENCE | LI_FLAG_MONITOR;
}
if (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC)
{
li_config_table[k].flag_table[i] |= LI_FLAG_CONFERENCE | LI_FLAG_MIX;
li_config_table[i].flag_table[k] |= LI_FLAG_CONFERENCE | LI_FLAG_MONITOR;
li_config_table[k].flag_table[j] |= LI_FLAG_CONFERENCE;
li_config_table[j].flag_table[k] |= LI_FLAG_CONFERENCE;
}
mixer_calculate_coefs(a);
li_config_table[i].curchnl = li_config_table[i].channel;
li_config_table[j].curchnl = li_config_table[j].channel;
if (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC)
li_config_table[k].curchnl = li_config_table[k].channel;
break;
case ADV_VOICE_WRITE_DEACTIVATION:
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].flag_table[j] = 0;
li_config_table[j].flag_table[i] = 0;
}
k = a->li_base + MIXER_IC_CHANNEL_BASE + (plci->li_bchannel_id - 1);
for (j = 0; j < li_total_channels; j++)
{
li_config_table[k].flag_table[j] = 0;
li_config_table[j].flag_table[k] = 0;
}
if (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC)
{
k = a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id);
for (j = 0; j < li_total_channels; j++)
{
li_config_table[k].flag_table[j] = 0;
li_config_table[j].flag_table[k] = 0;
}
}
mixer_calculate_coefs(a);
break;
}
if (plci->B1_facilities & B1_FACILITY_MIXER)
{
w = 0;
if (ADV_VOICE_NEW_COEF_BASE + sizeof(word) <= a->adv_voice_coef_length)
w = GET_WORD(a->adv_voice_coef_buffer + ADV_VOICE_NEW_COEF_BASE);
if (li_config_table[i].channel & LI_CHANNEL_TX_DATA)
w |= MIXER_FEATURE_ENABLE_TX_DATA;
if (li_config_table[i].channel & LI_CHANNEL_RX_DATA)
w |= MIXER_FEATURE_ENABLE_RX_DATA;
*(p++) = (byte) w;
*(p++) = (byte)(w >> 8);
for (j = 0; j < sizeof(ch_map); j += 2)
{
ch_map[j] = (byte)(j + (plci->li_bchannel_id - 1));
ch_map[j + 1] = (byte)(j + (2 - plci->li_bchannel_id));
}
for (n = 0; n < ARRAY_SIZE(mixer_write_prog_bri); n++)
{
i = a->li_base + ch_map[mixer_write_prog_bri[n].to_ch];
j = a->li_base + ch_map[mixer_write_prog_bri[n].from_ch];
if (li_config_table[i].channel & li_config_table[j].channel & LI_CHANNEL_INVOLVED)
{
*(p++) = ((li_config_table[i].coef_table[j] & mixer_write_prog_bri[n].mask) ? 0x80 : 0x01);
w = ((li_config_table[i].coef_table[j] & 0xf) ^ (li_config_table[i].coef_table[j] >> 4));
li_config_table[i].coef_table[j] ^= (w & mixer_write_prog_bri[n].mask) << 4;
}
else
{
*(p++) = (ADV_VOICE_NEW_COEF_BASE + sizeof(word) + n < a->adv_voice_coef_length) ?
a->adv_voice_coef_buffer[ADV_VOICE_NEW_COEF_BASE + sizeof(word) + n] : 0x00;
}
}
}
else
{
for (i = ADV_VOICE_NEW_COEF_BASE; i < a->adv_voice_coef_length; i++)
*(p++) = a->adv_voice_coef_buffer[i];
}
}
else
{
for (i = ADV_VOICE_NEW_COEF_BASE; i < a->adv_voice_coef_length; i++)
*(p++) = a->adv_voice_coef_buffer[i];
}
coef_buffer[0] = (p - coef_buffer) - 1;
add_p(plci, FTY, coef_buffer);
sig_req(plci, TEL_CTRL, 0);
send_req(plci);
}
static void adv_voice_clear_config(PLCI *plci)
{
DIVA_CAPI_ADAPTER *a;
word i, j;
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_clear_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
a = plci->adapter;
if ((plci->tel == ADV_VOICE) && (plci == a->AdvSignalPLCI))
{
a->adv_voice_coef_length = 0;
if (!a->li_pri && (plci->li_bchannel_id != 0)
&& (li_config_table[a->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
i = a->li_base + (plci->li_bchannel_id - 1);
li_config_table[i].curchnl = 0;
li_config_table[i].channel = 0;
li_config_table[i].chflags = 0;
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].flag_table[j] = 0;
li_config_table[j].flag_table[i] = 0;
li_config_table[i].coef_table[j] = 0;
li_config_table[j].coef_table[i] = 0;
}
li_config_table[i].coef_table[i] |= LI_COEF_CH_PC_SET | LI_COEF_PC_CH_SET;
i = a->li_base + MIXER_IC_CHANNEL_BASE + (plci->li_bchannel_id - 1);
li_config_table[i].curchnl = 0;
li_config_table[i].channel = 0;
li_config_table[i].chflags = 0;
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].flag_table[j] = 0;
li_config_table[j].flag_table[i] = 0;
li_config_table[i].coef_table[j] = 0;
li_config_table[j].coef_table[i] = 0;
}
if (a->manufacturer_features & MANUFACTURER_FEATURE_SLAVE_CODEC)
{
i = a->li_base + MIXER_IC_CHANNEL_BASE + (2 - plci->li_bchannel_id);
li_config_table[i].curchnl = 0;
li_config_table[i].channel = 0;
li_config_table[i].chflags = 0;
for (j = 0; j < li_total_channels; j++)
{
li_config_table[i].flag_table[j] = 0;
li_config_table[j].flag_table[i] = 0;
li_config_table[i].coef_table[j] = 0;
li_config_table[j].coef_table[i] = 0;
}
}
}
}
}
static void adv_voice_prepare_switch(dword Id, PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_prepare_switch",
UnMapId(Id), (char *)(FILE_), __LINE__));
}
static word adv_voice_save_config(dword Id, PLCI *plci, byte Rc)
{
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_save_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
return (GOOD);
}
static word adv_voice_restore_config(dword Id, PLCI *plci, byte Rc)
{
DIVA_CAPI_ADAPTER *a;
word Info;
dbug(1, dprintf("[%06lx] %s,%d: adv_voice_restore_config %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
Info = GOOD;
a = plci->adapter;
if ((plci->B1_facilities & B1_FACILITY_VOICE)
&& (plci->tel == ADV_VOICE) && (plci == a->AdvSignalPLCI))
{
switch (plci->adjust_b_state)
{
case ADJUST_B_RESTORE_VOICE_1:
plci->internal_command = plci->adjust_b_command;
if (plci->sig_req)
{
plci->adjust_b_state = ADJUST_B_RESTORE_VOICE_1;
break;
}
adv_voice_write_coefs(plci, ADV_VOICE_WRITE_UPDATE);
plci->adjust_b_state = ADJUST_B_RESTORE_VOICE_2;
break;
case ADJUST_B_RESTORE_VOICE_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Restore voice config failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
break;
}
}
return (Info);
}
/*------------------------------------------------------------------*/
/* B1 resource switching */
/*------------------------------------------------------------------*/
static byte b1_facilities_table[] =
{
0x00, /* 0 No bchannel resources */
0x00, /* 1 Codec (automatic law) */
0x00, /* 2 Codec (A-law) */
0x00, /* 3 Codec (y-law) */
0x00, /* 4 HDLC for X.21 */
0x00, /* 5 HDLC */
0x00, /* 6 External Device 0 */
0x00, /* 7 External Device 1 */
0x00, /* 8 HDLC 56k */
0x00, /* 9 Transparent */
0x00, /* 10 Loopback to network */
0x00, /* 11 Test pattern to net */
0x00, /* 12 Rate adaptation sync */
0x00, /* 13 Rate adaptation async */
0x00, /* 14 R-Interface */
0x00, /* 15 HDLC 128k leased line */
0x00, /* 16 FAX */
0x00, /* 17 Modem async */
0x00, /* 18 Modem sync HDLC */
0x00, /* 19 V.110 async HDLC */
0x12, /* 20 Adv voice (Trans,mixer) */
0x00, /* 21 Codec connected to IC */
0x0c, /* 22 Trans,DTMF */
0x1e, /* 23 Trans,DTMF+mixer */
0x1f, /* 24 Trans,DTMF+mixer+local */
0x13, /* 25 Trans,mixer+local */
0x12, /* 26 HDLC,mixer */
0x12, /* 27 HDLC 56k,mixer */
0x2c, /* 28 Trans,LEC+DTMF */
0x3e, /* 29 Trans,LEC+DTMF+mixer */
0x3f, /* 30 Trans,LEC+DTMF+mixer+local */
0x2c, /* 31 RTP,LEC+DTMF */
0x3e, /* 32 RTP,LEC+DTMF+mixer */
0x3f, /* 33 RTP,LEC+DTMF+mixer+local */
0x00, /* 34 Signaling task */
0x00, /* 35 PIAFS */
0x0c, /* 36 Trans,DTMF+TONE */
0x1e, /* 37 Trans,DTMF+TONE+mixer */
0x1f /* 38 Trans,DTMF+TONE+mixer+local*/
};
static word get_b1_facilities(PLCI *plci, byte b1_resource)
{
word b1_facilities;
b1_facilities = b1_facilities_table[b1_resource];
if ((b1_resource == 9) || (b1_resource == 20) || (b1_resource == 25))
{
if (!(((plci->requested_options_conn | plci->requested_options) & (1L << PRIVATE_DTMF_TONE))
|| (plci->appl && (plci->adapter->requested_options_table[plci->appl->Id - 1] & (1L << PRIVATE_DTMF_TONE)))))
{
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_SOFTDTMF_SEND)
b1_facilities |= B1_FACILITY_DTMFX;
if (plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_SOFTDTMF_RECEIVE)
b1_facilities |= B1_FACILITY_DTMFR;
}
}
if ((b1_resource == 17) || (b1_resource == 18))
{
if (plci->adapter->manufacturer_features & (MANUFACTURER_FEATURE_V18 | MANUFACTURER_FEATURE_VOWN))
b1_facilities |= B1_FACILITY_DTMFX | B1_FACILITY_DTMFR;
}
/*
dbug (1, dprintf("[%06lx] %s,%d: get_b1_facilities %d %04x",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char far *)(FILE_), __LINE__, b1_resource, b1_facilites));
*/
return (b1_facilities);
}
static byte add_b1_facilities(PLCI *plci, byte b1_resource, word b1_facilities)
{
byte b;
switch (b1_resource)
{
case 5:
case 26:
if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 26;
else
b = 5;
break;
case 8:
case 27:
if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 27;
else
b = 8;
break;
case 9:
case 20:
case 22:
case 23:
case 24:
case 25:
case 28:
case 29:
case 30:
case 36:
case 37:
case 38:
if (b1_facilities & B1_FACILITY_EC)
{
if (b1_facilities & B1_FACILITY_LOCAL)
b = 30;
else if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 29;
else
b = 28;
}
else if ((b1_facilities & (B1_FACILITY_DTMFX | B1_FACILITY_DTMFR | B1_FACILITY_MIXER))
&& (((plci->requested_options_conn | plci->requested_options) & (1L << PRIVATE_DTMF_TONE))
|| (plci->appl && (plci->adapter->requested_options_table[plci->appl->Id - 1] & (1L << PRIVATE_DTMF_TONE)))))
{
if (b1_facilities & B1_FACILITY_LOCAL)
b = 38;
else if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 37;
else
b = 36;
}
else if (((plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_HARDDTMF)
&& !(plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_SOFTDTMF_RECEIVE))
|| ((b1_facilities & B1_FACILITY_DTMFR)
&& ((b1_facilities & B1_FACILITY_MIXER)
|| !(plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_SOFTDTMF_RECEIVE)))
|| ((b1_facilities & B1_FACILITY_DTMFX)
&& ((b1_facilities & B1_FACILITY_MIXER)
|| !(plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_SOFTDTMF_SEND))))
{
if (b1_facilities & B1_FACILITY_LOCAL)
b = 24;
else if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 23;
else
b = 22;
}
else
{
if (b1_facilities & B1_FACILITY_LOCAL)
b = 25;
else if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 20;
else
b = 9;
}
break;
case 31:
case 32:
case 33:
if (b1_facilities & B1_FACILITY_LOCAL)
b = 33;
else if (b1_facilities & (B1_FACILITY_MIXER | B1_FACILITY_VOICE))
b = 32;
else
b = 31;
break;
default:
b = b1_resource;
}
dbug(1, dprintf("[%06lx] %s,%d: add_b1_facilities %d %04x %d %04x",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__,
b1_resource, b1_facilities, b, get_b1_facilities(plci, b)));
return (b);
}
static void adjust_b1_facilities(PLCI *plci, byte new_b1_resource, word new_b1_facilities)
{
word removed_facilities;
dbug(1, dprintf("[%06lx] %s,%d: adjust_b1_facilities %d %04x %04x",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__, new_b1_resource, new_b1_facilities,
new_b1_facilities & get_b1_facilities(plci, new_b1_resource)));
new_b1_facilities &= get_b1_facilities(plci, new_b1_resource);
removed_facilities = plci->B1_facilities & ~new_b1_facilities;
if (removed_facilities & B1_FACILITY_EC)
ec_clear_config(plci);
if (removed_facilities & B1_FACILITY_DTMFR)
{
dtmf_rec_clear_config(plci);
dtmf_parameter_clear_config(plci);
}
if (removed_facilities & B1_FACILITY_DTMFX)
dtmf_send_clear_config(plci);
if (removed_facilities & B1_FACILITY_MIXER)
mixer_clear_config(plci);
if (removed_facilities & B1_FACILITY_VOICE)
adv_voice_clear_config(plci);
plci->B1_facilities = new_b1_facilities;
}
static void adjust_b_clear(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: adjust_b_clear",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->adjust_b_restore = false;
}
static word adjust_b_process(dword Id, PLCI *plci, byte Rc)
{
word Info;
byte b1_resource;
NCCI *ncci_ptr;
API_PARSE bp[2];
dbug(1, dprintf("[%06lx] %s,%d: adjust_b_process %02x %d",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->adjust_b_state));
Info = GOOD;
switch (plci->adjust_b_state)
{
case ADJUST_B_START:
if ((plci->adjust_b_parms_msg == NULL)
&& (plci->adjust_b_mode & ADJUST_B_MODE_SWITCH_L1)
&& ((plci->adjust_b_mode & ~(ADJUST_B_MODE_SAVE | ADJUST_B_MODE_SWITCH_L1 |
ADJUST_B_MODE_NO_RESOURCE | ADJUST_B_MODE_RESTORE)) == 0))
{
b1_resource = (plci->adjust_b_mode == ADJUST_B_MODE_NO_RESOURCE) ?
0 : add_b1_facilities(plci, plci->B1_resource, plci->adjust_b_facilities);
if (b1_resource == plci->B1_resource)
{
adjust_b1_facilities(plci, b1_resource, plci->adjust_b_facilities);
break;
}
if (plci->adjust_b_facilities & ~get_b1_facilities(plci, b1_resource))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B nonsupported facilities %d %d %04x",
UnMapId(Id), (char *)(FILE_), __LINE__,
plci->B1_resource, b1_resource, plci->adjust_b_facilities));
Info = _WRONG_STATE;
break;
}
}
if (plci->adjust_b_mode & ADJUST_B_MODE_SAVE)
{
mixer_prepare_switch(Id, plci);
dtmf_prepare_switch(Id, plci);
dtmf_parameter_prepare_switch(Id, plci);
ec_prepare_switch(Id, plci);
adv_voice_prepare_switch(Id, plci);
}
plci->adjust_b_state = ADJUST_B_SAVE_MIXER_1;
Rc = OK;
case ADJUST_B_SAVE_MIXER_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_SAVE)
{
Info = mixer_save_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_SAVE_DTMF_1;
Rc = OK;
case ADJUST_B_SAVE_DTMF_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_SAVE)
{
Info = dtmf_save_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_REMOVE_L23_1;
case ADJUST_B_REMOVE_L23_1:
if ((plci->adjust_b_mode & ADJUST_B_MODE_REMOVE_L23)
&& plci->NL.Id && !plci->nl_remove_id)
{
plci->internal_command = plci->adjust_b_command;
if (plci->adjust_b_ncci != 0)
{
ncci_ptr = &(plci->adapter->ncci[plci->adjust_b_ncci]);
while (ncci_ptr->data_pending)
{
plci->data_sent_ptr = ncci_ptr->DBuffer[ncci_ptr->data_out].P;
data_rc(plci, plci->adapter->ncci_ch[plci->adjust_b_ncci]);
}
while (ncci_ptr->data_ack_pending)
data_ack(plci, plci->adapter->ncci_ch[plci->adjust_b_ncci]);
}
nl_req_ncci(plci, REMOVE,
(byte)((plci->adjust_b_mode & ADJUST_B_MODE_CONNECT) ? plci->adjust_b_ncci : 0));
send_req(plci);
plci->adjust_b_state = ADJUST_B_REMOVE_L23_2;
break;
}
plci->adjust_b_state = ADJUST_B_REMOVE_L23_2;
Rc = OK;
case ADJUST_B_REMOVE_L23_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B remove failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
if (plci->adjust_b_mode & ADJUST_B_MODE_REMOVE_L23)
{
if (plci_nl_busy(plci))
{
plci->internal_command = plci->adjust_b_command;
break;
}
}
plci->adjust_b_state = ADJUST_B_SAVE_EC_1;
Rc = OK;
case ADJUST_B_SAVE_EC_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_SAVE)
{
Info = ec_save_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_SAVE_DTMF_PARAMETER_1;
Rc = OK;
case ADJUST_B_SAVE_DTMF_PARAMETER_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_SAVE)
{
Info = dtmf_parameter_save_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_SAVE_VOICE_1;
Rc = OK;
case ADJUST_B_SAVE_VOICE_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_SAVE)
{
Info = adv_voice_save_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_SWITCH_L1_1;
case ADJUST_B_SWITCH_L1_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_SWITCH_L1)
{
if (plci->sig_req)
{
plci->internal_command = plci->adjust_b_command;
break;
}
if (plci->adjust_b_parms_msg != NULL)
api_load_msg(plci->adjust_b_parms_msg, bp);
else
api_load_msg(&plci->B_protocol, bp);
Info = add_b1(plci, bp,
(word)((plci->adjust_b_mode & ADJUST_B_MODE_NO_RESOURCE) ? 2 : 0),
plci->adjust_b_facilities);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B invalid L1 parameters %d %04x",
UnMapId(Id), (char *)(FILE_), __LINE__,
plci->B1_resource, plci->adjust_b_facilities));
break;
}
plci->internal_command = plci->adjust_b_command;
sig_req(plci, RESOURCES, 0);
send_req(plci);
plci->adjust_b_state = ADJUST_B_SWITCH_L1_2;
break;
}
plci->adjust_b_state = ADJUST_B_SWITCH_L1_2;
Rc = OK;
case ADJUST_B_SWITCH_L1_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B switch failed %02x %d %04x",
UnMapId(Id), (char *)(FILE_), __LINE__,
Rc, plci->B1_resource, plci->adjust_b_facilities));
Info = _WRONG_STATE;
break;
}
plci->adjust_b_state = ADJUST_B_RESTORE_VOICE_1;
Rc = OK;
case ADJUST_B_RESTORE_VOICE_1:
case ADJUST_B_RESTORE_VOICE_2:
if (plci->adjust_b_mode & ADJUST_B_MODE_RESTORE)
{
Info = adv_voice_restore_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_PARAMETER_1;
Rc = OK;
case ADJUST_B_RESTORE_DTMF_PARAMETER_1:
case ADJUST_B_RESTORE_DTMF_PARAMETER_2:
if (plci->adjust_b_mode & ADJUST_B_MODE_RESTORE)
{
Info = dtmf_parameter_restore_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_RESTORE_EC_1;
Rc = OK;
case ADJUST_B_RESTORE_EC_1:
case ADJUST_B_RESTORE_EC_2:
if (plci->adjust_b_mode & ADJUST_B_MODE_RESTORE)
{
Info = ec_restore_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_ASSIGN_L23_1;
case ADJUST_B_ASSIGN_L23_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_ASSIGN_L23)
{
if (plci_nl_busy(plci))
{
plci->internal_command = plci->adjust_b_command;
break;
}
if (plci->adjust_b_mode & ADJUST_B_MODE_CONNECT)
plci->call_dir |= CALL_DIR_FORCE_OUTG_NL;
if (plci->adjust_b_parms_msg != NULL)
api_load_msg(plci->adjust_b_parms_msg, bp);
else
api_load_msg(&plci->B_protocol, bp);
Info = add_b23(plci, bp);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B invalid L23 parameters %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Info));
break;
}
plci->internal_command = plci->adjust_b_command;
nl_req_ncci(plci, ASSIGN, 0);
send_req(plci);
plci->adjust_b_state = ADJUST_B_ASSIGN_L23_2;
break;
}
plci->adjust_b_state = ADJUST_B_ASSIGN_L23_2;
Rc = ASSIGN_OK;
case ADJUST_B_ASSIGN_L23_2:
if ((Rc != OK) && (Rc != OK_FC) && (Rc != ASSIGN_OK))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B assign failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
if (plci->adjust_b_mode & ADJUST_B_MODE_ASSIGN_L23)
{
if (Rc != ASSIGN_OK)
{
plci->internal_command = plci->adjust_b_command;
break;
}
}
if (plci->adjust_b_mode & ADJUST_B_MODE_USER_CONNECT)
{
plci->adjust_b_restore = true;
break;
}
plci->adjust_b_state = ADJUST_B_CONNECT_1;
case ADJUST_B_CONNECT_1:
if (plci->adjust_b_mode & ADJUST_B_MODE_CONNECT)
{
plci->internal_command = plci->adjust_b_command;
if (plci_nl_busy(plci))
break;
nl_req_ncci(plci, N_CONNECT, 0);
send_req(plci);
plci->adjust_b_state = ADJUST_B_CONNECT_2;
break;
}
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_1;
Rc = OK;
case ADJUST_B_CONNECT_2:
case ADJUST_B_CONNECT_3:
case ADJUST_B_CONNECT_4:
if ((Rc != OK) && (Rc != OK_FC) && (Rc != 0))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B connect failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
if (Rc == OK)
{
if (plci->adjust_b_mode & ADJUST_B_MODE_CONNECT)
{
get_ncci(plci, (byte)(Id >> 16), plci->adjust_b_ncci);
Id = (Id & 0xffff) | (((dword)(plci->adjust_b_ncci)) << 16);
}
if (plci->adjust_b_state == ADJUST_B_CONNECT_2)
plci->adjust_b_state = ADJUST_B_CONNECT_3;
else if (plci->adjust_b_state == ADJUST_B_CONNECT_4)
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_1;
}
else if (Rc == 0)
{
if (plci->adjust_b_state == ADJUST_B_CONNECT_2)
plci->adjust_b_state = ADJUST_B_CONNECT_4;
else if (plci->adjust_b_state == ADJUST_B_CONNECT_3)
plci->adjust_b_state = ADJUST_B_RESTORE_DTMF_1;
}
if (plci->adjust_b_state != ADJUST_B_RESTORE_DTMF_1)
{
plci->internal_command = plci->adjust_b_command;
break;
}
Rc = OK;
case ADJUST_B_RESTORE_DTMF_1:
case ADJUST_B_RESTORE_DTMF_2:
if (plci->adjust_b_mode & ADJUST_B_MODE_RESTORE)
{
Info = dtmf_restore_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_RESTORE_MIXER_1;
Rc = OK;
case ADJUST_B_RESTORE_MIXER_1:
case ADJUST_B_RESTORE_MIXER_2:
case ADJUST_B_RESTORE_MIXER_3:
case ADJUST_B_RESTORE_MIXER_4:
case ADJUST_B_RESTORE_MIXER_5:
case ADJUST_B_RESTORE_MIXER_6:
case ADJUST_B_RESTORE_MIXER_7:
if (plci->adjust_b_mode & ADJUST_B_MODE_RESTORE)
{
Info = mixer_restore_config(Id, plci, Rc);
if ((Info != GOOD) || plci->internal_command)
break;
}
plci->adjust_b_state = ADJUST_B_END;
case ADJUST_B_END:
break;
}
return (Info);
}
static void adjust_b1_resource(dword Id, PLCI *plci, API_SAVE *bp_msg, word b1_facilities, word internal_command)
{
dbug(1, dprintf("[%06lx] %s,%d: adjust_b1_resource %d %04x",
UnMapId(Id), (char *)(FILE_), __LINE__,
plci->B1_resource, b1_facilities));
plci->adjust_b_parms_msg = bp_msg;
plci->adjust_b_facilities = b1_facilities;
plci->adjust_b_command = internal_command;
plci->adjust_b_ncci = (word)(Id >> 16);
if ((bp_msg == NULL) && (plci->B1_resource == 0))
plci->adjust_b_mode = ADJUST_B_MODE_SAVE | ADJUST_B_MODE_NO_RESOURCE | ADJUST_B_MODE_SWITCH_L1;
else
plci->adjust_b_mode = ADJUST_B_MODE_SAVE | ADJUST_B_MODE_SWITCH_L1 | ADJUST_B_MODE_RESTORE;
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: Adjust B1 resource %d %04x...",
UnMapId(Id), (char *)(FILE_), __LINE__,
plci->B1_resource, b1_facilities));
}
static void adjust_b_restore(dword Id, PLCI *plci, byte Rc)
{
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: adjust_b_restore %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
if (plci->req_in != 0)
{
plci->internal_command = ADJUST_B_RESTORE_1;
break;
}
Rc = OK;
case ADJUST_B_RESTORE_1:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B enqueued failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
}
plci->adjust_b_parms_msg = NULL;
plci->adjust_b_facilities = plci->B1_facilities;
plci->adjust_b_command = ADJUST_B_RESTORE_2;
plci->adjust_b_ncci = (word)(Id >> 16);
plci->adjust_b_mode = ADJUST_B_MODE_RESTORE;
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: Adjust B restore...",
UnMapId(Id), (char *)(FILE_), __LINE__));
case ADJUST_B_RESTORE_2:
if (adjust_b_process(Id, plci, Rc) != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Adjust B restore failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
}
if (plci->internal_command)
break;
break;
}
}
static void reset_b3_command(dword Id, PLCI *plci, byte Rc)
{
word Info;
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: reset_b3_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
plci->adjust_b_parms_msg = NULL;
plci->adjust_b_facilities = plci->B1_facilities;
plci->adjust_b_command = RESET_B3_COMMAND_1;
plci->adjust_b_ncci = (word)(Id >> 16);
plci->adjust_b_mode = ADJUST_B_MODE_REMOVE_L23 | ADJUST_B_MODE_ASSIGN_L23 | ADJUST_B_MODE_CONNECT;
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: Reset B3...",
UnMapId(Id), (char *)(FILE_), __LINE__));
case RESET_B3_COMMAND_1:
Info = adjust_b_process(Id, plci, Rc);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Reset failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
break;
}
/* sendf (plci->appl, _RESET_B3_R | CONFIRM, Id, plci->number, "w", Info);*/
sendf(plci->appl, _RESET_B3_I, Id, 0, "s", "");
}
static void select_b_command(dword Id, PLCI *plci, byte Rc)
{
word Info;
word internal_command;
byte esc_chi[3];
dbug(1, dprintf("[%06lx] %s,%d: select_b_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
plci->adjust_b_parms_msg = &plci->saved_msg;
if ((plci->tel == ADV_VOICE) && (plci == plci->adapter->AdvSignalPLCI))
plci->adjust_b_facilities = plci->B1_facilities | B1_FACILITY_VOICE;
else
plci->adjust_b_facilities = plci->B1_facilities & ~B1_FACILITY_VOICE;
plci->adjust_b_command = SELECT_B_COMMAND_1;
plci->adjust_b_ncci = (word)(Id >> 16);
if (plci->saved_msg.parms[0].length == 0)
{
plci->adjust_b_mode = ADJUST_B_MODE_SAVE | ADJUST_B_MODE_REMOVE_L23 | ADJUST_B_MODE_SWITCH_L1 |
ADJUST_B_MODE_NO_RESOURCE;
}
else
{
plci->adjust_b_mode = ADJUST_B_MODE_SAVE | ADJUST_B_MODE_REMOVE_L23 | ADJUST_B_MODE_SWITCH_L1 |
ADJUST_B_MODE_ASSIGN_L23 | ADJUST_B_MODE_USER_CONNECT | ADJUST_B_MODE_RESTORE;
}
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: Select B protocol...",
UnMapId(Id), (char *)(FILE_), __LINE__));
case SELECT_B_COMMAND_1:
Info = adjust_b_process(Id, plci, Rc);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: Select B protocol failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
if (plci->tel == ADV_VOICE)
{
esc_chi[0] = 0x02;
esc_chi[1] = 0x18;
esc_chi[2] = plci->b_channel;
SetVoiceChannel(plci->adapter->AdvCodecPLCI, esc_chi, plci->adapter);
}
break;
}
sendf(plci->appl, _SELECT_B_REQ | CONFIRM, Id, plci->number, "w", Info);
}
static void fax_connect_ack_command(dword Id, PLCI *plci, byte Rc)
{
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: fax_connect_ack_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
case FAX_CONNECT_ACK_COMMAND_1:
if (plci_nl_busy(plci))
{
plci->internal_command = FAX_CONNECT_ACK_COMMAND_1;
return;
}
plci->internal_command = FAX_CONNECT_ACK_COMMAND_2;
plci->NData[0].P = plci->fax_connect_info_buffer;
plci->NData[0].PLength = plci->fax_connect_info_length;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_CONNECT_ACK;
plci->adapter->request(&plci->NL);
return;
case FAX_CONNECT_ACK_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: FAX issue CONNECT ACK failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
break;
}
}
if ((plci->ncpi_state & NCPI_VALID_CONNECT_B3_ACT)
&& !(plci->ncpi_state & NCPI_CONNECT_B3_ACT_SENT))
{
if (plci->B3_prot == 4)
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
else
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "S", plci->ncpi_buffer);
plci->ncpi_state |= NCPI_CONNECT_B3_ACT_SENT;
}
}
static void fax_edata_ack_command(dword Id, PLCI *plci, byte Rc)
{
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: fax_edata_ack_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
case FAX_EDATA_ACK_COMMAND_1:
if (plci_nl_busy(plci))
{
plci->internal_command = FAX_EDATA_ACK_COMMAND_1;
return;
}
plci->internal_command = FAX_EDATA_ACK_COMMAND_2;
plci->NData[0].P = plci->fax_connect_info_buffer;
plci->NData[0].PLength = plci->fax_edata_ack_length;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_EDATA;
plci->adapter->request(&plci->NL);
return;
case FAX_EDATA_ACK_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: FAX issue EDATA ACK failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
break;
}
}
}
static void fax_connect_info_command(dword Id, PLCI *plci, byte Rc)
{
word Info;
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: fax_connect_info_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
case FAX_CONNECT_INFO_COMMAND_1:
if (plci_nl_busy(plci))
{
plci->internal_command = FAX_CONNECT_INFO_COMMAND_1;
return;
}
plci->internal_command = FAX_CONNECT_INFO_COMMAND_2;
plci->NData[0].P = plci->fax_connect_info_buffer;
plci->NData[0].PLength = plci->fax_connect_info_length;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_EDATA;
plci->adapter->request(&plci->NL);
return;
case FAX_CONNECT_INFO_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: FAX setting connect info failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
if (plci_nl_busy(plci))
{
plci->internal_command = FAX_CONNECT_INFO_COMMAND_2;
return;
}
plci->command = _CONNECT_B3_R;
nl_req_ncci(plci, N_CONNECT, 0);
send_req(plci);
return;
}
sendf(plci->appl, _CONNECT_B3_R | CONFIRM, Id, plci->number, "w", Info);
}
static void fax_adjust_b23_command(dword Id, PLCI *plci, byte Rc)
{
word Info;
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: fax_adjust_b23_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
plci->adjust_b_parms_msg = NULL;
plci->adjust_b_facilities = plci->B1_facilities;
plci->adjust_b_command = FAX_ADJUST_B23_COMMAND_1;
plci->adjust_b_ncci = (word)(Id >> 16);
plci->adjust_b_mode = ADJUST_B_MODE_REMOVE_L23 | ADJUST_B_MODE_ASSIGN_L23;
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: FAX adjust B23...",
UnMapId(Id), (char *)(FILE_), __LINE__));
case FAX_ADJUST_B23_COMMAND_1:
Info = adjust_b_process(Id, plci, Rc);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: FAX adjust failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
case FAX_ADJUST_B23_COMMAND_2:
if (plci_nl_busy(plci))
{
plci->internal_command = FAX_ADJUST_B23_COMMAND_2;
return;
}
plci->command = _CONNECT_B3_R;
nl_req_ncci(plci, N_CONNECT, 0);
send_req(plci);
return;
}
sendf(plci->appl, _CONNECT_B3_R | CONFIRM, Id, plci->number, "w", Info);
}
static void fax_disconnect_command(dword Id, PLCI *plci, byte Rc)
{
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: fax_disconnect_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
plci->internal_command = FAX_DISCONNECT_COMMAND_1;
return;
case FAX_DISCONNECT_COMMAND_1:
case FAX_DISCONNECT_COMMAND_2:
case FAX_DISCONNECT_COMMAND_3:
if ((Rc != OK) && (Rc != OK_FC) && (Rc != 0))
{
dbug(1, dprintf("[%06lx] %s,%d: FAX disconnect EDATA failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
break;
}
if (Rc == OK)
{
if ((internal_command == FAX_DISCONNECT_COMMAND_1)
|| (internal_command == FAX_DISCONNECT_COMMAND_2))
{
plci->internal_command = FAX_DISCONNECT_COMMAND_2;
}
}
else if (Rc == 0)
{
if (internal_command == FAX_DISCONNECT_COMMAND_1)
plci->internal_command = FAX_DISCONNECT_COMMAND_3;
}
return;
}
}
static void rtp_connect_b3_req_command(dword Id, PLCI *plci, byte Rc)
{
word Info;
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: rtp_connect_b3_req_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
case RTP_CONNECT_B3_REQ_COMMAND_1:
if (plci_nl_busy(plci))
{
plci->internal_command = RTP_CONNECT_B3_REQ_COMMAND_1;
return;
}
plci->internal_command = RTP_CONNECT_B3_REQ_COMMAND_2;
nl_req_ncci(plci, N_CONNECT, 0);
send_req(plci);
return;
case RTP_CONNECT_B3_REQ_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: RTP setting connect info failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
Info = _WRONG_STATE;
break;
}
if (plci_nl_busy(plci))
{
plci->internal_command = RTP_CONNECT_B3_REQ_COMMAND_2;
return;
}
plci->internal_command = RTP_CONNECT_B3_REQ_COMMAND_3;
plci->NData[0].PLength = plci->internal_req_buffer[0];
plci->NData[0].P = plci->internal_req_buffer + 1;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_UDATA;
plci->adapter->request(&plci->NL);
break;
case RTP_CONNECT_B3_REQ_COMMAND_3:
return;
}
sendf(plci->appl, _CONNECT_B3_R | CONFIRM, Id, plci->number, "w", Info);
}
static void rtp_connect_b3_res_command(dword Id, PLCI *plci, byte Rc)
{
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: rtp_connect_b3_res_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
case RTP_CONNECT_B3_RES_COMMAND_1:
if (plci_nl_busy(plci))
{
plci->internal_command = RTP_CONNECT_B3_RES_COMMAND_1;
return;
}
plci->internal_command = RTP_CONNECT_B3_RES_COMMAND_2;
nl_req_ncci(plci, N_CONNECT_ACK, (byte)(Id >> 16));
send_req(plci);
return;
case RTP_CONNECT_B3_RES_COMMAND_2:
if ((Rc != OK) && (Rc != OK_FC))
{
dbug(1, dprintf("[%06lx] %s,%d: RTP setting connect resp info failed %02x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc));
break;
}
if (plci_nl_busy(plci))
{
plci->internal_command = RTP_CONNECT_B3_RES_COMMAND_2;
return;
}
sendf(plci->appl, _CONNECT_B3_ACTIVE_I, Id, 0, "s", "");
plci->internal_command = RTP_CONNECT_B3_RES_COMMAND_3;
plci->NData[0].PLength = plci->internal_req_buffer[0];
plci->NData[0].P = plci->internal_req_buffer + 1;
plci->NL.X = plci->NData;
plci->NL.ReqCh = 0;
plci->NL.Req = plci->nl_req = (byte) N_UDATA;
plci->adapter->request(&plci->NL);
return;
case RTP_CONNECT_B3_RES_COMMAND_3:
return;
}
}
static void hold_save_command(dword Id, PLCI *plci, byte Rc)
{
byte SS_Ind[] = "\x05\x02\x00\x02\x00\x00"; /* Hold_Ind struct*/
word Info;
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: hold_save_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
if (!plci->NL.Id)
break;
plci->command = 0;
plci->adjust_b_parms_msg = NULL;
plci->adjust_b_facilities = plci->B1_facilities;
plci->adjust_b_command = HOLD_SAVE_COMMAND_1;
plci->adjust_b_ncci = (word)(Id >> 16);
plci->adjust_b_mode = ADJUST_B_MODE_SAVE | ADJUST_B_MODE_REMOVE_L23;
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: HOLD save...",
UnMapId(Id), (char *)(FILE_), __LINE__));
case HOLD_SAVE_COMMAND_1:
Info = adjust_b_process(Id, plci, Rc);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: HOLD save failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
}
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0, "ws", 3, SS_Ind);
}
static void retrieve_restore_command(dword Id, PLCI *plci, byte Rc)
{
byte SS_Ind[] = "\x05\x03\x00\x02\x00\x00"; /* Retrieve_Ind struct*/
word Info;
word internal_command;
dbug(1, dprintf("[%06lx] %s,%d: retrieve_restore_command %02x %04x",
UnMapId(Id), (char *)(FILE_), __LINE__, Rc, plci->internal_command));
Info = GOOD;
internal_command = plci->internal_command;
plci->internal_command = 0;
switch (internal_command)
{
default:
plci->command = 0;
plci->adjust_b_parms_msg = NULL;
plci->adjust_b_facilities = plci->B1_facilities;
plci->adjust_b_command = RETRIEVE_RESTORE_COMMAND_1;
plci->adjust_b_ncci = (word)(Id >> 16);
plci->adjust_b_mode = ADJUST_B_MODE_ASSIGN_L23 | ADJUST_B_MODE_USER_CONNECT | ADJUST_B_MODE_RESTORE;
plci->adjust_b_state = ADJUST_B_START;
dbug(1, dprintf("[%06lx] %s,%d: RETRIEVE restore...",
UnMapId(Id), (char *)(FILE_), __LINE__));
case RETRIEVE_RESTORE_COMMAND_1:
Info = adjust_b_process(Id, plci, Rc);
if (Info != GOOD)
{
dbug(1, dprintf("[%06lx] %s,%d: RETRIEVE restore failed",
UnMapId(Id), (char *)(FILE_), __LINE__));
break;
}
if (plci->internal_command)
return;
}
sendf(plci->appl, _FACILITY_I, Id & 0xffffL, 0, "ws", 3, SS_Ind);
}
static void init_b1_config(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: init_b1_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
plci->B1_resource = 0;
plci->B1_facilities = 0;
plci->li_bchannel_id = 0;
mixer_clear_config(plci);
ec_clear_config(plci);
dtmf_rec_clear_config(plci);
dtmf_send_clear_config(plci);
dtmf_parameter_clear_config(plci);
adv_voice_clear_config(plci);
adjust_b_clear(plci);
}
static void clear_b1_config(PLCI *plci)
{
dbug(1, dprintf("[%06lx] %s,%d: clear_b1_config",
(dword)((plci->Id << 8) | UnMapController(plci->adapter->Id)),
(char *)(FILE_), __LINE__));
adv_voice_clear_config(plci);
adjust_b_clear(plci);
ec_clear_config(plci);
dtmf_rec_clear_config(plci);
dtmf_send_clear_config(plci);
dtmf_parameter_clear_config(plci);
if ((plci->li_bchannel_id != 0)
&& (li_config_table[plci->adapter->li_base + (plci->li_bchannel_id - 1)].plci == plci))
{
mixer_clear_config(plci);
li_config_table[plci->adapter->li_base + (plci->li_bchannel_id - 1)].plci = NULL;
plci->li_bchannel_id = 0;
}
plci->B1_resource = 0;
plci->B1_facilities = 0;
}
/* -----------------------------------------------------------------
XON protocol local helpers
----------------------------------------------------------------- */
static void channel_flow_control_remove(PLCI *plci) {
DIVA_CAPI_ADAPTER *a = plci->adapter;
word i;
for (i = 1; i < MAX_NL_CHANNEL + 1; i++) {
if (a->ch_flow_plci[i] == plci->Id) {
a->ch_flow_plci[i] = 0;
a->ch_flow_control[i] = 0;
}
}
}
static void channel_x_on(PLCI *plci, byte ch) {
DIVA_CAPI_ADAPTER *a = plci->adapter;
if (a->ch_flow_control[ch] & N_XON_SENT) {
a->ch_flow_control[ch] &= ~N_XON_SENT;
}
}
static void channel_x_off(PLCI *plci, byte ch, byte flag) {
DIVA_CAPI_ADAPTER *a = plci->adapter;
if ((a->ch_flow_control[ch] & N_RX_FLOW_CONTROL_MASK) == 0) {
a->ch_flow_control[ch] |= (N_CH_XOFF | flag);
a->ch_flow_plci[ch] = plci->Id;
a->ch_flow_control_pending++;
}
}
static void channel_request_xon(PLCI *plci, byte ch) {
DIVA_CAPI_ADAPTER *a = plci->adapter;
if (a->ch_flow_control[ch] & N_CH_XOFF) {
a->ch_flow_control[ch] |= N_XON_REQ;
a->ch_flow_control[ch] &= ~N_CH_XOFF;
a->ch_flow_control[ch] &= ~N_XON_CONNECT_IND;
}
}
static void channel_xmit_extended_xon(PLCI *plci) {
DIVA_CAPI_ADAPTER *a;
int max_ch = ARRAY_SIZE(a->ch_flow_control);
int i, one_requested = 0;
if ((!plci) || (!plci->Id) || ((a = plci->adapter) == NULL)) {
return;
}
for (i = 0; i < max_ch; i++) {
if ((a->ch_flow_control[i] & N_CH_XOFF) &&
(a->ch_flow_control[i] & N_XON_CONNECT_IND) &&
(plci->Id == a->ch_flow_plci[i])) {
channel_request_xon(plci, (byte)i);
one_requested = 1;
}
}
if (one_requested) {
channel_xmit_xon(plci);
}
}
/*
Try to xmit next X_ON
*/
static int find_channel_with_pending_x_on(DIVA_CAPI_ADAPTER *a, PLCI *plci) {
int max_ch = ARRAY_SIZE(a->ch_flow_control);
int i;
if (!(plci->adapter->manufacturer_features & MANUFACTURER_FEATURE_XONOFF_FLOW_CONTROL)) {
return (0);
}
if (a->last_flow_control_ch >= max_ch) {
a->last_flow_control_ch = 1;
}
for (i = a->last_flow_control_ch; i < max_ch; i++) {
if ((a->ch_flow_control[i] & N_XON_REQ) &&
(plci->Id == a->ch_flow_plci[i])) {
a->last_flow_control_ch = i + 1;
return (i);
}
}
for (i = 1; i < a->last_flow_control_ch; i++) {
if ((a->ch_flow_control[i] & N_XON_REQ) &&
(plci->Id == a->ch_flow_plci[i])) {
a->last_flow_control_ch = i + 1;
return (i);
}
}
return (0);
}
static void channel_xmit_xon(PLCI *plci) {
DIVA_CAPI_ADAPTER *a = plci->adapter;
byte ch;
if (plci->nl_req || !plci->NL.Id || plci->nl_remove_id) {
return;
}
if ((ch = (byte)find_channel_with_pending_x_on(a, plci)) == 0) {
return;
}
a->ch_flow_control[ch] &= ~N_XON_REQ;
a->ch_flow_control[ch] |= N_XON_SENT;
plci->NL.Req = plci->nl_req = (byte)N_XON;
plci->NL.ReqCh = ch;
plci->NL.X = plci->NData;
plci->NL.XNum = 1;
plci->NData[0].P = &plci->RBuffer[0];
plci->NData[0].PLength = 0;
plci->adapter->request(&plci->NL);
}
static int channel_can_xon(PLCI *plci, byte ch) {
APPL *APPLptr;
DIVA_CAPI_ADAPTER *a;
word NCCIcode;
dword count;
word Num;
word i;
APPLptr = plci->appl;
a = plci->adapter;
if (!APPLptr)
return (0);
NCCIcode = a->ch_ncci[ch] | (((word) a->Id) << 8);
/* count all buffers within the Application pool */
/* belonging to the same NCCI. XON if a first is */
/* used. */
count = 0;
Num = 0xffff;
for (i = 0; i < APPLptr->MaxBuffer; i++) {
if (NCCIcode == APPLptr->DataNCCI[i]) count++;
if (!APPLptr->DataNCCI[i] && Num == 0xffff) Num = i;
}
if ((count > 2) || (Num == 0xffff)) {
return (0);
}
return (1);
}
/*------------------------------------------------------------------*/
static word CPN_filter_ok(byte *cpn, DIVA_CAPI_ADAPTER *a, word offset)
{
return 1;
}
/**********************************************************************************/
/* function groups the listening applications according to the CIP mask and the */
/* Info_Mask. Each group gets just one Connect_Ind. Some application manufacturer */
/* are not multi-instance capable, so they start e.g. 30 applications what causes */
/* big problems on application level (one call, 30 Connect_Ind, ect). The */
/* function must be enabled by setting "a->group_optimization_enabled" from the */
/* OS specific part (per adapter). */
/**********************************************************************************/
static void group_optimization(DIVA_CAPI_ADAPTER *a, PLCI *plci)
{
word i, j, k, busy, group_found;
dword info_mask_group[MAX_CIP_TYPES];
dword cip_mask_group[MAX_CIP_TYPES];
word appl_number_group_type[MAX_APPL];
PLCI *auxplci;
set_group_ind_mask(plci); /* all APPLs within this inc. call are allowed to dial in */
if (!a->group_optimization_enabled)
{
dbug(1, dprintf("No group optimization"));
return;
}
dbug(1, dprintf("Group optimization = 0x%x...", a->group_optimization_enabled));
for (i = 0; i < MAX_CIP_TYPES; i++)
{
info_mask_group[i] = 0;
cip_mask_group[i] = 0;
}
for (i = 0; i < MAX_APPL; i++)
{
appl_number_group_type[i] = 0;
}
for (i = 0; i < max_appl; i++) /* check if any multi instance capable application is present */
{ /* group_optimization set to 1 means not to optimize multi-instance capable applications (default) */
if (application[i].Id && (application[i].MaxNCCI) > 1 && (a->CIP_Mask[i]) && (a->group_optimization_enabled == 1))
{
dbug(1, dprintf("Multi-Instance capable, no optimization required"));
return; /* allow good application unfiltered access */
}
}
for (i = 0; i < max_appl; i++) /* Build CIP Groups */
{
if (application[i].Id && a->CIP_Mask[i])
{
for (k = 0, busy = false; k < a->max_plci; k++)
{
if (a->plci[k].Id)
{
auxplci = &a->plci[k];
if (auxplci->appl == &application[i]) /* application has a busy PLCI */
{
busy = true;
dbug(1, dprintf("Appl 0x%x is busy", i + 1));
}
else if (test_c_ind_mask_bit(auxplci, i)) /* application has an incoming call pending */
{
busy = true;
dbug(1, dprintf("Appl 0x%x has inc. call pending", i + 1));
}
}
}
for (j = 0, group_found = 0; j <= (MAX_CIP_TYPES) && !busy && !group_found; j++) /* build groups with free applications only */
{
if (j == MAX_CIP_TYPES) /* all groups are in use but group still not found */
{ /* the MAX_CIP_TYPES group enables all calls because of field overflow */
appl_number_group_type[i] = MAX_CIP_TYPES;
group_found = true;
dbug(1, dprintf("Field overflow appl 0x%x", i + 1));
}
else if ((info_mask_group[j] == a->CIP_Mask[i]) && (cip_mask_group[j] == a->Info_Mask[i]))
{ /* is group already present ? */
appl_number_group_type[i] = j | 0x80; /* store the group number for each application */
group_found = true;
dbug(1, dprintf("Group 0x%x found with appl 0x%x, CIP=0x%lx", appl_number_group_type[i], i + 1, info_mask_group[j]));
}
else if (!info_mask_group[j])
{ /* establish a new group */
appl_number_group_type[i] = j | 0x80; /* store the group number for each application */
info_mask_group[j] = a->CIP_Mask[i]; /* store the new CIP mask for the new group */
cip_mask_group[j] = a->Info_Mask[i]; /* store the new Info_Mask for this new group */
group_found = true;
dbug(1, dprintf("New Group 0x%x established with appl 0x%x, CIP=0x%lx", appl_number_group_type[i], i + 1, info_mask_group[j]));
}
}
}
}
for (i = 0; i < max_appl; i++) /* Build group_optimization_mask_table */
{
if (appl_number_group_type[i]) /* application is free, has listens and is member of a group */
{
if (appl_number_group_type[i] == MAX_CIP_TYPES)
{
dbug(1, dprintf("OverflowGroup 0x%x, valid appl = 0x%x, call enabled", appl_number_group_type[i], i + 1));
}
else
{
dbug(1, dprintf("Group 0x%x, valid appl = 0x%x", appl_number_group_type[i], i + 1));
for (j = i + 1; j < max_appl; j++) /* search other group members and mark them as busy */
{
if (appl_number_group_type[i] == appl_number_group_type[j])
{
dbug(1, dprintf("Appl 0x%x is member of group 0x%x, no call", j + 1, appl_number_group_type[j]));
clear_group_ind_mask_bit(plci, j); /* disable call on other group members */
appl_number_group_type[j] = 0; /* remove disabled group member from group list */
}
}
}
}
else /* application should not get a call */
{
clear_group_ind_mask_bit(plci, i);
}
}
}
/* OS notifies the driver about a application Capi_Register */
word CapiRegister(word id)
{
word i, j, appls_found;
PLCI *plci;
DIVA_CAPI_ADAPTER *a;
for (i = 0, appls_found = 0; i < max_appl; i++)
{
if (application[i].Id && (application[i].Id != id))
{
appls_found++; /* an application has been found */
}
}
if (appls_found) return true;
for (i = 0; i < max_adapter; i++) /* scan all adapters... */
{
a = &adapter[i];
if (a->request)
{
if (a->flag_dynamic_l1_down) /* remove adapter from L1 tristate (Huntgroup) */
{
if (!appls_found) /* first application does a capi register */
{
if ((j = get_plci(a))) /* activate L1 of all adapters */
{
plci = &a->plci[j - 1];
plci->command = 0;
add_p(plci, OAD, "\x01\xfd");
add_p(plci, CAI, "\x01\x80");
add_p(plci, UID, "\x06\x43\x61\x70\x69\x32\x30");
add_p(plci, SHIFT | 6, NULL);
add_p(plci, SIN, "\x02\x00\x00");
plci->internal_command = START_L1_SIG_ASSIGN_PEND;
sig_req(plci, ASSIGN, DSIG_ID);
add_p(plci, FTY, "\x02\xff\x07"); /* l1 start */
sig_req(plci, SIG_CTRL, 0);
send_req(plci);
}
}
}
}
}
return false;
}
/*------------------------------------------------------------------*/
/* Functions for virtual Switching e.g. Transfer by join, Conference */
static void VSwitchReqInd(PLCI *plci, dword Id, byte **parms)
{
word i;
/* Format of vswitch_t:
0 byte length
1 byte VSWITCHIE
2 byte VSWITCH_REQ/VSWITCH_IND
3 byte reserved
4 word VSwitchcommand
6 word returnerror
8... Params
*/
if (!plci ||
!plci->appl ||
!plci->State ||
plci->Sig.Ind == NCR_FACILITY
)
return;
for (i = 0; i < MAX_MULTI_IE; i++)
{
if (!parms[i][0]) continue;
if (parms[i][0] < 7)
{
parms[i][0] = 0; /* kill it */
continue;
}
dbug(1, dprintf("VSwitchReqInd(%d)", parms[i][4]));
switch (parms[i][4])
{
case VSJOIN:
if (!plci->relatedPTYPLCI ||
(plci->ptyState != S_ECT && plci->relatedPTYPLCI->ptyState != S_ECT))
{ /* Error */
break;
}
/* remember all necessary informations */
if (parms[i][0] != 11 || parms[i][8] != 3) /* Length Test */
{
break;
}
if (parms[i][2] == VSWITCH_IND && parms[i][9] == 1)
{ /* first indication after ECT-Request on Consultation Call */
plci->vswitchstate = parms[i][9];
parms[i][9] = 2; /* State */
/* now ask first Call to join */
}
else if (parms[i][2] == VSWITCH_REQ && parms[i][9] == 3)
{ /* Answer of VSWITCH_REQ from first Call */
plci->vswitchstate = parms[i][9];
/* tell consultation call to join
and the protocol capabilities of the first call */
}
else
{ /* Error */
break;
}
plci->vsprot = parms[i][10]; /* protocol */
plci->vsprotdialect = parms[i][11]; /* protocoldialect */
/* send join request to related PLCI */
parms[i][1] = VSWITCHIE;
parms[i][2] = VSWITCH_REQ;
plci->relatedPTYPLCI->command = 0;
plci->relatedPTYPLCI->internal_command = VSWITCH_REQ_PEND;
add_p(plci->relatedPTYPLCI, ESC, &parms[i][0]);
sig_req(plci->relatedPTYPLCI, VSWITCH_REQ, 0);
send_req(plci->relatedPTYPLCI);
break;
case VSTRANSPORT:
default:
if (plci->relatedPTYPLCI &&
plci->vswitchstate == 3 &&
plci->relatedPTYPLCI->vswitchstate == 3)
{
add_p(plci->relatedPTYPLCI, ESC, &parms[i][0]);
sig_req(plci->relatedPTYPLCI, VSWITCH_REQ, 0);
send_req(plci->relatedPTYPLCI);
}
break;
}
parms[i][0] = 0; /* kill it */
}
}
/*------------------------------------------------------------------*/
static int diva_get_dma_descriptor(PLCI *plci, dword *dma_magic) {
ENTITY e;
IDI_SYNC_REQ *pReq = (IDI_SYNC_REQ *)&e;
if (!(diva_xdi_extended_features & DIVA_CAPI_XDI_PROVIDES_RX_DMA)) {
return (-1);
}
pReq->xdi_dma_descriptor_operation.Req = 0;
pReq->xdi_dma_descriptor_operation.Rc = IDI_SYNC_REQ_DMA_DESCRIPTOR_OPERATION;
pReq->xdi_dma_descriptor_operation.info.operation = IDI_SYNC_REQ_DMA_DESCRIPTOR_ALLOC;
pReq->xdi_dma_descriptor_operation.info.descriptor_number = -1;
pReq->xdi_dma_descriptor_operation.info.descriptor_address = NULL;
pReq->xdi_dma_descriptor_operation.info.descriptor_magic = 0;
e.user[0] = plci->adapter->Id - 1;
plci->adapter->request((ENTITY *)pReq);
if (!pReq->xdi_dma_descriptor_operation.info.operation &&
(pReq->xdi_dma_descriptor_operation.info.descriptor_number >= 0) &&
pReq->xdi_dma_descriptor_operation.info.descriptor_magic) {
*dma_magic = pReq->xdi_dma_descriptor_operation.info.descriptor_magic;
dbug(3, dprintf("dma_alloc, a:%d (%d-%08x)",
plci->adapter->Id,
pReq->xdi_dma_descriptor_operation.info.descriptor_number,
*dma_magic));
return (pReq->xdi_dma_descriptor_operation.info.descriptor_number);
} else {
dbug(1, dprintf("dma_alloc failed"));
return (-1);
}
}
static void diva_free_dma_descriptor(PLCI *plci, int nr) {
ENTITY e;
IDI_SYNC_REQ *pReq = (IDI_SYNC_REQ *)&e;
if (nr < 0) {
return;
}
pReq->xdi_dma_descriptor_operation.Req = 0;
pReq->xdi_dma_descriptor_operation.Rc = IDI_SYNC_REQ_DMA_DESCRIPTOR_OPERATION;
pReq->xdi_dma_descriptor_operation.info.operation = IDI_SYNC_REQ_DMA_DESCRIPTOR_FREE;
pReq->xdi_dma_descriptor_operation.info.descriptor_number = nr;
pReq->xdi_dma_descriptor_operation.info.descriptor_address = NULL;
pReq->xdi_dma_descriptor_operation.info.descriptor_magic = 0;
e.user[0] = plci->adapter->Id - 1;
plci->adapter->request((ENTITY *)pReq);
if (!pReq->xdi_dma_descriptor_operation.info.operation) {
dbug(1, dprintf("dma_free(%d)", nr));
} else {
dbug(1, dprintf("dma_free failed (%d)", nr));
}
}
/*------------------------------------------------------------------*/
| gpl-2.0 |
mixtile/garage-linux | drivers/media/video/saa7164/saa7164-fw.c | 8171 | 16461 | /*
* Driver for the NXP SAA7164 PCIe bridge
*
* Copyright (c) 2010 Steven Toth <stoth@kernellabs.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/firmware.h>
#include <linux/slab.h>
#include "saa7164.h"
#define SAA7164_REV2_FIRMWARE "NXP7164-2010-03-10.1.fw"
#define SAA7164_REV2_FIRMWARE_SIZE 4019072
#define SAA7164_REV3_FIRMWARE "NXP7164-2010-03-10.1.fw"
#define SAA7164_REV3_FIRMWARE_SIZE 4019072
struct fw_header {
u32 firmwaresize;
u32 bslsize;
u32 reserved;
u32 version;
};
int saa7164_dl_wait_ack(struct saa7164_dev *dev, u32 reg)
{
u32 timeout = SAA_DEVICE_TIMEOUT;
while ((saa7164_readl(reg) & 0x01) == 0) {
timeout -= 10;
if (timeout == 0) {
printk(KERN_ERR "%s() timeout (no d/l ack)\n",
__func__);
return -EBUSY;
}
msleep(100);
}
return 0;
}
int saa7164_dl_wait_clr(struct saa7164_dev *dev, u32 reg)
{
u32 timeout = SAA_DEVICE_TIMEOUT;
while (saa7164_readl(reg) & 0x01) {
timeout -= 10;
if (timeout == 0) {
printk(KERN_ERR "%s() timeout (no d/l clr)\n",
__func__);
return -EBUSY;
}
msleep(100);
}
return 0;
}
/* TODO: move dlflags into dev-> and change to write/readl/b */
/* TODO: Excessive levels of debug */
int saa7164_downloadimage(struct saa7164_dev *dev, u8 *src, u32 srcsize,
u32 dlflags, u8 *dst, u32 dstsize)
{
u32 reg, timeout, offset;
u8 *srcbuf = NULL;
int ret;
u32 dlflag = dlflags;
u32 dlflag_ack = dlflag + 4;
u32 drflag = dlflag_ack + 4;
u32 drflag_ack = drflag + 4;
u32 bleflag = drflag_ack + 4;
dprintk(DBGLVL_FW,
"%s(image=%p, size=%d, flags=0x%x, dst=%p, dstsize=0x%x)\n",
__func__, src, srcsize, dlflags, dst, dstsize);
if ((src == NULL) || (dst == NULL)) {
ret = -EIO;
goto out;
}
srcbuf = kzalloc(4 * 1048576, GFP_KERNEL);
if (NULL == srcbuf) {
ret = -ENOMEM;
goto out;
}
if (srcsize > (4*1048576)) {
ret = -ENOMEM;
goto out;
}
memcpy(srcbuf, src, srcsize);
dprintk(DBGLVL_FW, "%s() dlflag = 0x%x\n", __func__, dlflag);
dprintk(DBGLVL_FW, "%s() dlflag_ack = 0x%x\n", __func__, dlflag_ack);
dprintk(DBGLVL_FW, "%s() drflag = 0x%x\n", __func__, drflag);
dprintk(DBGLVL_FW, "%s() drflag_ack = 0x%x\n", __func__, drflag_ack);
dprintk(DBGLVL_FW, "%s() bleflag = 0x%x\n", __func__, bleflag);
reg = saa7164_readl(dlflag);
dprintk(DBGLVL_FW, "%s() dlflag (0x%x)= 0x%x\n", __func__, dlflag, reg);
if (reg == 1)
dprintk(DBGLVL_FW,
"%s() Download flag already set, please reboot\n",
__func__);
/* Indicate download start */
saa7164_writel(dlflag, 1);
ret = saa7164_dl_wait_ack(dev, dlflag_ack);
if (ret < 0)
goto out;
/* Ack download start, then wait for wait */
saa7164_writel(dlflag, 0);
ret = saa7164_dl_wait_clr(dev, dlflag_ack);
if (ret < 0)
goto out;
/* Deal with the raw firmware, in the appropriate chunk size */
for (offset = 0; srcsize > dstsize;
srcsize -= dstsize, offset += dstsize) {
dprintk(DBGLVL_FW, "%s() memcpy %d\n", __func__, dstsize);
memcpy(dst, srcbuf + offset, dstsize);
/* Flag the data as ready */
saa7164_writel(drflag, 1);
ret = saa7164_dl_wait_ack(dev, drflag_ack);
if (ret < 0)
goto out;
/* Wait for indication data was received */
saa7164_writel(drflag, 0);
ret = saa7164_dl_wait_clr(dev, drflag_ack);
if (ret < 0)
goto out;
}
dprintk(DBGLVL_FW, "%s() memcpy(l) %d\n", __func__, dstsize);
/* Write last block to the device */
memcpy(dst, srcbuf+offset, srcsize);
/* Flag the data as ready */
saa7164_writel(drflag, 1);
ret = saa7164_dl_wait_ack(dev, drflag_ack);
if (ret < 0)
goto out;
saa7164_writel(drflag, 0);
timeout = 0;
while (saa7164_readl(bleflag) != SAA_DEVICE_IMAGE_BOOTING) {
if (saa7164_readl(bleflag) & SAA_DEVICE_IMAGE_CORRUPT) {
printk(KERN_ERR "%s() image corrupt\n", __func__);
ret = -EBUSY;
goto out;
}
if (saa7164_readl(bleflag) & SAA_DEVICE_MEMORY_CORRUPT) {
printk(KERN_ERR "%s() device memory corrupt\n",
__func__);
ret = -EBUSY;
goto out;
}
msleep(10); /* Checkpatch throws a < 20ms warning */
if (timeout++ > 60)
break;
}
printk(KERN_INFO "%s() Image downloaded, booting...\n", __func__);
ret = saa7164_dl_wait_clr(dev, drflag_ack);
if (ret < 0)
goto out;
printk(KERN_INFO "%s() Image booted successfully.\n", __func__);
ret = 0;
out:
kfree(srcbuf);
return ret;
}
/* TODO: Excessive debug */
/* Load the firmware. Optionally it can be in ROM or newer versions
* can be on disk, saving the expense of the ROM hardware. */
int saa7164_downloadfirmware(struct saa7164_dev *dev)
{
/* u32 second_timeout = 60 * SAA_DEVICE_TIMEOUT; */
u32 tmp, filesize, version, err_flags, first_timeout, fwlength;
u32 second_timeout, updatebootloader = 1, bootloadersize = 0;
const struct firmware *fw = NULL;
struct fw_header *hdr, *boothdr = NULL, *fwhdr;
u32 bootloaderversion = 0, fwloadersize;
u8 *bootloaderoffset = NULL, *fwloaderoffset;
char *fwname;
int ret;
dprintk(DBGLVL_FW, "%s()\n", __func__);
if (saa7164_boards[dev->board].chiprev == SAA7164_CHIP_REV2) {
fwname = SAA7164_REV2_FIRMWARE;
fwlength = SAA7164_REV2_FIRMWARE_SIZE;
} else {
fwname = SAA7164_REV3_FIRMWARE;
fwlength = SAA7164_REV3_FIRMWARE_SIZE;
}
version = saa7164_getcurrentfirmwareversion(dev);
if (version == 0x00) {
second_timeout = 100;
first_timeout = 100;
err_flags = saa7164_readl(SAA_BOOTLOADERERROR_FLAGS);
dprintk(DBGLVL_FW, "%s() err_flags = %x\n",
__func__, err_flags);
while (err_flags != SAA_DEVICE_IMAGE_BOOTING) {
dprintk(DBGLVL_FW, "%s() err_flags = %x\n",
__func__, err_flags);
msleep(10); /* Checkpatch throws a < 20ms warning */
if (err_flags & SAA_DEVICE_IMAGE_CORRUPT) {
printk(KERN_ERR "%s() firmware corrupt\n",
__func__);
break;
}
if (err_flags & SAA_DEVICE_MEMORY_CORRUPT) {
printk(KERN_ERR "%s() device memory corrupt\n",
__func__);
break;
}
if (err_flags & SAA_DEVICE_NO_IMAGE) {
printk(KERN_ERR "%s() no first image\n",
__func__);
break;
}
if (err_flags & SAA_DEVICE_IMAGE_SEARCHING) {
first_timeout -= 10;
if (first_timeout == 0) {
printk(KERN_ERR
"%s() no first image\n",
__func__);
break;
}
} else if (err_flags & SAA_DEVICE_IMAGE_LOADING) {
second_timeout -= 10;
if (second_timeout == 0) {
printk(KERN_ERR
"%s() FW load time exceeded\n",
__func__);
break;
}
} else {
second_timeout -= 10;
if (second_timeout == 0) {
printk(KERN_ERR
"%s() Unknown bootloader flags 0x%x\n",
__func__, err_flags);
break;
}
}
err_flags = saa7164_readl(SAA_BOOTLOADERERROR_FLAGS);
} /* While != Booting */
if (err_flags == SAA_DEVICE_IMAGE_BOOTING) {
dprintk(DBGLVL_FW, "%s() Loader 1 has loaded.\n",
__func__);
first_timeout = SAA_DEVICE_TIMEOUT;
second_timeout = 60 * SAA_DEVICE_TIMEOUT;
second_timeout = 100;
err_flags = saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS);
dprintk(DBGLVL_FW, "%s() err_flags2 = %x\n",
__func__, err_flags);
while (err_flags != SAA_DEVICE_IMAGE_BOOTING) {
dprintk(DBGLVL_FW, "%s() err_flags2 = %x\n",
__func__, err_flags);
msleep(10); /* Checkpatch throws a < 20ms warning */
if (err_flags & SAA_DEVICE_IMAGE_CORRUPT) {
printk(KERN_ERR
"%s() firmware corrupt\n",
__func__);
break;
}
if (err_flags & SAA_DEVICE_MEMORY_CORRUPT) {
printk(KERN_ERR
"%s() device memory corrupt\n",
__func__);
break;
}
if (err_flags & SAA_DEVICE_NO_IMAGE) {
printk(KERN_ERR "%s() no first image\n",
__func__);
break;
}
if (err_flags & SAA_DEVICE_IMAGE_SEARCHING) {
first_timeout -= 10;
if (first_timeout == 0) {
printk(KERN_ERR
"%s() no second image\n",
__func__);
break;
}
} else if (err_flags &
SAA_DEVICE_IMAGE_LOADING) {
second_timeout -= 10;
if (second_timeout == 0) {
printk(KERN_ERR
"%s() FW load time exceeded\n",
__func__);
break;
}
} else {
second_timeout -= 10;
if (second_timeout == 0) {
printk(KERN_ERR
"%s() Unknown bootloader flags 0x%x\n",
__func__, err_flags);
break;
}
}
err_flags =
saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS);
} /* err_flags != SAA_DEVICE_IMAGE_BOOTING */
dprintk(DBGLVL_FW, "%s() Loader flags 1:0x%x 2:0x%x.\n",
__func__,
saa7164_readl(SAA_BOOTLOADERERROR_FLAGS),
saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS));
} /* err_flags == SAA_DEVICE_IMAGE_BOOTING */
/* It's possible for both firmwares to have booted,
* but that doesn't mean they've finished booting yet.
*/
if ((saa7164_readl(SAA_BOOTLOADERERROR_FLAGS) ==
SAA_DEVICE_IMAGE_BOOTING) &&
(saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS) ==
SAA_DEVICE_IMAGE_BOOTING)) {
dprintk(DBGLVL_FW, "%s() Loader 2 has loaded.\n",
__func__);
first_timeout = SAA_DEVICE_TIMEOUT;
while (first_timeout) {
msleep(10); /* Checkpatch throws a < 20ms warning */
version =
saa7164_getcurrentfirmwareversion(dev);
if (version) {
dprintk(DBGLVL_FW,
"%s() All f/w loaded successfully\n",
__func__);
break;
} else {
first_timeout -= 10;
if (first_timeout == 0) {
printk(KERN_ERR
"%s() FW did not boot\n",
__func__);
break;
}
}
}
}
version = saa7164_getcurrentfirmwareversion(dev);
} /* version == 0 */
/* Has the firmware really booted? */
if ((saa7164_readl(SAA_BOOTLOADERERROR_FLAGS) ==
SAA_DEVICE_IMAGE_BOOTING) &&
(saa7164_readl(SAA_SECONDSTAGEERROR_FLAGS) ==
SAA_DEVICE_IMAGE_BOOTING) && (version == 0)) {
printk(KERN_ERR
"%s() The firmware hung, probably bad firmware\n",
__func__);
/* Tell the second stage loader we have a deadlock */
saa7164_writel(SAA_DEVICE_DEADLOCK_DETECTED_OFFSET,
SAA_DEVICE_DEADLOCK_DETECTED);
saa7164_getfirmwarestatus(dev);
return -ENOMEM;
}
dprintk(DBGLVL_FW, "Device has Firmware Version %d.%d.%d.%d\n",
(version & 0x0000fc00) >> 10,
(version & 0x000003e0) >> 5,
(version & 0x0000001f),
(version & 0xffff0000) >> 16);
/* Load the firmwware from the disk if required */
if (version == 0) {
printk(KERN_INFO "%s() Waiting for firmware upload (%s)\n",
__func__, fwname);
ret = request_firmware(&fw, fwname, &dev->pci->dev);
if (ret) {
printk(KERN_ERR "%s() Upload failed. "
"(file not found?)\n", __func__);
return -ENOMEM;
}
printk(KERN_INFO "%s() firmware read %Zu bytes.\n",
__func__, fw->size);
if (fw->size != fwlength) {
printk(KERN_ERR "xc5000: firmware incorrect size\n");
ret = -ENOMEM;
goto out;
}
printk(KERN_INFO "%s() firmware loaded.\n", __func__);
hdr = (struct fw_header *)fw->data;
printk(KERN_INFO "Firmware file header part 1:\n");
printk(KERN_INFO " .FirmwareSize = 0x%x\n", hdr->firmwaresize);
printk(KERN_INFO " .BSLSize = 0x%x\n", hdr->bslsize);
printk(KERN_INFO " .Reserved = 0x%x\n", hdr->reserved);
printk(KERN_INFO " .Version = 0x%x\n", hdr->version);
/* Retrieve bootloader if reqd */
if ((hdr->firmwaresize == 0) && (hdr->bslsize == 0))
/* Second bootloader in the firmware file */
filesize = hdr->reserved * 16;
else
filesize = (hdr->firmwaresize + hdr->bslsize) *
16 + sizeof(struct fw_header);
printk(KERN_INFO "%s() SecBootLoader.FileSize = %d\n",
__func__, filesize);
/* Get bootloader (if reqd) and firmware header */
if ((hdr->firmwaresize == 0) && (hdr->bslsize == 0)) {
/* Second boot loader is required */
/* Get the loader header */
boothdr = (struct fw_header *)(fw->data +
sizeof(struct fw_header));
bootloaderversion =
saa7164_readl(SAA_DEVICE_2ND_VERSION);
dprintk(DBGLVL_FW, "Onboard BootLoader:\n");
dprintk(DBGLVL_FW, "->Flag 0x%x\n",
saa7164_readl(SAA_BOOTLOADERERROR_FLAGS));
dprintk(DBGLVL_FW, "->Ack 0x%x\n",
saa7164_readl(SAA_DATAREADY_FLAG_ACK));
dprintk(DBGLVL_FW, "->FW Version 0x%x\n", version);
dprintk(DBGLVL_FW, "->Loader Version 0x%x\n",
bootloaderversion);
if ((saa7164_readl(SAA_BOOTLOADERERROR_FLAGS) ==
0x03) && (saa7164_readl(SAA_DATAREADY_FLAG_ACK)
== 0x00) && (version == 0x00)) {
dprintk(DBGLVL_FW, "BootLoader version in "
"rom %d.%d.%d.%d\n",
(bootloaderversion & 0x0000fc00) >> 10,
(bootloaderversion & 0x000003e0) >> 5,
(bootloaderversion & 0x0000001f),
(bootloaderversion & 0xffff0000) >> 16
);
dprintk(DBGLVL_FW, "BootLoader version "
"in file %d.%d.%d.%d\n",
(boothdr->version & 0x0000fc00) >> 10,
(boothdr->version & 0x000003e0) >> 5,
(boothdr->version & 0x0000001f),
(boothdr->version & 0xffff0000) >> 16
);
if (bootloaderversion == boothdr->version)
updatebootloader = 0;
}
/* Calculate offset to firmware header */
tmp = (boothdr->firmwaresize + boothdr->bslsize) * 16 +
(sizeof(struct fw_header) +
sizeof(struct fw_header));
fwhdr = (struct fw_header *)(fw->data+tmp);
} else {
/* No second boot loader */
fwhdr = hdr;
}
dprintk(DBGLVL_FW, "Firmware version in file %d.%d.%d.%d\n",
(fwhdr->version & 0x0000fc00) >> 10,
(fwhdr->version & 0x000003e0) >> 5,
(fwhdr->version & 0x0000001f),
(fwhdr->version & 0xffff0000) >> 16
);
if (version == fwhdr->version) {
/* No download, firmware already on board */
ret = 0;
goto out;
}
if ((hdr->firmwaresize == 0) && (hdr->bslsize == 0)) {
if (updatebootloader) {
/* Get ready to upload the bootloader */
bootloadersize = (boothdr->firmwaresize +
boothdr->bslsize) * 16 +
sizeof(struct fw_header);
bootloaderoffset = (u8 *)(fw->data +
sizeof(struct fw_header));
dprintk(DBGLVL_FW, "bootloader d/l starts.\n");
printk(KERN_INFO "%s() FirmwareSize = 0x%x\n",
__func__, boothdr->firmwaresize);
printk(KERN_INFO "%s() BSLSize = 0x%x\n",
__func__, boothdr->bslsize);
printk(KERN_INFO "%s() Reserved = 0x%x\n",
__func__, boothdr->reserved);
printk(KERN_INFO "%s() Version = 0x%x\n",
__func__, boothdr->version);
ret = saa7164_downloadimage(
dev,
bootloaderoffset,
bootloadersize,
SAA_DOWNLOAD_FLAGS,
dev->bmmio + SAA_DEVICE_DOWNLOAD_OFFSET,
SAA_DEVICE_BUFFERBLOCKSIZE);
if (ret < 0) {
printk(KERN_ERR
"bootloader d/l has failed\n");
goto out;
}
dprintk(DBGLVL_FW,
"bootloader download complete.\n");
}
printk(KERN_ERR "starting firmware download(2)\n");
bootloadersize = (boothdr->firmwaresize +
boothdr->bslsize) * 16 +
sizeof(struct fw_header);
bootloaderoffset =
(u8 *)(fw->data + sizeof(struct fw_header));
fwloaderoffset = bootloaderoffset + bootloadersize;
/* TODO: fix this bounds overrun here with old f/ws */
fwloadersize = (fwhdr->firmwaresize + fwhdr->bslsize) *
16 + sizeof(struct fw_header);
ret = saa7164_downloadimage(
dev,
fwloaderoffset,
fwloadersize,
SAA_DEVICE_2ND_DOWNLOADFLAG_OFFSET,
dev->bmmio + SAA_DEVICE_2ND_DOWNLOAD_OFFSET,
SAA_DEVICE_2ND_BUFFERBLOCKSIZE);
if (ret < 0) {
printk(KERN_ERR "firmware download failed\n");
goto out;
}
printk(KERN_ERR "firmware download complete.\n");
} else {
/* No bootloader update reqd, download firmware only */
printk(KERN_ERR "starting firmware download(3)\n");
ret = saa7164_downloadimage(
dev,
(u8 *)fw->data,
fw->size,
SAA_DOWNLOAD_FLAGS,
dev->bmmio + SAA_DEVICE_DOWNLOAD_OFFSET,
SAA_DEVICE_BUFFERBLOCKSIZE);
if (ret < 0) {
printk(KERN_ERR "firmware download failed\n");
goto out;
}
printk(KERN_ERR "firmware download complete.\n");
}
}
dev->firmwareloaded = 1;
ret = 0;
out:
release_firmware(fw);
return ret;
}
| gpl-2.0 |
victormlourenco/android_kernel_lge_msm8974 | drivers/misc/sgi-gru/grutlbpurge.c | 9451 | 12169 | /*
* SN Platform GRU Driver
*
* MMUOPS callbacks + TLB flushing
*
* This file handles emu notifier callbacks from the core kernel. The callbacks
* are used to update the TLB in the GRU as a result of changes in the
* state of a process address space. This file also handles TLB invalidates
* from the GRU driver.
*
* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/hugetlb.h>
#include <linux/delay.h>
#include <linux/timex.h>
#include <linux/srcu.h>
#include <asm/processor.h>
#include "gru.h"
#include "grutables.h"
#include <asm/uv/uv_hub.h>
#define gru_random() get_cycles()
/* ---------------------------------- TLB Invalidation functions --------
* get_tgh_handle
*
* Find a TGH to use for issuing a TLB invalidate. For GRUs that are on the
* local blade, use a fixed TGH that is a function of the blade-local cpu
* number. Normally, this TGH is private to the cpu & no contention occurs for
* the TGH. For offblade GRUs, select a random TGH in the range above the
* private TGHs. A spinlock is required to access this TGH & the lock must be
* released when the invalidate is completes. This sucks, but it is the best we
* can do.
*
* Note that the spinlock is IN the TGH handle so locking does not involve
* additional cache lines.
*
*/
static inline int get_off_blade_tgh(struct gru_state *gru)
{
int n;
n = GRU_NUM_TGH - gru->gs_tgh_first_remote;
n = gru_random() % n;
n += gru->gs_tgh_first_remote;
return n;
}
static inline int get_on_blade_tgh(struct gru_state *gru)
{
return uv_blade_processor_id() >> gru->gs_tgh_local_shift;
}
static struct gru_tlb_global_handle *get_lock_tgh_handle(struct gru_state
*gru)
{
struct gru_tlb_global_handle *tgh;
int n;
preempt_disable();
if (uv_numa_blade_id() == gru->gs_blade_id)
n = get_on_blade_tgh(gru);
else
n = get_off_blade_tgh(gru);
tgh = get_tgh_by_index(gru, n);
lock_tgh_handle(tgh);
return tgh;
}
static void get_unlock_tgh_handle(struct gru_tlb_global_handle *tgh)
{
unlock_tgh_handle(tgh);
preempt_enable();
}
/*
* gru_flush_tlb_range
*
* General purpose TLB invalidation function. This function scans every GRU in
* the ENTIRE system (partition) looking for GRUs where the specified MM has
* been accessed by the GRU. For each GRU found, the TLB must be invalidated OR
* the ASID invalidated. Invalidating an ASID causes a new ASID to be assigned
* on the next fault. This effectively flushes the ENTIRE TLB for the MM at the
* cost of (possibly) a large number of future TLBmisses.
*
* The current algorithm is optimized based on the following (somewhat true)
* assumptions:
* - GRU contexts are not loaded into a GRU unless a reference is made to
* the data segment or control block (this is true, not an assumption).
* If a DS/CB is referenced, the user will also issue instructions that
* cause TLBmisses. It is not necessary to optimize for the case where
* contexts are loaded but no instructions cause TLB misses. (I know
* this will happen but I'm not optimizing for it).
* - GRU instructions to invalidate TLB entries are SLOOOOWWW - normally
* a few usec but in unusual cases, it could be longer. Avoid if
* possible.
* - intrablade process migration between cpus is not frequent but is
* common.
* - a GRU context is not typically migrated to a different GRU on the
* blade because of intrablade migration
* - interblade migration is rare. Processes migrate their GRU context to
* the new blade.
* - if interblade migration occurs, migration back to the original blade
* is very very rare (ie., no optimization for this case)
* - most GRU instruction operate on a subset of the user REGIONS. Code
* & shared library regions are not likely targets of GRU instructions.
*
* To help improve the efficiency of TLB invalidation, the GMS data
* structure is maintained for EACH address space (MM struct). The GMS is
* also the structure that contains the pointer to the mmu callout
* functions. This structure is linked to the mm_struct for the address space
* using the mmu "register" function. The mmu interfaces are used to
* provide the callbacks for TLB invalidation. The GMS contains:
*
* - asid[maxgrus] array. ASIDs are assigned to a GRU when a context is
* loaded into the GRU.
* - asidmap[maxgrus]. bitmap to make it easier to find non-zero asids in
* the above array
* - ctxbitmap[maxgrus]. Indicates the contexts that are currently active
* in the GRU for the address space. This bitmap must be passed to the
* GRU to do an invalidate.
*
* The current algorithm for invalidating TLBs is:
* - scan the asidmap for GRUs where the context has been loaded, ie,
* asid is non-zero.
* - for each gru found:
* - if the ctxtmap is non-zero, there are active contexts in the
* GRU. TLB invalidate instructions must be issued to the GRU.
* - if the ctxtmap is zero, no context is active. Set the ASID to
* zero to force a full TLB invalidation. This is fast but will
* cause a lot of TLB misses if the context is reloaded onto the
* GRU
*
*/
void gru_flush_tlb_range(struct gru_mm_struct *gms, unsigned long start,
unsigned long len)
{
struct gru_state *gru;
struct gru_mm_tracker *asids;
struct gru_tlb_global_handle *tgh;
unsigned long num;
int grupagesize, pagesize, pageshift, gid, asid;
/* ZZZ TODO - handle huge pages */
pageshift = PAGE_SHIFT;
pagesize = (1UL << pageshift);
grupagesize = GRU_PAGESIZE(pageshift);
num = min(((len + pagesize - 1) >> pageshift), GRUMAXINVAL);
STAT(flush_tlb);
gru_dbg(grudev, "gms %p, start 0x%lx, len 0x%lx, asidmap 0x%lx\n", gms,
start, len, gms->ms_asidmap[0]);
spin_lock(&gms->ms_asid_lock);
for_each_gru_in_bitmap(gid, gms->ms_asidmap) {
STAT(flush_tlb_gru);
gru = GID_TO_GRU(gid);
asids = gms->ms_asids + gid;
asid = asids->mt_asid;
if (asids->mt_ctxbitmap && asid) {
STAT(flush_tlb_gru_tgh);
asid = GRUASID(asid, start);
gru_dbg(grudev,
" FLUSH gruid %d, asid 0x%x, vaddr 0x%lx, vamask 0x%x, num %ld, cbmap 0x%x\n",
gid, asid, start, grupagesize, num, asids->mt_ctxbitmap);
tgh = get_lock_tgh_handle(gru);
tgh_invalidate(tgh, start, ~0, asid, grupagesize, 0,
num - 1, asids->mt_ctxbitmap);
get_unlock_tgh_handle(tgh);
} else {
STAT(flush_tlb_gru_zero_asid);
asids->mt_asid = 0;
__clear_bit(gru->gs_gid, gms->ms_asidmap);
gru_dbg(grudev,
" CLEARASID gruid %d, asid 0x%x, cbtmap 0x%x, asidmap 0x%lx\n",
gid, asid, asids->mt_ctxbitmap,
gms->ms_asidmap[0]);
}
}
spin_unlock(&gms->ms_asid_lock);
}
/*
* Flush the entire TLB on a chiplet.
*/
void gru_flush_all_tlb(struct gru_state *gru)
{
struct gru_tlb_global_handle *tgh;
gru_dbg(grudev, "gid %d\n", gru->gs_gid);
tgh = get_lock_tgh_handle(gru);
tgh_invalidate(tgh, 0, ~0, 0, 1, 1, GRUMAXINVAL - 1, 0xffff);
get_unlock_tgh_handle(tgh);
}
/*
* MMUOPS notifier callout functions
*/
static void gru_invalidate_range_start(struct mmu_notifier *mn,
struct mm_struct *mm,
unsigned long start, unsigned long end)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
STAT(mmu_invalidate_range);
atomic_inc(&gms->ms_range_active);
gru_dbg(grudev, "gms %p, start 0x%lx, end 0x%lx, act %d\n", gms,
start, end, atomic_read(&gms->ms_range_active));
gru_flush_tlb_range(gms, start, end - start);
}
static void gru_invalidate_range_end(struct mmu_notifier *mn,
struct mm_struct *mm, unsigned long start,
unsigned long end)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
/* ..._and_test() provides needed barrier */
(void)atomic_dec_and_test(&gms->ms_range_active);
wake_up_all(&gms->ms_wait_queue);
gru_dbg(grudev, "gms %p, start 0x%lx, end 0x%lx\n", gms, start, end);
}
static void gru_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm,
unsigned long address)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
STAT(mmu_invalidate_page);
gru_flush_tlb_range(gms, address, PAGE_SIZE);
gru_dbg(grudev, "gms %p, address 0x%lx\n", gms, address);
}
static void gru_release(struct mmu_notifier *mn, struct mm_struct *mm)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
gms->ms_released = 1;
gru_dbg(grudev, "gms %p\n", gms);
}
static const struct mmu_notifier_ops gru_mmuops = {
.invalidate_page = gru_invalidate_page,
.invalidate_range_start = gru_invalidate_range_start,
.invalidate_range_end = gru_invalidate_range_end,
.release = gru_release,
};
/* Move this to the basic mmu_notifier file. But for now... */
static struct mmu_notifier *mmu_find_ops(struct mm_struct *mm,
const struct mmu_notifier_ops *ops)
{
struct mmu_notifier *mn, *gru_mn = NULL;
struct hlist_node *n;
if (mm->mmu_notifier_mm) {
rcu_read_lock();
hlist_for_each_entry_rcu(mn, n, &mm->mmu_notifier_mm->list,
hlist)
if (mn->ops == ops) {
gru_mn = mn;
break;
}
rcu_read_unlock();
}
return gru_mn;
}
struct gru_mm_struct *gru_register_mmu_notifier(void)
{
struct gru_mm_struct *gms;
struct mmu_notifier *mn;
int err;
mn = mmu_find_ops(current->mm, &gru_mmuops);
if (mn) {
gms = container_of(mn, struct gru_mm_struct, ms_notifier);
atomic_inc(&gms->ms_refcnt);
} else {
gms = kzalloc(sizeof(*gms), GFP_KERNEL);
if (gms) {
STAT(gms_alloc);
spin_lock_init(&gms->ms_asid_lock);
gms->ms_notifier.ops = &gru_mmuops;
atomic_set(&gms->ms_refcnt, 1);
init_waitqueue_head(&gms->ms_wait_queue);
err = __mmu_notifier_register(&gms->ms_notifier, current->mm);
if (err)
goto error;
}
}
gru_dbg(grudev, "gms %p, refcnt %d\n", gms,
atomic_read(&gms->ms_refcnt));
return gms;
error:
kfree(gms);
return ERR_PTR(err);
}
void gru_drop_mmu_notifier(struct gru_mm_struct *gms)
{
gru_dbg(grudev, "gms %p, refcnt %d, released %d\n", gms,
atomic_read(&gms->ms_refcnt), gms->ms_released);
if (atomic_dec_return(&gms->ms_refcnt) == 0) {
if (!gms->ms_released)
mmu_notifier_unregister(&gms->ms_notifier, current->mm);
kfree(gms);
STAT(gms_free);
}
}
/*
* Setup TGH parameters. There are:
* - 24 TGH handles per GRU chiplet
* - a portion (MAX_LOCAL_TGH) of the handles are reserved for
* use by blade-local cpus
* - the rest are used by off-blade cpus. This usage is
* less frequent than blade-local usage.
*
* For now, use 16 handles for local flushes, 8 for remote flushes. If the blade
* has less tan or equal to 16 cpus, each cpu has a unique handle that it can
* use.
*/
#define MAX_LOCAL_TGH 16
void gru_tgh_flush_init(struct gru_state *gru)
{
int cpus, shift = 0, n;
cpus = uv_blade_nr_possible_cpus(gru->gs_blade_id);
/* n = cpus rounded up to next power of 2 */
if (cpus) {
n = 1 << fls(cpus - 1);
/*
* shift count for converting local cpu# to TGH index
* 0 if cpus <= MAX_LOCAL_TGH,
* 1 if cpus <= 2*MAX_LOCAL_TGH,
* etc
*/
shift = max(0, fls(n - 1) - fls(MAX_LOCAL_TGH - 1));
}
gru->gs_tgh_local_shift = shift;
/* first starting TGH index to use for remote purges */
gru->gs_tgh_first_remote = (cpus + (1 << shift) - 1) >> shift;
}
| gpl-2.0 |
Blechd0se/grouper_kernel | drivers/misc/sgi-gru/grutlbpurge.c | 9451 | 12169 | /*
* SN Platform GRU Driver
*
* MMUOPS callbacks + TLB flushing
*
* This file handles emu notifier callbacks from the core kernel. The callbacks
* are used to update the TLB in the GRU as a result of changes in the
* state of a process address space. This file also handles TLB invalidates
* from the GRU driver.
*
* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/hugetlb.h>
#include <linux/delay.h>
#include <linux/timex.h>
#include <linux/srcu.h>
#include <asm/processor.h>
#include "gru.h"
#include "grutables.h"
#include <asm/uv/uv_hub.h>
#define gru_random() get_cycles()
/* ---------------------------------- TLB Invalidation functions --------
* get_tgh_handle
*
* Find a TGH to use for issuing a TLB invalidate. For GRUs that are on the
* local blade, use a fixed TGH that is a function of the blade-local cpu
* number. Normally, this TGH is private to the cpu & no contention occurs for
* the TGH. For offblade GRUs, select a random TGH in the range above the
* private TGHs. A spinlock is required to access this TGH & the lock must be
* released when the invalidate is completes. This sucks, but it is the best we
* can do.
*
* Note that the spinlock is IN the TGH handle so locking does not involve
* additional cache lines.
*
*/
static inline int get_off_blade_tgh(struct gru_state *gru)
{
int n;
n = GRU_NUM_TGH - gru->gs_tgh_first_remote;
n = gru_random() % n;
n += gru->gs_tgh_first_remote;
return n;
}
static inline int get_on_blade_tgh(struct gru_state *gru)
{
return uv_blade_processor_id() >> gru->gs_tgh_local_shift;
}
static struct gru_tlb_global_handle *get_lock_tgh_handle(struct gru_state
*gru)
{
struct gru_tlb_global_handle *tgh;
int n;
preempt_disable();
if (uv_numa_blade_id() == gru->gs_blade_id)
n = get_on_blade_tgh(gru);
else
n = get_off_blade_tgh(gru);
tgh = get_tgh_by_index(gru, n);
lock_tgh_handle(tgh);
return tgh;
}
static void get_unlock_tgh_handle(struct gru_tlb_global_handle *tgh)
{
unlock_tgh_handle(tgh);
preempt_enable();
}
/*
* gru_flush_tlb_range
*
* General purpose TLB invalidation function. This function scans every GRU in
* the ENTIRE system (partition) looking for GRUs where the specified MM has
* been accessed by the GRU. For each GRU found, the TLB must be invalidated OR
* the ASID invalidated. Invalidating an ASID causes a new ASID to be assigned
* on the next fault. This effectively flushes the ENTIRE TLB for the MM at the
* cost of (possibly) a large number of future TLBmisses.
*
* The current algorithm is optimized based on the following (somewhat true)
* assumptions:
* - GRU contexts are not loaded into a GRU unless a reference is made to
* the data segment or control block (this is true, not an assumption).
* If a DS/CB is referenced, the user will also issue instructions that
* cause TLBmisses. It is not necessary to optimize for the case where
* contexts are loaded but no instructions cause TLB misses. (I know
* this will happen but I'm not optimizing for it).
* - GRU instructions to invalidate TLB entries are SLOOOOWWW - normally
* a few usec but in unusual cases, it could be longer. Avoid if
* possible.
* - intrablade process migration between cpus is not frequent but is
* common.
* - a GRU context is not typically migrated to a different GRU on the
* blade because of intrablade migration
* - interblade migration is rare. Processes migrate their GRU context to
* the new blade.
* - if interblade migration occurs, migration back to the original blade
* is very very rare (ie., no optimization for this case)
* - most GRU instruction operate on a subset of the user REGIONS. Code
* & shared library regions are not likely targets of GRU instructions.
*
* To help improve the efficiency of TLB invalidation, the GMS data
* structure is maintained for EACH address space (MM struct). The GMS is
* also the structure that contains the pointer to the mmu callout
* functions. This structure is linked to the mm_struct for the address space
* using the mmu "register" function. The mmu interfaces are used to
* provide the callbacks for TLB invalidation. The GMS contains:
*
* - asid[maxgrus] array. ASIDs are assigned to a GRU when a context is
* loaded into the GRU.
* - asidmap[maxgrus]. bitmap to make it easier to find non-zero asids in
* the above array
* - ctxbitmap[maxgrus]. Indicates the contexts that are currently active
* in the GRU for the address space. This bitmap must be passed to the
* GRU to do an invalidate.
*
* The current algorithm for invalidating TLBs is:
* - scan the asidmap for GRUs where the context has been loaded, ie,
* asid is non-zero.
* - for each gru found:
* - if the ctxtmap is non-zero, there are active contexts in the
* GRU. TLB invalidate instructions must be issued to the GRU.
* - if the ctxtmap is zero, no context is active. Set the ASID to
* zero to force a full TLB invalidation. This is fast but will
* cause a lot of TLB misses if the context is reloaded onto the
* GRU
*
*/
void gru_flush_tlb_range(struct gru_mm_struct *gms, unsigned long start,
unsigned long len)
{
struct gru_state *gru;
struct gru_mm_tracker *asids;
struct gru_tlb_global_handle *tgh;
unsigned long num;
int grupagesize, pagesize, pageshift, gid, asid;
/* ZZZ TODO - handle huge pages */
pageshift = PAGE_SHIFT;
pagesize = (1UL << pageshift);
grupagesize = GRU_PAGESIZE(pageshift);
num = min(((len + pagesize - 1) >> pageshift), GRUMAXINVAL);
STAT(flush_tlb);
gru_dbg(grudev, "gms %p, start 0x%lx, len 0x%lx, asidmap 0x%lx\n", gms,
start, len, gms->ms_asidmap[0]);
spin_lock(&gms->ms_asid_lock);
for_each_gru_in_bitmap(gid, gms->ms_asidmap) {
STAT(flush_tlb_gru);
gru = GID_TO_GRU(gid);
asids = gms->ms_asids + gid;
asid = asids->mt_asid;
if (asids->mt_ctxbitmap && asid) {
STAT(flush_tlb_gru_tgh);
asid = GRUASID(asid, start);
gru_dbg(grudev,
" FLUSH gruid %d, asid 0x%x, vaddr 0x%lx, vamask 0x%x, num %ld, cbmap 0x%x\n",
gid, asid, start, grupagesize, num, asids->mt_ctxbitmap);
tgh = get_lock_tgh_handle(gru);
tgh_invalidate(tgh, start, ~0, asid, grupagesize, 0,
num - 1, asids->mt_ctxbitmap);
get_unlock_tgh_handle(tgh);
} else {
STAT(flush_tlb_gru_zero_asid);
asids->mt_asid = 0;
__clear_bit(gru->gs_gid, gms->ms_asidmap);
gru_dbg(grudev,
" CLEARASID gruid %d, asid 0x%x, cbtmap 0x%x, asidmap 0x%lx\n",
gid, asid, asids->mt_ctxbitmap,
gms->ms_asidmap[0]);
}
}
spin_unlock(&gms->ms_asid_lock);
}
/*
* Flush the entire TLB on a chiplet.
*/
void gru_flush_all_tlb(struct gru_state *gru)
{
struct gru_tlb_global_handle *tgh;
gru_dbg(grudev, "gid %d\n", gru->gs_gid);
tgh = get_lock_tgh_handle(gru);
tgh_invalidate(tgh, 0, ~0, 0, 1, 1, GRUMAXINVAL - 1, 0xffff);
get_unlock_tgh_handle(tgh);
}
/*
* MMUOPS notifier callout functions
*/
static void gru_invalidate_range_start(struct mmu_notifier *mn,
struct mm_struct *mm,
unsigned long start, unsigned long end)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
STAT(mmu_invalidate_range);
atomic_inc(&gms->ms_range_active);
gru_dbg(grudev, "gms %p, start 0x%lx, end 0x%lx, act %d\n", gms,
start, end, atomic_read(&gms->ms_range_active));
gru_flush_tlb_range(gms, start, end - start);
}
static void gru_invalidate_range_end(struct mmu_notifier *mn,
struct mm_struct *mm, unsigned long start,
unsigned long end)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
/* ..._and_test() provides needed barrier */
(void)atomic_dec_and_test(&gms->ms_range_active);
wake_up_all(&gms->ms_wait_queue);
gru_dbg(grudev, "gms %p, start 0x%lx, end 0x%lx\n", gms, start, end);
}
static void gru_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm,
unsigned long address)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
STAT(mmu_invalidate_page);
gru_flush_tlb_range(gms, address, PAGE_SIZE);
gru_dbg(grudev, "gms %p, address 0x%lx\n", gms, address);
}
static void gru_release(struct mmu_notifier *mn, struct mm_struct *mm)
{
struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
ms_notifier);
gms->ms_released = 1;
gru_dbg(grudev, "gms %p\n", gms);
}
static const struct mmu_notifier_ops gru_mmuops = {
.invalidate_page = gru_invalidate_page,
.invalidate_range_start = gru_invalidate_range_start,
.invalidate_range_end = gru_invalidate_range_end,
.release = gru_release,
};
/* Move this to the basic mmu_notifier file. But for now... */
static struct mmu_notifier *mmu_find_ops(struct mm_struct *mm,
const struct mmu_notifier_ops *ops)
{
struct mmu_notifier *mn, *gru_mn = NULL;
struct hlist_node *n;
if (mm->mmu_notifier_mm) {
rcu_read_lock();
hlist_for_each_entry_rcu(mn, n, &mm->mmu_notifier_mm->list,
hlist)
if (mn->ops == ops) {
gru_mn = mn;
break;
}
rcu_read_unlock();
}
return gru_mn;
}
struct gru_mm_struct *gru_register_mmu_notifier(void)
{
struct gru_mm_struct *gms;
struct mmu_notifier *mn;
int err;
mn = mmu_find_ops(current->mm, &gru_mmuops);
if (mn) {
gms = container_of(mn, struct gru_mm_struct, ms_notifier);
atomic_inc(&gms->ms_refcnt);
} else {
gms = kzalloc(sizeof(*gms), GFP_KERNEL);
if (gms) {
STAT(gms_alloc);
spin_lock_init(&gms->ms_asid_lock);
gms->ms_notifier.ops = &gru_mmuops;
atomic_set(&gms->ms_refcnt, 1);
init_waitqueue_head(&gms->ms_wait_queue);
err = __mmu_notifier_register(&gms->ms_notifier, current->mm);
if (err)
goto error;
}
}
gru_dbg(grudev, "gms %p, refcnt %d\n", gms,
atomic_read(&gms->ms_refcnt));
return gms;
error:
kfree(gms);
return ERR_PTR(err);
}
void gru_drop_mmu_notifier(struct gru_mm_struct *gms)
{
gru_dbg(grudev, "gms %p, refcnt %d, released %d\n", gms,
atomic_read(&gms->ms_refcnt), gms->ms_released);
if (atomic_dec_return(&gms->ms_refcnt) == 0) {
if (!gms->ms_released)
mmu_notifier_unregister(&gms->ms_notifier, current->mm);
kfree(gms);
STAT(gms_free);
}
}
/*
* Setup TGH parameters. There are:
* - 24 TGH handles per GRU chiplet
* - a portion (MAX_LOCAL_TGH) of the handles are reserved for
* use by blade-local cpus
* - the rest are used by off-blade cpus. This usage is
* less frequent than blade-local usage.
*
* For now, use 16 handles for local flushes, 8 for remote flushes. If the blade
* has less tan or equal to 16 cpus, each cpu has a unique handle that it can
* use.
*/
#define MAX_LOCAL_TGH 16
void gru_tgh_flush_init(struct gru_state *gru)
{
int cpus, shift = 0, n;
cpus = uv_blade_nr_possible_cpus(gru->gs_blade_id);
/* n = cpus rounded up to next power of 2 */
if (cpus) {
n = 1 << fls(cpus - 1);
/*
* shift count for converting local cpu# to TGH index
* 0 if cpus <= MAX_LOCAL_TGH,
* 1 if cpus <= 2*MAX_LOCAL_TGH,
* etc
*/
shift = max(0, fls(n - 1) - fls(MAX_LOCAL_TGH - 1));
}
gru->gs_tgh_local_shift = shift;
/* first starting TGH index to use for remote purges */
gru->gs_tgh_first_remote = (cpus + (1 << shift) - 1) >> shift;
}
| gpl-2.0 |
dan-htc-touch/kernel_samsung_hlte | drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_n.c | 10219 | 135101 | /*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <types.h>
#include "phytbl_n.h"
static const u32 frame_struct_rev0[] = {
0x08004a04,
0x00100000,
0x01000a05,
0x00100020,
0x09804506,
0x00100030,
0x09804507,
0x00100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a0c,
0x00100004,
0x01000a0d,
0x00100024,
0x0980450e,
0x00100034,
0x0980450f,
0x00100034,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a04,
0x00100000,
0x11008a05,
0x00100020,
0x1980c506,
0x00100030,
0x21810506,
0x00100030,
0x21810506,
0x00100030,
0x01800504,
0x00100030,
0x11808505,
0x00100030,
0x29814507,
0x01100030,
0x00000a04,
0x00100000,
0x11008a05,
0x00100020,
0x21810506,
0x00100030,
0x21810506,
0x00100030,
0x29814507,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a0c,
0x00100008,
0x11008a0d,
0x00100028,
0x1980c50e,
0x00100038,
0x2181050e,
0x00100038,
0x2181050e,
0x00100038,
0x0180050c,
0x00100038,
0x1180850d,
0x00100038,
0x2981450f,
0x01100038,
0x00000a0c,
0x00100008,
0x11008a0d,
0x00100028,
0x2181050e,
0x00100038,
0x2181050e,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a04,
0x00100000,
0x01000a05,
0x00100020,
0x1980c506,
0x00100030,
0x1980c506,
0x00100030,
0x11808504,
0x00100030,
0x3981ca05,
0x00100030,
0x29814507,
0x01100030,
0x00000000,
0x00000000,
0x10008a04,
0x00100000,
0x3981ca05,
0x00100030,
0x1980c506,
0x00100030,
0x29814507,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a0c,
0x00100008,
0x01000a0d,
0x00100028,
0x1980c50e,
0x00100038,
0x1980c50e,
0x00100038,
0x1180850c,
0x00100038,
0x3981ca0d,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x10008a0c,
0x00100008,
0x3981ca0d,
0x00100038,
0x1980c50e,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x00100000,
0x02001405,
0x00100040,
0x0b004a06,
0x01900060,
0x13008a06,
0x01900060,
0x13008a06,
0x01900060,
0x43020a04,
0x00100060,
0x1b00ca05,
0x00100060,
0x23010a07,
0x01500060,
0x40021404,
0x00100000,
0x1a00d405,
0x00100040,
0x13008a06,
0x01900060,
0x13008a06,
0x01900060,
0x23010a07,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x0200140d,
0x00100050,
0x0b004a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x43020a0c,
0x00100070,
0x1b00ca0d,
0x00100070,
0x23010a0f,
0x01500070,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x13008a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x50029404,
0x00100000,
0x32019405,
0x00100040,
0x0b004a06,
0x01900060,
0x0b004a06,
0x01900060,
0x5b02ca04,
0x00100060,
0x3b01d405,
0x00100060,
0x23010a07,
0x01500060,
0x00000000,
0x00000000,
0x5802d404,
0x00100000,
0x3b01d405,
0x00100060,
0x0b004a06,
0x01900060,
0x23010a07,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x5002940c,
0x00100010,
0x3201940d,
0x00100050,
0x0b004a0e,
0x01900070,
0x0b004a0e,
0x01900070,
0x5b02ca0c,
0x00100070,
0x3b01d40d,
0x00100070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x5802d40c,
0x00100010,
0x3b01d40d,
0x00100070,
0x0b004a0e,
0x01900070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x000f4800,
0x62031405,
0x00100040,
0x53028a06,
0x01900060,
0x53028a07,
0x01900060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x000f4808,
0x6203140d,
0x00100048,
0x53028a0e,
0x01900068,
0x53028a0f,
0x01900068,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a0c,
0x00100004,
0x11008a0d,
0x00100024,
0x1980c50e,
0x00100034,
0x2181050e,
0x00100034,
0x2181050e,
0x00100034,
0x0180050c,
0x00100038,
0x1180850d,
0x00100038,
0x1181850d,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a0c,
0x00100008,
0x11008a0d,
0x00100028,
0x2181050e,
0x00100038,
0x2181050e,
0x00100038,
0x1181850d,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a04,
0x00100000,
0x01000a05,
0x00100020,
0x0180c506,
0x00100030,
0x0180c506,
0x00100030,
0x2180c50c,
0x00100030,
0x49820a0d,
0x0016a130,
0x41824a0d,
0x0016a130,
0x2981450f,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x2000ca0c,
0x00100000,
0x49820a0d,
0x0016a130,
0x1980c50e,
0x00100030,
0x41824a0d,
0x0016a130,
0x2981450f,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100008,
0x0200140d,
0x00100048,
0x0b004a0e,
0x01900068,
0x13008a0e,
0x01900068,
0x13008a0e,
0x01900068,
0x43020a0c,
0x00100070,
0x1b00ca0d,
0x00100070,
0x1b014a0d,
0x00100070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x13008a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x1b014a0d,
0x00100070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x50029404,
0x00100000,
0x32019405,
0x00100040,
0x03004a06,
0x01900060,
0x03004a06,
0x01900060,
0x6b030a0c,
0x00100060,
0x4b02140d,
0x0016a160,
0x4302540d,
0x0016a160,
0x23010a0f,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x6b03140c,
0x00100060,
0x4b02140d,
0x0016a160,
0x0b004a0e,
0x01900060,
0x4302540d,
0x0016a160,
0x23010a0f,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x00100000,
0x1a00d405,
0x00100040,
0x53028a06,
0x01900060,
0x5b02ca06,
0x01900060,
0x5b02ca06,
0x01900060,
0x43020a04,
0x00100060,
0x1b00ca05,
0x00100060,
0x53028a07,
0x0190c060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x53028a0e,
0x01900070,
0x5b02ca0e,
0x01900070,
0x5b02ca0e,
0x01900070,
0x43020a0c,
0x00100070,
0x1b00ca0d,
0x00100070,
0x53028a0f,
0x0190c070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x00100000,
0x1a00d405,
0x00100040,
0x5b02ca06,
0x01900060,
0x5b02ca06,
0x01900060,
0x53028a07,
0x0190c060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x5b02ca0e,
0x01900070,
0x5b02ca0e,
0x01900070,
0x53028a0f,
0x0190c070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u8 frame_lut_rev0[] = {
0x02,
0x04,
0x14,
0x14,
0x03,
0x05,
0x16,
0x16,
0x0a,
0x0c,
0x1c,
0x1c,
0x0b,
0x0d,
0x1e,
0x1e,
0x06,
0x08,
0x18,
0x18,
0x07,
0x09,
0x1a,
0x1a,
0x0e,
0x10,
0x20,
0x28,
0x0f,
0x11,
0x22,
0x2a,
};
static const u32 tmap_tbl_rev0[] = {
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0xf1111110,
0x11111111,
0x11f11111,
0x00000111,
0x11000000,
0x1111f111,
0x11111111,
0x111111f1,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x000aa888,
0x88880000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa2222220,
0x22222222,
0x22c22222,
0x00000222,
0x22000000,
0x2222a222,
0x22222222,
0x222222a2,
0xf1111110,
0x11111111,
0x11f11111,
0x00011111,
0x11110000,
0x1111f111,
0x11111111,
0x111111f1,
0xa8aa88a0,
0xa88888a8,
0xa8a8a88a,
0x00088aaa,
0xaaaa0000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xaaa8aaa0,
0x8aaa8aaa,
0xaa8a8a8a,
0x000aaa88,
0x8aaa0000,
0xaaa8a888,
0x8aa88a8a,
0x8a88a888,
0x08080a00,
0x0a08080a,
0x080a0a08,
0x00080808,
0x080a0000,
0x080a0808,
0x080a0808,
0x0a0a0a08,
0xa0a0a0a0,
0x80a0a080,
0x8080a0a0,
0x00008080,
0x80a00000,
0x80a080a0,
0xa080a0a0,
0x8080a0a0,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x99999000,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb90,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00aaa888,
0x22000000,
0x2222b222,
0x22222222,
0x222222b2,
0xb2222220,
0x22222222,
0x22d22222,
0x00000222,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x33000000,
0x3333b333,
0x33333333,
0x333333b3,
0xb3333330,
0x33333333,
0x33d33333,
0x00000333,
0x22000000,
0x2222a222,
0x22222222,
0x222222a2,
0xa2222220,
0x22222222,
0x22c22222,
0x00000222,
0x99b99b00,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb99,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x08aaa888,
0x22222200,
0x2222f222,
0x22222222,
0x222222f2,
0x22222222,
0x22222222,
0x22f22222,
0x00000222,
0x11000000,
0x1111f111,
0x11111111,
0x11111111,
0xf1111111,
0x11111111,
0x11f11111,
0x01111111,
0xbb9bb900,
0xb9b9bb99,
0xb99bbbbb,
0xbbbb9b9b,
0xb9bb99bb,
0xb99999b9,
0xb9b9b99b,
0x00000bbb,
0xaa000000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xa8aa88aa,
0xa88888a8,
0xa8a8a88a,
0x0a888aaa,
0xaa000000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xa8aa88a0,
0xa88888a8,
0xa8a8a88a,
0x00000aaa,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0xbbbbbb00,
0x999bbbbb,
0x9bb99b9b,
0xb9b9b9bb,
0xb9b99bbb,
0xb9b9b9bb,
0xb9bb9b99,
0x00000999,
0x8a000000,
0xaa88a888,
0xa88888aa,
0xa88a8a88,
0xa88aa88a,
0x88a8aaaa,
0xa8aa8aaa,
0x0888a88a,
0x0b0b0b00,
0x090b0b0b,
0x0b090b0b,
0x0909090b,
0x09090b0b,
0x09090b0b,
0x09090b09,
0x00000909,
0x0a000000,
0x0a080808,
0x080a080a,
0x080a0a08,
0x080a080a,
0x0808080a,
0x0a0a0a08,
0x0808080a,
0xb0b0b000,
0x9090b0b0,
0x90b09090,
0xb0b0b090,
0xb0b090b0,
0x90b0b0b0,
0xb0b09090,
0x00000090,
0x80000000,
0xa080a080,
0xa08080a0,
0xa0808080,
0xa080a080,
0x80a0a0a0,
0xa0a080a0,
0x00a0a0a0,
0x22000000,
0x2222f222,
0x22222222,
0x222222f2,
0xf2222220,
0x22222222,
0x22f22222,
0x00000222,
0x11000000,
0x1111f111,
0x11111111,
0x111111f1,
0xf1111110,
0x11111111,
0x11f11111,
0x00000111,
0x33000000,
0x3333f333,
0x33333333,
0x333333f3,
0xf3333330,
0x33333333,
0x33f33333,
0x00000333,
0x22000000,
0x2222f222,
0x22222222,
0x222222f2,
0xf2222220,
0x22222222,
0x22f22222,
0x00000222,
0x99000000,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb90,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88888000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00aaa888,
0x88a88a00,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x08aaa888,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 tdtrn_tbl_rev0[] = {
0x061c061c,
0x0050ee68,
0xf592fe36,
0xfe5212f6,
0x00000c38,
0xfe5212f6,
0xf592fe36,
0x0050ee68,
0x061c061c,
0xee680050,
0xfe36f592,
0x12f6fe52,
0x0c380000,
0x12f6fe52,
0xfe36f592,
0xee680050,
0x061c061c,
0x0050ee68,
0xf592fe36,
0xfe5212f6,
0x00000c38,
0xfe5212f6,
0xf592fe36,
0x0050ee68,
0x061c061c,
0xee680050,
0xfe36f592,
0x12f6fe52,
0x0c380000,
0x12f6fe52,
0xfe36f592,
0xee680050,
0x05e305e3,
0x004def0c,
0xf5f3fe47,
0xfe611246,
0x00000bc7,
0xfe611246,
0xf5f3fe47,
0x004def0c,
0x05e305e3,
0xef0c004d,
0xfe47f5f3,
0x1246fe61,
0x0bc70000,
0x1246fe61,
0xfe47f5f3,
0xef0c004d,
0x05e305e3,
0x004def0c,
0xf5f3fe47,
0xfe611246,
0x00000bc7,
0xfe611246,
0xf5f3fe47,
0x004def0c,
0x05e305e3,
0xef0c004d,
0xfe47f5f3,
0x1246fe61,
0x0bc70000,
0x1246fe61,
0xfe47f5f3,
0xef0c004d,
0xfa58fa58,
0xf895043b,
0xff4c09c0,
0xfbc6ffa8,
0xfb84f384,
0x0798f6f9,
0x05760122,
0x058409f6,
0x0b500000,
0x05b7f542,
0x08860432,
0x06ddfee7,
0xfb84f384,
0xf9d90664,
0xf7e8025c,
0x00fff7bd,
0x05a805a8,
0xf7bd00ff,
0x025cf7e8,
0x0664f9d9,
0xf384fb84,
0xfee706dd,
0x04320886,
0xf54205b7,
0x00000b50,
0x09f60584,
0x01220576,
0xf6f90798,
0xf384fb84,
0xffa8fbc6,
0x09c0ff4c,
0x043bf895,
0x02d402d4,
0x07de0270,
0xfc96079c,
0xf90afe94,
0xfe00ff2c,
0x02d4065d,
0x092a0096,
0x0014fbb8,
0xfd2cfd2c,
0x076afb3c,
0x0096f752,
0xf991fd87,
0xfb2c0200,
0xfeb8f960,
0x08e0fc96,
0x049802a8,
0xfd2cfd2c,
0x02a80498,
0xfc9608e0,
0xf960feb8,
0x0200fb2c,
0xfd87f991,
0xf7520096,
0xfb3c076a,
0xfd2cfd2c,
0xfbb80014,
0x0096092a,
0x065d02d4,
0xff2cfe00,
0xfe94f90a,
0x079cfc96,
0x027007de,
0x02d402d4,
0x027007de,
0x079cfc96,
0xfe94f90a,
0xff2cfe00,
0x065d02d4,
0x0096092a,
0xfbb80014,
0xfd2cfd2c,
0xfb3c076a,
0xf7520096,
0xfd87f991,
0x0200fb2c,
0xf960feb8,
0xfc9608e0,
0x02a80498,
0xfd2cfd2c,
0x049802a8,
0x08e0fc96,
0xfeb8f960,
0xfb2c0200,
0xf991fd87,
0x0096f752,
0x076afb3c,
0xfd2cfd2c,
0x0014fbb8,
0x092a0096,
0x02d4065d,
0xfe00ff2c,
0xf90afe94,
0xfc96079c,
0x07de0270,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x062a0000,
0xfefa0759,
0x08b80908,
0xf396fc2d,
0xf9d6045c,
0xfc4ef608,
0xf748f596,
0x07b207bf,
0x062a062a,
0xf84ef841,
0xf748f596,
0x03b209f8,
0xf9d6045c,
0x0c6a03d3,
0x08b80908,
0x0106f8a7,
0x062a0000,
0xfefaf8a7,
0x08b8f6f8,
0xf39603d3,
0xf9d6fba4,
0xfc4e09f8,
0xf7480a6a,
0x07b2f841,
0x062af9d6,
0xf84e07bf,
0xf7480a6a,
0x03b2f608,
0xf9d6fba4,
0x0c6afc2d,
0x08b8f6f8,
0x01060759,
0x062a0000,
0xfefa0759,
0x08b80908,
0xf396fc2d,
0xf9d6045c,
0xfc4ef608,
0xf748f596,
0x07b207bf,
0x062a062a,
0xf84ef841,
0xf748f596,
0x03b209f8,
0xf9d6045c,
0x0c6a03d3,
0x08b80908,
0x0106f8a7,
0x062a0000,
0xfefaf8a7,
0x08b8f6f8,
0xf39603d3,
0xf9d6fba4,
0xfc4e09f8,
0xf7480a6a,
0x07b2f841,
0x062af9d6,
0xf84e07bf,
0xf7480a6a,
0x03b2f608,
0xf9d6fba4,
0x0c6afc2d,
0x08b8f6f8,
0x01060759,
0x061c061c,
0xff30009d,
0xffb21141,
0xfd87fb54,
0xf65dfe59,
0x02eef99e,
0x0166f03c,
0xfff809b6,
0x000008a4,
0x000af42b,
0x00eff577,
0xfa840bf2,
0xfc02ff51,
0x08260f67,
0xfff0036f,
0x0842f9c3,
0x00000000,
0x063df7be,
0xfc910010,
0xf099f7da,
0x00af03fe,
0xf40e057c,
0x0a89ff11,
0x0bd5fff6,
0xf75c0000,
0xf64a0008,
0x0fc4fe9a,
0x0662fd12,
0x01a709a3,
0x04ac0279,
0xeebf004e,
0xff6300d0,
0xf9e4f9e4,
0x00d0ff63,
0x004eeebf,
0x027904ac,
0x09a301a7,
0xfd120662,
0xfe9a0fc4,
0x0008f64a,
0x0000f75c,
0xfff60bd5,
0xff110a89,
0x057cf40e,
0x03fe00af,
0xf7daf099,
0x0010fc91,
0xf7be063d,
0x00000000,
0xf9c30842,
0x036ffff0,
0x0f670826,
0xff51fc02,
0x0bf2fa84,
0xf57700ef,
0xf42b000a,
0x08a40000,
0x09b6fff8,
0xf03c0166,
0xf99e02ee,
0xfe59f65d,
0xfb54fd87,
0x1141ffb2,
0x009dff30,
0x05e30000,
0xff060705,
0x085408a0,
0xf425fc59,
0xfa1d042a,
0xfc78f67a,
0xf7acf60e,
0x075a0766,
0x05e305e3,
0xf8a6f89a,
0xf7acf60e,
0x03880986,
0xfa1d042a,
0x0bdb03a7,
0x085408a0,
0x00faf8fb,
0x05e30000,
0xff06f8fb,
0x0854f760,
0xf42503a7,
0xfa1dfbd6,
0xfc780986,
0xf7ac09f2,
0x075af89a,
0x05e3fa1d,
0xf8a60766,
0xf7ac09f2,
0x0388f67a,
0xfa1dfbd6,
0x0bdbfc59,
0x0854f760,
0x00fa0705,
0x05e30000,
0xff060705,
0x085408a0,
0xf425fc59,
0xfa1d042a,
0xfc78f67a,
0xf7acf60e,
0x075a0766,
0x05e305e3,
0xf8a6f89a,
0xf7acf60e,
0x03880986,
0xfa1d042a,
0x0bdb03a7,
0x085408a0,
0x00faf8fb,
0x05e30000,
0xff06f8fb,
0x0854f760,
0xf42503a7,
0xfa1dfbd6,
0xfc780986,
0xf7ac09f2,
0x075af89a,
0x05e3fa1d,
0xf8a60766,
0xf7ac09f2,
0x0388f67a,
0xfa1dfbd6,
0x0bdbfc59,
0x0854f760,
0x00fa0705,
0xfa58fa58,
0xf8f0fe00,
0x0448073d,
0xfdc9fe46,
0xf9910258,
0x089d0407,
0xfd5cf71a,
0x02affde0,
0x083e0496,
0xff5a0740,
0xff7afd97,
0x00fe01f1,
0x0009082e,
0xfa94ff75,
0xfecdf8ea,
0xffb0f693,
0xfd2cfa58,
0x0433ff16,
0xfba405dd,
0xfa610341,
0x06a606cb,
0x0039fd2d,
0x0677fa97,
0x01fa05e0,
0xf896003e,
0x075a068b,
0x012cfc3e,
0xfa23f98d,
0xfc7cfd43,
0xff90fc0d,
0x01c10982,
0x00c601d6,
0xfd2cfd2c,
0x01d600c6,
0x098201c1,
0xfc0dff90,
0xfd43fc7c,
0xf98dfa23,
0xfc3e012c,
0x068b075a,
0x003ef896,
0x05e001fa,
0xfa970677,
0xfd2d0039,
0x06cb06a6,
0x0341fa61,
0x05ddfba4,
0xff160433,
0xfa58fd2c,
0xf693ffb0,
0xf8eafecd,
0xff75fa94,
0x082e0009,
0x01f100fe,
0xfd97ff7a,
0x0740ff5a,
0x0496083e,
0xfde002af,
0xf71afd5c,
0x0407089d,
0x0258f991,
0xfe46fdc9,
0x073d0448,
0xfe00f8f0,
0xfd2cfd2c,
0xfce00500,
0xfc09fddc,
0xfe680157,
0x04c70571,
0xfc3aff21,
0xfcd70228,
0x056d0277,
0x0200fe00,
0x0022f927,
0xfe3c032b,
0xfc44ff3c,
0x03e9fbdb,
0x04570313,
0x04c9ff5c,
0x000d03b8,
0xfa580000,
0xfbe900d2,
0xf9d0fe0b,
0x0125fdf9,
0x042501bf,
0x0328fa2b,
0xffa902f0,
0xfa250157,
0x0200fe00,
0x03740438,
0xff0405fd,
0x030cfe52,
0x0037fb39,
0xff6904c5,
0x04f8fd23,
0xfd31fc1b,
0xfd2cfd2c,
0xfc1bfd31,
0xfd2304f8,
0x04c5ff69,
0xfb390037,
0xfe52030c,
0x05fdff04,
0x04380374,
0xfe000200,
0x0157fa25,
0x02f0ffa9,
0xfa2b0328,
0x01bf0425,
0xfdf90125,
0xfe0bf9d0,
0x00d2fbe9,
0x0000fa58,
0x03b8000d,
0xff5c04c9,
0x03130457,
0xfbdb03e9,
0xff3cfc44,
0x032bfe3c,
0xf9270022,
0xfe000200,
0x0277056d,
0x0228fcd7,
0xff21fc3a,
0x057104c7,
0x0157fe68,
0xfddcfc09,
0x0500fce0,
0xfd2cfd2c,
0x0500fce0,
0xfddcfc09,
0x0157fe68,
0x057104c7,
0xff21fc3a,
0x0228fcd7,
0x0277056d,
0xfe000200,
0xf9270022,
0x032bfe3c,
0xff3cfc44,
0xfbdb03e9,
0x03130457,
0xff5c04c9,
0x03b8000d,
0x0000fa58,
0x00d2fbe9,
0xfe0bf9d0,
0xfdf90125,
0x01bf0425,
0xfa2b0328,
0x02f0ffa9,
0x0157fa25,
0xfe000200,
0x04380374,
0x05fdff04,
0xfe52030c,
0xfb390037,
0x04c5ff69,
0xfd2304f8,
0xfc1bfd31,
0xfd2cfd2c,
0xfd31fc1b,
0x04f8fd23,
0xff6904c5,
0x0037fb39,
0x030cfe52,
0xff0405fd,
0x03740438,
0x0200fe00,
0xfa250157,
0xffa902f0,
0x0328fa2b,
0x042501bf,
0x0125fdf9,
0xf9d0fe0b,
0xfbe900d2,
0xfa580000,
0x000d03b8,
0x04c9ff5c,
0x04570313,
0x03e9fbdb,
0xfc44ff3c,
0xfe3c032b,
0x0022f927,
0x0200fe00,
0x056d0277,
0xfcd70228,
0xfc3aff21,
0x04c70571,
0xfe680157,
0xfc09fddc,
0xfce00500,
0x05a80000,
0xff1006be,
0x0800084a,
0xf49cfc7e,
0xfa580400,
0xfc9cf6da,
0xf800f672,
0x0710071c,
0x05a805a8,
0xf8f0f8e4,
0xf800f672,
0x03640926,
0xfa580400,
0x0b640382,
0x0800084a,
0x00f0f942,
0x05a80000,
0xff10f942,
0x0800f7b6,
0xf49c0382,
0xfa58fc00,
0xfc9c0926,
0xf800098e,
0x0710f8e4,
0x05a8fa58,
0xf8f0071c,
0xf800098e,
0x0364f6da,
0xfa58fc00,
0x0b64fc7e,
0x0800f7b6,
0x00f006be,
0x05a80000,
0xff1006be,
0x0800084a,
0xf49cfc7e,
0xfa580400,
0xfc9cf6da,
0xf800f672,
0x0710071c,
0x05a805a8,
0xf8f0f8e4,
0xf800f672,
0x03640926,
0xfa580400,
0x0b640382,
0x0800084a,
0x00f0f942,
0x05a80000,
0xff10f942,
0x0800f7b6,
0xf49c0382,
0xfa58fc00,
0xfc9c0926,
0xf800098e,
0x0710f8e4,
0x05a8fa58,
0xf8f0071c,
0xf800098e,
0x0364f6da,
0xfa58fc00,
0x0b64fc7e,
0x0800f7b6,
0x00f006be,
};
static const u32 intlv_tbl_rev0[] = {
0x00802070,
0x0671188d,
0x0a60192c,
0x0a300e46,
0x00c1188d,
0x080024d2,
0x00000070,
};
static const u16 pilot_tbl_rev0[] = {
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0xff0a,
0xff82,
0xffa0,
0xff28,
0xffff,
0xffff,
0xffff,
0xffff,
0xff82,
0xffa0,
0xff28,
0xff0a,
0xffff,
0xffff,
0xffff,
0xffff,
0xf83f,
0xfa1f,
0xfa97,
0xfab5,
0xf2bd,
0xf0bf,
0xffff,
0xffff,
0xf017,
0xf815,
0xf215,
0xf095,
0xf035,
0xf01d,
0xffff,
0xffff,
0xff08,
0xff02,
0xff80,
0xff20,
0xff08,
0xff02,
0xff80,
0xff20,
0xf01f,
0xf817,
0xfa15,
0xf295,
0xf0b5,
0xf03d,
0xffff,
0xffff,
0xf82a,
0xfa0a,
0xfa82,
0xfaa0,
0xf2a8,
0xf0aa,
0xffff,
0xffff,
0xf002,
0xf800,
0xf200,
0xf080,
0xf020,
0xf008,
0xffff,
0xffff,
0xf00a,
0xf802,
0xfa00,
0xf280,
0xf0a0,
0xf028,
0xffff,
0xffff,
};
static const u32 pltlut_tbl_rev0[] = {
0x76540123,
0x62407351,
0x76543201,
0x76540213,
0x76540123,
0x76430521,
};
static const u32 tdi_tbl20_ant0_rev0[] = {
0x00091226,
0x000a1429,
0x000b56ad,
0x000c58b0,
0x000d5ab3,
0x000e9cb6,
0x000f9eba,
0x0000c13d,
0x00020301,
0x00030504,
0x00040708,
0x0005090b,
0x00064b8e,
0x00095291,
0x000a5494,
0x000b9718,
0x000c9927,
0x000d9b2a,
0x000edd2e,
0x000fdf31,
0x000101b4,
0x000243b7,
0x000345bb,
0x000447be,
0x00058982,
0x00068c05,
0x00099309,
0x000a950c,
0x000bd78f,
0x000cd992,
0x000ddb96,
0x000f1d99,
0x00005fa8,
0x0001422c,
0x0002842f,
0x00038632,
0x00048835,
0x0005ca38,
0x0006ccbc,
0x0009d3bf,
0x000b1603,
0x000c1806,
0x000d1a0a,
0x000e1c0d,
0x000f5e10,
0x00008093,
0x00018297,
0x0002c49a,
0x0003c680,
0x0004c880,
0x00060b00,
0x00070d00,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 tdi_tbl20_ant1_rev0[] = {
0x00014b26,
0x00028d29,
0x000393ad,
0x00049630,
0x0005d833,
0x0006da36,
0x00099c3a,
0x000a9e3d,
0x000bc081,
0x000cc284,
0x000dc488,
0x000f068b,
0x0000488e,
0x00018b91,
0x0002d214,
0x0003d418,
0x0004d6a7,
0x000618aa,
0x00071aae,
0x0009dcb1,
0x000b1eb4,
0x000c0137,
0x000d033b,
0x000e053e,
0x000f4702,
0x00008905,
0x00020c09,
0x0003128c,
0x0004148f,
0x00051712,
0x00065916,
0x00091b19,
0x000a1d28,
0x000b5f2c,
0x000c41af,
0x000d43b2,
0x000e85b5,
0x000f87b8,
0x0000c9bc,
0x00024cbf,
0x00035303,
0x00045506,
0x0005978a,
0x0006998d,
0x00095b90,
0x000a5d93,
0x000b9f97,
0x000c821a,
0x000d8400,
0x000ec600,
0x000fc800,
0x00010a00,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 tdi_tbl40_ant0_rev0[] = {
0x0011a346,
0x00136ccf,
0x0014f5d9,
0x001641e2,
0x0017cb6b,
0x00195475,
0x001b2383,
0x001cad0c,
0x001e7616,
0x0000821f,
0x00020ba8,
0x0003d4b2,
0x00056447,
0x00072dd0,
0x0008b6da,
0x000a02e3,
0x000b8c6c,
0x000d15f6,
0x0011e484,
0x0013ae0d,
0x00153717,
0x00168320,
0x00180ca9,
0x00199633,
0x001b6548,
0x001ceed1,
0x001eb7db,
0x0000c3e4,
0x00024d6d,
0x000416f7,
0x0005a585,
0x00076f0f,
0x0008f818,
0x000a4421,
0x000bcdab,
0x000d9734,
0x00122649,
0x0013efd2,
0x001578dc,
0x0016c4e5,
0x00184e6e,
0x001a17f8,
0x001ba686,
0x001d3010,
0x001ef999,
0x00010522,
0x00028eac,
0x00045835,
0x0005e74a,
0x0007b0d3,
0x00093a5d,
0x000a85e6,
0x000c0f6f,
0x000dd8f9,
0x00126787,
0x00143111,
0x0015ba9a,
0x00170623,
0x00188fad,
0x001a5936,
0x001be84b,
0x001db1d4,
0x001f3b5e,
0x000146e7,
0x00031070,
0x000499fa,
0x00062888,
0x0007f212,
0x00097b9b,
0x000ac7a4,
0x000c50ae,
0x000e1a37,
0x0012a94c,
0x001472d5,
0x0015fc5f,
0x00174868,
0x0018d171,
0x001a9afb,
0x001c2989,
0x001df313,
0x001f7c9c,
0x000188a5,
0x000351af,
0x0004db38,
0x0006aa4d,
0x000833d7,
0x0009bd60,
0x000b0969,
0x000c9273,
0x000e5bfc,
0x00132a8a,
0x0014b414,
0x00163d9d,
0x001789a6,
0x001912b0,
0x001adc39,
0x001c6bce,
0x001e34d8,
0x001fbe61,
0x0001ca6a,
0x00039374,
0x00051cfd,
0x0006ec0b,
0x00087515,
0x0009fe9e,
0x000b4aa7,
0x000cd3b1,
0x000e9d3a,
0x00000000,
0x00000000,
};
static const u32 tdi_tbl40_ant1_rev0[] = {
0x001edb36,
0x000129ca,
0x0002b353,
0x00047cdd,
0x0005c8e6,
0x000791ef,
0x00091bf9,
0x000aaa07,
0x000c3391,
0x000dfd1a,
0x00120923,
0x0013d22d,
0x00155c37,
0x0016eacb,
0x00187454,
0x001a3dde,
0x001b89e7,
0x001d12f0,
0x001f1cfa,
0x00016b88,
0x00033492,
0x0004be1b,
0x00060a24,
0x0007d32e,
0x00095d38,
0x000aec4c,
0x000c7555,
0x000e3edf,
0x00124ae8,
0x001413f1,
0x0015a37b,
0x00172c89,
0x0018b593,
0x001a419c,
0x001bcb25,
0x001d942f,
0x001f63b9,
0x0001ad4d,
0x00037657,
0x0004c260,
0x00068be9,
0x000814f3,
0x0009a47c,
0x000b2d8a,
0x000cb694,
0x000e429d,
0x00128c26,
0x001455b0,
0x0015e4ba,
0x00176e4e,
0x0018f758,
0x001a8361,
0x001c0cea,
0x001dd674,
0x001fa57d,
0x0001ee8b,
0x0003b795,
0x0005039e,
0x0006cd27,
0x000856b1,
0x0009e5c6,
0x000b6f4f,
0x000cf859,
0x000e8462,
0x00130deb,
0x00149775,
0x00162603,
0x0017af8c,
0x00193896,
0x001ac49f,
0x001c4e28,
0x001e17b2,
0x0000a6c7,
0x00023050,
0x0003f9da,
0x00054563,
0x00070eec,
0x00089876,
0x000a2704,
0x000bb08d,
0x000d3a17,
0x001185a0,
0x00134f29,
0x0014d8b3,
0x001667c8,
0x0017f151,
0x00197adb,
0x001b0664,
0x001c8fed,
0x001e5977,
0x0000e805,
0x0002718f,
0x00043b18,
0x000586a1,
0x0007502b,
0x0008d9b4,
0x000a68c9,
0x000bf252,
0x000dbbdc,
0x0011c7e5,
0x001390ee,
0x00151a78,
0x0016a906,
0x00183290,
0x0019bc19,
0x001b4822,
0x001cd12c,
0x001e9ab5,
0x00000000,
0x00000000,
};
static const u16 bdi_tbl_rev0[] = {
0x0070,
0x0126,
0x012c,
0x0246,
0x048d,
0x04d2,
};
static const u32 chanest_tbl_rev0[] = {
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
};
static const u8 mcs_tbl_rev0[] = {
0x00,
0x08,
0x0a,
0x10,
0x12,
0x19,
0x1a,
0x1c,
0x40,
0x48,
0x4a,
0x50,
0x52,
0x59,
0x5a,
0x5c,
0x80,
0x88,
0x8a,
0x90,
0x92,
0x99,
0x9a,
0x9c,
0xc0,
0xc8,
0xca,
0xd0,
0xd2,
0xd9,
0xda,
0xdc,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x01,
0x02,
0x04,
0x08,
0x09,
0x0a,
0x0c,
0x10,
0x11,
0x12,
0x14,
0x18,
0x19,
0x1a,
0x1c,
0x20,
0x21,
0x22,
0x24,
0x40,
0x41,
0x42,
0x44,
0x48,
0x49,
0x4a,
0x4c,
0x50,
0x51,
0x52,
0x54,
0x58,
0x59,
0x5a,
0x5c,
0x60,
0x61,
0x62,
0x64,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
static const u32 noise_var_tbl0_rev0[] = {
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
};
static const u32 noise_var_tbl1_rev0[] = {
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
};
static const u8 est_pwr_lut_core0_rev0[] = {
0x50,
0x4f,
0x4e,
0x4d,
0x4c,
0x4b,
0x4a,
0x49,
0x48,
0x47,
0x46,
0x45,
0x44,
0x43,
0x42,
0x41,
0x40,
0x3f,
0x3e,
0x3d,
0x3c,
0x3b,
0x3a,
0x39,
0x38,
0x37,
0x36,
0x35,
0x34,
0x33,
0x32,
0x31,
0x30,
0x2f,
0x2e,
0x2d,
0x2c,
0x2b,
0x2a,
0x29,
0x28,
0x27,
0x26,
0x25,
0x24,
0x23,
0x22,
0x21,
0x20,
0x1f,
0x1e,
0x1d,
0x1c,
0x1b,
0x1a,
0x19,
0x18,
0x17,
0x16,
0x15,
0x14,
0x13,
0x12,
0x11,
};
static const u8 est_pwr_lut_core1_rev0[] = {
0x50,
0x4f,
0x4e,
0x4d,
0x4c,
0x4b,
0x4a,
0x49,
0x48,
0x47,
0x46,
0x45,
0x44,
0x43,
0x42,
0x41,
0x40,
0x3f,
0x3e,
0x3d,
0x3c,
0x3b,
0x3a,
0x39,
0x38,
0x37,
0x36,
0x35,
0x34,
0x33,
0x32,
0x31,
0x30,
0x2f,
0x2e,
0x2d,
0x2c,
0x2b,
0x2a,
0x29,
0x28,
0x27,
0x26,
0x25,
0x24,
0x23,
0x22,
0x21,
0x20,
0x1f,
0x1e,
0x1d,
0x1c,
0x1b,
0x1a,
0x19,
0x18,
0x17,
0x16,
0x15,
0x14,
0x13,
0x12,
0x11,
};
static const u8 adj_pwr_lut_core0_rev0[] = {
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
static const u8 adj_pwr_lut_core1_rev0[] = {
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
static const u32 gainctrl_lut_core0_rev0[] = {
0x03cc2b44,
0x03cc2b42,
0x03cc2b40,
0x03cc2b3e,
0x03cc2b3d,
0x03cc2b3b,
0x03c82b44,
0x03c82b42,
0x03c82b40,
0x03c82b3e,
0x03c82b3d,
0x03c82b3b,
0x03c82b39,
0x03c82b38,
0x03c82b36,
0x03c82b34,
0x03c42b44,
0x03c42b42,
0x03c42b40,
0x03c42b3e,
0x03c42b3d,
0x03c42b3b,
0x03c42b39,
0x03c42b38,
0x03c42b36,
0x03c42b34,
0x03c42b33,
0x03c42b32,
0x03c42b30,
0x03c42b2f,
0x03c42b2d,
0x03c02b44,
0x03c02b42,
0x03c02b40,
0x03c02b3e,
0x03c02b3d,
0x03c02b3b,
0x03c02b39,
0x03c02b38,
0x03c02b36,
0x03c02b34,
0x03b02b44,
0x03b02b42,
0x03b02b40,
0x03b02b3e,
0x03b02b3d,
0x03b02b3b,
0x03b02b39,
0x03b02b38,
0x03b02b36,
0x03b02b34,
0x03b02b33,
0x03b02b32,
0x03b02b30,
0x03b02b2f,
0x03b02b2d,
0x03a02b44,
0x03a02b42,
0x03a02b40,
0x03a02b3e,
0x03a02b3d,
0x03a02b3b,
0x03a02b39,
0x03a02b38,
0x03a02b36,
0x03a02b34,
0x03902b44,
0x03902b42,
0x03902b40,
0x03902b3e,
0x03902b3d,
0x03902b3b,
0x03902b39,
0x03902b38,
0x03902b36,
0x03902b34,
0x03902b33,
0x03902b32,
0x03902b30,
0x03802b44,
0x03802b42,
0x03802b40,
0x03802b3e,
0x03802b3d,
0x03802b3b,
0x03802b39,
0x03802b38,
0x03802b36,
0x03802b34,
0x03802b33,
0x03802b32,
0x03802b30,
0x03802b2f,
0x03802b2d,
0x03802b2c,
0x03802b2b,
0x03802b2a,
0x03802b29,
0x03802b27,
0x03802b26,
0x03802b25,
0x03802b24,
0x03802b23,
0x03802b22,
0x03802b21,
0x03802b20,
0x03802b1f,
0x03802b1e,
0x03802b1e,
0x03802b1d,
0x03802b1c,
0x03802b1b,
0x03802b1a,
0x03802b1a,
0x03802b19,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x00002b00,
};
static const u32 gainctrl_lut_core1_rev0[] = {
0x03cc2b44,
0x03cc2b42,
0x03cc2b40,
0x03cc2b3e,
0x03cc2b3d,
0x03cc2b3b,
0x03c82b44,
0x03c82b42,
0x03c82b40,
0x03c82b3e,
0x03c82b3d,
0x03c82b3b,
0x03c82b39,
0x03c82b38,
0x03c82b36,
0x03c82b34,
0x03c42b44,
0x03c42b42,
0x03c42b40,
0x03c42b3e,
0x03c42b3d,
0x03c42b3b,
0x03c42b39,
0x03c42b38,
0x03c42b36,
0x03c42b34,
0x03c42b33,
0x03c42b32,
0x03c42b30,
0x03c42b2f,
0x03c42b2d,
0x03c02b44,
0x03c02b42,
0x03c02b40,
0x03c02b3e,
0x03c02b3d,
0x03c02b3b,
0x03c02b39,
0x03c02b38,
0x03c02b36,
0x03c02b34,
0x03b02b44,
0x03b02b42,
0x03b02b40,
0x03b02b3e,
0x03b02b3d,
0x03b02b3b,
0x03b02b39,
0x03b02b38,
0x03b02b36,
0x03b02b34,
0x03b02b33,
0x03b02b32,
0x03b02b30,
0x03b02b2f,
0x03b02b2d,
0x03a02b44,
0x03a02b42,
0x03a02b40,
0x03a02b3e,
0x03a02b3d,
0x03a02b3b,
0x03a02b39,
0x03a02b38,
0x03a02b36,
0x03a02b34,
0x03902b44,
0x03902b42,
0x03902b40,
0x03902b3e,
0x03902b3d,
0x03902b3b,
0x03902b39,
0x03902b38,
0x03902b36,
0x03902b34,
0x03902b33,
0x03902b32,
0x03902b30,
0x03802b44,
0x03802b42,
0x03802b40,
0x03802b3e,
0x03802b3d,
0x03802b3b,
0x03802b39,
0x03802b38,
0x03802b36,
0x03802b34,
0x03802b33,
0x03802b32,
0x03802b30,
0x03802b2f,
0x03802b2d,
0x03802b2c,
0x03802b2b,
0x03802b2a,
0x03802b29,
0x03802b27,
0x03802b26,
0x03802b25,
0x03802b24,
0x03802b23,
0x03802b22,
0x03802b21,
0x03802b20,
0x03802b1f,
0x03802b1e,
0x03802b1e,
0x03802b1d,
0x03802b1c,
0x03802b1b,
0x03802b1a,
0x03802b1a,
0x03802b19,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x03802b18,
0x00002b00,
};
static const u32 iq_lut_core0_rev0[] = {
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
};
static const u32 iq_lut_core1_rev0[] = {
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
0x0000007f,
};
static const u16 loft_lut_core0_rev0[] = {
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
};
static const u16 loft_lut_core1_rev0[] = {
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
0x0000,
0x0101,
0x0002,
0x0103,
};
const struct phytbl_info mimophytbl_info_rev0_volatile[] = {
{&bdi_tbl_rev0, sizeof(bdi_tbl_rev0) / sizeof(bdi_tbl_rev0[0]), 21, 0,
16}
,
{&pltlut_tbl_rev0, sizeof(pltlut_tbl_rev0) / sizeof(pltlut_tbl_rev0[0]),
20, 0, 32}
,
{&gainctrl_lut_core0_rev0,
sizeof(gainctrl_lut_core0_rev0) / sizeof(gainctrl_lut_core0_rev0[0]),
26, 192, 32}
,
{&gainctrl_lut_core1_rev0,
sizeof(gainctrl_lut_core1_rev0) / sizeof(gainctrl_lut_core1_rev0[0]),
27, 192, 32}
,
{&est_pwr_lut_core0_rev0,
sizeof(est_pwr_lut_core0_rev0) / sizeof(est_pwr_lut_core0_rev0[0]), 26,
0, 8}
,
{&est_pwr_lut_core1_rev0,
sizeof(est_pwr_lut_core1_rev0) / sizeof(est_pwr_lut_core1_rev0[0]), 27,
0, 8}
,
{&adj_pwr_lut_core0_rev0,
sizeof(adj_pwr_lut_core0_rev0) / sizeof(adj_pwr_lut_core0_rev0[0]), 26,
64, 8}
,
{&adj_pwr_lut_core1_rev0,
sizeof(adj_pwr_lut_core1_rev0) / sizeof(adj_pwr_lut_core1_rev0[0]), 27,
64, 8}
,
{&iq_lut_core0_rev0,
sizeof(iq_lut_core0_rev0) / sizeof(iq_lut_core0_rev0[0]), 26, 320, 32}
,
{&iq_lut_core1_rev0,
sizeof(iq_lut_core1_rev0) / sizeof(iq_lut_core1_rev0[0]), 27, 320, 32}
,
{&loft_lut_core0_rev0,
sizeof(loft_lut_core0_rev0) / sizeof(loft_lut_core0_rev0[0]), 26, 448,
16}
,
{&loft_lut_core1_rev0,
sizeof(loft_lut_core1_rev0) / sizeof(loft_lut_core1_rev0[0]), 27, 448,
16}
,
};
const struct phytbl_info mimophytbl_info_rev0[] = {
{&frame_struct_rev0,
sizeof(frame_struct_rev0) / sizeof(frame_struct_rev0[0]), 10, 0, 32}
,
{&frame_lut_rev0, sizeof(frame_lut_rev0) / sizeof(frame_lut_rev0[0]),
24, 0, 8}
,
{&tmap_tbl_rev0, sizeof(tmap_tbl_rev0) / sizeof(tmap_tbl_rev0[0]), 12,
0, 32}
,
{&tdtrn_tbl_rev0, sizeof(tdtrn_tbl_rev0) / sizeof(tdtrn_tbl_rev0[0]),
14, 0, 32}
,
{&intlv_tbl_rev0, sizeof(intlv_tbl_rev0) / sizeof(intlv_tbl_rev0[0]),
13, 0, 32}
,
{&pilot_tbl_rev0, sizeof(pilot_tbl_rev0) / sizeof(pilot_tbl_rev0[0]),
11, 0, 16}
,
{&tdi_tbl20_ant0_rev0,
sizeof(tdi_tbl20_ant0_rev0) / sizeof(tdi_tbl20_ant0_rev0[0]), 19, 128,
32}
,
{&tdi_tbl20_ant1_rev0,
sizeof(tdi_tbl20_ant1_rev0) / sizeof(tdi_tbl20_ant1_rev0[0]), 19, 256,
32}
,
{&tdi_tbl40_ant0_rev0,
sizeof(tdi_tbl40_ant0_rev0) / sizeof(tdi_tbl40_ant0_rev0[0]), 19, 640,
32}
,
{&tdi_tbl40_ant1_rev0,
sizeof(tdi_tbl40_ant1_rev0) / sizeof(tdi_tbl40_ant1_rev0[0]), 19, 768,
32}
,
{&chanest_tbl_rev0,
sizeof(chanest_tbl_rev0) / sizeof(chanest_tbl_rev0[0]), 22, 0, 32}
,
{&mcs_tbl_rev0, sizeof(mcs_tbl_rev0) / sizeof(mcs_tbl_rev0[0]), 18, 0,
8}
,
{&noise_var_tbl0_rev0,
sizeof(noise_var_tbl0_rev0) / sizeof(noise_var_tbl0_rev0[0]), 16, 0,
32}
,
{&noise_var_tbl1_rev0,
sizeof(noise_var_tbl1_rev0) / sizeof(noise_var_tbl1_rev0[0]), 16, 128,
32}
,
};
const u32 mimophytbl_info_sz_rev0 =
sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]);
const u32 mimophytbl_info_sz_rev0_volatile =
sizeof(mimophytbl_info_rev0_volatile) /
sizeof(mimophytbl_info_rev0_volatile[0]);
static const u16 ant_swctrl_tbl_rev3[] = {
0x0082,
0x0082,
0x0211,
0x0222,
0x0328,
0x0000,
0x0000,
0x0000,
0x0144,
0x0000,
0x0000,
0x0000,
0x0188,
0x0000,
0x0000,
0x0000,
0x0082,
0x0082,
0x0211,
0x0222,
0x0328,
0x0000,
0x0000,
0x0000,
0x0144,
0x0000,
0x0000,
0x0000,
0x0188,
0x0000,
0x0000,
0x0000,
};
static const u16 ant_swctrl_tbl_rev3_1[] = {
0x0022,
0x0022,
0x0011,
0x0022,
0x0022,
0x0000,
0x0000,
0x0000,
0x0011,
0x0000,
0x0000,
0x0000,
0x0022,
0x0000,
0x0000,
0x0000,
0x0022,
0x0022,
0x0011,
0x0022,
0x0022,
0x0000,
0x0000,
0x0000,
0x0011,
0x0000,
0x0000,
0x0000,
0x0022,
0x0000,
0x0000,
0x0000,
};
static const u16 ant_swctrl_tbl_rev3_2[] = {
0x0088,
0x0088,
0x0044,
0x0088,
0x0088,
0x0000,
0x0000,
0x0000,
0x0044,
0x0000,
0x0000,
0x0000,
0x0088,
0x0000,
0x0000,
0x0000,
0x0088,
0x0088,
0x0044,
0x0088,
0x0088,
0x0000,
0x0000,
0x0000,
0x0044,
0x0000,
0x0000,
0x0000,
0x0088,
0x0000,
0x0000,
0x0000,
};
static const u16 ant_swctrl_tbl_rev3_3[] = {
0x022,
0x022,
0x011,
0x022,
0x000,
0x000,
0x000,
0x000,
0x011,
0x000,
0x000,
0x000,
0x022,
0x000,
0x000,
0x3cc,
0x022,
0x022,
0x011,
0x022,
0x000,
0x000,
0x000,
0x000,
0x011,
0x000,
0x000,
0x000,
0x022,
0x000,
0x000,
0x3cc
};
static const u32 frame_struct_rev3[] = {
0x08004a04,
0x00100000,
0x01000a05,
0x00100020,
0x09804506,
0x00100030,
0x09804507,
0x00100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a0c,
0x00100004,
0x01000a0d,
0x00100024,
0x0980450e,
0x00100034,
0x0980450f,
0x00100034,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a04,
0x00100000,
0x11008a05,
0x00100020,
0x1980c506,
0x00100030,
0x21810506,
0x00100030,
0x21810506,
0x00100030,
0x01800504,
0x00100030,
0x11808505,
0x00100030,
0x29814507,
0x01100030,
0x00000a04,
0x00100000,
0x11008a05,
0x00100020,
0x21810506,
0x00100030,
0x21810506,
0x00100030,
0x29814507,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a0c,
0x00100008,
0x11008a0d,
0x00100028,
0x1980c50e,
0x00100038,
0x2181050e,
0x00100038,
0x2181050e,
0x00100038,
0x0180050c,
0x00100038,
0x1180850d,
0x00100038,
0x2981450f,
0x01100038,
0x00000a0c,
0x00100008,
0x11008a0d,
0x00100028,
0x2181050e,
0x00100038,
0x2181050e,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a04,
0x00100000,
0x01000a05,
0x00100020,
0x1980c506,
0x00100030,
0x1980c506,
0x00100030,
0x11808504,
0x00100030,
0x3981ca05,
0x00100030,
0x29814507,
0x01100030,
0x00000000,
0x00000000,
0x10008a04,
0x00100000,
0x3981ca05,
0x00100030,
0x1980c506,
0x00100030,
0x29814507,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a0c,
0x00100008,
0x01000a0d,
0x00100028,
0x1980c50e,
0x00100038,
0x1980c50e,
0x00100038,
0x1180850c,
0x00100038,
0x3981ca0d,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x10008a0c,
0x00100008,
0x3981ca0d,
0x00100038,
0x1980c50e,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x00100000,
0x02001405,
0x00100040,
0x0b004a06,
0x01900060,
0x13008a06,
0x01900060,
0x13008a06,
0x01900060,
0x43020a04,
0x00100060,
0x1b00ca05,
0x00100060,
0x23010a07,
0x01500060,
0x40021404,
0x00100000,
0x1a00d405,
0x00100040,
0x13008a06,
0x01900060,
0x13008a06,
0x01900060,
0x23010a07,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x0200140d,
0x00100050,
0x0b004a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x43020a0c,
0x00100070,
0x1b00ca0d,
0x00100070,
0x23010a0f,
0x01500070,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x13008a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x50029404,
0x00100000,
0x32019405,
0x00100040,
0x0b004a06,
0x01900060,
0x0b004a06,
0x01900060,
0x5b02ca04,
0x00100060,
0x3b01d405,
0x00100060,
0x23010a07,
0x01500060,
0x00000000,
0x00000000,
0x5802d404,
0x00100000,
0x3b01d405,
0x00100060,
0x0b004a06,
0x01900060,
0x23010a07,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x5002940c,
0x00100010,
0x3201940d,
0x00100050,
0x0b004a0e,
0x01900070,
0x0b004a0e,
0x01900070,
0x5b02ca0c,
0x00100070,
0x3b01d40d,
0x00100070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x5802d40c,
0x00100010,
0x3b01d40d,
0x00100070,
0x0b004a0e,
0x01900070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x000f4800,
0x62031405,
0x00100040,
0x53028a06,
0x01900060,
0x53028a07,
0x01900060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x000f4808,
0x6203140d,
0x00100048,
0x53028a0e,
0x01900068,
0x53028a0f,
0x01900068,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a0c,
0x00100004,
0x11008a0d,
0x00100024,
0x1980c50e,
0x00100034,
0x2181050e,
0x00100034,
0x2181050e,
0x00100034,
0x0180050c,
0x00100038,
0x1180850d,
0x00100038,
0x1181850d,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000a0c,
0x00100008,
0x11008a0d,
0x00100028,
0x2181050e,
0x00100038,
0x2181050e,
0x00100038,
0x1181850d,
0x00100038,
0x2981450f,
0x01100038,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x08004a04,
0x00100000,
0x01000a05,
0x00100020,
0x0180c506,
0x00100030,
0x0180c506,
0x00100030,
0x2180c50c,
0x00100030,
0x49820a0d,
0x0016a130,
0x41824a0d,
0x0016a130,
0x2981450f,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x2000ca0c,
0x00100000,
0x49820a0d,
0x0016a130,
0x1980c50e,
0x00100030,
0x41824a0d,
0x0016a130,
0x2981450f,
0x01100030,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100008,
0x0200140d,
0x00100048,
0x0b004a0e,
0x01900068,
0x13008a0e,
0x01900068,
0x13008a0e,
0x01900068,
0x43020a0c,
0x00100070,
0x1b00ca0d,
0x00100070,
0x1b014a0d,
0x00100070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x13008a0e,
0x01900070,
0x13008a0e,
0x01900070,
0x1b014a0d,
0x00100070,
0x23010a0f,
0x01500070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x50029404,
0x00100000,
0x32019405,
0x00100040,
0x03004a06,
0x01900060,
0x03004a06,
0x01900060,
0x6b030a0c,
0x00100060,
0x4b02140d,
0x0016a160,
0x4302540d,
0x0016a160,
0x23010a0f,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x6b03140c,
0x00100060,
0x4b02140d,
0x0016a160,
0x0b004a0e,
0x01900060,
0x4302540d,
0x0016a160,
0x23010a0f,
0x01500060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x00100000,
0x1a00d405,
0x00100040,
0x53028a06,
0x01900060,
0x5b02ca06,
0x01900060,
0x5b02ca06,
0x01900060,
0x43020a04,
0x00100060,
0x1b00ca05,
0x00100060,
0x53028a07,
0x0190c060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x53028a0e,
0x01900070,
0x5b02ca0e,
0x01900070,
0x5b02ca0e,
0x01900070,
0x43020a0c,
0x00100070,
0x1b00ca0d,
0x00100070,
0x53028a0f,
0x0190c070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40021404,
0x00100000,
0x1a00d405,
0x00100040,
0x5b02ca06,
0x01900060,
0x5b02ca06,
0x01900060,
0x53028a07,
0x0190c060,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x4002140c,
0x00100010,
0x1a00d40d,
0x00100050,
0x5b02ca0e,
0x01900070,
0x5b02ca0e,
0x01900070,
0x53028a0f,
0x0190c070,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u16 pilot_tbl_rev3[] = {
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0xff08,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0x80d5,
0xff0a,
0xff82,
0xffa0,
0xff28,
0xffff,
0xffff,
0xffff,
0xffff,
0xff82,
0xffa0,
0xff28,
0xff0a,
0xffff,
0xffff,
0xffff,
0xffff,
0xf83f,
0xfa1f,
0xfa97,
0xfab5,
0xf2bd,
0xf0bf,
0xffff,
0xffff,
0xf017,
0xf815,
0xf215,
0xf095,
0xf035,
0xf01d,
0xffff,
0xffff,
0xff08,
0xff02,
0xff80,
0xff20,
0xff08,
0xff02,
0xff80,
0xff20,
0xf01f,
0xf817,
0xfa15,
0xf295,
0xf0b5,
0xf03d,
0xffff,
0xffff,
0xf82a,
0xfa0a,
0xfa82,
0xfaa0,
0xf2a8,
0xf0aa,
0xffff,
0xffff,
0xf002,
0xf800,
0xf200,
0xf080,
0xf020,
0xf008,
0xffff,
0xffff,
0xf00a,
0xf802,
0xfa00,
0xf280,
0xf0a0,
0xf028,
0xffff,
0xffff,
};
static const u32 tmap_tbl_rev3[] = {
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0xf1111110,
0x11111111,
0x11f11111,
0x00000111,
0x11000000,
0x1111f111,
0x11111111,
0x111111f1,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x000aa888,
0x88880000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa2222220,
0x22222222,
0x22c22222,
0x00000222,
0x22000000,
0x2222a222,
0x22222222,
0x222222a2,
0xf1111110,
0x11111111,
0x11f11111,
0x00011111,
0x11110000,
0x1111f111,
0x11111111,
0x111111f1,
0xa8aa88a0,
0xa88888a8,
0xa8a8a88a,
0x00088aaa,
0xaaaa0000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xaaa8aaa0,
0x8aaa8aaa,
0xaa8a8a8a,
0x000aaa88,
0x8aaa0000,
0xaaa8a888,
0x8aa88a8a,
0x8a88a888,
0x08080a00,
0x0a08080a,
0x080a0a08,
0x00080808,
0x080a0000,
0x080a0808,
0x080a0808,
0x0a0a0a08,
0xa0a0a0a0,
0x80a0a080,
0x8080a0a0,
0x00008080,
0x80a00000,
0x80a080a0,
0xa080a0a0,
0x8080a0a0,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x99999000,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb90,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00aaa888,
0x22000000,
0x2222b222,
0x22222222,
0x222222b2,
0xb2222220,
0x22222222,
0x22d22222,
0x00000222,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x33000000,
0x3333b333,
0x33333333,
0x333333b3,
0xb3333330,
0x33333333,
0x33d33333,
0x00000333,
0x22000000,
0x2222a222,
0x22222222,
0x222222a2,
0xa2222220,
0x22222222,
0x22c22222,
0x00000222,
0x99b99b00,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb99,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x08aaa888,
0x22222200,
0x2222f222,
0x22222222,
0x222222f2,
0x22222222,
0x22222222,
0x22f22222,
0x00000222,
0x11000000,
0x1111f111,
0x11111111,
0x11111111,
0xf1111111,
0x11111111,
0x11f11111,
0x01111111,
0xbb9bb900,
0xb9b9bb99,
0xb99bbbbb,
0xbbbb9b9b,
0xb9bb99bb,
0xb99999b9,
0xb9b9b99b,
0x00000bbb,
0xaa000000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xa8aa88aa,
0xa88888a8,
0xa8a8a88a,
0x0a888aaa,
0xaa000000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xa8aa88a0,
0xa88888a8,
0xa8a8a88a,
0x00000aaa,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0xbbbbbb00,
0x999bbbbb,
0x9bb99b9b,
0xb9b9b9bb,
0xb9b99bbb,
0xb9b9b9bb,
0xb9bb9b99,
0x00000999,
0x8a000000,
0xaa88a888,
0xa88888aa,
0xa88a8a88,
0xa88aa88a,
0x88a8aaaa,
0xa8aa8aaa,
0x0888a88a,
0x0b0b0b00,
0x090b0b0b,
0x0b090b0b,
0x0909090b,
0x09090b0b,
0x09090b0b,
0x09090b09,
0x00000909,
0x0a000000,
0x0a080808,
0x080a080a,
0x080a0a08,
0x080a080a,
0x0808080a,
0x0a0a0a08,
0x0808080a,
0xb0b0b000,
0x9090b0b0,
0x90b09090,
0xb0b0b090,
0xb0b090b0,
0x90b0b0b0,
0xb0b09090,
0x00000090,
0x80000000,
0xa080a080,
0xa08080a0,
0xa0808080,
0xa080a080,
0x80a0a0a0,
0xa0a080a0,
0x00a0a0a0,
0x22000000,
0x2222f222,
0x22222222,
0x222222f2,
0xf2222220,
0x22222222,
0x22f22222,
0x00000222,
0x11000000,
0x1111f111,
0x11111111,
0x111111f1,
0xf1111110,
0x11111111,
0x11f11111,
0x00000111,
0x33000000,
0x3333f333,
0x33333333,
0x333333f3,
0xf3333330,
0x33333333,
0x33f33333,
0x00000333,
0x22000000,
0x2222f222,
0x22222222,
0x222222f2,
0xf2222220,
0x22222222,
0x22f22222,
0x00000222,
0x99000000,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb90,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88888000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00aaa888,
0x88a88a00,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x08aaa888,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 intlv_tbl_rev3[] = {
0x00802070,
0x0671188d,
0x0a60192c,
0x0a300e46,
0x00c1188d,
0x080024d2,
0x00000070,
};
static const u32 tdtrn_tbl_rev3[] = {
0x061c061c,
0x0050ee68,
0xf592fe36,
0xfe5212f6,
0x00000c38,
0xfe5212f6,
0xf592fe36,
0x0050ee68,
0x061c061c,
0xee680050,
0xfe36f592,
0x12f6fe52,
0x0c380000,
0x12f6fe52,
0xfe36f592,
0xee680050,
0x061c061c,
0x0050ee68,
0xf592fe36,
0xfe5212f6,
0x00000c38,
0xfe5212f6,
0xf592fe36,
0x0050ee68,
0x061c061c,
0xee680050,
0xfe36f592,
0x12f6fe52,
0x0c380000,
0x12f6fe52,
0xfe36f592,
0xee680050,
0x05e305e3,
0x004def0c,
0xf5f3fe47,
0xfe611246,
0x00000bc7,
0xfe611246,
0xf5f3fe47,
0x004def0c,
0x05e305e3,
0xef0c004d,
0xfe47f5f3,
0x1246fe61,
0x0bc70000,
0x1246fe61,
0xfe47f5f3,
0xef0c004d,
0x05e305e3,
0x004def0c,
0xf5f3fe47,
0xfe611246,
0x00000bc7,
0xfe611246,
0xf5f3fe47,
0x004def0c,
0x05e305e3,
0xef0c004d,
0xfe47f5f3,
0x1246fe61,
0x0bc70000,
0x1246fe61,
0xfe47f5f3,
0xef0c004d,
0xfa58fa58,
0xf895043b,
0xff4c09c0,
0xfbc6ffa8,
0xfb84f384,
0x0798f6f9,
0x05760122,
0x058409f6,
0x0b500000,
0x05b7f542,
0x08860432,
0x06ddfee7,
0xfb84f384,
0xf9d90664,
0xf7e8025c,
0x00fff7bd,
0x05a805a8,
0xf7bd00ff,
0x025cf7e8,
0x0664f9d9,
0xf384fb84,
0xfee706dd,
0x04320886,
0xf54205b7,
0x00000b50,
0x09f60584,
0x01220576,
0xf6f90798,
0xf384fb84,
0xffa8fbc6,
0x09c0ff4c,
0x043bf895,
0x02d402d4,
0x07de0270,
0xfc96079c,
0xf90afe94,
0xfe00ff2c,
0x02d4065d,
0x092a0096,
0x0014fbb8,
0xfd2cfd2c,
0x076afb3c,
0x0096f752,
0xf991fd87,
0xfb2c0200,
0xfeb8f960,
0x08e0fc96,
0x049802a8,
0xfd2cfd2c,
0x02a80498,
0xfc9608e0,
0xf960feb8,
0x0200fb2c,
0xfd87f991,
0xf7520096,
0xfb3c076a,
0xfd2cfd2c,
0xfbb80014,
0x0096092a,
0x065d02d4,
0xff2cfe00,
0xfe94f90a,
0x079cfc96,
0x027007de,
0x02d402d4,
0x027007de,
0x079cfc96,
0xfe94f90a,
0xff2cfe00,
0x065d02d4,
0x0096092a,
0xfbb80014,
0xfd2cfd2c,
0xfb3c076a,
0xf7520096,
0xfd87f991,
0x0200fb2c,
0xf960feb8,
0xfc9608e0,
0x02a80498,
0xfd2cfd2c,
0x049802a8,
0x08e0fc96,
0xfeb8f960,
0xfb2c0200,
0xf991fd87,
0x0096f752,
0x076afb3c,
0xfd2cfd2c,
0x0014fbb8,
0x092a0096,
0x02d4065d,
0xfe00ff2c,
0xf90afe94,
0xfc96079c,
0x07de0270,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x062a0000,
0xfefa0759,
0x08b80908,
0xf396fc2d,
0xf9d6045c,
0xfc4ef608,
0xf748f596,
0x07b207bf,
0x062a062a,
0xf84ef841,
0xf748f596,
0x03b209f8,
0xf9d6045c,
0x0c6a03d3,
0x08b80908,
0x0106f8a7,
0x062a0000,
0xfefaf8a7,
0x08b8f6f8,
0xf39603d3,
0xf9d6fba4,
0xfc4e09f8,
0xf7480a6a,
0x07b2f841,
0x062af9d6,
0xf84e07bf,
0xf7480a6a,
0x03b2f608,
0xf9d6fba4,
0x0c6afc2d,
0x08b8f6f8,
0x01060759,
0x062a0000,
0xfefa0759,
0x08b80908,
0xf396fc2d,
0xf9d6045c,
0xfc4ef608,
0xf748f596,
0x07b207bf,
0x062a062a,
0xf84ef841,
0xf748f596,
0x03b209f8,
0xf9d6045c,
0x0c6a03d3,
0x08b80908,
0x0106f8a7,
0x062a0000,
0xfefaf8a7,
0x08b8f6f8,
0xf39603d3,
0xf9d6fba4,
0xfc4e09f8,
0xf7480a6a,
0x07b2f841,
0x062af9d6,
0xf84e07bf,
0xf7480a6a,
0x03b2f608,
0xf9d6fba4,
0x0c6afc2d,
0x08b8f6f8,
0x01060759,
0x061c061c,
0xff30009d,
0xffb21141,
0xfd87fb54,
0xf65dfe59,
0x02eef99e,
0x0166f03c,
0xfff809b6,
0x000008a4,
0x000af42b,
0x00eff577,
0xfa840bf2,
0xfc02ff51,
0x08260f67,
0xfff0036f,
0x0842f9c3,
0x00000000,
0x063df7be,
0xfc910010,
0xf099f7da,
0x00af03fe,
0xf40e057c,
0x0a89ff11,
0x0bd5fff6,
0xf75c0000,
0xf64a0008,
0x0fc4fe9a,
0x0662fd12,
0x01a709a3,
0x04ac0279,
0xeebf004e,
0xff6300d0,
0xf9e4f9e4,
0x00d0ff63,
0x004eeebf,
0x027904ac,
0x09a301a7,
0xfd120662,
0xfe9a0fc4,
0x0008f64a,
0x0000f75c,
0xfff60bd5,
0xff110a89,
0x057cf40e,
0x03fe00af,
0xf7daf099,
0x0010fc91,
0xf7be063d,
0x00000000,
0xf9c30842,
0x036ffff0,
0x0f670826,
0xff51fc02,
0x0bf2fa84,
0xf57700ef,
0xf42b000a,
0x08a40000,
0x09b6fff8,
0xf03c0166,
0xf99e02ee,
0xfe59f65d,
0xfb54fd87,
0x1141ffb2,
0x009dff30,
0x05e30000,
0xff060705,
0x085408a0,
0xf425fc59,
0xfa1d042a,
0xfc78f67a,
0xf7acf60e,
0x075a0766,
0x05e305e3,
0xf8a6f89a,
0xf7acf60e,
0x03880986,
0xfa1d042a,
0x0bdb03a7,
0x085408a0,
0x00faf8fb,
0x05e30000,
0xff06f8fb,
0x0854f760,
0xf42503a7,
0xfa1dfbd6,
0xfc780986,
0xf7ac09f2,
0x075af89a,
0x05e3fa1d,
0xf8a60766,
0xf7ac09f2,
0x0388f67a,
0xfa1dfbd6,
0x0bdbfc59,
0x0854f760,
0x00fa0705,
0x05e30000,
0xff060705,
0x085408a0,
0xf425fc59,
0xfa1d042a,
0xfc78f67a,
0xf7acf60e,
0x075a0766,
0x05e305e3,
0xf8a6f89a,
0xf7acf60e,
0x03880986,
0xfa1d042a,
0x0bdb03a7,
0x085408a0,
0x00faf8fb,
0x05e30000,
0xff06f8fb,
0x0854f760,
0xf42503a7,
0xfa1dfbd6,
0xfc780986,
0xf7ac09f2,
0x075af89a,
0x05e3fa1d,
0xf8a60766,
0xf7ac09f2,
0x0388f67a,
0xfa1dfbd6,
0x0bdbfc59,
0x0854f760,
0x00fa0705,
0xfa58fa58,
0xf8f0fe00,
0x0448073d,
0xfdc9fe46,
0xf9910258,
0x089d0407,
0xfd5cf71a,
0x02affde0,
0x083e0496,
0xff5a0740,
0xff7afd97,
0x00fe01f1,
0x0009082e,
0xfa94ff75,
0xfecdf8ea,
0xffb0f693,
0xfd2cfa58,
0x0433ff16,
0xfba405dd,
0xfa610341,
0x06a606cb,
0x0039fd2d,
0x0677fa97,
0x01fa05e0,
0xf896003e,
0x075a068b,
0x012cfc3e,
0xfa23f98d,
0xfc7cfd43,
0xff90fc0d,
0x01c10982,
0x00c601d6,
0xfd2cfd2c,
0x01d600c6,
0x098201c1,
0xfc0dff90,
0xfd43fc7c,
0xf98dfa23,
0xfc3e012c,
0x068b075a,
0x003ef896,
0x05e001fa,
0xfa970677,
0xfd2d0039,
0x06cb06a6,
0x0341fa61,
0x05ddfba4,
0xff160433,
0xfa58fd2c,
0xf693ffb0,
0xf8eafecd,
0xff75fa94,
0x082e0009,
0x01f100fe,
0xfd97ff7a,
0x0740ff5a,
0x0496083e,
0xfde002af,
0xf71afd5c,
0x0407089d,
0x0258f991,
0xfe46fdc9,
0x073d0448,
0xfe00f8f0,
0xfd2cfd2c,
0xfce00500,
0xfc09fddc,
0xfe680157,
0x04c70571,
0xfc3aff21,
0xfcd70228,
0x056d0277,
0x0200fe00,
0x0022f927,
0xfe3c032b,
0xfc44ff3c,
0x03e9fbdb,
0x04570313,
0x04c9ff5c,
0x000d03b8,
0xfa580000,
0xfbe900d2,
0xf9d0fe0b,
0x0125fdf9,
0x042501bf,
0x0328fa2b,
0xffa902f0,
0xfa250157,
0x0200fe00,
0x03740438,
0xff0405fd,
0x030cfe52,
0x0037fb39,
0xff6904c5,
0x04f8fd23,
0xfd31fc1b,
0xfd2cfd2c,
0xfc1bfd31,
0xfd2304f8,
0x04c5ff69,
0xfb390037,
0xfe52030c,
0x05fdff04,
0x04380374,
0xfe000200,
0x0157fa25,
0x02f0ffa9,
0xfa2b0328,
0x01bf0425,
0xfdf90125,
0xfe0bf9d0,
0x00d2fbe9,
0x0000fa58,
0x03b8000d,
0xff5c04c9,
0x03130457,
0xfbdb03e9,
0xff3cfc44,
0x032bfe3c,
0xf9270022,
0xfe000200,
0x0277056d,
0x0228fcd7,
0xff21fc3a,
0x057104c7,
0x0157fe68,
0xfddcfc09,
0x0500fce0,
0xfd2cfd2c,
0x0500fce0,
0xfddcfc09,
0x0157fe68,
0x057104c7,
0xff21fc3a,
0x0228fcd7,
0x0277056d,
0xfe000200,
0xf9270022,
0x032bfe3c,
0xff3cfc44,
0xfbdb03e9,
0x03130457,
0xff5c04c9,
0x03b8000d,
0x0000fa58,
0x00d2fbe9,
0xfe0bf9d0,
0xfdf90125,
0x01bf0425,
0xfa2b0328,
0x02f0ffa9,
0x0157fa25,
0xfe000200,
0x04380374,
0x05fdff04,
0xfe52030c,
0xfb390037,
0x04c5ff69,
0xfd2304f8,
0xfc1bfd31,
0xfd2cfd2c,
0xfd31fc1b,
0x04f8fd23,
0xff6904c5,
0x0037fb39,
0x030cfe52,
0xff0405fd,
0x03740438,
0x0200fe00,
0xfa250157,
0xffa902f0,
0x0328fa2b,
0x042501bf,
0x0125fdf9,
0xf9d0fe0b,
0xfbe900d2,
0xfa580000,
0x000d03b8,
0x04c9ff5c,
0x04570313,
0x03e9fbdb,
0xfc44ff3c,
0xfe3c032b,
0x0022f927,
0x0200fe00,
0x056d0277,
0xfcd70228,
0xfc3aff21,
0x04c70571,
0xfe680157,
0xfc09fddc,
0xfce00500,
0x05a80000,
0xff1006be,
0x0800084a,
0xf49cfc7e,
0xfa580400,
0xfc9cf6da,
0xf800f672,
0x0710071c,
0x05a805a8,
0xf8f0f8e4,
0xf800f672,
0x03640926,
0xfa580400,
0x0b640382,
0x0800084a,
0x00f0f942,
0x05a80000,
0xff10f942,
0x0800f7b6,
0xf49c0382,
0xfa58fc00,
0xfc9c0926,
0xf800098e,
0x0710f8e4,
0x05a8fa58,
0xf8f0071c,
0xf800098e,
0x0364f6da,
0xfa58fc00,
0x0b64fc7e,
0x0800f7b6,
0x00f006be,
0x05a80000,
0xff1006be,
0x0800084a,
0xf49cfc7e,
0xfa580400,
0xfc9cf6da,
0xf800f672,
0x0710071c,
0x05a805a8,
0xf8f0f8e4,
0xf800f672,
0x03640926,
0xfa580400,
0x0b640382,
0x0800084a,
0x00f0f942,
0x05a80000,
0xff10f942,
0x0800f7b6,
0xf49c0382,
0xfa58fc00,
0xfc9c0926,
0xf800098e,
0x0710f8e4,
0x05a8fa58,
0xf8f0071c,
0xf800098e,
0x0364f6da,
0xfa58fc00,
0x0b64fc7e,
0x0800f7b6,
0x00f006be,
};
const u32 noise_var_tbl_rev3[] = {
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
0x02110211,
0x0000014d,
};
static const u16 mcs_tbl_rev3[] = {
0x0000,
0x0008,
0x000a,
0x0010,
0x0012,
0x0019,
0x001a,
0x001c,
0x0080,
0x0088,
0x008a,
0x0090,
0x0092,
0x0099,
0x009a,
0x009c,
0x0100,
0x0108,
0x010a,
0x0110,
0x0112,
0x0119,
0x011a,
0x011c,
0x0180,
0x0188,
0x018a,
0x0190,
0x0192,
0x0199,
0x019a,
0x019c,
0x0000,
0x0098,
0x00a0,
0x00a8,
0x009a,
0x00a2,
0x00aa,
0x0120,
0x0128,
0x0128,
0x0130,
0x0138,
0x0138,
0x0140,
0x0122,
0x012a,
0x012a,
0x0132,
0x013a,
0x013a,
0x0142,
0x01a8,
0x01b0,
0x01b8,
0x01b0,
0x01b8,
0x01c0,
0x01c8,
0x01c0,
0x01c8,
0x01d0,
0x01d0,
0x01d8,
0x01aa,
0x01b2,
0x01ba,
0x01b2,
0x01ba,
0x01c2,
0x01ca,
0x01c2,
0x01ca,
0x01d2,
0x01d2,
0x01da,
0x0001,
0x0002,
0x0004,
0x0009,
0x000c,
0x0011,
0x0014,
0x0018,
0x0020,
0x0021,
0x0022,
0x0024,
0x0081,
0x0082,
0x0084,
0x0089,
0x008c,
0x0091,
0x0094,
0x0098,
0x00a0,
0x00a1,
0x00a2,
0x00a4,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
0x0007,
};
static const u32 tdi_tbl20_ant0_rev3[] = {
0x00091226,
0x000a1429,
0x000b56ad,
0x000c58b0,
0x000d5ab3,
0x000e9cb6,
0x000f9eba,
0x0000c13d,
0x00020301,
0x00030504,
0x00040708,
0x0005090b,
0x00064b8e,
0x00095291,
0x000a5494,
0x000b9718,
0x000c9927,
0x000d9b2a,
0x000edd2e,
0x000fdf31,
0x000101b4,
0x000243b7,
0x000345bb,
0x000447be,
0x00058982,
0x00068c05,
0x00099309,
0x000a950c,
0x000bd78f,
0x000cd992,
0x000ddb96,
0x000f1d99,
0x00005fa8,
0x0001422c,
0x0002842f,
0x00038632,
0x00048835,
0x0005ca38,
0x0006ccbc,
0x0009d3bf,
0x000b1603,
0x000c1806,
0x000d1a0a,
0x000e1c0d,
0x000f5e10,
0x00008093,
0x00018297,
0x0002c49a,
0x0003c680,
0x0004c880,
0x00060b00,
0x00070d00,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 tdi_tbl20_ant1_rev3[] = {
0x00014b26,
0x00028d29,
0x000393ad,
0x00049630,
0x0005d833,
0x0006da36,
0x00099c3a,
0x000a9e3d,
0x000bc081,
0x000cc284,
0x000dc488,
0x000f068b,
0x0000488e,
0x00018b91,
0x0002d214,
0x0003d418,
0x0004d6a7,
0x000618aa,
0x00071aae,
0x0009dcb1,
0x000b1eb4,
0x000c0137,
0x000d033b,
0x000e053e,
0x000f4702,
0x00008905,
0x00020c09,
0x0003128c,
0x0004148f,
0x00051712,
0x00065916,
0x00091b19,
0x000a1d28,
0x000b5f2c,
0x000c41af,
0x000d43b2,
0x000e85b5,
0x000f87b8,
0x0000c9bc,
0x00024cbf,
0x00035303,
0x00045506,
0x0005978a,
0x0006998d,
0x00095b90,
0x000a5d93,
0x000b9f97,
0x000c821a,
0x000d8400,
0x000ec600,
0x000fc800,
0x00010a00,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 tdi_tbl40_ant0_rev3[] = {
0x0011a346,
0x00136ccf,
0x0014f5d9,
0x001641e2,
0x0017cb6b,
0x00195475,
0x001b2383,
0x001cad0c,
0x001e7616,
0x0000821f,
0x00020ba8,
0x0003d4b2,
0x00056447,
0x00072dd0,
0x0008b6da,
0x000a02e3,
0x000b8c6c,
0x000d15f6,
0x0011e484,
0x0013ae0d,
0x00153717,
0x00168320,
0x00180ca9,
0x00199633,
0x001b6548,
0x001ceed1,
0x001eb7db,
0x0000c3e4,
0x00024d6d,
0x000416f7,
0x0005a585,
0x00076f0f,
0x0008f818,
0x000a4421,
0x000bcdab,
0x000d9734,
0x00122649,
0x0013efd2,
0x001578dc,
0x0016c4e5,
0x00184e6e,
0x001a17f8,
0x001ba686,
0x001d3010,
0x001ef999,
0x00010522,
0x00028eac,
0x00045835,
0x0005e74a,
0x0007b0d3,
0x00093a5d,
0x000a85e6,
0x000c0f6f,
0x000dd8f9,
0x00126787,
0x00143111,
0x0015ba9a,
0x00170623,
0x00188fad,
0x001a5936,
0x001be84b,
0x001db1d4,
0x001f3b5e,
0x000146e7,
0x00031070,
0x000499fa,
0x00062888,
0x0007f212,
0x00097b9b,
0x000ac7a4,
0x000c50ae,
0x000e1a37,
0x0012a94c,
0x001472d5,
0x0015fc5f,
0x00174868,
0x0018d171,
0x001a9afb,
0x001c2989,
0x001df313,
0x001f7c9c,
0x000188a5,
0x000351af,
0x0004db38,
0x0006aa4d,
0x000833d7,
0x0009bd60,
0x000b0969,
0x000c9273,
0x000e5bfc,
0x00132a8a,
0x0014b414,
0x00163d9d,
0x001789a6,
0x001912b0,
0x001adc39,
0x001c6bce,
0x001e34d8,
0x001fbe61,
0x0001ca6a,
0x00039374,
0x00051cfd,
0x0006ec0b,
0x00087515,
0x0009fe9e,
0x000b4aa7,
0x000cd3b1,
0x000e9d3a,
0x00000000,
0x00000000,
};
static const u32 tdi_tbl40_ant1_rev3[] = {
0x001edb36,
0x000129ca,
0x0002b353,
0x00047cdd,
0x0005c8e6,
0x000791ef,
0x00091bf9,
0x000aaa07,
0x000c3391,
0x000dfd1a,
0x00120923,
0x0013d22d,
0x00155c37,
0x0016eacb,
0x00187454,
0x001a3dde,
0x001b89e7,
0x001d12f0,
0x001f1cfa,
0x00016b88,
0x00033492,
0x0004be1b,
0x00060a24,
0x0007d32e,
0x00095d38,
0x000aec4c,
0x000c7555,
0x000e3edf,
0x00124ae8,
0x001413f1,
0x0015a37b,
0x00172c89,
0x0018b593,
0x001a419c,
0x001bcb25,
0x001d942f,
0x001f63b9,
0x0001ad4d,
0x00037657,
0x0004c260,
0x00068be9,
0x000814f3,
0x0009a47c,
0x000b2d8a,
0x000cb694,
0x000e429d,
0x00128c26,
0x001455b0,
0x0015e4ba,
0x00176e4e,
0x0018f758,
0x001a8361,
0x001c0cea,
0x001dd674,
0x001fa57d,
0x0001ee8b,
0x0003b795,
0x0005039e,
0x0006cd27,
0x000856b1,
0x0009e5c6,
0x000b6f4f,
0x000cf859,
0x000e8462,
0x00130deb,
0x00149775,
0x00162603,
0x0017af8c,
0x00193896,
0x001ac49f,
0x001c4e28,
0x001e17b2,
0x0000a6c7,
0x00023050,
0x0003f9da,
0x00054563,
0x00070eec,
0x00089876,
0x000a2704,
0x000bb08d,
0x000d3a17,
0x001185a0,
0x00134f29,
0x0014d8b3,
0x001667c8,
0x0017f151,
0x00197adb,
0x001b0664,
0x001c8fed,
0x001e5977,
0x0000e805,
0x0002718f,
0x00043b18,
0x000586a1,
0x0007502b,
0x0008d9b4,
0x000a68c9,
0x000bf252,
0x000dbbdc,
0x0011c7e5,
0x001390ee,
0x00151a78,
0x0016a906,
0x00183290,
0x0019bc19,
0x001b4822,
0x001cd12c,
0x001e9ab5,
0x00000000,
0x00000000,
};
static const u32 pltlut_tbl_rev3[] = {
0x76540213,
0x62407351,
0x76543210,
0x76540213,
0x76540213,
0x76430521,
};
static const u32 chanest_tbl_rev3[] = {
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x44444444,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
0x10101010,
};
static const u8 frame_lut_rev3[] = {
0x02,
0x04,
0x14,
0x14,
0x03,
0x05,
0x16,
0x16,
0x0a,
0x0c,
0x1c,
0x1c,
0x0b,
0x0d,
0x1e,
0x1e,
0x06,
0x08,
0x18,
0x18,
0x07,
0x09,
0x1a,
0x1a,
0x0e,
0x10,
0x20,
0x28,
0x0f,
0x11,
0x22,
0x2a,
};
static const u8 est_pwr_lut_core0_rev3[] = {
0x55,
0x54,
0x54,
0x53,
0x52,
0x52,
0x51,
0x51,
0x50,
0x4f,
0x4f,
0x4e,
0x4e,
0x4d,
0x4c,
0x4c,
0x4b,
0x4a,
0x49,
0x49,
0x48,
0x47,
0x46,
0x46,
0x45,
0x44,
0x43,
0x42,
0x41,
0x40,
0x40,
0x3f,
0x3e,
0x3d,
0x3c,
0x3a,
0x39,
0x38,
0x37,
0x36,
0x35,
0x33,
0x32,
0x31,
0x2f,
0x2e,
0x2c,
0x2b,
0x29,
0x27,
0x25,
0x23,
0x21,
0x1f,
0x1d,
0x1a,
0x18,
0x15,
0x12,
0x0e,
0x0b,
0x07,
0x02,
0xfd,
};
static const u8 est_pwr_lut_core1_rev3[] = {
0x55,
0x54,
0x54,
0x53,
0x52,
0x52,
0x51,
0x51,
0x50,
0x4f,
0x4f,
0x4e,
0x4e,
0x4d,
0x4c,
0x4c,
0x4b,
0x4a,
0x49,
0x49,
0x48,
0x47,
0x46,
0x46,
0x45,
0x44,
0x43,
0x42,
0x41,
0x40,
0x40,
0x3f,
0x3e,
0x3d,
0x3c,
0x3a,
0x39,
0x38,
0x37,
0x36,
0x35,
0x33,
0x32,
0x31,
0x2f,
0x2e,
0x2c,
0x2b,
0x29,
0x27,
0x25,
0x23,
0x21,
0x1f,
0x1d,
0x1a,
0x18,
0x15,
0x12,
0x0e,
0x0b,
0x07,
0x02,
0xfd,
};
static const u8 adj_pwr_lut_core0_rev3[] = {
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
static const u8 adj_pwr_lut_core1_rev3[] = {
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
static const u32 gainctrl_lut_core0_rev3[] = {
0x5bf70044,
0x5bf70042,
0x5bf70040,
0x5bf7003e,
0x5bf7003c,
0x5bf7003b,
0x5bf70039,
0x5bf70037,
0x5bf70036,
0x5bf70034,
0x5bf70033,
0x5bf70031,
0x5bf70030,
0x5ba70044,
0x5ba70042,
0x5ba70040,
0x5ba7003e,
0x5ba7003c,
0x5ba7003b,
0x5ba70039,
0x5ba70037,
0x5ba70036,
0x5ba70034,
0x5ba70033,
0x5b770044,
0x5b770042,
0x5b770040,
0x5b77003e,
0x5b77003c,
0x5b77003b,
0x5b770039,
0x5b770037,
0x5b770036,
0x5b770034,
0x5b770033,
0x5b770031,
0x5b770030,
0x5b77002f,
0x5b77002d,
0x5b77002c,
0x5b470044,
0x5b470042,
0x5b470040,
0x5b47003e,
0x5b47003c,
0x5b47003b,
0x5b470039,
0x5b470037,
0x5b470036,
0x5b470034,
0x5b470033,
0x5b470031,
0x5b470030,
0x5b47002f,
0x5b47002d,
0x5b47002c,
0x5b47002b,
0x5b47002a,
0x5b270044,
0x5b270042,
0x5b270040,
0x5b27003e,
0x5b27003c,
0x5b27003b,
0x5b270039,
0x5b270037,
0x5b270036,
0x5b270034,
0x5b270033,
0x5b270031,
0x5b270030,
0x5b27002f,
0x5b170044,
0x5b170042,
0x5b170040,
0x5b17003e,
0x5b17003c,
0x5b17003b,
0x5b170039,
0x5b170037,
0x5b170036,
0x5b170034,
0x5b170033,
0x5b170031,
0x5b170030,
0x5b17002f,
0x5b17002d,
0x5b17002c,
0x5b17002b,
0x5b17002a,
0x5b170028,
0x5b170027,
0x5b170026,
0x5b170025,
0x5b170024,
0x5b170023,
0x5b070044,
0x5b070042,
0x5b070040,
0x5b07003e,
0x5b07003c,
0x5b07003b,
0x5b070039,
0x5b070037,
0x5b070036,
0x5b070034,
0x5b070033,
0x5b070031,
0x5b070030,
0x5b07002f,
0x5b07002d,
0x5b07002c,
0x5b07002b,
0x5b07002a,
0x5b070028,
0x5b070027,
0x5b070026,
0x5b070025,
0x5b070024,
0x5b070023,
0x5b070022,
0x5b070021,
0x5b070020,
0x5b07001f,
0x5b07001e,
0x5b07001d,
0x5b07001d,
0x5b07001c,
};
static const u32 gainctrl_lut_core1_rev3[] = {
0x5bf70044,
0x5bf70042,
0x5bf70040,
0x5bf7003e,
0x5bf7003c,
0x5bf7003b,
0x5bf70039,
0x5bf70037,
0x5bf70036,
0x5bf70034,
0x5bf70033,
0x5bf70031,
0x5bf70030,
0x5ba70044,
0x5ba70042,
0x5ba70040,
0x5ba7003e,
0x5ba7003c,
0x5ba7003b,
0x5ba70039,
0x5ba70037,
0x5ba70036,
0x5ba70034,
0x5ba70033,
0x5b770044,
0x5b770042,
0x5b770040,
0x5b77003e,
0x5b77003c,
0x5b77003b,
0x5b770039,
0x5b770037,
0x5b770036,
0x5b770034,
0x5b770033,
0x5b770031,
0x5b770030,
0x5b77002f,
0x5b77002d,
0x5b77002c,
0x5b470044,
0x5b470042,
0x5b470040,
0x5b47003e,
0x5b47003c,
0x5b47003b,
0x5b470039,
0x5b470037,
0x5b470036,
0x5b470034,
0x5b470033,
0x5b470031,
0x5b470030,
0x5b47002f,
0x5b47002d,
0x5b47002c,
0x5b47002b,
0x5b47002a,
0x5b270044,
0x5b270042,
0x5b270040,
0x5b27003e,
0x5b27003c,
0x5b27003b,
0x5b270039,
0x5b270037,
0x5b270036,
0x5b270034,
0x5b270033,
0x5b270031,
0x5b270030,
0x5b27002f,
0x5b170044,
0x5b170042,
0x5b170040,
0x5b17003e,
0x5b17003c,
0x5b17003b,
0x5b170039,
0x5b170037,
0x5b170036,
0x5b170034,
0x5b170033,
0x5b170031,
0x5b170030,
0x5b17002f,
0x5b17002d,
0x5b17002c,
0x5b17002b,
0x5b17002a,
0x5b170028,
0x5b170027,
0x5b170026,
0x5b170025,
0x5b170024,
0x5b170023,
0x5b070044,
0x5b070042,
0x5b070040,
0x5b07003e,
0x5b07003c,
0x5b07003b,
0x5b070039,
0x5b070037,
0x5b070036,
0x5b070034,
0x5b070033,
0x5b070031,
0x5b070030,
0x5b07002f,
0x5b07002d,
0x5b07002c,
0x5b07002b,
0x5b07002a,
0x5b070028,
0x5b070027,
0x5b070026,
0x5b070025,
0x5b070024,
0x5b070023,
0x5b070022,
0x5b070021,
0x5b070020,
0x5b07001f,
0x5b07001e,
0x5b07001d,
0x5b07001d,
0x5b07001c,
};
static const u32 iq_lut_core0_rev3[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 iq_lut_core1_rev3[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u16 loft_lut_core0_rev3[] = {
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
};
static const u16 loft_lut_core1_rev3[] = {
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
};
static const u16 papd_comp_rfpwr_tbl_core0_rev3[] = {
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
};
static const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x0036,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x002a,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x001e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x000e,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01fc,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01ee,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
0x01d6,
};
static const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
0x00000000,
0x00001fa0,
0x00019f78,
0x0001df7e,
0x03fa9f86,
0x03fd1f90,
0x03fe5f8a,
0x03fb1f94,
0x03fd9fa0,
0x00009f98,
0x03fd1fac,
0x03ff9fa2,
0x03fe9fae,
0x00001fae,
0x03fddfb4,
0x03ff1fb8,
0x03ff9fbc,
0x03ffdfbe,
0x03fe9fc2,
0x03fedfc6,
0x03fedfc6,
0x03ff9fc8,
0x03ff5fc6,
0x03fedfc2,
0x03ff9fc0,
0x03ff5fac,
0x03ff5fac,
0x03ff9fa2,
0x03ff9fa6,
0x03ff9faa,
0x03ff5fb0,
0x03ff5fb4,
0x03ff1fca,
0x03ff5fce,
0x03fcdfdc,
0x03fb4006,
0x00000030,
0x03ff808a,
0x03ff80da,
0x0000016c,
0x03ff8318,
0x03ff063a,
0x03fd8bd6,
0x00014ffe,
0x00034ffe,
0x00034ffe,
0x0003cffe,
0x00040ffe,
0x00040ffe,
0x0003cffe,
0x0003cffe,
0x00020ffe,
0x03fe0ffe,
0x03fdcffe,
0x03f94ffe,
0x03f54ffe,
0x03f44ffe,
0x03ef8ffe,
0x03ee0ffe,
0x03ebcffe,
0x03e8cffe,
0x03e74ffe,
0x03e4cffe,
0x03e38ffe,
};
static const u32 papd_cal_scalars_tbl_core0_rev3[] = {
0x05af005a,
0x0571005e,
0x05040066,
0x04bd006c,
0x047d0072,
0x04430078,
0x03f70081,
0x03cb0087,
0x03870091,
0x035e0098,
0x032e00a1,
0x030300aa,
0x02d800b4,
0x02ae00bf,
0x028900ca,
0x026400d6,
0x024100e3,
0x022200f0,
0x020200ff,
0x01e5010e,
0x01ca011e,
0x01b0012f,
0x01990140,
0x01830153,
0x016c0168,
0x0158017d,
0x01450193,
0x013301ab,
0x012101c5,
0x011101e0,
0x010201fc,
0x00f4021a,
0x00e6011d,
0x00d9012e,
0x00cd0140,
0x00c20153,
0x00b70167,
0x00ac017c,
0x00a30193,
0x009a01ab,
0x009101c4,
0x008901df,
0x008101fb,
0x007a0219,
0x00730239,
0x006d025b,
0x0067027e,
0x006102a4,
0x005c02cc,
0x005602f6,
0x00520323,
0x004d0353,
0x00490385,
0x004503bb,
0x004103f3,
0x003d042f,
0x003a046f,
0x003704b2,
0x003404f9,
0x00310545,
0x002e0596,
0x002b05f5,
0x00290640,
0x002606a4,
};
static const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
0x00000000,
0x00001fa0,
0x00019f78,
0x0001df7e,
0x03fa9f86,
0x03fd1f90,
0x03fe5f8a,
0x03fb1f94,
0x03fd9fa0,
0x00009f98,
0x03fd1fac,
0x03ff9fa2,
0x03fe9fae,
0x00001fae,
0x03fddfb4,
0x03ff1fb8,
0x03ff9fbc,
0x03ffdfbe,
0x03fe9fc2,
0x03fedfc6,
0x03fedfc6,
0x03ff9fc8,
0x03ff5fc6,
0x03fedfc2,
0x03ff9fc0,
0x03ff5fac,
0x03ff5fac,
0x03ff9fa2,
0x03ff9fa6,
0x03ff9faa,
0x03ff5fb0,
0x03ff5fb4,
0x03ff1fca,
0x03ff5fce,
0x03fcdfdc,
0x03fb4006,
0x00000030,
0x03ff808a,
0x03ff80da,
0x0000016c,
0x03ff8318,
0x03ff063a,
0x03fd8bd6,
0x00014ffe,
0x00034ffe,
0x00034ffe,
0x0003cffe,
0x00040ffe,
0x00040ffe,
0x0003cffe,
0x0003cffe,
0x00020ffe,
0x03fe0ffe,
0x03fdcffe,
0x03f94ffe,
0x03f54ffe,
0x03f44ffe,
0x03ef8ffe,
0x03ee0ffe,
0x03ebcffe,
0x03e8cffe,
0x03e74ffe,
0x03e4cffe,
0x03e38ffe,
};
static const u32 papd_cal_scalars_tbl_core1_rev3[] = {
0x05af005a,
0x0571005e,
0x05040066,
0x04bd006c,
0x047d0072,
0x04430078,
0x03f70081,
0x03cb0087,
0x03870091,
0x035e0098,
0x032e00a1,
0x030300aa,
0x02d800b4,
0x02ae00bf,
0x028900ca,
0x026400d6,
0x024100e3,
0x022200f0,
0x020200ff,
0x01e5010e,
0x01ca011e,
0x01b0012f,
0x01990140,
0x01830153,
0x016c0168,
0x0158017d,
0x01450193,
0x013301ab,
0x012101c5,
0x011101e0,
0x010201fc,
0x00f4021a,
0x00e6011d,
0x00d9012e,
0x00cd0140,
0x00c20153,
0x00b70167,
0x00ac017c,
0x00a30193,
0x009a01ab,
0x009101c4,
0x008901df,
0x008101fb,
0x007a0219,
0x00730239,
0x006d025b,
0x0067027e,
0x006102a4,
0x005c02cc,
0x005602f6,
0x00520323,
0x004d0353,
0x00490385,
0x004503bb,
0x004103f3,
0x003d042f,
0x003a046f,
0x003704b2,
0x003404f9,
0x00310545,
0x002e0596,
0x002b05f5,
0x00290640,
0x002606a4,
};
const struct phytbl_info mimophytbl_info_rev3_volatile[] = {
{&ant_swctrl_tbl_rev3,
sizeof(ant_swctrl_tbl_rev3) / sizeof(ant_swctrl_tbl_rev3[0]), 9, 0, 16}
,
};
const struct phytbl_info mimophytbl_info_rev3_volatile1[] = {
{&ant_swctrl_tbl_rev3_1,
sizeof(ant_swctrl_tbl_rev3_1) / sizeof(ant_swctrl_tbl_rev3_1[0]), 9, 0,
16}
,
};
const struct phytbl_info mimophytbl_info_rev3_volatile2[] = {
{&ant_swctrl_tbl_rev3_2,
sizeof(ant_swctrl_tbl_rev3_2) / sizeof(ant_swctrl_tbl_rev3_2[0]), 9, 0,
16}
,
};
const struct phytbl_info mimophytbl_info_rev3_volatile3[] = {
{&ant_swctrl_tbl_rev3_3,
sizeof(ant_swctrl_tbl_rev3_3) / sizeof(ant_swctrl_tbl_rev3_3[0]), 9, 0,
16}
,
};
const struct phytbl_info mimophytbl_info_rev3[] = {
{&frame_struct_rev3,
sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
,
{&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
11, 0, 16}
,
{&tmap_tbl_rev3, sizeof(tmap_tbl_rev3) / sizeof(tmap_tbl_rev3[0]), 12,
0, 32}
,
{&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
13, 0, 32}
,
{&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
14, 0, 32}
,
{&noise_var_tbl_rev3,
sizeof(noise_var_tbl_rev3) / sizeof(noise_var_tbl_rev3[0]), 16, 0, 32}
,
{&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
16}
,
{&tdi_tbl20_ant0_rev3,
sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
32}
,
{&tdi_tbl20_ant1_rev3,
sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
32}
,
{&tdi_tbl40_ant0_rev3,
sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
32}
,
{&tdi_tbl40_ant1_rev3,
sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
32}
,
{&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
20, 0, 32}
,
{&chanest_tbl_rev3,
sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
,
{&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
24, 0, 8}
,
{&est_pwr_lut_core0_rev3,
sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
0, 8}
,
{&est_pwr_lut_core1_rev3,
sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
0, 8}
,
{&adj_pwr_lut_core0_rev3,
sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
64, 8}
,
{&adj_pwr_lut_core1_rev3,
sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
64, 8}
,
{&gainctrl_lut_core0_rev3,
sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
26, 192, 32}
,
{&gainctrl_lut_core1_rev3,
sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
27, 192, 32}
,
{&iq_lut_core0_rev3,
sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
,
{&iq_lut_core1_rev3,
sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
,
{&loft_lut_core0_rev3,
sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
16}
,
{&loft_lut_core1_rev3,
sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
16}
};
const u32 mimophytbl_info_sz_rev3 =
sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]);
const u32 mimophytbl_info_sz_rev3_volatile =
sizeof(mimophytbl_info_rev3_volatile) /
sizeof(mimophytbl_info_rev3_volatile[0]);
const u32 mimophytbl_info_sz_rev3_volatile1 =
sizeof(mimophytbl_info_rev3_volatile1) /
sizeof(mimophytbl_info_rev3_volatile1[0]);
const u32 mimophytbl_info_sz_rev3_volatile2 =
sizeof(mimophytbl_info_rev3_volatile2) /
sizeof(mimophytbl_info_rev3_volatile2[0]);
const u32 mimophytbl_info_sz_rev3_volatile3 =
sizeof(mimophytbl_info_rev3_volatile3) /
sizeof(mimophytbl_info_rev3_volatile3[0]);
static const u32 tmap_tbl_rev7[] = {
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0xf1111110,
0x11111111,
0x11f11111,
0x00000111,
0x11000000,
0x1111f111,
0x11111111,
0x111111f1,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x000aa888,
0x88880000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa2222220,
0x22222222,
0x22c22222,
0x00000222,
0x22000000,
0x2222a222,
0x22222222,
0x222222a2,
0xf1111110,
0x11111111,
0x11f11111,
0x00011111,
0x11110000,
0x1111f111,
0x11111111,
0x111111f1,
0xa8aa88a0,
0xa88888a8,
0xa8a8a88a,
0x00088aaa,
0xaaaa0000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xaaa8aaa0,
0x8aaa8aaa,
0xaa8a8a8a,
0x000aaa88,
0x8aaa0000,
0xaaa8a888,
0x8aa88a8a,
0x8a88a888,
0x08080a00,
0x0a08080a,
0x080a0a08,
0x00080808,
0x080a0000,
0x080a0808,
0x080a0808,
0x0a0a0a08,
0xa0a0a0a0,
0x80a0a080,
0x8080a0a0,
0x00008080,
0x80a00000,
0x80a080a0,
0xa080a0a0,
0x8080a0a0,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x99999000,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb90,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00aaa888,
0x22000000,
0x2222b222,
0x22222222,
0x222222b2,
0xb2222220,
0x22222222,
0x22d22222,
0x00000222,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x33000000,
0x3333b333,
0x33333333,
0x333333b3,
0xb3333330,
0x33333333,
0x33d33333,
0x00000333,
0x22000000,
0x2222a222,
0x22222222,
0x222222a2,
0xa2222220,
0x22222222,
0x22c22222,
0x00000222,
0x99b99b00,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb99,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x08aaa888,
0x22222200,
0x2222f222,
0x22222222,
0x222222f2,
0x22222222,
0x22222222,
0x22f22222,
0x00000222,
0x11000000,
0x1111f111,
0x11111111,
0x11111111,
0xf1111111,
0x11111111,
0x11f11111,
0x01111111,
0xbb9bb900,
0xb9b9bb99,
0xb99bbbbb,
0xbbbb9b9b,
0xb9bb99bb,
0xb99999b9,
0xb9b9b99b,
0x00000bbb,
0xaa000000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xa8aa88aa,
0xa88888a8,
0xa8a8a88a,
0x0a888aaa,
0xaa000000,
0xa8a8aa88,
0xa88aaaaa,
0xaaaa8a8a,
0xa8aa88a0,
0xa88888a8,
0xa8a8a88a,
0x00000aaa,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0xbbbbbb00,
0x999bbbbb,
0x9bb99b9b,
0xb9b9b9bb,
0xb9b99bbb,
0xb9b9b9bb,
0xb9bb9b99,
0x00000999,
0x8a000000,
0xaa88a888,
0xa88888aa,
0xa88a8a88,
0xa88aa88a,
0x88a8aaaa,
0xa8aa8aaa,
0x0888a88a,
0x0b0b0b00,
0x090b0b0b,
0x0b090b0b,
0x0909090b,
0x09090b0b,
0x09090b0b,
0x09090b09,
0x00000909,
0x0a000000,
0x0a080808,
0x080a080a,
0x080a0a08,
0x080a080a,
0x0808080a,
0x0a0a0a08,
0x0808080a,
0xb0b0b000,
0x9090b0b0,
0x90b09090,
0xb0b0b090,
0xb0b090b0,
0x90b0b0b0,
0xb0b09090,
0x00000090,
0x80000000,
0xa080a080,
0xa08080a0,
0xa0808080,
0xa080a080,
0x80a0a0a0,
0xa0a080a0,
0x00a0a0a0,
0x22000000,
0x2222f222,
0x22222222,
0x222222f2,
0xf2222220,
0x22222222,
0x22f22222,
0x00000222,
0x11000000,
0x1111f111,
0x11111111,
0x111111f1,
0xf1111110,
0x11111111,
0x11f11111,
0x00000111,
0x33000000,
0x3333f333,
0x33333333,
0x333333f3,
0xf3333330,
0x33333333,
0x33f33333,
0x00000333,
0x22000000,
0x2222f222,
0x22222222,
0x222222f2,
0xf2222220,
0x22222222,
0x22f22222,
0x00000222,
0x99000000,
0x9b9b99bb,
0x9bb99999,
0x9999b9b9,
0x9b99bb90,
0x9bbbbb9b,
0x9b9b9bb9,
0x00000999,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88888000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00aaa888,
0x88a88a00,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x000aa888,
0x88880000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa88,
0x8aaaaa8a,
0x8a8a8aa8,
0x08aaa888,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x11000000,
0x1111a111,
0x11111111,
0x111111a1,
0xa1111110,
0x11111111,
0x11c11111,
0x00000111,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x88000000,
0x8a8a88aa,
0x8aa88888,
0x8888a8a8,
0x8a88aa80,
0x8aaaaa8a,
0x8a8a8aa8,
0x00000888,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
const u32 noise_var_tbl_rev7[] = {
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
0x020c020c,
0x0000014d,
};
static const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
0x00000000,
0x00000000,
0x00016023,
0x00006028,
0x00034036,
0x0003402e,
0x0007203c,
0x0006e037,
0x00070030,
0x0009401f,
0x0009a00f,
0x000b600d,
0x000c8007,
0x000ce007,
0x00101fff,
0x00121ff9,
0x0012e004,
0x0014dffc,
0x0016dff6,
0x0018dfe9,
0x001b3fe5,
0x001c5fd0,
0x001ddfc2,
0x001f1fb6,
0x00207fa4,
0x00219f8f,
0x0022ff7d,
0x00247f6c,
0x0024df5b,
0x00267f4b,
0x0027df3b,
0x0029bf3b,
0x002b5f2f,
0x002d3f2e,
0x002f5f2a,
0x002fff15,
0x00315f0b,
0x0032defa,
0x0033beeb,
0x0034fed9,
0x00353ec5,
0x00361eb0,
0x00363e9b,
0x0036be87,
0x0036be70,
0x0038fe67,
0x0044beb2,
0x00513ef3,
0x00595f11,
0x00669f3d,
0x0078dfdf,
0x00a143aa,
0x01642fff,
0x0162afff,
0x01620fff,
0x0160cfff,
0x015f0fff,
0x015dafff,
0x015bcfff,
0x015bcfff,
0x015b4fff,
0x015acfff,
0x01590fff,
0x0156cfff,
};
static const u32 papd_cal_scalars_tbl_core0_rev7[] = {
0x0b5e002d,
0x0ae2002f,
0x0a3b0032,
0x09a70035,
0x09220038,
0x08ab003b,
0x081f003f,
0x07a20043,
0x07340047,
0x06d2004b,
0x067a004f,
0x06170054,
0x05bf0059,
0x0571005e,
0x051e0064,
0x04d3006a,
0x04910070,
0x044c0077,
0x040f007e,
0x03d90085,
0x03a1008d,
0x036f0095,
0x033d009e,
0x030b00a8,
0x02e000b2,
0x02b900bc,
0x029200c7,
0x026d00d3,
0x024900e0,
0x022900ed,
0x020a00fb,
0x01ec010a,
0x01d20119,
0x01b7012a,
0x019e013c,
0x0188014e,
0x01720162,
0x015d0177,
0x0149018e,
0x013701a5,
0x012601be,
0x011501d8,
0x010601f4,
0x00f70212,
0x00e90231,
0x00dc0253,
0x00d00276,
0x00c4029b,
0x00b902c3,
0x00af02ed,
0x00a50319,
0x009c0348,
0x0093037a,
0x008b03af,
0x008303e6,
0x007c0422,
0x00750460,
0x006e04a3,
0x006804e9,
0x00620533,
0x005d0582,
0x005805d6,
0x0053062e,
0x004e068c,
};
static const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
0x00000000,
0x00000000,
0x00016023,
0x00006028,
0x00034036,
0x0003402e,
0x0007203c,
0x0006e037,
0x00070030,
0x0009401f,
0x0009a00f,
0x000b600d,
0x000c8007,
0x000ce007,
0x00101fff,
0x00121ff9,
0x0012e004,
0x0014dffc,
0x0016dff6,
0x0018dfe9,
0x001b3fe5,
0x001c5fd0,
0x001ddfc2,
0x001f1fb6,
0x00207fa4,
0x00219f8f,
0x0022ff7d,
0x00247f6c,
0x0024df5b,
0x00267f4b,
0x0027df3b,
0x0029bf3b,
0x002b5f2f,
0x002d3f2e,
0x002f5f2a,
0x002fff15,
0x00315f0b,
0x0032defa,
0x0033beeb,
0x0034fed9,
0x00353ec5,
0x00361eb0,
0x00363e9b,
0x0036be87,
0x0036be70,
0x0038fe67,
0x0044beb2,
0x00513ef3,
0x00595f11,
0x00669f3d,
0x0078dfdf,
0x00a143aa,
0x01642fff,
0x0162afff,
0x01620fff,
0x0160cfff,
0x015f0fff,
0x015dafff,
0x015bcfff,
0x015bcfff,
0x015b4fff,
0x015acfff,
0x01590fff,
0x0156cfff,
};
static const u32 papd_cal_scalars_tbl_core1_rev7[] = {
0x0b5e002d,
0x0ae2002f,
0x0a3b0032,
0x09a70035,
0x09220038,
0x08ab003b,
0x081f003f,
0x07a20043,
0x07340047,
0x06d2004b,
0x067a004f,
0x06170054,
0x05bf0059,
0x0571005e,
0x051e0064,
0x04d3006a,
0x04910070,
0x044c0077,
0x040f007e,
0x03d90085,
0x03a1008d,
0x036f0095,
0x033d009e,
0x030b00a8,
0x02e000b2,
0x02b900bc,
0x029200c7,
0x026d00d3,
0x024900e0,
0x022900ed,
0x020a00fb,
0x01ec010a,
0x01d20119,
0x01b7012a,
0x019e013c,
0x0188014e,
0x01720162,
0x015d0177,
0x0149018e,
0x013701a5,
0x012601be,
0x011501d8,
0x010601f4,
0x00f70212,
0x00e90231,
0x00dc0253,
0x00d00276,
0x00c4029b,
0x00b902c3,
0x00af02ed,
0x00a50319,
0x009c0348,
0x0093037a,
0x008b03af,
0x008303e6,
0x007c0422,
0x00750460,
0x006e04a3,
0x006804e9,
0x00620533,
0x005d0582,
0x005805d6,
0x0053062e,
0x004e068c,
};
const struct phytbl_info mimophytbl_info_rev7[] = {
{&frame_struct_rev3,
sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
,
{&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
11, 0, 16}
,
{&tmap_tbl_rev7, sizeof(tmap_tbl_rev7) / sizeof(tmap_tbl_rev7[0]), 12,
0, 32}
,
{&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
13, 0, 32}
,
{&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
14, 0, 32}
,
{&noise_var_tbl_rev7,
sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
,
{&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
16}
,
{&tdi_tbl20_ant0_rev3,
sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
32}
,
{&tdi_tbl20_ant1_rev3,
sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
32}
,
{&tdi_tbl40_ant0_rev3,
sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
32}
,
{&tdi_tbl40_ant1_rev3,
sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
32}
,
{&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
20, 0, 32}
,
{&chanest_tbl_rev3,
sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
,
{&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
24, 0, 8}
,
{&est_pwr_lut_core0_rev3,
sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
0, 8}
,
{&est_pwr_lut_core1_rev3,
sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
0, 8}
,
{&adj_pwr_lut_core0_rev3,
sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
64, 8}
,
{&adj_pwr_lut_core1_rev3,
sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
64, 8}
,
{&gainctrl_lut_core0_rev3,
sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
26, 192, 32}
,
{&gainctrl_lut_core1_rev3,
sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
27, 192, 32}
,
{&iq_lut_core0_rev3,
sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
,
{&iq_lut_core1_rev3,
sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
,
{&loft_lut_core0_rev3,
sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
16}
,
{&loft_lut_core1_rev3,
sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
16}
,
{&papd_comp_rfpwr_tbl_core0_rev3,
sizeof(papd_comp_rfpwr_tbl_core0_rev3) /
sizeof(papd_comp_rfpwr_tbl_core0_rev3[0]), 26, 576, 16}
,
{&papd_comp_rfpwr_tbl_core1_rev3,
sizeof(papd_comp_rfpwr_tbl_core1_rev3) /
sizeof(papd_comp_rfpwr_tbl_core1_rev3[0]), 27, 576, 16}
,
{&papd_comp_epsilon_tbl_core0_rev7,
sizeof(papd_comp_epsilon_tbl_core0_rev7) /
sizeof(papd_comp_epsilon_tbl_core0_rev7[0]), 31, 0, 32}
,
{&papd_cal_scalars_tbl_core0_rev7,
sizeof(papd_cal_scalars_tbl_core0_rev7) /
sizeof(papd_cal_scalars_tbl_core0_rev7[0]), 32, 0, 32}
,
{&papd_comp_epsilon_tbl_core1_rev7,
sizeof(papd_comp_epsilon_tbl_core1_rev7) /
sizeof(papd_comp_epsilon_tbl_core1_rev7[0]), 33, 0, 32}
,
{&papd_cal_scalars_tbl_core1_rev7,
sizeof(papd_cal_scalars_tbl_core1_rev7) /
sizeof(papd_cal_scalars_tbl_core1_rev7[0]), 34, 0, 32}
,
};
const u32 mimophytbl_info_sz_rev7 =
sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]);
const struct phytbl_info mimophytbl_info_rev16[] = {
{&noise_var_tbl_rev7,
sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
,
{&est_pwr_lut_core0_rev3,
sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
0, 8}
,
{&est_pwr_lut_core1_rev3,
sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
0, 8}
,
{&adj_pwr_lut_core0_rev3,
sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
64, 8}
,
{&adj_pwr_lut_core1_rev3,
sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
64, 8}
,
{&gainctrl_lut_core0_rev3,
sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
26, 192, 32}
,
{&gainctrl_lut_core1_rev3,
sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
27, 192, 32}
,
{&iq_lut_core0_rev3,
sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
,
{&iq_lut_core1_rev3,
sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
,
{&loft_lut_core0_rev3,
sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
16}
,
{&loft_lut_core1_rev3,
sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
16}
,
};
const u32 mimophytbl_info_sz_rev16 =
sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]);
| gpl-2.0 |
Ginfred/TrinityCore434 | dep/StormLib/src/libtomcrypt/src/pk/asn1/der_decode_utf8_string.c | 236 | 2637 | /* LibTomCrypt, modular cryptographic library -- Tom St Denis
*
* LibTomCrypt is a library that provides various cryptographic
* algorithms in a highly modular and flexible manner.
*
* The library is free for all purposes without any express
* guarantee it works.
*
* Tom St Denis, tomstdenis@gmail.com, http://libtom.org
*/
#include "../../headers/tomcrypt.h"
/**
@file der_decode_utf8_string.c
ASN.1 DER, encode a UTF8 STRING, Tom St Denis
*/
#ifdef LTC_DER
/**
Store a UTF8 STRING
@param in The DER encoded UTF8 STRING
@param inlen The size of the DER UTF8 STRING
@param out [out] The array of utf8s stored (one per char)
@param outlen [in/out] The number of utf8s stored
@return CRYPT_OK if successful
*/
int der_decode_utf8_string(const unsigned char *in, unsigned long inlen,
wchar_t *out, unsigned long *outlen)
{
wchar_t tmp;
unsigned long x, y, z, len;
LTC_ARGCHK(in != NULL);
LTC_ARGCHK(out != NULL);
LTC_ARGCHK(outlen != NULL);
/* must have header at least */
if (inlen < 2) {
return CRYPT_INVALID_PACKET;
}
/* check for 0x0C */
if ((in[0] & 0x1F) != 0x0C) {
return CRYPT_INVALID_PACKET;
}
x = 1;
/* decode the length */
if (in[x] & 0x80) {
/* valid # of bytes in length are 1,2,3 */
y = in[x] & 0x7F;
if ((y == 0) || (y > 3) || ((x + y) > inlen)) {
return CRYPT_INVALID_PACKET;
}
/* read the length in */
len = 0;
++x;
while (y--) {
len = (len << 8) | in[x++];
}
} else {
len = in[x++] & 0x7F;
}
if (len + x > inlen) {
return CRYPT_INVALID_PACKET;
}
/* proceed to decode */
for (y = 0; x < inlen; ) {
/* get first byte */
tmp = in[x++];
/* count number of bytes */
for (z = 0; (tmp & 0x80) && (z <= 4); z++, tmp = (tmp << 1) & 0xFF);
if (z > 4 || (x + (z - 1) > inlen)) {
return CRYPT_INVALID_PACKET;
}
/* decode, grab upper bits */
tmp >>= z;
/* grab remaining bytes */
if (z > 1) { --z; }
while (z-- != 0) {
if ((in[x] & 0xC0) != 0x80) {
return CRYPT_INVALID_PACKET;
}
tmp = (tmp << 6) | ((wchar_t)in[x++] & 0x3F);
}
if (y > *outlen) {
*outlen = y;
return CRYPT_BUFFER_OVERFLOW;
}
out[y++] = tmp;
}
*outlen = y;
return CRYPT_OK;
}
#endif
/* $Source: /cvs/libtom/libtomcrypt/src/pk/asn1/der/utf8/der_decode_utf8_string.c,v $ */
/* $Revision: 1.8 $ */
/* $Date: 2006/12/28 01:27:24 $ */
| gpl-2.0 |
thanhphat11/android_kernel_xiaomi_msm8996 | net/8021q/vlan_core.c | 492 | 8544 | #include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#include <linux/netpoll.h>
#include <linux/export.h>
#include "vlan.h"
bool vlan_do_receive(struct sk_buff **skbp)
{
struct sk_buff *skb = *skbp;
__be16 vlan_proto = skb->vlan_proto;
u16 vlan_id = vlan_tx_tag_get_id(skb);
struct net_device *vlan_dev;
struct vlan_pcpu_stats *rx_stats;
vlan_dev = vlan_find_dev(skb->dev, vlan_proto, vlan_id);
if (!vlan_dev)
return false;
skb = *skbp = skb_share_check(skb, GFP_ATOMIC);
if (unlikely(!skb))
return false;
skb->dev = vlan_dev;
if (unlikely(skb->pkt_type == PACKET_OTHERHOST)) {
/* Our lower layer thinks this is not local, let's make sure.
* This allows the VLAN to have a different MAC than the
* underlying device, and still route correctly. */
if (ether_addr_equal_64bits(eth_hdr(skb)->h_dest, vlan_dev->dev_addr))
skb->pkt_type = PACKET_HOST;
}
if (!(vlan_dev_priv(vlan_dev)->flags & VLAN_FLAG_REORDER_HDR)) {
unsigned int offset = skb->data - skb_mac_header(skb);
/*
* vlan_insert_tag expect skb->data pointing to mac header.
* So change skb->data before calling it and change back to
* original position later
*/
skb_push(skb, offset);
skb = *skbp = vlan_insert_tag(skb, skb->vlan_proto,
skb->vlan_tci);
if (!skb)
return false;
skb_pull(skb, offset + VLAN_HLEN);
skb_reset_mac_len(skb);
}
skb->priority = vlan_get_ingress_priority(vlan_dev, skb->vlan_tci);
skb->vlan_tci = 0;
rx_stats = this_cpu_ptr(vlan_dev_priv(vlan_dev)->vlan_pcpu_stats);
u64_stats_update_begin(&rx_stats->syncp);
rx_stats->rx_packets++;
rx_stats->rx_bytes += skb->len;
if (skb->pkt_type == PACKET_MULTICAST)
rx_stats->rx_multicast++;
u64_stats_update_end(&rx_stats->syncp);
return true;
}
/* Must be invoked with rcu_read_lock. */
struct net_device *__vlan_find_dev_deep_rcu(struct net_device *dev,
__be16 vlan_proto, u16 vlan_id)
{
struct vlan_info *vlan_info = rcu_dereference(dev->vlan_info);
if (vlan_info) {
return vlan_group_get_device(&vlan_info->grp,
vlan_proto, vlan_id);
} else {
/*
* Lower devices of master uppers (bonding, team) do not have
* grp assigned to themselves. Grp is assigned to upper device
* instead.
*/
struct net_device *upper_dev;
upper_dev = netdev_master_upper_dev_get_rcu(dev);
if (upper_dev)
return __vlan_find_dev_deep_rcu(upper_dev,
vlan_proto, vlan_id);
}
return NULL;
}
EXPORT_SYMBOL(__vlan_find_dev_deep_rcu);
struct net_device *vlan_dev_real_dev(const struct net_device *dev)
{
struct net_device *ret = vlan_dev_priv(dev)->real_dev;
while (is_vlan_dev(ret))
ret = vlan_dev_priv(ret)->real_dev;
return ret;
}
EXPORT_SYMBOL(vlan_dev_real_dev);
u16 vlan_dev_vlan_id(const struct net_device *dev)
{
return vlan_dev_priv(dev)->vlan_id;
}
EXPORT_SYMBOL(vlan_dev_vlan_id);
__be16 vlan_dev_vlan_proto(const struct net_device *dev)
{
return vlan_dev_priv(dev)->vlan_proto;
}
EXPORT_SYMBOL(vlan_dev_vlan_proto);
/*
* vlan info and vid list
*/
static void vlan_group_free(struct vlan_group *grp)
{
int i, j;
for (i = 0; i < VLAN_PROTO_NUM; i++)
for (j = 0; j < VLAN_GROUP_ARRAY_SPLIT_PARTS; j++)
kfree(grp->vlan_devices_arrays[i][j]);
}
static void vlan_info_free(struct vlan_info *vlan_info)
{
vlan_group_free(&vlan_info->grp);
kfree(vlan_info);
}
static void vlan_info_rcu_free(struct rcu_head *rcu)
{
vlan_info_free(container_of(rcu, struct vlan_info, rcu));
}
static struct vlan_info *vlan_info_alloc(struct net_device *dev)
{
struct vlan_info *vlan_info;
vlan_info = kzalloc(sizeof(struct vlan_info), GFP_KERNEL);
if (!vlan_info)
return NULL;
vlan_info->real_dev = dev;
INIT_LIST_HEAD(&vlan_info->vid_list);
return vlan_info;
}
struct vlan_vid_info {
struct list_head list;
__be16 proto;
u16 vid;
int refcount;
};
static bool vlan_hw_filter_capable(const struct net_device *dev,
const struct vlan_vid_info *vid_info)
{
if (vid_info->proto == htons(ETH_P_8021Q) &&
dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
return true;
if (vid_info->proto == htons(ETH_P_8021AD) &&
dev->features & NETIF_F_HW_VLAN_STAG_FILTER)
return true;
return false;
}
static struct vlan_vid_info *vlan_vid_info_get(struct vlan_info *vlan_info,
__be16 proto, u16 vid)
{
struct vlan_vid_info *vid_info;
list_for_each_entry(vid_info, &vlan_info->vid_list, list) {
if (vid_info->proto == proto && vid_info->vid == vid)
return vid_info;
}
return NULL;
}
static struct vlan_vid_info *vlan_vid_info_alloc(__be16 proto, u16 vid)
{
struct vlan_vid_info *vid_info;
vid_info = kzalloc(sizeof(struct vlan_vid_info), GFP_KERNEL);
if (!vid_info)
return NULL;
vid_info->proto = proto;
vid_info->vid = vid;
return vid_info;
}
static int __vlan_vid_add(struct vlan_info *vlan_info, __be16 proto, u16 vid,
struct vlan_vid_info **pvid_info)
{
struct net_device *dev = vlan_info->real_dev;
const struct net_device_ops *ops = dev->netdev_ops;
struct vlan_vid_info *vid_info;
int err;
vid_info = vlan_vid_info_alloc(proto, vid);
if (!vid_info)
return -ENOMEM;
if (vlan_hw_filter_capable(dev, vid_info)) {
err = ops->ndo_vlan_rx_add_vid(dev, proto, vid);
if (err) {
kfree(vid_info);
return err;
}
}
list_add(&vid_info->list, &vlan_info->vid_list);
vlan_info->nr_vids++;
*pvid_info = vid_info;
return 0;
}
int vlan_vid_add(struct net_device *dev, __be16 proto, u16 vid)
{
struct vlan_info *vlan_info;
struct vlan_vid_info *vid_info;
bool vlan_info_created = false;
int err;
ASSERT_RTNL();
vlan_info = rtnl_dereference(dev->vlan_info);
if (!vlan_info) {
vlan_info = vlan_info_alloc(dev);
if (!vlan_info)
return -ENOMEM;
vlan_info_created = true;
}
vid_info = vlan_vid_info_get(vlan_info, proto, vid);
if (!vid_info) {
err = __vlan_vid_add(vlan_info, proto, vid, &vid_info);
if (err)
goto out_free_vlan_info;
}
vid_info->refcount++;
if (vlan_info_created)
rcu_assign_pointer(dev->vlan_info, vlan_info);
return 0;
out_free_vlan_info:
if (vlan_info_created)
kfree(vlan_info);
return err;
}
EXPORT_SYMBOL(vlan_vid_add);
static void __vlan_vid_del(struct vlan_info *vlan_info,
struct vlan_vid_info *vid_info)
{
struct net_device *dev = vlan_info->real_dev;
const struct net_device_ops *ops = dev->netdev_ops;
__be16 proto = vid_info->proto;
u16 vid = vid_info->vid;
int err;
if (vlan_hw_filter_capable(dev, vid_info)) {
err = ops->ndo_vlan_rx_kill_vid(dev, proto, vid);
if (err) {
pr_warn("failed to kill vid %04x/%d for device %s\n",
proto, vid, dev->name);
}
}
list_del(&vid_info->list);
kfree(vid_info);
vlan_info->nr_vids--;
}
void vlan_vid_del(struct net_device *dev, __be16 proto, u16 vid)
{
struct vlan_info *vlan_info;
struct vlan_vid_info *vid_info;
ASSERT_RTNL();
vlan_info = rtnl_dereference(dev->vlan_info);
if (!vlan_info)
return;
vid_info = vlan_vid_info_get(vlan_info, proto, vid);
if (!vid_info)
return;
vid_info->refcount--;
if (vid_info->refcount == 0) {
__vlan_vid_del(vlan_info, vid_info);
if (vlan_info->nr_vids == 0) {
RCU_INIT_POINTER(dev->vlan_info, NULL);
call_rcu(&vlan_info->rcu, vlan_info_rcu_free);
}
}
}
EXPORT_SYMBOL(vlan_vid_del);
int vlan_vids_add_by_dev(struct net_device *dev,
const struct net_device *by_dev)
{
struct vlan_vid_info *vid_info;
struct vlan_info *vlan_info;
int err;
ASSERT_RTNL();
vlan_info = rtnl_dereference(by_dev->vlan_info);
if (!vlan_info)
return 0;
list_for_each_entry(vid_info, &vlan_info->vid_list, list) {
err = vlan_vid_add(dev, vid_info->proto, vid_info->vid);
if (err)
goto unwind;
}
return 0;
unwind:
list_for_each_entry_continue_reverse(vid_info,
&vlan_info->vid_list,
list) {
vlan_vid_del(dev, vid_info->proto, vid_info->vid);
}
return err;
}
EXPORT_SYMBOL(vlan_vids_add_by_dev);
void vlan_vids_del_by_dev(struct net_device *dev,
const struct net_device *by_dev)
{
struct vlan_vid_info *vid_info;
struct vlan_info *vlan_info;
ASSERT_RTNL();
vlan_info = rtnl_dereference(by_dev->vlan_info);
if (!vlan_info)
return;
list_for_each_entry(vid_info, &vlan_info->vid_list, list)
vlan_vid_del(dev, vid_info->proto, vid_info->vid);
}
EXPORT_SYMBOL(vlan_vids_del_by_dev);
bool vlan_uses_dev(const struct net_device *dev)
{
struct vlan_info *vlan_info;
ASSERT_RTNL();
vlan_info = rtnl_dereference(dev->vlan_info);
if (!vlan_info)
return false;
return vlan_info->grp.nr_vlan_devs ? true : false;
}
EXPORT_SYMBOL(vlan_uses_dev);
| gpl-2.0 |
fkfk/sc02b_kernel | sound/soc/imx/imx-pcm-fiq.c | 748 | 7455 | /*
* imx-pcm-fiq.c -- ALSA Soc Audio Layer
*
* Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
*
* This code is based on code copyrighted by Freescale,
* Liam Girdwood, Javier Martin and probably others.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/fiq.h>
#include <mach/ssi.h>
#include "imx-ssi.h"
struct imx_pcm_runtime_data {
int period;
int periods;
unsigned long offset;
unsigned long last_offset;
unsigned long size;
struct hrtimer hrt;
int poll_time_ns;
struct snd_pcm_substream *substream;
atomic_t running;
};
static enum hrtimer_restart snd_hrtimer_callback(struct hrtimer *hrt)
{
struct imx_pcm_runtime_data *iprtd =
container_of(hrt, struct imx_pcm_runtime_data, hrt);
struct snd_pcm_substream *substream = iprtd->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
struct pt_regs regs;
unsigned long delta;
if (!atomic_read(&iprtd->running))
return HRTIMER_NORESTART;
get_fiq_regs(®s);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
iprtd->offset = regs.ARM_r8 & 0xffff;
else
iprtd->offset = regs.ARM_r9 & 0xffff;
/* How much data have we transferred since the last period report? */
if (iprtd->offset >= iprtd->last_offset)
delta = iprtd->offset - iprtd->last_offset;
else
delta = runtime->buffer_size + iprtd->offset
- iprtd->last_offset;
/* If we've transferred at least a period then report it and
* reset our poll time */
if (delta >= iprtd->period) {
snd_pcm_period_elapsed(substream);
iprtd->last_offset = iprtd->offset;
}
hrtimer_forward_now(hrt, ns_to_ktime(iprtd->poll_time_ns));
return HRTIMER_RESTART;
}
static struct fiq_handler fh = {
.name = DRV_NAME,
};
static int snd_imx_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
iprtd->size = params_buffer_bytes(params);
iprtd->periods = params_periods(params);
iprtd->period = params_period_bytes(params) ;
iprtd->offset = 0;
iprtd->last_offset = 0;
iprtd->poll_time_ns = 1000000000 / params_rate(params) *
params_period_size(params);
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
return 0;
}
static int snd_imx_pcm_prepare(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
struct pt_regs regs;
get_fiq_regs(®s);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16;
else
regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16;
set_fiq_regs(®s);
return 0;
}
static int fiq_enable;
static int imx_pcm_fiq;
static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
atomic_set(&iprtd->running, 1);
hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
HRTIMER_MODE_REL);
if (++fiq_enable == 1)
enable_fiq(imx_pcm_fiq);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
atomic_set(&iprtd->running, 0);
if (--fiq_enable == 0)
disable_fiq(imx_pcm_fiq);
break;
default:
return -EINVAL;
}
return 0;
}
static snd_pcm_uframes_t snd_imx_pcm_pointer(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
return bytes_to_frames(substream->runtime, iprtd->offset);
}
static struct snd_pcm_hardware snd_imx_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
.period_bytes_min = 128,
.period_bytes_max = 16 * 1024,
.periods_min = 4,
.periods_max = 255,
.fifo_size = 0,
};
static int snd_imx_open(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd;
int ret;
iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
runtime->private_data = iprtd;
iprtd->substream = substream;
atomic_set(&iprtd->running, 0);
hrtimer_init(&iprtd->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
iprtd->hrt.function = snd_hrtimer_callback;
ret = snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
return ret;
snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
return 0;
}
static int snd_imx_close(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
hrtimer_cancel(&iprtd->hrt);
kfree(iprtd);
return 0;
}
static struct snd_pcm_ops imx_pcm_ops = {
.open = snd_imx_open,
.close = snd_imx_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = snd_imx_pcm_hw_params,
.prepare = snd_imx_pcm_prepare,
.trigger = snd_imx_pcm_trigger,
.pointer = snd_imx_pcm_pointer,
.mmap = snd_imx_pcm_mmap,
};
static int imx_pcm_fiq_new(struct snd_card *card, struct snd_soc_dai *dai,
struct snd_pcm *pcm)
{
int ret;
ret = imx_pcm_new(card, dai, pcm);
if (ret)
return ret;
if (dai->playback.channels_min) {
struct snd_pcm_substream *substream =
pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
struct snd_dma_buffer *buf = &substream->dma_buffer;
imx_ssi_fiq_tx_buffer = (unsigned long)buf->area;
}
if (dai->capture.channels_min) {
struct snd_pcm_substream *substream =
pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
struct snd_dma_buffer *buf = &substream->dma_buffer;
imx_ssi_fiq_rx_buffer = (unsigned long)buf->area;
}
set_fiq_handler(&imx_ssi_fiq_start,
&imx_ssi_fiq_end - &imx_ssi_fiq_start);
return 0;
}
static struct snd_soc_platform imx_soc_platform_fiq = {
.pcm_ops = &imx_pcm_ops,
.pcm_new = imx_pcm_fiq_new,
.pcm_free = imx_pcm_free,
};
struct snd_soc_platform *imx_ssi_fiq_init(struct platform_device *pdev,
struct imx_ssi *ssi)
{
int ret = 0;
ret = claim_fiq(&fh);
if (ret) {
dev_err(&pdev->dev, "failed to claim fiq: %d", ret);
return ERR_PTR(ret);
}
mxc_set_irq_fiq(ssi->irq, 1);
imx_pcm_fiq = ssi->irq;
imx_ssi_fiq_base = (unsigned long)ssi->base;
ssi->dma_params_tx.burstsize = 4;
ssi->dma_params_rx.burstsize = 6;
return &imx_soc_platform_fiq;
}
void imx_ssi_fiq_exit(struct platform_device *pdev,
struct imx_ssi *ssi)
{
mxc_set_irq_fiq(ssi->irq, 0);
release_fiq(&fh);
}
| gpl-2.0 |
umaro/UmaroKernel | arch/sh/boards/mach-cayman/setup.c | 1516 | 5571 | /*
* arch/sh/mach-cayman/setup.c
*
* SH5 Cayman support
*
* Copyright (C) 2002 David J. Mckay & Benedict Gaster
* Copyright (C) 2003 - 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <cpu/irq.h>
/*
* Platform Dependent Interrupt Priorities.
*/
/* Using defaults defined in irq.h */
#define RES NO_PRIORITY /* Disabled */
#define IR0 IRL0_PRIORITY /* IRLs */
#define IR1 IRL1_PRIORITY
#define IR2 IRL2_PRIORITY
#define IR3 IRL3_PRIORITY
#define PCA INTA_PRIORITY /* PCI Ints */
#define PCB INTB_PRIORITY
#define PCC INTC_PRIORITY
#define PCD INTD_PRIORITY
#define SER TOP_PRIORITY
#define ERR TOP_PRIORITY
#define PW0 TOP_PRIORITY
#define PW1 TOP_PRIORITY
#define PW2 TOP_PRIORITY
#define PW3 TOP_PRIORITY
#define DM0 NO_PRIORITY /* DMA Ints */
#define DM1 NO_PRIORITY
#define DM2 NO_PRIORITY
#define DM3 NO_PRIORITY
#define DAE NO_PRIORITY
#define TU0 TIMER_PRIORITY /* TMU Ints */
#define TU1 NO_PRIORITY
#define TU2 NO_PRIORITY
#define TI2 NO_PRIORITY
#define ATI NO_PRIORITY /* RTC Ints */
#define PRI NO_PRIORITY
#define CUI RTC_PRIORITY
#define ERI SCIF_PRIORITY /* SCIF Ints */
#define RXI SCIF_PRIORITY
#define BRI SCIF_PRIORITY
#define TXI SCIF_PRIORITY
#define ITI TOP_PRIORITY /* WDT Ints */
/* Setup for the SMSC FDC37C935 */
#define SMSC_SUPERIO_BASE 0x04000000
#define SMSC_CONFIG_PORT_ADDR 0x3f0
#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
#define SMSC_DATA_PORT_ADDR 0x3f1
#define SMSC_ENTER_CONFIG_KEY 0x55
#define SMSC_EXIT_CONFIG_KEY 0xaa
#define SMCS_LOGICAL_DEV_INDEX 0x07
#define SMSC_DEVICE_ID_INDEX 0x20
#define SMSC_DEVICE_REV_INDEX 0x21
#define SMSC_ACTIVATE_INDEX 0x30
#define SMSC_PRIMARY_BASE_INDEX 0x60
#define SMSC_SECONDARY_BASE_INDEX 0x62
#define SMSC_PRIMARY_INT_INDEX 0x70
#define SMSC_SECONDARY_INT_INDEX 0x72
#define SMSC_IDE1_DEVICE 1
#define SMSC_KEYBOARD_DEVICE 7
#define SMSC_CONFIG_REGISTERS 8
#define SMSC_SUPERIO_READ_INDEXED(index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
inb(SMSC_DATA_PORT_ADDR); })
#define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
outb((val), SMSC_DATA_PORT_ADDR); })
#define IDE1_PRIMARY_BASE 0x01f0
#define IDE1_SECONDARY_BASE 0x03f6
unsigned long smsc_superio_virt;
int platform_int_priority[NR_INTC_IRQS] = {
IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ 0- 7 */
RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ 8-15 */
PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
};
static int __init smsc_superio_setup(void)
{
unsigned char devid, devrev;
smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
if (!smsc_superio_virt) {
panic("Unable to remap SMSC SuperIO\n");
}
/* Initially the chip is in run state */
/* Put it into configuration state */
outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
/* Read device ID info */
devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
/* Select the keyboard device */
SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* Select the interrupts */
/* On a PC keyboard is IRQ1, mouse is IRQ12 */
SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
#ifdef CONFIG_IDE
/*
* Only IDE1 exists on the Cayman
*/
/* Power it on */
SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22);
SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8,
SMSC_PRIMARY_BASE_INDEX + 0);
SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff,
SMSC_PRIMARY_BASE_INDEX + 1);
SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8,
SMSC_SECONDARY_BASE_INDEX + 0);
SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff,
SMSC_SECONDARY_BASE_INDEX + 1);
SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX);
SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS,
SMCS_LOGICAL_DEV_INDEX);
SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
#endif
/* Exit the configuration state */
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
return 0;
}
__initcall(smsc_superio_setup);
static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len)
{
if (port < 0x400) {
extern unsigned long smsc_superio_virt;
return (void __iomem *)((port << 2) | smsc_superio_virt);
}
return (void __iomem *)port;
}
extern void init_cayman_irq(void);
static struct sh_machine_vector mv_cayman __initmv = {
.mv_name = "Hitachi Cayman",
.mv_nr_irqs = 64,
.mv_ioport_map = cayman_ioport_map,
.mv_init_irq = init_cayman_irq,
};
| gpl-2.0 |
ffosilva/kernel | drivers/infiniband/hw/qib/qib_fs.c | 2284 | 14909 | /*
* Copyright (c) 2012 Intel Corporation. All rights reserved.
* Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
* Copyright (c) 2006 PathScale, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/mount.h>
#include <linux/pagemap.h>
#include <linux/init.h>
#include <linux/namei.h>
#include "qib.h"
#define QIBFS_MAGIC 0x726a77
static struct super_block *qib_super;
#define private2dd(file) (file_inode(file)->i_private)
static int qibfs_mknod(struct inode *dir, struct dentry *dentry,
umode_t mode, const struct file_operations *fops,
void *data)
{
int error;
struct inode *inode = new_inode(dir->i_sb);
if (!inode) {
error = -EPERM;
goto bail;
}
inode->i_ino = get_next_ino();
inode->i_mode = mode;
inode->i_uid = GLOBAL_ROOT_UID;
inode->i_gid = GLOBAL_ROOT_GID;
inode->i_blocks = 0;
inode->i_atime = CURRENT_TIME;
inode->i_mtime = inode->i_atime;
inode->i_ctime = inode->i_atime;
inode->i_private = data;
if (S_ISDIR(mode)) {
inode->i_op = &simple_dir_inode_operations;
inc_nlink(inode);
inc_nlink(dir);
}
inode->i_fop = fops;
d_instantiate(dentry, inode);
error = 0;
bail:
return error;
}
static int create_file(const char *name, umode_t mode,
struct dentry *parent, struct dentry **dentry,
const struct file_operations *fops, void *data)
{
int error;
*dentry = NULL;
mutex_lock(&parent->d_inode->i_mutex);
*dentry = lookup_one_len(name, parent, strlen(name));
if (!IS_ERR(*dentry))
error = qibfs_mknod(parent->d_inode, *dentry,
mode, fops, data);
else
error = PTR_ERR(*dentry);
mutex_unlock(&parent->d_inode->i_mutex);
return error;
}
static ssize_t driver_stats_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
return simple_read_from_buffer(buf, count, ppos, &qib_stats,
sizeof qib_stats);
}
/*
* driver stats field names, one line per stat, single string. Used by
* programs like ipathstats to print the stats in a way which works for
* different versions of drivers, without changing program source.
* if qlogic_ib_stats changes, this needs to change. Names need to be
* 12 chars or less (w/o newline), for proper display by ipathstats utility.
*/
static const char qib_statnames[] =
"KernIntr\n"
"ErrorIntr\n"
"Tx_Errs\n"
"Rcv_Errs\n"
"H/W_Errs\n"
"NoPIOBufs\n"
"CtxtsOpen\n"
"RcvLen_Errs\n"
"EgrBufFull\n"
"EgrHdrFull\n"
;
static ssize_t driver_names_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
return simple_read_from_buffer(buf, count, ppos, qib_statnames,
sizeof qib_statnames - 1); /* no null */
}
static const struct file_operations driver_ops[] = {
{ .read = driver_stats_read, .llseek = generic_file_llseek, },
{ .read = driver_names_read, .llseek = generic_file_llseek, },
};
/* read the per-device counters */
static ssize_t dev_counters_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
u64 *counters;
size_t avail;
struct qib_devdata *dd = private2dd(file);
avail = dd->f_read_cntrs(dd, *ppos, NULL, &counters);
return simple_read_from_buffer(buf, count, ppos, counters, avail);
}
/* read the per-device counters */
static ssize_t dev_names_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
char *names;
size_t avail;
struct qib_devdata *dd = private2dd(file);
avail = dd->f_read_cntrs(dd, *ppos, &names, NULL);
return simple_read_from_buffer(buf, count, ppos, names, avail);
}
static const struct file_operations cntr_ops[] = {
{ .read = dev_counters_read, .llseek = generic_file_llseek, },
{ .read = dev_names_read, .llseek = generic_file_llseek, },
};
/*
* Could use file_inode(file)->i_ino to figure out which file,
* instead of separate routine for each, but for now, this works...
*/
/* read the per-port names (same for each port) */
static ssize_t portnames_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
char *names;
size_t avail;
struct qib_devdata *dd = private2dd(file);
avail = dd->f_read_portcntrs(dd, *ppos, 0, &names, NULL);
return simple_read_from_buffer(buf, count, ppos, names, avail);
}
/* read the per-port counters for port 1 (pidx 0) */
static ssize_t portcntrs_1_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
u64 *counters;
size_t avail;
struct qib_devdata *dd = private2dd(file);
avail = dd->f_read_portcntrs(dd, *ppos, 0, NULL, &counters);
return simple_read_from_buffer(buf, count, ppos, counters, avail);
}
/* read the per-port counters for port 2 (pidx 1) */
static ssize_t portcntrs_2_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
u64 *counters;
size_t avail;
struct qib_devdata *dd = private2dd(file);
avail = dd->f_read_portcntrs(dd, *ppos, 1, NULL, &counters);
return simple_read_from_buffer(buf, count, ppos, counters, avail);
}
static const struct file_operations portcntr_ops[] = {
{ .read = portnames_read, .llseek = generic_file_llseek, },
{ .read = portcntrs_1_read, .llseek = generic_file_llseek, },
{ .read = portcntrs_2_read, .llseek = generic_file_llseek, },
};
/*
* read the per-port QSFP data for port 1 (pidx 0)
*/
static ssize_t qsfp_1_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct qib_devdata *dd = private2dd(file);
char *tmp;
int ret;
tmp = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!tmp)
return -ENOMEM;
ret = qib_qsfp_dump(dd->pport, tmp, PAGE_SIZE);
if (ret > 0)
ret = simple_read_from_buffer(buf, count, ppos, tmp, ret);
kfree(tmp);
return ret;
}
/*
* read the per-port QSFP data for port 2 (pidx 1)
*/
static ssize_t qsfp_2_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct qib_devdata *dd = private2dd(file);
char *tmp;
int ret;
if (dd->num_pports < 2)
return -ENODEV;
tmp = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!tmp)
return -ENOMEM;
ret = qib_qsfp_dump(dd->pport + 1, tmp, PAGE_SIZE);
if (ret > 0)
ret = simple_read_from_buffer(buf, count, ppos, tmp, ret);
kfree(tmp);
return ret;
}
static const struct file_operations qsfp_ops[] = {
{ .read = qsfp_1_read, .llseek = generic_file_llseek, },
{ .read = qsfp_2_read, .llseek = generic_file_llseek, },
};
static ssize_t flash_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct qib_devdata *dd;
ssize_t ret;
loff_t pos;
char *tmp;
pos = *ppos;
if (pos < 0) {
ret = -EINVAL;
goto bail;
}
if (pos >= sizeof(struct qib_flash)) {
ret = 0;
goto bail;
}
if (count > sizeof(struct qib_flash) - pos)
count = sizeof(struct qib_flash) - pos;
tmp = kmalloc(count, GFP_KERNEL);
if (!tmp) {
ret = -ENOMEM;
goto bail;
}
dd = private2dd(file);
if (qib_eeprom_read(dd, pos, tmp, count)) {
qib_dev_err(dd, "failed to read from flash\n");
ret = -ENXIO;
goto bail_tmp;
}
if (copy_to_user(buf, tmp, count)) {
ret = -EFAULT;
goto bail_tmp;
}
*ppos = pos + count;
ret = count;
bail_tmp:
kfree(tmp);
bail:
return ret;
}
static ssize_t flash_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
struct qib_devdata *dd;
ssize_t ret;
loff_t pos;
char *tmp;
pos = *ppos;
if (pos != 0) {
ret = -EINVAL;
goto bail;
}
if (count != sizeof(struct qib_flash)) {
ret = -EINVAL;
goto bail;
}
tmp = kmalloc(count, GFP_KERNEL);
if (!tmp) {
ret = -ENOMEM;
goto bail;
}
if (copy_from_user(tmp, buf, count)) {
ret = -EFAULT;
goto bail_tmp;
}
dd = private2dd(file);
if (qib_eeprom_write(dd, pos, tmp, count)) {
ret = -ENXIO;
qib_dev_err(dd, "failed to write to flash\n");
goto bail_tmp;
}
*ppos = pos + count;
ret = count;
bail_tmp:
kfree(tmp);
bail:
return ret;
}
static const struct file_operations flash_ops = {
.read = flash_read,
.write = flash_write,
.llseek = default_llseek,
};
static int add_cntr_files(struct super_block *sb, struct qib_devdata *dd)
{
struct dentry *dir, *tmp;
char unit[10];
int ret, i;
/* create the per-unit directory */
snprintf(unit, sizeof unit, "%u", dd->unit);
ret = create_file(unit, S_IFDIR|S_IRUGO|S_IXUGO, sb->s_root, &dir,
&simple_dir_operations, dd);
if (ret) {
pr_err("create_file(%s) failed: %d\n", unit, ret);
goto bail;
}
/* create the files in the new directory */
ret = create_file("counters", S_IFREG|S_IRUGO, dir, &tmp,
&cntr_ops[0], dd);
if (ret) {
pr_err("create_file(%s/counters) failed: %d\n",
unit, ret);
goto bail;
}
ret = create_file("counter_names", S_IFREG|S_IRUGO, dir, &tmp,
&cntr_ops[1], dd);
if (ret) {
pr_err("create_file(%s/counter_names) failed: %d\n",
unit, ret);
goto bail;
}
ret = create_file("portcounter_names", S_IFREG|S_IRUGO, dir, &tmp,
&portcntr_ops[0], dd);
if (ret) {
pr_err("create_file(%s/%s) failed: %d\n",
unit, "portcounter_names", ret);
goto bail;
}
for (i = 1; i <= dd->num_pports; i++) {
char fname[24];
sprintf(fname, "port%dcounters", i);
/* create the files in the new directory */
ret = create_file(fname, S_IFREG|S_IRUGO, dir, &tmp,
&portcntr_ops[i], dd);
if (ret) {
pr_err("create_file(%s/%s) failed: %d\n",
unit, fname, ret);
goto bail;
}
if (!(dd->flags & QIB_HAS_QSFP))
continue;
sprintf(fname, "qsfp%d", i);
ret = create_file(fname, S_IFREG|S_IRUGO, dir, &tmp,
&qsfp_ops[i - 1], dd);
if (ret) {
pr_err("create_file(%s/%s) failed: %d\n",
unit, fname, ret);
goto bail;
}
}
ret = create_file("flash", S_IFREG|S_IWUSR|S_IRUGO, dir, &tmp,
&flash_ops, dd);
if (ret)
pr_err("create_file(%s/flash) failed: %d\n",
unit, ret);
bail:
return ret;
}
static int remove_file(struct dentry *parent, char *name)
{
struct dentry *tmp;
int ret;
tmp = lookup_one_len(name, parent, strlen(name));
if (IS_ERR(tmp)) {
ret = PTR_ERR(tmp);
goto bail;
}
spin_lock(&tmp->d_lock);
if (!(d_unhashed(tmp) && tmp->d_inode)) {
dget_dlock(tmp);
__d_drop(tmp);
spin_unlock(&tmp->d_lock);
simple_unlink(parent->d_inode, tmp);
} else {
spin_unlock(&tmp->d_lock);
}
ret = 0;
bail:
/*
* We don't expect clients to care about the return value, but
* it's there if they need it.
*/
return ret;
}
static int remove_device_files(struct super_block *sb,
struct qib_devdata *dd)
{
struct dentry *dir, *root;
char unit[10];
int ret, i;
root = dget(sb->s_root);
mutex_lock(&root->d_inode->i_mutex);
snprintf(unit, sizeof unit, "%u", dd->unit);
dir = lookup_one_len(unit, root, strlen(unit));
if (IS_ERR(dir)) {
ret = PTR_ERR(dir);
pr_err("Lookup of %s failed\n", unit);
goto bail;
}
remove_file(dir, "counters");
remove_file(dir, "counter_names");
remove_file(dir, "portcounter_names");
for (i = 0; i < dd->num_pports; i++) {
char fname[24];
sprintf(fname, "port%dcounters", i + 1);
remove_file(dir, fname);
if (dd->flags & QIB_HAS_QSFP) {
sprintf(fname, "qsfp%d", i + 1);
remove_file(dir, fname);
}
}
remove_file(dir, "flash");
d_delete(dir);
ret = simple_rmdir(root->d_inode, dir);
bail:
mutex_unlock(&root->d_inode->i_mutex);
dput(root);
return ret;
}
/*
* This fills everything in when the fs is mounted, to handle umount/mount
* after device init. The direct add_cntr_files() call handles adding
* them from the init code, when the fs is already mounted.
*/
static int qibfs_fill_super(struct super_block *sb, void *data, int silent)
{
struct qib_devdata *dd, *tmp;
unsigned long flags;
int ret;
static struct tree_descr files[] = {
[2] = {"driver_stats", &driver_ops[0], S_IRUGO},
[3] = {"driver_stats_names", &driver_ops[1], S_IRUGO},
{""},
};
ret = simple_fill_super(sb, QIBFS_MAGIC, files);
if (ret) {
pr_err("simple_fill_super failed: %d\n", ret);
goto bail;
}
spin_lock_irqsave(&qib_devs_lock, flags);
list_for_each_entry_safe(dd, tmp, &qib_dev_list, list) {
spin_unlock_irqrestore(&qib_devs_lock, flags);
ret = add_cntr_files(sb, dd);
if (ret)
goto bail;
spin_lock_irqsave(&qib_devs_lock, flags);
}
spin_unlock_irqrestore(&qib_devs_lock, flags);
bail:
return ret;
}
static struct dentry *qibfs_mount(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data)
{
struct dentry *ret;
ret = mount_single(fs_type, flags, data, qibfs_fill_super);
if (!IS_ERR(ret))
qib_super = ret->d_sb;
return ret;
}
static void qibfs_kill_super(struct super_block *s)
{
kill_litter_super(s);
qib_super = NULL;
}
int qibfs_add(struct qib_devdata *dd)
{
int ret;
/*
* On first unit initialized, qib_super will not yet exist
* because nobody has yet tried to mount the filesystem, so
* we can't consider that to be an error; if an error occurs
* during the mount, that will get a complaint, so this is OK.
* add_cntr_files() for all units is done at mount from
* qibfs_fill_super(), so one way or another, everything works.
*/
if (qib_super == NULL)
ret = 0;
else
ret = add_cntr_files(qib_super, dd);
return ret;
}
int qibfs_remove(struct qib_devdata *dd)
{
int ret = 0;
if (qib_super)
ret = remove_device_files(qib_super, dd);
return ret;
}
static struct file_system_type qibfs_fs_type = {
.owner = THIS_MODULE,
.name = "ipathfs",
.mount = qibfs_mount,
.kill_sb = qibfs_kill_super,
};
MODULE_ALIAS_FS("ipathfs");
int __init qib_init_qibfs(void)
{
return register_filesystem(&qibfs_fs_type);
}
int __exit qib_exit_qibfs(void)
{
return unregister_filesystem(&qibfs_fs_type);
}
| gpl-2.0 |
crimeofheart/android_kernel_samsung_smdk4210 | arch/arm/kernel/tcm.c | 2540 | 6677 | /*
* Copyright (C) 2008-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* TCM memory handling for ARM systems
*
* Author: Linus Walleij <linus.walleij@stericsson.com>
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/genalloc.h>
#include <linux/string.h> /* memcpy */
#include <asm/cputype.h>
#include <asm/mach/map.h>
#include <asm/memory.h>
#include "tcm.h"
static struct gen_pool *tcm_pool;
/* TCM section definitions from the linker */
extern char __itcm_start, __sitcm_text, __eitcm_text;
extern char __dtcm_start, __sdtcm_data, __edtcm_data;
/* These will be increased as we run */
u32 dtcm_end = DTCM_OFFSET;
u32 itcm_end = ITCM_OFFSET;
/*
* TCM memory resources
*/
static struct resource dtcm_res = {
.name = "DTCM RAM",
.start = DTCM_OFFSET,
.end = DTCM_OFFSET,
.flags = IORESOURCE_MEM
};
static struct resource itcm_res = {
.name = "ITCM RAM",
.start = ITCM_OFFSET,
.end = ITCM_OFFSET,
.flags = IORESOURCE_MEM
};
static struct map_desc dtcm_iomap[] __initdata = {
{
.virtual = DTCM_OFFSET,
.pfn = __phys_to_pfn(DTCM_OFFSET),
.length = 0,
.type = MT_MEMORY_DTCM
}
};
static struct map_desc itcm_iomap[] __initdata = {
{
.virtual = ITCM_OFFSET,
.pfn = __phys_to_pfn(ITCM_OFFSET),
.length = 0,
.type = MT_MEMORY_ITCM
}
};
/*
* Allocate a chunk of TCM memory
*/
void *tcm_alloc(size_t len)
{
unsigned long vaddr;
if (!tcm_pool)
return NULL;
vaddr = gen_pool_alloc(tcm_pool, len);
if (!vaddr)
return NULL;
return (void *) vaddr;
}
EXPORT_SYMBOL(tcm_alloc);
/*
* Free a chunk of TCM memory
*/
void tcm_free(void *addr, size_t len)
{
gen_pool_free(tcm_pool, (unsigned long) addr, len);
}
EXPORT_SYMBOL(tcm_free);
static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
u32 *offset)
{
const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
256, 512, 1024, -1, -1, -1, -1 };
u32 tcm_region;
int tcm_size;
/*
* If there are more than one TCM bank of this type,
* select the TCM bank to operate on in the TCM selection
* register.
*/
if (banks > 1)
asm("mcr p15, 0, %0, c9, c2, 0"
: /* No output operands */
: "r" (bank));
/* Read the special TCM region register c9, 0 */
if (!type)
asm("mrc p15, 0, %0, c9, c1, 0"
: "=r" (tcm_region));
else
asm("mrc p15, 0, %0, c9, c1, 1"
: "=r" (tcm_region));
tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
if (tcm_size < 0) {
pr_err("CPU: %sTCM%d of unknown size\n",
type ? "I" : "D", bank);
return -EINVAL;
} else if (tcm_size > 32) {
pr_err("CPU: %sTCM%d larger than 32k found\n",
type ? "I" : "D", bank);
return -EINVAL;
} else {
pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
type ? "I" : "D",
bank,
tcm_size,
(tcm_region & 0xfffff000U),
(tcm_region & 1) ? "" : "not ");
}
/* Force move the TCM bank to where we want it, enable */
tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
if (!type)
asm("mcr p15, 0, %0, c9, c1, 0"
: /* No output operands */
: "r" (tcm_region));
else
asm("mcr p15, 0, %0, c9, c1, 1"
: /* No output operands */
: "r" (tcm_region));
/* Increase offset */
*offset += (tcm_size << 10);
pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
type ? "I" : "D",
bank,
tcm_size,
(tcm_region & 0xfffff000U));
return 0;
}
/*
* This initializes the TCM memory
*/
void __init tcm_init(void)
{
u32 tcm_status = read_cpuid_tcmstatus();
u8 dtcm_banks = (tcm_status >> 16) & 0x03;
u8 itcm_banks = (tcm_status & 0x03);
char *start;
char *end;
char *ram;
int ret;
int i;
/* Setup DTCM if present */
if (dtcm_banks > 0) {
for (i = 0; i < dtcm_banks; i++) {
ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
if (ret)
return;
}
dtcm_res.end = dtcm_end - 1;
request_resource(&iomem_resource, &dtcm_res);
dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
iotable_init(dtcm_iomap, 1);
/* Copy data from RAM to DTCM */
start = &__sdtcm_data;
end = &__edtcm_data;
ram = &__dtcm_start;
/* This means you compiled more code than fits into DTCM */
BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET));
memcpy(start, ram, (end-start));
pr_debug("CPU DTCM: copied data from %p - %p\n", start, end);
}
/* Setup ITCM if present */
if (itcm_banks > 0) {
for (i = 0; i < itcm_banks; i++) {
ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
if (ret)
return;
}
itcm_res.end = itcm_end - 1;
request_resource(&iomem_resource, &itcm_res);
itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
iotable_init(itcm_iomap, 1);
/* Copy code from RAM to ITCM */
start = &__sitcm_text;
end = &__eitcm_text;
ram = &__itcm_start;
/* This means you compiled more code than fits into ITCM */
BUG_ON((end - start) > (itcm_end - ITCM_OFFSET));
memcpy(start, ram, (end-start));
pr_debug("CPU ITCM: copied code from %p - %p\n", start, end);
}
}
/*
* This creates the TCM memory pool and has to be done later,
* during the core_initicalls, since the allocator is not yet
* up and running when the first initialization runs.
*/
static int __init setup_tcm_pool(void)
{
u32 tcm_status = read_cpuid_tcmstatus();
u32 dtcm_pool_start = (u32) &__edtcm_data;
u32 itcm_pool_start = (u32) &__eitcm_text;
int ret;
/*
* Set up malloc pool, 2^2 = 4 bytes granularity since
* the TCM is sometimes just 4 KiB. NB: pages and cache
* line alignments does not matter in TCM!
*/
tcm_pool = gen_pool_create(2, -1);
pr_debug("Setting up TCM memory pool\n");
/* Add the rest of DTCM to the TCM pool */
if (tcm_status & (0x03 << 16)) {
if (dtcm_pool_start < dtcm_end) {
ret = gen_pool_add(tcm_pool, dtcm_pool_start,
dtcm_end - dtcm_pool_start, -1);
if (ret) {
pr_err("CPU DTCM: could not add DTCM " \
"remainder to pool!\n");
return ret;
}
pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
"the TCM memory pool\n",
dtcm_end - dtcm_pool_start,
dtcm_pool_start);
}
}
/* Add the rest of ITCM to the TCM pool */
if (tcm_status & 0x03) {
if (itcm_pool_start < itcm_end) {
ret = gen_pool_add(tcm_pool, itcm_pool_start,
itcm_end - itcm_pool_start, -1);
if (ret) {
pr_err("CPU ITCM: could not add ITCM " \
"remainder to pool!\n");
return ret;
}
pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
"the TCM memory pool\n",
itcm_end - itcm_pool_start,
itcm_pool_start);
}
}
return 0;
}
core_initcall(setup_tcm_pool);
| gpl-2.0 |
S34Qu4K3/P6-U06-JellyBean-Kernel-3.0.8---China-Version | drivers/staging/gma500/psb_intel_opregion.c | 2540 | 2323 | /*
* Copyright 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "psb_drv.h"
struct opregion_header {
u8 signature[16];
u32 size;
u32 opregion_ver;
u8 bios_ver[32];
u8 vbios_ver[16];
u8 driver_ver[16];
u32 mboxes;
u8 reserved[164];
} __attribute__((packed));
struct opregion_apci {
/*FIXME: add it later*/
} __attribute__((packed));
struct opregion_swsci {
/*FIXME: add it later*/
} __attribute__((packed));
struct opregion_acpi {
/*FIXME: add it later*/
} __attribute__((packed));
int psb_intel_opregion_init(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
/*struct psb_intel_opregion * opregion = &dev_priv->opregion;*/
u32 opregion_phy;
void *base;
u32 *lid_state;
dev_priv->lid_state = NULL;
pci_read_config_dword(dev->pdev, 0xfc, &opregion_phy);
if (opregion_phy == 0) {
DRM_DEBUG("Opregion not supported, won't support lid-switch\n");
return -ENOTSUPP;
}
DRM_DEBUG("OpRegion detected at 0x%8x\n", opregion_phy);
base = ioremap(opregion_phy, 8*1024);
if (!base)
return -ENOMEM;
lid_state = base + 0x01ac;
DRM_DEBUG("Lid switch state 0x%08x\n", *lid_state);
dev_priv->lid_state = lid_state;
dev_priv->lid_last_state = *lid_state;
return 0;
}
| gpl-2.0 |
mrg666/android_kernel_shooter | drivers/staging/gma500/psb_intel_opregion.c | 2540 | 2323 | /*
* Copyright 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "psb_drv.h"
struct opregion_header {
u8 signature[16];
u32 size;
u32 opregion_ver;
u8 bios_ver[32];
u8 vbios_ver[16];
u8 driver_ver[16];
u32 mboxes;
u8 reserved[164];
} __attribute__((packed));
struct opregion_apci {
/*FIXME: add it later*/
} __attribute__((packed));
struct opregion_swsci {
/*FIXME: add it later*/
} __attribute__((packed));
struct opregion_acpi {
/*FIXME: add it later*/
} __attribute__((packed));
int psb_intel_opregion_init(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
/*struct psb_intel_opregion * opregion = &dev_priv->opregion;*/
u32 opregion_phy;
void *base;
u32 *lid_state;
dev_priv->lid_state = NULL;
pci_read_config_dword(dev->pdev, 0xfc, &opregion_phy);
if (opregion_phy == 0) {
DRM_DEBUG("Opregion not supported, won't support lid-switch\n");
return -ENOTSUPP;
}
DRM_DEBUG("OpRegion detected at 0x%8x\n", opregion_phy);
base = ioremap(opregion_phy, 8*1024);
if (!base)
return -ENOMEM;
lid_state = base + 0x01ac;
DRM_DEBUG("Lid switch state 0x%08x\n", *lid_state);
dev_priv->lid_state = lid_state;
dev_priv->lid_last_state = *lid_state;
return 0;
}
| gpl-2.0 |
Blechd0se/mako_kernel | arch/alpha/kernel/sys_titan.c | 4588 | 9605 | /*
* linux/arch/alpha/kernel/sys_titan.c
*
* Copyright (C) 1995 David A Rusling
* Copyright (C) 1996, 1999 Jay A Estabrook
* Copyright (C) 1998, 1999 Richard Henderson
* Copyright (C) 1999, 2000 Jeff Wiedemeier
*
* Code supporting TITAN systems (EV6+TITAN), currently:
* Privateer
* Falcon
* Granite
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <asm/ptrace.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_titan.h>
#include <asm/hwrpb.h>
#include <asm/tlbflush.h>
#include "proto.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"
#include "err_impl.h"
/*
* Titan generic
*/
/*
* Titan supports up to 4 CPUs
*/
static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
/*
* Mask is set (1) if enabled
*/
static unsigned long titan_cached_irq_mask;
/*
* Need SMP-safe access to interrupt CSRs
*/
DEFINE_SPINLOCK(titan_irq_lock);
static void
titan_update_irq_hw(unsigned long mask)
{
register titan_cchip *cchip = TITAN_cchip;
unsigned long isa_enable = 1UL << 55;
register int bcpu = boot_cpuid;
#ifdef CONFIG_SMP
cpumask_t cpm;
volatile unsigned long *dim0, *dim1, *dim2, *dim3;
unsigned long mask0, mask1, mask2, mask3, dummy;
cpumask_copy(&cpm, cpu_present_mask);
mask &= ~isa_enable;
mask0 = mask & titan_cpu_irq_affinity[0];
mask1 = mask & titan_cpu_irq_affinity[1];
mask2 = mask & titan_cpu_irq_affinity[2];
mask3 = mask & titan_cpu_irq_affinity[3];
if (bcpu == 0) mask0 |= isa_enable;
else if (bcpu == 1) mask1 |= isa_enable;
else if (bcpu == 2) mask2 |= isa_enable;
else mask3 |= isa_enable;
dim0 = &cchip->dim0.csr;
dim1 = &cchip->dim1.csr;
dim2 = &cchip->dim2.csr;
dim3 = &cchip->dim3.csr;
if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
*dim0 = mask0;
*dim1 = mask1;
*dim2 = mask2;
*dim3 = mask3;
mb();
*dim0;
*dim1;
*dim2;
*dim3;
#else
volatile unsigned long *dimB;
dimB = &cchip->dim0.csr;
if (bcpu == 1) dimB = &cchip->dim1.csr;
else if (bcpu == 2) dimB = &cchip->dim2.csr;
else if (bcpu == 3) dimB = &cchip->dim3.csr;
*dimB = mask | isa_enable;
mb();
*dimB;
#endif
}
static inline void
titan_enable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
spin_lock(&titan_irq_lock);
titan_cached_irq_mask |= 1UL << (irq - 16);
titan_update_irq_hw(titan_cached_irq_mask);
spin_unlock(&titan_irq_lock);
}
static inline void
titan_disable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
spin_lock(&titan_irq_lock);
titan_cached_irq_mask &= ~(1UL << (irq - 16));
titan_update_irq_hw(titan_cached_irq_mask);
spin_unlock(&titan_irq_lock);
}
static void
titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
{
int cpu;
for (cpu = 0; cpu < 4; cpu++) {
if (cpumask_test_cpu(cpu, &affinity))
titan_cpu_irq_affinity[cpu] |= 1UL << irq;
else
titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
}
}
static int
titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
bool force)
{
unsigned int irq = d->irq;
spin_lock(&titan_irq_lock);
titan_cpu_set_irq_affinity(irq - 16, *affinity);
titan_update_irq_hw(titan_cached_irq_mask);
spin_unlock(&titan_irq_lock);
return 0;
}
static void
titan_device_interrupt(unsigned long vector)
{
printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n");
}
static void
titan_srm_device_interrupt(unsigned long vector)
{
int irq;
irq = (vector - 0x800) >> 4;
handle_irq(irq);
}
static void __init
init_titan_irqs(struct irq_chip * ops, int imin, int imax)
{
long i;
for (i = imin; i <= imax; ++i) {
irq_set_chip_and_handler(i, ops, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
}
static struct irq_chip titan_irq_type = {
.name = "TITAN",
.irq_unmask = titan_enable_irq,
.irq_mask = titan_disable_irq,
.irq_mask_ack = titan_disable_irq,
.irq_set_affinity = titan_set_irq_affinity,
};
static irqreturn_t
titan_intr_nop(int irq, void *dev_id)
{
/*
* This is a NOP interrupt handler for the purposes of
* event counting -- just return.
*/
return IRQ_HANDLED;
}
static void __init
titan_init_irq(void)
{
if (alpha_using_srm && !alpha_mv.device_interrupt)
alpha_mv.device_interrupt = titan_srm_device_interrupt;
if (!alpha_mv.device_interrupt)
alpha_mv.device_interrupt = titan_device_interrupt;
titan_update_irq_hw(0);
init_titan_irqs(&titan_irq_type, 16, 63 + 16);
}
static void __init
titan_legacy_init_irq(void)
{
/* init the legacy dma controller */
outb(0, DMA1_RESET_REG);
outb(0, DMA2_RESET_REG);
outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
outb(0, DMA2_MASK_REG);
/* init the legacy irq controller */
init_i8259a_irqs();
/* init the titan irqs */
titan_init_irq();
}
void
titan_dispatch_irqs(u64 mask)
{
unsigned long vector;
/*
* Mask down to those interrupts which are enable on this processor
*/
mask &= titan_cpu_irq_affinity[smp_processor_id()];
/*
* Dispatch all requested interrupts
*/
while (mask) {
/* convert to SRM vector... priority is <63> -> <0> */
vector = 63 - __kernel_ctlz(mask);
mask &= ~(1UL << vector); /* clear it out */
vector = 0x900 + (vector << 4); /* convert to SRM vector */
/* dispatch it */
alpha_mv.device_interrupt(vector);
}
}
/*
* Titan Family
*/
static void __init
titan_request_irq(unsigned int irq, irq_handler_t handler,
unsigned long irqflags, const char *devname,
void *dev_id)
{
int err;
err = request_irq(irq, handler, irqflags, devname, dev_id);
if (err) {
printk("titan_request_irq for IRQ %d returned %d; ignoring\n",
irq, err);
}
}
static void __init
titan_late_init(void)
{
/*
* Enable the system error interrupts. These interrupts are
* all reported to the kernel as machine checks, so the handler
* is a nop so it can be called to count the individual events.
*/
titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
"CChip Error", NULL);
titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
"PChip 0 H_Error", NULL);
titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
"PChip 1 H_Error", NULL);
titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
"PChip 0 C_Error", NULL);
titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
"PChip 1 C_Error", NULL);
/*
* Register our error handlers.
*/
titan_register_error_handlers();
/*
* Check if the console left us any error logs.
*/
cdl_check_console_data_log();
}
static int __devinit
titan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u8 intline;
int irq;
/* Get the current intline. */
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
irq = intline;
/* Is it explicitly routed through ISA? */
if ((irq & 0xF0) == 0xE0)
return irq;
/* Offset by 16 to make room for ISA interrupts 0 - 15. */
return irq + 16;
}
static void __init
titan_init_pci(void)
{
/*
* This isn't really the right place, but there's some init
* that needs to be done after everything is basically up.
*/
titan_late_init();
/* Indicate that we trust the console to configure things properly */
pci_set_flags(PCI_PROBE_ONLY);
common_init_pci();
SMC669_Init(0);
locate_and_init_vga(NULL);
}
/*
* Privateer
*/
static void __init
privateer_init_pci(void)
{
/*
* Hook a couple of extra err interrupts that the
* common titan code won't.
*/
titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
"NMI", NULL);
titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
"Temperature Warning", NULL);
/*
* Finish with the common version.
*/
return titan_init_pci();
}
/*
* The System Vectors.
*/
struct alpha_machine_vector titan_mv __initmv = {
.vector_name = "TITAN",
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TITAN_IO,
.machine_check = titan_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
.min_mem_address = DEFAULT_MEM_BASE,
.pci_dac_offset = TITAN_DAC_OFFSET,
.nr_irqs = 80, /* 64 + 16 */
/* device_interrupt will be filled in by titan_init_irq */
.agp_info = titan_agp_info,
.init_arch = titan_init_arch,
.init_irq = titan_legacy_init_irq,
.init_rtc = common_init_rtc,
.init_pci = titan_init_pci,
.kill_arch = titan_kill_arch,
.pci_map_irq = titan_map_irq,
.pci_swizzle = common_swizzle,
};
ALIAS_MV(titan)
struct alpha_machine_vector privateer_mv __initmv = {
.vector_name = "PRIVATEER",
DO_EV6_MMU,
DO_DEFAULT_RTC,
DO_TITAN_IO,
.machine_check = privateer_machine_check,
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
.min_io_address = DEFAULT_IO_BASE,
.min_mem_address = DEFAULT_MEM_BASE,
.pci_dac_offset = TITAN_DAC_OFFSET,
.nr_irqs = 80, /* 64 + 16 */
/* device_interrupt will be filled in by titan_init_irq */
.agp_info = titan_agp_info,
.init_arch = titan_init_arch,
.init_irq = titan_legacy_init_irq,
.init_rtc = common_init_rtc,
.init_pci = privateer_init_pci,
.kill_arch = titan_kill_arch,
.pci_map_irq = titan_map_irq,
.pci_swizzle = common_swizzle,
};
/* No alpha_mv alias for privateer since we compile it
in unconditionally with titan; setup_arch knows how to cope. */
| gpl-2.0 |
ashwinr64/android_kernel_motorola_msm8974 | arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 5100 | 2242 | /*
* arch/arm/mach-mv78x00/rd78x00-masa-setup.c
*
* Marvell RD-78x00-mASA Development Board Setup
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/ethtool.h>
#include <mach/mv78xx0.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "common.h"
static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(9),
};
static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = {
};
static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = {
};
static struct mv_sata_platform_data rd78x00_masa_sata_data = {
.n_ports = 2,
};
static void __init rd78x00_masa_init(void)
{
/*
* Basic MV78x00 setup. Needs to be called early.
*/
mv78xx0_init();
/*
* Partition on-chip peripherals between the two CPU cores.
*/
if (mv78xx0_core_index() == 0) {
mv78xx0_ehci0_init();
mv78xx0_ehci1_init();
mv78xx0_ge00_init(&rd78x00_masa_ge00_data);
mv78xx0_ge10_init(&rd78x00_masa_ge10_data);
mv78xx0_sata_init(&rd78x00_masa_sata_data);
mv78xx0_uart0_init();
mv78xx0_uart2_init();
} else {
mv78xx0_ehci2_init();
mv78xx0_ge01_init(&rd78x00_masa_ge01_data);
mv78xx0_ge11_init(&rd78x00_masa_ge11_data);
mv78xx0_uart1_init();
mv78xx0_uart3_init();
}
}
static int __init rd78x00_pci_init(void)
{
/*
* Assign all PCIe devices to CPU core #0.
*/
if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0)
mv78xx0_pcie_init(1, 1);
return 0;
}
subsys_initcall(rd78x00_pci_init);
MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
.atag_offset = 0x100,
.init_machine = rd78x00_masa_init,
.map_io = mv78xx0_map_io,
.init_early = mv78xx0_init_early,
.init_irq = mv78xx0_init_irq,
.timer = &mv78xx0_timer,
.restart = mv78xx0_restart,
MACHINE_END
| gpl-2.0 |
KylinUI/android_kernel_samsung_exynos5410 | drivers/input/serio/libps2.c | 7660 | 8642 | /*
* PS/2 driver library
*
* Copyright (c) 1999-2002 Vojtech Pavlik
* Copyright (c) 2004 Dmitry Torokhov
*/
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/serio.h>
#include <linux/i8042.h>
#include <linux/init.h>
#include <linux/libps2.h>
#define DRIVER_DESC "PS/2 driver library"
MODULE_AUTHOR("Dmitry Torokhov <dtor@mail.ru>");
MODULE_DESCRIPTION("PS/2 driver library");
MODULE_LICENSE("GPL");
/*
* ps2_sendbyte() sends a byte to the device and waits for acknowledge.
* It doesn't handle retransmission, though it could - because if there
* is a need for retransmissions device has to be replaced anyway.
*
* ps2_sendbyte() can only be called from a process context.
*/
int ps2_sendbyte(struct ps2dev *ps2dev, unsigned char byte, int timeout)
{
serio_pause_rx(ps2dev->serio);
ps2dev->nak = 1;
ps2dev->flags |= PS2_FLAG_ACK;
serio_continue_rx(ps2dev->serio);
if (serio_write(ps2dev->serio, byte) == 0)
wait_event_timeout(ps2dev->wait,
!(ps2dev->flags & PS2_FLAG_ACK),
msecs_to_jiffies(timeout));
serio_pause_rx(ps2dev->serio);
ps2dev->flags &= ~PS2_FLAG_ACK;
serio_continue_rx(ps2dev->serio);
return -ps2dev->nak;
}
EXPORT_SYMBOL(ps2_sendbyte);
void ps2_begin_command(struct ps2dev *ps2dev)
{
mutex_lock(&ps2dev->cmd_mutex);
if (i8042_check_port_owner(ps2dev->serio))
i8042_lock_chip();
}
EXPORT_SYMBOL(ps2_begin_command);
void ps2_end_command(struct ps2dev *ps2dev)
{
if (i8042_check_port_owner(ps2dev->serio))
i8042_unlock_chip();
mutex_unlock(&ps2dev->cmd_mutex);
}
EXPORT_SYMBOL(ps2_end_command);
/*
* ps2_drain() waits for device to transmit requested number of bytes
* and discards them.
*/
void ps2_drain(struct ps2dev *ps2dev, int maxbytes, int timeout)
{
if (maxbytes > sizeof(ps2dev->cmdbuf)) {
WARN_ON(1);
maxbytes = sizeof(ps2dev->cmdbuf);
}
ps2_begin_command(ps2dev);
serio_pause_rx(ps2dev->serio);
ps2dev->flags = PS2_FLAG_CMD;
ps2dev->cmdcnt = maxbytes;
serio_continue_rx(ps2dev->serio);
wait_event_timeout(ps2dev->wait,
!(ps2dev->flags & PS2_FLAG_CMD),
msecs_to_jiffies(timeout));
ps2_end_command(ps2dev);
}
EXPORT_SYMBOL(ps2_drain);
/*
* ps2_is_keyboard_id() checks received ID byte against the list of
* known keyboard IDs.
*/
int ps2_is_keyboard_id(char id_byte)
{
static const char keyboard_ids[] = {
0xab, /* Regular keyboards */
0xac, /* NCD Sun keyboard */
0x2b, /* Trust keyboard, translated */
0x5d, /* Trust keyboard */
0x60, /* NMB SGI keyboard, translated */
0x47, /* NMB SGI keyboard */
};
return memchr(keyboard_ids, id_byte, sizeof(keyboard_ids)) != NULL;
}
EXPORT_SYMBOL(ps2_is_keyboard_id);
/*
* ps2_adjust_timeout() is called after receiving 1st byte of command
* response and tries to reduce remaining timeout to speed up command
* completion.
*/
static int ps2_adjust_timeout(struct ps2dev *ps2dev, int command, int timeout)
{
switch (command) {
case PS2_CMD_RESET_BAT:
/*
* Device has sent the first response byte after
* reset command, reset is thus done, so we can
* shorten the timeout.
* The next byte will come soon (keyboard) or not
* at all (mouse).
*/
if (timeout > msecs_to_jiffies(100))
timeout = msecs_to_jiffies(100);
break;
case PS2_CMD_GETID:
/*
* Microsoft Natural Elite keyboard responds to
* the GET ID command as it were a mouse, with
* a single byte. Fail the command so atkbd will
* use alternative probe to detect it.
*/
if (ps2dev->cmdbuf[1] == 0xaa) {
serio_pause_rx(ps2dev->serio);
ps2dev->flags = 0;
serio_continue_rx(ps2dev->serio);
timeout = 0;
}
/*
* If device behind the port is not a keyboard there
* won't be 2nd byte of ID response.
*/
if (!ps2_is_keyboard_id(ps2dev->cmdbuf[1])) {
serio_pause_rx(ps2dev->serio);
ps2dev->flags = ps2dev->cmdcnt = 0;
serio_continue_rx(ps2dev->serio);
timeout = 0;
}
break;
default:
break;
}
return timeout;
}
/*
* ps2_command() sends a command and its parameters to the mouse,
* then waits for the response and puts it in the param array.
*
* ps2_command() can only be called from a process context
*/
int __ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command)
{
int timeout;
int send = (command >> 12) & 0xf;
int receive = (command >> 8) & 0xf;
int rc = -1;
int i;
if (receive > sizeof(ps2dev->cmdbuf)) {
WARN_ON(1);
return -1;
}
if (send && !param) {
WARN_ON(1);
return -1;
}
serio_pause_rx(ps2dev->serio);
ps2dev->flags = command == PS2_CMD_GETID ? PS2_FLAG_WAITID : 0;
ps2dev->cmdcnt = receive;
if (receive && param)
for (i = 0; i < receive; i++)
ps2dev->cmdbuf[(receive - 1) - i] = param[i];
serio_continue_rx(ps2dev->serio);
/*
* Some devices (Synaptics) peform the reset before
* ACKing the reset command, and so it can take a long
* time before the ACK arrives.
*/
if (ps2_sendbyte(ps2dev, command & 0xff,
command == PS2_CMD_RESET_BAT ? 1000 : 200))
goto out;
for (i = 0; i < send; i++)
if (ps2_sendbyte(ps2dev, param[i], 200))
goto out;
/*
* The reset command takes a long time to execute.
*/
timeout = msecs_to_jiffies(command == PS2_CMD_RESET_BAT ? 4000 : 500);
timeout = wait_event_timeout(ps2dev->wait,
!(ps2dev->flags & PS2_FLAG_CMD1), timeout);
if (ps2dev->cmdcnt && !(ps2dev->flags & PS2_FLAG_CMD1)) {
timeout = ps2_adjust_timeout(ps2dev, command, timeout);
wait_event_timeout(ps2dev->wait,
!(ps2dev->flags & PS2_FLAG_CMD), timeout);
}
if (param)
for (i = 0; i < receive; i++)
param[i] = ps2dev->cmdbuf[(receive - 1) - i];
if (ps2dev->cmdcnt && (command != PS2_CMD_RESET_BAT || ps2dev->cmdcnt != 1))
goto out;
rc = 0;
out:
serio_pause_rx(ps2dev->serio);
ps2dev->flags = 0;
serio_continue_rx(ps2dev->serio);
return rc;
}
EXPORT_SYMBOL(__ps2_command);
int ps2_command(struct ps2dev *ps2dev, unsigned char *param, int command)
{
int rc;
ps2_begin_command(ps2dev);
rc = __ps2_command(ps2dev, param, command);
ps2_end_command(ps2dev);
return rc;
}
EXPORT_SYMBOL(ps2_command);
/*
* ps2_init() initializes ps2dev structure
*/
void ps2_init(struct ps2dev *ps2dev, struct serio *serio)
{
mutex_init(&ps2dev->cmd_mutex);
lockdep_set_subclass(&ps2dev->cmd_mutex, serio->depth);
init_waitqueue_head(&ps2dev->wait);
ps2dev->serio = serio;
}
EXPORT_SYMBOL(ps2_init);
/*
* ps2_handle_ack() is supposed to be used in interrupt handler
* to properly process ACK/NAK of a command from a PS/2 device.
*/
int ps2_handle_ack(struct ps2dev *ps2dev, unsigned char data)
{
switch (data) {
case PS2_RET_ACK:
ps2dev->nak = 0;
break;
case PS2_RET_NAK:
ps2dev->flags |= PS2_FLAG_NAK;
ps2dev->nak = PS2_RET_NAK;
break;
case PS2_RET_ERR:
if (ps2dev->flags & PS2_FLAG_NAK) {
ps2dev->flags &= ~PS2_FLAG_NAK;
ps2dev->nak = PS2_RET_ERR;
break;
}
/*
* Workaround for mice which don't ACK the Get ID command.
* These are valid mouse IDs that we recognize.
*/
case 0x00:
case 0x03:
case 0x04:
if (ps2dev->flags & PS2_FLAG_WAITID) {
ps2dev->nak = 0;
break;
}
/* Fall through */
default:
return 0;
}
if (!ps2dev->nak) {
ps2dev->flags &= ~PS2_FLAG_NAK;
if (ps2dev->cmdcnt)
ps2dev->flags |= PS2_FLAG_CMD | PS2_FLAG_CMD1;
}
ps2dev->flags &= ~PS2_FLAG_ACK;
wake_up(&ps2dev->wait);
if (data != PS2_RET_ACK)
ps2_handle_response(ps2dev, data);
return 1;
}
EXPORT_SYMBOL(ps2_handle_ack);
/*
* ps2_handle_response() is supposed to be used in interrupt handler
* to properly store device's response to a command and notify process
* waiting for completion of the command.
*/
int ps2_handle_response(struct ps2dev *ps2dev, unsigned char data)
{
if (ps2dev->cmdcnt)
ps2dev->cmdbuf[--ps2dev->cmdcnt] = data;
if (ps2dev->flags & PS2_FLAG_CMD1) {
ps2dev->flags &= ~PS2_FLAG_CMD1;
if (ps2dev->cmdcnt)
wake_up(&ps2dev->wait);
}
if (!ps2dev->cmdcnt) {
ps2dev->flags &= ~PS2_FLAG_CMD;
wake_up(&ps2dev->wait);
}
return 1;
}
EXPORT_SYMBOL(ps2_handle_response);
void ps2_cmd_aborted(struct ps2dev *ps2dev)
{
if (ps2dev->flags & PS2_FLAG_ACK)
ps2dev->nak = 1;
if (ps2dev->flags & (PS2_FLAG_ACK | PS2_FLAG_CMD))
wake_up(&ps2dev->wait);
/* reset all flags except last nack */
ps2dev->flags &= PS2_FLAG_NAK;
}
EXPORT_SYMBOL(ps2_cmd_aborted);
| gpl-2.0 |
sudosurootdev/kernel_lge_g3-wip | arch/h8300/kernel/signal.c | 8940 | 14395 | /*
* linux/arch/h8300/kernel/signal.c
*
* Copyright (C) 1991, 1992 Linus Torvalds
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/*
* uClinux H8/300 support by Yoshinori Sato <ysato@users.sourceforge.jp>
* and David McCullough <davidm@snapgear.com>
*
* Based on
* Linux/m68k by Hamish Macdonald
*/
/*
* ++roman (07/09/96): implemented signal stacks (specially for tosemu on
* Atari :-) Current limitation: Only one sigstack can be active at one time.
* If a second signal with SA_ONSTACK set arrives while working on a sigstack,
* SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
* signal handlers!
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/syscalls.h>
#include <linux/errno.h>
#include <linux/wait.h>
#include <linux/ptrace.h>
#include <linux/unistd.h>
#include <linux/stddef.h>
#include <linux/highuid.h>
#include <linux/personality.h>
#include <linux/tty.h>
#include <linux/binfmts.h>
#include <linux/freezer.h>
#include <linux/tracehook.h>
#include <asm/setup.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/traps.h>
#include <asm/ucontext.h>
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset);
/*
* Atomically swap in the new signal mask, and wait for a signal.
*/
asmlinkage int do_sigsuspend(struct pt_regs *regs)
{
old_sigset_t mask = regs->er3;
sigset_t saveset;
mask &= _BLOCKABLE;
spin_lock_irq(¤t->sighand->siglock);
saveset = current->blocked;
siginitset(¤t->blocked, mask);
recalc_sigpending();
spin_unlock_irq(¤t->sighand->siglock);
regs->er0 = -EINTR;
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
if (do_signal(regs, &saveset))
return -EINTR;
}
}
asmlinkage int
do_rt_sigsuspend(struct pt_regs *regs)
{
sigset_t *unewset = (sigset_t *)regs->er1;
size_t sigsetsize = (size_t)regs->er2;
sigset_t saveset, newset;
/* XXX: Don't preclude handling different sized sigset_t's. */
if (sigsetsize != sizeof(sigset_t))
return -EINVAL;
if (copy_from_user(&newset, unewset, sizeof(newset)))
return -EFAULT;
sigdelsetmask(&newset, ~_BLOCKABLE);
spin_lock_irq(¤t->sighand->siglock);
saveset = current->blocked;
current->blocked = newset;
recalc_sigpending();
spin_unlock_irq(¤t->sighand->siglock);
regs->er0 = -EINTR;
while (1) {
current->state = TASK_INTERRUPTIBLE;
schedule();
if (do_signal(regs, &saveset))
return -EINTR;
}
}
asmlinkage int
sys_sigaction(int sig, const struct old_sigaction *act,
struct old_sigaction *oact)
{
struct k_sigaction new_ka, old_ka;
int ret;
if (act) {
old_sigset_t mask;
if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
__get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
__get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
return -EFAULT;
__get_user(new_ka.sa.sa_flags, &act->sa_flags);
__get_user(mask, &act->sa_mask);
siginitset(&new_ka.sa.sa_mask, mask);
}
ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
if (!ret && oact) {
if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
__put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
__put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
return -EFAULT;
__put_user(old_ka.sa.sa_flags, &oact->sa_flags);
__put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
}
return ret;
}
asmlinkage int
sys_sigaltstack(const stack_t *uss, stack_t *uoss)
{
return do_sigaltstack(uss, uoss, rdusp());
}
/*
* Do a signal return; undo the signal stack.
*
* Keep the return code on the stack quadword aligned!
* That makes the cache flush below easier.
*/
struct sigframe
{
long dummy_er0;
long dummy_vector;
#if defined(CONFIG_CPU_H8S)
short dummy_exr;
#endif
long dummy_pc;
char *pretcode;
unsigned char retcode[8];
unsigned long extramask[_NSIG_WORDS-1];
struct sigcontext sc;
int sig;
} __attribute__((aligned(2),packed));
struct rt_sigframe
{
long dummy_er0;
long dummy_vector;
#if defined(CONFIG_CPU_H8S)
short dummy_exr;
#endif
long dummy_pc;
char *pretcode;
struct siginfo *pinfo;
void *puc;
unsigned char retcode[8];
struct siginfo info;
struct ucontext uc;
int sig;
} __attribute__((aligned(2),packed));
static inline int
restore_sigcontext(struct pt_regs *regs, struct sigcontext *usc,
int *pd0)
{
int err = 0;
unsigned int ccr;
unsigned int usp;
unsigned int er0;
/* Always make any pending restarted system calls return -EINTR */
current_thread_info()->restart_block.fn = do_no_restart_syscall;
#define COPY(r) err |= __get_user(regs->r, &usc->sc_##r) /* restore passed registers */
COPY(er1);
COPY(er2);
COPY(er3);
COPY(er5);
COPY(pc);
ccr = regs->ccr & 0x10;
COPY(ccr);
#undef COPY
regs->ccr &= 0xef;
regs->ccr |= ccr;
regs->orig_er0 = -1; /* disable syscall checks */
err |= __get_user(usp, &usc->sc_usp);
wrusp(usp);
err |= __get_user(er0, &usc->sc_er0);
*pd0 = er0;
return err;
}
asmlinkage int do_sigreturn(unsigned long __unused,...)
{
struct pt_regs *regs = (struct pt_regs *) (&__unused - 1);
unsigned long usp = rdusp();
struct sigframe *frame = (struct sigframe *)(usp - 4);
sigset_t set;
int er0;
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
(_NSIG_WORDS > 1 &&
__copy_from_user(&set.sig[1], &frame->extramask,
sizeof(frame->extramask))))
goto badframe;
sigdelsetmask(&set, ~_BLOCKABLE);
spin_lock_irq(¤t->sighand->siglock);
current->blocked = set;
recalc_sigpending();
spin_unlock_irq(¤t->sighand->siglock);
if (restore_sigcontext(regs, &frame->sc, &er0))
goto badframe;
return er0;
badframe:
force_sig(SIGSEGV, current);
return 0;
}
asmlinkage int do_rt_sigreturn(unsigned long __unused,...)
{
struct pt_regs *regs = (struct pt_regs *) &__unused;
unsigned long usp = rdusp();
struct rt_sigframe *frame = (struct rt_sigframe *)(usp - 4);
sigset_t set;
int er0;
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
goto badframe;
sigdelsetmask(&set, ~_BLOCKABLE);
spin_unlock_irq(¤t->sighand->siglock);
current->blocked = set;
recalc_sigpending();
spin_lock_irq(¤t->sighand->siglock);
if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &er0))
goto badframe;
if (do_sigaltstack(&frame->uc.uc_stack, NULL, usp) == -EFAULT)
goto badframe;
return er0;
badframe:
force_sig(SIGSEGV, current);
return 0;
}
static int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
unsigned long mask)
{
int err = 0;
err |= __put_user(regs->er0, &sc->sc_er0);
err |= __put_user(regs->er1, &sc->sc_er1);
err |= __put_user(regs->er2, &sc->sc_er2);
err |= __put_user(regs->er3, &sc->sc_er3);
err |= __put_user(regs->er4, &sc->sc_er4);
err |= __put_user(regs->er5, &sc->sc_er5);
err |= __put_user(regs->er6, &sc->sc_er6);
err |= __put_user(rdusp(), &sc->sc_usp);
err |= __put_user(regs->pc, &sc->sc_pc);
err |= __put_user(regs->ccr, &sc->sc_ccr);
err |= __put_user(mask, &sc->sc_mask);
return err;
}
static inline void *
get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
{
unsigned long usp;
/* Default to using normal stack. */
usp = rdusp();
/* This is the X/Open sanctioned signal stack switching. */
if (ka->sa.sa_flags & SA_ONSTACK) {
if (!sas_ss_flags(usp))
usp = current->sas_ss_sp + current->sas_ss_size;
}
return (void *)((usp - frame_size) & -8UL);
}
static void setup_frame (int sig, struct k_sigaction *ka,
sigset_t *set, struct pt_regs *regs)
{
struct sigframe *frame;
int err = 0;
int usig;
unsigned char *ret;
frame = get_sigframe(ka, regs, sizeof(*frame));
if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
goto give_sigsegv;
usig = current_thread_info()->exec_domain
&& current_thread_info()->exec_domain->signal_invmap
&& sig < 32
? current_thread_info()->exec_domain->signal_invmap[sig]
: sig;
err |= __put_user(usig, &frame->sig);
if (err)
goto give_sigsegv;
err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
if (err)
goto give_sigsegv;
if (_NSIG_WORDS > 1) {
err |= copy_to_user(frame->extramask, &set->sig[1],
sizeof(frame->extramask));
if (err)
goto give_sigsegv;
}
ret = frame->retcode;
if (ka->sa.sa_flags & SA_RESTORER)
ret = (unsigned char *)(ka->sa.sa_restorer);
else {
/* sub.l er0,er0; mov.b #__NR_sigreturn,r0l; trapa #0 */
err |= __put_user(0x1a80f800 + (__NR_sigreturn & 0xff),
(unsigned long *)(frame->retcode + 0));
err |= __put_user(0x5700, (unsigned short *)(frame->retcode + 4));
}
/* Set up to return from userspace. */
err |= __put_user(ret, &frame->pretcode);
if (err)
goto give_sigsegv;
/* Set up registers for signal handler */
wrusp ((unsigned long) frame);
regs->pc = (unsigned long) ka->sa.sa_handler;
regs->er0 = (current_thread_info()->exec_domain
&& current_thread_info()->exec_domain->signal_invmap
&& sig < 32
? current_thread_info()->exec_domain->signal_invmap[sig]
: sig);
regs->er1 = (unsigned long)&(frame->sc);
regs->er5 = current->mm->start_data; /* GOT base */
return;
give_sigsegv:
force_sigsegv(sig, current);
}
static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
sigset_t *set, struct pt_regs *regs)
{
struct rt_sigframe *frame;
int err = 0;
int usig;
unsigned char *ret;
frame = get_sigframe(ka, regs, sizeof(*frame));
if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
goto give_sigsegv;
usig = current_thread_info()->exec_domain
&& current_thread_info()->exec_domain->signal_invmap
&& sig < 32
? current_thread_info()->exec_domain->signal_invmap[sig]
: sig;
err |= __put_user(usig, &frame->sig);
if (err)
goto give_sigsegv;
err |= __put_user(&frame->info, &frame->pinfo);
err |= __put_user(&frame->uc, &frame->puc);
err |= copy_siginfo_to_user(&frame->info, info);
if (err)
goto give_sigsegv;
/* Create the ucontext. */
err |= __put_user(0, &frame->uc.uc_flags);
err |= __put_user(0, &frame->uc.uc_link);
err |= __put_user((void *)current->sas_ss_sp,
&frame->uc.uc_stack.ss_sp);
err |= __put_user(sas_ss_flags(rdusp()),
&frame->uc.uc_stack.ss_flags);
err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
if (err)
goto give_sigsegv;
/* Set up to return from userspace. */
ret = frame->retcode;
if (ka->sa.sa_flags & SA_RESTORER)
ret = (unsigned char *)(ka->sa.sa_restorer);
else {
/* sub.l er0,er0; mov.b #__NR_sigreturn,r0l; trapa #0 */
err |= __put_user(0x1a80f800 + (__NR_sigreturn & 0xff),
(unsigned long *)(frame->retcode + 0));
err |= __put_user(0x5700, (unsigned short *)(frame->retcode + 4));
}
err |= __put_user(ret, &frame->pretcode);
if (err)
goto give_sigsegv;
/* Set up registers for signal handler */
wrusp ((unsigned long) frame);
regs->pc = (unsigned long) ka->sa.sa_handler;
regs->er0 = (current_thread_info()->exec_domain
&& current_thread_info()->exec_domain->signal_invmap
&& sig < 32
? current_thread_info()->exec_domain->signal_invmap[sig]
: sig);
regs->er1 = (unsigned long)&(frame->info);
regs->er2 = (unsigned long)&frame->uc;
regs->er5 = current->mm->start_data; /* GOT base */
return;
give_sigsegv:
force_sigsegv(sig, current);
}
/*
* OK, we're invoking a handler
*/
static void
handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
sigset_t *oldset, struct pt_regs * regs)
{
/* are we from a system call? */
if (regs->orig_er0 >= 0) {
switch (regs->er0) {
case -ERESTART_RESTARTBLOCK:
case -ERESTARTNOHAND:
regs->er0 = -EINTR;
break;
case -ERESTARTSYS:
if (!(ka->sa.sa_flags & SA_RESTART)) {
regs->er0 = -EINTR;
break;
}
/* fallthrough */
case -ERESTARTNOINTR:
regs->er0 = regs->orig_er0;
regs->pc -= 2;
}
}
/* set up the stack frame */
if (ka->sa.sa_flags & SA_SIGINFO)
setup_rt_frame(sig, ka, info, oldset, regs);
else
setup_frame(sig, ka, oldset, regs);
spin_lock_irq(¤t->sighand->siglock);
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
if (!(ka->sa.sa_flags & SA_NODEFER))
sigaddset(¤t->blocked,sig);
recalc_sigpending();
spin_unlock_irq(¤t->sighand->siglock);
}
/*
* Note that 'init' is a special process: it doesn't get signals it doesn't
* want to handle. Thus you cannot kill init even with a SIGKILL even by
* mistake.
*/
asmlinkage int do_signal(struct pt_regs *regs, sigset_t *oldset)
{
siginfo_t info;
int signr;
struct k_sigaction ka;
/*
* We want the common case to go fast, which
* is why we may in certain cases get here from
* kernel mode. Just return without doing anything
* if so.
*/
if ((regs->ccr & 0x10))
return 1;
if (try_to_freeze())
goto no_signal;
current->thread.esp0 = (unsigned long) regs;
if (!oldset)
oldset = ¤t->blocked;
signr = get_signal_to_deliver(&info, &ka, regs, NULL);
if (signr > 0) {
/* Whee! Actually deliver the signal. */
handle_signal(signr, &info, &ka, oldset, regs);
return 1;
}
no_signal:
/* Did we come from a system call? */
if (regs->orig_er0 >= 0) {
/* Restart the system call - no handlers present */
if (regs->er0 == -ERESTARTNOHAND ||
regs->er0 == -ERESTARTSYS ||
regs->er0 == -ERESTARTNOINTR) {
regs->er0 = regs->orig_er0;
regs->pc -= 2;
}
if (regs->er0 == -ERESTART_RESTARTBLOCK){
regs->er0 = __NR_restart_syscall;
regs->pc -= 2;
}
}
return 0;
}
asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags)
{
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
do_signal(regs, NULL);
if (thread_info_flags & _TIF_NOTIFY_RESUME) {
clear_thread_flag(TIF_NOTIFY_RESUME);
tracehook_notify_resume(regs);
if (current->replacement_session_keyring)
key_replace_session_keyring();
}
}
| gpl-2.0 |
Twisted-Kernel/S6-MM | arch/sh/boards/mach-microdev/irq.c | 9196 | 5212 | /*
* arch/sh/boards/superh/microdev/irq.c
*
* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
*
* SuperH SH4-202 MicroDev board support.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <mach/microdev.h>
#define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */
static const struct {
unsigned char fpgaIrq;
unsigned char mapped;
const char *name;
} fpgaIrqTable[NUM_EXTERNAL_IRQS] = {
{ 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */
{ MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */
{ MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */
{ MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */
{ MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */
{ 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */
{ 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */
{ MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */
{ MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */
{ MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */
{ MICRODEV_IRQ_PCI_INTC, 1, "PCI INTC" }, /* IRQ #10 IRL=5 0x340 */
{ MICRODEV_IRQ_PCI_INTD, 1, "PCI INTD" }, /* IRQ #11 IRL=4 0x360 */
{ MICRODEV_FPGA_IRQ_MOUSE, 1, "mouse" }, /* IRQ #12 IRL=3 0x380 */
{ MICRODEV_FPGA_IRQ_IDE2, 1, "IDE #2" }, /* IRQ #13 IRL=2 0x3a0 */
{ MICRODEV_FPGA_IRQ_IDE1, 1, "IDE #1" }, /* IRQ #14 IRL=1 0x3c0 */
{ 0, 0, "unused" }, /* IRQ #15 IRL=0 0x3e0 */
};
#if (MICRODEV_LINUX_IRQ_KEYBOARD != 1)
# error Inconsistancy in defining the IRQ# for Keyboard!
#endif
#if (MICRODEV_LINUX_IRQ_ETHERNET != 3)
# error Inconsistancy in defining the IRQ# for Ethernet!
#endif
#if (MICRODEV_LINUX_IRQ_USB_HC != 7)
# error Inconsistancy in defining the IRQ# for USB!
#endif
#if (MICRODEV_LINUX_IRQ_MOUSE != 12)
# error Inconsistancy in defining the IRQ# for PS/2 Mouse!
#endif
#if (MICRODEV_LINUX_IRQ_IDE2 != 13)
# error Inconsistancy in defining the IRQ# for secondary IDE!
#endif
#if (MICRODEV_LINUX_IRQ_IDE1 != 14)
# error Inconsistancy in defining the IRQ# for primary IDE!
#endif
static void disable_microdev_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned int fpgaIrq;
if (irq >= NUM_EXTERNAL_IRQS)
return;
if (!fpgaIrqTable[irq].mapped)
return;
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
/* disable interrupts on the FPGA INTC register */
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
}
static void enable_microdev_irq(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned long priorityReg, priorities, pri;
unsigned int fpgaIrq;
if (unlikely(irq >= NUM_EXTERNAL_IRQS))
return;
if (unlikely(!fpgaIrqTable[irq].mapped))
return;
pri = 15 - irq;
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
/* set priority for the interrupt */
priorities = __raw_readl(priorityReg);
priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
__raw_writel(priorities, priorityReg);
/* enable interrupts on the FPGA INTC register */
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
}
static struct irq_chip microdev_irq_type = {
.name = "MicroDev-IRQ",
.irq_unmask = enable_microdev_irq,
.irq_mask = disable_microdev_irq,
};
/* This function sets the desired irq handler to be a MicroDev type */
static void __init make_microdev_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq);
disable_microdev_irq(irq_get_irq_data(irq));
}
extern void __init init_microdev_irq(void)
{
int i;
/* disable interrupts on the FPGA INTC register */
__raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
make_microdev_irq(i);
}
extern void microdev_print_fpga_intc_status(void)
{
volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG;
volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG;
volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0);
volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8);
volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16);
volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24);
volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG;
volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG;
printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n");
printk("FPGA_INTENB = 0x%08x\n", *intenb);
printk("FPGA_INTDSB = 0x%08x\n", *intdsb);
printk("FPGA_INTSRC = 0x%08x\n", *intsrc);
printk("FPGA_INTREQ = 0x%08x\n", *intreq);
printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
printk("-------------------------------------------------------------------------------\n");
}
| gpl-2.0 |
giantdisaster/btrfs | drivers/char/snsc.c | 10732 | 11216 | /*
* SN Platform system controller communication support
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004, 2006 Silicon Graphics, Inc. All rights reserved.
*/
/*
* System controller communication driver
*
* This driver allows a user process to communicate with the system
* controller (a.k.a. "IRouter") network in an SGI SN system.
*/
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/device.h>
#include <linux/poll.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <asm/sn/io.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/module.h>
#include <asm/sn/geo.h>
#include <asm/sn/nodepda.h>
#include "snsc.h"
#define SYSCTL_BASENAME "snsc"
#define SCDRV_BUFSZ 2048
#define SCDRV_TIMEOUT 1000
static DEFINE_MUTEX(scdrv_mutex);
static irqreturn_t
scdrv_interrupt(int irq, void *subch_data)
{
struct subch_data_s *sd = subch_data;
unsigned long flags;
int status;
spin_lock_irqsave(&sd->sd_rlock, flags);
spin_lock(&sd->sd_wlock);
status = ia64_sn_irtr_intr(sd->sd_nasid, sd->sd_subch);
if (status > 0) {
if (status & SAL_IROUTER_INTR_RECV) {
wake_up(&sd->sd_rq);
}
if (status & SAL_IROUTER_INTR_XMIT) {
ia64_sn_irtr_intr_disable
(sd->sd_nasid, sd->sd_subch,
SAL_IROUTER_INTR_XMIT);
wake_up(&sd->sd_wq);
}
}
spin_unlock(&sd->sd_wlock);
spin_unlock_irqrestore(&sd->sd_rlock, flags);
return IRQ_HANDLED;
}
/*
* scdrv_open
*
* Reserve a subchannel for system controller communication.
*/
static int
scdrv_open(struct inode *inode, struct file *file)
{
struct sysctl_data_s *scd;
struct subch_data_s *sd;
int rv;
/* look up device info for this device file */
scd = container_of(inode->i_cdev, struct sysctl_data_s, scd_cdev);
/* allocate memory for subchannel data */
sd = kzalloc(sizeof (struct subch_data_s), GFP_KERNEL);
if (sd == NULL) {
printk("%s: couldn't allocate subchannel data\n",
__func__);
return -ENOMEM;
}
/* initialize subch_data_s fields */
sd->sd_nasid = scd->scd_nasid;
sd->sd_subch = ia64_sn_irtr_open(scd->scd_nasid);
if (sd->sd_subch < 0) {
kfree(sd);
printk("%s: couldn't allocate subchannel\n", __func__);
return -EBUSY;
}
spin_lock_init(&sd->sd_rlock);
spin_lock_init(&sd->sd_wlock);
init_waitqueue_head(&sd->sd_rq);
init_waitqueue_head(&sd->sd_wq);
sema_init(&sd->sd_rbs, 1);
sema_init(&sd->sd_wbs, 1);
file->private_data = sd;
/* hook this subchannel up to the system controller interrupt */
mutex_lock(&scdrv_mutex);
rv = request_irq(SGI_UART_VECTOR, scdrv_interrupt,
IRQF_SHARED | IRQF_DISABLED,
SYSCTL_BASENAME, sd);
if (rv) {
ia64_sn_irtr_close(sd->sd_nasid, sd->sd_subch);
kfree(sd);
printk("%s: irq request failed (%d)\n", __func__, rv);
mutex_unlock(&scdrv_mutex);
return -EBUSY;
}
mutex_unlock(&scdrv_mutex);
return 0;
}
/*
* scdrv_release
*
* Release a previously-reserved subchannel.
*/
static int
scdrv_release(struct inode *inode, struct file *file)
{
struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
int rv;
/* free the interrupt */
free_irq(SGI_UART_VECTOR, sd);
/* ask SAL to close the subchannel */
rv = ia64_sn_irtr_close(sd->sd_nasid, sd->sd_subch);
kfree(sd);
return rv;
}
/*
* scdrv_read
*
* Called to read bytes from the open IRouter pipe.
*
*/
static inline int
read_status_check(struct subch_data_s *sd, int *len)
{
return ia64_sn_irtr_recv(sd->sd_nasid, sd->sd_subch, sd->sd_rb, len);
}
static ssize_t
scdrv_read(struct file *file, char __user *buf, size_t count, loff_t *f_pos)
{
int status;
int len;
unsigned long flags;
struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
/* try to get control of the read buffer */
if (down_trylock(&sd->sd_rbs)) {
/* somebody else has it now;
* if we're non-blocking, then exit...
*/
if (file->f_flags & O_NONBLOCK) {
return -EAGAIN;
}
/* ...or if we want to block, then do so here */
if (down_interruptible(&sd->sd_rbs)) {
/* something went wrong with wait */
return -ERESTARTSYS;
}
}
/* anything to read? */
len = CHUNKSIZE;
spin_lock_irqsave(&sd->sd_rlock, flags);
status = read_status_check(sd, &len);
/* if not, and we're blocking I/O, loop */
while (status < 0) {
DECLARE_WAITQUEUE(wait, current);
if (file->f_flags & O_NONBLOCK) {
spin_unlock_irqrestore(&sd->sd_rlock, flags);
up(&sd->sd_rbs);
return -EAGAIN;
}
len = CHUNKSIZE;
set_current_state(TASK_INTERRUPTIBLE);
add_wait_queue(&sd->sd_rq, &wait);
spin_unlock_irqrestore(&sd->sd_rlock, flags);
schedule_timeout(SCDRV_TIMEOUT);
remove_wait_queue(&sd->sd_rq, &wait);
if (signal_pending(current)) {
/* wait was interrupted */
up(&sd->sd_rbs);
return -ERESTARTSYS;
}
spin_lock_irqsave(&sd->sd_rlock, flags);
status = read_status_check(sd, &len);
}
spin_unlock_irqrestore(&sd->sd_rlock, flags);
if (len > 0) {
/* we read something in the last read_status_check(); copy
* it out to user space
*/
if (count < len) {
pr_debug("%s: only accepting %d of %d bytes\n",
__func__, (int) count, len);
}
len = min((int) count, len);
if (copy_to_user(buf, sd->sd_rb, len))
len = -EFAULT;
}
/* release the read buffer and wake anyone who might be
* waiting for it
*/
up(&sd->sd_rbs);
/* return the number of characters read in */
return len;
}
/*
* scdrv_write
*
* Writes a chunk of an IRouter packet (or other system controller data)
* to the system controller.
*
*/
static inline int
write_status_check(struct subch_data_s *sd, int count)
{
return ia64_sn_irtr_send(sd->sd_nasid, sd->sd_subch, sd->sd_wb, count);
}
static ssize_t
scdrv_write(struct file *file, const char __user *buf,
size_t count, loff_t *f_pos)
{
unsigned long flags;
int status;
struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
/* try to get control of the write buffer */
if (down_trylock(&sd->sd_wbs)) {
/* somebody else has it now;
* if we're non-blocking, then exit...
*/
if (file->f_flags & O_NONBLOCK) {
return -EAGAIN;
}
/* ...or if we want to block, then do so here */
if (down_interruptible(&sd->sd_wbs)) {
/* something went wrong with wait */
return -ERESTARTSYS;
}
}
count = min((int) count, CHUNKSIZE);
if (copy_from_user(sd->sd_wb, buf, count)) {
up(&sd->sd_wbs);
return -EFAULT;
}
/* try to send the buffer */
spin_lock_irqsave(&sd->sd_wlock, flags);
status = write_status_check(sd, count);
/* if we failed, and we want to block, then loop */
while (status <= 0) {
DECLARE_WAITQUEUE(wait, current);
if (file->f_flags & O_NONBLOCK) {
spin_unlock(&sd->sd_wlock);
up(&sd->sd_wbs);
return -EAGAIN;
}
set_current_state(TASK_INTERRUPTIBLE);
add_wait_queue(&sd->sd_wq, &wait);
spin_unlock_irqrestore(&sd->sd_wlock, flags);
schedule_timeout(SCDRV_TIMEOUT);
remove_wait_queue(&sd->sd_wq, &wait);
if (signal_pending(current)) {
/* wait was interrupted */
up(&sd->sd_wbs);
return -ERESTARTSYS;
}
spin_lock_irqsave(&sd->sd_wlock, flags);
status = write_status_check(sd, count);
}
spin_unlock_irqrestore(&sd->sd_wlock, flags);
/* release the write buffer and wake anyone who's waiting for it */
up(&sd->sd_wbs);
/* return the number of characters accepted (should be the complete
* "chunk" as requested)
*/
if ((status >= 0) && (status < count)) {
pr_debug("Didn't accept the full chunk; %d of %d\n",
status, (int) count);
}
return status;
}
static unsigned int
scdrv_poll(struct file *file, struct poll_table_struct *wait)
{
unsigned int mask = 0;
int status = 0;
struct subch_data_s *sd = (struct subch_data_s *) file->private_data;
unsigned long flags;
poll_wait(file, &sd->sd_rq, wait);
poll_wait(file, &sd->sd_wq, wait);
spin_lock_irqsave(&sd->sd_rlock, flags);
spin_lock(&sd->sd_wlock);
status = ia64_sn_irtr_intr(sd->sd_nasid, sd->sd_subch);
spin_unlock(&sd->sd_wlock);
spin_unlock_irqrestore(&sd->sd_rlock, flags);
if (status > 0) {
if (status & SAL_IROUTER_INTR_RECV) {
mask |= POLLIN | POLLRDNORM;
}
if (status & SAL_IROUTER_INTR_XMIT) {
mask |= POLLOUT | POLLWRNORM;
}
}
return mask;
}
static const struct file_operations scdrv_fops = {
.owner = THIS_MODULE,
.read = scdrv_read,
.write = scdrv_write,
.poll = scdrv_poll,
.open = scdrv_open,
.release = scdrv_release,
.llseek = noop_llseek,
};
static struct class *snsc_class;
/*
* scdrv_init
*
* Called at boot time to initialize the system controller communication
* facility.
*/
int __init
scdrv_init(void)
{
geoid_t geoid;
cnodeid_t cnode;
char devname[32];
char *devnamep;
struct sysctl_data_s *scd;
void *salbuf;
dev_t first_dev, dev;
nasid_t event_nasid;
if (!ia64_platform_is("sn2"))
return -ENODEV;
event_nasid = ia64_sn_get_console_nasid();
if (alloc_chrdev_region(&first_dev, 0, num_cnodes,
SYSCTL_BASENAME) < 0) {
printk("%s: failed to register SN system controller device\n",
__func__);
return -ENODEV;
}
snsc_class = class_create(THIS_MODULE, SYSCTL_BASENAME);
for (cnode = 0; cnode < num_cnodes; cnode++) {
geoid = cnodeid_get_geoid(cnode);
devnamep = devname;
format_module_id(devnamep, geo_module(geoid),
MODULE_FORMAT_BRIEF);
devnamep = devname + strlen(devname);
sprintf(devnamep, "^%d#%d", geo_slot(geoid),
geo_slab(geoid));
/* allocate sysctl device data */
scd = kzalloc(sizeof (struct sysctl_data_s),
GFP_KERNEL);
if (!scd) {
printk("%s: failed to allocate device info"
"for %s/%s\n", __func__,
SYSCTL_BASENAME, devname);
continue;
}
/* initialize sysctl device data fields */
scd->scd_nasid = cnodeid_to_nasid(cnode);
if (!(salbuf = kmalloc(SCDRV_BUFSZ, GFP_KERNEL))) {
printk("%s: failed to allocate driver buffer"
"(%s%s)\n", __func__,
SYSCTL_BASENAME, devname);
kfree(scd);
continue;
}
if (ia64_sn_irtr_init(scd->scd_nasid, salbuf,
SCDRV_BUFSZ) < 0) {
printk
("%s: failed to initialize SAL for"
" system controller communication"
" (%s/%s): outdated PROM?\n",
__func__, SYSCTL_BASENAME, devname);
kfree(scd);
kfree(salbuf);
continue;
}
dev = first_dev + cnode;
cdev_init(&scd->scd_cdev, &scdrv_fops);
if (cdev_add(&scd->scd_cdev, dev, 1)) {
printk("%s: failed to register system"
" controller device (%s%s)\n",
__func__, SYSCTL_BASENAME, devname);
kfree(scd);
kfree(salbuf);
continue;
}
device_create(snsc_class, NULL, dev, NULL,
"%s", devname);
ia64_sn_irtr_intr_enable(scd->scd_nasid,
0 /*ignored */ ,
SAL_IROUTER_INTR_RECV);
/* on the console nasid, prepare to receive
* system controller environmental events
*/
if(scd->scd_nasid == event_nasid) {
scdrv_event_init(scd);
}
}
return 0;
}
module_init(scdrv_init);
| gpl-2.0 |
rogersb11/android_kernel_samsung_smdk4412 | tools/firewire/decode-fcp.c | 13036 | 5617 | #include <linux/firewire-constants.h>
#include <stdio.h>
#include <stdlib.h>
#include "list.h"
#include "nosy-dump.h"
#define CSR_FCP_COMMAND 0xfffff0000b00ull
#define CSR_FCP_RESPONSE 0xfffff0000d00ull
static const char * const ctype_names[] = {
[0x0] = "control", [0x8] = "not implemented",
[0x1] = "status", [0x9] = "accepted",
[0x2] = "specific inquiry", [0xa] = "rejected",
[0x3] = "notify", [0xb] = "in transition",
[0x4] = "general inquiry", [0xc] = "stable",
[0x5] = "(reserved 0x05)", [0xd] = "changed",
[0x6] = "(reserved 0x06)", [0xe] = "(reserved 0x0e)",
[0x7] = "(reserved 0x07)", [0xf] = "interim",
};
static const char * const subunit_type_names[] = {
[0x00] = "monitor", [0x10] = "(reserved 0x10)",
[0x01] = "audio", [0x11] = "(reserved 0x11)",
[0x02] = "printer", [0x12] = "(reserved 0x12)",
[0x03] = "disc", [0x13] = "(reserved 0x13)",
[0x04] = "tape recorder/player",[0x14] = "(reserved 0x14)",
[0x05] = "tuner", [0x15] = "(reserved 0x15)",
[0x06] = "ca", [0x16] = "(reserved 0x16)",
[0x07] = "camera", [0x17] = "(reserved 0x17)",
[0x08] = "(reserved 0x08)", [0x18] = "(reserved 0x18)",
[0x09] = "panel", [0x19] = "(reserved 0x19)",
[0x0a] = "bulletin board", [0x1a] = "(reserved 0x1a)",
[0x0b] = "camera storage", [0x1b] = "(reserved 0x1b)",
[0x0c] = "(reserved 0x0c)", [0x1c] = "vendor unique",
[0x0d] = "(reserved 0x0d)", [0x1d] = "all subunit types",
[0x0e] = "(reserved 0x0e)", [0x1e] = "subunit_type extended to next byte",
[0x0f] = "(reserved 0x0f)", [0x1f] = "unit",
};
struct avc_enum {
int value;
const char *name;
};
struct avc_field {
const char *name; /* Short name for field. */
int offset; /* Location of field, specified in bits; */
/* negative means from end of packet. */
int width; /* Width of field, 0 means use data_length. */
struct avc_enum *names;
};
struct avc_opcode_info {
const char *name;
struct avc_field fields[8];
};
struct avc_enum power_field_names[] = {
{ 0x70, "on" },
{ 0x60, "off" },
{ }
};
static const struct avc_opcode_info opcode_info[256] = {
/* TA Document 1999026 */
/* AV/C Digital Interface Command Set General Specification 4.0 */
[0xb2] = { "power", {
{ "state", 0, 8, power_field_names }
}
},
[0x30] = { "unit info", {
{ "foo", 0, 8 },
{ "unit_type", 8, 5 },
{ "unit", 13, 3 },
{ "company id", 16, 24 },
}
},
[0x31] = { "subunit info" },
[0x01] = { "reserve" },
[0xb0] = { "version" },
[0x00] = { "vendor dependent" },
[0x02] = { "plug info" },
[0x12] = { "channel usage" },
[0x24] = { "connect" },
[0x20] = { "connect av" },
[0x22] = { "connections" },
[0x11] = { "digital input" },
[0x10] = { "digital output" },
[0x25] = { "disconnect" },
[0x21] = { "disconnect av" },
[0x19] = { "input plug signal format" },
[0x18] = { "output plug signal format" },
[0x1f] = { "general bus setup" },
/* TA Document 1999025 */
/* AV/C Descriptor Mechanism Specification Version 1.0 */
[0x0c] = { "create descriptor" },
[0x08] = { "open descriptor" },
[0x09] = { "read descriptor" },
[0x0a] = { "write descriptor" },
[0x05] = { "open info block" },
[0x06] = { "read info block" },
[0x07] = { "write info block" },
[0x0b] = { "search descriptor" },
[0x0d] = { "object number select" },
/* TA Document 1999015 */
/* AV/C Command Set for Rate Control of Isochronous Data Flow 1.0 */
[0xb3] = { "rate", {
{ "subfunction", 0, 8 },
{ "result", 8, 8 },
{ "plug_type", 16, 8 },
{ "plug_id", 16, 8 },
}
},
/* TA Document 1999008 */
/* AV/C Audio Subunit Specification 1.0 */
[0xb8] = { "function block" },
/* TA Document 2001001 */
/* AV/C Panel Subunit Specification 1.1 */
[0x7d] = { "gui update" },
[0x7e] = { "push gui data" },
[0x7f] = { "user action" },
[0x7c] = { "pass through" },
/* */
[0x26] = { "asynchronous connection" },
};
struct avc_frame {
uint32_t operand0:8;
uint32_t opcode:8;
uint32_t subunit_id:3;
uint32_t subunit_type:5;
uint32_t ctype:4;
uint32_t cts:4;
};
static void
decode_avc(struct link_transaction *t)
{
struct avc_frame *frame =
(struct avc_frame *) t->request->packet.write_block.data;
const struct avc_opcode_info *info;
const char *name;
char buffer[32];
int i;
info = &opcode_info[frame->opcode];
if (info->name == NULL) {
snprintf(buffer, sizeof(buffer),
"(unknown opcode 0x%02x)", frame->opcode);
name = buffer;
} else {
name = info->name;
}
printf("av/c %s, subunit_type=%s, subunit_id=%d, opcode=%s",
ctype_names[frame->ctype], subunit_type_names[frame->subunit_type],
frame->subunit_id, name);
for (i = 0; info->fields[i].name != NULL; i++)
printf(", %s", info->fields[i].name);
printf("\n");
}
int
decode_fcp(struct link_transaction *t)
{
struct avc_frame *frame =
(struct avc_frame *) t->request->packet.write_block.data;
unsigned long long offset =
((unsigned long long) t->request->packet.common.offset_high << 32) |
t->request->packet.common.offset_low;
if (t->request->packet.common.tcode != TCODE_WRITE_BLOCK_REQUEST)
return 0;
if (offset == CSR_FCP_COMMAND || offset == CSR_FCP_RESPONSE) {
switch (frame->cts) {
case 0x00:
decode_avc(t);
break;
case 0x01:
printf("cal fcp frame (cts=0x01)\n");
break;
case 0x02:
printf("ehs fcp frame (cts=0x02)\n");
break;
case 0x03:
printf("havi fcp frame (cts=0x03)\n");
break;
case 0x0e:
printf("vendor specific fcp frame (cts=0x0e)\n");
break;
case 0x0f:
printf("extended cts\n");
break;
default:
printf("reserved fcp frame (ctx=0x%02x)\n", frame->cts);
break;
}
return 1;
}
return 0;
}
| gpl-2.0 |
OMAP4-AOSP/android_kernel_samsung_espresso | arch/blackfin/kernel/stacktrace.c | 13548 | 1119 | /*
* Blackfin stacktrace code (mostly copied from avr32)
*
* Copyright 2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#include <linux/sched.h>
#include <linux/stacktrace.h>
#include <linux/thread_info.h>
#include <linux/module.h>
register unsigned long current_frame_pointer asm("FP");
struct stackframe {
unsigned long fp;
unsigned long rets;
};
/*
* Save stack-backtrace addresses into a stack_trace buffer.
*/
void save_stack_trace(struct stack_trace *trace)
{
unsigned long low, high;
unsigned long fp;
struct stackframe *frame;
int skip = trace->skip;
low = (unsigned long)task_stack_page(current);
high = low + THREAD_SIZE;
fp = current_frame_pointer;
while (fp >= low && fp <= (high - sizeof(*frame))) {
frame = (struct stackframe *)fp;
if (skip) {
skip--;
} else {
trace->entries[trace->nr_entries++] = frame->rets;
if (trace->nr_entries >= trace->max_entries)
break;
}
/*
* The next frame must be at a higher address than the
* current frame.
*/
low = fp + sizeof(*frame);
fp = frame->fp;
}
}
EXPORT_SYMBOL_GPL(save_stack_trace);
| gpl-2.0 |
coherentsolutions/linux-2.6.29-ts4700 | drivers/media/dvb/dvb-usb/opera1.c | 237 | 14215 | /* DVB USB framework compliant Linux driver for the Opera1 DVB-S Card
*
* Copyright (C) 2006 Mario Hlawitschka (dh1pa@amsat.org)
* Copyright (C) 2006 Marco Gittler (g.marco@freenet.de)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation, version 2.
*
* see Documentation/dvb/README.dvb-usb for more information
*/
#define DVB_USB_LOG_PREFIX "opera"
#include "dvb-usb.h"
#include "stv0299.h"
#define OPERA_READ_MSG 0
#define OPERA_WRITE_MSG 1
#define OPERA_I2C_TUNER 0xd1
#define READ_FX2_REG_REQ 0xba
#define READ_MAC_ADDR 0x08
#define OPERA_WRITE_FX2 0xbb
#define OPERA_TUNER_REQ 0xb1
#define REG_1F_SYMBOLRATE_BYTE0 0x1f
#define REG_20_SYMBOLRATE_BYTE1 0x20
#define REG_21_SYMBOLRATE_BYTE2 0x21
#define ADDR_B600_VOLTAGE_13V (0x02)
#define ADDR_B601_VOLTAGE_18V (0x03)
#define ADDR_B1A6_STREAM_CTRL (0x04)
#define ADDR_B880_READ_REMOTE (0x05)
struct opera1_state {
u32 last_key_pressed;
};
struct opera_rc_keys {
u32 keycode;
u32 event;
};
static int dvb_usb_opera1_debug;
module_param_named(debug, dvb_usb_opera1_debug, int, 0644);
MODULE_PARM_DESC(debug,
"set debugging level (1=info,xfer=2,pll=4,ts=8,err=16,rc=32,fw=64 (or-able))."
DVB_USB_DEBUG_STATUS);
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
static int opera1_xilinx_rw(struct usb_device *dev, u8 request, u16 value,
u8 * data, u16 len, int flags)
{
int ret;
u8 r;
u8 u8buf[len];
unsigned int pipe = (flags == OPERA_READ_MSG) ?
usb_rcvctrlpipe(dev,0) : usb_sndctrlpipe(dev, 0);
u8 request_type = (flags == OPERA_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT;
if (flags == OPERA_WRITE_MSG)
memcpy(u8buf, data, len);
ret =
usb_control_msg(dev, pipe, request, request_type | USB_TYPE_VENDOR,
value, 0x0, u8buf, len, 2000);
if (request == OPERA_TUNER_REQ) {
if (usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
OPERA_TUNER_REQ, USB_DIR_IN | USB_TYPE_VENDOR,
0x01, 0x0, &r, 1, 2000)<1 || r!=0x08)
return 0;
}
if (flags == OPERA_READ_MSG)
memcpy(data, u8buf, len);
return ret;
}
/* I2C */
static int opera1_usb_i2c_msgxfer(struct dvb_usb_device *dev, u16 addr,
u8 * buf, u16 len)
{
int ret = 0;
u8 request;
u16 value;
if (!dev) {
info("no usb_device");
return -EINVAL;
}
if (mutex_lock_interruptible(&dev->usb_mutex) < 0)
return -EAGAIN;
switch (addr>>1){
case ADDR_B600_VOLTAGE_13V:
request=0xb6;
value=0x00;
break;
case ADDR_B601_VOLTAGE_18V:
request=0xb6;
value=0x01;
break;
case ADDR_B1A6_STREAM_CTRL:
request=0xb1;
value=0xa6;
break;
case ADDR_B880_READ_REMOTE:
request=0xb8;
value=0x80;
break;
default:
request=0xb1;
value=addr;
}
ret = opera1_xilinx_rw(dev->udev, request,
value, buf, len,
addr&0x01?OPERA_READ_MSG:OPERA_WRITE_MSG);
mutex_unlock(&dev->usb_mutex);
return ret;
}
static int opera1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[],
int num)
{
struct dvb_usb_device *d = i2c_get_adapdata(adap);
int i = 0, tmp = 0;
if (!d)
return -ENODEV;
if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
return -EAGAIN;
for (i = 0; i < num; i++) {
if ((tmp = opera1_usb_i2c_msgxfer(d,
(msg[i].addr<<1)|(msg[i].flags&I2C_M_RD?0x01:0),
msg[i].buf,
msg[i].len
)!= msg[i].len)) {
break;
}
if (dvb_usb_opera1_debug & 0x10)
info("sending i2c mesage %d %d", tmp, msg[i].len);
}
mutex_unlock(&d->i2c_mutex);
return num;
}
static u32 opera1_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C;
}
static struct i2c_algorithm opera1_i2c_algo = {
.master_xfer = opera1_i2c_xfer,
.functionality = opera1_i2c_func,
};
static int opera1_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
{
static u8 command_13v[1]={0x00};
static u8 command_18v[1]={0x01};
struct i2c_msg msg[] = {
{.addr = ADDR_B600_VOLTAGE_13V,.flags = 0,.buf = command_13v,.len = 1},
};
struct dvb_usb_adapter *udev_adap =
(struct dvb_usb_adapter *)(fe->dvb->priv);
if (voltage == SEC_VOLTAGE_18) {
msg[0].addr = ADDR_B601_VOLTAGE_18V;
msg[0].buf = command_18v;
}
i2c_transfer(&udev_adap->dev->i2c_adap, msg, 1);
return 0;
}
static int opera1_stv0299_set_symbol_rate(struct dvb_frontend *fe, u32 srate,
u32 ratio)
{
stv0299_writereg(fe, 0x13, 0x98);
stv0299_writereg(fe, 0x14, 0x95);
stv0299_writereg(fe, REG_1F_SYMBOLRATE_BYTE0, (ratio >> 16) & 0xff);
stv0299_writereg(fe, REG_20_SYMBOLRATE_BYTE1, (ratio >> 8) & 0xff);
stv0299_writereg(fe, REG_21_SYMBOLRATE_BYTE2, (ratio) & 0xf0);
return 0;
}
static u8 opera1_inittab[] = {
0x00, 0xa1,
0x01, 0x15,
0x02, 0x00,
0x03, 0x00,
0x04, 0x7d,
0x05, 0x05,
0x06, 0x02,
0x07, 0x00,
0x0b, 0x00,
0x0c, 0x01,
0x0d, 0x81,
0x0e, 0x44,
0x0f, 0x19,
0x10, 0x3f,
0x11, 0x84,
0x12, 0xda,
0x13, 0x98,
0x14, 0x95,
0x15, 0xc9,
0x16, 0xeb,
0x17, 0x00,
0x18, 0x19,
0x19, 0x8b,
0x1a, 0x00,
0x1b, 0x82,
0x1c, 0x7f,
0x1d, 0x00,
0x1e, 0x00,
REG_1F_SYMBOLRATE_BYTE0, 0x06,
REG_20_SYMBOLRATE_BYTE1, 0x50,
REG_21_SYMBOLRATE_BYTE2, 0x10,
0x22, 0x00,
0x23, 0x00,
0x24, 0x37,
0x25, 0xbc,
0x26, 0x00,
0x27, 0x00,
0x28, 0x00,
0x29, 0x1e,
0x2a, 0x14,
0x2b, 0x1f,
0x2c, 0x09,
0x2d, 0x0a,
0x2e, 0x00,
0x2f, 0x00,
0x30, 0x00,
0x31, 0x1f,
0x32, 0x19,
0x33, 0xfc,
0x34, 0x13,
0xff, 0xff,
};
static struct stv0299_config opera1_stv0299_config = {
.demod_address = 0xd0>>1,
.min_delay_ms = 100,
.mclk = 88000000UL,
.invert = 1,
.skip_reinit = 0,
.lock_output = STV0299_LOCKOUTPUT_0,
.volt13_op0_op1 = STV0299_VOLT13_OP0,
.inittab = opera1_inittab,
.set_symbol_rate = opera1_stv0299_set_symbol_rate,
};
static int opera1_frontend_attach(struct dvb_usb_adapter *d)
{
if ((d->fe =
dvb_attach(stv0299_attach, &opera1_stv0299_config,
&d->dev->i2c_adap)) != NULL) {
d->fe->ops.set_voltage = opera1_set_voltage;
return 0;
}
info("not attached stv0299");
return -EIO;
}
static int opera1_tuner_attach(struct dvb_usb_adapter *adap)
{
dvb_attach(
dvb_pll_attach, adap->fe, 0xc0>>1,
&adap->dev->i2c_adap, DVB_PLL_OPERA1
);
return 0;
}
static int opera1_power_ctrl(struct dvb_usb_device *d, int onoff)
{
u8 val = onoff ? 0x01 : 0x00;
if (dvb_usb_opera1_debug)
info("power %s", onoff ? "on" : "off");
return opera1_xilinx_rw(d->udev, 0xb7, val,
&val, 1, OPERA_WRITE_MSG);
}
static int opera1_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
{
static u8 buf_start[2] = { 0xff, 0x03 };
static u8 buf_stop[2] = { 0xff, 0x00 };
struct i2c_msg start_tuner[] = {
{.addr = ADDR_B1A6_STREAM_CTRL,.buf = onoff ? buf_start : buf_stop,.len = 2},
};
if (dvb_usb_opera1_debug)
info("streaming %s", onoff ? "on" : "off");
i2c_transfer(&adap->dev->i2c_adap, start_tuner, 1);
return 0;
}
static int opera1_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid,
int onoff)
{
u8 b_pid[3];
struct i2c_msg msg[] = {
{.addr = ADDR_B1A6_STREAM_CTRL,.buf = b_pid,.len = 3},
};
if (dvb_usb_opera1_debug)
info("pidfilter index: %d pid: %d %s", index, pid,
onoff ? "on" : "off");
b_pid[0] = (2 * index) + 4;
b_pid[1] = onoff ? (pid & 0xff) : (0x00);
b_pid[2] = onoff ? ((pid >> 8) & 0xff) : (0x00);
i2c_transfer(&adap->dev->i2c_adap, msg, 1);
return 0;
}
static int opera1_pid_filter_control(struct dvb_usb_adapter *adap, int onoff)
{
int u = 0x04;
u8 b_pid[3];
struct i2c_msg msg[] = {
{.addr = ADDR_B1A6_STREAM_CTRL,.buf = b_pid,.len = 3},
};
if (dvb_usb_opera1_debug)
info("%s hw-pidfilter", onoff ? "enable" : "disable");
for (; u < 0x7e; u += 2) {
b_pid[0] = u;
b_pid[1] = 0;
b_pid[2] = 0x80;
i2c_transfer(&adap->dev->i2c_adap, msg, 1);
}
return 0;
}
static struct dvb_usb_rc_key opera1_rc_keys[] = {
{0x5f, 0xa0, KEY_1},
{0x51, 0xaf, KEY_2},
{0x5d, 0xa2, KEY_3},
{0x41, 0xbe, KEY_4},
{0x0b, 0xf5, KEY_5},
{0x43, 0xbd, KEY_6},
{0x47, 0xb8, KEY_7},
{0x49, 0xb6, KEY_8},
{0x05, 0xfa, KEY_9},
{0x45, 0xba, KEY_0},
{0x09, 0xf6, KEY_UP}, /*chanup */
{0x1b, 0xe5, KEY_DOWN}, /*chandown */
{0x5d, 0xa3, KEY_LEFT}, /*voldown */
{0x5f, 0xa1, KEY_RIGHT}, /*volup */
{0x07, 0xf8, KEY_SPACE}, /*tab */
{0x1f, 0xe1, KEY_ENTER}, /*play ok */
{0x1b, 0xe4, KEY_Z}, /*zoom */
{0x59, 0xa6, KEY_M}, /*mute */
{0x5b, 0xa5, KEY_F}, /*tv/f */
{0x19, 0xe7, KEY_R}, /*rec */
{0x01, 0xfe, KEY_S}, /*Stop */
{0x03, 0xfd, KEY_P}, /*pause */
{0x03, 0xfc, KEY_W}, /*<- -> */
{0x07, 0xf9, KEY_C}, /*capture */
{0x47, 0xb9, KEY_Q}, /*exit */
{0x43, 0xbc, KEY_O}, /*power */
};
static int opera1_rc_query(struct dvb_usb_device *dev, u32 * event, int *state)
{
struct opera1_state *opst = dev->priv;
u8 rcbuffer[32];
const u16 startmarker1 = 0x10ed;
const u16 startmarker2 = 0x11ec;
struct i2c_msg read_remote[] = {
{.addr = ADDR_B880_READ_REMOTE,.buf = rcbuffer,.flags = I2C_M_RD,.len = 32},
};
int i = 0;
u32 send_key = 0;
if (i2c_transfer(&dev->i2c_adap, read_remote, 1) == 1) {
for (i = 0; i < 32; i++) {
if (rcbuffer[i])
send_key |= 1;
if (i < 31)
send_key = send_key << 1;
}
if (send_key & 0x8000)
send_key = (send_key << 1) | (send_key >> 15 & 0x01);
if (send_key == 0xffff && opst->last_key_pressed != 0) {
*state = REMOTE_KEY_REPEAT;
*event = opst->last_key_pressed;
return 0;
}
for (; send_key != 0;) {
if (send_key >> 16 == startmarker2) {
break;
} else if (send_key >> 16 == startmarker1) {
send_key =
(send_key & 0xfffeffff) | (startmarker1 << 16);
break;
} else
send_key >>= 1;
}
if (send_key == 0)
return 0;
send_key = (send_key & 0xffff) | 0x0100;
for (i = 0; i < ARRAY_SIZE(opera1_rc_keys); i++) {
if ((opera1_rc_keys[i].custom * 256 +
opera1_rc_keys[i].data) == (send_key & 0xffff)) {
*state = REMOTE_KEY_PRESSED;
*event = opera1_rc_keys[i].event;
opst->last_key_pressed =
opera1_rc_keys[i].event;
break;
}
opst->last_key_pressed = 0;
}
} else
*state = REMOTE_NO_KEY_PRESSED;
return 0;
}
static struct usb_device_id opera1_table[] = {
{USB_DEVICE(USB_VID_CYPRESS, USB_PID_OPERA1_COLD)},
{USB_DEVICE(USB_VID_OPERA1, USB_PID_OPERA1_WARM)},
{}
};
MODULE_DEVICE_TABLE(usb, opera1_table);
static int opera1_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
{
u8 command[] = { READ_MAC_ADDR };
opera1_xilinx_rw(d->udev, 0xb1, 0xa0, command, 1, OPERA_WRITE_MSG);
opera1_xilinx_rw(d->udev, 0xb1, 0xa1, mac, 6, OPERA_READ_MSG);
return 0;
}
static int opera1_xilinx_load_firmware(struct usb_device *dev,
const char *filename)
{
const struct firmware *fw = NULL;
u8 *b, *p;
int ret = 0, i,fpgasize=40;
u8 testval;
info("start downloading fpga firmware %s",filename);
if ((ret = request_firmware(&fw, filename, &dev->dev)) != 0) {
err("did not find the firmware file. (%s) "
"Please see linux/Documentation/dvb/ for more details on firmware-problems.",
filename);
return ret;
} else {
p = kmalloc(fw->size, GFP_KERNEL);
opera1_xilinx_rw(dev, 0xbc, 0x00, &testval, 1, OPERA_READ_MSG);
if (p != NULL && testval != 0x67) {
u8 reset = 0, fpga_command = 0;
memcpy(p, fw->data, fw->size);
/* clear fpga ? */
opera1_xilinx_rw(dev, 0xbc, 0xaa, &fpga_command, 1,
OPERA_WRITE_MSG);
for (i = 0; i < fw->size;) {
if ( (fw->size - i) <fpgasize){
fpgasize=fw->size-i;
}
b = (u8 *) p + i;
if (opera1_xilinx_rw
(dev, OPERA_WRITE_FX2, 0x0, b , fpgasize,
OPERA_WRITE_MSG) != fpgasize
) {
err("error while transferring firmware");
ret = -EINVAL;
break;
}
i = i + fpgasize;
}
/* restart the CPU */
if (ret || opera1_xilinx_rw
(dev, 0xa0, 0xe600, &reset, 1,
OPERA_WRITE_MSG) != 1) {
err("could not restart the USB controller CPU.");
ret = -EINVAL;
}
}
}
kfree(p);
if (fw) {
release_firmware(fw);
}
return ret;
}
static struct dvb_usb_device_properties opera1_properties = {
.caps = DVB_USB_IS_AN_I2C_ADAPTER,
.usb_ctrl = CYPRESS_FX2,
.firmware = "dvb-usb-opera-01.fw",
.size_of_priv = sizeof(struct opera1_state),
.power_ctrl = opera1_power_ctrl,
.i2c_algo = &opera1_i2c_algo,
.rc_key_map = opera1_rc_keys,
.rc_key_map_size = ARRAY_SIZE(opera1_rc_keys),
.rc_interval = 200,
.rc_query = opera1_rc_query,
.read_mac_address = opera1_read_mac_address,
.generic_bulk_ctrl_endpoint = 0x00,
/* parameter for the MPEG2-data transfer */
.num_adapters = 1,
.adapter = {
{
.frontend_attach = opera1_frontend_attach,
.streaming_ctrl = opera1_streaming_ctrl,
.tuner_attach = opera1_tuner_attach,
.caps =
DVB_USB_ADAP_HAS_PID_FILTER |
DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
.pid_filter = opera1_pid_filter,
.pid_filter_ctrl = opera1_pid_filter_control,
.pid_filter_count = 252,
.stream = {
.type = USB_BULK,
.count = 10,
.endpoint = 0x82,
.u = {
.bulk = {
.buffersize = 4096,
}
}
},
}
},
.num_device_descs = 1,
.devices = {
{"Opera1 DVB-S USB2.0",
{&opera1_table[0], NULL},
{&opera1_table[1], NULL},
},
}
};
static int opera1_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
struct usb_device *udev = interface_to_usbdev(intf);
if (udev->descriptor.idProduct == USB_PID_OPERA1_WARM &&
udev->descriptor.idVendor == USB_VID_OPERA1 &&
opera1_xilinx_load_firmware(udev, "dvb-usb-opera1-fpga-01.fw") != 0
) {
return -EINVAL;
}
if (0 != dvb_usb_device_init(intf, &opera1_properties,
THIS_MODULE, NULL, adapter_nr))
return -EINVAL;
return 0;
}
static struct usb_driver opera1_driver = {
.name = "opera1",
.probe = opera1_probe,
.disconnect = dvb_usb_device_exit,
.id_table = opera1_table,
};
static int __init opera1_module_init(void)
{
int result = 0;
if ((result = usb_register(&opera1_driver))) {
err("usb_register failed. Error number %d", result);
}
return result;
}
static void __exit opera1_module_exit(void)
{
usb_deregister(&opera1_driver);
}
module_init(opera1_module_init);
module_exit(opera1_module_exit);
MODULE_AUTHOR("Mario Hlawitschka (c) dh1pa@amsat.org");
MODULE_AUTHOR("Marco Gittler (c) g.marco@freenet.de");
MODULE_DESCRIPTION("Driver for Opera1 DVB-S device");
MODULE_VERSION("0.1");
MODULE_LICENSE("GPL");
| gpl-2.0 |
RenderBroken/OP3-kernel | drivers/video/adf/adf_fbdev.c | 493 | 18822 | /*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/vmalloc.h>
#include <video/adf.h>
#include <video/adf_client.h>
#include <video/adf_fbdev.h>
#include <video/adf_format.h>
#include "adf.h"
struct adf_fbdev_format {
u32 fourcc;
u32 bpp;
u32 r_length;
u32 g_length;
u32 b_length;
u32 a_length;
u32 r_offset;
u32 g_offset;
u32 b_offset;
u32 a_offset;
};
static const struct adf_fbdev_format format_table[] = {
{DRM_FORMAT_RGB332, 8, 3, 3, 2, 0, 5, 2, 0, 0},
{DRM_FORMAT_BGR233, 8, 3, 3, 2, 0, 0, 3, 5, 0},
{DRM_FORMAT_XRGB4444, 16, 4, 4, 4, 0, 8, 4, 0, 0},
{DRM_FORMAT_XBGR4444, 16, 4, 4, 4, 0, 0, 4, 8, 0},
{DRM_FORMAT_RGBX4444, 16, 4, 4, 4, 0, 12, 8, 4, 0},
{DRM_FORMAT_BGRX4444, 16, 4, 4, 4, 0, 0, 4, 8, 0},
{DRM_FORMAT_ARGB4444, 16, 4, 4, 4, 4, 8, 4, 0, 12},
{DRM_FORMAT_ABGR4444, 16, 4, 4, 4, 4, 0, 4, 8, 12},
{DRM_FORMAT_RGBA4444, 16, 4, 4, 4, 4, 12, 8, 4, 0},
{DRM_FORMAT_BGRA4444, 16, 4, 4, 4, 4, 0, 4, 8, 0},
{DRM_FORMAT_XRGB1555, 16, 5, 5, 5, 0, 10, 5, 0, 0},
{DRM_FORMAT_XBGR1555, 16, 5, 5, 5, 0, 0, 5, 10, 0},
{DRM_FORMAT_RGBX5551, 16, 5, 5, 5, 0, 11, 6, 1, 0},
{DRM_FORMAT_BGRX5551, 16, 5, 5, 5, 0, 1, 6, 11, 0},
{DRM_FORMAT_ARGB1555, 16, 5, 5, 5, 1, 10, 5, 0, 15},
{DRM_FORMAT_ABGR1555, 16, 5, 5, 5, 1, 0, 5, 10, 15},
{DRM_FORMAT_RGBA5551, 16, 5, 5, 5, 1, 11, 6, 1, 0},
{DRM_FORMAT_BGRA5551, 16, 5, 5, 5, 1, 1, 6, 11, 0},
{DRM_FORMAT_RGB565, 16, 5, 6, 5, 0, 11, 5, 0, 0},
{DRM_FORMAT_BGR565, 16, 5, 6, 5, 0, 0, 5, 11, 0},
{DRM_FORMAT_RGB888, 24, 8, 8, 8, 0, 16, 8, 0, 0},
{DRM_FORMAT_BGR888, 24, 8, 8, 8, 0, 0, 8, 16, 0},
{DRM_FORMAT_XRGB8888, 32, 8, 8, 8, 0, 16, 8, 0, 0},
{DRM_FORMAT_XBGR8888, 32, 8, 8, 8, 0, 0, 8, 16, 0},
{DRM_FORMAT_RGBX8888, 32, 8, 8, 8, 0, 24, 16, 8, 0},
{DRM_FORMAT_BGRX8888, 32, 8, 8, 8, 0, 8, 16, 24, 0},
{DRM_FORMAT_ARGB8888, 32, 8, 8, 8, 8, 16, 8, 0, 24},
{DRM_FORMAT_ABGR8888, 32, 8, 8, 8, 8, 0, 8, 16, 24},
{DRM_FORMAT_RGBA8888, 32, 8, 8, 8, 8, 24, 16, 8, 0},
{DRM_FORMAT_BGRA8888, 32, 8, 8, 8, 8, 8, 16, 24, 0},
{DRM_FORMAT_XRGB2101010, 32, 10, 10, 10, 0, 20, 10, 0, 0},
{DRM_FORMAT_XBGR2101010, 32, 10, 10, 10, 0, 0, 10, 20, 0},
{DRM_FORMAT_RGBX1010102, 32, 10, 10, 10, 0, 22, 12, 2, 0},
{DRM_FORMAT_BGRX1010102, 32, 10, 10, 10, 0, 2, 12, 22, 0},
{DRM_FORMAT_ARGB2101010, 32, 10, 10, 10, 2, 20, 10, 0, 30},
{DRM_FORMAT_ABGR2101010, 32, 10, 10, 10, 2, 0, 10, 20, 30},
{DRM_FORMAT_RGBA1010102, 32, 10, 10, 10, 2, 22, 12, 2, 0},
{DRM_FORMAT_BGRA1010102, 32, 10, 10, 10, 2, 2, 12, 22, 0},
};
static u32 drm_fourcc_from_fb_var(struct fb_var_screeninfo *var)
{
size_t i;
for (i = 0; i < ARRAY_SIZE(format_table); i++) {
const struct adf_fbdev_format *f = &format_table[i];
if (var->red.length == f->r_length &&
var->red.offset == f->r_offset &&
var->green.length == f->g_length &&
var->green.offset == f->g_offset &&
var->blue.length == f->b_length &&
var->blue.offset == f->b_offset &&
var->transp.length == f->a_length &&
(var->transp.length == 0 ||
var->transp.offset == f->a_offset))
return f->fourcc;
}
return 0;
}
static const struct adf_fbdev_format *fbdev_format_info(u32 format)
{
size_t i;
for (i = 0; i < ARRAY_SIZE(format_table); i++) {
const struct adf_fbdev_format *f = &format_table[i];
if (f->fourcc == format)
return f;
}
BUG();
}
void adf_modeinfo_to_fb_videomode(const struct drm_mode_modeinfo *mode,
struct fb_videomode *vmode)
{
memset(vmode, 0, sizeof(*vmode));
vmode->refresh = mode->vrefresh;
vmode->xres = mode->hdisplay;
vmode->yres = mode->vdisplay;
vmode->pixclock = mode->clock ? KHZ2PICOS(mode->clock) : 0;
vmode->left_margin = mode->htotal - mode->hsync_end;
vmode->right_margin = mode->hsync_start - mode->hdisplay;
vmode->upper_margin = mode->vtotal - mode->vsync_end;
vmode->lower_margin = mode->vsync_start - mode->vdisplay;
vmode->hsync_len = mode->hsync_end - mode->hsync_start;
vmode->vsync_len = mode->vsync_end - mode->vsync_start;
vmode->sync = 0;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
vmode->sync |= FB_SYNC_HOR_HIGH_ACT;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
vmode->sync |= FB_SYNC_VERT_HIGH_ACT;
if (mode->flags & DRM_MODE_FLAG_PCSYNC)
vmode->sync |= FB_SYNC_COMP_HIGH_ACT;
if (mode->flags & DRM_MODE_FLAG_BCAST)
vmode->sync |= FB_SYNC_BROADCAST;
vmode->vmode = 0;
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vmode->vmode |= FB_VMODE_INTERLACED;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
vmode->vmode |= FB_VMODE_DOUBLE;
}
EXPORT_SYMBOL(adf_modeinfo_to_fb_videomode);
void adf_modeinfo_from_fb_videomode(const struct fb_videomode *vmode,
struct drm_mode_modeinfo *mode)
{
memset(mode, 0, sizeof(*mode));
mode->hdisplay = vmode->xres;
mode->hsync_start = mode->hdisplay + vmode->right_margin;
mode->hsync_end = mode->hsync_start + vmode->hsync_len;
mode->htotal = mode->hsync_end + vmode->left_margin;
mode->vdisplay = vmode->yres;
mode->vsync_start = mode->vdisplay + vmode->lower_margin;
mode->vsync_end = mode->vsync_start + vmode->vsync_len;
mode->vtotal = mode->vsync_end + vmode->upper_margin;
mode->clock = vmode->pixclock ? PICOS2KHZ(vmode->pixclock) : 0;
mode->flags = 0;
if (vmode->sync & FB_SYNC_HOR_HIGH_ACT)
mode->flags |= DRM_MODE_FLAG_PHSYNC;
if (vmode->sync & FB_SYNC_VERT_HIGH_ACT)
mode->flags |= DRM_MODE_FLAG_PVSYNC;
if (vmode->sync & FB_SYNC_COMP_HIGH_ACT)
mode->flags |= DRM_MODE_FLAG_PCSYNC;
if (vmode->sync & FB_SYNC_BROADCAST)
mode->flags |= DRM_MODE_FLAG_BCAST;
if (vmode->vmode & FB_VMODE_INTERLACED)
mode->flags |= DRM_MODE_FLAG_INTERLACE;
if (vmode->vmode & FB_VMODE_DOUBLE)
mode->flags |= DRM_MODE_FLAG_DBLSCAN;
if (vmode->refresh)
mode->vrefresh = vmode->refresh;
else
adf_modeinfo_set_vrefresh(mode);
if (vmode->name)
strlcpy(mode->name, vmode->name, sizeof(mode->name));
else
adf_modeinfo_set_name(mode);
}
EXPORT_SYMBOL(adf_modeinfo_from_fb_videomode);
static int adf_fbdev_post(struct adf_fbdev *fbdev)
{
struct adf_buffer buf;
struct sync_fence *complete_fence;
int ret = 0;
memset(&buf, 0, sizeof(buf));
buf.overlay_engine = fbdev->eng;
buf.w = fbdev->info->var.xres;
buf.h = fbdev->info->var.yres;
buf.format = fbdev->format;
buf.dma_bufs[0] = fbdev->dma_buf;
buf.offset[0] = fbdev->offset +
fbdev->info->var.yoffset * fbdev->pitch +
fbdev->info->var.xoffset *
(fbdev->info->var.bits_per_pixel / 8);
buf.pitch[0] = fbdev->pitch;
buf.n_planes = 1;
complete_fence = adf_interface_simple_post(fbdev->intf, &buf);
if (IS_ERR(complete_fence)) {
ret = PTR_ERR(complete_fence);
goto done;
}
sync_fence_put(complete_fence);
done:
return ret;
}
static const u16 vga_palette[][3] = {
{0x0000, 0x0000, 0x0000},
{0x0000, 0x0000, 0xAAAA},
{0x0000, 0xAAAA, 0x0000},
{0x0000, 0xAAAA, 0xAAAA},
{0xAAAA, 0x0000, 0x0000},
{0xAAAA, 0x0000, 0xAAAA},
{0xAAAA, 0x5555, 0x0000},
{0xAAAA, 0xAAAA, 0xAAAA},
{0x5555, 0x5555, 0x5555},
{0x5555, 0x5555, 0xFFFF},
{0x5555, 0xFFFF, 0x5555},
{0x5555, 0xFFFF, 0xFFFF},
{0xFFFF, 0x5555, 0x5555},
{0xFFFF, 0x5555, 0xFFFF},
{0xFFFF, 0xFFFF, 0x5555},
{0xFFFF, 0xFFFF, 0xFFFF},
};
static int adf_fb_alloc(struct adf_fbdev *fbdev)
{
int ret;
ret = adf_interface_simple_buffer_alloc(fbdev->intf,
fbdev->default_xres_virtual,
fbdev->default_yres_virtual,
fbdev->default_format,
&fbdev->dma_buf, &fbdev->offset, &fbdev->pitch);
if (ret < 0) {
dev_err(fbdev->info->dev, "allocating fb failed: %d\n", ret);
return ret;
}
fbdev->vaddr = dma_buf_vmap(fbdev->dma_buf);
if (!fbdev->vaddr) {
ret = -ENOMEM;
dev_err(fbdev->info->dev, "vmapping fb failed\n");
goto err_vmap;
}
fbdev->info->fix.line_length = fbdev->pitch;
fbdev->info->var.xres_virtual = fbdev->default_xres_virtual;
fbdev->info->var.yres_virtual = fbdev->default_yres_virtual;
fbdev->info->fix.smem_len = fbdev->dma_buf->size;
fbdev->info->screen_base = fbdev->vaddr;
return 0;
err_vmap:
dma_buf_put(fbdev->dma_buf);
return ret;
}
static void adf_fb_destroy(struct adf_fbdev *fbdev)
{
dma_buf_vunmap(fbdev->dma_buf, fbdev->vaddr);
dma_buf_put(fbdev->dma_buf);
}
static void adf_fbdev_set_format(struct adf_fbdev *fbdev, u32 format)
{
size_t i;
const struct adf_fbdev_format *info = fbdev_format_info(format);
for (i = 0; i < ARRAY_SIZE(vga_palette); i++) {
u16 r = vga_palette[i][0];
u16 g = vga_palette[i][1];
u16 b = vga_palette[i][2];
r >>= (16 - info->r_length);
g >>= (16 - info->g_length);
b >>= (16 - info->b_length);
fbdev->pseudo_palette[i] =
(r << info->r_offset) |
(g << info->g_offset) |
(b << info->b_offset);
if (info->a_length) {
u16 a = BIT(info->a_length) - 1;
fbdev->pseudo_palette[i] |= (a << info->a_offset);
}
}
fbdev->info->var.bits_per_pixel = adf_format_bpp(format);
fbdev->info->var.red.length = info->r_length;
fbdev->info->var.red.offset = info->r_offset;
fbdev->info->var.green.length = info->g_length;
fbdev->info->var.green.offset = info->g_offset;
fbdev->info->var.blue.length = info->b_length;
fbdev->info->var.blue.offset = info->b_offset;
fbdev->info->var.transp.length = info->a_length;
fbdev->info->var.transp.offset = info->a_offset;
fbdev->format = format;
}
static void adf_fbdev_fill_modelist(struct adf_fbdev *fbdev)
{
struct drm_mode_modeinfo *modelist;
struct fb_videomode fbmode;
size_t n_modes, i;
int ret = 0;
n_modes = adf_interface_modelist(fbdev->intf, NULL, 0);
modelist = kzalloc(sizeof(modelist[0]) * n_modes, GFP_KERNEL);
if (!modelist) {
dev_warn(fbdev->info->dev, "allocating new modelist failed; keeping old modelist\n");
return;
}
adf_interface_modelist(fbdev->intf, modelist, n_modes);
fb_destroy_modelist(&fbdev->info->modelist);
for (i = 0; i < n_modes; i++) {
adf_modeinfo_to_fb_videomode(&modelist[i], &fbmode);
ret = fb_add_videomode(&fbmode, &fbdev->info->modelist);
if (ret < 0)
dev_warn(fbdev->info->dev, "adding mode %s to modelist failed: %d\n",
modelist[i].name, ret);
}
kfree(modelist);
}
/**
* adf_fbdev_open - default implementation of fbdev open op
*/
int adf_fbdev_open(struct fb_info *info, int user)
{
struct adf_fbdev *fbdev = info->par;
int ret;
mutex_lock(&fbdev->refcount_lock);
if (unlikely(fbdev->refcount == UINT_MAX)) {
ret = -EMFILE;
goto done;
}
if (!fbdev->refcount) {
struct drm_mode_modeinfo mode;
struct fb_videomode fbmode;
struct adf_device *dev = adf_interface_parent(fbdev->intf);
ret = adf_device_attach(dev, fbdev->eng, fbdev->intf);
if (ret < 0 && ret != -EALREADY)
goto done;
ret = adf_fb_alloc(fbdev);
if (ret < 0)
goto done;
adf_interface_current_mode(fbdev->intf, &mode);
adf_modeinfo_to_fb_videomode(&mode, &fbmode);
fb_videomode_to_var(&fbdev->info->var, &fbmode);
adf_fbdev_set_format(fbdev, fbdev->default_format);
adf_fbdev_fill_modelist(fbdev);
}
ret = adf_fbdev_post(fbdev);
if (ret < 0) {
if (!fbdev->refcount)
adf_fb_destroy(fbdev);
goto done;
}
fbdev->refcount++;
done:
mutex_unlock(&fbdev->refcount_lock);
return ret;
}
EXPORT_SYMBOL(adf_fbdev_open);
/**
* adf_fbdev_release - default implementation of fbdev release op
*/
int adf_fbdev_release(struct fb_info *info, int user)
{
struct adf_fbdev *fbdev = info->par;
mutex_lock(&fbdev->refcount_lock);
BUG_ON(!fbdev->refcount);
fbdev->refcount--;
if (!fbdev->refcount)
adf_fb_destroy(fbdev);
mutex_unlock(&fbdev->refcount_lock);
return 0;
}
EXPORT_SYMBOL(adf_fbdev_release);
/**
* adf_fbdev_check_var - default implementation of fbdev check_var op
*/
int adf_fbdev_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct adf_fbdev *fbdev = info->par;
bool valid_format = true;
u32 format = drm_fourcc_from_fb_var(var);
u32 pitch = var->xres_virtual * var->bits_per_pixel / 8;
if (!format) {
dev_dbg(info->dev, "%s: unrecognized format\n", __func__);
valid_format = false;
}
if (valid_format && var->grayscale) {
dev_dbg(info->dev, "%s: grayscale modes not supported\n",
__func__);
valid_format = false;
}
if (valid_format && var->nonstd) {
dev_dbg(info->dev, "%s: nonstandard formats not supported\n",
__func__);
valid_format = false;
}
if (valid_format && !adf_overlay_engine_supports_format(fbdev->eng,
format)) {
char format_str[ADF_FORMAT_STR_SIZE];
adf_format_str(format, format_str);
dev_dbg(info->dev, "%s: format %s not supported by overlay engine %s\n",
__func__, format_str, fbdev->eng->base.name);
valid_format = false;
}
if (valid_format && pitch > fbdev->pitch) {
dev_dbg(info->dev, "%s: fb pitch too small for var (pitch = %u, xres_virtual = %u, bits_per_pixel = %u)\n",
__func__, fbdev->pitch, var->xres_virtual,
var->bits_per_pixel);
valid_format = false;
}
if (valid_format && var->yres_virtual > fbdev->default_yres_virtual) {
dev_dbg(info->dev, "%s: fb height too small for var (h = %u, yres_virtual = %u)\n",
__func__, fbdev->default_yres_virtual,
var->yres_virtual);
valid_format = false;
}
if (valid_format) {
var->activate = info->var.activate;
var->height = info->var.height;
var->width = info->var.width;
var->accel_flags = info->var.accel_flags;
var->rotate = info->var.rotate;
var->colorspace = info->var.colorspace;
/* userspace can't change these */
} else {
/* if any part of the format is invalid then fixing it up is
impractical, so save just the modesetting bits and
overwrite everything else */
struct fb_videomode mode;
fb_var_to_videomode(&mode, var);
memcpy(var, &info->var, sizeof(*var));
fb_videomode_to_var(var, &mode);
}
return 0;
}
EXPORT_SYMBOL(adf_fbdev_check_var);
/**
* adf_fbdev_set_par - default implementation of fbdev set_par op
*/
int adf_fbdev_set_par(struct fb_info *info)
{
struct adf_fbdev *fbdev = info->par;
struct adf_interface *intf = fbdev->intf;
struct fb_videomode vmode;
struct drm_mode_modeinfo mode;
int ret;
u32 format = drm_fourcc_from_fb_var(&info->var);
fb_var_to_videomode(&vmode, &info->var);
adf_modeinfo_from_fb_videomode(&vmode, &mode);
ret = adf_interface_set_mode(intf, &mode);
if (ret < 0)
return ret;
ret = adf_fbdev_post(fbdev);
if (ret < 0)
return ret;
if (format != fbdev->format)
adf_fbdev_set_format(fbdev, format);
return 0;
}
EXPORT_SYMBOL(adf_fbdev_set_par);
/**
* adf_fbdev_blank - default implementation of fbdev blank op
*/
int adf_fbdev_blank(int blank, struct fb_info *info)
{
struct adf_fbdev *fbdev = info->par;
struct adf_interface *intf = fbdev->intf;
u8 dpms_state;
switch (blank) {
case FB_BLANK_UNBLANK:
dpms_state = DRM_MODE_DPMS_ON;
break;
case FB_BLANK_NORMAL:
dpms_state = DRM_MODE_DPMS_STANDBY;
break;
case FB_BLANK_VSYNC_SUSPEND:
dpms_state = DRM_MODE_DPMS_SUSPEND;
break;
case FB_BLANK_HSYNC_SUSPEND:
dpms_state = DRM_MODE_DPMS_STANDBY;
break;
case FB_BLANK_POWERDOWN:
dpms_state = DRM_MODE_DPMS_OFF;
break;
default:
return -EINVAL;
}
return adf_interface_blank(intf, dpms_state);
}
EXPORT_SYMBOL(adf_fbdev_blank);
/**
* adf_fbdev_pan_display - default implementation of fbdev pan_display op
*/
int adf_fbdev_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct adf_fbdev *fbdev = info->par;
return adf_fbdev_post(fbdev);
}
EXPORT_SYMBOL(adf_fbdev_pan_display);
/**
* adf_fbdev_mmap - default implementation of fbdev mmap op
*/
int adf_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct adf_fbdev *fbdev = info->par;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
return dma_buf_mmap(fbdev->dma_buf, vma, 0);
}
EXPORT_SYMBOL(adf_fbdev_mmap);
/**
* adf_fbdev_init - initialize helper to wrap ADF device in fbdev API
*
* @fbdev: the fbdev helper
* @interface: the ADF interface that will display the framebuffer
* @eng: the ADF overlay engine that will scan out the framebuffer
* @xres_virtual: the virtual width of the framebuffer
* @yres_virtual: the virtual height of the framebuffer
* @format: the format of the framebuffer
* @fbops: the device's fbdev ops
* @fmt: formatting for the framebuffer identification string
* @...: variable arguments
*
* @format must be a standard, non-indexed RGB format, i.e.,
* adf_format_is_rgb(@format) && @format != @DRM_FORMAT_C8.
*
* Returns 0 on success or -errno on failure.
*/
int adf_fbdev_init(struct adf_fbdev *fbdev, struct adf_interface *interface,
struct adf_overlay_engine *eng,
u16 xres_virtual, u16 yres_virtual, u32 format,
struct fb_ops *fbops, const char *fmt, ...)
{
struct adf_device *parent = adf_interface_parent(interface);
struct device *dev = &parent->base.dev;
u16 width_mm, height_mm;
va_list args;
int ret;
if (!adf_format_is_rgb(format) ||
format == DRM_FORMAT_C8) {
dev_err(dev, "fbdev helper does not support format %u\n",
format);
return -EINVAL;
}
memset(fbdev, 0, sizeof(*fbdev));
fbdev->intf = interface;
fbdev->eng = eng;
fbdev->info = framebuffer_alloc(0, dev);
if (!fbdev->info) {
dev_err(dev, "allocating framebuffer device failed\n");
return -ENOMEM;
}
mutex_init(&fbdev->refcount_lock);
fbdev->default_xres_virtual = xres_virtual;
fbdev->default_yres_virtual = yres_virtual;
fbdev->default_format = format;
fbdev->info->flags = FBINFO_FLAG_DEFAULT;
ret = adf_interface_get_screen_size(interface, &width_mm, &height_mm);
if (ret < 0) {
width_mm = 0;
height_mm = 0;
}
fbdev->info->var.width = width_mm;
fbdev->info->var.height = height_mm;
fbdev->info->var.activate = FB_ACTIVATE_VBL;
va_start(args, fmt);
vsnprintf(fbdev->info->fix.id, sizeof(fbdev->info->fix.id), fmt, args);
va_end(args);
fbdev->info->fix.type = FB_TYPE_PACKED_PIXELS;
fbdev->info->fix.visual = FB_VISUAL_TRUECOLOR;
fbdev->info->fix.xpanstep = 1;
fbdev->info->fix.ypanstep = 1;
INIT_LIST_HEAD(&fbdev->info->modelist);
fbdev->info->fbops = fbops;
fbdev->info->pseudo_palette = fbdev->pseudo_palette;
fbdev->info->par = fbdev;
ret = register_framebuffer(fbdev->info);
if (ret < 0) {
dev_err(dev, "registering framebuffer failed: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL(adf_fbdev_init);
/**
* adf_fbdev_destroy - destroy helper to wrap ADF device in fbdev API
*
* @fbdev: the fbdev helper
*/
void adf_fbdev_destroy(struct adf_fbdev *fbdev)
{
unregister_framebuffer(fbdev->info);
BUG_ON(fbdev->refcount);
mutex_destroy(&fbdev->refcount_lock);
framebuffer_release(fbdev->info);
}
EXPORT_SYMBOL(adf_fbdev_destroy);
| gpl-2.0 |
Arc-Team/android_kernel_samsung_jflte | drivers/spi/spi_qsd.c | 493 | 63005 | /* Copyright (c) 2008-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* SPI driver for Qualcomm MSM platforms
*
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/io.h>
#include <linux/debugfs.h>
#include <mach/msm_spi.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <mach/dma.h>
#include <asm/atomic.h>
#include <linux/mutex.h>
#include <linux/gpio.h>
#include <linux/remote_spinlock.h>
#include <linux/pm_qos.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include "spi_qsd.h"
static int msm_spi_pm_resume_runtime(struct device *device);
static int msm_spi_pm_suspend_runtime(struct device *device);
static inline int msm_spi_configure_gsbi(struct msm_spi *dd,
struct platform_device *pdev)
{
struct resource *resource;
unsigned long gsbi_mem_phys_addr;
size_t gsbi_mem_size;
void __iomem *gsbi_base;
resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!resource)
return 0;
gsbi_mem_phys_addr = resource->start;
gsbi_mem_size = resource_size(resource);
if (!devm_request_mem_region(&pdev->dev, gsbi_mem_phys_addr,
gsbi_mem_size, SPI_DRV_NAME))
return -ENXIO;
gsbi_base = devm_ioremap(&pdev->dev, gsbi_mem_phys_addr,
gsbi_mem_size);
if (!gsbi_base)
return -ENXIO;
/* Set GSBI to SPI mode */
writel_relaxed(GSBI_SPI_CONFIG, gsbi_base + GSBI_CTRL_REG);
return 0;
}
static inline void msm_spi_register_init(struct msm_spi *dd)
{
writel_relaxed(0x00000001, dd->base + SPI_SW_RESET);
msm_spi_set_state(dd, SPI_OP_STATE_RESET);
writel_relaxed(0x00000000, dd->base + SPI_OPERATIONAL);
writel_relaxed(0x00000000, dd->base + SPI_CONFIG);
writel_relaxed(0x00000000, dd->base + SPI_IO_MODES);
if (dd->qup_ver)
writel_relaxed(0x00000000, dd->base + QUP_OPERATIONAL_MASK);
}
static inline int msm_spi_request_gpios(struct msm_spi *dd)
{
int i;
int result = 0;
for (i = 0; i < ARRAY_SIZE(spi_rsrcs); ++i) {
if (dd->spi_gpios[i] >= 0) {
result = gpio_request(dd->spi_gpios[i], spi_rsrcs[i]);
if (result) {
dev_err(dd->dev, "%s: gpio_request for pin %d "
"failed with error %d\n", __func__,
dd->spi_gpios[i], result);
goto error;
}
}
}
return 0;
error:
for (; --i >= 0;) {
if (dd->spi_gpios[i] >= 0)
gpio_free(dd->spi_gpios[i]);
}
return result;
}
static inline void msm_spi_free_gpios(struct msm_spi *dd)
{
int i;
for (i = 0; i < ARRAY_SIZE(spi_rsrcs); ++i) {
if (dd->spi_gpios[i] >= 0)
gpio_free(dd->spi_gpios[i]);
}
for (i = 0; i < ARRAY_SIZE(spi_cs_rsrcs); ++i) {
if (dd->cs_gpios[i].valid) {
gpio_free(dd->cs_gpios[i].gpio_num);
dd->cs_gpios[i].valid = 0;
}
}
}
/**
* msm_spi_clk_max_rate: finds the nearest lower rate for a clk
* @clk the clock for which to find nearest lower rate
* @rate clock frequency in Hz
* @return nearest lower rate or negative error value
*
* Public clock API extends clk_round_rate which is a ceiling function. This
* function is a floor function implemented as a binary search using the
* ceiling function.
*/
static long msm_spi_clk_max_rate(struct clk *clk, unsigned long rate)
{
long lowest_available, nearest_low, step_size, cur;
long step_direction = -1;
long guess = rate;
int max_steps = 10;
cur = clk_round_rate(clk, rate);
if (cur == rate)
return rate;
/* if we got here then: cur > rate */
lowest_available = clk_round_rate(clk, 0);
if (lowest_available > rate)
return -EINVAL;
step_size = (rate - lowest_available) >> 1;
nearest_low = lowest_available;
while (max_steps-- && step_size) {
guess += step_size * step_direction;
cur = clk_round_rate(clk, guess);
if ((cur < rate) && (cur > nearest_low))
nearest_low = cur;
/*
* if we stepped too far, then start stepping in the other
* direction with half the step size
*/
if (((cur > rate) && (step_direction > 0))
|| ((cur < rate) && (step_direction < 0))) {
step_direction = -step_direction;
step_size >>= 1;
}
}
return nearest_low;
}
static void msm_spi_clock_set(struct msm_spi *dd, int speed)
{
long rate;
int rc;
rate = msm_spi_clk_max_rate(dd->clk, speed);
if (rate < 0) {
dev_err(dd->dev,
"%s: no match found for requested clock frequency:%d",
__func__, speed);
return;
}
rc = clk_set_rate(dd->clk, rate);
if (!rc)
dd->clock_speed = rate;
}
static int msm_spi_calculate_size(int *fifo_size,
int *block_size,
int block,
int mult)
{
int words;
switch (block) {
case 0:
words = 1; /* 4 bytes */
break;
case 1:
words = 4; /* 16 bytes */
break;
case 2:
words = 8; /* 32 bytes */
break;
default:
return -EINVAL;
}
switch (mult) {
case 0:
*fifo_size = words * 2;
break;
case 1:
*fifo_size = words * 4;
break;
case 2:
*fifo_size = words * 8;
break;
case 3:
*fifo_size = words * 16;
break;
default:
return -EINVAL;
}
*block_size = words * sizeof(u32); /* in bytes */
return 0;
}
static void get_next_transfer(struct msm_spi *dd)
{
struct spi_transfer *t = dd->cur_transfer;
if (t->transfer_list.next != &dd->cur_msg->transfers) {
dd->cur_transfer = list_entry(t->transfer_list.next,
struct spi_transfer,
transfer_list);
dd->write_buf = dd->cur_transfer->tx_buf;
dd->read_buf = dd->cur_transfer->rx_buf;
}
}
static void __init msm_spi_calculate_fifo_size(struct msm_spi *dd)
{
u32 spi_iom;
int block;
int mult;
spi_iom = readl_relaxed(dd->base + SPI_IO_MODES);
block = (spi_iom & SPI_IO_M_INPUT_BLOCK_SIZE) >> INPUT_BLOCK_SZ_SHIFT;
mult = (spi_iom & SPI_IO_M_INPUT_FIFO_SIZE) >> INPUT_FIFO_SZ_SHIFT;
if (msm_spi_calculate_size(&dd->input_fifo_size, &dd->input_block_size,
block, mult)) {
goto fifo_size_err;
}
block = (spi_iom & SPI_IO_M_OUTPUT_BLOCK_SIZE) >> OUTPUT_BLOCK_SZ_SHIFT;
mult = (spi_iom & SPI_IO_M_OUTPUT_FIFO_SIZE) >> OUTPUT_FIFO_SZ_SHIFT;
if (msm_spi_calculate_size(&dd->output_fifo_size,
&dd->output_block_size, block, mult)) {
goto fifo_size_err;
}
/* DM mode is not available for this block size */
if (dd->input_block_size == 4 || dd->output_block_size == 4)
dd->use_dma = 0;
if (dd->use_dma) {
dd->input_burst_size = max(dd->input_block_size,
DM_BURST_SIZE);
dd->output_burst_size = max(dd->output_block_size,
DM_BURST_SIZE);
}
return;
fifo_size_err:
dd->use_dma = 0;
pr_err("%s: invalid FIFO size, SPI_IO_MODES=0x%x\n", __func__, spi_iom);
return;
}
static void msm_spi_read_word_from_fifo(struct msm_spi *dd)
{
u32 data_in;
int i;
int shift;
data_in = readl_relaxed(dd->base + SPI_INPUT_FIFO);
if (dd->read_buf) {
for (i = 0; (i < dd->bytes_per_word) &&
dd->rx_bytes_remaining; i++) {
/* The data format depends on bytes_per_word:
4 bytes: 0x12345678
3 bytes: 0x00123456
2 bytes: 0x00001234
1 byte : 0x00000012
*/
shift = 8 * (dd->bytes_per_word - i - 1);
*dd->read_buf++ = (data_in & (0xFF << shift)) >> shift;
dd->rx_bytes_remaining--;
}
} else {
if (dd->rx_bytes_remaining >= dd->bytes_per_word)
dd->rx_bytes_remaining -= dd->bytes_per_word;
else
dd->rx_bytes_remaining = 0;
}
dd->read_xfr_cnt++;
if (dd->multi_xfr) {
if (!dd->rx_bytes_remaining)
dd->read_xfr_cnt = 0;
else if ((dd->read_xfr_cnt * dd->bytes_per_word) ==
dd->read_len) {
struct spi_transfer *t = dd->cur_rx_transfer;
if (t->transfer_list.next != &dd->cur_msg->transfers) {
t = list_entry(t->transfer_list.next,
struct spi_transfer,
transfer_list);
dd->read_buf = t->rx_buf;
dd->read_len = t->len;
dd->read_xfr_cnt = 0;
dd->cur_rx_transfer = t;
}
}
}
}
static inline bool msm_spi_is_valid_state(struct msm_spi *dd)
{
u32 spi_op = readl_relaxed(dd->base + SPI_STATE);
return spi_op & SPI_OP_STATE_VALID;
}
static inline void msm_spi_udelay(unsigned long delay_usecs)
{
/*
* For smaller values of delay, context switch time
* would negate the usage of usleep
*/
if (delay_usecs > 20)
usleep_range(delay_usecs, delay_usecs);
else if (delay_usecs)
udelay(delay_usecs);
}
static inline int msm_spi_wait_valid(struct msm_spi *dd)
{
unsigned long delay = 0;
unsigned long timeout = 0;
if (dd->clock_speed == 0)
return -EINVAL;
/*
* Based on the SPI clock speed, sufficient time
* should be given for the SPI state transition
* to occur
*/
delay = (10 * USEC_PER_SEC) / dd->clock_speed;
/*
* For small delay values, the default timeout would
* be one jiffy
*/
if (delay < SPI_DELAY_THRESHOLD)
delay = SPI_DELAY_THRESHOLD;
/* Adding one to round off to the nearest jiffy */
timeout = jiffies + msecs_to_jiffies(delay * SPI_DEFAULT_TIMEOUT) + 1;
while (!msm_spi_is_valid_state(dd)) {
if (time_after(jiffies, timeout)) {
if (!msm_spi_is_valid_state(dd)) {
if (dd->cur_msg)
dd->cur_msg->status = -EIO;
dev_err(dd->dev, "%s: SPI operational state"
"not valid\n", __func__);
return -ETIMEDOUT;
} else
return 0;
}
msm_spi_udelay(delay);
}
return 0;
}
static inline int msm_spi_set_state(struct msm_spi *dd,
enum msm_spi_state state)
{
enum msm_spi_state cur_state;
if (msm_spi_wait_valid(dd))
return -EIO;
cur_state = readl_relaxed(dd->base + SPI_STATE);
/* Per spec:
For PAUSE_STATE to RESET_STATE, two writes of (10) are required */
if (((cur_state & SPI_OP_STATE) == SPI_OP_STATE_PAUSE) &&
(state == SPI_OP_STATE_RESET)) {
writel_relaxed(SPI_OP_STATE_CLEAR_BITS, dd->base + SPI_STATE);
writel_relaxed(SPI_OP_STATE_CLEAR_BITS, dd->base + SPI_STATE);
} else {
writel_relaxed((cur_state & ~SPI_OP_STATE) | state,
dd->base + SPI_STATE);
}
if (msm_spi_wait_valid(dd))
return -EIO;
return 0;
}
static inline void msm_spi_add_configs(struct msm_spi *dd, u32 *config, int n)
{
*config &= ~(SPI_NO_INPUT|SPI_NO_OUTPUT);
if (n != (*config & SPI_CFG_N))
*config = (*config & ~SPI_CFG_N) | n;
if ((dd->mode == SPI_DMOV_MODE) && (!dd->read_len)) {
if (dd->read_buf == NULL)
*config |= SPI_NO_INPUT;
if (dd->write_buf == NULL)
*config |= SPI_NO_OUTPUT;
}
}
static void msm_spi_set_config(struct msm_spi *dd, int bpw)
{
u32 spi_config;
spi_config = readl_relaxed(dd->base + SPI_CONFIG);
if (dd->cur_msg->spi->mode & SPI_CPHA)
spi_config &= ~SPI_CFG_INPUT_FIRST;
else
spi_config |= SPI_CFG_INPUT_FIRST;
if (dd->cur_msg->spi->mode & SPI_LOOP)
spi_config |= SPI_CFG_LOOPBACK;
else
spi_config &= ~SPI_CFG_LOOPBACK;
msm_spi_add_configs(dd, &spi_config, bpw-1);
writel_relaxed(spi_config, dd->base + SPI_CONFIG);
msm_spi_set_qup_config(dd, bpw);
}
static void msm_spi_setup_dm_transfer(struct msm_spi *dd)
{
dmov_box *box;
int bytes_to_send, bytes_sent;
int tx_num_rows, rx_num_rows;
u32 num_transfers;
atomic_set(&dd->rx_irq_called, 0);
atomic_set(&dd->tx_irq_called, 0);
if (dd->write_len && !dd->read_len) {
/* WR-WR transfer */
bytes_sent = dd->cur_msg_len - dd->tx_bytes_remaining;
dd->write_buf = dd->temp_buf;
} else {
bytes_sent = dd->cur_transfer->len - dd->tx_bytes_remaining;
/* For WR-RD transfer, bytes_sent can be negative */
if (bytes_sent < 0)
bytes_sent = 0;
}
/* We'll send in chunks of SPI_MAX_LEN if larger than
* 4K bytes for targets that have only 12 bits in
* QUP_MAX_OUTPUT_CNT register. If the target supports
* more than 12bits then we send the data in chunks of
* the infinite_mode value that is defined in the
* corresponding board file.
*/
if (!dd->pdata->infinite_mode)
dd->max_trfr_len = SPI_MAX_LEN;
else
dd->max_trfr_len = (dd->pdata->infinite_mode) *
(dd->bytes_per_word);
bytes_to_send = min_t(u32, dd->tx_bytes_remaining,
dd->max_trfr_len);
num_transfers = DIV_ROUND_UP(bytes_to_send, dd->bytes_per_word);
dd->tx_unaligned_len = bytes_to_send % dd->output_burst_size;
dd->rx_unaligned_len = bytes_to_send % dd->input_burst_size;
tx_num_rows = bytes_to_send / dd->output_burst_size;
rx_num_rows = bytes_to_send / dd->input_burst_size;
dd->mode = SPI_DMOV_MODE;
if (tx_num_rows) {
/* src in 16 MSB, dst in 16 LSB */
box = &dd->tx_dmov_cmd->box;
box->src_row_addr = dd->cur_transfer->tx_dma + bytes_sent;
box->src_dst_len
= (dd->output_burst_size << 16) | dd->output_burst_size;
box->num_rows = (tx_num_rows << 16) | tx_num_rows;
box->row_offset = (dd->output_burst_size << 16) | 0;
dd->tx_dmov_cmd->cmd_ptr = CMD_PTR_LP |
DMOV_CMD_ADDR(dd->tx_dmov_cmd_dma +
offsetof(struct spi_dmov_cmd, box));
} else {
dd->tx_dmov_cmd->cmd_ptr = CMD_PTR_LP |
DMOV_CMD_ADDR(dd->tx_dmov_cmd_dma +
offsetof(struct spi_dmov_cmd, single_pad));
}
if (rx_num_rows) {
/* src in 16 MSB, dst in 16 LSB */
box = &dd->rx_dmov_cmd->box;
box->dst_row_addr = dd->cur_transfer->rx_dma + bytes_sent;
box->src_dst_len
= (dd->input_burst_size << 16) | dd->input_burst_size;
box->num_rows = (rx_num_rows << 16) | rx_num_rows;
box->row_offset = (0 << 16) | dd->input_burst_size;
dd->rx_dmov_cmd->cmd_ptr = CMD_PTR_LP |
DMOV_CMD_ADDR(dd->rx_dmov_cmd_dma +
offsetof(struct spi_dmov_cmd, box));
} else {
dd->rx_dmov_cmd->cmd_ptr = CMD_PTR_LP |
DMOV_CMD_ADDR(dd->rx_dmov_cmd_dma +
offsetof(struct spi_dmov_cmd, single_pad));
}
if (!dd->tx_unaligned_len) {
dd->tx_dmov_cmd->box.cmd |= CMD_LC;
} else {
dmov_s *tx_cmd = &(dd->tx_dmov_cmd->single_pad);
u32 tx_offset = dd->cur_transfer->len - dd->tx_unaligned_len;
if ((dd->multi_xfr) && (dd->read_len <= 0))
tx_offset = dd->cur_msg_len - dd->tx_unaligned_len;
dd->tx_dmov_cmd->box.cmd &= ~CMD_LC;
memset(dd->tx_padding, 0, dd->output_burst_size);
if (dd->write_buf)
memcpy(dd->tx_padding, dd->write_buf + tx_offset,
dd->tx_unaligned_len);
tx_cmd->src = dd->tx_padding_dma;
tx_cmd->len = dd->output_burst_size;
}
if (!dd->rx_unaligned_len) {
dd->rx_dmov_cmd->box.cmd |= CMD_LC;
} else {
dmov_s *rx_cmd = &(dd->rx_dmov_cmd->single_pad);
dd->rx_dmov_cmd->box.cmd &= ~CMD_LC;
memset(dd->rx_padding, 0, dd->input_burst_size);
rx_cmd->dst = dd->rx_padding_dma;
rx_cmd->len = dd->input_burst_size;
}
/* This also takes care of the padding dummy buf
Since this is set to the correct length, the
dummy bytes won't be actually sent */
if (dd->multi_xfr) {
u32 write_transfers = 0;
u32 read_transfers = 0;
if (dd->write_len > 0) {
write_transfers = DIV_ROUND_UP(dd->write_len,
dd->bytes_per_word);
writel_relaxed(write_transfers,
dd->base + SPI_MX_OUTPUT_COUNT);
}
if (dd->read_len > 0) {
/*
* The read following a write transfer must take
* into account, that the bytes pertaining to
* the write transfer needs to be discarded,
* before the actual read begins.
*/
read_transfers = DIV_ROUND_UP(dd->read_len +
dd->write_len,
dd->bytes_per_word);
writel_relaxed(read_transfers,
dd->base + SPI_MX_INPUT_COUNT);
}
} else {
if (dd->write_buf)
writel_relaxed(num_transfers,
dd->base + SPI_MX_OUTPUT_COUNT);
if (dd->read_buf)
writel_relaxed(num_transfers,
dd->base + SPI_MX_INPUT_COUNT);
}
}
static void msm_spi_enqueue_dm_commands(struct msm_spi *dd)
{
dma_coherent_pre_ops();
if (dd->write_buf)
msm_dmov_enqueue_cmd(dd->tx_dma_chan, &dd->tx_hdr);
if (dd->read_buf)
msm_dmov_enqueue_cmd(dd->rx_dma_chan, &dd->rx_hdr);
}
/* SPI core on targets that does not support infinite mode can send
maximum of 4K transfers or 64K transfers depending up on size of
MAX_OUTPUT_COUNT register, Therefore, we are sending in several
chunks. Upon completion we send the next chunk, or complete the
transfer if everything is finished. On targets that support
infinite mode, we send all the bytes in as single chunk.
*/
static int msm_spi_dm_send_next(struct msm_spi *dd)
{
/* By now we should have sent all the bytes in FIFO mode,
* However to make things right, we'll check anyway.
*/
if (dd->mode != SPI_DMOV_MODE)
return 0;
/* On targets which does not support infinite mode,
We need to send more chunks, if we sent max last time */
if (dd->tx_bytes_remaining > dd->max_trfr_len) {
dd->tx_bytes_remaining -= dd->max_trfr_len;
if (msm_spi_set_state(dd, SPI_OP_STATE_RESET))
return 0;
dd->read_len = dd->write_len = 0;
msm_spi_setup_dm_transfer(dd);
msm_spi_enqueue_dm_commands(dd);
if (msm_spi_set_state(dd, SPI_OP_STATE_RUN))
return 0;
return 1;
} else if (dd->read_len && dd->write_len) {
dd->tx_bytes_remaining -= dd->cur_transfer->len;
if (list_is_last(&dd->cur_transfer->transfer_list,
&dd->cur_msg->transfers))
return 0;
get_next_transfer(dd);
if (msm_spi_set_state(dd, SPI_OP_STATE_PAUSE))
return 0;
dd->tx_bytes_remaining = dd->read_len + dd->write_len;
dd->read_buf = dd->temp_buf;
dd->read_len = dd->write_len = -1;
msm_spi_setup_dm_transfer(dd);
msm_spi_enqueue_dm_commands(dd);
if (msm_spi_set_state(dd, SPI_OP_STATE_RUN))
return 0;
return 1;
}
return 0;
}
static inline void msm_spi_ack_transfer(struct msm_spi *dd)
{
writel_relaxed(SPI_OP_MAX_INPUT_DONE_FLAG |
SPI_OP_MAX_OUTPUT_DONE_FLAG,
dd->base + SPI_OPERATIONAL);
/* Ensure done flag was cleared before proceeding further */
mb();
}
/* Figure which irq occured and call the relevant functions */
static inline irqreturn_t msm_spi_qup_irq(int irq, void *dev_id)
{
u32 op, ret = IRQ_NONE;
struct msm_spi *dd = dev_id;
if (pm_runtime_suspended(dd->dev)) {
dev_warn(dd->dev, "QUP: pm runtime suspend, irq:%d\n", irq);
return ret;
}
if (readl_relaxed(dd->base + SPI_ERROR_FLAGS) ||
readl_relaxed(dd->base + QUP_ERROR_FLAGS)) {
struct spi_master *master = dev_get_drvdata(dd->dev);
ret |= msm_spi_error_irq(irq, master);
}
op = readl_relaxed(dd->base + SPI_OPERATIONAL);
if (op & SPI_OP_INPUT_SERVICE_FLAG) {
writel_relaxed(SPI_OP_INPUT_SERVICE_FLAG,
dd->base + SPI_OPERATIONAL);
/*
* Ensure service flag was cleared before further
* processing of interrupt.
*/
mb();
ret |= msm_spi_input_irq(irq, dev_id);
}
if (op & SPI_OP_OUTPUT_SERVICE_FLAG) {
writel_relaxed(SPI_OP_OUTPUT_SERVICE_FLAG,
dd->base + SPI_OPERATIONAL);
/*
* Ensure service flag was cleared before further
* processing of interrupt.
*/
mb();
ret |= msm_spi_output_irq(irq, dev_id);
}
if (dd->done) {
complete(&dd->transfer_complete);
dd->done = 0;
}
return ret;
}
static irqreturn_t msm_spi_input_irq(int irq, void *dev_id)
{
struct msm_spi *dd = dev_id;
dd->stat_rx++;
if (dd->mode == SPI_MODE_NONE)
return IRQ_HANDLED;
if (dd->mode == SPI_DMOV_MODE) {
u32 op = readl_relaxed(dd->base + SPI_OPERATIONAL);
if ((!dd->read_buf || op & SPI_OP_MAX_INPUT_DONE_FLAG) &&
(!dd->write_buf || op & SPI_OP_MAX_OUTPUT_DONE_FLAG)) {
msm_spi_ack_transfer(dd);
if (dd->rx_unaligned_len == 0) {
if (atomic_inc_return(&dd->rx_irq_called) == 1)
return IRQ_HANDLED;
}
msm_spi_complete(dd);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
if (dd->mode == SPI_FIFO_MODE) {
while ((readl_relaxed(dd->base + SPI_OPERATIONAL) &
SPI_OP_IP_FIFO_NOT_EMPTY) &&
(dd->rx_bytes_remaining > 0)) {
msm_spi_read_word_from_fifo(dd);
}
if (dd->rx_bytes_remaining == 0)
msm_spi_complete(dd);
}
return IRQ_HANDLED;
}
static void msm_spi_write_word_to_fifo(struct msm_spi *dd)
{
u32 word;
u8 byte;
int i;
word = 0;
if (dd->write_buf) {
for (i = 0; (i < dd->bytes_per_word) &&
dd->tx_bytes_remaining; i++) {
dd->tx_bytes_remaining--;
byte = *dd->write_buf++;
word |= (byte << (BITS_PER_BYTE * (3 - i)));
}
} else
if (dd->tx_bytes_remaining > dd->bytes_per_word)
dd->tx_bytes_remaining -= dd->bytes_per_word;
else
dd->tx_bytes_remaining = 0;
dd->write_xfr_cnt++;
if (dd->multi_xfr) {
if (!dd->tx_bytes_remaining)
dd->write_xfr_cnt = 0;
else if ((dd->write_xfr_cnt * dd->bytes_per_word) ==
dd->write_len) {
struct spi_transfer *t = dd->cur_tx_transfer;
if (t->transfer_list.next != &dd->cur_msg->transfers) {
t = list_entry(t->transfer_list.next,
struct spi_transfer,
transfer_list);
dd->write_buf = t->tx_buf;
dd->write_len = t->len;
dd->write_xfr_cnt = 0;
dd->cur_tx_transfer = t;
}
}
}
writel_relaxed(word, dd->base + SPI_OUTPUT_FIFO);
}
static inline void msm_spi_write_rmn_to_fifo(struct msm_spi *dd)
{
int count = 0;
while ((dd->tx_bytes_remaining > 0) && (count < dd->input_fifo_size) &&
!(readl_relaxed(dd->base + SPI_OPERATIONAL) &
SPI_OP_OUTPUT_FIFO_FULL)) {
msm_spi_write_word_to_fifo(dd);
count++;
}
}
static irqreturn_t msm_spi_output_irq(int irq, void *dev_id)
{
struct msm_spi *dd = dev_id;
dd->stat_tx++;
if (dd->mode == SPI_MODE_NONE)
return IRQ_HANDLED;
if (dd->mode == SPI_DMOV_MODE) {
/* TX_ONLY transaction is handled here
This is the only place we send complete at tx and not rx */
if (dd->read_buf == NULL &&
readl_relaxed(dd->base + SPI_OPERATIONAL) &
SPI_OP_MAX_OUTPUT_DONE_FLAG) {
msm_spi_ack_transfer(dd);
if (atomic_inc_return(&dd->tx_irq_called) == 1)
return IRQ_HANDLED;
msm_spi_complete(dd);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
/* Output FIFO is empty. Transmit any outstanding write data. */
if (dd->mode == SPI_FIFO_MODE)
msm_spi_write_rmn_to_fifo(dd);
return IRQ_HANDLED;
}
static irqreturn_t msm_spi_error_irq(int irq, void *dev_id)
{
struct spi_master *master = dev_id;
struct msm_spi *dd = spi_master_get_devdata(master);
u32 spi_err;
spi_err = readl_relaxed(dd->base + SPI_ERROR_FLAGS);
if (spi_err & SPI_ERR_OUTPUT_OVER_RUN_ERR)
dev_warn(master->dev.parent, "SPI output overrun error\n");
if (spi_err & SPI_ERR_INPUT_UNDER_RUN_ERR)
dev_warn(master->dev.parent, "SPI input underrun error\n");
if (spi_err & SPI_ERR_OUTPUT_UNDER_RUN_ERR)
dev_warn(master->dev.parent, "SPI output underrun error\n");
msm_spi_get_clk_err(dd, &spi_err);
if (spi_err & SPI_ERR_CLK_OVER_RUN_ERR)
dev_warn(master->dev.parent, "SPI clock overrun error\n");
if (spi_err & SPI_ERR_CLK_UNDER_RUN_ERR)
dev_warn(master->dev.parent, "SPI clock underrun error\n");
msm_spi_clear_error_flags(dd);
msm_spi_ack_clk_err(dd);
/* Ensure clearing of QUP_ERROR_FLAGS was completed */
mb();
return IRQ_HANDLED;
}
static int msm_spi_map_dma_buffers(struct msm_spi *dd)
{
struct device *dev;
struct spi_transfer *first_xfr;
struct spi_transfer *nxt_xfr = NULL;
void *tx_buf, *rx_buf;
unsigned tx_len, rx_len;
int ret = -EINVAL;
dev = &dd->cur_msg->spi->dev;
first_xfr = dd->cur_transfer;
tx_buf = (void *)first_xfr->tx_buf;
rx_buf = first_xfr->rx_buf;
tx_len = rx_len = first_xfr->len;
/*
* For WR-WR and WR-RD transfers, we allocate our own temporary
* buffer and copy the data to/from the client buffers.
*/
if (dd->multi_xfr) {
dd->temp_buf = kzalloc(dd->cur_msg_len,
GFP_KERNEL | __GFP_DMA);
if (!dd->temp_buf)
return -ENOMEM;
nxt_xfr = list_entry(first_xfr->transfer_list.next,
struct spi_transfer, transfer_list);
if (dd->write_len && !dd->read_len) {
if (!first_xfr->tx_buf || !nxt_xfr->tx_buf)
goto error;
memcpy(dd->temp_buf, first_xfr->tx_buf, first_xfr->len);
memcpy(dd->temp_buf + first_xfr->len, nxt_xfr->tx_buf,
nxt_xfr->len);
tx_buf = dd->temp_buf;
tx_len = dd->cur_msg_len;
} else {
if (!first_xfr->tx_buf || !nxt_xfr->rx_buf)
goto error;
rx_buf = dd->temp_buf;
rx_len = dd->cur_msg_len;
}
}
if (tx_buf != NULL) {
first_xfr->tx_dma = dma_map_single(dev, tx_buf,
tx_len, DMA_TO_DEVICE);
if (dma_mapping_error(NULL, first_xfr->tx_dma)) {
dev_err(dev, "dma %cX %d bytes error\n",
'T', tx_len);
ret = -ENOMEM;
goto error;
}
}
if (rx_buf != NULL) {
dma_addr_t dma_handle;
dma_handle = dma_map_single(dev, rx_buf,
rx_len, DMA_FROM_DEVICE);
if (dma_mapping_error(NULL, dma_handle)) {
dev_err(dev, "dma %cX %d bytes error\n",
'R', rx_len);
if (tx_buf != NULL)
dma_unmap_single(NULL, first_xfr->tx_dma,
tx_len, DMA_TO_DEVICE);
ret = -ENOMEM;
goto error;
}
if (dd->multi_xfr)
nxt_xfr->rx_dma = dma_handle;
else
first_xfr->rx_dma = dma_handle;
}
return 0;
error:
kfree(dd->temp_buf);
dd->temp_buf = NULL;
return ret;
}
static void msm_spi_unmap_dma_buffers(struct msm_spi *dd)
{
struct device *dev;
u32 offset;
dev = &dd->cur_msg->spi->dev;
if (dd->cur_msg->is_dma_mapped)
goto unmap_end;
if (dd->multi_xfr) {
if (dd->write_len && !dd->read_len) {
dma_unmap_single(dev,
dd->cur_transfer->tx_dma,
dd->cur_msg_len,
DMA_TO_DEVICE);
} else {
struct spi_transfer *prev_xfr;
prev_xfr = list_entry(
dd->cur_transfer->transfer_list.prev,
struct spi_transfer,
transfer_list);
if (dd->cur_transfer->rx_buf) {
dma_unmap_single(dev,
dd->cur_transfer->rx_dma,
dd->cur_msg_len,
DMA_FROM_DEVICE);
}
if (prev_xfr->tx_buf) {
dma_unmap_single(dev,
prev_xfr->tx_dma,
prev_xfr->len,
DMA_TO_DEVICE);
}
if (dd->rx_unaligned_len && dd->read_buf) {
offset = dd->cur_msg_len - dd->rx_unaligned_len;
dma_coherent_post_ops();
memcpy(dd->read_buf + offset, dd->rx_padding,
dd->rx_unaligned_len);
memcpy(dd->cur_transfer->rx_buf,
dd->read_buf + prev_xfr->len,
dd->cur_transfer->len);
}
}
kfree(dd->temp_buf);
dd->temp_buf = NULL;
return;
} else {
if (dd->cur_transfer->rx_buf)
dma_unmap_single(dev, dd->cur_transfer->rx_dma,
dd->cur_transfer->len,
DMA_FROM_DEVICE);
if (dd->cur_transfer->tx_buf)
dma_unmap_single(dev, dd->cur_transfer->tx_dma,
dd->cur_transfer->len,
DMA_TO_DEVICE);
}
unmap_end:
/* If we padded the transfer, we copy it from the padding buf */
if (dd->rx_unaligned_len && dd->read_buf) {
offset = dd->cur_transfer->len - dd->rx_unaligned_len;
dma_coherent_post_ops();
memcpy(dd->read_buf + offset, dd->rx_padding,
dd->rx_unaligned_len);
}
}
/**
* msm_use_dm - decides whether to use data mover for this
* transfer
* @dd: device
* @tr: transfer
*
* Start using DM if:
* 1. Transfer is longer than 3*block size.
* 2. Buffers should be aligned to cache line.
* 3. For WR-RD or WR-WR transfers, if condition (1) and (2) above are met.
*/
static inline int msm_use_dm(struct msm_spi *dd, struct spi_transfer *tr,
u8 bpw)
{
u32 cache_line = dma_get_cache_alignment();
if (!dd->use_dma)
return 0;
if (dd->cur_msg_len < 3*dd->input_block_size)
return 0;
if (dd->multi_xfr && !dd->read_len && !dd->write_len)
return 0;
if (tr->tx_buf) {
if (!IS_ALIGNED((size_t)tr->tx_buf, cache_line))
return 0;
}
if (tr->rx_buf) {
if (!IS_ALIGNED((size_t)tr->rx_buf, cache_line))
return 0;
}
if (tr->cs_change &&
((bpw != 8) && (bpw != 16) && (bpw != 32)))
return 0;
return 1;
}
static void msm_spi_process_transfer(struct msm_spi *dd)
{
u8 bpw;
u32 spi_ioc;
u32 spi_iom;
u32 spi_ioc_orig;
u32 max_speed;
u32 chip_select;
u32 read_count;
u32 timeout;
u32 int_loopback = 0;
dd->tx_bytes_remaining = dd->cur_msg_len;
dd->rx_bytes_remaining = dd->cur_msg_len;
dd->read_buf = dd->cur_transfer->rx_buf;
dd->write_buf = dd->cur_transfer->tx_buf;
init_completion(&dd->transfer_complete);
if (dd->cur_transfer->bits_per_word)
bpw = dd->cur_transfer->bits_per_word;
else
if (dd->cur_msg->spi->bits_per_word)
bpw = dd->cur_msg->spi->bits_per_word;
else
bpw = 8;
dd->bytes_per_word = (bpw + 7) / 8;
if (dd->cur_transfer->speed_hz)
max_speed = dd->cur_transfer->speed_hz;
else
max_speed = dd->cur_msg->spi->max_speed_hz;
if (!dd->clock_speed || max_speed != dd->clock_speed)
msm_spi_clock_set(dd, max_speed);
read_count = DIV_ROUND_UP(dd->cur_msg_len, dd->bytes_per_word);
if (dd->cur_msg->spi->mode & SPI_LOOP)
int_loopback = 1;
if (int_loopback && dd->multi_xfr &&
(read_count > dd->input_fifo_size)) {
if (dd->read_len && dd->write_len)
pr_err(
"%s:Internal Loopback does not support > fifo size"
"for write-then-read transactions\n",
__func__);
else if (dd->write_len && !dd->read_len)
pr_err(
"%s:Internal Loopback does not support > fifo size"
"for write-then-write transactions\n",
__func__);
return;
}
if (!msm_use_dm(dd, dd->cur_transfer, bpw)) {
dd->mode = SPI_FIFO_MODE;
if (dd->multi_xfr) {
dd->read_len = dd->cur_transfer->len;
dd->write_len = dd->cur_transfer->len;
}
/* read_count cannot exceed fifo_size, and only one READ COUNT
interrupt is generated per transaction, so for transactions
larger than fifo size READ COUNT must be disabled.
For those transactions we usually move to Data Mover mode.
*/
if (read_count <= dd->input_fifo_size) {
writel_relaxed(read_count,
dd->base + SPI_MX_READ_COUNT);
msm_spi_set_write_count(dd, read_count);
} else {
writel_relaxed(0, dd->base + SPI_MX_READ_COUNT);
msm_spi_set_write_count(dd, 0);
}
} else {
dd->mode = SPI_DMOV_MODE;
if (dd->write_len && dd->read_len) {
dd->tx_bytes_remaining = dd->write_len;
dd->rx_bytes_remaining = dd->read_len;
}
}
/* Write mode - fifo or data mover*/
spi_iom = readl_relaxed(dd->base + SPI_IO_MODES);
spi_iom &= ~(SPI_IO_M_INPUT_MODE | SPI_IO_M_OUTPUT_MODE);
spi_iom = (spi_iom | (dd->mode << OUTPUT_MODE_SHIFT));
spi_iom = (spi_iom | (dd->mode << INPUT_MODE_SHIFT));
/* Turn on packing for data mover */
if (dd->mode == SPI_DMOV_MODE)
spi_iom |= SPI_IO_M_PACK_EN | SPI_IO_M_UNPACK_EN;
else
spi_iom &= ~(SPI_IO_M_PACK_EN | SPI_IO_M_UNPACK_EN);
writel_relaxed(spi_iom, dd->base + SPI_IO_MODES);
msm_spi_set_config(dd, bpw);
spi_ioc = readl_relaxed(dd->base + SPI_IO_CONTROL);
spi_ioc_orig = spi_ioc;
if (dd->cur_msg->spi->mode & SPI_CPOL)
spi_ioc |= SPI_IO_C_CLK_IDLE_HIGH;
else
spi_ioc &= ~SPI_IO_C_CLK_IDLE_HIGH;
chip_select = dd->cur_msg->spi->chip_select << 2;
if ((spi_ioc & SPI_IO_C_CS_SELECT) != chip_select)
spi_ioc = (spi_ioc & ~SPI_IO_C_CS_SELECT) | chip_select;
if (!dd->cur_transfer->cs_change)
spi_ioc |= SPI_IO_C_MX_CS_MODE;
if (spi_ioc != spi_ioc_orig)
writel_relaxed(spi_ioc, dd->base + SPI_IO_CONTROL);
if (dd->mode == SPI_DMOV_MODE) {
msm_spi_setup_dm_transfer(dd);
msm_spi_enqueue_dm_commands(dd);
}
/* The output fifo interrupt handler will handle all writes after
the first. Restricting this to one write avoids contention
issues and race conditions between this thread and the int handler
*/
else if (dd->mode == SPI_FIFO_MODE) {
if (msm_spi_prepare_for_write(dd))
goto transfer_end;
msm_spi_start_write(dd, read_count);
}
/* Only enter the RUN state after the first word is written into
the output FIFO. Otherwise, the output FIFO EMPTY interrupt
might fire before the first word is written resulting in a
possible race condition.
*/
if (msm_spi_set_state(dd, SPI_OP_STATE_RUN))
goto transfer_end;
timeout = 100 * msecs_to_jiffies(
DIV_ROUND_UP(dd->cur_msg_len * 8,
DIV_ROUND_UP(max_speed, MSEC_PER_SEC)));
/* Assume success, this might change later upon transaction result */
dd->cur_msg->status = 0;
do {
if (!wait_for_completion_timeout(&dd->transfer_complete,
timeout)) {
dev_err(dd->dev, "%s: SPI transaction "
"timeout\n", __func__);
dd->cur_msg->status = -EIO;
if (dd->mode == SPI_DMOV_MODE) {
msm_dmov_flush(dd->tx_dma_chan, 1);
msm_dmov_flush(dd->rx_dma_chan, 1);
}
break;
}
} while (msm_spi_dm_send_next(dd));
msm_spi_udelay(dd->cur_transfer->delay_usecs);
transfer_end:
if (dd->mode == SPI_DMOV_MODE)
msm_spi_unmap_dma_buffers(dd);
dd->mode = SPI_MODE_NONE;
msm_spi_set_state(dd, SPI_OP_STATE_RESET);
writel_relaxed(spi_ioc & ~SPI_IO_C_MX_CS_MODE,
dd->base + SPI_IO_CONTROL);
}
static void get_transfer_length(struct msm_spi *dd)
{
struct spi_transfer *tr;
int num_xfrs = 0;
int readlen = 0;
int writelen = 0;
dd->cur_msg_len = 0;
dd->multi_xfr = 0;
dd->read_len = dd->write_len = 0;
list_for_each_entry(tr, &dd->cur_msg->transfers, transfer_list) {
if (tr->tx_buf)
writelen += tr->len;
if (tr->rx_buf)
readlen += tr->len;
dd->cur_msg_len += tr->len;
num_xfrs++;
}
if (num_xfrs == 2) {
struct spi_transfer *first_xfr = dd->cur_transfer;
dd->multi_xfr = 1;
tr = list_entry(first_xfr->transfer_list.next,
struct spi_transfer,
transfer_list);
/*
* We update dd->read_len and dd->write_len only
* for WR-WR and WR-RD transfers.
*/
if ((first_xfr->tx_buf) && (!first_xfr->rx_buf)) {
if (((tr->tx_buf) && (!tr->rx_buf)) ||
((!tr->tx_buf) && (tr->rx_buf))) {
dd->read_len = readlen;
dd->write_len = writelen;
}
}
} else if (num_xfrs > 1)
dd->multi_xfr = 1;
}
static inline int combine_transfers(struct msm_spi *dd)
{
struct spi_transfer *t = dd->cur_transfer;
struct spi_transfer *nxt;
int xfrs_grped = 1;
dd->cur_msg_len = dd->cur_transfer->len;
while (t->transfer_list.next != &dd->cur_msg->transfers) {
nxt = list_entry(t->transfer_list.next,
struct spi_transfer,
transfer_list);
if (t->cs_change != nxt->cs_change)
return xfrs_grped;
dd->cur_msg_len += nxt->len;
xfrs_grped++;
t = nxt;
}
return xfrs_grped;
}
static inline void write_force_cs(struct msm_spi *dd, bool set_flag)
{
u32 spi_ioc;
u32 spi_ioc_orig;
spi_ioc = readl_relaxed(dd->base + SPI_IO_CONTROL);
spi_ioc_orig = spi_ioc;
if (set_flag)
spi_ioc |= SPI_IO_C_FORCE_CS;
else
spi_ioc &= ~SPI_IO_C_FORCE_CS;
if (spi_ioc != spi_ioc_orig)
writel_relaxed(spi_ioc, dd->base + SPI_IO_CONTROL);
}
static void msm_spi_process_message(struct msm_spi *dd)
{
int xfrs_grped = 0;
int cs_num;
int rc;
bool xfer_delay = false;
struct spi_transfer *tr;
dd->write_xfr_cnt = dd->read_xfr_cnt = 0;
cs_num = dd->cur_msg->spi->chip_select;
if ((!(dd->cur_msg->spi->mode & SPI_LOOP)) &&
(!(dd->cs_gpios[cs_num].valid)) &&
(dd->cs_gpios[cs_num].gpio_num >= 0)) {
rc = gpio_request(dd->cs_gpios[cs_num].gpio_num,
spi_cs_rsrcs[cs_num]);
if (rc) {
dev_err(dd->dev, "gpio_request for pin %d failed with "
"error %d\n", dd->cs_gpios[cs_num].gpio_num,
rc);
return;
}
dd->cs_gpios[cs_num].valid = 1;
}
list_for_each_entry(tr,
&dd->cur_msg->transfers,
transfer_list) {
if (tr->delay_usecs) {
dev_info(dd->dev, "SPI slave requests delay per txn :%d",
tr->delay_usecs);
xfer_delay = true;
break;
}
}
/* Don't combine xfers if delay is needed after every xfer */
if (dd->qup_ver || xfer_delay) {
if (dd->qup_ver)
write_force_cs(dd, 0);
list_for_each_entry(dd->cur_transfer,
&dd->cur_msg->transfers,
transfer_list) {
struct spi_transfer *t = dd->cur_transfer;
struct spi_transfer *nxt;
if (t->transfer_list.next != &dd->cur_msg->transfers) {
nxt = list_entry(t->transfer_list.next,
struct spi_transfer,
transfer_list);
if (dd->qup_ver &&
t->cs_change == nxt->cs_change)
write_force_cs(dd, 1);
else if (dd->qup_ver)
write_force_cs(dd, 0);
}
dd->cur_msg_len = dd->cur_transfer->len;
msm_spi_process_transfer(dd);
}
} else {
dd->cur_transfer = list_first_entry(&dd->cur_msg->transfers,
struct spi_transfer,
transfer_list);
get_transfer_length(dd);
if (dd->multi_xfr && !dd->read_len && !dd->write_len) {
/*
* Handling of multi-transfers.
* FIFO mode is used by default
*/
list_for_each_entry(dd->cur_transfer,
&dd->cur_msg->transfers,
transfer_list) {
if (!dd->cur_transfer->len)
goto error;
if (xfrs_grped) {
xfrs_grped--;
continue;
} else {
dd->read_len = dd->write_len = 0;
xfrs_grped = combine_transfers(dd);
}
dd->cur_tx_transfer = dd->cur_transfer;
dd->cur_rx_transfer = dd->cur_transfer;
msm_spi_process_transfer(dd);
xfrs_grped--;
}
} else {
/* Handling of a single transfer or
* WR-WR or WR-RD transfers
*/
if ((!dd->cur_msg->is_dma_mapped) &&
(msm_use_dm(dd, dd->cur_transfer,
dd->cur_transfer->bits_per_word))) {
/* Mapping of DMA buffers */
int ret = msm_spi_map_dma_buffers(dd);
if (ret < 0) {
dd->cur_msg->status = ret;
goto error;
}
}
dd->cur_tx_transfer = dd->cur_transfer;
dd->cur_rx_transfer = dd->cur_transfer;
msm_spi_process_transfer(dd);
}
}
return;
error:
if (dd->cs_gpios[cs_num].valid) {
gpio_free(dd->cs_gpios[cs_num].gpio_num);
dd->cs_gpios[cs_num].valid = 0;
}
}
/* workqueue - pull messages from queue & process */
static void msm_spi_workq(struct work_struct *work)
{
struct msm_spi *dd =
container_of(work, struct msm_spi, work_data);
unsigned long flags;
u32 status_error = 0;
pm_runtime_get_sync(dd->dev);
mutex_lock(&dd->core_lock);
/*
* Counter-part of system-suspend when runtime-pm is not enabled.
* This way, resume can be left empty and device will be put in
* active mode only if client requests anything on the bus
*/
if (!pm_runtime_enabled(dd->dev))
msm_spi_pm_resume_runtime(dd->dev);
if (dd->use_rlock)
remote_mutex_lock(&dd->r_lock);
if (!msm_spi_is_valid_state(dd)) {
dev_err(dd->dev, "%s: SPI operational state not valid\n",
__func__);
status_error = 1;
}
spin_lock_irqsave(&dd->queue_lock, flags);
dd->transfer_pending = 1;
while (!list_empty(&dd->queue)) {
dd->cur_msg = list_entry(dd->queue.next,
struct spi_message, queue);
list_del_init(&dd->cur_msg->queue);
spin_unlock_irqrestore(&dd->queue_lock, flags);
if (status_error)
dd->cur_msg->status = -EIO;
else
msm_spi_process_message(dd);
if (dd->cur_msg->complete)
dd->cur_msg->complete(dd->cur_msg->context);
spin_lock_irqsave(&dd->queue_lock, flags);
}
dd->transfer_pending = 0;
spin_unlock_irqrestore(&dd->queue_lock, flags);
if (dd->use_rlock)
remote_mutex_unlock(&dd->r_lock);
mutex_unlock(&dd->core_lock);
pm_runtime_mark_last_busy(dd->dev);
pm_runtime_put_autosuspend(dd->dev);
/* If needed, this can be done after the current message is complete,
and work can be continued upon resume. No motivation for now. */
if (dd->suspended)
wake_up_interruptible(&dd->continue_suspend);
}
static int msm_spi_transfer(struct spi_device *spi, struct spi_message *msg)
{
struct msm_spi *dd;
unsigned long flags;
struct spi_transfer *tr;
dd = spi_master_get_devdata(spi->master);
if (list_empty(&msg->transfers) || !msg->complete)
return -EINVAL;
list_for_each_entry(tr, &msg->transfers, transfer_list) {
/* Check message parameters */
if (tr->speed_hz > dd->pdata->max_clock_speed ||
(tr->bits_per_word &&
(tr->bits_per_word < 4 || tr->bits_per_word > 32)) ||
(tr->tx_buf == NULL && tr->rx_buf == NULL)) {
dev_err(&spi->dev, "Invalid transfer: %d Hz, %d bpw"
"tx=%p, rx=%p\n",
tr->speed_hz, tr->bits_per_word,
tr->tx_buf, tr->rx_buf);
return -EINVAL;
}
}
spin_lock_irqsave(&dd->queue_lock, flags);
list_add_tail(&msg->queue, &dd->queue);
spin_unlock_irqrestore(&dd->queue_lock, flags);
queue_work(dd->workqueue, &dd->work_data);
return 0;
}
static int msm_spi_setup(struct spi_device *spi)
{
struct msm_spi *dd;
int rc = 0;
u32 spi_ioc;
u32 spi_config;
u32 mask;
if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
dev_err(&spi->dev, "%s: invalid bits_per_word %d\n",
__func__, spi->bits_per_word);
rc = -EINVAL;
}
if (spi->chip_select > SPI_NUM_CHIPSELECTS-1) {
dev_err(&spi->dev, "%s, chip select %d exceeds max value %d\n",
__func__, spi->chip_select, SPI_NUM_CHIPSELECTS - 1);
rc = -EINVAL;
}
if (rc)
goto err_setup_exit;
dd = spi_master_get_devdata(spi->master);
pm_runtime_get_sync(dd->dev);
mutex_lock(&dd->core_lock);
/* Counter-part of system-suspend when runtime-pm is not enabled. */
if (!pm_runtime_enabled(dd->dev))
msm_spi_pm_resume_runtime(dd->dev);
if (dd->use_rlock)
remote_mutex_lock(&dd->r_lock);
spi_ioc = readl_relaxed(dd->base + SPI_IO_CONTROL);
mask = SPI_IO_C_CS_N_POLARITY_0 << spi->chip_select;
if (spi->mode & SPI_CS_HIGH)
spi_ioc |= mask;
else
spi_ioc &= ~mask;
if (spi->mode & SPI_CPOL)
spi_ioc |= SPI_IO_C_CLK_IDLE_HIGH;
else
spi_ioc &= ~SPI_IO_C_CLK_IDLE_HIGH;
writel_relaxed(spi_ioc, dd->base + SPI_IO_CONTROL);
spi_config = readl_relaxed(dd->base + SPI_CONFIG);
if (spi->mode & SPI_LOOP)
spi_config |= SPI_CFG_LOOPBACK;
else
spi_config &= ~SPI_CFG_LOOPBACK;
if (spi->mode & SPI_CPHA)
spi_config &= ~SPI_CFG_INPUT_FIRST;
else
spi_config |= SPI_CFG_INPUT_FIRST;
writel_relaxed(spi_config, dd->base + SPI_CONFIG);
/* Ensure previous write completed before disabling the clocks */
mb();
if (dd->use_rlock)
remote_mutex_unlock(&dd->r_lock);
/* Counter-part of system-resume when runtime-pm is not enabled. */
if (!pm_runtime_enabled(dd->dev))
msm_spi_pm_suspend_runtime(dd->dev);
mutex_unlock(&dd->core_lock);
pm_runtime_mark_last_busy(dd->dev);
pm_runtime_put_autosuspend(dd->dev);
err_setup_exit:
return rc;
}
#ifdef CONFIG_DEBUG_FS
static int debugfs_iomem_x32_set(void *data, u64 val)
{
writel_relaxed(val, data);
/* Ensure the previous write completed. */
mb();
return 0;
}
static int debugfs_iomem_x32_get(void *data, u64 *val)
{
*val = readl_relaxed(data);
/* Ensure the previous read completed. */
mb();
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_iomem_x32, debugfs_iomem_x32_get,
debugfs_iomem_x32_set, "0x%08llx\n");
static void spi_debugfs_init(struct msm_spi *dd)
{
dd->dent_spi = debugfs_create_dir(dev_name(dd->dev), NULL);
if (dd->dent_spi) {
int i;
for (i = 0; i < ARRAY_SIZE(debugfs_spi_regs); i++) {
dd->debugfs_spi_regs[i] =
debugfs_create_file(
debugfs_spi_regs[i].name,
debugfs_spi_regs[i].mode,
dd->dent_spi,
dd->base + debugfs_spi_regs[i].offset,
&fops_iomem_x32);
}
}
}
static void spi_debugfs_exit(struct msm_spi *dd)
{
if (dd->dent_spi) {
int i;
debugfs_remove_recursive(dd->dent_spi);
dd->dent_spi = NULL;
for (i = 0; i < ARRAY_SIZE(debugfs_spi_regs); i++)
dd->debugfs_spi_regs[i] = NULL;
}
}
#else
static void spi_debugfs_init(struct msm_spi *dd) {}
static void spi_debugfs_exit(struct msm_spi *dd) {}
#endif
/* ===Device attributes begin=== */
static ssize_t show_stats(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct spi_master *master = dev_get_drvdata(dev);
struct msm_spi *dd = spi_master_get_devdata(master);
return snprintf(buf, PAGE_SIZE,
"Device %s\n"
"rx fifo_size = %d spi words\n"
"tx fifo_size = %d spi words\n"
"use_dma ? %s\n"
"rx block size = %d bytes\n"
"tx block size = %d bytes\n"
"input burst size = %d bytes\n"
"output burst size = %d bytes\n"
"DMA configuration:\n"
"tx_ch=%d, rx_ch=%d, tx_crci= %d, rx_crci=%d\n"
"--statistics--\n"
"Rx isrs = %d\n"
"Tx isrs = %d\n"
"DMA error = %d\n"
"--debug--\n"
"NA yet\n",
dev_name(dev),
dd->input_fifo_size,
dd->output_fifo_size,
dd->use_dma ? "yes" : "no",
dd->input_block_size,
dd->output_block_size,
dd->input_burst_size,
dd->output_burst_size,
dd->tx_dma_chan,
dd->rx_dma_chan,
dd->tx_dma_crci,
dd->rx_dma_crci,
dd->stat_rx + dd->stat_dmov_rx,
dd->stat_tx + dd->stat_dmov_tx,
dd->stat_dmov_tx_err + dd->stat_dmov_rx_err
);
}
/* Reset statistics on write */
static ssize_t set_stats(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct msm_spi *dd = dev_get_drvdata(dev);
dd->stat_rx = 0;
dd->stat_tx = 0;
dd->stat_dmov_rx = 0;
dd->stat_dmov_tx = 0;
dd->stat_dmov_rx_err = 0;
dd->stat_dmov_tx_err = 0;
return count;
}
static DEVICE_ATTR(stats, S_IRUGO | S_IWUSR, show_stats, set_stats);
static struct attribute *dev_attrs[] = {
&dev_attr_stats.attr,
NULL,
};
static struct attribute_group dev_attr_grp = {
.attrs = dev_attrs,
};
/* ===Device attributes end=== */
/**
* spi_dmov_tx_complete_func - DataMover tx completion callback
*
* Executed in IRQ context (Data Mover's IRQ) DataMover's
* spinlock @msm_dmov_lock held.
*/
static void spi_dmov_tx_complete_func(struct msm_dmov_cmd *cmd,
unsigned int result,
struct msm_dmov_errdata *err)
{
struct msm_spi *dd;
if (!(result & DMOV_RSLT_VALID)) {
pr_err("Invalid DMOV result: rc=0x%08x, cmd = %p", result, cmd);
return;
}
/* restore original context */
dd = container_of(cmd, struct msm_spi, tx_hdr);
if (result & DMOV_RSLT_DONE) {
dd->stat_dmov_tx++;
if ((atomic_inc_return(&dd->tx_irq_called) == 1))
return;
complete(&dd->transfer_complete);
} else {
/* Error or flush */
if (result & DMOV_RSLT_ERROR) {
dev_err(dd->dev, "DMA error (0x%08x)\n", result);
dd->stat_dmov_tx_err++;
}
if (result & DMOV_RSLT_FLUSH) {
/*
* Flushing normally happens in process of
* removing, when we are waiting for outstanding
* DMA commands to be flushed.
*/
dev_info(dd->dev,
"DMA channel flushed (0x%08x)\n", result);
}
if (err)
dev_err(dd->dev,
"Flush data(%08x %08x %08x %08x %08x %08x)\n",
err->flush[0], err->flush[1], err->flush[2],
err->flush[3], err->flush[4], err->flush[5]);
dd->cur_msg->status = -EIO;
complete(&dd->transfer_complete);
}
}
/**
* spi_dmov_rx_complete_func - DataMover rx completion callback
*
* Executed in IRQ context (Data Mover's IRQ)
* DataMover's spinlock @msm_dmov_lock held.
*/
static void spi_dmov_rx_complete_func(struct msm_dmov_cmd *cmd,
unsigned int result,
struct msm_dmov_errdata *err)
{
struct msm_spi *dd;
if (!(result & DMOV_RSLT_VALID)) {
pr_err("Invalid DMOV result(rc = 0x%08x, cmd = %p)",
result, cmd);
return;
}
/* restore original context */
dd = container_of(cmd, struct msm_spi, rx_hdr);
if (result & DMOV_RSLT_DONE) {
dd->stat_dmov_rx++;
if (atomic_inc_return(&dd->rx_irq_called) == 1)
return;
complete(&dd->transfer_complete);
} else {
/** Error or flush */
if (result & DMOV_RSLT_ERROR) {
dev_err(dd->dev, "DMA error(0x%08x)\n", result);
dd->stat_dmov_rx_err++;
}
if (result & DMOV_RSLT_FLUSH) {
dev_info(dd->dev,
"DMA channel flushed(0x%08x)\n", result);
}
if (err)
dev_err(dd->dev,
"Flush data(%08x %08x %08x %08x %08x %08x)\n",
err->flush[0], err->flush[1], err->flush[2],
err->flush[3], err->flush[4], err->flush[5]);
dd->cur_msg->status = -EIO;
complete(&dd->transfer_complete);
}
}
static inline u32 get_chunk_size(struct msm_spi *dd, int input_burst_size,
int output_burst_size)
{
u32 cache_line = dma_get_cache_alignment();
int burst_size = (input_burst_size > output_burst_size) ?
input_burst_size : output_burst_size;
return (roundup(sizeof(struct spi_dmov_cmd), DM_BYTE_ALIGN) +
roundup(burst_size, cache_line))*2;
}
static void msm_spi_teardown_dma(struct msm_spi *dd)
{
int limit = 0;
if (!dd->use_dma)
return;
while (dd->mode == SPI_DMOV_MODE && limit++ < 50) {
msm_dmov_flush(dd->tx_dma_chan, 1);
msm_dmov_flush(dd->rx_dma_chan, 1);
msleep(10);
}
dma_free_coherent(NULL,
get_chunk_size(dd, dd->input_burst_size, dd->output_burst_size),
dd->tx_dmov_cmd,
dd->tx_dmov_cmd_dma);
dd->tx_dmov_cmd = dd->rx_dmov_cmd = NULL;
dd->tx_padding = dd->rx_padding = NULL;
}
static __init int msm_spi_init_dma(struct msm_spi *dd)
{
dmov_box *box;
u32 cache_line = dma_get_cache_alignment();
/* Allocate all as one chunk, since all is smaller than page size */
/* We send NULL device, since it requires coherent_dma_mask id
device definition, we're okay with using system pool */
dd->tx_dmov_cmd
= dma_alloc_coherent(NULL,
get_chunk_size(dd, dd->input_burst_size,
dd->output_burst_size),
&dd->tx_dmov_cmd_dma, GFP_KERNEL);
if (dd->tx_dmov_cmd == NULL)
return -ENOMEM;
/* DMA addresses should be 64 bit aligned aligned */
dd->rx_dmov_cmd = (struct spi_dmov_cmd *)
ALIGN((size_t)&dd->tx_dmov_cmd[1], DM_BYTE_ALIGN);
dd->rx_dmov_cmd_dma = ALIGN(dd->tx_dmov_cmd_dma +
sizeof(struct spi_dmov_cmd), DM_BYTE_ALIGN);
/* Buffers should be aligned to cache line */
dd->tx_padding = (u8 *)ALIGN((size_t)&dd->rx_dmov_cmd[1], cache_line);
dd->tx_padding_dma = ALIGN(dd->rx_dmov_cmd_dma +
sizeof(struct spi_dmov_cmd), cache_line);
dd->rx_padding = (u8 *)ALIGN((size_t)(dd->tx_padding +
dd->output_burst_size), cache_line);
dd->rx_padding_dma = ALIGN(dd->tx_padding_dma + dd->output_burst_size,
cache_line);
/* Setup DM commands */
box = &(dd->rx_dmov_cmd->box);
box->cmd = CMD_MODE_BOX | CMD_SRC_CRCI(dd->rx_dma_crci);
box->src_row_addr = (uint32_t)dd->mem_phys_addr + SPI_INPUT_FIFO;
dd->rx_hdr.cmdptr = DMOV_CMD_PTR_LIST |
DMOV_CMD_ADDR(dd->rx_dmov_cmd_dma +
offsetof(struct spi_dmov_cmd, cmd_ptr));
dd->rx_hdr.complete_func = spi_dmov_rx_complete_func;
box = &(dd->tx_dmov_cmd->box);
box->cmd = CMD_MODE_BOX | CMD_DST_CRCI(dd->tx_dma_crci);
box->dst_row_addr = (uint32_t)dd->mem_phys_addr + SPI_OUTPUT_FIFO;
dd->tx_hdr.cmdptr = DMOV_CMD_PTR_LIST |
DMOV_CMD_ADDR(dd->tx_dmov_cmd_dma +
offsetof(struct spi_dmov_cmd, cmd_ptr));
dd->tx_hdr.complete_func = spi_dmov_tx_complete_func;
dd->tx_dmov_cmd->single_pad.cmd = CMD_MODE_SINGLE | CMD_LC |
CMD_DST_CRCI(dd->tx_dma_crci);
dd->tx_dmov_cmd->single_pad.dst = (uint32_t)dd->mem_phys_addr +
SPI_OUTPUT_FIFO;
dd->rx_dmov_cmd->single_pad.cmd = CMD_MODE_SINGLE | CMD_LC |
CMD_SRC_CRCI(dd->rx_dma_crci);
dd->rx_dmov_cmd->single_pad.src = (uint32_t)dd->mem_phys_addr +
SPI_INPUT_FIFO;
/* Clear remaining activities on channel */
msm_dmov_flush(dd->tx_dma_chan, 1);
msm_dmov_flush(dd->rx_dma_chan, 1);
return 0;
}
struct msm_spi_platform_data *msm_spi_dt_to_pdata(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct msm_spi_platform_data *pdata;
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
pr_err("Unable to allocate platform data\n");
return NULL;
}
of_property_read_u32(node, "spi-max-frequency",
&pdata->max_clock_speed);
of_property_read_u32(node, "infinite_mode",
&pdata->infinite_mode);
return pdata;
}
static int __init msm_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct msm_spi *dd;
struct resource *resource;
int rc = -ENXIO;
int locked = 0;
int i = 0;
int clk_enabled = 0;
int pclk_enabled = 0;
struct msm_spi_platform_data *pdata;
enum of_gpio_flags flags;
master = spi_alloc_master(&pdev->dev, sizeof(struct msm_spi));
if (!master) {
rc = -ENOMEM;
dev_err(&pdev->dev, "master allocation failed\n");
goto err_probe_exit;
}
master->bus_num = pdev->id;
master->mode_bits = SPI_SUPPORTED_MODES;
master->num_chipselect = SPI_NUM_CHIPSELECTS;
master->setup = msm_spi_setup;
master->transfer = msm_spi_transfer;
platform_set_drvdata(pdev, master);
dd = spi_master_get_devdata(master);
if (pdev->dev.of_node) {
dd->qup_ver = SPI_QUP_VERSION_BFAM;
master->dev.of_node = pdev->dev.of_node;
pdata = msm_spi_dt_to_pdata(pdev);
if (!pdata) {
rc = -ENOMEM;
goto err_probe_exit;
}
rc = of_property_read_u32(pdev->dev.of_node,
"cell-index", &pdev->id);
if (rc)
dev_warn(&pdev->dev,
"using default bus_num %d\n", pdev->id);
else
master->bus_num = pdev->id;
for (i = 0; i < ARRAY_SIZE(spi_rsrcs); ++i) {
dd->spi_gpios[i] = of_get_gpio_flags(pdev->dev.of_node,
i, &flags);
}
for (i = 0; i < ARRAY_SIZE(spi_cs_rsrcs); ++i) {
dd->cs_gpios[i].gpio_num = of_get_named_gpio_flags(
pdev->dev.of_node, "cs-gpios",
i, &flags);
dd->cs_gpios[i].valid = 0;
}
} else {
pdata = pdev->dev.platform_data;
dd->qup_ver = SPI_QUP_VERSION_NONE;
for (i = 0; i < ARRAY_SIZE(spi_rsrcs); ++i) {
resource = platform_get_resource(pdev, IORESOURCE_IO,
i);
dd->spi_gpios[i] = resource ? resource->start : -1;
}
for (i = 0; i < ARRAY_SIZE(spi_cs_rsrcs); ++i) {
resource = platform_get_resource(pdev, IORESOURCE_IO,
i + ARRAY_SIZE(spi_rsrcs));
dd->cs_gpios[i].gpio_num = resource ?
resource->start : -1;
dd->cs_gpios[i].valid = 0;
}
}
dd->pdata = pdata;
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!resource) {
rc = -ENXIO;
goto err_probe_res;
}
dd->mem_phys_addr = resource->start;
dd->mem_size = resource_size(resource);
if (pdata) {
if (pdata->dma_config) {
rc = pdata->dma_config();
if (rc) {
dev_warn(&pdev->dev,
"%s: DM mode not supported\n",
__func__);
dd->use_dma = 0;
goto skip_dma_resources;
}
}
resource = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (resource) {
dd->rx_dma_chan = resource->start;
dd->tx_dma_chan = resource->end;
resource = platform_get_resource(pdev, IORESOURCE_DMA,
1);
if (!resource) {
rc = -ENXIO;
goto err_probe_res;
}
dd->rx_dma_crci = resource->start;
dd->tx_dma_crci = resource->end;
dd->use_dma = 1;
master->dma_alignment = dma_get_cache_alignment();
}
}
skip_dma_resources:
spin_lock_init(&dd->queue_lock);
mutex_init(&dd->core_lock);
INIT_LIST_HEAD(&dd->queue);
INIT_WORK(&dd->work_data, msm_spi_workq);
init_waitqueue_head(&dd->continue_suspend);
dd->workqueue = create_singlethread_workqueue(
dev_name(master->dev.parent));
if (!dd->workqueue)
goto err_probe_workq;
if (!devm_request_mem_region(&pdev->dev, dd->mem_phys_addr,
dd->mem_size, SPI_DRV_NAME)) {
rc = -ENXIO;
goto err_probe_reqmem;
}
dd->base = devm_ioremap(&pdev->dev, dd->mem_phys_addr, dd->mem_size);
if (!dd->base) {
rc = -ENOMEM;
goto err_probe_reqmem;
}
if (pdata && pdata->rsl_id) {
struct remote_mutex_id rmid;
rmid.r_spinlock_id = pdata->rsl_id;
rmid.delay_us = SPI_TRYLOCK_DELAY;
rc = remote_mutex_init(&dd->r_lock, &rmid);
if (rc) {
dev_err(&pdev->dev, "%s: unable to init remote_mutex "
"(%s), (rc=%d)\n", rmid.r_spinlock_id,
__func__, rc);
goto err_probe_rlock_init;
}
dd->use_rlock = 1;
dd->pm_lat = pdata->pm_lat;
pm_qos_add_request(&qos_req_list, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
}
mutex_lock(&dd->core_lock);
if (dd->use_rlock)
remote_mutex_lock(&dd->r_lock);
locked = 1;
dd->dev = &pdev->dev;
dd->clk = clk_get(&pdev->dev, "core_clk");
if (IS_ERR(dd->clk)) {
dev_err(&pdev->dev, "%s: unable to get core_clk\n", __func__);
rc = PTR_ERR(dd->clk);
goto err_probe_clk_get;
}
dd->pclk = clk_get(&pdev->dev, "iface_clk");
if (IS_ERR(dd->pclk)) {
dev_err(&pdev->dev, "%s: unable to get iface_clk\n", __func__);
rc = PTR_ERR(dd->pclk);
goto err_probe_pclk_get;
}
if (pdata && pdata->max_clock_speed)
msm_spi_clock_set(dd, dd->pdata->max_clock_speed);
rc = clk_prepare_enable(dd->clk);
if (rc) {
dev_err(&pdev->dev, "%s: unable to enable core_clk\n",
__func__);
goto err_probe_clk_enable;
}
clk_enabled = 1;
rc = clk_prepare_enable(dd->pclk);
if (rc) {
dev_err(&pdev->dev, "%s: unable to enable iface_clk\n",
__func__);
goto err_probe_pclk_enable;
}
pclk_enabled = 1;
rc = msm_spi_configure_gsbi(dd, pdev);
if (rc)
goto err_probe_gsbi;
msm_spi_calculate_fifo_size(dd);
if (dd->use_dma) {
rc = msm_spi_init_dma(dd);
if (rc)
goto err_probe_dma;
}
msm_spi_register_init(dd);
/*
* The SPI core generates a bogus input overrun error on some targets,
* when a transition from run to reset state occurs and if the FIFO has
* an odd number of entries. Hence we disable the INPUT_OVER_RUN_ERR_EN
* bit.
*/
msm_spi_enable_error_flags(dd);
writel_relaxed(SPI_IO_C_NO_TRI_STATE, dd->base + SPI_IO_CONTROL);
rc = msm_spi_set_state(dd, SPI_OP_STATE_RESET);
if (rc)
goto err_probe_state;
clk_disable_unprepare(dd->clk);
clk_disable_unprepare(dd->pclk);
clk_enabled = 0;
pclk_enabled = 0;
dd->suspended = 1;
dd->transfer_pending = 0;
dd->multi_xfr = 0;
dd->mode = SPI_MODE_NONE;
rc = msm_spi_request_irq(dd, pdev, master);
if (rc)
goto err_probe_irq;
msm_spi_disable_irqs(dd);
if (dd->use_rlock)
remote_mutex_unlock(&dd->r_lock);
mutex_unlock(&dd->core_lock);
locked = 0;
pm_runtime_set_autosuspend_delay(&pdev->dev, MSEC_PER_SEC);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
rc = spi_register_master(master);
if (rc)
goto err_probe_reg_master;
rc = sysfs_create_group(&(dd->dev->kobj), &dev_attr_grp);
if (rc) {
dev_err(&pdev->dev, "failed to create dev. attrs : %d\n", rc);
goto err_attrs;
}
spi_debugfs_init(dd);
return 0;
err_attrs:
spi_unregister_master(master);
err_probe_reg_master:
pm_runtime_disable(&pdev->dev);
err_probe_irq:
err_probe_state:
msm_spi_teardown_dma(dd);
err_probe_dma:
err_probe_gsbi:
if (pclk_enabled)
clk_disable_unprepare(dd->pclk);
err_probe_pclk_enable:
if (clk_enabled)
clk_disable_unprepare(dd->clk);
err_probe_clk_enable:
clk_put(dd->pclk);
err_probe_pclk_get:
clk_put(dd->clk);
err_probe_clk_get:
if (locked) {
if (dd->use_rlock)
remote_mutex_unlock(&dd->r_lock);
mutex_unlock(&dd->core_lock);
}
err_probe_rlock_init:
err_probe_reqmem:
destroy_workqueue(dd->workqueue);
err_probe_workq:
err_probe_res:
spi_master_put(master);
err_probe_exit:
return rc;
}
#ifdef CONFIG_PM
static int msm_spi_pm_suspend_runtime(struct device *device)
{
struct platform_device *pdev = to_platform_device(device);
struct spi_master *master = platform_get_drvdata(pdev);
struct msm_spi *dd;
unsigned long flags;
dev_dbg(device, "pm_runtime: suspending...\n");
if (!master)
goto suspend_exit;
dd = spi_master_get_devdata(master);
if (!dd)
goto suspend_exit;
if (dd->suspended)
return 0;
/*
* Make sure nothing is added to the queue while we're
* suspending
*/
spin_lock_irqsave(&dd->queue_lock, flags);
dd->suspended = 1;
spin_unlock_irqrestore(&dd->queue_lock, flags);
/* Wait for transactions to end, or time out */
wait_event_interruptible(dd->continue_suspend,
!dd->transfer_pending);
msm_spi_disable_irqs(dd);
clk_disable_unprepare(dd->clk);
clk_disable_unprepare(dd->pclk);
/* Free the spi clk, miso, mosi, cs gpio */
if (dd->pdata && dd->pdata->gpio_release)
dd->pdata->gpio_release();
msm_spi_free_gpios(dd);
if (pm_qos_request_active(&qos_req_list))
pm_qos_update_request(&qos_req_list,
PM_QOS_DEFAULT_VALUE);
suspend_exit:
return 0;
}
static int msm_spi_pm_resume_runtime(struct device *device)
{
struct platform_device *pdev = to_platform_device(device);
struct spi_master *master = platform_get_drvdata(pdev);
struct msm_spi *dd;
int ret = 0;
dev_dbg(device, "pm_runtime: resuming...\n");
if (!master)
goto resume_exit;
dd = spi_master_get_devdata(master);
if (!dd)
goto resume_exit;
if (!dd->suspended)
return 0;
if (pm_qos_request_active(&qos_req_list))
pm_qos_update_request(&qos_req_list,
dd->pm_lat);
/* Configure the spi clk, miso, mosi and cs gpio */
if (dd->pdata->gpio_config) {
ret = dd->pdata->gpio_config();
if (ret) {
dev_err(dd->dev,
"%s: error configuring GPIOs\n",
__func__);
return ret;
}
}
ret = msm_spi_request_gpios(dd);
if (ret)
return ret;
clk_prepare_enable(dd->clk);
clk_prepare_enable(dd->pclk);
msm_spi_enable_irqs(dd);
dd->suspended = 0;
resume_exit:
return 0;
}
static int msm_spi_suspend(struct device *device)
{
if (!pm_runtime_enabled(device) || !pm_runtime_suspended(device)) {
struct platform_device *pdev = to_platform_device(device);
struct spi_master *master = platform_get_drvdata(pdev);
struct msm_spi *dd;
dev_dbg(device, "system suspend");
if (!master)
goto suspend_exit;
dd = spi_master_get_devdata(master);
if (!dd)
goto suspend_exit;
msm_spi_pm_suspend_runtime(device);
/*
* set the device's runtime PM status to 'suspended'
*/
pm_runtime_disable(device);
pm_runtime_set_suspended(device);
pm_runtime_enable(device);
}
suspend_exit:
return 0;
}
static int msm_spi_resume(struct device *device)
{
/*
* Rely on runtime-PM to call resume in case it is enabled
* Even if it's not enabled, rely on 1st client transaction to do
* clock ON and gpio configuration
*/
dev_dbg(device, "system resume");
return 0;
}
#else
#define msm_spi_suspend NULL
#define msm_spi_resume NULL
#define msm_spi_pm_suspend_runtime NULL
#define msm_spi_pm_resume_runtime NULL
#endif /* CONFIG_PM */
static int __devexit msm_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct msm_spi *dd = spi_master_get_devdata(master);
pm_qos_remove_request(&qos_req_list);
spi_debugfs_exit(dd);
sysfs_remove_group(&pdev->dev.kobj, &dev_attr_grp);
msm_spi_teardown_dma(dd);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
clk_put(dd->clk);
clk_put(dd->pclk);
destroy_workqueue(dd->workqueue);
platform_set_drvdata(pdev, 0);
spi_unregister_master(master);
spi_master_put(master);
return 0;
}
static struct of_device_id msm_spi_dt_match[] = {
{
.compatible = "qcom,spi-qup-v2",
},
{}
};
static const struct dev_pm_ops msm_spi_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_spi_suspend, msm_spi_resume)
SET_RUNTIME_PM_OPS(msm_spi_pm_suspend_runtime,
msm_spi_pm_resume_runtime, NULL)
};
static struct platform_driver msm_spi_driver = {
.driver = {
.name = SPI_DRV_NAME,
.owner = THIS_MODULE,
.pm = &msm_spi_dev_pm_ops,
.of_match_table = msm_spi_dt_match,
},
.remove = __exit_p(msm_spi_remove),
};
static int __init msm_spi_init(void)
{
return platform_driver_probe(&msm_spi_driver, msm_spi_probe);
}
module_init(msm_spi_init);
static void __exit msm_spi_exit(void)
{
platform_driver_unregister(&msm_spi_driver);
}
module_exit(msm_spi_exit);
MODULE_LICENSE("GPL v2");
MODULE_VERSION("0.4");
MODULE_ALIAS("platform:"SPI_DRV_NAME);
| gpl-2.0 |
byzvulture/android_kernel_zte_nx503a | fs/fat/cache.c | 1517 | 8778 | /*
* linux/fs/fat/cache.c
*
* Written 1992,1993 by Werner Almesberger
*
* Mar 1999. AV. Changed cache, so that it uses the starting cluster instead
* of inode number.
* May 1999. AV. Fixed the bogosity with FAT32 (read "FAT28"). Fscking lusers.
*/
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/buffer_head.h>
#include "fat.h"
/* this must be > 0. */
#define FAT_MAX_CACHE 8
struct fat_cache {
struct list_head cache_list;
int nr_contig; /* number of contiguous clusters */
int fcluster; /* cluster number in the file. */
int dcluster; /* cluster number on disk. */
};
struct fat_cache_id {
unsigned int id;
int nr_contig;
int fcluster;
int dcluster;
};
static inline int fat_max_cache(struct inode *inode)
{
return FAT_MAX_CACHE;
}
static struct kmem_cache *fat_cache_cachep;
static void init_once(void *foo)
{
struct fat_cache *cache = (struct fat_cache *)foo;
INIT_LIST_HEAD(&cache->cache_list);
}
int __init fat_cache_init(void)
{
fat_cache_cachep = kmem_cache_create("fat_cache",
sizeof(struct fat_cache),
0, SLAB_RECLAIM_ACCOUNT|SLAB_MEM_SPREAD,
init_once);
if (fat_cache_cachep == NULL)
return -ENOMEM;
return 0;
}
void fat_cache_destroy(void)
{
kmem_cache_destroy(fat_cache_cachep);
}
static inline struct fat_cache *fat_cache_alloc(struct inode *inode)
{
return kmem_cache_alloc(fat_cache_cachep, GFP_NOFS);
}
static inline void fat_cache_free(struct fat_cache *cache)
{
BUG_ON(!list_empty(&cache->cache_list));
kmem_cache_free(fat_cache_cachep, cache);
}
static inline void fat_cache_update_lru(struct inode *inode,
struct fat_cache *cache)
{
if (MSDOS_I(inode)->cache_lru.next != &cache->cache_list)
list_move(&cache->cache_list, &MSDOS_I(inode)->cache_lru);
}
static int fat_cache_lookup(struct inode *inode, int fclus,
struct fat_cache_id *cid,
int *cached_fclus, int *cached_dclus)
{
static struct fat_cache nohit = { .fcluster = 0, };
struct fat_cache *hit = &nohit, *p;
int offset = -1;
spin_lock(&MSDOS_I(inode)->cache_lru_lock);
list_for_each_entry(p, &MSDOS_I(inode)->cache_lru, cache_list) {
/* Find the cache of "fclus" or nearest cache. */
if (p->fcluster <= fclus && hit->fcluster < p->fcluster) {
hit = p;
if ((hit->fcluster + hit->nr_contig) < fclus) {
offset = hit->nr_contig;
} else {
offset = fclus - hit->fcluster;
break;
}
}
}
if (hit != &nohit) {
fat_cache_update_lru(inode, hit);
cid->id = MSDOS_I(inode)->cache_valid_id;
cid->nr_contig = hit->nr_contig;
cid->fcluster = hit->fcluster;
cid->dcluster = hit->dcluster;
*cached_fclus = cid->fcluster + offset;
*cached_dclus = cid->dcluster + offset;
}
spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
return offset;
}
static struct fat_cache *fat_cache_merge(struct inode *inode,
struct fat_cache_id *new)
{
struct fat_cache *p;
list_for_each_entry(p, &MSDOS_I(inode)->cache_lru, cache_list) {
/* Find the same part as "new" in cluster-chain. */
if (p->fcluster == new->fcluster) {
BUG_ON(p->dcluster != new->dcluster);
if (new->nr_contig > p->nr_contig)
p->nr_contig = new->nr_contig;
return p;
}
}
return NULL;
}
static void fat_cache_add(struct inode *inode, struct fat_cache_id *new)
{
struct fat_cache *cache, *tmp;
if (new->fcluster == -1) /* dummy cache */
return;
spin_lock(&MSDOS_I(inode)->cache_lru_lock);
if (new->id != FAT_CACHE_VALID &&
new->id != MSDOS_I(inode)->cache_valid_id)
goto out; /* this cache was invalidated */
cache = fat_cache_merge(inode, new);
if (cache == NULL) {
if (MSDOS_I(inode)->nr_caches < fat_max_cache(inode)) {
MSDOS_I(inode)->nr_caches++;
spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
tmp = fat_cache_alloc(inode);
if (!tmp) {
spin_lock(&MSDOS_I(inode)->cache_lru_lock);
MSDOS_I(inode)->nr_caches--;
spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
return;
}
spin_lock(&MSDOS_I(inode)->cache_lru_lock);
cache = fat_cache_merge(inode, new);
if (cache != NULL) {
MSDOS_I(inode)->nr_caches--;
fat_cache_free(tmp);
goto out_update_lru;
}
cache = tmp;
} else {
struct list_head *p = MSDOS_I(inode)->cache_lru.prev;
cache = list_entry(p, struct fat_cache, cache_list);
}
cache->fcluster = new->fcluster;
cache->dcluster = new->dcluster;
cache->nr_contig = new->nr_contig;
}
out_update_lru:
fat_cache_update_lru(inode, cache);
out:
spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
}
/*
* Cache invalidation occurs rarely, thus the LRU chain is not updated. It
* fixes itself after a while.
*/
static void __fat_cache_inval_inode(struct inode *inode)
{
struct msdos_inode_info *i = MSDOS_I(inode);
struct fat_cache *cache;
while (!list_empty(&i->cache_lru)) {
cache = list_entry(i->cache_lru.next, struct fat_cache, cache_list);
list_del_init(&cache->cache_list);
i->nr_caches--;
fat_cache_free(cache);
}
/* Update. The copy of caches before this id is discarded. */
i->cache_valid_id++;
if (i->cache_valid_id == FAT_CACHE_VALID)
i->cache_valid_id++;
}
void fat_cache_inval_inode(struct inode *inode)
{
spin_lock(&MSDOS_I(inode)->cache_lru_lock);
__fat_cache_inval_inode(inode);
spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
}
static inline int cache_contiguous(struct fat_cache_id *cid, int dclus)
{
cid->nr_contig++;
return ((cid->dcluster + cid->nr_contig) == dclus);
}
static inline void cache_init(struct fat_cache_id *cid, int fclus, int dclus)
{
cid->id = FAT_CACHE_VALID;
cid->fcluster = fclus;
cid->dcluster = dclus;
cid->nr_contig = 0;
}
int fat_get_cluster(struct inode *inode, int cluster, int *fclus, int *dclus)
{
struct super_block *sb = inode->i_sb;
const int limit = sb->s_maxbytes >> MSDOS_SB(sb)->cluster_bits;
struct fat_entry fatent;
struct fat_cache_id cid;
int nr;
BUG_ON(MSDOS_I(inode)->i_start == 0);
*fclus = 0;
*dclus = MSDOS_I(inode)->i_start;
if (cluster == 0)
return 0;
if (fat_cache_lookup(inode, cluster, &cid, fclus, dclus) < 0) {
/*
* dummy, always not contiguous
* This is reinitialized by cache_init(), later.
*/
cache_init(&cid, -1, -1);
}
fatent_init(&fatent);
while (*fclus < cluster) {
/* prevent the infinite loop of cluster chain */
if (*fclus > limit) {
fat_fs_error_ratelimit(sb,
"%s: detected the cluster chain loop"
" (i_pos %lld)", __func__,
MSDOS_I(inode)->i_pos);
nr = -EIO;
goto out;
}
nr = fat_ent_read(inode, &fatent, *dclus);
if (nr < 0)
goto out;
else if (nr == FAT_ENT_FREE) {
fat_fs_error_ratelimit(sb, "%s: invalid cluster chain"
" (i_pos %lld)", __func__,
MSDOS_I(inode)->i_pos);
nr = -EIO;
goto out;
} else if (nr == FAT_ENT_EOF) {
fat_cache_add(inode, &cid);
goto out;
}
(*fclus)++;
*dclus = nr;
if (!cache_contiguous(&cid, *dclus))
cache_init(&cid, *fclus, *dclus);
}
nr = 0;
fat_cache_add(inode, &cid);
out:
fatent_brelse(&fatent);
return nr;
}
static int fat_bmap_cluster(struct inode *inode, int cluster)
{
struct super_block *sb = inode->i_sb;
int ret, fclus, dclus;
if (MSDOS_I(inode)->i_start == 0)
return 0;
ret = fat_get_cluster(inode, cluster, &fclus, &dclus);
if (ret < 0)
return ret;
else if (ret == FAT_ENT_EOF) {
fat_fs_error_ratelimit(sb,
"%s: request beyond EOF (i_pos %lld)",
__func__, MSDOS_I(inode)->i_pos);
return -EIO;
}
return dclus;
}
int fat_bmap(struct inode *inode, sector_t sector, sector_t *phys,
unsigned long *mapped_blocks, int create)
{
struct super_block *sb = inode->i_sb;
struct msdos_sb_info *sbi = MSDOS_SB(sb);
const unsigned long blocksize = sb->s_blocksize;
const unsigned char blocksize_bits = sb->s_blocksize_bits;
sector_t last_block;
int cluster, offset;
*phys = 0;
*mapped_blocks = 0;
if ((sbi->fat_bits != 32) && (inode->i_ino == MSDOS_ROOT_INO)) {
if (sector < (sbi->dir_entries >> sbi->dir_per_block_bits)) {
*phys = sector + sbi->dir_start;
*mapped_blocks = 1;
}
return 0;
}
last_block = (i_size_read(inode) + (blocksize - 1)) >> blocksize_bits;
if (sector >= last_block) {
if (!create)
return 0;
/*
* ->mmu_private can access on only allocation path.
* (caller must hold ->i_mutex)
*/
last_block = (MSDOS_I(inode)->mmu_private + (blocksize - 1))
>> blocksize_bits;
if (sector >= last_block)
return 0;
}
cluster = sector >> (sbi->cluster_bits - sb->s_blocksize_bits);
offset = sector & (sbi->sec_per_clus - 1);
cluster = fat_bmap_cluster(inode, cluster);
if (cluster < 0)
return cluster;
else if (cluster) {
*phys = fat_clus_to_blknr(sbi, cluster) + offset;
*mapped_blocks = sbi->sec_per_clus - offset;
if (*mapped_blocks > last_block - sector)
*mapped_blocks = last_block - sector;
}
return 0;
}
| gpl-2.0 |
dianlujitao/android_kernel_zte_msm8994 | arch/arm/mach-imx/ehci-imx25.c | 2797 | 2742 | /*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/platform_data/usb-ehci-mxc.h>
#include "hardware.h"
#define USBCTRL_OTGBASE_OFFSET 0x600
#define MX25_OTG_SIC_SHIFT 29
#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
#define MX25_OTG_PM_BIT (1 << 24)
#define MX25_OTG_PP_BIT (1 << 11)
#define MX25_OTG_OCPOL_BIT (1 << 3)
#define MX25_H1_SIC_SHIFT 21
#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
#define MX25_H1_PP_BIT (1 << 18)
#define MX25_H1_PM_BIT (1 << 16)
#define MX25_H1_IPPUE_UP_BIT (1 << 7)
#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
#define MX25_H1_TLL_BIT (1 << 5)
#define MX25_H1_USBTE_BIT (1 << 4)
#define MX25_H1_OCPOL_BIT (1 << 2)
int mx25_initialize_usb_hw(int port, unsigned int flags)
{
unsigned int v;
v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
switch (port) {
case 0: /* OTG port */
v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
MX25_OTG_OCPOL_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_OTG_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_OTG_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_OTG_OCPOL_BIT;
break;
case 1: /* H1 port */
v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_H1_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_H1_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_H1_OCPOL_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX25_H1_TLL_BIT;
if (flags & MXC_EHCI_INTERNAL_PHY)
v |= MX25_H1_USBTE_BIT;
if (flags & MXC_EHCI_IPPUE_DOWN)
v |= MX25_H1_IPPUE_DOWN_BIT;
if (flags & MXC_EHCI_IPPUE_UP)
v |= MX25_H1_IPPUE_UP_BIT;
break;
default:
return -EINVAL;
}
writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
return 0;
}
| gpl-2.0 |
mupuf/linux-nouveau-pm | sound/usb/proc.c | 3821 | 6138 | /*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/usb.h>
#include <sound/core.h>
#include <sound/info.h>
#include <sound/pcm.h>
#include "usbaudio.h"
#include "helper.h"
#include "card.h"
#include "endpoint.h"
#include "proc.h"
/* convert our full speed USB rate into sampling rate in Hz */
static inline unsigned get_full_speed_hz(unsigned int usb_rate)
{
return (usb_rate * 125 + (1 << 12)) >> 13;
}
/* convert our high speed USB rate into sampling rate in Hz */
static inline unsigned get_high_speed_hz(unsigned int usb_rate)
{
return (usb_rate * 125 + (1 << 9)) >> 10;
}
/*
* common proc files to show the usb device info
*/
static void proc_audio_usbbus_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
{
struct snd_usb_audio *chip = entry->private_data;
if (!chip->shutdown)
snd_iprintf(buffer, "%03d/%03d\n", chip->dev->bus->busnum, chip->dev->devnum);
}
static void proc_audio_usbid_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
{
struct snd_usb_audio *chip = entry->private_data;
if (!chip->shutdown)
snd_iprintf(buffer, "%04x:%04x\n",
USB_ID_VENDOR(chip->usb_id),
USB_ID_PRODUCT(chip->usb_id));
}
void snd_usb_audio_create_proc(struct snd_usb_audio *chip)
{
struct snd_info_entry *entry;
if (!snd_card_proc_new(chip->card, "usbbus", &entry))
snd_info_set_text_ops(entry, chip, proc_audio_usbbus_read);
if (!snd_card_proc_new(chip->card, "usbid", &entry))
snd_info_set_text_ops(entry, chip, proc_audio_usbid_read);
}
/*
* proc interface for list the supported pcm formats
*/
static void proc_dump_substream_formats(struct snd_usb_substream *subs, struct snd_info_buffer *buffer)
{
struct audioformat *fp;
static char *sync_types[4] = {
"NONE", "ASYNC", "ADAPTIVE", "SYNC"
};
list_for_each_entry(fp, &subs->fmt_list, list) {
snd_pcm_format_t fmt;
snd_iprintf(buffer, " Interface %d\n", fp->iface);
snd_iprintf(buffer, " Altset %d\n", fp->altsetting);
snd_iprintf(buffer, " Format:");
for (fmt = 0; fmt <= SNDRV_PCM_FORMAT_LAST; ++fmt)
if (fp->formats & pcm_format_to_bits(fmt))
snd_iprintf(buffer, " %s",
snd_pcm_format_name(fmt));
snd_iprintf(buffer, "\n");
snd_iprintf(buffer, " Channels: %d\n", fp->channels);
snd_iprintf(buffer, " Endpoint: %d %s (%s)\n",
fp->endpoint & USB_ENDPOINT_NUMBER_MASK,
fp->endpoint & USB_DIR_IN ? "IN" : "OUT",
sync_types[(fp->ep_attr & USB_ENDPOINT_SYNCTYPE) >> 2]);
if (fp->rates & SNDRV_PCM_RATE_CONTINUOUS) {
snd_iprintf(buffer, " Rates: %d - %d (continuous)\n",
fp->rate_min, fp->rate_max);
} else {
unsigned int i;
snd_iprintf(buffer, " Rates: ");
for (i = 0; i < fp->nr_rates; i++) {
if (i > 0)
snd_iprintf(buffer, ", ");
snd_iprintf(buffer, "%d", fp->rate_table[i]);
}
snd_iprintf(buffer, "\n");
}
if (subs->speed != USB_SPEED_FULL)
snd_iprintf(buffer, " Data packet interval: %d us\n",
125 * (1 << fp->datainterval));
// snd_iprintf(buffer, " Max Packet Size = %d\n", fp->maxpacksize);
// snd_iprintf(buffer, " EP Attribute = %#x\n", fp->attributes);
}
}
static void proc_dump_ep_status(struct snd_usb_substream *subs,
struct snd_usb_endpoint *data_ep,
struct snd_usb_endpoint *sync_ep,
struct snd_info_buffer *buffer)
{
if (!data_ep)
return;
snd_iprintf(buffer, " Packet Size = %d\n", data_ep->curpacksize);
snd_iprintf(buffer, " Momentary freq = %u Hz (%#x.%04x)\n",
subs->speed == USB_SPEED_FULL
? get_full_speed_hz(data_ep->freqm)
: get_high_speed_hz(data_ep->freqm),
data_ep->freqm >> 16, data_ep->freqm & 0xffff);
if (sync_ep && data_ep->freqshift != INT_MIN) {
int res = 16 - data_ep->freqshift;
snd_iprintf(buffer, " Feedback Format = %d.%d\n",
(sync_ep->syncmaxsize > 3 ? 32 : 24) - res, res);
}
}
static void proc_dump_substream_status(struct snd_usb_substream *subs, struct snd_info_buffer *buffer)
{
if (subs->running) {
snd_iprintf(buffer, " Status: Running\n");
snd_iprintf(buffer, " Interface = %d\n", subs->interface);
snd_iprintf(buffer, " Altset = %d\n", subs->altset_idx);
proc_dump_ep_status(subs, subs->data_endpoint, subs->sync_endpoint, buffer);
} else {
snd_iprintf(buffer, " Status: Stop\n");
}
}
static void proc_pcm_format_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
{
struct snd_usb_stream *stream = entry->private_data;
snd_iprintf(buffer, "%s : %s\n", stream->chip->card->longname, stream->pcm->name);
if (stream->substream[SNDRV_PCM_STREAM_PLAYBACK].num_formats) {
snd_iprintf(buffer, "\nPlayback:\n");
proc_dump_substream_status(&stream->substream[SNDRV_PCM_STREAM_PLAYBACK], buffer);
proc_dump_substream_formats(&stream->substream[SNDRV_PCM_STREAM_PLAYBACK], buffer);
}
if (stream->substream[SNDRV_PCM_STREAM_CAPTURE].num_formats) {
snd_iprintf(buffer, "\nCapture:\n");
proc_dump_substream_status(&stream->substream[SNDRV_PCM_STREAM_CAPTURE], buffer);
proc_dump_substream_formats(&stream->substream[SNDRV_PCM_STREAM_CAPTURE], buffer);
}
}
void snd_usb_proc_pcm_format_add(struct snd_usb_stream *stream)
{
struct snd_info_entry *entry;
char name[32];
struct snd_card *card = stream->chip->card;
sprintf(name, "stream%d", stream->pcm_index);
if (!snd_card_proc_new(card, name, &entry))
snd_info_set_text_ops(entry, stream, proc_pcm_format_read);
}
| gpl-2.0 |
Oi-Android/android_kernel_xiaomi_ferrari-mr | sound/oss/uart6850.c | 4589 | 7241 | /*
* sound/oss/uart6850.c
*
*
* Copyright (C) by Hannu Savolainen 1993-1997
*
* OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
* Version 2 (June 1991). See the "COPYING" file distributed with this software
* for more info.
* Extended by Alan Cox for Red Hat Software. Now a loadable MIDI driver.
* 28/4/97 - (C) Copyright Alan Cox. Released under the GPL version 2.
*
* Alan Cox: Updated for new modular code. Removed snd_* irq handling. Now
* uses native linux resources
* Christoph Hellwig: Adapted to module_init/module_exit
* Jeff Garzik: Made it work again, in theory
* FIXME: If the request_irq() succeeds, the probe succeeds. Ug.
*
* Status: Testing required (no shit -jgarzik)
*
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/spinlock.h>
/* Mon Nov 22 22:38:35 MET 1993 marco@driq.home.usn.nl:
* added 6850 support, used with COVOX SoundMaster II and custom cards.
*/
#include "sound_config.h"
static int uart6850_base = 0x330;
static int *uart6850_osp;
#define DATAPORT (uart6850_base)
#define COMDPORT (uart6850_base+1)
#define STATPORT (uart6850_base+1)
static int uart6850_status(void)
{
return inb(STATPORT);
}
#define input_avail() (uart6850_status()&INPUT_AVAIL)
#define output_ready() (uart6850_status()&OUTPUT_READY)
static void uart6850_cmd(unsigned char cmd)
{
outb(cmd, COMDPORT);
}
static int uart6850_read(void)
{
return inb(DATAPORT);
}
static void uart6850_write(unsigned char byte)
{
outb(byte, DATAPORT);
}
#define OUTPUT_READY 0x02 /* Mask for data ready Bit */
#define INPUT_AVAIL 0x01 /* Mask for Data Send Ready Bit */
#define UART_RESET 0x95
#define UART_MODE_ON 0x03
static int uart6850_opened;
static int uart6850_irq;
static int uart6850_detected;
static int my_dev;
static DEFINE_SPINLOCK(lock);
static void (*midi_input_intr) (int dev, unsigned char data);
static void poll_uart6850(unsigned long dummy);
static DEFINE_TIMER(uart6850_timer, poll_uart6850, 0, 0);
static void uart6850_input_loop(void)
{
int count = 10;
while (count)
{
/*
* Not timed out
*/
if (input_avail())
{
unsigned char c = uart6850_read();
count = 100;
if (uart6850_opened & OPEN_READ)
midi_input_intr(my_dev, c);
}
else
{
while (!input_avail() && count)
count--;
}
}
}
static irqreturn_t m6850intr(int irq, void *dev_id)
{
if (input_avail())
uart6850_input_loop();
return IRQ_HANDLED;
}
/*
* It looks like there is no input interrupts in the UART mode. Let's try
* polling.
*/
static void poll_uart6850(unsigned long dummy)
{
unsigned long flags;
if (!(uart6850_opened & OPEN_READ))
return; /* Device has been closed */
spin_lock_irqsave(&lock,flags);
if (input_avail())
uart6850_input_loop();
uart6850_timer.expires = 1 + jiffies;
add_timer(&uart6850_timer);
/*
* Come back later
*/
spin_unlock_irqrestore(&lock,flags);
}
static int uart6850_open(int dev, int mode,
void (*input) (int dev, unsigned char data),
void (*output) (int dev)
)
{
if (uart6850_opened)
{
/* printk("Midi6850: Midi busy\n");*/
return -EBUSY;
}
uart6850_cmd(UART_RESET);
uart6850_input_loop();
midi_input_intr = input;
uart6850_opened = mode;
poll_uart6850(0); /*
* Enable input polling
*/
return 0;
}
static void uart6850_close(int dev)
{
uart6850_cmd(UART_MODE_ON);
del_timer(&uart6850_timer);
uart6850_opened = 0;
}
static int uart6850_out(int dev, unsigned char midi_byte)
{
int timeout;
unsigned long flags;
/*
* Test for input since pending input seems to block the output.
*/
spin_lock_irqsave(&lock,flags);
if (input_avail())
uart6850_input_loop();
spin_unlock_irqrestore(&lock,flags);
/*
* Sometimes it takes about 13000 loops before the output becomes ready
* (After reset). Normally it takes just about 10 loops.
*/
for (timeout = 30000; timeout > 0 && !output_ready(); timeout--); /*
* Wait
*/
if (!output_ready())
{
printk(KERN_WARNING "Midi6850: Timeout\n");
return 0;
}
uart6850_write(midi_byte);
return 1;
}
static inline int uart6850_command(int dev, unsigned char *midi_byte)
{
return 1;
}
static inline int uart6850_start_read(int dev)
{
return 0;
}
static inline int uart6850_end_read(int dev)
{
return 0;
}
static inline void uart6850_kick(int dev)
{
}
static inline int uart6850_buffer_status(int dev)
{
return 0; /*
* No data in buffers
*/
}
#define MIDI_SYNTH_NAME "6850 UART Midi"
#define MIDI_SYNTH_CAPS SYNTH_CAP_INPUT
#include "midi_synth.h"
static struct midi_operations uart6850_operations =
{
.owner = THIS_MODULE,
.info = {"6850 UART", 0, 0, SNDCARD_UART6850},
.converter = &std_midi_synth,
.in_info = {0},
.open = uart6850_open,
.close = uart6850_close,
.outputc = uart6850_out,
.start_read = uart6850_start_read,
.end_read = uart6850_end_read,
.kick = uart6850_kick,
.command = uart6850_command,
.buffer_status = uart6850_buffer_status
};
static void __init attach_uart6850(struct address_info *hw_config)
{
int ok, timeout;
unsigned long flags;
if (!uart6850_detected)
return;
if ((my_dev = sound_alloc_mididev()) == -1)
{
printk(KERN_INFO "uart6850: Too many midi devices detected\n");
return;
}
uart6850_base = hw_config->io_base;
uart6850_osp = hw_config->osp;
uart6850_irq = hw_config->irq;
spin_lock_irqsave(&lock,flags);
for (timeout = 30000; timeout > 0 && !output_ready(); timeout--); /*
* Wait
*/
uart6850_cmd(UART_MODE_ON);
ok = 1;
spin_unlock_irqrestore(&lock,flags);
conf_printf("6850 Midi Interface", hw_config);
std_midi_synth.midi_dev = my_dev;
hw_config->slots[4] = my_dev;
midi_devs[my_dev] = &uart6850_operations;
sequencer_init();
}
static inline int reset_uart6850(void)
{
uart6850_read();
return 1; /*
* OK
*/
}
static int __init probe_uart6850(struct address_info *hw_config)
{
int ok;
uart6850_osp = hw_config->osp;
uart6850_base = hw_config->io_base;
uart6850_irq = hw_config->irq;
if (request_irq(uart6850_irq, m6850intr, 0, "MIDI6850", NULL) < 0)
return 0;
ok = reset_uart6850();
uart6850_detected = ok;
return ok;
}
static void __exit unload_uart6850(struct address_info *hw_config)
{
free_irq(hw_config->irq, NULL);
sound_unload_mididev(hw_config->slots[4]);
}
static struct address_info cfg_mpu;
static int __initdata io = -1;
static int __initdata irq = -1;
module_param(io, int, 0);
module_param(irq, int, 0);
static int __init init_uart6850(void)
{
cfg_mpu.io_base = io;
cfg_mpu.irq = irq;
if (cfg_mpu.io_base == -1 || cfg_mpu.irq == -1) {
printk(KERN_INFO "uart6850: irq and io must be set.\n");
return -EINVAL;
}
if (probe_uart6850(&cfg_mpu))
return -ENODEV;
attach_uart6850(&cfg_mpu);
return 0;
}
static void __exit cleanup_uart6850(void)
{
unload_uart6850(&cfg_mpu);
}
module_init(init_uart6850);
module_exit(cleanup_uart6850);
#ifndef MODULE
static int __init setup_uart6850(char *str)
{
/* io, irq */
int ints[3];
str = get_options(str, ARRAY_SIZE(ints), ints);
io = ints[1];
irq = ints[2];
return 1;
}
__setup("uart6850=", setup_uart6850);
#endif
MODULE_LICENSE("GPL");
| gpl-2.0 |
SnowDroid/kernel_lge_hammerhead | arch/mips/pmc-sierra/yosemite/prom.c | 4589 | 3135 | /*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 2003, 2004 PMC-Sierra Inc.
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
* Copyright (C) 2004 Ralf Baechle
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/smp.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>
#ifdef CONFIG_SMP
extern void prom_grab_secondary(void);
#else
#define prom_grab_secondary() do { } while (0)
#endif
#include "setup.h"
struct callvectors *debug_vectors;
extern unsigned long yosemite_base;
extern unsigned long cpu_clock_freq;
const char *get_system_type(void)
{
return "PMC-Sierra Yosemite";
}
static void prom_cpu0_exit(void *arg)
{
void *nvram = (void *) YOSEMITE_RTC_BASE;
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
mdelay(100 + (1000 / 16));
/* if the watchdog fails for some reason, let people know */
printk(KERN_NOTICE "Watchdog reset failed\n");
}
/*
* Reset the NVRAM over the local bus
*/
static void prom_exit(void)
{
#ifdef CONFIG_SMP
if (smp_processor_id())
/* CPU 1 */
smp_call_function(prom_cpu0_exit, NULL, 1);
#endif
prom_cpu0_exit(NULL);
}
/*
* Halt the system
*/
static void prom_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
}
extern struct plat_smp_ops yos_smp_ops;
/*
* Init routine which accepts the variables from PMON
*/
void __init prom_init(void)
{
int argc = fw_arg0;
char **arg = (char **) fw_arg1;
char **env = (char **) fw_arg2;
struct callvectors *cv = (struct callvectors *) fw_arg3;
int i = 0;
/* Callbacks for halt, restart */
_machine_restart = (void (*)(char *)) prom_exit;
_machine_halt = prom_halt;
pm_power_off = prom_halt;
debug_vectors = cv;
arcs_cmdline[0] = '\0';
/* Get the boot parameters */
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i]) + 1 >=
sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
if ((strstr(arcs_cmdline, "console=ttyS")) == NULL)
strcat(arcs_cmdline, "console=ttyS0,115200");
#endif
while (*env) {
if (strncmp("ocd_base", *env, strlen("ocd_base")) == 0)
yosemite_base =
simple_strtol(*env + strlen("ocd_base="), NULL,
16);
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0)
cpu_clock_freq =
simple_strtol(*env + strlen("cpuclock="), NULL,
10);
env++;
}
prom_grab_secondary();
register_smp_ops(&yos_smp_ops);
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
| gpl-2.0 |
onejay09/OLD----kernel_HTC_msm7x30_KK | sound/pci/echoaudio/gina20_dsp.c | 12525 | 5668 | /****************************************************************************
Copyright Echo Digital Audio Corporation (c) 1998 - 2004
All rights reserved
www.echoaudio.com
This file is part of Echo Digital Audio's generic driver library.
Echo Digital Audio's generic driver library is free software;
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by the Free Software
Foundation.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston,
MA 02111-1307, USA.
*************************************************************************
Translation from C++ and adaptation for use in ALSA-Driver
were made by Giuliano Pochini <pochini@shiny.it>
****************************************************************************/
static int set_professional_spdif(struct echoaudio *chip, char prof);
static int update_flags(struct echoaudio *chip);
static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
{
int err;
DE_INIT(("init_hw() - Gina20\n"));
if (snd_BUG_ON((subdevice_id & 0xfff0) != GINA20))
return -ENODEV;
if ((err = init_dsp_comm_page(chip))) {
DE_INIT(("init_hw - could not initialize DSP comm page\n"));
return err;
}
chip->device_id = device_id;
chip->subdevice_id = subdevice_id;
chip->bad_board = TRUE;
chip->dsp_code_to_load = FW_GINA20_DSP;
chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
chip->clock_state = GD_CLOCK_UNDEF;
/* Since this card has no ASIC, mark it as loaded so everything
works OK */
chip->asic_loaded = TRUE;
chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL |
ECHO_CLOCK_BIT_SPDIF;
if ((err = load_firmware(chip)) < 0)
return err;
chip->bad_board = FALSE;
DE_INIT(("init_hw done\n"));
return err;
}
static int set_mixer_defaults(struct echoaudio *chip)
{
chip->professional_spdif = FALSE;
return init_line_levels(chip);
}
static u32 detect_input_clocks(const struct echoaudio *chip)
{
u32 clocks_from_dsp, clock_bits;
/* Map the DSP clock detect bits to the generic driver clock
detect bits */
clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
clock_bits = ECHO_CLOCK_BIT_INTERNAL;
if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_SPDIF)
clock_bits |= ECHO_CLOCK_BIT_SPDIF;
return clock_bits;
}
/* The Gina20 has no ASIC. Just do nothing */
static int load_asic(struct echoaudio *chip)
{
return 0;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u8 clock_state, spdif_status;
if (wait_handshake(chip))
return -EIO;
switch (rate) {
case 44100:
clock_state = GD_CLOCK_44;
spdif_status = GD_SPDIF_STATUS_44;
break;
case 48000:
clock_state = GD_CLOCK_48;
spdif_status = GD_SPDIF_STATUS_48;
break;
default:
clock_state = GD_CLOCK_NOCHANGE;
spdif_status = GD_SPDIF_STATUS_NOCHANGE;
break;
}
if (chip->clock_state == clock_state)
clock_state = GD_CLOCK_NOCHANGE;
if (spdif_status == chip->spdif_status)
spdif_status = GD_SPDIF_STATUS_NOCHANGE;
chip->comm_page->sample_rate = cpu_to_le32(rate);
chip->comm_page->gd_clock_state = clock_state;
chip->comm_page->gd_spdif_status = spdif_status;
chip->comm_page->gd_resampler_state = 3; /* magic number - should always be 3 */
/* Save the new audio state if it changed */
if (clock_state != GD_CLOCK_NOCHANGE)
chip->clock_state = clock_state;
if (spdif_status != GD_SPDIF_STATUS_NOCHANGE)
chip->spdif_status = spdif_status;
chip->sample_rate = rate;
clear_handshake(chip);
return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
}
static int set_input_clock(struct echoaudio *chip, u16 clock)
{
DE_ACT(("set_input_clock:\n"));
switch (clock) {
case ECHO_CLOCK_INTERNAL:
/* Reset the audio state to unknown (just in case) */
chip->clock_state = GD_CLOCK_UNDEF;
chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
set_sample_rate(chip, chip->sample_rate);
chip->input_clock = clock;
DE_ACT(("Set Gina clock to INTERNAL\n"));
break;
case ECHO_CLOCK_SPDIF:
chip->comm_page->gd_clock_state = GD_CLOCK_SPDIFIN;
chip->comm_page->gd_spdif_status = GD_SPDIF_STATUS_NOCHANGE;
clear_handshake(chip);
send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
chip->clock_state = GD_CLOCK_SPDIFIN;
DE_ACT(("Set Gina20 clock to SPDIF\n"));
chip->input_clock = clock;
break;
default:
return -EINVAL;
}
return 0;
}
/* Set input bus gain (one unit is 0.5dB !) */
static int set_input_gain(struct echoaudio *chip, u16 input, int gain)
{
if (snd_BUG_ON(input >= num_busses_in(chip)))
return -EINVAL;
if (wait_handshake(chip))
return -EIO;
chip->input_gain[input] = gain;
gain += GL20_INPUT_GAIN_MAGIC_NUMBER;
chip->comm_page->line_in_level[input] = gain;
return 0;
}
/* Tell the DSP to reread the flags from the comm page */
static int update_flags(struct echoaudio *chip)
{
if (wait_handshake(chip))
return -EIO;
clear_handshake(chip);
return send_vector(chip, DSP_VC_UPDATE_FLAGS);
}
static int set_professional_spdif(struct echoaudio *chip, char prof)
{
DE_ACT(("set_professional_spdif %d\n", prof));
if (prof)
chip->comm_page->flags |=
cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
else
chip->comm_page->flags &=
~cpu_to_le32(DSP_FLAG_PROFESSIONAL_SPDIF);
chip->professional_spdif = prof;
return update_flags(chip);
}
| gpl-2.0 |
ZoliN/ChuwiHBKernel | drivers/scsi/lpfc/lpfc_debugfs.c | 238 | 135112 | /*******************************************************************
* This file is part of the Emulex Linux Device Driver for *
* Fibre Channel Host Bus Adapters. *
* Copyright (C) 2007-2012 Emulex. All rights reserved. *
* EMULEX and SLI are trademarks of Emulex. *
* www.emulex.com *
* *
* This program is free software; you can redistribute it and/or *
* modify it under the terms of version 2 of the GNU General *
* Public License as published by the Free Software Foundation. *
* This program is distributed in the hope that it will be useful. *
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
* WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
* DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
* TO BE LEGALLY INVALID. See the GNU General Public License for *
* more details, a copy of which can be found in the file COPYING *
* included with this package. *
*******************************************************************/
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/kthread.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/ctype.h>
#include <scsi/scsi.h>
#include <scsi/scsi_device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_transport_fc.h>
#include "lpfc_hw4.h"
#include "lpfc_hw.h"
#include "lpfc_sli.h"
#include "lpfc_sli4.h"
#include "lpfc_nl.h"
#include "lpfc_disc.h"
#include "lpfc_scsi.h"
#include "lpfc.h"
#include "lpfc_logmsg.h"
#include "lpfc_crtn.h"
#include "lpfc_vport.h"
#include "lpfc_version.h"
#include "lpfc_compat.h"
#include "lpfc_debugfs.h"
#include "lpfc_bsg.h"
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
/*
* debugfs interface
*
* To access this interface the user should:
* # mount -t debugfs none /sys/kernel/debug
*
* The lpfc debugfs directory hierarchy is:
* /sys/kernel/debug/lpfc/fnX/vportY
* where X is the lpfc hba function unique_id
* where Y is the vport VPI on that hba
*
* Debugging services available per vport:
* discovery_trace
* This is an ACSII readable file that contains a trace of the last
* lpfc_debugfs_max_disc_trc events that happened on a specific vport.
* See lpfc_debugfs.h for different categories of discovery events.
* To enable the discovery trace, the following module parameters must be set:
* lpfc_debugfs_enable=1 Turns on lpfc debugfs filesystem support
* lpfc_debugfs_max_disc_trc=X Where X is the event trace depth for
* EACH vport. X MUST also be a power of 2.
* lpfc_debugfs_mask_disc_trc=Y Where Y is an event mask as defined in
* lpfc_debugfs.h .
*
* slow_ring_trace
* This is an ACSII readable file that contains a trace of the last
* lpfc_debugfs_max_slow_ring_trc events that happened on a specific HBA.
* To enable the slow ring trace, the following module parameters must be set:
* lpfc_debugfs_enable=1 Turns on lpfc debugfs filesystem support
* lpfc_debugfs_max_slow_ring_trc=X Where X is the event trace depth for
* the HBA. X MUST also be a power of 2.
*/
static int lpfc_debugfs_enable = 1;
module_param(lpfc_debugfs_enable, int, S_IRUGO);
MODULE_PARM_DESC(lpfc_debugfs_enable, "Enable debugfs services");
/* This MUST be a power of 2 */
static int lpfc_debugfs_max_disc_trc;
module_param(lpfc_debugfs_max_disc_trc, int, S_IRUGO);
MODULE_PARM_DESC(lpfc_debugfs_max_disc_trc,
"Set debugfs discovery trace depth");
/* This MUST be a power of 2 */
static int lpfc_debugfs_max_slow_ring_trc;
module_param(lpfc_debugfs_max_slow_ring_trc, int, S_IRUGO);
MODULE_PARM_DESC(lpfc_debugfs_max_slow_ring_trc,
"Set debugfs slow ring trace depth");
static int lpfc_debugfs_mask_disc_trc;
module_param(lpfc_debugfs_mask_disc_trc, int, S_IRUGO);
MODULE_PARM_DESC(lpfc_debugfs_mask_disc_trc,
"Set debugfs discovery trace mask");
#include <linux/debugfs.h>
static atomic_t lpfc_debugfs_seq_trc_cnt = ATOMIC_INIT(0);
static unsigned long lpfc_debugfs_start_time = 0L;
/* iDiag */
static struct lpfc_idiag idiag;
/**
* lpfc_debugfs_disc_trc_data - Dump discovery logging to a buffer
* @vport: The vport to gather the log info from.
* @buf: The buffer to dump log into.
* @size: The maximum amount of data to process.
*
* Description:
* This routine gathers the lpfc discovery debugfs data from the @vport and
* dumps it to @buf up to @size number of bytes. It will start at the next entry
* in the log and process the log until the end of the buffer. Then it will
* gather from the beginning of the log and process until the current entry.
*
* Notes:
* Discovery logging will be disabled while while this routine dumps the log.
*
* Return Value:
* This routine returns the amount of bytes that were dumped into @buf and will
* not exceed @size.
**/
static int
lpfc_debugfs_disc_trc_data(struct lpfc_vport *vport, char *buf, int size)
{
int i, index, len, enable;
uint32_t ms;
struct lpfc_debugfs_trc *dtp;
char *buffer;
buffer = kmalloc(LPFC_DEBUG_TRC_ENTRY_SIZE, GFP_KERNEL);
if (!buffer)
return 0;
enable = lpfc_debugfs_enable;
lpfc_debugfs_enable = 0;
len = 0;
index = (atomic_read(&vport->disc_trc_cnt) + 1) &
(lpfc_debugfs_max_disc_trc - 1);
for (i = index; i < lpfc_debugfs_max_disc_trc; i++) {
dtp = vport->disc_trc + i;
if (!dtp->fmt)
continue;
ms = jiffies_to_msecs(dtp->jif - lpfc_debugfs_start_time);
snprintf(buffer,
LPFC_DEBUG_TRC_ENTRY_SIZE, "%010d:%010d ms:%s\n",
dtp->seq_cnt, ms, dtp->fmt);
len += snprintf(buf+len, size-len, buffer,
dtp->data1, dtp->data2, dtp->data3);
}
for (i = 0; i < index; i++) {
dtp = vport->disc_trc + i;
if (!dtp->fmt)
continue;
ms = jiffies_to_msecs(dtp->jif - lpfc_debugfs_start_time);
snprintf(buffer,
LPFC_DEBUG_TRC_ENTRY_SIZE, "%010d:%010d ms:%s\n",
dtp->seq_cnt, ms, dtp->fmt);
len += snprintf(buf+len, size-len, buffer,
dtp->data1, dtp->data2, dtp->data3);
}
lpfc_debugfs_enable = enable;
kfree(buffer);
return len;
}
/**
* lpfc_debugfs_slow_ring_trc_data - Dump slow ring logging to a buffer
* @phba: The HBA to gather the log info from.
* @buf: The buffer to dump log into.
* @size: The maximum amount of data to process.
*
* Description:
* This routine gathers the lpfc slow ring debugfs data from the @phba and
* dumps it to @buf up to @size number of bytes. It will start at the next entry
* in the log and process the log until the end of the buffer. Then it will
* gather from the beginning of the log and process until the current entry.
*
* Notes:
* Slow ring logging will be disabled while while this routine dumps the log.
*
* Return Value:
* This routine returns the amount of bytes that were dumped into @buf and will
* not exceed @size.
**/
static int
lpfc_debugfs_slow_ring_trc_data(struct lpfc_hba *phba, char *buf, int size)
{
int i, index, len, enable;
uint32_t ms;
struct lpfc_debugfs_trc *dtp;
char *buffer;
buffer = kmalloc(LPFC_DEBUG_TRC_ENTRY_SIZE, GFP_KERNEL);
if (!buffer)
return 0;
enable = lpfc_debugfs_enable;
lpfc_debugfs_enable = 0;
len = 0;
index = (atomic_read(&phba->slow_ring_trc_cnt) + 1) &
(lpfc_debugfs_max_slow_ring_trc - 1);
for (i = index; i < lpfc_debugfs_max_slow_ring_trc; i++) {
dtp = phba->slow_ring_trc + i;
if (!dtp->fmt)
continue;
ms = jiffies_to_msecs(dtp->jif - lpfc_debugfs_start_time);
snprintf(buffer,
LPFC_DEBUG_TRC_ENTRY_SIZE, "%010d:%010d ms:%s\n",
dtp->seq_cnt, ms, dtp->fmt);
len += snprintf(buf+len, size-len, buffer,
dtp->data1, dtp->data2, dtp->data3);
}
for (i = 0; i < index; i++) {
dtp = phba->slow_ring_trc + i;
if (!dtp->fmt)
continue;
ms = jiffies_to_msecs(dtp->jif - lpfc_debugfs_start_time);
snprintf(buffer,
LPFC_DEBUG_TRC_ENTRY_SIZE, "%010d:%010d ms:%s\n",
dtp->seq_cnt, ms, dtp->fmt);
len += snprintf(buf+len, size-len, buffer,
dtp->data1, dtp->data2, dtp->data3);
}
lpfc_debugfs_enable = enable;
kfree(buffer);
return len;
}
static int lpfc_debugfs_last_hbq = -1;
/**
* lpfc_debugfs_hbqinfo_data - Dump host buffer queue info to a buffer
* @phba: The HBA to gather host buffer info from.
* @buf: The buffer to dump log into.
* @size: The maximum amount of data to process.
*
* Description:
* This routine dumps the host buffer queue info from the @phba to @buf up to
* @size number of bytes. A header that describes the current hbq state will be
* dumped to @buf first and then info on each hbq entry will be dumped to @buf
* until @size bytes have been dumped or all the hbq info has been dumped.
*
* Notes:
* This routine will rotate through each configured HBQ each time called.
*
* Return Value:
* This routine returns the amount of bytes that were dumped into @buf and will
* not exceed @size.
**/
static int
lpfc_debugfs_hbqinfo_data(struct lpfc_hba *phba, char *buf, int size)
{
int len = 0;
int cnt, i, j, found, posted, low;
uint32_t phys, raw_index, getidx;
struct lpfc_hbq_init *hip;
struct hbq_s *hbqs;
struct lpfc_hbq_entry *hbqe;
struct lpfc_dmabuf *d_buf;
struct hbq_dmabuf *hbq_buf;
if (phba->sli_rev != 3)
return 0;
cnt = LPFC_HBQINFO_SIZE;
spin_lock_irq(&phba->hbalock);
/* toggle between multiple hbqs, if any */
i = lpfc_sli_hbq_count();
if (i > 1) {
lpfc_debugfs_last_hbq++;
if (lpfc_debugfs_last_hbq >= i)
lpfc_debugfs_last_hbq = 0;
}
else
lpfc_debugfs_last_hbq = 0;
i = lpfc_debugfs_last_hbq;
len += snprintf(buf+len, size-len, "HBQ %d Info\n", i);
hbqs = &phba->hbqs[i];
posted = 0;
list_for_each_entry(d_buf, &hbqs->hbq_buffer_list, list)
posted++;
hip = lpfc_hbq_defs[i];
len += snprintf(buf+len, size-len,
"idx:%d prof:%d rn:%d bufcnt:%d icnt:%d acnt:%d posted %d\n",
hip->hbq_index, hip->profile, hip->rn,
hip->buffer_count, hip->init_count, hip->add_count, posted);
raw_index = phba->hbq_get[i];
getidx = le32_to_cpu(raw_index);
len += snprintf(buf+len, size-len,
"entrys:%d bufcnt:%d Put:%d nPut:%d localGet:%d hbaGet:%d\n",
hbqs->entry_count, hbqs->buffer_count, hbqs->hbqPutIdx,
hbqs->next_hbqPutIdx, hbqs->local_hbqGetIdx, getidx);
hbqe = (struct lpfc_hbq_entry *) phba->hbqs[i].hbq_virt;
for (j=0; j<hbqs->entry_count; j++) {
len += snprintf(buf+len, size-len,
"%03d: %08x %04x %05x ", j,
le32_to_cpu(hbqe->bde.addrLow),
le32_to_cpu(hbqe->bde.tus.w),
le32_to_cpu(hbqe->buffer_tag));
i = 0;
found = 0;
/* First calculate if slot has an associated posted buffer */
low = hbqs->hbqPutIdx - posted;
if (low >= 0) {
if ((j >= hbqs->hbqPutIdx) || (j < low)) {
len += snprintf(buf+len, size-len, "Unused\n");
goto skipit;
}
}
else {
if ((j >= hbqs->hbqPutIdx) &&
(j < (hbqs->entry_count+low))) {
len += snprintf(buf+len, size-len, "Unused\n");
goto skipit;
}
}
/* Get the Buffer info for the posted buffer */
list_for_each_entry(d_buf, &hbqs->hbq_buffer_list, list) {
hbq_buf = container_of(d_buf, struct hbq_dmabuf, dbuf);
phys = ((uint64_t)hbq_buf->dbuf.phys & 0xffffffff);
if (phys == le32_to_cpu(hbqe->bde.addrLow)) {
len += snprintf(buf+len, size-len,
"Buf%d: %p %06x\n", i,
hbq_buf->dbuf.virt, hbq_buf->tag);
found = 1;
break;
}
i++;
}
if (!found) {
len += snprintf(buf+len, size-len, "No DMAinfo?\n");
}
skipit:
hbqe++;
if (len > LPFC_HBQINFO_SIZE - 54)
break;
}
spin_unlock_irq(&phba->hbalock);
return len;
}
static int lpfc_debugfs_last_hba_slim_off;
/**
* lpfc_debugfs_dumpHBASlim_data - Dump HBA SLIM info to a buffer
* @phba: The HBA to gather SLIM info from.
* @buf: The buffer to dump log into.
* @size: The maximum amount of data to process.
*
* Description:
* This routine dumps the current contents of HBA SLIM for the HBA associated
* with @phba to @buf up to @size bytes of data. This is the raw HBA SLIM data.
*
* Notes:
* This routine will only dump up to 1024 bytes of data each time called and
* should be called multiple times to dump the entire HBA SLIM.
*
* Return Value:
* This routine returns the amount of bytes that were dumped into @buf and will
* not exceed @size.
**/
static int
lpfc_debugfs_dumpHBASlim_data(struct lpfc_hba *phba, char *buf, int size)
{
int len = 0;
int i, off;
uint32_t *ptr;
char *buffer;
buffer = kmalloc(1024, GFP_KERNEL);
if (!buffer)
return 0;
off = 0;
spin_lock_irq(&phba->hbalock);
len += snprintf(buf+len, size-len, "HBA SLIM\n");
lpfc_memcpy_from_slim(buffer,
phba->MBslimaddr + lpfc_debugfs_last_hba_slim_off, 1024);
ptr = (uint32_t *)&buffer[0];
off = lpfc_debugfs_last_hba_slim_off;
/* Set it up for the next time */
lpfc_debugfs_last_hba_slim_off += 1024;
if (lpfc_debugfs_last_hba_slim_off >= 4096)
lpfc_debugfs_last_hba_slim_off = 0;
i = 1024;
while (i > 0) {
len += snprintf(buf+len, size-len,
"%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
off, *ptr, *(ptr+1), *(ptr+2), *(ptr+3), *(ptr+4),
*(ptr+5), *(ptr+6), *(ptr+7));
ptr += 8;
i -= (8 * sizeof(uint32_t));
off += (8 * sizeof(uint32_t));
}
spin_unlock_irq(&phba->hbalock);
kfree(buffer);
return len;
}
/**
* lpfc_debugfs_dumpHostSlim_data - Dump host SLIM info to a buffer
* @phba: The HBA to gather Host SLIM info from.
* @buf: The buffer to dump log into.
* @size: The maximum amount of data to process.
*
* Description:
* This routine dumps the current contents of host SLIM for the host associated
* with @phba to @buf up to @size bytes of data. The dump will contain the
* Mailbox, PCB, Rings, and Registers that are located in host memory.
*
* Return Value:
* This routine returns the amount of bytes that were dumped into @buf and will
* not exceed @size.
**/
static int
lpfc_debugfs_dumpHostSlim_data(struct lpfc_hba *phba, char *buf, int size)
{
int len = 0;
int i, off;
uint32_t word0, word1, word2, word3;
uint32_t *ptr;
struct lpfc_pgp *pgpp;
struct lpfc_sli *psli = &phba->sli;
struct lpfc_sli_ring *pring;
off = 0;
spin_lock_irq(&phba->hbalock);
len += snprintf(buf+len, size-len, "SLIM Mailbox\n");
ptr = (uint32_t *)phba->slim2p.virt;
i = sizeof(MAILBOX_t);
while (i > 0) {
len += snprintf(buf+len, size-len,
"%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
off, *ptr, *(ptr+1), *(ptr+2), *(ptr+3), *(ptr+4),
*(ptr+5), *(ptr+6), *(ptr+7));
ptr += 8;
i -= (8 * sizeof(uint32_t));
off += (8 * sizeof(uint32_t));
}
len += snprintf(buf+len, size-len, "SLIM PCB\n");
ptr = (uint32_t *)phba->pcb;
i = sizeof(PCB_t);
while (i > 0) {
len += snprintf(buf+len, size-len,
"%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
off, *ptr, *(ptr+1), *(ptr+2), *(ptr+3), *(ptr+4),
*(ptr+5), *(ptr+6), *(ptr+7));
ptr += 8;
i -= (8 * sizeof(uint32_t));
off += (8 * sizeof(uint32_t));
}
for (i = 0; i < 4; i++) {
pgpp = &phba->port_gp[i];
pring = &psli->ring[i];
len += snprintf(buf+len, size-len,
"Ring %d: CMD GetInx:%d (Max:%d Next:%d "
"Local:%d flg:x%x) RSP PutInx:%d Max:%d\n",
i, pgpp->cmdGetInx, pring->sli.sli3.numCiocb,
pring->sli.sli3.next_cmdidx,
pring->sli.sli3.local_getidx,
pring->flag, pgpp->rspPutInx,
pring->sli.sli3.numRiocb);
}
if (phba->sli_rev <= LPFC_SLI_REV3) {
word0 = readl(phba->HAregaddr);
word1 = readl(phba->CAregaddr);
word2 = readl(phba->HSregaddr);
word3 = readl(phba->HCregaddr);
len += snprintf(buf+len, size-len, "HA:%08x CA:%08x HS:%08x "
"HC:%08x\n", word0, word1, word2, word3);
}
spin_unlock_irq(&phba->hbalock);
return len;
}
/**
* lpfc_debugfs_nodelist_data - Dump target node list to a buffer
* @vport: The vport to gather target node info from.
* @buf: The buffer to dump log into.
* @size: The maximum amount of data to process.
*
* Description:
* This routine dumps the current target node list associated with @vport to
* @buf up to @size bytes of data. Each node entry in the dump will contain a
* node state, DID, WWPN, WWNN, RPI, flags, type, and other useful fields.
*
* Return Value:
* This routine returns the amount of bytes that were dumped into @buf and will
* not exceed @size.
**/
static int
lpfc_debugfs_nodelist_data(struct lpfc_vport *vport, char *buf, int size)
{
int len = 0;
int cnt;
struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
struct lpfc_nodelist *ndlp;
unsigned char *statep, *name;
cnt = (LPFC_NODELIST_SIZE / LPFC_NODELIST_ENTRY_SIZE);
spin_lock_irq(shost->host_lock);
list_for_each_entry(ndlp, &vport->fc_nodes, nlp_listp) {
if (!cnt) {
len += snprintf(buf+len, size-len,
"Missing Nodelist Entries\n");
break;
}
cnt--;
switch (ndlp->nlp_state) {
case NLP_STE_UNUSED_NODE:
statep = "UNUSED";
break;
case NLP_STE_PLOGI_ISSUE:
statep = "PLOGI ";
break;
case NLP_STE_ADISC_ISSUE:
statep = "ADISC ";
break;
case NLP_STE_REG_LOGIN_ISSUE:
statep = "REGLOG";
break;
case NLP_STE_PRLI_ISSUE:
statep = "PRLI ";
break;
case NLP_STE_LOGO_ISSUE:
statep = "LOGO ";
break;
case NLP_STE_UNMAPPED_NODE:
statep = "UNMAP ";
break;
case NLP_STE_MAPPED_NODE:
statep = "MAPPED";
break;
case NLP_STE_NPR_NODE:
statep = "NPR ";
break;
default:
statep = "UNKNOWN";
}
len += snprintf(buf+len, size-len, "%s DID:x%06x ",
statep, ndlp->nlp_DID);
name = (unsigned char *)&ndlp->nlp_portname;
len += snprintf(buf+len, size-len,
"WWPN %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x ",
*name, *(name+1), *(name+2), *(name+3),
*(name+4), *(name+5), *(name+6), *(name+7));
name = (unsigned char *)&ndlp->nlp_nodename;
len += snprintf(buf+len, size-len,
"WWNN %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x ",
*name, *(name+1), *(name+2), *(name+3),
*(name+4), *(name+5), *(name+6), *(name+7));
if (ndlp->nlp_flag & NLP_RPI_REGISTERED)
len += snprintf(buf+len, size-len, "RPI:%03d ",
ndlp->nlp_rpi);
else
len += snprintf(buf+len, size-len, "RPI:none ");
len += snprintf(buf+len, size-len, "flag:x%08x ",
ndlp->nlp_flag);
if (!ndlp->nlp_type)
len += snprintf(buf+len, size-len, "UNKNOWN_TYPE ");
if (ndlp->nlp_type & NLP_FC_NODE)
len += snprintf(buf+len, size-len, "FC_NODE ");
if (ndlp->nlp_type & NLP_FABRIC)
len += snprintf(buf+len, size-len, "FABRIC ");
if (ndlp->nlp_type & NLP_FCP_TARGET)
len += snprintf(buf+len, size-len, "FCP_TGT sid:%d ",
ndlp->nlp_sid);
if (ndlp->nlp_type & NLP_FCP_INITIATOR)
len += snprintf(buf+len, size-len, "FCP_INITIATOR ");
len += snprintf(buf+len, size-len, "usgmap:%x ",
ndlp->nlp_usg_map);
len += snprintf(buf+len, size-len, "refcnt:%x",
atomic_read(&ndlp->kref.refcount));
len += snprintf(buf+len, size-len, "\n");
}
spin_unlock_irq(shost->host_lock);
return len;
}
#endif
/**
* lpfc_debugfs_disc_trc - Store discovery trace log
* @vport: The vport to associate this trace string with for retrieval.
* @mask: Log entry classification.
* @fmt: Format string to be displayed when dumping the log.
* @data1: 1st data parameter to be applied to @fmt.
* @data2: 2nd data parameter to be applied to @fmt.
* @data3: 3rd data parameter to be applied to @fmt.
*
* Description:
* This routine is used by the driver code to add a debugfs log entry to the
* discovery trace buffer associated with @vport. Only entries with a @mask that
* match the current debugfs discovery mask will be saved. Entries that do not
* match will be thrown away. @fmt, @data1, @data2, and @data3 are used like
* printf when displaying the log.
**/
inline void
lpfc_debugfs_disc_trc(struct lpfc_vport *vport, int mask, char *fmt,
uint32_t data1, uint32_t data2, uint32_t data3)
{
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
struct lpfc_debugfs_trc *dtp;
int index;
if (!(lpfc_debugfs_mask_disc_trc & mask))
return;
if (!lpfc_debugfs_enable || !lpfc_debugfs_max_disc_trc ||
!vport || !vport->disc_trc)
return;
index = atomic_inc_return(&vport->disc_trc_cnt) &
(lpfc_debugfs_max_disc_trc - 1);
dtp = vport->disc_trc + index;
dtp->fmt = fmt;
dtp->data1 = data1;
dtp->data2 = data2;
dtp->data3 = data3;
dtp->seq_cnt = atomic_inc_return(&lpfc_debugfs_seq_trc_cnt);
dtp->jif = jiffies;
#endif
return;
}
/**
* lpfc_debugfs_slow_ring_trc - Store slow ring trace log
* @phba: The phba to associate this trace string with for retrieval.
* @fmt: Format string to be displayed when dumping the log.
* @data1: 1st data parameter to be applied to @fmt.
* @data2: 2nd data parameter to be applied to @fmt.
* @data3: 3rd data parameter to be applied to @fmt.
*
* Description:
* This routine is used by the driver code to add a debugfs log entry to the
* discovery trace buffer associated with @vport. @fmt, @data1, @data2, and
* @data3 are used like printf when displaying the log.
**/
inline void
lpfc_debugfs_slow_ring_trc(struct lpfc_hba *phba, char *fmt,
uint32_t data1, uint32_t data2, uint32_t data3)
{
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
struct lpfc_debugfs_trc *dtp;
int index;
if (!lpfc_debugfs_enable || !lpfc_debugfs_max_slow_ring_trc ||
!phba || !phba->slow_ring_trc)
return;
index = atomic_inc_return(&phba->slow_ring_trc_cnt) &
(lpfc_debugfs_max_slow_ring_trc - 1);
dtp = phba->slow_ring_trc + index;
dtp->fmt = fmt;
dtp->data1 = data1;
dtp->data2 = data2;
dtp->data3 = data3;
dtp->seq_cnt = atomic_inc_return(&lpfc_debugfs_seq_trc_cnt);
dtp->jif = jiffies;
#endif
return;
}
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
/**
* lpfc_debugfs_disc_trc_open - Open the discovery trace log
* @inode: The inode pointer that contains a vport pointer.
* @file: The file pointer to attach the log output.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It gets
* the vport from the i_private field in @inode, allocates the necessary buffer
* for the log, fills the buffer from the in-memory log for this vport, and then
* returns a pointer to that log in the private_data field in @file.
*
* Returns:
* This function returns zero if successful. On error it will return an negative
* error value.
**/
static int
lpfc_debugfs_disc_trc_open(struct inode *inode, struct file *file)
{
struct lpfc_vport *vport = inode->i_private;
struct lpfc_debug *debug;
int size;
int rc = -ENOMEM;
if (!lpfc_debugfs_max_disc_trc) {
rc = -ENOSPC;
goto out;
}
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
size = (lpfc_debugfs_max_disc_trc * LPFC_DEBUG_TRC_ENTRY_SIZE);
size = PAGE_ALIGN(size);
debug->buffer = kmalloc(size, GFP_KERNEL);
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = lpfc_debugfs_disc_trc_data(vport, debug->buffer, size);
file->private_data = debug;
rc = 0;
out:
return rc;
}
/**
* lpfc_debugfs_slow_ring_trc_open - Open the Slow Ring trace log
* @inode: The inode pointer that contains a vport pointer.
* @file: The file pointer to attach the log output.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It gets
* the vport from the i_private field in @inode, allocates the necessary buffer
* for the log, fills the buffer from the in-memory log for this vport, and then
* returns a pointer to that log in the private_data field in @file.
*
* Returns:
* This function returns zero if successful. On error it will return an negative
* error value.
**/
static int
lpfc_debugfs_slow_ring_trc_open(struct inode *inode, struct file *file)
{
struct lpfc_hba *phba = inode->i_private;
struct lpfc_debug *debug;
int size;
int rc = -ENOMEM;
if (!lpfc_debugfs_max_slow_ring_trc) {
rc = -ENOSPC;
goto out;
}
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
size = (lpfc_debugfs_max_slow_ring_trc * LPFC_DEBUG_TRC_ENTRY_SIZE);
size = PAGE_ALIGN(size);
debug->buffer = kmalloc(size, GFP_KERNEL);
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = lpfc_debugfs_slow_ring_trc_data(phba, debug->buffer, size);
file->private_data = debug;
rc = 0;
out:
return rc;
}
/**
* lpfc_debugfs_hbqinfo_open - Open the hbqinfo debugfs buffer
* @inode: The inode pointer that contains a vport pointer.
* @file: The file pointer to attach the log output.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It gets
* the vport from the i_private field in @inode, allocates the necessary buffer
* for the log, fills the buffer from the in-memory log for this vport, and then
* returns a pointer to that log in the private_data field in @file.
*
* Returns:
* This function returns zero if successful. On error it will return an negative
* error value.
**/
static int
lpfc_debugfs_hbqinfo_open(struct inode *inode, struct file *file)
{
struct lpfc_hba *phba = inode->i_private;
struct lpfc_debug *debug;
int rc = -ENOMEM;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
debug->buffer = kmalloc(LPFC_HBQINFO_SIZE, GFP_KERNEL);
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = lpfc_debugfs_hbqinfo_data(phba, debug->buffer,
LPFC_HBQINFO_SIZE);
file->private_data = debug;
rc = 0;
out:
return rc;
}
/**
* lpfc_debugfs_dumpHBASlim_open - Open the Dump HBA SLIM debugfs buffer
* @inode: The inode pointer that contains a vport pointer.
* @file: The file pointer to attach the log output.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It gets
* the vport from the i_private field in @inode, allocates the necessary buffer
* for the log, fills the buffer from the in-memory log for this vport, and then
* returns a pointer to that log in the private_data field in @file.
*
* Returns:
* This function returns zero if successful. On error it will return an negative
* error value.
**/
static int
lpfc_debugfs_dumpHBASlim_open(struct inode *inode, struct file *file)
{
struct lpfc_hba *phba = inode->i_private;
struct lpfc_debug *debug;
int rc = -ENOMEM;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
debug->buffer = kmalloc(LPFC_DUMPHBASLIM_SIZE, GFP_KERNEL);
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = lpfc_debugfs_dumpHBASlim_data(phba, debug->buffer,
LPFC_DUMPHBASLIM_SIZE);
file->private_data = debug;
rc = 0;
out:
return rc;
}
/**
* lpfc_debugfs_dumpHostSlim_open - Open the Dump Host SLIM debugfs buffer
* @inode: The inode pointer that contains a vport pointer.
* @file: The file pointer to attach the log output.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It gets
* the vport from the i_private field in @inode, allocates the necessary buffer
* for the log, fills the buffer from the in-memory log for this vport, and then
* returns a pointer to that log in the private_data field in @file.
*
* Returns:
* This function returns zero if successful. On error it will return an negative
* error value.
**/
static int
lpfc_debugfs_dumpHostSlim_open(struct inode *inode, struct file *file)
{
struct lpfc_hba *phba = inode->i_private;
struct lpfc_debug *debug;
int rc = -ENOMEM;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
debug->buffer = kmalloc(LPFC_DUMPHOSTSLIM_SIZE, GFP_KERNEL);
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = lpfc_debugfs_dumpHostSlim_data(phba, debug->buffer,
LPFC_DUMPHOSTSLIM_SIZE);
file->private_data = debug;
rc = 0;
out:
return rc;
}
static int
lpfc_debugfs_dumpData_open(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug;
int rc = -ENOMEM;
if (!_dump_buf_data)
return -EBUSY;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
printk(KERN_ERR "9059 BLKGRD: %s: _dump_buf_data=0x%p\n",
__func__, _dump_buf_data);
debug->buffer = _dump_buf_data;
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = (1 << _dump_buf_data_order) << PAGE_SHIFT;
file->private_data = debug;
rc = 0;
out:
return rc;
}
static int
lpfc_debugfs_dumpDif_open(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug;
int rc = -ENOMEM;
if (!_dump_buf_dif)
return -EBUSY;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
printk(KERN_ERR "9060 BLKGRD: %s: _dump_buf_dif=0x%p file=%s\n",
__func__, _dump_buf_dif, file->f_dentry->d_name.name);
debug->buffer = _dump_buf_dif;
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = (1 << _dump_buf_dif_order) << PAGE_SHIFT;
file->private_data = debug;
rc = 0;
out:
return rc;
}
static ssize_t
lpfc_debugfs_dumpDataDif_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
/*
* The Data/DIF buffers only save one failing IO
* The write op is used as a reset mechanism after an IO has
* already been saved to the next one can be saved
*/
spin_lock(&_dump_buf_lock);
memset((void *)_dump_buf_data, 0,
((1 << PAGE_SHIFT) << _dump_buf_data_order));
memset((void *)_dump_buf_dif, 0,
((1 << PAGE_SHIFT) << _dump_buf_dif_order));
_dump_buf_done = 0;
spin_unlock(&_dump_buf_lock);
return nbytes;
}
static ssize_t
lpfc_debugfs_dif_err_read(struct file *file, char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct dentry *dent = file->f_dentry;
struct lpfc_hba *phba = file->private_data;
char cbuf[32];
uint64_t tmp = 0;
int cnt = 0;
if (dent == phba->debug_writeGuard)
cnt = snprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_wgrd_cnt);
else if (dent == phba->debug_writeApp)
cnt = snprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_wapp_cnt);
else if (dent == phba->debug_writeRef)
cnt = snprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_wref_cnt);
else if (dent == phba->debug_readGuard)
cnt = snprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_rgrd_cnt);
else if (dent == phba->debug_readApp)
cnt = snprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_rapp_cnt);
else if (dent == phba->debug_readRef)
cnt = snprintf(cbuf, 32, "%u\n", phba->lpfc_injerr_rref_cnt);
else if (dent == phba->debug_InjErrNPortID)
cnt = snprintf(cbuf, 32, "0x%06x\n", phba->lpfc_injerr_nportid);
else if (dent == phba->debug_InjErrWWPN) {
memcpy(&tmp, &phba->lpfc_injerr_wwpn, sizeof(struct lpfc_name));
tmp = cpu_to_be64(tmp);
cnt = snprintf(cbuf, 32, "0x%016llx\n", tmp);
} else if (dent == phba->debug_InjErrLBA) {
if (phba->lpfc_injerr_lba == (sector_t)(-1))
cnt = snprintf(cbuf, 32, "off\n");
else
cnt = snprintf(cbuf, 32, "0x%llx\n",
(uint64_t) phba->lpfc_injerr_lba);
} else
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"0547 Unknown debugfs error injection entry\n");
return simple_read_from_buffer(buf, nbytes, ppos, &cbuf, cnt);
}
static ssize_t
lpfc_debugfs_dif_err_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct dentry *dent = file->f_dentry;
struct lpfc_hba *phba = file->private_data;
char dstbuf[32];
uint64_t tmp = 0;
int size;
memset(dstbuf, 0, 32);
size = (nbytes < 32) ? nbytes : 32;
if (copy_from_user(dstbuf, buf, size))
return 0;
if (dent == phba->debug_InjErrLBA) {
if ((buf[0] == 'o') && (buf[1] == 'f') && (buf[2] == 'f'))
tmp = (uint64_t)(-1);
}
if ((tmp == 0) && (kstrtoull(dstbuf, 0, &tmp)))
return 0;
if (dent == phba->debug_writeGuard)
phba->lpfc_injerr_wgrd_cnt = (uint32_t)tmp;
else if (dent == phba->debug_writeApp)
phba->lpfc_injerr_wapp_cnt = (uint32_t)tmp;
else if (dent == phba->debug_writeRef)
phba->lpfc_injerr_wref_cnt = (uint32_t)tmp;
else if (dent == phba->debug_readGuard)
phba->lpfc_injerr_rgrd_cnt = (uint32_t)tmp;
else if (dent == phba->debug_readApp)
phba->lpfc_injerr_rapp_cnt = (uint32_t)tmp;
else if (dent == phba->debug_readRef)
phba->lpfc_injerr_rref_cnt = (uint32_t)tmp;
else if (dent == phba->debug_InjErrLBA)
phba->lpfc_injerr_lba = (sector_t)tmp;
else if (dent == phba->debug_InjErrNPortID)
phba->lpfc_injerr_nportid = (uint32_t)(tmp & Mask_DID);
else if (dent == phba->debug_InjErrWWPN) {
tmp = cpu_to_be64(tmp);
memcpy(&phba->lpfc_injerr_wwpn, &tmp, sizeof(struct lpfc_name));
} else
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"0548 Unknown debugfs error injection entry\n");
return nbytes;
}
static int
lpfc_debugfs_dif_err_release(struct inode *inode, struct file *file)
{
return 0;
}
/**
* lpfc_debugfs_nodelist_open - Open the nodelist debugfs file
* @inode: The inode pointer that contains a vport pointer.
* @file: The file pointer to attach the log output.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It gets
* the vport from the i_private field in @inode, allocates the necessary buffer
* for the log, fills the buffer from the in-memory log for this vport, and then
* returns a pointer to that log in the private_data field in @file.
*
* Returns:
* This function returns zero if successful. On error it will return an negative
* error value.
**/
static int
lpfc_debugfs_nodelist_open(struct inode *inode, struct file *file)
{
struct lpfc_vport *vport = inode->i_private;
struct lpfc_debug *debug;
int rc = -ENOMEM;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
goto out;
/* Round to page boundary */
debug->buffer = kmalloc(LPFC_NODELIST_SIZE, GFP_KERNEL);
if (!debug->buffer) {
kfree(debug);
goto out;
}
debug->len = lpfc_debugfs_nodelist_data(vport, debug->buffer,
LPFC_NODELIST_SIZE);
file->private_data = debug;
rc = 0;
out:
return rc;
}
/**
* lpfc_debugfs_lseek - Seek through a debugfs file
* @file: The file pointer to seek through.
* @off: The offset to seek to or the amount to seek by.
* @whence: Indicates how to seek.
*
* Description:
* This routine is the entry point for the debugfs lseek file operation. The
* @whence parameter indicates whether @off is the offset to directly seek to,
* or if it is a value to seek forward or reverse by. This function figures out
* what the new offset of the debugfs file will be and assigns that value to the
* f_pos field of @file.
*
* Returns:
* This function returns the new offset if successful and returns a negative
* error if unable to process the seek.
**/
static loff_t
lpfc_debugfs_lseek(struct file *file, loff_t off, int whence)
{
struct lpfc_debug *debug = file->private_data;
return fixed_size_llseek(file, off, whence, debug->len);
}
/**
* lpfc_debugfs_read - Read a debugfs file
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from from the buffer indicated in the private_data
* field of @file. It will start reading at @ppos and copy up to @nbytes of
* data to @buf.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_debugfs_read(struct file *file, char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
return simple_read_from_buffer(buf, nbytes, ppos, debug->buffer,
debug->len);
}
/**
* lpfc_debugfs_release - Release the buffer used to store debugfs file data
* @inode: The inode pointer that contains a vport pointer. (unused)
* @file: The file pointer that contains the buffer to release.
*
* Description:
* This routine frees the buffer that was allocated when the debugfs file was
* opened.
*
* Returns:
* This function returns zero.
**/
static int
lpfc_debugfs_release(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug = file->private_data;
kfree(debug->buffer);
kfree(debug);
return 0;
}
static int
lpfc_debugfs_dumpDataDif_release(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug = file->private_data;
debug->buffer = NULL;
kfree(debug);
return 0;
}
/*
* ---------------------------------
* iDiag debugfs file access methods
* ---------------------------------
*
* All access methods are through the proper SLI4 PCI function's debugfs
* iDiag directory:
*
* /sys/kernel/debug/lpfc/fn<#>/iDiag
*/
/**
* lpfc_idiag_cmd_get - Get and parse idiag debugfs comands from user space
* @buf: The pointer to the user space buffer.
* @nbytes: The number of bytes in the user space buffer.
* @idiag_cmd: pointer to the idiag command struct.
*
* This routine reads data from debugfs user space buffer and parses the
* buffer for getting the idiag command and arguments. The while space in
* between the set of data is used as the parsing separator.
*
* This routine returns 0 when successful, it returns proper error code
* back to the user space in error conditions.
*/
static int lpfc_idiag_cmd_get(const char __user *buf, size_t nbytes,
struct lpfc_idiag_cmd *idiag_cmd)
{
char mybuf[64];
char *pbuf, *step_str;
int i;
size_t bsize;
/* Protect copy from user */
if (!access_ok(VERIFY_READ, buf, nbytes))
return -EFAULT;
memset(mybuf, 0, sizeof(mybuf));
memset(idiag_cmd, 0, sizeof(*idiag_cmd));
bsize = min(nbytes, (sizeof(mybuf)-1));
if (copy_from_user(mybuf, buf, bsize))
return -EFAULT;
pbuf = &mybuf[0];
step_str = strsep(&pbuf, "\t ");
/* The opcode must present */
if (!step_str)
return -EINVAL;
idiag_cmd->opcode = simple_strtol(step_str, NULL, 0);
if (idiag_cmd->opcode == 0)
return -EINVAL;
for (i = 0; i < LPFC_IDIAG_CMD_DATA_SIZE; i++) {
step_str = strsep(&pbuf, "\t ");
if (!step_str)
return i;
idiag_cmd->data[i] = simple_strtol(step_str, NULL, 0);
}
return i;
}
/**
* lpfc_idiag_open - idiag open debugfs
* @inode: The inode pointer that contains a pointer to phba.
* @file: The file pointer to attach the file operation.
*
* Description:
* This routine is the entry point for the debugfs open file operation. It
* gets the reference to phba from the i_private field in @inode, it then
* allocates buffer for the file operation, performs the necessary PCI config
* space read into the allocated buffer according to the idiag user command
* setup, and then returns a pointer to buffer in the private_data field in
* @file.
*
* Returns:
* This function returns zero if successful. On error it will return an
* negative error value.
**/
static int
lpfc_idiag_open(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug;
debug = kmalloc(sizeof(*debug), GFP_KERNEL);
if (!debug)
return -ENOMEM;
debug->i_private = inode->i_private;
debug->buffer = NULL;
file->private_data = debug;
return 0;
}
/**
* lpfc_idiag_release - Release idiag access file operation
* @inode: The inode pointer that contains a vport pointer. (unused)
* @file: The file pointer that contains the buffer to release.
*
* Description:
* This routine is the generic release routine for the idiag access file
* operation, it frees the buffer that was allocated when the debugfs file
* was opened.
*
* Returns:
* This function returns zero.
**/
static int
lpfc_idiag_release(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug = file->private_data;
/* Free the buffers to the file operation */
kfree(debug->buffer);
kfree(debug);
return 0;
}
/**
* lpfc_idiag_cmd_release - Release idiag cmd access file operation
* @inode: The inode pointer that contains a vport pointer. (unused)
* @file: The file pointer that contains the buffer to release.
*
* Description:
* This routine frees the buffer that was allocated when the debugfs file
* was opened. It also reset the fields in the idiag command struct in the
* case of command for write operation.
*
* Returns:
* This function returns zero.
**/
static int
lpfc_idiag_cmd_release(struct inode *inode, struct file *file)
{
struct lpfc_debug *debug = file->private_data;
if (debug->op == LPFC_IDIAG_OP_WR) {
switch (idiag.cmd.opcode) {
case LPFC_IDIAG_CMD_PCICFG_WR:
case LPFC_IDIAG_CMD_PCICFG_ST:
case LPFC_IDIAG_CMD_PCICFG_CL:
case LPFC_IDIAG_CMD_QUEACC_WR:
case LPFC_IDIAG_CMD_QUEACC_ST:
case LPFC_IDIAG_CMD_QUEACC_CL:
memset(&idiag, 0, sizeof(idiag));
break;
default:
break;
}
}
/* Free the buffers to the file operation */
kfree(debug->buffer);
kfree(debug);
return 0;
}
/**
* lpfc_idiag_pcicfg_read - idiag debugfs read pcicfg
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba pci config space according to the
* idiag command, and copies to user @buf. Depending on the PCI config space
* read command setup, it does either a single register read of a byte
* (8 bits), a word (16 bits), or a dword (32 bits) or browsing through all
* registers from the 4K extended PCI config space.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_pcicfg_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
int offset_label, offset, len = 0, index = LPFC_PCI_CFG_RD_SIZE;
int where, count;
char *pbuffer;
struct pci_dev *pdev;
uint32_t u32val;
uint16_t u16val;
uint8_t u8val;
pdev = phba->pcidev;
if (!pdev)
return 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_PCI_CFG_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_RD) {
where = idiag.cmd.data[IDIAG_PCICFG_WHERE_INDX];
count = idiag.cmd.data[IDIAG_PCICFG_COUNT_INDX];
} else
return 0;
/* Read single PCI config space register */
switch (count) {
case SIZE_U8: /* byte (8 bits) */
pci_read_config_byte(pdev, where, &u8val);
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"%03x: %02x\n", where, u8val);
break;
case SIZE_U16: /* word (16 bits) */
pci_read_config_word(pdev, where, &u16val);
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"%03x: %04x\n", where, u16val);
break;
case SIZE_U32: /* double word (32 bits) */
pci_read_config_dword(pdev, where, &u32val);
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"%03x: %08x\n", where, u32val);
break;
case LPFC_PCI_CFG_BROWSE: /* browse all */
goto pcicfg_browse;
break;
default:
/* illegal count */
len = 0;
break;
}
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
pcicfg_browse:
/* Browse all PCI config space registers */
offset_label = idiag.offset.last_rd;
offset = offset_label;
/* Read PCI config space */
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"%03x: ", offset_label);
while (index > 0) {
pci_read_config_dword(pdev, offset, &u32val);
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"%08x ", u32val);
offset += sizeof(uint32_t);
if (offset >= LPFC_PCI_CFG_SIZE) {
len += snprintf(pbuffer+len,
LPFC_PCI_CFG_SIZE-len, "\n");
break;
}
index -= sizeof(uint32_t);
if (!index)
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"\n");
else if (!(index % (8 * sizeof(uint32_t)))) {
offset_label += (8 * sizeof(uint32_t));
len += snprintf(pbuffer+len, LPFC_PCI_CFG_SIZE-len,
"\n%03x: ", offset_label);
}
}
/* Set up the offset for next portion of pci cfg read */
if (index == 0) {
idiag.offset.last_rd += LPFC_PCI_CFG_RD_SIZE;
if (idiag.offset.last_rd >= LPFC_PCI_CFG_SIZE)
idiag.offset.last_rd = 0;
} else
idiag.offset.last_rd = 0;
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_pcicfg_write - Syntax check and set up idiag pcicfg commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and
* then perform the syntax check for PCI config space read or write command
* accordingly. In the case of PCI config space read command, it sets up
* the command in the idiag command struct for the debugfs read operation.
* In the case of PCI config space write operation, it executes the write
* operation into the PCI config space accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
*/
static ssize_t
lpfc_idiag_pcicfg_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t where, value, count;
uint32_t u32val;
uint16_t u16val;
uint8_t u8val;
struct pci_dev *pdev;
int rc;
pdev = phba->pcidev;
if (!pdev)
return -EFAULT;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_RD) {
/* Sanity check on PCI config read command line arguments */
if (rc != LPFC_PCI_CFG_RD_CMD_ARG)
goto error_out;
/* Read command from PCI config space, set up command fields */
where = idiag.cmd.data[IDIAG_PCICFG_WHERE_INDX];
count = idiag.cmd.data[IDIAG_PCICFG_COUNT_INDX];
if (count == LPFC_PCI_CFG_BROWSE) {
if (where % sizeof(uint32_t))
goto error_out;
/* Starting offset to browse */
idiag.offset.last_rd = where;
} else if ((count != sizeof(uint8_t)) &&
(count != sizeof(uint16_t)) &&
(count != sizeof(uint32_t)))
goto error_out;
if (count == sizeof(uint8_t)) {
if (where > LPFC_PCI_CFG_SIZE - sizeof(uint8_t))
goto error_out;
if (where % sizeof(uint8_t))
goto error_out;
}
if (count == sizeof(uint16_t)) {
if (where > LPFC_PCI_CFG_SIZE - sizeof(uint16_t))
goto error_out;
if (where % sizeof(uint16_t))
goto error_out;
}
if (count == sizeof(uint32_t)) {
if (where > LPFC_PCI_CFG_SIZE - sizeof(uint32_t))
goto error_out;
if (where % sizeof(uint32_t))
goto error_out;
}
} else if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_CL) {
/* Sanity check on PCI config write command line arguments */
if (rc != LPFC_PCI_CFG_WR_CMD_ARG)
goto error_out;
/* Write command to PCI config space, read-modify-write */
where = idiag.cmd.data[IDIAG_PCICFG_WHERE_INDX];
count = idiag.cmd.data[IDIAG_PCICFG_COUNT_INDX];
value = idiag.cmd.data[IDIAG_PCICFG_VALUE_INDX];
/* Sanity checks */
if ((count != sizeof(uint8_t)) &&
(count != sizeof(uint16_t)) &&
(count != sizeof(uint32_t)))
goto error_out;
if (count == sizeof(uint8_t)) {
if (where > LPFC_PCI_CFG_SIZE - sizeof(uint8_t))
goto error_out;
if (where % sizeof(uint8_t))
goto error_out;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_WR)
pci_write_config_byte(pdev, where,
(uint8_t)value);
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_ST) {
rc = pci_read_config_byte(pdev, where, &u8val);
if (!rc) {
u8val |= (uint8_t)value;
pci_write_config_byte(pdev, where,
u8val);
}
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_CL) {
rc = pci_read_config_byte(pdev, where, &u8val);
if (!rc) {
u8val &= (uint8_t)(~value);
pci_write_config_byte(pdev, where,
u8val);
}
}
}
if (count == sizeof(uint16_t)) {
if (where > LPFC_PCI_CFG_SIZE - sizeof(uint16_t))
goto error_out;
if (where % sizeof(uint16_t))
goto error_out;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_WR)
pci_write_config_word(pdev, where,
(uint16_t)value);
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_ST) {
rc = pci_read_config_word(pdev, where, &u16val);
if (!rc) {
u16val |= (uint16_t)value;
pci_write_config_word(pdev, where,
u16val);
}
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_CL) {
rc = pci_read_config_word(pdev, where, &u16val);
if (!rc) {
u16val &= (uint16_t)(~value);
pci_write_config_word(pdev, where,
u16val);
}
}
}
if (count == sizeof(uint32_t)) {
if (where > LPFC_PCI_CFG_SIZE - sizeof(uint32_t))
goto error_out;
if (where % sizeof(uint32_t))
goto error_out;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_WR)
pci_write_config_dword(pdev, where, value);
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_ST) {
rc = pci_read_config_dword(pdev, where,
&u32val);
if (!rc) {
u32val |= value;
pci_write_config_dword(pdev, where,
u32val);
}
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_PCICFG_CL) {
rc = pci_read_config_dword(pdev, where,
&u32val);
if (!rc) {
u32val &= ~value;
pci_write_config_dword(pdev, where,
u32val);
}
}
}
} else
/* All other opecodes are illegal for now */
goto error_out;
return nbytes;
error_out:
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_baracc_read - idiag debugfs pci bar access read
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba pci bar memory mapped space
* according to the idiag command, and copies to user @buf.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_baracc_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
int offset_label, offset, offset_run, len = 0, index;
int bar_num, acc_range, bar_size;
char *pbuffer;
void __iomem *mem_mapped_bar;
uint32_t if_type;
struct pci_dev *pdev;
uint32_t u32val;
pdev = phba->pcidev;
if (!pdev)
return 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_PCI_BAR_RD_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_RD) {
bar_num = idiag.cmd.data[IDIAG_BARACC_BAR_NUM_INDX];
offset = idiag.cmd.data[IDIAG_BARACC_OFF_SET_INDX];
acc_range = idiag.cmd.data[IDIAG_BARACC_ACC_MOD_INDX];
bar_size = idiag.cmd.data[IDIAG_BARACC_BAR_SZE_INDX];
} else
return 0;
if (acc_range == 0)
return 0;
if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
if (bar_num == IDIAG_BARACC_BAR_0)
mem_mapped_bar = phba->sli4_hba.conf_regs_memmap_p;
else if (bar_num == IDIAG_BARACC_BAR_1)
mem_mapped_bar = phba->sli4_hba.ctrl_regs_memmap_p;
else if (bar_num == IDIAG_BARACC_BAR_2)
mem_mapped_bar = phba->sli4_hba.drbl_regs_memmap_p;
else
return 0;
} else if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
if (bar_num == IDIAG_BARACC_BAR_0)
mem_mapped_bar = phba->sli4_hba.conf_regs_memmap_p;
else
return 0;
} else
return 0;
/* Read single PCI bar space register */
if (acc_range == SINGLE_WORD) {
offset_run = offset;
u32val = readl(mem_mapped_bar + offset_run);
len += snprintf(pbuffer+len, LPFC_PCI_BAR_RD_BUF_SIZE-len,
"%05x: %08x\n", offset_run, u32val);
} else
goto baracc_browse;
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
baracc_browse:
/* Browse all PCI bar space registers */
offset_label = idiag.offset.last_rd;
offset_run = offset_label;
/* Read PCI bar memory mapped space */
len += snprintf(pbuffer+len, LPFC_PCI_BAR_RD_BUF_SIZE-len,
"%05x: ", offset_label);
index = LPFC_PCI_BAR_RD_SIZE;
while (index > 0) {
u32val = readl(mem_mapped_bar + offset_run);
len += snprintf(pbuffer+len, LPFC_PCI_BAR_RD_BUF_SIZE-len,
"%08x ", u32val);
offset_run += sizeof(uint32_t);
if (acc_range == LPFC_PCI_BAR_BROWSE) {
if (offset_run >= bar_size) {
len += snprintf(pbuffer+len,
LPFC_PCI_BAR_RD_BUF_SIZE-len, "\n");
break;
}
} else {
if (offset_run >= offset +
(acc_range * sizeof(uint32_t))) {
len += snprintf(pbuffer+len,
LPFC_PCI_BAR_RD_BUF_SIZE-len, "\n");
break;
}
}
index -= sizeof(uint32_t);
if (!index)
len += snprintf(pbuffer+len,
LPFC_PCI_BAR_RD_BUF_SIZE-len, "\n");
else if (!(index % (8 * sizeof(uint32_t)))) {
offset_label += (8 * sizeof(uint32_t));
len += snprintf(pbuffer+len,
LPFC_PCI_BAR_RD_BUF_SIZE-len,
"\n%05x: ", offset_label);
}
}
/* Set up the offset for next portion of pci bar read */
if (index == 0) {
idiag.offset.last_rd += LPFC_PCI_BAR_RD_SIZE;
if (acc_range == LPFC_PCI_BAR_BROWSE) {
if (idiag.offset.last_rd >= bar_size)
idiag.offset.last_rd = 0;
} else {
if (offset_run >= offset +
(acc_range * sizeof(uint32_t)))
idiag.offset.last_rd = offset;
}
} else {
if (acc_range == LPFC_PCI_BAR_BROWSE)
idiag.offset.last_rd = 0;
else
idiag.offset.last_rd = offset;
}
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_baracc_write - Syntax check and set up idiag bar access commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and
* then perform the syntax check for PCI bar memory mapped space read or
* write command accordingly. In the case of PCI bar memory mapped space
* read command, it sets up the command in the idiag command struct for
* the debugfs read operation. In the case of PCI bar memorpy mapped space
* write operation, it executes the write operation into the PCI bar memory
* mapped space accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
*/
static ssize_t
lpfc_idiag_baracc_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t bar_num, bar_size, offset, value, acc_range;
struct pci_dev *pdev;
void __iomem *mem_mapped_bar;
uint32_t if_type;
uint32_t u32val;
int rc;
pdev = phba->pcidev;
if (!pdev)
return -EFAULT;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
bar_num = idiag.cmd.data[IDIAG_BARACC_BAR_NUM_INDX];
if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
if ((bar_num != IDIAG_BARACC_BAR_0) &&
(bar_num != IDIAG_BARACC_BAR_1) &&
(bar_num != IDIAG_BARACC_BAR_2))
goto error_out;
} else if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
if (bar_num != IDIAG_BARACC_BAR_0)
goto error_out;
} else
goto error_out;
if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
if (bar_num == IDIAG_BARACC_BAR_0) {
idiag.cmd.data[IDIAG_BARACC_BAR_SZE_INDX] =
LPFC_PCI_IF0_BAR0_SIZE;
mem_mapped_bar = phba->sli4_hba.conf_regs_memmap_p;
} else if (bar_num == IDIAG_BARACC_BAR_1) {
idiag.cmd.data[IDIAG_BARACC_BAR_SZE_INDX] =
LPFC_PCI_IF0_BAR1_SIZE;
mem_mapped_bar = phba->sli4_hba.ctrl_regs_memmap_p;
} else if (bar_num == IDIAG_BARACC_BAR_2) {
idiag.cmd.data[IDIAG_BARACC_BAR_SZE_INDX] =
LPFC_PCI_IF0_BAR2_SIZE;
mem_mapped_bar = phba->sli4_hba.drbl_regs_memmap_p;
} else
goto error_out;
} else if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
if (bar_num == IDIAG_BARACC_BAR_0) {
idiag.cmd.data[IDIAG_BARACC_BAR_SZE_INDX] =
LPFC_PCI_IF2_BAR0_SIZE;
mem_mapped_bar = phba->sli4_hba.conf_regs_memmap_p;
} else
goto error_out;
} else
goto error_out;
offset = idiag.cmd.data[IDIAG_BARACC_OFF_SET_INDX];
if (offset % sizeof(uint32_t))
goto error_out;
bar_size = idiag.cmd.data[IDIAG_BARACC_BAR_SZE_INDX];
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_RD) {
/* Sanity check on PCI config read command line arguments */
if (rc != LPFC_PCI_BAR_RD_CMD_ARG)
goto error_out;
acc_range = idiag.cmd.data[IDIAG_BARACC_ACC_MOD_INDX];
if (acc_range == LPFC_PCI_BAR_BROWSE) {
if (offset > bar_size - sizeof(uint32_t))
goto error_out;
/* Starting offset to browse */
idiag.offset.last_rd = offset;
} else if (acc_range > SINGLE_WORD) {
if (offset + acc_range * sizeof(uint32_t) > bar_size)
goto error_out;
/* Starting offset to browse */
idiag.offset.last_rd = offset;
} else if (acc_range != SINGLE_WORD)
goto error_out;
} else if (idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_CL) {
/* Sanity check on PCI bar write command line arguments */
if (rc != LPFC_PCI_BAR_WR_CMD_ARG)
goto error_out;
/* Write command to PCI bar space, read-modify-write */
acc_range = SINGLE_WORD;
value = idiag.cmd.data[IDIAG_BARACC_REG_VAL_INDX];
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_WR) {
writel(value, mem_mapped_bar + offset);
readl(mem_mapped_bar + offset);
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_ST) {
u32val = readl(mem_mapped_bar + offset);
u32val |= value;
writel(u32val, mem_mapped_bar + offset);
readl(mem_mapped_bar + offset);
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_BARACC_CL) {
u32val = readl(mem_mapped_bar + offset);
u32val &= ~value;
writel(u32val, mem_mapped_bar + offset);
readl(mem_mapped_bar + offset);
}
} else
/* All other opecodes are illegal for now */
goto error_out;
return nbytes;
error_out:
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_queinfo_read - idiag debugfs read queue information
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba SLI4 PCI function queue information,
* and copies to user @buf.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_queinfo_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
int len = 0;
char *pbuffer;
int x, cnt;
int max_cnt;
struct lpfc_queue *qp = NULL;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_QUE_INFO_GET_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
max_cnt = LPFC_QUE_INFO_GET_BUF_SIZE - 128;
if (*ppos)
return 0;
spin_lock_irq(&phba->hbalock);
/* Fast-path event queue */
if (phba->sli4_hba.hba_eq && phba->cfg_fcp_io_channel) {
cnt = phba->cfg_fcp_io_channel;
for (x = 0; x < cnt; x++) {
/* Fast-path EQ */
qp = phba->sli4_hba.hba_eq[x];
if (!qp)
goto proc_cq;
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\nHBA EQ info: "
"EQ-STAT[max:x%x noE:x%x "
"bs:x%x proc:x%llx]\n",
qp->q_cnt_1, qp->q_cnt_2,
qp->q_cnt_3, (unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"EQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id,
qp->entry_count,
qp->entry_size,
qp->host_index,
qp->hba_index);
/* Reset max counter */
qp->EQ_max_eqe = 0;
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
proc_cq:
/* Fast-path FCP CQ */
qp = phba->sli4_hba.fcp_cq[x];
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\tFCP CQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocEQID[%02d]: "
"CQ STAT[max:x%x relw:x%x "
"xabt:x%x wq:x%llx]\n",
qp->assoc_qid,
qp->q_cnt_1, qp->q_cnt_2,
qp->q_cnt_3, (unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\tCQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id, qp->entry_count,
qp->entry_size, qp->host_index,
qp->hba_index);
/* Reset max counter */
qp->CQ_max_cqe = 0;
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
/* Fast-path FCP WQ */
qp = phba->sli4_hba.fcp_wq[x];
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tFCP WQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocCQID[%02d]: "
"WQ-STAT[oflow:x%x posted:x%llx]\n",
qp->assoc_qid,
qp->q_cnt_1, (unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tWQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id,
qp->entry_count,
qp->entry_size,
qp->host_index,
qp->hba_index);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
if (x)
continue;
/* Only EQ 0 has slow path CQs configured */
/* Slow-path mailbox CQ */
qp = phba->sli4_hba.mbx_cq;
if (qp) {
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\tMBX CQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocEQID[%02d]: "
"CQ-STAT[mbox:x%x relw:x%x "
"xabt:x%x wq:x%llx]\n",
qp->assoc_qid,
qp->q_cnt_1, qp->q_cnt_2,
qp->q_cnt_3,
(unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\tCQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id, qp->entry_count,
qp->entry_size, qp->host_index,
qp->hba_index);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
}
/* Slow-path MBOX MQ */
qp = phba->sli4_hba.mbx_wq;
if (qp) {
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tMBX MQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocCQID[%02d]:\n",
phba->sli4_hba.mbx_wq->assoc_qid);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tWQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id, qp->entry_count,
qp->entry_size, qp->host_index,
qp->hba_index);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
}
/* Slow-path ELS response CQ */
qp = phba->sli4_hba.els_cq;
if (qp) {
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\tELS CQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocEQID[%02d]: "
"CQ-STAT[max:x%x relw:x%x "
"xabt:x%x wq:x%llx]\n",
qp->assoc_qid,
qp->q_cnt_1, qp->q_cnt_2,
qp->q_cnt_3,
(unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\tCQID [%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id, qp->entry_count,
qp->entry_size, qp->host_index,
qp->hba_index);
/* Reset max counter */
qp->CQ_max_cqe = 0;
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
}
/* Slow-path ELS WQ */
qp = phba->sli4_hba.els_wq;
if (qp) {
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tELS WQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocCQID[%02d]: "
" WQ-STAT[oflow:x%x "
"posted:x%llx]\n",
qp->assoc_qid,
qp->q_cnt_1,
(unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tWQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]",
qp->queue_id, qp->entry_count,
qp->entry_size, qp->host_index,
qp->hba_index);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
if (len >= max_cnt)
goto too_big;
}
if (phba->sli4_hba.hdr_rq && phba->sli4_hba.dat_rq) {
/* Slow-path RQ header */
qp = phba->sli4_hba.hdr_rq;
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tRQ info: ");
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"AssocCQID[%02d]: "
"RQ-STAT[nopost:x%x nobuf:x%x "
"trunc:x%x rcv:x%llx]\n",
qp->assoc_qid,
qp->q_cnt_1, qp->q_cnt_2,
qp->q_cnt_3,
(unsigned long long)qp->q_cnt_4);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tHQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]\n",
qp->queue_id,
qp->entry_count,
qp->entry_size,
qp->host_index,
qp->hba_index);
/* Slow-path RQ data */
qp = phba->sli4_hba.dat_rq;
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len,
"\t\tDQID[%02d], "
"QE-CNT[%04d], QE-SIZE[%04d], "
"HOST-IDX[%04d], PORT-IDX[%04d]\n",
qp->queue_id,
qp->entry_count,
qp->entry_size,
qp->host_index,
qp->hba_index);
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "\n");
}
}
}
spin_unlock_irq(&phba->hbalock);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
too_big:
len += snprintf(pbuffer+len,
LPFC_QUE_INFO_GET_BUF_SIZE-len, "Truncated ...\n");
spin_unlock_irq(&phba->hbalock);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_que_param_check - queue access command parameter sanity check
* @q: The pointer to queue structure.
* @index: The index into a queue entry.
* @count: The number of queue entries to access.
*
* Description:
* The routine performs sanity check on device queue access method commands.
*
* Returns:
* This function returns -EINVAL when fails the sanity check, otherwise, it
* returns 0.
**/
static int
lpfc_idiag_que_param_check(struct lpfc_queue *q, int index, int count)
{
/* Only support single entry read or browsing */
if ((count != 1) && (count != LPFC_QUE_ACC_BROWSE))
return -EINVAL;
if (index > q->entry_count - 1)
return -EINVAL;
return 0;
}
/**
* lpfc_idiag_queacc_read_qe - read a single entry from the given queue index
* @pbuffer: The pointer to buffer to copy the read data into.
* @pque: The pointer to the queue to be read.
* @index: The index into the queue entry.
*
* Description:
* This routine reads out a single entry from the given queue's index location
* and copies it into the buffer provided.
*
* Returns:
* This function returns 0 when it fails, otherwise, it returns the length of
* the data read into the buffer provided.
**/
static int
lpfc_idiag_queacc_read_qe(char *pbuffer, int len, struct lpfc_queue *pque,
uint32_t index)
{
int offset, esize;
uint32_t *pentry;
if (!pbuffer || !pque)
return 0;
esize = pque->entry_size;
len += snprintf(pbuffer+len, LPFC_QUE_ACC_BUF_SIZE-len,
"QE-INDEX[%04d]:\n", index);
offset = 0;
pentry = pque->qe[index].address;
while (esize > 0) {
len += snprintf(pbuffer+len, LPFC_QUE_ACC_BUF_SIZE-len,
"%08x ", *pentry);
pentry++;
offset += sizeof(uint32_t);
esize -= sizeof(uint32_t);
if (esize > 0 && !(offset % (4 * sizeof(uint32_t))))
len += snprintf(pbuffer+len,
LPFC_QUE_ACC_BUF_SIZE-len, "\n");
}
len += snprintf(pbuffer+len, LPFC_QUE_ACC_BUF_SIZE-len, "\n");
return len;
}
/**
* lpfc_idiag_queacc_read - idiag debugfs read port queue
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba device queue memory according to the
* idiag command, and copies to user @buf. Depending on the queue dump read
* command setup, it does either a single queue entry read or browing through
* all entries of the queue.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_queacc_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
uint32_t last_index, index, count;
struct lpfc_queue *pque = NULL;
char *pbuffer;
int len = 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_QUE_ACC_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_RD) {
index = idiag.cmd.data[IDIAG_QUEACC_INDEX_INDX];
count = idiag.cmd.data[IDIAG_QUEACC_COUNT_INDX];
pque = (struct lpfc_queue *)idiag.ptr_private;
} else
return 0;
/* Browse the queue starting from index */
if (count == LPFC_QUE_ACC_BROWSE)
goto que_browse;
/* Read a single entry from the queue */
len = lpfc_idiag_queacc_read_qe(pbuffer, len, pque, index);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
que_browse:
/* Browse all entries from the queue */
last_index = idiag.offset.last_rd;
index = last_index;
while (len < LPFC_QUE_ACC_SIZE - pque->entry_size) {
len = lpfc_idiag_queacc_read_qe(pbuffer, len, pque, index);
index++;
if (index > pque->entry_count - 1)
break;
}
/* Set up the offset for next portion of pci cfg read */
if (index > pque->entry_count - 1)
index = 0;
idiag.offset.last_rd = index;
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_queacc_write - Syntax check and set up idiag queacc commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and then
* perform the syntax check for port queue read (dump) or write (set) command
* accordingly. In the case of port queue read command, it sets up the command
* in the idiag command struct for the following debugfs read operation. In
* the case of port queue write operation, it executes the write operation
* into the port queue entry accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
**/
static ssize_t
lpfc_idiag_queacc_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t qidx, quetp, queid, index, count, offset, value;
uint32_t *pentry;
struct lpfc_queue *pque;
int rc;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
/* Get and sanity check on command feilds */
quetp = idiag.cmd.data[IDIAG_QUEACC_QUETP_INDX];
queid = idiag.cmd.data[IDIAG_QUEACC_QUEID_INDX];
index = idiag.cmd.data[IDIAG_QUEACC_INDEX_INDX];
count = idiag.cmd.data[IDIAG_QUEACC_COUNT_INDX];
offset = idiag.cmd.data[IDIAG_QUEACC_OFFST_INDX];
value = idiag.cmd.data[IDIAG_QUEACC_VALUE_INDX];
/* Sanity check on command line arguments */
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_CL) {
if (rc != LPFC_QUE_ACC_WR_CMD_ARG)
goto error_out;
if (count != 1)
goto error_out;
} else if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_RD) {
if (rc != LPFC_QUE_ACC_RD_CMD_ARG)
goto error_out;
} else
goto error_out;
switch (quetp) {
case LPFC_IDIAG_EQ:
/* HBA event queue */
if (phba->sli4_hba.hba_eq) {
for (qidx = 0; qidx < phba->cfg_fcp_io_channel;
qidx++) {
if (phba->sli4_hba.hba_eq[qidx] &&
phba->sli4_hba.hba_eq[qidx]->queue_id ==
queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.hba_eq[qidx],
index, count);
if (rc)
goto error_out;
idiag.ptr_private =
phba->sli4_hba.hba_eq[qidx];
goto pass_check;
}
}
}
goto error_out;
break;
case LPFC_IDIAG_CQ:
/* MBX complete queue */
if (phba->sli4_hba.mbx_cq &&
phba->sli4_hba.mbx_cq->queue_id == queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.mbx_cq, index, count);
if (rc)
goto error_out;
idiag.ptr_private = phba->sli4_hba.mbx_cq;
goto pass_check;
}
/* ELS complete queue */
if (phba->sli4_hba.els_cq &&
phba->sli4_hba.els_cq->queue_id == queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.els_cq, index, count);
if (rc)
goto error_out;
idiag.ptr_private = phba->sli4_hba.els_cq;
goto pass_check;
}
/* FCP complete queue */
if (phba->sli4_hba.fcp_cq) {
qidx = 0;
do {
if (phba->sli4_hba.fcp_cq[qidx] &&
phba->sli4_hba.fcp_cq[qidx]->queue_id ==
queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.fcp_cq[qidx],
index, count);
if (rc)
goto error_out;
idiag.ptr_private =
phba->sli4_hba.fcp_cq[qidx];
goto pass_check;
}
} while (++qidx < phba->cfg_fcp_io_channel);
}
goto error_out;
break;
case LPFC_IDIAG_MQ:
/* MBX work queue */
if (phba->sli4_hba.mbx_wq &&
phba->sli4_hba.mbx_wq->queue_id == queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.mbx_wq, index, count);
if (rc)
goto error_out;
idiag.ptr_private = phba->sli4_hba.mbx_wq;
goto pass_check;
}
goto error_out;
break;
case LPFC_IDIAG_WQ:
/* ELS work queue */
if (phba->sli4_hba.els_wq &&
phba->sli4_hba.els_wq->queue_id == queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.els_wq, index, count);
if (rc)
goto error_out;
idiag.ptr_private = phba->sli4_hba.els_wq;
goto pass_check;
}
/* FCP work queue */
if (phba->sli4_hba.fcp_wq) {
for (qidx = 0; qidx < phba->cfg_fcp_io_channel;
qidx++) {
if (!phba->sli4_hba.fcp_wq[qidx])
continue;
if (phba->sli4_hba.fcp_wq[qidx]->queue_id ==
queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.fcp_wq[qidx],
index, count);
if (rc)
goto error_out;
idiag.ptr_private =
phba->sli4_hba.fcp_wq[qidx];
goto pass_check;
}
}
}
goto error_out;
break;
case LPFC_IDIAG_RQ:
/* HDR queue */
if (phba->sli4_hba.hdr_rq &&
phba->sli4_hba.hdr_rq->queue_id == queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.hdr_rq, index, count);
if (rc)
goto error_out;
idiag.ptr_private = phba->sli4_hba.hdr_rq;
goto pass_check;
}
/* DAT queue */
if (phba->sli4_hba.dat_rq &&
phba->sli4_hba.dat_rq->queue_id == queid) {
/* Sanity check */
rc = lpfc_idiag_que_param_check(
phba->sli4_hba.dat_rq, index, count);
if (rc)
goto error_out;
idiag.ptr_private = phba->sli4_hba.dat_rq;
goto pass_check;
}
goto error_out;
break;
default:
goto error_out;
break;
}
pass_check:
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_RD) {
if (count == LPFC_QUE_ACC_BROWSE)
idiag.offset.last_rd = index;
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_CL) {
/* Additional sanity checks on write operation */
pque = (struct lpfc_queue *)idiag.ptr_private;
if (offset > pque->entry_size/sizeof(uint32_t) - 1)
goto error_out;
pentry = pque->qe[index].address;
pentry += offset;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_WR)
*pentry = value;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_ST)
*pentry |= value;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_QUEACC_CL)
*pentry &= ~value;
}
return nbytes;
error_out:
/* Clean out command structure on command error out */
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_drbacc_read_reg - idiag debugfs read a doorbell register
* @phba: The pointer to hba structure.
* @pbuffer: The pointer to the buffer to copy the data to.
* @len: The lenght of bytes to copied.
* @drbregid: The id to doorbell registers.
*
* Description:
* This routine reads a doorbell register and copies its content to the
* user buffer pointed to by @pbuffer.
*
* Returns:
* This function returns the amount of data that was copied into @pbuffer.
**/
static int
lpfc_idiag_drbacc_read_reg(struct lpfc_hba *phba, char *pbuffer,
int len, uint32_t drbregid)
{
if (!pbuffer)
return 0;
switch (drbregid) {
case LPFC_DRB_EQCQ:
len += snprintf(pbuffer+len, LPFC_DRB_ACC_BUF_SIZE-len,
"EQCQ-DRB-REG: 0x%08x\n",
readl(phba->sli4_hba.EQCQDBregaddr));
break;
case LPFC_DRB_MQ:
len += snprintf(pbuffer+len, LPFC_DRB_ACC_BUF_SIZE-len,
"MQ-DRB-REG: 0x%08x\n",
readl(phba->sli4_hba.MQDBregaddr));
break;
case LPFC_DRB_WQ:
len += snprintf(pbuffer+len, LPFC_DRB_ACC_BUF_SIZE-len,
"WQ-DRB-REG: 0x%08x\n",
readl(phba->sli4_hba.WQDBregaddr));
break;
case LPFC_DRB_RQ:
len += snprintf(pbuffer+len, LPFC_DRB_ACC_BUF_SIZE-len,
"RQ-DRB-REG: 0x%08x\n",
readl(phba->sli4_hba.RQDBregaddr));
break;
default:
break;
}
return len;
}
/**
* lpfc_idiag_drbacc_read - idiag debugfs read port doorbell
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba device doorbell register according
* to the idiag command, and copies to user @buf. Depending on the doorbell
* register read command setup, it does either a single doorbell register
* read or dump all doorbell registers.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_drbacc_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t drb_reg_id, i;
char *pbuffer;
int len = 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_DRB_ACC_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_RD)
drb_reg_id = idiag.cmd.data[IDIAG_DRBACC_REGID_INDX];
else
return 0;
if (drb_reg_id == LPFC_DRB_ACC_ALL)
for (i = 1; i <= LPFC_DRB_MAX; i++)
len = lpfc_idiag_drbacc_read_reg(phba,
pbuffer, len, i);
else
len = lpfc_idiag_drbacc_read_reg(phba,
pbuffer, len, drb_reg_id);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_drbacc_write - Syntax check and set up idiag drbacc commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and then
* perform the syntax check for port doorbell register read (dump) or write
* (set) command accordingly. In the case of port queue read command, it sets
* up the command in the idiag command struct for the following debugfs read
* operation. In the case of port doorbell register write operation, it
* executes the write operation into the port doorbell register accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
**/
static ssize_t
lpfc_idiag_drbacc_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t drb_reg_id, value, reg_val = 0;
void __iomem *drb_reg;
int rc;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
/* Sanity check on command line arguments */
drb_reg_id = idiag.cmd.data[IDIAG_DRBACC_REGID_INDX];
value = idiag.cmd.data[IDIAG_DRBACC_VALUE_INDX];
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_CL) {
if (rc != LPFC_DRB_ACC_WR_CMD_ARG)
goto error_out;
if (drb_reg_id > LPFC_DRB_MAX)
goto error_out;
} else if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_RD) {
if (rc != LPFC_DRB_ACC_RD_CMD_ARG)
goto error_out;
if ((drb_reg_id > LPFC_DRB_MAX) &&
(drb_reg_id != LPFC_DRB_ACC_ALL))
goto error_out;
} else
goto error_out;
/* Perform the write access operation */
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_CL) {
switch (drb_reg_id) {
case LPFC_DRB_EQCQ:
drb_reg = phba->sli4_hba.EQCQDBregaddr;
break;
case LPFC_DRB_MQ:
drb_reg = phba->sli4_hba.MQDBregaddr;
break;
case LPFC_DRB_WQ:
drb_reg = phba->sli4_hba.WQDBregaddr;
break;
case LPFC_DRB_RQ:
drb_reg = phba->sli4_hba.RQDBregaddr;
break;
default:
goto error_out;
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_WR)
reg_val = value;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_ST) {
reg_val = readl(drb_reg);
reg_val |= value;
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_DRBACC_CL) {
reg_val = readl(drb_reg);
reg_val &= ~value;
}
writel(reg_val, drb_reg);
readl(drb_reg); /* flush */
}
return nbytes;
error_out:
/* Clean out command structure on command error out */
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_ctlacc_read_reg - idiag debugfs read a control registers
* @phba: The pointer to hba structure.
* @pbuffer: The pointer to the buffer to copy the data to.
* @len: The lenght of bytes to copied.
* @drbregid: The id to doorbell registers.
*
* Description:
* This routine reads a control register and copies its content to the
* user buffer pointed to by @pbuffer.
*
* Returns:
* This function returns the amount of data that was copied into @pbuffer.
**/
static int
lpfc_idiag_ctlacc_read_reg(struct lpfc_hba *phba, char *pbuffer,
int len, uint32_t ctlregid)
{
if (!pbuffer)
return 0;
switch (ctlregid) {
case LPFC_CTL_PORT_SEM:
len += snprintf(pbuffer+len, LPFC_CTL_ACC_BUF_SIZE-len,
"Port SemReg: 0x%08x\n",
readl(phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_SEM_OFFSET));
break;
case LPFC_CTL_PORT_STA:
len += snprintf(pbuffer+len, LPFC_CTL_ACC_BUF_SIZE-len,
"Port StaReg: 0x%08x\n",
readl(phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_STA_OFFSET));
break;
case LPFC_CTL_PORT_CTL:
len += snprintf(pbuffer+len, LPFC_CTL_ACC_BUF_SIZE-len,
"Port CtlReg: 0x%08x\n",
readl(phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_CTL_OFFSET));
break;
case LPFC_CTL_PORT_ER1:
len += snprintf(pbuffer+len, LPFC_CTL_ACC_BUF_SIZE-len,
"Port Er1Reg: 0x%08x\n",
readl(phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_ER1_OFFSET));
break;
case LPFC_CTL_PORT_ER2:
len += snprintf(pbuffer+len, LPFC_CTL_ACC_BUF_SIZE-len,
"Port Er2Reg: 0x%08x\n",
readl(phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_ER2_OFFSET));
break;
case LPFC_CTL_PDEV_CTL:
len += snprintf(pbuffer+len, LPFC_CTL_ACC_BUF_SIZE-len,
"PDev CtlReg: 0x%08x\n",
readl(phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PDEV_CTL_OFFSET));
break;
default:
break;
}
return len;
}
/**
* lpfc_idiag_ctlacc_read - idiag debugfs read port and device control register
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba port and device registers according
* to the idiag command, and copies to user @buf.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_ctlacc_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t ctl_reg_id, i;
char *pbuffer;
int len = 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_CTL_ACC_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_RD)
ctl_reg_id = idiag.cmd.data[IDIAG_CTLACC_REGID_INDX];
else
return 0;
if (ctl_reg_id == LPFC_CTL_ACC_ALL)
for (i = 1; i <= LPFC_CTL_MAX; i++)
len = lpfc_idiag_ctlacc_read_reg(phba,
pbuffer, len, i);
else
len = lpfc_idiag_ctlacc_read_reg(phba,
pbuffer, len, ctl_reg_id);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_ctlacc_write - Syntax check and set up idiag ctlacc commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and then
* perform the syntax check for port and device control register read (dump)
* or write (set) command accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
**/
static ssize_t
lpfc_idiag_ctlacc_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
uint32_t ctl_reg_id, value, reg_val = 0;
void __iomem *ctl_reg;
int rc;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
/* Sanity check on command line arguments */
ctl_reg_id = idiag.cmd.data[IDIAG_CTLACC_REGID_INDX];
value = idiag.cmd.data[IDIAG_CTLACC_VALUE_INDX];
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_CL) {
if (rc != LPFC_CTL_ACC_WR_CMD_ARG)
goto error_out;
if (ctl_reg_id > LPFC_CTL_MAX)
goto error_out;
} else if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_RD) {
if (rc != LPFC_CTL_ACC_RD_CMD_ARG)
goto error_out;
if ((ctl_reg_id > LPFC_CTL_MAX) &&
(ctl_reg_id != LPFC_CTL_ACC_ALL))
goto error_out;
} else
goto error_out;
/* Perform the write access operation */
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_WR ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_ST ||
idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_CL) {
switch (ctl_reg_id) {
case LPFC_CTL_PORT_SEM:
ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_SEM_OFFSET;
break;
case LPFC_CTL_PORT_STA:
ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_STA_OFFSET;
break;
case LPFC_CTL_PORT_CTL:
ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_CTL_OFFSET;
break;
case LPFC_CTL_PORT_ER1:
ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_ER1_OFFSET;
break;
case LPFC_CTL_PORT_ER2:
ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_ER2_OFFSET;
break;
case LPFC_CTL_PDEV_CTL:
ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PDEV_CTL_OFFSET;
break;
default:
goto error_out;
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_WR)
reg_val = value;
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_ST) {
reg_val = readl(ctl_reg);
reg_val |= value;
}
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_CTLACC_CL) {
reg_val = readl(ctl_reg);
reg_val &= ~value;
}
writel(reg_val, ctl_reg);
readl(ctl_reg); /* flush */
}
return nbytes;
error_out:
/* Clean out command structure on command error out */
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_mbxacc_get_setup - idiag debugfs get mailbox access setup
* @phba: Pointer to HBA context object.
* @pbuffer: Pointer to data buffer.
*
* Description:
* This routine gets the driver mailbox access debugfs setup information.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static int
lpfc_idiag_mbxacc_get_setup(struct lpfc_hba *phba, char *pbuffer)
{
uint32_t mbx_dump_map, mbx_dump_cnt, mbx_word_cnt, mbx_mbox_cmd;
int len = 0;
mbx_mbox_cmd = idiag.cmd.data[IDIAG_MBXACC_MBCMD_INDX];
mbx_dump_map = idiag.cmd.data[IDIAG_MBXACC_DPMAP_INDX];
mbx_dump_cnt = idiag.cmd.data[IDIAG_MBXACC_DPCNT_INDX];
mbx_word_cnt = idiag.cmd.data[IDIAG_MBXACC_WDCNT_INDX];
len += snprintf(pbuffer+len, LPFC_MBX_ACC_BUF_SIZE-len,
"mbx_dump_map: 0x%08x\n", mbx_dump_map);
len += snprintf(pbuffer+len, LPFC_MBX_ACC_BUF_SIZE-len,
"mbx_dump_cnt: %04d\n", mbx_dump_cnt);
len += snprintf(pbuffer+len, LPFC_MBX_ACC_BUF_SIZE-len,
"mbx_word_cnt: %04d\n", mbx_word_cnt);
len += snprintf(pbuffer+len, LPFC_MBX_ACC_BUF_SIZE-len,
"mbx_mbox_cmd: 0x%02x\n", mbx_mbox_cmd);
return len;
}
/**
* lpfc_idiag_mbxacc_read - idiag debugfs read on mailbox access
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the @phba driver mailbox access debugfs setup
* information.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_mbxacc_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
char *pbuffer;
int len = 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_MBX_ACC_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if ((idiag.cmd.opcode != LPFC_IDIAG_CMD_MBXACC_DP) &&
(idiag.cmd.opcode != LPFC_IDIAG_BSG_MBXACC_DP))
return 0;
len = lpfc_idiag_mbxacc_get_setup(phba, pbuffer);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
/**
* lpfc_idiag_mbxacc_write - Syntax check and set up idiag mbxacc commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and then
* perform the syntax check for driver mailbox command (dump) and sets up the
* necessary states in the idiag command struct accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
**/
static ssize_t
lpfc_idiag_mbxacc_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
uint32_t mbx_dump_map, mbx_dump_cnt, mbx_word_cnt, mbx_mbox_cmd;
int rc;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
/* Sanity check on command line arguments */
mbx_mbox_cmd = idiag.cmd.data[IDIAG_MBXACC_MBCMD_INDX];
mbx_dump_map = idiag.cmd.data[IDIAG_MBXACC_DPMAP_INDX];
mbx_dump_cnt = idiag.cmd.data[IDIAG_MBXACC_DPCNT_INDX];
mbx_word_cnt = idiag.cmd.data[IDIAG_MBXACC_WDCNT_INDX];
if (idiag.cmd.opcode == LPFC_IDIAG_CMD_MBXACC_DP) {
if (!(mbx_dump_map & LPFC_MBX_DMP_MBX_ALL))
goto error_out;
if ((mbx_dump_map & ~LPFC_MBX_DMP_MBX_ALL) &&
(mbx_dump_map != LPFC_MBX_DMP_ALL))
goto error_out;
if (mbx_word_cnt > sizeof(MAILBOX_t))
goto error_out;
} else if (idiag.cmd.opcode == LPFC_IDIAG_BSG_MBXACC_DP) {
if (!(mbx_dump_map & LPFC_BSG_DMP_MBX_ALL))
goto error_out;
if ((mbx_dump_map & ~LPFC_BSG_DMP_MBX_ALL) &&
(mbx_dump_map != LPFC_MBX_DMP_ALL))
goto error_out;
if (mbx_word_cnt > (BSG_MBOX_SIZE)/4)
goto error_out;
if (mbx_mbox_cmd != 0x9b)
goto error_out;
} else
goto error_out;
if (mbx_word_cnt == 0)
goto error_out;
if (rc != LPFC_MBX_DMP_ARG)
goto error_out;
if (mbx_mbox_cmd & ~0xff)
goto error_out;
/* condition for stop mailbox dump */
if (mbx_dump_cnt == 0)
goto reset_out;
return nbytes;
reset_out:
/* Clean out command structure on command error out */
memset(&idiag, 0, sizeof(idiag));
return nbytes;
error_out:
/* Clean out command structure on command error out */
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_extacc_avail_get - get the available extents information
* @phba: pointer to lpfc hba data structure.
* @pbuffer: pointer to internal buffer.
* @len: length into the internal buffer data has been copied.
*
* Description:
* This routine is to get the available extent information.
*
* Returns:
* overall lenth of the data read into the internal buffer.
**/
static int
lpfc_idiag_extacc_avail_get(struct lpfc_hba *phba, char *pbuffer, int len)
{
uint16_t ext_cnt, ext_size;
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\nAvailable Extents Information:\n");
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tPort Available VPI extents: ");
lpfc_sli4_get_avail_extnt_rsrc(phba, LPFC_RSC_TYPE_FCOE_VPI,
&ext_cnt, &ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Count %3d, Size %3d\n", ext_cnt, ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tPort Available VFI extents: ");
lpfc_sli4_get_avail_extnt_rsrc(phba, LPFC_RSC_TYPE_FCOE_VFI,
&ext_cnt, &ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Count %3d, Size %3d\n", ext_cnt, ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tPort Available RPI extents: ");
lpfc_sli4_get_avail_extnt_rsrc(phba, LPFC_RSC_TYPE_FCOE_RPI,
&ext_cnt, &ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Count %3d, Size %3d\n", ext_cnt, ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tPort Available XRI extents: ");
lpfc_sli4_get_avail_extnt_rsrc(phba, LPFC_RSC_TYPE_FCOE_XRI,
&ext_cnt, &ext_size);
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Count %3d, Size %3d\n", ext_cnt, ext_size);
return len;
}
/**
* lpfc_idiag_extacc_alloc_get - get the allocated extents information
* @phba: pointer to lpfc hba data structure.
* @pbuffer: pointer to internal buffer.
* @len: length into the internal buffer data has been copied.
*
* Description:
* This routine is to get the allocated extent information.
*
* Returns:
* overall lenth of the data read into the internal buffer.
**/
static int
lpfc_idiag_extacc_alloc_get(struct lpfc_hba *phba, char *pbuffer, int len)
{
uint16_t ext_cnt, ext_size;
int rc;
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\nAllocated Extents Information:\n");
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tHost Allocated VPI extents: ");
rc = lpfc_sli4_get_allocated_extnts(phba, LPFC_RSC_TYPE_FCOE_VPI,
&ext_cnt, &ext_size);
if (!rc)
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Port %d Extent %3d, Size %3d\n",
phba->brd_no, ext_cnt, ext_size);
else
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"N/A\n");
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tHost Allocated VFI extents: ");
rc = lpfc_sli4_get_allocated_extnts(phba, LPFC_RSC_TYPE_FCOE_VFI,
&ext_cnt, &ext_size);
if (!rc)
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Port %d Extent %3d, Size %3d\n",
phba->brd_no, ext_cnt, ext_size);
else
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"N/A\n");
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tHost Allocated RPI extents: ");
rc = lpfc_sli4_get_allocated_extnts(phba, LPFC_RSC_TYPE_FCOE_RPI,
&ext_cnt, &ext_size);
if (!rc)
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Port %d Extent %3d, Size %3d\n",
phba->brd_no, ext_cnt, ext_size);
else
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"N/A\n");
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tHost Allocated XRI extents: ");
rc = lpfc_sli4_get_allocated_extnts(phba, LPFC_RSC_TYPE_FCOE_XRI,
&ext_cnt, &ext_size);
if (!rc)
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"Port %d Extent %3d, Size %3d\n",
phba->brd_no, ext_cnt, ext_size);
else
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"N/A\n");
return len;
}
/**
* lpfc_idiag_extacc_drivr_get - get driver extent information
* @phba: pointer to lpfc hba data structure.
* @pbuffer: pointer to internal buffer.
* @len: length into the internal buffer data has been copied.
*
* Description:
* This routine is to get the driver extent information.
*
* Returns:
* overall lenth of the data read into the internal buffer.
**/
static int
lpfc_idiag_extacc_drivr_get(struct lpfc_hba *phba, char *pbuffer, int len)
{
struct lpfc_rsrc_blks *rsrc_blks;
int index;
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\nDriver Extents Information:\n");
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tVPI extents:\n");
index = 0;
list_for_each_entry(rsrc_blks, &phba->lpfc_vpi_blk_list, list) {
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\t\tBlock %3d: Start %4d, Count %4d\n",
index, rsrc_blks->rsrc_start,
rsrc_blks->rsrc_size);
index++;
}
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tVFI extents:\n");
index = 0;
list_for_each_entry(rsrc_blks, &phba->sli4_hba.lpfc_vfi_blk_list,
list) {
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\t\tBlock %3d: Start %4d, Count %4d\n",
index, rsrc_blks->rsrc_start,
rsrc_blks->rsrc_size);
index++;
}
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tRPI extents:\n");
index = 0;
list_for_each_entry(rsrc_blks, &phba->sli4_hba.lpfc_rpi_blk_list,
list) {
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\t\tBlock %3d: Start %4d, Count %4d\n",
index, rsrc_blks->rsrc_start,
rsrc_blks->rsrc_size);
index++;
}
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\tXRI extents:\n");
index = 0;
list_for_each_entry(rsrc_blks, &phba->sli4_hba.lpfc_xri_blk_list,
list) {
len += snprintf(pbuffer+len, LPFC_EXT_ACC_BUF_SIZE-len,
"\t\tBlock %3d: Start %4d, Count %4d\n",
index, rsrc_blks->rsrc_start,
rsrc_blks->rsrc_size);
index++;
}
return len;
}
/**
* lpfc_idiag_extacc_write - Syntax check and set up idiag extacc commands
* @file: The file pointer to read from.
* @buf: The buffer to copy the user data from.
* @nbytes: The number of bytes to get.
* @ppos: The position in the file to start reading from.
*
* This routine get the debugfs idiag command struct from user space and then
* perform the syntax check for extent information access commands and sets
* up the necessary states in the idiag command struct accordingly.
*
* It returns the @nbytges passing in from debugfs user space when successful.
* In case of error conditions, it returns proper error code back to the user
* space.
**/
static ssize_t
lpfc_idiag_extacc_write(struct file *file, const char __user *buf,
size_t nbytes, loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
uint32_t ext_map;
int rc;
/* This is a user write operation */
debug->op = LPFC_IDIAG_OP_WR;
rc = lpfc_idiag_cmd_get(buf, nbytes, &idiag.cmd);
if (rc < 0)
return rc;
ext_map = idiag.cmd.data[IDIAG_EXTACC_EXMAP_INDX];
if (idiag.cmd.opcode != LPFC_IDIAG_CMD_EXTACC_RD)
goto error_out;
if (rc != LPFC_EXT_ACC_CMD_ARG)
goto error_out;
if (!(ext_map & LPFC_EXT_ACC_ALL))
goto error_out;
return nbytes;
error_out:
/* Clean out command structure on command error out */
memset(&idiag, 0, sizeof(idiag));
return -EINVAL;
}
/**
* lpfc_idiag_extacc_read - idiag debugfs read access to extent information
* @file: The file pointer to read from.
* @buf: The buffer to copy the data to.
* @nbytes: The number of bytes to read.
* @ppos: The position in the file to start reading from.
*
* Description:
* This routine reads data from the proper extent information according to
* the idiag command, and copies to user @buf.
*
* Returns:
* This function returns the amount of data that was read (this could be less
* than @nbytes if the end of the file was reached) or a negative error value.
**/
static ssize_t
lpfc_idiag_extacc_read(struct file *file, char __user *buf, size_t nbytes,
loff_t *ppos)
{
struct lpfc_debug *debug = file->private_data;
struct lpfc_hba *phba = (struct lpfc_hba *)debug->i_private;
char *pbuffer;
uint32_t ext_map;
int len = 0;
/* This is a user read operation */
debug->op = LPFC_IDIAG_OP_RD;
if (!debug->buffer)
debug->buffer = kmalloc(LPFC_EXT_ACC_BUF_SIZE, GFP_KERNEL);
if (!debug->buffer)
return 0;
pbuffer = debug->buffer;
if (*ppos)
return 0;
if (idiag.cmd.opcode != LPFC_IDIAG_CMD_EXTACC_RD)
return 0;
ext_map = idiag.cmd.data[IDIAG_EXTACC_EXMAP_INDX];
if (ext_map & LPFC_EXT_ACC_AVAIL)
len = lpfc_idiag_extacc_avail_get(phba, pbuffer, len);
if (ext_map & LPFC_EXT_ACC_ALLOC)
len = lpfc_idiag_extacc_alloc_get(phba, pbuffer, len);
if (ext_map & LPFC_EXT_ACC_DRIVR)
len = lpfc_idiag_extacc_drivr_get(phba, pbuffer, len);
return simple_read_from_buffer(buf, nbytes, ppos, pbuffer, len);
}
#undef lpfc_debugfs_op_disc_trc
static const struct file_operations lpfc_debugfs_op_disc_trc = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_disc_trc_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.release = lpfc_debugfs_release,
};
#undef lpfc_debugfs_op_nodelist
static const struct file_operations lpfc_debugfs_op_nodelist = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_nodelist_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.release = lpfc_debugfs_release,
};
#undef lpfc_debugfs_op_hbqinfo
static const struct file_operations lpfc_debugfs_op_hbqinfo = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_hbqinfo_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.release = lpfc_debugfs_release,
};
#undef lpfc_debugfs_op_dumpHBASlim
static const struct file_operations lpfc_debugfs_op_dumpHBASlim = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_dumpHBASlim_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.release = lpfc_debugfs_release,
};
#undef lpfc_debugfs_op_dumpHostSlim
static const struct file_operations lpfc_debugfs_op_dumpHostSlim = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_dumpHostSlim_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.release = lpfc_debugfs_release,
};
#undef lpfc_debugfs_op_dumpData
static const struct file_operations lpfc_debugfs_op_dumpData = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_dumpData_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.write = lpfc_debugfs_dumpDataDif_write,
.release = lpfc_debugfs_dumpDataDif_release,
};
#undef lpfc_debugfs_op_dumpDif
static const struct file_operations lpfc_debugfs_op_dumpDif = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_dumpDif_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.write = lpfc_debugfs_dumpDataDif_write,
.release = lpfc_debugfs_dumpDataDif_release,
};
#undef lpfc_debugfs_op_dif_err
static const struct file_operations lpfc_debugfs_op_dif_err = {
.owner = THIS_MODULE,
.open = simple_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_dif_err_read,
.write = lpfc_debugfs_dif_err_write,
.release = lpfc_debugfs_dif_err_release,
};
#undef lpfc_debugfs_op_slow_ring_trc
static const struct file_operations lpfc_debugfs_op_slow_ring_trc = {
.owner = THIS_MODULE,
.open = lpfc_debugfs_slow_ring_trc_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_debugfs_read,
.release = lpfc_debugfs_release,
};
static struct dentry *lpfc_debugfs_root = NULL;
static atomic_t lpfc_debugfs_hba_count;
/*
* File operations for the iDiag debugfs
*/
#undef lpfc_idiag_op_pciCfg
static const struct file_operations lpfc_idiag_op_pciCfg = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_pcicfg_read,
.write = lpfc_idiag_pcicfg_write,
.release = lpfc_idiag_cmd_release,
};
#undef lpfc_idiag_op_barAcc
static const struct file_operations lpfc_idiag_op_barAcc = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_baracc_read,
.write = lpfc_idiag_baracc_write,
.release = lpfc_idiag_cmd_release,
};
#undef lpfc_idiag_op_queInfo
static const struct file_operations lpfc_idiag_op_queInfo = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.read = lpfc_idiag_queinfo_read,
.release = lpfc_idiag_release,
};
#undef lpfc_idiag_op_queAcc
static const struct file_operations lpfc_idiag_op_queAcc = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_queacc_read,
.write = lpfc_idiag_queacc_write,
.release = lpfc_idiag_cmd_release,
};
#undef lpfc_idiag_op_drbAcc
static const struct file_operations lpfc_idiag_op_drbAcc = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_drbacc_read,
.write = lpfc_idiag_drbacc_write,
.release = lpfc_idiag_cmd_release,
};
#undef lpfc_idiag_op_ctlAcc
static const struct file_operations lpfc_idiag_op_ctlAcc = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_ctlacc_read,
.write = lpfc_idiag_ctlacc_write,
.release = lpfc_idiag_cmd_release,
};
#undef lpfc_idiag_op_mbxAcc
static const struct file_operations lpfc_idiag_op_mbxAcc = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_mbxacc_read,
.write = lpfc_idiag_mbxacc_write,
.release = lpfc_idiag_cmd_release,
};
#undef lpfc_idiag_op_extAcc
static const struct file_operations lpfc_idiag_op_extAcc = {
.owner = THIS_MODULE,
.open = lpfc_idiag_open,
.llseek = lpfc_debugfs_lseek,
.read = lpfc_idiag_extacc_read,
.write = lpfc_idiag_extacc_write,
.release = lpfc_idiag_cmd_release,
};
#endif
/* lpfc_idiag_mbxacc_dump_bsg_mbox - idiag debugfs dump bsg mailbox command
* @phba: Pointer to HBA context object.
* @dmabuf: Pointer to a DMA buffer descriptor.
*
* Description:
* This routine dump a bsg pass-through non-embedded mailbox command with
* external buffer.
**/
void
lpfc_idiag_mbxacc_dump_bsg_mbox(struct lpfc_hba *phba, enum nemb_type nemb_tp,
enum mbox_type mbox_tp, enum dma_type dma_tp,
enum sta_type sta_tp,
struct lpfc_dmabuf *dmabuf, uint32_t ext_buf)
{
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
uint32_t *mbx_mbox_cmd, *mbx_dump_map, *mbx_dump_cnt, *mbx_word_cnt;
char line_buf[LPFC_MBX_ACC_LBUF_SZ];
int len = 0;
uint32_t do_dump = 0;
uint32_t *pword;
uint32_t i;
if (idiag.cmd.opcode != LPFC_IDIAG_BSG_MBXACC_DP)
return;
mbx_mbox_cmd = &idiag.cmd.data[IDIAG_MBXACC_MBCMD_INDX];
mbx_dump_map = &idiag.cmd.data[IDIAG_MBXACC_DPMAP_INDX];
mbx_dump_cnt = &idiag.cmd.data[IDIAG_MBXACC_DPCNT_INDX];
mbx_word_cnt = &idiag.cmd.data[IDIAG_MBXACC_WDCNT_INDX];
if (!(*mbx_dump_map & LPFC_MBX_DMP_ALL) ||
(*mbx_dump_cnt == 0) ||
(*mbx_word_cnt == 0))
return;
if (*mbx_mbox_cmd != 0x9B)
return;
if ((mbox_tp == mbox_rd) && (dma_tp == dma_mbox)) {
if (*mbx_dump_map & LPFC_BSG_DMP_MBX_RD_MBX) {
do_dump |= LPFC_BSG_DMP_MBX_RD_MBX;
printk(KERN_ERR "\nRead mbox command (x%x), "
"nemb:0x%x, extbuf_cnt:%d:\n",
sta_tp, nemb_tp, ext_buf);
}
}
if ((mbox_tp == mbox_rd) && (dma_tp == dma_ebuf)) {
if (*mbx_dump_map & LPFC_BSG_DMP_MBX_RD_BUF) {
do_dump |= LPFC_BSG_DMP_MBX_RD_BUF;
printk(KERN_ERR "\nRead mbox buffer (x%x), "
"nemb:0x%x, extbuf_seq:%d:\n",
sta_tp, nemb_tp, ext_buf);
}
}
if ((mbox_tp == mbox_wr) && (dma_tp == dma_mbox)) {
if (*mbx_dump_map & LPFC_BSG_DMP_MBX_WR_MBX) {
do_dump |= LPFC_BSG_DMP_MBX_WR_MBX;
printk(KERN_ERR "\nWrite mbox command (x%x), "
"nemb:0x%x, extbuf_cnt:%d:\n",
sta_tp, nemb_tp, ext_buf);
}
}
if ((mbox_tp == mbox_wr) && (dma_tp == dma_ebuf)) {
if (*mbx_dump_map & LPFC_BSG_DMP_MBX_WR_BUF) {
do_dump |= LPFC_BSG_DMP_MBX_WR_BUF;
printk(KERN_ERR "\nWrite mbox buffer (x%x), "
"nemb:0x%x, extbuf_seq:%d:\n",
sta_tp, nemb_tp, ext_buf);
}
}
/* dump buffer content */
if (do_dump) {
pword = (uint32_t *)dmabuf->virt;
for (i = 0; i < *mbx_word_cnt; i++) {
if (!(i % 8)) {
if (i != 0)
printk(KERN_ERR "%s\n", line_buf);
len = 0;
len += snprintf(line_buf+len,
LPFC_MBX_ACC_LBUF_SZ-len,
"%03d: ", i);
}
len += snprintf(line_buf+len, LPFC_MBX_ACC_LBUF_SZ-len,
"%08x ", (uint32_t)*pword);
pword++;
}
if ((i - 1) % 8)
printk(KERN_ERR "%s\n", line_buf);
(*mbx_dump_cnt)--;
}
/* Clean out command structure on reaching dump count */
if (*mbx_dump_cnt == 0)
memset(&idiag, 0, sizeof(idiag));
return;
#endif
}
/* lpfc_idiag_mbxacc_dump_issue_mbox - idiag debugfs dump issue mailbox command
* @phba: Pointer to HBA context object.
* @dmabuf: Pointer to a DMA buffer descriptor.
*
* Description:
* This routine dump a pass-through non-embedded mailbox command from issue
* mailbox command.
**/
void
lpfc_idiag_mbxacc_dump_issue_mbox(struct lpfc_hba *phba, MAILBOX_t *pmbox)
{
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
uint32_t *mbx_dump_map, *mbx_dump_cnt, *mbx_word_cnt, *mbx_mbox_cmd;
char line_buf[LPFC_MBX_ACC_LBUF_SZ];
int len = 0;
uint32_t *pword;
uint8_t *pbyte;
uint32_t i, j;
if (idiag.cmd.opcode != LPFC_IDIAG_CMD_MBXACC_DP)
return;
mbx_mbox_cmd = &idiag.cmd.data[IDIAG_MBXACC_MBCMD_INDX];
mbx_dump_map = &idiag.cmd.data[IDIAG_MBXACC_DPMAP_INDX];
mbx_dump_cnt = &idiag.cmd.data[IDIAG_MBXACC_DPCNT_INDX];
mbx_word_cnt = &idiag.cmd.data[IDIAG_MBXACC_WDCNT_INDX];
if (!(*mbx_dump_map & LPFC_MBX_DMP_MBX_ALL) ||
(*mbx_dump_cnt == 0) ||
(*mbx_word_cnt == 0))
return;
if ((*mbx_mbox_cmd != LPFC_MBX_ALL_CMD) &&
(*mbx_mbox_cmd != pmbox->mbxCommand))
return;
/* dump buffer content */
if (*mbx_dump_map & LPFC_MBX_DMP_MBX_WORD) {
printk(KERN_ERR "Mailbox command:0x%x dump by word:\n",
pmbox->mbxCommand);
pword = (uint32_t *)pmbox;
for (i = 0; i < *mbx_word_cnt; i++) {
if (!(i % 8)) {
if (i != 0)
printk(KERN_ERR "%s\n", line_buf);
len = 0;
memset(line_buf, 0, LPFC_MBX_ACC_LBUF_SZ);
len += snprintf(line_buf+len,
LPFC_MBX_ACC_LBUF_SZ-len,
"%03d: ", i);
}
len += snprintf(line_buf+len, LPFC_MBX_ACC_LBUF_SZ-len,
"%08x ",
((uint32_t)*pword) & 0xffffffff);
pword++;
}
if ((i - 1) % 8)
printk(KERN_ERR "%s\n", line_buf);
printk(KERN_ERR "\n");
}
if (*mbx_dump_map & LPFC_MBX_DMP_MBX_BYTE) {
printk(KERN_ERR "Mailbox command:0x%x dump by byte:\n",
pmbox->mbxCommand);
pbyte = (uint8_t *)pmbox;
for (i = 0; i < *mbx_word_cnt; i++) {
if (!(i % 8)) {
if (i != 0)
printk(KERN_ERR "%s\n", line_buf);
len = 0;
memset(line_buf, 0, LPFC_MBX_ACC_LBUF_SZ);
len += snprintf(line_buf+len,
LPFC_MBX_ACC_LBUF_SZ-len,
"%03d: ", i);
}
for (j = 0; j < 4; j++) {
len += snprintf(line_buf+len,
LPFC_MBX_ACC_LBUF_SZ-len,
"%02x",
((uint8_t)*pbyte) & 0xff);
pbyte++;
}
len += snprintf(line_buf+len,
LPFC_MBX_ACC_LBUF_SZ-len, " ");
}
if ((i - 1) % 8)
printk(KERN_ERR "%s\n", line_buf);
printk(KERN_ERR "\n");
}
(*mbx_dump_cnt)--;
/* Clean out command structure on reaching dump count */
if (*mbx_dump_cnt == 0)
memset(&idiag, 0, sizeof(idiag));
return;
#endif
}
/**
* lpfc_debugfs_initialize - Initialize debugfs for a vport
* @vport: The vport pointer to initialize.
*
* Description:
* When Debugfs is configured this routine sets up the lpfc debugfs file system.
* If not already created, this routine will create the lpfc directory, and
* lpfcX directory (for this HBA), and vportX directory for this vport. It will
* also create each file used to access lpfc specific debugfs information.
**/
inline void
lpfc_debugfs_initialize(struct lpfc_vport *vport)
{
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
struct lpfc_hba *phba = vport->phba;
char name[64];
uint32_t num, i;
if (!lpfc_debugfs_enable)
return;
/* Setup lpfc root directory */
if (!lpfc_debugfs_root) {
lpfc_debugfs_root = debugfs_create_dir("lpfc", NULL);
atomic_set(&lpfc_debugfs_hba_count, 0);
if (!lpfc_debugfs_root) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0408 Cannot create debugfs root\n");
goto debug_failed;
}
}
if (!lpfc_debugfs_start_time)
lpfc_debugfs_start_time = jiffies;
/* Setup funcX directory for specific HBA PCI function */
snprintf(name, sizeof(name), "fn%d", phba->brd_no);
if (!phba->hba_debugfs_root) {
phba->hba_debugfs_root =
debugfs_create_dir(name, lpfc_debugfs_root);
if (!phba->hba_debugfs_root) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0412 Cannot create debugfs hba\n");
goto debug_failed;
}
atomic_inc(&lpfc_debugfs_hba_count);
atomic_set(&phba->debugfs_vport_count, 0);
/* Setup hbqinfo */
snprintf(name, sizeof(name), "hbqinfo");
phba->debug_hbqinfo =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_hbqinfo);
if (!phba->debug_hbqinfo) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0411 Cannot create debugfs hbqinfo\n");
goto debug_failed;
}
/* Setup dumpHBASlim */
if (phba->sli_rev < LPFC_SLI_REV4) {
snprintf(name, sizeof(name), "dumpHBASlim");
phba->debug_dumpHBASlim =
debugfs_create_file(name,
S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dumpHBASlim);
if (!phba->debug_dumpHBASlim) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0413 Cannot create debugfs "
"dumpHBASlim\n");
goto debug_failed;
}
} else
phba->debug_dumpHBASlim = NULL;
/* Setup dumpHostSlim */
if (phba->sli_rev < LPFC_SLI_REV4) {
snprintf(name, sizeof(name), "dumpHostSlim");
phba->debug_dumpHostSlim =
debugfs_create_file(name,
S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dumpHostSlim);
if (!phba->debug_dumpHostSlim) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0414 Cannot create debugfs "
"dumpHostSlim\n");
goto debug_failed;
}
} else
phba->debug_dumpHostSlim = NULL;
/* Setup dumpData */
snprintf(name, sizeof(name), "dumpData");
phba->debug_dumpData =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dumpData);
if (!phba->debug_dumpData) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0800 Cannot create debugfs dumpData\n");
goto debug_failed;
}
/* Setup dumpDif */
snprintf(name, sizeof(name), "dumpDif");
phba->debug_dumpDif =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dumpDif);
if (!phba->debug_dumpDif) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0801 Cannot create debugfs dumpDif\n");
goto debug_failed;
}
/* Setup DIF Error Injections */
snprintf(name, sizeof(name), "InjErrLBA");
phba->debug_InjErrLBA =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_InjErrLBA) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0807 Cannot create debugfs InjErrLBA\n");
goto debug_failed;
}
phba->lpfc_injerr_lba = LPFC_INJERR_LBA_OFF;
snprintf(name, sizeof(name), "InjErrNPortID");
phba->debug_InjErrNPortID =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_InjErrNPortID) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0809 Cannot create debugfs InjErrNPortID\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "InjErrWWPN");
phba->debug_InjErrWWPN =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_InjErrWWPN) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0810 Cannot create debugfs InjErrWWPN\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "writeGuardInjErr");
phba->debug_writeGuard =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_writeGuard) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0802 Cannot create debugfs writeGuard\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "writeAppInjErr");
phba->debug_writeApp =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_writeApp) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0803 Cannot create debugfs writeApp\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "writeRefInjErr");
phba->debug_writeRef =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_writeRef) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0804 Cannot create debugfs writeRef\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "readGuardInjErr");
phba->debug_readGuard =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_readGuard) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0808 Cannot create debugfs readGuard\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "readAppInjErr");
phba->debug_readApp =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_readApp) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0805 Cannot create debugfs readApp\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "readRefInjErr");
phba->debug_readRef =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_dif_err);
if (!phba->debug_readRef) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0806 Cannot create debugfs readApp\n");
goto debug_failed;
}
/* Setup slow ring trace */
if (lpfc_debugfs_max_slow_ring_trc) {
num = lpfc_debugfs_max_slow_ring_trc - 1;
if (num & lpfc_debugfs_max_slow_ring_trc) {
/* Change to be a power of 2 */
num = lpfc_debugfs_max_slow_ring_trc;
i = 0;
while (num > 1) {
num = num >> 1;
i++;
}
lpfc_debugfs_max_slow_ring_trc = (1 << i);
printk(KERN_ERR
"lpfc_debugfs_max_disc_trc changed to "
"%d\n", lpfc_debugfs_max_disc_trc);
}
}
snprintf(name, sizeof(name), "slow_ring_trace");
phba->debug_slow_ring_trc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->hba_debugfs_root,
phba, &lpfc_debugfs_op_slow_ring_trc);
if (!phba->debug_slow_ring_trc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0415 Cannot create debugfs "
"slow_ring_trace\n");
goto debug_failed;
}
if (!phba->slow_ring_trc) {
phba->slow_ring_trc = kmalloc(
(sizeof(struct lpfc_debugfs_trc) *
lpfc_debugfs_max_slow_ring_trc),
GFP_KERNEL);
if (!phba->slow_ring_trc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0416 Cannot create debugfs "
"slow_ring buffer\n");
goto debug_failed;
}
atomic_set(&phba->slow_ring_trc_cnt, 0);
memset(phba->slow_ring_trc, 0,
(sizeof(struct lpfc_debugfs_trc) *
lpfc_debugfs_max_slow_ring_trc));
}
}
snprintf(name, sizeof(name), "vport%d", vport->vpi);
if (!vport->vport_debugfs_root) {
vport->vport_debugfs_root =
debugfs_create_dir(name, phba->hba_debugfs_root);
if (!vport->vport_debugfs_root) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0417 Can't create debugfs\n");
goto debug_failed;
}
atomic_inc(&phba->debugfs_vport_count);
}
if (lpfc_debugfs_max_disc_trc) {
num = lpfc_debugfs_max_disc_trc - 1;
if (num & lpfc_debugfs_max_disc_trc) {
/* Change to be a power of 2 */
num = lpfc_debugfs_max_disc_trc;
i = 0;
while (num > 1) {
num = num >> 1;
i++;
}
lpfc_debugfs_max_disc_trc = (1 << i);
printk(KERN_ERR
"lpfc_debugfs_max_disc_trc changed to %d\n",
lpfc_debugfs_max_disc_trc);
}
}
vport->disc_trc = kzalloc(
(sizeof(struct lpfc_debugfs_trc) * lpfc_debugfs_max_disc_trc),
GFP_KERNEL);
if (!vport->disc_trc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0418 Cannot create debugfs disc trace "
"buffer\n");
goto debug_failed;
}
atomic_set(&vport->disc_trc_cnt, 0);
snprintf(name, sizeof(name), "discovery_trace");
vport->debug_disc_trc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
vport->vport_debugfs_root,
vport, &lpfc_debugfs_op_disc_trc);
if (!vport->debug_disc_trc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"0419 Cannot create debugfs "
"discovery_trace\n");
goto debug_failed;
}
snprintf(name, sizeof(name), "nodelist");
vport->debug_nodelist =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
vport->vport_debugfs_root,
vport, &lpfc_debugfs_op_nodelist);
if (!vport->debug_nodelist) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2985 Can't create debugfs nodelist\n");
goto debug_failed;
}
/*
* iDiag debugfs root entry points for SLI4 device only
*/
if (phba->sli_rev < LPFC_SLI_REV4)
goto debug_failed;
snprintf(name, sizeof(name), "iDiag");
if (!phba->idiag_root) {
phba->idiag_root =
debugfs_create_dir(name, phba->hba_debugfs_root);
if (!phba->idiag_root) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2922 Can't create idiag debugfs\n");
goto debug_failed;
}
/* Initialize iDiag data structure */
memset(&idiag, 0, sizeof(idiag));
}
/* iDiag read PCI config space */
snprintf(name, sizeof(name), "pciCfg");
if (!phba->idiag_pci_cfg) {
phba->idiag_pci_cfg =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba, &lpfc_idiag_op_pciCfg);
if (!phba->idiag_pci_cfg) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2923 Can't create idiag debugfs\n");
goto debug_failed;
}
idiag.offset.last_rd = 0;
}
/* iDiag PCI BAR access */
snprintf(name, sizeof(name), "barAcc");
if (!phba->idiag_bar_acc) {
phba->idiag_bar_acc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba, &lpfc_idiag_op_barAcc);
if (!phba->idiag_bar_acc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"3056 Can't create idiag debugfs\n");
goto debug_failed;
}
idiag.offset.last_rd = 0;
}
/* iDiag get PCI function queue information */
snprintf(name, sizeof(name), "queInfo");
if (!phba->idiag_que_info) {
phba->idiag_que_info =
debugfs_create_file(name, S_IFREG|S_IRUGO,
phba->idiag_root, phba, &lpfc_idiag_op_queInfo);
if (!phba->idiag_que_info) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2924 Can't create idiag debugfs\n");
goto debug_failed;
}
}
/* iDiag access PCI function queue */
snprintf(name, sizeof(name), "queAcc");
if (!phba->idiag_que_acc) {
phba->idiag_que_acc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba, &lpfc_idiag_op_queAcc);
if (!phba->idiag_que_acc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2926 Can't create idiag debugfs\n");
goto debug_failed;
}
}
/* iDiag access PCI function doorbell registers */
snprintf(name, sizeof(name), "drbAcc");
if (!phba->idiag_drb_acc) {
phba->idiag_drb_acc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba, &lpfc_idiag_op_drbAcc);
if (!phba->idiag_drb_acc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2927 Can't create idiag debugfs\n");
goto debug_failed;
}
}
/* iDiag access PCI function control registers */
snprintf(name, sizeof(name), "ctlAcc");
if (!phba->idiag_ctl_acc) {
phba->idiag_ctl_acc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba, &lpfc_idiag_op_ctlAcc);
if (!phba->idiag_ctl_acc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2981 Can't create idiag debugfs\n");
goto debug_failed;
}
}
/* iDiag access mbox commands */
snprintf(name, sizeof(name), "mbxAcc");
if (!phba->idiag_mbx_acc) {
phba->idiag_mbx_acc =
debugfs_create_file(name, S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba, &lpfc_idiag_op_mbxAcc);
if (!phba->idiag_mbx_acc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2980 Can't create idiag debugfs\n");
goto debug_failed;
}
}
/* iDiag extents access commands */
if (phba->sli4_hba.extents_in_use) {
snprintf(name, sizeof(name), "extAcc");
if (!phba->idiag_ext_acc) {
phba->idiag_ext_acc =
debugfs_create_file(name,
S_IFREG|S_IRUGO|S_IWUSR,
phba->idiag_root, phba,
&lpfc_idiag_op_extAcc);
if (!phba->idiag_ext_acc) {
lpfc_printf_vlog(vport, KERN_ERR, LOG_INIT,
"2986 Cant create "
"idiag debugfs\n");
goto debug_failed;
}
}
}
debug_failed:
return;
#endif
}
/**
* lpfc_debugfs_terminate - Tear down debugfs infrastructure for this vport
* @vport: The vport pointer to remove from debugfs.
*
* Description:
* When Debugfs is configured this routine removes debugfs file system elements
* that are specific to this vport. It also checks to see if there are any
* users left for the debugfs directories associated with the HBA and driver. If
* this is the last user of the HBA directory or driver directory then it will
* remove those from the debugfs infrastructure as well.
**/
inline void
lpfc_debugfs_terminate(struct lpfc_vport *vport)
{
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
struct lpfc_hba *phba = vport->phba;
if (vport->disc_trc) {
kfree(vport->disc_trc);
vport->disc_trc = NULL;
}
if (vport->debug_disc_trc) {
debugfs_remove(vport->debug_disc_trc); /* discovery_trace */
vport->debug_disc_trc = NULL;
}
if (vport->debug_nodelist) {
debugfs_remove(vport->debug_nodelist); /* nodelist */
vport->debug_nodelist = NULL;
}
if (vport->vport_debugfs_root) {
debugfs_remove(vport->vport_debugfs_root); /* vportX */
vport->vport_debugfs_root = NULL;
atomic_dec(&phba->debugfs_vport_count);
}
if (atomic_read(&phba->debugfs_vport_count) == 0) {
if (phba->debug_hbqinfo) {
debugfs_remove(phba->debug_hbqinfo); /* hbqinfo */
phba->debug_hbqinfo = NULL;
}
if (phba->debug_dumpHBASlim) {
debugfs_remove(phba->debug_dumpHBASlim); /* HBASlim */
phba->debug_dumpHBASlim = NULL;
}
if (phba->debug_dumpHostSlim) {
debugfs_remove(phba->debug_dumpHostSlim); /* HostSlim */
phba->debug_dumpHostSlim = NULL;
}
if (phba->debug_dumpData) {
debugfs_remove(phba->debug_dumpData); /* dumpData */
phba->debug_dumpData = NULL;
}
if (phba->debug_dumpDif) {
debugfs_remove(phba->debug_dumpDif); /* dumpDif */
phba->debug_dumpDif = NULL;
}
if (phba->debug_InjErrLBA) {
debugfs_remove(phba->debug_InjErrLBA); /* InjErrLBA */
phba->debug_InjErrLBA = NULL;
}
if (phba->debug_InjErrNPortID) { /* InjErrNPortID */
debugfs_remove(phba->debug_InjErrNPortID);
phba->debug_InjErrNPortID = NULL;
}
if (phba->debug_InjErrWWPN) {
debugfs_remove(phba->debug_InjErrWWPN); /* InjErrWWPN */
phba->debug_InjErrWWPN = NULL;
}
if (phba->debug_writeGuard) {
debugfs_remove(phba->debug_writeGuard); /* writeGuard */
phba->debug_writeGuard = NULL;
}
if (phba->debug_writeApp) {
debugfs_remove(phba->debug_writeApp); /* writeApp */
phba->debug_writeApp = NULL;
}
if (phba->debug_writeRef) {
debugfs_remove(phba->debug_writeRef); /* writeRef */
phba->debug_writeRef = NULL;
}
if (phba->debug_readGuard) {
debugfs_remove(phba->debug_readGuard); /* readGuard */
phba->debug_readGuard = NULL;
}
if (phba->debug_readApp) {
debugfs_remove(phba->debug_readApp); /* readApp */
phba->debug_readApp = NULL;
}
if (phba->debug_readRef) {
debugfs_remove(phba->debug_readRef); /* readRef */
phba->debug_readRef = NULL;
}
if (phba->slow_ring_trc) {
kfree(phba->slow_ring_trc);
phba->slow_ring_trc = NULL;
}
if (phba->debug_slow_ring_trc) {
/* slow_ring_trace */
debugfs_remove(phba->debug_slow_ring_trc);
phba->debug_slow_ring_trc = NULL;
}
/*
* iDiag release
*/
if (phba->sli_rev == LPFC_SLI_REV4) {
if (phba->idiag_ext_acc) {
/* iDiag extAcc */
debugfs_remove(phba->idiag_ext_acc);
phba->idiag_ext_acc = NULL;
}
if (phba->idiag_mbx_acc) {
/* iDiag mbxAcc */
debugfs_remove(phba->idiag_mbx_acc);
phba->idiag_mbx_acc = NULL;
}
if (phba->idiag_ctl_acc) {
/* iDiag ctlAcc */
debugfs_remove(phba->idiag_ctl_acc);
phba->idiag_ctl_acc = NULL;
}
if (phba->idiag_drb_acc) {
/* iDiag drbAcc */
debugfs_remove(phba->idiag_drb_acc);
phba->idiag_drb_acc = NULL;
}
if (phba->idiag_que_acc) {
/* iDiag queAcc */
debugfs_remove(phba->idiag_que_acc);
phba->idiag_que_acc = NULL;
}
if (phba->idiag_que_info) {
/* iDiag queInfo */
debugfs_remove(phba->idiag_que_info);
phba->idiag_que_info = NULL;
}
if (phba->idiag_bar_acc) {
/* iDiag barAcc */
debugfs_remove(phba->idiag_bar_acc);
phba->idiag_bar_acc = NULL;
}
if (phba->idiag_pci_cfg) {
/* iDiag pciCfg */
debugfs_remove(phba->idiag_pci_cfg);
phba->idiag_pci_cfg = NULL;
}
/* Finally remove the iDiag debugfs root */
if (phba->idiag_root) {
/* iDiag root */
debugfs_remove(phba->idiag_root);
phba->idiag_root = NULL;
}
}
if (phba->hba_debugfs_root) {
debugfs_remove(phba->hba_debugfs_root); /* fnX */
phba->hba_debugfs_root = NULL;
atomic_dec(&lpfc_debugfs_hba_count);
}
if (atomic_read(&lpfc_debugfs_hba_count) == 0) {
debugfs_remove(lpfc_debugfs_root); /* lpfc */
lpfc_debugfs_root = NULL;
}
}
#endif
return;
}
/*
* Driver debug utility routines outside of debugfs. The debug utility
* routines implemented here is intended to be used in the instrumented
* debug driver for debugging host or port issues.
*/
/**
* lpfc_debug_dump_all_queues - dump all the queues with a hba
* @phba: Pointer to HBA context object.
*
* This function dumps entries of all the queues asociated with the @phba.
**/
void
lpfc_debug_dump_all_queues(struct lpfc_hba *phba)
{
int fcp_wqidx;
/*
* Dump Work Queues (WQs)
*/
lpfc_debug_dump_mbx_wq(phba);
lpfc_debug_dump_els_wq(phba);
for (fcp_wqidx = 0; fcp_wqidx < phba->cfg_fcp_io_channel; fcp_wqidx++)
lpfc_debug_dump_fcp_wq(phba, fcp_wqidx);
lpfc_debug_dump_hdr_rq(phba);
lpfc_debug_dump_dat_rq(phba);
/*
* Dump Complete Queues (CQs)
*/
lpfc_debug_dump_mbx_cq(phba);
lpfc_debug_dump_els_cq(phba);
for (fcp_wqidx = 0; fcp_wqidx < phba->cfg_fcp_io_channel; fcp_wqidx++)
lpfc_debug_dump_fcp_cq(phba, fcp_wqidx);
/*
* Dump Event Queues (EQs)
*/
for (fcp_wqidx = 0; fcp_wqidx < phba->cfg_fcp_io_channel; fcp_wqidx++)
lpfc_debug_dump_hba_eq(phba, fcp_wqidx);
}
| gpl-2.0 |
GuneetAtwal/kernel_g900f | drivers/pci/remove.c | 1518 | 4520 | #include <linux/pci.h>
#include <linux/module.h>
#include <linux/pci-aspm.h>
#include "pci.h"
static void pci_free_resources(struct pci_dev *dev)
{
int i;
msi_remove_pci_irq_vectors(dev);
pci_cleanup_rom(dev);
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
struct resource *res = dev->resource + i;
if (res->parent)
release_resource(res);
}
}
static void pci_stop_dev(struct pci_dev *dev)
{
pci_pme_active(dev, false);
if (dev->is_added) {
pci_proc_detach_device(dev);
pci_remove_sysfs_dev_files(dev);
device_unregister(&dev->dev);
dev->is_added = 0;
}
if (dev->bus->self)
pcie_aspm_exit_link_state(dev);
}
static void pci_destroy_dev(struct pci_dev *dev)
{
/* Remove the device from the device lists, and prevent any further
* list accesses from this device */
down_write(&pci_bus_sem);
list_del(&dev->bus_list);
dev->bus_list.next = dev->bus_list.prev = NULL;
up_write(&pci_bus_sem);
pci_free_resources(dev);
pci_dev_put(dev);
}
/**
* pci_remove_device_safe - remove an unused hotplug device
* @dev: the device to remove
*
* Delete the device structure from the device lists and
* notify userspace (/sbin/hotplug), but only if the device
* in question is not being used by a driver.
* Returns 0 on success.
*/
#if 0
int pci_remove_device_safe(struct pci_dev *dev)
{
if (pci_dev_driver(dev))
return -EBUSY;
pci_destroy_dev(dev);
return 0;
}
#endif /* 0 */
void pci_remove_bus(struct pci_bus *pci_bus)
{
pci_proc_detach_bus(pci_bus);
down_write(&pci_bus_sem);
list_del(&pci_bus->node);
up_write(&pci_bus_sem);
if (!pci_bus->is_added)
return;
pci_remove_legacy_files(pci_bus);
device_unregister(&pci_bus->dev);
}
EXPORT_SYMBOL(pci_remove_bus);
static void __pci_remove_behind_bridge(struct pci_dev *dev);
/**
* pci_stop_and_remove_bus_device - remove a PCI device and any children
* @dev: the device to remove
*
* Remove a PCI device from the device lists, informing the drivers
* that the device has been removed. We also remove any subordinate
* buses and children in a depth-first manner.
*
* For each device we remove, delete the device structure from the
* device lists, remove the /proc entry, and notify userspace
* (/sbin/hotplug).
*/
void __pci_remove_bus_device(struct pci_dev *dev)
{
if (dev->subordinate) {
struct pci_bus *b = dev->subordinate;
__pci_remove_behind_bridge(dev);
pci_remove_bus(b);
dev->subordinate = NULL;
}
pci_destroy_dev(dev);
}
EXPORT_SYMBOL(__pci_remove_bus_device);
void pci_stop_and_remove_bus_device(struct pci_dev *dev)
{
pci_stop_bus_device(dev);
__pci_remove_bus_device(dev);
}
static void __pci_remove_behind_bridge(struct pci_dev *dev)
{
struct list_head *l, *n;
if (dev->subordinate)
list_for_each_safe(l, n, &dev->subordinate->devices)
__pci_remove_bus_device(pci_dev_b(l));
}
static void pci_stop_behind_bridge(struct pci_dev *dev)
{
struct list_head *l, *n;
if (dev->subordinate)
list_for_each_safe(l, n, &dev->subordinate->devices)
pci_stop_bus_device(pci_dev_b(l));
}
/**
* pci_stop_and_remove_behind_bridge - stop and remove all devices behind
* a PCI bridge
* @dev: PCI bridge device
*
* Remove all devices on the bus, except for the parent bridge.
* This also removes any child buses, and any devices they may
* contain in a depth-first manner.
*/
void pci_stop_and_remove_behind_bridge(struct pci_dev *dev)
{
pci_stop_behind_bridge(dev);
__pci_remove_behind_bridge(dev);
}
static void pci_stop_bus_devices(struct pci_bus *bus)
{
struct list_head *l, *n;
/*
* VFs could be removed by pci_stop_and_remove_bus_device() in the
* pci_stop_bus_devices() code path for PF.
* aka, bus->devices get updated in the process.
* but VFs are inserted after PFs when SRIOV is enabled for PF,
* We can iterate the list backwards to get prev valid PF instead
* of removed VF.
*/
list_for_each_prev_safe(l, n, &bus->devices) {
struct pci_dev *dev = pci_dev_b(l);
pci_stop_bus_device(dev);
}
}
/**
* pci_stop_bus_device - stop a PCI device and any children
* @dev: the device to stop
*
* Stop a PCI device (detach the driver, remove from the global list
* and so on). This also stop any subordinate buses and children in a
* depth-first manner.
*/
void pci_stop_bus_device(struct pci_dev *dev)
{
if (dev->subordinate)
pci_stop_bus_devices(dev->subordinate);
pci_stop_dev(dev);
}
EXPORT_SYMBOL(pci_stop_and_remove_bus_device);
EXPORT_SYMBOL(pci_stop_and_remove_behind_bridge);
EXPORT_SYMBOL_GPL(pci_stop_bus_device);
| gpl-2.0 |
turuchan/ISW11SC_ICS_Kernel | fs/proc/meminfo.c | 1518 | 4967 | #include <linux/fs.h>
#include <linux/hugetlb.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/mmzone.h>
#include <linux/proc_fs.h>
#include <linux/quicklist.h>
#include <linux/seq_file.h>
#include <linux/swap.h>
#include <linux/vmstat.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include "internal.h"
void __attribute__((weak)) arch_report_meminfo(struct seq_file *m)
{
}
static int meminfo_proc_show(struct seq_file *m, void *v)
{
struct sysinfo i;
unsigned long committed;
unsigned long allowed;
struct vmalloc_info vmi;
long cached;
unsigned long pages[NR_LRU_LISTS];
int lru;
/*
* display in kilobytes.
*/
#define K(x) ((x) << (PAGE_SHIFT - 10))
si_meminfo(&i);
si_swapinfo(&i);
committed = percpu_counter_read_positive(&vm_committed_as);
allowed = ((totalram_pages - hugetlb_total_pages())
* sysctl_overcommit_ratio / 100) + total_swap_pages;
cached = global_page_state(NR_FILE_PAGES) -
total_swapcache_pages - i.bufferram;
if (cached < 0)
cached = 0;
get_vmalloc_info(&vmi);
for (lru = LRU_BASE; lru < NR_LRU_LISTS; lru++)
pages[lru] = global_page_state(NR_LRU_BASE + lru);
/*
* Tagged format, for easy grepping and expansion.
*/
seq_printf(m,
"MemTotal: %8lu kB\n"
"MemFree: %8lu kB\n"
"Buffers: %8lu kB\n"
"Cached: %8lu kB\n"
"SwapCached: %8lu kB\n"
"Active: %8lu kB\n"
"Inactive: %8lu kB\n"
"Active(anon): %8lu kB\n"
"Inactive(anon): %8lu kB\n"
"Active(file): %8lu kB\n"
"Inactive(file): %8lu kB\n"
"Unevictable: %8lu kB\n"
"Mlocked: %8lu kB\n"
#ifdef CONFIG_HIGHMEM
"HighTotal: %8lu kB\n"
"HighFree: %8lu kB\n"
"LowTotal: %8lu kB\n"
"LowFree: %8lu kB\n"
#endif
#ifndef CONFIG_MMU
"MmapCopy: %8lu kB\n"
#endif
"SwapTotal: %8lu kB\n"
"SwapFree: %8lu kB\n"
"Dirty: %8lu kB\n"
"Writeback: %8lu kB\n"
"AnonPages: %8lu kB\n"
"Mapped: %8lu kB\n"
"Shmem: %8lu kB\n"
"Slab: %8lu kB\n"
"SReclaimable: %8lu kB\n"
"SUnreclaim: %8lu kB\n"
"KernelStack: %8lu kB\n"
"PageTables: %8lu kB\n"
#ifdef CONFIG_QUICKLIST
"Quicklists: %8lu kB\n"
#endif
"NFS_Unstable: %8lu kB\n"
"Bounce: %8lu kB\n"
"WritebackTmp: %8lu kB\n"
"CommitLimit: %8lu kB\n"
"Committed_AS: %8lu kB\n"
"VmallocTotal: %8lu kB\n"
"VmallocUsed: %8lu kB\n"
"VmallocChunk: %8lu kB\n"
#ifdef CONFIG_MEMORY_FAILURE
"HardwareCorrupted: %5lu kB\n"
#endif
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
"AnonHugePages: %8lu kB\n"
#endif
,
K(i.totalram),
K(i.freeram),
K(i.bufferram),
K(cached),
K(total_swapcache_pages),
K(pages[LRU_ACTIVE_ANON] + pages[LRU_ACTIVE_FILE]),
K(pages[LRU_INACTIVE_ANON] + pages[LRU_INACTIVE_FILE]),
K(pages[LRU_ACTIVE_ANON]),
K(pages[LRU_INACTIVE_ANON]),
K(pages[LRU_ACTIVE_FILE]),
K(pages[LRU_INACTIVE_FILE]),
K(pages[LRU_UNEVICTABLE]),
K(global_page_state(NR_MLOCK)),
#ifdef CONFIG_HIGHMEM
K(i.totalhigh),
K(i.freehigh),
K(i.totalram-i.totalhigh),
K(i.freeram-i.freehigh),
#endif
#ifndef CONFIG_MMU
K((unsigned long) atomic_long_read(&mmap_pages_allocated)),
#endif
K(i.totalswap),
K(i.freeswap),
K(global_page_state(NR_FILE_DIRTY)),
K(global_page_state(NR_WRITEBACK)),
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
K(global_page_state(NR_ANON_PAGES)
+ global_page_state(NR_ANON_TRANSPARENT_HUGEPAGES) *
HPAGE_PMD_NR),
#else
K(global_page_state(NR_ANON_PAGES)),
#endif
K(global_page_state(NR_FILE_MAPPED)),
K(global_page_state(NR_SHMEM)),
K(global_page_state(NR_SLAB_RECLAIMABLE) +
global_page_state(NR_SLAB_UNRECLAIMABLE)),
K(global_page_state(NR_SLAB_RECLAIMABLE)),
K(global_page_state(NR_SLAB_UNRECLAIMABLE)),
global_page_state(NR_KERNEL_STACK) * THREAD_SIZE / 1024,
K(global_page_state(NR_PAGETABLE)),
#ifdef CONFIG_QUICKLIST
K(quicklist_total_size()),
#endif
K(global_page_state(NR_UNSTABLE_NFS)),
K(global_page_state(NR_BOUNCE)),
K(global_page_state(NR_WRITEBACK_TEMP)),
K(allowed),
K(committed),
(unsigned long)VMALLOC_TOTAL >> 10,
vmi.used >> 10,
vmi.largest_chunk >> 10
#ifdef CONFIG_MEMORY_FAILURE
,atomic_long_read(&mce_bad_pages) << (PAGE_SHIFT - 10)
#endif
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
,K(global_page_state(NR_ANON_TRANSPARENT_HUGEPAGES) *
HPAGE_PMD_NR)
#endif
);
hugetlb_report_meminfo(m);
arch_report_meminfo(m);
return 0;
#undef K
}
static int meminfo_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, meminfo_proc_show, NULL);
}
static const struct file_operations meminfo_proc_fops = {
.open = meminfo_proc_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init proc_meminfo_init(void)
{
proc_create("meminfo", 0, NULL, &meminfo_proc_fops);
return 0;
}
module_init(proc_meminfo_init);
| gpl-2.0 |
theme/linux | drivers/isdn/i4l/isdn_common.c | 1774 | 58043 | /* $Id: isdn_common.c,v 1.1.2.3 2004/02/10 01:07:13 keil Exp $
*
* Linux ISDN subsystem, common used functions (linklevel).
*
* Copyright 1994-1999 by Fritz Elfert (fritz@isdn4linux.de)
* Copyright 1995,96 Thinking Objects Software GmbH Wuerzburg
* Copyright 1995,96 by Michael Hipp (Michael.Hipp@student.uni-tuebingen.de)
*
* This software may be used and distributed according to the terms
* of the GNU General Public License, incorporated herein by reference.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/isdn.h>
#include <linux/mutex.h>
#include "isdn_common.h"
#include "isdn_tty.h"
#include "isdn_net.h"
#include "isdn_ppp.h"
#ifdef CONFIG_ISDN_AUDIO
#include "isdn_audio.h"
#endif
#ifdef CONFIG_ISDN_DIVERSION_MODULE
#define CONFIG_ISDN_DIVERSION
#endif
#ifdef CONFIG_ISDN_DIVERSION
#include <linux/isdn_divertif.h>
#endif /* CONFIG_ISDN_DIVERSION */
#include "isdn_v110.h"
/* Debugflags */
#undef ISDN_DEBUG_STATCALLB
MODULE_DESCRIPTION("ISDN4Linux: link layer");
MODULE_AUTHOR("Fritz Elfert");
MODULE_LICENSE("GPL");
isdn_dev *dev;
static DEFINE_MUTEX(isdn_mutex);
static char *isdn_revision = "$Revision: 1.1.2.3 $";
extern char *isdn_net_revision;
#ifdef CONFIG_ISDN_PPP
extern char *isdn_ppp_revision;
#else
static char *isdn_ppp_revision = ": none $";
#endif
#ifdef CONFIG_ISDN_AUDIO
extern char *isdn_audio_revision;
#else
static char *isdn_audio_revision = ": none $";
#endif
extern char *isdn_v110_revision;
#ifdef CONFIG_ISDN_DIVERSION
static isdn_divert_if *divert_if; /* = NULL */
#endif /* CONFIG_ISDN_DIVERSION */
static int isdn_writebuf_stub(int, int, const u_char __user *, int);
static void set_global_features(void);
static int isdn_wildmat(char *s, char *p);
static int isdn_add_channels(isdn_driver_t *d, int drvidx, int n, int adding);
static inline void
isdn_lock_driver(isdn_driver_t *drv)
{
try_module_get(drv->interface->owner);
drv->locks++;
}
void
isdn_lock_drivers(void)
{
int i;
for (i = 0; i < ISDN_MAX_DRIVERS; i++) {
if (!dev->drv[i])
continue;
isdn_lock_driver(dev->drv[i]);
}
}
static inline void
isdn_unlock_driver(isdn_driver_t *drv)
{
if (drv->locks > 0) {
drv->locks--;
module_put(drv->interface->owner);
}
}
void
isdn_unlock_drivers(void)
{
int i;
for (i = 0; i < ISDN_MAX_DRIVERS; i++) {
if (!dev->drv[i])
continue;
isdn_unlock_driver(dev->drv[i]);
}
}
#if defined(ISDN_DEBUG_NET_DUMP) || defined(ISDN_DEBUG_MODEM_DUMP)
void
isdn_dumppkt(char *s, u_char *p, int len, int dumplen)
{
int dumpc;
printk(KERN_DEBUG "%s(%d) ", s, len);
for (dumpc = 0; (dumpc < dumplen) && (len); len--, dumpc++)
printk(" %02x", *p++);
printk("\n");
}
#endif
/*
* I picked the pattern-matching-functions from an old GNU-tar version (1.10)
* It was originally written and put to PD by rs@mirror.TMC.COM (Rich Salz)
*/
static int
isdn_star(char *s, char *p)
{
while (isdn_wildmat(s, p)) {
if (*++s == '\0')
return (2);
}
return (0);
}
/*
* Shell-type Pattern-matching for incoming caller-Ids
* This function gets a string in s and checks, if it matches the pattern
* given in p.
*
* Return:
* 0 = match.
* 1 = no match.
* 2 = no match. Would eventually match, if s would be longer.
*
* Possible Patterns:
*
* '?' matches one character
* '*' matches zero or more characters
* [xyz] matches the set of characters in brackets.
* [^xyz] matches any single character not in the set of characters
*/
static int
isdn_wildmat(char *s, char *p)
{
register int last;
register int matched;
register int reverse;
register int nostar = 1;
if (!(*s) && !(*p))
return (1);
for (; *p; s++, p++)
switch (*p) {
case '\\':
/*
* Literal match with following character,
* fall through.
*/
p++;
default:
if (*s != *p)
return (*s == '\0') ? 2 : 1;
continue;
case '?':
/* Match anything. */
if (*s == '\0')
return (2);
continue;
case '*':
nostar = 0;
/* Trailing star matches everything. */
return (*++p ? isdn_star(s, p) : 0);
case '[':
/* [^....] means inverse character class. */
if ((reverse = (p[1] == '^')))
p++;
for (last = 0, matched = 0; *++p && (*p != ']'); last = *p)
/* This next line requires a good C compiler. */
if (*p == '-' ? *s <= *++p && *s >= last : *s == *p)
matched = 1;
if (matched == reverse)
return (1);
continue;
}
return (*s == '\0') ? 0 : nostar;
}
int isdn_msncmp(const char *msn1, const char *msn2)
{
char TmpMsn1[ISDN_MSNLEN];
char TmpMsn2[ISDN_MSNLEN];
char *p;
for (p = TmpMsn1; *msn1 && *msn1 != ':';) // Strip off a SPID
*p++ = *msn1++;
*p = '\0';
for (p = TmpMsn2; *msn2 && *msn2 != ':';) // Strip off a SPID
*p++ = *msn2++;
*p = '\0';
return isdn_wildmat(TmpMsn1, TmpMsn2);
}
int
isdn_dc2minor(int di, int ch)
{
int i;
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if (dev->chanmap[i] == ch && dev->drvmap[i] == di)
return i;
return -1;
}
static int isdn_timer_cnt1 = 0;
static int isdn_timer_cnt2 = 0;
static int isdn_timer_cnt3 = 0;
static void
isdn_timer_funct(ulong dummy)
{
int tf = dev->tflags;
if (tf & ISDN_TIMER_FAST) {
if (tf & ISDN_TIMER_MODEMREAD)
isdn_tty_readmodem();
if (tf & ISDN_TIMER_MODEMPLUS)
isdn_tty_modem_escape();
if (tf & ISDN_TIMER_MODEMXMIT)
isdn_tty_modem_xmit();
}
if (tf & ISDN_TIMER_SLOW) {
if (++isdn_timer_cnt1 >= ISDN_TIMER_02SEC) {
isdn_timer_cnt1 = 0;
if (tf & ISDN_TIMER_NETDIAL)
isdn_net_dial();
}
if (++isdn_timer_cnt2 >= ISDN_TIMER_1SEC) {
isdn_timer_cnt2 = 0;
if (tf & ISDN_TIMER_NETHANGUP)
isdn_net_autohup();
if (++isdn_timer_cnt3 >= ISDN_TIMER_RINGING) {
isdn_timer_cnt3 = 0;
if (tf & ISDN_TIMER_MODEMRING)
isdn_tty_modem_ring();
}
if (tf & ISDN_TIMER_CARRIER)
isdn_tty_carrier_timeout();
}
}
if (tf)
mod_timer(&dev->timer, jiffies + ISDN_TIMER_RES);
}
void
isdn_timer_ctrl(int tf, int onoff)
{
unsigned long flags;
int old_tflags;
spin_lock_irqsave(&dev->timerlock, flags);
if ((tf & ISDN_TIMER_SLOW) && (!(dev->tflags & ISDN_TIMER_SLOW))) {
/* If the slow-timer wasn't activated until now */
isdn_timer_cnt1 = 0;
isdn_timer_cnt2 = 0;
}
old_tflags = dev->tflags;
if (onoff)
dev->tflags |= tf;
else
dev->tflags &= ~tf;
if (dev->tflags && !old_tflags)
mod_timer(&dev->timer, jiffies + ISDN_TIMER_RES);
spin_unlock_irqrestore(&dev->timerlock, flags);
}
/*
* Receive a packet from B-Channel. (Called from low-level-module)
*/
static void
isdn_receive_skb_callback(int di, int channel, struct sk_buff *skb)
{
int i;
if ((i = isdn_dc2minor(di, channel)) == -1) {
dev_kfree_skb(skb);
return;
}
/* Update statistics */
dev->ibytes[i] += skb->len;
/* First, try to deliver data to network-device */
if (isdn_net_rcv_skb(i, skb))
return;
/* V.110 handling
* makes sense for async streams only, so it is
* called after possible net-device delivery.
*/
if (dev->v110[i]) {
atomic_inc(&dev->v110use[i]);
skb = isdn_v110_decode(dev->v110[i], skb);
atomic_dec(&dev->v110use[i]);
if (!skb)
return;
}
/* No network-device found, deliver to tty or raw-channel */
if (skb->len) {
if (isdn_tty_rcv_skb(i, di, channel, skb))
return;
wake_up_interruptible(&dev->drv[di]->rcv_waitq[channel]);
} else
dev_kfree_skb(skb);
}
/*
* Intercept command from Linklevel to Lowlevel.
* If layer 2 protocol is V.110 and this is not supported by current
* lowlevel-driver, use driver's transparent mode and handle V.110 in
* linklevel instead.
*/
int
isdn_command(isdn_ctrl *cmd)
{
if (cmd->driver == -1) {
printk(KERN_WARNING "isdn_command command(%x) driver -1\n", cmd->command);
return (1);
}
if (!dev->drv[cmd->driver]) {
printk(KERN_WARNING "isdn_command command(%x) dev->drv[%d] NULL\n",
cmd->command, cmd->driver);
return (1);
}
if (!dev->drv[cmd->driver]->interface) {
printk(KERN_WARNING "isdn_command command(%x) dev->drv[%d]->interface NULL\n",
cmd->command, cmd->driver);
return (1);
}
if (cmd->command == ISDN_CMD_SETL2) {
int idx = isdn_dc2minor(cmd->driver, cmd->arg & 255);
unsigned long l2prot = (cmd->arg >> 8) & 255;
unsigned long features = (dev->drv[cmd->driver]->interface->features
>> ISDN_FEATURE_L2_SHIFT) &
ISDN_FEATURE_L2_MASK;
unsigned long l2_feature = (1 << l2prot);
switch (l2prot) {
case ISDN_PROTO_L2_V11096:
case ISDN_PROTO_L2_V11019:
case ISDN_PROTO_L2_V11038:
/* If V.110 requested, but not supported by
* HL-driver, set emulator-flag and change
* Layer-2 to transparent
*/
if (!(features & l2_feature)) {
dev->v110emu[idx] = l2prot;
cmd->arg = (cmd->arg & 255) |
(ISDN_PROTO_L2_TRANS << 8);
} else
dev->v110emu[idx] = 0;
}
}
return dev->drv[cmd->driver]->interface->command(cmd);
}
void
isdn_all_eaz(int di, int ch)
{
isdn_ctrl cmd;
if (di < 0)
return;
cmd.driver = di;
cmd.arg = ch;
cmd.command = ISDN_CMD_SETEAZ;
cmd.parm.num[0] = '\0';
isdn_command(&cmd);
}
/*
* Begin of a CAPI like LL<->HL interface, currently used only for
* supplementary service (CAPI 2.0 part III)
*/
#include <linux/isdn/capicmd.h>
static int
isdn_capi_rec_hl_msg(capi_msg *cm)
{
switch (cm->Command) {
case CAPI_FACILITY:
/* in the moment only handled in tty */
return (isdn_tty_capi_facility(cm));
default:
return (-1);
}
}
static int
isdn_status_callback(isdn_ctrl *c)
{
int di;
u_long flags;
int i;
int r;
int retval = 0;
isdn_ctrl cmd;
isdn_net_dev *p;
di = c->driver;
i = isdn_dc2minor(di, c->arg);
switch (c->command) {
case ISDN_STAT_BSENT:
if (i < 0)
return -1;
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
if (isdn_net_stat_callback(i, c))
return 0;
if (isdn_v110_stat_callback(i, c))
return 0;
if (isdn_tty_stat_callback(i, c))
return 0;
wake_up_interruptible(&dev->drv[di]->snd_waitq[c->arg]);
break;
case ISDN_STAT_STAVAIL:
dev->drv[di]->stavail += c->arg;
wake_up_interruptible(&dev->drv[di]->st_waitq);
break;
case ISDN_STAT_RUN:
dev->drv[di]->flags |= DRV_FLAG_RUNNING;
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if (dev->drvmap[i] == di)
isdn_all_eaz(di, dev->chanmap[i]);
set_global_features();
break;
case ISDN_STAT_STOP:
dev->drv[di]->flags &= ~DRV_FLAG_RUNNING;
break;
case ISDN_STAT_ICALL:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "ICALL (net): %d %ld %s\n", di, c->arg, c->parm.num);
#endif
if (dev->global_flags & ISDN_GLOBAL_STOPPED) {
cmd.driver = di;
cmd.arg = c->arg;
cmd.command = ISDN_CMD_HANGUP;
isdn_command(&cmd);
return 0;
}
/* Try to find a network-interface which will accept incoming call */
r = ((c->command == ISDN_STAT_ICALLW) ? 0 : isdn_net_find_icall(di, c->arg, i, &c->parm.setup));
switch (r) {
case 0:
/* No network-device replies.
* Try ttyI's.
* These return 0 on no match, 1 on match and
* 3 on eventually match, if CID is longer.
*/
if (c->command == ISDN_STAT_ICALL)
if ((retval = isdn_tty_find_icall(di, c->arg, &c->parm.setup))) return (retval);
#ifdef CONFIG_ISDN_DIVERSION
if (divert_if)
if ((retval = divert_if->stat_callback(c)))
return (retval); /* processed */
#endif /* CONFIG_ISDN_DIVERSION */
if ((!retval) && (dev->drv[di]->flags & DRV_FLAG_REJBUS)) {
/* No tty responding */
cmd.driver = di;
cmd.arg = c->arg;
cmd.command = ISDN_CMD_HANGUP;
isdn_command(&cmd);
retval = 2;
}
break;
case 1:
/* Schedule connection-setup */
isdn_net_dial();
cmd.driver = di;
cmd.arg = c->arg;
cmd.command = ISDN_CMD_ACCEPTD;
for (p = dev->netdev; p; p = p->next)
if (p->local->isdn_channel == cmd.arg)
{
strcpy(cmd.parm.setup.eazmsn, p->local->msn);
isdn_command(&cmd);
retval = 1;
break;
}
break;
case 2: /* For calling back, first reject incoming call ... */
case 3: /* Interface found, but down, reject call actively */
retval = 2;
printk(KERN_INFO "isdn: Rejecting Call\n");
cmd.driver = di;
cmd.arg = c->arg;
cmd.command = ISDN_CMD_HANGUP;
isdn_command(&cmd);
if (r == 3)
break;
/* Fall through */
case 4:
/* ... then start callback. */
isdn_net_dial();
break;
case 5:
/* Number would eventually match, if longer */
retval = 3;
break;
}
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "ICALL: ret=%d\n", retval);
#endif
return retval;
break;
case ISDN_STAT_CINF:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "CINF: %ld %s\n", c->arg, c->parm.num);
#endif
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
if (strcmp(c->parm.num, "0"))
isdn_net_stat_callback(i, c);
isdn_tty_stat_callback(i, c);
break;
case ISDN_STAT_CAUSE:
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "CAUSE: %ld %s\n", c->arg, c->parm.num);
#endif
printk(KERN_INFO "isdn: %s,ch%ld cause: %s\n",
dev->drvid[di], c->arg, c->parm.num);
isdn_tty_stat_callback(i, c);
#ifdef CONFIG_ISDN_DIVERSION
if (divert_if)
divert_if->stat_callback(c);
#endif /* CONFIG_ISDN_DIVERSION */
break;
case ISDN_STAT_DISPLAY:
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "DISPLAY: %ld %s\n", c->arg, c->parm.display);
#endif
isdn_tty_stat_callback(i, c);
#ifdef CONFIG_ISDN_DIVERSION
if (divert_if)
divert_if->stat_callback(c);
#endif /* CONFIG_ISDN_DIVERSION */
break;
case ISDN_STAT_DCONN:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "DCONN: %ld\n", c->arg);
#endif
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
/* Find any net-device, waiting for D-channel setup */
if (isdn_net_stat_callback(i, c))
break;
isdn_v110_stat_callback(i, c);
/* Find any ttyI, waiting for D-channel setup */
if (isdn_tty_stat_callback(i, c)) {
cmd.driver = di;
cmd.arg = c->arg;
cmd.command = ISDN_CMD_ACCEPTB;
isdn_command(&cmd);
break;
}
break;
case ISDN_STAT_DHUP:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "DHUP: %ld\n", c->arg);
#endif
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
dev->drv[di]->online &= ~(1 << (c->arg));
isdn_info_update();
/* Signal hangup to network-devices */
if (isdn_net_stat_callback(i, c))
break;
isdn_v110_stat_callback(i, c);
if (isdn_tty_stat_callback(i, c))
break;
#ifdef CONFIG_ISDN_DIVERSION
if (divert_if)
divert_if->stat_callback(c);
#endif /* CONFIG_ISDN_DIVERSION */
break;
break;
case ISDN_STAT_BCONN:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "BCONN: %ld\n", c->arg);
#endif
/* Signal B-channel-connect to network-devices */
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
dev->drv[di]->online |= (1 << (c->arg));
isdn_info_update();
if (isdn_net_stat_callback(i, c))
break;
isdn_v110_stat_callback(i, c);
if (isdn_tty_stat_callback(i, c))
break;
break;
case ISDN_STAT_BHUP:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "BHUP: %ld\n", c->arg);
#endif
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
dev->drv[di]->online &= ~(1 << (c->arg));
isdn_info_update();
#ifdef CONFIG_ISDN_X25
/* Signal hangup to network-devices */
if (isdn_net_stat_callback(i, c))
break;
#endif
isdn_v110_stat_callback(i, c);
if (isdn_tty_stat_callback(i, c))
break;
break;
case ISDN_STAT_NODCH:
if (i < 0)
return -1;
#ifdef ISDN_DEBUG_STATCALLB
printk(KERN_DEBUG "NODCH: %ld\n", c->arg);
#endif
if (dev->global_flags & ISDN_GLOBAL_STOPPED)
return 0;
if (isdn_net_stat_callback(i, c))
break;
if (isdn_tty_stat_callback(i, c))
break;
break;
case ISDN_STAT_ADDCH:
spin_lock_irqsave(&dev->lock, flags);
if (isdn_add_channels(dev->drv[di], di, c->arg, 1)) {
spin_unlock_irqrestore(&dev->lock, flags);
return -1;
}
spin_unlock_irqrestore(&dev->lock, flags);
isdn_info_update();
break;
case ISDN_STAT_DISCH:
spin_lock_irqsave(&dev->lock, flags);
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if ((dev->drvmap[i] == di) &&
(dev->chanmap[i] == c->arg)) {
if (c->parm.num[0])
dev->usage[i] &= ~ISDN_USAGE_DISABLED;
else
if (USG_NONE(dev->usage[i])) {
dev->usage[i] |= ISDN_USAGE_DISABLED;
}
else
retval = -1;
break;
}
spin_unlock_irqrestore(&dev->lock, flags);
isdn_info_update();
break;
case ISDN_STAT_UNLOAD:
while (dev->drv[di]->locks > 0) {
isdn_unlock_driver(dev->drv[di]);
}
spin_lock_irqsave(&dev->lock, flags);
isdn_tty_stat_callback(i, c);
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if (dev->drvmap[i] == di) {
dev->drvmap[i] = -1;
dev->chanmap[i] = -1;
dev->usage[i] &= ~ISDN_USAGE_DISABLED;
}
dev->drivers--;
dev->channels -= dev->drv[di]->channels;
kfree(dev->drv[di]->rcverr);
kfree(dev->drv[di]->rcvcount);
for (i = 0; i < dev->drv[di]->channels; i++)
skb_queue_purge(&dev->drv[di]->rpqueue[i]);
kfree(dev->drv[di]->rpqueue);
kfree(dev->drv[di]->rcv_waitq);
kfree(dev->drv[di]);
dev->drv[di] = NULL;
dev->drvid[di][0] = '\0';
isdn_info_update();
set_global_features();
spin_unlock_irqrestore(&dev->lock, flags);
return 0;
case ISDN_STAT_L1ERR:
break;
case CAPI_PUT_MESSAGE:
return (isdn_capi_rec_hl_msg(&c->parm.cmsg));
#ifdef CONFIG_ISDN_TTY_FAX
case ISDN_STAT_FAXIND:
isdn_tty_stat_callback(i, c);
break;
#endif
#ifdef CONFIG_ISDN_AUDIO
case ISDN_STAT_AUDIO:
isdn_tty_stat_callback(i, c);
break;
#endif
#ifdef CONFIG_ISDN_DIVERSION
case ISDN_STAT_PROT:
case ISDN_STAT_REDIR:
if (divert_if)
return (divert_if->stat_callback(c));
#endif /* CONFIG_ISDN_DIVERSION */
default:
return -1;
}
return 0;
}
/*
* Get integer from char-pointer, set pointer to end of number
*/
int
isdn_getnum(char **p)
{
int v = -1;
while (*p[0] >= '0' && *p[0] <= '9')
v = ((v < 0) ? 0 : (v * 10)) + (int) ((*p[0]++) - '0');
return v;
}
#define DLE 0x10
/*
* isdn_readbchan() tries to get data from the read-queue.
* It MUST be called with interrupts off.
*
* Be aware that this is not an atomic operation when sleep != 0, even though
* interrupts are turned off! Well, like that we are currently only called
* on behalf of a read system call on raw device files (which are documented
* to be dangerous and for debugging purpose only). The inode semaphore
* takes care that this is not called for the same minor device number while
* we are sleeping, but access is not serialized against simultaneous read()
* from the corresponding ttyI device. Can other ugly events, like changes
* of the mapping (di,ch)<->minor, happen during the sleep? --he
*/
int
isdn_readbchan(int di, int channel, u_char *buf, u_char *fp, int len, wait_queue_head_t *sleep)
{
int count;
int count_pull;
int count_put;
int dflag;
struct sk_buff *skb;
u_char *cp;
if (!dev->drv[di])
return 0;
if (skb_queue_empty(&dev->drv[di]->rpqueue[channel])) {
if (sleep)
wait_event_interruptible(*sleep,
!skb_queue_empty(&dev->drv[di]->rpqueue[channel]));
else
return 0;
}
if (len > dev->drv[di]->rcvcount[channel])
len = dev->drv[di]->rcvcount[channel];
cp = buf;
count = 0;
while (len) {
if (!(skb = skb_peek(&dev->drv[di]->rpqueue[channel])))
break;
#ifdef CONFIG_ISDN_AUDIO
if (ISDN_AUDIO_SKB_LOCK(skb))
break;
ISDN_AUDIO_SKB_LOCK(skb) = 1;
if ((ISDN_AUDIO_SKB_DLECOUNT(skb)) || (dev->drv[di]->DLEflag & (1 << channel))) {
char *p = skb->data;
unsigned long DLEmask = (1 << channel);
dflag = 0;
count_pull = count_put = 0;
while ((count_pull < skb->len) && (len > 0)) {
len--;
if (dev->drv[di]->DLEflag & DLEmask) {
*cp++ = DLE;
dev->drv[di]->DLEflag &= ~DLEmask;
} else {
*cp++ = *p;
if (*p == DLE) {
dev->drv[di]->DLEflag |= DLEmask;
(ISDN_AUDIO_SKB_DLECOUNT(skb))--;
}
p++;
count_pull++;
}
count_put++;
}
if (count_pull >= skb->len)
dflag = 1;
} else {
#endif
/* No DLE's in buff, so simply copy it */
dflag = 1;
if ((count_pull = skb->len) > len) {
count_pull = len;
dflag = 0;
}
count_put = count_pull;
skb_copy_from_linear_data(skb, cp, count_put);
cp += count_put;
len -= count_put;
#ifdef CONFIG_ISDN_AUDIO
}
#endif
count += count_put;
if (fp) {
memset(fp, 0, count_put);
fp += count_put;
}
if (dflag) {
/* We got all the data in this buff.
* Now we can dequeue it.
*/
if (fp)
*(fp - 1) = 0xff;
#ifdef CONFIG_ISDN_AUDIO
ISDN_AUDIO_SKB_LOCK(skb) = 0;
#endif
skb = skb_dequeue(&dev->drv[di]->rpqueue[channel]);
dev_kfree_skb(skb);
} else {
/* Not yet emptied this buff, so it
* must stay in the queue, for further calls
* but we pull off the data we got until now.
*/
skb_pull(skb, count_pull);
#ifdef CONFIG_ISDN_AUDIO
ISDN_AUDIO_SKB_LOCK(skb) = 0;
#endif
}
dev->drv[di]->rcvcount[channel] -= count_put;
}
return count;
}
/*
* isdn_readbchan_tty() tries to get data from the read-queue.
* It MUST be called with interrupts off.
*
* Be aware that this is not an atomic operation when sleep != 0, even though
* interrupts are turned off! Well, like that we are currently only called
* on behalf of a read system call on raw device files (which are documented
* to be dangerous and for debugging purpose only). The inode semaphore
* takes care that this is not called for the same minor device number while
* we are sleeping, but access is not serialized against simultaneous read()
* from the corresponding ttyI device. Can other ugly events, like changes
* of the mapping (di,ch)<->minor, happen during the sleep? --he
*/
int
isdn_readbchan_tty(int di, int channel, struct tty_port *port, int cisco_hack)
{
int count;
int count_pull;
int count_put;
int dflag;
struct sk_buff *skb;
char last = 0;
int len;
if (!dev->drv[di])
return 0;
if (skb_queue_empty(&dev->drv[di]->rpqueue[channel]))
return 0;
len = tty_buffer_request_room(port, dev->drv[di]->rcvcount[channel]);
if (len == 0)
return len;
count = 0;
while (len) {
if (!(skb = skb_peek(&dev->drv[di]->rpqueue[channel])))
break;
#ifdef CONFIG_ISDN_AUDIO
if (ISDN_AUDIO_SKB_LOCK(skb))
break;
ISDN_AUDIO_SKB_LOCK(skb) = 1;
if ((ISDN_AUDIO_SKB_DLECOUNT(skb)) || (dev->drv[di]->DLEflag & (1 << channel))) {
char *p = skb->data;
unsigned long DLEmask = (1 << channel);
dflag = 0;
count_pull = count_put = 0;
while ((count_pull < skb->len) && (len > 0)) {
/* push every character but the last to the tty buffer directly */
if (count_put)
tty_insert_flip_char(port, last, TTY_NORMAL);
len--;
if (dev->drv[di]->DLEflag & DLEmask) {
last = DLE;
dev->drv[di]->DLEflag &= ~DLEmask;
} else {
last = *p;
if (last == DLE) {
dev->drv[di]->DLEflag |= DLEmask;
(ISDN_AUDIO_SKB_DLECOUNT(skb))--;
}
p++;
count_pull++;
}
count_put++;
}
if (count_pull >= skb->len)
dflag = 1;
} else {
#endif
/* No DLE's in buff, so simply copy it */
dflag = 1;
if ((count_pull = skb->len) > len) {
count_pull = len;
dflag = 0;
}
count_put = count_pull;
if (count_put > 1)
tty_insert_flip_string(port, skb->data, count_put - 1);
last = skb->data[count_put - 1];
len -= count_put;
#ifdef CONFIG_ISDN_AUDIO
}
#endif
count += count_put;
if (dflag) {
/* We got all the data in this buff.
* Now we can dequeue it.
*/
if (cisco_hack)
tty_insert_flip_char(port, last, 0xFF);
else
tty_insert_flip_char(port, last, TTY_NORMAL);
#ifdef CONFIG_ISDN_AUDIO
ISDN_AUDIO_SKB_LOCK(skb) = 0;
#endif
skb = skb_dequeue(&dev->drv[di]->rpqueue[channel]);
dev_kfree_skb(skb);
} else {
tty_insert_flip_char(port, last, TTY_NORMAL);
/* Not yet emptied this buff, so it
* must stay in the queue, for further calls
* but we pull off the data we got until now.
*/
skb_pull(skb, count_pull);
#ifdef CONFIG_ISDN_AUDIO
ISDN_AUDIO_SKB_LOCK(skb) = 0;
#endif
}
dev->drv[di]->rcvcount[channel] -= count_put;
}
return count;
}
static inline int
isdn_minor2drv(int minor)
{
return (dev->drvmap[minor]);
}
static inline int
isdn_minor2chan(int minor)
{
return (dev->chanmap[minor]);
}
static char *
isdn_statstr(void)
{
static char istatbuf[2048];
char *p;
int i;
sprintf(istatbuf, "idmap:\t");
p = istatbuf + strlen(istatbuf);
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
sprintf(p, "%s ", (dev->drvmap[i] < 0) ? "-" : dev->drvid[dev->drvmap[i]]);
p = istatbuf + strlen(istatbuf);
}
sprintf(p, "\nchmap:\t");
p = istatbuf + strlen(istatbuf);
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
sprintf(p, "%d ", dev->chanmap[i]);
p = istatbuf + strlen(istatbuf);
}
sprintf(p, "\ndrmap:\t");
p = istatbuf + strlen(istatbuf);
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
sprintf(p, "%d ", dev->drvmap[i]);
p = istatbuf + strlen(istatbuf);
}
sprintf(p, "\nusage:\t");
p = istatbuf + strlen(istatbuf);
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
sprintf(p, "%d ", dev->usage[i]);
p = istatbuf + strlen(istatbuf);
}
sprintf(p, "\nflags:\t");
p = istatbuf + strlen(istatbuf);
for (i = 0; i < ISDN_MAX_DRIVERS; i++) {
if (dev->drv[i]) {
sprintf(p, "%ld ", dev->drv[i]->online);
p = istatbuf + strlen(istatbuf);
} else {
sprintf(p, "? ");
p = istatbuf + strlen(istatbuf);
}
}
sprintf(p, "\nphone:\t");
p = istatbuf + strlen(istatbuf);
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
sprintf(p, "%s ", dev->num[i]);
p = istatbuf + strlen(istatbuf);
}
sprintf(p, "\n");
return istatbuf;
}
/* Module interface-code */
void
isdn_info_update(void)
{
infostruct *p = dev->infochain;
while (p) {
*(p->private) = 1;
p = (infostruct *) p->next;
}
wake_up_interruptible(&(dev->info_waitq));
}
static ssize_t
isdn_read(struct file *file, char __user *buf, size_t count, loff_t *off)
{
uint minor = iminor(file_inode(file));
int len = 0;
int drvidx;
int chidx;
int retval;
char *p;
mutex_lock(&isdn_mutex);
if (minor == ISDN_MINOR_STATUS) {
if (!file->private_data) {
if (file->f_flags & O_NONBLOCK) {
retval = -EAGAIN;
goto out;
}
wait_event_interruptible(dev->info_waitq,
file->private_data);
}
p = isdn_statstr();
file->private_data = NULL;
if ((len = strlen(p)) <= count) {
if (copy_to_user(buf, p, len)) {
retval = -EFAULT;
goto out;
}
*off += len;
retval = len;
goto out;
}
retval = 0;
goto out;
}
if (!dev->drivers) {
retval = -ENODEV;
goto out;
}
if (minor <= ISDN_MINOR_BMAX) {
printk(KERN_WARNING "isdn_read minor %d obsolete!\n", minor);
drvidx = isdn_minor2drv(minor);
if (drvidx < 0) {
retval = -ENODEV;
goto out;
}
if (!(dev->drv[drvidx]->flags & DRV_FLAG_RUNNING)) {
retval = -ENODEV;
goto out;
}
chidx = isdn_minor2chan(minor);
if (!(p = kmalloc(count, GFP_KERNEL))) {
retval = -ENOMEM;
goto out;
}
len = isdn_readbchan(drvidx, chidx, p, NULL, count,
&dev->drv[drvidx]->rcv_waitq[chidx]);
*off += len;
if (copy_to_user(buf, p, len))
len = -EFAULT;
kfree(p);
retval = len;
goto out;
}
if (minor <= ISDN_MINOR_CTRLMAX) {
drvidx = isdn_minor2drv(minor - ISDN_MINOR_CTRL);
if (drvidx < 0) {
retval = -ENODEV;
goto out;
}
if (!dev->drv[drvidx]->stavail) {
if (file->f_flags & O_NONBLOCK) {
retval = -EAGAIN;
goto out;
}
wait_event_interruptible(dev->drv[drvidx]->st_waitq,
dev->drv[drvidx]->stavail);
}
if (dev->drv[drvidx]->interface->readstat) {
if (count > dev->drv[drvidx]->stavail)
count = dev->drv[drvidx]->stavail;
len = dev->drv[drvidx]->interface->readstat(buf, count,
drvidx, isdn_minor2chan(minor - ISDN_MINOR_CTRL));
if (len < 0) {
retval = len;
goto out;
}
} else {
len = 0;
}
if (len)
dev->drv[drvidx]->stavail -= len;
else
dev->drv[drvidx]->stavail = 0;
*off += len;
retval = len;
goto out;
}
#ifdef CONFIG_ISDN_PPP
if (minor <= ISDN_MINOR_PPPMAX) {
retval = isdn_ppp_read(minor - ISDN_MINOR_PPP, file, buf, count);
goto out;
}
#endif
retval = -ENODEV;
out:
mutex_unlock(&isdn_mutex);
return retval;
}
static ssize_t
isdn_write(struct file *file, const char __user *buf, size_t count, loff_t *off)
{
uint minor = iminor(file_inode(file));
int drvidx;
int chidx;
int retval;
if (minor == ISDN_MINOR_STATUS)
return -EPERM;
if (!dev->drivers)
return -ENODEV;
mutex_lock(&isdn_mutex);
if (minor <= ISDN_MINOR_BMAX) {
printk(KERN_WARNING "isdn_write minor %d obsolete!\n", minor);
drvidx = isdn_minor2drv(minor);
if (drvidx < 0) {
retval = -ENODEV;
goto out;
}
if (!(dev->drv[drvidx]->flags & DRV_FLAG_RUNNING)) {
retval = -ENODEV;
goto out;
}
chidx = isdn_minor2chan(minor);
wait_event_interruptible(dev->drv[drvidx]->snd_waitq[chidx],
(retval = isdn_writebuf_stub(drvidx, chidx, buf, count)));
goto out;
}
if (minor <= ISDN_MINOR_CTRLMAX) {
drvidx = isdn_minor2drv(minor - ISDN_MINOR_CTRL);
if (drvidx < 0) {
retval = -ENODEV;
goto out;
}
/*
* We want to use the isdnctrl device to load the firmware
*
if (!(dev->drv[drvidx]->flags & DRV_FLAG_RUNNING))
return -ENODEV;
*/
if (dev->drv[drvidx]->interface->writecmd)
retval = dev->drv[drvidx]->interface->
writecmd(buf, count, drvidx,
isdn_minor2chan(minor - ISDN_MINOR_CTRL));
else
retval = count;
goto out;
}
#ifdef CONFIG_ISDN_PPP
if (minor <= ISDN_MINOR_PPPMAX) {
retval = isdn_ppp_write(minor - ISDN_MINOR_PPP, file, buf, count);
goto out;
}
#endif
retval = -ENODEV;
out:
mutex_unlock(&isdn_mutex);
return retval;
}
static unsigned int
isdn_poll(struct file *file, poll_table *wait)
{
unsigned int mask = 0;
unsigned int minor = iminor(file_inode(file));
int drvidx = isdn_minor2drv(minor - ISDN_MINOR_CTRL);
mutex_lock(&isdn_mutex);
if (minor == ISDN_MINOR_STATUS) {
poll_wait(file, &(dev->info_waitq), wait);
/* mask = POLLOUT | POLLWRNORM; */
if (file->private_data) {
mask |= POLLIN | POLLRDNORM;
}
goto out;
}
if (minor >= ISDN_MINOR_CTRL && minor <= ISDN_MINOR_CTRLMAX) {
if (drvidx < 0) {
/* driver deregistered while file open */
mask = POLLHUP;
goto out;
}
poll_wait(file, &(dev->drv[drvidx]->st_waitq), wait);
mask = POLLOUT | POLLWRNORM;
if (dev->drv[drvidx]->stavail) {
mask |= POLLIN | POLLRDNORM;
}
goto out;
}
#ifdef CONFIG_ISDN_PPP
if (minor <= ISDN_MINOR_PPPMAX) {
mask = isdn_ppp_poll(file, wait);
goto out;
}
#endif
mask = POLLERR;
out:
mutex_unlock(&isdn_mutex);
return mask;
}
static int
isdn_ioctl(struct file *file, uint cmd, ulong arg)
{
uint minor = iminor(file_inode(file));
isdn_ctrl c;
int drvidx;
int ret;
int i;
char __user *p;
char *s;
union iocpar {
char name[10];
char bname[22];
isdn_ioctl_struct iocts;
isdn_net_ioctl_phone phone;
isdn_net_ioctl_cfg cfg;
} iocpar;
void __user *argp = (void __user *)arg;
#define name iocpar.name
#define bname iocpar.bname
#define iocts iocpar.iocts
#define phone iocpar.phone
#define cfg iocpar.cfg
if (minor == ISDN_MINOR_STATUS) {
switch (cmd) {
case IIOCGETDVR:
return (TTY_DV +
(NET_DV << 8) +
(INF_DV << 16));
case IIOCGETCPS:
if (arg) {
ulong __user *p = argp;
int i;
if (!access_ok(VERIFY_WRITE, p,
sizeof(ulong) * ISDN_MAX_CHANNELS * 2))
return -EFAULT;
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
put_user(dev->ibytes[i], p++);
put_user(dev->obytes[i], p++);
}
return 0;
} else
return -EINVAL;
break;
case IIOCNETGPN:
/* Get peer phone number of a connected
* isdn network interface */
if (arg) {
if (copy_from_user(&phone, argp, sizeof(phone)))
return -EFAULT;
return isdn_net_getpeer(&phone, argp);
} else
return -EINVAL;
default:
return -EINVAL;
}
}
if (!dev->drivers)
return -ENODEV;
if (minor <= ISDN_MINOR_BMAX) {
drvidx = isdn_minor2drv(minor);
if (drvidx < 0)
return -ENODEV;
if (!(dev->drv[drvidx]->flags & DRV_FLAG_RUNNING))
return -ENODEV;
return 0;
}
if (minor <= ISDN_MINOR_CTRLMAX) {
/*
* isdn net devices manage lots of configuration variables as linked lists.
* Those lists must only be manipulated from user space. Some of the ioctl's
* service routines access user space and are not atomic. Therefore, ioctl's
* manipulating the lists and ioctl's sleeping while accessing the lists
* are serialized by means of a semaphore.
*/
switch (cmd) {
case IIOCNETDWRSET:
printk(KERN_INFO "INFO: ISDN_DW_ABC_EXTENSION not enabled\n");
return (-EINVAL);
case IIOCNETLCR:
printk(KERN_INFO "INFO: ISDN_ABC_LCR_SUPPORT not enabled\n");
return -ENODEV;
case IIOCNETAIF:
/* Add a network-interface */
if (arg) {
if (copy_from_user(name, argp, sizeof(name)))
return -EFAULT;
s = name;
} else {
s = NULL;
}
ret = mutex_lock_interruptible(&dev->mtx);
if (ret) return ret;
if ((s = isdn_net_new(s, NULL))) {
if (copy_to_user(argp, s, strlen(s) + 1)) {
ret = -EFAULT;
} else {
ret = 0;
}
} else
ret = -ENODEV;
mutex_unlock(&dev->mtx);
return ret;
case IIOCNETASL:
/* Add a slave to a network-interface */
if (arg) {
if (copy_from_user(bname, argp, sizeof(bname) - 1))
return -EFAULT;
} else
return -EINVAL;
ret = mutex_lock_interruptible(&dev->mtx);
if (ret) return ret;
if ((s = isdn_net_newslave(bname))) {
if (copy_to_user(argp, s, strlen(s) + 1)) {
ret = -EFAULT;
} else {
ret = 0;
}
} else
ret = -ENODEV;
mutex_unlock(&dev->mtx);
return ret;
case IIOCNETDIF:
/* Delete a network-interface */
if (arg) {
if (copy_from_user(name, argp, sizeof(name)))
return -EFAULT;
ret = mutex_lock_interruptible(&dev->mtx);
if (ret) return ret;
ret = isdn_net_rm(name);
mutex_unlock(&dev->mtx);
return ret;
} else
return -EINVAL;
case IIOCNETSCF:
/* Set configurable parameters of a network-interface */
if (arg) {
if (copy_from_user(&cfg, argp, sizeof(cfg)))
return -EFAULT;
return isdn_net_setcfg(&cfg);
} else
return -EINVAL;
case IIOCNETGCF:
/* Get configurable parameters of a network-interface */
if (arg) {
if (copy_from_user(&cfg, argp, sizeof(cfg)))
return -EFAULT;
if (!(ret = isdn_net_getcfg(&cfg))) {
if (copy_to_user(argp, &cfg, sizeof(cfg)))
return -EFAULT;
}
return ret;
} else
return -EINVAL;
case IIOCNETANM:
/* Add a phone-number to a network-interface */
if (arg) {
if (copy_from_user(&phone, argp, sizeof(phone)))
return -EFAULT;
ret = mutex_lock_interruptible(&dev->mtx);
if (ret) return ret;
ret = isdn_net_addphone(&phone);
mutex_unlock(&dev->mtx);
return ret;
} else
return -EINVAL;
case IIOCNETGNM:
/* Get list of phone-numbers of a network-interface */
if (arg) {
if (copy_from_user(&phone, argp, sizeof(phone)))
return -EFAULT;
ret = mutex_lock_interruptible(&dev->mtx);
if (ret) return ret;
ret = isdn_net_getphones(&phone, argp);
mutex_unlock(&dev->mtx);
return ret;
} else
return -EINVAL;
case IIOCNETDNM:
/* Delete a phone-number of a network-interface */
if (arg) {
if (copy_from_user(&phone, argp, sizeof(phone)))
return -EFAULT;
ret = mutex_lock_interruptible(&dev->mtx);
if (ret) return ret;
ret = isdn_net_delphone(&phone);
mutex_unlock(&dev->mtx);
return ret;
} else
return -EINVAL;
case IIOCNETDIL:
/* Force dialing of a network-interface */
if (arg) {
if (copy_from_user(name, argp, sizeof(name)))
return -EFAULT;
return isdn_net_force_dial(name);
} else
return -EINVAL;
#ifdef CONFIG_ISDN_PPP
case IIOCNETALN:
if (!arg)
return -EINVAL;
if (copy_from_user(name, argp, sizeof(name)))
return -EFAULT;
return isdn_ppp_dial_slave(name);
case IIOCNETDLN:
if (!arg)
return -EINVAL;
if (copy_from_user(name, argp, sizeof(name)))
return -EFAULT;
return isdn_ppp_hangup_slave(name);
#endif
case IIOCNETHUP:
/* Force hangup of a network-interface */
if (!arg)
return -EINVAL;
if (copy_from_user(name, argp, sizeof(name)))
return -EFAULT;
return isdn_net_force_hangup(name);
break;
case IIOCSETVER:
dev->net_verbose = arg;
printk(KERN_INFO "isdn: Verbose-Level is %d\n", dev->net_verbose);
return 0;
case IIOCSETGST:
if (arg)
dev->global_flags |= ISDN_GLOBAL_STOPPED;
else
dev->global_flags &= ~ISDN_GLOBAL_STOPPED;
printk(KERN_INFO "isdn: Global Mode %s\n",
(dev->global_flags & ISDN_GLOBAL_STOPPED) ? "stopped" : "running");
return 0;
case IIOCSETBRJ:
drvidx = -1;
if (arg) {
int i;
char *p;
if (copy_from_user(&iocts, argp,
sizeof(isdn_ioctl_struct)))
return -EFAULT;
iocts.drvid[sizeof(iocts.drvid) - 1] = 0;
if (strlen(iocts.drvid)) {
if ((p = strchr(iocts.drvid, ',')))
*p = 0;
drvidx = -1;
for (i = 0; i < ISDN_MAX_DRIVERS; i++)
if (!(strcmp(dev->drvid[i], iocts.drvid))) {
drvidx = i;
break;
}
}
}
if (drvidx == -1)
return -ENODEV;
if (iocts.arg)
dev->drv[drvidx]->flags |= DRV_FLAG_REJBUS;
else
dev->drv[drvidx]->flags &= ~DRV_FLAG_REJBUS;
return 0;
case IIOCSIGPRF:
dev->profd = current;
return 0;
break;
case IIOCGETPRF:
/* Get all Modem-Profiles */
if (arg) {
char __user *p = argp;
int i;
if (!access_ok(VERIFY_WRITE, argp,
(ISDN_MODEM_NUMREG + ISDN_MSNLEN + ISDN_LMSNLEN)
* ISDN_MAX_CHANNELS))
return -EFAULT;
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
if (copy_to_user(p, dev->mdm.info[i].emu.profile,
ISDN_MODEM_NUMREG))
return -EFAULT;
p += ISDN_MODEM_NUMREG;
if (copy_to_user(p, dev->mdm.info[i].emu.pmsn, ISDN_MSNLEN))
return -EFAULT;
p += ISDN_MSNLEN;
if (copy_to_user(p, dev->mdm.info[i].emu.plmsn, ISDN_LMSNLEN))
return -EFAULT;
p += ISDN_LMSNLEN;
}
return (ISDN_MODEM_NUMREG + ISDN_MSNLEN + ISDN_LMSNLEN) * ISDN_MAX_CHANNELS;
} else
return -EINVAL;
break;
case IIOCSETPRF:
/* Set all Modem-Profiles */
if (arg) {
char __user *p = argp;
int i;
if (!access_ok(VERIFY_READ, argp,
(ISDN_MODEM_NUMREG + ISDN_MSNLEN + ISDN_LMSNLEN)
* ISDN_MAX_CHANNELS))
return -EFAULT;
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
if (copy_from_user(dev->mdm.info[i].emu.profile, p,
ISDN_MODEM_NUMREG))
return -EFAULT;
p += ISDN_MODEM_NUMREG;
if (copy_from_user(dev->mdm.info[i].emu.plmsn, p, ISDN_LMSNLEN))
return -EFAULT;
p += ISDN_LMSNLEN;
if (copy_from_user(dev->mdm.info[i].emu.pmsn, p, ISDN_MSNLEN))
return -EFAULT;
p += ISDN_MSNLEN;
}
return 0;
} else
return -EINVAL;
break;
case IIOCSETMAP:
case IIOCGETMAP:
/* Set/Get MSN->EAZ-Mapping for a driver */
if (arg) {
if (copy_from_user(&iocts, argp,
sizeof(isdn_ioctl_struct)))
return -EFAULT;
iocts.drvid[sizeof(iocts.drvid) - 1] = 0;
if (strlen(iocts.drvid)) {
drvidx = -1;
for (i = 0; i < ISDN_MAX_DRIVERS; i++)
if (!(strcmp(dev->drvid[i], iocts.drvid))) {
drvidx = i;
break;
}
} else
drvidx = 0;
if (drvidx == -1)
return -ENODEV;
if (cmd == IIOCSETMAP) {
int loop = 1;
p = (char __user *) iocts.arg;
i = 0;
while (loop) {
int j = 0;
while (1) {
if (!access_ok(VERIFY_READ, p, 1))
return -EFAULT;
get_user(bname[j], p++);
switch (bname[j]) {
case '\0':
loop = 0;
/* Fall through */
case ',':
bname[j] = '\0';
strcpy(dev->drv[drvidx]->msn2eaz[i], bname);
j = ISDN_MSNLEN;
break;
default:
j++;
}
if (j >= ISDN_MSNLEN)
break;
}
if (++i > 9)
break;
}
} else {
p = (char __user *) iocts.arg;
for (i = 0; i < 10; i++) {
snprintf(bname, sizeof(bname), "%s%s",
strlen(dev->drv[drvidx]->msn2eaz[i]) ?
dev->drv[drvidx]->msn2eaz[i] : "_",
(i < 9) ? "," : "\0");
if (copy_to_user(p, bname, strlen(bname) + 1))
return -EFAULT;
p += strlen(bname);
}
}
return 0;
} else
return -EINVAL;
case IIOCDBGVAR:
if (arg) {
if (copy_to_user(argp, &dev, sizeof(ulong)))
return -EFAULT;
return 0;
} else
return -EINVAL;
break;
default:
if ((cmd & IIOCDRVCTL) == IIOCDRVCTL)
cmd = ((cmd >> _IOC_NRSHIFT) & _IOC_NRMASK) & ISDN_DRVIOCTL_MASK;
else
return -EINVAL;
if (arg) {
int i;
char *p;
if (copy_from_user(&iocts, argp, sizeof(isdn_ioctl_struct)))
return -EFAULT;
iocts.drvid[sizeof(iocts.drvid) - 1] = 0;
if (strlen(iocts.drvid)) {
if ((p = strchr(iocts.drvid, ',')))
*p = 0;
drvidx = -1;
for (i = 0; i < ISDN_MAX_DRIVERS; i++)
if (!(strcmp(dev->drvid[i], iocts.drvid))) {
drvidx = i;
break;
}
} else
drvidx = 0;
if (drvidx == -1)
return -ENODEV;
if (!access_ok(VERIFY_WRITE, argp,
sizeof(isdn_ioctl_struct)))
return -EFAULT;
c.driver = drvidx;
c.command = ISDN_CMD_IOCTL;
c.arg = cmd;
memcpy(c.parm.num, &iocts.arg, sizeof(ulong));
ret = isdn_command(&c);
memcpy(&iocts.arg, c.parm.num, sizeof(ulong));
if (copy_to_user(argp, &iocts, sizeof(isdn_ioctl_struct)))
return -EFAULT;
return ret;
} else
return -EINVAL;
}
}
#ifdef CONFIG_ISDN_PPP
if (minor <= ISDN_MINOR_PPPMAX)
return (isdn_ppp_ioctl(minor - ISDN_MINOR_PPP, file, cmd, arg));
#endif
return -ENODEV;
#undef name
#undef bname
#undef iocts
#undef phone
#undef cfg
}
static long
isdn_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int ret;
mutex_lock(&isdn_mutex);
ret = isdn_ioctl(file, cmd, arg);
mutex_unlock(&isdn_mutex);
return ret;
}
/*
* Open the device code.
*/
static int
isdn_open(struct inode *ino, struct file *filep)
{
uint minor = iminor(ino);
int drvidx;
int chidx;
int retval = -ENODEV;
mutex_lock(&isdn_mutex);
if (minor == ISDN_MINOR_STATUS) {
infostruct *p;
if ((p = kmalloc(sizeof(infostruct), GFP_KERNEL))) {
p->next = (char *) dev->infochain;
p->private = (char *) &(filep->private_data);
dev->infochain = p;
/* At opening we allow a single update */
filep->private_data = (char *) 1;
retval = 0;
goto out;
} else {
retval = -ENOMEM;
goto out;
}
}
if (!dev->channels)
goto out;
if (minor <= ISDN_MINOR_BMAX) {
printk(KERN_WARNING "isdn_open minor %d obsolete!\n", minor);
drvidx = isdn_minor2drv(minor);
if (drvidx < 0)
goto out;
chidx = isdn_minor2chan(minor);
if (!(dev->drv[drvidx]->flags & DRV_FLAG_RUNNING))
goto out;
if (!(dev->drv[drvidx]->online & (1 << chidx)))
goto out;
isdn_lock_drivers();
retval = 0;
goto out;
}
if (minor <= ISDN_MINOR_CTRLMAX) {
drvidx = isdn_minor2drv(minor - ISDN_MINOR_CTRL);
if (drvidx < 0)
goto out;
isdn_lock_drivers();
retval = 0;
goto out;
}
#ifdef CONFIG_ISDN_PPP
if (minor <= ISDN_MINOR_PPPMAX) {
retval = isdn_ppp_open(minor - ISDN_MINOR_PPP, filep);
if (retval == 0)
isdn_lock_drivers();
goto out;
}
#endif
out:
nonseekable_open(ino, filep);
mutex_unlock(&isdn_mutex);
return retval;
}
static int
isdn_close(struct inode *ino, struct file *filep)
{
uint minor = iminor(ino);
mutex_lock(&isdn_mutex);
if (minor == ISDN_MINOR_STATUS) {
infostruct *p = dev->infochain;
infostruct *q = NULL;
while (p) {
if (p->private == (char *) &(filep->private_data)) {
if (q)
q->next = p->next;
else
dev->infochain = (infostruct *) (p->next);
kfree(p);
goto out;
}
q = p;
p = (infostruct *) (p->next);
}
printk(KERN_WARNING "isdn: No private data while closing isdnctrl\n");
goto out;
}
isdn_unlock_drivers();
if (minor <= ISDN_MINOR_BMAX)
goto out;
if (minor <= ISDN_MINOR_CTRLMAX) {
if (dev->profd == current)
dev->profd = NULL;
goto out;
}
#ifdef CONFIG_ISDN_PPP
if (minor <= ISDN_MINOR_PPPMAX)
isdn_ppp_release(minor - ISDN_MINOR_PPP, filep);
#endif
out:
mutex_unlock(&isdn_mutex);
return 0;
}
static const struct file_operations isdn_fops =
{
.owner = THIS_MODULE,
.llseek = no_llseek,
.read = isdn_read,
.write = isdn_write,
.poll = isdn_poll,
.unlocked_ioctl = isdn_unlocked_ioctl,
.open = isdn_open,
.release = isdn_close,
};
char *
isdn_map_eaz2msn(char *msn, int di)
{
isdn_driver_t *this = dev->drv[di];
int i;
if (strlen(msn) == 1) {
i = msn[0] - '0';
if ((i >= 0) && (i <= 9))
if (strlen(this->msn2eaz[i]))
return (this->msn2eaz[i]);
}
return (msn);
}
/*
* Find an unused ISDN-channel, whose feature-flags match the
* given L2- and L3-protocols.
*/
#define L2V (~(ISDN_FEATURE_L2_V11096 | ISDN_FEATURE_L2_V11019 | ISDN_FEATURE_L2_V11038))
/*
* This function must be called with holding the dev->lock.
*/
int
isdn_get_free_channel(int usage, int l2_proto, int l3_proto, int pre_dev
, int pre_chan, char *msn)
{
int i;
ulong features;
ulong vfeatures;
features = ((1 << l2_proto) | (0x10000 << l3_proto));
vfeatures = (((1 << l2_proto) | (0x10000 << l3_proto)) &
~(ISDN_FEATURE_L2_V11096 | ISDN_FEATURE_L2_V11019 | ISDN_FEATURE_L2_V11038));
/* If Layer-2 protocol is V.110, accept drivers with
* transparent feature even if these don't support V.110
* because we can emulate this in linklevel.
*/
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if (USG_NONE(dev->usage[i]) &&
(dev->drvmap[i] != -1)) {
int d = dev->drvmap[i];
if ((dev->usage[i] & ISDN_USAGE_EXCLUSIVE) &&
((pre_dev != d) || (pre_chan != dev->chanmap[i])))
continue;
if (!strcmp(isdn_map_eaz2msn(msn, d), "-"))
continue;
if (dev->usage[i] & ISDN_USAGE_DISABLED)
continue; /* usage not allowed */
if (dev->drv[d]->flags & DRV_FLAG_RUNNING) {
if (((dev->drv[d]->interface->features & features) == features) ||
(((dev->drv[d]->interface->features & vfeatures) == vfeatures) &&
(dev->drv[d]->interface->features & ISDN_FEATURE_L2_TRANS))) {
if ((pre_dev < 0) || (pre_chan < 0)) {
dev->usage[i] &= ISDN_USAGE_EXCLUSIVE;
dev->usage[i] |= usage;
isdn_info_update();
return i;
} else {
if ((pre_dev == d) && (pre_chan == dev->chanmap[i])) {
dev->usage[i] &= ISDN_USAGE_EXCLUSIVE;
dev->usage[i] |= usage;
isdn_info_update();
return i;
}
}
}
}
}
return -1;
}
/*
* Set state of ISDN-channel to 'unused'
*/
void
isdn_free_channel(int di, int ch, int usage)
{
int i;
if ((di < 0) || (ch < 0)) {
printk(KERN_WARNING "%s: called with invalid drv(%d) or channel(%d)\n",
__func__, di, ch);
return;
}
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if (((!usage) || ((dev->usage[i] & ISDN_USAGE_MASK) == usage)) &&
(dev->drvmap[i] == di) &&
(dev->chanmap[i] == ch)) {
dev->usage[i] &= (ISDN_USAGE_NONE | ISDN_USAGE_EXCLUSIVE);
strcpy(dev->num[i], "???");
dev->ibytes[i] = 0;
dev->obytes[i] = 0;
// 20.10.99 JIM, try to reinitialize v110 !
dev->v110emu[i] = 0;
atomic_set(&(dev->v110use[i]), 0);
isdn_v110_close(dev->v110[i]);
dev->v110[i] = NULL;
// 20.10.99 JIM, try to reinitialize v110 !
isdn_info_update();
if (dev->drv[di])
skb_queue_purge(&dev->drv[di]->rpqueue[ch]);
}
}
/*
* Cancel Exclusive-Flag for ISDN-channel
*/
void
isdn_unexclusive_channel(int di, int ch)
{
int i;
for (i = 0; i < ISDN_MAX_CHANNELS; i++)
if ((dev->drvmap[i] == di) &&
(dev->chanmap[i] == ch)) {
dev->usage[i] &= ~ISDN_USAGE_EXCLUSIVE;
isdn_info_update();
return;
}
}
/*
* writebuf replacement for SKB_ABLE drivers
*/
static int
isdn_writebuf_stub(int drvidx, int chan, const u_char __user *buf, int len)
{
int ret;
int hl = dev->drv[drvidx]->interface->hl_hdrlen;
struct sk_buff *skb = alloc_skb(hl + len, GFP_ATOMIC);
if (!skb)
return -ENOMEM;
skb_reserve(skb, hl);
if (copy_from_user(skb_put(skb, len), buf, len)) {
dev_kfree_skb(skb);
return -EFAULT;
}
ret = dev->drv[drvidx]->interface->writebuf_skb(drvidx, chan, 1, skb);
if (ret <= 0)
dev_kfree_skb(skb);
if (ret > 0)
dev->obytes[isdn_dc2minor(drvidx, chan)] += ret;
return ret;
}
/*
* Return: length of data on success, -ERRcode on failure.
*/
int
isdn_writebuf_skb_stub(int drvidx, int chan, int ack, struct sk_buff *skb)
{
int ret;
struct sk_buff *nskb = NULL;
int v110_ret = skb->len;
int idx = isdn_dc2minor(drvidx, chan);
if (dev->v110[idx]) {
atomic_inc(&dev->v110use[idx]);
nskb = isdn_v110_encode(dev->v110[idx], skb);
atomic_dec(&dev->v110use[idx]);
if (!nskb)
return 0;
v110_ret = *((int *)nskb->data);
skb_pull(nskb, sizeof(int));
if (!nskb->len) {
dev_kfree_skb(nskb);
return v110_ret;
}
/* V.110 must always be acknowledged */
ack = 1;
ret = dev->drv[drvidx]->interface->writebuf_skb(drvidx, chan, ack, nskb);
} else {
int hl = dev->drv[drvidx]->interface->hl_hdrlen;
if (skb_headroom(skb) < hl) {
/*
* This should only occur when new HL driver with
* increased hl_hdrlen was loaded after netdevice
* was created and connected to the new driver.
*
* The V.110 branch (re-allocates on its own) does
* not need this
*/
struct sk_buff *skb_tmp;
skb_tmp = skb_realloc_headroom(skb, hl);
printk(KERN_DEBUG "isdn_writebuf_skb_stub: reallocating headroom%s\n", skb_tmp ? "" : " failed");
if (!skb_tmp) return -ENOMEM; /* 0 better? */
ret = dev->drv[drvidx]->interface->writebuf_skb(drvidx, chan, ack, skb_tmp);
if (ret > 0) {
dev_kfree_skb(skb);
} else {
dev_kfree_skb(skb_tmp);
}
} else {
ret = dev->drv[drvidx]->interface->writebuf_skb(drvidx, chan, ack, skb);
}
}
if (ret > 0) {
dev->obytes[idx] += ret;
if (dev->v110[idx]) {
atomic_inc(&dev->v110use[idx]);
dev->v110[idx]->skbuser++;
atomic_dec(&dev->v110use[idx]);
/* For V.110 return unencoded data length */
ret = v110_ret;
/* if the complete frame was send we free the skb;
if not upper function will requeue the skb */
if (ret == skb->len)
dev_kfree_skb(skb);
}
} else
if (dev->v110[idx])
dev_kfree_skb(nskb);
return ret;
}
static int
isdn_add_channels(isdn_driver_t *d, int drvidx, int n, int adding)
{
int j, k, m;
init_waitqueue_head(&d->st_waitq);
if (d->flags & DRV_FLAG_RUNNING)
return -1;
if (n < 1) return 0;
m = (adding) ? d->channels + n : n;
if (dev->channels + n > ISDN_MAX_CHANNELS) {
printk(KERN_WARNING "register_isdn: Max. %d channels supported\n",
ISDN_MAX_CHANNELS);
return -1;
}
if ((adding) && (d->rcverr))
kfree(d->rcverr);
if (!(d->rcverr = kzalloc(sizeof(int) * m, GFP_ATOMIC))) {
printk(KERN_WARNING "register_isdn: Could not alloc rcverr\n");
return -1;
}
if ((adding) && (d->rcvcount))
kfree(d->rcvcount);
if (!(d->rcvcount = kzalloc(sizeof(int) * m, GFP_ATOMIC))) {
printk(KERN_WARNING "register_isdn: Could not alloc rcvcount\n");
if (!adding)
kfree(d->rcverr);
return -1;
}
if ((adding) && (d->rpqueue)) {
for (j = 0; j < d->channels; j++)
skb_queue_purge(&d->rpqueue[j]);
kfree(d->rpqueue);
}
if (!(d->rpqueue = kmalloc(sizeof(struct sk_buff_head) * m, GFP_ATOMIC))) {
printk(KERN_WARNING "register_isdn: Could not alloc rpqueue\n");
if (!adding) {
kfree(d->rcvcount);
kfree(d->rcverr);
}
return -1;
}
for (j = 0; j < m; j++) {
skb_queue_head_init(&d->rpqueue[j]);
}
if ((adding) && (d->rcv_waitq))
kfree(d->rcv_waitq);
d->rcv_waitq = kmalloc(sizeof(wait_queue_head_t) * 2 * m, GFP_ATOMIC);
if (!d->rcv_waitq) {
printk(KERN_WARNING "register_isdn: Could not alloc rcv_waitq\n");
if (!adding) {
kfree(d->rpqueue);
kfree(d->rcvcount);
kfree(d->rcverr);
}
return -1;
}
d->snd_waitq = d->rcv_waitq + m;
for (j = 0; j < m; j++) {
init_waitqueue_head(&d->rcv_waitq[j]);
init_waitqueue_head(&d->snd_waitq[j]);
}
dev->channels += n;
for (j = d->channels; j < m; j++)
for (k = 0; k < ISDN_MAX_CHANNELS; k++)
if (dev->chanmap[k] < 0) {
dev->chanmap[k] = j;
dev->drvmap[k] = drvidx;
break;
}
d->channels = m;
return 0;
}
/*
* Low-level-driver registration
*/
static void
set_global_features(void)
{
int drvidx;
dev->global_features = 0;
for (drvidx = 0; drvidx < ISDN_MAX_DRIVERS; drvidx++) {
if (!dev->drv[drvidx])
continue;
if (dev->drv[drvidx]->interface)
dev->global_features |= dev->drv[drvidx]->interface->features;
}
}
#ifdef CONFIG_ISDN_DIVERSION
static char *map_drvname(int di)
{
if ((di < 0) || (di >= ISDN_MAX_DRIVERS))
return (NULL);
return (dev->drvid[di]); /* driver name */
} /* map_drvname */
static int map_namedrv(char *id)
{ int i;
for (i = 0; i < ISDN_MAX_DRIVERS; i++)
{ if (!strcmp(dev->drvid[i], id))
return (i);
}
return (-1);
} /* map_namedrv */
int DIVERT_REG_NAME(isdn_divert_if *i_div)
{
if (i_div->if_magic != DIVERT_IF_MAGIC)
return (DIVERT_VER_ERR);
switch (i_div->cmd)
{
case DIVERT_CMD_REL:
if (divert_if != i_div)
return (DIVERT_REL_ERR);
divert_if = NULL; /* free interface */
return (DIVERT_NO_ERR);
case DIVERT_CMD_REG:
if (divert_if)
return (DIVERT_REG_ERR);
i_div->ll_cmd = isdn_command; /* set command function */
i_div->drv_to_name = map_drvname;
i_div->name_to_drv = map_namedrv;
divert_if = i_div; /* remember interface */
return (DIVERT_NO_ERR);
default:
return (DIVERT_CMD_ERR);
}
} /* DIVERT_REG_NAME */
EXPORT_SYMBOL(DIVERT_REG_NAME);
#endif /* CONFIG_ISDN_DIVERSION */
EXPORT_SYMBOL(register_isdn);
#ifdef CONFIG_ISDN_PPP
EXPORT_SYMBOL(isdn_ppp_register_compressor);
EXPORT_SYMBOL(isdn_ppp_unregister_compressor);
#endif
int
register_isdn(isdn_if *i)
{
isdn_driver_t *d;
int j;
ulong flags;
int drvidx;
if (dev->drivers >= ISDN_MAX_DRIVERS) {
printk(KERN_WARNING "register_isdn: Max. %d drivers supported\n",
ISDN_MAX_DRIVERS);
return 0;
}
if (!i->writebuf_skb) {
printk(KERN_WARNING "register_isdn: No write routine given.\n");
return 0;
}
if (!(d = kzalloc(sizeof(isdn_driver_t), GFP_KERNEL))) {
printk(KERN_WARNING "register_isdn: Could not alloc driver-struct\n");
return 0;
}
d->maxbufsize = i->maxbufsize;
d->pktcount = 0;
d->stavail = 0;
d->flags = DRV_FLAG_LOADED;
d->online = 0;
d->interface = i;
d->channels = 0;
spin_lock_irqsave(&dev->lock, flags);
for (drvidx = 0; drvidx < ISDN_MAX_DRIVERS; drvidx++)
if (!dev->drv[drvidx])
break;
if (isdn_add_channels(d, drvidx, i->channels, 0)) {
spin_unlock_irqrestore(&dev->lock, flags);
kfree(d);
return 0;
}
i->channels = drvidx;
i->rcvcallb_skb = isdn_receive_skb_callback;
i->statcallb = isdn_status_callback;
if (!strlen(i->id))
sprintf(i->id, "line%d", drvidx);
for (j = 0; j < drvidx; j++)
if (!strcmp(i->id, dev->drvid[j]))
sprintf(i->id, "line%d", drvidx);
dev->drv[drvidx] = d;
strcpy(dev->drvid[drvidx], i->id);
isdn_info_update();
dev->drivers++;
set_global_features();
spin_unlock_irqrestore(&dev->lock, flags);
return 1;
}
/*
*****************************************************************************
* And now the modules code.
*****************************************************************************
*/
static char *
isdn_getrev(const char *revision)
{
char *rev;
char *p;
if ((p = strchr(revision, ':'))) {
rev = p + 2;
p = strchr(rev, '$');
*--p = 0;
} else
rev = "???";
return rev;
}
/*
* Allocate and initialize all data, register modem-devices
*/
static int __init isdn_init(void)
{
int i;
char tmprev[50];
dev = vzalloc(sizeof(isdn_dev));
if (!dev) {
printk(KERN_WARNING "isdn: Could not allocate device-struct.\n");
return -EIO;
}
init_timer(&dev->timer);
dev->timer.function = isdn_timer_funct;
spin_lock_init(&dev->lock);
spin_lock_init(&dev->timerlock);
#ifdef MODULE
dev->owner = THIS_MODULE;
#endif
mutex_init(&dev->mtx);
init_waitqueue_head(&dev->info_waitq);
for (i = 0; i < ISDN_MAX_CHANNELS; i++) {
dev->drvmap[i] = -1;
dev->chanmap[i] = -1;
dev->m_idx[i] = -1;
strcpy(dev->num[i], "???");
}
if (register_chrdev(ISDN_MAJOR, "isdn", &isdn_fops)) {
printk(KERN_WARNING "isdn: Could not register control devices\n");
vfree(dev);
return -EIO;
}
if ((isdn_tty_modem_init()) < 0) {
printk(KERN_WARNING "isdn: Could not register tty devices\n");
vfree(dev);
unregister_chrdev(ISDN_MAJOR, "isdn");
return -EIO;
}
#ifdef CONFIG_ISDN_PPP
if (isdn_ppp_init() < 0) {
printk(KERN_WARNING "isdn: Could not create PPP-device-structs\n");
isdn_tty_exit();
unregister_chrdev(ISDN_MAJOR, "isdn");
vfree(dev);
return -EIO;
}
#endif /* CONFIG_ISDN_PPP */
strcpy(tmprev, isdn_revision);
printk(KERN_NOTICE "ISDN subsystem Rev: %s/", isdn_getrev(tmprev));
strcpy(tmprev, isdn_net_revision);
printk("%s/", isdn_getrev(tmprev));
strcpy(tmprev, isdn_ppp_revision);
printk("%s/", isdn_getrev(tmprev));
strcpy(tmprev, isdn_audio_revision);
printk("%s/", isdn_getrev(tmprev));
strcpy(tmprev, isdn_v110_revision);
printk("%s", isdn_getrev(tmprev));
#ifdef MODULE
printk(" loaded\n");
#else
printk("\n");
#endif
isdn_info_update();
return 0;
}
/*
* Unload module
*/
static void __exit isdn_exit(void)
{
#ifdef CONFIG_ISDN_PPP
isdn_ppp_cleanup();
#endif
if (isdn_net_rmall() < 0) {
printk(KERN_WARNING "isdn: net-device busy, remove cancelled\n");
return;
}
isdn_tty_exit();
unregister_chrdev(ISDN_MAJOR, "isdn");
del_timer_sync(&dev->timer);
/* call vfree with interrupts enabled, else it will hang */
vfree(dev);
printk(KERN_NOTICE "ISDN-subsystem unloaded\n");
}
module_init(isdn_init);
module_exit(isdn_exit);
| gpl-2.0 |
wangshaowei/ok6410-linux | arch/mips/kernel/i8253.c | 2286 | 3247 | /*
* i8253.c 8253/PIT functions
*
*/
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/delay.h>
#include <asm/i8253.h>
#include <asm/io.h>
#include <asm/time.h>
DEFINE_RAW_SPINLOCK(i8253_lock);
EXPORT_SYMBOL(i8253_lock);
/*
* Initialize the PIT timer.
*
* This is also called after resume to bring the PIT into operation again.
*/
static void init_pit_timer(enum clock_event_mode mode,
struct clock_event_device *evt)
{
raw_spin_lock(&i8253_lock);
switch(mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* binary, mode 2, LSB/MSB, ch 0 */
outb_p(0x34, PIT_MODE);
outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
outb(LATCH >> 8 , PIT_CH0); /* MSB */
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
evt->mode == CLOCK_EVT_MODE_ONESHOT) {
outb_p(0x30, PIT_MODE);
outb_p(0, PIT_CH0);
outb_p(0, PIT_CH0);
}
break;
case CLOCK_EVT_MODE_ONESHOT:
/* One shot setup */
outb_p(0x38, PIT_MODE);
break;
case CLOCK_EVT_MODE_RESUME:
/* Nothing to do here */
break;
}
raw_spin_unlock(&i8253_lock);
}
/*
* Program the next event in oneshot mode
*
* Delta is given in PIT ticks
*/
static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
{
raw_spin_lock(&i8253_lock);
outb_p(delta & 0xff , PIT_CH0); /* LSB */
outb(delta >> 8 , PIT_CH0); /* MSB */
raw_spin_unlock(&i8253_lock);
return 0;
}
/*
* On UP the PIT can serve all of the possible timer functions. On SMP systems
* it can be solely used for the global tick.
*
* The profiling and update capabilites are switched off once the local apic is
* registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
* !using_apic_timer decisions in do_timer_interrupt_hook()
*/
static struct clock_event_device pit_clockevent = {
.name = "pit",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = init_pit_timer,
.set_next_event = pit_next_event,
.irq = 0,
};
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
pit_clockevent.event_handler(&pit_clockevent);
return IRQ_HANDLED;
}
static struct irqaction irq0 = {
.handler = timer_interrupt,
.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
.name = "timer"
};
/*
* Initialize the conversion factor and the min/max deltas of the clock event
* structure and register the clock event source with the framework.
*/
void __init setup_pit_timer(void)
{
struct clock_event_device *cd = &pit_clockevent;
unsigned int cpu = smp_processor_id();
/*
* Start pit with the boot cpu mask and make it global after the
* IO_APIC has been initialized.
*/
cd->cpumask = cpumask_of(cpu);
clockevent_set_clock(cd, CLOCK_TICK_RATE);
cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
clockevents_register_device(cd);
setup_irq(0, &irq0);
}
static int __init init_pit_clocksource(void)
{
if (num_possible_cpus() > 1) /* PIT does not scale! */
return 0;
return clocksource_i8253_init();
}
arch_initcall(init_pit_clocksource);
| gpl-2.0 |
gdetal/mptcp_nexus5 | fs/ext4/resize.c | 2542 | 50395 | /*
* linux/fs/ext4/resize.c
*
* Support for resizing an ext4 filesystem while it is mounted.
*
* Copyright (C) 2001, 2002 Andreas Dilger <adilger@clusterfs.com>
*
* This could probably be made into a module, because it is not often in use.
*/
#define EXT4FS_DEBUG
#include <linux/errno.h>
#include <linux/slab.h>
#include "ext4_jbd2.h"
int ext4_resize_begin(struct super_block *sb)
{
int ret = 0;
if (!capable(CAP_SYS_RESOURCE))
return -EPERM;
/*
* We are not allowed to do online-resizing on a filesystem mounted
* with error, because it can destroy the filesystem easily.
*/
if (EXT4_SB(sb)->s_mount_state & EXT4_ERROR_FS) {
ext4_warning(sb, "There are errors in the filesystem, "
"so online resizing is not allowed\n");
return -EPERM;
}
if (test_and_set_bit_lock(EXT4_RESIZING, &EXT4_SB(sb)->s_resize_flags))
ret = -EBUSY;
return ret;
}
void ext4_resize_end(struct super_block *sb)
{
clear_bit_unlock(EXT4_RESIZING, &EXT4_SB(sb)->s_resize_flags);
smp_mb__after_clear_bit();
}
#define outside(b, first, last) ((b) < (first) || (b) >= (last))
#define inside(b, first, last) ((b) >= (first) && (b) < (last))
static int verify_group_input(struct super_block *sb,
struct ext4_new_group_data *input)
{
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
ext4_fsblk_t start = ext4_blocks_count(es);
ext4_fsblk_t end = start + input->blocks_count;
ext4_group_t group = input->group;
ext4_fsblk_t itend = input->inode_table + sbi->s_itb_per_group;
unsigned overhead = ext4_bg_has_super(sb, group) ?
(1 + ext4_bg_num_gdb(sb, group) +
le16_to_cpu(es->s_reserved_gdt_blocks)) : 0;
ext4_fsblk_t metaend = start + overhead;
struct buffer_head *bh = NULL;
ext4_grpblk_t free_blocks_count, offset;
int err = -EINVAL;
input->free_blocks_count = free_blocks_count =
input->blocks_count - 2 - overhead - sbi->s_itb_per_group;
if (test_opt(sb, DEBUG))
printk(KERN_DEBUG "EXT4-fs: adding %s group %u: %u blocks "
"(%d free, %u reserved)\n",
ext4_bg_has_super(sb, input->group) ? "normal" :
"no-super", input->group, input->blocks_count,
free_blocks_count, input->reserved_blocks);
ext4_get_group_no_and_offset(sb, start, NULL, &offset);
if (group != sbi->s_groups_count)
ext4_warning(sb, "Cannot add at group %u (only %u groups)",
input->group, sbi->s_groups_count);
else if (offset != 0)
ext4_warning(sb, "Last group not full");
else if (input->reserved_blocks > input->blocks_count / 5)
ext4_warning(sb, "Reserved blocks too high (%u)",
input->reserved_blocks);
else if (free_blocks_count < 0)
ext4_warning(sb, "Bad blocks count %u",
input->blocks_count);
else if (!(bh = sb_bread(sb, end - 1)))
ext4_warning(sb, "Cannot read last block (%llu)",
end - 1);
else if (outside(input->block_bitmap, start, end))
ext4_warning(sb, "Block bitmap not in group (block %llu)",
(unsigned long long)input->block_bitmap);
else if (outside(input->inode_bitmap, start, end))
ext4_warning(sb, "Inode bitmap not in group (block %llu)",
(unsigned long long)input->inode_bitmap);
else if (outside(input->inode_table, start, end) ||
outside(itend - 1, start, end))
ext4_warning(sb, "Inode table not in group (blocks %llu-%llu)",
(unsigned long long)input->inode_table, itend - 1);
else if (input->inode_bitmap == input->block_bitmap)
ext4_warning(sb, "Block bitmap same as inode bitmap (%llu)",
(unsigned long long)input->block_bitmap);
else if (inside(input->block_bitmap, input->inode_table, itend))
ext4_warning(sb, "Block bitmap (%llu) in inode table "
"(%llu-%llu)",
(unsigned long long)input->block_bitmap,
(unsigned long long)input->inode_table, itend - 1);
else if (inside(input->inode_bitmap, input->inode_table, itend))
ext4_warning(sb, "Inode bitmap (%llu) in inode table "
"(%llu-%llu)",
(unsigned long long)input->inode_bitmap,
(unsigned long long)input->inode_table, itend - 1);
else if (inside(input->block_bitmap, start, metaend))
ext4_warning(sb, "Block bitmap (%llu) in GDT table (%llu-%llu)",
(unsigned long long)input->block_bitmap,
start, metaend - 1);
else if (inside(input->inode_bitmap, start, metaend))
ext4_warning(sb, "Inode bitmap (%llu) in GDT table (%llu-%llu)",
(unsigned long long)input->inode_bitmap,
start, metaend - 1);
else if (inside(input->inode_table, start, metaend) ||
inside(itend - 1, start, metaend))
ext4_warning(sb, "Inode table (%llu-%llu) overlaps GDT table "
"(%llu-%llu)",
(unsigned long long)input->inode_table,
itend - 1, start, metaend - 1);
else
err = 0;
brelse(bh);
return err;
}
/*
* ext4_new_flex_group_data is used by 64bit-resize interface to add a flex
* group each time.
*/
struct ext4_new_flex_group_data {
struct ext4_new_group_data *groups; /* new_group_data for groups
in the flex group */
__u16 *bg_flags; /* block group flags of groups
in @groups */
ext4_group_t count; /* number of groups in @groups
*/
};
/*
* alloc_flex_gd() allocates a ext4_new_flex_group_data with size of
* @flexbg_size.
*
* Returns NULL on failure otherwise address of the allocated structure.
*/
static struct ext4_new_flex_group_data *alloc_flex_gd(unsigned long flexbg_size)
{
struct ext4_new_flex_group_data *flex_gd;
flex_gd = kmalloc(sizeof(*flex_gd), GFP_NOFS);
if (flex_gd == NULL)
goto out3;
flex_gd->count = flexbg_size;
flex_gd->groups = kmalloc(sizeof(struct ext4_new_group_data) *
flexbg_size, GFP_NOFS);
if (flex_gd->groups == NULL)
goto out2;
flex_gd->bg_flags = kmalloc(flexbg_size * sizeof(__u16), GFP_NOFS);
if (flex_gd->bg_flags == NULL)
goto out1;
return flex_gd;
out1:
kfree(flex_gd->groups);
out2:
kfree(flex_gd);
out3:
return NULL;
}
static void free_flex_gd(struct ext4_new_flex_group_data *flex_gd)
{
kfree(flex_gd->bg_flags);
kfree(flex_gd->groups);
kfree(flex_gd);
}
/*
* ext4_alloc_group_tables() allocates block bitmaps, inode bitmaps
* and inode tables for a flex group.
*
* This function is used by 64bit-resize. Note that this function allocates
* group tables from the 1st group of groups contained by @flexgd, which may
* be a partial of a flex group.
*
* @sb: super block of fs to which the groups belongs
*/
static void ext4_alloc_group_tables(struct super_block *sb,
struct ext4_new_flex_group_data *flex_gd,
int flexbg_size)
{
struct ext4_new_group_data *group_data = flex_gd->groups;
struct ext4_super_block *es = EXT4_SB(sb)->s_es;
ext4_fsblk_t start_blk;
ext4_fsblk_t last_blk;
ext4_group_t src_group;
ext4_group_t bb_index = 0;
ext4_group_t ib_index = 0;
ext4_group_t it_index = 0;
ext4_group_t group;
ext4_group_t last_group;
unsigned overhead;
BUG_ON(flex_gd->count == 0 || group_data == NULL);
src_group = group_data[0].group;
last_group = src_group + flex_gd->count - 1;
BUG_ON((flexbg_size > 1) && ((src_group & ~(flexbg_size - 1)) !=
(last_group & ~(flexbg_size - 1))));
next_group:
group = group_data[0].group;
start_blk = ext4_group_first_block_no(sb, src_group);
last_blk = start_blk + group_data[src_group - group].blocks_count;
overhead = ext4_bg_has_super(sb, src_group) ?
(1 + ext4_bg_num_gdb(sb, src_group) +
le16_to_cpu(es->s_reserved_gdt_blocks)) : 0;
start_blk += overhead;
BUG_ON(src_group >= group_data[0].group + flex_gd->count);
/* We collect contiguous blocks as much as possible. */
src_group++;
for (; src_group <= last_group; src_group++)
if (!ext4_bg_has_super(sb, src_group))
last_blk += group_data[src_group - group].blocks_count;
else
break;
/* Allocate block bitmaps */
for (; bb_index < flex_gd->count; bb_index++) {
if (start_blk >= last_blk)
goto next_group;
group_data[bb_index].block_bitmap = start_blk++;
ext4_get_group_no_and_offset(sb, start_blk - 1, &group, NULL);
group -= group_data[0].group;
group_data[group].free_blocks_count--;
if (flexbg_size > 1)
flex_gd->bg_flags[group] &= ~EXT4_BG_BLOCK_UNINIT;
}
/* Allocate inode bitmaps */
for (; ib_index < flex_gd->count; ib_index++) {
if (start_blk >= last_blk)
goto next_group;
group_data[ib_index].inode_bitmap = start_blk++;
ext4_get_group_no_and_offset(sb, start_blk - 1, &group, NULL);
group -= group_data[0].group;
group_data[group].free_blocks_count--;
if (flexbg_size > 1)
flex_gd->bg_flags[group] &= ~EXT4_BG_BLOCK_UNINIT;
}
/* Allocate inode tables */
for (; it_index < flex_gd->count; it_index++) {
if (start_blk + EXT4_SB(sb)->s_itb_per_group > last_blk)
goto next_group;
group_data[it_index].inode_table = start_blk;
ext4_get_group_no_and_offset(sb, start_blk, &group, NULL);
group -= group_data[0].group;
group_data[group].free_blocks_count -=
EXT4_SB(sb)->s_itb_per_group;
if (flexbg_size > 1)
flex_gd->bg_flags[group] &= ~EXT4_BG_BLOCK_UNINIT;
start_blk += EXT4_SB(sb)->s_itb_per_group;
}
if (test_opt(sb, DEBUG)) {
int i;
group = group_data[0].group;
printk(KERN_DEBUG "EXT4-fs: adding a flex group with "
"%d groups, flexbg size is %d:\n", flex_gd->count,
flexbg_size);
for (i = 0; i < flex_gd->count; i++) {
printk(KERN_DEBUG "adding %s group %u: %u "
"blocks (%d free)\n",
ext4_bg_has_super(sb, group + i) ? "normal" :
"no-super", group + i,
group_data[i].blocks_count,
group_data[i].free_blocks_count);
}
}
}
static struct buffer_head *bclean(handle_t *handle, struct super_block *sb,
ext4_fsblk_t blk)
{
struct buffer_head *bh;
int err;
bh = sb_getblk(sb, blk);
if (!bh)
return ERR_PTR(-EIO);
if ((err = ext4_journal_get_write_access(handle, bh))) {
brelse(bh);
bh = ERR_PTR(err);
} else {
memset(bh->b_data, 0, sb->s_blocksize);
set_buffer_uptodate(bh);
}
return bh;
}
/*
* If we have fewer than thresh credits, extend by EXT4_MAX_TRANS_DATA.
* If that fails, restart the transaction & regain write access for the
* buffer head which is used for block_bitmap modifications.
*/
static int extend_or_restart_transaction(handle_t *handle, int thresh)
{
int err;
if (ext4_handle_has_enough_credits(handle, thresh))
return 0;
err = ext4_journal_extend(handle, EXT4_MAX_TRANS_DATA);
if (err < 0)
return err;
if (err) {
err = ext4_journal_restart(handle, EXT4_MAX_TRANS_DATA);
if (err)
return err;
}
return 0;
}
/*
* set_flexbg_block_bitmap() mark @count blocks starting from @block used.
*
* Helper function for ext4_setup_new_group_blocks() which set .
*
* @sb: super block
* @handle: journal handle
* @flex_gd: flex group data
*/
static int set_flexbg_block_bitmap(struct super_block *sb, handle_t *handle,
struct ext4_new_flex_group_data *flex_gd,
ext4_fsblk_t block, ext4_group_t count)
{
ext4_group_t count2;
ext4_debug("mark blocks [%llu/%u] used\n", block, count);
for (count2 = count; count > 0; count -= count2, block += count2) {
ext4_fsblk_t start;
struct buffer_head *bh;
ext4_group_t group;
int err;
ext4_get_group_no_and_offset(sb, block, &group, NULL);
start = ext4_group_first_block_no(sb, group);
group -= flex_gd->groups[0].group;
count2 = sb->s_blocksize * 8 - (block - start);
if (count2 > count)
count2 = count;
if (flex_gd->bg_flags[group] & EXT4_BG_BLOCK_UNINIT) {
BUG_ON(flex_gd->count > 1);
continue;
}
err = extend_or_restart_transaction(handle, 1);
if (err)
return err;
bh = sb_getblk(sb, flex_gd->groups[group].block_bitmap);
if (!bh)
return -EIO;
err = ext4_journal_get_write_access(handle, bh);
if (err)
return err;
ext4_debug("mark block bitmap %#04llx (+%llu/%u)\n", block,
block - start, count2);
ext4_set_bits(bh->b_data, block - start, count2);
err = ext4_handle_dirty_metadata(handle, NULL, bh);
if (unlikely(err))
return err;
brelse(bh);
}
return 0;
}
/*
* Set up the block and inode bitmaps, and the inode table for the new groups.
* This doesn't need to be part of the main transaction, since we are only
* changing blocks outside the actual filesystem. We still do journaling to
* ensure the recovery is correct in case of a failure just after resize.
* If any part of this fails, we simply abort the resize.
*
* setup_new_flex_group_blocks handles a flex group as follow:
* 1. copy super block and GDT, and initialize group tables if necessary.
* In this step, we only set bits in blocks bitmaps for blocks taken by
* super block and GDT.
* 2. allocate group tables in block bitmaps, that is, set bits in block
* bitmap for blocks taken by group tables.
*/
static int setup_new_flex_group_blocks(struct super_block *sb,
struct ext4_new_flex_group_data *flex_gd)
{
int group_table_count[] = {1, 1, EXT4_SB(sb)->s_itb_per_group};
ext4_fsblk_t start;
ext4_fsblk_t block;
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
struct ext4_new_group_data *group_data = flex_gd->groups;
__u16 *bg_flags = flex_gd->bg_flags;
handle_t *handle;
ext4_group_t group, count;
struct buffer_head *bh = NULL;
int reserved_gdb, i, j, err = 0, err2;
BUG_ON(!flex_gd->count || !group_data ||
group_data[0].group != sbi->s_groups_count);
reserved_gdb = le16_to_cpu(es->s_reserved_gdt_blocks);
/* This transaction may be extended/restarted along the way */
handle = ext4_journal_start_sb(sb, EXT4_MAX_TRANS_DATA);
if (IS_ERR(handle))
return PTR_ERR(handle);
group = group_data[0].group;
for (i = 0; i < flex_gd->count; i++, group++) {
unsigned long gdblocks;
gdblocks = ext4_bg_num_gdb(sb, group);
start = ext4_group_first_block_no(sb, group);
/* Copy all of the GDT blocks into the backup in this group */
for (j = 0, block = start + 1; j < gdblocks; j++, block++) {
struct buffer_head *gdb;
ext4_debug("update backup group %#04llx\n", block);
err = extend_or_restart_transaction(handle, 1);
if (err)
goto out;
gdb = sb_getblk(sb, block);
if (!gdb) {
err = -EIO;
goto out;
}
err = ext4_journal_get_write_access(handle, gdb);
if (err) {
brelse(gdb);
goto out;
}
memcpy(gdb->b_data, sbi->s_group_desc[j]->b_data,
gdb->b_size);
set_buffer_uptodate(gdb);
err = ext4_handle_dirty_metadata(handle, NULL, gdb);
if (unlikely(err)) {
brelse(gdb);
goto out;
}
brelse(gdb);
}
/* Zero out all of the reserved backup group descriptor
* table blocks
*/
if (ext4_bg_has_super(sb, group)) {
err = sb_issue_zeroout(sb, gdblocks + start + 1,
reserved_gdb, GFP_NOFS);
if (err)
goto out;
}
/* Initialize group tables of the grop @group */
if (!(bg_flags[i] & EXT4_BG_INODE_ZEROED))
goto handle_bb;
/* Zero out all of the inode table blocks */
block = group_data[i].inode_table;
ext4_debug("clear inode table blocks %#04llx -> %#04lx\n",
block, sbi->s_itb_per_group);
err = sb_issue_zeroout(sb, block, sbi->s_itb_per_group,
GFP_NOFS);
if (err)
goto out;
handle_bb:
if (bg_flags[i] & EXT4_BG_BLOCK_UNINIT)
goto handle_ib;
/* Initialize block bitmap of the @group */
block = group_data[i].block_bitmap;
err = extend_or_restart_transaction(handle, 1);
if (err)
goto out;
bh = bclean(handle, sb, block);
if (IS_ERR(bh)) {
err = PTR_ERR(bh);
goto out;
}
if (ext4_bg_has_super(sb, group)) {
ext4_debug("mark backup superblock %#04llx (+0)\n",
start);
ext4_set_bits(bh->b_data, 0, gdblocks + reserved_gdb +
1);
}
ext4_mark_bitmap_end(group_data[i].blocks_count,
sb->s_blocksize * 8, bh->b_data);
err = ext4_handle_dirty_metadata(handle, NULL, bh);
if (err)
goto out;
brelse(bh);
handle_ib:
if (bg_flags[i] & EXT4_BG_INODE_UNINIT)
continue;
/* Initialize inode bitmap of the @group */
block = group_data[i].inode_bitmap;
err = extend_or_restart_transaction(handle, 1);
if (err)
goto out;
/* Mark unused entries in inode bitmap used */
bh = bclean(handle, sb, block);
if (IS_ERR(bh)) {
err = PTR_ERR(bh);
goto out;
}
ext4_mark_bitmap_end(EXT4_INODES_PER_GROUP(sb),
sb->s_blocksize * 8, bh->b_data);
err = ext4_handle_dirty_metadata(handle, NULL, bh);
if (err)
goto out;
brelse(bh);
}
bh = NULL;
/* Mark group tables in block bitmap */
for (j = 0; j < GROUP_TABLE_COUNT; j++) {
count = group_table_count[j];
start = (&group_data[0].block_bitmap)[j];
block = start;
for (i = 1; i < flex_gd->count; i++) {
block += group_table_count[j];
if (block == (&group_data[i].block_bitmap)[j]) {
count += group_table_count[j];
continue;
}
err = set_flexbg_block_bitmap(sb, handle,
flex_gd, start, count);
if (err)
goto out;
count = group_table_count[j];
start = group_data[i].block_bitmap;
block = start;
}
if (count) {
err = set_flexbg_block_bitmap(sb, handle,
flex_gd, start, count);
if (err)
goto out;
}
}
out:
brelse(bh);
err2 = ext4_journal_stop(handle);
if (err2 && !err)
err = err2;
return err;
}
/*
* Iterate through the groups which hold BACKUP superblock/GDT copies in an
* ext4 filesystem. The counters should be initialized to 1, 5, and 7 before
* calling this for the first time. In a sparse filesystem it will be the
* sequence of powers of 3, 5, and 7: 1, 3, 5, 7, 9, 25, 27, 49, 81, ...
* For a non-sparse filesystem it will be every group: 1, 2, 3, 4, ...
*/
static unsigned ext4_list_backups(struct super_block *sb, unsigned *three,
unsigned *five, unsigned *seven)
{
unsigned *min = three;
int mult = 3;
unsigned ret;
if (!EXT4_HAS_RO_COMPAT_FEATURE(sb,
EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER)) {
ret = *min;
*min += 1;
return ret;
}
if (*five < *min) {
min = five;
mult = 5;
}
if (*seven < *min) {
min = seven;
mult = 7;
}
ret = *min;
*min *= mult;
return ret;
}
/*
* Check that all of the backup GDT blocks are held in the primary GDT block.
* It is assumed that they are stored in group order. Returns the number of
* groups in current filesystem that have BACKUPS, or -ve error code.
*/
static int verify_reserved_gdb(struct super_block *sb,
ext4_group_t end,
struct buffer_head *primary)
{
const ext4_fsblk_t blk = primary->b_blocknr;
unsigned three = 1;
unsigned five = 5;
unsigned seven = 7;
unsigned grp;
__le32 *p = (__le32 *)primary->b_data;
int gdbackups = 0;
while ((grp = ext4_list_backups(sb, &three, &five, &seven)) < end) {
if (le32_to_cpu(*p++) !=
grp * EXT4_BLOCKS_PER_GROUP(sb) + blk){
ext4_warning(sb, "reserved GDT %llu"
" missing grp %d (%llu)",
blk, grp,
grp *
(ext4_fsblk_t)EXT4_BLOCKS_PER_GROUP(sb) +
blk);
return -EINVAL;
}
if (++gdbackups > EXT4_ADDR_PER_BLOCK(sb))
return -EFBIG;
}
return gdbackups;
}
/*
* Called when we need to bring a reserved group descriptor table block into
* use from the resize inode. The primary copy of the new GDT block currently
* is an indirect block (under the double indirect block in the resize inode).
* The new backup GDT blocks will be stored as leaf blocks in this indirect
* block, in group order. Even though we know all the block numbers we need,
* we check to ensure that the resize inode has actually reserved these blocks.
*
* Don't need to update the block bitmaps because the blocks are still in use.
*
* We get all of the error cases out of the way, so that we are sure to not
* fail once we start modifying the data on disk, because JBD has no rollback.
*/
static int add_new_gdb(handle_t *handle, struct inode *inode,
ext4_group_t group)
{
struct super_block *sb = inode->i_sb;
struct ext4_super_block *es = EXT4_SB(sb)->s_es;
unsigned long gdb_num = group / EXT4_DESC_PER_BLOCK(sb);
ext4_fsblk_t gdblock = EXT4_SB(sb)->s_sbh->b_blocknr + 1 + gdb_num;
struct buffer_head **o_group_desc, **n_group_desc;
struct buffer_head *dind;
struct buffer_head *gdb_bh;
int gdbackups;
struct ext4_iloc iloc;
__le32 *data;
int err;
if (test_opt(sb, DEBUG))
printk(KERN_DEBUG
"EXT4-fs: ext4_add_new_gdb: adding group block %lu\n",
gdb_num);
/*
* If we are not using the primary superblock/GDT copy don't resize,
* because the user tools have no way of handling this. Probably a
* bad time to do it anyways.
*/
if (EXT4_SB(sb)->s_sbh->b_blocknr !=
le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block)) {
ext4_warning(sb, "won't resize using backup superblock at %llu",
(unsigned long long)EXT4_SB(sb)->s_sbh->b_blocknr);
return -EPERM;
}
gdb_bh = sb_bread(sb, gdblock);
if (!gdb_bh)
return -EIO;
gdbackups = verify_reserved_gdb(sb, group, gdb_bh);
if (gdbackups < 0) {
err = gdbackups;
goto exit_bh;
}
data = EXT4_I(inode)->i_data + EXT4_DIND_BLOCK;
dind = sb_bread(sb, le32_to_cpu(*data));
if (!dind) {
err = -EIO;
goto exit_bh;
}
data = (__le32 *)dind->b_data;
if (le32_to_cpu(data[gdb_num % EXT4_ADDR_PER_BLOCK(sb)]) != gdblock) {
ext4_warning(sb, "new group %u GDT block %llu not reserved",
group, gdblock);
err = -EINVAL;
goto exit_dind;
}
err = ext4_journal_get_write_access(handle, EXT4_SB(sb)->s_sbh);
if (unlikely(err))
goto exit_dind;
err = ext4_journal_get_write_access(handle, gdb_bh);
if (unlikely(err))
goto exit_sbh;
err = ext4_journal_get_write_access(handle, dind);
if (unlikely(err))
ext4_std_error(sb, err);
/* ext4_reserve_inode_write() gets a reference on the iloc */
err = ext4_reserve_inode_write(handle, inode, &iloc);
if (unlikely(err))
goto exit_dindj;
n_group_desc = ext4_kvmalloc((gdb_num + 1) *
sizeof(struct buffer_head *),
GFP_NOFS);
if (!n_group_desc) {
err = -ENOMEM;
ext4_warning(sb, "not enough memory for %lu groups",
gdb_num + 1);
goto exit_inode;
}
/*
* Finally, we have all of the possible failures behind us...
*
* Remove new GDT block from inode double-indirect block and clear out
* the new GDT block for use (which also "frees" the backup GDT blocks
* from the reserved inode). We don't need to change the bitmaps for
* these blocks, because they are marked as in-use from being in the
* reserved inode, and will become GDT blocks (primary and backup).
*/
data[gdb_num % EXT4_ADDR_PER_BLOCK(sb)] = 0;
err = ext4_handle_dirty_metadata(handle, NULL, dind);
if (unlikely(err)) {
ext4_std_error(sb, err);
goto exit_inode;
}
inode->i_blocks -= (gdbackups + 1) * sb->s_blocksize >> 9;
ext4_mark_iloc_dirty(handle, inode, &iloc);
memset(gdb_bh->b_data, 0, sb->s_blocksize);
err = ext4_handle_dirty_metadata(handle, NULL, gdb_bh);
if (unlikely(err)) {
ext4_std_error(sb, err);
goto exit_inode;
}
brelse(dind);
o_group_desc = EXT4_SB(sb)->s_group_desc;
memcpy(n_group_desc, o_group_desc,
EXT4_SB(sb)->s_gdb_count * sizeof(struct buffer_head *));
n_group_desc[gdb_num] = gdb_bh;
EXT4_SB(sb)->s_group_desc = n_group_desc;
EXT4_SB(sb)->s_gdb_count++;
ext4_kvfree(o_group_desc);
le16_add_cpu(&es->s_reserved_gdt_blocks, -1);
err = ext4_handle_dirty_metadata(handle, NULL, EXT4_SB(sb)->s_sbh);
if (err)
ext4_std_error(sb, err);
return err;
exit_inode:
ext4_kvfree(n_group_desc);
/* ext4_handle_release_buffer(handle, iloc.bh); */
brelse(iloc.bh);
exit_dindj:
/* ext4_handle_release_buffer(handle, dind); */
exit_sbh:
/* ext4_handle_release_buffer(handle, EXT4_SB(sb)->s_sbh); */
exit_dind:
brelse(dind);
exit_bh:
brelse(gdb_bh);
ext4_debug("leaving with error %d\n", err);
return err;
}
/*
* Called when we are adding a new group which has a backup copy of each of
* the GDT blocks (i.e. sparse group) and there are reserved GDT blocks.
* We need to add these reserved backup GDT blocks to the resize inode, so
* that they are kept for future resizing and not allocated to files.
*
* Each reserved backup GDT block will go into a different indirect block.
* The indirect blocks are actually the primary reserved GDT blocks,
* so we know in advance what their block numbers are. We only get the
* double-indirect block to verify it is pointing to the primary reserved
* GDT blocks so we don't overwrite a data block by accident. The reserved
* backup GDT blocks are stored in their reserved primary GDT block.
*/
static int reserve_backup_gdb(handle_t *handle, struct inode *inode,
ext4_group_t group)
{
struct super_block *sb = inode->i_sb;
int reserved_gdb =le16_to_cpu(EXT4_SB(sb)->s_es->s_reserved_gdt_blocks);
struct buffer_head **primary;
struct buffer_head *dind;
struct ext4_iloc iloc;
ext4_fsblk_t blk;
__le32 *data, *end;
int gdbackups = 0;
int res, i;
int err;
primary = kmalloc(reserved_gdb * sizeof(*primary), GFP_NOFS);
if (!primary)
return -ENOMEM;
data = EXT4_I(inode)->i_data + EXT4_DIND_BLOCK;
dind = sb_bread(sb, le32_to_cpu(*data));
if (!dind) {
err = -EIO;
goto exit_free;
}
blk = EXT4_SB(sb)->s_sbh->b_blocknr + 1 + EXT4_SB(sb)->s_gdb_count;
data = (__le32 *)dind->b_data + (EXT4_SB(sb)->s_gdb_count %
EXT4_ADDR_PER_BLOCK(sb));
end = (__le32 *)dind->b_data + EXT4_ADDR_PER_BLOCK(sb);
/* Get each reserved primary GDT block and verify it holds backups */
for (res = 0; res < reserved_gdb; res++, blk++) {
if (le32_to_cpu(*data) != blk) {
ext4_warning(sb, "reserved block %llu"
" not at offset %ld",
blk,
(long)(data - (__le32 *)dind->b_data));
err = -EINVAL;
goto exit_bh;
}
primary[res] = sb_bread(sb, blk);
if (!primary[res]) {
err = -EIO;
goto exit_bh;
}
gdbackups = verify_reserved_gdb(sb, group, primary[res]);
if (gdbackups < 0) {
brelse(primary[res]);
err = gdbackups;
goto exit_bh;
}
if (++data >= end)
data = (__le32 *)dind->b_data;
}
for (i = 0; i < reserved_gdb; i++) {
if ((err = ext4_journal_get_write_access(handle, primary[i]))) {
/*
int j;
for (j = 0; j < i; j++)
ext4_handle_release_buffer(handle, primary[j]);
*/
goto exit_bh;
}
}
if ((err = ext4_reserve_inode_write(handle, inode, &iloc)))
goto exit_bh;
/*
* Finally we can add each of the reserved backup GDT blocks from
* the new group to its reserved primary GDT block.
*/
blk = group * EXT4_BLOCKS_PER_GROUP(sb);
for (i = 0; i < reserved_gdb; i++) {
int err2;
data = (__le32 *)primary[i]->b_data;
/* printk("reserving backup %lu[%u] = %lu\n",
primary[i]->b_blocknr, gdbackups,
blk + primary[i]->b_blocknr); */
data[gdbackups] = cpu_to_le32(blk + primary[i]->b_blocknr);
err2 = ext4_handle_dirty_metadata(handle, NULL, primary[i]);
if (!err)
err = err2;
}
inode->i_blocks += reserved_gdb * sb->s_blocksize >> 9;
ext4_mark_iloc_dirty(handle, inode, &iloc);
exit_bh:
while (--res >= 0)
brelse(primary[res]);
brelse(dind);
exit_free:
kfree(primary);
return err;
}
/*
* Update the backup copies of the ext4 metadata. These don't need to be part
* of the main resize transaction, because e2fsck will re-write them if there
* is a problem (basically only OOM will cause a problem). However, we
* _should_ update the backups if possible, in case the primary gets trashed
* for some reason and we need to run e2fsck from a backup superblock. The
* important part is that the new block and inode counts are in the backup
* superblocks, and the location of the new group metadata in the GDT backups.
*
* We do not need take the s_resize_lock for this, because these
* blocks are not otherwise touched by the filesystem code when it is
* mounted. We don't need to worry about last changing from
* sbi->s_groups_count, because the worst that can happen is that we
* do not copy the full number of backups at this time. The resize
* which changed s_groups_count will backup again.
*/
static void update_backups(struct super_block *sb,
int blk_off, char *data, int size)
{
struct ext4_sb_info *sbi = EXT4_SB(sb);
const ext4_group_t last = sbi->s_groups_count;
const int bpg = EXT4_BLOCKS_PER_GROUP(sb);
unsigned three = 1;
unsigned five = 5;
unsigned seven = 7;
ext4_group_t group;
int rest = sb->s_blocksize - size;
handle_t *handle;
int err = 0, err2;
handle = ext4_journal_start_sb(sb, EXT4_MAX_TRANS_DATA);
if (IS_ERR(handle)) {
group = 1;
err = PTR_ERR(handle);
goto exit_err;
}
while ((group = ext4_list_backups(sb, &three, &five, &seven)) < last) {
struct buffer_head *bh;
/* Out of journal space, and can't get more - abort - so sad */
if (ext4_handle_valid(handle) &&
handle->h_buffer_credits == 0 &&
ext4_journal_extend(handle, EXT4_MAX_TRANS_DATA) &&
(err = ext4_journal_restart(handle, EXT4_MAX_TRANS_DATA)))
break;
bh = sb_getblk(sb, group * bpg + blk_off);
if (!bh) {
err = -EIO;
break;
}
ext4_debug("update metadata backup %#04lx\n",
(unsigned long)bh->b_blocknr);
if ((err = ext4_journal_get_write_access(handle, bh)))
break;
lock_buffer(bh);
memcpy(bh->b_data, data, size);
if (rest)
memset(bh->b_data + size, 0, rest);
set_buffer_uptodate(bh);
unlock_buffer(bh);
err = ext4_handle_dirty_metadata(handle, NULL, bh);
if (unlikely(err))
ext4_std_error(sb, err);
brelse(bh);
}
if ((err2 = ext4_journal_stop(handle)) && !err)
err = err2;
/*
* Ugh! Need to have e2fsck write the backup copies. It is too
* late to revert the resize, we shouldn't fail just because of
* the backup copies (they are only needed in case of corruption).
*
* However, if we got here we have a journal problem too, so we
* can't really start a transaction to mark the superblock.
* Chicken out and just set the flag on the hope it will be written
* to disk, and if not - we will simply wait until next fsck.
*/
exit_err:
if (err) {
ext4_warning(sb, "can't update backup for group %u (err %d), "
"forcing fsck on next reboot", group, err);
sbi->s_mount_state &= ~EXT4_VALID_FS;
sbi->s_es->s_state &= cpu_to_le16(~EXT4_VALID_FS);
mark_buffer_dirty(sbi->s_sbh);
}
}
/*
* ext4_add_new_descs() adds @count group descriptor of groups
* starting at @group
*
* @handle: journal handle
* @sb: super block
* @group: the group no. of the first group desc to be added
* @resize_inode: the resize inode
* @count: number of group descriptors to be added
*/
static int ext4_add_new_descs(handle_t *handle, struct super_block *sb,
ext4_group_t group, struct inode *resize_inode,
ext4_group_t count)
{
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
struct buffer_head *gdb_bh;
int i, gdb_off, gdb_num, err = 0;
for (i = 0; i < count; i++, group++) {
int reserved_gdb = ext4_bg_has_super(sb, group) ?
le16_to_cpu(es->s_reserved_gdt_blocks) : 0;
gdb_off = group % EXT4_DESC_PER_BLOCK(sb);
gdb_num = group / EXT4_DESC_PER_BLOCK(sb);
/*
* We will only either add reserved group blocks to a backup group
* or remove reserved blocks for the first group in a new group block.
* Doing both would be mean more complex code, and sane people don't
* use non-sparse filesystems anymore. This is already checked above.
*/
if (gdb_off) {
gdb_bh = sbi->s_group_desc[gdb_num];
err = ext4_journal_get_write_access(handle, gdb_bh);
if (!err && reserved_gdb && ext4_bg_num_gdb(sb, group))
err = reserve_backup_gdb(handle, resize_inode, group);
} else
err = add_new_gdb(handle, resize_inode, group);
if (err)
break;
}
return err;
}
/*
* ext4_setup_new_descs() will set up the group descriptor descriptors of a flex bg
*/
static int ext4_setup_new_descs(handle_t *handle, struct super_block *sb,
struct ext4_new_flex_group_data *flex_gd)
{
struct ext4_new_group_data *group_data = flex_gd->groups;
struct ext4_group_desc *gdp;
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct buffer_head *gdb_bh;
ext4_group_t group;
__u16 *bg_flags = flex_gd->bg_flags;
int i, gdb_off, gdb_num, err = 0;
for (i = 0; i < flex_gd->count; i++, group_data++, bg_flags++) {
group = group_data->group;
gdb_off = group % EXT4_DESC_PER_BLOCK(sb);
gdb_num = group / EXT4_DESC_PER_BLOCK(sb);
/*
* get_write_access() has been called on gdb_bh by ext4_add_new_desc().
*/
gdb_bh = sbi->s_group_desc[gdb_num];
/* Update group descriptor block for new group */
gdp = (struct ext4_group_desc *)((char *)gdb_bh->b_data +
gdb_off * EXT4_DESC_SIZE(sb));
memset(gdp, 0, EXT4_DESC_SIZE(sb));
ext4_block_bitmap_set(sb, gdp, group_data->block_bitmap);
ext4_inode_bitmap_set(sb, gdp, group_data->inode_bitmap);
ext4_inode_table_set(sb, gdp, group_data->inode_table);
ext4_free_group_clusters_set(sb, gdp,
EXT4_B2C(sbi, group_data->free_blocks_count));
ext4_free_inodes_set(sb, gdp, EXT4_INODES_PER_GROUP(sb));
gdp->bg_flags = cpu_to_le16(*bg_flags);
gdp->bg_checksum = ext4_group_desc_csum(sbi, group, gdp);
err = ext4_handle_dirty_metadata(handle, NULL, gdb_bh);
if (unlikely(err)) {
ext4_std_error(sb, err);
break;
}
/*
* We can allocate memory for mb_alloc based on the new group
* descriptor
*/
err = ext4_mb_add_groupinfo(sb, group, gdp);
if (err)
break;
}
return err;
}
/*
* ext4_update_super() updates the super block so that the newly added
* groups can be seen by the filesystem.
*
* @sb: super block
* @flex_gd: new added groups
*/
static void ext4_update_super(struct super_block *sb,
struct ext4_new_flex_group_data *flex_gd)
{
ext4_fsblk_t blocks_count = 0;
ext4_fsblk_t free_blocks = 0;
ext4_fsblk_t reserved_blocks = 0;
struct ext4_new_group_data *group_data = flex_gd->groups;
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
int i;
BUG_ON(flex_gd->count == 0 || group_data == NULL);
/*
* Make the new blocks and inodes valid next. We do this before
* increasing the group count so that once the group is enabled,
* all of its blocks and inodes are already valid.
*
* We always allocate group-by-group, then block-by-block or
* inode-by-inode within a group, so enabling these
* blocks/inodes before the group is live won't actually let us
* allocate the new space yet.
*/
for (i = 0; i < flex_gd->count; i++) {
blocks_count += group_data[i].blocks_count;
free_blocks += group_data[i].free_blocks_count;
}
reserved_blocks = ext4_r_blocks_count(es) * 100;
do_div(reserved_blocks, ext4_blocks_count(es));
reserved_blocks *= blocks_count;
do_div(reserved_blocks, 100);
ext4_blocks_count_set(es, ext4_blocks_count(es) + blocks_count);
ext4_free_blocks_count_set(es, ext4_free_blocks_count(es) + free_blocks);
le32_add_cpu(&es->s_inodes_count, EXT4_INODES_PER_GROUP(sb) *
flex_gd->count);
le32_add_cpu(&es->s_free_inodes_count, EXT4_INODES_PER_GROUP(sb) *
flex_gd->count);
/*
* We need to protect s_groups_count against other CPUs seeing
* inconsistent state in the superblock.
*
* The precise rules we use are:
*
* * Writers must perform a smp_wmb() after updating all
* dependent data and before modifying the groups count
*
* * Readers must perform an smp_rmb() after reading the groups
* count and before reading any dependent data.
*
* NB. These rules can be relaxed when checking the group count
* while freeing data, as we can only allocate from a block
* group after serialising against the group count, and we can
* only then free after serialising in turn against that
* allocation.
*/
smp_wmb();
/* Update the global fs size fields */
sbi->s_groups_count += flex_gd->count;
/* Update the reserved block counts only once the new group is
* active. */
ext4_r_blocks_count_set(es, ext4_r_blocks_count(es) +
reserved_blocks);
/* Update the free space counts */
percpu_counter_add(&sbi->s_freeclusters_counter,
EXT4_B2C(sbi, free_blocks));
percpu_counter_add(&sbi->s_freeinodes_counter,
EXT4_INODES_PER_GROUP(sb) * flex_gd->count);
if (EXT4_HAS_INCOMPAT_FEATURE(sb,
EXT4_FEATURE_INCOMPAT_FLEX_BG) &&
sbi->s_log_groups_per_flex) {
ext4_group_t flex_group;
flex_group = ext4_flex_group(sbi, group_data[0].group);
atomic_add(EXT4_B2C(sbi, free_blocks),
&sbi->s_flex_groups[flex_group].free_clusters);
atomic_add(EXT4_INODES_PER_GROUP(sb) * flex_gd->count,
&sbi->s_flex_groups[flex_group].free_inodes);
}
if (test_opt(sb, DEBUG))
printk(KERN_DEBUG "EXT4-fs: added group %u:"
"%llu blocks(%llu free %llu reserved)\n", flex_gd->count,
blocks_count, free_blocks, reserved_blocks);
}
/* Add a flex group to an fs. Ensure we handle all possible error conditions
* _before_ we start modifying the filesystem, because we cannot abort the
* transaction and not have it write the data to disk.
*/
static int ext4_flex_group_add(struct super_block *sb,
struct inode *resize_inode,
struct ext4_new_flex_group_data *flex_gd)
{
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
ext4_fsblk_t o_blocks_count;
ext4_grpblk_t last;
ext4_group_t group;
handle_t *handle;
unsigned reserved_gdb;
int err = 0, err2 = 0, credit;
BUG_ON(!flex_gd->count || !flex_gd->groups || !flex_gd->bg_flags);
reserved_gdb = le16_to_cpu(es->s_reserved_gdt_blocks);
o_blocks_count = ext4_blocks_count(es);
ext4_get_group_no_and_offset(sb, o_blocks_count, &group, &last);
BUG_ON(last);
err = setup_new_flex_group_blocks(sb, flex_gd);
if (err)
goto exit;
/*
* We will always be modifying at least the superblock and GDT
* block. If we are adding a group past the last current GDT block,
* we will also modify the inode and the dindirect block. If we
* are adding a group with superblock/GDT backups we will also
* modify each of the reserved GDT dindirect blocks.
*/
credit = flex_gd->count * 4 + reserved_gdb;
handle = ext4_journal_start_sb(sb, credit);
if (IS_ERR(handle)) {
err = PTR_ERR(handle);
goto exit;
}
err = ext4_journal_get_write_access(handle, sbi->s_sbh);
if (err)
goto exit_journal;
group = flex_gd->groups[0].group;
BUG_ON(group != EXT4_SB(sb)->s_groups_count);
err = ext4_add_new_descs(handle, sb, group,
resize_inode, flex_gd->count);
if (err)
goto exit_journal;
err = ext4_setup_new_descs(handle, sb, flex_gd);
if (err)
goto exit_journal;
ext4_update_super(sb, flex_gd);
err = ext4_handle_dirty_super(handle, sb);
exit_journal:
err2 = ext4_journal_stop(handle);
if (!err)
err = err2;
if (!err) {
int i;
update_backups(sb, sbi->s_sbh->b_blocknr, (char *)es,
sizeof(struct ext4_super_block));
for (i = 0; i < flex_gd->count; i++, group++) {
struct buffer_head *gdb_bh;
int gdb_num;
gdb_num = group / EXT4_BLOCKS_PER_GROUP(sb);
gdb_bh = sbi->s_group_desc[gdb_num];
update_backups(sb, gdb_bh->b_blocknr, gdb_bh->b_data,
gdb_bh->b_size);
}
}
exit:
return err;
}
static int ext4_setup_next_flex_gd(struct super_block *sb,
struct ext4_new_flex_group_data *flex_gd,
ext4_fsblk_t n_blocks_count,
unsigned long flexbg_size)
{
struct ext4_super_block *es = EXT4_SB(sb)->s_es;
struct ext4_new_group_data *group_data = flex_gd->groups;
ext4_fsblk_t o_blocks_count;
ext4_group_t n_group;
ext4_group_t group;
ext4_group_t last_group;
ext4_grpblk_t last;
ext4_grpblk_t blocks_per_group;
unsigned long i;
blocks_per_group = EXT4_BLOCKS_PER_GROUP(sb);
o_blocks_count = ext4_blocks_count(es);
if (o_blocks_count == n_blocks_count)
return 0;
ext4_get_group_no_and_offset(sb, o_blocks_count, &group, &last);
BUG_ON(last);
ext4_get_group_no_and_offset(sb, n_blocks_count - 1, &n_group, &last);
last_group = group | (flexbg_size - 1);
if (last_group > n_group)
last_group = n_group;
flex_gd->count = last_group - group + 1;
for (i = 0; i < flex_gd->count; i++) {
int overhead;
group_data[i].group = group + i;
group_data[i].blocks_count = blocks_per_group;
overhead = ext4_bg_has_super(sb, group + i) ?
(1 + ext4_bg_num_gdb(sb, group + i) +
le16_to_cpu(es->s_reserved_gdt_blocks)) : 0;
group_data[i].free_blocks_count = blocks_per_group - overhead;
if (EXT4_HAS_RO_COMPAT_FEATURE(sb,
EXT4_FEATURE_RO_COMPAT_GDT_CSUM))
flex_gd->bg_flags[i] = EXT4_BG_BLOCK_UNINIT |
EXT4_BG_INODE_UNINIT;
else
flex_gd->bg_flags[i] = EXT4_BG_INODE_ZEROED;
}
if (last_group == n_group &&
EXT4_HAS_RO_COMPAT_FEATURE(sb,
EXT4_FEATURE_RO_COMPAT_GDT_CSUM))
/* We need to initialize block bitmap of last group. */
flex_gd->bg_flags[i - 1] &= ~EXT4_BG_BLOCK_UNINIT;
if ((last_group == n_group) && (last != blocks_per_group - 1)) {
group_data[i - 1].blocks_count = last + 1;
group_data[i - 1].free_blocks_count -= blocks_per_group-
last - 1;
}
return 1;
}
/* Add group descriptor data to an existing or new group descriptor block.
* Ensure we handle all possible error conditions _before_ we start modifying
* the filesystem, because we cannot abort the transaction and not have it
* write the data to disk.
*
* If we are on a GDT block boundary, we need to get the reserved GDT block.
* Otherwise, we may need to add backup GDT blocks for a sparse group.
*
* We only need to hold the superblock lock while we are actually adding
* in the new group's counts to the superblock. Prior to that we have
* not really "added" the group at all. We re-check that we are still
* adding in the last group in case things have changed since verifying.
*/
int ext4_group_add(struct super_block *sb, struct ext4_new_group_data *input)
{
struct ext4_new_flex_group_data flex_gd;
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
int reserved_gdb = ext4_bg_has_super(sb, input->group) ?
le16_to_cpu(es->s_reserved_gdt_blocks) : 0;
struct inode *inode = NULL;
int gdb_off, gdb_num;
int err;
__u16 bg_flags = 0;
gdb_num = input->group / EXT4_DESC_PER_BLOCK(sb);
gdb_off = input->group % EXT4_DESC_PER_BLOCK(sb);
if (gdb_off == 0 && !EXT4_HAS_RO_COMPAT_FEATURE(sb,
EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER)) {
ext4_warning(sb, "Can't resize non-sparse filesystem further");
return -EPERM;
}
if (ext4_blocks_count(es) + input->blocks_count <
ext4_blocks_count(es)) {
ext4_warning(sb, "blocks_count overflow");
return -EINVAL;
}
if (le32_to_cpu(es->s_inodes_count) + EXT4_INODES_PER_GROUP(sb) <
le32_to_cpu(es->s_inodes_count)) {
ext4_warning(sb, "inodes_count overflow");
return -EINVAL;
}
if (reserved_gdb || gdb_off == 0) {
if (!EXT4_HAS_COMPAT_FEATURE(sb,
EXT4_FEATURE_COMPAT_RESIZE_INODE)
|| !le16_to_cpu(es->s_reserved_gdt_blocks)) {
ext4_warning(sb,
"No reserved GDT blocks, can't resize");
return -EPERM;
}
inode = ext4_iget(sb, EXT4_RESIZE_INO);
if (IS_ERR(inode)) {
ext4_warning(sb, "Error opening resize inode");
return PTR_ERR(inode);
}
}
err = verify_group_input(sb, input);
if (err)
goto out;
flex_gd.count = 1;
flex_gd.groups = input;
flex_gd.bg_flags = &bg_flags;
err = ext4_flex_group_add(sb, inode, &flex_gd);
out:
iput(inode);
return err;
} /* ext4_group_add */
/*
* extend a group without checking assuming that checking has been done.
*/
static int ext4_group_extend_no_check(struct super_block *sb,
ext4_fsblk_t o_blocks_count, ext4_grpblk_t add)
{
struct ext4_super_block *es = EXT4_SB(sb)->s_es;
handle_t *handle;
int err = 0, err2;
/* We will update the superblock, one block bitmap, and
* one group descriptor via ext4_group_add_blocks().
*/
handle = ext4_journal_start_sb(sb, 3);
if (IS_ERR(handle)) {
err = PTR_ERR(handle);
ext4_warning(sb, "error %d on journal start", err);
return err;
}
err = ext4_journal_get_write_access(handle, EXT4_SB(sb)->s_sbh);
if (err) {
ext4_warning(sb, "error %d on journal write access", err);
goto errout;
}
ext4_blocks_count_set(es, o_blocks_count + add);
ext4_free_blocks_count_set(es, ext4_free_blocks_count(es) + add);
ext4_debug("freeing blocks %llu through %llu\n", o_blocks_count,
o_blocks_count + add);
/* We add the blocks to the bitmap and set the group need init bit */
err = ext4_group_add_blocks(handle, sb, o_blocks_count, add);
if (err)
goto errout;
ext4_handle_dirty_super(handle, sb);
ext4_debug("freed blocks %llu through %llu\n", o_blocks_count,
o_blocks_count + add);
errout:
err2 = ext4_journal_stop(handle);
if (err2 && !err)
err = err2;
if (!err) {
if (test_opt(sb, DEBUG))
printk(KERN_DEBUG "EXT4-fs: extended group to %llu "
"blocks\n", ext4_blocks_count(es));
update_backups(sb, EXT4_SB(sb)->s_sbh->b_blocknr, (char *)es,
sizeof(struct ext4_super_block));
}
return err;
}
/*
* Extend the filesystem to the new number of blocks specified. This entry
* point is only used to extend the current filesystem to the end of the last
* existing group. It can be accessed via ioctl, or by "remount,resize=<size>"
* for emergencies (because it has no dependencies on reserved blocks).
*
* If we _really_ wanted, we could use default values to call ext4_group_add()
* allow the "remount" trick to work for arbitrary resizing, assuming enough
* GDT blocks are reserved to grow to the desired size.
*/
int ext4_group_extend(struct super_block *sb, struct ext4_super_block *es,
ext4_fsblk_t n_blocks_count)
{
ext4_fsblk_t o_blocks_count;
ext4_grpblk_t last;
ext4_grpblk_t add;
struct buffer_head *bh;
int err;
ext4_group_t group;
o_blocks_count = ext4_blocks_count(es);
if (test_opt(sb, DEBUG))
ext4_msg(sb, KERN_DEBUG,
"extending last group from %llu to %llu blocks",
o_blocks_count, n_blocks_count);
if (n_blocks_count == 0 || n_blocks_count == o_blocks_count)
return 0;
if (n_blocks_count > (sector_t)(~0ULL) >> (sb->s_blocksize_bits - 9)) {
ext4_msg(sb, KERN_ERR,
"filesystem too large to resize to %llu blocks safely",
n_blocks_count);
if (sizeof(sector_t) < 8)
ext4_warning(sb, "CONFIG_LBDAF not enabled");
return -EINVAL;
}
if (n_blocks_count < o_blocks_count) {
ext4_warning(sb, "can't shrink FS - resize aborted");
return -EINVAL;
}
/* Handle the remaining blocks in the last group only. */
ext4_get_group_no_and_offset(sb, o_blocks_count, &group, &last);
if (last == 0) {
ext4_warning(sb, "need to use ext2online to resize further");
return -EPERM;
}
add = EXT4_BLOCKS_PER_GROUP(sb) - last;
if (o_blocks_count + add < o_blocks_count) {
ext4_warning(sb, "blocks_count overflow");
return -EINVAL;
}
if (o_blocks_count + add > n_blocks_count)
add = n_blocks_count - o_blocks_count;
if (o_blocks_count + add < n_blocks_count)
ext4_warning(sb, "will only finish group (%llu blocks, %u new)",
o_blocks_count + add, add);
/* See if the device is actually as big as what was requested */
bh = sb_bread(sb, o_blocks_count + add - 1);
if (!bh) {
ext4_warning(sb, "can't read last block, resize aborted");
return -ENOSPC;
}
brelse(bh);
err = ext4_group_extend_no_check(sb, o_blocks_count, add);
return err;
} /* ext4_group_extend */
/*
* ext4_resize_fs() resizes a fs to new size specified by @n_blocks_count
*
* @sb: super block of the fs to be resized
* @n_blocks_count: the number of blocks resides in the resized fs
*/
int ext4_resize_fs(struct super_block *sb, ext4_fsblk_t n_blocks_count)
{
struct ext4_new_flex_group_data *flex_gd = NULL;
struct ext4_sb_info *sbi = EXT4_SB(sb);
struct ext4_super_block *es = sbi->s_es;
struct buffer_head *bh;
struct inode *resize_inode;
ext4_fsblk_t o_blocks_count;
ext4_group_t o_group;
ext4_group_t n_group;
ext4_grpblk_t offset, add;
unsigned long n_desc_blocks;
unsigned long o_desc_blocks;
unsigned long desc_blocks;
int err = 0, flexbg_size = 1;
o_blocks_count = ext4_blocks_count(es);
if (test_opt(sb, DEBUG))
ext4_msg(sb, KERN_DEBUG, "resizing filesystem from %llu "
"to %llu blocks", o_blocks_count, n_blocks_count);
if (n_blocks_count < o_blocks_count) {
/* On-line shrinking not supported */
ext4_warning(sb, "can't shrink FS - resize aborted");
return -EINVAL;
}
if (n_blocks_count == o_blocks_count)
/* Nothing need to do */
return 0;
ext4_get_group_no_and_offset(sb, n_blocks_count - 1, &n_group, &offset);
ext4_get_group_no_and_offset(sb, o_blocks_count - 1, &o_group, &offset);
n_desc_blocks = (n_group + EXT4_DESC_PER_BLOCK(sb)) /
EXT4_DESC_PER_BLOCK(sb);
o_desc_blocks = (sbi->s_groups_count + EXT4_DESC_PER_BLOCK(sb) - 1) /
EXT4_DESC_PER_BLOCK(sb);
desc_blocks = n_desc_blocks - o_desc_blocks;
if (desc_blocks &&
(!EXT4_HAS_COMPAT_FEATURE(sb, EXT4_FEATURE_COMPAT_RESIZE_INODE) ||
le16_to_cpu(es->s_reserved_gdt_blocks) < desc_blocks)) {
ext4_warning(sb, "No reserved GDT blocks, can't resize");
return -EPERM;
}
resize_inode = ext4_iget(sb, EXT4_RESIZE_INO);
if (IS_ERR(resize_inode)) {
ext4_warning(sb, "Error opening resize inode");
return PTR_ERR(resize_inode);
}
/* See if the device is actually as big as what was requested */
bh = sb_bread(sb, n_blocks_count - 1);
if (!bh) {
ext4_warning(sb, "can't read last block, resize aborted");
return -ENOSPC;
}
brelse(bh);
/* extend the last group */
if (n_group == o_group)
add = n_blocks_count - o_blocks_count;
else
add = EXT4_BLOCKS_PER_GROUP(sb) - (offset + 1);
if (add > 0) {
err = ext4_group_extend_no_check(sb, o_blocks_count, add);
if (err)
goto out;
}
if (EXT4_HAS_INCOMPAT_FEATURE(sb, EXT4_FEATURE_INCOMPAT_FLEX_BG) &&
es->s_log_groups_per_flex)
flexbg_size = 1 << es->s_log_groups_per_flex;
o_blocks_count = ext4_blocks_count(es);
if (o_blocks_count == n_blocks_count)
goto out;
flex_gd = alloc_flex_gd(flexbg_size);
if (flex_gd == NULL) {
err = -ENOMEM;
goto out;
}
/* Add flex groups. Note that a regular group is a
* flex group with 1 group.
*/
while (ext4_setup_next_flex_gd(sb, flex_gd, n_blocks_count,
flexbg_size)) {
ext4_alloc_group_tables(sb, flex_gd, flexbg_size);
err = ext4_flex_group_add(sb, resize_inode, flex_gd);
if (unlikely(err))
break;
}
out:
if (flex_gd)
free_flex_gd(flex_gd);
iput(resize_inode);
if (test_opt(sb, DEBUG))
ext4_msg(sb, KERN_DEBUG, "resized filesystem from %llu "
"upto %llu blocks", o_blocks_count, n_blocks_count);
return err;
}
| gpl-2.0 |
beaka/RK3188_tablet_kernel_sources | fs/fcntl.c | 3054 | 19167 | /*
* linux/fs/fcntl.c
*
* Copyright (C) 1991, 1992 Linus Torvalds
*/
#include <linux/syscalls.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/file.h>
#include <linux/fdtable.h>
#include <linux/capability.h>
#include <linux/dnotify.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pipe_fs_i.h>
#include <linux/security.h>
#include <linux/ptrace.h>
#include <linux/signal.h>
#include <linux/rcupdate.h>
#include <linux/pid_namespace.h>
#include <asm/poll.h>
#include <asm/siginfo.h>
#include <asm/uaccess.h>
void set_close_on_exec(unsigned int fd, int flag)
{
struct files_struct *files = current->files;
struct fdtable *fdt;
spin_lock(&files->file_lock);
fdt = files_fdtable(files);
if (flag)
FD_SET(fd, fdt->close_on_exec);
else
FD_CLR(fd, fdt->close_on_exec);
spin_unlock(&files->file_lock);
}
static int get_close_on_exec(unsigned int fd)
{
struct files_struct *files = current->files;
struct fdtable *fdt;
int res;
rcu_read_lock();
fdt = files_fdtable(files);
res = FD_ISSET(fd, fdt->close_on_exec);
rcu_read_unlock();
return res;
}
SYSCALL_DEFINE3(dup3, unsigned int, oldfd, unsigned int, newfd, int, flags)
{
int err = -EBADF;
struct file * file, *tofree;
struct files_struct * files = current->files;
struct fdtable *fdt;
if ((flags & ~O_CLOEXEC) != 0)
return -EINVAL;
if (unlikely(oldfd == newfd))
return -EINVAL;
spin_lock(&files->file_lock);
err = expand_files(files, newfd);
file = fcheck(oldfd);
if (unlikely(!file))
goto Ebadf;
if (unlikely(err < 0)) {
if (err == -EMFILE)
goto Ebadf;
goto out_unlock;
}
/*
* We need to detect attempts to do dup2() over allocated but still
* not finished descriptor. NB: OpenBSD avoids that at the price of
* extra work in their equivalent of fget() - they insert struct
* file immediately after grabbing descriptor, mark it larval if
* more work (e.g. actual opening) is needed and make sure that
* fget() treats larval files as absent. Potentially interesting,
* but while extra work in fget() is trivial, locking implications
* and amount of surgery on open()-related paths in VFS are not.
* FreeBSD fails with -EBADF in the same situation, NetBSD "solution"
* deadlocks in rather amusing ways, AFAICS. All of that is out of
* scope of POSIX or SUS, since neither considers shared descriptor
* tables and this condition does not arise without those.
*/
err = -EBUSY;
fdt = files_fdtable(files);
tofree = fdt->fd[newfd];
if (!tofree && FD_ISSET(newfd, fdt->open_fds))
goto out_unlock;
get_file(file);
rcu_assign_pointer(fdt->fd[newfd], file);
FD_SET(newfd, fdt->open_fds);
if (flags & O_CLOEXEC)
FD_SET(newfd, fdt->close_on_exec);
else
FD_CLR(newfd, fdt->close_on_exec);
spin_unlock(&files->file_lock);
if (tofree)
filp_close(tofree, files);
return newfd;
Ebadf:
err = -EBADF;
out_unlock:
spin_unlock(&files->file_lock);
return err;
}
SYSCALL_DEFINE2(dup2, unsigned int, oldfd, unsigned int, newfd)
{
if (unlikely(newfd == oldfd)) { /* corner case */
struct files_struct *files = current->files;
int retval = oldfd;
rcu_read_lock();
if (!fcheck_files(files, oldfd))
retval = -EBADF;
rcu_read_unlock();
return retval;
}
return sys_dup3(oldfd, newfd, 0);
}
SYSCALL_DEFINE1(dup, unsigned int, fildes)
{
int ret = -EBADF;
struct file *file = fget_raw(fildes);
if (file) {
ret = get_unused_fd();
if (ret >= 0)
fd_install(ret, file);
else
fput(file);
}
return ret;
}
#define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME)
static int setfl(int fd, struct file * filp, unsigned long arg)
{
struct inode * inode = filp->f_path.dentry->d_inode;
int error = 0;
/*
* O_APPEND cannot be cleared if the file is marked as append-only
* and the file is open for write.
*/
if (((arg ^ filp->f_flags) & O_APPEND) && IS_APPEND(inode))
return -EPERM;
/* O_NOATIME can only be set by the owner or superuser */
if ((arg & O_NOATIME) && !(filp->f_flags & O_NOATIME))
if (!inode_owner_or_capable(inode))
return -EPERM;
/* required for strict SunOS emulation */
if (O_NONBLOCK != O_NDELAY)
if (arg & O_NDELAY)
arg |= O_NONBLOCK;
if (arg & O_DIRECT) {
if (!filp->f_mapping || !filp->f_mapping->a_ops ||
!filp->f_mapping->a_ops->direct_IO)
return -EINVAL;
}
if (filp->f_op && filp->f_op->check_flags)
error = filp->f_op->check_flags(arg);
if (error)
return error;
/*
* ->fasync() is responsible for setting the FASYNC bit.
*/
if (((arg ^ filp->f_flags) & FASYNC) && filp->f_op &&
filp->f_op->fasync) {
error = filp->f_op->fasync(fd, filp, (arg & FASYNC) != 0);
if (error < 0)
goto out;
if (error > 0)
error = 0;
}
spin_lock(&filp->f_lock);
filp->f_flags = (arg & SETFL_MASK) | (filp->f_flags & ~SETFL_MASK);
spin_unlock(&filp->f_lock);
out:
return error;
}
static void f_modown(struct file *filp, struct pid *pid, enum pid_type type,
int force)
{
write_lock_irq(&filp->f_owner.lock);
if (force || !filp->f_owner.pid) {
put_pid(filp->f_owner.pid);
filp->f_owner.pid = get_pid(pid);
filp->f_owner.pid_type = type;
if (pid) {
const struct cred *cred = current_cred();
filp->f_owner.uid = cred->uid;
filp->f_owner.euid = cred->euid;
}
}
write_unlock_irq(&filp->f_owner.lock);
}
int __f_setown(struct file *filp, struct pid *pid, enum pid_type type,
int force)
{
int err;
err = security_file_set_fowner(filp);
if (err)
return err;
f_modown(filp, pid, type, force);
return 0;
}
EXPORT_SYMBOL(__f_setown);
int f_setown(struct file *filp, unsigned long arg, int force)
{
enum pid_type type;
struct pid *pid;
int who = arg;
int result;
type = PIDTYPE_PID;
if (who < 0) {
type = PIDTYPE_PGID;
who = -who;
}
rcu_read_lock();
pid = find_vpid(who);
result = __f_setown(filp, pid, type, force);
rcu_read_unlock();
return result;
}
EXPORT_SYMBOL(f_setown);
void f_delown(struct file *filp)
{
f_modown(filp, NULL, PIDTYPE_PID, 1);
}
pid_t f_getown(struct file *filp)
{
pid_t pid;
read_lock(&filp->f_owner.lock);
pid = pid_vnr(filp->f_owner.pid);
if (filp->f_owner.pid_type == PIDTYPE_PGID)
pid = -pid;
read_unlock(&filp->f_owner.lock);
return pid;
}
static int f_setown_ex(struct file *filp, unsigned long arg)
{
struct f_owner_ex * __user owner_p = (void * __user)arg;
struct f_owner_ex owner;
struct pid *pid;
int type;
int ret;
ret = copy_from_user(&owner, owner_p, sizeof(owner));
if (ret)
return -EFAULT;
switch (owner.type) {
case F_OWNER_TID:
type = PIDTYPE_MAX;
break;
case F_OWNER_PID:
type = PIDTYPE_PID;
break;
case F_OWNER_PGRP:
type = PIDTYPE_PGID;
break;
default:
return -EINVAL;
}
rcu_read_lock();
pid = find_vpid(owner.pid);
if (owner.pid && !pid)
ret = -ESRCH;
else
ret = __f_setown(filp, pid, type, 1);
rcu_read_unlock();
return ret;
}
static int f_getown_ex(struct file *filp, unsigned long arg)
{
struct f_owner_ex * __user owner_p = (void * __user)arg;
struct f_owner_ex owner;
int ret = 0;
read_lock(&filp->f_owner.lock);
owner.pid = pid_vnr(filp->f_owner.pid);
switch (filp->f_owner.pid_type) {
case PIDTYPE_MAX:
owner.type = F_OWNER_TID;
break;
case PIDTYPE_PID:
owner.type = F_OWNER_PID;
break;
case PIDTYPE_PGID:
owner.type = F_OWNER_PGRP;
break;
default:
WARN_ON(1);
ret = -EINVAL;
break;
}
read_unlock(&filp->f_owner.lock);
if (!ret) {
ret = copy_to_user(owner_p, &owner, sizeof(owner));
if (ret)
ret = -EFAULT;
}
return ret;
}
static long do_fcntl(int fd, unsigned int cmd, unsigned long arg,
struct file *filp)
{
long err = -EINVAL;
switch (cmd) {
case F_DUPFD:
case F_DUPFD_CLOEXEC:
if (arg >= rlimit(RLIMIT_NOFILE))
break;
err = alloc_fd(arg, cmd == F_DUPFD_CLOEXEC ? O_CLOEXEC : 0);
if (err >= 0) {
get_file(filp);
fd_install(err, filp);
}
break;
case F_GETFD:
err = get_close_on_exec(fd) ? FD_CLOEXEC : 0;
break;
case F_SETFD:
err = 0;
set_close_on_exec(fd, arg & FD_CLOEXEC);
break;
case F_GETFL:
err = filp->f_flags;
break;
case F_SETFL:
err = setfl(fd, filp, arg);
break;
case F_GETLK:
err = fcntl_getlk(filp, (struct flock __user *) arg);
break;
case F_SETLK:
case F_SETLKW:
err = fcntl_setlk(fd, filp, cmd, (struct flock __user *) arg);
break;
case F_GETOWN:
/*
* XXX If f_owner is a process group, the
* negative return value will get converted
* into an error. Oops. If we keep the
* current syscall conventions, the only way
* to fix this will be in libc.
*/
err = f_getown(filp);
force_successful_syscall_return();
break;
case F_SETOWN:
err = f_setown(filp, arg, 1);
break;
case F_GETOWN_EX:
err = f_getown_ex(filp, arg);
break;
case F_SETOWN_EX:
err = f_setown_ex(filp, arg);
break;
case F_GETSIG:
err = filp->f_owner.signum;
break;
case F_SETSIG:
/* arg == 0 restores default behaviour. */
if (!valid_signal(arg)) {
break;
}
err = 0;
filp->f_owner.signum = arg;
break;
case F_GETLEASE:
err = fcntl_getlease(filp);
break;
case F_SETLEASE:
err = fcntl_setlease(fd, filp, arg);
break;
case F_NOTIFY:
err = fcntl_dirnotify(fd, filp, arg);
break;
case F_SETPIPE_SZ:
case F_GETPIPE_SZ:
err = pipe_fcntl(filp, cmd, arg);
break;
default:
break;
}
return err;
}
static int check_fcntl_cmd(unsigned cmd)
{
switch (cmd) {
case F_DUPFD:
case F_DUPFD_CLOEXEC:
case F_GETFD:
case F_SETFD:
case F_GETFL:
return 1;
}
return 0;
}
SYSCALL_DEFINE3(fcntl, unsigned int, fd, unsigned int, cmd, unsigned long, arg)
{
struct file *filp;
long err = -EBADF;
filp = fget_raw(fd);
if (!filp)
goto out;
if (unlikely(filp->f_mode & FMODE_PATH)) {
if (!check_fcntl_cmd(cmd)) {
fput(filp);
goto out;
}
}
err = security_file_fcntl(filp, cmd, arg);
if (err) {
fput(filp);
return err;
}
err = do_fcntl(fd, cmd, arg, filp);
fput(filp);
out:
return err;
}
#if BITS_PER_LONG == 32
SYSCALL_DEFINE3(fcntl64, unsigned int, fd, unsigned int, cmd,
unsigned long, arg)
{
struct file * filp;
long err;
err = -EBADF;
filp = fget_raw(fd);
if (!filp)
goto out;
if (unlikely(filp->f_mode & FMODE_PATH)) {
if (!check_fcntl_cmd(cmd)) {
fput(filp);
goto out;
}
}
err = security_file_fcntl(filp, cmd, arg);
if (err) {
fput(filp);
return err;
}
err = -EBADF;
switch (cmd) {
case F_GETLK64:
err = fcntl_getlk64(filp, (struct flock64 __user *) arg);
break;
case F_SETLK64:
case F_SETLKW64:
err = fcntl_setlk64(fd, filp, cmd,
(struct flock64 __user *) arg);
break;
default:
err = do_fcntl(fd, cmd, arg, filp);
break;
}
fput(filp);
out:
return err;
}
#endif
/* Table to convert sigio signal codes into poll band bitmaps */
static const long band_table[NSIGPOLL] = {
POLLIN | POLLRDNORM, /* POLL_IN */
POLLOUT | POLLWRNORM | POLLWRBAND, /* POLL_OUT */
POLLIN | POLLRDNORM | POLLMSG, /* POLL_MSG */
POLLERR, /* POLL_ERR */
POLLPRI | POLLRDBAND, /* POLL_PRI */
POLLHUP | POLLERR /* POLL_HUP */
};
static inline int sigio_perm(struct task_struct *p,
struct fown_struct *fown, int sig)
{
const struct cred *cred;
int ret;
rcu_read_lock();
cred = __task_cred(p);
ret = ((fown->euid == 0 ||
fown->euid == cred->suid || fown->euid == cred->uid ||
fown->uid == cred->suid || fown->uid == cred->uid) &&
!security_file_send_sigiotask(p, fown, sig));
rcu_read_unlock();
return ret;
}
static void send_sigio_to_task(struct task_struct *p,
struct fown_struct *fown,
int fd, int reason, int group)
{
/*
* F_SETSIG can change ->signum lockless in parallel, make
* sure we read it once and use the same value throughout.
*/
int signum = ACCESS_ONCE(fown->signum);
if (!sigio_perm(p, fown, signum))
return;
switch (signum) {
siginfo_t si;
default:
/* Queue a rt signal with the appropriate fd as its
value. We use SI_SIGIO as the source, not
SI_KERNEL, since kernel signals always get
delivered even if we can't queue. Failure to
queue in this case _should_ be reported; we fall
back to SIGIO in that case. --sct */
si.si_signo = signum;
si.si_errno = 0;
si.si_code = reason;
/* Make sure we are called with one of the POLL_*
reasons, otherwise we could leak kernel stack into
userspace. */
BUG_ON((reason & __SI_MASK) != __SI_POLL);
if (reason - POLL_IN >= NSIGPOLL)
si.si_band = ~0L;
else
si.si_band = band_table[reason - POLL_IN];
si.si_fd = fd;
if (!do_send_sig_info(signum, &si, p, group))
break;
/* fall-through: fall back on the old plain SIGIO signal */
case 0:
do_send_sig_info(SIGIO, SEND_SIG_PRIV, p, group);
}
}
void send_sigio(struct fown_struct *fown, int fd, int band)
{
struct task_struct *p;
enum pid_type type;
struct pid *pid;
int group = 1;
read_lock(&fown->lock);
type = fown->pid_type;
if (type == PIDTYPE_MAX) {
group = 0;
type = PIDTYPE_PID;
}
pid = fown->pid;
if (!pid)
goto out_unlock_fown;
read_lock(&tasklist_lock);
do_each_pid_task(pid, type, p) {
send_sigio_to_task(p, fown, fd, band, group);
} while_each_pid_task(pid, type, p);
read_unlock(&tasklist_lock);
out_unlock_fown:
read_unlock(&fown->lock);
}
static void send_sigurg_to_task(struct task_struct *p,
struct fown_struct *fown, int group)
{
if (sigio_perm(p, fown, SIGURG))
do_send_sig_info(SIGURG, SEND_SIG_PRIV, p, group);
}
int send_sigurg(struct fown_struct *fown)
{
struct task_struct *p;
enum pid_type type;
struct pid *pid;
int group = 1;
int ret = 0;
read_lock(&fown->lock);
type = fown->pid_type;
if (type == PIDTYPE_MAX) {
group = 0;
type = PIDTYPE_PID;
}
pid = fown->pid;
if (!pid)
goto out_unlock_fown;
ret = 1;
read_lock(&tasklist_lock);
do_each_pid_task(pid, type, p) {
send_sigurg_to_task(p, fown, group);
} while_each_pid_task(pid, type, p);
read_unlock(&tasklist_lock);
out_unlock_fown:
read_unlock(&fown->lock);
return ret;
}
static DEFINE_SPINLOCK(fasync_lock);
static struct kmem_cache *fasync_cache __read_mostly;
static void fasync_free_rcu(struct rcu_head *head)
{
kmem_cache_free(fasync_cache,
container_of(head, struct fasync_struct, fa_rcu));
}
/*
* Remove a fasync entry. If successfully removed, return
* positive and clear the FASYNC flag. If no entry exists,
* do nothing and return 0.
*
* NOTE! It is very important that the FASYNC flag always
* match the state "is the filp on a fasync list".
*
*/
int fasync_remove_entry(struct file *filp, struct fasync_struct **fapp)
{
struct fasync_struct *fa, **fp;
int result = 0;
spin_lock(&filp->f_lock);
spin_lock(&fasync_lock);
for (fp = fapp; (fa = *fp) != NULL; fp = &fa->fa_next) {
if (fa->fa_file != filp)
continue;
spin_lock_irq(&fa->fa_lock);
fa->fa_file = NULL;
spin_unlock_irq(&fa->fa_lock);
*fp = fa->fa_next;
call_rcu(&fa->fa_rcu, fasync_free_rcu);
filp->f_flags &= ~FASYNC;
result = 1;
break;
}
spin_unlock(&fasync_lock);
spin_unlock(&filp->f_lock);
return result;
}
struct fasync_struct *fasync_alloc(void)
{
return kmem_cache_alloc(fasync_cache, GFP_KERNEL);
}
/*
* NOTE! This can be used only for unused fasync entries:
* entries that actually got inserted on the fasync list
* need to be released by rcu - see fasync_remove_entry.
*/
void fasync_free(struct fasync_struct *new)
{
kmem_cache_free(fasync_cache, new);
}
/*
* Insert a new entry into the fasync list. Return the pointer to the
* old one if we didn't use the new one.
*
* NOTE! It is very important that the FASYNC flag always
* match the state "is the filp on a fasync list".
*/
struct fasync_struct *fasync_insert_entry(int fd, struct file *filp, struct fasync_struct **fapp, struct fasync_struct *new)
{
struct fasync_struct *fa, **fp;
spin_lock(&filp->f_lock);
spin_lock(&fasync_lock);
for (fp = fapp; (fa = *fp) != NULL; fp = &fa->fa_next) {
if (fa->fa_file != filp)
continue;
spin_lock_irq(&fa->fa_lock);
fa->fa_fd = fd;
spin_unlock_irq(&fa->fa_lock);
goto out;
}
spin_lock_init(&new->fa_lock);
new->magic = FASYNC_MAGIC;
new->fa_file = filp;
new->fa_fd = fd;
new->fa_next = *fapp;
rcu_assign_pointer(*fapp, new);
filp->f_flags |= FASYNC;
out:
spin_unlock(&fasync_lock);
spin_unlock(&filp->f_lock);
return fa;
}
/*
* Add a fasync entry. Return negative on error, positive if
* added, and zero if did nothing but change an existing one.
*/
static int fasync_add_entry(int fd, struct file *filp, struct fasync_struct **fapp)
{
struct fasync_struct *new;
new = fasync_alloc();
if (!new)
return -ENOMEM;
/*
* fasync_insert_entry() returns the old (update) entry if
* it existed.
*
* So free the (unused) new entry and return 0 to let the
* caller know that we didn't add any new fasync entries.
*/
if (fasync_insert_entry(fd, filp, fapp, new)) {
fasync_free(new);
return 0;
}
return 1;
}
/*
* fasync_helper() is used by almost all character device drivers
* to set up the fasync queue, and for regular files by the file
* lease code. It returns negative on error, 0 if it did no changes
* and positive if it added/deleted the entry.
*/
int fasync_helper(int fd, struct file * filp, int on, struct fasync_struct **fapp)
{
if (!on)
return fasync_remove_entry(filp, fapp);
return fasync_add_entry(fd, filp, fapp);
}
EXPORT_SYMBOL(fasync_helper);
/*
* rcu_read_lock() is held
*/
static void kill_fasync_rcu(struct fasync_struct *fa, int sig, int band)
{
while (fa) {
struct fown_struct *fown;
unsigned long flags;
if (fa->magic != FASYNC_MAGIC) {
printk(KERN_ERR "kill_fasync: bad magic number in "
"fasync_struct!\n");
return;
}
spin_lock_irqsave(&fa->fa_lock, flags);
if (fa->fa_file) {
fown = &fa->fa_file->f_owner;
/* Don't send SIGURG to processes which have not set a
queued signum: SIGURG has its own default signalling
mechanism. */
if (!(sig == SIGURG && fown->signum == 0))
send_sigio(fown, fa->fa_fd, band);
}
spin_unlock_irqrestore(&fa->fa_lock, flags);
fa = rcu_dereference(fa->fa_next);
}
}
void kill_fasync(struct fasync_struct **fp, int sig, int band)
{
/* First a quick test without locking: usually
* the list is empty.
*/
if (*fp) {
rcu_read_lock();
kill_fasync_rcu(rcu_dereference(*fp), sig, band);
rcu_read_unlock();
}
}
EXPORT_SYMBOL(kill_fasync);
static int __init fcntl_init(void)
{
/*
* Please add new bits here to ensure allocation uniqueness.
* Exceptions: O_NONBLOCK is a two bit define on parisc; O_NDELAY
* is defined as O_NONBLOCK on some platforms and not on others.
*/
BUILD_BUG_ON(19 - 1 /* for O_RDONLY being 0 */ != HWEIGHT32(
O_RDONLY | O_WRONLY | O_RDWR |
O_CREAT | O_EXCL | O_NOCTTY |
O_TRUNC | O_APPEND | /* O_NONBLOCK | */
__O_SYNC | O_DSYNC | FASYNC |
O_DIRECT | O_LARGEFILE | O_DIRECTORY |
O_NOFOLLOW | O_NOATIME | O_CLOEXEC |
__FMODE_EXEC | O_PATH
));
fasync_cache = kmem_cache_create("fasync_cache",
sizeof(struct fasync_struct), 0, SLAB_PANIC, NULL);
return 0;
}
module_init(fcntl_init)
| gpl-2.0 |
Pivosgroup/buildroot-linux-kernel-m3 | arch/m68knommu/platform/5407/config.c | 4590 | 3287 | /***************************************************************************/
/*
* linux/arch/m68knommu/platform/5407/config.c
*
* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
* Copyright (C) 2000, Lineo (www.lineo.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
/***************************************************************************/
static struct mcf_platform_uart m5407_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.irq = 73,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.irq = 74,
},
{ },
};
static struct platform_device m5407_uart = {
.name = "mcfuart",
.id = 0,
.dev.platform_data = m5407_uart_platform,
};
static struct platform_device *m5407_devices[] __initdata = {
&m5407_uart,
};
/***************************************************************************/
static void __init m5407_uart_init_line(int line, int irq)
{
if (line == 0) {
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(irq, MCFINTC_UART0);
} else if (line == 1) {
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
mcf_mapirq2imr(irq, MCFINTC_UART1);
}
}
static void __init m5407_uarts_init(void)
{
const int nrlines = ARRAY_SIZE(m5407_uart_platform);
int line;
for (line = 0; (line < nrlines); line++)
m5407_uart_init_line(line, m5407_uart_platform[line].irq);
}
/***************************************************************************/
static void __init m5407_timers_init(void)
{
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif
}
/***************************************************************************/
void m5407_cpu_reset(void)
{
local_irq_disable();
/* set watchdog to soft reset, and enabled */
__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
for (;;)
/* wait for watchdog to timeout */;
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_reset = m5407_cpu_reset;
m5407_timers_init();
m5407_uarts_init();
/* Only support the external interrupts on their primary level */
mcf_mapirq2imr(25, MCFINTC_EINT1);
mcf_mapirq2imr(27, MCFINTC_EINT3);
mcf_mapirq2imr(29, MCFINTC_EINT5);
mcf_mapirq2imr(31, MCFINTC_EINT7);
}
/***************************************************************************/
static int __init init_BSP(void)
{
platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
return 0;
}
arch_initcall(init_BSP);
/***************************************************************************/
| gpl-2.0 |
AshleyLai/testing1 | sound/i2c/other/ak4xxx-adda.c | 6638 | 27244 | /*
* ALSA driver for AK4524 / AK4528 / AK4529 / AK4355 / AK4358 / AK4381
* AD and DA converters
*
* Copyright (c) 2000-2004 Jaroslav Kysela <perex@perex.cz>,
* Takashi Iwai <tiwai@suse.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/tlv.h>
#include <sound/ak4xxx-adda.h>
#include <sound/info.h>
MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.de>");
MODULE_DESCRIPTION("Routines for control of AK452x / AK43xx AD/DA converters");
MODULE_LICENSE("GPL");
/* write the given register and save the data to the cache */
void snd_akm4xxx_write(struct snd_akm4xxx *ak, int chip, unsigned char reg,
unsigned char val)
{
ak->ops.lock(ak, chip);
ak->ops.write(ak, chip, reg, val);
/* save the data */
snd_akm4xxx_set(ak, chip, reg, val);
ak->ops.unlock(ak, chip);
}
EXPORT_SYMBOL(snd_akm4xxx_write);
/* reset procedure for AK4524 and AK4528 */
static void ak4524_reset(struct snd_akm4xxx *ak, int state)
{
unsigned int chip;
unsigned char reg;
for (chip = 0; chip < ak->num_dacs/2; chip++) {
snd_akm4xxx_write(ak, chip, 0x01, state ? 0x00 : 0x03);
if (state)
continue;
/* DAC volumes */
for (reg = 0x04; reg < ak->total_regs; reg++)
snd_akm4xxx_write(ak, chip, reg,
snd_akm4xxx_get(ak, chip, reg));
}
}
/* reset procedure for AK4355 and AK4358 */
static void ak435X_reset(struct snd_akm4xxx *ak, int state)
{
unsigned char reg;
if (state) {
snd_akm4xxx_write(ak, 0, 0x01, 0x02); /* reset and soft-mute */
return;
}
for (reg = 0x00; reg < ak->total_regs; reg++)
if (reg != 0x01)
snd_akm4xxx_write(ak, 0, reg,
snd_akm4xxx_get(ak, 0, reg));
snd_akm4xxx_write(ak, 0, 0x01, 0x01); /* un-reset, unmute */
}
/* reset procedure for AK4381 */
static void ak4381_reset(struct snd_akm4xxx *ak, int state)
{
unsigned int chip;
unsigned char reg;
for (chip = 0; chip < ak->num_dacs/2; chip++) {
snd_akm4xxx_write(ak, chip, 0x00, state ? 0x0c : 0x0f);
if (state)
continue;
for (reg = 0x01; reg < ak->total_regs; reg++)
snd_akm4xxx_write(ak, chip, reg,
snd_akm4xxx_get(ak, chip, reg));
}
}
/*
* reset the AKM codecs
* @state: 1 = reset codec, 0 = restore the registers
*
* assert the reset operation and restores the register values to the chips.
*/
void snd_akm4xxx_reset(struct snd_akm4xxx *ak, int state)
{
switch (ak->type) {
case SND_AK4524:
case SND_AK4528:
case SND_AK4620:
ak4524_reset(ak, state);
break;
case SND_AK4529:
/* FIXME: needed for ak4529? */
break;
case SND_AK4355:
ak435X_reset(ak, state);
break;
case SND_AK4358:
ak435X_reset(ak, state);
break;
case SND_AK4381:
ak4381_reset(ak, state);
break;
default:
break;
}
}
EXPORT_SYMBOL(snd_akm4xxx_reset);
/*
* Volume conversion table for non-linear volumes
* from -63.5dB (mute) to 0dB step 0.5dB
*
* Used for AK4524/AK4620 input/ouput attenuation, AK4528, and
* AK5365 input attenuation
*/
static const unsigned char vol_cvt_datt[128] = {
0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04,
0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, 0x06,
0x06, 0x07, 0x07, 0x08, 0x08, 0x08, 0x09, 0x0a,
0x0a, 0x0b, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x0f,
0x10, 0x10, 0x11, 0x12, 0x12, 0x13, 0x13, 0x14,
0x15, 0x16, 0x17, 0x17, 0x18, 0x19, 0x1a, 0x1c,
0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x23,
0x24, 0x25, 0x26, 0x28, 0x29, 0x2a, 0x2b, 0x2d,
0x2e, 0x30, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
0x37, 0x38, 0x39, 0x3b, 0x3c, 0x3e, 0x3f, 0x40,
0x41, 0x42, 0x43, 0x44, 0x46, 0x47, 0x48, 0x4a,
0x4b, 0x4d, 0x4e, 0x50, 0x51, 0x52, 0x53, 0x54,
0x55, 0x56, 0x58, 0x59, 0x5b, 0x5c, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x64, 0x65, 0x66, 0x67, 0x69,
0x6a, 0x6c, 0x6d, 0x6f, 0x70, 0x71, 0x72, 0x73,
0x75, 0x76, 0x77, 0x79, 0x7a, 0x7c, 0x7d, 0x7f,
};
/*
* dB tables
*/
static const DECLARE_TLV_DB_SCALE(db_scale_vol_datt, -6350, 50, 1);
static const DECLARE_TLV_DB_SCALE(db_scale_8bit, -12750, 50, 1);
static const DECLARE_TLV_DB_SCALE(db_scale_7bit, -6350, 50, 1);
static const DECLARE_TLV_DB_LINEAR(db_scale_linear, TLV_DB_GAIN_MUTE, 0);
/*
* initialize all the ak4xxx chips
*/
void snd_akm4xxx_init(struct snd_akm4xxx *ak)
{
static const unsigned char inits_ak4524[] = {
0x00, 0x07, /* 0: all power up */
0x01, 0x00, /* 1: ADC/DAC reset */
0x02, 0x60, /* 2: 24bit I2S */
0x03, 0x19, /* 3: deemphasis off */
0x01, 0x03, /* 1: ADC/DAC enable */
0x04, 0x00, /* 4: ADC left muted */
0x05, 0x00, /* 5: ADC right muted */
0x06, 0x00, /* 6: DAC left muted */
0x07, 0x00, /* 7: DAC right muted */
0xff, 0xff
};
static const unsigned char inits_ak4528[] = {
0x00, 0x07, /* 0: all power up */
0x01, 0x00, /* 1: ADC/DAC reset */
0x02, 0x60, /* 2: 24bit I2S */
0x03, 0x0d, /* 3: deemphasis off, turn LR highpass filters on */
0x01, 0x03, /* 1: ADC/DAC enable */
0x04, 0x00, /* 4: ADC left muted */
0x05, 0x00, /* 5: ADC right muted */
0xff, 0xff
};
static const unsigned char inits_ak4529[] = {
0x09, 0x01, /* 9: ATS=0, RSTN=1 */
0x0a, 0x3f, /* A: all power up, no zero/overflow detection */
0x00, 0x0c, /* 0: TDM=0, 24bit I2S, SMUTE=0 */
0x01, 0x00, /* 1: ACKS=0, ADC, loop off */
0x02, 0xff, /* 2: LOUT1 muted */
0x03, 0xff, /* 3: ROUT1 muted */
0x04, 0xff, /* 4: LOUT2 muted */
0x05, 0xff, /* 5: ROUT2 muted */
0x06, 0xff, /* 6: LOUT3 muted */
0x07, 0xff, /* 7: ROUT3 muted */
0x0b, 0xff, /* B: LOUT4 muted */
0x0c, 0xff, /* C: ROUT4 muted */
0x08, 0x55, /* 8: deemphasis all off */
0xff, 0xff
};
static const unsigned char inits_ak4355[] = {
0x01, 0x02, /* 1: reset and soft-mute */
0x00, 0x06, /* 0: mode3(i2s), disable auto-clock detect,
* disable DZF, sharp roll-off, RSTN#=0 */
0x02, 0x0e, /* 2: DA's power up, normal speed, RSTN#=0 */
// 0x02, 0x2e, /* quad speed */
0x03, 0x01, /* 3: de-emphasis off */
0x04, 0x00, /* 4: LOUT1 volume muted */
0x05, 0x00, /* 5: ROUT1 volume muted */
0x06, 0x00, /* 6: LOUT2 volume muted */
0x07, 0x00, /* 7: ROUT2 volume muted */
0x08, 0x00, /* 8: LOUT3 volume muted */
0x09, 0x00, /* 9: ROUT3 volume muted */
0x0a, 0x00, /* a: DATT speed=0, ignore DZF */
0x01, 0x01, /* 1: un-reset, unmute */
0xff, 0xff
};
static const unsigned char inits_ak4358[] = {
0x01, 0x02, /* 1: reset and soft-mute */
0x00, 0x06, /* 0: mode3(i2s), disable auto-clock detect,
* disable DZF, sharp roll-off, RSTN#=0 */
0x02, 0x4e, /* 2: DA's power up, normal speed, RSTN#=0 */
/* 0x02, 0x6e,*/ /* quad speed */
0x03, 0x01, /* 3: de-emphasis off */
0x04, 0x00, /* 4: LOUT1 volume muted */
0x05, 0x00, /* 5: ROUT1 volume muted */
0x06, 0x00, /* 6: LOUT2 volume muted */
0x07, 0x00, /* 7: ROUT2 volume muted */
0x08, 0x00, /* 8: LOUT3 volume muted */
0x09, 0x00, /* 9: ROUT3 volume muted */
0x0b, 0x00, /* b: LOUT4 volume muted */
0x0c, 0x00, /* c: ROUT4 volume muted */
0x0a, 0x00, /* a: DATT speed=0, ignore DZF */
0x01, 0x01, /* 1: un-reset, unmute */
0xff, 0xff
};
static const unsigned char inits_ak4381[] = {
0x00, 0x0c, /* 0: mode3(i2s), disable auto-clock detect */
0x01, 0x02, /* 1: de-emphasis off, normal speed,
* sharp roll-off, DZF off */
// 0x01, 0x12, /* quad speed */
0x02, 0x00, /* 2: DZF disabled */
0x03, 0x00, /* 3: LATT 0 */
0x04, 0x00, /* 4: RATT 0 */
0x00, 0x0f, /* 0: power-up, un-reset */
0xff, 0xff
};
static const unsigned char inits_ak4620[] = {
0x00, 0x07, /* 0: normal */
0x01, 0x00, /* 0: reset */
0x01, 0x02, /* 1: RSTAD */
0x01, 0x03, /* 1: RSTDA */
0x01, 0x0f, /* 1: normal */
0x02, 0x60, /* 2: 24bit I2S */
0x03, 0x01, /* 3: deemphasis off */
0x04, 0x00, /* 4: LIN muted */
0x05, 0x00, /* 5: RIN muted */
0x06, 0x00, /* 6: LOUT muted */
0x07, 0x00, /* 7: ROUT muted */
0xff, 0xff
};
int chip;
const unsigned char *ptr, *inits;
unsigned char reg, data;
memset(ak->images, 0, sizeof(ak->images));
memset(ak->volumes, 0, sizeof(ak->volumes));
switch (ak->type) {
case SND_AK4524:
inits = inits_ak4524;
ak->num_chips = ak->num_dacs / 2;
ak->name = "ak4524";
ak->total_regs = 0x08;
break;
case SND_AK4528:
inits = inits_ak4528;
ak->num_chips = ak->num_dacs / 2;
ak->name = "ak4528";
ak->total_regs = 0x06;
break;
case SND_AK4529:
inits = inits_ak4529;
ak->num_chips = 1;
ak->name = "ak4529";
ak->total_regs = 0x0d;
break;
case SND_AK4355:
inits = inits_ak4355;
ak->num_chips = 1;
ak->name = "ak4355";
ak->total_regs = 0x0b;
break;
case SND_AK4358:
inits = inits_ak4358;
ak->num_chips = 1;
ak->name = "ak4358";
ak->total_regs = 0x10;
break;
case SND_AK4381:
inits = inits_ak4381;
ak->num_chips = ak->num_dacs / 2;
ak->name = "ak4381";
ak->total_regs = 0x05;
break;
case SND_AK5365:
/* FIXME: any init sequence? */
ak->num_chips = 1;
ak->name = "ak5365";
ak->total_regs = 0x08;
return;
case SND_AK4620:
inits = inits_ak4620;
ak->num_chips = ak->num_dacs / 2;
ak->name = "ak4620";
ak->total_regs = 0x08;
break;
default:
snd_BUG();
return;
}
for (chip = 0; chip < ak->num_chips; chip++) {
ptr = inits;
while (*ptr != 0xff) {
reg = *ptr++;
data = *ptr++;
snd_akm4xxx_write(ak, chip, reg, data);
udelay(10);
}
}
}
EXPORT_SYMBOL(snd_akm4xxx_init);
/*
* Mixer callbacks
*/
#define AK_IPGA (1<<20) /* including IPGA */
#define AK_VOL_CVT (1<<21) /* need dB conversion */
#define AK_NEEDSMSB (1<<22) /* need MSB update bit */
#define AK_INVERT (1<<23) /* data is inverted */
#define AK_GET_CHIP(val) (((val) >> 8) & 0xff)
#define AK_GET_ADDR(val) ((val) & 0xff)
#define AK_GET_SHIFT(val) (((val) >> 16) & 0x0f)
#define AK_GET_VOL_CVT(val) (((val) >> 21) & 1)
#define AK_GET_IPGA(val) (((val) >> 20) & 1)
#define AK_GET_NEEDSMSB(val) (((val) >> 22) & 1)
#define AK_GET_INVERT(val) (((val) >> 23) & 1)
#define AK_GET_MASK(val) (((val) >> 24) & 0xff)
#define AK_COMPOSE(chip,addr,shift,mask) \
(((chip) << 8) | (addr) | ((shift) << 16) | ((mask) << 24))
static int snd_akm4xxx_volume_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
unsigned int mask = AK_GET_MASK(kcontrol->private_value);
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = mask;
return 0;
}
static int snd_akm4xxx_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
ucontrol->value.integer.value[0] = snd_akm4xxx_get_vol(ak, chip, addr);
return 0;
}
static int put_ak_reg(struct snd_kcontrol *kcontrol, int addr,
unsigned char nval)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
unsigned int mask = AK_GET_MASK(kcontrol->private_value);
int chip = AK_GET_CHIP(kcontrol->private_value);
if (snd_akm4xxx_get_vol(ak, chip, addr) == nval)
return 0;
snd_akm4xxx_set_vol(ak, chip, addr, nval);
if (AK_GET_VOL_CVT(kcontrol->private_value) && nval < 128)
nval = vol_cvt_datt[nval];
if (AK_GET_IPGA(kcontrol->private_value) && nval >= 128)
nval++; /* need to correct + 1 since both 127 and 128 are 0dB */
if (AK_GET_INVERT(kcontrol->private_value))
nval = mask - nval;
if (AK_GET_NEEDSMSB(kcontrol->private_value))
nval |= 0x80;
/* printk(KERN_DEBUG "DEBUG - AK writing reg: chip %x addr %x,
nval %x\n", chip, addr, nval); */
snd_akm4xxx_write(ak, chip, addr, nval);
return 1;
}
static int snd_akm4xxx_volume_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
unsigned int mask = AK_GET_MASK(kcontrol->private_value);
unsigned int val = ucontrol->value.integer.value[0];
if (val > mask)
return -EINVAL;
return put_ak_reg(kcontrol, AK_GET_ADDR(kcontrol->private_value), val);
}
static int snd_akm4xxx_stereo_volume_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
unsigned int mask = AK_GET_MASK(kcontrol->private_value);
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = mask;
return 0;
}
static int snd_akm4xxx_stereo_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
ucontrol->value.integer.value[0] = snd_akm4xxx_get_vol(ak, chip, addr);
ucontrol->value.integer.value[1] = snd_akm4xxx_get_vol(ak, chip, addr+1);
return 0;
}
static int snd_akm4xxx_stereo_volume_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
int addr = AK_GET_ADDR(kcontrol->private_value);
unsigned int mask = AK_GET_MASK(kcontrol->private_value);
unsigned int val[2];
int change;
val[0] = ucontrol->value.integer.value[0];
val[1] = ucontrol->value.integer.value[1];
if (val[0] > mask || val[1] > mask)
return -EINVAL;
change = put_ak_reg(kcontrol, addr, val[0]);
change |= put_ak_reg(kcontrol, addr + 1, val[1]);
return change;
}
static int snd_akm4xxx_deemphasis_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
static char *texts[4] = {
"44.1kHz", "Off", "48kHz", "32kHz",
};
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = 4;
if (uinfo->value.enumerated.item >= 4)
uinfo->value.enumerated.item = 3;
strcpy(uinfo->value.enumerated.name,
texts[uinfo->value.enumerated.item]);
return 0;
}
static int snd_akm4xxx_deemphasis_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
int shift = AK_GET_SHIFT(kcontrol->private_value);
ucontrol->value.enumerated.item[0] =
(snd_akm4xxx_get(ak, chip, addr) >> shift) & 3;
return 0;
}
static int snd_akm4xxx_deemphasis_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
int shift = AK_GET_SHIFT(kcontrol->private_value);
unsigned char nval = ucontrol->value.enumerated.item[0] & 3;
int change;
nval = (nval << shift) |
(snd_akm4xxx_get(ak, chip, addr) & ~(3 << shift));
change = snd_akm4xxx_get(ak, chip, addr) != nval;
if (change)
snd_akm4xxx_write(ak, chip, addr, nval);
return change;
}
#define ak4xxx_switch_info snd_ctl_boolean_mono_info
static int ak4xxx_switch_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
int shift = AK_GET_SHIFT(kcontrol->private_value);
int invert = AK_GET_INVERT(kcontrol->private_value);
/* we observe the (1<<shift) bit only */
unsigned char val = snd_akm4xxx_get(ak, chip, addr) & (1<<shift);
if (invert)
val = ! val;
ucontrol->value.integer.value[0] = (val & (1<<shift)) != 0;
return 0;
}
static int ak4xxx_switch_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
int shift = AK_GET_SHIFT(kcontrol->private_value);
int invert = AK_GET_INVERT(kcontrol->private_value);
long flag = ucontrol->value.integer.value[0];
unsigned char val, oval;
int change;
if (invert)
flag = ! flag;
oval = snd_akm4xxx_get(ak, chip, addr);
if (flag)
val = oval | (1<<shift);
else
val = oval & ~(1<<shift);
change = (oval != val);
if (change)
snd_akm4xxx_write(ak, chip, addr, val);
return change;
}
#define AK5365_NUM_INPUTS 5
static int ak4xxx_capture_num_inputs(struct snd_akm4xxx *ak, int mixer_ch)
{
int num_names;
const char **input_names;
input_names = ak->adc_info[mixer_ch].input_names;
num_names = 0;
while (num_names < AK5365_NUM_INPUTS && input_names[num_names])
++num_names;
return num_names;
}
static int ak4xxx_capture_source_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int mixer_ch = AK_GET_SHIFT(kcontrol->private_value);
const char **input_names;
int num_names, idx;
num_names = ak4xxx_capture_num_inputs(ak, mixer_ch);
if (!num_names)
return -EINVAL;
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
uinfo->value.enumerated.items = num_names;
idx = uinfo->value.enumerated.item;
if (idx >= num_names)
return -EINVAL;
input_names = ak->adc_info[mixer_ch].input_names;
strncpy(uinfo->value.enumerated.name, input_names[idx],
sizeof(uinfo->value.enumerated.name));
return 0;
}
static int ak4xxx_capture_source_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
int mask = AK_GET_MASK(kcontrol->private_value);
unsigned char val;
val = snd_akm4xxx_get(ak, chip, addr) & mask;
ucontrol->value.enumerated.item[0] = val;
return 0;
}
static int ak4xxx_capture_source_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_akm4xxx *ak = snd_kcontrol_chip(kcontrol);
int mixer_ch = AK_GET_SHIFT(kcontrol->private_value);
int chip = AK_GET_CHIP(kcontrol->private_value);
int addr = AK_GET_ADDR(kcontrol->private_value);
int mask = AK_GET_MASK(kcontrol->private_value);
unsigned char oval, val;
int num_names = ak4xxx_capture_num_inputs(ak, mixer_ch);
if (ucontrol->value.enumerated.item[0] >= num_names)
return -EINVAL;
oval = snd_akm4xxx_get(ak, chip, addr);
val = oval & ~mask;
val |= ucontrol->value.enumerated.item[0] & mask;
if (val != oval) {
snd_akm4xxx_write(ak, chip, addr, val);
return 1;
}
return 0;
}
/*
* build AK4xxx controls
*/
static int build_dac_controls(struct snd_akm4xxx *ak)
{
int idx, err, mixer_ch, num_stereo;
struct snd_kcontrol_new knew;
mixer_ch = 0;
for (idx = 0; idx < ak->num_dacs; ) {
/* mute control for Revolution 7.1 - AK4381 */
if (ak->type == SND_AK4381
&& ak->dac_info[mixer_ch].switch_name) {
memset(&knew, 0, sizeof(knew));
knew.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
knew.count = 1;
knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
knew.name = ak->dac_info[mixer_ch].switch_name;
knew.info = ak4xxx_switch_info;
knew.get = ak4xxx_switch_get;
knew.put = ak4xxx_switch_put;
knew.access = 0;
/* register 1, bit 0 (SMUTE): 0 = normal operation,
1 = mute */
knew.private_value =
AK_COMPOSE(idx/2, 1, 0, 0) | AK_INVERT;
err = snd_ctl_add(ak->card, snd_ctl_new1(&knew, ak));
if (err < 0)
return err;
}
memset(&knew, 0, sizeof(knew));
if (! ak->dac_info || ! ak->dac_info[mixer_ch].name) {
knew.name = "DAC Volume";
knew.index = mixer_ch + ak->idx_offset * 2;
num_stereo = 1;
} else {
knew.name = ak->dac_info[mixer_ch].name;
num_stereo = ak->dac_info[mixer_ch].num_channels;
}
knew.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
knew.count = 1;
knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
SNDRV_CTL_ELEM_ACCESS_TLV_READ;
if (num_stereo == 2) {
knew.info = snd_akm4xxx_stereo_volume_info;
knew.get = snd_akm4xxx_stereo_volume_get;
knew.put = snd_akm4xxx_stereo_volume_put;
} else {
knew.info = snd_akm4xxx_volume_info;
knew.get = snd_akm4xxx_volume_get;
knew.put = snd_akm4xxx_volume_put;
}
switch (ak->type) {
case SND_AK4524:
/* register 6 & 7 */
knew.private_value =
AK_COMPOSE(idx/2, (idx%2) + 6, 0, 127) |
AK_VOL_CVT;
knew.tlv.p = db_scale_vol_datt;
break;
case SND_AK4528:
/* register 4 & 5 */
knew.private_value =
AK_COMPOSE(idx/2, (idx%2) + 4, 0, 127) |
AK_VOL_CVT;
knew.tlv.p = db_scale_vol_datt;
break;
case SND_AK4529: {
/* registers 2-7 and b,c */
int val = idx < 6 ? idx + 2 : (idx - 6) + 0xb;
knew.private_value =
AK_COMPOSE(0, val, 0, 255) | AK_INVERT;
knew.tlv.p = db_scale_8bit;
break;
}
case SND_AK4355:
/* register 4-9, chip #0 only */
knew.private_value = AK_COMPOSE(0, idx + 4, 0, 255);
knew.tlv.p = db_scale_8bit;
break;
case SND_AK4358: {
/* register 4-9 and 11-12, chip #0 only */
int addr = idx < 6 ? idx + 4 : idx + 5;
knew.private_value =
AK_COMPOSE(0, addr, 0, 127) | AK_NEEDSMSB;
knew.tlv.p = db_scale_7bit;
break;
}
case SND_AK4381:
/* register 3 & 4 */
knew.private_value =
AK_COMPOSE(idx/2, (idx%2) + 3, 0, 255);
knew.tlv.p = db_scale_linear;
break;
case SND_AK4620:
/* register 6 & 7 */
knew.private_value =
AK_COMPOSE(idx/2, (idx%2) + 6, 0, 255);
knew.tlv.p = db_scale_linear;
break;
default:
return -EINVAL;
}
err = snd_ctl_add(ak->card, snd_ctl_new1(&knew, ak));
if (err < 0)
return err;
idx += num_stereo;
mixer_ch++;
}
return 0;
}
static int build_adc_controls(struct snd_akm4xxx *ak)
{
int idx, err, mixer_ch, num_stereo, max_steps;
struct snd_kcontrol_new knew;
mixer_ch = 0;
if (ak->type == SND_AK4528)
return 0; /* no controls */
for (idx = 0; idx < ak->num_adcs;) {
memset(&knew, 0, sizeof(knew));
if (! ak->adc_info || ! ak->adc_info[mixer_ch].name) {
knew.name = "ADC Volume";
knew.index = mixer_ch + ak->idx_offset * 2;
num_stereo = 1;
} else {
knew.name = ak->adc_info[mixer_ch].name;
num_stereo = ak->adc_info[mixer_ch].num_channels;
}
knew.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
knew.count = 1;
knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
SNDRV_CTL_ELEM_ACCESS_TLV_READ;
if (num_stereo == 2) {
knew.info = snd_akm4xxx_stereo_volume_info;
knew.get = snd_akm4xxx_stereo_volume_get;
knew.put = snd_akm4xxx_stereo_volume_put;
} else {
knew.info = snd_akm4xxx_volume_info;
knew.get = snd_akm4xxx_volume_get;
knew.put = snd_akm4xxx_volume_put;
}
/* register 4 & 5 */
if (ak->type == SND_AK5365)
max_steps = 152;
else
max_steps = 164;
knew.private_value =
AK_COMPOSE(idx/2, (idx%2) + 4, 0, max_steps) |
AK_VOL_CVT | AK_IPGA;
knew.tlv.p = db_scale_vol_datt;
err = snd_ctl_add(ak->card, snd_ctl_new1(&knew, ak));
if (err < 0)
return err;
if (ak->type == SND_AK5365 && (idx % 2) == 0) {
if (! ak->adc_info ||
! ak->adc_info[mixer_ch].switch_name) {
knew.name = "Capture Switch";
knew.index = mixer_ch + ak->idx_offset * 2;
} else
knew.name = ak->adc_info[mixer_ch].switch_name;
knew.info = ak4xxx_switch_info;
knew.get = ak4xxx_switch_get;
knew.put = ak4xxx_switch_put;
knew.access = 0;
/* register 2, bit 0 (SMUTE): 0 = normal operation,
1 = mute */
knew.private_value =
AK_COMPOSE(idx/2, 2, 0, 0) | AK_INVERT;
err = snd_ctl_add(ak->card, snd_ctl_new1(&knew, ak));
if (err < 0)
return err;
memset(&knew, 0, sizeof(knew));
knew.name = ak->adc_info[mixer_ch].selector_name;
if (!knew.name) {
knew.name = "Capture Channel";
knew.index = mixer_ch + ak->idx_offset * 2;
}
knew.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
knew.info = ak4xxx_capture_source_info;
knew.get = ak4xxx_capture_source_get;
knew.put = ak4xxx_capture_source_put;
knew.access = 0;
/* input selector control: reg. 1, bits 0-2.
* mis-use 'shift' to pass mixer_ch */
knew.private_value
= AK_COMPOSE(idx/2, 1, mixer_ch, 0x07);
err = snd_ctl_add(ak->card, snd_ctl_new1(&knew, ak));
if (err < 0)
return err;
}
idx += num_stereo;
mixer_ch++;
}
return 0;
}
static int build_deemphasis(struct snd_akm4xxx *ak, int num_emphs)
{
int idx, err;
struct snd_kcontrol_new knew;
for (idx = 0; idx < num_emphs; idx++) {
memset(&knew, 0, sizeof(knew));
knew.name = "Deemphasis";
knew.index = idx + ak->idx_offset;
knew.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
knew.count = 1;
knew.info = snd_akm4xxx_deemphasis_info;
knew.get = snd_akm4xxx_deemphasis_get;
knew.put = snd_akm4xxx_deemphasis_put;
switch (ak->type) {
case SND_AK4524:
case SND_AK4528:
case SND_AK4620:
/* register 3 */
knew.private_value = AK_COMPOSE(idx, 3, 0, 0);
break;
case SND_AK4529: {
int shift = idx == 3 ? 6 : (2 - idx) * 2;
/* register 8 with shift */
knew.private_value = AK_COMPOSE(0, 8, shift, 0);
break;
}
case SND_AK4355:
case SND_AK4358:
knew.private_value = AK_COMPOSE(idx, 3, 0, 0);
break;
case SND_AK4381:
knew.private_value = AK_COMPOSE(idx, 1, 1, 0);
break;
default:
return -EINVAL;
}
err = snd_ctl_add(ak->card, snd_ctl_new1(&knew, ak));
if (err < 0)
return err;
}
return 0;
}
#ifdef CONFIG_PROC_FS
static void proc_regs_read(struct snd_info_entry *entry,
struct snd_info_buffer *buffer)
{
struct snd_akm4xxx *ak = entry->private_data;
int reg, val, chip;
for (chip = 0; chip < ak->num_chips; chip++) {
for (reg = 0; reg < ak->total_regs; reg++) {
val = snd_akm4xxx_get(ak, chip, reg);
snd_iprintf(buffer, "chip %d: 0x%02x = 0x%02x\n", chip,
reg, val);
}
}
}
static int proc_init(struct snd_akm4xxx *ak)
{
struct snd_info_entry *entry;
int err;
err = snd_card_proc_new(ak->card, ak->name, &entry);
if (err < 0)
return err;
snd_info_set_text_ops(entry, ak, proc_regs_read);
return 0;
}
#else /* !CONFIG_PROC_FS */
static int proc_init(struct snd_akm4xxx *ak) { return 0; }
#endif
int snd_akm4xxx_build_controls(struct snd_akm4xxx *ak)
{
int err, num_emphs;
err = build_dac_controls(ak);
if (err < 0)
return err;
err = build_adc_controls(ak);
if (err < 0)
return err;
if (ak->type == SND_AK4355 || ak->type == SND_AK4358)
num_emphs = 1;
else if (ak->type == SND_AK4620)
num_emphs = 0;
else
num_emphs = ak->num_dacs / 2;
err = build_deemphasis(ak, num_emphs);
if (err < 0)
return err;
err = proc_init(ak);
if (err < 0)
return err;
return 0;
}
EXPORT_SYMBOL(snd_akm4xxx_build_controls);
static int __init alsa_akm4xxx_module_init(void)
{
return 0;
}
static void __exit alsa_akm4xxx_module_exit(void)
{
}
module_init(alsa_akm4xxx_module_init)
module_exit(alsa_akm4xxx_module_exit)
| gpl-2.0 |
shaowei-wang/linux-3.4-hummingbird | arch/mips/loongson/common/irq.c | 7918 | 1577 | /*
* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
* Author: Fuxin Zhang, zhangfx@lemote.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <loongson.h>
/*
* the first level int-handler will jump here if it is a bonito irq
*/
void bonito_irqdispatch(void)
{
u32 int_status;
int i;
/* workaround the IO dma problem: let cpu looping to allow DMA finish */
int_status = LOONGSON_INTISR;
while (int_status & (1 << 10)) {
udelay(1);
int_status = LOONGSON_INTISR;
}
/* Get pending sources, masked by current enables */
int_status = LOONGSON_INTISR & LOONGSON_INTEN;
if (int_status) {
i = __ffs(int_status);
do_IRQ(LOONGSON_IRQ_BASE + i);
}
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending;
pending = read_c0_cause() & read_c0_status() & ST0_IM;
/* machine-specific plat_irq_dispatch */
mach_irq_dispatch(pending);
}
void __init arch_init_irq(void)
{
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM | ST0_BEV);
/* no steer */
LOONGSON_INTSTEER = 0;
/*
* Mask out all interrupt by writing "1" to all bit position in
* the interrupt reset reg.
*/
LOONGSON_INTENCLR = ~0;
/* machine specific irq init */
mach_init_irq();
}
| gpl-2.0 |
iBluemind/android_kernel_lge_su760 | drivers/i2c/busses/i2c-elektor.c | 8174 | 8995 | /* ------------------------------------------------------------------------- */
/* i2c-elektor.c i2c-hw access for PCF8584 style isa bus adaptes */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 1995-97 Simon G. Vogl
1998-99 Hans Berglund
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* ------------------------------------------------------------------------- */
/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
Frodo Looijaard <frodol@dds.nl> */
/* Partially rewriten by Oleg I. Vdovikin for mmapped support of
for Alpha Processor Inc. UP-2000(+) boards */
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/wait.h>
#include <linux/isa.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-pcf.h>
#include <linux/io.h>
#include <asm/irq.h>
#include "../algos/i2c-algo-pcf.h"
#define DEFAULT_BASE 0x330
static int base;
static u8 __iomem *base_iomem;
static int irq;
static int clock = 0x1c;
static int own = 0x55;
static int mmapped;
/* vdovikin: removed static struct i2c_pcf_isa gpi; code -
this module in real supports only one device, due to missing arguments
in some functions, called from the algo-pcf module. Sometimes it's
need to be rewriten - but for now just remove this for simpler reading */
static wait_queue_head_t pcf_wait;
static int pcf_pending;
static spinlock_t lock;
static struct i2c_adapter pcf_isa_ops;
/* ----- local functions ---------------------------------------------- */
static void pcf_isa_setbyte(void *data, int ctl, int val)
{
u8 __iomem *address = ctl ? (base_iomem + 1) : base_iomem;
/* enable irq if any specified for serial operation */
if (ctl && irq && (val & I2C_PCF_ESO)) {
val |= I2C_PCF_ENI;
}
pr_debug("%s: Write %p 0x%02X\n", pcf_isa_ops.name, address, val);
iowrite8(val, address);
#ifdef __alpha__
/* API UP2000 needs some hardware fudging to make the write stick */
iowrite8(val, address);
#endif
}
static int pcf_isa_getbyte(void *data, int ctl)
{
u8 __iomem *address = ctl ? (base_iomem + 1) : base_iomem;
int val = ioread8(address);
pr_debug("%s: Read %p 0x%02X\n", pcf_isa_ops.name, address, val);
return (val);
}
static int pcf_isa_getown(void *data)
{
return (own);
}
static int pcf_isa_getclock(void *data)
{
return (clock);
}
static void pcf_isa_waitforpin(void *data)
{
DEFINE_WAIT(wait);
int timeout = 2;
unsigned long flags;
if (irq > 0) {
spin_lock_irqsave(&lock, flags);
if (pcf_pending == 0) {
spin_unlock_irqrestore(&lock, flags);
prepare_to_wait(&pcf_wait, &wait, TASK_INTERRUPTIBLE);
if (schedule_timeout(timeout*HZ)) {
spin_lock_irqsave(&lock, flags);
if (pcf_pending == 1) {
pcf_pending = 0;
}
spin_unlock_irqrestore(&lock, flags);
}
finish_wait(&pcf_wait, &wait);
} else {
pcf_pending = 0;
spin_unlock_irqrestore(&lock, flags);
}
} else {
udelay(100);
}
}
static irqreturn_t pcf_isa_handler(int this_irq, void *dev_id) {
spin_lock(&lock);
pcf_pending = 1;
spin_unlock(&lock);
wake_up_interruptible(&pcf_wait);
return IRQ_HANDLED;
}
static int pcf_isa_init(void)
{
spin_lock_init(&lock);
if (!mmapped) {
if (!request_region(base, 2, pcf_isa_ops.name)) {
printk(KERN_ERR "%s: requested I/O region (%#x:2) is "
"in use\n", pcf_isa_ops.name, base);
return -ENODEV;
}
base_iomem = ioport_map(base, 2);
if (!base_iomem) {
printk(KERN_ERR "%s: remap of I/O region %#x failed\n",
pcf_isa_ops.name, base);
release_region(base, 2);
return -ENODEV;
}
} else {
if (!request_mem_region(base, 2, pcf_isa_ops.name)) {
printk(KERN_ERR "%s: requested memory region (%#x:2) "
"is in use\n", pcf_isa_ops.name, base);
return -ENODEV;
}
base_iomem = ioremap(base, 2);
if (base_iomem == NULL) {
printk(KERN_ERR "%s: remap of memory region %#x "
"failed\n", pcf_isa_ops.name, base);
release_mem_region(base, 2);
return -ENODEV;
}
}
pr_debug("%s: registers %#x remapped to %p\n", pcf_isa_ops.name, base,
base_iomem);
if (irq > 0) {
if (request_irq(irq, pcf_isa_handler, 0, pcf_isa_ops.name,
NULL) < 0) {
printk(KERN_ERR "%s: Request irq%d failed\n",
pcf_isa_ops.name, irq);
irq = 0;
} else
enable_irq(irq);
}
return 0;
}
/* ------------------------------------------------------------------------
* Encapsulate the above functions in the correct operations structure.
* This is only done when more than one hardware adapter is supported.
*/
static struct i2c_algo_pcf_data pcf_isa_data = {
.setpcf = pcf_isa_setbyte,
.getpcf = pcf_isa_getbyte,
.getown = pcf_isa_getown,
.getclock = pcf_isa_getclock,
.waitforpin = pcf_isa_waitforpin,
};
static struct i2c_adapter pcf_isa_ops = {
.owner = THIS_MODULE,
.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
.algo_data = &pcf_isa_data,
.name = "i2c-elektor",
};
static int __devinit elektor_match(struct device *dev, unsigned int id)
{
#ifdef __alpha__
/* check to see we have memory mapped PCF8584 connected to the
Cypress cy82c693 PCI-ISA bridge as on UP2000 board */
if (base == 0) {
struct pci_dev *cy693_dev;
cy693_dev = pci_get_device(PCI_VENDOR_ID_CONTAQ,
PCI_DEVICE_ID_CONTAQ_82C693, NULL);
if (cy693_dev) {
unsigned char config;
/* yeap, we've found cypress, let's check config */
if (!pci_read_config_byte(cy693_dev, 0x47, &config)) {
dev_dbg(dev, "found cy82c693, config "
"register 0x47 = 0x%02x\n", config);
/* UP2000 board has this register set to 0xe1,
but the most significant bit as seems can be
reset during the proper initialisation
sequence if guys from API decides to do that
(so, we can even enable Tsunami Pchip
window for the upper 1 Gb) */
/* so just check for ROMCS at 0xe0000,
ROMCS enabled for writes
and external XD Bus buffer in use. */
if ((config & 0x7f) == 0x61) {
/* seems to be UP2000 like board */
base = 0xe0000;
mmapped = 1;
/* UP2000 drives ISA with
8.25 MHz (PCI/4) clock
(this can be read from cypress) */
clock = I2C_PCF_CLK | I2C_PCF_TRNS90;
dev_info(dev, "found API UP2000 like "
"board, will probe PCF8584 "
"later\n");
}
}
pci_dev_put(cy693_dev);
}
}
#endif
/* sanity checks for mmapped I/O */
if (mmapped && base < 0xc8000) {
dev_err(dev, "incorrect base address (%#x) specified "
"for mmapped I/O\n", base);
return 0;
}
if (base == 0) {
base = DEFAULT_BASE;
}
return 1;
}
static int __devinit elektor_probe(struct device *dev, unsigned int id)
{
init_waitqueue_head(&pcf_wait);
if (pcf_isa_init())
return -ENODEV;
pcf_isa_ops.dev.parent = dev;
if (i2c_pcf_add_bus(&pcf_isa_ops) < 0)
goto fail;
dev_info(dev, "found device at %#x\n", base);
return 0;
fail:
if (irq > 0) {
disable_irq(irq);
free_irq(irq, NULL);
}
if (!mmapped) {
ioport_unmap(base_iomem);
release_region(base, 2);
} else {
iounmap(base_iomem);
release_mem_region(base, 2);
}
return -ENODEV;
}
static int __devexit elektor_remove(struct device *dev, unsigned int id)
{
i2c_del_adapter(&pcf_isa_ops);
if (irq > 0) {
disable_irq(irq);
free_irq(irq, NULL);
}
if (!mmapped) {
ioport_unmap(base_iomem);
release_region(base, 2);
} else {
iounmap(base_iomem);
release_mem_region(base, 2);
}
return 0;
}
static struct isa_driver i2c_elektor_driver = {
.match = elektor_match,
.probe = elektor_probe,
.remove = __devexit_p(elektor_remove),
.driver = {
.owner = THIS_MODULE,
.name = "i2c-elektor",
},
};
static int __init i2c_pcfisa_init(void)
{
return isa_register_driver(&i2c_elektor_driver, 1);
}
static void __exit i2c_pcfisa_exit(void)
{
isa_unregister_driver(&i2c_elektor_driver);
}
MODULE_AUTHOR("Hans Berglund <hb@spacetec.no>");
MODULE_DESCRIPTION("I2C-Bus adapter routines for PCF8584 ISA bus adapter");
MODULE_LICENSE("GPL");
module_param(base, int, 0);
module_param(irq, int, 0);
module_param(clock, int, 0);
module_param(own, int, 0);
module_param(mmapped, int, 0);
module_init(i2c_pcfisa_init);
module_exit(i2c_pcfisa_exit);
| gpl-2.0 |
MarshedOut/android_kernel_lge_msm8974 | drivers/usb/host/ohci-jz4740.c | 8430 | 6214 | /*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
struct jz4740_ohci_hcd {
struct ohci_hcd ohci_hcd;
struct regulator *vbus;
bool vbus_enabled;
struct clk *clk;
};
static inline struct jz4740_ohci_hcd *hcd_to_jz4740_hcd(struct usb_hcd *hcd)
{
return (struct jz4740_ohci_hcd *)(hcd->hcd_priv);
}
static inline struct usb_hcd *jz4740_hcd_to_hcd(struct jz4740_ohci_hcd *jz4740_ohci)
{
return container_of((void *)jz4740_ohci, struct usb_hcd, hcd_priv);
}
static int ohci_jz4740_start(struct usb_hcd *hcd)
{
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
int ret;
ret = ohci_init(ohci);
if (ret < 0)
return ret;
ohci->num_ports = 1;
ret = ohci_run(ohci);
if (ret < 0) {
dev_err(hcd->self.controller, "Can not start %s",
hcd->self.bus_name);
ohci_stop(hcd);
return ret;
}
return 0;
}
static int ohci_jz4740_set_vbus_power(struct jz4740_ohci_hcd *jz4740_ohci,
bool enabled)
{
int ret = 0;
if (!jz4740_ohci->vbus)
return 0;
if (enabled && !jz4740_ohci->vbus_enabled) {
ret = regulator_enable(jz4740_ohci->vbus);
if (ret)
dev_err(jz4740_hcd_to_hcd(jz4740_ohci)->self.controller,
"Could not power vbus\n");
} else if (!enabled && jz4740_ohci->vbus_enabled) {
ret = regulator_disable(jz4740_ohci->vbus);
}
if (ret == 0)
jz4740_ohci->vbus_enabled = enabled;
return ret;
}
static int ohci_jz4740_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
u16 wIndex, char *buf, u16 wLength)
{
struct jz4740_ohci_hcd *jz4740_ohci = hcd_to_jz4740_hcd(hcd);
int ret;
switch (typeReq) {
case SetHubFeature:
if (wValue == USB_PORT_FEAT_POWER)
ret = ohci_jz4740_set_vbus_power(jz4740_ohci, true);
break;
case ClearHubFeature:
if (wValue == USB_PORT_FEAT_POWER)
ret = ohci_jz4740_set_vbus_power(jz4740_ohci, false);
break;
}
if (ret)
return ret;
return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
}
static const struct hc_driver ohci_jz4740_hc_driver = {
.description = hcd_name,
.product_desc = "JZ4740 OHCI",
.hcd_priv_size = sizeof(struct jz4740_ohci_hcd),
/*
* generic hardware linkage
*/
.irq = ohci_irq,
.flags = HCD_USB11 | HCD_MEMORY,
/*
* basic lifecycle operations
*/
.start = ohci_jz4740_start,
.stop = ohci_stop,
.shutdown = ohci_shutdown,
/*
* managing i/o requests and associated device resources
*/
.urb_enqueue = ohci_urb_enqueue,
.urb_dequeue = ohci_urb_dequeue,
.endpoint_disable = ohci_endpoint_disable,
/*
* scheduling support
*/
.get_frame_number = ohci_get_frame,
/*
* root hub support
*/
.hub_status_data = ohci_hub_status_data,
.hub_control = ohci_jz4740_hub_control,
#ifdef CONFIG_PM
.bus_suspend = ohci_bus_suspend,
.bus_resume = ohci_bus_resume,
#endif
.start_port_reset = ohci_start_port_reset,
};
static __devinit int jz4740_ohci_probe(struct platform_device *pdev)
{
int ret;
struct usb_hcd *hcd;
struct jz4740_ohci_hcd *jz4740_ohci;
struct resource *res;
int irq;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Failed to get platform resource\n");
return -ENOENT;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "Failed to get platform irq\n");
return irq;
}
hcd = usb_create_hcd(&ohci_jz4740_hc_driver, &pdev->dev, "jz4740");
if (!hcd) {
dev_err(&pdev->dev, "Failed to create hcd.\n");
return -ENOMEM;
}
jz4740_ohci = hcd_to_jz4740_hcd(hcd);
res = request_mem_region(res->start, resource_size(res), hcd_name);
if (!res) {
dev_err(&pdev->dev, "Failed to request mem region.\n");
ret = -EBUSY;
goto err_free;
}
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
hcd->regs = ioremap(res->start, resource_size(res));
if (!hcd->regs) {
dev_err(&pdev->dev, "Failed to ioremap registers.\n");
ret = -EBUSY;
goto err_release_mem;
}
jz4740_ohci->clk = clk_get(&pdev->dev, "uhc");
if (IS_ERR(jz4740_ohci->clk)) {
ret = PTR_ERR(jz4740_ohci->clk);
dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
goto err_iounmap;
}
jz4740_ohci->vbus = regulator_get(&pdev->dev, "vbus");
if (IS_ERR(jz4740_ohci->vbus))
jz4740_ohci->vbus = NULL;
clk_set_rate(jz4740_ohci->clk, 48000000);
clk_enable(jz4740_ohci->clk);
if (jz4740_ohci->vbus)
ohci_jz4740_set_vbus_power(jz4740_ohci, true);
platform_set_drvdata(pdev, hcd);
ohci_hcd_init(hcd_to_ohci(hcd));
ret = usb_add_hcd(hcd, irq, 0);
if (ret) {
dev_err(&pdev->dev, "Failed to add hcd: %d\n", ret);
goto err_disable;
}
return 0;
err_disable:
platform_set_drvdata(pdev, NULL);
if (jz4740_ohci->vbus) {
regulator_disable(jz4740_ohci->vbus);
regulator_put(jz4740_ohci->vbus);
}
clk_disable(jz4740_ohci->clk);
clk_put(jz4740_ohci->clk);
err_iounmap:
iounmap(hcd->regs);
err_release_mem:
release_mem_region(res->start, resource_size(res));
err_free:
usb_put_hcd(hcd);
return ret;
}
static __devexit int jz4740_ohci_remove(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct jz4740_ohci_hcd *jz4740_ohci = hcd_to_jz4740_hcd(hcd);
usb_remove_hcd(hcd);
platform_set_drvdata(pdev, NULL);
if (jz4740_ohci->vbus) {
regulator_disable(jz4740_ohci->vbus);
regulator_put(jz4740_ohci->vbus);
}
clk_disable(jz4740_ohci->clk);
clk_put(jz4740_ohci->clk);
iounmap(hcd->regs);
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
return 0;
}
static struct platform_driver ohci_hcd_jz4740_driver = {
.probe = jz4740_ohci_probe,
.remove = __devexit_p(jz4740_ohci_remove),
.driver = {
.name = "jz4740-ohci",
.owner = THIS_MODULE,
},
};
MODULE_ALIAS("platform:jz4740-ohci");
| gpl-2.0 |
Droid-Concepts/DC-Elite_kernel_jf | drivers/mfd/wm8350-regmap.c | 9198 | 126729 | /*
* wm8350-regmap.c -- Wolfson Microelectronics WM8350 register map
*
* This file splits out the tables describing the defaults and access
* status of the WM8350 registers since they are rather large.
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/mfd/wm8350/core.h>
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8350_mode0_defaults[] = {
0x17FF, /* R0 - Reset/ID */
0x1000, /* R1 - ID */
0x0000, /* R2 */
0x1002, /* R3 - System Control 1 */
0x0004, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 - Power Up Interrupt Status */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 - Power Up Interrupt Status Mask */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3B00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - LOUT1 Volume */
0x00E4, /* R105 - ROUT1 Volume */
0x00E4, /* R106 - LOUT2 Volume */
0x02E4, /* R107 - ROUT2 Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 - AIF Test */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x03FC, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0FFC, /* R134 - GPIO Configuration (i/o) */
0x0FFC, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0013, /* R140 - GPIO Function Select 1 */
0x0000, /* R141 - GPIO Function Select 2 */
0x0000, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x002D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0000, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0000, /* R186 - DCDC3 Control */
0x0000, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0000, /* R189 - DCDC4 Control */
0x0000, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0000, /* R195 - DCDC6 Control */
0x0000, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001C, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x001B, /* R203 - LDO2 Control */
0x0000, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001B, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001B, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 */
0x4000, /* R220 - RAM BIST 1 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 */
0x0000, /* R227 */
0x0000, /* R228 */
0x0000, /* R229 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 */
0x0000, /* R232 */
0x0000, /* R233 */
0x0000, /* R234 */
0x0000, /* R235 */
0x0000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0000, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0000, /* R243 */
0x0000, /* R244 */
0x0000, /* R245 */
0x0000, /* R246 */
0x0000, /* R247 */
0x0000, /* R248 */
0x0000, /* R249 */
0x0000, /* R250 */
0x0000, /* R251 */
0x0000, /* R252 */
0x0000, /* R253 */
0x0000, /* R254 */
0x0000, /* R255 */
};
#endif
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8350_mode1_defaults[] = {
0x17FF, /* R0 - Reset/ID */
0x1000, /* R1 - ID */
0x0000, /* R2 */
0x1002, /* R3 - System Control 1 */
0x0014, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 - Power Up Interrupt Status */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 - Power Up Interrupt Status Mask */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3B00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - LOUT1 Volume */
0x00E4, /* R105 - ROUT1 Volume */
0x00E4, /* R106 - LOUT2 Volume */
0x02E4, /* R107 - ROUT2 Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 - AIF Test */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x03FC, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x00FB, /* R134 - GPIO Configuration (i/o) */
0x04FE, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0312, /* R140 - GPIO Function Select 1 */
0x1003, /* R141 - GPIO Function Select 2 */
0x1331, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x002D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x0062, /* R180 - DCDC1 Control */
0x0400, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0026, /* R186 - DCDC3 Control */
0x0400, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0062, /* R189 - DCDC4 Control */
0x0400, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0026, /* R195 - DCDC6 Control */
0x0800, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x0006, /* R200 - LDO1 Control */
0x0400, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0006, /* R203 - LDO2 Control */
0x0400, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001B, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001B, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 */
0x4000, /* R220 - RAM BIST 1 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 */
0x0000, /* R227 */
0x0000, /* R228 */
0x0000, /* R229 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 */
0x0000, /* R232 */
0x0000, /* R233 */
0x0000, /* R234 */
0x0000, /* R235 */
0x0000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0000, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0000, /* R243 */
0x0000, /* R244 */
0x0000, /* R245 */
0x0000, /* R246 */
0x0000, /* R247 */
0x0000, /* R248 */
0x0000, /* R249 */
0x0000, /* R250 */
0x0000, /* R251 */
0x0000, /* R252 */
0x0000, /* R253 */
0x0000, /* R254 */
0x0000, /* R255 */
};
#endif
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8350_mode2_defaults[] = {
0x17FF, /* R0 - Reset/ID */
0x1000, /* R1 - ID */
0x0000, /* R2 */
0x1002, /* R3 - System Control 1 */
0x0014, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 - Power Up Interrupt Status */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 - Power Up Interrupt Status Mask */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3B00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - LOUT1 Volume */
0x00E4, /* R105 - ROUT1 Volume */
0x00E4, /* R106 - LOUT2 Volume */
0x02E4, /* R107 - ROUT2 Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 - AIF Test */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x03FC, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x08FB, /* R134 - GPIO Configuration (i/o) */
0x0CFE, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0312, /* R140 - GPIO Function Select 1 */
0x0003, /* R141 - GPIO Function Select 2 */
0x2331, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x002D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0400, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x002E, /* R186 - DCDC3 Control */
0x0800, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x000E, /* R189 - DCDC4 Control */
0x0800, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0026, /* R195 - DCDC6 Control */
0x0C00, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001A, /* R200 - LDO1 Control */
0x0800, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0010, /* R203 - LDO2 Control */
0x0800, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x000A, /* R206 - LDO3 Control */
0x0C00, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001A, /* R209 - LDO4 Control */
0x0800, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 */
0x4000, /* R220 - RAM BIST 1 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 */
0x0000, /* R227 */
0x0000, /* R228 */
0x0000, /* R229 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 */
0x0000, /* R232 */
0x0000, /* R233 */
0x0000, /* R234 */
0x0000, /* R235 */
0x0000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0000, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0000, /* R243 */
0x0000, /* R244 */
0x0000, /* R245 */
0x0000, /* R246 */
0x0000, /* R247 */
0x0000, /* R248 */
0x0000, /* R249 */
0x0000, /* R250 */
0x0000, /* R251 */
0x0000, /* R252 */
0x0000, /* R253 */
0x0000, /* R254 */
0x0000, /* R255 */
};
#endif
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8350_mode3_defaults[] = {
0x17FF, /* R0 - Reset/ID */
0x1000, /* R1 - ID */
0x0000, /* R2 */
0x1000, /* R3 - System Control 1 */
0x0004, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 - Power Up Interrupt Status */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 - Power Up Interrupt Status Mask */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3B00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - LOUT1 Volume */
0x00E4, /* R105 - ROUT1 Volume */
0x00E4, /* R106 - LOUT2 Volume */
0x02E4, /* R107 - ROUT2 Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 - AIF Test */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x03FC, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0A7B, /* R134 - GPIO Configuration (i/o) */
0x06FE, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x1312, /* R140 - GPIO Function Select 1 */
0x1030, /* R141 - GPIO Function Select 2 */
0x2231, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x002D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0400, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x000E, /* R186 - DCDC3 Control */
0x0400, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0026, /* R189 - DCDC4 Control */
0x0400, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0026, /* R195 - DCDC6 Control */
0x0400, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001C, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x001C, /* R203 - LDO2 Control */
0x0400, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001C, /* R206 - LDO3 Control */
0x0400, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001F, /* R209 - LDO4 Control */
0x0400, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 */
0x4000, /* R220 - RAM BIST 1 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 */
0x0000, /* R227 */
0x0000, /* R228 */
0x0000, /* R229 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 */
0x0000, /* R232 */
0x0000, /* R233 */
0x0000, /* R234 */
0x0000, /* R235 */
0x0000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0000, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0000, /* R243 */
0x0000, /* R244 */
0x0000, /* R245 */
0x0000, /* R246 */
0x0000, /* R247 */
0x0000, /* R248 */
0x0000, /* R249 */
0x0000, /* R250 */
0x0000, /* R251 */
0x0000, /* R252 */
0x0000, /* R253 */
0x0000, /* R254 */
0x0000, /* R255 */
};
#endif
#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8351_mode0_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0001, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0004, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x0000, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0FFC, /* R134 - GPIO Configuration (i/o) */
0x0FFC, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0013, /* R140 - GPIO Function Select 1 */
0x0000, /* R141 - GPIO Function Select 2 */
0x0000, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 */
0x0000, /* R175 */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0000, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0000, /* R186 - DCDC3 Control */
0x0000, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0000, /* R189 - DCDC4 Control */
0x0000, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 */
0x0000, /* R193 */
0x0000, /* R194 */
0x0000, /* R195 */
0x0000, /* R196 */
0x0006, /* R197 */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001C, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x001B, /* R203 - LDO2 Control */
0x0000, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001B, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001B, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 - FLL Test 1 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x1000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8351_mode1_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0001, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0204, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x0000, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0CFB, /* R134 - GPIO Configuration (i/o) */
0x0C1F, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0300, /* R140 - GPIO Function Select 1 */
0x1110, /* R141 - GPIO Function Select 2 */
0x0013, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 */
0x0000, /* R175 */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0C00, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0026, /* R186 - DCDC3 Control */
0x0400, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0062, /* R189 - DCDC4 Control */
0x0800, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 */
0x0000, /* R193 */
0x0000, /* R194 */
0x000A, /* R195 */
0x1000, /* R196 */
0x0006, /* R197 */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x0006, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0010, /* R203 - LDO2 Control */
0x0C00, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001F, /* R206 - LDO3 Control */
0x0800, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x000A, /* R209 - LDO4 Control */
0x0800, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 - FLL Test 1 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x1000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x1000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8351_mode2_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0001, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0214, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x0110, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x09FA, /* R134 - GPIO Configuration (i/o) */
0x0DF6, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x1310, /* R140 - GPIO Function Select 1 */
0x0003, /* R141 - GPIO Function Select 2 */
0x2000, /* R142 - GPIO Function Select 3 */
0x0000, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 */
0x0000, /* R175 */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x001A, /* R180 - DCDC1 Control */
0x0800, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0056, /* R186 - DCDC3 Control */
0x0400, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0026, /* R189 - DCDC4 Control */
0x0C00, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 */
0x0000, /* R193 */
0x0000, /* R194 */
0x0026, /* R195 */
0x0C00, /* R196 */
0x0006, /* R197 */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001C, /* R200 - LDO1 Control */
0x0400, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0010, /* R203 - LDO2 Control */
0x0C00, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x0015, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001A, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 - FLL Test 1 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x1000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8351_mode3_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0001, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0204, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0010, /* R129 - GPIO Pin pull up Control */
0x0000, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0BFB, /* R134 - GPIO Configuration (i/o) */
0x0FFD, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0310, /* R140 - GPIO Function Select 1 */
0x0001, /* R141 - GPIO Function Select 2 */
0x2300, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 */
0x0000, /* R175 */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0400, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0026, /* R186 - DCDC3 Control */
0x0800, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0062, /* R189 - DCDC4 Control */
0x1400, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 */
0x0000, /* R193 */
0x0000, /* R194 */
0x0026, /* R195 */
0x0400, /* R196 */
0x0006, /* R197 */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x0006, /* R200 - LDO1 Control */
0x0C00, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0016, /* R203 - LDO2 Control */
0x0000, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x0019, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001A, /* R209 - LDO4 Control */
0x1000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 - FLL Test 1 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x1000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8352_mode0_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0002, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0004, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x0000, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0FFC, /* R134 - GPIO Configuration (i/o) */
0x0FFC, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0013, /* R140 - GPIO Function Select 1 */
0x0000, /* R141 - GPIO Function Select 2 */
0x0000, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0000, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0000, /* R186 - DCDC3 Control */
0x0000, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0000, /* R189 - DCDC4 Control */
0x0000, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0000, /* R195 - DCDC6 Control */
0x0000, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001C, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x001B, /* R203 - LDO2 Control */
0x0000, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001B, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001B, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x5000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
0x5100, /* R252 */
0x1000, /* R253 - DCDC6 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8352_mode1_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0002, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0204, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x0000, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0BFB, /* R134 - GPIO Configuration (i/o) */
0x0FFF, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0300, /* R140 - GPIO Function Select 1 */
0x0000, /* R141 - GPIO Function Select 2 */
0x2300, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x0062, /* R180 - DCDC1 Control */
0x0400, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0006, /* R186 - DCDC3 Control */
0x0800, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x0006, /* R189 - DCDC4 Control */
0x0C00, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0026, /* R195 - DCDC6 Control */
0x1000, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x0002, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x001A, /* R203 - LDO2 Control */
0x0000, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001F, /* R206 - LDO3 Control */
0x0000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001F, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x5000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
0x5100, /* R252 */
0x1000, /* R253 - DCDC6 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8352_mode2_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0002, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0204, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0000, /* R129 - GPIO Pin pull up Control */
0x0110, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x09DA, /* R134 - GPIO Configuration (i/o) */
0x0DD6, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x1310, /* R140 - GPIO Function Select 1 */
0x0033, /* R141 - GPIO Function Select 2 */
0x2000, /* R142 - GPIO Function Select 3 */
0x0000, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x000E, /* R180 - DCDC1 Control */
0x0800, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0056, /* R186 - DCDC3 Control */
0x1800, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x000E, /* R189 - DCDC4 Control */
0x1000, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0026, /* R195 - DCDC6 Control */
0x0C00, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001C, /* R200 - LDO1 Control */
0x0000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0006, /* R203 - LDO2 Control */
0x0400, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x001C, /* R206 - LDO3 Control */
0x1400, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x001A, /* R209 - LDO4 Control */
0x0000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x5000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
0x5100, /* R252 */
0x1000, /* R253 - DCDC6 Test Controls */
};
#endif
#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
#undef WM8350_HAVE_CONFIG_MODE
#define WM8350_HAVE_CONFIG_MODE
const u16 wm8352_mode3_defaults[] = {
0x6143, /* R0 - Reset/ID */
0x0000, /* R1 - ID */
0x0002, /* R2 - Revision */
0x1C02, /* R3 - System Control 1 */
0x0204, /* R4 - System Control 2 */
0x0000, /* R5 - System Hibernate */
0x8A00, /* R6 - Interface Control */
0x0000, /* R7 */
0x8000, /* R8 - Power mgmt (1) */
0x0000, /* R9 - Power mgmt (2) */
0x0000, /* R10 - Power mgmt (3) */
0x2000, /* R11 - Power mgmt (4) */
0x0E00, /* R12 - Power mgmt (5) */
0x0000, /* R13 - Power mgmt (6) */
0x0000, /* R14 - Power mgmt (7) */
0x0000, /* R15 */
0x0000, /* R16 - RTC Seconds/Minutes */
0x0100, /* R17 - RTC Hours/Day */
0x0101, /* R18 - RTC Date/Month */
0x1400, /* R19 - RTC Year */
0x0000, /* R20 - Alarm Seconds/Minutes */
0x0000, /* R21 - Alarm Hours/Day */
0x0000, /* R22 - Alarm Date/Month */
0x0320, /* R23 - RTC Time Control */
0x0000, /* R24 - System Interrupts */
0x0000, /* R25 - Interrupt Status 1 */
0x0000, /* R26 - Interrupt Status 2 */
0x0000, /* R27 */
0x0000, /* R28 - Under Voltage Interrupt status */
0x0000, /* R29 - Over Current Interrupt status */
0x0000, /* R30 - GPIO Interrupt Status */
0x0000, /* R31 - Comparator Interrupt Status */
0x3FFF, /* R32 - System Interrupts Mask */
0x0000, /* R33 - Interrupt Status 1 Mask */
0x0000, /* R34 - Interrupt Status 2 Mask */
0x0000, /* R35 */
0x0000, /* R36 - Under Voltage Interrupt status Mask */
0x0000, /* R37 - Over Current Interrupt status Mask */
0x0000, /* R38 - GPIO Interrupt Status Mask */
0x0000, /* R39 - Comparator Interrupt Status Mask */
0x0040, /* R40 - Clock Control 1 */
0x0000, /* R41 - Clock Control 2 */
0x3A00, /* R42 - FLL Control 1 */
0x7086, /* R43 - FLL Control 2 */
0xC226, /* R44 - FLL Control 3 */
0x0000, /* R45 - FLL Control 4 */
0x0000, /* R46 */
0x0000, /* R47 */
0x0000, /* R48 - DAC Control */
0x0000, /* R49 */
0x00C0, /* R50 - DAC Digital Volume L */
0x00C0, /* R51 - DAC Digital Volume R */
0x0000, /* R52 */
0x0040, /* R53 - DAC LR Rate */
0x0000, /* R54 - DAC Clock Control */
0x0000, /* R55 */
0x0000, /* R56 */
0x0000, /* R57 */
0x4000, /* R58 - DAC Mute */
0x0000, /* R59 - DAC Mute Volume */
0x0000, /* R60 - DAC Side */
0x0000, /* R61 */
0x0000, /* R62 */
0x0000, /* R63 */
0x8000, /* R64 - ADC Control */
0x0000, /* R65 */
0x00C0, /* R66 - ADC Digital Volume L */
0x00C0, /* R67 - ADC Digital Volume R */
0x0000, /* R68 - ADC Divider */
0x0000, /* R69 */
0x0040, /* R70 - ADC LR Rate */
0x0000, /* R71 */
0x0303, /* R72 - Input Control */
0x0000, /* R73 - IN3 Input Control */
0x0000, /* R74 - Mic Bias Control */
0x0000, /* R75 */
0x0000, /* R76 - Output Control */
0x0000, /* R77 - Jack Detect */
0x0000, /* R78 - Anti Pop Control */
0x0000, /* R79 */
0x0040, /* R80 - Left Input Volume */
0x0040, /* R81 - Right Input Volume */
0x0000, /* R82 */
0x0000, /* R83 */
0x0000, /* R84 */
0x0000, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 */
0x0800, /* R88 - Left Mixer Control */
0x1000, /* R89 - Right Mixer Control */
0x0000, /* R90 */
0x0000, /* R91 */
0x0000, /* R92 - OUT3 Mixer Control */
0x0000, /* R93 - OUT4 Mixer Control */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 - Output Left Mixer Volume */
0x0000, /* R97 - Output Right Mixer Volume */
0x0000, /* R98 - Input Mixer Volume L */
0x0000, /* R99 - Input Mixer Volume R */
0x0000, /* R100 - Input Mixer Volume */
0x0000, /* R101 */
0x0000, /* R102 */
0x0000, /* R103 */
0x00E4, /* R104 - OUT1L Volume */
0x00E4, /* R105 - OUT1R Volume */
0x00E4, /* R106 - OUT2L Volume */
0x02E4, /* R107 - OUT2R Volume */
0x0000, /* R108 */
0x0000, /* R109 */
0x0000, /* R110 */
0x0000, /* R111 - BEEP Volume */
0x0A00, /* R112 - AI Formating */
0x0000, /* R113 - ADC DAC COMP */
0x0020, /* R114 - AI ADC Control */
0x0020, /* R115 - AI DAC Control */
0x0000, /* R116 */
0x0000, /* R117 */
0x0000, /* R118 */
0x0000, /* R119 */
0x0000, /* R120 */
0x0000, /* R121 */
0x0000, /* R122 */
0x0000, /* R123 */
0x0000, /* R124 */
0x0000, /* R125 */
0x0000, /* R126 */
0x0000, /* R127 */
0x1FFF, /* R128 - GPIO Debounce */
0x0010, /* R129 - GPIO Pin pull up Control */
0x0000, /* R130 - GPIO Pull down Control */
0x0000, /* R131 - GPIO Interrupt Mode */
0x0000, /* R132 */
0x0000, /* R133 - GPIO Control */
0x0BFB, /* R134 - GPIO Configuration (i/o) */
0x0FFD, /* R135 - GPIO Pin Polarity / Type */
0x0000, /* R136 */
0x0000, /* R137 */
0x0000, /* R138 */
0x0000, /* R139 */
0x0310, /* R140 - GPIO Function Select 1 */
0x0001, /* R141 - GPIO Function Select 2 */
0x2300, /* R142 - GPIO Function Select 3 */
0x0003, /* R143 - GPIO Function Select 4 */
0x0000, /* R144 - Digitiser Control (1) */
0x0002, /* R145 - Digitiser Control (2) */
0x0000, /* R146 */
0x0000, /* R147 */
0x0000, /* R148 */
0x0000, /* R149 */
0x0000, /* R150 */
0x0000, /* R151 */
0x7000, /* R152 - AUX1 Readback */
0x7000, /* R153 - AUX2 Readback */
0x7000, /* R154 - AUX3 Readback */
0x7000, /* R155 - AUX4 Readback */
0x0000, /* R156 - USB Voltage Readback */
0x0000, /* R157 - LINE Voltage Readback */
0x0000, /* R158 - BATT Voltage Readback */
0x0000, /* R159 - Chip Temp Readback */
0x0000, /* R160 */
0x0000, /* R161 */
0x0000, /* R162 */
0x0000, /* R163 - Generic Comparator Control */
0x0000, /* R164 - Generic comparator 1 */
0x0000, /* R165 - Generic comparator 2 */
0x0000, /* R166 - Generic comparator 3 */
0x0000, /* R167 - Generic comparator 4 */
0xA00F, /* R168 - Battery Charger Control 1 */
0x0B06, /* R169 - Battery Charger Control 2 */
0x0000, /* R170 - Battery Charger Control 3 */
0x0000, /* R171 */
0x0000, /* R172 - Current Sink Driver A */
0x0000, /* R173 - CSA Flash control */
0x0000, /* R174 - Current Sink Driver B */
0x0000, /* R175 - CSB Flash control */
0x0000, /* R176 - DCDC/LDO requested */
0x032D, /* R177 - DCDC Active options */
0x0000, /* R178 - DCDC Sleep options */
0x0025, /* R179 - Power-check comparator */
0x0006, /* R180 - DCDC1 Control */
0x0400, /* R181 - DCDC1 Timeouts */
0x1006, /* R182 - DCDC1 Low Power */
0x0018, /* R183 - DCDC2 Control */
0x0000, /* R184 - DCDC2 Timeouts */
0x0000, /* R185 */
0x0050, /* R186 - DCDC3 Control */
0x0C00, /* R187 - DCDC3 Timeouts */
0x0006, /* R188 - DCDC3 Low Power */
0x000E, /* R189 - DCDC4 Control */
0x0400, /* R190 - DCDC4 Timeouts */
0x0006, /* R191 - DCDC4 Low Power */
0x0008, /* R192 - DCDC5 Control */
0x0000, /* R193 - DCDC5 Timeouts */
0x0000, /* R194 */
0x0029, /* R195 - DCDC6 Control */
0x0800, /* R196 - DCDC6 Timeouts */
0x0006, /* R197 - DCDC6 Low Power */
0x0000, /* R198 */
0x0003, /* R199 - Limit Switch Control */
0x001D, /* R200 - LDO1 Control */
0x1000, /* R201 - LDO1 Timeouts */
0x001C, /* R202 - LDO1 Low Power */
0x0017, /* R203 - LDO2 Control */
0x1000, /* R204 - LDO2 Timeouts */
0x001C, /* R205 - LDO2 Low Power */
0x0006, /* R206 - LDO3 Control */
0x1000, /* R207 - LDO3 Timeouts */
0x001C, /* R208 - LDO3 Low Power */
0x0010, /* R209 - LDO4 Control */
0x1000, /* R210 - LDO4 Timeouts */
0x001C, /* R211 - LDO4 Low Power */
0x0000, /* R212 */
0x0000, /* R213 */
0x0000, /* R214 */
0x0000, /* R215 - VCC_FAULT Masks */
0x001F, /* R216 - Main Bandgap Control */
0x0000, /* R217 - OSC Control */
0x9000, /* R218 - RTC Tick Control */
0x0000, /* R219 - Security1 */
0x4000, /* R220 */
0x0000, /* R221 */
0x0000, /* R222 */
0x0000, /* R223 */
0x0000, /* R224 - Signal overrides */
0x0000, /* R225 - DCDC/LDO status */
0x0000, /* R226 - Charger Overides/status */
0x0000, /* R227 - misc overrides */
0x0000, /* R228 - Supply overrides/status 1 */
0x0000, /* R229 - Supply overrides/status 2 */
0xE000, /* R230 - GPIO Pin Status */
0x0000, /* R231 - comparotor overrides */
0x0000, /* R232 */
0x0000, /* R233 - State Machine status */
0x1200, /* R234 */
0x0000, /* R235 */
0x8000, /* R236 */
0x0000, /* R237 */
0x0000, /* R238 */
0x0000, /* R239 */
0x0003, /* R240 */
0x0000, /* R241 */
0x0000, /* R242 */
0x0004, /* R243 */
0x0300, /* R244 */
0x0000, /* R245 */
0x0200, /* R246 */
0x0000, /* R247 */
0x1000, /* R248 - DCDC1 Test Controls */
0x5000, /* R249 */
0x1000, /* R250 - DCDC3 Test Controls */
0x1000, /* R251 - DCDC4 Test Controls */
0x5100, /* R252 */
0x1000, /* R253 - DCDC6 Test Controls */
};
#endif
/*
* Access masks.
*/
const struct wm8350_reg_access wm8350_reg_io_map[] = {
/* read write volatile */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R0 - Reset/ID */
{ 0x7CFF, 0x0C00, 0x7FFF }, /* R1 - ID */
{ 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
{ 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
{ 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
{ 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
{ 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
{ 0x0000, 0x0000, 0x0000 }, /* R7 */
{ 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
{ 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
{ 0x008F, 0x008F, 0xFFFF }, /* R10 - Power mgmt (3) */
{ 0x6D3C, 0x6D3C, 0xFFFF }, /* R11 - Power mgmt (4) */
{ 0x1F8F, 0x1F8F, 0xFFFF }, /* R12 - Power mgmt (5) */
{ 0x8F3F, 0x8F3F, 0xFFFF }, /* R13 - Power mgmt (6) */
{ 0x0003, 0x0003, 0xFFFF }, /* R14 - Power mgmt (7) */
{ 0x0000, 0x0000, 0x0000 }, /* R15 */
{ 0x7F7F, 0x7F7F, 0xFFFF }, /* R16 - RTC Seconds/Minutes */
{ 0x073F, 0x073F, 0xFFFF }, /* R17 - RTC Hours/Day */
{ 0x1F3F, 0x1F3F, 0xFFFF }, /* R18 - RTC Date/Month */
{ 0x3FFF, 0x00FF, 0xFFFF }, /* R19 - RTC Year */
{ 0x7F7F, 0x7F7F, 0x0000 }, /* R20 - Alarm Seconds/Minutes */
{ 0x0F3F, 0x0F3F, 0x0000 }, /* R21 - Alarm Hours/Day */
{ 0x1F3F, 0x1F3F, 0x0000 }, /* R22 - Alarm Date/Month */
{ 0xEF7F, 0xEA7F, 0xFFFF }, /* R23 - RTC Time Control */
{ 0x3BFF, 0x0000, 0xFFFF }, /* R24 - System Interrupts */
{ 0xFEE7, 0x0000, 0xFFFF }, /* R25 - Interrupt Status 1 */
{ 0x35FF, 0x0000, 0xFFFF }, /* R26 - Interrupt Status 2 */
{ 0x0F3F, 0x0000, 0xFFFF }, /* R27 - Power Up Interrupt Status */
{ 0x0F3F, 0x0000, 0xFFFF }, /* R28 - Under Voltage Interrupt status */
{ 0x8000, 0x0000, 0xFFFF }, /* R29 - Over Current Interrupt status */
{ 0x1FFF, 0x0000, 0xFFFF }, /* R30 - GPIO Interrupt Status */
{ 0xEF7F, 0x0000, 0xFFFF }, /* R31 - Comparator Interrupt Status */
{ 0x3FFF, 0x3FFF, 0x0000 }, /* R32 - System Interrupts Mask */
{ 0xFEE7, 0xFEE7, 0x0000 }, /* R33 - Interrupt Status 1 Mask */
{ 0xF5FF, 0xF5FF, 0x0000 }, /* R34 - Interrupt Status 2 Mask */
{ 0x0F3F, 0x0F3F, 0x0000 }, /* R35 - Power Up Interrupt Status Mask */
{ 0x0F3F, 0x0F3F, 0x0000 }, /* R36 - Under Voltage Int status Mask */
{ 0x8000, 0x8000, 0x0000 }, /* R37 - Over Current Int status Mask */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R38 - GPIO Interrupt Status Mask */
{ 0xEF7F, 0xEF7F, 0x0000 }, /* R39 - Comparator IntStatus Mask */
{ 0xC9F7, 0xC9F7, 0xFFFF }, /* R40 - Clock Control 1 */
{ 0x8001, 0x8001, 0x0000 }, /* R41 - Clock Control 2 */
{ 0xFFF7, 0xFFF7, 0xFFFF }, /* R42 - FLL Control 1 */
{ 0xFBFF, 0xFBFF, 0x0000 }, /* R43 - FLL Control 2 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R44 - FLL Control 3 */
{ 0x0033, 0x0033, 0x0000 }, /* R45 - FLL Control 4 */
{ 0x0000, 0x0000, 0x0000 }, /* R46 */
{ 0x0000, 0x0000, 0x0000 }, /* R47 */
{ 0x3033, 0x3033, 0x0000 }, /* R48 - DAC Control */
{ 0x0000, 0x0000, 0x0000 }, /* R49 */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R50 - DAC Digital Volume L */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R51 - DAC Digital Volume R */
{ 0x0000, 0x0000, 0x0000 }, /* R52 */
{ 0x0FFF, 0x0FFF, 0xFFFF }, /* R53 - DAC LR Rate */
{ 0x0017, 0x0017, 0x0000 }, /* R54 - DAC Clock Control */
{ 0x0000, 0x0000, 0x0000 }, /* R55 */
{ 0x0000, 0x0000, 0x0000 }, /* R56 */
{ 0x0000, 0x0000, 0x0000 }, /* R57 */
{ 0x4000, 0x4000, 0x0000 }, /* R58 - DAC Mute */
{ 0x7000, 0x7000, 0x0000 }, /* R59 - DAC Mute Volume */
{ 0x3C00, 0x3C00, 0x0000 }, /* R60 - DAC Side */
{ 0x0000, 0x0000, 0x0000 }, /* R61 */
{ 0x0000, 0x0000, 0x0000 }, /* R62 */
{ 0x0000, 0x0000, 0x0000 }, /* R63 */
{ 0x8303, 0x8303, 0xFFFF }, /* R64 - ADC Control */
{ 0x0000, 0x0000, 0x0000 }, /* R65 */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R66 - ADC Digital Volume L */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R67 - ADC Digital Volume R */
{ 0x0FFF, 0x0FFF, 0x0000 }, /* R68 - ADC Divider */
{ 0x0000, 0x0000, 0x0000 }, /* R69 */
{ 0x0FFF, 0x0FFF, 0xFFFF }, /* R70 - ADC LR Rate */
{ 0x0000, 0x0000, 0x0000 }, /* R71 */
{ 0x0707, 0x0707, 0xFFFF }, /* R72 - Input Control */
{ 0xC0C0, 0xC0C0, 0xFFFF }, /* R73 - IN3 Input Control */
{ 0xC09F, 0xC09F, 0xFFFF }, /* R74 - Mic Bias Control */
{ 0x0000, 0x0000, 0x0000 }, /* R75 */
{ 0x0F15, 0x0F15, 0xFFFF }, /* R76 - Output Control */
{ 0xC000, 0xC000, 0xFFFF }, /* R77 - Jack Detect */
{ 0x03FF, 0x03FF, 0x0000 }, /* R78 - Anti Pop Control */
{ 0x0000, 0x0000, 0x0000 }, /* R79 */
{ 0xE1FC, 0xE1FC, 0x8000 }, /* R80 - Left Input Volume */
{ 0xE1FC, 0xE1FC, 0x8000 }, /* R81 - Right Input Volume */
{ 0x0000, 0x0000, 0x0000 }, /* R82 */
{ 0x0000, 0x0000, 0x0000 }, /* R83 */
{ 0x0000, 0x0000, 0x0000 }, /* R84 */
{ 0x0000, 0x0000, 0x0000 }, /* R85 */
{ 0x0000, 0x0000, 0x0000 }, /* R86 */
{ 0x0000, 0x0000, 0x0000 }, /* R87 */
{ 0x9807, 0x9807, 0xFFFF }, /* R88 - Left Mixer Control */
{ 0x980B, 0x980B, 0xFFFF }, /* R89 - Right Mixer Control */
{ 0x0000, 0x0000, 0x0000 }, /* R90 */
{ 0x0000, 0x0000, 0x0000 }, /* R91 */
{ 0x8909, 0x8909, 0xFFFF }, /* R92 - OUT3 Mixer Control */
{ 0x9E07, 0x9E07, 0xFFFF }, /* R93 - OUT4 Mixer Control */
{ 0x0000, 0x0000, 0x0000 }, /* R94 */
{ 0x0000, 0x0000, 0x0000 }, /* R95 */
{ 0x0EEE, 0x0EEE, 0x0000 }, /* R96 - Output Left Mixer Volume */
{ 0xE0EE, 0xE0EE, 0x0000 }, /* R97 - Output Right Mixer Volume */
{ 0x0E0F, 0x0E0F, 0x0000 }, /* R98 - Input Mixer Volume L */
{ 0xE0E1, 0xE0E1, 0x0000 }, /* R99 - Input Mixer Volume R */
{ 0x800E, 0x800E, 0x0000 }, /* R100 - Input Mixer Volume */
{ 0x0000, 0x0000, 0x0000 }, /* R101 */
{ 0x0000, 0x0000, 0x0000 }, /* R102 */
{ 0x0000, 0x0000, 0x0000 }, /* R103 */
{ 0xE1FC, 0xE1FC, 0xFFFF }, /* R104 - LOUT1 Volume */
{ 0xE1FC, 0xE1FC, 0xFFFF }, /* R105 - ROUT1 Volume */
{ 0xE1FC, 0xE1FC, 0xFFFF }, /* R106 - LOUT2 Volume */
{ 0xE7FC, 0xE7FC, 0xFFFF }, /* R107 - ROUT2 Volume */
{ 0x0000, 0x0000, 0x0000 }, /* R108 */
{ 0x0000, 0x0000, 0x0000 }, /* R109 */
{ 0x0000, 0x0000, 0x0000 }, /* R110 */
{ 0x80E0, 0x80E0, 0xFFFF }, /* R111 - BEEP Volume */
{ 0xBF00, 0xBF00, 0x0000 }, /* R112 - AI Formating */
{ 0x00F1, 0x00F1, 0x0000 }, /* R113 - ADC DAC COMP */
{ 0x00F8, 0x00F8, 0x0000 }, /* R114 - AI ADC Control */
{ 0x40FB, 0x40FB, 0x0000 }, /* R115 - AI DAC Control */
{ 0x7C30, 0x7C30, 0x0000 }, /* R116 - AIF Test */
{ 0x0000, 0x0000, 0x0000 }, /* R117 */
{ 0x0000, 0x0000, 0x0000 }, /* R118 */
{ 0x0000, 0x0000, 0x0000 }, /* R119 */
{ 0x0000, 0x0000, 0x0000 }, /* R120 */
{ 0x0000, 0x0000, 0x0000 }, /* R121 */
{ 0x0000, 0x0000, 0x0000 }, /* R122 */
{ 0x0000, 0x0000, 0x0000 }, /* R123 */
{ 0x0000, 0x0000, 0x0000 }, /* R124 */
{ 0x0000, 0x0000, 0x0000 }, /* R125 */
{ 0x0000, 0x0000, 0x0000 }, /* R126 */
{ 0x0000, 0x0000, 0x0000 }, /* R127 */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R128 - GPIO Debounce */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R129 - GPIO Pin pull up Control */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R130 - GPIO Pull down Control */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R131 - GPIO Interrupt Mode */
{ 0x0000, 0x0000, 0x0000 }, /* R132 */
{ 0x00C0, 0x00C0, 0x0000 }, /* R133 - GPIO Control */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R134 - GPIO Configuration (i/o) */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R135 - GPIO Pin Polarity / Type */
{ 0x0000, 0x0000, 0x0000 }, /* R136 */
{ 0x0000, 0x0000, 0x0000 }, /* R137 */
{ 0x0000, 0x0000, 0x0000 }, /* R138 */
{ 0x0000, 0x0000, 0x0000 }, /* R139 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R140 - GPIO Function Select 1 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R141 - GPIO Function Select 2 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R142 - GPIO Function Select 3 */
{ 0x000F, 0x000F, 0x0000 }, /* R143 - GPIO Function Select 4 */
{ 0xF0FF, 0xF0FF, 0xA000 }, /* R144 - Digitiser Control (1) */
{ 0x3707, 0x3707, 0x0000 }, /* R145 - Digitiser Control (2) */
{ 0x0000, 0x0000, 0x0000 }, /* R146 */
{ 0x0000, 0x0000, 0x0000 }, /* R147 */
{ 0x0000, 0x0000, 0x0000 }, /* R148 */
{ 0x0000, 0x0000, 0x0000 }, /* R149 */
{ 0x0000, 0x0000, 0x0000 }, /* R150 */
{ 0x0000, 0x0000, 0x0000 }, /* R151 */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R152 - AUX1 Readback */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R153 - AUX2 Readback */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R154 - AUX3 Readback */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R155 - AUX4 Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R156 - USB Voltage Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R157 - LINE Voltage Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R158 - BATT Voltage Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R159 - Chip Temp Readback */
{ 0x0000, 0x0000, 0x0000 }, /* R160 */
{ 0x0000, 0x0000, 0x0000 }, /* R161 */
{ 0x0000, 0x0000, 0x0000 }, /* R162 */
{ 0x000F, 0x000F, 0x0000 }, /* R163 - Generic Comparator Control */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R164 - Generic comparator 1 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R165 - Generic comparator 2 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R166 - Generic comparator 3 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R167 - Generic comparator 4 */
{ 0xBFFF, 0xBFFF, 0x8000 }, /* R168 - Battery Charger Control 1 */
{ 0xFFFF, 0x4FFF, 0xB000 }, /* R169 - Battery Charger Control 2 */
{ 0x007F, 0x007F, 0x0000 }, /* R170 - Battery Charger Control 3 */
{ 0x0000, 0x0000, 0x0000 }, /* R171 */
{ 0x903F, 0x903F, 0xFFFF }, /* R172 - Current Sink Driver A */
{ 0xE333, 0xE333, 0xFFFF }, /* R173 - CSA Flash control */
{ 0x903F, 0x903F, 0xFFFF }, /* R174 - Current Sink Driver B */
{ 0xE333, 0xE333, 0xFFFF }, /* R175 - CSB Flash control */
{ 0x8F3F, 0x8F3F, 0xFFFF }, /* R176 - DCDC/LDO requested */
{ 0x332D, 0x332D, 0x0000 }, /* R177 - DCDC Active options */
{ 0x002D, 0x002D, 0x0000 }, /* R178 - DCDC Sleep options */
{ 0x5177, 0x5177, 0x8000 }, /* R179 - Power-check comparator */
{ 0x047F, 0x047F, 0x0000 }, /* R180 - DCDC1 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R181 - DCDC1 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R182 - DCDC1 Low Power */
{ 0x535B, 0x535B, 0x0000 }, /* R183 - DCDC2 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R184 - DCDC2 Timeouts */
{ 0x0000, 0x0000, 0x0000 }, /* R185 */
{ 0x047F, 0x047F, 0x0000 }, /* R186 - DCDC3 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R187 - DCDC3 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R188 - DCDC3 Low Power */
{ 0x047F, 0x047F, 0x0000 }, /* R189 - DCDC4 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R190 - DCDC4 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R191 - DCDC4 Low Power */
{ 0x535B, 0x535B, 0x0000 }, /* R192 - DCDC5 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R193 - DCDC5 Timeouts */
{ 0x0000, 0x0000, 0x0000 }, /* R194 */
{ 0x047F, 0x047F, 0x0000 }, /* R195 - DCDC6 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R196 - DCDC6 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R197 - DCDC6 Low Power */
{ 0x0000, 0x0000, 0x0000 }, /* R198 */
{ 0xFFD3, 0xFFD3, 0x0000 }, /* R199 - Limit Switch Control */
{ 0x441F, 0x441F, 0x0000 }, /* R200 - LDO1 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R201 - LDO1 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R202 - LDO1 Low Power */
{ 0x441F, 0x441F, 0x0000 }, /* R203 - LDO2 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R204 - LDO2 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R205 - LDO2 Low Power */
{ 0x441F, 0x441F, 0x0000 }, /* R206 - LDO3 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R207 - LDO3 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R208 - LDO3 Low Power */
{ 0x441F, 0x441F, 0x0000 }, /* R209 - LDO4 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R210 - LDO4 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R211 - LDO4 Low Power */
{ 0x0000, 0x0000, 0x0000 }, /* R212 */
{ 0x0000, 0x0000, 0x0000 }, /* R213 */
{ 0x0000, 0x0000, 0x0000 }, /* R214 */
{ 0x8F3F, 0x8F3F, 0x0000 }, /* R215 - VCC_FAULT Masks */
{ 0xFF3F, 0xE03F, 0x0000 }, /* R216 - Main Bandgap Control */
{ 0xEF2F, 0xE02F, 0x0000 }, /* R217 - OSC Control */
{ 0xF3FF, 0xB3FF, 0xc000 }, /* R218 - RTC Tick Control */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R219 - Security */
{ 0x09FF, 0x01FF, 0x0000 }, /* R220 - RAM BIST 1 */
{ 0x0000, 0x0000, 0x0000 }, /* R221 */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R222 */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R223 */
{ 0x0000, 0x0000, 0x0000 }, /* R224 */
{ 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
{ 0x0000, 0x0000, 0xFFFF }, /* R226 - Charger status */
{ 0x34FE, 0x0000, 0xFFFF }, /* R227 */
{ 0x0000, 0x0000, 0x0000 }, /* R228 */
{ 0x0000, 0x0000, 0x0000 }, /* R229 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R230 - GPIO Pin Status */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R231 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R232 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R233 */
{ 0x0000, 0x0000, 0x0000 }, /* R234 */
{ 0x0000, 0x0000, 0x0000 }, /* R235 */
{ 0x0000, 0x0000, 0x0000 }, /* R236 */
{ 0x0000, 0x0000, 0x0000 }, /* R237 */
{ 0x0000, 0x0000, 0x0000 }, /* R238 */
{ 0x0000, 0x0000, 0x0000 }, /* R239 */
{ 0x0000, 0x0000, 0x0000 }, /* R240 */
{ 0x0000, 0x0000, 0x0000 }, /* R241 */
{ 0x0000, 0x0000, 0x0000 }, /* R242 */
{ 0x0000, 0x0000, 0x0000 }, /* R243 */
{ 0x0000, 0x0000, 0x0000 }, /* R244 */
{ 0x0000, 0x0000, 0x0000 }, /* R245 */
{ 0x0000, 0x0000, 0x0000 }, /* R246 */
{ 0x0000, 0x0000, 0x0000 }, /* R247 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R248 */
{ 0x0000, 0x0000, 0x0000 }, /* R249 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R250 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R251 */
{ 0x0000, 0x0000, 0x0000 }, /* R252 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R253 */
{ 0x0000, 0x0000, 0x0000 }, /* R254 */
{ 0x0000, 0x0000, 0x0000 }, /* R255 */
};
| gpl-2.0 |
CyanogenMod/android_kernel_htc_endeavoru | sound/pci/echoaudio/darla20_dsp.c | 12526 | 3506 | /***************************************************************************
Copyright Echo Digital Audio Corporation (c) 1998 - 2004
All rights reserved
www.echoaudio.com
This file is part of Echo Digital Audio's generic driver library.
Echo Digital Audio's generic driver library is free software;
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by the Free Software
Foundation.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston,
MA 02111-1307, USA.
*************************************************************************
Translation from C++ and adaptation for use in ALSA-Driver
were made by Giuliano Pochini <pochini@shiny.it>
****************************************************************************/
static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
{
int err;
DE_INIT(("init_hw() - Darla20\n"));
if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA20))
return -ENODEV;
if ((err = init_dsp_comm_page(chip))) {
DE_INIT(("init_hw - could not initialize DSP comm page\n"));
return err;
}
chip->device_id = device_id;
chip->subdevice_id = subdevice_id;
chip->bad_board = TRUE;
chip->dsp_code_to_load = FW_DARLA20_DSP;
chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
chip->clock_state = GD_CLOCK_UNDEF;
/* Since this card has no ASIC, mark it as loaded so everything
works OK */
chip->asic_loaded = TRUE;
chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL;
if ((err = load_firmware(chip)) < 0)
return err;
chip->bad_board = FALSE;
DE_INIT(("init_hw done\n"));
return err;
}
static int set_mixer_defaults(struct echoaudio *chip)
{
return init_line_levels(chip);
}
/* The Darla20 has no external clock sources */
static u32 detect_input_clocks(const struct echoaudio *chip)
{
return ECHO_CLOCK_BIT_INTERNAL;
}
/* The Darla20 has no ASIC. Just do nothing */
static int load_asic(struct echoaudio *chip)
{
return 0;
}
static int set_sample_rate(struct echoaudio *chip, u32 rate)
{
u8 clock_state, spdif_status;
if (wait_handshake(chip))
return -EIO;
switch (rate) {
case 44100:
clock_state = GD_CLOCK_44;
spdif_status = GD_SPDIF_STATUS_44;
break;
case 48000:
clock_state = GD_CLOCK_48;
spdif_status = GD_SPDIF_STATUS_48;
break;
default:
clock_state = GD_CLOCK_NOCHANGE;
spdif_status = GD_SPDIF_STATUS_NOCHANGE;
break;
}
if (chip->clock_state == clock_state)
clock_state = GD_CLOCK_NOCHANGE;
if (spdif_status == chip->spdif_status)
spdif_status = GD_SPDIF_STATUS_NOCHANGE;
chip->comm_page->sample_rate = cpu_to_le32(rate);
chip->comm_page->gd_clock_state = clock_state;
chip->comm_page->gd_spdif_status = spdif_status;
chip->comm_page->gd_resampler_state = 3; /* magic number - should always be 3 */
/* Save the new audio state if it changed */
if (clock_state != GD_CLOCK_NOCHANGE)
chip->clock_state = clock_state;
if (spdif_status != GD_SPDIF_STATUS_NOCHANGE)
chip->spdif_status = spdif_status;
chip->sample_rate = rate;
clear_handshake(chip);
return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
}
| gpl-2.0 |
JASON-RR/Imperium_Kernel_TW_5.0.1 | drivers/hv/channel.c | 239 | 23424 | /*
* Copyright (c) 2009, Microsoft Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/hyperv.h>
#include "hyperv_vmbus.h"
#define NUM_PAGES_SPANNED(addr, len) \
((PAGE_ALIGN(addr + len) >> PAGE_SHIFT) - (addr >> PAGE_SHIFT))
/* Internal routines */
static int create_gpadl_header(
void *kbuffer, /* must be phys and virt contiguous */
u32 size, /* page-size multiple */
struct vmbus_channel_msginfo **msginfo,
u32 *messagecount);
static void vmbus_setevent(struct vmbus_channel *channel);
/*
* vmbus_setevent- Trigger an event notification on the specified
* channel.
*/
static void vmbus_setevent(struct vmbus_channel *channel)
{
struct hv_monitor_page *monitorpage;
if (channel->offermsg.monitor_allocated) {
/* Each u32 represents 32 channels */
sync_set_bit(channel->offermsg.child_relid & 31,
(unsigned long *) vmbus_connection.send_int_page +
(channel->offermsg.child_relid >> 5));
monitorpage = vmbus_connection.monitor_pages;
monitorpage++; /* Get the child to parent monitor page */
sync_set_bit(channel->monitor_bit,
(unsigned long *)&monitorpage->trigger_group
[channel->monitor_grp].pending);
} else {
vmbus_set_event(channel->offermsg.child_relid);
}
}
/*
* vmbus_get_debug_info -Retrieve various channel debug info
*/
void vmbus_get_debug_info(struct vmbus_channel *channel,
struct vmbus_channel_debug_info *debuginfo)
{
struct hv_monitor_page *monitorpage;
u8 monitor_group = (u8)channel->offermsg.monitorid / 32;
u8 monitor_offset = (u8)channel->offermsg.monitorid % 32;
debuginfo->relid = channel->offermsg.child_relid;
debuginfo->state = channel->state;
memcpy(&debuginfo->interfacetype,
&channel->offermsg.offer.if_type, sizeof(uuid_le));
memcpy(&debuginfo->interface_instance,
&channel->offermsg.offer.if_instance,
sizeof(uuid_le));
monitorpage = (struct hv_monitor_page *)vmbus_connection.monitor_pages;
debuginfo->monitorid = channel->offermsg.monitorid;
debuginfo->servermonitor_pending =
monitorpage->trigger_group[monitor_group].pending;
debuginfo->servermonitor_latency =
monitorpage->latency[monitor_group][monitor_offset];
debuginfo->servermonitor_connectionid =
monitorpage->parameter[monitor_group]
[monitor_offset].connectionid.u.id;
monitorpage++;
debuginfo->clientmonitor_pending =
monitorpage->trigger_group[monitor_group].pending;
debuginfo->clientmonitor_latency =
monitorpage->latency[monitor_group][monitor_offset];
debuginfo->clientmonitor_connectionid =
monitorpage->parameter[monitor_group]
[monitor_offset].connectionid.u.id;
hv_ringbuffer_get_debuginfo(&channel->inbound, &debuginfo->inbound);
hv_ringbuffer_get_debuginfo(&channel->outbound, &debuginfo->outbound);
}
/*
* vmbus_open - Open the specified channel.
*/
int vmbus_open(struct vmbus_channel *newchannel, u32 send_ringbuffer_size,
u32 recv_ringbuffer_size, void *userdata, u32 userdatalen,
void (*onchannelcallback)(void *context), void *context)
{
struct vmbus_channel_open_channel *open_msg;
struct vmbus_channel_msginfo *open_info = NULL;
void *in, *out;
unsigned long flags;
int ret, t, err = 0;
newchannel->onchannel_callback = onchannelcallback;
newchannel->channel_callback_context = context;
/* Allocate the ring buffer */
out = (void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
get_order(send_ringbuffer_size + recv_ringbuffer_size));
if (!out)
return -ENOMEM;
in = (void *)((unsigned long)out + send_ringbuffer_size);
newchannel->ringbuffer_pages = out;
newchannel->ringbuffer_pagecount = (send_ringbuffer_size +
recv_ringbuffer_size) >> PAGE_SHIFT;
ret = hv_ringbuffer_init(
&newchannel->outbound, out, send_ringbuffer_size);
if (ret != 0) {
err = ret;
goto error0;
}
ret = hv_ringbuffer_init(
&newchannel->inbound, in, recv_ringbuffer_size);
if (ret != 0) {
err = ret;
goto error0;
}
/* Establish the gpadl for the ring buffer */
newchannel->ringbuffer_gpadlhandle = 0;
ret = vmbus_establish_gpadl(newchannel,
newchannel->outbound.ring_buffer,
send_ringbuffer_size +
recv_ringbuffer_size,
&newchannel->ringbuffer_gpadlhandle);
if (ret != 0) {
err = ret;
goto error0;
}
/* Create and init the channel open message */
open_info = kmalloc(sizeof(*open_info) +
sizeof(struct vmbus_channel_open_channel),
GFP_KERNEL);
if (!open_info) {
err = -ENOMEM;
goto error0;
}
init_completion(&open_info->waitevent);
open_msg = (struct vmbus_channel_open_channel *)open_info->msg;
open_msg->header.msgtype = CHANNELMSG_OPENCHANNEL;
open_msg->openid = newchannel->offermsg.child_relid;
open_msg->child_relid = newchannel->offermsg.child_relid;
open_msg->ringbuffer_gpadlhandle = newchannel->ringbuffer_gpadlhandle;
open_msg->downstream_ringbuffer_pageoffset = send_ringbuffer_size >>
PAGE_SHIFT;
open_msg->server_contextarea_gpadlhandle = 0;
if (userdatalen > MAX_USER_DEFINED_BYTES) {
err = -EINVAL;
goto error0;
}
if (userdatalen)
memcpy(open_msg->userdata, userdata, userdatalen);
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_add_tail(&open_info->msglistentry,
&vmbus_connection.chn_msg_list);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
ret = vmbus_post_msg(open_msg,
sizeof(struct vmbus_channel_open_channel));
if (ret != 0) {
err = ret;
goto error1;
}
t = wait_for_completion_timeout(&open_info->waitevent, 5*HZ);
if (t == 0) {
err = -ETIMEDOUT;
goto error1;
}
if (open_info->response.open_result.status)
err = open_info->response.open_result.status;
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_del(&open_info->msglistentry);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
kfree(open_info);
return err;
error1:
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_del(&open_info->msglistentry);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
error0:
free_pages((unsigned long)out,
get_order(send_ringbuffer_size + recv_ringbuffer_size));
kfree(open_info);
return err;
}
EXPORT_SYMBOL_GPL(vmbus_open);
/*
* create_gpadl_header - Creates a gpadl for the specified buffer
*/
static int create_gpadl_header(void *kbuffer, u32 size,
struct vmbus_channel_msginfo **msginfo,
u32 *messagecount)
{
int i;
int pagecount;
unsigned long long pfn;
struct vmbus_channel_gpadl_header *gpadl_header;
struct vmbus_channel_gpadl_body *gpadl_body;
struct vmbus_channel_msginfo *msgheader;
struct vmbus_channel_msginfo *msgbody = NULL;
u32 msgsize;
int pfnsum, pfncount, pfnleft, pfncurr, pfnsize;
pagecount = size >> PAGE_SHIFT;
pfn = virt_to_phys(kbuffer) >> PAGE_SHIFT;
/* do we need a gpadl body msg */
pfnsize = MAX_SIZE_CHANNEL_MESSAGE -
sizeof(struct vmbus_channel_gpadl_header) -
sizeof(struct gpa_range);
pfncount = pfnsize / sizeof(u64);
if (pagecount > pfncount) {
/* we need a gpadl body */
/* fill in the header */
msgsize = sizeof(struct vmbus_channel_msginfo) +
sizeof(struct vmbus_channel_gpadl_header) +
sizeof(struct gpa_range) + pfncount * sizeof(u64);
msgheader = kzalloc(msgsize, GFP_KERNEL);
if (!msgheader)
goto nomem;
INIT_LIST_HEAD(&msgheader->submsglist);
msgheader->msgsize = msgsize;
gpadl_header = (struct vmbus_channel_gpadl_header *)
msgheader->msg;
gpadl_header->rangecount = 1;
gpadl_header->range_buflen = sizeof(struct gpa_range) +
pagecount * sizeof(u64);
gpadl_header->range[0].byte_offset = 0;
gpadl_header->range[0].byte_count = size;
for (i = 0; i < pfncount; i++)
gpadl_header->range[0].pfn_array[i] = pfn+i;
*msginfo = msgheader;
*messagecount = 1;
pfnsum = pfncount;
pfnleft = pagecount - pfncount;
/* how many pfns can we fit */
pfnsize = MAX_SIZE_CHANNEL_MESSAGE -
sizeof(struct vmbus_channel_gpadl_body);
pfncount = pfnsize / sizeof(u64);
/* fill in the body */
while (pfnleft) {
if (pfnleft > pfncount)
pfncurr = pfncount;
else
pfncurr = pfnleft;
msgsize = sizeof(struct vmbus_channel_msginfo) +
sizeof(struct vmbus_channel_gpadl_body) +
pfncurr * sizeof(u64);
msgbody = kzalloc(msgsize, GFP_KERNEL);
if (!msgbody) {
struct vmbus_channel_msginfo *pos = NULL;
struct vmbus_channel_msginfo *tmp = NULL;
/*
* Free up all the allocated messages.
*/
list_for_each_entry_safe(pos, tmp,
&msgheader->submsglist,
msglistentry) {
list_del(&pos->msglistentry);
kfree(pos);
}
goto nomem;
}
msgbody->msgsize = msgsize;
(*messagecount)++;
gpadl_body =
(struct vmbus_channel_gpadl_body *)msgbody->msg;
/*
* Gpadl is u32 and we are using a pointer which could
* be 64-bit
* This is governed by the guest/host protocol and
* so the hypervisor gurantees that this is ok.
*/
for (i = 0; i < pfncurr; i++)
gpadl_body->pfn[i] = pfn + pfnsum + i;
/* add to msg header */
list_add_tail(&msgbody->msglistentry,
&msgheader->submsglist);
pfnsum += pfncurr;
pfnleft -= pfncurr;
}
} else {
/* everything fits in a header */
msgsize = sizeof(struct vmbus_channel_msginfo) +
sizeof(struct vmbus_channel_gpadl_header) +
sizeof(struct gpa_range) + pagecount * sizeof(u64);
msgheader = kzalloc(msgsize, GFP_KERNEL);
if (msgheader == NULL)
goto nomem;
msgheader->msgsize = msgsize;
gpadl_header = (struct vmbus_channel_gpadl_header *)
msgheader->msg;
gpadl_header->rangecount = 1;
gpadl_header->range_buflen = sizeof(struct gpa_range) +
pagecount * sizeof(u64);
gpadl_header->range[0].byte_offset = 0;
gpadl_header->range[0].byte_count = size;
for (i = 0; i < pagecount; i++)
gpadl_header->range[0].pfn_array[i] = pfn+i;
*msginfo = msgheader;
*messagecount = 1;
}
return 0;
nomem:
kfree(msgheader);
kfree(msgbody);
return -ENOMEM;
}
/*
* vmbus_establish_gpadl - Estabish a GPADL for the specified buffer
*
* @channel: a channel
* @kbuffer: from kmalloc
* @size: page-size multiple
* @gpadl_handle: some funky thing
*/
int vmbus_establish_gpadl(struct vmbus_channel *channel, void *kbuffer,
u32 size, u32 *gpadl_handle)
{
struct vmbus_channel_gpadl_header *gpadlmsg;
struct vmbus_channel_gpadl_body *gpadl_body;
struct vmbus_channel_msginfo *msginfo = NULL;
struct vmbus_channel_msginfo *submsginfo;
u32 msgcount;
struct list_head *curr;
u32 next_gpadl_handle;
unsigned long flags;
int ret = 0;
next_gpadl_handle = atomic_read(&vmbus_connection.next_gpadl_handle);
atomic_inc(&vmbus_connection.next_gpadl_handle);
ret = create_gpadl_header(kbuffer, size, &msginfo, &msgcount);
if (ret)
return ret;
init_completion(&msginfo->waitevent);
gpadlmsg = (struct vmbus_channel_gpadl_header *)msginfo->msg;
gpadlmsg->header.msgtype = CHANNELMSG_GPADL_HEADER;
gpadlmsg->child_relid = channel->offermsg.child_relid;
gpadlmsg->gpadl = next_gpadl_handle;
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_add_tail(&msginfo->msglistentry,
&vmbus_connection.chn_msg_list);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
ret = vmbus_post_msg(gpadlmsg, msginfo->msgsize -
sizeof(*msginfo));
if (ret != 0)
goto cleanup;
if (msgcount > 1) {
list_for_each(curr, &msginfo->submsglist) {
submsginfo = (struct vmbus_channel_msginfo *)curr;
gpadl_body =
(struct vmbus_channel_gpadl_body *)submsginfo->msg;
gpadl_body->header.msgtype =
CHANNELMSG_GPADL_BODY;
gpadl_body->gpadl = next_gpadl_handle;
ret = vmbus_post_msg(gpadl_body,
submsginfo->msgsize -
sizeof(*submsginfo));
if (ret != 0)
goto cleanup;
}
}
wait_for_completion(&msginfo->waitevent);
/* At this point, we received the gpadl created msg */
*gpadl_handle = gpadlmsg->gpadl;
cleanup:
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_del(&msginfo->msglistentry);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
kfree(msginfo);
return ret;
}
EXPORT_SYMBOL_GPL(vmbus_establish_gpadl);
/*
* vmbus_teardown_gpadl -Teardown the specified GPADL handle
*/
int vmbus_teardown_gpadl(struct vmbus_channel *channel, u32 gpadl_handle)
{
struct vmbus_channel_gpadl_teardown *msg;
struct vmbus_channel_msginfo *info;
unsigned long flags;
int ret;
info = kmalloc(sizeof(*info) +
sizeof(struct vmbus_channel_gpadl_teardown), GFP_KERNEL);
if (!info)
return -ENOMEM;
init_completion(&info->waitevent);
msg = (struct vmbus_channel_gpadl_teardown *)info->msg;
msg->header.msgtype = CHANNELMSG_GPADL_TEARDOWN;
msg->child_relid = channel->offermsg.child_relid;
msg->gpadl = gpadl_handle;
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_add_tail(&info->msglistentry,
&vmbus_connection.chn_msg_list);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
ret = vmbus_post_msg(msg,
sizeof(struct vmbus_channel_gpadl_teardown));
if (ret)
goto post_msg_err;
wait_for_completion(&info->waitevent);
post_msg_err:
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
list_del(&info->msglistentry);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
kfree(info);
return ret;
}
EXPORT_SYMBOL_GPL(vmbus_teardown_gpadl);
/*
* vmbus_close - Close the specified channel
*/
void vmbus_close(struct vmbus_channel *channel)
{
struct vmbus_channel_close_channel *msg;
int ret;
unsigned long flags;
/* Stop callback and cancel the timer asap */
spin_lock_irqsave(&channel->inbound_lock, flags);
channel->onchannel_callback = NULL;
spin_unlock_irqrestore(&channel->inbound_lock, flags);
/* Send a closing message */
msg = &channel->close_msg.msg;
msg->header.msgtype = CHANNELMSG_CLOSECHANNEL;
msg->child_relid = channel->offermsg.child_relid;
ret = vmbus_post_msg(msg, sizeof(struct vmbus_channel_close_channel));
if (ret) {
pr_err("Close failed: close post msg return is %d\n", ret);
/*
* If we failed to post the close msg,
* it is perhaps better to leak memory.
*/
return;
}
/* Tear down the gpadl for the channel's ring buffer */
if (channel->ringbuffer_gpadlhandle) {
ret = vmbus_teardown_gpadl(channel,
channel->ringbuffer_gpadlhandle);
if (ret) {
pr_err("Close failed: teardown gpadl return %d\n", ret);
/*
* If we failed to teardown gpadl,
* it is perhaps better to leak memory.
*/
return;
}
}
/* Cleanup the ring buffers for this channel */
hv_ringbuffer_cleanup(&channel->outbound);
hv_ringbuffer_cleanup(&channel->inbound);
free_pages((unsigned long)channel->ringbuffer_pages,
get_order(channel->ringbuffer_pagecount * PAGE_SIZE));
}
EXPORT_SYMBOL_GPL(vmbus_close);
/**
* vmbus_sendpacket() - Send the specified buffer on the given channel
* @channel: Pointer to vmbus_channel structure.
* @buffer: Pointer to the buffer you want to receive the data into.
* @bufferlen: Maximum size of what the the buffer will hold
* @requestid: Identifier of the request
* @type: Type of packet that is being send e.g. negotiate, time
* packet etc.
*
* Sends data in @buffer directly to hyper-v via the vmbus
* This will send the data unparsed to hyper-v.
*
* Mainly used by Hyper-V drivers.
*/
int vmbus_sendpacket(struct vmbus_channel *channel, const void *buffer,
u32 bufferlen, u64 requestid,
enum vmbus_packet_type type, u32 flags)
{
struct vmpacket_descriptor desc;
u32 packetlen = sizeof(struct vmpacket_descriptor) + bufferlen;
u32 packetlen_aligned = ALIGN(packetlen, sizeof(u64));
struct scatterlist bufferlist[3];
u64 aligned_data = 0;
int ret;
/* Setup the descriptor */
desc.type = type; /* VmbusPacketTypeDataInBand; */
desc.flags = flags; /* VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED; */
/* in 8-bytes granularity */
desc.offset8 = sizeof(struct vmpacket_descriptor) >> 3;
desc.len8 = (u16)(packetlen_aligned >> 3);
desc.trans_id = requestid;
sg_init_table(bufferlist, 3);
sg_set_buf(&bufferlist[0], &desc, sizeof(struct vmpacket_descriptor));
sg_set_buf(&bufferlist[1], buffer, bufferlen);
sg_set_buf(&bufferlist[2], &aligned_data,
packetlen_aligned - packetlen);
ret = hv_ringbuffer_write(&channel->outbound, bufferlist, 3);
if (ret == 0 && !hv_get_ringbuffer_interrupt_mask(&channel->outbound))
vmbus_setevent(channel);
return ret;
}
EXPORT_SYMBOL(vmbus_sendpacket);
/*
* vmbus_sendpacket_pagebuffer - Send a range of single-page buffer
* packets using a GPADL Direct packet type.
*/
int vmbus_sendpacket_pagebuffer(struct vmbus_channel *channel,
struct hv_page_buffer pagebuffers[],
u32 pagecount, void *buffer, u32 bufferlen,
u64 requestid)
{
int ret;
int i;
struct vmbus_channel_packet_page_buffer desc;
u32 descsize;
u32 packetlen;
u32 packetlen_aligned;
struct scatterlist bufferlist[3];
u64 aligned_data = 0;
if (pagecount > MAX_PAGE_BUFFER_COUNT)
return -EINVAL;
/*
* Adjust the size down since vmbus_channel_packet_page_buffer is the
* largest size we support
*/
descsize = sizeof(struct vmbus_channel_packet_page_buffer) -
((MAX_PAGE_BUFFER_COUNT - pagecount) *
sizeof(struct hv_page_buffer));
packetlen = descsize + bufferlen;
packetlen_aligned = ALIGN(packetlen, sizeof(u64));
/* Setup the descriptor */
desc.type = VM_PKT_DATA_USING_GPA_DIRECT;
desc.flags = VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED;
desc.dataoffset8 = descsize >> 3; /* in 8-bytes grandularity */
desc.length8 = (u16)(packetlen_aligned >> 3);
desc.transactionid = requestid;
desc.rangecount = pagecount;
for (i = 0; i < pagecount; i++) {
desc.range[i].len = pagebuffers[i].len;
desc.range[i].offset = pagebuffers[i].offset;
desc.range[i].pfn = pagebuffers[i].pfn;
}
sg_init_table(bufferlist, 3);
sg_set_buf(&bufferlist[0], &desc, descsize);
sg_set_buf(&bufferlist[1], buffer, bufferlen);
sg_set_buf(&bufferlist[2], &aligned_data,
packetlen_aligned - packetlen);
ret = hv_ringbuffer_write(&channel->outbound, bufferlist, 3);
if (ret == 0 && !hv_get_ringbuffer_interrupt_mask(&channel->outbound))
vmbus_setevent(channel);
return ret;
}
EXPORT_SYMBOL_GPL(vmbus_sendpacket_pagebuffer);
/*
* vmbus_sendpacket_multipagebuffer - Send a multi-page buffer packet
* using a GPADL Direct packet type.
*/
int vmbus_sendpacket_multipagebuffer(struct vmbus_channel *channel,
struct hv_multipage_buffer *multi_pagebuffer,
void *buffer, u32 bufferlen, u64 requestid)
{
int ret;
struct vmbus_channel_packet_multipage_buffer desc;
u32 descsize;
u32 packetlen;
u32 packetlen_aligned;
struct scatterlist bufferlist[3];
u64 aligned_data = 0;
u32 pfncount = NUM_PAGES_SPANNED(multi_pagebuffer->offset,
multi_pagebuffer->len);
if ((pfncount < 0) || (pfncount > MAX_MULTIPAGE_BUFFER_COUNT))
return -EINVAL;
/*
* Adjust the size down since vmbus_channel_packet_multipage_buffer is
* the largest size we support
*/
descsize = sizeof(struct vmbus_channel_packet_multipage_buffer) -
((MAX_MULTIPAGE_BUFFER_COUNT - pfncount) *
sizeof(u64));
packetlen = descsize + bufferlen;
packetlen_aligned = ALIGN(packetlen, sizeof(u64));
/* Setup the descriptor */
desc.type = VM_PKT_DATA_USING_GPA_DIRECT;
desc.flags = VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED;
desc.dataoffset8 = descsize >> 3; /* in 8-bytes grandularity */
desc.length8 = (u16)(packetlen_aligned >> 3);
desc.transactionid = requestid;
desc.rangecount = 1;
desc.range.len = multi_pagebuffer->len;
desc.range.offset = multi_pagebuffer->offset;
memcpy(desc.range.pfn_array, multi_pagebuffer->pfn_array,
pfncount * sizeof(u64));
sg_init_table(bufferlist, 3);
sg_set_buf(&bufferlist[0], &desc, descsize);
sg_set_buf(&bufferlist[1], buffer, bufferlen);
sg_set_buf(&bufferlist[2], &aligned_data,
packetlen_aligned - packetlen);
ret = hv_ringbuffer_write(&channel->outbound, bufferlist, 3);
if (ret == 0 && !hv_get_ringbuffer_interrupt_mask(&channel->outbound))
vmbus_setevent(channel);
return ret;
}
EXPORT_SYMBOL_GPL(vmbus_sendpacket_multipagebuffer);
/**
* vmbus_recvpacket() - Retrieve the user packet on the specified channel
* @channel: Pointer to vmbus_channel structure.
* @buffer: Pointer to the buffer you want to receive the data into.
* @bufferlen: Maximum size of what the the buffer will hold
* @buffer_actual_len: The actual size of the data after it was received
* @requestid: Identifier of the request
*
* Receives directly from the hyper-v vmbus and puts the data it received
* into Buffer. This will receive the data unparsed from hyper-v.
*
* Mainly used by Hyper-V drivers.
*/
int vmbus_recvpacket(struct vmbus_channel *channel, void *buffer,
u32 bufferlen, u32 *buffer_actual_len, u64 *requestid)
{
struct vmpacket_descriptor desc;
u32 packetlen;
u32 userlen;
int ret;
*buffer_actual_len = 0;
*requestid = 0;
ret = hv_ringbuffer_peek(&channel->inbound, &desc,
sizeof(struct vmpacket_descriptor));
if (ret != 0)
return 0;
packetlen = desc.len8 << 3;
userlen = packetlen - (desc.offset8 << 3);
*buffer_actual_len = userlen;
if (userlen > bufferlen) {
pr_err("Buffer too small - got %d needs %d\n",
bufferlen, userlen);
return -ETOOSMALL;
}
*requestid = desc.trans_id;
/* Copy over the packet to the user buffer */
ret = hv_ringbuffer_read(&channel->inbound, buffer, userlen,
(desc.offset8 << 3));
return 0;
}
EXPORT_SYMBOL(vmbus_recvpacket);
/*
* vmbus_recvpacket_raw - Retrieve the raw packet on the specified channel
*/
int vmbus_recvpacket_raw(struct vmbus_channel *channel, void *buffer,
u32 bufferlen, u32 *buffer_actual_len,
u64 *requestid)
{
struct vmpacket_descriptor desc;
u32 packetlen;
u32 userlen;
int ret;
*buffer_actual_len = 0;
*requestid = 0;
ret = hv_ringbuffer_peek(&channel->inbound, &desc,
sizeof(struct vmpacket_descriptor));
if (ret != 0)
return 0;
packetlen = desc.len8 << 3;
userlen = packetlen - (desc.offset8 << 3);
*buffer_actual_len = packetlen;
if (packetlen > bufferlen) {
pr_err("Buffer too small - needed %d bytes but "
"got space for only %d bytes\n",
packetlen, bufferlen);
return -ENOBUFS;
}
*requestid = desc.trans_id;
/* Copy over the entire packet to the user buffer */
ret = hv_ringbuffer_read(&channel->inbound, buffer, packetlen, 0);
return 0;
}
EXPORT_SYMBOL_GPL(vmbus_recvpacket_raw);
| gpl-2.0 |
KimLemon/AKL-Kernel | drivers/mmc/core/debugfs.c | 239 | 8209 | /*
* Debugfs support for hosts and cards
*
* Copyright (C) 2008 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/moduleparam.h>
#include <linux/export.h>
#include <linux/debugfs.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/stat.h>
#include <linux/fault-inject.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include "core.h"
#include "mmc_ops.h"
#ifdef CONFIG_FAIL_MMC_REQUEST
static DECLARE_FAULT_ATTR(fail_default_attr);
static char *fail_request;
module_param(fail_request, charp, 0);
#endif /* CONFIG_FAIL_MMC_REQUEST */
/* The debugfs functions are optimized away when CONFIG_DEBUG_FS isn't set. */
static int mmc_ios_show(struct seq_file *s, void *data)
{
static const char *vdd_str[] = {
[8] = "2.0",
[9] = "2.1",
[10] = "2.2",
[11] = "2.3",
[12] = "2.4",
[13] = "2.5",
[14] = "2.6",
[15] = "2.7",
[16] = "2.8",
[17] = "2.9",
[18] = "3.0",
[19] = "3.1",
[20] = "3.2",
[21] = "3.3",
[22] = "3.4",
[23] = "3.5",
[24] = "3.6",
};
struct mmc_host *host = s->private;
struct mmc_ios *ios = &host->ios;
const char *str;
seq_printf(s, "clock:\t\t%u Hz\n", ios->clock);
if (host->actual_clock)
seq_printf(s, "actual clock:\t%u Hz\n", host->actual_clock);
seq_printf(s, "vdd:\t\t%u ", ios->vdd);
if ((1 << ios->vdd) & MMC_VDD_165_195)
seq_printf(s, "(1.65 - 1.95 V)\n");
else if (ios->vdd < (ARRAY_SIZE(vdd_str) - 1)
&& vdd_str[ios->vdd] && vdd_str[ios->vdd + 1])
seq_printf(s, "(%s ~ %s V)\n", vdd_str[ios->vdd],
vdd_str[ios->vdd + 1]);
else
seq_printf(s, "(invalid)\n");
switch (ios->bus_mode) {
case MMC_BUSMODE_OPENDRAIN:
str = "open drain";
break;
case MMC_BUSMODE_PUSHPULL:
str = "push-pull";
break;
default:
str = "invalid";
break;
}
seq_printf(s, "bus mode:\t%u (%s)\n", ios->bus_mode, str);
switch (ios->chip_select) {
case MMC_CS_DONTCARE:
str = "don't care";
break;
case MMC_CS_HIGH:
str = "active high";
break;
case MMC_CS_LOW:
str = "active low";
break;
default:
str = "invalid";
break;
}
seq_printf(s, "chip select:\t%u (%s)\n", ios->chip_select, str);
switch (ios->power_mode) {
case MMC_POWER_OFF:
str = "off";
break;
case MMC_POWER_UP:
str = "up";
break;
case MMC_POWER_ON:
str = "on";
break;
default:
str = "invalid";
break;
}
seq_printf(s, "power mode:\t%u (%s)\n", ios->power_mode, str);
seq_printf(s, "bus width:\t%u (%u bits)\n",
ios->bus_width, 1 << ios->bus_width);
switch (ios->timing) {
case MMC_TIMING_LEGACY:
str = "legacy";
break;
case MMC_TIMING_MMC_HS:
str = "mmc high-speed";
break;
case MMC_TIMING_SD_HS:
str = "sd high-speed";
break;
case MMC_TIMING_UHS_SDR50:
str = "sd uhs SDR50";
break;
case MMC_TIMING_UHS_SDR104:
str = "sd uhs SDR104";
break;
case MMC_TIMING_UHS_DDR50:
str = "sd uhs DDR50";
break;
case MMC_TIMING_MMC_HS200:
str = "mmc high-speed SDR200";
break;
default:
str = "invalid";
break;
}
seq_printf(s, "timing spec:\t%u (%s)\n", ios->timing, str);
switch (ios->signal_voltage) {
case MMC_SIGNAL_VOLTAGE_330:
str = "3.30 V";
break;
case MMC_SIGNAL_VOLTAGE_180:
str = "1.80 V";
break;
case MMC_SIGNAL_VOLTAGE_120:
str = "1.20 V";
break;
default:
str = "invalid";
break;
}
seq_printf(s, "signal voltage:\t%u (%s)\n", ios->chip_select, str);
return 0;
}
static int mmc_ios_open(struct inode *inode, struct file *file)
{
return single_open(file, mmc_ios_show, inode->i_private);
}
static const struct file_operations mmc_ios_fops = {
.open = mmc_ios_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int mmc_clock_opt_get(void *data, u64 *val)
{
struct mmc_host *host = data;
*val = host->ios.clock;
return 0;
}
static int mmc_clock_opt_set(void *data, u64 val)
{
struct mmc_host *host = data;
/* We need this check due to input value is u64 */
if (val > host->f_max)
return -EINVAL;
mmc_claim_host(host);
mmc_set_clock(host, (unsigned int) val);
mmc_release_host(host);
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(mmc_clock_fops, mmc_clock_opt_get, mmc_clock_opt_set,
"%llu\n");
void mmc_add_host_debugfs(struct mmc_host *host)
{
struct dentry *root;
root = debugfs_create_dir(mmc_hostname(host), NULL);
if (IS_ERR(root))
/* Don't complain -- debugfs just isn't enabled */
return;
if (!root)
/* Complain -- debugfs is enabled, but it failed to
* create the directory. */
goto err_root;
host->debugfs_root = root;
if (!debugfs_create_file("ios", S_IRUSR, root, host, &mmc_ios_fops))
goto err_node;
if (!debugfs_create_file("clock", S_IRUSR | S_IWUSR, root, host,
&mmc_clock_fops))
goto err_node;
#ifdef CONFIG_MMC_CLKGATE
if (!debugfs_create_u32("clk_delay", (S_IRUSR | S_IWUSR),
root, &host->clk_delay))
goto err_node;
#endif
#ifdef CONFIG_FAIL_MMC_REQUEST
if (fail_request)
setup_fault_attr(&fail_default_attr, fail_request);
host->fail_mmc_request = fail_default_attr;
if (IS_ERR(fault_create_debugfs_attr("fail_mmc_request",
root,
&host->fail_mmc_request)))
goto err_node;
#endif
return;
err_node:
debugfs_remove_recursive(root);
host->debugfs_root = NULL;
err_root:
dev_err(&host->class_dev, "failed to initialize debugfs\n");
}
void mmc_remove_host_debugfs(struct mmc_host *host)
{
debugfs_remove_recursive(host->debugfs_root);
}
static int mmc_dbg_card_status_get(void *data, u64 *val)
{
struct mmc_card *card = data;
u32 status;
int ret;
mmc_claim_host(card->host);
ret = mmc_send_status(data, &status, 0);
if (!ret)
*val = status;
mmc_release_host(card->host);
return ret;
}
DEFINE_SIMPLE_ATTRIBUTE(mmc_dbg_card_status_fops, mmc_dbg_card_status_get,
NULL, "%08llx\n");
#define EXT_CSD_STR_LEN 1025
static int mmc_ext_csd_open(struct inode *inode, struct file *filp)
{
struct mmc_card *card = inode->i_private;
char *buf;
ssize_t n = 0;
u8 *ext_csd;
int err, i;
buf = kmalloc(EXT_CSD_STR_LEN + 1, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ext_csd = kmalloc(512, GFP_KERNEL);
if (!ext_csd) {
err = -ENOMEM;
goto out_free;
}
mmc_claim_host(card->host);
err = mmc_send_ext_csd(card, ext_csd);
mmc_release_host(card->host);
if (err)
goto out_free;
for (i = 0; i < 512; i++)
n += sprintf(buf + n, "%02x", ext_csd[i]);
n += sprintf(buf + n, "\n");
BUG_ON(n != EXT_CSD_STR_LEN);
filp->private_data = buf;
kfree(ext_csd);
return 0;
out_free:
kfree(buf);
kfree(ext_csd);
return err;
}
static ssize_t mmc_ext_csd_read(struct file *filp, char __user *ubuf,
size_t cnt, loff_t *ppos)
{
char *buf = filp->private_data;
return simple_read_from_buffer(ubuf, cnt, ppos,
buf, EXT_CSD_STR_LEN);
}
static int mmc_ext_csd_release(struct inode *inode, struct file *file)
{
kfree(file->private_data);
return 0;
}
static const struct file_operations mmc_dbg_ext_csd_fops = {
.open = mmc_ext_csd_open,
.read = mmc_ext_csd_read,
.release = mmc_ext_csd_release,
.llseek = default_llseek,
};
void mmc_add_card_debugfs(struct mmc_card *card)
{
struct mmc_host *host = card->host;
struct dentry *root;
if (!host->debugfs_root)
return;
root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root);
if (IS_ERR(root))
/* Don't complain -- debugfs just isn't enabled */
return;
if (!root)
/* Complain -- debugfs is enabled, but it failed to
* create the directory. */
goto err;
card->debugfs_root = root;
if (!debugfs_create_x32("state", S_IRUSR, root, &card->state))
goto err;
if (mmc_card_mmc(card) || mmc_card_sd(card))
if (!debugfs_create_file("status", S_IRUSR, root, card,
&mmc_dbg_card_status_fops))
goto err;
if (mmc_card_mmc(card))
if (!debugfs_create_file("ext_csd", S_IRUSR, root, card,
&mmc_dbg_ext_csd_fops))
goto err;
return;
err:
debugfs_remove_recursive(root);
card->debugfs_root = NULL;
dev_err(&card->dev, "failed to initialize debugfs\n");
}
void mmc_remove_card_debugfs(struct mmc_card *card)
{
debugfs_remove_recursive(card->debugfs_root);
}
| gpl-2.0 |
tezet/kernel-milestone2 | arch/x86/kernel/x8664_ksyms_64.c | 495 | 1427 | /* Exports for assembly files.
All C exports should go in the respective C files. */
#include <linux/module.h>
#include <linux/smp.h>
#include <net/checksum.h>
#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/uaccess.h>
#include <asm/desc.h>
#include <asm/ftrace.h>
#ifdef CONFIG_FUNCTION_TRACER
/* mcount is defined in assembly */
EXPORT_SYMBOL(mcount);
#endif
EXPORT_SYMBOL(kernel_thread);
EXPORT_SYMBOL(__get_user_1);
EXPORT_SYMBOL(__get_user_2);
EXPORT_SYMBOL(__get_user_4);
EXPORT_SYMBOL(__get_user_8);
EXPORT_SYMBOL(__put_user_1);
EXPORT_SYMBOL(__put_user_2);
EXPORT_SYMBOL(__put_user_4);
EXPORT_SYMBOL(__put_user_8);
EXPORT_SYMBOL(copy_user_generic);
EXPORT_SYMBOL(__copy_user_nocache);
EXPORT_SYMBOL(copy_from_user);
EXPORT_SYMBOL(copy_to_user);
EXPORT_SYMBOL(__copy_from_user_inatomic);
EXPORT_SYMBOL(copy_page);
EXPORT_SYMBOL(clear_page);
EXPORT_SYMBOL(csum_partial);
/*
* Export string functions. We normally rely on gcc builtin for most of these,
* but gcc sometimes decides not to inline them.
*/
#undef memcpy
#undef memset
#undef memmove
extern void *memset(void *, int, __kernel_size_t);
extern void *memcpy(void *, const void *, __kernel_size_t);
extern void *__memcpy(void *, const void *, __kernel_size_t);
EXPORT_SYMBOL(memset);
EXPORT_SYMBOL(memcpy);
EXPORT_SYMBOL(__memcpy);
EXPORT_SYMBOL(empty_zero_page);
EXPORT_SYMBOL(init_level4_pgt);
EXPORT_SYMBOL(load_gs_index);
| gpl-2.0 |
edgestorm/lu3700-cm-gin | drivers/char/nozomi.c | 751 | 50250 | /*
* nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
*
* Written by: Ulf Jakobsson,
* Jan Åkerfeldt,
* Stefan Thomasson,
*
* Maintained by: Paul Hardwick (p.hardwick@option.com)
*
* Patches:
* Locking code changes for Vodafone by Sphere Systems Ltd,
* Andrew Bird (ajb@spheresystems.co.uk )
* & Phil Sanderson
*
* Source has been ported from an implementation made by Filip Aben @ Option
*
* --------------------------------------------------------------------------
*
* Copyright (c) 2005,2006 Option Wireless Sweden AB
* Copyright (c) 2006 Sphere Systems Ltd
* Copyright (c) 2006 Option Wireless n/v
* All rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* --------------------------------------------------------------------------
*/
/* Enable this to have a lot of debug printouts */
#define DEBUG
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/tty_flip.h>
#include <linux/sched.h>
#include <linux/serial.h>
#include <linux/interrupt.h>
#include <linux/kmod.h>
#include <linux/init.h>
#include <linux/kfifo.h>
#include <linux/uaccess.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <linux/delay.h>
#define VERSION_STRING DRIVER_DESC " 2.1d (build date: " \
__DATE__ " " __TIME__ ")"
/* Macros definitions */
/* Default debug printout level */
#define NOZOMI_DEBUG_LEVEL 0x00
#define P_BUF_SIZE 128
#define NFO(_err_flag_, args...) \
do { \
char tmp[P_BUF_SIZE]; \
snprintf(tmp, sizeof(tmp), ##args); \
printk(_err_flag_ "[%d] %s(): %s\n", __LINE__, \
__func__, tmp); \
} while (0)
#define DBG1(args...) D_(0x01, ##args)
#define DBG2(args...) D_(0x02, ##args)
#define DBG3(args...) D_(0x04, ##args)
#define DBG4(args...) D_(0x08, ##args)
#define DBG5(args...) D_(0x10, ##args)
#define DBG6(args...) D_(0x20, ##args)
#define DBG7(args...) D_(0x40, ##args)
#define DBG8(args...) D_(0x80, ##args)
#ifdef DEBUG
/* Do we need this settable at runtime? */
static int debug = NOZOMI_DEBUG_LEVEL;
#define D(lvl, args...) do \
{if (lvl & debug) NFO(KERN_DEBUG, ##args); } \
while (0)
#define D_(lvl, args...) D(lvl, ##args)
/* These printouts are always printed */
#else
static int debug;
#define D_(lvl, args...)
#endif
/* TODO: rewrite to optimize macros... */
#define TMP_BUF_MAX 256
#define DUMP(buf__,len__) \
do { \
char tbuf[TMP_BUF_MAX] = {0};\
if (len__ > 1) {\
snprintf(tbuf, len__ > TMP_BUF_MAX ? TMP_BUF_MAX : len__, "%s", buf__);\
if (tbuf[len__-2] == '\r') {\
tbuf[len__-2] = 'r';\
} \
DBG1("SENDING: '%s' (%d+n)", tbuf, len__);\
} else {\
DBG1("SENDING: '%s' (%d)", tbuf, len__);\
} \
} while (0)
/* Defines */
#define NOZOMI_NAME "nozomi"
#define NOZOMI_NAME_TTY "nozomi_tty"
#define DRIVER_DESC "Nozomi driver"
#define NTTY_TTY_MAXMINORS 256
#define NTTY_FIFO_BUFFER_SIZE 8192
/* Must be power of 2 */
#define FIFO_BUFFER_SIZE_UL 8192
/* Size of tmp send buffer to card */
#define SEND_BUF_MAX 1024
#define RECEIVE_BUF_MAX 4
#define R_IIR 0x0000 /* Interrupt Identity Register */
#define R_FCR 0x0000 /* Flow Control Register */
#define R_IER 0x0004 /* Interrupt Enable Register */
#define CONFIG_MAGIC 0xEFEFFEFE
#define TOGGLE_VALID 0x0000
/* Definition of interrupt tokens */
#define MDM_DL1 0x0001
#define MDM_UL1 0x0002
#define MDM_DL2 0x0004
#define MDM_UL2 0x0008
#define DIAG_DL1 0x0010
#define DIAG_DL2 0x0020
#define DIAG_UL 0x0040
#define APP1_DL 0x0080
#define APP1_UL 0x0100
#define APP2_DL 0x0200
#define APP2_UL 0x0400
#define CTRL_DL 0x0800
#define CTRL_UL 0x1000
#define RESET 0x8000
#define MDM_DL (MDM_DL1 | MDM_DL2)
#define MDM_UL (MDM_UL1 | MDM_UL2)
#define DIAG_DL (DIAG_DL1 | DIAG_DL2)
/* modem signal definition */
#define CTRL_DSR 0x0001
#define CTRL_DCD 0x0002
#define CTRL_RI 0x0004
#define CTRL_CTS 0x0008
#define CTRL_DTR 0x0001
#define CTRL_RTS 0x0002
#define MAX_PORT 4
#define NOZOMI_MAX_PORTS 5
#define NOZOMI_MAX_CARDS (NTTY_TTY_MAXMINORS / MAX_PORT)
/* Type definitions */
/*
* There are two types of nozomi cards,
* one with 2048 memory and with 8192 memory
*/
enum card_type {
F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
};
/* Initialization states a card can be in */
enum card_state {
NOZOMI_STATE_UKNOWN = 0,
NOZOMI_STATE_ENABLED = 1, /* pci device enabled */
NOZOMI_STATE_ALLOCATED = 2, /* config setup done */
NOZOMI_STATE_READY = 3, /* flowcontrols received */
};
/* Two different toggle channels exist */
enum channel_type {
CH_A = 0,
CH_B = 1,
};
/* Port definition for the card regarding flow control */
enum ctrl_port_type {
CTRL_CMD = 0,
CTRL_MDM = 1,
CTRL_DIAG = 2,
CTRL_APP1 = 3,
CTRL_APP2 = 4,
CTRL_ERROR = -1,
};
/* Ports that the nozomi has */
enum port_type {
PORT_MDM = 0,
PORT_DIAG = 1,
PORT_APP1 = 2,
PORT_APP2 = 3,
PORT_CTRL = 4,
PORT_ERROR = -1,
};
#ifdef __BIG_ENDIAN
/* Big endian */
struct toggles {
unsigned int enabled:5; /*
* Toggle fields are valid if enabled is 0,
* else A-channels must always be used.
*/
unsigned int diag_dl:1;
unsigned int mdm_dl:1;
unsigned int mdm_ul:1;
} __attribute__ ((packed));
/* Configuration table to read at startup of card */
/* Is for now only needed during initialization phase */
struct config_table {
u32 signature;
u16 product_information;
u16 version;
u8 pad3[3];
struct toggles toggle;
u8 pad1[4];
u16 dl_mdm_len1; /*
* If this is 64, it can hold
* 60 bytes + 4 that is length field
*/
u16 dl_start;
u16 dl_diag_len1;
u16 dl_mdm_len2; /*
* If this is 64, it can hold
* 60 bytes + 4 that is length field
*/
u16 dl_app1_len;
u16 dl_diag_len2;
u16 dl_ctrl_len;
u16 dl_app2_len;
u8 pad2[16];
u16 ul_mdm_len1;
u16 ul_start;
u16 ul_diag_len;
u16 ul_mdm_len2;
u16 ul_app1_len;
u16 ul_app2_len;
u16 ul_ctrl_len;
} __attribute__ ((packed));
/* This stores all control downlink flags */
struct ctrl_dl {
u8 port;
unsigned int reserved:4;
unsigned int CTS:1;
unsigned int RI:1;
unsigned int DCD:1;
unsigned int DSR:1;
} __attribute__ ((packed));
/* This stores all control uplink flags */
struct ctrl_ul {
u8 port;
unsigned int reserved:6;
unsigned int RTS:1;
unsigned int DTR:1;
} __attribute__ ((packed));
#else
/* Little endian */
/* This represents the toggle information */
struct toggles {
unsigned int mdm_ul:1;
unsigned int mdm_dl:1;
unsigned int diag_dl:1;
unsigned int enabled:5; /*
* Toggle fields are valid if enabled is 0,
* else A-channels must always be used.
*/
} __attribute__ ((packed));
/* Configuration table to read at startup of card */
struct config_table {
u32 signature;
u16 version;
u16 product_information;
struct toggles toggle;
u8 pad1[7];
u16 dl_start;
u16 dl_mdm_len1; /*
* If this is 64, it can hold
* 60 bytes + 4 that is length field
*/
u16 dl_mdm_len2;
u16 dl_diag_len1;
u16 dl_diag_len2;
u16 dl_app1_len;
u16 dl_app2_len;
u16 dl_ctrl_len;
u8 pad2[16];
u16 ul_start;
u16 ul_mdm_len2;
u16 ul_mdm_len1;
u16 ul_diag_len;
u16 ul_app1_len;
u16 ul_app2_len;
u16 ul_ctrl_len;
} __attribute__ ((packed));
/* This stores all control downlink flags */
struct ctrl_dl {
unsigned int DSR:1;
unsigned int DCD:1;
unsigned int RI:1;
unsigned int CTS:1;
unsigned int reserverd:4;
u8 port;
} __attribute__ ((packed));
/* This stores all control uplink flags */
struct ctrl_ul {
unsigned int DTR:1;
unsigned int RTS:1;
unsigned int reserved:6;
u8 port;
} __attribute__ ((packed));
#endif
/* This holds all information that is needed regarding a port */
struct port {
struct tty_port port;
u8 update_flow_control;
struct ctrl_ul ctrl_ul;
struct ctrl_dl ctrl_dl;
struct kfifo fifo_ul;
void __iomem *dl_addr[2];
u32 dl_size[2];
u8 toggle_dl;
void __iomem *ul_addr[2];
u32 ul_size[2];
u8 toggle_ul;
u16 token_dl;
/* mutex to ensure one access patch to this port */
struct mutex tty_sem;
wait_queue_head_t tty_wait;
struct async_icount tty_icount;
struct nozomi *dc;
};
/* Private data one for each card in the system */
struct nozomi {
void __iomem *base_addr;
unsigned long flip;
/* Pointers to registers */
void __iomem *reg_iir;
void __iomem *reg_fcr;
void __iomem *reg_ier;
u16 last_ier;
enum card_type card_type;
struct config_table config_table; /* Configuration table */
struct pci_dev *pdev;
struct port port[NOZOMI_MAX_PORTS];
u8 *send_buf;
spinlock_t spin_mutex; /* secures access to registers and tty */
unsigned int index_start;
enum card_state state;
u32 open_ttys;
};
/* This is a data packet that is read or written to/from card */
struct buffer {
u32 size; /* size is the length of the data buffer */
u8 *data;
} __attribute__ ((packed));
/* Global variables */
static const struct pci_device_id nozomi_pci_tbl[] __devinitconst = {
{PCI_DEVICE(0x1931, 0x000c)}, /* Nozomi HSDPA */
{},
};
MODULE_DEVICE_TABLE(pci, nozomi_pci_tbl);
static struct nozomi *ndevs[NOZOMI_MAX_CARDS];
static struct tty_driver *ntty_driver;
static const struct tty_port_operations noz_tty_port_ops;
/*
* find card by tty_index
*/
static inline struct nozomi *get_dc_by_tty(const struct tty_struct *tty)
{
return tty ? ndevs[tty->index / MAX_PORT] : NULL;
}
static inline struct port *get_port_by_tty(const struct tty_struct *tty)
{
struct nozomi *ndev = get_dc_by_tty(tty);
return ndev ? &ndev->port[tty->index % MAX_PORT] : NULL;
}
/*
* TODO:
* -Optimize
* -Rewrite cleaner
*/
static void read_mem32(u32 *buf, const void __iomem *mem_addr_start,
u32 size_bytes)
{
u32 i = 0;
const u32 __iomem *ptr = mem_addr_start;
u16 *buf16;
if (unlikely(!ptr || !buf))
goto out;
/* shortcut for extremely often used cases */
switch (size_bytes) {
case 2: /* 2 bytes */
buf16 = (u16 *) buf;
*buf16 = __le16_to_cpu(readw(ptr));
goto out;
break;
case 4: /* 4 bytes */
*(buf) = __le32_to_cpu(readl(ptr));
goto out;
break;
}
while (i < size_bytes) {
if (size_bytes - i == 2) {
/* Handle 2 bytes in the end */
buf16 = (u16 *) buf;
*(buf16) = __le16_to_cpu(readw(ptr));
i += 2;
} else {
/* Read 4 bytes */
*(buf) = __le32_to_cpu(readl(ptr));
i += 4;
}
buf++;
ptr++;
}
out:
return;
}
/*
* TODO:
* -Optimize
* -Rewrite cleaner
*/
static u32 write_mem32(void __iomem *mem_addr_start, const u32 *buf,
u32 size_bytes)
{
u32 i = 0;
u32 __iomem *ptr = mem_addr_start;
const u16 *buf16;
if (unlikely(!ptr || !buf))
return 0;
/* shortcut for extremely often used cases */
switch (size_bytes) {
case 2: /* 2 bytes */
buf16 = (const u16 *)buf;
writew(__cpu_to_le16(*buf16), ptr);
return 2;
break;
case 1: /*
* also needs to write 4 bytes in this case
* so falling through..
*/
case 4: /* 4 bytes */
writel(__cpu_to_le32(*buf), ptr);
return 4;
break;
}
while (i < size_bytes) {
if (size_bytes - i == 2) {
/* 2 bytes */
buf16 = (const u16 *)buf;
writew(__cpu_to_le16(*buf16), ptr);
i += 2;
} else {
/* 4 bytes */
writel(__cpu_to_le32(*buf), ptr);
i += 4;
}
buf++;
ptr++;
}
return i;
}
/* Setup pointers to different channels and also setup buffer sizes. */
static void setup_memory(struct nozomi *dc)
{
void __iomem *offset = dc->base_addr + dc->config_table.dl_start;
/* The length reported is including the length field of 4 bytes,
* hence subtract with 4.
*/
const u16 buff_offset = 4;
/* Modem port dl configuration */
dc->port[PORT_MDM].dl_addr[CH_A] = offset;
dc->port[PORT_MDM].dl_addr[CH_B] =
(offset += dc->config_table.dl_mdm_len1);
dc->port[PORT_MDM].dl_size[CH_A] =
dc->config_table.dl_mdm_len1 - buff_offset;
dc->port[PORT_MDM].dl_size[CH_B] =
dc->config_table.dl_mdm_len2 - buff_offset;
/* Diag port dl configuration */
dc->port[PORT_DIAG].dl_addr[CH_A] =
(offset += dc->config_table.dl_mdm_len2);
dc->port[PORT_DIAG].dl_size[CH_A] =
dc->config_table.dl_diag_len1 - buff_offset;
dc->port[PORT_DIAG].dl_addr[CH_B] =
(offset += dc->config_table.dl_diag_len1);
dc->port[PORT_DIAG].dl_size[CH_B] =
dc->config_table.dl_diag_len2 - buff_offset;
/* App1 port dl configuration */
dc->port[PORT_APP1].dl_addr[CH_A] =
(offset += dc->config_table.dl_diag_len2);
dc->port[PORT_APP1].dl_size[CH_A] =
dc->config_table.dl_app1_len - buff_offset;
/* App2 port dl configuration */
dc->port[PORT_APP2].dl_addr[CH_A] =
(offset += dc->config_table.dl_app1_len);
dc->port[PORT_APP2].dl_size[CH_A] =
dc->config_table.dl_app2_len - buff_offset;
/* Ctrl dl configuration */
dc->port[PORT_CTRL].dl_addr[CH_A] =
(offset += dc->config_table.dl_app2_len);
dc->port[PORT_CTRL].dl_size[CH_A] =
dc->config_table.dl_ctrl_len - buff_offset;
offset = dc->base_addr + dc->config_table.ul_start;
/* Modem Port ul configuration */
dc->port[PORT_MDM].ul_addr[CH_A] = offset;
dc->port[PORT_MDM].ul_size[CH_A] =
dc->config_table.ul_mdm_len1 - buff_offset;
dc->port[PORT_MDM].ul_addr[CH_B] =
(offset += dc->config_table.ul_mdm_len1);
dc->port[PORT_MDM].ul_size[CH_B] =
dc->config_table.ul_mdm_len2 - buff_offset;
/* Diag port ul configuration */
dc->port[PORT_DIAG].ul_addr[CH_A] =
(offset += dc->config_table.ul_mdm_len2);
dc->port[PORT_DIAG].ul_size[CH_A] =
dc->config_table.ul_diag_len - buff_offset;
/* App1 port ul configuration */
dc->port[PORT_APP1].ul_addr[CH_A] =
(offset += dc->config_table.ul_diag_len);
dc->port[PORT_APP1].ul_size[CH_A] =
dc->config_table.ul_app1_len - buff_offset;
/* App2 port ul configuration */
dc->port[PORT_APP2].ul_addr[CH_A] =
(offset += dc->config_table.ul_app1_len);
dc->port[PORT_APP2].ul_size[CH_A] =
dc->config_table.ul_app2_len - buff_offset;
/* Ctrl ul configuration */
dc->port[PORT_CTRL].ul_addr[CH_A] =
(offset += dc->config_table.ul_app2_len);
dc->port[PORT_CTRL].ul_size[CH_A] =
dc->config_table.ul_ctrl_len - buff_offset;
}
/* Dump config table under initalization phase */
#ifdef DEBUG
static void dump_table(const struct nozomi *dc)
{
DBG3("signature: 0x%08X", dc->config_table.signature);
DBG3("version: 0x%04X", dc->config_table.version);
DBG3("product_information: 0x%04X", \
dc->config_table.product_information);
DBG3("toggle enabled: %d", dc->config_table.toggle.enabled);
DBG3("toggle up_mdm: %d", dc->config_table.toggle.mdm_ul);
DBG3("toggle dl_mdm: %d", dc->config_table.toggle.mdm_dl);
DBG3("toggle dl_dbg: %d", dc->config_table.toggle.diag_dl);
DBG3("dl_start: 0x%04X", dc->config_table.dl_start);
DBG3("dl_mdm_len0: 0x%04X, %d", dc->config_table.dl_mdm_len1,
dc->config_table.dl_mdm_len1);
DBG3("dl_mdm_len1: 0x%04X, %d", dc->config_table.dl_mdm_len2,
dc->config_table.dl_mdm_len2);
DBG3("dl_diag_len0: 0x%04X, %d", dc->config_table.dl_diag_len1,
dc->config_table.dl_diag_len1);
DBG3("dl_diag_len1: 0x%04X, %d", dc->config_table.dl_diag_len2,
dc->config_table.dl_diag_len2);
DBG3("dl_app1_len: 0x%04X, %d", dc->config_table.dl_app1_len,
dc->config_table.dl_app1_len);
DBG3("dl_app2_len: 0x%04X, %d", dc->config_table.dl_app2_len,
dc->config_table.dl_app2_len);
DBG3("dl_ctrl_len: 0x%04X, %d", dc->config_table.dl_ctrl_len,
dc->config_table.dl_ctrl_len);
DBG3("ul_start: 0x%04X, %d", dc->config_table.ul_start,
dc->config_table.ul_start);
DBG3("ul_mdm_len[0]: 0x%04X, %d", dc->config_table.ul_mdm_len1,
dc->config_table.ul_mdm_len1);
DBG3("ul_mdm_len[1]: 0x%04X, %d", dc->config_table.ul_mdm_len2,
dc->config_table.ul_mdm_len2);
DBG3("ul_diag_len: 0x%04X, %d", dc->config_table.ul_diag_len,
dc->config_table.ul_diag_len);
DBG3("ul_app1_len: 0x%04X, %d", dc->config_table.ul_app1_len,
dc->config_table.ul_app1_len);
DBG3("ul_app2_len: 0x%04X, %d", dc->config_table.ul_app2_len,
dc->config_table.ul_app2_len);
DBG3("ul_ctrl_len: 0x%04X, %d", dc->config_table.ul_ctrl_len,
dc->config_table.ul_ctrl_len);
}
#else
static inline void dump_table(const struct nozomi *dc) { }
#endif
/*
* Read configuration table from card under intalization phase
* Returns 1 if ok, else 0
*/
static int nozomi_read_config_table(struct nozomi *dc)
{
read_mem32((u32 *) &dc->config_table, dc->base_addr + 0,
sizeof(struct config_table));
if (dc->config_table.signature != CONFIG_MAGIC) {
dev_err(&dc->pdev->dev, "ConfigTable Bad! 0x%08X != 0x%08X\n",
dc->config_table.signature, CONFIG_MAGIC);
return 0;
}
if ((dc->config_table.version == 0)
|| (dc->config_table.toggle.enabled == TOGGLE_VALID)) {
int i;
DBG1("Second phase, configuring card");
setup_memory(dc);
dc->port[PORT_MDM].toggle_ul = dc->config_table.toggle.mdm_ul;
dc->port[PORT_MDM].toggle_dl = dc->config_table.toggle.mdm_dl;
dc->port[PORT_DIAG].toggle_dl = dc->config_table.toggle.diag_dl;
DBG1("toggle ports: MDM UL:%d MDM DL:%d, DIAG DL:%d",
dc->port[PORT_MDM].toggle_ul,
dc->port[PORT_MDM].toggle_dl, dc->port[PORT_DIAG].toggle_dl);
dump_table(dc);
for (i = PORT_MDM; i < MAX_PORT; i++) {
memset(&dc->port[i].ctrl_dl, 0, sizeof(struct ctrl_dl));
memset(&dc->port[i].ctrl_ul, 0, sizeof(struct ctrl_ul));
}
/* Enable control channel */
dc->last_ier = dc->last_ier | CTRL_DL;
writew(dc->last_ier, dc->reg_ier);
dc->state = NOZOMI_STATE_ALLOCATED;
dev_info(&dc->pdev->dev, "Initialization OK!\n");
return 1;
}
if ((dc->config_table.version > 0)
&& (dc->config_table.toggle.enabled != TOGGLE_VALID)) {
u32 offset = 0;
DBG1("First phase: pushing upload buffers, clearing download");
dev_info(&dc->pdev->dev, "Version of card: %d\n",
dc->config_table.version);
/* Here we should disable all I/O over F32. */
setup_memory(dc);
/*
* We should send ALL channel pair tokens back along
* with reset token
*/
/* push upload modem buffers */
write_mem32(dc->port[PORT_MDM].ul_addr[CH_A],
(u32 *) &offset, 4);
write_mem32(dc->port[PORT_MDM].ul_addr[CH_B],
(u32 *) &offset, 4);
writew(MDM_UL | DIAG_DL | MDM_DL, dc->reg_fcr);
DBG1("First phase done");
}
return 1;
}
/* Enable uplink interrupts */
static void enable_transmit_ul(enum port_type port, struct nozomi *dc)
{
static const u16 mask[] = {MDM_UL, DIAG_UL, APP1_UL, APP2_UL, CTRL_UL};
if (port < NOZOMI_MAX_PORTS) {
dc->last_ier |= mask[port];
writew(dc->last_ier, dc->reg_ier);
} else {
dev_err(&dc->pdev->dev, "Called with wrong port?\n");
}
}
/* Disable uplink interrupts */
static void disable_transmit_ul(enum port_type port, struct nozomi *dc)
{
static const u16 mask[] =
{~MDM_UL, ~DIAG_UL, ~APP1_UL, ~APP2_UL, ~CTRL_UL};
if (port < NOZOMI_MAX_PORTS) {
dc->last_ier &= mask[port];
writew(dc->last_ier, dc->reg_ier);
} else {
dev_err(&dc->pdev->dev, "Called with wrong port?\n");
}
}
/* Enable downlink interrupts */
static void enable_transmit_dl(enum port_type port, struct nozomi *dc)
{
static const u16 mask[] = {MDM_DL, DIAG_DL, APP1_DL, APP2_DL, CTRL_DL};
if (port < NOZOMI_MAX_PORTS) {
dc->last_ier |= mask[port];
writew(dc->last_ier, dc->reg_ier);
} else {
dev_err(&dc->pdev->dev, "Called with wrong port?\n");
}
}
/* Disable downlink interrupts */
static void disable_transmit_dl(enum port_type port, struct nozomi *dc)
{
static const u16 mask[] =
{~MDM_DL, ~DIAG_DL, ~APP1_DL, ~APP2_DL, ~CTRL_DL};
if (port < NOZOMI_MAX_PORTS) {
dc->last_ier &= mask[port];
writew(dc->last_ier, dc->reg_ier);
} else {
dev_err(&dc->pdev->dev, "Called with wrong port?\n");
}
}
/*
* Return 1 - send buffer to card and ack.
* Return 0 - don't ack, don't send buffer to card.
*/
static int send_data(enum port_type index, struct nozomi *dc)
{
u32 size = 0;
struct port *port = &dc->port[index];
const u8 toggle = port->toggle_ul;
void __iomem *addr = port->ul_addr[toggle];
const u32 ul_size = port->ul_size[toggle];
struct tty_struct *tty = tty_port_tty_get(&port->port);
/* Get data from tty and place in buf for now */
size = kfifo_out(&port->fifo_ul, dc->send_buf,
ul_size < SEND_BUF_MAX ? ul_size : SEND_BUF_MAX);
if (size == 0) {
DBG4("No more data to send, disable link:");
tty_kref_put(tty);
return 0;
}
/* DUMP(buf, size); */
/* Write length + data */
write_mem32(addr, (u32 *) &size, 4);
write_mem32(addr + 4, (u32 *) dc->send_buf, size);
if (tty)
tty_wakeup(tty);
tty_kref_put(tty);
return 1;
}
/* If all data has been read, return 1, else 0 */
static int receive_data(enum port_type index, struct nozomi *dc)
{
u8 buf[RECEIVE_BUF_MAX] = { 0 };
int size;
u32 offset = 4;
struct port *port = &dc->port[index];
void __iomem *addr = port->dl_addr[port->toggle_dl];
struct tty_struct *tty = tty_port_tty_get(&port->port);
int i, ret;
if (unlikely(!tty)) {
DBG1("tty not open for port: %d?", index);
return 1;
}
read_mem32((u32 *) &size, addr, 4);
/* DBG1( "%d bytes port: %d", size, index); */
if (test_bit(TTY_THROTTLED, &tty->flags)) {
DBG1("No room in tty, don't read data, don't ack interrupt, "
"disable interrupt");
/* disable interrupt in downlink... */
disable_transmit_dl(index, dc);
ret = 0;
goto put;
}
if (unlikely(size == 0)) {
dev_err(&dc->pdev->dev, "size == 0?\n");
ret = 1;
goto put;
}
while (size > 0) {
read_mem32((u32 *) buf, addr + offset, RECEIVE_BUF_MAX);
if (size == 1) {
tty_insert_flip_char(tty, buf[0], TTY_NORMAL);
size = 0;
} else if (size < RECEIVE_BUF_MAX) {
size -= tty_insert_flip_string(tty, (char *) buf, size);
} else {
i = tty_insert_flip_string(tty, \
(char *) buf, RECEIVE_BUF_MAX);
size -= i;
offset += i;
}
}
set_bit(index, &dc->flip);
ret = 1;
put:
tty_kref_put(tty);
return ret;
}
/* Debug for interrupts */
#ifdef DEBUG
static char *interrupt2str(u16 interrupt)
{
static char buf[TMP_BUF_MAX];
char *p = buf;
interrupt & MDM_DL1 ? p += snprintf(p, TMP_BUF_MAX, "MDM_DL1 ") : NULL;
interrupt & MDM_DL2 ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"MDM_DL2 ") : NULL;
interrupt & MDM_UL1 ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"MDM_UL1 ") : NULL;
interrupt & MDM_UL2 ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"MDM_UL2 ") : NULL;
interrupt & DIAG_DL1 ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"DIAG_DL1 ") : NULL;
interrupt & DIAG_DL2 ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"DIAG_DL2 ") : NULL;
interrupt & DIAG_UL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"DIAG_UL ") : NULL;
interrupt & APP1_DL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"APP1_DL ") : NULL;
interrupt & APP2_DL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"APP2_DL ") : NULL;
interrupt & APP1_UL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"APP1_UL ") : NULL;
interrupt & APP2_UL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"APP2_UL ") : NULL;
interrupt & CTRL_DL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"CTRL_DL ") : NULL;
interrupt & CTRL_UL ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"CTRL_UL ") : NULL;
interrupt & RESET ? p += snprintf(p, TMP_BUF_MAX - (p - buf),
"RESET ") : NULL;
return buf;
}
#endif
/*
* Receive flow control
* Return 1 - If ok, else 0
*/
static int receive_flow_control(struct nozomi *dc)
{
enum port_type port = PORT_MDM;
struct ctrl_dl ctrl_dl;
struct ctrl_dl old_ctrl;
u16 enable_ier = 0;
read_mem32((u32 *) &ctrl_dl, dc->port[PORT_CTRL].dl_addr[CH_A], 2);
switch (ctrl_dl.port) {
case CTRL_CMD:
DBG1("The Base Band sends this value as a response to a "
"request for IMSI detach sent over the control "
"channel uplink (see section 7.6.1).");
break;
case CTRL_MDM:
port = PORT_MDM;
enable_ier = MDM_DL;
break;
case CTRL_DIAG:
port = PORT_DIAG;
enable_ier = DIAG_DL;
break;
case CTRL_APP1:
port = PORT_APP1;
enable_ier = APP1_DL;
break;
case CTRL_APP2:
port = PORT_APP2;
enable_ier = APP2_DL;
if (dc->state == NOZOMI_STATE_ALLOCATED) {
/*
* After card initialization the flow control
* received for APP2 is always the last
*/
dc->state = NOZOMI_STATE_READY;
dev_info(&dc->pdev->dev, "Device READY!\n");
}
break;
default:
dev_err(&dc->pdev->dev,
"ERROR: flow control received for non-existing port\n");
return 0;
};
DBG1("0x%04X->0x%04X", *((u16 *)&dc->port[port].ctrl_dl),
*((u16 *)&ctrl_dl));
old_ctrl = dc->port[port].ctrl_dl;
dc->port[port].ctrl_dl = ctrl_dl;
if (old_ctrl.CTS == 1 && ctrl_dl.CTS == 0) {
DBG1("Disable interrupt (0x%04X) on port: %d",
enable_ier, port);
disable_transmit_ul(port, dc);
} else if (old_ctrl.CTS == 0 && ctrl_dl.CTS == 1) {
if (kfifo_len(&dc->port[port].fifo_ul)) {
DBG1("Enable interrupt (0x%04X) on port: %d",
enable_ier, port);
DBG1("Data in buffer [%d], enable transmit! ",
kfifo_len(&dc->port[port].fifo_ul));
enable_transmit_ul(port, dc);
} else {
DBG1("No data in buffer...");
}
}
if (*(u16 *)&old_ctrl == *(u16 *)&ctrl_dl) {
DBG1(" No change in mctrl");
return 1;
}
/* Update statistics */
if (old_ctrl.CTS != ctrl_dl.CTS)
dc->port[port].tty_icount.cts++;
if (old_ctrl.DSR != ctrl_dl.DSR)
dc->port[port].tty_icount.dsr++;
if (old_ctrl.RI != ctrl_dl.RI)
dc->port[port].tty_icount.rng++;
if (old_ctrl.DCD != ctrl_dl.DCD)
dc->port[port].tty_icount.dcd++;
wake_up_interruptible(&dc->port[port].tty_wait);
DBG1("port: %d DCD(%d), CTS(%d), RI(%d), DSR(%d)",
port,
dc->port[port].tty_icount.dcd, dc->port[port].tty_icount.cts,
dc->port[port].tty_icount.rng, dc->port[port].tty_icount.dsr);
return 1;
}
static enum ctrl_port_type port2ctrl(enum port_type port,
const struct nozomi *dc)
{
switch (port) {
case PORT_MDM:
return CTRL_MDM;
case PORT_DIAG:
return CTRL_DIAG;
case PORT_APP1:
return CTRL_APP1;
case PORT_APP2:
return CTRL_APP2;
default:
dev_err(&dc->pdev->dev,
"ERROR: send flow control " \
"received for non-existing port\n");
};
return CTRL_ERROR;
}
/*
* Send flow control, can only update one channel at a time
* Return 0 - If we have updated all flow control
* Return 1 - If we need to update more flow control, ack current enable more
*/
static int send_flow_control(struct nozomi *dc)
{
u32 i, more_flow_control_to_be_updated = 0;
u16 *ctrl;
for (i = PORT_MDM; i < MAX_PORT; i++) {
if (dc->port[i].update_flow_control) {
if (more_flow_control_to_be_updated) {
/* We have more flow control to be updated */
return 1;
}
dc->port[i].ctrl_ul.port = port2ctrl(i, dc);
ctrl = (u16 *)&dc->port[i].ctrl_ul;
write_mem32(dc->port[PORT_CTRL].ul_addr[0], \
(u32 *) ctrl, 2);
dc->port[i].update_flow_control = 0;
more_flow_control_to_be_updated = 1;
}
}
return 0;
}
/*
* Handle downlink data, ports that are handled are modem and diagnostics
* Return 1 - ok
* Return 0 - toggle fields are out of sync
*/
static int handle_data_dl(struct nozomi *dc, enum port_type port, u8 *toggle,
u16 read_iir, u16 mask1, u16 mask2)
{
if (*toggle == 0 && read_iir & mask1) {
if (receive_data(port, dc)) {
writew(mask1, dc->reg_fcr);
*toggle = !(*toggle);
}
if (read_iir & mask2) {
if (receive_data(port, dc)) {
writew(mask2, dc->reg_fcr);
*toggle = !(*toggle);
}
}
} else if (*toggle == 1 && read_iir & mask2) {
if (receive_data(port, dc)) {
writew(mask2, dc->reg_fcr);
*toggle = !(*toggle);
}
if (read_iir & mask1) {
if (receive_data(port, dc)) {
writew(mask1, dc->reg_fcr);
*toggle = !(*toggle);
}
}
} else {
dev_err(&dc->pdev->dev, "port out of sync!, toggle:%d\n",
*toggle);
return 0;
}
return 1;
}
/*
* Handle uplink data, this is currently for the modem port
* Return 1 - ok
* Return 0 - toggle field are out of sync
*/
static int handle_data_ul(struct nozomi *dc, enum port_type port, u16 read_iir)
{
u8 *toggle = &(dc->port[port].toggle_ul);
if (*toggle == 0 && read_iir & MDM_UL1) {
dc->last_ier &= ~MDM_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(port, dc)) {
writew(MDM_UL1, dc->reg_fcr);
dc->last_ier = dc->last_ier | MDM_UL;
writew(dc->last_ier, dc->reg_ier);
*toggle = !*toggle;
}
if (read_iir & MDM_UL2) {
dc->last_ier &= ~MDM_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(port, dc)) {
writew(MDM_UL2, dc->reg_fcr);
dc->last_ier = dc->last_ier | MDM_UL;
writew(dc->last_ier, dc->reg_ier);
*toggle = !*toggle;
}
}
} else if (*toggle == 1 && read_iir & MDM_UL2) {
dc->last_ier &= ~MDM_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(port, dc)) {
writew(MDM_UL2, dc->reg_fcr);
dc->last_ier = dc->last_ier | MDM_UL;
writew(dc->last_ier, dc->reg_ier);
*toggle = !*toggle;
}
if (read_iir & MDM_UL1) {
dc->last_ier &= ~MDM_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(port, dc)) {
writew(MDM_UL1, dc->reg_fcr);
dc->last_ier = dc->last_ier | MDM_UL;
writew(dc->last_ier, dc->reg_ier);
*toggle = !*toggle;
}
}
} else {
writew(read_iir & MDM_UL, dc->reg_fcr);
dev_err(&dc->pdev->dev, "port out of sync!\n");
return 0;
}
return 1;
}
static irqreturn_t interrupt_handler(int irq, void *dev_id)
{
struct nozomi *dc = dev_id;
unsigned int a;
u16 read_iir;
if (!dc)
return IRQ_NONE;
spin_lock(&dc->spin_mutex);
read_iir = readw(dc->reg_iir);
/* Card removed */
if (read_iir == (u16)-1)
goto none;
/*
* Just handle interrupt enabled in IER
* (by masking with dc->last_ier)
*/
read_iir &= dc->last_ier;
if (read_iir == 0)
goto none;
DBG4("%s irq:0x%04X, prev:0x%04X", interrupt2str(read_iir), read_iir,
dc->last_ier);
if (read_iir & RESET) {
if (unlikely(!nozomi_read_config_table(dc))) {
dc->last_ier = 0x0;
writew(dc->last_ier, dc->reg_ier);
dev_err(&dc->pdev->dev, "Could not read status from "
"card, we should disable interface\n");
} else {
writew(RESET, dc->reg_fcr);
}
/* No more useful info if this was the reset interrupt. */
goto exit_handler;
}
if (read_iir & CTRL_UL) {
DBG1("CTRL_UL");
dc->last_ier &= ~CTRL_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_flow_control(dc)) {
writew(CTRL_UL, dc->reg_fcr);
dc->last_ier = dc->last_ier | CTRL_UL;
writew(dc->last_ier, dc->reg_ier);
}
}
if (read_iir & CTRL_DL) {
receive_flow_control(dc);
writew(CTRL_DL, dc->reg_fcr);
}
if (read_iir & MDM_DL) {
if (!handle_data_dl(dc, PORT_MDM,
&(dc->port[PORT_MDM].toggle_dl), read_iir,
MDM_DL1, MDM_DL2)) {
dev_err(&dc->pdev->dev, "MDM_DL out of sync!\n");
goto exit_handler;
}
}
if (read_iir & MDM_UL) {
if (!handle_data_ul(dc, PORT_MDM, read_iir)) {
dev_err(&dc->pdev->dev, "MDM_UL out of sync!\n");
goto exit_handler;
}
}
if (read_iir & DIAG_DL) {
if (!handle_data_dl(dc, PORT_DIAG,
&(dc->port[PORT_DIAG].toggle_dl), read_iir,
DIAG_DL1, DIAG_DL2)) {
dev_err(&dc->pdev->dev, "DIAG_DL out of sync!\n");
goto exit_handler;
}
}
if (read_iir & DIAG_UL) {
dc->last_ier &= ~DIAG_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(PORT_DIAG, dc)) {
writew(DIAG_UL, dc->reg_fcr);
dc->last_ier = dc->last_ier | DIAG_UL;
writew(dc->last_ier, dc->reg_ier);
}
}
if (read_iir & APP1_DL) {
if (receive_data(PORT_APP1, dc))
writew(APP1_DL, dc->reg_fcr);
}
if (read_iir & APP1_UL) {
dc->last_ier &= ~APP1_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(PORT_APP1, dc)) {
writew(APP1_UL, dc->reg_fcr);
dc->last_ier = dc->last_ier | APP1_UL;
writew(dc->last_ier, dc->reg_ier);
}
}
if (read_iir & APP2_DL) {
if (receive_data(PORT_APP2, dc))
writew(APP2_DL, dc->reg_fcr);
}
if (read_iir & APP2_UL) {
dc->last_ier &= ~APP2_UL;
writew(dc->last_ier, dc->reg_ier);
if (send_data(PORT_APP2, dc)) {
writew(APP2_UL, dc->reg_fcr);
dc->last_ier = dc->last_ier | APP2_UL;
writew(dc->last_ier, dc->reg_ier);
}
}
exit_handler:
spin_unlock(&dc->spin_mutex);
for (a = 0; a < NOZOMI_MAX_PORTS; a++) {
struct tty_struct *tty;
if (test_and_clear_bit(a, &dc->flip)) {
tty = tty_port_tty_get(&dc->port[a].port);
if (tty)
tty_flip_buffer_push(tty);
tty_kref_put(tty);
}
}
return IRQ_HANDLED;
none:
spin_unlock(&dc->spin_mutex);
return IRQ_NONE;
}
static void nozomi_get_card_type(struct nozomi *dc)
{
int i;
u32 size = 0;
for (i = 0; i < 6; i++)
size += pci_resource_len(dc->pdev, i);
/* Assume card type F32_8 if no match */
dc->card_type = size == 2048 ? F32_2 : F32_8;
dev_info(&dc->pdev->dev, "Card type is: %d\n", dc->card_type);
}
static void nozomi_setup_private_data(struct nozomi *dc)
{
void __iomem *offset = dc->base_addr + dc->card_type / 2;
unsigned int i;
dc->reg_fcr = (void __iomem *)(offset + R_FCR);
dc->reg_iir = (void __iomem *)(offset + R_IIR);
dc->reg_ier = (void __iomem *)(offset + R_IER);
dc->last_ier = 0;
dc->flip = 0;
dc->port[PORT_MDM].token_dl = MDM_DL;
dc->port[PORT_DIAG].token_dl = DIAG_DL;
dc->port[PORT_APP1].token_dl = APP1_DL;
dc->port[PORT_APP2].token_dl = APP2_DL;
for (i = 0; i < MAX_PORT; i++)
init_waitqueue_head(&dc->port[i].tty_wait);
}
static ssize_t card_type_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
const struct nozomi *dc = pci_get_drvdata(to_pci_dev(dev));
return sprintf(buf, "%d\n", dc->card_type);
}
static DEVICE_ATTR(card_type, S_IRUGO, card_type_show, NULL);
static ssize_t open_ttys_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
const struct nozomi *dc = pci_get_drvdata(to_pci_dev(dev));
return sprintf(buf, "%u\n", dc->open_ttys);
}
static DEVICE_ATTR(open_ttys, S_IRUGO, open_ttys_show, NULL);
static void make_sysfs_files(struct nozomi *dc)
{
if (device_create_file(&dc->pdev->dev, &dev_attr_card_type))
dev_err(&dc->pdev->dev,
"Could not create sysfs file for card_type\n");
if (device_create_file(&dc->pdev->dev, &dev_attr_open_ttys))
dev_err(&dc->pdev->dev,
"Could not create sysfs file for open_ttys\n");
}
static void remove_sysfs_files(struct nozomi *dc)
{
device_remove_file(&dc->pdev->dev, &dev_attr_card_type);
device_remove_file(&dc->pdev->dev, &dev_attr_open_ttys);
}
/* Allocate memory for one device */
static int __devinit nozomi_card_init(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
resource_size_t start;
int ret;
struct nozomi *dc = NULL;
int ndev_idx;
int i;
dev_dbg(&pdev->dev, "Init, new card found\n");
for (ndev_idx = 0; ndev_idx < ARRAY_SIZE(ndevs); ndev_idx++)
if (!ndevs[ndev_idx])
break;
if (ndev_idx >= ARRAY_SIZE(ndevs)) {
dev_err(&pdev->dev, "no free tty range for this card left\n");
ret = -EIO;
goto err;
}
dc = kzalloc(sizeof(struct nozomi), GFP_KERNEL);
if (unlikely(!dc)) {
dev_err(&pdev->dev, "Could not allocate memory\n");
ret = -ENOMEM;
goto err_free;
}
dc->pdev = pdev;
ret = pci_enable_device(dc->pdev);
if (ret) {
dev_err(&pdev->dev, "Failed to enable PCI Device\n");
goto err_free;
}
ret = pci_request_regions(dc->pdev, NOZOMI_NAME);
if (ret) {
dev_err(&pdev->dev, "I/O address 0x%04x already in use\n",
(int) /* nozomi_private.io_addr */ 0);
goto err_disable_device;
}
start = pci_resource_start(dc->pdev, 0);
if (start == 0) {
dev_err(&pdev->dev, "No I/O address for card detected\n");
ret = -ENODEV;
goto err_rel_regs;
}
/* Find out what card type it is */
nozomi_get_card_type(dc);
dc->base_addr = ioremap_nocache(start, dc->card_type);
if (!dc->base_addr) {
dev_err(&pdev->dev, "Unable to map card MMIO\n");
ret = -ENODEV;
goto err_rel_regs;
}
dc->send_buf = kmalloc(SEND_BUF_MAX, GFP_KERNEL);
if (!dc->send_buf) {
dev_err(&pdev->dev, "Could not allocate send buffer?\n");
ret = -ENOMEM;
goto err_free_sbuf;
}
for (i = PORT_MDM; i < MAX_PORT; i++) {
if (kfifo_alloc(&dc->port[i].fifo_ul,
FIFO_BUFFER_SIZE_UL, GFP_ATOMIC)) {
dev_err(&pdev->dev,
"Could not allocate kfifo buffer\n");
ret = -ENOMEM;
goto err_free_kfifo;
}
}
spin_lock_init(&dc->spin_mutex);
nozomi_setup_private_data(dc);
/* Disable all interrupts */
dc->last_ier = 0;
writew(dc->last_ier, dc->reg_ier);
ret = request_irq(pdev->irq, &interrupt_handler, IRQF_SHARED,
NOZOMI_NAME, dc);
if (unlikely(ret)) {
dev_err(&pdev->dev, "can't request irq %d\n", pdev->irq);
goto err_free_kfifo;
}
DBG1("base_addr: %p", dc->base_addr);
make_sysfs_files(dc);
dc->index_start = ndev_idx * MAX_PORT;
ndevs[ndev_idx] = dc;
pci_set_drvdata(pdev, dc);
/* Enable RESET interrupt */
dc->last_ier = RESET;
iowrite16(dc->last_ier, dc->reg_ier);
dc->state = NOZOMI_STATE_ENABLED;
for (i = 0; i < MAX_PORT; i++) {
struct device *tty_dev;
struct port *port = &dc->port[i];
port->dc = dc;
mutex_init(&port->tty_sem);
tty_port_init(&port->port);
port->port.ops = &noz_tty_port_ops;
tty_dev = tty_register_device(ntty_driver, dc->index_start + i,
&pdev->dev);
if (IS_ERR(tty_dev)) {
ret = PTR_ERR(tty_dev);
dev_err(&pdev->dev, "Could not allocate tty?\n");
goto err_free_tty;
}
}
return 0;
err_free_tty:
for (i = dc->index_start; i < dc->index_start + MAX_PORT; ++i)
tty_unregister_device(ntty_driver, i);
err_free_kfifo:
for (i = 0; i < MAX_PORT; i++)
kfifo_free(&dc->port[i].fifo_ul);
err_free_sbuf:
kfree(dc->send_buf);
iounmap(dc->base_addr);
err_rel_regs:
pci_release_regions(pdev);
err_disable_device:
pci_disable_device(pdev);
err_free:
kfree(dc);
err:
return ret;
}
static void __devexit tty_exit(struct nozomi *dc)
{
unsigned int i;
DBG1(" ");
flush_scheduled_work();
for (i = 0; i < MAX_PORT; ++i) {
struct tty_struct *tty = tty_port_tty_get(&dc->port[i].port);
if (tty && list_empty(&tty->hangup_work.entry))
tty_hangup(tty);
tty_kref_put(tty);
}
/* Racy below - surely should wait for scheduled work to be done or
complete off a hangup method ? */
while (dc->open_ttys)
msleep(1);
for (i = dc->index_start; i < dc->index_start + MAX_PORT; ++i)
tty_unregister_device(ntty_driver, i);
}
/* Deallocate memory for one device */
static void __devexit nozomi_card_exit(struct pci_dev *pdev)
{
int i;
struct ctrl_ul ctrl;
struct nozomi *dc = pci_get_drvdata(pdev);
/* Disable all interrupts */
dc->last_ier = 0;
writew(dc->last_ier, dc->reg_ier);
tty_exit(dc);
/* Send 0x0001, command card to resend the reset token. */
/* This is to get the reset when the module is reloaded. */
ctrl.port = 0x00;
ctrl.reserved = 0;
ctrl.RTS = 0;
ctrl.DTR = 1;
DBG1("sending flow control 0x%04X", *((u16 *)&ctrl));
/* Setup dc->reg addresses to we can use defines here */
write_mem32(dc->port[PORT_CTRL].ul_addr[0], (u32 *)&ctrl, 2);
writew(CTRL_UL, dc->reg_fcr); /* push the token to the card. */
remove_sysfs_files(dc);
free_irq(pdev->irq, dc);
for (i = 0; i < MAX_PORT; i++)
kfifo_free(&dc->port[i].fifo_ul);
kfree(dc->send_buf);
iounmap(dc->base_addr);
pci_release_regions(pdev);
pci_disable_device(pdev);
ndevs[dc->index_start / MAX_PORT] = NULL;
kfree(dc);
}
static void set_rts(const struct tty_struct *tty, int rts)
{
struct port *port = get_port_by_tty(tty);
port->ctrl_ul.RTS = rts;
port->update_flow_control = 1;
enable_transmit_ul(PORT_CTRL, get_dc_by_tty(tty));
}
static void set_dtr(const struct tty_struct *tty, int dtr)
{
struct port *port = get_port_by_tty(tty);
DBG1("SETTING DTR index: %d, dtr: %d", tty->index, dtr);
port->ctrl_ul.DTR = dtr;
port->update_flow_control = 1;
enable_transmit_ul(PORT_CTRL, get_dc_by_tty(tty));
}
/*
* ----------------------------------------------------------------------------
* TTY code
* ----------------------------------------------------------------------------
*/
static int ntty_install(struct tty_driver *driver, struct tty_struct *tty)
{
struct port *port = get_port_by_tty(tty);
struct nozomi *dc = get_dc_by_tty(tty);
int ret;
if (!port || !dc || dc->state != NOZOMI_STATE_READY)
return -ENODEV;
ret = tty_init_termios(tty);
if (ret == 0) {
tty_driver_kref_get(driver);
tty->count++;
tty->driver_data = port;
driver->ttys[tty->index] = tty;
}
return ret;
}
static void ntty_cleanup(struct tty_struct *tty)
{
tty->driver_data = NULL;
}
static int ntty_activate(struct tty_port *tport, struct tty_struct *tty)
{
struct port *port = container_of(tport, struct port, port);
struct nozomi *dc = port->dc;
unsigned long flags;
DBG1("open: %d", port->token_dl);
spin_lock_irqsave(&dc->spin_mutex, flags);
dc->last_ier = dc->last_ier | port->token_dl;
writew(dc->last_ier, dc->reg_ier);
dc->open_ttys++;
spin_unlock_irqrestore(&dc->spin_mutex, flags);
printk("noz: activated %d: %p\n", tty->index, tport);
return 0;
}
static int ntty_open(struct tty_struct *tty, struct file *filp)
{
struct port *port = tty->driver_data;
return tty_port_open(&port->port, tty, filp);
}
static void ntty_shutdown(struct tty_port *tport)
{
struct port *port = container_of(tport, struct port, port);
struct nozomi *dc = port->dc;
unsigned long flags;
DBG1("close: %d", port->token_dl);
spin_lock_irqsave(&dc->spin_mutex, flags);
dc->last_ier &= ~(port->token_dl);
writew(dc->last_ier, dc->reg_ier);
dc->open_ttys--;
spin_unlock_irqrestore(&dc->spin_mutex, flags);
printk("noz: shutdown %p\n", tport);
}
static void ntty_close(struct tty_struct *tty, struct file *filp)
{
struct port *port = tty->driver_data;
if (port)
tty_port_close(&port->port, tty, filp);
}
static void ntty_hangup(struct tty_struct *tty)
{
struct port *port = tty->driver_data;
tty_port_hangup(&port->port);
}
/*
* called when the userspace process writes to the tty (/dev/noz*).
* Data is inserted into a fifo, which is then read and transfered to the modem.
*/
static int ntty_write(struct tty_struct *tty, const unsigned char *buffer,
int count)
{
int rval = -EINVAL;
struct nozomi *dc = get_dc_by_tty(tty);
struct port *port = tty->driver_data;
unsigned long flags;
/* DBG1( "WRITEx: %d, index = %d", count, index); */
if (!dc || !port)
return -ENODEV;
mutex_lock(&port->tty_sem);
if (unlikely(!port->port.count)) {
DBG1(" ");
goto exit;
}
rval = kfifo_in(&port->fifo_ul, (unsigned char *)buffer, count);
/* notify card */
if (unlikely(dc == NULL)) {
DBG1("No device context?");
goto exit;
}
spin_lock_irqsave(&dc->spin_mutex, flags);
/* CTS is only valid on the modem channel */
if (port == &(dc->port[PORT_MDM])) {
if (port->ctrl_dl.CTS) {
DBG4("Enable interrupt");
enable_transmit_ul(tty->index % MAX_PORT, dc);
} else {
dev_err(&dc->pdev->dev,
"CTS not active on modem port?\n");
}
} else {
enable_transmit_ul(tty->index % MAX_PORT, dc);
}
spin_unlock_irqrestore(&dc->spin_mutex, flags);
exit:
mutex_unlock(&port->tty_sem);
return rval;
}
/*
* Calculate how much is left in device
* This method is called by the upper tty layer.
* #according to sources N_TTY.c it expects a value >= 0 and
* does not check for negative values.
*
* If the port is unplugged report lots of room and let the bits
* dribble away so we don't block anything.
*/
static int ntty_write_room(struct tty_struct *tty)
{
struct port *port = tty->driver_data;
int room = 4096;
const struct nozomi *dc = get_dc_by_tty(tty);
if (dc) {
mutex_lock(&port->tty_sem);
if (port->port.count)
room = port->fifo_ul.size -
kfifo_len(&port->fifo_ul);
mutex_unlock(&port->tty_sem);
}
return room;
}
/* Gets io control parameters */
static int ntty_tiocmget(struct tty_struct *tty, struct file *file)
{
const struct port *port = tty->driver_data;
const struct ctrl_dl *ctrl_dl = &port->ctrl_dl;
const struct ctrl_ul *ctrl_ul = &port->ctrl_ul;
/* Note: these could change under us but it is not clear this
matters if so */
return (ctrl_ul->RTS ? TIOCM_RTS : 0) |
(ctrl_ul->DTR ? TIOCM_DTR : 0) |
(ctrl_dl->DCD ? TIOCM_CAR : 0) |
(ctrl_dl->RI ? TIOCM_RNG : 0) |
(ctrl_dl->DSR ? TIOCM_DSR : 0) |
(ctrl_dl->CTS ? TIOCM_CTS : 0);
}
/* Sets io controls parameters */
static int ntty_tiocmset(struct tty_struct *tty, struct file *file,
unsigned int set, unsigned int clear)
{
struct nozomi *dc = get_dc_by_tty(tty);
unsigned long flags;
spin_lock_irqsave(&dc->spin_mutex, flags);
if (set & TIOCM_RTS)
set_rts(tty, 1);
else if (clear & TIOCM_RTS)
set_rts(tty, 0);
if (set & TIOCM_DTR)
set_dtr(tty, 1);
else if (clear & TIOCM_DTR)
set_dtr(tty, 0);
spin_unlock_irqrestore(&dc->spin_mutex, flags);
return 0;
}
static int ntty_cflags_changed(struct port *port, unsigned long flags,
struct async_icount *cprev)
{
const struct async_icount cnow = port->tty_icount;
int ret;
ret = ((flags & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
((flags & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
((flags & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
((flags & TIOCM_CTS) && (cnow.cts != cprev->cts));
*cprev = cnow;
return ret;
}
static int ntty_ioctl_tiocgicount(struct port *port, void __user *argp)
{
const struct async_icount cnow = port->tty_icount;
struct serial_icounter_struct icount;
icount.cts = cnow.cts;
icount.dsr = cnow.dsr;
icount.rng = cnow.rng;
icount.dcd = cnow.dcd;
icount.rx = cnow.rx;
icount.tx = cnow.tx;
icount.frame = cnow.frame;
icount.overrun = cnow.overrun;
icount.parity = cnow.parity;
icount.brk = cnow.brk;
icount.buf_overrun = cnow.buf_overrun;
return copy_to_user(argp, &icount, sizeof(icount)) ? -EFAULT : 0;
}
static int ntty_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg)
{
struct port *port = tty->driver_data;
void __user *argp = (void __user *)arg;
int rval = -ENOIOCTLCMD;
DBG1("******** IOCTL, cmd: %d", cmd);
switch (cmd) {
case TIOCMIWAIT: {
struct async_icount cprev = port->tty_icount;
rval = wait_event_interruptible(port->tty_wait,
ntty_cflags_changed(port, arg, &cprev));
break;
} case TIOCGICOUNT:
rval = ntty_ioctl_tiocgicount(port, argp);
break;
default:
DBG1("ERR: 0x%08X, %d", cmd, cmd);
break;
};
return rval;
}
/*
* Called by the upper tty layer when tty buffers are ready
* to receive data again after a call to throttle.
*/
static void ntty_unthrottle(struct tty_struct *tty)
{
struct nozomi *dc = get_dc_by_tty(tty);
unsigned long flags;
DBG1("UNTHROTTLE");
spin_lock_irqsave(&dc->spin_mutex, flags);
enable_transmit_dl(tty->index % MAX_PORT, dc);
set_rts(tty, 1);
spin_unlock_irqrestore(&dc->spin_mutex, flags);
}
/*
* Called by the upper tty layer when the tty buffers are almost full.
* The driver should stop send more data.
*/
static void ntty_throttle(struct tty_struct *tty)
{
struct nozomi *dc = get_dc_by_tty(tty);
unsigned long flags;
DBG1("THROTTLE");
spin_lock_irqsave(&dc->spin_mutex, flags);
set_rts(tty, 0);
spin_unlock_irqrestore(&dc->spin_mutex, flags);
}
/* Returns number of chars in buffer, called by tty layer */
static s32 ntty_chars_in_buffer(struct tty_struct *tty)
{
struct port *port = tty->driver_data;
struct nozomi *dc = get_dc_by_tty(tty);
s32 rval = 0;
if (unlikely(!dc || !port)) {
goto exit_in_buffer;
}
if (unlikely(!port->port.count)) {
dev_err(&dc->pdev->dev, "No tty open?\n");
goto exit_in_buffer;
}
rval = kfifo_len(&port->fifo_ul);
exit_in_buffer:
return rval;
}
static const struct tty_port_operations noz_tty_port_ops = {
.activate = ntty_activate,
.shutdown = ntty_shutdown,
};
static const struct tty_operations tty_ops = {
.ioctl = ntty_ioctl,
.open = ntty_open,
.close = ntty_close,
.hangup = ntty_hangup,
.write = ntty_write,
.write_room = ntty_write_room,
.unthrottle = ntty_unthrottle,
.throttle = ntty_throttle,
.chars_in_buffer = ntty_chars_in_buffer,
.tiocmget = ntty_tiocmget,
.tiocmset = ntty_tiocmset,
.install = ntty_install,
.cleanup = ntty_cleanup,
};
/* Module initialization */
static struct pci_driver nozomi_driver = {
.name = NOZOMI_NAME,
.id_table = nozomi_pci_tbl,
.probe = nozomi_card_init,
.remove = __devexit_p(nozomi_card_exit),
};
static __init int nozomi_init(void)
{
int ret;
printk(KERN_INFO "Initializing %s\n", VERSION_STRING);
ntty_driver = alloc_tty_driver(NTTY_TTY_MAXMINORS);
if (!ntty_driver)
return -ENOMEM;
ntty_driver->owner = THIS_MODULE;
ntty_driver->driver_name = NOZOMI_NAME_TTY;
ntty_driver->name = "noz";
ntty_driver->major = 0;
ntty_driver->type = TTY_DRIVER_TYPE_SERIAL;
ntty_driver->subtype = SERIAL_TYPE_NORMAL;
ntty_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
ntty_driver->init_termios = tty_std_termios;
ntty_driver->init_termios.c_cflag = B115200 | CS8 | CREAD | \
HUPCL | CLOCAL;
ntty_driver->init_termios.c_ispeed = 115200;
ntty_driver->init_termios.c_ospeed = 115200;
tty_set_operations(ntty_driver, &tty_ops);
ret = tty_register_driver(ntty_driver);
if (ret) {
printk(KERN_ERR "Nozomi: failed to register ntty driver\n");
goto free_tty;
}
ret = pci_register_driver(&nozomi_driver);
if (ret) {
printk(KERN_ERR "Nozomi: can't register pci driver\n");
goto unr_tty;
}
return 0;
unr_tty:
tty_unregister_driver(ntty_driver);
free_tty:
put_tty_driver(ntty_driver);
return ret;
}
static __exit void nozomi_exit(void)
{
printk(KERN_INFO "Unloading %s\n", DRIVER_DESC);
pci_unregister_driver(&nozomi_driver);
tty_unregister_driver(ntty_driver);
put_tty_driver(ntty_driver);
}
module_init(nozomi_init);
module_exit(nozomi_exit);
module_param(debug, int, S_IRUGO | S_IWUSR);
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION(DRIVER_DESC);
| gpl-2.0 |
SerenityS/android_kernel_samsung_msm8916 | fs/lockd/svc.c | 751 | 15975 | /*
* linux/fs/lockd/svc.c
*
* This is the central lockd service.
*
* FIXME: Separate the lockd NFS server functionality from the lockd NFS
* client functionality. Oh why didn't Sun create two separate
* services in the first place?
*
* Authors: Olaf Kirch (okir@monad.swb.de)
*
* Copyright (C) 1995, 1996 Olaf Kirch <okir@monad.swb.de>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sysctl.h>
#include <linux/moduleparam.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/in.h>
#include <linux/uio.h>
#include <linux/smp.h>
#include <linux/mutex.h>
#include <linux/kthread.h>
#include <linux/freezer.h>
#include <linux/sunrpc/types.h>
#include <linux/sunrpc/stats.h>
#include <linux/sunrpc/clnt.h>
#include <linux/sunrpc/svc.h>
#include <linux/sunrpc/svcsock.h>
#include <net/ip.h>
#include <linux/lockd/lockd.h>
#include <linux/nfs.h>
#include "netns.h"
#define NLMDBG_FACILITY NLMDBG_SVC
#define LOCKD_BUFSIZE (1024 + NLMSVC_XDRSIZE)
#define ALLOWED_SIGS (sigmask(SIGKILL))
static struct svc_program nlmsvc_program;
struct nlmsvc_binding * nlmsvc_ops;
EXPORT_SYMBOL_GPL(nlmsvc_ops);
static DEFINE_MUTEX(nlmsvc_mutex);
static unsigned int nlmsvc_users;
static struct task_struct *nlmsvc_task;
static struct svc_rqst *nlmsvc_rqst;
unsigned long nlmsvc_timeout;
int lockd_net_id;
/*
* These can be set at insmod time (useful for NFS as root filesystem),
* and also changed through the sysctl interface. -- Jamie Lokier, Aug 2003
*/
static unsigned long nlm_grace_period;
static unsigned long nlm_timeout = LOCKD_DFLT_TIMEO;
static int nlm_udpport, nlm_tcpport;
/* RLIM_NOFILE defaults to 1024. That seems like a reasonable default here. */
static unsigned int nlm_max_connections = 1024;
/*
* Constants needed for the sysctl interface.
*/
static const unsigned long nlm_grace_period_min = 0;
static const unsigned long nlm_grace_period_max = 240;
static const unsigned long nlm_timeout_min = 3;
static const unsigned long nlm_timeout_max = 20;
static const int nlm_port_min = 0, nlm_port_max = 65535;
#ifdef CONFIG_SYSCTL
static struct ctl_table_header * nlm_sysctl_table;
#endif
static unsigned long get_lockd_grace_period(void)
{
/* Note: nlm_timeout should always be nonzero */
if (nlm_grace_period)
return roundup(nlm_grace_period, nlm_timeout) * HZ;
else
return nlm_timeout * 5 * HZ;
}
static void grace_ender(struct work_struct *grace)
{
struct delayed_work *dwork = container_of(grace, struct delayed_work,
work);
struct lockd_net *ln = container_of(dwork, struct lockd_net,
grace_period_end);
locks_end_grace(&ln->lockd_manager);
}
static void set_grace_period(struct net *net)
{
unsigned long grace_period = get_lockd_grace_period();
struct lockd_net *ln = net_generic(net, lockd_net_id);
locks_start_grace(net, &ln->lockd_manager);
cancel_delayed_work_sync(&ln->grace_period_end);
schedule_delayed_work(&ln->grace_period_end, grace_period);
}
static void restart_grace(void)
{
if (nlmsvc_ops) {
struct net *net = &init_net;
struct lockd_net *ln = net_generic(net, lockd_net_id);
cancel_delayed_work_sync(&ln->grace_period_end);
locks_end_grace(&ln->lockd_manager);
nlmsvc_invalidate_all();
set_grace_period(net);
}
}
/*
* This is the lockd kernel thread
*/
static int
lockd(void *vrqstp)
{
int err = 0;
struct svc_rqst *rqstp = vrqstp;
/* try_to_freeze() is called from svc_recv() */
set_freezable();
/* Allow SIGKILL to tell lockd to drop all of its locks */
allow_signal(SIGKILL);
dprintk("NFS locking service started (ver " LOCKD_VERSION ").\n");
if (!nlm_timeout)
nlm_timeout = LOCKD_DFLT_TIMEO;
nlmsvc_timeout = nlm_timeout * HZ;
/*
* The main request loop. We don't terminate until the last
* NFS mount or NFS daemon has gone away.
*/
while (!kthread_should_stop()) {
long timeout = MAX_SCHEDULE_TIMEOUT;
RPC_IFDEBUG(char buf[RPC_MAX_ADDRBUFLEN]);
/* update sv_maxconn if it has changed */
rqstp->rq_server->sv_maxconn = nlm_max_connections;
if (signalled()) {
flush_signals(current);
restart_grace();
continue;
}
timeout = nlmsvc_retry_blocked();
/*
* Find a socket with data available and call its
* recvfrom routine.
*/
err = svc_recv(rqstp, timeout);
if (err == -EAGAIN || err == -EINTR)
continue;
dprintk("lockd: request from %s\n",
svc_print_addr(rqstp, buf, sizeof(buf)));
svc_process(rqstp);
}
flush_signals(current);
if (nlmsvc_ops)
nlmsvc_invalidate_all();
nlm_shutdown_hosts();
return 0;
}
static int create_lockd_listener(struct svc_serv *serv, const char *name,
struct net *net, const int family,
const unsigned short port)
{
struct svc_xprt *xprt;
xprt = svc_find_xprt(serv, name, net, family, 0);
if (xprt == NULL)
return svc_create_xprt(serv, name, net, family, port,
SVC_SOCK_DEFAULTS);
svc_xprt_put(xprt);
return 0;
}
static int create_lockd_family(struct svc_serv *serv, struct net *net,
const int family)
{
int err;
err = create_lockd_listener(serv, "udp", net, family, nlm_udpport);
if (err < 0)
return err;
return create_lockd_listener(serv, "tcp", net, family, nlm_tcpport);
}
/*
* Ensure there are active UDP and TCP listeners for lockd.
*
* Even if we have only TCP NFS mounts and/or TCP NFSDs, some
* local services (such as rpc.statd) still require UDP, and
* some NFS servers do not yet support NLM over TCP.
*
* Returns zero if all listeners are available; otherwise a
* negative errno value is returned.
*/
static int make_socks(struct svc_serv *serv, struct net *net)
{
static int warned;
int err;
err = create_lockd_family(serv, net, PF_INET);
if (err < 0)
goto out_err;
err = create_lockd_family(serv, net, PF_INET6);
if (err < 0 && err != -EAFNOSUPPORT)
goto out_err;
warned = 0;
return 0;
out_err:
if (warned++ == 0)
printk(KERN_WARNING
"lockd_up: makesock failed, error=%d\n", err);
svc_shutdown_net(serv, net);
return err;
}
static int lockd_up_net(struct svc_serv *serv, struct net *net)
{
struct lockd_net *ln = net_generic(net, lockd_net_id);
int error;
if (ln->nlmsvc_users++)
return 0;
error = svc_bind(serv, net);
if (error)
goto err_bind;
error = make_socks(serv, net);
if (error < 0)
goto err_socks;
set_grace_period(net);
dprintk("lockd_up_net: per-net data created; net=%p\n", net);
return 0;
err_socks:
svc_rpcb_cleanup(serv, net);
err_bind:
ln->nlmsvc_users--;
return error;
}
static void lockd_down_net(struct svc_serv *serv, struct net *net)
{
struct lockd_net *ln = net_generic(net, lockd_net_id);
if (ln->nlmsvc_users) {
if (--ln->nlmsvc_users == 0) {
nlm_shutdown_hosts_net(net);
cancel_delayed_work_sync(&ln->grace_period_end);
locks_end_grace(&ln->lockd_manager);
svc_shutdown_net(serv, net);
dprintk("lockd_down_net: per-net data destroyed; net=%p\n", net);
}
} else {
printk(KERN_ERR "lockd_down_net: no users! task=%p, net=%p\n",
nlmsvc_task, net);
BUG();
}
}
static int lockd_start_svc(struct svc_serv *serv)
{
int error;
if (nlmsvc_rqst)
return 0;
/*
* Create the kernel thread and wait for it to start.
*/
nlmsvc_rqst = svc_prepare_thread(serv, &serv->sv_pools[0], NUMA_NO_NODE);
if (IS_ERR(nlmsvc_rqst)) {
error = PTR_ERR(nlmsvc_rqst);
printk(KERN_WARNING
"lockd_up: svc_rqst allocation failed, error=%d\n",
error);
goto out_rqst;
}
svc_sock_update_bufs(serv);
serv->sv_maxconn = nlm_max_connections;
nlmsvc_task = kthread_run(lockd, nlmsvc_rqst, serv->sv_name);
if (IS_ERR(nlmsvc_task)) {
error = PTR_ERR(nlmsvc_task);
printk(KERN_WARNING
"lockd_up: kthread_run failed, error=%d\n", error);
goto out_task;
}
dprintk("lockd_up: service started\n");
return 0;
out_task:
svc_exit_thread(nlmsvc_rqst);
nlmsvc_task = NULL;
out_rqst:
nlmsvc_rqst = NULL;
return error;
}
static struct svc_serv *lockd_create_svc(void)
{
struct svc_serv *serv;
/*
* Check whether we're already up and running.
*/
if (nlmsvc_rqst) {
/*
* Note: increase service usage, because later in case of error
* svc_destroy() will be called.
*/
svc_get(nlmsvc_rqst->rq_server);
return nlmsvc_rqst->rq_server;
}
/*
* Sanity check: if there's no pid,
* we should be the first user ...
*/
if (nlmsvc_users)
printk(KERN_WARNING
"lockd_up: no pid, %d users??\n", nlmsvc_users);
serv = svc_create(&nlmsvc_program, LOCKD_BUFSIZE, NULL);
if (!serv) {
printk(KERN_WARNING "lockd_up: create service failed\n");
return ERR_PTR(-ENOMEM);
}
dprintk("lockd_up: service created\n");
return serv;
}
/*
* Bring up the lockd process if it's not already up.
*/
int lockd_up(struct net *net)
{
struct svc_serv *serv;
int error;
mutex_lock(&nlmsvc_mutex);
serv = lockd_create_svc();
if (IS_ERR(serv)) {
error = PTR_ERR(serv);
goto err_create;
}
error = lockd_up_net(serv, net);
if (error < 0)
goto err_net;
error = lockd_start_svc(serv);
if (error < 0)
goto err_start;
nlmsvc_users++;
/*
* Note: svc_serv structures have an initial use count of 1,
* so we exit through here on both success and failure.
*/
err_net:
svc_destroy(serv);
err_create:
mutex_unlock(&nlmsvc_mutex);
return error;
err_start:
lockd_down_net(serv, net);
goto err_net;
}
EXPORT_SYMBOL_GPL(lockd_up);
/*
* Decrement the user count and bring down lockd if we're the last.
*/
void
lockd_down(struct net *net)
{
mutex_lock(&nlmsvc_mutex);
lockd_down_net(nlmsvc_rqst->rq_server, net);
if (nlmsvc_users) {
if (--nlmsvc_users)
goto out;
} else {
printk(KERN_ERR "lockd_down: no users! task=%p\n",
nlmsvc_task);
BUG();
}
if (!nlmsvc_task) {
printk(KERN_ERR "lockd_down: no lockd running.\n");
BUG();
}
kthread_stop(nlmsvc_task);
dprintk("lockd_down: service stopped\n");
svc_exit_thread(nlmsvc_rqst);
dprintk("lockd_down: service destroyed\n");
nlmsvc_task = NULL;
nlmsvc_rqst = NULL;
out:
mutex_unlock(&nlmsvc_mutex);
}
EXPORT_SYMBOL_GPL(lockd_down);
#ifdef CONFIG_SYSCTL
/*
* Sysctl parameters (same as module parameters, different interface).
*/
static ctl_table nlm_sysctls[] = {
{
.procname = "nlm_grace_period",
.data = &nlm_grace_period,
.maxlen = sizeof(unsigned long),
.mode = 0644,
.proc_handler = proc_doulongvec_minmax,
.extra1 = (unsigned long *) &nlm_grace_period_min,
.extra2 = (unsigned long *) &nlm_grace_period_max,
},
{
.procname = "nlm_timeout",
.data = &nlm_timeout,
.maxlen = sizeof(unsigned long),
.mode = 0644,
.proc_handler = proc_doulongvec_minmax,
.extra1 = (unsigned long *) &nlm_timeout_min,
.extra2 = (unsigned long *) &nlm_timeout_max,
},
{
.procname = "nlm_udpport",
.data = &nlm_udpport,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec_minmax,
.extra1 = (int *) &nlm_port_min,
.extra2 = (int *) &nlm_port_max,
},
{
.procname = "nlm_tcpport",
.data = &nlm_tcpport,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec_minmax,
.extra1 = (int *) &nlm_port_min,
.extra2 = (int *) &nlm_port_max,
},
{
.procname = "nsm_use_hostnames",
.data = &nsm_use_hostnames,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec,
},
{
.procname = "nsm_local_state",
.data = &nsm_local_state,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec,
},
{ }
};
static ctl_table nlm_sysctl_dir[] = {
{
.procname = "nfs",
.mode = 0555,
.child = nlm_sysctls,
},
{ }
};
static ctl_table nlm_sysctl_root[] = {
{
.procname = "fs",
.mode = 0555,
.child = nlm_sysctl_dir,
},
{ }
};
#endif /* CONFIG_SYSCTL */
/*
* Module (and sysfs) parameters.
*/
#define param_set_min_max(name, type, which_strtol, min, max) \
static int param_set_##name(const char *val, struct kernel_param *kp) \
{ \
char *endp; \
__typeof__(type) num = which_strtol(val, &endp, 0); \
if (endp == val || *endp || num < (min) || num > (max)) \
return -EINVAL; \
*((type *) kp->arg) = num; \
return 0; \
}
static inline int is_callback(u32 proc)
{
return proc == NLMPROC_GRANTED
|| proc == NLMPROC_GRANTED_MSG
|| proc == NLMPROC_TEST_RES
|| proc == NLMPROC_LOCK_RES
|| proc == NLMPROC_CANCEL_RES
|| proc == NLMPROC_UNLOCK_RES
|| proc == NLMPROC_NSM_NOTIFY;
}
static int lockd_authenticate(struct svc_rqst *rqstp)
{
rqstp->rq_client = NULL;
switch (rqstp->rq_authop->flavour) {
case RPC_AUTH_NULL:
case RPC_AUTH_UNIX:
if (rqstp->rq_proc == 0)
return SVC_OK;
if (is_callback(rqstp->rq_proc)) {
/* Leave it to individual procedures to
* call nlmsvc_lookup_host(rqstp)
*/
return SVC_OK;
}
return svc_set_client(rqstp);
}
return SVC_DENIED;
}
param_set_min_max(port, int, simple_strtol, 0, 65535)
param_set_min_max(grace_period, unsigned long, simple_strtoul,
nlm_grace_period_min, nlm_grace_period_max)
param_set_min_max(timeout, unsigned long, simple_strtoul,
nlm_timeout_min, nlm_timeout_max)
MODULE_AUTHOR("Olaf Kirch <okir@monad.swb.de>");
MODULE_DESCRIPTION("NFS file locking service version " LOCKD_VERSION ".");
MODULE_LICENSE("GPL");
module_param_call(nlm_grace_period, param_set_grace_period, param_get_ulong,
&nlm_grace_period, 0644);
module_param_call(nlm_timeout, param_set_timeout, param_get_ulong,
&nlm_timeout, 0644);
module_param_call(nlm_udpport, param_set_port, param_get_int,
&nlm_udpport, 0644);
module_param_call(nlm_tcpport, param_set_port, param_get_int,
&nlm_tcpport, 0644);
module_param(nsm_use_hostnames, bool, 0644);
module_param(nlm_max_connections, uint, 0644);
static int lockd_init_net(struct net *net)
{
struct lockd_net *ln = net_generic(net, lockd_net_id);
INIT_DELAYED_WORK(&ln->grace_period_end, grace_ender);
INIT_LIST_HEAD(&ln->grace_list);
spin_lock_init(&ln->nsm_clnt_lock);
return 0;
}
static void lockd_exit_net(struct net *net)
{
}
static struct pernet_operations lockd_net_ops = {
.init = lockd_init_net,
.exit = lockd_exit_net,
.id = &lockd_net_id,
.size = sizeof(struct lockd_net),
};
/*
* Initialising and terminating the module.
*/
static int __init init_nlm(void)
{
int err;
#ifdef CONFIG_SYSCTL
err = -ENOMEM;
nlm_sysctl_table = register_sysctl_table(nlm_sysctl_root);
if (nlm_sysctl_table == NULL)
goto err_sysctl;
#endif
err = register_pernet_subsys(&lockd_net_ops);
if (err)
goto err_pernet;
return 0;
err_pernet:
#ifdef CONFIG_SYSCTL
unregister_sysctl_table(nlm_sysctl_table);
#endif
err_sysctl:
return err;
}
static void __exit exit_nlm(void)
{
/* FIXME: delete all NLM clients */
nlm_shutdown_hosts();
unregister_pernet_subsys(&lockd_net_ops);
#ifdef CONFIG_SYSCTL
unregister_sysctl_table(nlm_sysctl_table);
#endif
}
module_init(init_nlm);
module_exit(exit_nlm);
/*
* Define NLM program and procedures
*/
static struct svc_version nlmsvc_version1 = {
.vs_vers = 1,
.vs_nproc = 17,
.vs_proc = nlmsvc_procedures,
.vs_xdrsize = NLMSVC_XDRSIZE,
};
static struct svc_version nlmsvc_version3 = {
.vs_vers = 3,
.vs_nproc = 24,
.vs_proc = nlmsvc_procedures,
.vs_xdrsize = NLMSVC_XDRSIZE,
};
#ifdef CONFIG_LOCKD_V4
static struct svc_version nlmsvc_version4 = {
.vs_vers = 4,
.vs_nproc = 24,
.vs_proc = nlmsvc_procedures4,
.vs_xdrsize = NLMSVC_XDRSIZE,
};
#endif
static struct svc_version * nlmsvc_version[] = {
[1] = &nlmsvc_version1,
[3] = &nlmsvc_version3,
#ifdef CONFIG_LOCKD_V4
[4] = &nlmsvc_version4,
#endif
};
static struct svc_stat nlmsvc_stats;
#define NLM_NRVERS ARRAY_SIZE(nlmsvc_version)
static struct svc_program nlmsvc_program = {
.pg_prog = NLM_PROGRAM, /* program number */
.pg_nvers = NLM_NRVERS, /* number of entries in nlmsvc_version */
.pg_vers = nlmsvc_version, /* version table */
.pg_name = "lockd", /* service name */
.pg_class = "nfsd", /* share authentication with nfsd */
.pg_stats = &nlmsvc_stats, /* stats table */
.pg_authenticate = &lockd_authenticate /* export authentication */
};
| gpl-2.0 |
arjen75/ics-lge-kernel-msm7x27-chick | arch/mips/jazz/jazzdma.c | 1007 | 13244 | /*
* Mips Jazz DMA controller support
* Copyright (C) 1995, 1996 by Andreas Busse
*
* NOTE: Some of the argument checking could be removed when
* things have settled down. Also, instead of returning 0xffffffff
* on failure of vdma_alloc() one could leave page #0 unused
* and return the more usual NULL pointer as logical address.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/gfp.h>
#include <asm/mipsregs.h>
#include <asm/jazz.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/dma.h>
#include <asm/jazzdma.h>
#include <asm/pgtable.h>
/*
* Set this to one to enable additional vdma debug code.
*/
#define CONF_DEBUG_VDMA 0
static VDMA_PGTBL_ENTRY *pgtbl;
static DEFINE_SPINLOCK(vdma_lock);
/*
* Debug stuff
*/
#define vdma_debug ((CONF_DEBUG_VDMA) ? debuglvl : 0)
static int debuglvl = 3;
/*
* Initialize the pagetable with a one-to-one mapping of
* the first 16 Mbytes of main memory and declare all
* entries to be unused. Using this method will at least
* allow some early device driver operations to work.
*/
static inline void vdma_pgtbl_init(void)
{
unsigned long paddr = 0;
int i;
for (i = 0; i < VDMA_PGTBL_ENTRIES; i++) {
pgtbl[i].frame = paddr;
pgtbl[i].owner = VDMA_PAGE_EMPTY;
paddr += VDMA_PAGESIZE;
}
}
/*
* Initialize the Jazz R4030 dma controller
*/
static int __init vdma_init(void)
{
/*
* Allocate 32k of memory for DMA page tables. This needs to be page
* aligned and should be uncached to avoid cache flushing after every
* update.
*/
pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
get_order(VDMA_PGTBL_SIZE));
BUG_ON(!pgtbl);
dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
/*
* Clear the R4030 translation table
*/
vdma_pgtbl_init();
r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n");
return 0;
}
/*
* Allocate DMA pagetables using a simple first-fit algorithm
*/
unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
{
int first, last, pages, frame, i;
unsigned long laddr, flags;
/* check arguments */
if (paddr > 0x1fffffff) {
if (vdma_debug)
printk("vdma_alloc: Invalid physical address: %08lx\n",
paddr);
return VDMA_ERROR; /* invalid physical address */
}
if (size > 0x400000 || size == 0) {
if (vdma_debug)
printk("vdma_alloc: Invalid size: %08lx\n", size);
return VDMA_ERROR; /* invalid physical address */
}
spin_lock_irqsave(&vdma_lock, flags);
/*
* Find free chunk
*/
pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1;
first = 0;
while (1) {
while (pgtbl[first].owner != VDMA_PAGE_EMPTY &&
first < VDMA_PGTBL_ENTRIES) first++;
if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */
spin_unlock_irqrestore(&vdma_lock, flags);
return VDMA_ERROR;
}
last = first + 1;
while (pgtbl[last].owner == VDMA_PAGE_EMPTY
&& last - first < pages)
last++;
if (last - first == pages)
break; /* found */
first = last + 1;
}
/*
* Mark pages as allocated
*/
laddr = (first << 12) + (paddr & (VDMA_PAGESIZE - 1));
frame = paddr & ~(VDMA_PAGESIZE - 1);
for (i = first; i < last; i++) {
pgtbl[i].frame = frame;
pgtbl[i].owner = laddr;
frame += VDMA_PAGESIZE;
}
/*
* Update translation table and return logical start address
*/
r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
if (vdma_debug > 1)
printk("vdma_alloc: Allocated %d pages starting from %08lx\n",
pages, laddr);
if (vdma_debug > 2) {
printk("LADDR: ");
for (i = first; i < last; i++)
printk("%08x ", i << 12);
printk("\nPADDR: ");
for (i = first; i < last; i++)
printk("%08x ", pgtbl[i].frame);
printk("\nOWNER: ");
for (i = first; i < last; i++)
printk("%08x ", pgtbl[i].owner);
printk("\n");
}
spin_unlock_irqrestore(&vdma_lock, flags);
return laddr;
}
EXPORT_SYMBOL(vdma_alloc);
/*
* Free previously allocated dma translation pages
* Note that this does NOT change the translation table,
* it just marks the free'd pages as unused!
*/
int vdma_free(unsigned long laddr)
{
int i;
i = laddr >> 12;
if (pgtbl[i].owner != laddr) {
printk
("vdma_free: trying to free other's dma pages, laddr=%8lx\n",
laddr);
return -1;
}
while (i < VDMA_PGTBL_ENTRIES && pgtbl[i].owner == laddr) {
pgtbl[i].owner = VDMA_PAGE_EMPTY;
i++;
}
if (vdma_debug > 1)
printk("vdma_free: freed %ld pages starting from %08lx\n",
i - (laddr >> 12), laddr);
return 0;
}
EXPORT_SYMBOL(vdma_free);
/*
* Map certain page(s) to another physical address.
* Caller must have allocated the page(s) before.
*/
int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
{
int first, pages, npages;
if (laddr > 0xffffff) {
if (vdma_debug)
printk
("vdma_map: Invalid logical address: %08lx\n",
laddr);
return -EINVAL; /* invalid logical address */
}
if (paddr > 0x1fffffff) {
if (vdma_debug)
printk
("vdma_map: Invalid physical address: %08lx\n",
paddr);
return -EINVAL; /* invalid physical address */
}
npages = pages =
(((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
first = laddr >> 12;
if (vdma_debug)
printk("vdma_remap: first=%x, pages=%x\n", first, pages);
if (first + pages > VDMA_PGTBL_ENTRIES) {
if (vdma_debug)
printk("vdma_alloc: Invalid size: %08lx\n", size);
return -EINVAL;
}
paddr &= ~(VDMA_PAGESIZE - 1);
while (pages > 0 && first < VDMA_PGTBL_ENTRIES) {
if (pgtbl[first].owner != laddr) {
if (vdma_debug)
printk("Trying to remap other's pages.\n");
return -EPERM; /* not owner */
}
pgtbl[first].frame = paddr;
paddr += VDMA_PAGESIZE;
first++;
pages--;
}
/*
* Update translation table
*/
r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
if (vdma_debug > 2) {
int i;
pages = (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
first = laddr >> 12;
printk("LADDR: ");
for (i = first; i < first + pages; i++)
printk("%08x ", i << 12);
printk("\nPADDR: ");
for (i = first; i < first + pages; i++)
printk("%08x ", pgtbl[i].frame);
printk("\nOWNER: ");
for (i = first; i < first + pages; i++)
printk("%08x ", pgtbl[i].owner);
printk("\n");
}
return 0;
}
/*
* Translate a physical address to a logical address.
* This will return the logical address of the first
* match.
*/
unsigned long vdma_phys2log(unsigned long paddr)
{
int i;
int frame;
frame = paddr & ~(VDMA_PAGESIZE - 1);
for (i = 0; i < VDMA_PGTBL_ENTRIES; i++) {
if (pgtbl[i].frame == frame)
break;
}
if (i == VDMA_PGTBL_ENTRIES)
return ~0UL;
return (i << 12) + (paddr & (VDMA_PAGESIZE - 1));
}
EXPORT_SYMBOL(vdma_phys2log);
/*
* Translate a logical DMA address to a physical address
*/
unsigned long vdma_log2phys(unsigned long laddr)
{
return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1));
}
EXPORT_SYMBOL(vdma_log2phys);
/*
* Print DMA statistics
*/
void vdma_stats(void)
{
int i;
printk("vdma_stats: CONFIG: %08x\n",
r4030_read_reg32(JAZZ_R4030_CONFIG));
printk("R4030 translation table base: %08x\n",
r4030_read_reg32(JAZZ_R4030_TRSTBL_BASE));
printk("R4030 translation table limit: %08x\n",
r4030_read_reg32(JAZZ_R4030_TRSTBL_LIM));
printk("vdma_stats: INV_ADDR: %08x\n",
r4030_read_reg32(JAZZ_R4030_INV_ADDR));
printk("vdma_stats: R_FAIL_ADDR: %08x\n",
r4030_read_reg32(JAZZ_R4030_R_FAIL_ADDR));
printk("vdma_stats: M_FAIL_ADDR: %08x\n",
r4030_read_reg32(JAZZ_R4030_M_FAIL_ADDR));
printk("vdma_stats: IRQ_SOURCE: %08x\n",
r4030_read_reg32(JAZZ_R4030_IRQ_SOURCE));
printk("vdma_stats: I386_ERROR: %08x\n",
r4030_read_reg32(JAZZ_R4030_I386_ERROR));
printk("vdma_chnl_modes: ");
for (i = 0; i < 8; i++)
printk("%04x ",
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +
(i << 5)));
printk("\n");
printk("vdma_chnl_enables: ");
for (i = 0; i < 8; i++)
printk("%04x ",
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(i << 5)));
printk("\n");
}
/*
* DMA transfer functions
*/
/*
* Enable a DMA channel. Also clear any error conditions.
*/
void vdma_enable(int channel)
{
int status;
if (vdma_debug)
printk("vdma_enable: channel %d\n", channel);
/*
* Check error conditions first
*/
status = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));
if (status & 0x400)
printk("VDMA: Channel %d: Address error!\n", channel);
if (status & 0x200)
printk("VDMA: Channel %d: Memory error!\n", channel);
/*
* Clear all interrupt flags
*/
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(channel << 5)) | R4030_TC_INTR
| R4030_MEM_INTR | R4030_ADDR_INTR);
/*
* Enable the desired channel
*/
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(channel << 5)) |
R4030_CHNL_ENABLE);
}
EXPORT_SYMBOL(vdma_enable);
/*
* Disable a DMA channel
*/
void vdma_disable(int channel)
{
if (vdma_debug) {
int status =
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(channel << 5));
printk("vdma_disable: channel %d\n", channel);
printk("VDMA: channel %d status: %04x (%s) mode: "
"%02x addr: %06x count: %06x\n",
channel, status,
((status & 0x600) ? "ERROR" : "OK"),
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +
(channel << 5)),
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ADDR +
(channel << 5)),
(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_COUNT +
(channel << 5)));
}
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(channel << 5)) &
~R4030_CHNL_ENABLE);
/*
* After disabling a DMA channel a remote bus register should be
* read to ensure that the current DMA acknowledge cycle is completed.
*/
*((volatile unsigned int *) JAZZ_DUMMY_DEVICE);
}
EXPORT_SYMBOL(vdma_disable);
/*
* Set DMA mode. This function accepts the mode values used
* to set a PC-style DMA controller. For the SCSI and FDC
* channels, we also set the default modes each time we're
* called.
* NOTE: The FAST and BURST dma modes are supported by the
* R4030 Rev. 2 and PICA chipsets only. I leave them disabled
* for now.
*/
void vdma_set_mode(int channel, int mode)
{
if (vdma_debug)
printk("vdma_set_mode: channel %d, mode 0x%x\n", channel,
mode);
switch (channel) {
case JAZZ_SCSI_DMA: /* scsi */
r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),
/* R4030_MODE_FAST | */
/* R4030_MODE_BURST | */
R4030_MODE_INTR_EN |
R4030_MODE_WIDTH_16 |
R4030_MODE_ATIME_80);
break;
case JAZZ_FLOPPY_DMA: /* floppy */
r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),
/* R4030_MODE_FAST | */
/* R4030_MODE_BURST | */
R4030_MODE_INTR_EN |
R4030_MODE_WIDTH_8 |
R4030_MODE_ATIME_120);
break;
case JAZZ_AUDIOL_DMA:
case JAZZ_AUDIOR_DMA:
printk("VDMA: Audio DMA not supported yet.\n");
break;
default:
printk
("VDMA: vdma_set_mode() called with unsupported channel %d!\n",
channel);
}
switch (mode) {
case DMA_MODE_READ:
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(channel << 5)) &
~R4030_CHNL_WRITE);
break;
case DMA_MODE_WRITE:
r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +
(channel << 5)) |
R4030_CHNL_WRITE);
break;
default:
printk
("VDMA: vdma_set_mode() called with unknown dma mode 0x%x\n",
mode);
}
}
EXPORT_SYMBOL(vdma_set_mode);
/*
* Set Transfer Address
*/
void vdma_set_addr(int channel, long addr)
{
if (vdma_debug)
printk("vdma_set_addr: channel %d, addr %lx\n", channel,
addr);
r4030_write_reg32(JAZZ_R4030_CHNL_ADDR + (channel << 5), addr);
}
EXPORT_SYMBOL(vdma_set_addr);
/*
* Set Transfer Count
*/
void vdma_set_count(int channel, int count)
{
if (vdma_debug)
printk("vdma_set_count: channel %d, count %08x\n", channel,
(unsigned) count);
r4030_write_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5), count);
}
EXPORT_SYMBOL(vdma_set_count);
/*
* Get Residual
*/
int vdma_get_residue(int channel)
{
int residual;
residual = r4030_read_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5));
if (vdma_debug)
printk("vdma_get_residual: channel %d: residual=%d\n",
channel, residual);
return residual;
}
/*
* Get DMA channel enable register
*/
int vdma_get_enable(int channel)
{
int enable;
enable = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));
if (vdma_debug)
printk("vdma_get_enable: channel %d: enable=%d\n", channel,
enable);
return enable;
}
arch_initcall(vdma_init);
| gpl-2.0 |
2fast4u88/Htc-Design-FastKernel | drivers/media/dvb/frontends/tda1004x.c | 1519 | 39784 | /*
Driver for Philips tda1004xh OFDM Demodulator
(c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* This driver needs external firmware. Please use the commands
* "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
* "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
* download/extract them, and then copy them to /usr/lib/hotplug/firmware
* or /lib/firmware (depending on configuration of firmware hotplug).
*/
#define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
#define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/string.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "tda1004x.h"
static int debug;
#define dprintk(args...) \
do { \
if (debug) printk(KERN_DEBUG "tda1004x: " args); \
} while (0)
#define TDA1004X_CHIPID 0x00
#define TDA1004X_AUTO 0x01
#define TDA1004X_IN_CONF1 0x02
#define TDA1004X_IN_CONF2 0x03
#define TDA1004X_OUT_CONF1 0x04
#define TDA1004X_OUT_CONF2 0x05
#define TDA1004X_STATUS_CD 0x06
#define TDA1004X_CONFC4 0x07
#define TDA1004X_DSSPARE2 0x0C
#define TDA10045H_CODE_IN 0x0D
#define TDA10045H_FWPAGE 0x0E
#define TDA1004X_SCAN_CPT 0x10
#define TDA1004X_DSP_CMD 0x11
#define TDA1004X_DSP_ARG 0x12
#define TDA1004X_DSP_DATA1 0x13
#define TDA1004X_DSP_DATA2 0x14
#define TDA1004X_CONFADC1 0x15
#define TDA1004X_CONFC1 0x16
#define TDA10045H_S_AGC 0x1a
#define TDA10046H_AGC_TUN_LEVEL 0x1a
#define TDA1004X_SNR 0x1c
#define TDA1004X_CONF_TS1 0x1e
#define TDA1004X_CONF_TS2 0x1f
#define TDA1004X_CBER_RESET 0x20
#define TDA1004X_CBER_MSB 0x21
#define TDA1004X_CBER_LSB 0x22
#define TDA1004X_CVBER_LUT 0x23
#define TDA1004X_VBER_MSB 0x24
#define TDA1004X_VBER_MID 0x25
#define TDA1004X_VBER_LSB 0x26
#define TDA1004X_UNCOR 0x27
#define TDA10045H_CONFPLL_P 0x2D
#define TDA10045H_CONFPLL_M_MSB 0x2E
#define TDA10045H_CONFPLL_M_LSB 0x2F
#define TDA10045H_CONFPLL_N 0x30
#define TDA10046H_CONFPLL1 0x2D
#define TDA10046H_CONFPLL2 0x2F
#define TDA10046H_CONFPLL3 0x30
#define TDA10046H_TIME_WREF1 0x31
#define TDA10046H_TIME_WREF2 0x32
#define TDA10046H_TIME_WREF3 0x33
#define TDA10046H_TIME_WREF4 0x34
#define TDA10046H_TIME_WREF5 0x35
#define TDA10045H_UNSURW_MSB 0x31
#define TDA10045H_UNSURW_LSB 0x32
#define TDA10045H_WREF_MSB 0x33
#define TDA10045H_WREF_MID 0x34
#define TDA10045H_WREF_LSB 0x35
#define TDA10045H_MUXOUT 0x36
#define TDA1004X_CONFADC2 0x37
#define TDA10045H_IOFFSET 0x38
#define TDA10046H_CONF_TRISTATE1 0x3B
#define TDA10046H_CONF_TRISTATE2 0x3C
#define TDA10046H_CONF_POLARITY 0x3D
#define TDA10046H_FREQ_OFFSET 0x3E
#define TDA10046H_GPIO_OUT_SEL 0x41
#define TDA10046H_GPIO_SELECT 0x42
#define TDA10046H_AGC_CONF 0x43
#define TDA10046H_AGC_THR 0x44
#define TDA10046H_AGC_RENORM 0x45
#define TDA10046H_AGC_GAINS 0x46
#define TDA10046H_AGC_TUN_MIN 0x47
#define TDA10046H_AGC_TUN_MAX 0x48
#define TDA10046H_AGC_IF_MIN 0x49
#define TDA10046H_AGC_IF_MAX 0x4A
#define TDA10046H_FREQ_PHY2_MSB 0x4D
#define TDA10046H_FREQ_PHY2_LSB 0x4E
#define TDA10046H_CVBER_CTRL 0x4F
#define TDA10046H_AGC_IF_LEVEL 0x52
#define TDA10046H_CODE_CPT 0x57
#define TDA10046H_CODE_IN 0x58
static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
{
int ret;
u8 buf[] = { reg, data };
struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
msg.addr = state->config->demod_address;
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1)
dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
__func__, reg, data, ret);
dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
reg, data, ret);
return (ret != 1) ? -1 : 0;
}
static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
{
int ret;
u8 b0[] = { reg };
u8 b1[] = { 0 };
struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
{ .flags = I2C_M_RD, .buf = b1, .len = 1 }};
dprintk("%s: reg=0x%x\n", __func__, reg);
msg[0].addr = state->config->demod_address;
msg[1].addr = state->config->demod_address;
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
ret);
return -EINVAL;
}
dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
reg, b1[0], ret);
return b1[0];
}
static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
{
int val;
dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
mask, data);
// read a byte and check
val = tda1004x_read_byte(state, reg);
if (val < 0)
return val;
// mask if off
val = val & ~mask;
val |= data & 0xff;
// write it out again
return tda1004x_write_byteI(state, reg, val);
}
static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
{
int i;
int result;
dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
result = 0;
for (i = 0; i < len; i++) {
result = tda1004x_write_byteI(state, reg + i, buf[i]);
if (result != 0)
break;
}
return result;
}
static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
{
int result;
dprintk("%s\n", __func__);
result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
msleep(20);
return result;
}
static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
{
dprintk("%s\n", __func__);
return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
}
static int tda10045h_set_bandwidth(struct tda1004x_state *state,
fe_bandwidth_t bandwidth)
{
static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
switch (bandwidth) {
case BANDWIDTH_6_MHZ:
tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
break;
case BANDWIDTH_7_MHZ:
tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
break;
case BANDWIDTH_8_MHZ:
tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
break;
default:
return -EINVAL;
}
tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
return 0;
}
static int tda10046h_set_bandwidth(struct tda1004x_state *state,
fe_bandwidth_t bandwidth)
{
static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
int tda10046_clk53m;
if ((state->config->if_freq == TDA10046_FREQ_045) ||
(state->config->if_freq == TDA10046_FREQ_052))
tda10046_clk53m = 0;
else
tda10046_clk53m = 1;
switch (bandwidth) {
case BANDWIDTH_6_MHZ:
if (tda10046_clk53m)
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
sizeof(bandwidth_6mhz_53M));
else
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
sizeof(bandwidth_6mhz_48M));
if (state->config->if_freq == TDA10046_FREQ_045) {
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
}
break;
case BANDWIDTH_7_MHZ:
if (tda10046_clk53m)
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
sizeof(bandwidth_7mhz_53M));
else
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
sizeof(bandwidth_7mhz_48M));
if (state->config->if_freq == TDA10046_FREQ_045) {
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
}
break;
case BANDWIDTH_8_MHZ:
if (tda10046_clk53m)
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
sizeof(bandwidth_8mhz_53M));
else
tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
sizeof(bandwidth_8mhz_48M));
if (state->config->if_freq == TDA10046_FREQ_045) {
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
}
break;
default:
return -EINVAL;
}
return 0;
}
static int tda1004x_do_upload(struct tda1004x_state *state,
const unsigned char *mem, unsigned int len,
u8 dspCodeCounterReg, u8 dspCodeInReg)
{
u8 buf[65];
struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
int tx_size;
int pos = 0;
/* clear code counter */
tda1004x_write_byteI(state, dspCodeCounterReg, 0);
fw_msg.addr = state->config->demod_address;
buf[0] = dspCodeInReg;
while (pos != len) {
// work out how much to send this time
tx_size = len - pos;
if (tx_size > 0x10)
tx_size = 0x10;
// send the chunk
memcpy(buf + 1, mem + pos, tx_size);
fw_msg.len = tx_size + 1;
if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
printk(KERN_ERR "tda1004x: Error during firmware upload\n");
return -EIO;
}
pos += tx_size;
dprintk("%s: fw_pos=0x%x\n", __func__, pos);
}
// give the DSP a chance to settle 03/10/05 Hac
msleep(100);
return 0;
}
static int tda1004x_check_upload_ok(struct tda1004x_state *state)
{
u8 data1, data2;
unsigned long timeout;
if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
timeout = jiffies + 2 * HZ;
while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
if (time_after(jiffies, timeout)) {
printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
break;
}
msleep(1);
}
} else
msleep(100);
// check upload was OK
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
return -EIO;
}
printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
return 0;
}
static int tda10045_fwupload(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int ret;
const struct firmware *fw;
/* don't re-upload unless necessary */
if (tda1004x_check_upload_ok(state) == 0)
return 0;
/* request the firmware, this will block until someone uploads it */
printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
if (ret) {
printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
return ret;
}
/* reset chip */
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
msleep(10);
/* set parameters */
tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
release_firmware(fw);
if (ret)
return ret;
printk(KERN_INFO "tda1004x: firmware upload complete\n");
/* wait for DSP to initialise */
/* DSPREADY doesn't seem to work on the TDA10045H */
msleep(100);
return tda1004x_check_upload_ok(state);
}
static void tda10046_init_plls(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tda10046_clk53m;
if ((state->config->if_freq == TDA10046_FREQ_045) ||
(state->config->if_freq == TDA10046_FREQ_052))
tda10046_clk53m = 0;
else
tda10046_clk53m = 1;
tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
if(tda10046_clk53m) {
printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
} else {
printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
}
if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
} else {
dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
}
if(tda10046_clk53m)
tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
else
tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
/* Note clock frequency is handled implicitly */
switch (state->config->if_freq) {
case TDA10046_FREQ_045:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
break;
case TDA10046_FREQ_052:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
break;
case TDA10046_FREQ_3617:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
break;
case TDA10046_FREQ_3613:
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
break;
}
tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
/* let the PLLs settle */
msleep(120);
}
static int tda10046_fwupload(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int ret, confc4;
const struct firmware *fw;
/* reset + wake up chip */
if (state->config->xtal_freq == TDA10046_XTAL_4M) {
confc4 = 0;
} else {
dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
confc4 = 0x80;
}
tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
/* set GPIO 1 and 3 */
if (state->config->gpio_config != TDA10046_GPTRI) {
tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
}
/* let the clocks recover from sleep */
msleep(10);
/* The PLLs need to be reprogrammed after sleep */
tda10046_init_plls(fe);
tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
/* don't re-upload unless necessary */
if (tda1004x_check_upload_ok(state) == 0)
return 0;
/*
For i2c normal work, we need to slow down the bus speed.
However, the slow down breaks the eeprom firmware load.
So, use normal speed for eeprom booting and then restore the
i2c speed after that. Tested with MSI TV @nyware A/D board,
that comes with firmware version 29 inside their eeprom.
It should also be noticed that no other I2C transfer should
be in course while booting from eeprom, otherwise, tda10046
goes into an instable state. So, proper locking are needed
at the i2c bus master.
*/
printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
msleep(300);
tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
/* Checks if eeprom firmware went without troubles */
if (tda1004x_check_upload_ok(state) == 0)
return 0;
/* eeprom firmware didn't work. Load one manually. */
if (state->config->request_firmware != NULL) {
/* request the firmware, this will block until someone uploads it */
printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
if (ret) {
/* remain compatible to old bug: try to load with tda10045 image name */
ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
if (ret) {
printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
return ret;
} else {
printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
TDA10046_DEFAULT_FIRMWARE);
}
}
} else {
printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
return -EIO;
}
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
release_firmware(fw);
return tda1004x_check_upload_ok(state);
}
static int tda1004x_encode_fec(int fec)
{
// convert known FEC values
switch (fec) {
case FEC_1_2:
return 0;
case FEC_2_3:
return 1;
case FEC_3_4:
return 2;
case FEC_5_6:
return 3;
case FEC_7_8:
return 4;
}
// unsupported
return -EINVAL;
}
static int tda1004x_decode_fec(int tdafec)
{
// convert known FEC values
switch (tdafec) {
case 0:
return FEC_1_2;
case 1:
return FEC_2_3;
case 2:
return FEC_3_4;
case 3:
return FEC_5_6;
case 4:
return FEC_7_8;
}
// unsupported
return -1;
}
static int tda1004x_write(struct dvb_frontend* fe, u8 *buf, int len)
{
struct tda1004x_state* state = fe->demodulator_priv;
if (len != 2)
return -EINVAL;
return tda1004x_write_byteI(state, buf[0], buf[1]);
}
static int tda10045_init(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (tda10045_fwupload(fe)) {
printk("tda1004x: firmware upload failed\n");
return -EIO;
}
tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
// tda setup
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
return 0;
}
static int tda10046_init(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
dprintk("%s\n", __func__);
if (tda10046_fwupload(fe)) {
printk("tda1004x: firmware upload failed\n");
return -EIO;
}
// tda setup
tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
switch (state->config->agc_config) {
case TDA10046_AGC_DEFAULT:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
case TDA10046_AGC_IFO_AUTO_NEG:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
case TDA10046_AGC_IFO_AUTO_POS:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
break;
case TDA10046_AGC_TDA827X:
tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
}
if (state->config->ts_mode == 0) {
tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
} else {
tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
state->config->invert_oclk << 4);
}
tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
// tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
return 0;
}
static int tda1004x_set_fe(struct dvb_frontend* fe,
struct dvb_frontend_parameters *fe_params)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
int inversion;
dprintk("%s\n", __func__);
if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
// setup auto offset
tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
// disable agc_conf[2]
tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
}
// set frequency
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe, fe_params);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
// Hardcoded to use auto as much as possible on the TDA10045 as it
// is very unreliable if AUTO mode is _not_ used.
if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
}
// Set standard params.. or put them to auto
if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
(fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
(fe_params->u.ofdm.constellation == QAM_AUTO) ||
(fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
} else {
tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
// set HP FEC
tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
if (tmp < 0)
return tmp;
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
// set LP FEC
tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
if (tmp < 0)
return tmp;
tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
// set constellation
switch (fe_params->u.ofdm.constellation) {
case QPSK:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
break;
case QAM_16:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
break;
case QAM_64:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
break;
default:
return -EINVAL;
}
// set hierarchy
switch (fe_params->u.ofdm.hierarchy_information) {
case HIERARCHY_NONE:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
break;
case HIERARCHY_1:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
break;
case HIERARCHY_2:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
break;
case HIERARCHY_4:
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
break;
default:
return -EINVAL;
}
}
// set bandwidth
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
break;
case TDA1004X_DEMOD_TDA10046:
tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
break;
}
// set inversion
inversion = fe_params->inversion;
if (state->config->invert)
inversion = inversion ? INVERSION_OFF : INVERSION_ON;
switch (inversion) {
case INVERSION_OFF:
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
break;
case INVERSION_ON:
tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
break;
default:
return -EINVAL;
}
// set guard interval
switch (fe_params->u.ofdm.guard_interval) {
case GUARD_INTERVAL_1_32:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
break;
case GUARD_INTERVAL_1_16:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
break;
case GUARD_INTERVAL_1_8:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
break;
case GUARD_INTERVAL_1_4:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
break;
case GUARD_INTERVAL_AUTO:
tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
break;
default:
return -EINVAL;
}
// set transmission mode
switch (fe_params->u.ofdm.transmission_mode) {
case TRANSMISSION_MODE_2K:
tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
break;
case TRANSMISSION_MODE_8K:
tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
break;
case TRANSMISSION_MODE_AUTO:
tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
break;
default:
return -EINVAL;
}
// start the lock
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
break;
case TDA1004X_DEMOD_TDA10046:
tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
msleep(1);
tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
break;
}
msleep(10);
return 0;
}
static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
{
struct tda1004x_state* state = fe->demodulator_priv;
dprintk("%s\n", __func__);
// inversion status
fe_params->inversion = INVERSION_OFF;
if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
fe_params->inversion = INVERSION_ON;
if (state->config->invert)
fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
// bandwidth
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
case 0x14:
fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
break;
case 0xdb:
fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
break;
case 0x4f:
fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
break;
}
break;
case TDA1004X_DEMOD_TDA10046:
switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
case 0x5c:
case 0x54:
fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
break;
case 0x6a:
case 0x60:
fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
break;
case 0x7b:
case 0x70:
fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
break;
}
break;
}
// FEC
fe_params->u.ofdm.code_rate_HP =
tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
fe_params->u.ofdm.code_rate_LP =
tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
// constellation
switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
case 0:
fe_params->u.ofdm.constellation = QPSK;
break;
case 1:
fe_params->u.ofdm.constellation = QAM_16;
break;
case 2:
fe_params->u.ofdm.constellation = QAM_64;
break;
}
// transmission mode
fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
// guard interval
switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
case 0:
fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
break;
}
// hierarchy
switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
case 0:
fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
break;
case 1:
fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
break;
case 2:
fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
break;
case 3:
fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
break;
}
return 0;
}
static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
{
struct tda1004x_state* state = fe->demodulator_priv;
int status;
int cber;
int vber;
dprintk("%s\n", __func__);
// read status
status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
if (status == -1)
return -EIO;
// decode
*fe_status = 0;
if (status & 4)
*fe_status |= FE_HAS_SIGNAL;
if (status & 2)
*fe_status |= FE_HAS_CARRIER;
if (status & 8)
*fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
// if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
// is getting anything valid
if (!(*fe_status & FE_HAS_VITERBI)) {
// read the CBER
cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
if (cber == -1)
return -EIO;
status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
if (status == -1)
return -EIO;
cber |= (status << 8);
// The address 0x20 should be read to cope with a TDA10046 bug
tda1004x_read_byte(state, TDA1004X_CBER_RESET);
if (cber != 65535)
*fe_status |= FE_HAS_VITERBI;
}
// if we DO have some valid VITERBI output, but don't already have SYNC
// bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
// read the VBER
vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
if (vber == -1)
return -EIO;
status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
if (status == -1)
return -EIO;
vber |= (status << 8);
status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
if (status == -1)
return -EIO;
vber |= (status & 0x0f) << 16;
// The CVBER_LUT should be read to cope with TDA10046 hardware bug
tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
// if RS has passed some valid TS packets, then we must be
// getting some SYNC bytes
if (vber < 16632)
*fe_status |= FE_HAS_SYNC;
}
// success
dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
return 0;
}
static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
int reg = 0;
dprintk("%s\n", __func__);
// determine the register to use
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
reg = TDA10045H_S_AGC;
break;
case TDA1004X_DEMOD_TDA10046:
reg = TDA10046H_AGC_IF_LEVEL;
break;
}
// read it
tmp = tda1004x_read_byte(state, reg);
if (tmp < 0)
return -EIO;
*signal = (tmp << 8) | tmp;
dprintk("%s: signal=0x%x\n", __func__, *signal);
return 0;
}
static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
dprintk("%s\n", __func__);
// read it
tmp = tda1004x_read_byte(state, TDA1004X_SNR);
if (tmp < 0)
return -EIO;
tmp = 255 - tmp;
*snr = ((tmp << 8) | tmp);
dprintk("%s: snr=0x%x\n", __func__, *snr);
return 0;
}
static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
int tmp2;
int counter;
dprintk("%s\n", __func__);
// read the UCBLOCKS and reset
counter = 0;
tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
if (tmp < 0)
return -EIO;
tmp &= 0x7f;
while (counter++ < 5) {
tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
if (tmp2 < 0)
return -EIO;
tmp2 &= 0x7f;
if ((tmp2 < tmp) || (tmp2 == 0))
break;
}
if (tmp != 0x7f)
*ucblocks = tmp;
else
*ucblocks = 0xffffffff;
dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
return 0;
}
static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct tda1004x_state* state = fe->demodulator_priv;
int tmp;
dprintk("%s\n", __func__);
// read it in
tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
if (tmp < 0)
return -EIO;
*ber = tmp << 1;
tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
if (tmp < 0)
return -EIO;
*ber |= (tmp << 9);
// The address 0x20 should be read to cope with a TDA10046 bug
tda1004x_read_byte(state, TDA1004X_CBER_RESET);
dprintk("%s: ber=0x%x\n", __func__, *ber);
return 0;
}
static int tda1004x_sleep(struct dvb_frontend* fe)
{
struct tda1004x_state* state = fe->demodulator_priv;
int gpio_conf;
switch (state->demod_type) {
case TDA1004X_DEMOD_TDA10045:
tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
break;
case TDA1004X_DEMOD_TDA10046:
/* set outputs to tristate */
tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
/* invert GPIO 1 and 3 if desired*/
gpio_conf = state->config->gpio_config;
if (gpio_conf >= TDA10046_GP00_I)
tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
(gpio_conf & 0x0f) ^ 0x0a);
tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
break;
}
return 0;
}
static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct tda1004x_state* state = fe->demodulator_priv;
if (enable) {
return tda1004x_enable_tuner_i2c(state);
} else {
return tda1004x_disable_tuner_i2c(state);
}
}
static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
fesettings->min_delay_ms = 800;
/* Drift compensation makes no sense for DVB-T */
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static void tda1004x_release(struct dvb_frontend* fe)
{
struct tda1004x_state *state = fe->demodulator_priv;
kfree(state);
}
static struct dvb_frontend_ops tda10045_ops = {
.info = {
.name = "Philips TDA10045H DVB-T",
.type = FE_OFDM,
.frequency_min = 51000000,
.frequency_max = 858000000,
.frequency_stepsize = 166667,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
},
.release = tda1004x_release,
.init = tda10045_init,
.sleep = tda1004x_sleep,
.write = tda1004x_write,
.i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
.set_frontend = tda1004x_set_fe,
.get_frontend = tda1004x_get_fe,
.get_tune_settings = tda1004x_get_tune_settings,
.read_status = tda1004x_read_status,
.read_ber = tda1004x_read_ber,
.read_signal_strength = tda1004x_read_signal_strength,
.read_snr = tda1004x_read_snr,
.read_ucblocks = tda1004x_read_ucblocks,
};
struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
struct i2c_adapter* i2c)
{
struct tda1004x_state *state;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
if (!state) {
printk(KERN_ERR "Can't alocate memory for tda10045 state\n");
return NULL;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
state->demod_type = TDA1004X_DEMOD_TDA10045;
/* check if the demod is there */
id = tda1004x_read_byte(state, TDA1004X_CHIPID);
if (id < 0) {
printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
kfree(state);
return NULL;
}
if (id != 0x25) {
printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
kfree(state);
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
static struct dvb_frontend_ops tda10046_ops = {
.info = {
.name = "Philips TDA10046H DVB-T",
.type = FE_OFDM,
.frequency_min = 51000000,
.frequency_max = 858000000,
.frequency_stepsize = 166667,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
},
.release = tda1004x_release,
.init = tda10046_init,
.sleep = tda1004x_sleep,
.write = tda1004x_write,
.i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
.set_frontend = tda1004x_set_fe,
.get_frontend = tda1004x_get_fe,
.get_tune_settings = tda1004x_get_tune_settings,
.read_status = tda1004x_read_status,
.read_ber = tda1004x_read_ber,
.read_signal_strength = tda1004x_read_signal_strength,
.read_snr = tda1004x_read_snr,
.read_ucblocks = tda1004x_read_ucblocks,
};
struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
struct i2c_adapter* i2c)
{
struct tda1004x_state *state;
int id;
/* allocate memory for the internal state */
state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
if (!state) {
printk(KERN_ERR "Can't alocate memory for tda10046 state\n");
return NULL;
}
/* setup the state */
state->config = config;
state->i2c = i2c;
state->demod_type = TDA1004X_DEMOD_TDA10046;
/* check if the demod is there */
id = tda1004x_read_byte(state, TDA1004X_CHIPID);
if (id < 0) {
printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
kfree(state);
return NULL;
}
if (id != 0x46) {
printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
kfree(state);
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
}
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(tda10045_attach);
EXPORT_SYMBOL(tda10046_attach);
| gpl-2.0 |
bilalliberty/kernel_golfu | drivers/pcmcia/pxa2xx_sharpsl.c | 1775 | 7860 | /*
* Sharp SL-C7xx Series PCMCIA routines
*
* Copyright (c) 2004-2005 Richard Purdie
*
* Based on Sharp's 2.4 kernel patches and pxa2xx_mainstone.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/hardware/scoop.h>
#include "soc_common.h"
#define NO_KEEP_VS 0x0001
#define SCOOP_DEV platform_scoop_config->devs
static void sharpsl_pcmcia_init_reset(struct soc_pcmcia_socket *skt)
{
struct scoop_pcmcia_dev *scoopdev = &SCOOP_DEV[skt->nr];
reset_scoop(scoopdev->dev);
/* Shared power controls need to be handled carefully */
if (platform_scoop_config->power_ctrl)
platform_scoop_config->power_ctrl(scoopdev->dev, 0x0000, skt->nr);
else
write_scoop_reg(scoopdev->dev, SCOOP_CPR, 0x0000);
scoopdev->keep_vs = NO_KEEP_VS;
scoopdev->keep_rd = 0;
}
static int sharpsl_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
int ret;
if (platform_scoop_config->pcmcia_init)
platform_scoop_config->pcmcia_init();
/* Register interrupts */
if (SCOOP_DEV[skt->nr].cd_irq >= 0) {
struct pcmcia_irqs cd_irq;
cd_irq.sock = skt->nr;
cd_irq.irq = SCOOP_DEV[skt->nr].cd_irq;
cd_irq.str = SCOOP_DEV[skt->nr].cd_irq_str;
ret = soc_pcmcia_request_irqs(skt, &cd_irq, 1);
if (ret) {
printk(KERN_ERR "Request for Compact Flash IRQ failed\n");
return ret;
}
}
skt->socket.pci_irq = SCOOP_DEV[skt->nr].irq;
return 0;
}
static void sharpsl_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
{
if (SCOOP_DEV[skt->nr].cd_irq >= 0) {
struct pcmcia_irqs cd_irq;
cd_irq.sock = skt->nr;
cd_irq.irq = SCOOP_DEV[skt->nr].cd_irq;
cd_irq.str = SCOOP_DEV[skt->nr].cd_irq_str;
soc_pcmcia_free_irqs(skt, &cd_irq, 1);
}
}
static void sharpsl_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
struct pcmcia_state *state)
{
unsigned short cpr, csr;
struct device *scoop = SCOOP_DEV[skt->nr].dev;
cpr = read_scoop_reg(SCOOP_DEV[skt->nr].dev, SCOOP_CPR);
write_scoop_reg(scoop, SCOOP_IRM, 0x00FF);
write_scoop_reg(scoop, SCOOP_ISR, 0x0000);
write_scoop_reg(scoop, SCOOP_IRM, 0x0000);
csr = read_scoop_reg(scoop, SCOOP_CSR);
if (csr & 0x0004) {
/* card eject */
write_scoop_reg(scoop, SCOOP_CDR, 0x0000);
SCOOP_DEV[skt->nr].keep_vs = NO_KEEP_VS;
}
else if (!(SCOOP_DEV[skt->nr].keep_vs & NO_KEEP_VS)) {
/* keep vs1,vs2 */
write_scoop_reg(scoop, SCOOP_CDR, 0x0000);
csr |= SCOOP_DEV[skt->nr].keep_vs;
}
else if (cpr & 0x0003) {
/* power on */
write_scoop_reg(scoop, SCOOP_CDR, 0x0000);
SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0);
}
else {
/* card detect */
if ((machine_is_spitz() || machine_is_borzoi()) && skt->nr == 1) {
write_scoop_reg(scoop, SCOOP_CDR, 0x0000);
} else {
write_scoop_reg(scoop, SCOOP_CDR, 0x0002);
}
}
state->detect = (csr & 0x0004) ? 0 : 1;
state->ready = (csr & 0x0002) ? 1 : 0;
state->bvd1 = (csr & 0x0010) ? 1 : 0;
state->bvd2 = (csr & 0x0020) ? 1 : 0;
state->wrprot = (csr & 0x0008) ? 1 : 0;
state->vs_3v = (csr & 0x0040) ? 0 : 1;
state->vs_Xv = (csr & 0x0080) ? 0 : 1;
if ((cpr & 0x0080) && ((cpr & 0x8040) != 0x8040)) {
printk(KERN_ERR "sharpsl_pcmcia_socket_state(): CPR=%04X, Low voltage!\n", cpr);
}
}
static int sharpsl_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
const socket_state_t *state)
{
unsigned long flags;
struct device *scoop = SCOOP_DEV[skt->nr].dev;
unsigned short cpr, ncpr, ccr, nccr, mcr, nmcr, imr, nimr;
switch (state->Vcc) {
case 0: break;
case 33: break;
case 50: break;
default:
printk(KERN_ERR "sharpsl_pcmcia_configure_socket(): bad Vcc %u\n", state->Vcc);
return -1;
}
if ((state->Vpp!=state->Vcc) && (state->Vpp!=0)) {
printk(KERN_ERR "CF slot cannot support Vpp %u\n", state->Vpp);
return -1;
}
local_irq_save(flags);
nmcr = (mcr = read_scoop_reg(scoop, SCOOP_MCR)) & ~0x0010;
ncpr = (cpr = read_scoop_reg(scoop, SCOOP_CPR)) & ~0x0083;
nccr = (ccr = read_scoop_reg(scoop, SCOOP_CCR)) & ~0x0080;
nimr = (imr = read_scoop_reg(scoop, SCOOP_IMR)) & ~0x003E;
if ((machine_is_spitz() || machine_is_borzoi() || machine_is_akita()) && skt->nr == 0) {
ncpr |= (state->Vcc == 33) ? 0x0002 :
(state->Vcc == 50) ? 0x0002 : 0;
} else {
ncpr |= (state->Vcc == 33) ? 0x0001 :
(state->Vcc == 50) ? 0x0002 : 0;
}
nmcr |= (state->flags&SS_IOCARD) ? 0x0010 : 0;
ncpr |= (state->flags&SS_OUTPUT_ENA) ? 0x0080 : 0;
nccr |= (state->flags&SS_RESET)? 0x0080: 0;
nimr |= ((skt->status&SS_DETECT) ? 0x0004 : 0)|
((skt->status&SS_READY) ? 0x0002 : 0)|
((skt->status&SS_BATDEAD)? 0x0010 : 0)|
((skt->status&SS_BATWARN)? 0x0020 : 0)|
((skt->status&SS_STSCHG) ? 0x0010 : 0)|
((skt->status&SS_WRPROT) ? 0x0008 : 0);
if (!(ncpr & 0x0003)) {
SCOOP_DEV[skt->nr].keep_rd = 0;
} else if (!SCOOP_DEV[skt->nr].keep_rd) {
if (nccr & 0x0080)
SCOOP_DEV[skt->nr].keep_rd = 1;
else
nccr |= 0x0080;
}
if (mcr != nmcr)
write_scoop_reg(scoop, SCOOP_MCR, nmcr);
if (cpr != ncpr) {
if (platform_scoop_config->power_ctrl)
platform_scoop_config->power_ctrl(scoop, ncpr , skt->nr);
else
write_scoop_reg(scoop, SCOOP_CPR, ncpr);
}
if (ccr != nccr)
write_scoop_reg(scoop, SCOOP_CCR, nccr);
if (imr != nimr)
write_scoop_reg(scoop, SCOOP_IMR, nimr);
local_irq_restore(flags);
return 0;
}
static void sharpsl_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
{
sharpsl_pcmcia_init_reset(skt);
/* Enable interrupt */
write_scoop_reg(SCOOP_DEV[skt->nr].dev, SCOOP_IMR, 0x00C0);
write_scoop_reg(SCOOP_DEV[skt->nr].dev, SCOOP_MCR, 0x0101);
SCOOP_DEV[skt->nr].keep_vs = NO_KEEP_VS;
}
static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
{
sharpsl_pcmcia_init_reset(skt);
}
static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = {
.owner = THIS_MODULE,
.hw_init = sharpsl_pcmcia_hw_init,
.hw_shutdown = sharpsl_pcmcia_hw_shutdown,
.socket_state = sharpsl_pcmcia_socket_state,
.configure_socket = sharpsl_pcmcia_configure_socket,
.socket_init = sharpsl_pcmcia_socket_init,
.socket_suspend = sharpsl_pcmcia_socket_suspend,
.first = 0,
.nr = 0,
};
#ifdef CONFIG_SA1100_COLLIE
#include "sa11xx_base.h"
int __devinit pcmcia_collie_init(struct device *dev)
{
int ret = -ENODEV;
if (machine_is_collie())
ret = sa11xx_drv_pcmcia_probe(dev, &sharpsl_pcmcia_ops, 0, 1);
return ret;
}
#else
static struct platform_device *sharpsl_pcmcia_device;
static int __init sharpsl_pcmcia_init(void)
{
int ret;
if (!platform_scoop_config)
return -ENODEV;
sharpsl_pcmcia_ops.nr = platform_scoop_config->num_devs;
sharpsl_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
if (!sharpsl_pcmcia_device)
return -ENOMEM;
ret = platform_device_add_data(sharpsl_pcmcia_device,
&sharpsl_pcmcia_ops, sizeof(sharpsl_pcmcia_ops));
if (ret == 0) {
sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
ret = platform_device_add(sharpsl_pcmcia_device);
}
if (ret)
platform_device_put(sharpsl_pcmcia_device);
return ret;
}
static void __exit sharpsl_pcmcia_exit(void)
{
platform_device_unregister(sharpsl_pcmcia_device);
}
fs_initcall(sharpsl_pcmcia_init);
module_exit(sharpsl_pcmcia_exit);
#endif
MODULE_DESCRIPTION("Sharp SL Series PCMCIA Support");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-pcmcia");
| gpl-2.0 |
Jeongdeokho/Dai5y | arch/arm/mach-omap2/board-cm-t3517.c | 2287 | 7946 | /*
* linux/arch/arm/mach-omap2/board-cm-t3517.c
*
* Support for the CompuLab CM-T3517 modules
*
* Copyright (C) 2010 CompuLab, Ltd.
* Author: Igor Grinberg <grinberg@compulab.co.il>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/rtc-v3020.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/can/platform/ti_hecc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/usb.h>
#include <plat/nand.h>
#include <plat/gpmc.h>
#include <mach/am35xx.h>
#include "mux.h"
#include "control.h"
#include "common-board-devices.h"
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cm_t3517_leds[] = {
[0] = {
.gpio = 186,
.name = "cm-t3517:green",
.default_trigger = "heartbeat",
.active_low = 0,
},
};
static struct gpio_led_platform_data cm_t3517_led_pdata = {
.num_leds = ARRAY_SIZE(cm_t3517_leds),
.leds = cm_t3517_leds,
};
static struct platform_device cm_t3517_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cm_t3517_led_pdata,
},
};
static void __init cm_t3517_init_leds(void)
{
platform_device_register(&cm_t3517_led_device);
}
#else
static inline void cm_t3517_init_leds(void) {}
#endif
#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE)
static struct resource cm_t3517_hecc_resources[] = {
{
.start = AM35XX_IPSS_HECC_BASE,
.end = AM35XX_IPSS_HECC_BASE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = INT_35XX_HECC0_IRQ,
.end = INT_35XX_HECC0_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct ti_hecc_platform_data cm_t3517_hecc_pdata = {
.scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET,
.scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET,
.hecc_ram_offset = AM35XX_HECC_RAM_OFFSET,
.mbx_offset = AM35XX_HECC_MBOX_OFFSET,
.int_line = AM35XX_HECC_INT_LINE,
.version = AM35XX_HECC_VERSION,
};
static struct platform_device cm_t3517_hecc_device = {
.name = "ti_hecc",
.id = 1,
.num_resources = ARRAY_SIZE(cm_t3517_hecc_resources),
.resource = cm_t3517_hecc_resources,
.dev = {
.platform_data = &cm_t3517_hecc_pdata,
},
};
static void cm_t3517_init_hecc(void)
{
platform_device_register(&cm_t3517_hecc_device);
}
#else
static inline void cm_t3517_init_hecc(void) {}
#endif
#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
#define RTC_IO_GPIO (153)
#define RTC_WR_GPIO (154)
#define RTC_RD_GPIO (53)
#define RTC_CS_GPIO (163)
#define RTC_CS_EN_GPIO (160)
struct v3020_platform_data cm_t3517_v3020_pdata = {
.use_gpio = 1,
.gpio_cs = RTC_CS_GPIO,
.gpio_wr = RTC_WR_GPIO,
.gpio_rd = RTC_RD_GPIO,
.gpio_io = RTC_IO_GPIO,
};
static struct platform_device cm_t3517_rtc_device = {
.name = "v3020",
.id = -1,
.dev = {
.platform_data = &cm_t3517_v3020_pdata,
}
};
static void __init cm_t3517_init_rtc(void)
{
int err;
err = gpio_request_one(RTC_CS_EN_GPIO, GPIOF_OUT_INIT_HIGH,
"rtc cs en");
if (err) {
pr_err("CM-T3517: rtc cs en gpio request failed: %d\n", err);
return;
}
platform_device_register(&cm_t3517_rtc_device);
}
#else
static inline void cm_t3517_init_rtc(void) {}
#endif
#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
#define HSUSB1_RESET_GPIO (146)
#define HSUSB2_RESET_GPIO (147)
#define USB_HUB_RESET_GPIO (152)
static struct usbhs_omap_board_data cm_t3517_ehci_pdata __initdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
.phy_reset = true,
.reset_gpio_port[0] = HSUSB1_RESET_GPIO,
.reset_gpio_port[1] = HSUSB2_RESET_GPIO,
.reset_gpio_port[2] = -EINVAL,
};
static int __init cm_t3517_init_usbh(void)
{
int err;
err = gpio_request_one(USB_HUB_RESET_GPIO, GPIOF_OUT_INIT_LOW,
"usb hub rst");
if (err) {
pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err);
} else {
udelay(10);
gpio_set_value(USB_HUB_RESET_GPIO, 1);
msleep(1);
}
usbhs_init(&cm_t3517_ehci_pdata);
return 0;
}
#else
static inline int cm_t3517_init_usbh(void)
{
return 0;
}
#endif
#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
static struct mtd_partition cm_t3517_nand_partitions[] = {
{
.name = "xloader",
.offset = 0, /* Offset = 0x00000 */
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE
},
{
.name = "uboot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 15 * NAND_BLOCK_SIZE,
},
{
.name = "uboot environment",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
.size = 2 * NAND_BLOCK_SIZE,
},
{
.name = "linux",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
.size = MTDPART_SIZ_FULL,
},
};
static struct omap_nand_platform_data cm_t3517_nand_data = {
.parts = cm_t3517_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.cs = 0,
};
static void __init cm_t3517_init_nand(void)
{
if (gpmc_nand_init(&cm_t3517_nand_data) < 0)
pr_err("CM-T3517: NAND initialization failed\n");
}
#else
static inline void cm_t3517_init_nand(void) {}
#endif
static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
};
static void __init cm_t3517_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
/* GPIO186 - Green LED */
OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* RTC GPIOs: */
/* IO - GPIO153 */
OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* WR# - GPIO154 */
OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* RD# - GPIO53 */
OMAP3_MUX(GPMC_NCS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* CS# - GPIO163 */
OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* CS EN - GPIO160 */
OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* HSUSB1 RESET */
OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* HSUSB2 RESET */
OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
/* CM-T3517 USB HUB nRESET */
OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#endif
static void __init cm_t3517_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
omap_board_config = cm_t3517_config;
omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
cm_t3517_init_leds();
cm_t3517_init_nand();
cm_t3517_init_rtc();
cm_t3517_init_usbh();
cm_t3517_init_hecc();
}
MACHINE_START(CM_T3517, "Compulab CM-T3517")
.boot_params = 0x80000100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = cm_t3517_init_early,
.init_irq = omap_init_irq,
.init_machine = cm_t3517_init,
.timer = &omap_timer,
MACHINE_END
| gpl-2.0 |
maxwen/primou-kernel-HTC | arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 2287 | 5012 | /*
* arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
*
* Marvell Orion-VoIP GE Reference Design Setup
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/ethtool.h>
#include <linux/i2c.h>
#include <net/dsa.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <mach/orion5x.h>
#include "common.h"
#include "mpp.h"
/*****************************************************************************
* RD-88F5181L GE Info
****************************************************************************/
/*
* 16M NOR flash Device bus boot chip select
*/
#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000
#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M
/*****************************************************************************
* 16M NOR Flash on Device bus Boot chip select
****************************************************************************/
static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
.width = 1,
};
static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
.flags = IORESOURCE_MEM,
.start = RD88F5181L_GE_NOR_BOOT_BASE,
.end = RD88F5181L_GE_NOR_BOOT_BASE +
RD88F5181L_GE_NOR_BOOT_SIZE - 1,
};
static struct platform_device rd88f5181l_ge_nor_boot_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &rd88f5181l_ge_nor_boot_flash_data,
},
.num_resources = 1,
.resource = &rd88f5181l_ge_nor_boot_flash_resource,
};
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
MPP0_GPIO, /* LED1 */
MPP1_GPIO, /* LED5 */
MPP2_GPIO, /* LED4 */
MPP3_GPIO, /* LED3 */
MPP4_GPIO, /* PCI_intA */
MPP5_GPIO, /* RTC interrupt */
MPP6_PCI_CLK, /* CPU PCI refclk */
MPP7_PCI_CLK, /* PCI/PCIe refclk */
MPP8_GPIO, /* 88e6131 interrupt */
MPP9_GPIO, /* GE_RXERR */
MPP10_GPIO, /* PCI_intB */
MPP11_GPIO, /* LED2 */
MPP12_GIGE, /* GE_TXD[4] */
MPP13_GIGE, /* GE_TXD[5] */
MPP14_GIGE, /* GE_TXD[6] */
MPP15_GIGE, /* GE_TXD[7] */
MPP16_GIGE, /* GE_RXD[4] */
MPP17_GIGE, /* GE_RXD[5] */
MPP18_GIGE, /* GE_RXD[6] */
MPP19_GIGE, /* GE_RXD[7] */
0,
};
static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
.phy_addr = MV643XX_ETH_PHY_NONE,
.speed = SPEED_1000,
.duplex = DUPLEX_FULL,
};
static struct dsa_chip_data rd88f5181l_ge_switch_chip_data = {
.port_names[0] = "lan2",
.port_names[1] = "lan1",
.port_names[2] = "wan",
.port_names[3] = "cpu",
.port_names[5] = "lan4",
.port_names[7] = "lan3",
};
static struct dsa_platform_data rd88f5181l_ge_switch_plat_data = {
.nr_chips = 1,
.chip = &rd88f5181l_ge_switch_chip_data,
};
static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
I2C_BOARD_INFO("ds1338", 0x68),
};
static void __init rd88f5181l_ge_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
/*
* Configure peripherals.
*/
orion5x_ehci0_init();
orion5x_eth_init(&rd88f5181l_ge_eth_data);
orion5x_eth_switch_init(&rd88f5181l_ge_switch_plat_data,
gpio_to_irq(8));
orion5x_i2c_init();
orion5x_uart0_init();
orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
RD88F5181L_GE_NOR_BOOT_SIZE);
platform_device_register(&rd88f5181l_ge_nor_boot_flash);
i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
}
static int __init
rd88f5181l_ge_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
/*
* Cardbus slot.
*/
if (pin == 1)
return gpio_to_irq(4);
else
return gpio_to_irq(10);
}
static struct hw_pci rd88f5181l_ge_pci __initdata = {
.nr_controllers = 2,
.swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = rd88f5181l_ge_pci_map_irq,
};
static int __init rd88f5181l_ge_pci_init(void)
{
if (machine_is_rd88f5181l_ge()) {
orion5x_pci_set_cardbus_mode();
pci_common_init(&rd88f5181l_ge_pci);
}
return 0;
}
subsys_initcall(rd88f5181l_ge_pci_init);
MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
.boot_params = 0x00000100,
.init_machine = rd88f5181l_ge_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.timer = &orion5x_timer,
.fixup = tag_fixup_mem32,
MACHINE_END
| gpl-2.0 |
hei1125/Nova_Kernel | net/dccp/ccids/ccid2.c | 2543 | 19459 | /*
* Copyright (c) 2005, 2006 Andrea Bittau <a.bittau@cs.ucl.ac.uk>
*
* Changes to meet Linux coding standards, and DCCP infrastructure fixes.
*
* Copyright (c) 2006 Arnaldo Carvalho de Melo <acme@conectiva.com.br>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* This implementation should follow RFC 4341
*/
#include <linux/slab.h>
#include "../feat.h"
#include "ccid2.h"
#ifdef CONFIG_IP_DCCP_CCID2_DEBUG
static int ccid2_debug;
#define ccid2_pr_debug(format, a...) DCCP_PR_DEBUG(ccid2_debug, format, ##a)
#else
#define ccid2_pr_debug(format, a...)
#endif
static int ccid2_hc_tx_alloc_seq(struct ccid2_hc_tx_sock *hc)
{
struct ccid2_seq *seqp;
int i;
/* check if we have space to preserve the pointer to the buffer */
if (hc->tx_seqbufc >= (sizeof(hc->tx_seqbuf) /
sizeof(struct ccid2_seq *)))
return -ENOMEM;
/* allocate buffer and initialize linked list */
seqp = kmalloc(CCID2_SEQBUF_LEN * sizeof(struct ccid2_seq), gfp_any());
if (seqp == NULL)
return -ENOMEM;
for (i = 0; i < (CCID2_SEQBUF_LEN - 1); i++) {
seqp[i].ccid2s_next = &seqp[i + 1];
seqp[i + 1].ccid2s_prev = &seqp[i];
}
seqp[CCID2_SEQBUF_LEN - 1].ccid2s_next = seqp;
seqp->ccid2s_prev = &seqp[CCID2_SEQBUF_LEN - 1];
/* This is the first allocation. Initiate the head and tail. */
if (hc->tx_seqbufc == 0)
hc->tx_seqh = hc->tx_seqt = seqp;
else {
/* link the existing list with the one we just created */
hc->tx_seqh->ccid2s_next = seqp;
seqp->ccid2s_prev = hc->tx_seqh;
hc->tx_seqt->ccid2s_prev = &seqp[CCID2_SEQBUF_LEN - 1];
seqp[CCID2_SEQBUF_LEN - 1].ccid2s_next = hc->tx_seqt;
}
/* store the original pointer to the buffer so we can free it */
hc->tx_seqbuf[hc->tx_seqbufc] = seqp;
hc->tx_seqbufc++;
return 0;
}
static int ccid2_hc_tx_send_packet(struct sock *sk, struct sk_buff *skb)
{
if (ccid2_cwnd_network_limited(ccid2_hc_tx_sk(sk)))
return CCID_PACKET_WILL_DEQUEUE_LATER;
return CCID_PACKET_SEND_AT_ONCE;
}
static void ccid2_change_l_ack_ratio(struct sock *sk, u32 val)
{
struct dccp_sock *dp = dccp_sk(sk);
u32 max_ratio = DIV_ROUND_UP(ccid2_hc_tx_sk(sk)->tx_cwnd, 2);
/*
* Ensure that Ack Ratio does not exceed ceil(cwnd/2), which is (2) from
* RFC 4341, 6.1.2. We ignore the statement that Ack Ratio 2 is always
* acceptable since this causes starvation/deadlock whenever cwnd < 2.
* The same problem arises when Ack Ratio is 0 (ie. Ack Ratio disabled).
*/
if (val == 0 || val > max_ratio) {
DCCP_WARN("Limiting Ack Ratio (%u) to %u\n", val, max_ratio);
val = max_ratio;
}
if (val > DCCPF_ACK_RATIO_MAX)
val = DCCPF_ACK_RATIO_MAX;
if (val == dp->dccps_l_ack_ratio)
return;
ccid2_pr_debug("changing local ack ratio to %u\n", val);
dp->dccps_l_ack_ratio = val;
}
static void ccid2_hc_tx_rto_expire(unsigned long data)
{
struct sock *sk = (struct sock *)data;
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
const bool sender_was_blocked = ccid2_cwnd_network_limited(hc);
bh_lock_sock(sk);
if (sock_owned_by_user(sk)) {
sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + HZ / 5);
goto out;
}
ccid2_pr_debug("RTO_EXPIRE\n");
/* back-off timer */
hc->tx_rto <<= 1;
if (hc->tx_rto > DCCP_RTO_MAX)
hc->tx_rto = DCCP_RTO_MAX;
/* adjust pipe, cwnd etc */
hc->tx_ssthresh = hc->tx_cwnd / 2;
if (hc->tx_ssthresh < 2)
hc->tx_ssthresh = 2;
hc->tx_cwnd = 1;
hc->tx_pipe = 0;
/* clear state about stuff we sent */
hc->tx_seqt = hc->tx_seqh;
hc->tx_packets_acked = 0;
/* clear ack ratio state. */
hc->tx_rpseq = 0;
hc->tx_rpdupack = -1;
ccid2_change_l_ack_ratio(sk, 1);
/* if we were blocked before, we may now send cwnd=1 packet */
if (sender_was_blocked)
tasklet_schedule(&dccp_sk(sk)->dccps_xmitlet);
/* restart backed-off timer */
sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);
out:
bh_unlock_sock(sk);
sock_put(sk);
}
static void ccid2_hc_tx_packet_sent(struct sock *sk, unsigned int len)
{
struct dccp_sock *dp = dccp_sk(sk);
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
struct ccid2_seq *next;
hc->tx_pipe++;
hc->tx_seqh->ccid2s_seq = dp->dccps_gss;
hc->tx_seqh->ccid2s_acked = 0;
hc->tx_seqh->ccid2s_sent = ccid2_time_stamp;
next = hc->tx_seqh->ccid2s_next;
/* check if we need to alloc more space */
if (next == hc->tx_seqt) {
if (ccid2_hc_tx_alloc_seq(hc)) {
DCCP_CRIT("packet history - out of memory!");
/* FIXME: find a more graceful way to bail out */
return;
}
next = hc->tx_seqh->ccid2s_next;
BUG_ON(next == hc->tx_seqt);
}
hc->tx_seqh = next;
ccid2_pr_debug("cwnd=%d pipe=%d\n", hc->tx_cwnd, hc->tx_pipe);
/*
* FIXME: The code below is broken and the variables have been removed
* from the socket struct. The `ackloss' variable was always set to 0,
* and with arsent there are several problems:
* (i) it doesn't just count the number of Acks, but all sent packets;
* (ii) it is expressed in # of packets, not # of windows, so the
* comparison below uses the wrong formula: Appendix A of RFC 4341
* comes up with the number K = cwnd / (R^2 - R) of consecutive windows
* of data with no lost or marked Ack packets. If arsent were the # of
* consecutive Acks received without loss, then Ack Ratio needs to be
* decreased by 1 when
* arsent >= K * cwnd / R = cwnd^2 / (R^3 - R^2)
* where cwnd / R is the number of Acks received per window of data
* (cf. RFC 4341, App. A). The problems are that
* - arsent counts other packets as well;
* - the comparison uses a formula different from RFC 4341;
* - computing a cubic/quadratic equation each time is too complicated.
* Hence a different algorithm is needed.
*/
#if 0
/* Ack Ratio. Need to maintain a concept of how many windows we sent */
hc->tx_arsent++;
/* We had an ack loss in this window... */
if (hc->tx_ackloss) {
if (hc->tx_arsent >= hc->tx_cwnd) {
hc->tx_arsent = 0;
hc->tx_ackloss = 0;
}
} else {
/* No acks lost up to now... */
/* decrease ack ratio if enough packets were sent */
if (dp->dccps_l_ack_ratio > 1) {
/* XXX don't calculate denominator each time */
int denom = dp->dccps_l_ack_ratio * dp->dccps_l_ack_ratio -
dp->dccps_l_ack_ratio;
denom = hc->tx_cwnd * hc->tx_cwnd / denom;
if (hc->tx_arsent >= denom) {
ccid2_change_l_ack_ratio(sk, dp->dccps_l_ack_ratio - 1);
hc->tx_arsent = 0;
}
} else {
/* we can't increase ack ratio further [1] */
hc->tx_arsent = 0; /* or maybe set it to cwnd*/
}
}
#endif
sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);
#ifdef CONFIG_IP_DCCP_CCID2_DEBUG
do {
struct ccid2_seq *seqp = hc->tx_seqt;
while (seqp != hc->tx_seqh) {
ccid2_pr_debug("out seq=%llu acked=%d time=%u\n",
(unsigned long long)seqp->ccid2s_seq,
seqp->ccid2s_acked, seqp->ccid2s_sent);
seqp = seqp->ccid2s_next;
}
} while (0);
ccid2_pr_debug("=========\n");
#endif
}
/**
* ccid2_rtt_estimator - Sample RTT and compute RTO using RFC2988 algorithm
* This code is almost identical with TCP's tcp_rtt_estimator(), since
* - it has a higher sampling frequency (recommended by RFC 1323),
* - the RTO does not collapse into RTT due to RTTVAR going towards zero,
* - it is simple (cf. more complex proposals such as Eifel timer or research
* which suggests that the gain should be set according to window size),
* - in tests it was found to work well with CCID2 [gerrit].
*/
static void ccid2_rtt_estimator(struct sock *sk, const long mrtt)
{
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
long m = mrtt ? : 1;
if (hc->tx_srtt == 0) {
/* First measurement m */
hc->tx_srtt = m << 3;
hc->tx_mdev = m << 1;
hc->tx_mdev_max = max(hc->tx_mdev, tcp_rto_min(sk));
hc->tx_rttvar = hc->tx_mdev_max;
hc->tx_rtt_seq = dccp_sk(sk)->dccps_gss;
} else {
/* Update scaled SRTT as SRTT += 1/8 * (m - SRTT) */
m -= (hc->tx_srtt >> 3);
hc->tx_srtt += m;
/* Similarly, update scaled mdev with regard to |m| */
if (m < 0) {
m = -m;
m -= (hc->tx_mdev >> 2);
/*
* This neutralises RTO increase when RTT < SRTT - mdev
* (see P. Sarolahti, A. Kuznetsov,"Congestion Control
* in Linux TCP", USENIX 2002, pp. 49-62).
*/
if (m > 0)
m >>= 3;
} else {
m -= (hc->tx_mdev >> 2);
}
hc->tx_mdev += m;
if (hc->tx_mdev > hc->tx_mdev_max) {
hc->tx_mdev_max = hc->tx_mdev;
if (hc->tx_mdev_max > hc->tx_rttvar)
hc->tx_rttvar = hc->tx_mdev_max;
}
/*
* Decay RTTVAR at most once per flight, exploiting that
* 1) pipe <= cwnd <= Sequence_Window = W (RFC 4340, 7.5.2)
* 2) AWL = GSS-W+1 <= GAR <= GSS (RFC 4340, 7.5.1)
* GAR is a useful bound for FlightSize = pipe.
* AWL is probably too low here, as it over-estimates pipe.
*/
if (after48(dccp_sk(sk)->dccps_gar, hc->tx_rtt_seq)) {
if (hc->tx_mdev_max < hc->tx_rttvar)
hc->tx_rttvar -= (hc->tx_rttvar -
hc->tx_mdev_max) >> 2;
hc->tx_rtt_seq = dccp_sk(sk)->dccps_gss;
hc->tx_mdev_max = tcp_rto_min(sk);
}
}
/*
* Set RTO from SRTT and RTTVAR
* As in TCP, 4 * RTTVAR >= TCP_RTO_MIN, giving a minimum RTO of 200 ms.
* This agrees with RFC 4341, 5:
* "Because DCCP does not retransmit data, DCCP does not require
* TCP's recommended minimum timeout of one second".
*/
hc->tx_rto = (hc->tx_srtt >> 3) + hc->tx_rttvar;
if (hc->tx_rto > DCCP_RTO_MAX)
hc->tx_rto = DCCP_RTO_MAX;
}
static void ccid2_new_ack(struct sock *sk, struct ccid2_seq *seqp,
unsigned int *maxincr)
{
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
if (hc->tx_cwnd < hc->tx_ssthresh) {
if (*maxincr > 0 && ++hc->tx_packets_acked == 2) {
hc->tx_cwnd += 1;
*maxincr -= 1;
hc->tx_packets_acked = 0;
}
} else if (++hc->tx_packets_acked >= hc->tx_cwnd) {
hc->tx_cwnd += 1;
hc->tx_packets_acked = 0;
}
/*
* FIXME: RTT is sampled several times per acknowledgment (for each
* entry in the Ack Vector), instead of once per Ack (as in TCP SACK).
* This causes the RTT to be over-estimated, since the older entries
* in the Ack Vector have earlier sending times.
* The cleanest solution is to not use the ccid2s_sent field at all
* and instead use DCCP timestamps: requires changes in other places.
*/
ccid2_rtt_estimator(sk, ccid2_time_stamp - seqp->ccid2s_sent);
}
static void ccid2_congestion_event(struct sock *sk, struct ccid2_seq *seqp)
{
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
if ((s32)(seqp->ccid2s_sent - hc->tx_last_cong) < 0) {
ccid2_pr_debug("Multiple losses in an RTT---treating as one\n");
return;
}
hc->tx_last_cong = ccid2_time_stamp;
hc->tx_cwnd = hc->tx_cwnd / 2 ? : 1U;
hc->tx_ssthresh = max(hc->tx_cwnd, 2U);
/* Avoid spurious timeouts resulting from Ack Ratio > cwnd */
if (dccp_sk(sk)->dccps_l_ack_ratio > hc->tx_cwnd)
ccid2_change_l_ack_ratio(sk, hc->tx_cwnd);
}
static int ccid2_hc_tx_parse_options(struct sock *sk, u8 packet_type,
u8 option, u8 *optval, u8 optlen)
{
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
switch (option) {
case DCCPO_ACK_VECTOR_0:
case DCCPO_ACK_VECTOR_1:
return dccp_ackvec_parsed_add(&hc->tx_av_chunks, optval, optlen,
option - DCCPO_ACK_VECTOR_0);
}
return 0;
}
static void ccid2_hc_tx_packet_recv(struct sock *sk, struct sk_buff *skb)
{
struct dccp_sock *dp = dccp_sk(sk);
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
const bool sender_was_blocked = ccid2_cwnd_network_limited(hc);
struct dccp_ackvec_parsed *avp;
u64 ackno, seqno;
struct ccid2_seq *seqp;
int done = 0;
unsigned int maxincr = 0;
/* check reverse path congestion */
seqno = DCCP_SKB_CB(skb)->dccpd_seq;
/* XXX this whole "algorithm" is broken. Need to fix it to keep track
* of the seqnos of the dupacks so that rpseq and rpdupack are correct
* -sorbo.
*/
/* need to bootstrap */
if (hc->tx_rpdupack == -1) {
hc->tx_rpdupack = 0;
hc->tx_rpseq = seqno;
} else {
/* check if packet is consecutive */
if (dccp_delta_seqno(hc->tx_rpseq, seqno) == 1)
hc->tx_rpseq = seqno;
/* it's a later packet */
else if (after48(seqno, hc->tx_rpseq)) {
hc->tx_rpdupack++;
/* check if we got enough dupacks */
if (hc->tx_rpdupack >= NUMDUPACK) {
hc->tx_rpdupack = -1; /* XXX lame */
hc->tx_rpseq = 0;
ccid2_change_l_ack_ratio(sk, 2 * dp->dccps_l_ack_ratio);
}
}
}
/* check forward path congestion */
if (dccp_packet_without_ack(skb))
return;
/* still didn't send out new data packets */
if (hc->tx_seqh == hc->tx_seqt)
goto done;
ackno = DCCP_SKB_CB(skb)->dccpd_ack_seq;
if (after48(ackno, hc->tx_high_ack))
hc->tx_high_ack = ackno;
seqp = hc->tx_seqt;
while (before48(seqp->ccid2s_seq, ackno)) {
seqp = seqp->ccid2s_next;
if (seqp == hc->tx_seqh) {
seqp = hc->tx_seqh->ccid2s_prev;
break;
}
}
/*
* In slow-start, cwnd can increase up to a maximum of Ack Ratio/2
* packets per acknowledgement. Rounding up avoids that cwnd is not
* advanced when Ack Ratio is 1 and gives a slight edge otherwise.
*/
if (hc->tx_cwnd < hc->tx_ssthresh)
maxincr = DIV_ROUND_UP(dp->dccps_l_ack_ratio, 2);
/* go through all ack vectors */
list_for_each_entry(avp, &hc->tx_av_chunks, node) {
/* go through this ack vector */
for (; avp->len--; avp->vec++) {
u64 ackno_end_rl = SUB48(ackno,
dccp_ackvec_runlen(avp->vec));
ccid2_pr_debug("ackvec %llu |%u,%u|\n",
(unsigned long long)ackno,
dccp_ackvec_state(avp->vec) >> 6,
dccp_ackvec_runlen(avp->vec));
/* if the seqno we are analyzing is larger than the
* current ackno, then move towards the tail of our
* seqnos.
*/
while (after48(seqp->ccid2s_seq, ackno)) {
if (seqp == hc->tx_seqt) {
done = 1;
break;
}
seqp = seqp->ccid2s_prev;
}
if (done)
break;
/* check all seqnos in the range of the vector
* run length
*/
while (between48(seqp->ccid2s_seq,ackno_end_rl,ackno)) {
const u8 state = dccp_ackvec_state(avp->vec);
/* new packet received or marked */
if (state != DCCPAV_NOT_RECEIVED &&
!seqp->ccid2s_acked) {
if (state == DCCPAV_ECN_MARKED)
ccid2_congestion_event(sk,
seqp);
else
ccid2_new_ack(sk, seqp,
&maxincr);
seqp->ccid2s_acked = 1;
ccid2_pr_debug("Got ack for %llu\n",
(unsigned long long)seqp->ccid2s_seq);
hc->tx_pipe--;
}
if (seqp == hc->tx_seqt) {
done = 1;
break;
}
seqp = seqp->ccid2s_prev;
}
if (done)
break;
ackno = SUB48(ackno_end_rl, 1);
}
if (done)
break;
}
/* The state about what is acked should be correct now
* Check for NUMDUPACK
*/
seqp = hc->tx_seqt;
while (before48(seqp->ccid2s_seq, hc->tx_high_ack)) {
seqp = seqp->ccid2s_next;
if (seqp == hc->tx_seqh) {
seqp = hc->tx_seqh->ccid2s_prev;
break;
}
}
done = 0;
while (1) {
if (seqp->ccid2s_acked) {
done++;
if (done == NUMDUPACK)
break;
}
if (seqp == hc->tx_seqt)
break;
seqp = seqp->ccid2s_prev;
}
/* If there are at least 3 acknowledgements, anything unacknowledged
* below the last sequence number is considered lost
*/
if (done == NUMDUPACK) {
struct ccid2_seq *last_acked = seqp;
/* check for lost packets */
while (1) {
if (!seqp->ccid2s_acked) {
ccid2_pr_debug("Packet lost: %llu\n",
(unsigned long long)seqp->ccid2s_seq);
/* XXX need to traverse from tail -> head in
* order to detect multiple congestion events in
* one ack vector.
*/
ccid2_congestion_event(sk, seqp);
hc->tx_pipe--;
}
if (seqp == hc->tx_seqt)
break;
seqp = seqp->ccid2s_prev;
}
hc->tx_seqt = last_acked;
}
/* trim acked packets in tail */
while (hc->tx_seqt != hc->tx_seqh) {
if (!hc->tx_seqt->ccid2s_acked)
break;
hc->tx_seqt = hc->tx_seqt->ccid2s_next;
}
/* restart RTO timer if not all outstanding data has been acked */
if (hc->tx_pipe == 0)
sk_stop_timer(sk, &hc->tx_rtotimer);
else
sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);
done:
/* check if incoming Acks allow pending packets to be sent */
if (sender_was_blocked && !ccid2_cwnd_network_limited(hc))
tasklet_schedule(&dccp_sk(sk)->dccps_xmitlet);
dccp_ackvec_parsed_cleanup(&hc->tx_av_chunks);
}
/*
* Convert RFC 3390 larger initial window into an equivalent number of packets.
* This is based on the numbers specified in RFC 5681, 3.1.
*/
static inline u32 rfc3390_bytes_to_packets(const u32 smss)
{
return smss <= 1095 ? 4 : (smss > 2190 ? 2 : 3);
}
static int ccid2_hc_tx_init(struct ccid *ccid, struct sock *sk)
{
struct ccid2_hc_tx_sock *hc = ccid_priv(ccid);
struct dccp_sock *dp = dccp_sk(sk);
u32 max_ratio;
/* RFC 4341, 5: initialise ssthresh to arbitrarily high (max) value */
hc->tx_ssthresh = ~0U;
/* Use larger initial windows (RFC 4341, section 5). */
hc->tx_cwnd = rfc3390_bytes_to_packets(dp->dccps_mss_cache);
/* Make sure that Ack Ratio is enabled and within bounds. */
max_ratio = DIV_ROUND_UP(hc->tx_cwnd, 2);
if (dp->dccps_l_ack_ratio == 0 || dp->dccps_l_ack_ratio > max_ratio)
dp->dccps_l_ack_ratio = max_ratio;
/* XXX init ~ to window size... */
if (ccid2_hc_tx_alloc_seq(hc))
return -ENOMEM;
hc->tx_rto = DCCP_TIMEOUT_INIT;
hc->tx_rpdupack = -1;
hc->tx_last_cong = ccid2_time_stamp;
setup_timer(&hc->tx_rtotimer, ccid2_hc_tx_rto_expire,
(unsigned long)sk);
INIT_LIST_HEAD(&hc->tx_av_chunks);
return 0;
}
static void ccid2_hc_tx_exit(struct sock *sk)
{
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
int i;
sk_stop_timer(sk, &hc->tx_rtotimer);
for (i = 0; i < hc->tx_seqbufc; i++)
kfree(hc->tx_seqbuf[i]);
hc->tx_seqbufc = 0;
}
static void ccid2_hc_rx_packet_recv(struct sock *sk, struct sk_buff *skb)
{
const struct dccp_sock *dp = dccp_sk(sk);
struct ccid2_hc_rx_sock *hc = ccid2_hc_rx_sk(sk);
switch (DCCP_SKB_CB(skb)->dccpd_type) {
case DCCP_PKT_DATA:
case DCCP_PKT_DATAACK:
hc->rx_data++;
if (hc->rx_data >= dp->dccps_r_ack_ratio) {
dccp_send_ack(sk);
hc->rx_data = 0;
}
break;
}
}
struct ccid_operations ccid2_ops = {
.ccid_id = DCCPC_CCID2,
.ccid_name = "TCP-like",
.ccid_hc_tx_obj_size = sizeof(struct ccid2_hc_tx_sock),
.ccid_hc_tx_init = ccid2_hc_tx_init,
.ccid_hc_tx_exit = ccid2_hc_tx_exit,
.ccid_hc_tx_send_packet = ccid2_hc_tx_send_packet,
.ccid_hc_tx_packet_sent = ccid2_hc_tx_packet_sent,
.ccid_hc_tx_parse_options = ccid2_hc_tx_parse_options,
.ccid_hc_tx_packet_recv = ccid2_hc_tx_packet_recv,
.ccid_hc_rx_obj_size = sizeof(struct ccid2_hc_rx_sock),
.ccid_hc_rx_packet_recv = ccid2_hc_rx_packet_recv,
};
#ifdef CONFIG_IP_DCCP_CCID2_DEBUG
module_param(ccid2_debug, bool, 0644);
MODULE_PARM_DESC(ccid2_debug, "Enable CCID-2 debug messages");
#endif
| gpl-2.0 |
CyanogenMod/android_kernel_sony_tianchi | arch/mn10300/kernel/mn10300-serial.c | 4591 | 42503 | /* MN10300 On-chip serial port UART driver
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
static const char serial_name[] = "MN10300 Serial driver";
static const char serial_version[] = "mn10300_serial-1.0";
static const char serial_revdate[] = "2007-11-06";
#if defined(CONFIG_MN10300_TTYSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif
#include <linux/module.h>
#include <linux/serial.h>
#include <linux/circ_buf.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/bitops.h>
#include <asm/serial-regs.h>
#include <unit/timex.h>
#include "mn10300-serial.h"
#ifdef CONFIG_SMP
#undef GxICR
#define GxICR(X) CROSS_GxICR(X, 0)
#endif /* CONFIG_SMP */
#define kenter(FMT, ...) \
printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
#define _enter(FMT, ...) \
no_printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
#define kdebug(FMT, ...) \
printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
#define _debug(FMT, ...) \
no_printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
#define kproto(FMT, ...) \
printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
#define _proto(FMT, ...) \
no_printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
#ifndef CODMSB
/* c_cflag bit meaning */
#define CODMSB 004000000000 /* change Transfer bit-order */
#endif
#define NR_UARTS 3
#ifdef CONFIG_MN10300_TTYSM_CONSOLE
static void mn10300_serial_console_write(struct console *co,
const char *s, unsigned count);
static int __init mn10300_serial_console_setup(struct console *co,
char *options);
static struct uart_driver mn10300_serial_driver;
static struct console mn10300_serial_console = {
.name = "ttySM",
.write = mn10300_serial_console_write,
.device = uart_console_device,
.setup = mn10300_serial_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &mn10300_serial_driver,
};
#endif
static struct uart_driver mn10300_serial_driver = {
.owner = NULL,
.driver_name = "mn10300-serial",
.dev_name = "ttySM",
.major = TTY_MAJOR,
.minor = 128,
.nr = NR_UARTS,
#ifdef CONFIG_MN10300_TTYSM_CONSOLE
.cons = &mn10300_serial_console,
#endif
};
static unsigned int mn10300_serial_tx_empty(struct uart_port *);
static void mn10300_serial_set_mctrl(struct uart_port *, unsigned int mctrl);
static unsigned int mn10300_serial_get_mctrl(struct uart_port *);
static void mn10300_serial_stop_tx(struct uart_port *);
static void mn10300_serial_start_tx(struct uart_port *);
static void mn10300_serial_send_xchar(struct uart_port *, char ch);
static void mn10300_serial_stop_rx(struct uart_port *);
static void mn10300_serial_enable_ms(struct uart_port *);
static void mn10300_serial_break_ctl(struct uart_port *, int ctl);
static int mn10300_serial_startup(struct uart_port *);
static void mn10300_serial_shutdown(struct uart_port *);
static void mn10300_serial_set_termios(struct uart_port *,
struct ktermios *new,
struct ktermios *old);
static const char *mn10300_serial_type(struct uart_port *);
static void mn10300_serial_release_port(struct uart_port *);
static int mn10300_serial_request_port(struct uart_port *);
static void mn10300_serial_config_port(struct uart_port *, int);
static int mn10300_serial_verify_port(struct uart_port *,
struct serial_struct *);
#ifdef CONFIG_CONSOLE_POLL
static void mn10300_serial_poll_put_char(struct uart_port *, unsigned char);
static int mn10300_serial_poll_get_char(struct uart_port *);
#endif
static const struct uart_ops mn10300_serial_ops = {
.tx_empty = mn10300_serial_tx_empty,
.set_mctrl = mn10300_serial_set_mctrl,
.get_mctrl = mn10300_serial_get_mctrl,
.stop_tx = mn10300_serial_stop_tx,
.start_tx = mn10300_serial_start_tx,
.send_xchar = mn10300_serial_send_xchar,
.stop_rx = mn10300_serial_stop_rx,
.enable_ms = mn10300_serial_enable_ms,
.break_ctl = mn10300_serial_break_ctl,
.startup = mn10300_serial_startup,
.shutdown = mn10300_serial_shutdown,
.set_termios = mn10300_serial_set_termios,
.type = mn10300_serial_type,
.release_port = mn10300_serial_release_port,
.request_port = mn10300_serial_request_port,
.config_port = mn10300_serial_config_port,
.verify_port = mn10300_serial_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_put_char = mn10300_serial_poll_put_char,
.poll_get_char = mn10300_serial_poll_get_char,
#endif
};
static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id);
/*
* the first on-chip serial port: ttySM0 (aka SIF0)
*/
#ifdef CONFIG_MN10300_TTYSM0
struct mn10300_serial_port mn10300_serial_port_sif0 = {
.uart.ops = &mn10300_serial_ops,
.uart.membase = (void __iomem *) &SC0CTR,
.uart.mapbase = (unsigned long) &SC0CTR,
.uart.iotype = UPIO_MEM,
.uart.irq = 0,
.uart.uartclk = 0, /* MN10300_IOCLK, */
.uart.fifosize = 1,
.uart.flags = UPF_BOOT_AUTOCONF,
.uart.line = 0,
.uart.type = PORT_MN10300,
.uart.lock =
__SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif0.uart.lock),
.name = "ttySM0",
._iobase = &SC0CTR,
._control = &SC0CTR,
._status = (volatile u8 *)&SC0STR,
._intr = &SC0ICR,
._rxb = &SC0RXB,
._txb = &SC0TXB,
.rx_name = "ttySM0:Rx",
.tx_name = "ttySM0:Tx",
#if defined(CONFIG_MN10300_TTYSM0_TIMER8)
.tm_name = "ttySM0:Timer8",
._tmxmd = &TM8MD,
._tmxbr = &TM8BR,
._tmicr = &TM8ICR,
.tm_irq = TM8IRQ,
.div_timer = MNSCx_DIV_TIMER_16BIT,
#elif defined(CONFIG_MN10300_TTYSM0_TIMER0)
.tm_name = "ttySM0:Timer0",
._tmxmd = &TM0MD,
._tmxbr = (volatile u16 *)&TM0BR,
._tmicr = &TM0ICR,
.tm_irq = TM0IRQ,
.div_timer = MNSCx_DIV_TIMER_8BIT,
#elif defined(CONFIG_MN10300_TTYSM0_TIMER2)
.tm_name = "ttySM0:Timer2",
._tmxmd = &TM2MD,
._tmxbr = (volatile u16 *)&TM2BR,
._tmicr = &TM2ICR,
.tm_irq = TM2IRQ,
.div_timer = MNSCx_DIV_TIMER_8BIT,
#else
#error "Unknown config for ttySM0"
#endif
.rx_irq = SC0RXIRQ,
.tx_irq = SC0TXIRQ,
.rx_icr = &GxICR(SC0RXIRQ),
.tx_icr = &GxICR(SC0TXIRQ),
.clock_src = MNSCx_CLOCK_SRC_IOCLK,
.options = 0,
#ifdef CONFIG_GDBSTUB_ON_TTYSM0
.gdbstub = 1,
#endif
};
#endif /* CONFIG_MN10300_TTYSM0 */
/*
* the second on-chip serial port: ttySM1 (aka SIF1)
*/
#ifdef CONFIG_MN10300_TTYSM1
struct mn10300_serial_port mn10300_serial_port_sif1 = {
.uart.ops = &mn10300_serial_ops,
.uart.membase = (void __iomem *) &SC1CTR,
.uart.mapbase = (unsigned long) &SC1CTR,
.uart.iotype = UPIO_MEM,
.uart.irq = 0,
.uart.uartclk = 0, /* MN10300_IOCLK, */
.uart.fifosize = 1,
.uart.flags = UPF_BOOT_AUTOCONF,
.uart.line = 1,
.uart.type = PORT_MN10300,
.uart.lock =
__SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif1.uart.lock),
.name = "ttySM1",
._iobase = &SC1CTR,
._control = &SC1CTR,
._status = (volatile u8 *)&SC1STR,
._intr = &SC1ICR,
._rxb = &SC1RXB,
._txb = &SC1TXB,
.rx_name = "ttySM1:Rx",
.tx_name = "ttySM1:Tx",
#if defined(CONFIG_MN10300_TTYSM1_TIMER9)
.tm_name = "ttySM1:Timer9",
._tmxmd = &TM9MD,
._tmxbr = &TM9BR,
._tmicr = &TM9ICR,
.tm_irq = TM9IRQ,
.div_timer = MNSCx_DIV_TIMER_16BIT,
#elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
.tm_name = "ttySM1:Timer3",
._tmxmd = &TM3MD,
._tmxbr = (volatile u16 *)&TM3BR,
._tmicr = &TM3ICR,
.tm_irq = TM3IRQ,
.div_timer = MNSCx_DIV_TIMER_8BIT,
#elif defined(CONFIG_MN10300_TTYSM1_TIMER12)
.tm_name = "ttySM1/Timer12",
._tmxmd = &TM12MD,
._tmxbr = &TM12BR,
._tmicr = &TM12ICR,
.tm_irq = TM12IRQ,
.div_timer = MNSCx_DIV_TIMER_16BIT,
#else
#error "Unknown config for ttySM1"
#endif
.rx_irq = SC1RXIRQ,
.tx_irq = SC1TXIRQ,
.rx_icr = &GxICR(SC1RXIRQ),
.tx_icr = &GxICR(SC1TXIRQ),
.clock_src = MNSCx_CLOCK_SRC_IOCLK,
.options = 0,
#ifdef CONFIG_GDBSTUB_ON_TTYSM1
.gdbstub = 1,
#endif
};
#endif /* CONFIG_MN10300_TTYSM1 */
/*
* the third on-chip serial port: ttySM2 (aka SIF2)
*/
#ifdef CONFIG_MN10300_TTYSM2
struct mn10300_serial_port mn10300_serial_port_sif2 = {
.uart.ops = &mn10300_serial_ops,
.uart.membase = (void __iomem *) &SC2CTR,
.uart.mapbase = (unsigned long) &SC2CTR,
.uart.iotype = UPIO_MEM,
.uart.irq = 0,
.uart.uartclk = 0, /* MN10300_IOCLK, */
.uart.fifosize = 1,
.uart.flags = UPF_BOOT_AUTOCONF,
.uart.line = 2,
#ifdef CONFIG_MN10300_TTYSM2_CTS
.uart.type = PORT_MN10300_CTS,
#else
.uart.type = PORT_MN10300,
#endif
.uart.lock =
__SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock),
.name = "ttySM2",
._iobase = &SC2CTR,
._control = &SC2CTR,
._status = (volatile u8 *)&SC2STR,
._intr = &SC2ICR,
._rxb = &SC2RXB,
._txb = &SC2TXB,
.rx_name = "ttySM2:Rx",
.tx_name = "ttySM2:Tx",
#if defined(CONFIG_MN10300_TTYSM2_TIMER10)
.tm_name = "ttySM2/Timer10",
._tmxmd = &TM10MD,
._tmxbr = &TM10BR,
._tmicr = &TM10ICR,
.tm_irq = TM10IRQ,
.div_timer = MNSCx_DIV_TIMER_16BIT,
#elif defined(CONFIG_MN10300_TTYSM2_TIMER9)
.tm_name = "ttySM2/Timer9",
._tmxmd = &TM9MD,
._tmxbr = &TM9BR,
._tmicr = &TM9ICR,
.tm_irq = TM9IRQ,
.div_timer = MNSCx_DIV_TIMER_16BIT,
#elif defined(CONFIG_MN10300_TTYSM2_TIMER1)
.tm_name = "ttySM2/Timer1",
._tmxmd = &TM1MD,
._tmxbr = (volatile u16 *)&TM1BR,
._tmicr = &TM1ICR,
.tm_irq = TM1IRQ,
.div_timer = MNSCx_DIV_TIMER_8BIT,
#elif defined(CONFIG_MN10300_TTYSM2_TIMER3)
.tm_name = "ttySM2/Timer3",
._tmxmd = &TM3MD,
._tmxbr = (volatile u16 *)&TM3BR,
._tmicr = &TM3ICR,
.tm_irq = TM3IRQ,
.div_timer = MNSCx_DIV_TIMER_8BIT,
#else
#error "Unknown config for ttySM2"
#endif
.rx_irq = SC2RXIRQ,
.tx_irq = SC2TXIRQ,
.rx_icr = &GxICR(SC2RXIRQ),
.tx_icr = &GxICR(SC2TXIRQ),
.clock_src = MNSCx_CLOCK_SRC_IOCLK,
#ifdef CONFIG_MN10300_TTYSM2_CTS
.options = MNSCx_OPT_CTS,
#else
.options = 0,
#endif
#ifdef CONFIG_GDBSTUB_ON_TTYSM2
.gdbstub = 1,
#endif
};
#endif /* CONFIG_MN10300_TTYSM2 */
/*
* list of available serial ports
*/
struct mn10300_serial_port *mn10300_serial_ports[NR_UARTS + 1] = {
#ifdef CONFIG_MN10300_TTYSM0
[0] = &mn10300_serial_port_sif0,
#endif
#ifdef CONFIG_MN10300_TTYSM1
[1] = &mn10300_serial_port_sif1,
#endif
#ifdef CONFIG_MN10300_TTYSM2
[2] = &mn10300_serial_port_sif2,
#endif
[NR_UARTS] = NULL,
};
/*
* we abuse the serial ports' baud timers' interrupt lines to get the ability
* to deliver interrupts to userspace as we use the ports' interrupt lines to
* do virtual DMA on account of the ports having no hardware FIFOs
*
* we can generate an interrupt manually in the assembly stubs by writing to
* the enable and detect bits in the interrupt control register, so all we need
* to do here is disable the interrupt line
*
* note that we can't just leave the line enabled as the baud rate timer *also*
* generates interrupts
*/
static void mn10300_serial_mask_ack(unsigned int irq)
{
unsigned long flags;
u16 tmp;
flags = arch_local_cli_save();
GxICR(irq) = GxICR_LEVEL_6;
tmp = GxICR(irq); /* flush write buffer */
arch_local_irq_restore(flags);
}
static void mn10300_serial_chip_mask_ack(struct irq_data *d)
{
mn10300_serial_mask_ack(d->irq);
}
static void mn10300_serial_nop(struct irq_data *d)
{
}
static struct irq_chip mn10300_serial_pic = {
.name = "mnserial",
.irq_ack = mn10300_serial_chip_mask_ack,
.irq_mask = mn10300_serial_chip_mask_ack,
.irq_mask_ack = mn10300_serial_chip_mask_ack,
.irq_unmask = mn10300_serial_nop,
};
/*
* serial virtual DMA interrupt jump table
*/
struct mn10300_serial_int mn10300_serial_int_tbl[NR_IRQS];
static void mn10300_serial_dis_tx_intr(struct mn10300_serial_port *port)
{
unsigned long flags;
u16 x;
flags = arch_local_cli_save();
*port->tx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
x = *port->tx_icr;
arch_local_irq_restore(flags);
}
static void mn10300_serial_en_tx_intr(struct mn10300_serial_port *port)
{
unsigned long flags;
u16 x;
flags = arch_local_cli_save();
*port->tx_icr =
NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL) | GxICR_ENABLE;
x = *port->tx_icr;
arch_local_irq_restore(flags);
}
static void mn10300_serial_dis_rx_intr(struct mn10300_serial_port *port)
{
unsigned long flags;
u16 x;
flags = arch_local_cli_save();
*port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
x = *port->rx_icr;
arch_local_irq_restore(flags);
}
/*
* multi-bit equivalent of test_and_clear_bit()
*/
static int mask_test_and_clear(volatile u8 *ptr, u8 mask)
{
u32 epsw;
asm volatile(" bclr %1,(%2) \n"
" mov epsw,%0 \n"
: "=d"(epsw) : "d"(mask), "a"(ptr)
: "cc", "memory");
return !(epsw & EPSW_FLAG_Z);
}
/*
* receive chars from the ring buffer for this serial port
* - must do break detection here (not done in the UART)
*/
static void mn10300_serial_receive_interrupt(struct mn10300_serial_port *port)
{
struct uart_icount *icount = &port->uart.icount;
struct tty_struct *tty = port->uart.state->port.tty;
unsigned ix;
int count;
u8 st, ch, push, status, overrun;
_enter("%s", port->name);
push = 0;
count = CIRC_CNT(port->rx_inp, port->rx_outp, MNSC_BUFFER_SIZE);
count = tty_buffer_request_room(tty, count);
if (count == 0) {
if (!tty->low_latency)
tty_flip_buffer_push(tty);
return;
}
try_again:
/* pull chars out of the hat */
ix = port->rx_outp;
if (ix == port->rx_inp) {
if (push && !tty->low_latency)
tty_flip_buffer_push(tty);
return;
}
ch = port->rx_buffer[ix++];
st = port->rx_buffer[ix++];
smp_rmb();
port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
port->uart.icount.rx++;
st &= SC01STR_FEF | SC01STR_PEF | SC01STR_OEF;
status = 0;
overrun = 0;
/* the UART doesn't detect BREAK, so we have to do that ourselves
* - it starts as a framing error on a NUL character
* - then we count another two NUL characters before issuing TTY_BREAK
* - then we end on a normal char or one that has all the bottom bits
* zero and the top bits set
*/
switch (port->rx_brk) {
case 0:
/* not breaking at the moment */
break;
case 1:
if (st & SC01STR_FEF && ch == 0) {
port->rx_brk = 2;
goto try_again;
}
goto not_break;
case 2:
if (st & SC01STR_FEF && ch == 0) {
port->rx_brk = 3;
_proto("Rx Break Detected");
icount->brk++;
if (uart_handle_break(&port->uart))
goto ignore_char;
status |= 1 << TTY_BREAK;
goto insert;
}
goto not_break;
default:
if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF))
goto try_again; /* still breaking */
port->rx_brk = 0; /* end of the break */
switch (ch) {
case 0xFF:
case 0xFE:
case 0xFC:
case 0xF8:
case 0xF0:
case 0xE0:
case 0xC0:
case 0x80:
case 0x00:
/* discard char at probable break end */
goto try_again;
}
break;
}
process_errors:
/* handle framing error */
if (st & SC01STR_FEF) {
if (ch == 0) {
/* framing error with NUL char is probably a BREAK */
port->rx_brk = 1;
goto try_again;
}
_proto("Rx Framing Error");
icount->frame++;
status |= 1 << TTY_FRAME;
}
/* handle parity error */
if (st & SC01STR_PEF) {
_proto("Rx Parity Error");
icount->parity++;
status = TTY_PARITY;
}
/* handle normal char */
if (status == 0) {
if (uart_handle_sysrq_char(&port->uart, ch))
goto ignore_char;
status = (1 << TTY_NORMAL);
}
/* handle overrun error */
if (st & SC01STR_OEF) {
if (port->rx_brk)
goto try_again;
_proto("Rx Overrun Error");
icount->overrun++;
overrun = 1;
}
insert:
status &= port->uart.read_status_mask;
if (!overrun && !(status & port->uart.ignore_status_mask)) {
int flag;
if (status & (1 << TTY_BREAK))
flag = TTY_BREAK;
else if (status & (1 << TTY_PARITY))
flag = TTY_PARITY;
else if (status & (1 << TTY_FRAME))
flag = TTY_FRAME;
else
flag = TTY_NORMAL;
tty_insert_flip_char(tty, ch, flag);
}
/* overrun is special, since it's reported immediately, and doesn't
* affect the current character
*/
if (overrun)
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
count--;
if (count <= 0) {
if (!tty->low_latency)
tty_flip_buffer_push(tty);
return;
}
ignore_char:
push = 1;
goto try_again;
not_break:
port->rx_brk = 0;
goto process_errors;
}
/*
* handle an interrupt from the serial transmission "virtual DMA" driver
* - note: the interrupt routine will disable its own interrupts when the Tx
* buffer is empty
*/
static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port)
{
_enter("%s", port->name);
if (!port->uart.state || !port->uart.state->port.tty) {
mn10300_serial_dis_tx_intr(port);
return;
}
if (uart_tx_stopped(&port->uart) ||
uart_circ_empty(&port->uart.state->xmit))
mn10300_serial_dis_tx_intr(port);
if (uart_circ_chars_pending(&port->uart.state->xmit) < WAKEUP_CHARS)
uart_write_wakeup(&port->uart);
}
/*
* deal with a change in the status of the CTS line
*/
static void mn10300_serial_cts_changed(struct mn10300_serial_port *port, u8 st)
{
u16 ctr;
port->tx_cts = st;
port->uart.icount.cts++;
/* flip the CTS state selector flag to interrupt when it changes
* back */
ctr = *port->_control;
ctr ^= SC2CTR_TWS;
*port->_control = ctr;
uart_handle_cts_change(&port->uart, st & SC2STR_CTS);
wake_up_interruptible(&port->uart.state->port.delta_msr_wait);
}
/*
* handle a virtual interrupt generated by the lower level "virtual DMA"
* routines (irq is the baud timer interrupt)
*/
static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id)
{
struct mn10300_serial_port *port = dev_id;
u8 st;
spin_lock(&port->uart.lock);
if (port->intr_flags) {
_debug("INT %s: %x", port->name, port->intr_flags);
if (mask_test_and_clear(&port->intr_flags, MNSCx_RX_AVAIL))
mn10300_serial_receive_interrupt(port);
if (mask_test_and_clear(&port->intr_flags,
MNSCx_TX_SPACE | MNSCx_TX_EMPTY))
mn10300_serial_transmit_interrupt(port);
}
/* the only modem control line amongst the whole lot is CTS on
* serial port 2 */
if (port->type == PORT_MN10300_CTS) {
st = *port->_status;
if ((port->tx_cts ^ st) & SC2STR_CTS)
mn10300_serial_cts_changed(port, st);
}
spin_unlock(&port->uart.lock);
return IRQ_HANDLED;
}
/*
* return indication of whether the hardware transmit buffer is empty
*/
static unsigned int mn10300_serial_tx_empty(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
return (*port->_status & (SC01STR_TXF | SC01STR_TBF)) ?
0 : TIOCSER_TEMT;
}
/*
* set the modem control lines (we don't have any)
*/
static void mn10300_serial_set_mctrl(struct uart_port *_port,
unsigned int mctrl)
{
struct mn10300_serial_port *port __attribute__ ((unused)) =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s,%x", port->name, mctrl);
}
/*
* get the modem control line statuses
*/
static unsigned int mn10300_serial_get_mctrl(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
if (port->type == PORT_MN10300_CTS && !(*port->_status & SC2STR_CTS))
return TIOCM_CAR | TIOCM_DSR;
return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
}
/*
* stop transmitting characters
*/
static void mn10300_serial_stop_tx(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
/* disable the virtual DMA */
mn10300_serial_dis_tx_intr(port);
}
/*
* start transmitting characters
* - jump-start transmission if it has stalled
* - enable the serial Tx interrupt (used by the virtual DMA controller)
* - force an interrupt to happen if necessary
*/
static void mn10300_serial_start_tx(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
u16 x;
_enter("%s{%lu}",
port->name,
CIRC_CNT(&port->uart.state->xmit.head,
&port->uart.state->xmit.tail,
UART_XMIT_SIZE));
/* kick the virtual DMA controller */
arch_local_cli();
x = *port->tx_icr;
x |= GxICR_ENABLE;
if (*port->_status & SC01STR_TBF)
x &= ~(GxICR_REQUEST | GxICR_DETECT);
else
x |= GxICR_REQUEST | GxICR_DETECT;
_debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx",
*port->_control, *port->_intr, *port->_status,
*port->_tmxmd,
(port->div_timer == MNSCx_DIV_TIMER_8BIT) ?
*(volatile u8 *)port->_tmxbr : *port->_tmxbr,
*port->tx_icr);
*port->tx_icr = x;
x = *port->tx_icr;
arch_local_sti();
}
/*
* transmit a high-priority XON/XOFF character
*/
static void mn10300_serial_send_xchar(struct uart_port *_port, char ch)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s,%02x", port->name, ch);
if (likely(port->gdbstub)) {
port->tx_xchar = ch;
if (ch)
mn10300_serial_en_tx_intr(port);
}
}
/*
* stop receiving characters
* - called whilst the port is being closed
*/
static void mn10300_serial_stop_rx(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
u16 ctr;
_enter("%s", port->name);
ctr = *port->_control;
ctr &= ~SC01CTR_RXE;
*port->_control = ctr;
mn10300_serial_dis_rx_intr(port);
}
/*
* enable modem status interrupts
*/
static void mn10300_serial_enable_ms(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
u16 ctr, cts;
_enter("%s", port->name);
if (port->type == PORT_MN10300_CTS) {
/* want to interrupt when CTS goes low if CTS is now high and
* vice versa
*/
port->tx_cts = *port->_status;
cts = (port->tx_cts & SC2STR_CTS) ?
SC2CTR_TWE : SC2CTR_TWE | SC2CTR_TWS;
ctr = *port->_control;
ctr &= ~SC2CTR_TWS;
ctr |= cts;
*port->_control = ctr;
mn10300_serial_en_tx_intr(port);
}
}
/*
* transmit or cease transmitting a break signal
*/
static void mn10300_serial_break_ctl(struct uart_port *_port, int ctl)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s,%d", port->name, ctl);
if (ctl) {
/* tell the virtual DMA handler to assert BREAK */
port->tx_break = 1;
mn10300_serial_en_tx_intr(port);
} else {
port->tx_break = 0;
*port->_control &= ~SC01CTR_BKE;
mn10300_serial_en_tx_intr(port);
}
}
/*
* grab the interrupts and enable the port for reception
*/
static int mn10300_serial_startup(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
struct mn10300_serial_int *pint;
_enter("%s{%d}", port->name, port->gdbstub);
if (unlikely(port->gdbstub))
return -EBUSY;
/* allocate an Rx buffer for the virtual DMA handler */
port->rx_buffer = kmalloc(MNSC_BUFFER_SIZE, GFP_KERNEL);
if (!port->rx_buffer)
return -ENOMEM;
port->rx_inp = port->rx_outp = 0;
/* finally, enable the device */
*port->_intr = SC01ICR_TI;
*port->_control |= SC01CTR_TXE | SC01CTR_RXE;
pint = &mn10300_serial_int_tbl[port->rx_irq];
pint->port = port;
pint->vdma = mn10300_serial_vdma_rx_handler;
pint = &mn10300_serial_int_tbl[port->tx_irq];
pint->port = port;
pint->vdma = mn10300_serial_vdma_tx_handler;
set_intr_level(port->rx_irq,
NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
set_intr_level(port->tx_irq,
NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
irq_set_chip(port->tm_irq, &mn10300_serial_pic);
if (request_irq(port->rx_irq, mn10300_serial_interrupt,
IRQF_DISABLED, port->rx_name, port) < 0)
goto error;
if (request_irq(port->tx_irq, mn10300_serial_interrupt,
IRQF_DISABLED, port->tx_name, port) < 0)
goto error2;
if (request_irq(port->tm_irq, mn10300_serial_interrupt,
IRQF_DISABLED, port->tm_name, port) < 0)
goto error3;
mn10300_serial_mask_ack(port->tm_irq);
return 0;
error3:
free_irq(port->tx_irq, port);
error2:
free_irq(port->rx_irq, port);
error:
kfree(port->rx_buffer);
port->rx_buffer = NULL;
return -EBUSY;
}
/*
* shutdown the port and release interrupts
*/
static void mn10300_serial_shutdown(struct uart_port *_port)
{
u16 x;
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
/* disable the serial port and its baud rate timer */
port->tx_break = 0;
*port->_control &= ~(SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
*port->_tmxmd = 0;
if (port->rx_buffer) {
void *buf = port->rx_buffer;
port->rx_buffer = NULL;
kfree(buf);
}
/* disable all intrs */
free_irq(port->tm_irq, port);
free_irq(port->rx_irq, port);
free_irq(port->tx_irq, port);
arch_local_cli();
*port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
x = *port->rx_icr;
*port->tx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
x = *port->tx_icr;
arch_local_sti();
}
/*
* this routine is called to set the UART divisor registers to match the
* specified baud rate for a serial port.
*/
static void mn10300_serial_change_speed(struct mn10300_serial_port *port,
struct ktermios *new,
struct ktermios *old)
{
unsigned long flags;
unsigned long ioclk = port->ioclk;
unsigned cflag;
int baud, bits, xdiv, tmp;
u16 tmxbr, scxctr;
u8 tmxmd, battempt;
u8 div_timer = port->div_timer;
_enter("%s{%lu}", port->name, ioclk);
/* byte size and parity */
cflag = new->c_cflag;
switch (cflag & CSIZE) {
case CS7: scxctr = SC01CTR_CLN_7BIT; bits = 9; break;
case CS8: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
default: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
}
if (cflag & CSTOPB) {
scxctr |= SC01CTR_STB_2BIT;
bits++;
}
if (cflag & PARENB) {
bits++;
if (cflag & PARODD)
scxctr |= SC01CTR_PB_ODD;
#ifdef CMSPAR
else if (cflag & CMSPAR)
scxctr |= SC01CTR_PB_FIXED0;
#endif
else
scxctr |= SC01CTR_PB_EVEN;
}
/* Determine divisor based on baud rate */
battempt = 0;
switch (port->uart.line) {
#ifdef CONFIG_MN10300_TTYSM0
case 0: /* ttySM0 */
#if defined(CONFIG_MN10300_TTYSM0_TIMER8)
scxctr |= SC0CTR_CK_TM8UFLOW_8;
#elif defined(CONFIG_MN10300_TTYSM0_TIMER0)
scxctr |= SC0CTR_CK_TM0UFLOW_8;
#elif defined(CONFIG_MN10300_TTYSM0_TIMER2)
scxctr |= SC0CTR_CK_TM2UFLOW_8;
#else
#error "Unknown config for ttySM0"
#endif
break;
#endif /* CONFIG_MN10300_TTYSM0 */
#ifdef CONFIG_MN10300_TTYSM1
case 1: /* ttySM1 */
#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
#if defined(CONFIG_MN10300_TTYSM1_TIMER9)
scxctr |= SC1CTR_CK_TM9UFLOW_8;
#elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
scxctr |= SC1CTR_CK_TM3UFLOW_8;
#else
#error "Unknown config for ttySM1"
#endif
#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
#if defined(CONFIG_MN10300_TTYSM1_TIMER12)
scxctr |= SC1CTR_CK_TM12UFLOW_8;
#else
#error "Unknown config for ttySM1"
#endif
#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
break;
#endif /* CONFIG_MN10300_TTYSM1 */
#ifdef CONFIG_MN10300_TTYSM2
case 2: /* ttySM2 */
#if defined(CONFIG_AM33_2)
#if defined(CONFIG_MN10300_TTYSM2_TIMER10)
scxctr |= SC2CTR_CK_TM10UFLOW;
#else
#error "Unknown config for ttySM2"
#endif
#else /* CONFIG_AM33_2 */
#if defined(CONFIG_MN10300_TTYSM2_TIMER9)
scxctr |= SC2CTR_CK_TM9UFLOW_8;
#elif defined(CONFIG_MN10300_TTYSM2_TIMER1)
scxctr |= SC2CTR_CK_TM1UFLOW_8;
#elif defined(CONFIG_MN10300_TTYSM2_TIMER3)
scxctr |= SC2CTR_CK_TM3UFLOW_8;
#else
#error "Unknown config for ttySM2"
#endif
#endif /* CONFIG_AM33_2 */
break;
#endif /* CONFIG_MN10300_TTYSM2 */
default:
break;
}
try_alternative:
baud = uart_get_baud_rate(&port->uart, new, old, 0,
port->ioclk / 8);
_debug("ALT %d [baud %d]", battempt, baud);
if (!baud)
baud = 9600; /* B0 transition handled in rs_set_termios */
xdiv = 1;
if (baud == 134) {
baud = 269; /* 134 is really 134.5 */
xdiv = 2;
}
if (baud == 38400 &&
(port->uart.flags & UPF_SPD_MASK) == UPF_SPD_CUST
) {
_debug("CUSTOM %u", port->uart.custom_divisor);
if (div_timer == MNSCx_DIV_TIMER_16BIT) {
if (port->uart.custom_divisor <= 65535) {
tmxmd = TM8MD_SRC_IOCLK;
tmxbr = port->uart.custom_divisor;
port->uart.uartclk = ioclk;
goto timer_okay;
}
if (port->uart.custom_divisor / 8 <= 65535) {
tmxmd = TM8MD_SRC_IOCLK_8;
tmxbr = port->uart.custom_divisor / 8;
port->uart.custom_divisor = tmxbr * 8;
port->uart.uartclk = ioclk / 8;
goto timer_okay;
}
if (port->uart.custom_divisor / 32 <= 65535) {
tmxmd = TM8MD_SRC_IOCLK_32;
tmxbr = port->uart.custom_divisor / 32;
port->uart.custom_divisor = tmxbr * 32;
port->uart.uartclk = ioclk / 32;
goto timer_okay;
}
} else if (div_timer == MNSCx_DIV_TIMER_8BIT) {
if (port->uart.custom_divisor <= 255) {
tmxmd = TM2MD_SRC_IOCLK;
tmxbr = port->uart.custom_divisor;
port->uart.uartclk = ioclk;
goto timer_okay;
}
if (port->uart.custom_divisor / 8 <= 255) {
tmxmd = TM2MD_SRC_IOCLK_8;
tmxbr = port->uart.custom_divisor / 8;
port->uart.custom_divisor = tmxbr * 8;
port->uart.uartclk = ioclk / 8;
goto timer_okay;
}
if (port->uart.custom_divisor / 32 <= 255) {
tmxmd = TM2MD_SRC_IOCLK_32;
tmxbr = port->uart.custom_divisor / 32;
port->uart.custom_divisor = tmxbr * 32;
port->uart.uartclk = ioclk / 32;
goto timer_okay;
}
}
}
switch (div_timer) {
case MNSCx_DIV_TIMER_16BIT:
port->uart.uartclk = ioclk;
tmxmd = TM8MD_SRC_IOCLK;
tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
if (tmp > 0 && tmp <= 65535)
goto timer_okay;
port->uart.uartclk = ioclk / 8;
tmxmd = TM8MD_SRC_IOCLK_8;
tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
if (tmp > 0 && tmp <= 65535)
goto timer_okay;
port->uart.uartclk = ioclk / 32;
tmxmd = TM8MD_SRC_IOCLK_32;
tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
if (tmp > 0 && tmp <= 65535)
goto timer_okay;
break;
case MNSCx_DIV_TIMER_8BIT:
port->uart.uartclk = ioclk;
tmxmd = TM2MD_SRC_IOCLK;
tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
if (tmp > 0 && tmp <= 255)
goto timer_okay;
port->uart.uartclk = ioclk / 8;
tmxmd = TM2MD_SRC_IOCLK_8;
tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
if (tmp > 0 && tmp <= 255)
goto timer_okay;
port->uart.uartclk = ioclk / 32;
tmxmd = TM2MD_SRC_IOCLK_32;
tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
if (tmp > 0 && tmp <= 255)
goto timer_okay;
break;
default:
BUG();
return;
}
/* refuse to change to a baud rate we can't support */
_debug("CAN'T SUPPORT");
switch (battempt) {
case 0:
if (old) {
new->c_cflag &= ~CBAUD;
new->c_cflag |= (old->c_cflag & CBAUD);
battempt = 1;
goto try_alternative;
}
case 1:
/* as a last resort, if the quotient is zero, default to 9600
* bps */
new->c_cflag &= ~CBAUD;
new->c_cflag |= B9600;
battempt = 2;
goto try_alternative;
default:
/* hmmm... can't seem to support 9600 either
* - we could try iterating through the speeds we know about to
* find the lowest
*/
new->c_cflag &= ~CBAUD;
new->c_cflag |= B0;
if (div_timer == MNSCx_DIV_TIMER_16BIT)
tmxmd = TM8MD_SRC_IOCLK_32;
else if (div_timer == MNSCx_DIV_TIMER_8BIT)
tmxmd = TM2MD_SRC_IOCLK_32;
tmxbr = 1;
port->uart.uartclk = ioclk / 32;
break;
}
timer_okay:
_debug("UARTCLK: %u / %hu", port->uart.uartclk, tmxbr);
/* make the changes */
spin_lock_irqsave(&port->uart.lock, flags);
uart_update_timeout(&port->uart, new->c_cflag, baud);
/* set the timer to produce the required baud rate */
switch (div_timer) {
case MNSCx_DIV_TIMER_16BIT:
*port->_tmxmd = 0;
*port->_tmxbr = tmxbr;
*port->_tmxmd = TM8MD_INIT_COUNTER;
*port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
break;
case MNSCx_DIV_TIMER_8BIT:
*port->_tmxmd = 0;
*(volatile u8 *) port->_tmxbr = (u8) tmxbr;
*port->_tmxmd = TM2MD_INIT_COUNTER;
*port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
break;
}
/* CTS flow control flag and modem status interrupts */
scxctr &= ~(SC2CTR_TWE | SC2CTR_TWS);
if (port->type == PORT_MN10300_CTS && cflag & CRTSCTS) {
/* want to interrupt when CTS goes low if CTS is now
* high and vice versa
*/
port->tx_cts = *port->_status;
if (port->tx_cts & SC2STR_CTS)
scxctr |= SC2CTR_TWE;
else
scxctr |= SC2CTR_TWE | SC2CTR_TWS;
}
/* set up parity check flag */
port->uart.read_status_mask = (1 << TTY_NORMAL) | (1 << TTY_OVERRUN);
if (new->c_iflag & INPCK)
port->uart.read_status_mask |=
(1 << TTY_PARITY) | (1 << TTY_FRAME);
if (new->c_iflag & (BRKINT | PARMRK))
port->uart.read_status_mask |= (1 << TTY_BREAK);
/* characters to ignore */
port->uart.ignore_status_mask = 0;
if (new->c_iflag & IGNPAR)
port->uart.ignore_status_mask |=
(1 << TTY_PARITY) | (1 << TTY_FRAME);
if (new->c_iflag & IGNBRK) {
port->uart.ignore_status_mask |= (1 << TTY_BREAK);
/*
* If we're ignoring parity and break indicators,
* ignore overruns to (for real raw support).
*/
if (new->c_iflag & IGNPAR)
port->uart.ignore_status_mask |= (1 << TTY_OVERRUN);
}
/* Ignore all characters if CREAD is not set */
if ((new->c_cflag & CREAD) == 0)
port->uart.ignore_status_mask |= (1 << TTY_NORMAL);
scxctr |= *port->_control & (SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
*port->_control = scxctr;
spin_unlock_irqrestore(&port->uart.lock, flags);
}
/*
* set the terminal I/O parameters
*/
static void mn10300_serial_set_termios(struct uart_port *_port,
struct ktermios *new,
struct ktermios *old)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s,%p,%p", port->name, new, old);
mn10300_serial_change_speed(port, new, old);
/* handle turning off CRTSCTS */
if (!(new->c_cflag & CRTSCTS)) {
u16 ctr = *port->_control;
ctr &= ~SC2CTR_TWE;
*port->_control = ctr;
}
/* change Transfer bit-order (LSB/MSB) */
if (new->c_cflag & CODMSB)
*port->_control |= SC01CTR_OD_MSBFIRST; /* MSB MODE */
else
*port->_control &= ~SC01CTR_OD_MSBFIRST; /* LSB MODE */
}
/*
* return description of port type
*/
static const char *mn10300_serial_type(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
if (port->uart.type == PORT_MN10300_CTS)
return "MN10300 SIF_CTS";
return "MN10300 SIF";
}
/*
* release I/O and memory regions in use by port
*/
static void mn10300_serial_release_port(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
release_mem_region((unsigned long) port->_iobase, 16);
}
/*
* request I/O and memory regions for port
*/
static int mn10300_serial_request_port(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
request_mem_region((unsigned long) port->_iobase, 16, port->name);
return 0;
}
/*
* configure the type and reserve the ports
*/
static void mn10300_serial_config_port(struct uart_port *_port, int type)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
_enter("%s", port->name);
port->uart.type = PORT_MN10300;
if (port->options & MNSCx_OPT_CTS)
port->uart.type = PORT_MN10300_CTS;
mn10300_serial_request_port(_port);
}
/*
* verify serial parameters are suitable for this port type
*/
static int mn10300_serial_verify_port(struct uart_port *_port,
struct serial_struct *ss)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
void *mapbase = (void *) (unsigned long) port->uart.mapbase;
_enter("%s", port->name);
/* these things may not be changed */
if (ss->irq != port->uart.irq ||
ss->port != port->uart.iobase ||
ss->io_type != port->uart.iotype ||
ss->iomem_base != mapbase ||
ss->iomem_reg_shift != port->uart.regshift ||
ss->hub6 != port->uart.hub6 ||
ss->xmit_fifo_size != port->uart.fifosize)
return -EINVAL;
/* type may be changed on a port that supports CTS */
if (ss->type != port->uart.type) {
if (!(port->options & MNSCx_OPT_CTS))
return -EINVAL;
if (ss->type != PORT_MN10300 &&
ss->type != PORT_MN10300_CTS)
return -EINVAL;
}
return 0;
}
/*
* initialise the MN10300 on-chip UARTs
*/
static int __init mn10300_serial_init(void)
{
struct mn10300_serial_port *port;
int ret, i;
printk(KERN_INFO "%s version %s (%s)\n",
serial_name, serial_version, serial_revdate);
#if defined(CONFIG_MN10300_TTYSM2) && defined(CONFIG_AM33_2)
{
int tmp;
SC2TIM = 8; /* make the baud base of timer 2 IOCLK/8 */
tmp = SC2TIM;
}
#endif
set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL),
mn10300_serial_vdma_interrupt);
ret = uart_register_driver(&mn10300_serial_driver);
if (!ret) {
for (i = 0 ; i < NR_PORTS ; i++) {
port = mn10300_serial_ports[i];
if (!port || port->gdbstub)
continue;
switch (port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
ret = uart_add_one_port(&mn10300_serial_driver,
&port->uart);
if (ret < 0) {
_debug("ERROR %d", -ret);
break;
}
}
if (ret)
uart_unregister_driver(&mn10300_serial_driver);
}
return ret;
}
__initcall(mn10300_serial_init);
#ifdef CONFIG_MN10300_TTYSM_CONSOLE
/*
* print a string to the serial port without disturbing the real user of the
* port too much
* - the console must be locked by the caller
*/
static void mn10300_serial_console_write(struct console *co,
const char *s, unsigned count)
{
struct mn10300_serial_port *port;
unsigned i;
u16 scxctr, txicr, tmp;
u8 tmxmd;
port = mn10300_serial_ports[co->index];
/* firstly hijack the serial port from the "virtual DMA" controller */
arch_local_cli();
txicr = *port->tx_icr;
*port->tx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
tmp = *port->tx_icr;
arch_local_sti();
/* the transmitter may be disabled */
scxctr = *port->_control;
if (!(scxctr & SC01CTR_TXE)) {
/* restart the UART clock */
tmxmd = *port->_tmxmd;
switch (port->div_timer) {
case MNSCx_DIV_TIMER_16BIT:
*port->_tmxmd = 0;
*port->_tmxmd = TM8MD_INIT_COUNTER;
*port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
break;
case MNSCx_DIV_TIMER_8BIT:
*port->_tmxmd = 0;
*port->_tmxmd = TM2MD_INIT_COUNTER;
*port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
break;
}
/* enable the transmitter */
*port->_control = (scxctr & ~SC01CTR_BKE) | SC01CTR_TXE;
} else if (scxctr & SC01CTR_BKE) {
/* stop transmitting BREAK */
*port->_control = (scxctr & ~SC01CTR_BKE);
}
/* send the chars into the serial port (with LF -> LFCR conversion) */
for (i = 0; i < count; i++) {
char ch = *s++;
while (*port->_status & SC01STR_TBF)
continue;
*(u8 *) port->_txb = ch;
if (ch == 0x0a) {
while (*port->_status & SC01STR_TBF)
continue;
*(u8 *) port->_txb = 0xd;
}
}
/* can't let the transmitter be turned off if it's actually
* transmitting */
while (*port->_status & (SC01STR_TXF | SC01STR_TBF))
continue;
/* disable the transmitter if we re-enabled it */
if (!(scxctr & SC01CTR_TXE))
*port->_control = scxctr;
arch_local_cli();
*port->tx_icr = txicr;
tmp = *port->tx_icr;
arch_local_sti();
}
/*
* set up a serial port as a console
* - construct a cflag setting for the first rs_open()
* - initialize the serial port
* - return non-zero if we didn't find a serial port.
*/
static int __init mn10300_serial_console_setup(struct console *co,
char *options)
{
struct mn10300_serial_port *port;
int i, parity = 'n', baud = 9600, bits = 8, flow = 0;
for (i = 0 ; i < NR_PORTS ; i++) {
port = mn10300_serial_ports[i];
if (port && !port->gdbstub && port->uart.line == co->index)
goto found_device;
}
return -ENODEV;
found_device:
switch (port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(&port->uart, co, baud, parity, bits, flow);
}
/*
* register console
*/
static int __init mn10300_serial_console_init(void)
{
register_console(&mn10300_serial_console);
return 0;
}
console_initcall(mn10300_serial_console_init);
#endif
#ifdef CONFIG_CONSOLE_POLL
/*
* Polled character reception for the kernel debugger
*/
static int mn10300_serial_poll_get_char(struct uart_port *_port)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
unsigned ix;
u8 st, ch;
_enter("%s", port->name);
do {
/* pull chars out of the hat */
ix = port->rx_outp;
if (ix == port->rx_inp)
return NO_POLL_CHAR;
ch = port->rx_buffer[ix++];
st = port->rx_buffer[ix++];
smp_rmb();
port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
} while (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF));
return ch;
}
/*
* Polled character transmission for the kernel debugger
*/
static void mn10300_serial_poll_put_char(struct uart_port *_port,
unsigned char ch)
{
struct mn10300_serial_port *port =
container_of(_port, struct mn10300_serial_port, uart);
u8 intr, tmp;
/* wait for the transmitter to finish anything it might be doing (and
* this includes the virtual DMA handler, so it might take a while) */
while (*port->_status & (SC01STR_TBF | SC01STR_TXF))
continue;
/* disable the Tx ready interrupt */
intr = *port->_intr;
*port->_intr = intr & ~SC01ICR_TI;
tmp = *port->_intr;
if (ch == 0x0a) {
*(u8 *) port->_txb = 0x0d;
while (*port->_status & SC01STR_TBF)
continue;
}
*(u8 *) port->_txb = ch;
while (*port->_status & SC01STR_TBF)
continue;
/* restore the Tx interrupt flag */
*port->_intr = intr;
tmp = *port->_intr;
}
#endif /* CONFIG_CONSOLE_POLL */
| gpl-2.0 |
bensonhsu2013/old_samsung-lt02wifi-kernel | arch/arm/mach-shmobile/pfc-sh7367.c | 5103 | 69550 | /*
* sh7367 processor support - PFC hardware block
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <mach/sh7367.h>
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
/* Special Pull-up / Pull-down Functions */
PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
PORT58_KEYIN6_PU_MARK,
/* 49-1 */
VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
XCTS1_MARK, SCIFA4_CTS_MARK,
/* 49-2 */
HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
HSU_SDI_MARK, PORT55_KEYIN3_MARK,
HSU_SCO_MARK, PORT56_KEYIN4_MARK,
HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
HSU_DACK_MARK, PORT58_KEYIN6_MARK,
HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
XTALB1L_MARK,
GPS_AGC1_MARK, SCIFA0_RTS_MARK,
GPS_AGC2_MARK, SCIFA0_SCK_MARK,
GPS_AGC3_MARK, SCIFA0_TXD_MARK,
GPS_AGC4_MARK, SCIFA0_RXD_MARK,
GPS_PWRD_MARK, SCIFA0_CTS_MARK,
GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
SIUBOMC_MARK, TPU2TO0_MARK,
SIUCKB_MARK, TPU2TO1_MARK,
SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
SIUBILR_MARK, TPU3TO1_MARK,
SIUBIBT_MARK, TPU3TO2_MARK,
SIUBISLD_MARK, TPU3TO3_MARK,
NMI_MARK, TPU4TO0_MARK,
DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
IRQ_TMPB_MARK,
PWEN_MARK, MFG1_OUT1_MARK,
OVCN_MARK, MFG1_IN1_MARK,
OVCN2_MARK, MFG1_IN2_MARK,
/* 49-3 */
RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
SCIFA5_CTS_MARK, MFG0_IN1_MARK,
SCIFA5_RTS_MARK, MFG0_IN2_MARK,
SCIFA5_RXD_MARK,
SCIFA5_TXD_MARK,
SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
A0_EA0_MARK, BS_MARK,
A14_EA14_MARK, PORT102_KEYOUT0_MARK,
A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
A16_EA16_MARK, PORT104_KEYOUT2_MARK,
DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
A17_EA17_MARK, PORT105_KEYOUT3_MARK,
DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
A18_EA18_MARK, PORT106_KEYOUT4_MARK,
DV_DL0_MARK, MSIOF0_TSCK_MARK,
A19_EA19_MARK, PORT107_KEYOUT5_MARK,
DV_DL1_MARK, MSIOF0_TXD_MARK,
A20_EA20_MARK, PORT108_KEYIN0_MARK,
DV_DL2_MARK, MSIOF0_RSCK_MARK,
A21_EA21_MARK, PORT109_KEYIN1_MARK,
DV_DL3_MARK, MSIOF0_RSYNC_MARK,
A22_EA22_MARK, PORT110_KEYIN2_MARK,
DV_DL4_MARK, MSIOF0_MCK0_MARK,
A23_EA23_MARK, PORT111_KEYIN3_MARK,
DV_DL5_MARK, MSIOF0_MCK1_MARK,
A24_EA24_MARK, PORT112_KEYIN4_MARK,
DV_DL6_MARK, MSIOF0_RXD_MARK,
A25_EA25_MARK, PORT113_KEYIN5_MARK,
DV_DL7_MARK, MSIOF0_SS2_MARK,
A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
NBRSTOUT_MARK, NBRST_MARK,
/* 49-4 */
RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
VIO_VD_MARK, VIO_HD_MARK,
VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
VIO_CKO_MARK,
MFG3_IN1_MARK, MFG3_IN2_MARK,
M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
SIUCKA_MARK, MFG0_OUT2_MARK,
LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
SIUAOBT_MARK, BBIF2_TSCK1_MARK,
LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
SIUAOSLD_MARK, BBIF2_TXD1_MARK,
LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
SIUAISPD_MARK, MFG1_OUT2_MARK,
LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
SIUAILR_MARK, MFG2_OUT2_MARK,
LCDD6_MARK, DV_D6_MARK,
SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
LCDD7_MARK, DV_D7_MARK,
SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
D26_MARK, ED26_MARK,
LCDD19_MARK, MSIOF0L_TSYNC_MARK,
D27_MARK, ED27_MARK,
LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
D28_MARK, ED28_MARK,
LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
D29_MARK, ED29_MARK,
LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
D30_MARK, ED30_MARK,
LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
D31_MARK, ED31_MARK,
LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
/* 49-5 */
LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
VIO_VDR_MARK, VIO_HDR_MARK,
VIO_CLKR_MARK, VIO_CKOR_MARK,
SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
MSIOF1_SS1_MARK, EDBGREQ3_MARK,
MSIOF1_SS2_MARK,
PORT236_IROUT_MARK, IRDA_OUT_MARK,
IRDA_IN_MARK, IRDA_FIRSEL_MARK,
TPU1TO0_MARK, TS_SPSYNC3_MARK,
TPU1TO1_MARK, TS_SDAT3_MARK,
TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
PORT245_IROUT_MARK, M15_RSW_MARK,
SOUT3_MARK, SCIFA2_TXD1_MARK,
SIN3_MARK, SCIFA2_RXD1_MARK,
XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
SDHICLK0_MARK, TCK2_MARK,
SDHICD0_MARK,
SDHID0_0_MARK, TMS2_MARK,
SDHID0_1_MARK, TDO2_MARK,
SDHID0_2_MARK, TDI2_MARK,
SDHID0_3_MARK, RTCK2_MARK,
/* 49-6 */
SDHICMD0_MARK, TRST2_MARK,
SDHIWP0_MARK, EDBGREQ2_MARK,
SDHICLK1_MARK, TCK3_MARK,
SDHID1_0_MARK, M11_SLCD_SO2_MARK,
TS_SPSYNC2_MARK, TMS3_MARK,
SDHID1_1_MARK, M9_SLCD_AO2_MARK,
TS_SDAT2_MARK, TDO3_MARK,
SDHID1_2_MARK, M10_SLCD_CK2_MARK,
TS_SDEN2_MARK, TDI3_MARK,
SDHID1_3_MARK, M12_SLCD_CE2_MARK,
TS_SCK2_MARK, RTCK3_MARK,
SDHICMD1_MARK, TRST3_MARK,
SDHICLK2_MARK, SCIFB_SCK_MARK,
SDHID2_0_MARK, SCIFB_TXD_MARK,
SDHID2_1_MARK, SCIFB_CTS_MARK,
SDHID2_2_MARK, SCIFB_RXD_MARK,
SDHID2_3_MARK, SCIFB_RTS_MARK,
SDHICMD2_MARK,
RESETOUTS_MARK,
DIVLOCK_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* 49-1 (GPIO) */
PORT_DATA_I_PD(0),
PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
PORT_DATA_I_PU(13),
PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
PORT_DATA_IO_PU(33),
PORT_DATA_O(34),
PORT_DATA_I_PU(35),
PORT_DATA_O(36),
PORT_DATA_I_PU_PD(37),
/* 49-2 (GPIO) */
PORT_DATA_IO_PU_PD(38),
PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
PORT_DATA_O(46), PORT_DATA_O(47),
PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
PORT_DATA_O(53),
PORT_DATA_IO_PD(54),
PORT_DATA_I_PU_PD(55),
PORT_DATA_IO_PU_PD(56),
PORT_DATA_I_PU_PD(57),
PORT_DATA_IO_PU_PD(58),
PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
PORT_DATA_O(63),
PORT_DATA_I_PU(64),
PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
PORT_DATA_I_PD(74),
PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
PORT_DATA_O(79),
PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
PORT_DATA_I_PD(87),
PORT_DATA_IO_PU_PD(88),
PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
/* 49-3 (GPIO) */
PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
PORT_DATA_I_PU_PD(95),
PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
PORT_DATA_IO_PD(107),
PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
PORT_DATA_IO_PU_PD(114),
PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
PORT_DATA_IO_PU(130),
PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
PORT_DATA_IO_PU(134),
PORT_DATA_O(135), PORT_DATA_O(136),
PORT_DATA_I_PU_PD(137),
PORT_DATA_IO(138),
PORT_DATA_IO_PU_PD(139),
PORT_DATA_IO(140), PORT_DATA_IO(141),
PORT_DATA_I_PU(142),
PORT_DATA_O(143), PORT_DATA_O(144),
PORT_DATA_I_PU(145),
/* 49-4 (GPIO) */
PORT_DATA_O(146),
PORT_DATA_I_PU_PD(147),
PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
PORT_DATA_IO_PU_PD(167),
PORT_DATA_O(168),
PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
PORT_DATA_O(171),
PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
PORT_DATA_O(174),
PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
PORT_DATA_O(199),
PORT_DATA_IO_PD(200),
/* 49-5 (GPIO) */
PORT_DATA_O(201),
PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
PORT_DATA_I(204),
PORT_DATA_O(205),
PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
PORT_DATA_O(217),
PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
PORT_DATA_I_PD(223),
PORT_DATA_I_PU_PD(224),
PORT_DATA_O(225),
PORT_DATA_IO_PD(226),
PORT_DATA_IO_PU_PD(227),
PORT_DATA_I_PD(228),
PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
PORT_DATA_I_PU_PD(235),
PORT_DATA_O(236),
PORT_DATA_I_PD(237),
PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
PORT_DATA_O(244),
PORT_DATA_IO_PU_PD(245),
PORT_DATA_O(246),
PORT_DATA_I_PD(247),
PORT_DATA_IO_PU_PD(248),
PORT_DATA_I_PU_PD(249),
PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
PORT_DATA_IO_PU_PD(256),
/* 49-6 (GPIO) */
PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
PORT_DATA_IO_PD(259),
PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
PORT_DATA_O(265),
PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
PORT_DATA_O(271),
PORT_DATA_I_PD(272),
/* Special Pull-up / Pull-down Functions */
PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
PORT48_FN2, PORT48_IN_PU),
PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
PORT49_FN2, PORT49_IN_PU),
PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
PORT50_FN2, PORT50_IN_PU),
PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
PORT55_FN2, PORT55_IN_PU),
PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
PORT56_FN2, PORT56_IN_PU),
PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
PORT57_FN2, PORT57_IN_PU),
PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
PORT58_FN2, PORT58_IN_PU),
/* 49-1 (FN) */
PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
PINMUX_DATA(SIN2_MARK, PORT12_FN2),
PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
PINMUX_DATA(IDIO_MARK, PORT33_FN1),
PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
PINMUX_DATA(SIN1_MARK, PORT35_FN1),
PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
PINMUX_DATA(XWUP_MARK, PORT35_FN3),
PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
/* 49-2 (FN) */
PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
PINMUX_DATA(NMI_MARK, PORT83_FN1),
PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
PINMUX_DATA(PWEN_MARK, PORT88_FN1),
PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
PINMUX_DATA(OVCN_MARK, PORT89_FN1),
PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
/* 49-3 (FN) */
PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
PINMUX_DATA(IDIN_MARK, PORT95_FN1),
PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
PINMUX_DATA(BS_MARK, PORT101_FN2),
PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
PINMUX_DATA(A26_MARK, PORT114_FN1),
PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
PINMUX_DATA(CS4_MARK, PORT131_FN1),
PINMUX_DATA(CS5A_MARK, PORT132_FN1),
PINMUX_DATA(CS5B_MARK, PORT133_FN1),
PINMUX_DATA(FCE1_MARK, PORT133_FN2),
PINMUX_DATA(CS6B_MARK, PORT134_FN1),
PINMUX_DATA(XCS2_MARK, PORT134_FN2),
PINMUX_DATA(FCE0_MARK, PORT135_FN1),
PINMUX_DATA(CS6A_MARK, PORT136_FN1),
PINMUX_DATA(DACK0_MARK, PORT136_FN2),
PINMUX_DATA(WAIT_MARK, PORT137_FN1),
PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
PINMUX_DATA(A27_MARK, PORT139_FN1),
PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
PINMUX_DATA(FRB_MARK, PORT142_FN1),
PINMUX_DATA(CKO_MARK, PORT143_FN1),
PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
PINMUX_DATA(NBRST_MARK, PORT145_FN1),
/* 49-4 (FN) */
PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
PINMUX_DATA(XWR2_MARK, PORT181_FN7),
PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
PINMUX_DATA(XWR3_MARK, PORT182_FN7),
PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
PINMUX_DATA(D16_MARK, PORT183_FN6),
PINMUX_DATA(ED16_MARK, PORT183_FN7),
PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
PINMUX_DATA(D17_MARK, PORT184_FN6),
PINMUX_DATA(ED17_MARK, PORT184_FN7),
PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
PINMUX_DATA(D18_MARK, PORT185_FN6),
PINMUX_DATA(ED18_MARK, PORT185_FN7),
PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
PINMUX_DATA(D19_MARK, PORT186_FN6),
PINMUX_DATA(ED19_MARK, PORT186_FN7),
PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
PINMUX_DATA(D20_MARK, PORT187_FN6),
PINMUX_DATA(ED20_MARK, PORT187_FN7),
PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
PINMUX_DATA(D21_MARK, PORT188_FN6),
PINMUX_DATA(ED21_MARK, PORT188_FN7),
PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
PINMUX_DATA(D22_MARK, PORT189_FN6),
PINMUX_DATA(ED22_MARK, PORT189_FN7),
PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
PINMUX_DATA(D23_MARK, PORT190_FN6),
PINMUX_DATA(ED23_MARK, PORT190_FN7),
PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
PINMUX_DATA(D24_MARK, PORT191_FN6),
PINMUX_DATA(ED24_MARK, PORT191_FN7),
PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
PINMUX_DATA(D25_MARK, PORT192_FN6),
PINMUX_DATA(ED25_MARK, PORT192_FN7),
PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
PINMUX_DATA(D26_MARK, PORT193_FN6),
PINMUX_DATA(ED26_MARK, PORT193_FN7),
PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
PINMUX_DATA(D27_MARK, PORT194_FN6),
PINMUX_DATA(ED27_MARK, PORT194_FN7),
PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
PINMUX_DATA(D28_MARK, PORT195_FN6),
PINMUX_DATA(ED28_MARK, PORT195_FN7),
PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
PINMUX_DATA(D29_MARK, PORT196_FN6),
PINMUX_DATA(ED29_MARK, PORT196_FN7),
PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
PINMUX_DATA(D30_MARK, PORT197_FN6),
PINMUX_DATA(ED30_MARK, PORT197_FN7),
PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
PINMUX_DATA(D31_MARK, PORT198_FN6),
PINMUX_DATA(ED31_MARK, PORT198_FN7),
PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
PINMUX_DATA(DACK2_MARK, PORT200_FN2),
PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
/* 49-5 (FN) */
PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
PINMUX_DATA(DACK3_MARK, PORT201_FN4),
PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
PINMUX_DATA(DACK1_MARK, PORT205_FN3),
PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
PINMUX_DATA(SIN3_MARK, PORT247_FN1),
PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
PINMUX_DATA(DINT_MARK, PORT250_FN1),
PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
PINMUX_DATA(TCK2_MARK, PORT251_FN2),
PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
PINMUX_DATA(TMS2_MARK, PORT253_FN2),
PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
PINMUX_DATA(TDO2_MARK, PORT254_FN2),
PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
PINMUX_DATA(TDI2_MARK, PORT255_FN2),
PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
/* 49-6 (FN) */
PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
PINMUX_DATA(TRST2_MARK, PORT257_FN2),
PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
PINMUX_DATA(TCK3_MARK, PORT259_FN4),
PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
PINMUX_DATA(TMS3_MARK, PORT260_FN4),
PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
PINMUX_DATA(TDO3_MARK, PORT261_FN4),
PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
PINMUX_DATA(TDI3_MARK, PORT262_FN4),
PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
PINMUX_DATA(TRST3_MARK, PORT264_FN4),
PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
};
static struct pinmux_gpio pinmux_gpios[] = {
/* 49-1 -> 49-6 (GPIO) */
GPIO_PORT_ALL(),
/* Special Pull-up / Pull-down Functions */
GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
GPIO_FN(PORT58_KEYIN6_PU),
/* 49-1 (FN) */
GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
/* 49-2 (FN) */
GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
GPIO_FN(XTALB1L),
GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
GPIO_FN(NMI), GPIO_FN(TPU4TO0),
GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
GPIO_FN(IRQ_TMPB),
GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
/* 49-3 (FN) */
GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
GPIO_FN(PORT93_VIO_CKO2),
GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
GPIO_FN(SCIFA5_RXD),
GPIO_FN(SCIFA5_TXD),
GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
GPIO_FN(A0_EA0), GPIO_FN(BS),
GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
/* 49-4 (FN) */
GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
GPIO_FN(VIO_CKO),
GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
GPIO_FN(LCDD6), GPIO_FN(DV_D6),
GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
GPIO_FN(LCDD7), GPIO_FN(DV_D7),
GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
GPIO_FN(D26), GPIO_FN(ED26),
GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
GPIO_FN(D27), GPIO_FN(ED27),
GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
GPIO_FN(D28), GPIO_FN(ED28),
GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
GPIO_FN(D29), GPIO_FN(ED29),
GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
GPIO_FN(D30), GPIO_FN(ED30),
GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
GPIO_FN(D31), GPIO_FN(ED31),
GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
/* 49-5 (FN) */
GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
GPIO_FN(MSIOF1_SS2),
GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
GPIO_FN(SDHICD0),
GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
/* 49-6 (FN) */
GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
GPIO_FN(SDHICMD2),
GPIO_FN(RESETOUTS),
GPIO_FN(DIVLOCK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
PORTCR(3, 0xe6050003), /* PORT3CR */
PORTCR(4, 0xe6050004), /* PORT4CR */
PORTCR(5, 0xe6050005), /* PORT5CR */
PORTCR(6, 0xe6050006), /* PORT6CR */
PORTCR(7, 0xe6050007), /* PORT7CR */
PORTCR(8, 0xe6050008), /* PORT8CR */
PORTCR(9, 0xe6050009), /* PORT9CR */
PORTCR(10, 0xe605000a), /* PORT10CR */
PORTCR(11, 0xe605000b), /* PORT11CR */
PORTCR(12, 0xe605000c), /* PORT12CR */
PORTCR(13, 0xe605000d), /* PORT13CR */
PORTCR(14, 0xe605000e), /* PORT14CR */
PORTCR(15, 0xe605000f), /* PORT15CR */
PORTCR(16, 0xe6050010), /* PORT16CR */
PORTCR(17, 0xe6050011), /* PORT17CR */
PORTCR(18, 0xe6050012), /* PORT18CR */
PORTCR(19, 0xe6050013), /* PORT19CR */
PORTCR(20, 0xe6050014), /* PORT20CR */
PORTCR(21, 0xe6050015), /* PORT21CR */
PORTCR(22, 0xe6050016), /* PORT22CR */
PORTCR(23, 0xe6050017), /* PORT23CR */
PORTCR(24, 0xe6050018), /* PORT24CR */
PORTCR(25, 0xe6050019), /* PORT25CR */
PORTCR(26, 0xe605001a), /* PORT26CR */
PORTCR(27, 0xe605001b), /* PORT27CR */
PORTCR(28, 0xe605001c), /* PORT28CR */
PORTCR(29, 0xe605001d), /* PORT29CR */
PORTCR(30, 0xe605001e), /* PORT30CR */
PORTCR(31, 0xe605001f), /* PORT31CR */
PORTCR(32, 0xe6050020), /* PORT32CR */
PORTCR(33, 0xe6050021), /* PORT33CR */
PORTCR(34, 0xe6050022), /* PORT34CR */
PORTCR(35, 0xe6050023), /* PORT35CR */
PORTCR(36, 0xe6050024), /* PORT36CR */
PORTCR(37, 0xe6050025), /* PORT37CR */
PORTCR(38, 0xe6050026), /* PORT38CR */
PORTCR(39, 0xe6050027), /* PORT39CR */
PORTCR(40, 0xe6050028), /* PORT40CR */
PORTCR(41, 0xe6050029), /* PORT41CR */
PORTCR(42, 0xe605002a), /* PORT42CR */
PORTCR(43, 0xe605002b), /* PORT43CR */
PORTCR(44, 0xe605002c), /* PORT44CR */
PORTCR(45, 0xe605002d), /* PORT45CR */
PORTCR(46, 0xe605002e), /* PORT46CR */
PORTCR(47, 0xe605002f), /* PORT47CR */
PORTCR(48, 0xe6050030), /* PORT48CR */
PORTCR(49, 0xe6050031), /* PORT49CR */
PORTCR(50, 0xe6050032), /* PORT50CR */
PORTCR(51, 0xe6050033), /* PORT51CR */
PORTCR(52, 0xe6050034), /* PORT52CR */
PORTCR(53, 0xe6050035), /* PORT53CR */
PORTCR(54, 0xe6050036), /* PORT54CR */
PORTCR(55, 0xe6050037), /* PORT55CR */
PORTCR(56, 0xe6050038), /* PORT56CR */
PORTCR(57, 0xe6050039), /* PORT57CR */
PORTCR(58, 0xe605003a), /* PORT58CR */
PORTCR(59, 0xe605003b), /* PORT59CR */
PORTCR(60, 0xe605003c), /* PORT60CR */
PORTCR(61, 0xe605003d), /* PORT61CR */
PORTCR(62, 0xe605003e), /* PORT62CR */
PORTCR(63, 0xe605003f), /* PORT63CR */
PORTCR(64, 0xe6050040), /* PORT64CR */
PORTCR(65, 0xe6050041), /* PORT65CR */
PORTCR(66, 0xe6050042), /* PORT66CR */
PORTCR(67, 0xe6050043), /* PORT67CR */
PORTCR(68, 0xe6050044), /* PORT68CR */
PORTCR(69, 0xe6050045), /* PORT69CR */
PORTCR(70, 0xe6050046), /* PORT70CR */
PORTCR(71, 0xe6050047), /* PORT71CR */
PORTCR(72, 0xe6050048), /* PORT72CR */
PORTCR(73, 0xe6050049), /* PORT73CR */
PORTCR(74, 0xe605004a), /* PORT74CR */
PORTCR(75, 0xe605004b), /* PORT75CR */
PORTCR(76, 0xe605004c), /* PORT76CR */
PORTCR(77, 0xe605004d), /* PORT77CR */
PORTCR(78, 0xe605004e), /* PORT78CR */
PORTCR(79, 0xe605004f), /* PORT79CR */
PORTCR(80, 0xe6050050), /* PORT80CR */
PORTCR(81, 0xe6050051), /* PORT81CR */
PORTCR(82, 0xe6050052), /* PORT82CR */
PORTCR(83, 0xe6050053), /* PORT83CR */
PORTCR(84, 0xe6050054), /* PORT84CR */
PORTCR(85, 0xe6050055), /* PORT85CR */
PORTCR(86, 0xe6050056), /* PORT86CR */
PORTCR(87, 0xe6050057), /* PORT87CR */
PORTCR(88, 0xe6051058), /* PORT88CR */
PORTCR(89, 0xe6051059), /* PORT89CR */
PORTCR(90, 0xe605105a), /* PORT90CR */
PORTCR(91, 0xe605105b), /* PORT91CR */
PORTCR(92, 0xe605105c), /* PORT92CR */
PORTCR(93, 0xe605105d), /* PORT93CR */
PORTCR(94, 0xe605105e), /* PORT94CR */
PORTCR(95, 0xe605105f), /* PORT95CR */
PORTCR(96, 0xe6051060), /* PORT96CR */
PORTCR(97, 0xe6051061), /* PORT97CR */
PORTCR(98, 0xe6051062), /* PORT98CR */
PORTCR(99, 0xe6051063), /* PORT99CR */
PORTCR(100, 0xe6051064), /* PORT100CR */
PORTCR(101, 0xe6051065), /* PORT101CR */
PORTCR(102, 0xe6051066), /* PORT102CR */
PORTCR(103, 0xe6051067), /* PORT103CR */
PORTCR(104, 0xe6051068), /* PORT104CR */
PORTCR(105, 0xe6051069), /* PORT105CR */
PORTCR(106, 0xe605106a), /* PORT106CR */
PORTCR(107, 0xe605106b), /* PORT107CR */
PORTCR(108, 0xe605106c), /* PORT108CR */
PORTCR(109, 0xe605106d), /* PORT109CR */
PORTCR(110, 0xe605106e), /* PORT110CR */
PORTCR(111, 0xe605106f), /* PORT111CR */
PORTCR(112, 0xe6051070), /* PORT112CR */
PORTCR(113, 0xe6051071), /* PORT113CR */
PORTCR(114, 0xe6051072), /* PORT114CR */
PORTCR(115, 0xe6051073), /* PORT115CR */
PORTCR(116, 0xe6051074), /* PORT116CR */
PORTCR(117, 0xe6051075), /* PORT117CR */
PORTCR(118, 0xe6051076), /* PORT118CR */
PORTCR(119, 0xe6051077), /* PORT119CR */
PORTCR(120, 0xe6051078), /* PORT120CR */
PORTCR(121, 0xe6051079), /* PORT121CR */
PORTCR(122, 0xe605107a), /* PORT122CR */
PORTCR(123, 0xe605107b), /* PORT123CR */
PORTCR(124, 0xe605107c), /* PORT124CR */
PORTCR(125, 0xe605107d), /* PORT125CR */
PORTCR(126, 0xe605107e), /* PORT126CR */
PORTCR(127, 0xe605107f), /* PORT127CR */
PORTCR(128, 0xe6051080), /* PORT128CR */
PORTCR(129, 0xe6051081), /* PORT129CR */
PORTCR(130, 0xe6051082), /* PORT130CR */
PORTCR(131, 0xe6051083), /* PORT131CR */
PORTCR(132, 0xe6051084), /* PORT132CR */
PORTCR(133, 0xe6051085), /* PORT133CR */
PORTCR(134, 0xe6051086), /* PORT134CR */
PORTCR(135, 0xe6051087), /* PORT135CR */
PORTCR(136, 0xe6051088), /* PORT136CR */
PORTCR(137, 0xe6051089), /* PORT137CR */
PORTCR(138, 0xe605108a), /* PORT138CR */
PORTCR(139, 0xe605108b), /* PORT139CR */
PORTCR(140, 0xe605108c), /* PORT140CR */
PORTCR(141, 0xe605108d), /* PORT141CR */
PORTCR(142, 0xe605108e), /* PORT142CR */
PORTCR(143, 0xe605108f), /* PORT143CR */
PORTCR(144, 0xe6051090), /* PORT144CR */
PORTCR(145, 0xe6051091), /* PORT145CR */
PORTCR(146, 0xe6051092), /* PORT146CR */
PORTCR(147, 0xe6051093), /* PORT147CR */
PORTCR(148, 0xe6051094), /* PORT148CR */
PORTCR(149, 0xe6051095), /* PORT149CR */
PORTCR(150, 0xe6051096), /* PORT150CR */
PORTCR(151, 0xe6051097), /* PORT151CR */
PORTCR(152, 0xe6051098), /* PORT152CR */
PORTCR(153, 0xe6051099), /* PORT153CR */
PORTCR(154, 0xe605109a), /* PORT154CR */
PORTCR(155, 0xe605109b), /* PORT155CR */
PORTCR(156, 0xe605109c), /* PORT156CR */
PORTCR(157, 0xe605109d), /* PORT157CR */
PORTCR(158, 0xe605109e), /* PORT158CR */
PORTCR(159, 0xe605109f), /* PORT159CR */
PORTCR(160, 0xe60510a0), /* PORT160CR */
PORTCR(161, 0xe60510a1), /* PORT161CR */
PORTCR(162, 0xe60510a2), /* PORT162CR */
PORTCR(163, 0xe60510a3), /* PORT163CR */
PORTCR(164, 0xe60510a4), /* PORT164CR */
PORTCR(165, 0xe60510a5), /* PORT165CR */
PORTCR(166, 0xe60510a6), /* PORT166CR */
PORTCR(167, 0xe60510a7), /* PORT167CR */
PORTCR(168, 0xe60510a8), /* PORT168CR */
PORTCR(169, 0xe60510a9), /* PORT169CR */
PORTCR(170, 0xe60510aa), /* PORT170CR */
PORTCR(171, 0xe60510ab), /* PORT171CR */
PORTCR(172, 0xe60510ac), /* PORT172CR */
PORTCR(173, 0xe60510ad), /* PORT173CR */
PORTCR(174, 0xe60510ae), /* PORT174CR */
PORTCR(175, 0xe60520af), /* PORT175CR */
PORTCR(176, 0xe60520b0), /* PORT176CR */
PORTCR(177, 0xe60520b1), /* PORT177CR */
PORTCR(178, 0xe60520b2), /* PORT178CR */
PORTCR(179, 0xe60520b3), /* PORT179CR */
PORTCR(180, 0xe60520b4), /* PORT180CR */
PORTCR(181, 0xe60520b5), /* PORT181CR */
PORTCR(182, 0xe60520b6), /* PORT182CR */
PORTCR(183, 0xe60520b7), /* PORT183CR */
PORTCR(184, 0xe60520b8), /* PORT184CR */
PORTCR(185, 0xe60520b9), /* PORT185CR */
PORTCR(186, 0xe60520ba), /* PORT186CR */
PORTCR(187, 0xe60520bb), /* PORT187CR */
PORTCR(188, 0xe60520bc), /* PORT188CR */
PORTCR(189, 0xe60520bd), /* PORT189CR */
PORTCR(190, 0xe60520be), /* PORT190CR */
PORTCR(191, 0xe60520bf), /* PORT191CR */
PORTCR(192, 0xe60520c0), /* PORT192CR */
PORTCR(193, 0xe60520c1), /* PORT193CR */
PORTCR(194, 0xe60520c2), /* PORT194CR */
PORTCR(195, 0xe60520c3), /* PORT195CR */
PORTCR(196, 0xe60520c4), /* PORT196CR */
PORTCR(197, 0xe60520c5), /* PORT197CR */
PORTCR(198, 0xe60520c6), /* PORT198CR */
PORTCR(199, 0xe60520c7), /* PORT199CR */
PORTCR(200, 0xe60520c8), /* PORT200CR */
PORTCR(201, 0xe60520c9), /* PORT201CR */
PORTCR(202, 0xe60520ca), /* PORT202CR */
PORTCR(203, 0xe60520cb), /* PORT203CR */
PORTCR(204, 0xe60520cc), /* PORT204CR */
PORTCR(205, 0xe60520cd), /* PORT205CR */
PORTCR(206, 0xe60520ce), /* PORT206CR */
PORTCR(207, 0xe60520cf), /* PORT207CR */
PORTCR(208, 0xe60520d0), /* PORT208CR */
PORTCR(209, 0xe60520d1), /* PORT209CR */
PORTCR(210, 0xe60520d2), /* PORT210CR */
PORTCR(211, 0xe60520d3), /* PORT211CR */
PORTCR(212, 0xe60520d4), /* PORT212CR */
PORTCR(213, 0xe60520d5), /* PORT213CR */
PORTCR(214, 0xe60520d6), /* PORT214CR */
PORTCR(215, 0xe60520d7), /* PORT215CR */
PORTCR(216, 0xe60520d8), /* PORT216CR */
PORTCR(217, 0xe60520d9), /* PORT217CR */
PORTCR(218, 0xe60520da), /* PORT218CR */
PORTCR(219, 0xe60520db), /* PORT219CR */
PORTCR(220, 0xe60520dc), /* PORT220CR */
PORTCR(221, 0xe60520dd), /* PORT221CR */
PORTCR(222, 0xe60520de), /* PORT222CR */
PORTCR(223, 0xe60520df), /* PORT223CR */
PORTCR(224, 0xe60520e0), /* PORT224CR */
PORTCR(225, 0xe60520e1), /* PORT225CR */
PORTCR(226, 0xe60520e2), /* PORT226CR */
PORTCR(227, 0xe60520e3), /* PORT227CR */
PORTCR(228, 0xe60520e4), /* PORT228CR */
PORTCR(229, 0xe60520e5), /* PORT229CR */
PORTCR(230, 0xe60520e6), /* PORT230CR */
PORTCR(231, 0xe60520e7), /* PORT231CR */
PORTCR(232, 0xe60520e8), /* PORT232CR */
PORTCR(233, 0xe60520e9), /* PORT233CR */
PORTCR(234, 0xe60520ea), /* PORT234CR */
PORTCR(235, 0xe60520eb), /* PORT235CR */
PORTCR(236, 0xe60530ec), /* PORT236CR */
PORTCR(237, 0xe60530ed), /* PORT237CR */
PORTCR(238, 0xe60530ee), /* PORT238CR */
PORTCR(239, 0xe60530ef), /* PORT239CR */
PORTCR(240, 0xe60530f0), /* PORT240CR */
PORTCR(241, 0xe60530f1), /* PORT241CR */
PORTCR(242, 0xe60530f2), /* PORT242CR */
PORTCR(243, 0xe60530f3), /* PORT243CR */
PORTCR(244, 0xe60530f4), /* PORT244CR */
PORTCR(245, 0xe60530f5), /* PORT245CR */
PORTCR(246, 0xe60530f6), /* PORT246CR */
PORTCR(247, 0xe60530f7), /* PORT247CR */
PORTCR(248, 0xe60530f8), /* PORT248CR */
PORTCR(249, 0xe60530f9), /* PORT249CR */
PORTCR(250, 0xe60530fa), /* PORT250CR */
PORTCR(251, 0xe60530fb), /* PORT251CR */
PORTCR(252, 0xe60530fc), /* PORT252CR */
PORTCR(253, 0xe60530fd), /* PORT253CR */
PORTCR(254, 0xe60530fe), /* PORT254CR */
PORTCR(255, 0xe60530ff), /* PORT255CR */
PORTCR(256, 0xe6053100), /* PORT256CR */
PORTCR(257, 0xe6053101), /* PORT257CR */
PORTCR(258, 0xe6053102), /* PORT258CR */
PORTCR(259, 0xe6053103), /* PORT259CR */
PORTCR(260, 0xe6053104), /* PORT260CR */
PORTCR(261, 0xe6053105), /* PORT261CR */
PORTCR(262, 0xe6053106), /* PORT262CR */
PORTCR(263, 0xe6053107), /* PORT263CR */
PORTCR(264, 0xe6053108), /* PORT264CR */
PORTCR(265, 0xe6053109), /* PORT265CR */
PORTCR(266, 0xe605310a), /* PORT266CR */
PORTCR(267, 0xe605310b), /* PORT267CR */
PORTCR(268, 0xe605310c), /* PORT268CR */
PORTCR(269, 0xe605310d), /* PORT269CR */
PORTCR(270, 0xe605310e), /* PORT270CR */
PORTCR(271, 0xe605310f), /* PORT271CR */
PORTCR(272, 0xe6053110), /* PORT272CR */
{ PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
0, 0,
0, 0 }
},
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
},
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
},
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
},
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
},
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT272_DATA,
PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
},
{ },
};
static struct pinmux_info sh7367_pinmux_info = {
.name = "sh7367_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PORT0,
.last_gpio = GPIO_FN_DIVLOCK,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
void sh7367_pinmux_init(void)
{
register_pinmux(&sh7367_pinmux_info);
}
| gpl-2.0 |
imoseyon/leanKernel-shamu | arch/cris/kernel/irq.c | 6895 | 1749 | /*
*
* linux/arch/cris/kernel/irq.c
*
* Copyright (c) 2000,2007 Axis Communications AB
*
* Authors: Bjorn Wesen (bjornw@axis.com)
*
* This file contains the code used by various IRQ handling routines:
* asking for different IRQs should be done through these routines
* instead of just grabbing them. Thus setups with different IRQ numbers
* shouldn't result in any weird surprises, and installing new handlers
* should be easier.
*
*/
/*
* IRQs are in fact implemented a bit like signal handlers for the kernel.
* Naturally it's not a 1:1 relation, but there are similarities.
*/
#include <linux/module.h>
#include <linux/ptrace.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <arch/system.h>
/* called by the assembler IRQ entry functions defined in irq.h
* to dispatch the interrupts to registered handlers
* interrupts are disabled upon entry - depending on if the
* interrupt was registered with IRQF_DISABLED or not, interrupts
* are re-enabled or not.
*/
asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
{
unsigned long sp;
struct pt_regs *old_regs = set_irq_regs(regs);
irq_enter();
sp = rdsp();
if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) {
printk("do_IRQ: stack overflow: %lX\n", sp);
show_stack(NULL, (unsigned long *)sp);
}
generic_handle_irq(irq);
irq_exit();
set_irq_regs(old_regs);
}
void weird_irq(void)
{
local_irq_disable();
printk("weird irq\n");
while(1);
}
| gpl-2.0 |
civato/CivZ-P900-KitKat-SOURCE | arch/cris/arch-v10/drivers/gpio.c | 6895 | 22473 | /*
* Etrax general port I/O device
*
* Copyright (c) 1999-2007 Axis Communications AB
*
* Authors: Bjorn Wesen (initial version)
* Ola Knutsson (LED handling)
* Johan Adolfsson (read/set directions, write, port G)
*/
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/etraxgpio.h>
#include <arch/svinto.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <arch/io_interface_mux.h>
#define GPIO_MAJOR 120 /* experimental MAJOR number */
#define D(x)
#if 0
static int dp_cnt;
#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
#else
#define DP(x)
#endif
static char gpio_name[] = "etrax gpio";
#if 0
static wait_queue_head_t *gpio_wq;
#endif
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
static ssize_t gpio_write(struct file *file, const char __user *buf,
size_t count, loff_t *off);
static int gpio_open(struct inode *inode, struct file *filp);
static int gpio_release(struct inode *inode, struct file *filp);
static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
/* private data per open() of this driver */
struct gpio_private {
struct gpio_private *next;
/* These fields are for PA and PB only */
volatile unsigned char *port, *shadow;
volatile unsigned char *dir, *dir_shadow;
unsigned char changeable_dir;
unsigned char changeable_bits;
unsigned char clk_mask;
unsigned char data_mask;
unsigned char write_msb;
unsigned char pad1, pad2, pad3;
/* These fields are generic */
unsigned long highalarm, lowalarm;
wait_queue_head_t alarm_wq;
int minor;
};
/* linked list of alarms to check for */
static struct gpio_private *alarmlist;
static int gpio_some_alarms; /* Set if someone uses alarm */
static unsigned long gpio_pa_irq_enabled_mask;
static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
/* Port A and B use 8 bit access, but Port G is 32 bit */
#define NUM_PORTS (GPIO_MINOR_B+1)
static volatile unsigned char *ports[NUM_PORTS] = {
R_PORT_PA_DATA,
R_PORT_PB_DATA,
};
static volatile unsigned char *shads[NUM_PORTS] = {
&port_pa_data_shadow,
&port_pb_data_shadow
};
/* What direction bits that are user changeable 1=changeable*/
#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00
#endif
#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR
#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00
#endif
#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS
#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF
#endif
#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS
#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF
#endif
static unsigned char changeable_dir[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_DIR,
CONFIG_ETRAX_PB_CHANGEABLE_DIR
};
static unsigned char changeable_bits[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_BITS,
CONFIG_ETRAX_PB_CHANGEABLE_BITS
};
static volatile unsigned char *dir[NUM_PORTS] = {
R_PORT_PA_DIR,
R_PORT_PB_DIR
};
static volatile unsigned char *dir_shadow[NUM_PORTS] = {
&port_pa_dir_shadow,
&port_pb_dir_shadow
};
/* All bits in port g that can change dir. */
static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
/* Port G is 32 bit, handle it special, some bits are both inputs
and outputs at the same time, only some of the bits can change direction
and some of them in groups of 8 bit. */
static unsigned long changeable_dir_g;
static unsigned long dir_g_in_bits;
static unsigned long dir_g_out_bits;
static unsigned long dir_g_shadow; /* 1=output */
#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
static unsigned int gpio_poll(struct file *file, poll_table *wait)
{
unsigned int mask = 0;
struct gpio_private *priv = file->private_data;
unsigned long data;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
poll_wait(file, &priv->alarm_wq, wait);
if (priv->minor == GPIO_MINOR_A) {
unsigned long tmp;
data = *R_PORT_PA_DATA;
/* PA has support for high level interrupt -
* lets activate for those low and with highalarm set
*/
tmp = ~data & priv->highalarm & 0xFF;
tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
gpio_pa_irq_enabled_mask |= tmp;
*R_IRQ_MASK1_SET = tmp;
} else if (priv->minor == GPIO_MINOR_B)
data = *R_PORT_PB_DATA;
else if (priv->minor == GPIO_MINOR_G)
data = *R_PORT_G_DATA;
else {
mask = 0;
goto out;
}
if ((data & priv->highalarm) ||
(~data & priv->lowalarm)) {
mask = POLLIN|POLLRDNORM;
}
out:
spin_unlock_irqrestore(&gpio_lock, flags);
DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
return mask;
}
int etrax_gpio_wake_up_check(void)
{
struct gpio_private *priv;
unsigned long data = 0;
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
priv = alarmlist;
while (priv) {
if (USE_PORTS(priv))
data = *priv->port;
else if (priv->minor == GPIO_MINOR_G)
data = *R_PORT_G_DATA;
if ((data & priv->highalarm) ||
(~data & priv->lowalarm)) {
DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
wake_up_interruptible(&priv->alarm_wq);
ret = 1;
}
priv = priv->next;
}
spin_unlock_irqrestore(&gpio_lock, flags);
return ret;
}
static irqreturn_t
gpio_poll_timer_interrupt(int irq, void *dev_id)
{
if (gpio_some_alarms) {
etrax_gpio_wake_up_check();
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static irqreturn_t
gpio_interrupt(int irq, void *dev_id)
{
unsigned long tmp;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
/* Find what PA interrupts are active */
tmp = (*R_IRQ_READ1);
/* Find those that we have enabled */
tmp &= gpio_pa_irq_enabled_mask;
/* Clear them.. */
*R_IRQ_MASK1_CLR = tmp;
gpio_pa_irq_enabled_mask &= ~tmp;
spin_unlock_irqrestore(&gpio_lock, flags);
if (gpio_some_alarms)
return IRQ_RETVAL(etrax_gpio_wake_up_check());
return IRQ_NONE;
}
static void gpio_write_bit(struct gpio_private *priv,
unsigned char data, int bit)
{
*priv->port = *priv->shadow &= ~(priv->clk_mask);
if (data & 1 << bit)
*priv->port = *priv->shadow |= priv->data_mask;
else
*priv->port = *priv->shadow &= ~(priv->data_mask);
/* For FPGA: min 5.0ns (DCC) before CCLK high */
*priv->port = *priv->shadow |= priv->clk_mask;
}
static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
{
int i;
if (priv->write_msb)
for (i = 7; i >= 0; i--)
gpio_write_bit(priv, data, i);
else
for (i = 0; i <= 7; i++)
gpio_write_bit(priv, data, i);
}
static ssize_t gpio_write(struct file *file, const char __user *buf,
size_t count, loff_t *off)
{
struct gpio_private *priv = file->private_data;
unsigned long flags;
ssize_t retval = count;
if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
return -EFAULT;
if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
spin_lock_irqsave(&gpio_lock, flags);
/* It must have been configured using the IO_CFG_WRITE_MODE */
/* Perhaps a better error code? */
if (priv->clk_mask == 0 || priv->data_mask == 0) {
retval = -EPERM;
goto out;
}
D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
"clk 0x%02X msb: %i\n",
count, priv->data_mask, priv->clk_mask, priv->write_msb));
while (count--)
gpio_write_byte(priv, *buf++);
out:
spin_unlock_irqrestore(&gpio_lock, flags);
return retval;
}
static int
gpio_open(struct inode *inode, struct file *filp)
{
struct gpio_private *priv;
int p = iminor(inode);
unsigned long flags;
if (p > GPIO_MINOR_LAST)
return -EINVAL;
priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->minor = p;
/* initialize the io/alarm struct */
if (USE_PORTS(priv)) { /* A and B */
priv->port = ports[p];
priv->shadow = shads[p];
priv->dir = dir[p];
priv->dir_shadow = dir_shadow[p];
priv->changeable_dir = changeable_dir[p];
priv->changeable_bits = changeable_bits[p];
} else {
priv->port = NULL;
priv->shadow = NULL;
priv->dir = NULL;
priv->dir_shadow = NULL;
priv->changeable_dir = 0;
priv->changeable_bits = 0;
}
priv->highalarm = 0;
priv->lowalarm = 0;
priv->clk_mask = 0;
priv->data_mask = 0;
init_waitqueue_head(&priv->alarm_wq);
filp->private_data = priv;
/* link it into our alarmlist */
spin_lock_irqsave(&gpio_lock, flags);
priv->next = alarmlist;
alarmlist = priv;
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
static int
gpio_release(struct inode *inode, struct file *filp)
{
struct gpio_private *p;
struct gpio_private *todel;
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
p = alarmlist;
todel = filp->private_data;
/* unlink from alarmlist and free the private structure */
if (p == todel) {
alarmlist = todel->next;
} else {
while (p->next != todel)
p = p->next;
p->next = todel->next;
}
kfree(todel);
/* Check if there are still any alarms set */
p = alarmlist;
while (p) {
if (p->highalarm | p->lowalarm) {
gpio_some_alarms = 1;
goto out;
}
p = p->next;
}
gpio_some_alarms = 0;
out:
spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
/* Main device API. ioctl's to read/set/clear bits, as well as to
* set alarms to wait for using a subsequent select().
*/
unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
{
/* Set direction 0=unchanged 1=input,
* return mask with 1=input */
if (USE_PORTS(priv)) {
*priv->dir = *priv->dir_shadow &=
~((unsigned char)arg & priv->changeable_dir);
return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
}
if (priv->minor != GPIO_MINOR_G)
return 0;
/* We must fiddle with R_GEN_CONFIG to change dir */
if (((arg & dir_g_in_bits) != arg) &&
(arg & changeable_dir_g)) {
arg &= changeable_dir_g;
/* Clear bits in genconfig to set to input */
if (arg & (1<<0)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
dir_g_in_bits |= (1<<0);
dir_g_out_bits &= ~(1<<0);
}
if ((arg & 0x0000FF00) == 0x0000FF00) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
dir_g_in_bits |= 0x0000FF00;
dir_g_out_bits &= ~0x0000FF00;
}
if ((arg & 0x00FF0000) == 0x00FF0000) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
dir_g_in_bits |= 0x00FF0000;
dir_g_out_bits &= ~0x00FF0000;
}
if (arg & (1<<24)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
dir_g_in_bits |= (1<<24);
dir_g_out_bits &= ~(1<<24);
}
D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
"genconfig to 0x%08lX "
"in_bits: 0x%08lX "
"out_bits: 0x%08lX\n",
(unsigned long)genconfig_shadow,
dir_g_in_bits, dir_g_out_bits));
*R_GEN_CONFIG = genconfig_shadow;
/* Must be a >120 ns delay before writing this again */
}
return dir_g_in_bits;
} /* setget_input */
unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
{
if (USE_PORTS(priv)) {
*priv->dir = *priv->dir_shadow |=
((unsigned char)arg & priv->changeable_dir);
return *priv->dir_shadow;
}
if (priv->minor != GPIO_MINOR_G)
return 0;
/* We must fiddle with R_GEN_CONFIG to change dir */
if (((arg & dir_g_out_bits) != arg) &&
(arg & changeable_dir_g)) {
/* Set bits in genconfig to set to output */
if (arg & (1<<0)) {
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
dir_g_out_bits |= (1<<0);
dir_g_in_bits &= ~(1<<0);
}
if ((arg & 0x0000FF00) == 0x0000FF00) {
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
dir_g_out_bits |= 0x0000FF00;
dir_g_in_bits &= ~0x0000FF00;
}
if ((arg & 0x00FF0000) == 0x00FF0000) {
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
dir_g_out_bits |= 0x00FF0000;
dir_g_in_bits &= ~0x00FF0000;
}
if (arg & (1<<24)) {
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
dir_g_out_bits |= (1<<24);
dir_g_in_bits &= ~(1<<24);
}
D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
"genconfig to 0x%08lX "
"in_bits: 0x%08lX "
"out_bits: 0x%08lX\n",
(unsigned long)genconfig_shadow,
dir_g_in_bits, dir_g_out_bits));
*R_GEN_CONFIG = genconfig_shadow;
/* Must be a >120 ns delay before writing this again */
}
return dir_g_out_bits & 0x7FFFFFFF;
} /* setget_output */
static int
gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
unsigned long flags;
unsigned long val;
int ret = 0;
struct gpio_private *priv = file->private_data;
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
return -EINVAL;
switch (_IOC_NR(cmd)) {
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
// read the port
spin_lock_irqsave(&gpio_lock, flags);
if (USE_PORTS(priv)) {
ret = *priv->port;
} else if (priv->minor == GPIO_MINOR_G) {
ret = (*R_PORT_G_DATA) & 0x7FFFFFFF;
}
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_SETBITS:
// set changeable bits with a 1 in arg
spin_lock_irqsave(&gpio_lock, flags);
if (USE_PORTS(priv)) {
*priv->port = *priv->shadow |=
((unsigned char)arg & priv->changeable_bits);
} else if (priv->minor == GPIO_MINOR_G) {
*R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
}
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_CLRBITS:
// clear changeable bits with a 1 in arg
spin_lock_irqsave(&gpio_lock, flags);
if (USE_PORTS(priv)) {
*priv->port = *priv->shadow &=
~((unsigned char)arg & priv->changeable_bits);
} else if (priv->minor == GPIO_MINOR_G) {
*R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
}
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_HIGHALARM:
// set alarm when bits with 1 in arg go high
spin_lock_irqsave(&gpio_lock, flags);
priv->highalarm |= arg;
gpio_some_alarms = 1;
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_LOWALARM:
// set alarm when bits with 1 in arg go low
spin_lock_irqsave(&gpio_lock, flags);
priv->lowalarm |= arg;
gpio_some_alarms = 1;
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_CLRALARM:
/* clear alarm for bits with 1 in arg */
spin_lock_irqsave(&gpio_lock, flags);
priv->highalarm &= ~arg;
priv->lowalarm &= ~arg;
{
/* Must update gpio_some_alarms */
struct gpio_private *p = alarmlist;
int some_alarms;
p = alarmlist;
some_alarms = 0;
while (p) {
if (p->highalarm | p->lowalarm) {
some_alarms = 1;
break;
}
p = p->next;
}
gpio_some_alarms = some_alarms;
}
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
/* Read direction 0=input 1=output */
spin_lock_irqsave(&gpio_lock, flags);
if (USE_PORTS(priv)) {
ret = *priv->dir_shadow;
} else if (priv->minor == GPIO_MINOR_G) {
/* Note: Some bits are both in and out,
* Those that are dual is set here as well.
*/
ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
}
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
/* Set direction 0=unchanged 1=input,
* return mask with 1=input
*/
spin_lock_irqsave(&gpio_lock, flags);
ret = setget_input(priv, arg) & 0x7FFFFFFF;
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
/* Set direction 0=unchanged 1=output,
* return mask with 1=output
*/
spin_lock_irqsave(&gpio_lock, flags);
ret = setget_output(priv, arg) & 0x7FFFFFFF;
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_SHUTDOWN:
spin_lock_irqsave(&gpio_lock, flags);
SOFT_SHUTDOWN();
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_GET_PWR_BT:
spin_lock_irqsave(&gpio_lock, flags);
#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
#else
ret = 0;
#endif
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_CFG_WRITE_MODE:
spin_lock_irqsave(&gpio_lock, flags);
priv->clk_mask = arg & 0xFF;
priv->data_mask = (arg >> 8) & 0xFF;
priv->write_msb = (arg >> 16) & 0x01;
/* Check if we're allowed to change the bits and
* the direction is correct
*/
if (!((priv->clk_mask & priv->changeable_bits) &&
(priv->data_mask & priv->changeable_bits) &&
(priv->clk_mask & *priv->dir_shadow) &&
(priv->data_mask & *priv->dir_shadow)))
{
priv->clk_mask = 0;
priv->data_mask = 0;
ret = -EPERM;
}
spin_unlock_irqrestore(&gpio_lock, flags);
break;
case IO_READ_INBITS:
/* *arg is result of reading the input pins */
spin_lock_irqsave(&gpio_lock, flags);
if (USE_PORTS(priv)) {
val = *priv->port;
} else if (priv->minor == GPIO_MINOR_G) {
val = *R_PORT_G_DATA;
}
spin_unlock_irqrestore(&gpio_lock, flags);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
case IO_READ_OUTBITS:
/* *arg is result of reading the output shadow */
spin_lock_irqsave(&gpio_lock, flags);
if (USE_PORTS(priv)) {
val = *priv->shadow;
} else if (priv->minor == GPIO_MINOR_G) {
val = port_g_data_shadow;
}
spin_unlock_irqrestore(&gpio_lock, flags);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
case IO_SETGET_INPUT:
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
{
ret = -EFAULT;
break;
}
spin_lock_irqsave(&gpio_lock, flags);
val = setget_input(priv, val);
spin_unlock_irqrestore(&gpio_lock, flags);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
ret = -EFAULT;
break;
}
spin_lock_irqsave(&gpio_lock, flags);
val = setget_output(priv, val);
spin_unlock_irqrestore(&gpio_lock, flags);
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
default:
spin_lock_irqsave(&gpio_lock, flags);
if (priv->minor == GPIO_MINOR_LEDS)
ret = gpio_leds_ioctl(cmd, arg);
else
ret = -EINVAL;
spin_unlock_irqrestore(&gpio_lock, flags);
} /* switch */
return ret;
}
static int
gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
{
unsigned char green;
unsigned char red;
switch (_IOC_NR(cmd)) {
case IO_LEDACTIVE_SET:
green = ((unsigned char)arg) & 1;
red = (((unsigned char)arg) >> 1) & 1;
CRIS_LED_ACTIVE_SET_G(green);
CRIS_LED_ACTIVE_SET_R(red);
break;
case IO_LED_SETBIT:
CRIS_LED_BIT_SET(arg);
break;
case IO_LED_CLRBIT:
CRIS_LED_BIT_CLR(arg);
break;
default:
return -EINVAL;
} /* switch */
return 0;
}
static const struct file_operations gpio_fops = {
.owner = THIS_MODULE,
.poll = gpio_poll,
.unlocked_ioctl = gpio_ioctl,
.write = gpio_write,
.open = gpio_open,
.release = gpio_release,
.llseek = noop_llseek,
};
static void ioif_watcher(const unsigned int gpio_in_available,
const unsigned int gpio_out_available,
const unsigned char pa_available,
const unsigned char pb_available)
{
unsigned long int flags;
D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
"PA: 0x%02x PB: 0x%02x\n",
gpio_in_available, gpio_out_available,
pa_available, pb_available));
spin_lock_irqsave(&gpio_lock, flags);
dir_g_in_bits = gpio_in_available;
dir_g_out_bits = gpio_out_available;
/* Initialise the dir_g_shadow etc. depending on genconfig */
/* 0=input 1=output */
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
dir_g_shadow |= (1 << 0);
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
dir_g_shadow |= 0x0000FF00;
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
dir_g_shadow |= 0x00FF0000;
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
dir_g_shadow |= (1 << 24);
changeable_dir_g = changeable_dir_g_mask;
changeable_dir_g &= dir_g_out_bits;
changeable_dir_g &= dir_g_in_bits;
/* Correct the bits that can change direction */
dir_g_out_bits &= ~changeable_dir_g;
dir_g_out_bits |= dir_g_shadow;
dir_g_in_bits &= ~changeable_dir_g;
dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
spin_unlock_irqrestore(&gpio_lock, flags);
printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
"val: %08lX\n",
dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
dir_g_shadow, changeable_dir_g);
}
/* main driver initialization routine, called from mem.c */
static int __init gpio_init(void)
{
int res;
#if defined (CONFIG_ETRAX_CSP0_LEDS)
int i;
#endif
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
if (res < 0) {
printk(KERN_ERR "gpio: couldn't get a major number.\n");
return res;
}
/* Clear all leds */
#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
CRIS_LED_NETWORK_SET(0);
CRIS_LED_ACTIVE_SET(0);
CRIS_LED_DISK_READ(0);
CRIS_LED_DISK_WRITE(0);
#if defined (CONFIG_ETRAX_CSP0_LEDS)
for (i = 0; i < 32; i++)
CRIS_LED_BIT_SET(i);
#endif
#endif
/* The I/O interface allocation watcher will be called when
* registering it. */
if (cris_io_interface_register_watcher(ioif_watcher)){
printk(KERN_WARNING "gpio_init: Failed to install IO "
"if allocator watcher\n");
}
printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
"Axis Communications AB\n");
/* We call etrax_gpio_wake_up_check() from timer interrupt and
* from cpu_idle() in kernel/process.c
* The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
* in some tests.
*/
res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name);
if (res) {
printk(KERN_CRIT "err: timer0 irq for gpio\n");
return res;
}
res = request_irq(PA_IRQ_NBR, gpio_interrupt,
IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name);
if (res)
printk(KERN_CRIT "err: PA irq for gpio\n");
return res;
}
/* this makes sure that gpio_init is called during kernel boot */
module_init(gpio_init);
| gpl-2.0 |
agx/linux-wpan-next | sound/isa/msnd/msnd_midi.c | 9711 | 5014 | /*
* Copyright (c) by Jaroslav Kysela <perex@perex.cz>
* Copyright (c) 2009 by Krzysztof Helt
* Routines for control of MPU-401 in UART mode
*
* MPU-401 supports UART mode which is not capable generate transmit
* interrupts thus output is done via polling. Also, if irq < 0, then
* input is done also via polling. Do not expect good performance.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <sound/core.h>
#include <sound/rawmidi.h>
#include "msnd.h"
#define MSNDMIDI_MODE_BIT_INPUT 0
#define MSNDMIDI_MODE_BIT_OUTPUT 1
#define MSNDMIDI_MODE_BIT_INPUT_TRIGGER 2
#define MSNDMIDI_MODE_BIT_OUTPUT_TRIGGER 3
struct snd_msndmidi {
struct snd_msnd *dev;
unsigned long mode; /* MSNDMIDI_MODE_XXXX */
struct snd_rawmidi_substream *substream_input;
spinlock_t input_lock;
};
/*
* input/output open/close - protected by open_mutex in rawmidi.c
*/
static int snd_msndmidi_input_open(struct snd_rawmidi_substream *substream)
{
struct snd_msndmidi *mpu;
snd_printdd("snd_msndmidi_input_open()\n");
mpu = substream->rmidi->private_data;
mpu->substream_input = substream;
snd_msnd_enable_irq(mpu->dev);
snd_msnd_send_dsp_cmd(mpu->dev, HDEX_MIDI_IN_START);
set_bit(MSNDMIDI_MODE_BIT_INPUT, &mpu->mode);
return 0;
}
static int snd_msndmidi_input_close(struct snd_rawmidi_substream *substream)
{
struct snd_msndmidi *mpu;
mpu = substream->rmidi->private_data;
snd_msnd_send_dsp_cmd(mpu->dev, HDEX_MIDI_IN_STOP);
clear_bit(MSNDMIDI_MODE_BIT_INPUT, &mpu->mode);
mpu->substream_input = NULL;
snd_msnd_disable_irq(mpu->dev);
return 0;
}
static void snd_msndmidi_input_drop(struct snd_msndmidi *mpu)
{
u16 tail;
tail = readw(mpu->dev->MIDQ + JQS_wTail);
writew(tail, mpu->dev->MIDQ + JQS_wHead);
}
/*
* trigger input
*/
static void snd_msndmidi_input_trigger(struct snd_rawmidi_substream *substream,
int up)
{
unsigned long flags;
struct snd_msndmidi *mpu;
snd_printdd("snd_msndmidi_input_trigger(, %i)\n", up);
mpu = substream->rmidi->private_data;
spin_lock_irqsave(&mpu->input_lock, flags);
if (up) {
if (!test_and_set_bit(MSNDMIDI_MODE_BIT_INPUT_TRIGGER,
&mpu->mode))
snd_msndmidi_input_drop(mpu);
} else {
clear_bit(MSNDMIDI_MODE_BIT_INPUT_TRIGGER, &mpu->mode);
}
spin_unlock_irqrestore(&mpu->input_lock, flags);
if (up)
snd_msndmidi_input_read(mpu);
}
void snd_msndmidi_input_read(void *mpuv)
{
unsigned long flags;
struct snd_msndmidi *mpu = mpuv;
void *pwMIDQData = mpu->dev->mappedbase + MIDQ_DATA_BUFF;
spin_lock_irqsave(&mpu->input_lock, flags);
while (readw(mpu->dev->MIDQ + JQS_wTail) !=
readw(mpu->dev->MIDQ + JQS_wHead)) {
u16 wTmp, val;
val = readw(pwMIDQData + 2 * readw(mpu->dev->MIDQ + JQS_wHead));
if (test_bit(MSNDMIDI_MODE_BIT_INPUT_TRIGGER,
&mpu->mode))
snd_rawmidi_receive(mpu->substream_input,
(unsigned char *)&val, 1);
wTmp = readw(mpu->dev->MIDQ + JQS_wHead) + 1;
if (wTmp > readw(mpu->dev->MIDQ + JQS_wSize))
writew(0, mpu->dev->MIDQ + JQS_wHead);
else
writew(wTmp, mpu->dev->MIDQ + JQS_wHead);
}
spin_unlock_irqrestore(&mpu->input_lock, flags);
}
EXPORT_SYMBOL(snd_msndmidi_input_read);
static struct snd_rawmidi_ops snd_msndmidi_input = {
.open = snd_msndmidi_input_open,
.close = snd_msndmidi_input_close,
.trigger = snd_msndmidi_input_trigger,
};
static void snd_msndmidi_free(struct snd_rawmidi *rmidi)
{
struct snd_msndmidi *mpu = rmidi->private_data;
kfree(mpu);
}
int snd_msndmidi_new(struct snd_card *card, int device)
{
struct snd_msnd *chip = card->private_data;
struct snd_msndmidi *mpu;
struct snd_rawmidi *rmidi;
int err;
err = snd_rawmidi_new(card, "MSND-MIDI", device, 1, 1, &rmidi);
if (err < 0)
return err;
mpu = kzalloc(sizeof(*mpu), GFP_KERNEL);
if (mpu == NULL) {
snd_device_free(card, rmidi);
return -ENOMEM;
}
mpu->dev = chip;
chip->msndmidi_mpu = mpu;
rmidi->private_data = mpu;
rmidi->private_free = snd_msndmidi_free;
spin_lock_init(&mpu->input_lock);
strcpy(rmidi->name, "MSND MIDI");
snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
&snd_msndmidi_input);
rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
return 0;
}
| gpl-2.0 |
F35X70/Z7Mini_NX507J_H128_kernel | arch/m68k/platform/coldfire/cache.c | 12015 | 1286 | /***************************************************************************/
/*
* cache.c -- general ColdFire Cache maintenance code
*
* Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/***************************************************************************/
#ifdef CACHE_PUSH
/***************************************************************************/
/*
* Use cpushl to push all dirty cache lines back to memory.
* Older versions of GAS don't seem to know how to generate the
* ColdFire cpushl instruction... Oh well, bit stuff it for now.
*/
void mcf_cache_push(void)
{
__asm__ __volatile__ (
"clrl %%d0\n\t"
"1:\n\t"
"movel %%d0,%%a0\n\t"
"2:\n\t"
".word 0xf468\n\t"
"addl %0,%%a0\n\t"
"cmpl %1,%%a0\n\t"
"blt 2b\n\t"
"addql #1,%%d0\n\t"
"cmpil %2,%%d0\n\t"
"bne 1b\n\t"
: /* No output */
: "i" (CACHE_LINE_SIZE),
"i" (DCACHE_SIZE / CACHE_WAYS),
"i" (CACHE_WAYS)
: "d0", "a0" );
}
/***************************************************************************/
#endif /* CACHE_PUSH */
/***************************************************************************/
| gpl-2.0 |
photon-dev-team/ics_kernel | drivers/media/video/gspca/spca505.c | 496 | 19547 | /*
* SPCA505 chip based cameras initialization data
*
* V4L2 by Jean-Francis Moine <http://moinejf.free.fr>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define MODULE_NAME "spca505"
#include "gspca.h"
MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
MODULE_DESCRIPTION("GSPCA/SPCA505 USB Camera Driver");
MODULE_LICENSE("GPL");
/* specific webcam descriptor */
struct sd {
struct gspca_dev gspca_dev; /* !! must be the first item */
u8 brightness;
u8 subtype;
#define IntelPCCameraPro 0
#define Nxultra 1
};
/* V4L2 controls supported by the driver */
static int sd_setbrightness(struct gspca_dev *gspca_dev, __s32 val);
static int sd_getbrightness(struct gspca_dev *gspca_dev, __s32 *val);
static struct ctrl sd_ctrls[] = {
{
{
.id = V4L2_CID_BRIGHTNESS,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Brightness",
.minimum = 0,
.maximum = 255,
.step = 1,
#define BRIGHTNESS_DEF 127
.default_value = BRIGHTNESS_DEF,
},
.set = sd_setbrightness,
.get = sd_getbrightness,
},
};
static const struct v4l2_pix_format vga_mode[] = {
{160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
.bytesperline = 160,
.sizeimage = 160 * 120 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 4},
{176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
.bytesperline = 176,
.sizeimage = 176 * 144 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 3},
{320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
.bytesperline = 320,
.sizeimage = 320 * 240 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 2},
{352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
.bytesperline = 352,
.sizeimage = 352 * 288 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 1},
{640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
.bytesperline = 640,
.sizeimage = 640 * 480 * 3 / 2,
.colorspace = V4L2_COLORSPACE_SRGB,
.priv = 0},
};
#define SPCA50X_OFFSET_DATA 10
#define SPCA50X_REG_USB 0x02 /* spca505 501 */
#define SPCA50X_USB_CTRL 0x00 /* spca505 */
#define SPCA50X_CUSB_ENABLE 0x01 /* spca505 */
#define SPCA50X_REG_GLOBAL 0x03 /* spca505 */
#define SPCA50X_GMISC0_IDSEL 0x01 /* Global control device ID select spca505 */
#define SPCA50X_GLOBAL_MISC0 0x00 /* Global control miscellaneous 0 spca505 */
#define SPCA50X_GLOBAL_MISC1 0x01 /* 505 */
#define SPCA50X_GLOBAL_MISC3 0x03 /* 505 */
#define SPCA50X_GMISC3_SAA7113RST 0x20 /* Not sure about this one spca505 */
/* Image format and compression control */
#define SPCA50X_REG_COMPRESS 0x04
/*
* Data to initialize a SPCA505. Common to the CCD and external modes
*/
static const u8 spca505_init_data[][3] = {
/* bmRequest,value,index */
{SPCA50X_REG_GLOBAL, SPCA50X_GMISC3_SAA7113RST, SPCA50X_GLOBAL_MISC3},
/* Sensor reset */
{SPCA50X_REG_GLOBAL, 0x00, SPCA50X_GLOBAL_MISC3},
{SPCA50X_REG_GLOBAL, 0x00, SPCA50X_GLOBAL_MISC1},
/* Block USB reset */
{SPCA50X_REG_GLOBAL, SPCA50X_GMISC0_IDSEL, SPCA50X_GLOBAL_MISC0},
{0x05, 0x01, 0x10},
/* Maybe power down some stuff */
{0x05, 0x0f, 0x11},
/* Setup internal CCD ? */
{0x06, 0x10, 0x08},
{0x06, 0x00, 0x09},
{0x06, 0x00, 0x0a},
{0x06, 0x00, 0x0b},
{0x06, 0x10, 0x0c},
{0x06, 0x00, 0x0d},
{0x06, 0x00, 0x0e},
{0x06, 0x00, 0x0f},
{0x06, 0x10, 0x10},
{0x06, 0x02, 0x11},
{0x06, 0x00, 0x12},
{0x06, 0x04, 0x13},
{0x06, 0x02, 0x14},
{0x06, 0x8a, 0x51},
{0x06, 0x40, 0x52},
{0x06, 0xb6, 0x53},
{0x06, 0x3d, 0x54},
{}
};
/*
* Data to initialize the camera using the internal CCD
*/
static const u8 spca505_open_data_ccd[][3] = {
/* bmRequest,value,index */
/* Internal CCD data set */
{0x03, 0x04, 0x01},
/* This could be a reset */
{0x03, 0x00, 0x01},
/* Setup compression and image registers. 0x6 and 0x7 seem to be
related to H&V hold, and are resolution mode specific */
{0x04, 0x10, 0x01},
/* DIFF(0x50), was (0x10) */
{0x04, 0x00, 0x04},
{0x04, 0x00, 0x05},
{0x04, 0x20, 0x06},
{0x04, 0x20, 0x07},
{0x08, 0x0a, 0x00},
/* DIFF (0x4a), was (0xa) */
{0x05, 0x00, 0x10},
{0x05, 0x00, 0x11},
{0x05, 0x00, 0x00},
/* DIFF not written */
{0x05, 0x00, 0x01},
/* DIFF not written */
{0x05, 0x00, 0x02},
/* DIFF not written */
{0x05, 0x00, 0x03},
/* DIFF not written */
{0x05, 0x00, 0x04},
/* DIFF not written */
{0x05, 0x80, 0x05},
/* DIFF not written */
{0x05, 0xe0, 0x06},
/* DIFF not written */
{0x05, 0x20, 0x07},
/* DIFF not written */
{0x05, 0xa0, 0x08},
/* DIFF not written */
{0x05, 0x0, 0x12},
/* DIFF not written */
{0x05, 0x02, 0x0f},
/* DIFF not written */
{0x05, 0x10, 0x46},
/* DIFF not written */
{0x05, 0x8, 0x4a},
/* DIFF not written */
{0x03, 0x08, 0x03},
/* DIFF (0x3,0x28,0x3) */
{0x03, 0x08, 0x01},
{0x03, 0x0c, 0x03},
/* DIFF not written */
{0x03, 0x21, 0x00},
/* DIFF (0x39) */
/* Extra block copied from init to hopefully ensure CCD is in a sane state */
{0x06, 0x10, 0x08},
{0x06, 0x00, 0x09},
{0x06, 0x00, 0x0a},
{0x06, 0x00, 0x0b},
{0x06, 0x10, 0x0c},
{0x06, 0x00, 0x0d},
{0x06, 0x00, 0x0e},
{0x06, 0x00, 0x0f},
{0x06, 0x10, 0x10},
{0x06, 0x02, 0x11},
{0x06, 0x00, 0x12},
{0x06, 0x04, 0x13},
{0x06, 0x02, 0x14},
{0x06, 0x8a, 0x51},
{0x06, 0x40, 0x52},
{0x06, 0xb6, 0x53},
{0x06, 0x3d, 0x54},
/* End of extra block */
{0x06, 0x3f, 0x1},
/* Block skipped */
{0x06, 0x10, 0x02},
{0x06, 0x64, 0x07},
{0x06, 0x10, 0x08},
{0x06, 0x00, 0x09},
{0x06, 0x00, 0x0a},
{0x06, 0x00, 0x0b},
{0x06, 0x10, 0x0c},
{0x06, 0x00, 0x0d},
{0x06, 0x00, 0x0e},
{0x06, 0x00, 0x0f},
{0x06, 0x10, 0x10},
{0x06, 0x02, 0x11},
{0x06, 0x00, 0x12},
{0x06, 0x04, 0x13},
{0x06, 0x02, 0x14},
{0x06, 0x8a, 0x51},
{0x06, 0x40, 0x52},
{0x06, 0xb6, 0x53},
{0x06, 0x3d, 0x54},
{0x06, 0x60, 0x57},
{0x06, 0x20, 0x58},
{0x06, 0x15, 0x59},
{0x06, 0x05, 0x5a},
{0x05, 0x01, 0xc0},
{0x05, 0x10, 0xcb},
{0x05, 0x80, 0xc1},
/* */
{0x05, 0x0, 0xc2},
/* 4 was 0 */
{0x05, 0x00, 0xca},
{0x05, 0x80, 0xc1},
/* */
{0x05, 0x04, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x0, 0xc1},
/* */
{0x05, 0x00, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x40, 0xc1},
/* */
{0x05, 0x17, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x80, 0xc1},
/* */
{0x05, 0x06, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x80, 0xc1},
/* */
{0x05, 0x04, 0xc2},
{0x05, 0x00, 0xca},
{0x03, 0x4c, 0x3},
{0x03, 0x18, 0x1},
{0x06, 0x70, 0x51},
{0x06, 0xbe, 0x53},
{0x06, 0x71, 0x57},
{0x06, 0x20, 0x58},
{0x06, 0x05, 0x59},
{0x06, 0x15, 0x5a},
{0x04, 0x00, 0x08},
/* Compress = OFF (0x1 to turn on) */
{0x04, 0x12, 0x09},
{0x04, 0x21, 0x0a},
{0x04, 0x10, 0x0b},
{0x04, 0x21, 0x0c},
{0x04, 0x05, 0x00},
/* was 5 (Image Type ? ) */
{0x04, 0x00, 0x01},
{0x06, 0x3f, 0x01},
{0x04, 0x00, 0x04},
{0x04, 0x00, 0x05},
{0x04, 0x40, 0x06},
{0x04, 0x40, 0x07},
{0x06, 0x1c, 0x17},
{0x06, 0xe2, 0x19},
{0x06, 0x1c, 0x1b},
{0x06, 0xe2, 0x1d},
{0x06, 0xaa, 0x1f},
{0x06, 0x70, 0x20},
{0x05, 0x01, 0x10},
{0x05, 0x00, 0x11},
{0x05, 0x01, 0x00},
{0x05, 0x05, 0x01},
{0x05, 0x00, 0xc1},
/* */
{0x05, 0x00, 0xc2},
{0x05, 0x00, 0xca},
{0x06, 0x70, 0x51},
{0x06, 0xbe, 0x53},
{}
};
/*
* Made by Tomasz Zablocki (skalamandra@poczta.onet.pl)
* SPCA505b chip based cameras initialization data
*/
/* jfm */
#define initial_brightness 0x7f /* 0x0(white)-0xff(black) */
/* #define initial_brightness 0x0 //0x0(white)-0xff(black) */
/*
* Data to initialize a SPCA505. Common to the CCD and external modes
*/
static const u8 spca505b_init_data[][3] = {
/* start */
{0x02, 0x00, 0x00}, /* init */
{0x02, 0x00, 0x01},
{0x02, 0x00, 0x02},
{0x02, 0x00, 0x03},
{0x02, 0x00, 0x04},
{0x02, 0x00, 0x05},
{0x02, 0x00, 0x06},
{0x02, 0x00, 0x07},
{0x02, 0x00, 0x08},
{0x02, 0x00, 0x09},
{0x03, 0x00, 0x00},
{0x03, 0x00, 0x01},
{0x03, 0x00, 0x02},
{0x03, 0x00, 0x03},
{0x03, 0x00, 0x04},
{0x03, 0x00, 0x05},
{0x03, 0x00, 0x06},
{0x04, 0x00, 0x00},
{0x04, 0x00, 0x02},
{0x04, 0x00, 0x04},
{0x04, 0x00, 0x05},
{0x04, 0x00, 0x06},
{0x04, 0x00, 0x07},
{0x04, 0x00, 0x08},
{0x04, 0x00, 0x09},
{0x04, 0x00, 0x0a},
{0x04, 0x00, 0x0b},
{0x04, 0x00, 0x0c},
{0x07, 0x00, 0x00},
{0x07, 0x00, 0x03},
{0x08, 0x00, 0x00},
{0x08, 0x00, 0x01},
{0x08, 0x00, 0x02},
{0x00, 0x01, 0x00},
{0x00, 0x01, 0x01},
{0x00, 0x01, 0x34},
{0x00, 0x01, 0x35},
{0x06, 0x18, 0x08},
{0x06, 0xfc, 0x09},
{0x06, 0xfc, 0x0a},
{0x06, 0xfc, 0x0b},
{0x06, 0x18, 0x0c},
{0x06, 0xfc, 0x0d},
{0x06, 0xfc, 0x0e},
{0x06, 0xfc, 0x0f},
{0x06, 0x18, 0x10},
{0x06, 0xfe, 0x12},
{0x06, 0x00, 0x11},
{0x06, 0x00, 0x14},
{0x06, 0x00, 0x13},
{0x06, 0x28, 0x51},
{0x06, 0xff, 0x53},
{0x02, 0x00, 0x08},
{0x03, 0x00, 0x03},
{0x03, 0x10, 0x03},
{}
};
/*
* Data to initialize the camera using the internal CCD
*/
static const u8 spca505b_open_data_ccd[][3] = {
/* {0x02,0x00,0x00}, */
{0x03, 0x04, 0x01}, /* rst */
{0x03, 0x00, 0x01},
{0x03, 0x00, 0x00},
{0x03, 0x21, 0x00},
{0x03, 0x00, 0x04},
{0x03, 0x00, 0x03},
{0x03, 0x18, 0x03},
{0x03, 0x08, 0x01},
{0x03, 0x1c, 0x03},
{0x03, 0x5c, 0x03},
{0x03, 0x5c, 0x03},
{0x03, 0x18, 0x01},
/* same as 505 */
{0x04, 0x10, 0x01},
{0x04, 0x00, 0x04},
{0x04, 0x00, 0x05},
{0x04, 0x20, 0x06},
{0x04, 0x20, 0x07},
{0x08, 0x0a, 0x00},
{0x05, 0x00, 0x10},
{0x05, 0x00, 0x11},
{0x05, 0x00, 0x12},
{0x05, 0x6f, 0x00},
{0x05, initial_brightness >> 6, 0x00},
{0x05, (initial_brightness << 2) & 0xff, 0x01},
{0x05, 0x00, 0x02},
{0x05, 0x01, 0x03},
{0x05, 0x00, 0x04},
{0x05, 0x03, 0x05},
{0x05, 0xe0, 0x06},
{0x05, 0x20, 0x07},
{0x05, 0xa0, 0x08},
{0x05, 0x00, 0x12},
{0x05, 0x02, 0x0f},
{0x05, 0x80, 0x14}, /* max exposure off (0=on) */
{0x05, 0x01, 0xb0},
{0x05, 0x01, 0xbf},
{0x03, 0x02, 0x06},
{0x05, 0x10, 0x46},
{0x05, 0x08, 0x4a},
{0x06, 0x00, 0x01},
{0x06, 0x10, 0x02},
{0x06, 0x64, 0x07},
{0x06, 0x18, 0x08},
{0x06, 0xfc, 0x09},
{0x06, 0xfc, 0x0a},
{0x06, 0xfc, 0x0b},
{0x04, 0x00, 0x01},
{0x06, 0x18, 0x0c},
{0x06, 0xfc, 0x0d},
{0x06, 0xfc, 0x0e},
{0x06, 0xfc, 0x0f},
{0x06, 0x11, 0x10}, /* contrast */
{0x06, 0x00, 0x11},
{0x06, 0xfe, 0x12},
{0x06, 0x00, 0x13},
{0x06, 0x00, 0x14},
{0x06, 0x9d, 0x51},
{0x06, 0x40, 0x52},
{0x06, 0x7c, 0x53},
{0x06, 0x40, 0x54},
{0x06, 0x02, 0x57},
{0x06, 0x03, 0x58},
{0x06, 0x15, 0x59},
{0x06, 0x05, 0x5a},
{0x06, 0x03, 0x56},
{0x06, 0x02, 0x3f},
{0x06, 0x00, 0x40},
{0x06, 0x39, 0x41},
{0x06, 0x69, 0x42},
{0x06, 0x87, 0x43},
{0x06, 0x9e, 0x44},
{0x06, 0xb1, 0x45},
{0x06, 0xbf, 0x46},
{0x06, 0xcc, 0x47},
{0x06, 0xd5, 0x48},
{0x06, 0xdd, 0x49},
{0x06, 0xe3, 0x4a},
{0x06, 0xe8, 0x4b},
{0x06, 0xed, 0x4c},
{0x06, 0xf2, 0x4d},
{0x06, 0xf7, 0x4e},
{0x06, 0xfc, 0x4f},
{0x06, 0xff, 0x50},
{0x05, 0x01, 0xc0},
{0x05, 0x10, 0xcb},
{0x05, 0x40, 0xc1},
{0x05, 0x04, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x40, 0xc1},
{0x05, 0x09, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0xc0, 0xc1},
{0x05, 0x09, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x40, 0xc1},
{0x05, 0x59, 0xc2},
{0x05, 0x00, 0xca},
{0x04, 0x00, 0x01},
{0x05, 0x80, 0xc1},
{0x05, 0xec, 0xc2},
{0x05, 0x0, 0xca},
{0x06, 0x02, 0x57},
{0x06, 0x01, 0x58},
{0x06, 0x15, 0x59},
{0x06, 0x0a, 0x5a},
{0x06, 0x01, 0x57},
{0x06, 0x8a, 0x03},
{0x06, 0x0a, 0x6c},
{0x06, 0x30, 0x01},
{0x06, 0x20, 0x02},
{0x06, 0x00, 0x03},
{0x05, 0x8c, 0x25},
{0x06, 0x4d, 0x51}, /* maybe saturation (4d) */
{0x06, 0x84, 0x53}, /* making green (84) */
{0x06, 0x00, 0x57}, /* sharpness (1) */
{0x06, 0x18, 0x08},
{0x06, 0xfc, 0x09},
{0x06, 0xfc, 0x0a},
{0x06, 0xfc, 0x0b},
{0x06, 0x18, 0x0c}, /* maybe hue (18) */
{0x06, 0xfc, 0x0d},
{0x06, 0xfc, 0x0e},
{0x06, 0xfc, 0x0f},
{0x06, 0x18, 0x10}, /* maybe contrast (18) */
{0x05, 0x01, 0x02},
{0x04, 0x00, 0x08}, /* compression */
{0x04, 0x12, 0x09},
{0x04, 0x21, 0x0a},
{0x04, 0x10, 0x0b},
{0x04, 0x21, 0x0c},
{0x04, 0x1d, 0x00}, /* imagetype (1d) */
{0x04, 0x41, 0x01}, /* hardware snapcontrol */
{0x04, 0x00, 0x04},
{0x04, 0x00, 0x05},
{0x04, 0x10, 0x06},
{0x04, 0x10, 0x07},
{0x04, 0x40, 0x06},
{0x04, 0x40, 0x07},
{0x04, 0x00, 0x04},
{0x04, 0x00, 0x05},
{0x06, 0x1c, 0x17},
{0x06, 0xe2, 0x19},
{0x06, 0x1c, 0x1b},
{0x06, 0xe2, 0x1d},
{0x06, 0x5f, 0x1f},
{0x06, 0x32, 0x20},
{0x05, initial_brightness >> 6, 0x00},
{0x05, (initial_brightness << 2) & 0xff, 0x01},
{0x05, 0x06, 0xc1},
{0x05, 0x58, 0xc2},
{0x05, 0x00, 0xca},
{0x05, 0x00, 0x11},
{}
};
static int reg_write(struct usb_device *dev,
u16 req, u16 index, u16 value)
{
int ret;
ret = usb_control_msg(dev,
usb_sndctrlpipe(dev, 0),
req,
USB_TYPE_VENDOR | USB_RECIP_DEVICE,
value, index, NULL, 0, 500);
PDEBUG(D_USBO, "reg write: 0x%02x,0x%02x:0x%02x, %d",
req, index, value, ret);
if (ret < 0)
PDEBUG(D_ERR, "reg write: error %d", ret);
return ret;
}
/* returns: negative is error, pos or zero is data */
static int reg_read(struct gspca_dev *gspca_dev,
u16 req, /* bRequest */
u16 index) /* wIndex */
{
int ret;
ret = usb_control_msg(gspca_dev->dev,
usb_rcvctrlpipe(gspca_dev->dev, 0),
req,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, /* value */
index,
gspca_dev->usb_buf, 2,
500); /* timeout */
if (ret < 0)
return ret;
return (gspca_dev->usb_buf[1] << 8) + gspca_dev->usb_buf[0];
}
static int write_vector(struct gspca_dev *gspca_dev,
const u8 data[][3])
{
struct usb_device *dev = gspca_dev->dev;
int ret, i = 0;
while (data[i][0] != 0) {
ret = reg_write(dev, data[i][0], data[i][2], data[i][1]);
if (ret < 0)
return ret;
i++;
}
return 0;
}
/* this function is called at probe time */
static int sd_config(struct gspca_dev *gspca_dev,
const struct usb_device_id *id)
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
cam = &gspca_dev->cam;
cam->cam_mode = vga_mode;
sd->subtype = id->driver_info;
if (sd->subtype != IntelPCCameraPro)
cam->nmodes = ARRAY_SIZE(vga_mode);
else /* no 640x480 for IntelPCCameraPro */
cam->nmodes = ARRAY_SIZE(vga_mode) - 1;
sd->brightness = BRIGHTNESS_DEF;
return 0;
}
/* this function is called at probe and resume time */
static int sd_init(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
if (write_vector(gspca_dev,
sd->subtype == Nxultra
? spca505b_init_data
: spca505_init_data))
return -EIO;
return 0;
}
static void setbrightness(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
u8 brightness = sd->brightness;
reg_write(gspca_dev->dev, 0x05, 0x00, (255 - brightness) >> 6);
reg_write(gspca_dev->dev, 0x05, 0x01, (255 - brightness) << 2);
}
static int sd_start(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
struct usb_device *dev = gspca_dev->dev;
int ret, mode;
static u8 mode_tb[][3] = {
/* r00 r06 r07 */
{0x00, 0x10, 0x10}, /* 640x480 */
{0x01, 0x1a, 0x1a}, /* 352x288 */
{0x02, 0x1c, 0x1d}, /* 320x240 */
{0x04, 0x34, 0x34}, /* 176x144 */
{0x05, 0x40, 0x40} /* 160x120 */
};
if (sd->subtype == Nxultra)
write_vector(gspca_dev, spca505b_open_data_ccd);
else
write_vector(gspca_dev, spca505_open_data_ccd);
ret = reg_read(gspca_dev, 0x06, 0x16);
if (ret < 0) {
PDEBUG(D_ERR|D_CONF,
"register read failed err: %d",
ret);
return ret;
}
if (ret != 0x0101) {
PDEBUG(D_ERR|D_CONF,
"After vector read returns 0x%04x should be 0x0101",
ret);
}
ret = reg_write(gspca_dev->dev, 0x06, 0x16, 0x0a);
if (ret < 0)
return ret;
reg_write(gspca_dev->dev, 0x05, 0xc2, 0x12);
/* necessary because without it we can see stream
* only once after loading module */
/* stopping usb registers Tomasz change */
reg_write(dev, 0x02, 0x00, 0x00);
mode = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv;
reg_write(dev, SPCA50X_REG_COMPRESS, 0x00, mode_tb[mode][0]);
reg_write(dev, SPCA50X_REG_COMPRESS, 0x06, mode_tb[mode][1]);
reg_write(dev, SPCA50X_REG_COMPRESS, 0x07, mode_tb[mode][2]);
ret = reg_write(dev, SPCA50X_REG_USB,
SPCA50X_USB_CTRL,
SPCA50X_CUSB_ENABLE);
setbrightness(gspca_dev);
return ret;
}
static void sd_stopN(struct gspca_dev *gspca_dev)
{
/* Disable ISO packet machine */
reg_write(gspca_dev->dev, 0x02, 0x00, 0x00);
}
/* called on streamoff with alt 0 and on disconnect */
static void sd_stop0(struct gspca_dev *gspca_dev)
{
if (!gspca_dev->present)
return;
/* This maybe reset or power control */
reg_write(gspca_dev->dev, 0x03, 0x03, 0x20);
reg_write(gspca_dev->dev, 0x03, 0x01, 0x00);
reg_write(gspca_dev->dev, 0x03, 0x00, 0x01);
reg_write(gspca_dev->dev, 0x05, 0x10, 0x01);
reg_write(gspca_dev->dev, 0x05, 0x11, 0x0f);
}
static void sd_pkt_scan(struct gspca_dev *gspca_dev,
struct gspca_frame *frame, /* target */
u8 *data, /* isoc packet */
int len) /* iso packet length */
{
switch (data[0]) {
case 0: /* start of frame */
frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame,
data, 0);
data += SPCA50X_OFFSET_DATA;
len -= SPCA50X_OFFSET_DATA;
gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
data, len);
break;
case 0xff: /* drop */
break;
default:
data += 1;
len -= 1;
gspca_frame_add(gspca_dev, INTER_PACKET, frame,
data, len);
break;
}
}
static int sd_setbrightness(struct gspca_dev *gspca_dev, __s32 val)
{
struct sd *sd = (struct sd *) gspca_dev;
sd->brightness = val;
if (gspca_dev->streaming)
setbrightness(gspca_dev);
return 0;
}
static int sd_getbrightness(struct gspca_dev *gspca_dev, __s32 *val)
{
struct sd *sd = (struct sd *) gspca_dev;
*val = sd->brightness;
return 0;
}
/* sub-driver description */
static const struct sd_desc sd_desc = {
.name = MODULE_NAME,
.ctrls = sd_ctrls,
.nctrls = ARRAY_SIZE(sd_ctrls),
.config = sd_config,
.init = sd_init,
.start = sd_start,
.stopN = sd_stopN,
.stop0 = sd_stop0,
.pkt_scan = sd_pkt_scan,
};
/* -- module initialisation -- */
static const __devinitdata struct usb_device_id device_table[] = {
{USB_DEVICE(0x041e, 0x401d), .driver_info = Nxultra},
{USB_DEVICE(0x0733, 0x0430), .driver_info = IntelPCCameraPro},
/*fixme: may be UsbGrabberPV321 BRIDGE_SPCA506 SENSOR_SAA7113 */
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
/* -- device connect -- */
static int sd_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
THIS_MODULE);
}
static struct usb_driver sd_driver = {
.name = MODULE_NAME,
.id_table = device_table,
.probe = sd_probe,
.disconnect = gspca_disconnect,
#ifdef CONFIG_PM
.suspend = gspca_suspend,
.resume = gspca_resume,
#endif
};
/* -- module insert / remove -- */
static int __init sd_mod_init(void)
{
int ret;
ret = usb_register(&sd_driver);
if (ret < 0)
return ret;
PDEBUG(D_PROBE, "registered");
return 0;
}
static void __exit sd_mod_exit(void)
{
usb_deregister(&sd_driver);
PDEBUG(D_PROBE, "deregistered");
}
module_init(sd_mod_init);
module_exit(sd_mod_exit);
| gpl-2.0 |
nagataka/linux-2.6.32.65 | arch/arm/mach-pxa/palmz72.c | 496 | 13086 | /*
* Hardware definitions for Palm Zire72
*
* Authors:
* Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>
* Sergey Lapin <slapin@ossfans.org>
* Alex Osborne <bobofdoom@gmail.com>
* Jan Herman <2hp@seznam.cz>
*
* Rewrite for mainline:
* Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* (find more info at www.hackndev.com)
*
*/
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
#include <linux/wm97xx_batt.h>
#include <linux/power_supply.h>
#include <linux/usb/gpio_vbus.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/pxa27x.h>
#include <mach/audio.h>
#include <mach/palmz72.h>
#include <mach/mmc.h>
#include <mach/pxafb.h>
#include <mach/irda.h>
#include <mach/pxa27x_keypad.h>
#include <mach/udc.h>
#include <mach/palmasoc.h>
#include <mach/pm.h>
#include "generic.h"
#include "devices.h"
/******************************************************************************
* Pin configuration
******************************************************************************/
static unsigned long palmz72_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
GPIO14_GPIO, /* SD detect */
GPIO115_GPIO, /* SD RO */
GPIO98_GPIO, /* SD power */
/* AC97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
GPIO89_AC97_SYSCLK,
GPIO113_AC97_nRESET,
/* IrDA */
GPIO49_GPIO, /* ir disable */
GPIO46_FICP_RXD,
GPIO47_FICP_TXD,
/* PWM */
GPIO16_PWM0_OUT,
/* USB */
GPIO15_GPIO, /* usb detect */
GPIO95_GPIO, /* usb pullup */
/* Matrix keypad */
GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
GPIO103_KP_MKOUT_0,
GPIO104_KP_MKOUT_1,
GPIO105_KP_MKOUT_2,
/* LCD */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
GPIO77_LCD_BIAS,
GPIO20_GPIO, /* bl power */
GPIO21_GPIO, /* LCD border switch */
GPIO22_GPIO, /* LCD border color */
GPIO96_GPIO, /* lcd power */
/* Misc. */
GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */
GPIO88_GPIO, /* green led */
GPIO27_GPIO, /* WM9712 IRQ */
};
/******************************************************************************
* SD/MMC card controller
******************************************************************************/
/* SD_POWER is not actually power, but it is more like chip
* select, i.e. it is inverted */
static struct pxamci_platform_data palmz72_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.gpio_card_detect = GPIO_NR_PALMZ72_SD_DETECT_N,
.gpio_card_ro = GPIO_NR_PALMZ72_SD_RO,
.gpio_power = GPIO_NR_PALMZ72_SD_POWER_N,
.gpio_power_invert = 1,
};
/******************************************************************************
* GPIO keyboard
******************************************************************************/
static unsigned int palmz72_matrix_keys[] = {
KEY(0, 0, KEY_POWER),
KEY(0, 1, KEY_F1),
KEY(0, 2, KEY_ENTER),
KEY(1, 0, KEY_F2),
KEY(1, 1, KEY_F3),
KEY(1, 2, KEY_F4),
KEY(2, 0, KEY_UP),
KEY(2, 2, KEY_DOWN),
KEY(3, 0, KEY_RIGHT),
KEY(3, 2, KEY_LEFT),
};
static struct pxa27x_keypad_platform_data palmz72_keypad_platform_data = {
.matrix_key_rows = 4,
.matrix_key_cols = 3,
.matrix_key_map = palmz72_matrix_keys,
.matrix_key_map_size = ARRAY_SIZE(palmz72_matrix_keys),
.debounce_interval = 30,
};
/******************************************************************************
* Backlight
******************************************************************************/
static int palmz72_backlight_init(struct device *dev)
{
int ret;
ret = gpio_request(GPIO_NR_PALMZ72_BL_POWER, "BL POWER");
if (ret)
goto err;
ret = gpio_direction_output(GPIO_NR_PALMZ72_BL_POWER, 0);
if (ret)
goto err2;
ret = gpio_request(GPIO_NR_PALMZ72_LCD_POWER, "LCD POWER");
if (ret)
goto err2;
ret = gpio_direction_output(GPIO_NR_PALMZ72_LCD_POWER, 0);
if (ret)
goto err3;
return 0;
err3:
gpio_free(GPIO_NR_PALMZ72_LCD_POWER);
err2:
gpio_free(GPIO_NR_PALMZ72_BL_POWER);
err:
return ret;
}
static int palmz72_backlight_notify(int brightness)
{
gpio_set_value(GPIO_NR_PALMZ72_BL_POWER, brightness);
gpio_set_value(GPIO_NR_PALMZ72_LCD_POWER, brightness);
return brightness;
}
static void palmz72_backlight_exit(struct device *dev)
{
gpio_free(GPIO_NR_PALMZ72_BL_POWER);
gpio_free(GPIO_NR_PALMZ72_LCD_POWER);
}
static struct platform_pwm_backlight_data palmz72_backlight_data = {
.pwm_id = 0,
.max_brightness = PALMZ72_MAX_INTENSITY,
.dft_brightness = PALMZ72_MAX_INTENSITY,
.pwm_period_ns = PALMZ72_PERIOD_NS,
.init = palmz72_backlight_init,
.notify = palmz72_backlight_notify,
.exit = palmz72_backlight_exit,
};
static struct platform_device palmz72_backlight = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &palmz72_backlight_data,
},
};
/******************************************************************************
* IrDA
******************************************************************************/
static struct pxaficp_platform_data palmz72_ficp_platform_data = {
.gpio_pwdown = GPIO_NR_PALMZ72_IR_DISABLE,
.transceiver_cap = IR_SIRMODE | IR_OFF,
};
/******************************************************************************
* LEDs
******************************************************************************/
static struct gpio_led gpio_leds[] = {
{
.name = "palmz72:green:led",
.default_trigger = "none",
.gpio = GPIO_NR_PALMZ72_LED_GREEN,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device palmz72_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
}
};
/******************************************************************************
* UDC
******************************************************************************/
static struct gpio_vbus_mach_info palmz72_udc_info = {
.gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N,
.gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP,
};
static struct platform_device palmz72_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
.dev = {
.platform_data = &palmz72_udc_info,
},
};
/******************************************************************************
* Power supply
******************************************************************************/
static int power_supply_init(struct device *dev)
{
int ret;
ret = gpio_request(GPIO_NR_PALMZ72_POWER_DETECT, "CABLE_STATE_AC");
if (ret)
goto err1;
ret = gpio_direction_input(GPIO_NR_PALMZ72_POWER_DETECT);
if (ret)
goto err2;
ret = gpio_request(GPIO_NR_PALMZ72_USB_DETECT_N, "CABLE_STATE_USB");
if (ret)
goto err2;
ret = gpio_direction_input(GPIO_NR_PALMZ72_USB_DETECT_N);
if (ret)
goto err3;
return 0;
err3:
gpio_free(GPIO_NR_PALMZ72_USB_DETECT_N);
err2:
gpio_free(GPIO_NR_PALMZ72_POWER_DETECT);
err1:
return ret;
}
static int palmz72_is_ac_online(void)
{
return gpio_get_value(GPIO_NR_PALMZ72_POWER_DETECT);
}
static int palmz72_is_usb_online(void)
{
return !gpio_get_value(GPIO_NR_PALMZ72_USB_DETECT_N);
}
static void power_supply_exit(struct device *dev)
{
gpio_free(GPIO_NR_PALMZ72_USB_DETECT_N);
gpio_free(GPIO_NR_PALMZ72_POWER_DETECT);
}
static char *palmz72_supplicants[] = {
"main-battery",
};
static struct pda_power_pdata power_supply_info = {
.init = power_supply_init,
.is_ac_online = palmz72_is_ac_online,
.is_usb_online = palmz72_is_usb_online,
.exit = power_supply_exit,
.supplied_to = palmz72_supplicants,
.num_supplicants = ARRAY_SIZE(palmz72_supplicants),
};
static struct platform_device power_supply = {
.name = "pda-power",
.id = -1,
.dev = {
.platform_data = &power_supply_info,
},
};
/******************************************************************************
* WM97xx battery
******************************************************************************/
static struct wm97xx_batt_info wm97xx_batt_pdata = {
.batt_aux = WM97XX_AUX_ID3,
.temp_aux = WM97XX_AUX_ID2,
.charge_gpio = -1,
.max_voltage = PALMZ72_BAT_MAX_VOLTAGE,
.min_voltage = PALMZ72_BAT_MIN_VOLTAGE,
.batt_mult = 1000,
.batt_div = 414,
.temp_mult = 1,
.temp_div = 1,
.batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO,
.batt_name = "main-batt",
};
/******************************************************************************
* aSoC audio
******************************************************************************/
static struct platform_device palmz72_asoc = {
.name = "palm27x-asoc",
.id = -1,
};
/******************************************************************************
* Framebuffer
******************************************************************************/
static struct pxafb_mode_info palmz72_lcd_modes[] = {
{
.pixclock = 115384,
.xres = 320,
.yres = 320,
.bpp = 16,
.left_margin = 27,
.right_margin = 7,
.upper_margin = 7,
.lower_margin = 8,
.hsync_len = 6,
.vsync_len = 1,
},
};
static struct pxafb_mach_info palmz72_lcd_screen = {
.modes = palmz72_lcd_modes,
.num_modes = ARRAY_SIZE(palmz72_lcd_modes),
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
};
#ifdef CONFIG_PM
/* We have some black magic here
* PalmOS ROM on recover expects special struct physical address
* to be transferred via PSPR. Using this struct PalmOS restores
* its state after sleep. As for Linux, we need to setup it the
* same way. More than that, PalmOS ROM changes some values in memory.
* For now only one location is found, which needs special treatment.
* Thanks to Alex Osborne, Andrzej Zaborowski, and lots of other people
* for reading backtraces for me :)
*/
#define PALMZ72_SAVE_DWORD ((unsigned long *)0xc0000050)
static struct palmz72_resume_info palmz72_resume_info = {
.magic0 = 0xb4e6,
.magic1 = 1,
/* reset state, MMU off etc */
.arm_control = 0,
.aux_control = 0,
.ttb = 0,
.domain_access = 0,
.process_id = 0,
};
static unsigned long store_ptr;
/* sys_device for Palm Zire 72 PM */
static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg)
{
/* setup the resume_info struct for the original bootloader */
palmz72_resume_info.resume_addr = (u32) pxa_cpu_resume;
/* Storing memory touched by ROM */
store_ptr = *PALMZ72_SAVE_DWORD;
/* Setting PSPR to a proper value */
PSPR = virt_to_phys(&palmz72_resume_info);
return 0;
}
static int palmz72_pm_resume(struct sys_device *dev)
{
*PALMZ72_SAVE_DWORD = store_ptr;
return 0;
}
static struct sysdev_class palmz72_pm_sysclass = {
.name = "palmz72_pm",
.suspend = palmz72_pm_suspend,
.resume = palmz72_pm_resume,
};
static struct sys_device palmz72_pm_device = {
.cls = &palmz72_pm_sysclass,
};
static int __init palmz72_pm_init(void)
{
int ret = -ENODEV;
if (machine_is_palmz72()) {
ret = sysdev_class_register(&palmz72_pm_sysclass);
if (ret == 0)
ret = sysdev_register(&palmz72_pm_device);
}
return ret;
}
device_initcall(palmz72_pm_init);
#endif
/******************************************************************************
* Machine init
******************************************************************************/
static struct platform_device *devices[] __initdata = {
&palmz72_backlight,
&palmz72_leds,
&palmz72_asoc,
&power_supply,
&palmz72_gpio_vbus,
};
/* setup udc GPIOs initial state */
static void __init palmz72_udc_init(void)
{
if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) {
gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0);
gpio_free(GPIO_NR_PALMZ72_USB_PULLUP);
}
}
static void __init palmz72_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
set_pxa_fb_info(&palmz72_lcd_screen);
pxa_set_mci_info(&palmz72_mci_platform_data);
palmz72_udc_init();
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&palmz72_ficp_platform_data);
pxa_set_keypad_info(&palmz72_keypad_platform_data);
wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
MACHINE_START(PALMZ72, "Palm Zire72")
.phys_io = 0x40000000,
.io_pg_offst = io_p2v(0x40000000),
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = palmz72_init
MACHINE_END
| gpl-2.0 |
yangyang1989/linux-2.6.32.2-mini2440 | fs/ext4/xattr_trusted.c | 752 | 1502 | /*
* linux/fs/ext4/xattr_trusted.c
* Handler for trusted extended attributes.
*
* Copyright (C) 2003 by Andreas Gruenbacher, <a.gruenbacher@computer.org>
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/capability.h>
#include <linux/fs.h>
#include "ext4_jbd2.h"
#include "ext4.h"
#include "xattr.h"
static size_t
ext4_xattr_trusted_list(struct inode *inode, char *list, size_t list_size,
const char *name, size_t name_len)
{
const size_t prefix_len = XATTR_TRUSTED_PREFIX_LEN;
const size_t total_len = prefix_len + name_len + 1;
if (!capable(CAP_SYS_ADMIN))
return 0;
if (list && total_len <= list_size) {
memcpy(list, XATTR_TRUSTED_PREFIX, prefix_len);
memcpy(list+prefix_len, name, name_len);
list[prefix_len + name_len] = '\0';
}
return total_len;
}
static int
ext4_xattr_trusted_get(struct inode *inode, const char *name,
void *buffer, size_t size)
{
if (strcmp(name, "") == 0)
return -EINVAL;
return ext4_xattr_get(inode, EXT4_XATTR_INDEX_TRUSTED, name,
buffer, size);
}
static int
ext4_xattr_trusted_set(struct inode *inode, const char *name,
const void *value, size_t size, int flags)
{
if (strcmp(name, "") == 0)
return -EINVAL;
return ext4_xattr_set(inode, EXT4_XATTR_INDEX_TRUSTED, name,
value, size, flags);
}
struct xattr_handler ext4_xattr_trusted_handler = {
.prefix = XATTR_TRUSTED_PREFIX,
.list = ext4_xattr_trusted_list,
.get = ext4_xattr_trusted_get,
.set = ext4_xattr_trusted_set,
};
| gpl-2.0 |
DerTeufel/cm7 | drivers/rtc/rtc-ab3100.c | 752 | 7005 | /*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* RTC clock driver for the AB3100 Analog Baseband Chip
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/mfd/abx500.h>
/* Clock rate in Hz */
#define AB3100_RTC_CLOCK_RATE 32768
/*
* The AB3100 RTC registers. These are the same for
* AB3000 and AB3100.
* Control register:
* Bit 0: RTC Monitor cleared=0, active=1, if you set it
* to 1 it remains active until RTC power is lost.
* Bit 1: 32 kHz Oscillator, 0 = on, 1 = bypass
* Bit 2: Alarm on, 0 = off, 1 = on
* Bit 3: 32 kHz buffer disabling, 0 = enabled, 1 = disabled
*/
#define AB3100_RTC 0x53
/* default setting, buffer disabled, alarm on */
#define RTC_SETTING 0x30
/* Alarm when AL0-AL3 == TI0-TI3 */
#define AB3100_AL0 0x56
#define AB3100_AL1 0x57
#define AB3100_AL2 0x58
#define AB3100_AL3 0x59
/* This 48-bit register that counts up at 32768 Hz */
#define AB3100_TI0 0x5a
#define AB3100_TI1 0x5b
#define AB3100_TI2 0x5c
#define AB3100_TI3 0x5d
#define AB3100_TI4 0x5e
#define AB3100_TI5 0x5f
/*
* RTC clock functions and device struct declaration
*/
static int ab3100_rtc_set_mmss(struct device *dev, unsigned long secs)
{
u8 regs[] = {AB3100_TI0, AB3100_TI1, AB3100_TI2,
AB3100_TI3, AB3100_TI4, AB3100_TI5};
unsigned char buf[6];
u64 fat_time = (u64) secs * AB3100_RTC_CLOCK_RATE * 2;
int err = 0;
int i;
buf[0] = (fat_time) & 0xFF;
buf[1] = (fat_time >> 8) & 0xFF;
buf[2] = (fat_time >> 16) & 0xFF;
buf[3] = (fat_time >> 24) & 0xFF;
buf[4] = (fat_time >> 32) & 0xFF;
buf[5] = (fat_time >> 40) & 0xFF;
for (i = 0; i < 6; i++) {
err = abx500_set_register_interruptible(dev, 0,
regs[i], buf[i]);
if (err)
return err;
}
/* Set the flag to mark that the clock is now set */
return abx500_mask_and_set_register_interruptible(dev, 0,
AB3100_RTC,
0x01, 0x01);
}
static int ab3100_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
unsigned long time;
u8 rtcval;
int err;
err = abx500_get_register_interruptible(dev, 0,
AB3100_RTC, &rtcval);
if (err)
return err;
if (!(rtcval & 0x01)) {
dev_info(dev, "clock not set (lost power)");
return -EINVAL;
} else {
u64 fat_time;
u8 buf[6];
/* Read out time registers */
err = abx500_get_register_page_interruptible(dev, 0,
AB3100_TI0,
buf, 6);
if (err != 0)
return err;
fat_time = ((u64) buf[5] << 40) | ((u64) buf[4] << 32) |
((u64) buf[3] << 24) | ((u64) buf[2] << 16) |
((u64) buf[1] << 8) | (u64) buf[0];
time = (unsigned long) (fat_time /
(u64) (AB3100_RTC_CLOCK_RATE * 2));
}
rtc_time_to_tm(time, tm);
return rtc_valid_tm(tm);
}
static int ab3100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
unsigned long time;
u64 fat_time;
u8 buf[6];
u8 rtcval;
int err;
/* Figure out if alarm is enabled or not */
err = abx500_get_register_interruptible(dev, 0,
AB3100_RTC, &rtcval);
if (err)
return err;
if (rtcval & 0x04)
alarm->enabled = 1;
else
alarm->enabled = 0;
/* No idea how this could be represented */
alarm->pending = 0;
/* Read out alarm registers, only 4 bytes */
err = abx500_get_register_page_interruptible(dev, 0,
AB3100_AL0, buf, 4);
if (err)
return err;
fat_time = ((u64) buf[3] << 40) | ((u64) buf[2] << 32) |
((u64) buf[1] << 24) | ((u64) buf[0] << 16);
time = (unsigned long) (fat_time / (u64) (AB3100_RTC_CLOCK_RATE * 2));
rtc_time_to_tm(time, &alarm->time);
return rtc_valid_tm(&alarm->time);
}
static int ab3100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
u8 regs[] = {AB3100_AL0, AB3100_AL1, AB3100_AL2, AB3100_AL3};
unsigned char buf[4];
unsigned long secs;
u64 fat_time;
int err;
int i;
rtc_tm_to_time(&alarm->time, &secs);
fat_time = (u64) secs * AB3100_RTC_CLOCK_RATE * 2;
buf[0] = (fat_time >> 16) & 0xFF;
buf[1] = (fat_time >> 24) & 0xFF;
buf[2] = (fat_time >> 32) & 0xFF;
buf[3] = (fat_time >> 40) & 0xFF;
/* Set the alarm */
for (i = 0; i < 4; i++) {
err = abx500_set_register_interruptible(dev, 0,
regs[i], buf[i]);
if (err)
return err;
}
/* Then enable the alarm */
return abx500_mask_and_set_register_interruptible(dev, 0,
AB3100_RTC, (1 << 2),
alarm->enabled << 2);
}
static int ab3100_rtc_irq_enable(struct device *dev, unsigned int enabled)
{
/*
* It's not possible to enable/disable the alarm IRQ for this RTC.
* It does not actually trigger any IRQ: instead its only function is
* to power up the system, if it wasn't on. This will manifest as
* a "power up cause" in the AB3100 power driver (battery charging etc)
* and need to be handled there instead.
*/
if (enabled)
return abx500_mask_and_set_register_interruptible(dev, 0,
AB3100_RTC, (1 << 2),
1 << 2);
else
return abx500_mask_and_set_register_interruptible(dev, 0,
AB3100_RTC, (1 << 2),
0);
}
static const struct rtc_class_ops ab3100_rtc_ops = {
.read_time = ab3100_rtc_read_time,
.set_mmss = ab3100_rtc_set_mmss,
.read_alarm = ab3100_rtc_read_alarm,
.set_alarm = ab3100_rtc_set_alarm,
.alarm_irq_enable = ab3100_rtc_irq_enable,
};
static int __init ab3100_rtc_probe(struct platform_device *pdev)
{
int err;
u8 regval;
struct rtc_device *rtc;
/* The first RTC register needs special treatment */
err = abx500_get_register_interruptible(&pdev->dev, 0,
AB3100_RTC, ®val);
if (err) {
dev_err(&pdev->dev, "unable to read RTC register\n");
return -ENODEV;
}
if ((regval & 0xFE) != RTC_SETTING) {
dev_warn(&pdev->dev, "not default value in RTC reg 0x%x\n",
regval);
}
if ((regval & 1) == 0) {
/*
* Set bit to detect power loss.
* This bit remains until RTC power is lost.
*/
regval = 1 | RTC_SETTING;
err = abx500_set_register_interruptible(&pdev->dev, 0,
AB3100_RTC, regval);
/* Ignore any error on this write */
}
rtc = rtc_device_register("ab3100-rtc", &pdev->dev, &ab3100_rtc_ops,
THIS_MODULE);
if (IS_ERR(rtc)) {
err = PTR_ERR(rtc);
return err;
}
return 0;
}
static int __exit ab3100_rtc_remove(struct platform_device *pdev)
{
struct rtc_device *rtc = platform_get_drvdata(pdev);
rtc_device_unregister(rtc);
return 0;
}
static struct platform_driver ab3100_rtc_driver = {
.driver = {
.name = "ab3100-rtc",
.owner = THIS_MODULE,
},
.remove = __exit_p(ab3100_rtc_remove),
};
static int __init ab3100_rtc_init(void)
{
return platform_driver_probe(&ab3100_rtc_driver,
ab3100_rtc_probe);
}
static void __exit ab3100_rtc_exit(void)
{
platform_driver_unregister(&ab3100_rtc_driver);
}
module_init(ab3100_rtc_init);
module_exit(ab3100_rtc_exit);
MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
MODULE_DESCRIPTION("AB3100 RTC Driver");
MODULE_LICENSE("GPL");
| gpl-2.0 |
TheNikiz/android_kernel_samsung_hawaii | drivers/usb/serial/opticon.c | 1264 | 11149 | /*
* Opticon USB barcode to serial driver
*
* Copyright (C) 2011 - 2012 Johan Hovold <jhovold@gmail.com>
* Copyright (C) 2011 Martin Jansen <martin.jansen@opticon.com>
* Copyright (C) 2008 - 2009 Greg Kroah-Hartman <gregkh@suse.de>
* Copyright (C) 2008 - 2009 Novell Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version
* 2 as published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/slab.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/module.h>
#include <linux/usb.h>
#include <linux/usb/serial.h>
#include <linux/uaccess.h>
#define CONTROL_RTS 0x02
#define RESEND_CTS_STATE 0x03
/* max number of write urbs in flight */
#define URB_UPPER_LIMIT 8
/* This driver works for the Opticon 1D barcode reader
* an examples of 1D barcode types are EAN, UPC, Code39, IATA etc.. */
#define DRIVER_DESC "Opticon USB barcode to serial driver (1D)"
static const struct usb_device_id id_table[] = {
{ USB_DEVICE(0x065a, 0x0009) },
{ },
};
MODULE_DEVICE_TABLE(usb, id_table);
/* This structure holds all of the individual device information */
struct opticon_private {
spinlock_t lock; /* protects the following flags */
bool rts;
bool cts;
int outstanding_urbs;
};
static void opticon_process_data_packet(struct usb_serial_port *port,
const unsigned char *buf, size_t len)
{
tty_insert_flip_string(&port->port, buf, len);
tty_flip_buffer_push(&port->port);
}
static void opticon_process_status_packet(struct usb_serial_port *port,
const unsigned char *buf, size_t len)
{
struct opticon_private *priv = usb_get_serial_port_data(port);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
if (buf[0] == 0x00)
priv->cts = false;
else
priv->cts = true;
spin_unlock_irqrestore(&priv->lock, flags);
}
static void opticon_process_read_urb(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
const unsigned char *hdr = urb->transfer_buffer;
const unsigned char *data = hdr + 2;
size_t data_len = urb->actual_length - 2;
if (urb->actual_length <= 2) {
dev_dbg(&port->dev, "malformed packet received: %d bytes\n",
urb->actual_length);
return;
}
/*
* Data from the device comes with a 2 byte header:
*
* <0x00><0x00>data...
* This is real data to be sent to the tty layer
* <0x00><0x01>level
* This is a CTS level change, the third byte is the CTS
* value (0 for low, 1 for high).
*/
if ((hdr[0] == 0x00) && (hdr[1] == 0x00)) {
opticon_process_data_packet(port, data, data_len);
} else if ((hdr[0] == 0x00) && (hdr[1] == 0x01)) {
opticon_process_status_packet(port, data, data_len);
} else {
dev_dbg(&port->dev, "unknown packet received: %02x %02x\n",
hdr[0], hdr[1]);
}
}
static int send_control_msg(struct usb_serial_port *port, u8 requesttype,
u8 val)
{
struct usb_serial *serial = port->serial;
int retval;
u8 *buffer;
buffer = kzalloc(1, GFP_KERNEL);
if (!buffer)
return -ENOMEM;
buffer[0] = val;
/* Send the message to the vendor control endpoint
* of the connected device */
retval = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0),
requesttype,
USB_DIR_OUT|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
0, 0, buffer, 1, 0);
kfree(buffer);
if (retval < 0)
return retval;
return 0;
}
static int opticon_open(struct tty_struct *tty, struct usb_serial_port *port)
{
struct opticon_private *priv = usb_get_serial_port_data(port);
unsigned long flags;
int res;
spin_lock_irqsave(&priv->lock, flags);
priv->rts = false;
spin_unlock_irqrestore(&priv->lock, flags);
/* Clear RTS line */
send_control_msg(port, CONTROL_RTS, 0);
/* clear the halt status of the enpoint */
usb_clear_halt(port->serial->dev, port->read_urb->pipe);
res = usb_serial_generic_open(tty, port);
if (!res)
return res;
/* Request CTS line state, sometimes during opening the current
* CTS state can be missed. */
send_control_msg(port, RESEND_CTS_STATE, 1);
return res;
}
static void opticon_write_control_callback(struct urb *urb)
{
struct usb_serial_port *port = urb->context;
struct opticon_private *priv = usb_get_serial_port_data(port);
int status = urb->status;
unsigned long flags;
/* free up the transfer buffer, as usb_free_urb() does not do this */
kfree(urb->transfer_buffer);
/* setup packet may be set if we're using it for writing */
kfree(urb->setup_packet);
if (status)
dev_dbg(&port->dev,
"%s - non-zero urb status received: %d\n",
__func__, status);
spin_lock_irqsave(&priv->lock, flags);
--priv->outstanding_urbs;
spin_unlock_irqrestore(&priv->lock, flags);
usb_serial_port_softint(port);
}
static int opticon_write(struct tty_struct *tty, struct usb_serial_port *port,
const unsigned char *buf, int count)
{
struct opticon_private *priv = usb_get_serial_port_data(port);
struct usb_serial *serial = port->serial;
struct urb *urb;
unsigned char *buffer;
unsigned long flags;
int status;
struct usb_ctrlrequest *dr;
spin_lock_irqsave(&priv->lock, flags);
if (priv->outstanding_urbs > URB_UPPER_LIMIT) {
spin_unlock_irqrestore(&priv->lock, flags);
dev_dbg(&port->dev, "%s - write limit hit\n", __func__);
return 0;
}
priv->outstanding_urbs++;
spin_unlock_irqrestore(&priv->lock, flags);
buffer = kmalloc(count, GFP_ATOMIC);
if (!buffer) {
dev_err(&port->dev, "out of memory\n");
count = -ENOMEM;
goto error_no_buffer;
}
urb = usb_alloc_urb(0, GFP_ATOMIC);
if (!urb) {
dev_err(&port->dev, "no more free urbs\n");
count = -ENOMEM;
goto error_no_urb;
}
memcpy(buffer, buf, count);
usb_serial_debug_data(&port->dev, __func__, count, buffer);
/* The conncected devices do not have a bulk write endpoint,
* to transmit data to de barcode device the control endpoint is used */
dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
if (!dr) {
dev_err(&port->dev, "out of memory\n");
count = -ENOMEM;
goto error_no_dr;
}
dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_INTERFACE | USB_DIR_OUT;
dr->bRequest = 0x01;
dr->wValue = 0;
dr->wIndex = 0;
dr->wLength = cpu_to_le16(count);
usb_fill_control_urb(urb, serial->dev,
usb_sndctrlpipe(serial->dev, 0),
(unsigned char *)dr, buffer, count,
opticon_write_control_callback, port);
/* send it down the pipe */
status = usb_submit_urb(urb, GFP_ATOMIC);
if (status) {
dev_err(&port->dev,
"%s - usb_submit_urb(write endpoint) failed status = %d\n",
__func__, status);
count = status;
goto error;
}
/* we are done with this urb, so let the host driver
* really free it when it is finished with it */
usb_free_urb(urb);
return count;
error:
kfree(dr);
error_no_dr:
usb_free_urb(urb);
error_no_urb:
kfree(buffer);
error_no_buffer:
spin_lock_irqsave(&priv->lock, flags);
--priv->outstanding_urbs;
spin_unlock_irqrestore(&priv->lock, flags);
return count;
}
static int opticon_write_room(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct opticon_private *priv = usb_get_serial_port_data(port);
unsigned long flags;
/*
* We really can take almost anything the user throws at us
* but let's pick a nice big number to tell the tty
* layer that we have lots of free space, unless we don't.
*/
spin_lock_irqsave(&priv->lock, flags);
if (priv->outstanding_urbs > URB_UPPER_LIMIT * 2 / 3) {
spin_unlock_irqrestore(&priv->lock, flags);
dev_dbg(&port->dev, "%s - write limit hit\n", __func__);
return 0;
}
spin_unlock_irqrestore(&priv->lock, flags);
return 2048;
}
static int opticon_tiocmget(struct tty_struct *tty)
{
struct usb_serial_port *port = tty->driver_data;
struct opticon_private *priv = usb_get_serial_port_data(port);
unsigned long flags;
int result = 0;
spin_lock_irqsave(&priv->lock, flags);
if (priv->rts)
result |= TIOCM_RTS;
if (priv->cts)
result |= TIOCM_CTS;
spin_unlock_irqrestore(&priv->lock, flags);
dev_dbg(&port->dev, "%s - %x\n", __func__, result);
return result;
}
static int opticon_tiocmset(struct tty_struct *tty,
unsigned int set, unsigned int clear)
{
struct usb_serial_port *port = tty->driver_data;
struct opticon_private *priv = usb_get_serial_port_data(port);
unsigned long flags;
bool rts;
bool changed = false;
int ret;
/* We only support RTS so we only handle that */
spin_lock_irqsave(&priv->lock, flags);
rts = priv->rts;
if (set & TIOCM_RTS)
priv->rts = true;
if (clear & TIOCM_RTS)
priv->rts = false;
changed = rts ^ priv->rts;
spin_unlock_irqrestore(&priv->lock, flags);
if (!changed)
return 0;
ret = send_control_msg(port, CONTROL_RTS, !rts);
if (ret)
return usb_translate_errors(ret);
return 0;
}
static int get_serial_info(struct usb_serial_port *port,
struct serial_struct __user *serial)
{
struct serial_struct tmp;
if (!serial)
return -EFAULT;
memset(&tmp, 0x00, sizeof(tmp));
/* fake emulate a 16550 uart to make userspace code happy */
tmp.type = PORT_16550A;
tmp.line = port->serial->minor;
tmp.port = 0;
tmp.irq = 0;
tmp.flags = ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ;
tmp.xmit_fifo_size = 1024;
tmp.baud_base = 9600;
tmp.close_delay = 5*HZ;
tmp.closing_wait = 30*HZ;
if (copy_to_user(serial, &tmp, sizeof(*serial)))
return -EFAULT;
return 0;
}
static int opticon_ioctl(struct tty_struct *tty,
unsigned int cmd, unsigned long arg)
{
struct usb_serial_port *port = tty->driver_data;
dev_dbg(&port->dev, "%s - port %d, cmd = 0x%x\n", __func__, port->number, cmd);
switch (cmd) {
case TIOCGSERIAL:
return get_serial_info(port,
(struct serial_struct __user *)arg);
}
return -ENOIOCTLCMD;
}
static int opticon_startup(struct usb_serial *serial)
{
if (!serial->num_bulk_in) {
dev_err(&serial->dev->dev, "no bulk in endpoint\n");
return -ENODEV;
}
return 0;
}
static int opticon_port_probe(struct usb_serial_port *port)
{
struct opticon_private *priv;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->lock);
usb_set_serial_port_data(port, priv);
return 0;
}
static int opticon_port_remove(struct usb_serial_port *port)
{
struct opticon_private *priv = usb_get_serial_port_data(port);
kfree(priv);
return 0;
}
static struct usb_serial_driver opticon_device = {
.driver = {
.owner = THIS_MODULE,
.name = "opticon",
},
.id_table = id_table,
.num_ports = 1,
.bulk_in_size = 256,
.attach = opticon_startup,
.port_probe = opticon_port_probe,
.port_remove = opticon_port_remove,
.open = opticon_open,
.write = opticon_write,
.write_room = opticon_write_room,
.throttle = usb_serial_generic_throttle,
.unthrottle = usb_serial_generic_unthrottle,
.ioctl = opticon_ioctl,
.tiocmget = opticon_tiocmget,
.tiocmset = opticon_tiocmset,
.process_read_urb = opticon_process_read_urb,
};
static struct usb_serial_driver * const serial_drivers[] = {
&opticon_device, NULL
};
module_usb_serial_driver(serial_drivers, id_table);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
| gpl-2.0 |
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