idx int64 | func_before string | Vulnerability Classification string | vul int64 | func_after string | patch string | CWE ID string | lines_before string | lines_after string |
|---|---|---|---|---|---|---|---|---|
12,500 | ssh_stdio_confirm(int id, int success, void *arg)
{
if (!success)
fatal("stdio forwarding failed");
}
| null | 0 | ssh_stdio_confirm(int id, int success, void *arg)
{
if (!success)
fatal("stdio forwarding failed");
}
| @@ -1,4 +1,4 @@
-/* $OpenBSD: ssh.c,v 1.432 2015/12/11 03:20:09 djm Exp $ */
+/* $OpenBSD: ssh.c,v 1.433 2016/01/13 23:04:47 djm Exp $ */
/*
* Author: Tatu Ylonen <ylo@cs.hut.fi>
* Copyright (c) 1995 Tatu Ylonen <ylo@cs.hut.fi>, Espoo, Finland
@@ -1626,6 +1626,7 @@ ssh_session(void)
struct winsize ws;
char *cp;
const char *display;
+ char *proto = NULL, *data = NULL;
/* Enable compression if requested. */
if (options.compression) {
@@ -1696,13 +1697,9 @@ ssh_session(void)
display = getenv("DISPLAY");
if (display == NULL && options.forward_x11)
debug("X11 forwarding requested but DISPLAY not set");
- if (options.forward_x11 && display != NULL) {
- char *proto, *data;
- /* Get reasonable local authentication information. */
- client_x11_get_proto(display, options.xauth_location,
- options.forward_x11_trusted,
- options.forward_x11_timeout,
- &proto, &data);
+ if (options.forward_x11 && client_x11_get_proto(display,
+ options.xauth_location, options.forward_x11_trusted,
+ options.forward_x11_timeout, &proto, &data) == 0) {
/* Request forwarding with authentication spoofing. */
debug("Requesting X11 forwarding with authentication "
"spoofing.");
@@ -1792,6 +1789,7 @@ ssh_session2_setup(int id, int success, void *arg)
extern char **environ;
const char *display;
int interactive = tty_flag;
+ char *proto = NULL, *data = NULL;
if (!success)
return; /* No need for error message, channels code sens one */
@@ -1799,12 +1797,9 @@ ssh_session2_setup(int id, int success, void *arg)
display = getenv("DISPLAY");
if (display == NULL && options.forward_x11)
debug("X11 forwarding requested but DISPLAY not set");
- if (options.forward_x11 && display != NULL) {
- char *proto, *data;
- /* Get reasonable local authentication information. */
- client_x11_get_proto(display, options.xauth_location,
- options.forward_x11_trusted,
- options.forward_x11_timeout, &proto, &data);
+ if (options.forward_x11 && client_x11_get_proto(display,
+ options.xauth_location, options.forward_x11_trusted,
+ options.forward_x11_timeout, &proto, &data) == 0) {
/* Request forwarding with authentication spoofing. */
debug("Requesting X11 forwarding with authentication "
"spoofing."); | CWE-254 | null | null |
12,501 | usage(void)
{
fprintf(stderr,
"usage: ssh [-1246AaCfGgKkMNnqsTtVvXxYy] [-b bind_address] [-c cipher_spec]\n"
" [-D [bind_address:]port] [-E log_file] [-e escape_char]\n"
" [-F configfile] [-I pkcs11] [-i identity_file] [-L address]\n"
" [-l login_name] [-m mac_spec] [-O ctl_cmd] [-o option] [-p port]\n"
" [-Q query_option] [-R address] [-S ctl_path] [-W host:port]\n"
" [-w local_tun[:remote_tun]] [user@]hostname [command]\n"
);
exit(255);
}
| null | 0 | usage(void)
{
fprintf(stderr,
"usage: ssh [-1246AaCfGgKkMNnqsTtVvXxYy] [-b bind_address] [-c cipher_spec]\n"
" [-D [bind_address:]port] [-E log_file] [-e escape_char]\n"
" [-F configfile] [-I pkcs11] [-i identity_file] [-L address]\n"
" [-l login_name] [-m mac_spec] [-O ctl_cmd] [-o option] [-p port]\n"
" [-Q query_option] [-R address] [-S ctl_path] [-W host:port]\n"
" [-w local_tun[:remote_tun]] [user@]hostname [command]\n"
);
exit(255);
}
| @@ -1,4 +1,4 @@
-/* $OpenBSD: ssh.c,v 1.432 2015/12/11 03:20:09 djm Exp $ */
+/* $OpenBSD: ssh.c,v 1.433 2016/01/13 23:04:47 djm Exp $ */
/*
* Author: Tatu Ylonen <ylo@cs.hut.fi>
* Copyright (c) 1995 Tatu Ylonen <ylo@cs.hut.fi>, Espoo, Finland
@@ -1626,6 +1626,7 @@ ssh_session(void)
struct winsize ws;
char *cp;
const char *display;
+ char *proto = NULL, *data = NULL;
/* Enable compression if requested. */
if (options.compression) {
@@ -1696,13 +1697,9 @@ ssh_session(void)
display = getenv("DISPLAY");
if (display == NULL && options.forward_x11)
debug("X11 forwarding requested but DISPLAY not set");
- if (options.forward_x11 && display != NULL) {
- char *proto, *data;
- /* Get reasonable local authentication information. */
- client_x11_get_proto(display, options.xauth_location,
- options.forward_x11_trusted,
- options.forward_x11_timeout,
- &proto, &data);
+ if (options.forward_x11 && client_x11_get_proto(display,
+ options.xauth_location, options.forward_x11_trusted,
+ options.forward_x11_timeout, &proto, &data) == 0) {
/* Request forwarding with authentication spoofing. */
debug("Requesting X11 forwarding with authentication "
"spoofing.");
@@ -1792,6 +1789,7 @@ ssh_session2_setup(int id, int success, void *arg)
extern char **environ;
const char *display;
int interactive = tty_flag;
+ char *proto = NULL, *data = NULL;
if (!success)
return; /* No need for error message, channels code sens one */
@@ -1799,12 +1797,9 @@ ssh_session2_setup(int id, int success, void *arg)
display = getenv("DISPLAY");
if (display == NULL && options.forward_x11)
debug("X11 forwarding requested but DISPLAY not set");
- if (options.forward_x11 && display != NULL) {
- char *proto, *data;
- /* Get reasonable local authentication information. */
- client_x11_get_proto(display, options.xauth_location,
- options.forward_x11_trusted,
- options.forward_x11_timeout, &proto, &data);
+ if (options.forward_x11 && client_x11_get_proto(display,
+ options.xauth_location, options.forward_x11_trusted,
+ options.forward_x11_timeout, &proto, &data) == 0) {
/* Request forwarding with authentication spoofing. */
debug("Requesting X11 forwarding with authentication "
"spoofing."); | CWE-254 | null | null |
12,502 | static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
{
uint32_t events;
VMW_CBPRN("Clearing events: 0x%x", val);
events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
}
| DoS Exec Code | 0 | static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
{
uint32_t events;
VMW_CBPRN("Clearing events: 0x%x", val);
events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,503 | static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
{
struct Vmxnet3_GOSInfo gos;
VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
&gos, sizeof(gos));
s->rx_packets_compound =
(gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
}
| DoS Exec Code | 0 | static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
{
struct Vmxnet3_GOSInfo gos;
VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
&gos, sizeof(gos));
s->rx_packets_compound =
(gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,504 | static void vmxnet3_class_init(ObjectClass *class, void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
c->init = vmxnet3_pci_init;
c->exit = vmxnet3_pci_uninit;
c->vendor_id = PCI_VENDOR_ID_VMWARE;
c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
c->config_write = vmxnet3_write_config,
dc->desc = "VMWare Paravirtualized Ethernet v3";
dc->reset = vmxnet3_qdev_reset;
dc->vmsd = &vmstate_vmxnet3;
dc->props = vmxnet3_properties;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
| DoS Exec Code | 0 | static void vmxnet3_class_init(ObjectClass *class, void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
c->init = vmxnet3_pci_init;
c->exit = vmxnet3_pci_uninit;
c->vendor_id = PCI_VENDOR_ID_VMWARE;
c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
c->config_write = vmxnet3_write_config,
dc->desc = "VMWare Paravirtualized Ethernet v3";
dc->reset = vmxnet3_qdev_reset;
dc->vmsd = &vmstate_vmxnet3;
dc->props = vmxnet3_properties;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,505 | static void vmxnet3_cleanup(NetClientState *nc)
{
VMXNET3State *s = qemu_get_nic_opaque(nc);
s->nic = NULL;
}
| DoS Exec Code | 0 | static void vmxnet3_cleanup(NetClientState *nc)
{
VMXNET3State *s = qemu_get_nic_opaque(nc);
s->nic = NULL;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,506 | vmxnet3_cleanup_msi(VMXNET3State *s)
{
PCIDevice *d = PCI_DEVICE(s);
if (s->msi_used) {
msi_uninit(d);
}
}
| DoS Exec Code | 0 | vmxnet3_cleanup_msi(VMXNET3State *s)
{
PCIDevice *d = PCI_DEVICE(s);
if (s->msi_used) {
msi_uninit(d);
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,507 | static void vmxnet3_fill_stats(VMXNET3State *s)
{
int i;
for (i = 0; i < s->txq_num; i++) {
cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
&s->txq_descr[i].txq_stats,
sizeof(s->txq_descr[i].txq_stats));
}
for (i = 0; i < s->rxq_num; i++) {
cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
&s->rxq_descr[i].rxq_stats,
sizeof(s->rxq_descr[i].rxq_stats));
}
}
| DoS Exec Code | 0 | static void vmxnet3_fill_stats(VMXNET3State *s)
{
int i;
for (i = 0; i < s->txq_num; i++) {
cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
&s->txq_descr[i].txq_stats,
sizeof(s->txq_descr[i].txq_stats));
}
for (i = 0; i < s->rxq_num; i++) {
cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
&s->rxq_descr[i].rxq_stats,
sizeof(s->rxq_descr[i].rxq_stats));
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,508 | static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
{
uint64_t ret;
switch (s->last_command) {
case VMXNET3_CMD_ACTIVATE_DEV:
ret = (s->device_active) ? 0 : -1;
VMW_CFPRN("Device active: %" PRIx64, ret);
break;
case VMXNET3_CMD_RESET_DEV:
case VMXNET3_CMD_QUIESCE_DEV:
case VMXNET3_CMD_GET_QUEUE_STATUS:
ret = 0;
break;
case VMXNET3_CMD_GET_LINK:
ret = s->link_status_and_speed;
VMW_CFPRN("Link and speed: %" PRIx64, ret);
break;
case VMXNET3_CMD_GET_PERM_MAC_LO:
ret = vmxnet3_get_mac_low(&s->perm_mac);
break;
case VMXNET3_CMD_GET_PERM_MAC_HI:
ret = vmxnet3_get_mac_high(&s->perm_mac);
break;
case VMXNET3_CMD_GET_CONF_INTR:
ret = vmxnet3_get_interrupt_config(s);
break;
default:
VMW_WRPRN("Received request for unknown command: %x", s->last_command);
ret = -1;
break;
}
return ret;
}
| DoS Exec Code | 0 | static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
{
uint64_t ret;
switch (s->last_command) {
case VMXNET3_CMD_ACTIVATE_DEV:
ret = (s->device_active) ? 0 : -1;
VMW_CFPRN("Device active: %" PRIx64, ret);
break;
case VMXNET3_CMD_RESET_DEV:
case VMXNET3_CMD_QUIESCE_DEV:
case VMXNET3_CMD_GET_QUEUE_STATUS:
ret = 0;
break;
case VMXNET3_CMD_GET_LINK:
ret = s->link_status_and_speed;
VMW_CFPRN("Link and speed: %" PRIx64, ret);
break;
case VMXNET3_CMD_GET_PERM_MAC_LO:
ret = vmxnet3_get_mac_low(&s->perm_mac);
break;
case VMXNET3_CMD_GET_PERM_MAC_HI:
ret = vmxnet3_get_mac_high(&s->perm_mac);
break;
case VMXNET3_CMD_GET_CONF_INTR:
ret = vmxnet3_get_interrupt_config(s);
break;
default:
VMW_WRPRN("Received request for unknown command: %x", s->last_command);
ret = -1;
break;
}
return ret;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,509 | static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
{
s->last_command = cmd;
switch (cmd) {
case VMXNET3_CMD_GET_PERM_MAC_HI:
VMW_CBPRN("Set: Get upper part of permanent MAC");
break;
case VMXNET3_CMD_GET_PERM_MAC_LO:
VMW_CBPRN("Set: Get lower part of permanent MAC");
break;
case VMXNET3_CMD_GET_STATS:
VMW_CBPRN("Set: Get device statistics");
vmxnet3_fill_stats(s);
break;
case VMXNET3_CMD_ACTIVATE_DEV:
VMW_CBPRN("Set: Activating vmxnet3 device");
vmxnet3_activate_device(s);
break;
case VMXNET3_CMD_UPDATE_RX_MODE:
VMW_CBPRN("Set: Update rx mode");
vmxnet3_update_rx_mode(s);
break;
case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
VMW_CBPRN("Set: Update VLAN filters");
vmxnet3_update_vlan_filters(s);
break;
case VMXNET3_CMD_UPDATE_MAC_FILTERS:
VMW_CBPRN("Set: Update MAC filters");
vmxnet3_update_mcast_filters(s);
break;
case VMXNET3_CMD_UPDATE_FEATURE:
VMW_CBPRN("Set: Update features");
vmxnet3_update_features(s);
break;
case VMXNET3_CMD_UPDATE_PMCFG:
VMW_CBPRN("Set: Update power management config");
vmxnet3_update_pm_state(s);
break;
case VMXNET3_CMD_GET_LINK:
VMW_CBPRN("Set: Get link");
break;
case VMXNET3_CMD_RESET_DEV:
VMW_CBPRN("Set: Reset device");
vmxnet3_reset(s);
break;
case VMXNET3_CMD_QUIESCE_DEV:
VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
vmxnet3_deactivate_device(s);
break;
case VMXNET3_CMD_GET_CONF_INTR:
VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
break;
default:
VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
break;
}
}
| DoS Exec Code | 0 | static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
{
s->last_command = cmd;
switch (cmd) {
case VMXNET3_CMD_GET_PERM_MAC_HI:
VMW_CBPRN("Set: Get upper part of permanent MAC");
break;
case VMXNET3_CMD_GET_PERM_MAC_LO:
VMW_CBPRN("Set: Get lower part of permanent MAC");
break;
case VMXNET3_CMD_GET_STATS:
VMW_CBPRN("Set: Get device statistics");
vmxnet3_fill_stats(s);
break;
case VMXNET3_CMD_ACTIVATE_DEV:
VMW_CBPRN("Set: Activating vmxnet3 device");
vmxnet3_activate_device(s);
break;
case VMXNET3_CMD_UPDATE_RX_MODE:
VMW_CBPRN("Set: Update rx mode");
vmxnet3_update_rx_mode(s);
break;
case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
VMW_CBPRN("Set: Update VLAN filters");
vmxnet3_update_vlan_filters(s);
break;
case VMXNET3_CMD_UPDATE_MAC_FILTERS:
VMW_CBPRN("Set: Update MAC filters");
vmxnet3_update_mcast_filters(s);
break;
case VMXNET3_CMD_UPDATE_FEATURE:
VMW_CBPRN("Set: Update features");
vmxnet3_update_features(s);
break;
case VMXNET3_CMD_UPDATE_PMCFG:
VMW_CBPRN("Set: Update power management config");
vmxnet3_update_pm_state(s);
break;
case VMXNET3_CMD_GET_LINK:
VMW_CBPRN("Set: Get link");
break;
case VMXNET3_CMD_RESET_DEV:
VMW_CBPRN("Set: Reset device");
vmxnet3_reset(s);
break;
case VMXNET3_CMD_QUIESCE_DEV:
VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
vmxnet3_deactivate_device(s);
break;
case VMXNET3_CMD_GET_CONF_INTR:
VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
break;
default:
VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
break;
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,510 | vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
{
if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
g_assert_not_reached();
}
VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
return 0;
}
| DoS Exec Code | 0 | vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
{
if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
g_assert_not_reached();
}
VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
return 0;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,511 | vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
{
VMXNET3State *s = opaque;
uint64_t ret = 0;
switch (addr) {
/* Vmxnet3 Revision Report Selection */
case VMXNET3_REG_VRRS:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
ret = VMXNET3_DEVICE_REVISION;
break;
/* UPT Version Report Selection */
case VMXNET3_REG_UVRS:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
ret = VMXNET3_DEVICE_VERSION;
break;
/* Command */
case VMXNET3_REG_CMD:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
ret = vmxnet3_get_command_status(s);
break;
/* MAC Address Low */
case VMXNET3_REG_MACL:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
ret = vmxnet3_get_mac_low(&s->conf.macaddr);
break;
/* MAC Address High */
case VMXNET3_REG_MACH:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
ret = vmxnet3_get_mac_high(&s->conf.macaddr);
break;
/*
* Interrupt Cause Register
* Used for legacy interrupts only so interrupt index always 0
*/
case VMXNET3_REG_ICR:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
if (vmxnet3_interrupt_asserted(s, 0)) {
vmxnet3_clear_interrupt(s, 0);
ret = true;
} else {
ret = false;
}
break;
default:
VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
break;
}
return ret;
}
| DoS Exec Code | 0 | vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
{
VMXNET3State *s = opaque;
uint64_t ret = 0;
switch (addr) {
/* Vmxnet3 Revision Report Selection */
case VMXNET3_REG_VRRS:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
ret = VMXNET3_DEVICE_REVISION;
break;
/* UPT Version Report Selection */
case VMXNET3_REG_UVRS:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
ret = VMXNET3_DEVICE_VERSION;
break;
/* Command */
case VMXNET3_REG_CMD:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
ret = vmxnet3_get_command_status(s);
break;
/* MAC Address Low */
case VMXNET3_REG_MACL:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
ret = vmxnet3_get_mac_low(&s->conf.macaddr);
break;
/* MAC Address High */
case VMXNET3_REG_MACH:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
ret = vmxnet3_get_mac_high(&s->conf.macaddr);
break;
/*
* Interrupt Cause Register
* Used for legacy interrupts only so interrupt index always 0
*/
case VMXNET3_REG_ICR:
VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
if (vmxnet3_interrupt_asserted(s, 0)) {
vmxnet3_clear_interrupt(s, 0);
ret = true;
} else {
ret = false;
}
break;
default:
VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
break;
}
return ret;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,512 | vmxnet3_io_bar1_write(void *opaque,
hwaddr addr,
uint64_t val,
unsigned size)
{
VMXNET3State *s = opaque;
switch (addr) {
/* Vmxnet3 Revision Report Selection */
case VMXNET3_REG_VRRS:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
val, size);
break;
/* UPT Version Report Selection */
case VMXNET3_REG_UVRS:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
val, size);
break;
/* Driver Shared Address Low */
case VMXNET3_REG_DSAL:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
val, size);
/*
* Guest driver will first write the low part of the shared
* memory address. We save it to temp variable and set the
* shared address only after we get the high part
*/
if (0 == val) {
s->device_active = false;
}
s->temp_shared_guest_driver_memory = val;
s->drv_shmem = 0;
break;
/* Driver Shared Address High */
case VMXNET3_REG_DSAH:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
val, size);
/*
* Set the shared memory between guest driver and device.
* We already should have low address part.
*/
s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
break;
/* Command */
case VMXNET3_REG_CMD:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
val, size);
vmxnet3_handle_command(s, val);
break;
/* MAC Address Low */
case VMXNET3_REG_MACL:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
val, size);
s->temp_mac = val;
break;
/* MAC Address High */
case VMXNET3_REG_MACH:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
val, size);
vmxnet3_set_variable_mac(s, val, s->temp_mac);
break;
/* Interrupt Cause Register */
case VMXNET3_REG_ICR:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
val, size);
g_assert_not_reached();
break;
/* Event Cause Register */
case VMXNET3_REG_ECR:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
val, size);
vmxnet3_ack_events(s, val);
break;
default:
VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
addr, val, size);
break;
}
}
| DoS Exec Code | 0 | vmxnet3_io_bar1_write(void *opaque,
hwaddr addr,
uint64_t val,
unsigned size)
{
VMXNET3State *s = opaque;
switch (addr) {
/* Vmxnet3 Revision Report Selection */
case VMXNET3_REG_VRRS:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
val, size);
break;
/* UPT Version Report Selection */
case VMXNET3_REG_UVRS:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
val, size);
break;
/* Driver Shared Address Low */
case VMXNET3_REG_DSAL:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
val, size);
/*
* Guest driver will first write the low part of the shared
* memory address. We save it to temp variable and set the
* shared address only after we get the high part
*/
if (0 == val) {
s->device_active = false;
}
s->temp_shared_guest_driver_memory = val;
s->drv_shmem = 0;
break;
/* Driver Shared Address High */
case VMXNET3_REG_DSAH:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
val, size);
/*
* Set the shared memory between guest driver and device.
* We already should have low address part.
*/
s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
break;
/* Command */
case VMXNET3_REG_CMD:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
val, size);
vmxnet3_handle_command(s, val);
break;
/* MAC Address Low */
case VMXNET3_REG_MACL:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
val, size);
s->temp_mac = val;
break;
/* MAC Address High */
case VMXNET3_REG_MACH:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
val, size);
vmxnet3_set_variable_mac(s, val, s->temp_mac);
break;
/* Interrupt Cause Register */
case VMXNET3_REG_ICR:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
val, size);
g_assert_not_reached();
break;
/* Event Cause Register */
case VMXNET3_REG_ECR:
VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
val, size);
vmxnet3_ack_events(s, val);
break;
default:
VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
addr, val, size);
break;
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,513 | static void vmxnet3_net_uninit(VMXNET3State *s)
{
g_free(s->mcast_list);
vmxnet_tx_pkt_reset(s->tx_pkt);
vmxnet_tx_pkt_uninit(s->tx_pkt);
vmxnet_rx_pkt_uninit(s->rx_pkt);
qemu_del_nic(s->nic);
}
| DoS Exec Code | 0 | static void vmxnet3_net_uninit(VMXNET3State *s)
{
g_free(s->mcast_list);
vmxnet_tx_pkt_reset(s->tx_pkt);
vmxnet_tx_pkt_uninit(s->tx_pkt);
vmxnet_rx_pkt_uninit(s->rx_pkt);
qemu_del_nic(s->nic);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,514 | static int vmxnet3_pci_init(PCIDevice *pci_dev)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
VMW_CBPRN("Starting init...");
memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
"vmxnet3-b0", VMXNET3_PT_REG_SIZE);
pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
"vmxnet3-b1", VMXNET3_VD_REG_SIZE);
pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
VMXNET3_MSIX_BAR_SIZE);
pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
vmxnet3_reset_interrupt_states(s);
/* Interrupt pin A */
pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
if (!vmxnet3_init_msix(s)) {
VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
}
if (!vmxnet3_init_msi(s)) {
VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
}
vmxnet3_net_init(s);
register_savevm(dev, "vmxnet3-msix", -1, 1,
vmxnet3_msix_save, vmxnet3_msix_load, s);
add_boot_device_path(s->conf.bootindex, dev, "/ethernet-phy@0");
return 0;
}
| DoS Exec Code | 0 | static int vmxnet3_pci_init(PCIDevice *pci_dev)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
VMW_CBPRN("Starting init...");
memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
"vmxnet3-b0", VMXNET3_PT_REG_SIZE);
pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
"vmxnet3-b1", VMXNET3_VD_REG_SIZE);
pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
VMXNET3_MSIX_BAR_SIZE);
pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
vmxnet3_reset_interrupt_states(s);
/* Interrupt pin A */
pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
if (!vmxnet3_init_msix(s)) {
VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
}
if (!vmxnet3_init_msi(s)) {
VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
}
vmxnet3_net_init(s);
register_savevm(dev, "vmxnet3-msix", -1, 1,
vmxnet3_msix_save, vmxnet3_msix_load, s);
add_boot_device_path(s->conf.bootindex, dev, "/ethernet-phy@0");
return 0;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,515 | static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
VMW_CBPRN("Starting uninit...");
unregister_savevm(dev, "vmxnet3-msix", s);
vmxnet3_net_uninit(s);
vmxnet3_cleanup_msix(s);
vmxnet3_cleanup_msi(s);
memory_region_destroy(&s->bar0);
memory_region_destroy(&s->bar1);
memory_region_destroy(&s->msix_bar);
}
| DoS Exec Code | 0 | static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
VMW_CBPRN("Starting uninit...");
unregister_savevm(dev, "vmxnet3-msix", s);
vmxnet3_net_uninit(s);
vmxnet3_cleanup_msix(s);
vmxnet3_cleanup_msi(s);
memory_region_destroy(&s->bar0);
memory_region_destroy(&s->bar1);
memory_region_destroy(&s->msix_bar);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,516 | static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
{
NetClientState *nc = qemu_get_queue(s->nic);
if (qemu_has_vnet_hdr(nc->peer)) {
return true;
}
VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
return false;
}
| DoS Exec Code | 0 | static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
{
NetClientState *nc = qemu_get_queue(s->nic);
if (qemu_has_vnet_hdr(nc->peer)) {
return true;
}
VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
return false;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,517 | vmxnet3_physical_memory_writev(const struct iovec *iov,
size_t start_iov_off,
hwaddr target_addr,
size_t bytes_to_copy)
{
size_t curr_off = 0;
size_t copied = 0;
while (bytes_to_copy) {
if (start_iov_off < (curr_off + iov->iov_len)) {
size_t chunk_len =
MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
cpu_physical_memory_write(target_addr + copied,
iov->iov_base + start_iov_off - curr_off,
chunk_len);
copied += chunk_len;
start_iov_off += chunk_len;
curr_off = start_iov_off;
bytes_to_copy -= chunk_len;
} else {
curr_off += iov->iov_len;
}
iov++;
}
}
| DoS Exec Code | 0 | vmxnet3_physical_memory_writev(const struct iovec *iov,
size_t start_iov_off,
hwaddr target_addr,
size_t bytes_to_copy)
{
size_t curr_off = 0;
size_t copied = 0;
while (bytes_to_copy) {
if (start_iov_off < (curr_off + iov->iov_len)) {
size_t chunk_len =
MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
cpu_physical_memory_write(target_addr + copied,
iov->iov_base + start_iov_off - curr_off,
chunk_len);
copied += chunk_len;
start_iov_off += chunk_len;
curr_off = start_iov_off;
bytes_to_copy -= chunk_len;
} else {
curr_off += iov->iov_len;
}
iov++;
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,518 | vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
{
uint8_t ring_gen;
struct Vmxnet3_RxCompDesc rxcd;
hwaddr daddr =
vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
if (rxcd.gen != ring_gen) {
*descr_gen = ring_gen;
vmxnet3_inc_rx_completion_counter(s, qidx);
return daddr;
}
return 0;
}
| DoS Exec Code | 0 | vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
{
uint8_t ring_gen;
struct Vmxnet3_RxCompDesc rxcd;
hwaddr daddr =
vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
if (rxcd.gen != ring_gen) {
*descr_gen = ring_gen;
vmxnet3_inc_rx_completion_counter(s, qidx);
return daddr;
}
return 0;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,519 | static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
{
struct Vmxnet3_TxDesc txd;
uint32_t txd_idx;
uint32_t data_len;
hwaddr data_pa;
for (;;) {
if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
break;
}
vmxnet3_dump_tx_descr(&txd);
if (!s->skip_current_tx_pkt) {
data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
data_pa = le64_to_cpu(txd.addr);
if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
data_pa,
data_len)) {
s->skip_current_tx_pkt = true;
}
}
if (s->tx_sop) {
vmxnet3_tx_retrieve_metadata(s, &txd);
s->tx_sop = false;
}
if (txd.eop) {
if (!s->skip_current_tx_pkt) {
vmxnet_tx_pkt_parse(s->tx_pkt);
if (s->needs_vlan) {
vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
}
vmxnet3_send_packet(s, qidx);
} else {
vmxnet3_on_tx_done_update_stats(s, qidx,
VMXNET3_PKT_STATUS_ERROR);
}
vmxnet3_complete_packet(s, qidx, txd_idx);
s->tx_sop = true;
s->skip_current_tx_pkt = false;
vmxnet_tx_pkt_reset(s->tx_pkt);
}
}
}
| DoS Exec Code | 0 | static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
{
struct Vmxnet3_TxDesc txd;
uint32_t txd_idx;
uint32_t data_len;
hwaddr data_pa;
for (;;) {
if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
break;
}
vmxnet3_dump_tx_descr(&txd);
if (!s->skip_current_tx_pkt) {
data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
data_pa = le64_to_cpu(txd.addr);
if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
data_pa,
data_len)) {
s->skip_current_tx_pkt = true;
}
}
if (s->tx_sop) {
vmxnet3_tx_retrieve_metadata(s, &txd);
s->tx_sop = false;
}
if (txd.eop) {
if (!s->skip_current_tx_pkt) {
vmxnet_tx_pkt_parse(s->tx_pkt);
if (s->needs_vlan) {
vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
}
vmxnet3_send_packet(s, qidx);
} else {
vmxnet3_on_tx_done_update_stats(s, qidx,
VMXNET3_PKT_STATUS_ERROR);
}
vmxnet3_complete_packet(s, qidx, txd_idx);
s->tx_sop = true;
s->skip_current_tx_pkt = false;
vmxnet_tx_pkt_reset(s->tx_pkt);
}
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,520 | vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
{
Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
*didx = vmxnet3_ring_curr_cell_idx(ring);
vmxnet3_ring_read_curr_cell(ring, dbuf);
}
| DoS Exec Code | 0 | vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
{
Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
*didx = vmxnet3_ring_curr_cell_idx(ring);
vmxnet3_ring_read_curr_cell(ring, dbuf);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,521 | vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
VMXNET3State *s = qemu_get_nic_opaque(nc);
size_t bytes_indicated;
if (!vmxnet3_can_receive(nc)) {
VMW_PKPRN("Cannot receive now");
return -1;
}
if (s->peer_has_vhdr) {
vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
buf += sizeof(struct virtio_net_hdr);
size -= sizeof(struct virtio_net_hdr);
}
vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
if (bytes_indicated < size) {
VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size);
}
} else {
VMW_PKPRN("Packet dropped by RX filter");
bytes_indicated = size;
}
assert(size > 0);
assert(bytes_indicated != 0);
return bytes_indicated;
}
| DoS Exec Code | 0 | vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
VMXNET3State *s = qemu_get_nic_opaque(nc);
size_t bytes_indicated;
if (!vmxnet3_can_receive(nc)) {
VMW_PKPRN("Cannot receive now");
return -1;
}
if (s->peer_has_vhdr) {
vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
buf += sizeof(struct virtio_net_hdr);
size -= sizeof(struct virtio_net_hdr);
}
vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
if (bytes_indicated < size) {
VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size);
}
} else {
VMW_PKPRN("Packet dropped by RX filter");
bytes_indicated = size;
}
assert(size > 0);
assert(bytes_indicated != 0);
return bytes_indicated;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,522 | static void vmxnet3_reset(VMXNET3State *s)
{
VMW_CBPRN("Resetting vmxnet3...");
vmxnet3_deactivate_device(s);
vmxnet3_reset_interrupt_states(s);
vmxnet_tx_pkt_reset(s->tx_pkt);
s->drv_shmem = 0;
s->tx_sop = true;
s->skip_current_tx_pkt = false;
}
| DoS Exec Code | 0 | static void vmxnet3_reset(VMXNET3State *s)
{
VMW_CBPRN("Resetting vmxnet3...");
vmxnet3_deactivate_device(s);
vmxnet3_reset_interrupt_states(s);
vmxnet_tx_pkt_reset(s->tx_pkt);
s->drv_shmem = 0;
s->tx_sop = true;
s->skip_current_tx_pkt = false;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,523 | static void vmxnet3_reset_mac(VMXNET3State *s)
{
memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
}
| DoS Exec Code | 0 | static void vmxnet3_reset_mac(VMXNET3State *s)
{
memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,524 | static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
struct Vmxnet3_RxCompDesc *rxcd)
{
int csum_ok, is_gso;
bool isip4, isip6, istcp, isudp;
struct virtio_net_hdr *vhdr;
uint8_t offload_type;
if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
rxcd->ts = 1;
rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
}
if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
goto nocsum;
}
vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
/*
* Checksum is valid when lower level tell so or when lower level
* requires checksum offload telling that packet produced/bridged
* locally and did travel over network after last checksum calculation
* or production
*/
csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
if (!csum_ok && !is_gso) {
goto nocsum;
}
vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
if ((!istcp && !isudp) || (!isip4 && !isip6)) {
goto nocsum;
}
rxcd->cnc = 0;
rxcd->v4 = isip4 ? 1 : 0;
rxcd->v6 = isip6 ? 1 : 0;
rxcd->tcp = istcp ? 1 : 0;
rxcd->udp = isudp ? 1 : 0;
rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
return;
nocsum:
rxcd->cnc = 1;
return;
}
| DoS Exec Code | 0 | static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
struct Vmxnet3_RxCompDesc *rxcd)
{
int csum_ok, is_gso;
bool isip4, isip6, istcp, isudp;
struct virtio_net_hdr *vhdr;
uint8_t offload_type;
if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
rxcd->ts = 1;
rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
}
if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
goto nocsum;
}
vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
/*
* Checksum is valid when lower level tell so or when lower level
* requires checksum offload telling that packet produced/bridged
* locally and did travel over network after last checksum calculation
* or production
*/
csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
if (!csum_ok && !is_gso) {
goto nocsum;
}
vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
if ((!istcp && !isudp) || (!isip4 && !isip6)) {
goto nocsum;
}
rxcd->cnc = 0;
rxcd->v4 = isip4 ? 1 : 0;
rxcd->v6 = isip6 ? 1 : 0;
rxcd->tcp = istcp ? 1 : 0;
rxcd->udp = isudp ? 1 : 0;
rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
return;
nocsum:
rxcd->cnc = 1;
return;
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,525 | static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
{
uint32_t events;
VMW_CBPRN("Setting events: 0x%x", val);
events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
}
| DoS Exec Code | 0 | static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
{
uint32_t events;
VMW_CBPRN("Setting events: 0x%x", val);
events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,526 | static void vmxnet3_update_features(VMXNET3State *s)
{
uint32_t guest_features;
int rxcso_supported;
guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
devRead.misc.uptFeatures);
rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
s->lro_supported, rxcso_supported,
s->rx_vlan_stripping);
if (s->peer_has_vhdr) {
qemu_set_offload(qemu_get_queue(s->nic)->peer,
rxcso_supported,
s->lro_supported,
s->lro_supported,
0,
0);
}
}
| DoS Exec Code | 0 | static void vmxnet3_update_features(VMXNET3State *s)
{
uint32_t guest_features;
int rxcso_supported;
guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
devRead.misc.uptFeatures);
rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
s->lro_supported, rxcso_supported,
s->rx_vlan_stripping);
if (s->peer_has_vhdr) {
qemu_set_offload(qemu_get_queue(s->nic)->peer,
rxcso_supported,
s->lro_supported,
s->lro_supported,
0,
0);
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,527 | static void vmxnet3_update_mcast_filters(VMXNET3State *s)
{
uint16_t list_bytes =
VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
devRead.rxFilterConf.mfTableLen);
s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
s->mcast_list = g_realloc(s->mcast_list, list_bytes);
if (NULL == s->mcast_list) {
if (0 == s->mcast_list_len) {
VMW_CFPRN("Current multicast list is empty");
} else {
VMW_ERPRN("Failed to allocate multicast list of %d elements",
s->mcast_list_len);
}
s->mcast_list_len = 0;
} else {
int i;
hwaddr mcast_list_pa =
VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
devRead.rxFilterConf.mfTablePA);
cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
for (i = 0; i < s->mcast_list_len; i++) {
VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
}
}
}
| DoS Exec Code | 0 | static void vmxnet3_update_mcast_filters(VMXNET3State *s)
{
uint16_t list_bytes =
VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
devRead.rxFilterConf.mfTableLen);
s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
s->mcast_list = g_realloc(s->mcast_list, list_bytes);
if (NULL == s->mcast_list) {
if (0 == s->mcast_list_len) {
VMW_CFPRN("Current multicast list is empty");
} else {
VMW_ERPRN("Failed to allocate multicast list of %d elements",
s->mcast_list_len);
}
s->mcast_list_len = 0;
} else {
int i;
hwaddr mcast_list_pa =
VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
devRead.rxFilterConf.mfTablePA);
cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
for (i = 0; i < s->mcast_list_len; i++) {
VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
}
}
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,528 | static void vmxnet3_update_pm_state(VMXNET3State *s)
{
struct Vmxnet3_VariableLenConfDesc pm_descr;
pm_descr.confLen =
VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
pm_descr.confVer =
VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
pm_descr.confPA =
VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
vmxnet3_dump_conf_descr("PM State", &pm_descr);
}
| DoS Exec Code | 0 | static void vmxnet3_update_pm_state(VMXNET3State *s)
{
struct Vmxnet3_VariableLenConfDesc pm_descr;
pm_descr.confLen =
VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
pm_descr.confVer =
VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
pm_descr.confPA =
VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
vmxnet3_dump_conf_descr("PM State", &pm_descr);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,529 | static void vmxnet3_update_rx_mode(VMXNET3State *s)
{
s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
devRead.rxFilterConf.rxMode);
VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
}
| DoS Exec Code | 0 | static void vmxnet3_update_rx_mode(VMXNET3State *s)
{
s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
devRead.rxFilterConf.rxMode);
VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
}
| @@ -2391,6 +2391,8 @@ static int vmxnet3_post_load(void *opaque, int version_id)
}
}
+ vmxnet3_validate_interrupts(s);
+
return 0;
} | CWE-20 | null | null |
12,530 | static int vmxnet3_post_load(void *opaque, int version_id)
{
VMXNET3State *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
if (s->msix_used) {
if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
VMW_WRPRN("Failed to re-use MSI-X vectors");
msix_uninit(d, &s->msix_bar, &s->msix_bar);
s->msix_used = false;
return -1;
}
}
return 0;
}
| DoS Exec Code | 0 | static int vmxnet3_post_load(void *opaque, int version_id)
{
VMXNET3State *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
if (s->msix_used) {
if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
VMW_WRPRN("Failed to re-use MSI-X vectors");
msix_uninit(d, &s->msix_bar, &s->msix_bar);
s->msix_used = false;
return -1;
}
}
return 0;
}
| @@ -1336,6 +1336,23 @@ static void vmxnet3_validate_interrupts(VMXNET3State *s)
}
}
+static void vmxnet3_validate_queues(VMXNET3State *s)
+{
+ /*
+ * txq_num and rxq_num are total number of queues
+ * configured by guest. These numbers must not
+ * exceed corresponding maximal values.
+ */
+
+ if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
+ hw_error("Bad TX queues number: %d\n", s->txq_num);
+ }
+
+ if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
+ hw_error("Bad RX queues number: %d\n", s->rxq_num);
+ }
+}
+
static void vmxnet3_activate_device(VMXNET3State *s)
{
int i;
@@ -1382,7 +1399,7 @@ static void vmxnet3_activate_device(VMXNET3State *s)
VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
- assert(s->txq_num <= VMXNET3_DEVICE_MAX_TX_QUEUES);
+ vmxnet3_validate_queues(s);
qdescr_table_pa =
VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA); | CWE-20 | null | null |
12,531 | static void vmxnet3_validate_interrupts(VMXNET3State *s)
{
int i;
VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
for (i = 0; i < s->txq_num; i++) {
int idx = s->txq_descr[i].intr_idx;
VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
vmxnet3_validate_interrupt_idx(s->msix_used, idx);
}
for (i = 0; i < s->rxq_num; i++) {
int idx = s->rxq_descr[i].intr_idx;
VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
vmxnet3_validate_interrupt_idx(s->msix_used, idx);
}
}
| DoS Exec Code | 0 | static void vmxnet3_validate_interrupts(VMXNET3State *s)
{
int i;
VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
for (i = 0; i < s->txq_num; i++) {
int idx = s->txq_descr[i].intr_idx;
VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
vmxnet3_validate_interrupt_idx(s->msix_used, idx);
}
for (i = 0; i < s->rxq_num; i++) {
int idx = s->rxq_descr[i].intr_idx;
VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
vmxnet3_validate_interrupt_idx(s->msix_used, idx);
}
}
| @@ -1336,6 +1336,23 @@ static void vmxnet3_validate_interrupts(VMXNET3State *s)
}
}
+static void vmxnet3_validate_queues(VMXNET3State *s)
+{
+ /*
+ * txq_num and rxq_num are total number of queues
+ * configured by guest. These numbers must not
+ * exceed corresponding maximal values.
+ */
+
+ if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
+ hw_error("Bad TX queues number: %d\n", s->txq_num);
+ }
+
+ if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
+ hw_error("Bad RX queues number: %d\n", s->rxq_num);
+ }
+}
+
static void vmxnet3_activate_device(VMXNET3State *s)
{
int i;
@@ -1382,7 +1399,7 @@ static void vmxnet3_activate_device(VMXNET3State *s)
VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
- assert(s->txq_num <= VMXNET3_DEVICE_MAX_TX_QUEUES);
+ vmxnet3_validate_queues(s);
qdescr_table_pa =
VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA); | CWE-20 | null | null |
12,532 | static void qemu_sgl_init_external(VirtIOSCSIReq *req, struct iovec *sg,
hwaddr *addr, int num)
{
QEMUSGList *qsgl = &req->qsgl;
qemu_sglist_init(qsgl, DEVICE(req->dev), num, &address_space_memory);
while (num--) {
qemu_sglist_add(qsgl, *(addr++), (sg++)->iov_len);
}
}
| Exec Code Overflow | 0 | static void qemu_sgl_init_external(VirtIOSCSIReq *req, struct iovec *sg,
hwaddr *addr, int num)
{
QEMUSGList *qsgl = &req->qsgl;
qemu_sglist_init(qsgl, DEVICE(req->dev), num, &address_space_memory);
while (num--) {
qemu_sglist_add(qsgl, *(addr++), (sg++)->iov_len);
}
}
| @@ -147,6 +147,15 @@ static void *virtio_scsi_load_request(QEMUFile *f, SCSIRequest *sreq)
qemu_get_be32s(f, &n);
assert(n < vs->conf.num_queues);
qemu_get_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
+ /* TODO: add a way for SCSIBusInfo's load_request to fail,
+ * and fail migration instead of asserting here.
+ * When we do, we might be able to re-enable NDEBUG below.
+ */
+#ifdef NDEBUG
+#error building with NDEBUG is not supported
+#endif
+ assert(req->elem.in_num <= ARRAY_SIZE(req->elem.in_sg));
+ assert(req->elem.out_num <= ARRAY_SIZE(req->elem.out_sg));
virtio_scsi_parse_req(s, vs->cmd_vqs[n], req);
scsi_req_ref(sreq); | CWE-119 | null | null |
12,533 | static void virtio_scsi_bad_req(void)
{
error_report("wrong size for virtio-scsi headers");
exit(1);
}
| Exec Code Overflow | 0 | static void virtio_scsi_bad_req(void)
{
error_report("wrong size for virtio-scsi headers");
exit(1);
}
| @@ -147,6 +147,15 @@ static void *virtio_scsi_load_request(QEMUFile *f, SCSIRequest *sreq)
qemu_get_be32s(f, &n);
assert(n < vs->conf.num_queues);
qemu_get_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
+ /* TODO: add a way for SCSIBusInfo's load_request to fail,
+ * and fail migration instead of asserting here.
+ * When we do, we might be able to re-enable NDEBUG below.
+ */
+#ifdef NDEBUG
+#error building with NDEBUG is not supported
+#endif
+ assert(req->elem.in_num <= ARRAY_SIZE(req->elem.in_sg));
+ assert(req->elem.out_num <= ARRAY_SIZE(req->elem.out_sg));
virtio_scsi_parse_req(s, vs->cmd_vqs[n], req);
scsi_req_ref(sreq); | CWE-119 | null | null |
12,534 | static void virtio_scsi_complete_req(VirtIOSCSIReq *req)
{
VirtIOSCSI *s = req->dev;
VirtQueue *vq = req->vq;
VirtIODevice *vdev = VIRTIO_DEVICE(s);
virtqueue_push(vq, &req->elem, req->qsgl.size + req->elem.in_sg[0].iov_len);
qemu_sglist_destroy(&req->qsgl);
if (req->sreq) {
req->sreq->hba_private = NULL;
scsi_req_unref(req->sreq);
}
g_free(req);
virtio_notify(vdev, vq);
}
| Exec Code Overflow | 0 | static void virtio_scsi_complete_req(VirtIOSCSIReq *req)
{
VirtIOSCSI *s = req->dev;
VirtQueue *vq = req->vq;
VirtIODevice *vdev = VIRTIO_DEVICE(s);
virtqueue_push(vq, &req->elem, req->qsgl.size + req->elem.in_sg[0].iov_len);
qemu_sglist_destroy(&req->qsgl);
if (req->sreq) {
req->sreq->hba_private = NULL;
scsi_req_unref(req->sreq);
}
g_free(req);
virtio_notify(vdev, vq);
}
| @@ -147,6 +147,15 @@ static void *virtio_scsi_load_request(QEMUFile *f, SCSIRequest *sreq)
qemu_get_be32s(f, &n);
assert(n < vs->conf.num_queues);
qemu_get_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
+ /* TODO: add a way for SCSIBusInfo's load_request to fail,
+ * and fail migration instead of asserting here.
+ * When we do, we might be able to re-enable NDEBUG below.
+ */
+#ifdef NDEBUG
+#error building with NDEBUG is not supported
+#endif
+ assert(req->elem.in_num <= ARRAY_SIZE(req->elem.in_sg));
+ assert(req->elem.out_num <= ARRAY_SIZE(req->elem.out_sg));
virtio_scsi_parse_req(s, vs->cmd_vqs[n], req);
scsi_req_ref(sreq); | CWE-119 | null | null |
12,535 | static inline SCSIDevice *virtio_scsi_device_find(VirtIOSCSI *s, uint8_t *lun)
{
if (lun[0] != 1) {
return NULL;
}
if (lun[2] != 0 && !(lun[2] >= 0x40 && lun[2] < 0x80)) {
return NULL;
}
return scsi_device_find(&s->bus, 0, lun[1], virtio_scsi_get_lun(lun));
}
| Exec Code Overflow | 0 | static inline SCSIDevice *virtio_scsi_device_find(VirtIOSCSI *s, uint8_t *lun)
{
if (lun[0] != 1) {
return NULL;
}
if (lun[2] != 0 && !(lun[2] >= 0x40 && lun[2] < 0x80)) {
return NULL;
}
return scsi_device_find(&s->bus, 0, lun[1], virtio_scsi_get_lun(lun));
}
| @@ -147,6 +147,15 @@ static void *virtio_scsi_load_request(QEMUFile *f, SCSIRequest *sreq)
qemu_get_be32s(f, &n);
assert(n < vs->conf.num_queues);
qemu_get_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
+ /* TODO: add a way for SCSIBusInfo's load_request to fail,
+ * and fail migration instead of asserting here.
+ * When we do, we might be able to re-enable NDEBUG below.
+ */
+#ifdef NDEBUG
+#error building with NDEBUG is not supported
+#endif
+ assert(req->elem.in_num <= ARRAY_SIZE(req->elem.in_sg));
+ assert(req->elem.out_num <= ARRAY_SIZE(req->elem.out_sg));
virtio_scsi_parse_req(s, vs->cmd_vqs[n], req);
scsi_req_ref(sreq); | CWE-119 | null | null |
12,536 | static inline int virtio_scsi_get_lun(uint8_t *lun)
{
return ((lun[2] << 8) | lun[3]) & 0x3FFF;
}
| Exec Code Overflow | 0 | static inline int virtio_scsi_get_lun(uint8_t *lun)
{
return ((lun[2] << 8) | lun[3]) & 0x3FFF;
}
| @@ -147,6 +147,15 @@ static void *virtio_scsi_load_request(QEMUFile *f, SCSIRequest *sreq)
qemu_get_be32s(f, &n);
assert(n < vs->conf.num_queues);
qemu_get_buffer(f, (unsigned char *)&req->elem, sizeof(req->elem));
+ /* TODO: add a way for SCSIBusInfo's load_request to fail,
+ * and fail migration instead of asserting here.
+ * When we do, we might be able to re-enable NDEBUG below.
+ */
+#ifdef NDEBUG
+#error building with NDEBUG is not supported
+#endif
+ assert(req->elem.in_num <= ARRAY_SIZE(req->elem.in_sg));
+ assert(req->elem.out_num <= ARRAY_SIZE(req->elem.out_sg));
virtio_scsi_parse_req(s, vs->cmd_vqs[n], req);
scsi_req_ref(sreq); | CWE-119 | null | null |
12,537 | static void usb_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
k->print_dev = usb_bus_dev_print;
k->get_dev_path = usb_get_dev_path;
k->get_fw_dev_path = usb_get_fw_dev_path;
}
| Exec Code Overflow | 0 | static void usb_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
k->print_dev = usb_bus_dev_print;
k->get_dev_path = usb_get_dev_path;
k->get_fw_dev_path = usb_get_fw_dev_path;
}
| @@ -49,7 +49,9 @@ static int usb_device_post_load(void *opaque, int version_id)
} else {
dev->attached = 1;
}
- if (dev->setup_index >= sizeof(dev->data_buf) ||
+ if (dev->setup_index < 0 ||
+ dev->setup_len < 0 ||
+ dev->setup_index >= sizeof(dev->data_buf) ||
dev->setup_len >= sizeof(dev->data_buf)) {
return -EINVAL;
} | CWE-119 | null | null |
12,538 | static void scoop_gpio_set(void *opaque, int line, int level)
{
ScoopInfo *s = (ScoopInfo *) opaque;
if (level)
s->gpio_level |= (1 << line);
else
s->gpio_level &= ~(1 << line);
}
| Exec Code Overflow | 0 | static void scoop_gpio_set(void *opaque, int line, int level)
{
ScoopInfo *s = (ScoopInfo *) opaque;
if (level)
s->gpio_level |= (1 << line);
else
s->gpio_level &= ~(1 << line);
}
| @@ -203,6 +203,15 @@ static bool is_version_0 (void *opaque, int version_id)
return version_id == 0;
}
+static bool vmstate_scoop_validate(void *opaque, int version_id)
+{
+ ScoopInfo *s = opaque;
+
+ return !(s->prev_level & 0xffff0000) &&
+ !(s->gpio_level & 0xffff0000) &&
+ !(s->gpio_dir & 0xffff0000);
+}
+
static const VMStateDescription vmstate_scoop_regs = {
.name = "scoop",
.version_id = 1,
@@ -215,6 +224,7 @@ static const VMStateDescription vmstate_scoop_regs = {
VMSTATE_UINT32(gpio_level, ScoopInfo),
VMSTATE_UINT32(gpio_dir, ScoopInfo),
VMSTATE_UINT32(prev_level, ScoopInfo),
+ VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
VMSTATE_UINT16(mcr, ScoopInfo),
VMSTATE_UINT16(cdr, ScoopInfo),
VMSTATE_UINT16(ccr, ScoopInfo), | CWE-119 | null | null |
12,539 | static int scoop_post_load(void *opaque, int version_id)
{
ScoopInfo *s = (ScoopInfo *) opaque;
int i;
uint32_t level;
level = s->gpio_level & s->gpio_dir;
for (i = 0; i < 16; i++) {
qemu_set_irq(s->handler[i], (level >> i) & 1);
}
s->prev_level = level;
return 0;
}
| Exec Code Overflow | 0 | static int scoop_post_load(void *opaque, int version_id)
{
ScoopInfo *s = (ScoopInfo *) opaque;
int i;
uint32_t level;
level = s->gpio_level & s->gpio_dir;
for (i = 0; i < 16; i++) {
qemu_set_irq(s->handler[i], (level >> i) & 1);
}
s->prev_level = level;
return 0;
}
| @@ -203,6 +203,15 @@ static bool is_version_0 (void *opaque, int version_id)
return version_id == 0;
}
+static bool vmstate_scoop_validate(void *opaque, int version_id)
+{
+ ScoopInfo *s = opaque;
+
+ return !(s->prev_level & 0xffff0000) &&
+ !(s->gpio_level & 0xffff0000) &&
+ !(s->gpio_dir & 0xffff0000);
+}
+
static const VMStateDescription vmstate_scoop_regs = {
.name = "scoop",
.version_id = 1,
@@ -215,6 +224,7 @@ static const VMStateDescription vmstate_scoop_regs = {
VMSTATE_UINT32(gpio_level, ScoopInfo),
VMSTATE_UINT32(gpio_dir, ScoopInfo),
VMSTATE_UINT32(prev_level, ScoopInfo),
+ VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
VMSTATE_UINT16(mcr, ScoopInfo),
VMSTATE_UINT16(cdr, ScoopInfo),
VMSTATE_UINT16(ccr, ScoopInfo), | CWE-119 | null | null |
12,540 | static uint64_t scoop_read(void *opaque, hwaddr addr,
unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
switch (addr & 0x3f) {
case SCOOP_MCR:
return s->mcr;
case SCOOP_CDR:
return s->cdr;
case SCOOP_CSR:
return s->status;
case SCOOP_CPR:
return s->power;
case SCOOP_CCR:
return s->ccr;
case SCOOP_IRR_IRM:
return s->irr;
case SCOOP_IMR:
return s->imr;
case SCOOP_ISR:
return s->isr;
case SCOOP_GPCR:
return s->gpio_dir;
case SCOOP_GPWR:
case SCOOP_GPRR:
return s->gpio_level;
default:
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
}
return 0;
}
| Exec Code Overflow | 0 | static uint64_t scoop_read(void *opaque, hwaddr addr,
unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
switch (addr & 0x3f) {
case SCOOP_MCR:
return s->mcr;
case SCOOP_CDR:
return s->cdr;
case SCOOP_CSR:
return s->status;
case SCOOP_CPR:
return s->power;
case SCOOP_CCR:
return s->ccr;
case SCOOP_IRR_IRM:
return s->irr;
case SCOOP_IMR:
return s->imr;
case SCOOP_ISR:
return s->isr;
case SCOOP_GPCR:
return s->gpio_dir;
case SCOOP_GPWR:
case SCOOP_GPRR:
return s->gpio_level;
default:
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
}
return 0;
}
| @@ -203,6 +203,15 @@ static bool is_version_0 (void *opaque, int version_id)
return version_id == 0;
}
+static bool vmstate_scoop_validate(void *opaque, int version_id)
+{
+ ScoopInfo *s = opaque;
+
+ return !(s->prev_level & 0xffff0000) &&
+ !(s->gpio_level & 0xffff0000) &&
+ !(s->gpio_dir & 0xffff0000);
+}
+
static const VMStateDescription vmstate_scoop_regs = {
.name = "scoop",
.version_id = 1,
@@ -215,6 +224,7 @@ static const VMStateDescription vmstate_scoop_regs = {
VMSTATE_UINT32(gpio_level, ScoopInfo),
VMSTATE_UINT32(gpio_dir, ScoopInfo),
VMSTATE_UINT32(prev_level, ScoopInfo),
+ VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
VMSTATE_UINT16(mcr, ScoopInfo),
VMSTATE_UINT16(cdr, ScoopInfo),
VMSTATE_UINT16(ccr, ScoopInfo), | CWE-119 | null | null |
12,541 | static void scoop_register_types(void)
{
type_register_static(&scoop_sysbus_info);
}
| Exec Code Overflow | 0 | static void scoop_register_types(void)
{
type_register_static(&scoop_sysbus_info);
}
| @@ -203,6 +203,15 @@ static bool is_version_0 (void *opaque, int version_id)
return version_id == 0;
}
+static bool vmstate_scoop_validate(void *opaque, int version_id)
+{
+ ScoopInfo *s = opaque;
+
+ return !(s->prev_level & 0xffff0000) &&
+ !(s->gpio_level & 0xffff0000) &&
+ !(s->gpio_dir & 0xffff0000);
+}
+
static const VMStateDescription vmstate_scoop_regs = {
.name = "scoop",
.version_id = 1,
@@ -215,6 +224,7 @@ static const VMStateDescription vmstate_scoop_regs = {
VMSTATE_UINT32(gpio_level, ScoopInfo),
VMSTATE_UINT32(gpio_dir, ScoopInfo),
VMSTATE_UINT32(prev_level, ScoopInfo),
+ VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
VMSTATE_UINT16(mcr, ScoopInfo),
VMSTATE_UINT16(cdr, ScoopInfo),
VMSTATE_UINT16(ccr, ScoopInfo), | CWE-119 | null | null |
12,542 | static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = scoop_init;
dc->desc = "Scoop2 Sharp custom ASIC";
dc->vmsd = &vmstate_scoop_regs;
dc->props = scoop_sysbus_properties;
}
| Exec Code Overflow | 0 | static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = scoop_init;
dc->desc = "Scoop2 Sharp custom ASIC";
dc->vmsd = &vmstate_scoop_regs;
dc->props = scoop_sysbus_properties;
}
| @@ -203,6 +203,15 @@ static bool is_version_0 (void *opaque, int version_id)
return version_id == 0;
}
+static bool vmstate_scoop_validate(void *opaque, int version_id)
+{
+ ScoopInfo *s = opaque;
+
+ return !(s->prev_level & 0xffff0000) &&
+ !(s->gpio_level & 0xffff0000) &&
+ !(s->gpio_dir & 0xffff0000);
+}
+
static const VMStateDescription vmstate_scoop_regs = {
.name = "scoop",
.version_id = 1,
@@ -215,6 +224,7 @@ static const VMStateDescription vmstate_scoop_regs = {
VMSTATE_UINT32(gpio_level, ScoopInfo),
VMSTATE_UINT32(gpio_dir, ScoopInfo),
VMSTATE_UINT32(prev_level, ScoopInfo),
+ VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
VMSTATE_UINT16(mcr, ScoopInfo),
VMSTATE_UINT16(cdr, ScoopInfo),
VMSTATE_UINT16(ccr, ScoopInfo), | CWE-119 | null | null |
12,543 | static void scoop_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
value &= 0xffff;
switch (addr & 0x3f) {
case SCOOP_MCR:
s->mcr = value;
break;
case SCOOP_CDR:
s->cdr = value;
break;
case SCOOP_CPR:
s->power = value;
if (value & 0x80)
s->power |= 0x8040;
break;
case SCOOP_CCR:
s->ccr = value;
break;
case SCOOP_IRR_IRM:
s->irr = value;
break;
case SCOOP_IMR:
s->imr = value;
break;
case SCOOP_ISR:
s->isr = value;
break;
case SCOOP_GPCR:
s->gpio_dir = value;
scoop_gpio_handler_update(s);
break;
case SCOOP_GPWR:
case SCOOP_GPRR: /* GPRR is probably R/O in real HW */
s->gpio_level = value & s->gpio_dir;
scoop_gpio_handler_update(s);
break;
default:
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
}
}
| Exec Code Overflow | 0 | static void scoop_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
value &= 0xffff;
switch (addr & 0x3f) {
case SCOOP_MCR:
s->mcr = value;
break;
case SCOOP_CDR:
s->cdr = value;
break;
case SCOOP_CPR:
s->power = value;
if (value & 0x80)
s->power |= 0x8040;
break;
case SCOOP_CCR:
s->ccr = value;
break;
case SCOOP_IRR_IRM:
s->irr = value;
break;
case SCOOP_IMR:
s->imr = value;
break;
case SCOOP_ISR:
s->isr = value;
break;
case SCOOP_GPCR:
s->gpio_dir = value;
scoop_gpio_handler_update(s);
break;
case SCOOP_GPWR:
case SCOOP_GPRR: /* GPRR is probably R/O in real HW */
s->gpio_level = value & s->gpio_dir;
scoop_gpio_handler_update(s);
break;
default:
zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
}
}
| @@ -203,6 +203,15 @@ static bool is_version_0 (void *opaque, int version_id)
return version_id == 0;
}
+static bool vmstate_scoop_validate(void *opaque, int version_id)
+{
+ ScoopInfo *s = opaque;
+
+ return !(s->prev_level & 0xffff0000) &&
+ !(s->gpio_level & 0xffff0000) &&
+ !(s->gpio_dir & 0xffff0000);
+}
+
static const VMStateDescription vmstate_scoop_regs = {
.name = "scoop",
.version_id = 1,
@@ -215,6 +224,7 @@ static const VMStateDescription vmstate_scoop_regs = {
VMSTATE_UINT32(gpio_level, ScoopInfo),
VMSTATE_UINT32(gpio_dir, ScoopInfo),
VMSTATE_UINT32(prev_level, ScoopInfo),
+ VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
VMSTATE_UINT16(mcr, ScoopInfo),
VMSTATE_UINT16(cdr, ScoopInfo),
VMSTATE_UINT16(ccr, ScoopInfo), | CWE-119 | null | null |
12,544 | static void tsc2102_audio_output_update(TSC210xState *s)
{
int enable;
struct audsettings fmt;
if (s->dac_voice[0]) {
tsc210x_out_flush(s, s->codec.out.len);
s->codec.out.size = 0;
AUD_set_active_out(s->dac_voice[0], 0);
AUD_close_out(&s->card, s->dac_voice[0]);
s->dac_voice[0] = NULL;
}
s->codec.cts = 0;
enable =
(~s->dac_power & (1 << 15)) && /* PWDNC */
(~s->dac_power & (1 << 10)); /* DAPWDN */
if (!enable || !s->codec.tx_rate)
return;
/* Force our own sampling rate even in slave DAC mode */
fmt.endianness = 0;
fmt.nchannels = 2;
fmt.freq = s->codec.tx_rate;
fmt.fmt = AUD_FMT_S16;
s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
"tsc2102.sink", s, (void *) tsc210x_audio_out_cb, &fmt);
if (s->dac_voice[0]) {
s->codec.cts = 1;
AUD_set_active_out(s->dac_voice[0], 1);
}
}
| Exec Code Overflow | 0 | static void tsc2102_audio_output_update(TSC210xState *s)
{
int enable;
struct audsettings fmt;
if (s->dac_voice[0]) {
tsc210x_out_flush(s, s->codec.out.len);
s->codec.out.size = 0;
AUD_set_active_out(s->dac_voice[0], 0);
AUD_close_out(&s->card, s->dac_voice[0]);
s->dac_voice[0] = NULL;
}
s->codec.cts = 0;
enable =
(~s->dac_power & (1 << 15)) && /* PWDNC */
(~s->dac_power & (1 << 10)); /* DAPWDN */
if (!enable || !s->codec.tx_rate)
return;
/* Force our own sampling rate even in slave DAC mode */
fmt.endianness = 0;
fmt.nchannels = 2;
fmt.freq = s->codec.tx_rate;
fmt.fmt = AUD_FMT_S16;
s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
"tsc2102.sink", s, (void *) tsc210x_audio_out_cb, &fmt);
if (s->dac_voice[0]) {
s->codec.cts = 1;
AUD_set_active_out(s->dac_voice[0], 1);
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,545 | static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
{
int l_ch, r_ch;
uint16_t val;
switch (reg) {
case 0x00: /* Audio Control 1 */
return s->audio_ctrl1;
case 0x01:
return 0xff00;
case 0x02: /* DAC Volume Control */
return s->volume;
case 0x03:
return 0x8b00;
case 0x04: /* Audio Control 2 */
l_ch = 1;
r_ch = 1;
if (s->softstep && !(s->dac_power & (1 << 10))) {
l_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->volume_change + TSC_SOFTSTEP_DELAY);
r_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->volume_change + TSC_SOFTSTEP_DELAY);
}
return s->audio_ctrl2 | (l_ch << 3) | (r_ch << 2);
case 0x05: /* Stereo DAC Power Control */
return 0x2aa0 | s->dac_power |
(((s->dac_power & (1 << 10)) &&
(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->powerdown + TSC_POWEROFF_DELAY)) << 6);
case 0x06: /* Audio Control 3 */
val = s->audio_ctrl3 | 0x0001;
s->audio_ctrl3 &= 0xff3f;
return val;
case 0x07: /* LCH_BASS_BOOST_N0 */
case 0x08: /* LCH_BASS_BOOST_N1 */
case 0x09: /* LCH_BASS_BOOST_N2 */
case 0x0a: /* LCH_BASS_BOOST_N3 */
case 0x0b: /* LCH_BASS_BOOST_N4 */
case 0x0c: /* LCH_BASS_BOOST_N5 */
case 0x0d: /* LCH_BASS_BOOST_D1 */
case 0x0e: /* LCH_BASS_BOOST_D2 */
case 0x0f: /* LCH_BASS_BOOST_D4 */
case 0x10: /* LCH_BASS_BOOST_D5 */
case 0x11: /* RCH_BASS_BOOST_N0 */
case 0x12: /* RCH_BASS_BOOST_N1 */
case 0x13: /* RCH_BASS_BOOST_N2 */
case 0x14: /* RCH_BASS_BOOST_N3 */
case 0x15: /* RCH_BASS_BOOST_N4 */
case 0x16: /* RCH_BASS_BOOST_N5 */
case 0x17: /* RCH_BASS_BOOST_D1 */
case 0x18: /* RCH_BASS_BOOST_D2 */
case 0x19: /* RCH_BASS_BOOST_D4 */
case 0x1a: /* RCH_BASS_BOOST_D5 */
return s->filter_data[reg - 0x07];
case 0x1b: /* PLL Programmability 1 */
return s->pll[0];
case 0x1c: /* PLL Programmability 2 */
return s->pll[1];
case 0x1d: /* Audio Control 4 */
return (!s->softstep) << 14;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_audio_register_read: "
"no such register: 0x%02x\n", reg);
#endif
return 0xffff;
}
}
| Exec Code Overflow | 0 | static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
{
int l_ch, r_ch;
uint16_t val;
switch (reg) {
case 0x00: /* Audio Control 1 */
return s->audio_ctrl1;
case 0x01:
return 0xff00;
case 0x02: /* DAC Volume Control */
return s->volume;
case 0x03:
return 0x8b00;
case 0x04: /* Audio Control 2 */
l_ch = 1;
r_ch = 1;
if (s->softstep && !(s->dac_power & (1 << 10))) {
l_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->volume_change + TSC_SOFTSTEP_DELAY);
r_ch = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->volume_change + TSC_SOFTSTEP_DELAY);
}
return s->audio_ctrl2 | (l_ch << 3) | (r_ch << 2);
case 0x05: /* Stereo DAC Power Control */
return 0x2aa0 | s->dac_power |
(((s->dac_power & (1 << 10)) &&
(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >
s->powerdown + TSC_POWEROFF_DELAY)) << 6);
case 0x06: /* Audio Control 3 */
val = s->audio_ctrl3 | 0x0001;
s->audio_ctrl3 &= 0xff3f;
return val;
case 0x07: /* LCH_BASS_BOOST_N0 */
case 0x08: /* LCH_BASS_BOOST_N1 */
case 0x09: /* LCH_BASS_BOOST_N2 */
case 0x0a: /* LCH_BASS_BOOST_N3 */
case 0x0b: /* LCH_BASS_BOOST_N4 */
case 0x0c: /* LCH_BASS_BOOST_N5 */
case 0x0d: /* LCH_BASS_BOOST_D1 */
case 0x0e: /* LCH_BASS_BOOST_D2 */
case 0x0f: /* LCH_BASS_BOOST_D4 */
case 0x10: /* LCH_BASS_BOOST_D5 */
case 0x11: /* RCH_BASS_BOOST_N0 */
case 0x12: /* RCH_BASS_BOOST_N1 */
case 0x13: /* RCH_BASS_BOOST_N2 */
case 0x14: /* RCH_BASS_BOOST_N3 */
case 0x15: /* RCH_BASS_BOOST_N4 */
case 0x16: /* RCH_BASS_BOOST_N5 */
case 0x17: /* RCH_BASS_BOOST_D1 */
case 0x18: /* RCH_BASS_BOOST_D2 */
case 0x19: /* RCH_BASS_BOOST_D4 */
case 0x1a: /* RCH_BASS_BOOST_D5 */
return s->filter_data[reg - 0x07];
case 0x1b: /* PLL Programmability 1 */
return s->pll[0];
case 0x1c: /* PLL Programmability 2 */
return s->pll[1];
case 0x1d: /* Audio Control 4 */
return (!s->softstep) << 14;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_audio_register_read: "
"no such register: 0x%02x\n", reg);
#endif
return 0xffff;
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,546 | static void tsc2102_audio_register_write(
TSC210xState *s, int reg, uint16_t value)
{
switch (reg) {
case 0x00: /* Audio Control 1 */
s->audio_ctrl1 = value & 0x0f3f;
#ifdef TSC_VERBOSE
if ((value & ~0x0f3f) || ((value & 7) != ((value >> 3) & 7)))
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 1\n");
#endif
tsc2102_audio_rate_update(s);
tsc2102_audio_output_update(s);
return;
case 0x01:
#ifdef TSC_VERBOSE
if (value != 0xff00)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into reg 0x01\n");
#endif
return;
case 0x02: /* DAC Volume Control */
s->volume = value;
s->volume_change = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return;
case 0x03:
#ifdef TSC_VERBOSE
if (value != 0x8b00)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into reg 0x03\n");
#endif
return;
case 0x04: /* Audio Control 2 */
s->audio_ctrl2 = value & 0xf7f2;
#ifdef TSC_VERBOSE
if (value & ~0xf7fd)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 2\n");
#endif
return;
case 0x05: /* Stereo DAC Power Control */
if ((value & ~s->dac_power) & (1 << 10))
s->powerdown = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->dac_power = value & 0x9543;
#ifdef TSC_VERBOSE
if ((value & ~0x9543) != 0x2aa0)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Power\n");
#endif
tsc2102_audio_rate_update(s);
tsc2102_audio_output_update(s);
return;
case 0x06: /* Audio Control 3 */
s->audio_ctrl3 &= 0x00c0;
s->audio_ctrl3 |= value & 0xf800;
#ifdef TSC_VERBOSE
if (value & ~0xf8c7)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 3\n");
#endif
tsc2102_audio_output_update(s);
return;
case 0x07: /* LCH_BASS_BOOST_N0 */
case 0x08: /* LCH_BASS_BOOST_N1 */
case 0x09: /* LCH_BASS_BOOST_N2 */
case 0x0a: /* LCH_BASS_BOOST_N3 */
case 0x0b: /* LCH_BASS_BOOST_N4 */
case 0x0c: /* LCH_BASS_BOOST_N5 */
case 0x0d: /* LCH_BASS_BOOST_D1 */
case 0x0e: /* LCH_BASS_BOOST_D2 */
case 0x0f: /* LCH_BASS_BOOST_D4 */
case 0x10: /* LCH_BASS_BOOST_D5 */
case 0x11: /* RCH_BASS_BOOST_N0 */
case 0x12: /* RCH_BASS_BOOST_N1 */
case 0x13: /* RCH_BASS_BOOST_N2 */
case 0x14: /* RCH_BASS_BOOST_N3 */
case 0x15: /* RCH_BASS_BOOST_N4 */
case 0x16: /* RCH_BASS_BOOST_N5 */
case 0x17: /* RCH_BASS_BOOST_D1 */
case 0x18: /* RCH_BASS_BOOST_D2 */
case 0x19: /* RCH_BASS_BOOST_D4 */
case 0x1a: /* RCH_BASS_BOOST_D5 */
s->filter_data[reg - 0x07] = value;
return;
case 0x1b: /* PLL Programmability 1 */
s->pll[0] = value & 0xfffc;
#ifdef TSC_VERBOSE
if (value & ~0xfffc)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into PLL 1\n");
#endif
return;
case 0x1c: /* PLL Programmability 2 */
s->pll[1] = value & 0xfffc;
#ifdef TSC_VERBOSE
if (value & ~0xfffc)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into PLL 2\n");
#endif
return;
case 0x1d: /* Audio Control 4 */
s->softstep = !(value & 0x4000);
#ifdef TSC_VERBOSE
if (value & ~0x4000)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 4\n");
#endif
return;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_audio_register_write: "
"no such register: 0x%02x\n", reg);
#endif
}
}
| Exec Code Overflow | 0 | static void tsc2102_audio_register_write(
TSC210xState *s, int reg, uint16_t value)
{
switch (reg) {
case 0x00: /* Audio Control 1 */
s->audio_ctrl1 = value & 0x0f3f;
#ifdef TSC_VERBOSE
if ((value & ~0x0f3f) || ((value & 7) != ((value >> 3) & 7)))
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 1\n");
#endif
tsc2102_audio_rate_update(s);
tsc2102_audio_output_update(s);
return;
case 0x01:
#ifdef TSC_VERBOSE
if (value != 0xff00)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into reg 0x01\n");
#endif
return;
case 0x02: /* DAC Volume Control */
s->volume = value;
s->volume_change = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return;
case 0x03:
#ifdef TSC_VERBOSE
if (value != 0x8b00)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into reg 0x03\n");
#endif
return;
case 0x04: /* Audio Control 2 */
s->audio_ctrl2 = value & 0xf7f2;
#ifdef TSC_VERBOSE
if (value & ~0xf7fd)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 2\n");
#endif
return;
case 0x05: /* Stereo DAC Power Control */
if ((value & ~s->dac_power) & (1 << 10))
s->powerdown = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
s->dac_power = value & 0x9543;
#ifdef TSC_VERBOSE
if ((value & ~0x9543) != 0x2aa0)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Power\n");
#endif
tsc2102_audio_rate_update(s);
tsc2102_audio_output_update(s);
return;
case 0x06: /* Audio Control 3 */
s->audio_ctrl3 &= 0x00c0;
s->audio_ctrl3 |= value & 0xf800;
#ifdef TSC_VERBOSE
if (value & ~0xf8c7)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 3\n");
#endif
tsc2102_audio_output_update(s);
return;
case 0x07: /* LCH_BASS_BOOST_N0 */
case 0x08: /* LCH_BASS_BOOST_N1 */
case 0x09: /* LCH_BASS_BOOST_N2 */
case 0x0a: /* LCH_BASS_BOOST_N3 */
case 0x0b: /* LCH_BASS_BOOST_N4 */
case 0x0c: /* LCH_BASS_BOOST_N5 */
case 0x0d: /* LCH_BASS_BOOST_D1 */
case 0x0e: /* LCH_BASS_BOOST_D2 */
case 0x0f: /* LCH_BASS_BOOST_D4 */
case 0x10: /* LCH_BASS_BOOST_D5 */
case 0x11: /* RCH_BASS_BOOST_N0 */
case 0x12: /* RCH_BASS_BOOST_N1 */
case 0x13: /* RCH_BASS_BOOST_N2 */
case 0x14: /* RCH_BASS_BOOST_N3 */
case 0x15: /* RCH_BASS_BOOST_N4 */
case 0x16: /* RCH_BASS_BOOST_N5 */
case 0x17: /* RCH_BASS_BOOST_D1 */
case 0x18: /* RCH_BASS_BOOST_D2 */
case 0x19: /* RCH_BASS_BOOST_D4 */
case 0x1a: /* RCH_BASS_BOOST_D5 */
s->filter_data[reg - 0x07] = value;
return;
case 0x1b: /* PLL Programmability 1 */
s->pll[0] = value & 0xfffc;
#ifdef TSC_VERBOSE
if (value & ~0xfffc)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into PLL 1\n");
#endif
return;
case 0x1c: /* PLL Programmability 2 */
s->pll[1] = value & 0xfffc;
#ifdef TSC_VERBOSE
if (value & ~0xfffc)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into PLL 2\n");
#endif
return;
case 0x1d: /* Audio Control 4 */
s->softstep = !(value & 0x4000);
#ifdef TSC_VERBOSE
if (value & ~0x4000)
fprintf(stderr, "tsc2102_audio_register_write: "
"wrong value written into Audio 4\n");
#endif
return;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_audio_register_write: "
"no such register: 0x%02x\n", reg);
#endif
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,547 | static uint16_t tsc2102_control_register_read(
TSC210xState *s, int reg)
{
switch (reg) {
case 0x00: /* TSC ADC */
return (s->pressure << 15) | ((!s->busy) << 14) |
(s->nextfunction << 10) | (s->nextprecision << 8) | s->filter;
case 0x01: /* Status / Keypad Control */
if ((s->model & 0xff00) == 0x2100)
return (s->pin_func << 14) | ((!s->enabled) << 13) |
(s->host_mode << 12) | ((!!s->dav) << 11) | s->dav;
else
return (s->kb.intr << 15) | ((s->kb.scan || !s->kb.down) << 14) |
(s->kb.debounce << 11);
case 0x02: /* DAC Control */
if ((s->model & 0xff00) == 0x2300)
return s->dac_power & 0x8000;
else
goto bad_reg;
case 0x03: /* Reference */
return s->ref;
case 0x04: /* Reset */
return 0xffff;
case 0x05: /* Configuration */
return s->timing;
case 0x06: /* Secondary configuration */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
return ((!s->dav) << 15) | ((s->kb.mode & 1) << 14) | s->pll[2];
case 0x10: /* Keypad Mask */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
return s->kb.mask;
default:
bad_reg:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_control_register_read: "
"no such register: 0x%02x\n", reg);
#endif
return 0xffff;
}
}
| Exec Code Overflow | 0 | static uint16_t tsc2102_control_register_read(
TSC210xState *s, int reg)
{
switch (reg) {
case 0x00: /* TSC ADC */
return (s->pressure << 15) | ((!s->busy) << 14) |
(s->nextfunction << 10) | (s->nextprecision << 8) | s->filter;
case 0x01: /* Status / Keypad Control */
if ((s->model & 0xff00) == 0x2100)
return (s->pin_func << 14) | ((!s->enabled) << 13) |
(s->host_mode << 12) | ((!!s->dav) << 11) | s->dav;
else
return (s->kb.intr << 15) | ((s->kb.scan || !s->kb.down) << 14) |
(s->kb.debounce << 11);
case 0x02: /* DAC Control */
if ((s->model & 0xff00) == 0x2300)
return s->dac_power & 0x8000;
else
goto bad_reg;
case 0x03: /* Reference */
return s->ref;
case 0x04: /* Reset */
return 0xffff;
case 0x05: /* Configuration */
return s->timing;
case 0x06: /* Secondary configuration */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
return ((!s->dav) << 15) | ((s->kb.mode & 1) << 14) | s->pll[2];
case 0x10: /* Keypad Mask */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
return s->kb.mask;
default:
bad_reg:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_control_register_read: "
"no such register: 0x%02x\n", reg);
#endif
return 0xffff;
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,548 | static void tsc2102_control_register_write(
TSC210xState *s, int reg, uint16_t value)
{
switch (reg) {
case 0x00: /* TSC ADC */
s->host_mode = value >> 15;
s->enabled = !(value & 0x4000);
if (s->busy && !s->enabled)
timer_del(s->timer);
s->busy &= s->enabled;
s->nextfunction = (value >> 10) & 0xf;
s->nextprecision = (value >> 8) & 3;
s->filter = value & 0xff;
return;
case 0x01: /* Status / Keypad Control */
if ((s->model & 0xff00) == 0x2100)
s->pin_func = value >> 14;
else {
s->kb.scan = (value >> 14) & 1;
s->kb.debounce = (value >> 11) & 7;
if (s->kb.intr && s->kb.scan) {
s->kb.intr = 0;
qemu_irq_raise(s->kbint);
}
}
return;
case 0x02: /* DAC Control */
if ((s->model & 0xff00) == 0x2300) {
s->dac_power &= 0x7fff;
s->dac_power |= 0x8000 & value;
} else
goto bad_reg;
break;
case 0x03: /* Reference */
s->ref = value & 0x1f;
return;
case 0x04: /* Reset */
if (value == 0xbb00) {
if (s->busy)
timer_del(s->timer);
tsc210x_reset(s);
#ifdef TSC_VERBOSE
} else {
fprintf(stderr, "tsc2102_control_register_write: "
"wrong value written into RESET\n");
#endif
}
return;
case 0x05: /* Configuration */
s->timing = value & 0x3f;
#ifdef TSC_VERBOSE
if (value & ~0x3f)
fprintf(stderr, "tsc2102_control_register_write: "
"wrong value written into CONFIG\n");
#endif
return;
case 0x06: /* Secondary configuration */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
s->kb.mode = value >> 14;
s->pll[2] = value & 0x3ffff;
return;
case 0x10: /* Keypad Mask */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
s->kb.mask = value;
return;
default:
bad_reg:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_control_register_write: "
"no such register: 0x%02x\n", reg);
#endif
}
}
| Exec Code Overflow | 0 | static void tsc2102_control_register_write(
TSC210xState *s, int reg, uint16_t value)
{
switch (reg) {
case 0x00: /* TSC ADC */
s->host_mode = value >> 15;
s->enabled = !(value & 0x4000);
if (s->busy && !s->enabled)
timer_del(s->timer);
s->busy &= s->enabled;
s->nextfunction = (value >> 10) & 0xf;
s->nextprecision = (value >> 8) & 3;
s->filter = value & 0xff;
return;
case 0x01: /* Status / Keypad Control */
if ((s->model & 0xff00) == 0x2100)
s->pin_func = value >> 14;
else {
s->kb.scan = (value >> 14) & 1;
s->kb.debounce = (value >> 11) & 7;
if (s->kb.intr && s->kb.scan) {
s->kb.intr = 0;
qemu_irq_raise(s->kbint);
}
}
return;
case 0x02: /* DAC Control */
if ((s->model & 0xff00) == 0x2300) {
s->dac_power &= 0x7fff;
s->dac_power |= 0x8000 & value;
} else
goto bad_reg;
break;
case 0x03: /* Reference */
s->ref = value & 0x1f;
return;
case 0x04: /* Reset */
if (value == 0xbb00) {
if (s->busy)
timer_del(s->timer);
tsc210x_reset(s);
#ifdef TSC_VERBOSE
} else {
fprintf(stderr, "tsc2102_control_register_write: "
"wrong value written into RESET\n");
#endif
}
return;
case 0x05: /* Configuration */
s->timing = value & 0x3f;
#ifdef TSC_VERBOSE
if (value & ~0x3f)
fprintf(stderr, "tsc2102_control_register_write: "
"wrong value written into CONFIG\n");
#endif
return;
case 0x06: /* Secondary configuration */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
s->kb.mode = value >> 14;
s->pll[2] = value & 0x3ffff;
return;
case 0x10: /* Keypad Mask */
if ((s->model & 0xff00) == 0x2100)
goto bad_reg;
s->kb.mask = value;
return;
default:
bad_reg:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_control_register_write: "
"no such register: 0x%02x\n", reg);
#endif
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,549 | static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg)
{
switch (reg) {
case 0x00: /* X */
s->dav &= 0xfbff;
return TSC_CUT_RESOLUTION(X_TRANSFORM(s), s->precision) +
(s->noise & 3);
case 0x01: /* Y */
s->noise ++;
s->dav &= 0xfdff;
return TSC_CUT_RESOLUTION(Y_TRANSFORM(s), s->precision) ^
(s->noise & 3);
case 0x02: /* Z1 */
s->dav &= 0xfeff;
return TSC_CUT_RESOLUTION(Z1_TRANSFORM(s), s->precision) -
(s->noise & 3);
case 0x03: /* Z2 */
s->dav &= 0xff7f;
return TSC_CUT_RESOLUTION(Z2_TRANSFORM(s), s->precision) |
(s->noise & 3);
case 0x04: /* KPData */
if ((s->model & 0xff00) == 0x2300) {
if (s->kb.intr && (s->kb.mode & 2)) {
s->kb.intr = 0;
qemu_irq_raise(s->kbint);
}
return s->kb.down;
}
return 0xffff;
case 0x05: /* BAT1 */
s->dav &= 0xffbf;
return TSC_CUT_RESOLUTION(BAT1_VAL, s->precision) +
(s->noise & 6);
case 0x06: /* BAT2 */
s->dav &= 0xffdf;
return TSC_CUT_RESOLUTION(BAT2_VAL, s->precision);
case 0x07: /* AUX1 */
s->dav &= 0xffef;
return TSC_CUT_RESOLUTION(AUX1_VAL, s->precision);
case 0x08: /* AUX2 */
s->dav &= 0xfff7;
return 0xffff;
case 0x09: /* TEMP1 */
s->dav &= 0xfffb;
return TSC_CUT_RESOLUTION(TEMP1_VAL, s->precision) -
(s->noise & 5);
case 0x0a: /* TEMP2 */
s->dav &= 0xfffd;
return TSC_CUT_RESOLUTION(TEMP2_VAL, s->precision) ^
(s->noise & 3);
case 0x0b: /* DAC */
s->dav &= 0xfffe;
return 0xffff;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_data_register_read: "
"no such register: 0x%02x\n", reg);
#endif
return 0xffff;
}
}
| Exec Code Overflow | 0 | static uint16_t tsc2102_data_register_read(TSC210xState *s, int reg)
{
switch (reg) {
case 0x00: /* X */
s->dav &= 0xfbff;
return TSC_CUT_RESOLUTION(X_TRANSFORM(s), s->precision) +
(s->noise & 3);
case 0x01: /* Y */
s->noise ++;
s->dav &= 0xfdff;
return TSC_CUT_RESOLUTION(Y_TRANSFORM(s), s->precision) ^
(s->noise & 3);
case 0x02: /* Z1 */
s->dav &= 0xfeff;
return TSC_CUT_RESOLUTION(Z1_TRANSFORM(s), s->precision) -
(s->noise & 3);
case 0x03: /* Z2 */
s->dav &= 0xff7f;
return TSC_CUT_RESOLUTION(Z2_TRANSFORM(s), s->precision) |
(s->noise & 3);
case 0x04: /* KPData */
if ((s->model & 0xff00) == 0x2300) {
if (s->kb.intr && (s->kb.mode & 2)) {
s->kb.intr = 0;
qemu_irq_raise(s->kbint);
}
return s->kb.down;
}
return 0xffff;
case 0x05: /* BAT1 */
s->dav &= 0xffbf;
return TSC_CUT_RESOLUTION(BAT1_VAL, s->precision) +
(s->noise & 6);
case 0x06: /* BAT2 */
s->dav &= 0xffdf;
return TSC_CUT_RESOLUTION(BAT2_VAL, s->precision);
case 0x07: /* AUX1 */
s->dav &= 0xffef;
return TSC_CUT_RESOLUTION(AUX1_VAL, s->precision);
case 0x08: /* AUX2 */
s->dav &= 0xfff7;
return 0xffff;
case 0x09: /* TEMP1 */
s->dav &= 0xfffb;
return TSC_CUT_RESOLUTION(TEMP1_VAL, s->precision) -
(s->noise & 5);
case 0x0a: /* TEMP2 */
s->dav &= 0xfffd;
return TSC_CUT_RESOLUTION(TEMP2_VAL, s->precision) ^
(s->noise & 3);
case 0x0b: /* DAC */
s->dav &= 0xfffe;
return 0xffff;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_data_register_read: "
"no such register: 0x%02x\n", reg);
#endif
return 0xffff;
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,550 | static void tsc2102_data_register_write(
TSC210xState *s, int reg, uint16_t value)
{
switch (reg) {
case 0x00: /* X */
case 0x01: /* Y */
case 0x02: /* Z1 */
case 0x03: /* Z2 */
case 0x05: /* BAT1 */
case 0x06: /* BAT2 */
case 0x07: /* AUX1 */
case 0x08: /* AUX2 */
case 0x09: /* TEMP1 */
case 0x0a: /* TEMP2 */
return;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_data_register_write: "
"no such register: 0x%02x\n", reg);
#endif
}
}
| Exec Code Overflow | 0 | static void tsc2102_data_register_write(
TSC210xState *s, int reg, uint16_t value)
{
switch (reg) {
case 0x00: /* X */
case 0x01: /* Y */
case 0x02: /* Z1 */
case 0x03: /* Z2 */
case 0x05: /* BAT1 */
case 0x06: /* BAT2 */
case 0x07: /* AUX1 */
case 0x08: /* AUX2 */
case 0x09: /* TEMP1 */
case 0x0a: /* TEMP2 */
return;
default:
#ifdef TSC_VERBOSE
fprintf(stderr, "tsc2102_data_register_write: "
"no such register: 0x%02x\n", reg);
#endif
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,551 | static void tsc210x_audio_out_cb(TSC210xState *s, int free_b)
{
if (s->codec.out.len >= free_b) {
tsc210x_out_flush(s, free_b);
return;
}
s->codec.out.size = MIN(free_b, 16384);
qemu_irq_raise(s->codec.tx_start);
}
| Exec Code Overflow | 0 | static void tsc210x_audio_out_cb(TSC210xState *s, int free_b)
{
if (s->codec.out.len >= free_b) {
tsc210x_out_flush(s, free_b);
return;
}
s->codec.out.size = MIN(free_b, 16384);
qemu_irq_raise(s->codec.tx_start);
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,552 | static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
{
s->i2s_tx_rate = out;
s->i2s_rx_rate = in;
}
| Exec Code Overflow | 0 | static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
{
s->i2s_tx_rate = out;
s->i2s_rx_rate = in;
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,553 | static void tsc210x_i2s_swallow(TSC210xState *s)
{
if (s->dac_voice[0])
tsc210x_out_flush(s, s->codec.out.len);
else
s->codec.out.len = 0;
}
| Exec Code Overflow | 0 | static void tsc210x_i2s_swallow(TSC210xState *s)
{
if (s->dac_voice[0])
tsc210x_out_flush(s, s->codec.out.len);
else
s->codec.out.len = 0;
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,554 | void tsc210x_key_event(uWireSlave *chip, int key, int down)
{
TSC210xState *s = (TSC210xState *) chip->opaque;
if (down)
s->kb.down |= 1 << key;
else
s->kb.down &= ~(1 << key);
if (down && (s->kb.down & ~s->kb.mask) && !s->kb.intr) {
s->kb.intr = 1;
qemu_irq_lower(s->kbint);
} else if (s->kb.intr && !(s->kb.down & ~s->kb.mask) &&
!(s->kb.mode & 1)) {
s->kb.intr = 0;
qemu_irq_raise(s->kbint);
}
}
| Exec Code Overflow | 0 | void tsc210x_key_event(uWireSlave *chip, int key, int down)
{
TSC210xState *s = (TSC210xState *) chip->opaque;
if (down)
s->kb.down |= 1 << key;
else
s->kb.down &= ~(1 << key);
if (down && (s->kb.down & ~s->kb.mask) && !s->kb.intr) {
s->kb.intr = 1;
qemu_irq_lower(s->kbint);
} else if (s->kb.intr && !(s->kb.down & ~s->kb.mask) &&
!(s->kb.mode & 1)) {
s->kb.intr = 0;
qemu_irq_raise(s->kbint);
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,555 | static inline void tsc210x_out_flush(TSC210xState *s, int len)
{
uint8_t *data = s->codec.out.fifo + s->codec.out.start;
uint8_t *end = data + len;
while (data < end)
data += AUD_write(s->dac_voice[0], data, end - data) ?: (end - data);
s->codec.out.len -= len;
if (s->codec.out.len)
memmove(s->codec.out.fifo, end, s->codec.out.len);
s->codec.out.start = 0;
}
| Exec Code Overflow | 0 | static inline void tsc210x_out_flush(TSC210xState *s, int len)
{
uint8_t *data = s->codec.out.fifo + s->codec.out.start;
uint8_t *end = data + len;
while (data < end)
data += AUD_write(s->dac_voice[0], data, end - data) ?: (end - data);
s->codec.out.len -= len;
if (s->codec.out.len)
memmove(s->codec.out.fifo, end, s->codec.out.len);
s->codec.out.start = 0;
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,556 | static uint16_t tsc210x_read(TSC210xState *s)
{
uint16_t ret = 0x0000;
if (!s->command)
fprintf(stderr, "tsc210x_read: SPI underrun!\n");
switch (s->page) {
case TSC_DATA_REGISTERS_PAGE:
ret = tsc2102_data_register_read(s, s->offset);
if (!s->dav)
qemu_irq_raise(s->davint);
break;
case TSC_CONTROL_REGISTERS_PAGE:
ret = tsc2102_control_register_read(s, s->offset);
break;
case TSC_AUDIO_REGISTERS_PAGE:
ret = tsc2102_audio_register_read(s, s->offset);
break;
default:
hw_error("tsc210x_read: wrong memory page\n");
}
tsc210x_pin_update(s);
/* Allow sequential reads. */
s->offset ++;
s->state = 0;
return ret;
}
| Exec Code Overflow | 0 | static uint16_t tsc210x_read(TSC210xState *s)
{
uint16_t ret = 0x0000;
if (!s->command)
fprintf(stderr, "tsc210x_read: SPI underrun!\n");
switch (s->page) {
case TSC_DATA_REGISTERS_PAGE:
ret = tsc2102_data_register_read(s, s->offset);
if (!s->dav)
qemu_irq_raise(s->davint);
break;
case TSC_CONTROL_REGISTERS_PAGE:
ret = tsc2102_control_register_read(s, s->offset);
break;
case TSC_AUDIO_REGISTERS_PAGE:
ret = tsc2102_audio_register_read(s, s->offset);
break;
default:
hw_error("tsc210x_read: wrong memory page\n");
}
tsc210x_pin_update(s);
/* Allow sequential reads. */
s->offset ++;
s->state = 0;
return ret;
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,557 | static void tsc210x_reset(TSC210xState *s)
{
s->state = 0;
s->pin_func = 2;
s->enabled = 0;
s->busy = 0;
s->nextfunction = 0;
s->ref = 0;
s->timing = 0;
s->irq = 0;
s->dav = 0;
s->audio_ctrl1 = 0x0000;
s->audio_ctrl2 = 0x4410;
s->audio_ctrl3 = 0x0000;
s->pll[0] = 0x1004;
s->pll[1] = 0x0000;
s->pll[2] = 0x1fff;
s->volume = 0xffff;
s->dac_power = 0x8540;
s->softstep = 1;
s->volume_change = 0;
s->powerdown = 0;
s->filter_data[0x00] = 0x6be3;
s->filter_data[0x01] = 0x9666;
s->filter_data[0x02] = 0x675d;
s->filter_data[0x03] = 0x6be3;
s->filter_data[0x04] = 0x9666;
s->filter_data[0x05] = 0x675d;
s->filter_data[0x06] = 0x7d83;
s->filter_data[0x07] = 0x84ee;
s->filter_data[0x08] = 0x7d83;
s->filter_data[0x09] = 0x84ee;
s->filter_data[0x0a] = 0x6be3;
s->filter_data[0x0b] = 0x9666;
s->filter_data[0x0c] = 0x675d;
s->filter_data[0x0d] = 0x6be3;
s->filter_data[0x0e] = 0x9666;
s->filter_data[0x0f] = 0x675d;
s->filter_data[0x10] = 0x7d83;
s->filter_data[0x11] = 0x84ee;
s->filter_data[0x12] = 0x7d83;
s->filter_data[0x13] = 0x84ee;
s->i2s_tx_rate = 0;
s->i2s_rx_rate = 0;
s->kb.scan = 1;
s->kb.debounce = 0;
s->kb.mask = 0x0000;
s->kb.mode = 3;
s->kb.intr = 0;
qemu_set_irq(s->pint, !s->irq);
qemu_set_irq(s->davint, !s->dav);
qemu_irq_raise(s->kbint);
}
| Exec Code Overflow | 0 | static void tsc210x_reset(TSC210xState *s)
{
s->state = 0;
s->pin_func = 2;
s->enabled = 0;
s->busy = 0;
s->nextfunction = 0;
s->ref = 0;
s->timing = 0;
s->irq = 0;
s->dav = 0;
s->audio_ctrl1 = 0x0000;
s->audio_ctrl2 = 0x4410;
s->audio_ctrl3 = 0x0000;
s->pll[0] = 0x1004;
s->pll[1] = 0x0000;
s->pll[2] = 0x1fff;
s->volume = 0xffff;
s->dac_power = 0x8540;
s->softstep = 1;
s->volume_change = 0;
s->powerdown = 0;
s->filter_data[0x00] = 0x6be3;
s->filter_data[0x01] = 0x9666;
s->filter_data[0x02] = 0x675d;
s->filter_data[0x03] = 0x6be3;
s->filter_data[0x04] = 0x9666;
s->filter_data[0x05] = 0x675d;
s->filter_data[0x06] = 0x7d83;
s->filter_data[0x07] = 0x84ee;
s->filter_data[0x08] = 0x7d83;
s->filter_data[0x09] = 0x84ee;
s->filter_data[0x0a] = 0x6be3;
s->filter_data[0x0b] = 0x9666;
s->filter_data[0x0c] = 0x675d;
s->filter_data[0x0d] = 0x6be3;
s->filter_data[0x0e] = 0x9666;
s->filter_data[0x0f] = 0x675d;
s->filter_data[0x10] = 0x7d83;
s->filter_data[0x11] = 0x84ee;
s->filter_data[0x12] = 0x7d83;
s->filter_data[0x13] = 0x84ee;
s->i2s_tx_rate = 0;
s->i2s_rx_rate = 0;
s->kb.scan = 1;
s->kb.debounce = 0;
s->kb.mask = 0x0000;
s->kb.mode = 3;
s->kb.intr = 0;
qemu_set_irq(s->pint, !s->irq);
qemu_set_irq(s->davint, !s->dav);
qemu_irq_raise(s->kbint);
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,558 | static void tsc210x_save(QEMUFile *f, void *opaque)
{
TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int i;
qemu_put_be16(f, s->x);
qemu_put_be16(f, s->y);
qemu_put_byte(f, s->pressure);
qemu_put_byte(f, s->state);
qemu_put_byte(f, s->page);
qemu_put_byte(f, s->offset);
qemu_put_byte(f, s->command);
qemu_put_byte(f, s->irq);
qemu_put_be16s(f, &s->dav);
timer_put(f, s->timer);
qemu_put_byte(f, s->enabled);
qemu_put_byte(f, s->host_mode);
qemu_put_byte(f, s->function);
qemu_put_byte(f, s->nextfunction);
qemu_put_byte(f, s->precision);
qemu_put_byte(f, s->nextprecision);
qemu_put_byte(f, s->filter);
qemu_put_byte(f, s->pin_func);
qemu_put_byte(f, s->ref);
qemu_put_byte(f, s->timing);
qemu_put_be32(f, s->noise);
qemu_put_be16s(f, &s->audio_ctrl1);
qemu_put_be16s(f, &s->audio_ctrl2);
qemu_put_be16s(f, &s->audio_ctrl3);
qemu_put_be16s(f, &s->pll[0]);
qemu_put_be16s(f, &s->pll[1]);
qemu_put_be16s(f, &s->volume);
qemu_put_sbe64(f, (s->volume_change - now));
qemu_put_sbe64(f, (s->powerdown - now));
qemu_put_byte(f, s->softstep);
qemu_put_be16s(f, &s->dac_power);
for (i = 0; i < 0x14; i ++)
qemu_put_be16s(f, &s->filter_data[i]);
}
| Exec Code Overflow | 0 | static void tsc210x_save(QEMUFile *f, void *opaque)
{
TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
int i;
qemu_put_be16(f, s->x);
qemu_put_be16(f, s->y);
qemu_put_byte(f, s->pressure);
qemu_put_byte(f, s->state);
qemu_put_byte(f, s->page);
qemu_put_byte(f, s->offset);
qemu_put_byte(f, s->command);
qemu_put_byte(f, s->irq);
qemu_put_be16s(f, &s->dav);
timer_put(f, s->timer);
qemu_put_byte(f, s->enabled);
qemu_put_byte(f, s->host_mode);
qemu_put_byte(f, s->function);
qemu_put_byte(f, s->nextfunction);
qemu_put_byte(f, s->precision);
qemu_put_byte(f, s->nextprecision);
qemu_put_byte(f, s->filter);
qemu_put_byte(f, s->pin_func);
qemu_put_byte(f, s->ref);
qemu_put_byte(f, s->timing);
qemu_put_be32(f, s->noise);
qemu_put_be16s(f, &s->audio_ctrl1);
qemu_put_be16s(f, &s->audio_ctrl2);
qemu_put_be16s(f, &s->audio_ctrl3);
qemu_put_be16s(f, &s->pll[0]);
qemu_put_be16s(f, &s->pll[1]);
qemu_put_be16s(f, &s->volume);
qemu_put_sbe64(f, (s->volume_change - now));
qemu_put_sbe64(f, (s->powerdown - now));
qemu_put_byte(f, s->softstep);
qemu_put_be16s(f, &s->dac_power);
for (i = 0; i < 0x14; i ++)
qemu_put_be16s(f, &s->filter_data[i]);
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,559 | void tsc210x_set_transform(uWireSlave *chip,
MouseTransformInfo *info)
{
TSC210xState *s = (TSC210xState *) chip->opaque;
#if 0
int64_t ltr[8];
ltr[0] = (int64_t) info->a[1] * info->y;
ltr[1] = (int64_t) info->a[4] * info->x;
ltr[2] = (int64_t) info->a[1] * info->a[3] -
(int64_t) info->a[4] * info->a[0];
ltr[3] = (int64_t) info->a[2] * info->a[4] -
(int64_t) info->a[5] * info->a[1];
ltr[4] = (int64_t) info->a[0] * info->y;
ltr[5] = (int64_t) info->a[3] * info->x;
ltr[6] = (int64_t) info->a[4] * info->a[0] -
(int64_t) info->a[1] * info->a[3];
ltr[7] = (int64_t) info->a[2] * info->a[3] -
(int64_t) info->a[5] * info->a[0];
/* Avoid integer overflow */
s->tr[0] = ltr[0] >> 11;
s->tr[1] = ltr[1] >> 11;
s->tr[2] = muldiv64(ltr[2], 1, info->a[6]);
s->tr[3] = muldiv64(ltr[3], 1 << 4, ltr[2]);
s->tr[4] = ltr[4] >> 11;
s->tr[5] = ltr[5] >> 11;
s->tr[6] = muldiv64(ltr[6], 1, info->a[6]);
s->tr[7] = muldiv64(ltr[7], 1 << 4, ltr[6]);
#else
/* This version assumes touchscreen X & Y axis are parallel or
* perpendicular to LCD's X & Y axis in some way. */
if (abs(info->a[0]) > abs(info->a[1])) {
s->tr[0] = 0;
s->tr[1] = -info->a[6] * info->x;
s->tr[2] = info->a[0];
s->tr[3] = -info->a[2] / info->a[0];
s->tr[4] = info->a[6] * info->y;
s->tr[5] = 0;
s->tr[6] = info->a[4];
s->tr[7] = -info->a[5] / info->a[4];
} else {
s->tr[0] = info->a[6] * info->y;
s->tr[1] = 0;
s->tr[2] = info->a[1];
s->tr[3] = -info->a[2] / info->a[1];
s->tr[4] = 0;
s->tr[5] = -info->a[6] * info->x;
s->tr[6] = info->a[3];
s->tr[7] = -info->a[5] / info->a[3];
}
s->tr[0] >>= 11;
s->tr[1] >>= 11;
s->tr[3] <<= 4;
s->tr[4] >>= 11;
s->tr[5] >>= 11;
s->tr[7] <<= 4;
#endif
}
| Exec Code Overflow | 0 | void tsc210x_set_transform(uWireSlave *chip,
MouseTransformInfo *info)
{
TSC210xState *s = (TSC210xState *) chip->opaque;
#if 0
int64_t ltr[8];
ltr[0] = (int64_t) info->a[1] * info->y;
ltr[1] = (int64_t) info->a[4] * info->x;
ltr[2] = (int64_t) info->a[1] * info->a[3] -
(int64_t) info->a[4] * info->a[0];
ltr[3] = (int64_t) info->a[2] * info->a[4] -
(int64_t) info->a[5] * info->a[1];
ltr[4] = (int64_t) info->a[0] * info->y;
ltr[5] = (int64_t) info->a[3] * info->x;
ltr[6] = (int64_t) info->a[4] * info->a[0] -
(int64_t) info->a[1] * info->a[3];
ltr[7] = (int64_t) info->a[2] * info->a[3] -
(int64_t) info->a[5] * info->a[0];
/* Avoid integer overflow */
s->tr[0] = ltr[0] >> 11;
s->tr[1] = ltr[1] >> 11;
s->tr[2] = muldiv64(ltr[2], 1, info->a[6]);
s->tr[3] = muldiv64(ltr[3], 1 << 4, ltr[2]);
s->tr[4] = ltr[4] >> 11;
s->tr[5] = ltr[5] >> 11;
s->tr[6] = muldiv64(ltr[6], 1, info->a[6]);
s->tr[7] = muldiv64(ltr[7], 1 << 4, ltr[6]);
#else
/* This version assumes touchscreen X & Y axis are parallel or
* perpendicular to LCD's X & Y axis in some way. */
if (abs(info->a[0]) > abs(info->a[1])) {
s->tr[0] = 0;
s->tr[1] = -info->a[6] * info->x;
s->tr[2] = info->a[0];
s->tr[3] = -info->a[2] / info->a[0];
s->tr[4] = info->a[6] * info->y;
s->tr[5] = 0;
s->tr[6] = info->a[4];
s->tr[7] = -info->a[5] / info->a[4];
} else {
s->tr[0] = info->a[6] * info->y;
s->tr[1] = 0;
s->tr[2] = info->a[1];
s->tr[3] = -info->a[2] / info->a[1];
s->tr[4] = 0;
s->tr[5] = -info->a[6] * info->x;
s->tr[6] = info->a[3];
s->tr[7] = -info->a[5] / info->a[3];
}
s->tr[0] >>= 11;
s->tr[1] >>= 11;
s->tr[3] <<= 4;
s->tr[4] >>= 11;
s->tr[5] >>= 11;
s->tr[7] <<= 4;
#endif
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,560 | static void tsc210x_timer_tick(void *opaque)
{
TSC210xState *s = opaque;
/* Timer ticked -- a set of conversions has been finished. */
if (!s->busy)
return;
s->busy = 0;
s->dav |= mode_regs[s->function];
tsc210x_pin_update(s);
qemu_irq_lower(s->davint);
}
| Exec Code Overflow | 0 | static void tsc210x_timer_tick(void *opaque)
{
TSC210xState *s = opaque;
/* Timer ticked -- a set of conversions has been finished. */
if (!s->busy)
return;
s->busy = 0;
s->dav |= mode_regs[s->function];
tsc210x_pin_update(s);
qemu_irq_lower(s->davint);
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,561 | uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
{
TSC210xState *s = opaque;
uint32_t ret = 0;
if (len != 16)
hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
/* TODO: sequential reads etc - how do we make sure the host doesn't
* unintentionally read out a conversion result from a register while
* transmitting the command word of the next command? */
if (!value || (s->state && s->command))
ret = tsc210x_read(s);
if (value || (s->state && !s->command))
tsc210x_write(s, value);
return ret;
}
| Exec Code Overflow | 0 | uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
{
TSC210xState *s = opaque;
uint32_t ret = 0;
if (len != 16)
hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
/* TODO: sequential reads etc - how do we make sure the host doesn't
* unintentionally read out a conversion result from a register while
* transmitting the command word of the next command? */
if (!value || (s->state && s->command))
ret = tsc210x_read(s);
if (value || (s->state && !s->command))
tsc210x_write(s, value);
return ret;
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,562 | static void tsc210x_write(TSC210xState *s, uint16_t value)
{
/*
* This is a two-state state machine for reading
* command and data every second time.
*/
if (!s->state) {
s->command = value >> 15;
s->page = (value >> 11) & 0x0f;
s->offset = (value >> 5) & 0x3f;
s->state = 1;
} else {
if (s->command)
fprintf(stderr, "tsc210x_write: SPI overrun!\n");
else
switch (s->page) {
case TSC_DATA_REGISTERS_PAGE:
tsc2102_data_register_write(s, s->offset, value);
break;
case TSC_CONTROL_REGISTERS_PAGE:
tsc2102_control_register_write(s, s->offset, value);
break;
case TSC_AUDIO_REGISTERS_PAGE:
tsc2102_audio_register_write(s, s->offset, value);
break;
default:
hw_error("tsc210x_write: wrong memory page\n");
}
tsc210x_pin_update(s);
s->state = 0;
}
}
| Exec Code Overflow | 0 | static void tsc210x_write(TSC210xState *s, uint16_t value)
{
/*
* This is a two-state state machine for reading
* command and data every second time.
*/
if (!s->state) {
s->command = value >> 15;
s->page = (value >> 11) & 0x0f;
s->offset = (value >> 5) & 0x3f;
s->state = 1;
} else {
if (s->command)
fprintf(stderr, "tsc210x_write: SPI overrun!\n");
else
switch (s->page) {
case TSC_DATA_REGISTERS_PAGE:
tsc2102_data_register_write(s, s->offset, value);
break;
case TSC_CONTROL_REGISTERS_PAGE:
tsc2102_control_register_write(s, s->offset, value);
break;
case TSC_AUDIO_REGISTERS_PAGE:
tsc2102_audio_register_write(s, s->offset, value);
break;
default:
hw_error("tsc210x_write: wrong memory page\n");
}
tsc210x_pin_update(s);
s->state = 0;
}
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,563 | uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
{
TSC210xState *s;
s = (TSC210xState *)
g_malloc0(sizeof(TSC210xState));
memset(s, 0, sizeof(TSC210xState));
s->x = 400;
s->y = 240;
s->pressure = 0;
s->precision = s->nextprecision = 0;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc210x_timer_tick, s);
s->pint = penirq;
s->kbint = kbirq;
s->davint = dav;
s->model = 0x2301;
s->name = "tsc2301";
s->tr[0] = 0;
s->tr[1] = 1;
s->tr[2] = 1;
s->tr[3] = 0;
s->tr[4] = 1;
s->tr[5] = 0;
s->tr[6] = 1;
s->tr[7] = 0;
s->chip.opaque = s;
s->chip.send = (void *) tsc210x_write;
s->chip.receive = (void *) tsc210x_read;
s->codec.opaque = s;
s->codec.tx_swallow = (void *) tsc210x_i2s_swallow;
s->codec.set_rate = (void *) tsc210x_i2s_set_rate;
s->codec.in.fifo = s->in_fifo;
s->codec.out.fifo = s->out_fifo;
tsc210x_reset(s);
qemu_add_mouse_event_handler(tsc210x_touchscreen_event, s, 1,
"QEMU TSC2301-driven Touchscreen");
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
register_savevm(NULL, s->name, -1, 0, tsc210x_save, tsc210x_load, s);
return &s->chip;
}
| Exec Code Overflow | 0 | uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
{
TSC210xState *s;
s = (TSC210xState *)
g_malloc0(sizeof(TSC210xState));
memset(s, 0, sizeof(TSC210xState));
s->x = 400;
s->y = 240;
s->pressure = 0;
s->precision = s->nextprecision = 0;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tsc210x_timer_tick, s);
s->pint = penirq;
s->kbint = kbirq;
s->davint = dav;
s->model = 0x2301;
s->name = "tsc2301";
s->tr[0] = 0;
s->tr[1] = 1;
s->tr[2] = 1;
s->tr[3] = 0;
s->tr[4] = 1;
s->tr[5] = 0;
s->tr[6] = 1;
s->tr[7] = 0;
s->chip.opaque = s;
s->chip.send = (void *) tsc210x_write;
s->chip.receive = (void *) tsc210x_read;
s->codec.opaque = s;
s->codec.tx_swallow = (void *) tsc210x_i2s_swallow;
s->codec.set_rate = (void *) tsc210x_i2s_set_rate;
s->codec.in.fifo = s->in_fifo;
s->codec.out.fifo = s->out_fifo;
tsc210x_reset(s);
qemu_add_mouse_event_handler(tsc210x_touchscreen_event, s, 1,
"QEMU TSC2301-driven Touchscreen");
AUD_register_card(s->name, &s->card);
qemu_register_reset((void *) tsc210x_reset, s);
register_savevm(NULL, s->name, -1, 0, tsc210x_save, tsc210x_load, s);
return &s->chip;
}
| @@ -1070,9 +1070,21 @@ static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
s->enabled = qemu_get_byte(f);
s->host_mode = qemu_get_byte(f);
s->function = qemu_get_byte(f);
+ if (s->function < 0 || s->function >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->nextfunction = qemu_get_byte(f);
+ if (s->nextfunction < 0 || s->nextfunction >= ARRAY_SIZE(mode_regs)) {
+ return -EINVAL;
+ }
s->precision = qemu_get_byte(f);
+ if (s->precision < 0 || s->precision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->nextprecision = qemu_get_byte(f);
+ if (s->nextprecision < 0 || s->nextprecision >= ARRAY_SIZE(resolution)) {
+ return -EINVAL;
+ }
s->filter = qemu_get_byte(f);
s->pin_func = qemu_get_byte(f);
s->ref = qemu_get_byte(f); | CWE-119 | null | null |
12,564 | static void ssd03232_register_types(void)
{
type_register_static(&ssd0323_info);
}
| DoS Exec Code Overflow Mem. Corr. | 0 | static void ssd03232_register_types(void)
{
type_register_static(&ssd0323_info);
}
| @@ -312,18 +312,42 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return -EINVAL;
s->cmd_len = qemu_get_be32(f);
+ if (s->cmd_len < 0 || s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
+ return -EINVAL;
+ }
s->cmd = qemu_get_be32(f);
for (i = 0; i < 8; i++)
s->cmd_data[i] = qemu_get_be32(f);
s->row = qemu_get_be32(f);
+ if (s->row < 0 || s->row >= 80) {
+ return -EINVAL;
+ }
s->row_start = qemu_get_be32(f);
+ if (s->row_start < 0 || s->row_start >= 80) {
+ return -EINVAL;
+ }
s->row_end = qemu_get_be32(f);
+ if (s->row_end < 0 || s->row_end >= 80) {
+ return -EINVAL;
+ }
s->col = qemu_get_be32(f);
+ if (s->col < 0 || s->col >= 64) {
+ return -EINVAL;
+ }
s->col_start = qemu_get_be32(f);
+ if (s->col_start < 0 || s->col_start >= 64) {
+ return -EINVAL;
+ }
s->col_end = qemu_get_be32(f);
+ if (s->col_end < 0 || s->col_end >= 64) {
+ return -EINVAL;
+ }
s->redraw = qemu_get_be32(f);
s->remap = qemu_get_be32(f);
s->mode = qemu_get_be32(f);
+ if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
+ return -EINVAL;
+ }
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
ss->cs = qemu_get_be32(f); | CWE-119 | null | null |
12,565 | static void ssd0323_cd(void *opaque, int n, int level)
{
ssd0323_state *s = (ssd0323_state *)opaque;
DPRINTF("%s mode\n", level ? "Data" : "Command");
s->mode = level ? SSD0323_DATA : SSD0323_CMD;
}
| DoS Exec Code Overflow Mem. Corr. | 0 | static void ssd0323_cd(void *opaque, int n, int level)
{
ssd0323_state *s = (ssd0323_state *)opaque;
DPRINTF("%s mode\n", level ? "Data" : "Command");
s->mode = level ? SSD0323_DATA : SSD0323_CMD;
}
| @@ -312,18 +312,42 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return -EINVAL;
s->cmd_len = qemu_get_be32(f);
+ if (s->cmd_len < 0 || s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
+ return -EINVAL;
+ }
s->cmd = qemu_get_be32(f);
for (i = 0; i < 8; i++)
s->cmd_data[i] = qemu_get_be32(f);
s->row = qemu_get_be32(f);
+ if (s->row < 0 || s->row >= 80) {
+ return -EINVAL;
+ }
s->row_start = qemu_get_be32(f);
+ if (s->row_start < 0 || s->row_start >= 80) {
+ return -EINVAL;
+ }
s->row_end = qemu_get_be32(f);
+ if (s->row_end < 0 || s->row_end >= 80) {
+ return -EINVAL;
+ }
s->col = qemu_get_be32(f);
+ if (s->col < 0 || s->col >= 64) {
+ return -EINVAL;
+ }
s->col_start = qemu_get_be32(f);
+ if (s->col_start < 0 || s->col_start >= 64) {
+ return -EINVAL;
+ }
s->col_end = qemu_get_be32(f);
+ if (s->col_end < 0 || s->col_end >= 64) {
+ return -EINVAL;
+ }
s->redraw = qemu_get_be32(f);
s->remap = qemu_get_be32(f);
s->mode = qemu_get_be32(f);
+ if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
+ return -EINVAL;
+ }
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
ss->cs = qemu_get_be32(f); | CWE-119 | null | null |
12,566 | static void ssd0323_invalidate_display(void * opaque)
{
ssd0323_state *s = (ssd0323_state *)opaque;
s->redraw = 1;
}
| DoS Exec Code Overflow Mem. Corr. | 0 | static void ssd0323_invalidate_display(void * opaque)
{
ssd0323_state *s = (ssd0323_state *)opaque;
s->redraw = 1;
}
| @@ -312,18 +312,42 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return -EINVAL;
s->cmd_len = qemu_get_be32(f);
+ if (s->cmd_len < 0 || s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
+ return -EINVAL;
+ }
s->cmd = qemu_get_be32(f);
for (i = 0; i < 8; i++)
s->cmd_data[i] = qemu_get_be32(f);
s->row = qemu_get_be32(f);
+ if (s->row < 0 || s->row >= 80) {
+ return -EINVAL;
+ }
s->row_start = qemu_get_be32(f);
+ if (s->row_start < 0 || s->row_start >= 80) {
+ return -EINVAL;
+ }
s->row_end = qemu_get_be32(f);
+ if (s->row_end < 0 || s->row_end >= 80) {
+ return -EINVAL;
+ }
s->col = qemu_get_be32(f);
+ if (s->col < 0 || s->col >= 64) {
+ return -EINVAL;
+ }
s->col_start = qemu_get_be32(f);
+ if (s->col_start < 0 || s->col_start >= 64) {
+ return -EINVAL;
+ }
s->col_end = qemu_get_be32(f);
+ if (s->col_end < 0 || s->col_end >= 64) {
+ return -EINVAL;
+ }
s->redraw = qemu_get_be32(f);
s->remap = qemu_get_be32(f);
s->mode = qemu_get_be32(f);
+ if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
+ return -EINVAL;
+ }
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
ss->cs = qemu_get_be32(f); | CWE-119 | null | null |
12,567 | static void ssd0323_save(QEMUFile *f, void *opaque)
{
SSISlave *ss = SSI_SLAVE(opaque);
ssd0323_state *s = (ssd0323_state *)opaque;
int i;
qemu_put_be32(f, s->cmd_len);
qemu_put_be32(f, s->cmd);
for (i = 0; i < 8; i++)
qemu_put_be32(f, s->cmd_data[i]);
qemu_put_be32(f, s->row);
qemu_put_be32(f, s->row_start);
qemu_put_be32(f, s->row_end);
qemu_put_be32(f, s->col);
qemu_put_be32(f, s->col_start);
qemu_put_be32(f, s->col_end);
qemu_put_be32(f, s->redraw);
qemu_put_be32(f, s->remap);
qemu_put_be32(f, s->mode);
qemu_put_buffer(f, s->framebuffer, sizeof(s->framebuffer));
qemu_put_be32(f, ss->cs);
}
| DoS Exec Code Overflow Mem. Corr. | 0 | static void ssd0323_save(QEMUFile *f, void *opaque)
{
SSISlave *ss = SSI_SLAVE(opaque);
ssd0323_state *s = (ssd0323_state *)opaque;
int i;
qemu_put_be32(f, s->cmd_len);
qemu_put_be32(f, s->cmd);
for (i = 0; i < 8; i++)
qemu_put_be32(f, s->cmd_data[i]);
qemu_put_be32(f, s->row);
qemu_put_be32(f, s->row_start);
qemu_put_be32(f, s->row_end);
qemu_put_be32(f, s->col);
qemu_put_be32(f, s->col_start);
qemu_put_be32(f, s->col_end);
qemu_put_be32(f, s->redraw);
qemu_put_be32(f, s->remap);
qemu_put_be32(f, s->mode);
qemu_put_buffer(f, s->framebuffer, sizeof(s->framebuffer));
qemu_put_be32(f, ss->cs);
}
| @@ -312,18 +312,42 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return -EINVAL;
s->cmd_len = qemu_get_be32(f);
+ if (s->cmd_len < 0 || s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
+ return -EINVAL;
+ }
s->cmd = qemu_get_be32(f);
for (i = 0; i < 8; i++)
s->cmd_data[i] = qemu_get_be32(f);
s->row = qemu_get_be32(f);
+ if (s->row < 0 || s->row >= 80) {
+ return -EINVAL;
+ }
s->row_start = qemu_get_be32(f);
+ if (s->row_start < 0 || s->row_start >= 80) {
+ return -EINVAL;
+ }
s->row_end = qemu_get_be32(f);
+ if (s->row_end < 0 || s->row_end >= 80) {
+ return -EINVAL;
+ }
s->col = qemu_get_be32(f);
+ if (s->col < 0 || s->col >= 64) {
+ return -EINVAL;
+ }
s->col_start = qemu_get_be32(f);
+ if (s->col_start < 0 || s->col_start >= 64) {
+ return -EINVAL;
+ }
s->col_end = qemu_get_be32(f);
+ if (s->col_end < 0 || s->col_end >= 64) {
+ return -EINVAL;
+ }
s->redraw = qemu_get_be32(f);
s->remap = qemu_get_be32(f);
s->mode = qemu_get_be32(f);
+ if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
+ return -EINVAL;
+ }
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
ss->cs = qemu_get_be32(f); | CWE-119 | null | null |
12,568 | static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
{
ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
switch (s->mode) {
case SSD0323_DATA:
DPRINTF("data 0x%02x\n", data);
s->framebuffer[s->col + s->row * 64] = data;
if (s->remap & REMAP_VERTICAL) {
s->row++;
if (s->row > s->row_end) {
s->row = s->row_start;
s->col++;
}
if (s->col > s->col_end) {
s->col = s->col_start;
}
} else {
s->col++;
if (s->col > s->col_end) {
s->row++;
s->col = s->col_start;
}
if (s->row > s->row_end) {
s->row = s->row_start;
}
}
s->redraw = 1;
break;
case SSD0323_CMD:
DPRINTF("cmd 0x%02x\n", data);
if (s->cmd_len == 0) {
s->cmd = data;
} else {
s->cmd_data[s->cmd_len - 1] = data;
}
s->cmd_len++;
switch (s->cmd) {
#define DATA(x) if (s->cmd_len <= (x)) return 0
case 0x15: /* Set column. */
DATA(2);
s->col = s->col_start = s->cmd_data[0] % 64;
s->col_end = s->cmd_data[1] % 64;
break;
case 0x75: /* Set row. */
DATA(2);
s->row = s->row_start = s->cmd_data[0] % 80;
s->row_end = s->cmd_data[1] % 80;
break;
case 0x81: /* Set contrast */
DATA(1);
break;
case 0x84: case 0x85: case 0x86: /* Max current. */
DATA(0);
break;
case 0xa0: /* Set remapping. */
/* FIXME: Implement this. */
DATA(1);
s->remap = s->cmd_data[0];
break;
case 0xa1: /* Set display start line. */
case 0xa2: /* Set display offset. */
/* FIXME: Implement these. */
DATA(1);
break;
case 0xa4: /* Normal mode. */
case 0xa5: /* All on. */
case 0xa6: /* All off. */
case 0xa7: /* Inverse. */
/* FIXME: Implement these. */
DATA(0);
break;
case 0xa8: /* Set multiplex ratio. */
case 0xad: /* Set DC-DC converter. */
DATA(1);
/* Ignored. Don't care. */
break;
case 0xae: /* Display off. */
case 0xaf: /* Display on. */
DATA(0);
/* TODO: Implement power control. */
break;
case 0xb1: /* Set phase length. */
case 0xb2: /* Set row period. */
case 0xb3: /* Set clock rate. */
case 0xbc: /* Set precharge. */
case 0xbe: /* Set VCOMH. */
case 0xbf: /* Set segment low. */
DATA(1);
/* Ignored. Don't care. */
break;
case 0xb8: /* Set grey scale table. */
/* FIXME: Implement this. */
DATA(8);
break;
case 0xe3: /* NOP. */
DATA(0);
break;
case 0xff: /* Nasty hack because we don't handle chip selects
properly. */
break;
default:
BADF("Unknown command: 0x%x\n", data);
}
s->cmd_len = 0;
return 0;
}
return 0;
}
| DoS Exec Code Overflow Mem. Corr. | 0 | static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
{
ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
switch (s->mode) {
case SSD0323_DATA:
DPRINTF("data 0x%02x\n", data);
s->framebuffer[s->col + s->row * 64] = data;
if (s->remap & REMAP_VERTICAL) {
s->row++;
if (s->row > s->row_end) {
s->row = s->row_start;
s->col++;
}
if (s->col > s->col_end) {
s->col = s->col_start;
}
} else {
s->col++;
if (s->col > s->col_end) {
s->row++;
s->col = s->col_start;
}
if (s->row > s->row_end) {
s->row = s->row_start;
}
}
s->redraw = 1;
break;
case SSD0323_CMD:
DPRINTF("cmd 0x%02x\n", data);
if (s->cmd_len == 0) {
s->cmd = data;
} else {
s->cmd_data[s->cmd_len - 1] = data;
}
s->cmd_len++;
switch (s->cmd) {
#define DATA(x) if (s->cmd_len <= (x)) return 0
case 0x15: /* Set column. */
DATA(2);
s->col = s->col_start = s->cmd_data[0] % 64;
s->col_end = s->cmd_data[1] % 64;
break;
case 0x75: /* Set row. */
DATA(2);
s->row = s->row_start = s->cmd_data[0] % 80;
s->row_end = s->cmd_data[1] % 80;
break;
case 0x81: /* Set contrast */
DATA(1);
break;
case 0x84: case 0x85: case 0x86: /* Max current. */
DATA(0);
break;
case 0xa0: /* Set remapping. */
/* FIXME: Implement this. */
DATA(1);
s->remap = s->cmd_data[0];
break;
case 0xa1: /* Set display start line. */
case 0xa2: /* Set display offset. */
/* FIXME: Implement these. */
DATA(1);
break;
case 0xa4: /* Normal mode. */
case 0xa5: /* All on. */
case 0xa6: /* All off. */
case 0xa7: /* Inverse. */
/* FIXME: Implement these. */
DATA(0);
break;
case 0xa8: /* Set multiplex ratio. */
case 0xad: /* Set DC-DC converter. */
DATA(1);
/* Ignored. Don't care. */
break;
case 0xae: /* Display off. */
case 0xaf: /* Display on. */
DATA(0);
/* TODO: Implement power control. */
break;
case 0xb1: /* Set phase length. */
case 0xb2: /* Set row period. */
case 0xb3: /* Set clock rate. */
case 0xbc: /* Set precharge. */
case 0xbe: /* Set VCOMH. */
case 0xbf: /* Set segment low. */
DATA(1);
/* Ignored. Don't care. */
break;
case 0xb8: /* Set grey scale table. */
/* FIXME: Implement this. */
DATA(8);
break;
case 0xe3: /* NOP. */
DATA(0);
break;
case 0xff: /* Nasty hack because we don't handle chip selects
properly. */
break;
default:
BADF("Unknown command: 0x%x\n", data);
}
s->cmd_len = 0;
return 0;
}
return 0;
}
| @@ -312,18 +312,42 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return -EINVAL;
s->cmd_len = qemu_get_be32(f);
+ if (s->cmd_len < 0 || s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
+ return -EINVAL;
+ }
s->cmd = qemu_get_be32(f);
for (i = 0; i < 8; i++)
s->cmd_data[i] = qemu_get_be32(f);
s->row = qemu_get_be32(f);
+ if (s->row < 0 || s->row >= 80) {
+ return -EINVAL;
+ }
s->row_start = qemu_get_be32(f);
+ if (s->row_start < 0 || s->row_start >= 80) {
+ return -EINVAL;
+ }
s->row_end = qemu_get_be32(f);
+ if (s->row_end < 0 || s->row_end >= 80) {
+ return -EINVAL;
+ }
s->col = qemu_get_be32(f);
+ if (s->col < 0 || s->col >= 64) {
+ return -EINVAL;
+ }
s->col_start = qemu_get_be32(f);
+ if (s->col_start < 0 || s->col_start >= 64) {
+ return -EINVAL;
+ }
s->col_end = qemu_get_be32(f);
+ if (s->col_end < 0 || s->col_end >= 64) {
+ return -EINVAL;
+ }
s->redraw = qemu_get_be32(f);
s->remap = qemu_get_be32(f);
s->mode = qemu_get_be32(f);
+ if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
+ return -EINVAL;
+ }
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
ss->cs = qemu_get_be32(f); | CWE-119 | null | null |
12,569 | static void ssd0323_update_display(void *opaque)
{
ssd0323_state *s = (ssd0323_state *)opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *dest;
uint8_t *src;
int x;
int y;
int i;
int line;
char *colors[16];
char colortab[MAGNIFY * 64];
char *p;
int dest_width;
if (!s->redraw)
return;
switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 15:
dest_width = 2;
break;
case 16:
dest_width = 2;
break;
case 24:
dest_width = 3;
break;
case 32:
dest_width = 4;
break;
default:
BADF("Bad color depth\n");
return;
}
p = colortab;
for (i = 0; i < 16; i++) {
int n;
colors[i] = p;
switch (surface_bits_per_pixel(surface)) {
case 15:
n = i * 2 + (i >> 3);
p[0] = n | (n << 5);
p[1] = (n << 2) | (n >> 3);
break;
case 16:
n = i * 2 + (i >> 3);
p[0] = n | (n << 6) | ((n << 1) & 0x20);
p[1] = (n << 3) | (n >> 2);
break;
case 24:
case 32:
n = (i << 4) | i;
p[0] = p[1] = p[2] = n;
break;
default:
BADF("Bad color depth\n");
return;
}
p += dest_width;
}
/* TODO: Implement row/column remapping. */
dest = surface_data(surface);
for (y = 0; y < 64; y++) {
line = y;
src = s->framebuffer + 64 * line;
for (x = 0; x < 64; x++) {
int val;
val = *src >> 4;
for (i = 0; i < MAGNIFY; i++) {
memcpy(dest, colors[val], dest_width);
dest += dest_width;
}
val = *src & 0xf;
for (i = 0; i < MAGNIFY; i++) {
memcpy(dest, colors[val], dest_width);
dest += dest_width;
}
src++;
}
for (i = 1; i < MAGNIFY; i++) {
memcpy(dest, dest - dest_width * MAGNIFY * 128,
dest_width * 128 * MAGNIFY);
dest += dest_width * 128 * MAGNIFY;
}
}
s->redraw = 0;
dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
}
| DoS Exec Code Overflow Mem. Corr. | 0 | static void ssd0323_update_display(void *opaque)
{
ssd0323_state *s = (ssd0323_state *)opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
uint8_t *dest;
uint8_t *src;
int x;
int y;
int i;
int line;
char *colors[16];
char colortab[MAGNIFY * 64];
char *p;
int dest_width;
if (!s->redraw)
return;
switch (surface_bits_per_pixel(surface)) {
case 0:
return;
case 15:
dest_width = 2;
break;
case 16:
dest_width = 2;
break;
case 24:
dest_width = 3;
break;
case 32:
dest_width = 4;
break;
default:
BADF("Bad color depth\n");
return;
}
p = colortab;
for (i = 0; i < 16; i++) {
int n;
colors[i] = p;
switch (surface_bits_per_pixel(surface)) {
case 15:
n = i * 2 + (i >> 3);
p[0] = n | (n << 5);
p[1] = (n << 2) | (n >> 3);
break;
case 16:
n = i * 2 + (i >> 3);
p[0] = n | (n << 6) | ((n << 1) & 0x20);
p[1] = (n << 3) | (n >> 2);
break;
case 24:
case 32:
n = (i << 4) | i;
p[0] = p[1] = p[2] = n;
break;
default:
BADF("Bad color depth\n");
return;
}
p += dest_width;
}
/* TODO: Implement row/column remapping. */
dest = surface_data(surface);
for (y = 0; y < 64; y++) {
line = y;
src = s->framebuffer + 64 * line;
for (x = 0; x < 64; x++) {
int val;
val = *src >> 4;
for (i = 0; i < MAGNIFY; i++) {
memcpy(dest, colors[val], dest_width);
dest += dest_width;
}
val = *src & 0xf;
for (i = 0; i < MAGNIFY; i++) {
memcpy(dest, colors[val], dest_width);
dest += dest_width;
}
src++;
}
for (i = 1; i < MAGNIFY; i++) {
memcpy(dest, dest - dest_width * MAGNIFY * 128,
dest_width * 128 * MAGNIFY);
dest += dest_width * 128 * MAGNIFY;
}
}
s->redraw = 0;
dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
}
| @@ -312,18 +312,42 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return -EINVAL;
s->cmd_len = qemu_get_be32(f);
+ if (s->cmd_len < 0 || s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
+ return -EINVAL;
+ }
s->cmd = qemu_get_be32(f);
for (i = 0; i < 8; i++)
s->cmd_data[i] = qemu_get_be32(f);
s->row = qemu_get_be32(f);
+ if (s->row < 0 || s->row >= 80) {
+ return -EINVAL;
+ }
s->row_start = qemu_get_be32(f);
+ if (s->row_start < 0 || s->row_start >= 80) {
+ return -EINVAL;
+ }
s->row_end = qemu_get_be32(f);
+ if (s->row_end < 0 || s->row_end >= 80) {
+ return -EINVAL;
+ }
s->col = qemu_get_be32(f);
+ if (s->col < 0 || s->col >= 64) {
+ return -EINVAL;
+ }
s->col_start = qemu_get_be32(f);
+ if (s->col_start < 0 || s->col_start >= 64) {
+ return -EINVAL;
+ }
s->col_end = qemu_get_be32(f);
+ if (s->col_end < 0 || s->col_end >= 64) {
+ return -EINVAL;
+ }
s->redraw = qemu_get_be32(f);
s->remap = qemu_get_be32(f);
s->mode = qemu_get_be32(f);
+ if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
+ return -EINVAL;
+ }
qemu_get_buffer(f, s->framebuffer, sizeof(s->framebuffer));
ss->cs = qemu_get_be32(f); | CWE-119 | null | null |
12,570 | static void ssi_sd_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
k->init = ssi_sd_init;
k->transfer = ssi_sd_transfer;
k->cs_polarity = SSI_CS_LOW;
}
| Exec Code | 0 | static void ssi_sd_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
k->init = ssi_sd_init;
k->transfer = ssi_sd_transfer;
k->cs_polarity = SSI_CS_LOW;
}
| @@ -230,8 +230,17 @@ static int ssi_sd_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 5; i++)
s->response[i] = qemu_get_be32(f);
s->arglen = qemu_get_be32(f);
+ if (s->mode == SSI_SD_CMDARG &&
+ (s->arglen < 0 || s->arglen >= ARRAY_SIZE(s->cmdarg))) {
+ return -EINVAL;
+ }
s->response_pos = qemu_get_be32(f);
s->stopping = qemu_get_be32(f);
+ if (s->mode == SSI_SD_RESPONSE &&
+ (s->response_pos < 0 || s->response_pos >= ARRAY_SIZE(s->response) ||
+ (!s->stopping && s->arglen > ARRAY_SIZE(s->response)))) {
+ return -EINVAL;
+ }
ss->cs = qemu_get_be32(f); | CWE-94 | null | null |
12,571 | static void ssi_sd_register_types(void)
{
type_register_static(&ssi_sd_info);
}
| Exec Code | 0 | static void ssi_sd_register_types(void)
{
type_register_static(&ssi_sd_info);
}
| @@ -230,8 +230,17 @@ static int ssi_sd_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 5; i++)
s->response[i] = qemu_get_be32(f);
s->arglen = qemu_get_be32(f);
+ if (s->mode == SSI_SD_CMDARG &&
+ (s->arglen < 0 || s->arglen >= ARRAY_SIZE(s->cmdarg))) {
+ return -EINVAL;
+ }
s->response_pos = qemu_get_be32(f);
s->stopping = qemu_get_be32(f);
+ if (s->mode == SSI_SD_RESPONSE &&
+ (s->response_pos < 0 || s->response_pos >= ARRAY_SIZE(s->response) ||
+ (!s->stopping && s->arglen > ARRAY_SIZE(s->response)))) {
+ return -EINVAL;
+ }
ss->cs = qemu_get_be32(f); | CWE-94 | null | null |
12,572 | static void ssi_sd_save(QEMUFile *f, void *opaque)
{
SSISlave *ss = SSI_SLAVE(opaque);
ssi_sd_state *s = (ssi_sd_state *)opaque;
int i;
qemu_put_be32(f, s->mode);
qemu_put_be32(f, s->cmd);
for (i = 0; i < 4; i++)
qemu_put_be32(f, s->cmdarg[i]);
for (i = 0; i < 5; i++)
qemu_put_be32(f, s->response[i]);
qemu_put_be32(f, s->arglen);
qemu_put_be32(f, s->response_pos);
qemu_put_be32(f, s->stopping);
qemu_put_be32(f, ss->cs);
}
| Exec Code | 0 | static void ssi_sd_save(QEMUFile *f, void *opaque)
{
SSISlave *ss = SSI_SLAVE(opaque);
ssi_sd_state *s = (ssi_sd_state *)opaque;
int i;
qemu_put_be32(f, s->mode);
qemu_put_be32(f, s->cmd);
for (i = 0; i < 4; i++)
qemu_put_be32(f, s->cmdarg[i]);
for (i = 0; i < 5; i++)
qemu_put_be32(f, s->response[i]);
qemu_put_be32(f, s->arglen);
qemu_put_be32(f, s->response_pos);
qemu_put_be32(f, s->stopping);
qemu_put_be32(f, ss->cs);
}
| @@ -230,8 +230,17 @@ static int ssi_sd_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 5; i++)
s->response[i] = qemu_get_be32(f);
s->arglen = qemu_get_be32(f);
+ if (s->mode == SSI_SD_CMDARG &&
+ (s->arglen < 0 || s->arglen >= ARRAY_SIZE(s->cmdarg))) {
+ return -EINVAL;
+ }
s->response_pos = qemu_get_be32(f);
s->stopping = qemu_get_be32(f);
+ if (s->mode == SSI_SD_RESPONSE &&
+ (s->response_pos < 0 || s->response_pos >= ARRAY_SIZE(s->response) ||
+ (!s->stopping && s->arglen > ARRAY_SIZE(s->response)))) {
+ return -EINVAL;
+ }
ss->cs = qemu_get_be32(f); | CWE-94 | null | null |
12,573 | static void IRQ_check(OpenPICState *opp, IRQQueue *q)
{
int irq = -1;
int next = -1;
int priority = -1;
for (;;) {
irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
if (irq == opp->max_irq) {
break;
}
DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
next = irq;
priority = IVPR_PRIORITY(opp->src[irq].ivpr);
}
}
q->next = next;
q->priority = priority;
}
| DoS Exec Code Overflow | 0 | static void IRQ_check(OpenPICState *opp, IRQQueue *q)
{
int irq = -1;
int next = -1;
int priority = -1;
for (;;) {
irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
if (irq == opp->max_irq) {
break;
}
DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
next = irq;
priority = IVPR_PRIORITY(opp->src[irq].ivpr);
}
}
q->next = next;
q->priority = priority;
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,574 | static int IRQ_get_next(OpenPICState *opp, IRQQueue *q)
{
/* XXX: optimize */
IRQ_check(opp, q);
return q->next;
}
| DoS Exec Code Overflow | 0 | static int IRQ_get_next(OpenPICState *opp, IRQQueue *q)
{
/* XXX: optimize */
IRQ_check(opp, q);
return q->next;
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,575 | static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
bool active, bool was_active)
{
IRQDest *dst;
IRQSource *src;
int priority;
dst = &opp->dst[n_CPU];
src = &opp->src[n_IRQ];
DPRINTF("%s: IRQ %d active %d was %d\n",
__func__, n_IRQ, active, was_active);
if (src->output != OPENPIC_OUTPUT_INT) {
DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
__func__, src->output, n_IRQ, active, was_active,
dst->outputs_active[src->output]);
/* On Freescale MPIC, critical interrupts ignore priority,
* IACK, EOI, etc. Before MPIC v4.1 they also ignore
* masking.
*/
if (active) {
if (!was_active && dst->outputs_active[src->output]++ == 0) {
DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
__func__, src->output, n_CPU, n_IRQ);
qemu_irq_raise(dst->irqs[src->output]);
}
} else {
if (was_active && --dst->outputs_active[src->output] == 0) {
DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
__func__, src->output, n_CPU, n_IRQ);
qemu_irq_lower(dst->irqs[src->output]);
}
}
return;
}
priority = IVPR_PRIORITY(src->ivpr);
/* Even if the interrupt doesn't have enough priority,
* it is still raised, in case ctpr is lowered later.
*/
if (active) {
IRQ_setbit(&dst->raised, n_IRQ);
} else {
IRQ_resetbit(&dst->raised, n_IRQ);
}
IRQ_check(opp, &dst->raised);
if (active && priority <= dst->ctpr) {
DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
__func__, n_IRQ, priority, dst->ctpr, n_CPU);
active = 0;
}
if (active) {
if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
priority <= dst->servicing.priority) {
DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
__func__, n_IRQ, dst->servicing.next, n_CPU);
} else {
DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
__func__, n_CPU, n_IRQ, dst->raised.next);
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
}
} else {
IRQ_get_next(opp, &dst->servicing);
if (dst->raised.priority > dst->ctpr &&
dst->raised.priority > dst->servicing.priority) {
DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
__func__, n_IRQ, dst->raised.next, dst->raised.priority,
dst->ctpr, dst->servicing.priority, n_CPU);
/* IRQ line stays asserted */
} else {
DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
__func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU);
qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
}
}
}
| DoS Exec Code Overflow | 0 | static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
bool active, bool was_active)
{
IRQDest *dst;
IRQSource *src;
int priority;
dst = &opp->dst[n_CPU];
src = &opp->src[n_IRQ];
DPRINTF("%s: IRQ %d active %d was %d\n",
__func__, n_IRQ, active, was_active);
if (src->output != OPENPIC_OUTPUT_INT) {
DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
__func__, src->output, n_IRQ, active, was_active,
dst->outputs_active[src->output]);
/* On Freescale MPIC, critical interrupts ignore priority,
* IACK, EOI, etc. Before MPIC v4.1 they also ignore
* masking.
*/
if (active) {
if (!was_active && dst->outputs_active[src->output]++ == 0) {
DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
__func__, src->output, n_CPU, n_IRQ);
qemu_irq_raise(dst->irqs[src->output]);
}
} else {
if (was_active && --dst->outputs_active[src->output] == 0) {
DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
__func__, src->output, n_CPU, n_IRQ);
qemu_irq_lower(dst->irqs[src->output]);
}
}
return;
}
priority = IVPR_PRIORITY(src->ivpr);
/* Even if the interrupt doesn't have enough priority,
* it is still raised, in case ctpr is lowered later.
*/
if (active) {
IRQ_setbit(&dst->raised, n_IRQ);
} else {
IRQ_resetbit(&dst->raised, n_IRQ);
}
IRQ_check(opp, &dst->raised);
if (active && priority <= dst->ctpr) {
DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
__func__, n_IRQ, priority, dst->ctpr, n_CPU);
active = 0;
}
if (active) {
if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
priority <= dst->servicing.priority) {
DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
__func__, n_IRQ, dst->servicing.next, n_CPU);
} else {
DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
__func__, n_CPU, n_IRQ, dst->raised.next);
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
}
} else {
IRQ_get_next(opp, &dst->servicing);
if (dst->raised.priority > dst->ctpr &&
dst->raised.priority > dst->servicing.priority) {
DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
__func__, n_IRQ, dst->raised.next, dst->raised.priority,
dst->ctpr, dst->servicing.priority, n_CPU);
/* IRQ line stays asserted */
} else {
DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
__func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU);
qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
}
}
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,576 | static inline void IRQ_setbit(IRQQueue *q, int n_IRQ)
{
set_bit(n_IRQ, q->queue);
}
| DoS Exec Code Overflow | 0 | static inline void IRQ_setbit(IRQQueue *q, int n_IRQ)
{
set_bit(n_IRQ, q->queue);
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,577 | static inline int IRQ_testbit(IRQQueue *q, int n_IRQ)
{
return test_bit(n_IRQ, q->queue);
}
| DoS Exec Code Overflow | 0 | static inline int IRQ_testbit(IRQQueue *q, int n_IRQ)
{
return test_bit(n_IRQ, q->queue);
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,578 | static int inttgt_to_output(int inttgt)
{
int i;
for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
if (inttgt_output[i][0] == inttgt) {
return inttgt_output[i][1];
}
}
fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt);
return OPENPIC_OUTPUT_INT;
}
| DoS Exec Code Overflow | 0 | static int inttgt_to_output(int inttgt)
{
int i;
for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
if (inttgt_output[i][0] == inttgt) {
return inttgt_output[i][1];
}
}
fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt);
return OPENPIC_OUTPUT_INT;
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,579 | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
{
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
}
| DoS Exec Code Overflow | 0 | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
{
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,580 | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len)
{
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
}
| DoS Exec Code Overflow | 0 | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len)
{
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,581 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx)
{
OpenPICState *opp = opaque;
IRQSource *src;
IRQDest *dst;
int s_IRQ, n_IRQ;
DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx,
addr, val);
if (idx < 0) {
return;
}
if (addr & 0xF) {
return;
}
dst = &opp->dst[idx];
addr &= 0xFF0;
switch (addr) {
case 0x40: /* IPIDR */
case 0x50:
case 0x60:
case 0x70:
idx = (addr - 0x40) >> 4;
/* we use IDE as mask which CPUs to deliver the IPI to still. */
opp->src[opp->irq_ipi0 + idx].destmask |= val;
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
break;
case 0x80: /* CTPR */
dst->ctpr = val & 0x0000000F;
DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
__func__, idx, dst->ctpr, dst->raised.priority,
dst->servicing.priority);
if (dst->raised.priority <= dst->ctpr) {
DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
__func__, idx);
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
} else if (dst->raised.priority > dst->servicing.priority) {
DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
__func__, idx, dst->raised.next);
qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
}
break;
case 0x90: /* WHOAMI */
/* Read-only register */
break;
case 0xA0: /* IACK */
/* Read-only register */
break;
case 0xB0: /* EOI */
DPRINTF("EOI\n");
s_IRQ = IRQ_get_next(opp, &dst->servicing);
if (s_IRQ < 0) {
DPRINTF("%s: EOI with no interrupt in service\n", __func__);
break;
}
IRQ_resetbit(&dst->servicing, s_IRQ);
/* Set up next servicing IRQ */
s_IRQ = IRQ_get_next(opp, &dst->servicing);
/* Check queued interrupts. */
n_IRQ = IRQ_get_next(opp, &dst->raised);
src = &opp->src[n_IRQ];
if (n_IRQ != -1 &&
(s_IRQ == -1 ||
IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
idx, n_IRQ);
qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]);
}
break;
default:
break;
}
}
| DoS Exec Code Overflow | 0 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx)
{
OpenPICState *opp = opaque;
IRQSource *src;
IRQDest *dst;
int s_IRQ, n_IRQ;
DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx,
addr, val);
if (idx < 0) {
return;
}
if (addr & 0xF) {
return;
}
dst = &opp->dst[idx];
addr &= 0xFF0;
switch (addr) {
case 0x40: /* IPIDR */
case 0x50:
case 0x60:
case 0x70:
idx = (addr - 0x40) >> 4;
/* we use IDE as mask which CPUs to deliver the IPI to still. */
opp->src[opp->irq_ipi0 + idx].destmask |= val;
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
break;
case 0x80: /* CTPR */
dst->ctpr = val & 0x0000000F;
DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
__func__, idx, dst->ctpr, dst->raised.priority,
dst->servicing.priority);
if (dst->raised.priority <= dst->ctpr) {
DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
__func__, idx);
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
} else if (dst->raised.priority > dst->servicing.priority) {
DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
__func__, idx, dst->raised.next);
qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
}
break;
case 0x90: /* WHOAMI */
/* Read-only register */
break;
case 0xA0: /* IACK */
/* Read-only register */
break;
case 0xB0: /* EOI */
DPRINTF("EOI\n");
s_IRQ = IRQ_get_next(opp, &dst->servicing);
if (s_IRQ < 0) {
DPRINTF("%s: EOI with no interrupt in service\n", __func__);
break;
}
IRQ_resetbit(&dst->servicing, s_IRQ);
/* Set up next servicing IRQ */
s_IRQ = IRQ_get_next(opp, &dst->servicing);
/* Check queued interrupts. */
n_IRQ = IRQ_get_next(opp, &dst->raised);
src = &opp->src[n_IRQ];
if (n_IRQ != -1 &&
(s_IRQ == -1 ||
IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
idx, n_IRQ);
qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]);
}
break;
default:
break;
}
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,582 | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
{
OpenPICState *opp = opaque;
uint32_t retval;
DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF) {
return retval;
}
switch (addr) {
case 0x1000: /* FRR */
retval = opp->frr;
break;
case 0x1020: /* GCR */
retval = opp->gcr;
break;
case 0x1080: /* VIR */
retval = opp->vir;
break;
case 0x1090: /* PIR */
retval = 0x00000000;
break;
case 0x00: /* Block Revision Register1 (BRR1) */
retval = opp->brr1;
break;
case 0x40:
case 0x50:
case 0x60:
case 0x70:
case 0x80:
case 0x90:
case 0xA0:
case 0xB0:
retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
break;
case 0x10A0: /* IPI_IVPR */
case 0x10B0:
case 0x10C0:
case 0x10D0:
{
int idx;
idx = (addr - 0x10A0) >> 4;
retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
}
break;
case 0x10E0: /* SPVE */
retval = opp->spve;
break;
default:
break;
}
DPRINTF("%s: => 0x%08x\n", __func__, retval);
return retval;
}
| DoS Exec Code Overflow | 0 | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
{
OpenPICState *opp = opaque;
uint32_t retval;
DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF) {
return retval;
}
switch (addr) {
case 0x1000: /* FRR */
retval = opp->frr;
break;
case 0x1020: /* GCR */
retval = opp->gcr;
break;
case 0x1080: /* VIR */
retval = opp->vir;
break;
case 0x1090: /* PIR */
retval = 0x00000000;
break;
case 0x00: /* Block Revision Register1 (BRR1) */
retval = opp->brr1;
break;
case 0x40:
case 0x50:
case 0x60:
case 0x70:
case 0x80:
case 0x90:
case 0xA0:
case 0xB0:
retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
break;
case 0x10A0: /* IPI_IVPR */
case 0x10B0:
case 0x10C0:
case 0x10D0:
{
int idx;
idx = (addr - 0x10A0) >> 4;
retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
}
break;
case 0x10E0: /* SPVE */
retval = opp->spve;
break;
default:
break;
}
DPRINTF("%s: => 0x%08x\n", __func__, retval);
return retval;
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,583 | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len)
{
OpenPICState *opp = opaque;
IRQDest *dst;
int idx;
DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
__func__, addr, val);
if (addr & 0xF) {
return;
}
switch (addr) {
case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
break;
case 0x40:
case 0x50:
case 0x60:
case 0x70:
case 0x80:
case 0x90:
case 0xA0:
case 0xB0:
openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
break;
case 0x1000: /* FRR */
break;
case 0x1020: /* GCR */
openpic_gcr_write(opp, val);
break;
case 0x1080: /* VIR */
break;
case 0x1090: /* PIR */
for (idx = 0; idx < opp->nb_cpus; idx++) {
if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
dst = &opp->dst[idx];
qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
} else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
dst = &opp->dst[idx];
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
}
}
opp->pir = val;
break;
case 0x10A0: /* IPI_IVPR */
case 0x10B0:
case 0x10C0:
case 0x10D0:
{
int idx;
idx = (addr - 0x10A0) >> 4;
write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
}
break;
case 0x10E0: /* SPVE */
opp->spve = val & opp->vector_mask;
break;
default:
break;
}
}
| DoS Exec Code Overflow | 0 | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
unsigned len)
{
OpenPICState *opp = opaque;
IRQDest *dst;
int idx;
DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
__func__, addr, val);
if (addr & 0xF) {
return;
}
switch (addr) {
case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
break;
case 0x40:
case 0x50:
case 0x60:
case 0x70:
case 0x80:
case 0x90:
case 0xA0:
case 0xB0:
openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
break;
case 0x1000: /* FRR */
break;
case 0x1020: /* GCR */
openpic_gcr_write(opp, val);
break;
case 0x1080: /* VIR */
break;
case 0x1090: /* PIR */
for (idx = 0; idx < opp->nb_cpus; idx++) {
if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
dst = &opp->dst[idx];
qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
} else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
dst = &opp->dst[idx];
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
}
}
opp->pir = val;
break;
case 0x10A0: /* IPI_IVPR */
case 0x10B0:
case 0x10C0:
case 0x10D0:
{
int idx;
idx = (addr - 0x10A0) >> 4;
write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
}
break;
case 0x10E0: /* SPVE */
opp->spve = val & opp->vector_mask;
break;
default:
break;
}
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,584 | static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
{
bool mpic_proxy = false;
if (val & GCR_RESET) {
openpic_reset(DEVICE(opp));
return;
}
opp->gcr &= ~opp->mpic_mode_mask;
opp->gcr |= val & opp->mpic_mode_mask;
/* Set external proxy mode */
if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
mpic_proxy = true;
}
ppce500_set_mpic_proxy(mpic_proxy);
}
| DoS Exec Code Overflow | 0 | static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
{
bool mpic_proxy = false;
if (val & GCR_RESET) {
openpic_reset(DEVICE(opp));
return;
}
opp->gcr &= ~opp->mpic_mode_mask;
opp->gcr |= val & opp->mpic_mode_mask;
/* Set external proxy mode */
if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
mpic_proxy = true;
}
ppce500_set_mpic_proxy(mpic_proxy);
}
| @@ -41,6 +41,7 @@
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
//#define DEBUG_OPENPIC
@@ -1416,7 +1417,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
static int openpic_load(QEMUFile* f, void *opaque, int version_id)
{
OpenPICState *opp = (OpenPICState *)opaque;
- unsigned int i;
+ unsigned int i, nb_cpus;
if (version_id != 1) {
return -EINVAL;
@@ -1428,7 +1429,11 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
qemu_get_be32s(f, &opp->spve);
qemu_get_be32s(f, &opp->tfrr);
- qemu_get_be32s(f, &opp->nb_cpus);
+ qemu_get_be32s(f, &nb_cpus);
+ if (opp->nb_cpus != nb_cpus) {
+ return -EINVAL;
+ }
+ assert(nb_cpus > 0 && nb_cpus <= MAX_CPU);
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_sbe32s(f, &opp->dst[i].ctpr);
@@ -1567,6 +1572,13 @@ static void openpic_realize(DeviceState *dev, Error **errp)
{NULL}
};
+ if (opp->nb_cpus > MAX_CPU) {
+ error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
+ TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
+ (uint64_t)0, (uint64_t)MAX_CPU);
+ return;
+ }
+
switch (opp->model) {
case OPENPIC_MODEL_FSL_MPIC_20:
default: | CWE-119 | null | null |
12,585 | static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->clkcfg = value & 0xf;
if (value & 2) {
printf("%s: CPU frequency change attempt\n", __func__);
}
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->clkcfg = value & 0xf;
if (value & 2) {
printf("%s: CPU frequency change attempt\n", __func__);
}
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,586 | static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case CCCR:
case CKEN:
case OSCC:
return s->cm_regs[addr >> 2];
case CCSR:
return s->cm_regs[CCCR >> 2] | (3 << 28);
default:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
return 0;
}
| DoS Exec Code Overflow | 0 | static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case CCCR:
case CKEN:
case OSCC:
return s->cm_regs[addr >> 2];
case CCSR:
return s->cm_regs[CCCR >> 2] | (3 << 28);
default:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
return 0;
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,587 | static void pxa2xx_cm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case CCCR:
case CKEN:
s->cm_regs[addr >> 2] = value;
break;
case OSCC:
s->cm_regs[addr >> 2] &= ~0x6c;
s->cm_regs[addr >> 2] |= value & 0x6e;
if ((value >> 1) & 1) /* OON */
s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
break;
default:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_cm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case CCCR:
case CKEN:
s->cm_regs[addr >> 2] = value;
break;
case OSCC:
s->cm_regs[addr >> 2] &= ~0x6c;
s->cm_regs[addr >> 2] |= value & 0x6e;
if ((value >> 1) & 1) /* OON */
s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
break;
default:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,588 | static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->pmnc = value;
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
s->pmnc = value;
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,589 | static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
if ((addr & 3) == 0)
return s->mm_regs[addr >> 2];
default:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
return 0;
}
| DoS Exec Code Overflow | 0 | static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
if ((addr & 3) == 0)
return s->mm_regs[addr >> 2];
default:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
return 0;
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,590 | static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case PMCR ... PCMD31:
if (addr & 3)
goto fail;
return s->pm_regs[addr >> 2];
default:
fail:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
return 0;
}
| DoS Exec Code Overflow | 0 | static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case PMCR ... PCMD31:
if (addr & 3)
goto fail;
return s->pm_regs[addr >> 2];
default:
fail:
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
return 0;
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,591 | static void pxa2xx_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case PMCR:
/* Clear the write-one-to-clear bits... */
s->pm_regs[addr >> 2] &= ~(value & 0x2a);
/* ...and set the plain r/w bits */
s->pm_regs[addr >> 2] &= ~0x15;
s->pm_regs[addr >> 2] |= value & 0x15;
break;
case PSSR: /* Read-clean registers */
case RCSR:
case PKSR:
s->pm_regs[addr >> 2] &= ~value;
break;
default: /* Read-write registers */
if (!(addr & 3)) {
s->pm_regs[addr >> 2] = value;
break;
}
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case PMCR:
/* Clear the write-one-to-clear bits... */
s->pm_regs[addr >> 2] &= ~(value & 0x2a);
/* ...and set the plain r/w bits */
s->pm_regs[addr >> 2] &= ~0x15;
s->pm_regs[addr >> 2] |= value & 0x15;
break;
case PSSR: /* Read-clean registers */
case RCSR:
case PKSR:
s->pm_regs[addr >> 2] &= ~value;
break;
default: /* Read-write registers */
if (!(addr & 3)) {
s->pm_regs[addr >> 2] = value;
break;
}
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
break;
}
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,592 | static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
static const char *pwrmode[8] = {
"Normal", "Idle", "Deep-idle", "Standby",
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
};
if (value & 8) {
printf("%s: CPU voltage change attempt\n", __func__);
}
switch (value & 7) {
case 0:
/* Do nothing */
break;
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
/* Fall through. */
case 2:
/* Deep-Idle */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
case 3:
s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
s->cpu->env.cp15.c1_sys = 0;
s->cpu->env.cp15.c1_coproc = 0;
s->cpu->env.cp15.ttbr0_el1 = 0;
s->cpu->env.cp15.c3 = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
/*
* The scratch-pad register is almost universally used
* for storing the return address on suspend. For the
* lack of a resuming bootloader, perform a jump
* directly to that address.
*/
memset(s->cpu->env.regs, 0, 4 * 15);
s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
#if 0
buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
cpu_physical_memory_write(0, &buffer, 4);
buffer = s->pm_regs[PSPR >> 2];
cpu_physical_memory_write(8, &buffer, 4);
#endif
/* Suspend */
cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
goto message;
default:
message:
printf("%s: machine entered %s mode\n", __func__,
pwrmode[value & 7]);
}
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
PXA2xxState *s = (PXA2xxState *)ri->opaque;
static const char *pwrmode[8] = {
"Normal", "Idle", "Deep-idle", "Standby",
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
};
if (value & 8) {
printf("%s: CPU voltage change attempt\n", __func__);
}
switch (value & 7) {
case 0:
/* Do nothing */
break;
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
/* Fall through. */
case 2:
/* Deep-Idle */
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
case 3:
s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
s->cpu->env.cp15.c1_sys = 0;
s->cpu->env.cp15.c1_coproc = 0;
s->cpu->env.cp15.ttbr0_el1 = 0;
s->cpu->env.cp15.c3 = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
/*
* The scratch-pad register is almost universally used
* for storing the return address on suspend. For the
* lack of a resuming bootloader, perform a jump
* directly to that address.
*/
memset(s->cpu->env.regs, 0, 4 * 15);
s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
#if 0
buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
cpu_physical_memory_write(0, &buffer, 4);
buffer = s->pm_regs[PSPR >> 2];
cpu_physical_memory_write(8, &buffer, 4);
#endif
/* Suspend */
cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
goto message;
default:
message:
printf("%s: machine entered %s mode\n", __func__,
pwrmode[value & 7]);
}
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,593 | static void pxa2xx_setup_cp14(PXA2xxState *s)
{
define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_setup_cp14(PXA2xxState *s)
{
define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,594 | static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
{
s->sssr &= ~(0xf << 12); /* Clear RFL */
s->sssr &= ~(0xf << 8); /* Clear TFL */
s->sssr &= ~SSSR_TFS;
s->sssr &= ~SSSR_TNF;
if (s->enable) {
s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
s->sssr |= SSSR_RFS;
else
s->sssr &= ~SSSR_RFS;
if (s->rx_level)
s->sssr |= SSSR_RNE;
else
s->sssr &= ~SSSR_RNE;
/* TX FIFO is never filled, so it is always in underrun
condition if SSP is enabled */
s->sssr |= SSSR_TFS;
s->sssr |= SSSR_TNF;
}
pxa2xx_ssp_int_update(s);
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
{
s->sssr &= ~(0xf << 12); /* Clear RFL */
s->sssr &= ~(0xf << 8); /* Clear TFL */
s->sssr &= ~SSSR_TFS;
s->sssr &= ~SSSR_TNF;
if (s->enable) {
s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
s->sssr |= SSSR_RFS;
else
s->sssr &= ~SSSR_RFS;
if (s->rx_level)
s->sssr |= SSSR_RNE;
else
s->sssr &= ~SSSR_RNE;
/* TX FIFO is never filled, so it is always in underrun
condition if SSP is enabled */
s->sssr |= SSSR_TFS;
s->sssr |= SSSR_TNF;
}
pxa2xx_ssp_int_update(s);
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,595 | static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
{
int level = 0;
level |= s->ssitr & SSITR_INT;
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
qemu_set_irq(s->irq, !!level);
}
| DoS Exec Code Overflow | 0 | static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
{
int level = 0;
level |= s->ssitr & SSITR_INT;
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
qemu_set_irq(s->irq, !!level);
}
| @@ -732,7 +732,7 @@ static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
- int i;
+ int i, v;
s->enable = qemu_get_be32(f);
@@ -746,7 +746,11 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_8s(f, &s->ssrsa);
qemu_get_8s(f, &s->ssacd);
- s->rx_level = qemu_get_byte(f);
+ v = qemu_get_byte(f);
+ if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
+ return -EINVAL;
+ }
+ s->rx_level = v;
s->rx_start = 0;
for (i = 0; i < s->rx_level; i ++)
s->rx_fifo[i] = qemu_get_byte(f); | CWE-119 | null | null |
12,596 | static int get_bitmap(QEMUFile *f, void *pv, size_t size)
{
unsigned long *bmp = pv;
int i, idx = 0;
for (i = 0; i < BITS_TO_U64S(size); i++) {
uint64_t w = qemu_get_be64(f);
bmp[idx++] = w;
if (sizeof(unsigned long) == 4 && idx < BITS_TO_LONGS(size)) {
bmp[idx++] = w >> 32;
}
}
return 0;
}
| DoS Exec Code Overflow | 0 | static int get_bitmap(QEMUFile *f, void *pv, size_t size)
{
unsigned long *bmp = pv;
int i, idx = 0;
for (i = 0; i < BITS_TO_U64S(size); i++) {
uint64_t w = qemu_get_be64(f);
bmp[idx++] = w;
if (sizeof(unsigned long) == 4 && idx < BITS_TO_LONGS(size)) {
bmp[idx++] = w >> 32;
}
}
return 0;
}
| @@ -337,8 +337,9 @@ const VMStateInfo vmstate_info_int32_equal = {
.put = put_int32,
};
-/* 32 bit int. Check that the received value is less than or equal to
- the one in the field */
+/* 32 bit int. Check that the received value is non-negative
+ * and less than or equal to the one in the field.
+ */
static int get_int32_le(QEMUFile *f, void *pv, size_t size)
{
@@ -346,7 +347,7 @@ static int get_int32_le(QEMUFile *f, void *pv, size_t size)
int32_t loaded;
qemu_get_sbe32s(f, &loaded);
- if (loaded <= *cur) {
+ if (loaded >= 0 && loaded <= *cur) {
*cur = loaded;
return 0;
} | CWE-119 | null | null |
12,597 | static int get_buffer(QEMUFile *f, void *pv, size_t size)
{
uint8_t *v = pv;
qemu_get_buffer(f, v, size);
return 0;
}
| DoS Exec Code Overflow | 0 | static int get_buffer(QEMUFile *f, void *pv, size_t size)
{
uint8_t *v = pv;
qemu_get_buffer(f, v, size);
return 0;
}
| @@ -337,8 +337,9 @@ const VMStateInfo vmstate_info_int32_equal = {
.put = put_int32,
};
-/* 32 bit int. Check that the received value is less than or equal to
- the one in the field */
+/* 32 bit int. Check that the received value is non-negative
+ * and less than or equal to the one in the field.
+ */
static int get_int32_le(QEMUFile *f, void *pv, size_t size)
{
@@ -346,7 +347,7 @@ static int get_int32_le(QEMUFile *f, void *pv, size_t size)
int32_t loaded;
qemu_get_sbe32s(f, &loaded);
- if (loaded <= *cur) {
+ if (loaded >= 0 && loaded <= *cur) {
*cur = loaded;
return 0;
} | CWE-119 | null | null |
12,598 | static int get_float64(QEMUFile *f, void *pv, size_t size)
{
float64 *v = pv;
*v = make_float64(qemu_get_be64(f));
return 0;
}
| DoS Exec Code Overflow | 0 | static int get_float64(QEMUFile *f, void *pv, size_t size)
{
float64 *v = pv;
*v = make_float64(qemu_get_be64(f));
return 0;
}
| @@ -337,8 +337,9 @@ const VMStateInfo vmstate_info_int32_equal = {
.put = put_int32,
};
-/* 32 bit int. Check that the received value is less than or equal to
- the one in the field */
+/* 32 bit int. Check that the received value is non-negative
+ * and less than or equal to the one in the field.
+ */
static int get_int32_le(QEMUFile *f, void *pv, size_t size)
{
@@ -346,7 +347,7 @@ static int get_int32_le(QEMUFile *f, void *pv, size_t size)
int32_t loaded;
qemu_get_sbe32s(f, &loaded);
- if (loaded <= *cur) {
+ if (loaded >= 0 && loaded <= *cur) {
*cur = loaded;
return 0;
} | CWE-119 | null | null |
12,599 | static int get_int32(QEMUFile *f, void *pv, size_t size)
{
int32_t *v = pv;
qemu_get_sbe32s(f, v);
return 0;
}
| DoS Exec Code Overflow | 0 | static int get_int32(QEMUFile *f, void *pv, size_t size)
{
int32_t *v = pv;
qemu_get_sbe32s(f, v);
return 0;
}
| @@ -337,8 +337,9 @@ const VMStateInfo vmstate_info_int32_equal = {
.put = put_int32,
};
-/* 32 bit int. Check that the received value is less than or equal to
- the one in the field */
+/* 32 bit int. Check that the received value is non-negative
+ * and less than or equal to the one in the field.
+ */
static int get_int32_le(QEMUFile *f, void *pv, size_t size)
{
@@ -346,7 +347,7 @@ static int get_int32_le(QEMUFile *f, void *pv, size_t size)
int32_t loaded;
qemu_get_sbe32s(f, &loaded);
- if (loaded <= *cur) {
+ if (loaded >= 0 && loaded <= *cur) {
*cur = loaded;
return 0;
} | CWE-119 | null | null |
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