idx int64 | func_before string | Vulnerability Classification string | vul int64 | func_after string | patch string | CWE ID string | lines_before string | lines_after string |
|---|---|---|---|---|---|---|---|---|
26,200 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
{
static const u32 test_pat[4][6] = {
{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
{ 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
{ 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
};
int chan;
for (chan = 0; chan < 4; chan++) {
int i;
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
(chan * 0x2000) | 0x0200);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
for (i = 0; i < 6; i++)
tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
test_pat[chan][i]);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
(chan * 0x2000) | 0x0200);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
for (i = 0; i < 6; i += 2) {
u32 low, high;
if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
low &= 0x7fff;
high &= 0x000f;
if (low != test_pat[chan][i] ||
high != test_pat[chan][i+1]) {
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
return -EBUSY;
}
}
}
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
{
static const u32 test_pat[4][6] = {
{ 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
{ 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
{ 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
{ 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
};
int chan;
for (chan = 0; chan < 4; chan++) {
int i;
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
(chan * 0x2000) | 0x0200);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
for (i = 0; i < 6; i++)
tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
test_pat[chan][i]);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
(chan * 0x2000) | 0x0200);
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
if (tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
for (i = 0; i < 6; i += 2) {
u32 low, high;
if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
tg3_wait_macro_done(tp)) {
*resetp = 1;
return -EBUSY;
}
low &= 0x7fff;
high &= 0x000f;
if (low != test_pat[chan][i] ||
high != test_pat[chan][i+1]) {
tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
return -EBUSY;
}
}
}
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,201 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
{
int err;
err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
if (!err)
err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
{
int err;
err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
if (!err)
err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,202 | static int tg3_poll(struct napi_struct *napi, int budget)
{
struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
struct tg3 *tp = tnapi->tp;
int work_done = 0;
struct tg3_hw_status *sblk = tnapi->hw_status;
while (1) {
if (sblk->status & SD_STATUS_ERROR)
tg3_process_error(tp);
tg3_poll_link(tp);
work_done = tg3_poll_work(tnapi, work_done, budget);
if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
goto tx_recovery;
if (unlikely(work_done >= budget))
break;
if (tg3_flag(tp, TAGGED_STATUS)) {
/* tp->last_tag is used in tg3_int_reenable() below
* to tell the hw how much work has been processed,
* so we must read it before checking for more work.
*/
tnapi->last_tag = sblk->status_tag;
tnapi->last_irq_tag = tnapi->last_tag;
rmb();
} else
sblk->status &= ~SD_STATUS_UPDATED;
if (likely(!tg3_has_work(tnapi))) {
napi_complete(napi);
tg3_int_reenable(tnapi);
break;
}
}
return work_done;
tx_recovery:
/* work_done is guaranteed to be less than budget. */
napi_complete(napi);
tg3_reset_task_schedule(tp);
return work_done;
}
| DoS Exec Code Overflow | 0 | static int tg3_poll(struct napi_struct *napi, int budget)
{
struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
struct tg3 *tp = tnapi->tp;
int work_done = 0;
struct tg3_hw_status *sblk = tnapi->hw_status;
while (1) {
if (sblk->status & SD_STATUS_ERROR)
tg3_process_error(tp);
tg3_poll_link(tp);
work_done = tg3_poll_work(tnapi, work_done, budget);
if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
goto tx_recovery;
if (unlikely(work_done >= budget))
break;
if (tg3_flag(tp, TAGGED_STATUS)) {
/* tp->last_tag is used in tg3_int_reenable() below
* to tell the hw how much work has been processed,
* so we must read it before checking for more work.
*/
tnapi->last_tag = sblk->status_tag;
tnapi->last_irq_tag = tnapi->last_tag;
rmb();
} else
sblk->status &= ~SD_STATUS_UPDATED;
if (likely(!tg3_has_work(tnapi))) {
napi_complete(napi);
tg3_int_reenable(tnapi);
break;
}
}
return work_done;
tx_recovery:
/* work_done is guaranteed to be less than budget. */
napi_complete(napi);
tg3_reset_task_schedule(tp);
return work_done;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,203 | static int tg3_poll_fw(struct tg3 *tp)
{
int i;
u32 val;
if (tg3_flag(tp, IS_SSB_CORE)) {
/* We don't use firmware. */
return 0;
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) {
if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
return 0;
udelay(100);
}
return -ENODEV;
}
/* Wait for firmware initialization to complete. */
for (i = 0; i < 100000; i++) {
tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
break;
udelay(10);
}
/* Chip might not be fitted with firmware. Some Sun onboard
* parts are configured like that. So don't signal the timeout
* of the above loop as an error, but do report the lack of
* running firmware once.
*/
if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
tg3_flag_set(tp, NO_FWARE_REPORTED);
netdev_info(tp->dev, "No firmware running\n");
}
if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
/* The 57765 A0 needs a little more
* time to do some important work.
*/
mdelay(10);
}
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_poll_fw(struct tg3 *tp)
{
int i;
u32 val;
if (tg3_flag(tp, IS_SSB_CORE)) {
/* We don't use firmware. */
return 0;
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
/* Wait up to 20ms for init done. */
for (i = 0; i < 200; i++) {
if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
return 0;
udelay(100);
}
return -ENODEV;
}
/* Wait for firmware initialization to complete. */
for (i = 0; i < 100000; i++) {
tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
break;
udelay(10);
}
/* Chip might not be fitted with firmware. Some Sun onboard
* parts are configured like that. So don't signal the timeout
* of the above loop as an error, but do report the lack of
* running firmware once.
*/
if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
tg3_flag_set(tp, NO_FWARE_REPORTED);
netdev_info(tp->dev, "No firmware running\n");
}
if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
/* The 57765 A0 needs a little more
* time to do some important work.
*/
mdelay(10);
}
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,204 | static int tg3_poll_msix(struct napi_struct *napi, int budget)
{
struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
struct tg3 *tp = tnapi->tp;
int work_done = 0;
struct tg3_hw_status *sblk = tnapi->hw_status;
while (1) {
work_done = tg3_poll_work(tnapi, work_done, budget);
if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
goto tx_recovery;
if (unlikely(work_done >= budget))
break;
/* tp->last_tag is used in tg3_int_reenable() below
* to tell the hw how much work has been processed,
* so we must read it before checking for more work.
*/
tnapi->last_tag = sblk->status_tag;
tnapi->last_irq_tag = tnapi->last_tag;
rmb();
/* check for RX/TX work to do */
if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
*(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
/* This test here is not race free, but will reduce
* the number of interrupts by looping again.
*/
if (tnapi == &tp->napi[1] && tp->rx_refill)
continue;
napi_complete(napi);
/* Reenable interrupts. */
tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
/* This test here is synchronized by napi_schedule()
* and napi_complete() to close the race condition.
*/
if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
tw32(HOSTCC_MODE, tp->coalesce_mode |
HOSTCC_MODE_ENABLE |
tnapi->coal_now);
}
mmiowb();
break;
}
}
return work_done;
tx_recovery:
/* work_done is guaranteed to be less than budget. */
napi_complete(napi);
tg3_reset_task_schedule(tp);
return work_done;
}
| DoS Exec Code Overflow | 0 | static int tg3_poll_msix(struct napi_struct *napi, int budget)
{
struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
struct tg3 *tp = tnapi->tp;
int work_done = 0;
struct tg3_hw_status *sblk = tnapi->hw_status;
while (1) {
work_done = tg3_poll_work(tnapi, work_done, budget);
if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
goto tx_recovery;
if (unlikely(work_done >= budget))
break;
/* tp->last_tag is used in tg3_int_reenable() below
* to tell the hw how much work has been processed,
* so we must read it before checking for more work.
*/
tnapi->last_tag = sblk->status_tag;
tnapi->last_irq_tag = tnapi->last_tag;
rmb();
/* check for RX/TX work to do */
if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
*(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
/* This test here is not race free, but will reduce
* the number of interrupts by looping again.
*/
if (tnapi == &tp->napi[1] && tp->rx_refill)
continue;
napi_complete(napi);
/* Reenable interrupts. */
tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
/* This test here is synchronized by napi_schedule()
* and napi_complete() to close the race condition.
*/
if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
tw32(HOSTCC_MODE, tp->coalesce_mode |
HOSTCC_MODE_ENABLE |
tnapi->coal_now);
}
mmiowb();
break;
}
}
return work_done;
tx_recovery:
/* work_done is guaranteed to be less than budget. */
napi_complete(napi);
tg3_reset_task_schedule(tp);
return work_done;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,205 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
{
u32 val;
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
if (tg3_asic_rev(tp) == ASIC_REV_5704) {
u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
u32 serdes_cfg = tr32(MAC_SERDES_CFG);
sg_dig_ctrl |=
SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
tw32(SG_DIG_CTRL, sg_dig_ctrl);
tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
}
return;
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
tg3_bmcr_reset(tp);
val = tr32(GRC_MISC_CFG);
tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
udelay(40);
return;
} else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
u32 phytest;
if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
u32 phy;
tg3_writephy(tp, MII_ADVERTISE, 0);
tg3_writephy(tp, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);
tg3_writephy(tp, MII_TG3_FET_TEST,
phytest | MII_TG3_FET_SHADOW_EN);
if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
tg3_writephy(tp,
MII_TG3_FET_SHDW_AUXMODE4,
phy);
}
tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
}
return;
} else if (do_low_power) {
tg3_writephy(tp, MII_TG3_EXT_CTRL,
MII_TG3_EXT_CTRL_FORCE_LED_OFF);
val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
MII_TG3_AUXCTL_PCTL_VREG_11V;
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
}
/* The PHY should not be powered down on some chips because
* of bugs.
*/
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5704 ||
(tg3_asic_rev(tp) == ASIC_REV_5780 &&
(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
(tg3_asic_rev(tp) == ASIC_REV_5717 &&
!tp->pci_fn))
return;
if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
tg3_chip_rev(tp) == CHIPREV_5761_AX) {
val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
val |= CPMU_LSPD_1000MB_MACCLK_12_5;
tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
}
tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
}
| DoS Exec Code Overflow | 0 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
{
u32 val;
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
if (tg3_asic_rev(tp) == ASIC_REV_5704) {
u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
u32 serdes_cfg = tr32(MAC_SERDES_CFG);
sg_dig_ctrl |=
SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
tw32(SG_DIG_CTRL, sg_dig_ctrl);
tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
}
return;
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
tg3_bmcr_reset(tp);
val = tr32(GRC_MISC_CFG);
tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
udelay(40);
return;
} else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
u32 phytest;
if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
u32 phy;
tg3_writephy(tp, MII_ADVERTISE, 0);
tg3_writephy(tp, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);
tg3_writephy(tp, MII_TG3_FET_TEST,
phytest | MII_TG3_FET_SHADOW_EN);
if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
tg3_writephy(tp,
MII_TG3_FET_SHDW_AUXMODE4,
phy);
}
tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
}
return;
} else if (do_low_power) {
tg3_writephy(tp, MII_TG3_EXT_CTRL,
MII_TG3_EXT_CTRL_FORCE_LED_OFF);
val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
MII_TG3_AUXCTL_PCTL_VREG_11V;
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
}
/* The PHY should not be powered down on some chips because
* of bugs.
*/
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5704 ||
(tg3_asic_rev(tp) == ASIC_REV_5780 &&
(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
(tg3_asic_rev(tp) == ASIC_REV_5717 &&
!tp->pci_fn))
return;
if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
tg3_chip_rev(tp) == CHIPREV_5761_AX) {
val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
val |= CPMU_LSPD_1000MB_MACCLK_12_5;
tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
}
tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,206 | static int tg3_power_down_prepare(struct tg3 *tp)
{
u32 misc_host_ctrl;
bool device_should_wake, do_low_power;
tg3_enable_register_access(tp);
/* Restore the CLKREQ setting. */
if (tg3_flag(tp, CLKREQ_BUG))
pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CLKREQ_EN);
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
tw32(TG3PCI_MISC_HOST_CTRL,
misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
tg3_flag(tp, WOL_ENABLE);
if (tg3_flag(tp, USE_PHYLIB)) {
do_low_power = false;
if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
struct phy_device *phydev;
u32 phyid, advertising;
phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
tp->link_config.speed = phydev->speed;
tp->link_config.duplex = phydev->duplex;
tp->link_config.autoneg = phydev->autoneg;
tp->link_config.advertising = phydev->advertising;
advertising = ADVERTISED_TP |
ADVERTISED_Pause |
ADVERTISED_Autoneg |
ADVERTISED_10baseT_Half;
if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
if (tg3_flag(tp, WOL_SPEED_100MB))
advertising |=
ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_10baseT_Full;
else
advertising |= ADVERTISED_10baseT_Full;
}
phydev->advertising = advertising;
phy_start_aneg(phydev);
phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
if (phyid != PHY_ID_BCMAC131) {
phyid &= PHY_BCM_OUI_MASK;
if (phyid == PHY_BCM_OUI_1 ||
phyid == PHY_BCM_OUI_2 ||
phyid == PHY_BCM_OUI_3)
do_low_power = true;
}
}
} else {
do_low_power = true;
if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
tg3_setup_phy(tp, 0);
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
u32 val;
val = tr32(GRC_VCPU_EXT_CTRL);
tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
} else if (!tg3_flag(tp, ENABLE_ASF)) {
int i;
u32 val;
for (i = 0; i < 200; i++) {
tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
break;
msleep(1);
}
}
if (tg3_flag(tp, WOL_CAP))
tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
WOL_DRV_STATE_SHUTDOWN |
WOL_DRV_WOL |
WOL_SET_MAGIC_PKT);
if (device_should_wake) {
u32 mac_mode;
if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
if (do_low_power &&
!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
tg3_phy_auxctl_write(tp,
MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
MII_TG3_AUXCTL_PCTL_WOL_EN |
MII_TG3_AUXCTL_PCTL_100TX_LPWR |
MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
udelay(40);
}
if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
mac_mode = MAC_MODE_PORT_MODE_GMII;
else
mac_mode = MAC_MODE_PORT_MODE_MII;
mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
if (tg3_asic_rev(tp) == ASIC_REV_5700) {
u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
SPEED_100 : SPEED_10;
if (tg3_5700_link_polarity(tp, speed))
mac_mode |= MAC_MODE_LINK_POLARITY;
else
mac_mode &= ~MAC_MODE_LINK_POLARITY;
}
} else {
mac_mode = MAC_MODE_PORT_MODE_TBI;
}
if (!tg3_flag(tp, 5750_PLUS))
tw32(MAC_LED_CTRL, tp->led_ctrl);
mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
(tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
if (tg3_flag(tp, ENABLE_APE))
mac_mode |= MAC_MODE_APE_TX_EN |
MAC_MODE_APE_RX_EN |
MAC_MODE_TDE_ENABLE;
tw32_f(MAC_MODE, mac_mode);
udelay(100);
tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
udelay(10);
}
if (!tg3_flag(tp, WOL_SPEED_100MB) &&
(tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701)) {
u32 base_val;
base_val = tp->pci_clock_ctrl;
base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE);
tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
CLOCK_CTRL_PWRDOWN_PLL133, 40);
} else if (tg3_flag(tp, 5780_CLASS) ||
tg3_flag(tp, CPMU_PRESENT) ||
tg3_asic_rev(tp) == ASIC_REV_5906) {
/* do nothing */
} else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
u32 newbits1, newbits2;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE |
CLOCK_CTRL_ALTCLK);
newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
} else if (tg3_flag(tp, 5705_PLUS)) {
newbits1 = CLOCK_CTRL_625_CORE;
newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
} else {
newbits1 = CLOCK_CTRL_ALTCLK;
newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
}
tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
40);
tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
40);
if (!tg3_flag(tp, 5705_PLUS)) {
u32 newbits3;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE |
CLOCK_CTRL_44MHZ_CORE);
} else {
newbits3 = CLOCK_CTRL_44MHZ_CORE;
}
tw32_wait_f(TG3PCI_CLOCK_CTRL,
tp->pci_clock_ctrl | newbits3, 40);
}
}
if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
tg3_power_down_phy(tp, do_low_power);
tg3_frob_aux_power(tp, true);
/* Workaround for unstable PLL clock */
if ((!tg3_flag(tp, IS_SSB_CORE)) &&
((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
(tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
u32 val = tr32(0x7d00);
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
tw32(0x7d00, val);
if (!tg3_flag(tp, ENABLE_ASF)) {
int err;
err = tg3_nvram_lock(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
if (!err)
tg3_nvram_unlock(tp);
}
}
tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_power_down_prepare(struct tg3 *tp)
{
u32 misc_host_ctrl;
bool device_should_wake, do_low_power;
tg3_enable_register_access(tp);
/* Restore the CLKREQ setting. */
if (tg3_flag(tp, CLKREQ_BUG))
pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CLKREQ_EN);
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
tw32(TG3PCI_MISC_HOST_CTRL,
misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
tg3_flag(tp, WOL_ENABLE);
if (tg3_flag(tp, USE_PHYLIB)) {
do_low_power = false;
if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
struct phy_device *phydev;
u32 phyid, advertising;
phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
tp->link_config.speed = phydev->speed;
tp->link_config.duplex = phydev->duplex;
tp->link_config.autoneg = phydev->autoneg;
tp->link_config.advertising = phydev->advertising;
advertising = ADVERTISED_TP |
ADVERTISED_Pause |
ADVERTISED_Autoneg |
ADVERTISED_10baseT_Half;
if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
if (tg3_flag(tp, WOL_SPEED_100MB))
advertising |=
ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_10baseT_Full;
else
advertising |= ADVERTISED_10baseT_Full;
}
phydev->advertising = advertising;
phy_start_aneg(phydev);
phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
if (phyid != PHY_ID_BCMAC131) {
phyid &= PHY_BCM_OUI_MASK;
if (phyid == PHY_BCM_OUI_1 ||
phyid == PHY_BCM_OUI_2 ||
phyid == PHY_BCM_OUI_3)
do_low_power = true;
}
}
} else {
do_low_power = true;
if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
tg3_setup_phy(tp, 0);
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
u32 val;
val = tr32(GRC_VCPU_EXT_CTRL);
tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
} else if (!tg3_flag(tp, ENABLE_ASF)) {
int i;
u32 val;
for (i = 0; i < 200; i++) {
tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
break;
msleep(1);
}
}
if (tg3_flag(tp, WOL_CAP))
tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
WOL_DRV_STATE_SHUTDOWN |
WOL_DRV_WOL |
WOL_SET_MAGIC_PKT);
if (device_should_wake) {
u32 mac_mode;
if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
if (do_low_power &&
!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
tg3_phy_auxctl_write(tp,
MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
MII_TG3_AUXCTL_PCTL_WOL_EN |
MII_TG3_AUXCTL_PCTL_100TX_LPWR |
MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
udelay(40);
}
if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
mac_mode = MAC_MODE_PORT_MODE_GMII;
else
mac_mode = MAC_MODE_PORT_MODE_MII;
mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
if (tg3_asic_rev(tp) == ASIC_REV_5700) {
u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
SPEED_100 : SPEED_10;
if (tg3_5700_link_polarity(tp, speed))
mac_mode |= MAC_MODE_LINK_POLARITY;
else
mac_mode &= ~MAC_MODE_LINK_POLARITY;
}
} else {
mac_mode = MAC_MODE_PORT_MODE_TBI;
}
if (!tg3_flag(tp, 5750_PLUS))
tw32(MAC_LED_CTRL, tp->led_ctrl);
mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
(tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
if (tg3_flag(tp, ENABLE_APE))
mac_mode |= MAC_MODE_APE_TX_EN |
MAC_MODE_APE_RX_EN |
MAC_MODE_TDE_ENABLE;
tw32_f(MAC_MODE, mac_mode);
udelay(100);
tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
udelay(10);
}
if (!tg3_flag(tp, WOL_SPEED_100MB) &&
(tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701)) {
u32 base_val;
base_val = tp->pci_clock_ctrl;
base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE);
tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
CLOCK_CTRL_PWRDOWN_PLL133, 40);
} else if (tg3_flag(tp, 5780_CLASS) ||
tg3_flag(tp, CPMU_PRESENT) ||
tg3_asic_rev(tp) == ASIC_REV_5906) {
/* do nothing */
} else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
u32 newbits1, newbits2;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE |
CLOCK_CTRL_ALTCLK);
newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
} else if (tg3_flag(tp, 5705_PLUS)) {
newbits1 = CLOCK_CTRL_625_CORE;
newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
} else {
newbits1 = CLOCK_CTRL_ALTCLK;
newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
}
tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
40);
tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
40);
if (!tg3_flag(tp, 5705_PLUS)) {
u32 newbits3;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
CLOCK_CTRL_TXCLK_DISABLE |
CLOCK_CTRL_44MHZ_CORE);
} else {
newbits3 = CLOCK_CTRL_44MHZ_CORE;
}
tw32_wait_f(TG3PCI_CLOCK_CTRL,
tp->pci_clock_ctrl | newbits3, 40);
}
}
if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
tg3_power_down_phy(tp, do_low_power);
tg3_frob_aux_power(tp, true);
/* Workaround for unstable PLL clock */
if ((!tg3_flag(tp, IS_SSB_CORE)) &&
((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
(tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
u32 val = tr32(0x7d00);
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
tw32(0x7d00, val);
if (!tg3_flag(tp, ENABLE_ASF)) {
int err;
err = tg3_nvram_lock(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
if (!err)
tg3_nvram_unlock(tp);
}
}
tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,207 | static int tg3_power_up(struct tg3 *tp)
{
int err;
tg3_enable_register_access(tp);
err = pci_set_power_state(tp->pdev, PCI_D0);
if (!err) {
/* Switch out of Vaux if it is a NIC */
tg3_pwrsrc_switch_to_vmain(tp);
} else {
netdev_err(tp->dev, "Transition to D0 failed\n");
}
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_power_up(struct tg3 *tp)
{
int err;
tg3_enable_register_access(tp);
err = pci_set_power_state(tp->pdev, PCI_D0);
if (!err) {
/* Switch out of Vaux if it is a NIC */
tg3_pwrsrc_switch_to_vmain(tp);
} else {
netdev_err(tp->dev, "Transition to D0 failed\n");
}
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,208 | static void tg3_probe_ncsi(struct tg3 *tp)
{
u32 apedata;
apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
if (apedata != APE_SEG_SIG_MAGIC)
return;
apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
if (!(apedata & APE_FW_STATUS_READY))
return;
if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
tg3_flag_set(tp, APE_HAS_NCSI);
}
| DoS Exec Code Overflow | 0 | static void tg3_probe_ncsi(struct tg3 *tp)
{
u32 apedata;
apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
if (apedata != APE_SEG_SIG_MAGIC)
return;
apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
if (!(apedata & APE_FW_STATUS_READY))
return;
if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
tg3_flag_set(tp, APE_HAS_NCSI);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,209 | static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
bool neg_adj = false;
u32 correction = 0;
if (ppb < 0) {
neg_adj = true;
ppb = -ppb;
}
/* Frequency adjustment is performed using hardware with a 24 bit
* accumulator and a programmable correction value. On each clk, the
* correction value gets added to the accumulator and when it
* overflows, the time counter is incremented/decremented.
*
* So conversion from ppb to correction value is
* ppb * (1 << 24) / 1000000000
*/
correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
TG3_EAV_REF_CLK_CORRECT_MASK;
tg3_full_lock(tp, 0);
if (correction)
tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
TG3_EAV_REF_CLK_CORRECT_EN |
(neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
else
tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
tg3_full_unlock(tp);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
bool neg_adj = false;
u32 correction = 0;
if (ppb < 0) {
neg_adj = true;
ppb = -ppb;
}
/* Frequency adjustment is performed using hardware with a 24 bit
* accumulator and a programmable correction value. On each clk, the
* correction value gets added to the accumulator and when it
* overflows, the time counter is incremented/decremented.
*
* So conversion from ppb to correction value is
* ppb * (1 << 24) / 1000000000
*/
correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
TG3_EAV_REF_CLK_CORRECT_MASK;
tg3_full_lock(tp, 0);
if (correction)
tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
TG3_EAV_REF_CLK_CORRECT_EN |
(neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
else
tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
tg3_full_unlock(tp);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,210 | static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
tg3_full_lock(tp, 0);
tp->ptp_adjust += delta;
tg3_full_unlock(tp);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
tg3_full_lock(tp, 0);
tp->ptp_adjust += delta;
tg3_full_unlock(tp);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,211 | static int tg3_ptp_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
return -EOPNOTSUPP;
}
| DoS Exec Code Overflow | 0 | static int tg3_ptp_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
return -EOPNOTSUPP;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,212 | static void tg3_ptp_fini(struct tg3 *tp)
{
if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
return;
ptp_clock_unregister(tp->ptp_clock);
tp->ptp_clock = NULL;
tp->ptp_adjust = 0;
}
| DoS Exec Code Overflow | 0 | static void tg3_ptp_fini(struct tg3 *tp)
{
if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
return;
ptp_clock_unregister(tp->ptp_clock);
tp->ptp_clock = NULL;
tp->ptp_adjust = 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,213 | static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
u64 ns;
u32 remainder;
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
tg3_full_lock(tp, 0);
ns = tg3_refclk_read(tp);
ns += tp->ptp_adjust;
tg3_full_unlock(tp);
ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
ts->tv_nsec = remainder;
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
u64 ns;
u32 remainder;
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
tg3_full_lock(tp, 0);
ns = tg3_refclk_read(tp);
ns += tp->ptp_adjust;
tg3_full_unlock(tp);
ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
ts->tv_nsec = remainder;
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,214 | static void tg3_ptp_init(struct tg3 *tp)
{
if (!tg3_flag(tp, PTP_CAPABLE))
return;
/* Initialize the hardware clock to the system time. */
tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
tp->ptp_adjust = 0;
tp->ptp_info = tg3_ptp_caps;
}
| DoS Exec Code Overflow | 0 | static void tg3_ptp_init(struct tg3 *tp)
{
if (!tg3_flag(tp, PTP_CAPABLE))
return;
/* Initialize the hardware clock to the system time. */
tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
tp->ptp_adjust = 0;
tp->ptp_info = tg3_ptp_caps;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,215 | static void tg3_ptp_resume(struct tg3 *tp)
{
if (!tg3_flag(tp, PTP_CAPABLE))
return;
tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
tp->ptp_adjust = 0;
}
| DoS Exec Code Overflow | 0 | static void tg3_ptp_resume(struct tg3 *tp)
{
if (!tg3_flag(tp, PTP_CAPABLE))
return;
tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
tp->ptp_adjust = 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,216 | static int tg3_ptp_settime(struct ptp_clock_info *ptp,
const struct timespec *ts)
{
u64 ns;
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
ns = timespec_to_ns(ts);
tg3_full_lock(tp, 0);
tg3_refclk_write(tp, ns);
tp->ptp_adjust = 0;
tg3_full_unlock(tp);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_ptp_settime(struct ptp_clock_info *ptp,
const struct timespec *ts)
{
u64 ns;
struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
ns = timespec_to_ns(ts);
tg3_full_lock(tp, 0);
tg3_refclk_write(tp, ns);
tp->ptp_adjust = 0;
tg3_full_unlock(tp);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,217 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
{
u32 grc_local_ctrl;
if (!tg3_flag(tp, IS_NIC) ||
tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701)
return;
grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
tw32_wait_f(GRC_LOCAL_CTRL,
grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
TG3_GRC_LCLCTL_PWRSW_DELAY);
tw32_wait_f(GRC_LOCAL_CTRL,
grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
tw32_wait_f(GRC_LOCAL_CTRL,
grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
| DoS Exec Code Overflow | 0 | static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
{
u32 grc_local_ctrl;
if (!tg3_flag(tp, IS_NIC) ||
tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701)
return;
grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
tw32_wait_f(GRC_LOCAL_CTRL,
grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
TG3_GRC_LCLCTL_PWRSW_DELAY);
tw32_wait_f(GRC_LOCAL_CTRL,
grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
tw32_wait_f(GRC_LOCAL_CTRL,
grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,218 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
{
if (!tg3_flag(tp, IS_NIC))
return;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1),
TG3_GRC_LCLCTL_PWRSW_DELAY);
} else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
/* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1 |
tp->grc_local_ctrl;
tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
} else {
u32 no_gpio2;
u32 grc_local_ctrl = 0;
/* Workaround to prevent overdrawing Amps. */
if (tg3_asic_rev(tp) == ASIC_REV_5714) {
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
/* On 5753 and variants, GPIO2 cannot be used. */
no_gpio2 = tp->nic_sram_data_cfg &
NIC_SRAM_DATA_CFG_NO_GPIO2;
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT1 |
GRC_LCLCTRL_GPIO_OUTPUT2;
if (no_gpio2) {
grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT2);
}
tw32_wait_f(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
tw32_wait_f(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
if (!no_gpio2) {
grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
tw32_wait_f(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
}
}
| DoS Exec Code Overflow | 0 | static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
{
if (!tg3_flag(tp, IS_NIC))
return;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
(GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1),
TG3_GRC_LCLCTL_PWRSW_DELAY);
} else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
/* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT0 |
GRC_LCLCTRL_GPIO_OUTPUT1 |
tp->grc_local_ctrl;
tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
} else {
u32 no_gpio2;
u32 grc_local_ctrl = 0;
/* Workaround to prevent overdrawing Amps. */
if (tg3_asic_rev(tp) == ASIC_REV_5714) {
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
/* On 5753 and variants, GPIO2 cannot be used. */
no_gpio2 = tp->nic_sram_data_cfg &
NIC_SRAM_DATA_CFG_NO_GPIO2;
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT1 |
GRC_LCLCTRL_GPIO_OUTPUT2;
if (no_gpio2) {
grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
GRC_LCLCTRL_GPIO_OUTPUT2);
}
tw32_wait_f(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
tw32_wait_f(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
if (!no_gpio2) {
grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
tw32_wait_f(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,219 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
{
if (!tg3_flag(tp, IS_NIC))
return 0;
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719 ||
tg3_asic_rev(tp) == ASIC_REV_5720) {
if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
return -EIO;
tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
} else {
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
return 0;
}
| DoS Exec Code Overflow | 0 | static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
{
if (!tg3_flag(tp, IS_NIC))
return 0;
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719 ||
tg3_asic_rev(tp) == ASIC_REV_5720) {
if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
return -EIO;
tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
} else {
tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
TG3_GRC_LCLCTL_PWRSW_DELAY);
}
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,220 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
{
int i;
dst = (u32 *)((u8 *)dst + off);
for (i = 0; i < len; i += sizeof(u32))
*dst++ = tr32(off + i);
}
| DoS Exec Code Overflow | 0 | static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
{
int i;
dst = (u32 *)((u8 *)dst + off);
for (i = 0; i < len; i += sizeof(u32))
*dst++ = tr32(off + i);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,221 | static u32 tg3_read32(struct tg3 *tp, u32 off)
{
return readl(tp->regs + off);
}
| DoS Exec Code Overflow | 0 | static u32 tg3_read32(struct tg3 *tp, u32 off)
{
return readl(tp->regs + off);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,222 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
{
return readl(tp->regs + off + GRCMBOX_BASE);
}
| DoS Exec Code Overflow | 0 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
{
return readl(tp->regs + off + GRCMBOX_BASE);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,223 | static void tg3_read_bc_ver(struct tg3 *tp)
{
u32 val, offset, start, ver_offset;
int i, dst_off;
bool newver = false;
if (tg3_nvram_read(tp, 0xc, &offset) ||
tg3_nvram_read(tp, 0x4, &start))
return;
offset = tg3_nvram_logical_addr(tp, offset);
if (tg3_nvram_read(tp, offset, &val))
return;
if ((val & 0xfc000000) == 0x0c000000) {
if (tg3_nvram_read(tp, offset + 4, &val))
return;
if (val == 0)
newver = true;
}
dst_off = strlen(tp->fw_ver);
if (newver) {
if (TG3_VER_SIZE - dst_off < 16 ||
tg3_nvram_read(tp, offset + 8, &ver_offset))
return;
offset = offset + ver_offset - start;
for (i = 0; i < 16; i += 4) {
__be32 v;
if (tg3_nvram_read_be32(tp, offset + i, &v))
return;
memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
}
} else {
u32 major, minor;
if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
return;
major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
TG3_NVM_BCVER_MAJSFT;
minor = ver_offset & TG3_NVM_BCVER_MINMSK;
snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
"v%d.%02d", major, minor);
}
}
| DoS Exec Code Overflow | 0 | static void tg3_read_bc_ver(struct tg3 *tp)
{
u32 val, offset, start, ver_offset;
int i, dst_off;
bool newver = false;
if (tg3_nvram_read(tp, 0xc, &offset) ||
tg3_nvram_read(tp, 0x4, &start))
return;
offset = tg3_nvram_logical_addr(tp, offset);
if (tg3_nvram_read(tp, offset, &val))
return;
if ((val & 0xfc000000) == 0x0c000000) {
if (tg3_nvram_read(tp, offset + 4, &val))
return;
if (val == 0)
newver = true;
}
dst_off = strlen(tp->fw_ver);
if (newver) {
if (TG3_VER_SIZE - dst_off < 16 ||
tg3_nvram_read(tp, offset + 8, &ver_offset))
return;
offset = offset + ver_offset - start;
for (i = 0; i < 16; i += 4) {
__be32 v;
if (tg3_nvram_read_be32(tp, offset + i, &v))
return;
memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
}
} else {
u32 major, minor;
if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
return;
major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
TG3_NVM_BCVER_MAJSFT;
minor = ver_offset & TG3_NVM_BCVER_MINMSK;
snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
"v%d.%02d", major, minor);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,224 | static void tg3_read_dash_ver(struct tg3 *tp)
{
int vlen;
u32 apedata;
char *fwtype;
apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
if (tg3_flag(tp, APE_HAS_NCSI))
fwtype = "NCSI";
else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
fwtype = "SMASH";
else
fwtype = "DASH";
vlen = strlen(tp->fw_ver);
snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
fwtype,
(apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
(apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
(apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
(apedata & APE_FW_VERSION_BLDMSK));
}
| DoS Exec Code Overflow | 0 | static void tg3_read_dash_ver(struct tg3 *tp)
{
int vlen;
u32 apedata;
char *fwtype;
apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
if (tg3_flag(tp, APE_HAS_NCSI))
fwtype = "NCSI";
else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
fwtype = "SMASH";
else
fwtype = "DASH";
vlen = strlen(tp->fw_ver);
snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
fwtype,
(apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
(apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
(apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
(apedata & APE_FW_VERSION_BLDMSK));
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,225 | static void tg3_read_hwsb_ver(struct tg3 *tp)
{
u32 val, major, minor;
/* Use native endian representation */
if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
return;
major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
TG3_NVM_HWSB_CFG1_MAJSFT;
minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
TG3_NVM_HWSB_CFG1_MINSFT;
snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
}
| DoS Exec Code Overflow | 0 | static void tg3_read_hwsb_ver(struct tg3 *tp)
{
u32 val, major, minor;
/* Use native endian representation */
if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
return;
major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
TG3_NVM_HWSB_CFG1_MAJSFT;
minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
TG3_NVM_HWSB_CFG1_MINSFT;
snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,226 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&tp->indirect_lock, flags);
pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
spin_unlock_irqrestore(&tp->indirect_lock, flags);
return val;
}
| DoS Exec Code Overflow | 0 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&tp->indirect_lock, flags);
pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
spin_unlock_irqrestore(&tp->indirect_lock, flags);
return val;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,227 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&tp->indirect_lock, flags);
pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
spin_unlock_irqrestore(&tp->indirect_lock, flags);
return val;
}
| DoS Exec Code Overflow | 0 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&tp->indirect_lock, flags);
pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
spin_unlock_irqrestore(&tp->indirect_lock, flags);
return val;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,228 | static void tg3_read_mgmtfw_ver(struct tg3 *tp)
{
u32 val, offset, start;
int i, vlen;
for (offset = TG3_NVM_DIR_START;
offset < TG3_NVM_DIR_END;
offset += TG3_NVM_DIRENT_SIZE) {
if (tg3_nvram_read(tp, offset, &val))
return;
if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
break;
}
if (offset == TG3_NVM_DIR_END)
return;
if (!tg3_flag(tp, 5705_PLUS))
start = 0x08000000;
else if (tg3_nvram_read(tp, offset - 4, &start))
return;
if (tg3_nvram_read(tp, offset + 4, &offset) ||
!tg3_fw_img_is_valid(tp, offset) ||
tg3_nvram_read(tp, offset + 8, &val))
return;
offset += val - start;
vlen = strlen(tp->fw_ver);
tp->fw_ver[vlen++] = ',';
tp->fw_ver[vlen++] = ' ';
for (i = 0; i < 4; i++) {
__be32 v;
if (tg3_nvram_read_be32(tp, offset, &v))
return;
offset += sizeof(v);
if (vlen > TG3_VER_SIZE - sizeof(v)) {
memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
break;
}
memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
vlen += sizeof(v);
}
}
| DoS Exec Code Overflow | 0 | static void tg3_read_mgmtfw_ver(struct tg3 *tp)
{
u32 val, offset, start;
int i, vlen;
for (offset = TG3_NVM_DIR_START;
offset < TG3_NVM_DIR_END;
offset += TG3_NVM_DIRENT_SIZE) {
if (tg3_nvram_read(tp, offset, &val))
return;
if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
break;
}
if (offset == TG3_NVM_DIR_END)
return;
if (!tg3_flag(tp, 5705_PLUS))
start = 0x08000000;
else if (tg3_nvram_read(tp, offset - 4, &start))
return;
if (tg3_nvram_read(tp, offset + 4, &offset) ||
!tg3_fw_img_is_valid(tp, offset) ||
tg3_nvram_read(tp, offset + 8, &val))
return;
offset += val - start;
vlen = strlen(tp->fw_ver);
tp->fw_ver[vlen++] = ',';
tp->fw_ver[vlen++] = ' ';
for (i = 0; i < 4; i++) {
__be32 v;
if (tg3_nvram_read_be32(tp, offset, &v))
return;
offset += sizeof(v);
if (vlen > TG3_VER_SIZE - sizeof(v)) {
memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
break;
}
memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
vlen += sizeof(v);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,229 | static u32 tg3_read_otp_phycfg(struct tg3 *tp)
{
u32 bhalf_otp, thalf_otp;
tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
return 0;
tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
return 0;
thalf_otp = tr32(OTP_READ_DATA);
tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
return 0;
bhalf_otp = tr32(OTP_READ_DATA);
return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
}
| DoS Exec Code Overflow | 0 | static u32 tg3_read_otp_phycfg(struct tg3 *tp)
{
u32 bhalf_otp, thalf_otp;
tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
return 0;
tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
return 0;
thalf_otp = tr32(OTP_READ_DATA);
tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
return 0;
bhalf_otp = tr32(OTP_READ_DATA);
return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,230 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
{
return __tg3_readphy(tp, tp->phy_addr, reg, val);
}
| DoS Exec Code Overflow | 0 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
{
return __tg3_readphy(tp, tp->phy_addr, reg, val);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,231 | static void tg3_recycle_rx(struct tg3_napi *tnapi,
struct tg3_rx_prodring_set *dpr,
u32 opaque_key, int src_idx,
u32 dest_idx_unmasked)
{
struct tg3 *tp = tnapi->tp;
struct tg3_rx_buffer_desc *src_desc, *dest_desc;
struct ring_info *src_map, *dest_map;
struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
int dest_idx;
switch (opaque_key) {
case RXD_OPAQUE_RING_STD:
dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
dest_desc = &dpr->rx_std[dest_idx];
dest_map = &dpr->rx_std_buffers[dest_idx];
src_desc = &spr->rx_std[src_idx];
src_map = &spr->rx_std_buffers[src_idx];
break;
case RXD_OPAQUE_RING_JUMBO:
dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
dest_desc = &dpr->rx_jmb[dest_idx].std;
dest_map = &dpr->rx_jmb_buffers[dest_idx];
src_desc = &spr->rx_jmb[src_idx].std;
src_map = &spr->rx_jmb_buffers[src_idx];
break;
default:
return;
}
dest_map->data = src_map->data;
dma_unmap_addr_set(dest_map, mapping,
dma_unmap_addr(src_map, mapping));
dest_desc->addr_hi = src_desc->addr_hi;
dest_desc->addr_lo = src_desc->addr_lo;
/* Ensure that the update to the skb happens after the physical
* addresses have been transferred to the new BD location.
*/
smp_wmb();
src_map->data = NULL;
}
| DoS Exec Code Overflow | 0 | static void tg3_recycle_rx(struct tg3_napi *tnapi,
struct tg3_rx_prodring_set *dpr,
u32 opaque_key, int src_idx,
u32 dest_idx_unmasked)
{
struct tg3 *tp = tnapi->tp;
struct tg3_rx_buffer_desc *src_desc, *dest_desc;
struct ring_info *src_map, *dest_map;
struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
int dest_idx;
switch (opaque_key) {
case RXD_OPAQUE_RING_STD:
dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
dest_desc = &dpr->rx_std[dest_idx];
dest_map = &dpr->rx_std_buffers[dest_idx];
src_desc = &spr->rx_std[src_idx];
src_map = &spr->rx_std_buffers[src_idx];
break;
case RXD_OPAQUE_RING_JUMBO:
dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
dest_desc = &dpr->rx_jmb[dest_idx].std;
dest_map = &dpr->rx_jmb_buffers[dest_idx];
src_desc = &spr->rx_jmb[src_idx].std;
src_map = &spr->rx_jmb_buffers[src_idx];
break;
default:
return;
}
dest_map->data = src_map->data;
dma_unmap_addr_set(dest_map, mapping,
dma_unmap_addr(src_map, mapping));
dest_desc->addr_hi = src_desc->addr_hi;
dest_desc->addr_lo = src_desc->addr_lo;
/* Ensure that the update to the skb happens after the physical
* addresses have been transferred to the new BD location.
*/
smp_wmb();
src_map->data = NULL;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,232 | static u64 tg3_refclk_read(struct tg3 *tp)
{
u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
}
| DoS Exec Code Overflow | 0 | static u64 tg3_refclk_read(struct tg3 *tp)
{
u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,233 | static void tg3_refclk_write(struct tg3 *tp, u64 newval)
{
tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
}
| DoS Exec Code Overflow | 0 | static void tg3_refclk_write(struct tg3 *tp, u64 newval)
{
tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,234 | static int tg3_request_firmware(struct tg3 *tp)
{
const __be32 *fw_data;
if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
tp->fw_needed);
return -ENOENT;
}
fw_data = (void *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by
* start address and _full_ length including BSS sections
* (which must be longer than the actual data, of course
*/
tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
if (tp->fw_len < (tp->fw->size - 12)) {
netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
tp->fw_len, tp->fw_needed);
release_firmware(tp->fw);
tp->fw = NULL;
return -EINVAL;
}
/* We no longer need firmware; we have it. */
tp->fw_needed = NULL;
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_request_firmware(struct tg3 *tp)
{
const __be32 *fw_data;
if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
tp->fw_needed);
return -ENOENT;
}
fw_data = (void *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by
* start address and _full_ length including BSS sections
* (which must be longer than the actual data, of course
*/
tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
if (tp->fw_len < (tp->fw->size - 12)) {
netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
tp->fw_len, tp->fw_needed);
release_firmware(tp->fw);
tp->fw = NULL;
return -EINVAL;
}
/* We no longer need firmware; we have it. */
tp->fw_needed = NULL;
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,235 | static int tg3_request_irq(struct tg3 *tp, int irq_num)
{
irq_handler_t fn;
unsigned long flags;
char *name;
struct tg3_napi *tnapi = &tp->napi[irq_num];
if (tp->irq_cnt == 1)
name = tp->dev->name;
else {
name = &tnapi->irq_lbl[0];
snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
name[IFNAMSIZ-1] = 0;
}
if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fn = tg3_msi;
if (tg3_flag(tp, 1SHOT_MSI))
fn = tg3_msi_1shot;
flags = 0;
} else {
fn = tg3_interrupt;
if (tg3_flag(tp, TAGGED_STATUS))
fn = tg3_interrupt_tagged;
flags = IRQF_SHARED;
}
return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
}
| DoS Exec Code Overflow | 0 | static int tg3_request_irq(struct tg3 *tp, int irq_num)
{
irq_handler_t fn;
unsigned long flags;
char *name;
struct tg3_napi *tnapi = &tp->napi[irq_num];
if (tp->irq_cnt == 1)
name = tp->dev->name;
else {
name = &tnapi->irq_lbl[0];
snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
name[IFNAMSIZ-1] = 0;
}
if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fn = tg3_msi;
if (tg3_flag(tp, 1SHOT_MSI))
fn = tg3_msi_1shot;
flags = 0;
} else {
fn = tg3_interrupt;
if (tg3_flag(tp, TAGGED_STATUS))
fn = tg3_interrupt_tagged;
flags = IRQF_SHARED;
}
return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,236 | static void tg3_reset_task(struct work_struct *work)
{
struct tg3 *tp = container_of(work, struct tg3, reset_task);
int err;
tg3_full_lock(tp, 0);
if (!netif_running(tp->dev)) {
tg3_flag_clear(tp, RESET_TASK_PENDING);
tg3_full_unlock(tp);
return;
}
tg3_full_unlock(tp);
tg3_phy_stop(tp);
tg3_netif_stop(tp);
tg3_full_lock(tp, 1);
if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
tp->write32_tx_mbox = tg3_write32_tx_mbox;
tp->write32_rx_mbox = tg3_write_flush_reg32;
tg3_flag_set(tp, MBOX_WRITE_REORDER);
tg3_flag_clear(tp, TX_RECOVERY_PENDING);
}
tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
err = tg3_init_hw(tp, 1);
if (err)
goto out;
tg3_netif_start(tp);
out:
tg3_full_unlock(tp);
if (!err)
tg3_phy_start(tp);
tg3_flag_clear(tp, RESET_TASK_PENDING);
}
| DoS Exec Code Overflow | 0 | static void tg3_reset_task(struct work_struct *work)
{
struct tg3 *tp = container_of(work, struct tg3, reset_task);
int err;
tg3_full_lock(tp, 0);
if (!netif_running(tp->dev)) {
tg3_flag_clear(tp, RESET_TASK_PENDING);
tg3_full_unlock(tp);
return;
}
tg3_full_unlock(tp);
tg3_phy_stop(tp);
tg3_netif_stop(tp);
tg3_full_lock(tp, 1);
if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
tp->write32_tx_mbox = tg3_write32_tx_mbox;
tp->write32_rx_mbox = tg3_write_flush_reg32;
tg3_flag_set(tp, MBOX_WRITE_REORDER);
tg3_flag_clear(tp, TX_RECOVERY_PENDING);
}
tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
err = tg3_init_hw(tp, 1);
if (err)
goto out;
tg3_netif_start(tp);
out:
tg3_full_unlock(tp);
if (!err)
tg3_phy_start(tp);
tg3_flag_clear(tp, RESET_TASK_PENDING);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,237 | static inline void tg3_reset_task_cancel(struct tg3 *tp)
{
cancel_work_sync(&tp->reset_task);
tg3_flag_clear(tp, RESET_TASK_PENDING);
tg3_flag_clear(tp, TX_RECOVERY_PENDING);
}
| DoS Exec Code Overflow | 0 | static inline void tg3_reset_task_cancel(struct tg3 *tp)
{
cancel_work_sync(&tp->reset_task);
tg3_flag_clear(tp, RESET_TASK_PENDING);
tg3_flag_clear(tp, TX_RECOVERY_PENDING);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,238 | static inline void tg3_reset_task_schedule(struct tg3 *tp)
{
if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
schedule_work(&tp->reset_task);
}
| DoS Exec Code Overflow | 0 | static inline void tg3_reset_task_schedule(struct tg3 *tp)
{
if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
schedule_work(&tp->reset_task);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,239 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
{
u8 cap = 0;
if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
} else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
if (lcladv & ADVERTISE_1000XPAUSE)
cap = FLOW_CTRL_RX;
if (rmtadv & ADVERTISE_1000XPAUSE)
cap = FLOW_CTRL_TX;
}
return cap;
}
| DoS Exec Code Overflow | 0 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
{
u8 cap = 0;
if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
} else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
if (lcladv & ADVERTISE_1000XPAUSE)
cap = FLOW_CTRL_RX;
if (rmtadv & ADVERTISE_1000XPAUSE)
cap = FLOW_CTRL_TX;
}
return cap;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,240 | static void tg3_restore_pci_state(struct tg3 *tp)
{
u32 val;
/* Re-enable indirect register accesses. */
pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
tp->misc_host_ctrl);
/* Set MAX PCI retry to zero. */
val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
tg3_flag(tp, PCIX_MODE))
val |= PCISTATE_RETRY_SAME_DMA;
/* Allow reads and writes to the APE register and memory space. */
if (tg3_flag(tp, ENABLE_APE))
val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
PCISTATE_ALLOW_APE_SHMEM_WR |
PCISTATE_ALLOW_APE_PSPACE_WR;
pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
if (!tg3_flag(tp, PCI_EXPRESS)) {
pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
tp->pci_cacheline_sz);
pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
tp->pci_lat_timer);
}
/* Make sure PCI-X relaxed ordering bit is clear. */
if (tg3_flag(tp, PCIX_MODE)) {
u16 pcix_cmd;
pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
&pcix_cmd);
pcix_cmd &= ~PCI_X_CMD_ERO;
pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
pcix_cmd);
}
if (tg3_flag(tp, 5780_CLASS)) {
/* Chip reset on 5780 will reset MSI enable bit,
* so need to restore it.
*/
if (tg3_flag(tp, USING_MSI)) {
u16 ctrl;
pci_read_config_word(tp->pdev,
tp->msi_cap + PCI_MSI_FLAGS,
&ctrl);
pci_write_config_word(tp->pdev,
tp->msi_cap + PCI_MSI_FLAGS,
ctrl | PCI_MSI_FLAGS_ENABLE);
val = tr32(MSGINT_MODE);
tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
}
}
}
| DoS Exec Code Overflow | 0 | static void tg3_restore_pci_state(struct tg3 *tp)
{
u32 val;
/* Re-enable indirect register accesses. */
pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
tp->misc_host_ctrl);
/* Set MAX PCI retry to zero. */
val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
tg3_flag(tp, PCIX_MODE))
val |= PCISTATE_RETRY_SAME_DMA;
/* Allow reads and writes to the APE register and memory space. */
if (tg3_flag(tp, ENABLE_APE))
val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
PCISTATE_ALLOW_APE_SHMEM_WR |
PCISTATE_ALLOW_APE_PSPACE_WR;
pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
if (!tg3_flag(tp, PCI_EXPRESS)) {
pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
tp->pci_cacheline_sz);
pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
tp->pci_lat_timer);
}
/* Make sure PCI-X relaxed ordering bit is clear. */
if (tg3_flag(tp, PCIX_MODE)) {
u16 pcix_cmd;
pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
&pcix_cmd);
pcix_cmd &= ~PCI_X_CMD_ERO;
pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
pcix_cmd);
}
if (tg3_flag(tp, 5780_CLASS)) {
/* Chip reset on 5780 will reset MSI enable bit,
* so need to restore it.
*/
if (tg3_flag(tp, USING_MSI)) {
u16 ctrl;
pci_read_config_word(tp->pdev,
tp->msi_cap + PCI_MSI_FLAGS,
&ctrl);
pci_write_config_word(tp->pdev,
tp->msi_cap + PCI_MSI_FLAGS,
ctrl | PCI_MSI_FLAGS_ENABLE);
val = tr32(MSGINT_MODE);
tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
}
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,241 | static int tg3_resume(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
struct net_device *dev = pci_get_drvdata(pdev);
struct tg3 *tp = netdev_priv(dev);
int err;
if (!netif_running(dev))
return 0;
netif_device_attach(dev);
tg3_full_lock(tp, 0);
tg3_flag_set(tp, INIT_COMPLETE);
err = tg3_restart_hw(tp, 1);
if (err)
goto out;
tg3_timer_start(tp);
tg3_netif_start(tp);
out:
tg3_full_unlock(tp);
if (!err)
tg3_phy_start(tp);
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_resume(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
struct net_device *dev = pci_get_drvdata(pdev);
struct tg3 *tp = netdev_priv(dev);
int err;
if (!netif_running(dev))
return 0;
netif_device_attach(dev);
tg3_full_lock(tp, 0);
tg3_flag_set(tp, INIT_COMPLETE);
err = tg3_restart_hw(tp, 1);
if (err)
goto out;
tg3_timer_start(tp);
tg3_netif_start(tp);
out:
tg3_full_unlock(tp);
if (!err)
tg3_phy_start(tp);
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,242 | static void tg3_rings_reset(struct tg3 *tp)
{
int i;
u32 stblk, txrcb, rxrcb, limit;
struct tg3_napi *tnapi = &tp->napi[0];
/* Disable all transmit rings but the first. */
if (!tg3_flag(tp, 5705_PLUS))
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
else if (tg3_flag(tp, 5717_PLUS))
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
else if (tg3_flag(tp, 57765_CLASS) ||
tg3_asic_rev(tp) == ASIC_REV_5762)
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
else
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
txrcb < limit; txrcb += TG3_BDINFO_SIZE)
tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
BDINFO_FLAGS_DISABLED);
/* Disable all receive return rings but the first. */
if (tg3_flag(tp, 5717_PLUS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
else if (!tg3_flag(tp, 5705_PLUS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
tg3_asic_rev(tp) == ASIC_REV_5762 ||
tg3_flag(tp, 57765_CLASS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
else
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
BDINFO_FLAGS_DISABLED);
/* Disable interrupts */
tw32_mailbox_f(tp->napi[0].int_mbox, 1);
tp->napi[0].chk_msi_cnt = 0;
tp->napi[0].last_rx_cons = 0;
tp->napi[0].last_tx_cons = 0;
/* Zero mailbox registers. */
if (tg3_flag(tp, SUPPORT_MSIX)) {
for (i = 1; i < tp->irq_max; i++) {
tp->napi[i].tx_prod = 0;
tp->napi[i].tx_cons = 0;
if (tg3_flag(tp, ENABLE_TSS))
tw32_mailbox(tp->napi[i].prodmbox, 0);
tw32_rx_mbox(tp->napi[i].consmbox, 0);
tw32_mailbox_f(tp->napi[i].int_mbox, 1);
tp->napi[i].chk_msi_cnt = 0;
tp->napi[i].last_rx_cons = 0;
tp->napi[i].last_tx_cons = 0;
}
if (!tg3_flag(tp, ENABLE_TSS))
tw32_mailbox(tp->napi[0].prodmbox, 0);
} else {
tp->napi[0].tx_prod = 0;
tp->napi[0].tx_cons = 0;
tw32_mailbox(tp->napi[0].prodmbox, 0);
tw32_rx_mbox(tp->napi[0].consmbox, 0);
}
/* Make sure the NIC-based send BD rings are disabled. */
if (!tg3_flag(tp, 5705_PLUS)) {
u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
for (i = 0; i < 16; i++)
tw32_tx_mbox(mbox + i * 8, 0);
}
txrcb = NIC_SRAM_SEND_RCB;
rxrcb = NIC_SRAM_RCV_RET_RCB;
/* Clear status block in ram. */
memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
/* Set status block DMA address */
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
((u64) tnapi->status_mapping >> 32));
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
((u64) tnapi->status_mapping & 0xffffffff));
if (tnapi->tx_ring) {
tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
(TG3_TX_RING_SIZE <<
BDINFO_FLAGS_MAXLEN_SHIFT),
NIC_SRAM_TX_BUFFER_DESC);
txrcb += TG3_BDINFO_SIZE;
}
if (tnapi->rx_rcb) {
tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
(tp->rx_ret_ring_mask + 1) <<
BDINFO_FLAGS_MAXLEN_SHIFT, 0);
rxrcb += TG3_BDINFO_SIZE;
}
stblk = HOSTCC_STATBLCK_RING1;
for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
u64 mapping = (u64)tnapi->status_mapping;
tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
/* Clear status block in ram. */
memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
if (tnapi->tx_ring) {
tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
(TG3_TX_RING_SIZE <<
BDINFO_FLAGS_MAXLEN_SHIFT),
NIC_SRAM_TX_BUFFER_DESC);
txrcb += TG3_BDINFO_SIZE;
}
tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
((tp->rx_ret_ring_mask + 1) <<
BDINFO_FLAGS_MAXLEN_SHIFT), 0);
stblk += 8;
rxrcb += TG3_BDINFO_SIZE;
}
}
| DoS Exec Code Overflow | 0 | static void tg3_rings_reset(struct tg3 *tp)
{
int i;
u32 stblk, txrcb, rxrcb, limit;
struct tg3_napi *tnapi = &tp->napi[0];
/* Disable all transmit rings but the first. */
if (!tg3_flag(tp, 5705_PLUS))
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
else if (tg3_flag(tp, 5717_PLUS))
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
else if (tg3_flag(tp, 57765_CLASS) ||
tg3_asic_rev(tp) == ASIC_REV_5762)
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
else
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
txrcb < limit; txrcb += TG3_BDINFO_SIZE)
tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
BDINFO_FLAGS_DISABLED);
/* Disable all receive return rings but the first. */
if (tg3_flag(tp, 5717_PLUS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
else if (!tg3_flag(tp, 5705_PLUS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
tg3_asic_rev(tp) == ASIC_REV_5762 ||
tg3_flag(tp, 57765_CLASS))
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
else
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
BDINFO_FLAGS_DISABLED);
/* Disable interrupts */
tw32_mailbox_f(tp->napi[0].int_mbox, 1);
tp->napi[0].chk_msi_cnt = 0;
tp->napi[0].last_rx_cons = 0;
tp->napi[0].last_tx_cons = 0;
/* Zero mailbox registers. */
if (tg3_flag(tp, SUPPORT_MSIX)) {
for (i = 1; i < tp->irq_max; i++) {
tp->napi[i].tx_prod = 0;
tp->napi[i].tx_cons = 0;
if (tg3_flag(tp, ENABLE_TSS))
tw32_mailbox(tp->napi[i].prodmbox, 0);
tw32_rx_mbox(tp->napi[i].consmbox, 0);
tw32_mailbox_f(tp->napi[i].int_mbox, 1);
tp->napi[i].chk_msi_cnt = 0;
tp->napi[i].last_rx_cons = 0;
tp->napi[i].last_tx_cons = 0;
}
if (!tg3_flag(tp, ENABLE_TSS))
tw32_mailbox(tp->napi[0].prodmbox, 0);
} else {
tp->napi[0].tx_prod = 0;
tp->napi[0].tx_cons = 0;
tw32_mailbox(tp->napi[0].prodmbox, 0);
tw32_rx_mbox(tp->napi[0].consmbox, 0);
}
/* Make sure the NIC-based send BD rings are disabled. */
if (!tg3_flag(tp, 5705_PLUS)) {
u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
for (i = 0; i < 16; i++)
tw32_tx_mbox(mbox + i * 8, 0);
}
txrcb = NIC_SRAM_SEND_RCB;
rxrcb = NIC_SRAM_RCV_RET_RCB;
/* Clear status block in ram. */
memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
/* Set status block DMA address */
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
((u64) tnapi->status_mapping >> 32));
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
((u64) tnapi->status_mapping & 0xffffffff));
if (tnapi->tx_ring) {
tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
(TG3_TX_RING_SIZE <<
BDINFO_FLAGS_MAXLEN_SHIFT),
NIC_SRAM_TX_BUFFER_DESC);
txrcb += TG3_BDINFO_SIZE;
}
if (tnapi->rx_rcb) {
tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
(tp->rx_ret_ring_mask + 1) <<
BDINFO_FLAGS_MAXLEN_SHIFT, 0);
rxrcb += TG3_BDINFO_SIZE;
}
stblk = HOSTCC_STATBLCK_RING1;
for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
u64 mapping = (u64)tnapi->status_mapping;
tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
/* Clear status block in ram. */
memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
if (tnapi->tx_ring) {
tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
(TG3_TX_RING_SIZE <<
BDINFO_FLAGS_MAXLEN_SHIFT),
NIC_SRAM_TX_BUFFER_DESC);
txrcb += TG3_BDINFO_SIZE;
}
tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
((tp->rx_ret_ring_mask + 1) <<
BDINFO_FLAGS_MAXLEN_SHIFT), 0);
stblk += 8;
rxrcb += TG3_BDINFO_SIZE;
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,243 | static void tg3_rss_check_indir_tbl(struct tg3 *tp)
{
int i;
if (!tg3_flag(tp, SUPPORT_MSIX))
return;
if (tp->rxq_cnt == 1) {
memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
return;
}
/* Validate table against current IRQ count */
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
break;
}
if (i != TG3_RSS_INDIR_TBL_SIZE)
tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
}
| DoS Exec Code Overflow | 0 | static void tg3_rss_check_indir_tbl(struct tg3 *tp)
{
int i;
if (!tg3_flag(tp, SUPPORT_MSIX))
return;
if (tp->rxq_cnt == 1) {
memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
return;
}
/* Validate table against current IRQ count */
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
break;
}
if (i != TG3_RSS_INDIR_TBL_SIZE)
tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,244 | static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
{
int i;
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
}
| DoS Exec Code Overflow | 0 | static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
{
int i;
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,245 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
{
u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
u32 budget;
struct sk_buff *skb;
u8 *tx_data, *rx_data;
dma_addr_t map;
int num_pkts, tx_len, rx_len, i, err;
struct tg3_rx_buffer_desc *desc;
struct tg3_napi *tnapi, *rnapi;
struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
tnapi = &tp->napi[0];
rnapi = &tp->napi[0];
if (tp->irq_cnt > 1) {
if (tg3_flag(tp, ENABLE_RSS))
rnapi = &tp->napi[1];
if (tg3_flag(tp, ENABLE_TSS))
tnapi = &tp->napi[1];
}
coal_now = tnapi->coal_now | rnapi->coal_now;
err = -EIO;
tx_len = pktsz;
skb = netdev_alloc_skb(tp->dev, tx_len);
if (!skb)
return -ENOMEM;
tx_data = skb_put(skb, tx_len);
memcpy(tx_data, tp->dev->dev_addr, 6);
memset(tx_data + 6, 0x0, 8);
tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
if (tso_loopback) {
struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
TG3_TSO_TCP_OPT_LEN;
memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
sizeof(tg3_tso_header));
mss = TG3_TSO_MSS;
val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
/* Set the total length field in the IP header */
iph->tot_len = htons((u16)(mss + hdr_len));
base_flags = (TXD_FLAG_CPU_PRE_DMA |
TXD_FLAG_CPU_POST_DMA);
if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3)) {
struct tcphdr *th;
val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
th = (struct tcphdr *)&tx_data[val];
th->check = 0;
} else
base_flags |= TXD_FLAG_TCPUDP_CSUM;
if (tg3_flag(tp, HW_TSO_3)) {
mss |= (hdr_len & 0xc) << 12;
if (hdr_len & 0x10)
base_flags |= 0x00000010;
base_flags |= (hdr_len & 0x3e0) << 5;
} else if (tg3_flag(tp, HW_TSO_2))
mss |= hdr_len << 9;
else if (tg3_flag(tp, HW_TSO_1) ||
tg3_asic_rev(tp) == ASIC_REV_5705) {
mss |= (TG3_TSO_TCP_OPT_LEN << 9);
} else {
base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
}
data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
} else {
num_pkts = 1;
data_off = ETH_HLEN;
if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
tx_len > VLAN_ETH_FRAME_LEN)
base_flags |= TXD_FLAG_JMB_PKT;
}
for (i = data_off; i < tx_len; i++)
tx_data[i] = (u8) (i & 0xff);
map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
if (pci_dma_mapping_error(tp->pdev, map)) {
dev_kfree_skb(skb);
return -EIO;
}
val = tnapi->tx_prod;
tnapi->tx_buffers[val].skb = skb;
dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
rnapi->coal_now);
udelay(10);
rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
budget = tg3_tx_avail(tnapi);
if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
base_flags | TXD_FLAG_END, mss, 0)) {
tnapi->tx_buffers[val].skb = NULL;
dev_kfree_skb(skb);
return -EIO;
}
tnapi->tx_prod++;
/* Sync BD data before updating mailbox */
wmb();
tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
tr32_mailbox(tnapi->prodmbox);
udelay(10);
/* 350 usec to allow enough time on some 10/100 Mbps devices. */
for (i = 0; i < 35; i++) {
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
coal_now);
udelay(10);
tx_idx = tnapi->hw_status->idx[0].tx_consumer;
rx_idx = rnapi->hw_status->idx[0].rx_producer;
if ((tx_idx == tnapi->tx_prod) &&
(rx_idx == (rx_start_idx + num_pkts)))
break;
}
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
dev_kfree_skb(skb);
if (tx_idx != tnapi->tx_prod)
goto out;
if (rx_idx != rx_start_idx + num_pkts)
goto out;
val = data_off;
while (rx_idx != rx_start_idx) {
desc = &rnapi->rx_rcb[rx_start_idx++];
desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
(desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
goto out;
rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
- ETH_FCS_LEN;
if (!tso_loopback) {
if (rx_len != tx_len)
goto out;
if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
if (opaque_key != RXD_OPAQUE_RING_STD)
goto out;
} else {
if (opaque_key != RXD_OPAQUE_RING_JUMBO)
goto out;
}
} else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
(desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
>> RXD_TCPCSUM_SHIFT != 0xffff) {
goto out;
}
if (opaque_key == RXD_OPAQUE_RING_STD) {
rx_data = tpr->rx_std_buffers[desc_idx].data;
map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
mapping);
} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
rx_data = tpr->rx_jmb_buffers[desc_idx].data;
map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
mapping);
} else
goto out;
pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
PCI_DMA_FROMDEVICE);
rx_data += TG3_RX_OFFSET(tp);
for (i = data_off; i < rx_len; i++, val++) {
if (*(rx_data + i) != (u8) (val & 0xff))
goto out;
}
}
err = 0;
/* tg3_free_rings will unmap and free the rx_data */
out:
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
{
u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
u32 budget;
struct sk_buff *skb;
u8 *tx_data, *rx_data;
dma_addr_t map;
int num_pkts, tx_len, rx_len, i, err;
struct tg3_rx_buffer_desc *desc;
struct tg3_napi *tnapi, *rnapi;
struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
tnapi = &tp->napi[0];
rnapi = &tp->napi[0];
if (tp->irq_cnt > 1) {
if (tg3_flag(tp, ENABLE_RSS))
rnapi = &tp->napi[1];
if (tg3_flag(tp, ENABLE_TSS))
tnapi = &tp->napi[1];
}
coal_now = tnapi->coal_now | rnapi->coal_now;
err = -EIO;
tx_len = pktsz;
skb = netdev_alloc_skb(tp->dev, tx_len);
if (!skb)
return -ENOMEM;
tx_data = skb_put(skb, tx_len);
memcpy(tx_data, tp->dev->dev_addr, 6);
memset(tx_data + 6, 0x0, 8);
tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
if (tso_loopback) {
struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
TG3_TSO_TCP_OPT_LEN;
memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
sizeof(tg3_tso_header));
mss = TG3_TSO_MSS;
val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
/* Set the total length field in the IP header */
iph->tot_len = htons((u16)(mss + hdr_len));
base_flags = (TXD_FLAG_CPU_PRE_DMA |
TXD_FLAG_CPU_POST_DMA);
if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3)) {
struct tcphdr *th;
val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
th = (struct tcphdr *)&tx_data[val];
th->check = 0;
} else
base_flags |= TXD_FLAG_TCPUDP_CSUM;
if (tg3_flag(tp, HW_TSO_3)) {
mss |= (hdr_len & 0xc) << 12;
if (hdr_len & 0x10)
base_flags |= 0x00000010;
base_flags |= (hdr_len & 0x3e0) << 5;
} else if (tg3_flag(tp, HW_TSO_2))
mss |= hdr_len << 9;
else if (tg3_flag(tp, HW_TSO_1) ||
tg3_asic_rev(tp) == ASIC_REV_5705) {
mss |= (TG3_TSO_TCP_OPT_LEN << 9);
} else {
base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
}
data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
} else {
num_pkts = 1;
data_off = ETH_HLEN;
if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
tx_len > VLAN_ETH_FRAME_LEN)
base_flags |= TXD_FLAG_JMB_PKT;
}
for (i = data_off; i < tx_len; i++)
tx_data[i] = (u8) (i & 0xff);
map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
if (pci_dma_mapping_error(tp->pdev, map)) {
dev_kfree_skb(skb);
return -EIO;
}
val = tnapi->tx_prod;
tnapi->tx_buffers[val].skb = skb;
dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
rnapi->coal_now);
udelay(10);
rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
budget = tg3_tx_avail(tnapi);
if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
base_flags | TXD_FLAG_END, mss, 0)) {
tnapi->tx_buffers[val].skb = NULL;
dev_kfree_skb(skb);
return -EIO;
}
tnapi->tx_prod++;
/* Sync BD data before updating mailbox */
wmb();
tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
tr32_mailbox(tnapi->prodmbox);
udelay(10);
/* 350 usec to allow enough time on some 10/100 Mbps devices. */
for (i = 0; i < 35; i++) {
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
coal_now);
udelay(10);
tx_idx = tnapi->hw_status->idx[0].tx_consumer;
rx_idx = rnapi->hw_status->idx[0].rx_producer;
if ((tx_idx == tnapi->tx_prod) &&
(rx_idx == (rx_start_idx + num_pkts)))
break;
}
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
dev_kfree_skb(skb);
if (tx_idx != tnapi->tx_prod)
goto out;
if (rx_idx != rx_start_idx + num_pkts)
goto out;
val = data_off;
while (rx_idx != rx_start_idx) {
desc = &rnapi->rx_rcb[rx_start_idx++];
desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
(desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
goto out;
rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
- ETH_FCS_LEN;
if (!tso_loopback) {
if (rx_len != tx_len)
goto out;
if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
if (opaque_key != RXD_OPAQUE_RING_STD)
goto out;
} else {
if (opaque_key != RXD_OPAQUE_RING_JUMBO)
goto out;
}
} else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
(desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
>> RXD_TCPCSUM_SHIFT != 0xffff) {
goto out;
}
if (opaque_key == RXD_OPAQUE_RING_STD) {
rx_data = tpr->rx_std_buffers[desc_idx].data;
map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
mapping);
} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
rx_data = tpr->rx_jmb_buffers[desc_idx].data;
map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
mapping);
} else
goto out;
pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
PCI_DMA_FROMDEVICE);
rx_data += TG3_RX_OFFSET(tp);
for (i = data_off; i < rx_len; i++, val++) {
if (*(rx_data + i) != (u8) (val & 0xff))
goto out;
}
}
err = 0;
/* tg3_free_rings will unmap and free the rx_data */
out:
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,246 | static int tg3_rx(struct tg3_napi *tnapi, int budget)
{
struct tg3 *tp = tnapi->tp;
u32 work_mask, rx_std_posted = 0;
u32 std_prod_idx, jmb_prod_idx;
u32 sw_idx = tnapi->rx_rcb_ptr;
u16 hw_idx;
int received;
struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
hw_idx = *(tnapi->rx_rcb_prod_idx);
/*
* We need to order the read of hw_idx and the read of
* the opaque cookie.
*/
rmb();
work_mask = 0;
received = 0;
std_prod_idx = tpr->rx_std_prod_idx;
jmb_prod_idx = tpr->rx_jmb_prod_idx;
while (sw_idx != hw_idx && budget > 0) {
struct ring_info *ri;
struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
unsigned int len;
struct sk_buff *skb;
dma_addr_t dma_addr;
u32 opaque_key, desc_idx, *post_ptr;
u8 *data;
u64 tstamp = 0;
desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
if (opaque_key == RXD_OPAQUE_RING_STD) {
ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
dma_addr = dma_unmap_addr(ri, mapping);
data = ri->data;
post_ptr = &std_prod_idx;
rx_std_posted++;
} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
dma_addr = dma_unmap_addr(ri, mapping);
data = ri->data;
post_ptr = &jmb_prod_idx;
} else
goto next_pkt_nopost;
work_mask |= opaque_key;
if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
(desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
drop_it:
tg3_recycle_rx(tnapi, tpr, opaque_key,
desc_idx, *post_ptr);
drop_it_no_recycle:
/* Other statistics kept track of by card. */
tp->rx_dropped++;
goto next_pkt;
}
prefetch(data + TG3_RX_OFFSET(tp));
len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
ETH_FCS_LEN;
if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
RXD_FLAG_PTPSTAT_PTPV1 ||
(desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
RXD_FLAG_PTPSTAT_PTPV2) {
tstamp = tr32(TG3_RX_TSTAMP_LSB);
tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
}
if (len > TG3_RX_COPY_THRESH(tp)) {
int skb_size;
unsigned int frag_size;
skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
*post_ptr, &frag_size);
if (skb_size < 0)
goto drop_it;
pci_unmap_single(tp->pdev, dma_addr, skb_size,
PCI_DMA_FROMDEVICE);
skb = build_skb(data, frag_size);
if (!skb) {
tg3_frag_free(frag_size != 0, data);
goto drop_it_no_recycle;
}
skb_reserve(skb, TG3_RX_OFFSET(tp));
/* Ensure that the update to the data happens
* after the usage of the old DMA mapping.
*/
smp_wmb();
ri->data = NULL;
} else {
tg3_recycle_rx(tnapi, tpr, opaque_key,
desc_idx, *post_ptr);
skb = netdev_alloc_skb(tp->dev,
len + TG3_RAW_IP_ALIGN);
if (skb == NULL)
goto drop_it_no_recycle;
skb_reserve(skb, TG3_RAW_IP_ALIGN);
pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
memcpy(skb->data,
data + TG3_RX_OFFSET(tp),
len);
pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
}
skb_put(skb, len);
if (tstamp)
tg3_hwclock_to_timestamp(tp, tstamp,
skb_hwtstamps(skb));
if ((tp->dev->features & NETIF_F_RXCSUM) &&
(desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
(((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
>> RXD_TCPCSUM_SHIFT) == 0xffff))
skb->ip_summed = CHECKSUM_UNNECESSARY;
else
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, tp->dev);
if (len > (tp->dev->mtu + ETH_HLEN) &&
skb->protocol != htons(ETH_P_8021Q)) {
dev_kfree_skb(skb);
goto drop_it_no_recycle;
}
if (desc->type_flags & RXD_FLAG_VLAN &&
!(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
__vlan_hwaccel_put_tag(skb,
desc->err_vlan & RXD_VLAN_MASK);
napi_gro_receive(&tnapi->napi, skb);
received++;
budget--;
next_pkt:
(*post_ptr)++;
if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
tpr->rx_std_prod_idx = std_prod_idx &
tp->rx_std_ring_mask;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
tpr->rx_std_prod_idx);
work_mask &= ~RXD_OPAQUE_RING_STD;
rx_std_posted = 0;
}
next_pkt_nopost:
sw_idx++;
sw_idx &= tp->rx_ret_ring_mask;
/* Refresh hw_idx to see if there is new work */
if (sw_idx == hw_idx) {
hw_idx = *(tnapi->rx_rcb_prod_idx);
rmb();
}
}
/* ACK the status ring. */
tnapi->rx_rcb_ptr = sw_idx;
tw32_rx_mbox(tnapi->consmbox, sw_idx);
/* Refill RX ring(s). */
if (!tg3_flag(tp, ENABLE_RSS)) {
/* Sync BD data before updating mailbox */
wmb();
if (work_mask & RXD_OPAQUE_RING_STD) {
tpr->rx_std_prod_idx = std_prod_idx &
tp->rx_std_ring_mask;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
tpr->rx_std_prod_idx);
}
if (work_mask & RXD_OPAQUE_RING_JUMBO) {
tpr->rx_jmb_prod_idx = jmb_prod_idx &
tp->rx_jmb_ring_mask;
tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
tpr->rx_jmb_prod_idx);
}
mmiowb();
} else if (work_mask) {
/* rx_std_buffers[] and rx_jmb_buffers[] entries must be
* updated before the producer indices can be updated.
*/
smp_wmb();
tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
if (tnapi != &tp->napi[1]) {
tp->rx_refill = true;
napi_schedule(&tp->napi[1].napi);
}
}
return received;
}
| DoS Exec Code Overflow | 0 | static int tg3_rx(struct tg3_napi *tnapi, int budget)
{
struct tg3 *tp = tnapi->tp;
u32 work_mask, rx_std_posted = 0;
u32 std_prod_idx, jmb_prod_idx;
u32 sw_idx = tnapi->rx_rcb_ptr;
u16 hw_idx;
int received;
struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
hw_idx = *(tnapi->rx_rcb_prod_idx);
/*
* We need to order the read of hw_idx and the read of
* the opaque cookie.
*/
rmb();
work_mask = 0;
received = 0;
std_prod_idx = tpr->rx_std_prod_idx;
jmb_prod_idx = tpr->rx_jmb_prod_idx;
while (sw_idx != hw_idx && budget > 0) {
struct ring_info *ri;
struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
unsigned int len;
struct sk_buff *skb;
dma_addr_t dma_addr;
u32 opaque_key, desc_idx, *post_ptr;
u8 *data;
u64 tstamp = 0;
desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
if (opaque_key == RXD_OPAQUE_RING_STD) {
ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
dma_addr = dma_unmap_addr(ri, mapping);
data = ri->data;
post_ptr = &std_prod_idx;
rx_std_posted++;
} else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
dma_addr = dma_unmap_addr(ri, mapping);
data = ri->data;
post_ptr = &jmb_prod_idx;
} else
goto next_pkt_nopost;
work_mask |= opaque_key;
if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
(desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
drop_it:
tg3_recycle_rx(tnapi, tpr, opaque_key,
desc_idx, *post_ptr);
drop_it_no_recycle:
/* Other statistics kept track of by card. */
tp->rx_dropped++;
goto next_pkt;
}
prefetch(data + TG3_RX_OFFSET(tp));
len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
ETH_FCS_LEN;
if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
RXD_FLAG_PTPSTAT_PTPV1 ||
(desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
RXD_FLAG_PTPSTAT_PTPV2) {
tstamp = tr32(TG3_RX_TSTAMP_LSB);
tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
}
if (len > TG3_RX_COPY_THRESH(tp)) {
int skb_size;
unsigned int frag_size;
skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
*post_ptr, &frag_size);
if (skb_size < 0)
goto drop_it;
pci_unmap_single(tp->pdev, dma_addr, skb_size,
PCI_DMA_FROMDEVICE);
skb = build_skb(data, frag_size);
if (!skb) {
tg3_frag_free(frag_size != 0, data);
goto drop_it_no_recycle;
}
skb_reserve(skb, TG3_RX_OFFSET(tp));
/* Ensure that the update to the data happens
* after the usage of the old DMA mapping.
*/
smp_wmb();
ri->data = NULL;
} else {
tg3_recycle_rx(tnapi, tpr, opaque_key,
desc_idx, *post_ptr);
skb = netdev_alloc_skb(tp->dev,
len + TG3_RAW_IP_ALIGN);
if (skb == NULL)
goto drop_it_no_recycle;
skb_reserve(skb, TG3_RAW_IP_ALIGN);
pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
memcpy(skb->data,
data + TG3_RX_OFFSET(tp),
len);
pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
}
skb_put(skb, len);
if (tstamp)
tg3_hwclock_to_timestamp(tp, tstamp,
skb_hwtstamps(skb));
if ((tp->dev->features & NETIF_F_RXCSUM) &&
(desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
(((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
>> RXD_TCPCSUM_SHIFT) == 0xffff))
skb->ip_summed = CHECKSUM_UNNECESSARY;
else
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, tp->dev);
if (len > (tp->dev->mtu + ETH_HLEN) &&
skb->protocol != htons(ETH_P_8021Q)) {
dev_kfree_skb(skb);
goto drop_it_no_recycle;
}
if (desc->type_flags & RXD_FLAG_VLAN &&
!(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
__vlan_hwaccel_put_tag(skb,
desc->err_vlan & RXD_VLAN_MASK);
napi_gro_receive(&tnapi->napi, skb);
received++;
budget--;
next_pkt:
(*post_ptr)++;
if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
tpr->rx_std_prod_idx = std_prod_idx &
tp->rx_std_ring_mask;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
tpr->rx_std_prod_idx);
work_mask &= ~RXD_OPAQUE_RING_STD;
rx_std_posted = 0;
}
next_pkt_nopost:
sw_idx++;
sw_idx &= tp->rx_ret_ring_mask;
/* Refresh hw_idx to see if there is new work */
if (sw_idx == hw_idx) {
hw_idx = *(tnapi->rx_rcb_prod_idx);
rmb();
}
}
/* ACK the status ring. */
tnapi->rx_rcb_ptr = sw_idx;
tw32_rx_mbox(tnapi->consmbox, sw_idx);
/* Refill RX ring(s). */
if (!tg3_flag(tp, ENABLE_RSS)) {
/* Sync BD data before updating mailbox */
wmb();
if (work_mask & RXD_OPAQUE_RING_STD) {
tpr->rx_std_prod_idx = std_prod_idx &
tp->rx_std_ring_mask;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
tpr->rx_std_prod_idx);
}
if (work_mask & RXD_OPAQUE_RING_JUMBO) {
tpr->rx_jmb_prod_idx = jmb_prod_idx &
tp->rx_jmb_ring_mask;
tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
tpr->rx_jmb_prod_idx);
}
mmiowb();
} else if (work_mask) {
/* rx_std_buffers[] and rx_jmb_buffers[] entries must be
* updated before the producer indices can be updated.
*/
smp_wmb();
tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
if (tnapi != &tp->napi[1]) {
tp->rx_refill = true;
napi_schedule(&tp->napi[1].napi);
}
}
return received;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,247 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
{
unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
if (!ri->data)
return;
pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
map_sz, PCI_DMA_FROMDEVICE);
tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
ri->data = NULL;
}
| DoS Exec Code Overflow | 0 | static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
{
unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
if (!ri->data)
return;
pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
map_sz, PCI_DMA_FROMDEVICE);
tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
ri->data = NULL;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,248 | static int tg3_rx_prodring_alloc(struct tg3 *tp,
struct tg3_rx_prodring_set *tpr)
{
u32 i, rx_pkt_dma_sz;
tpr->rx_std_cons_idx = 0;
tpr->rx_std_prod_idx = 0;
tpr->rx_jmb_cons_idx = 0;
tpr->rx_jmb_prod_idx = 0;
if (tpr != &tp->napi[0].prodring) {
memset(&tpr->rx_std_buffers[0], 0,
TG3_RX_STD_BUFF_RING_SIZE(tp));
if (tpr->rx_jmb_buffers)
memset(&tpr->rx_jmb_buffers[0], 0,
TG3_RX_JMB_BUFF_RING_SIZE(tp));
goto done;
}
/* Zero out all descriptors. */
memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
if (tg3_flag(tp, 5780_CLASS) &&
tp->dev->mtu > ETH_DATA_LEN)
rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
/* Initialize invariants of the rings, we only set this
* stuff once. This works because the card does not
* write into the rx buffer posting rings.
*/
for (i = 0; i <= tp->rx_std_ring_mask; i++) {
struct tg3_rx_buffer_desc *rxd;
rxd = &tpr->rx_std[i];
rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
rxd->opaque = (RXD_OPAQUE_RING_STD |
(i << RXD_OPAQUE_INDEX_SHIFT));
}
/* Now allocate fresh SKBs for each rx ring. */
for (i = 0; i < tp->rx_pending; i++) {
unsigned int frag_size;
if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
&frag_size) < 0) {
netdev_warn(tp->dev,
"Using a smaller RX standard ring. Only "
"%d out of %d buffers were allocated "
"successfully\n", i, tp->rx_pending);
if (i == 0)
goto initfail;
tp->rx_pending = i;
break;
}
}
if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
goto done;
memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
if (!tg3_flag(tp, JUMBO_RING_ENABLE))
goto done;
for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
struct tg3_rx_buffer_desc *rxd;
rxd = &tpr->rx_jmb[i].std;
rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
RXD_FLAG_JUMBO;
rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
(i << RXD_OPAQUE_INDEX_SHIFT));
}
for (i = 0; i < tp->rx_jumbo_pending; i++) {
unsigned int frag_size;
if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
&frag_size) < 0) {
netdev_warn(tp->dev,
"Using a smaller RX jumbo ring. Only %d "
"out of %d buffers were allocated "
"successfully\n", i, tp->rx_jumbo_pending);
if (i == 0)
goto initfail;
tp->rx_jumbo_pending = i;
break;
}
}
done:
return 0;
initfail:
tg3_rx_prodring_free(tp, tpr);
return -ENOMEM;
}
| DoS Exec Code Overflow | 0 | static int tg3_rx_prodring_alloc(struct tg3 *tp,
struct tg3_rx_prodring_set *tpr)
{
u32 i, rx_pkt_dma_sz;
tpr->rx_std_cons_idx = 0;
tpr->rx_std_prod_idx = 0;
tpr->rx_jmb_cons_idx = 0;
tpr->rx_jmb_prod_idx = 0;
if (tpr != &tp->napi[0].prodring) {
memset(&tpr->rx_std_buffers[0], 0,
TG3_RX_STD_BUFF_RING_SIZE(tp));
if (tpr->rx_jmb_buffers)
memset(&tpr->rx_jmb_buffers[0], 0,
TG3_RX_JMB_BUFF_RING_SIZE(tp));
goto done;
}
/* Zero out all descriptors. */
memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
if (tg3_flag(tp, 5780_CLASS) &&
tp->dev->mtu > ETH_DATA_LEN)
rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
/* Initialize invariants of the rings, we only set this
* stuff once. This works because the card does not
* write into the rx buffer posting rings.
*/
for (i = 0; i <= tp->rx_std_ring_mask; i++) {
struct tg3_rx_buffer_desc *rxd;
rxd = &tpr->rx_std[i];
rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
rxd->opaque = (RXD_OPAQUE_RING_STD |
(i << RXD_OPAQUE_INDEX_SHIFT));
}
/* Now allocate fresh SKBs for each rx ring. */
for (i = 0; i < tp->rx_pending; i++) {
unsigned int frag_size;
if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
&frag_size) < 0) {
netdev_warn(tp->dev,
"Using a smaller RX standard ring. Only "
"%d out of %d buffers were allocated "
"successfully\n", i, tp->rx_pending);
if (i == 0)
goto initfail;
tp->rx_pending = i;
break;
}
}
if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
goto done;
memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
if (!tg3_flag(tp, JUMBO_RING_ENABLE))
goto done;
for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
struct tg3_rx_buffer_desc *rxd;
rxd = &tpr->rx_jmb[i].std;
rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
RXD_FLAG_JUMBO;
rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
(i << RXD_OPAQUE_INDEX_SHIFT));
}
for (i = 0; i < tp->rx_jumbo_pending; i++) {
unsigned int frag_size;
if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
&frag_size) < 0) {
netdev_warn(tp->dev,
"Using a smaller RX jumbo ring. Only %d "
"out of %d buffers were allocated "
"successfully\n", i, tp->rx_jumbo_pending);
if (i == 0)
goto initfail;
tp->rx_jumbo_pending = i;
break;
}
}
done:
return 0;
initfail:
tg3_rx_prodring_free(tp, tpr);
return -ENOMEM;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,249 | static void tg3_rx_prodring_free(struct tg3 *tp,
struct tg3_rx_prodring_set *tpr)
{
int i;
if (tpr != &tp->napi[0].prodring) {
for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
i = (i + 1) & tp->rx_std_ring_mask)
tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
tp->rx_pkt_map_sz);
if (tg3_flag(tp, JUMBO_CAPABLE)) {
for (i = tpr->rx_jmb_cons_idx;
i != tpr->rx_jmb_prod_idx;
i = (i + 1) & tp->rx_jmb_ring_mask) {
tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
TG3_RX_JMB_MAP_SZ);
}
}
return;
}
for (i = 0; i <= tp->rx_std_ring_mask; i++)
tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
tp->rx_pkt_map_sz);
if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
TG3_RX_JMB_MAP_SZ);
}
}
| DoS Exec Code Overflow | 0 | static void tg3_rx_prodring_free(struct tg3 *tp,
struct tg3_rx_prodring_set *tpr)
{
int i;
if (tpr != &tp->napi[0].prodring) {
for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
i = (i + 1) & tp->rx_std_ring_mask)
tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
tp->rx_pkt_map_sz);
if (tg3_flag(tp, JUMBO_CAPABLE)) {
for (i = tpr->rx_jmb_cons_idx;
i != tpr->rx_jmb_prod_idx;
i = (i + 1) & tp->rx_jmb_ring_mask) {
tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
TG3_RX_JMB_MAP_SZ);
}
}
return;
}
for (i = 0; i <= tp->rx_std_ring_mask; i++)
tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
tp->rx_pkt_map_sz);
if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
TG3_RX_JMB_MAP_SZ);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,250 | static int tg3_rx_prodring_xfer(struct tg3 *tp,
struct tg3_rx_prodring_set *dpr,
struct tg3_rx_prodring_set *spr)
{
u32 si, di, cpycnt, src_prod_idx;
int i, err = 0;
while (1) {
src_prod_idx = spr->rx_std_prod_idx;
/* Make sure updates to the rx_std_buffers[] entries and the
* standard producer index are seen in the correct order.
*/
smp_rmb();
if (spr->rx_std_cons_idx == src_prod_idx)
break;
if (spr->rx_std_cons_idx < src_prod_idx)
cpycnt = src_prod_idx - spr->rx_std_cons_idx;
else
cpycnt = tp->rx_std_ring_mask + 1 -
spr->rx_std_cons_idx;
cpycnt = min(cpycnt,
tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
si = spr->rx_std_cons_idx;
di = dpr->rx_std_prod_idx;
for (i = di; i < di + cpycnt; i++) {
if (dpr->rx_std_buffers[i].data) {
cpycnt = i - di;
err = -ENOSPC;
break;
}
}
if (!cpycnt)
break;
/* Ensure that updates to the rx_std_buffers ring and the
* shadowed hardware producer ring from tg3_recycle_skb() are
* ordered correctly WRT the skb check above.
*/
smp_rmb();
memcpy(&dpr->rx_std_buffers[di],
&spr->rx_std_buffers[si],
cpycnt * sizeof(struct ring_info));
for (i = 0; i < cpycnt; i++, di++, si++) {
struct tg3_rx_buffer_desc *sbd, *dbd;
sbd = &spr->rx_std[si];
dbd = &dpr->rx_std[di];
dbd->addr_hi = sbd->addr_hi;
dbd->addr_lo = sbd->addr_lo;
}
spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
tp->rx_std_ring_mask;
dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
tp->rx_std_ring_mask;
}
while (1) {
src_prod_idx = spr->rx_jmb_prod_idx;
/* Make sure updates to the rx_jmb_buffers[] entries and
* the jumbo producer index are seen in the correct order.
*/
smp_rmb();
if (spr->rx_jmb_cons_idx == src_prod_idx)
break;
if (spr->rx_jmb_cons_idx < src_prod_idx)
cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
else
cpycnt = tp->rx_jmb_ring_mask + 1 -
spr->rx_jmb_cons_idx;
cpycnt = min(cpycnt,
tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
si = spr->rx_jmb_cons_idx;
di = dpr->rx_jmb_prod_idx;
for (i = di; i < di + cpycnt; i++) {
if (dpr->rx_jmb_buffers[i].data) {
cpycnt = i - di;
err = -ENOSPC;
break;
}
}
if (!cpycnt)
break;
/* Ensure that updates to the rx_jmb_buffers ring and the
* shadowed hardware producer ring from tg3_recycle_skb() are
* ordered correctly WRT the skb check above.
*/
smp_rmb();
memcpy(&dpr->rx_jmb_buffers[di],
&spr->rx_jmb_buffers[si],
cpycnt * sizeof(struct ring_info));
for (i = 0; i < cpycnt; i++, di++, si++) {
struct tg3_rx_buffer_desc *sbd, *dbd;
sbd = &spr->rx_jmb[si].std;
dbd = &dpr->rx_jmb[di].std;
dbd->addr_hi = sbd->addr_hi;
dbd->addr_lo = sbd->addr_lo;
}
spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
tp->rx_jmb_ring_mask;
dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
tp->rx_jmb_ring_mask;
}
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_rx_prodring_xfer(struct tg3 *tp,
struct tg3_rx_prodring_set *dpr,
struct tg3_rx_prodring_set *spr)
{
u32 si, di, cpycnt, src_prod_idx;
int i, err = 0;
while (1) {
src_prod_idx = spr->rx_std_prod_idx;
/* Make sure updates to the rx_std_buffers[] entries and the
* standard producer index are seen in the correct order.
*/
smp_rmb();
if (spr->rx_std_cons_idx == src_prod_idx)
break;
if (spr->rx_std_cons_idx < src_prod_idx)
cpycnt = src_prod_idx - spr->rx_std_cons_idx;
else
cpycnt = tp->rx_std_ring_mask + 1 -
spr->rx_std_cons_idx;
cpycnt = min(cpycnt,
tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
si = spr->rx_std_cons_idx;
di = dpr->rx_std_prod_idx;
for (i = di; i < di + cpycnt; i++) {
if (dpr->rx_std_buffers[i].data) {
cpycnt = i - di;
err = -ENOSPC;
break;
}
}
if (!cpycnt)
break;
/* Ensure that updates to the rx_std_buffers ring and the
* shadowed hardware producer ring from tg3_recycle_skb() are
* ordered correctly WRT the skb check above.
*/
smp_rmb();
memcpy(&dpr->rx_std_buffers[di],
&spr->rx_std_buffers[si],
cpycnt * sizeof(struct ring_info));
for (i = 0; i < cpycnt; i++, di++, si++) {
struct tg3_rx_buffer_desc *sbd, *dbd;
sbd = &spr->rx_std[si];
dbd = &dpr->rx_std[di];
dbd->addr_hi = sbd->addr_hi;
dbd->addr_lo = sbd->addr_lo;
}
spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
tp->rx_std_ring_mask;
dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
tp->rx_std_ring_mask;
}
while (1) {
src_prod_idx = spr->rx_jmb_prod_idx;
/* Make sure updates to the rx_jmb_buffers[] entries and
* the jumbo producer index are seen in the correct order.
*/
smp_rmb();
if (spr->rx_jmb_cons_idx == src_prod_idx)
break;
if (spr->rx_jmb_cons_idx < src_prod_idx)
cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
else
cpycnt = tp->rx_jmb_ring_mask + 1 -
spr->rx_jmb_cons_idx;
cpycnt = min(cpycnt,
tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
si = spr->rx_jmb_cons_idx;
di = dpr->rx_jmb_prod_idx;
for (i = di; i < di + cpycnt; i++) {
if (dpr->rx_jmb_buffers[i].data) {
cpycnt = i - di;
err = -ENOSPC;
break;
}
}
if (!cpycnt)
break;
/* Ensure that updates to the rx_jmb_buffers ring and the
* shadowed hardware producer ring from tg3_recycle_skb() are
* ordered correctly WRT the skb check above.
*/
smp_rmb();
memcpy(&dpr->rx_jmb_buffers[di],
&spr->rx_jmb_buffers[si],
cpycnt * sizeof(struct ring_info));
for (i = 0; i < cpycnt; i++, di++, si++) {
struct tg3_rx_buffer_desc *sbd, *dbd;
sbd = &spr->rx_jmb[si].std;
dbd = &dpr->rx_jmb[di].std;
dbd->addr_hi = sbd->addr_hi;
dbd->addr_lo = sbd->addr_lo;
}
spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
tp->rx_jmb_ring_mask;
dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
tp->rx_jmb_ring_mask;
}
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,251 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
{
if (tg3_flag(tp, LRG_PROD_RING_CAP))
return TG3_RX_RET_MAX_SIZE_5717;
else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
return TG3_RX_RET_MAX_SIZE_5700;
else
return TG3_RX_RET_MAX_SIZE_5705;
}
| DoS Exec Code Overflow | 0 | static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
{
if (tg3_flag(tp, LRG_PROD_RING_CAP))
return TG3_RX_RET_MAX_SIZE_5717;
else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
return TG3_RX_RET_MAX_SIZE_5700;
else
return TG3_RX_RET_MAX_SIZE_5705;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,252 | static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
{
int i;
for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
off += len;
if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
!(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
memset(ocir, 0, TG3_OCIR_LEN);
}
}
| DoS Exec Code Overflow | 0 | static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
{
int i;
for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
off += len;
if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
!(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
memset(ocir, 0, TG3_OCIR_LEN);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,253 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
u64 *data)
{
struct tg3 *tp = netdev_priv(dev);
bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
tg3_power_up(tp)) {
etest->flags |= ETH_TEST_FL_FAILED;
memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
return;
}
memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
if (tg3_test_nvram(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_NVRAM_TEST] = 1;
}
if (!doextlpbk && tg3_test_link(tp)) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_LINK_TEST] = 1;
}
if (etest->flags & ETH_TEST_FL_OFFLINE) {
int err, err2 = 0, irq_sync = 0;
if (netif_running(dev)) {
tg3_phy_stop(tp);
tg3_netif_stop(tp);
irq_sync = 1;
}
tg3_full_lock(tp, irq_sync);
tg3_halt(tp, RESET_KIND_SUSPEND, 1);
err = tg3_nvram_lock(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
if (!tg3_flag(tp, 5705_PLUS))
tg3_halt_cpu(tp, TX_CPU_BASE);
if (!err)
tg3_nvram_unlock(tp);
if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
tg3_phy_reset(tp);
if (tg3_test_registers(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_REGISTER_TEST] = 1;
}
if (tg3_test_memory(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_MEMORY_TEST] = 1;
}
if (doextlpbk)
etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
if (tg3_test_loopback(tp, data, doextlpbk))
etest->flags |= ETH_TEST_FL_FAILED;
tg3_full_unlock(tp);
if (tg3_test_interrupt(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_INTERRUPT_TEST] = 1;
}
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
if (netif_running(dev)) {
tg3_flag_set(tp, INIT_COMPLETE);
err2 = tg3_restart_hw(tp, 1);
if (!err2)
tg3_netif_start(tp);
}
tg3_full_unlock(tp);
if (irq_sync && !err2)
tg3_phy_start(tp);
}
if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
tg3_power_down(tp);
}
| DoS Exec Code Overflow | 0 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
u64 *data)
{
struct tg3 *tp = netdev_priv(dev);
bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
tg3_power_up(tp)) {
etest->flags |= ETH_TEST_FL_FAILED;
memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
return;
}
memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
if (tg3_test_nvram(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_NVRAM_TEST] = 1;
}
if (!doextlpbk && tg3_test_link(tp)) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_LINK_TEST] = 1;
}
if (etest->flags & ETH_TEST_FL_OFFLINE) {
int err, err2 = 0, irq_sync = 0;
if (netif_running(dev)) {
tg3_phy_stop(tp);
tg3_netif_stop(tp);
irq_sync = 1;
}
tg3_full_lock(tp, irq_sync);
tg3_halt(tp, RESET_KIND_SUSPEND, 1);
err = tg3_nvram_lock(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
if (!tg3_flag(tp, 5705_PLUS))
tg3_halt_cpu(tp, TX_CPU_BASE);
if (!err)
tg3_nvram_unlock(tp);
if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
tg3_phy_reset(tp);
if (tg3_test_registers(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_REGISTER_TEST] = 1;
}
if (tg3_test_memory(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_MEMORY_TEST] = 1;
}
if (doextlpbk)
etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
if (tg3_test_loopback(tp, data, doextlpbk))
etest->flags |= ETH_TEST_FL_FAILED;
tg3_full_unlock(tp);
if (tg3_test_interrupt(tp) != 0) {
etest->flags |= ETH_TEST_FL_FAILED;
data[TG3_INTERRUPT_TEST] = 1;
}
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
if (netif_running(dev)) {
tg3_flag_set(tp, INIT_COMPLETE);
err2 = tg3_restart_hw(tp, 1);
if (!err2)
tg3_netif_start(tp);
}
tg3_full_unlock(tp);
if (irq_sync && !err2)
tg3_phy_start(tp);
}
if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
tg3_power_down(tp);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,254 | static void tg3_serdes_parallel_detect(struct tg3 *tp)
{
if (tp->serdes_counter) {
/* Give autoneg time to complete. */
tp->serdes_counter--;
return;
}
if (!tp->link_up &&
(tp->link_config.autoneg == AUTONEG_ENABLE)) {
u32 bmcr;
tg3_readphy(tp, MII_BMCR, &bmcr);
if (bmcr & BMCR_ANENABLE) {
u32 phy1, phy2;
/* Select shadow register 0x1f */
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
/* Select expansion interrupt status register */
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
MII_TG3_DSP_EXP1_INT_STAT);
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
if ((phy1 & 0x10) && !(phy2 & 0x20)) {
/* We have signal detect and not receiving
* config code words, link is up by parallel
* detection.
*/
bmcr &= ~BMCR_ANENABLE;
bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
tg3_writephy(tp, MII_BMCR, bmcr);
tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
}
}
} else if (tp->link_up &&
(tp->link_config.autoneg == AUTONEG_ENABLE) &&
(tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
u32 phy2;
/* Select expansion interrupt status register */
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
MII_TG3_DSP_EXP1_INT_STAT);
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
if (phy2 & 0x20) {
u32 bmcr;
/* Config code words received, turn on autoneg. */
tg3_readphy(tp, MII_BMCR, &bmcr);
tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
}
}
}
| DoS Exec Code Overflow | 0 | static void tg3_serdes_parallel_detect(struct tg3 *tp)
{
if (tp->serdes_counter) {
/* Give autoneg time to complete. */
tp->serdes_counter--;
return;
}
if (!tp->link_up &&
(tp->link_config.autoneg == AUTONEG_ENABLE)) {
u32 bmcr;
tg3_readphy(tp, MII_BMCR, &bmcr);
if (bmcr & BMCR_ANENABLE) {
u32 phy1, phy2;
/* Select shadow register 0x1f */
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
/* Select expansion interrupt status register */
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
MII_TG3_DSP_EXP1_INT_STAT);
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
if ((phy1 & 0x10) && !(phy2 & 0x20)) {
/* We have signal detect and not receiving
* config code words, link is up by parallel
* detection.
*/
bmcr &= ~BMCR_ANENABLE;
bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
tg3_writephy(tp, MII_BMCR, bmcr);
tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
}
}
} else if (tp->link_up &&
(tp->link_config.autoneg == AUTONEG_ENABLE) &&
(tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
u32 phy2;
/* Select expansion interrupt status register */
tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
MII_TG3_DSP_EXP1_INT_STAT);
tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
if (phy2 & 0x20) {
u32 bmcr;
/* Config code words received, turn on autoneg. */
tg3_readphy(tp, MII_BMCR, &bmcr);
tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
}
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,255 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
dma_addr_t mapping, u32 maxlen_flags,
u32 nic_addr)
{
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
((u64) mapping >> 32));
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
((u64) mapping & 0xffffffff));
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
maxlen_flags);
if (!tg3_flag(tp, 5705_PLUS))
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_NIC_ADDR),
nic_addr);
}
| DoS Exec Code Overflow | 0 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
dma_addr_t mapping, u32 maxlen_flags,
u32 nic_addr)
{
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
((u64) mapping >> 32));
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
((u64) mapping & 0xffffffff));
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
maxlen_flags);
if (!tg3_flag(tp, 5705_PLUS))
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_NIC_ADDR),
nic_addr);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,256 | static int tg3_set_channels(struct net_device *dev,
struct ethtool_channels *channel)
{
struct tg3 *tp = netdev_priv(dev);
if (!tg3_flag(tp, SUPPORT_MSIX))
return -EOPNOTSUPP;
if (channel->rx_count > tp->rxq_max ||
channel->tx_count > tp->txq_max)
return -EINVAL;
tp->rxq_req = channel->rx_count;
tp->txq_req = channel->tx_count;
if (!netif_running(dev))
return 0;
tg3_stop(tp);
tg3_carrier_off(tp);
tg3_start(tp, true, false, false);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_channels(struct net_device *dev,
struct ethtool_channels *channel)
{
struct tg3 *tp = netdev_priv(dev);
if (!tg3_flag(tp, SUPPORT_MSIX))
return -EOPNOTSUPP;
if (channel->rx_count > tp->rxq_max ||
channel->tx_count > tp->txq_max)
return -EINVAL;
tp->rxq_req = channel->rx_count;
tp->txq_req = channel->tx_count;
if (!netif_running(dev))
return 0;
tg3_stop(tp);
tg3_carrier_off(tp);
tg3_start(tp, true, false, false);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,257 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
{
struct tg3 *tp = netdev_priv(dev);
int ret;
u32 offset, len, b_offset, odd_len;
u8 *buf;
__be32 start, end;
if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
return -EAGAIN;
if (tg3_flag(tp, NO_NVRAM) ||
eeprom->magic != TG3_EEPROM_MAGIC)
return -EINVAL;
offset = eeprom->offset;
len = eeprom->len;
if ((b_offset = (offset & 3))) {
/* adjustments to start on required 4 byte boundary */
ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
if (ret)
return ret;
len += b_offset;
offset &= ~3;
if (len < 4)
len = 4;
}
odd_len = 0;
if (len & 3) {
/* adjustments to end on required 4 byte boundary */
odd_len = 1;
len = (len + 3) & ~3;
ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
if (ret)
return ret;
}
buf = data;
if (b_offset || odd_len) {
buf = kmalloc(len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
if (b_offset)
memcpy(buf, &start, 4);
if (odd_len)
memcpy(buf+len-4, &end, 4);
memcpy(buf + b_offset, data, eeprom->len);
}
ret = tg3_nvram_write_block(tp, offset, len, buf);
if (buf != data)
kfree(buf);
return ret;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
{
struct tg3 *tp = netdev_priv(dev);
int ret;
u32 offset, len, b_offset, odd_len;
u8 *buf;
__be32 start, end;
if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
return -EAGAIN;
if (tg3_flag(tp, NO_NVRAM) ||
eeprom->magic != TG3_EEPROM_MAGIC)
return -EINVAL;
offset = eeprom->offset;
len = eeprom->len;
if ((b_offset = (offset & 3))) {
/* adjustments to start on required 4 byte boundary */
ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
if (ret)
return ret;
len += b_offset;
offset &= ~3;
if (len < 4)
len = 4;
}
odd_len = 0;
if (len & 3) {
/* adjustments to end on required 4 byte boundary */
odd_len = 1;
len = (len + 3) & ~3;
ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
if (ret)
return ret;
}
buf = data;
if (b_offset || odd_len) {
buf = kmalloc(len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
if (b_offset)
memcpy(buf, &start, 4);
if (odd_len)
memcpy(buf+len-4, &end, 4);
memcpy(buf + b_offset, data, eeprom->len);
}
ret = tg3_nvram_write_block(tp, offset, len, buf);
if (buf != data)
kfree(buf);
return ret;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,258 | static int tg3_set_features(struct net_device *dev, netdev_features_t features)
{
netdev_features_t changed = dev->features ^ features;
if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
tg3_set_loopback(dev, features);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_features(struct net_device *dev, netdev_features_t features)
{
netdev_features_t changed = dev->features ^ features;
if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
tg3_set_loopback(dev, features);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,259 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
{
u32 status, shift;
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719)
status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
else
status = tr32(TG3_CPMU_DRV_STATUS);
shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
status &= ~(TG3_GPIO_MSG_MASK << shift);
status |= (newstat << shift);
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719)
tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
else
tw32(TG3_CPMU_DRV_STATUS, status);
return status >> TG3_APE_GPIO_MSG_SHIFT;
}
| DoS Exec Code Overflow | 0 | static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
{
u32 status, shift;
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719)
status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
else
status = tr32(TG3_CPMU_DRV_STATUS);
shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
status &= ~(TG3_GPIO_MSG_MASK << shift);
status |= (newstat << shift);
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719)
tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
else
tw32(TG3_CPMU_DRV_STATUS, status);
return status >> TG3_APE_GPIO_MSG_SHIFT;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,260 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
{
struct tg3 *tp = netdev_priv(dev);
if (features & NETIF_F_LOOPBACK) {
if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
return;
spin_lock_bh(&tp->lock);
tg3_mac_loopback(tp, true);
netif_carrier_on(tp->dev);
spin_unlock_bh(&tp->lock);
netdev_info(dev, "Internal MAC loopback mode enabled.\n");
} else {
if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
return;
spin_lock_bh(&tp->lock);
tg3_mac_loopback(tp, false);
/* Force link status check */
tg3_setup_phy(tp, 1);
spin_unlock_bh(&tp->lock);
netdev_info(dev, "Internal MAC loopback mode disabled.\n");
}
}
| DoS Exec Code Overflow | 0 | static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
{
struct tg3 *tp = netdev_priv(dev);
if (features & NETIF_F_LOOPBACK) {
if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
return;
spin_lock_bh(&tp->lock);
tg3_mac_loopback(tp, true);
netif_carrier_on(tp->dev);
spin_unlock_bh(&tp->lock);
netdev_info(dev, "Internal MAC loopback mode enabled.\n");
} else {
if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
return;
spin_lock_bh(&tp->lock);
tg3_mac_loopback(tp, false);
/* Force link status check */
tg3_setup_phy(tp, 1);
spin_unlock_bh(&tp->lock);
netdev_info(dev, "Internal MAC loopback mode disabled.\n");
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,261 | static int tg3_set_mac_addr(struct net_device *dev, void *p)
{
struct tg3 *tp = netdev_priv(dev);
struct sockaddr *addr = p;
int err = 0, skip_mac_1 = 0;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
if (!netif_running(dev))
return 0;
if (tg3_flag(tp, ENABLE_ASF)) {
u32 addr0_high, addr0_low, addr1_high, addr1_low;
addr0_high = tr32(MAC_ADDR_0_HIGH);
addr0_low = tr32(MAC_ADDR_0_LOW);
addr1_high = tr32(MAC_ADDR_1_HIGH);
addr1_low = tr32(MAC_ADDR_1_LOW);
/* Skip MAC addr 1 if ASF is using it. */
if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
!(addr1_high == 0 && addr1_low == 0))
skip_mac_1 = 1;
}
spin_lock_bh(&tp->lock);
__tg3_set_mac_addr(tp, skip_mac_1);
spin_unlock_bh(&tp->lock);
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_mac_addr(struct net_device *dev, void *p)
{
struct tg3 *tp = netdev_priv(dev);
struct sockaddr *addr = p;
int err = 0, skip_mac_1 = 0;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
if (!netif_running(dev))
return 0;
if (tg3_flag(tp, ENABLE_ASF)) {
u32 addr0_high, addr0_low, addr1_high, addr1_low;
addr0_high = tr32(MAC_ADDR_0_HIGH);
addr0_low = tr32(MAC_ADDR_0_LOW);
addr1_high = tr32(MAC_ADDR_1_HIGH);
addr1_low = tr32(MAC_ADDR_1_LOW);
/* Skip MAC addr 1 if ASF is using it. */
if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
!(addr1_high == 0 && addr1_low == 0))
skip_mac_1 = 1;
}
spin_lock_bh(&tp->lock);
__tg3_set_mac_addr(tp, skip_mac_1);
spin_unlock_bh(&tp->lock);
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,262 | static void tg3_set_msglevel(struct net_device *dev, u32 value)
{
struct tg3 *tp = netdev_priv(dev);
tp->msg_enable = value;
}
| DoS Exec Code Overflow | 0 | static void tg3_set_msglevel(struct net_device *dev, u32 value)
{
struct tg3 *tp = netdev_priv(dev);
tp->msg_enable = value;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,263 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
int new_mtu)
{
dev->mtu = new_mtu;
if (new_mtu > ETH_DATA_LEN) {
if (tg3_flag(tp, 5780_CLASS)) {
netdev_update_features(dev);
tg3_flag_clear(tp, TSO_CAPABLE);
} else {
tg3_flag_set(tp, JUMBO_RING_ENABLE);
}
} else {
if (tg3_flag(tp, 5780_CLASS)) {
tg3_flag_set(tp, TSO_CAPABLE);
netdev_update_features(dev);
}
tg3_flag_clear(tp, JUMBO_RING_ENABLE);
}
}
| DoS Exec Code Overflow | 0 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
int new_mtu)
{
dev->mtu = new_mtu;
if (new_mtu > ETH_DATA_LEN) {
if (tg3_flag(tp, 5780_CLASS)) {
netdev_update_features(dev);
tg3_flag_clear(tp, TSO_CAPABLE);
} else {
tg3_flag_set(tp, JUMBO_RING_ENABLE);
}
} else {
if (tg3_flag(tp, 5780_CLASS)) {
tg3_flag_set(tp, TSO_CAPABLE);
netdev_update_features(dev);
}
tg3_flag_clear(tp, JUMBO_RING_ENABLE);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,264 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
{
/* accept or reject all multicast frames */
tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
}
| DoS Exec Code Overflow | 0 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
{
/* accept or reject all multicast frames */
tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,265 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
struct tg3 *tp = netdev_priv(dev);
int err = 0;
if (tg3_flag(tp, USE_PHYLIB)) {
u32 newadv;
struct phy_device *phydev;
phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
if (!(phydev->supported & SUPPORTED_Pause) ||
(!(phydev->supported & SUPPORTED_Asym_Pause) &&
(epause->rx_pause != epause->tx_pause)))
return -EINVAL;
tp->link_config.flowctrl = 0;
if (epause->rx_pause) {
tp->link_config.flowctrl |= FLOW_CTRL_RX;
if (epause->tx_pause) {
tp->link_config.flowctrl |= FLOW_CTRL_TX;
newadv = ADVERTISED_Pause;
} else
newadv = ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
} else if (epause->tx_pause) {
tp->link_config.flowctrl |= FLOW_CTRL_TX;
newadv = ADVERTISED_Asym_Pause;
} else
newadv = 0;
if (epause->autoneg)
tg3_flag_set(tp, PAUSE_AUTONEG);
else
tg3_flag_clear(tp, PAUSE_AUTONEG);
if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
u32 oldadv = phydev->advertising &
(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
if (oldadv != newadv) {
phydev->advertising &=
~(ADVERTISED_Pause |
ADVERTISED_Asym_Pause);
phydev->advertising |= newadv;
if (phydev->autoneg) {
/*
* Always renegotiate the link to
* inform our link partner of our
* flow control settings, even if the
* flow control is forced. Let
* tg3_adjust_link() do the final
* flow control setup.
*/
return phy_start_aneg(phydev);
}
}
if (!epause->autoneg)
tg3_setup_flow_control(tp, 0, 0);
} else {
tp->link_config.advertising &=
~(ADVERTISED_Pause |
ADVERTISED_Asym_Pause);
tp->link_config.advertising |= newadv;
}
} else {
int irq_sync = 0;
if (netif_running(dev)) {
tg3_netif_stop(tp);
irq_sync = 1;
}
tg3_full_lock(tp, irq_sync);
if (epause->autoneg)
tg3_flag_set(tp, PAUSE_AUTONEG);
else
tg3_flag_clear(tp, PAUSE_AUTONEG);
if (epause->rx_pause)
tp->link_config.flowctrl |= FLOW_CTRL_RX;
else
tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
if (epause->tx_pause)
tp->link_config.flowctrl |= FLOW_CTRL_TX;
else
tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
if (netif_running(dev)) {
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
err = tg3_restart_hw(tp, 1);
if (!err)
tg3_netif_start(tp);
}
tg3_full_unlock(tp);
}
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
struct tg3 *tp = netdev_priv(dev);
int err = 0;
if (tg3_flag(tp, USE_PHYLIB)) {
u32 newadv;
struct phy_device *phydev;
phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
if (!(phydev->supported & SUPPORTED_Pause) ||
(!(phydev->supported & SUPPORTED_Asym_Pause) &&
(epause->rx_pause != epause->tx_pause)))
return -EINVAL;
tp->link_config.flowctrl = 0;
if (epause->rx_pause) {
tp->link_config.flowctrl |= FLOW_CTRL_RX;
if (epause->tx_pause) {
tp->link_config.flowctrl |= FLOW_CTRL_TX;
newadv = ADVERTISED_Pause;
} else
newadv = ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
} else if (epause->tx_pause) {
tp->link_config.flowctrl |= FLOW_CTRL_TX;
newadv = ADVERTISED_Asym_Pause;
} else
newadv = 0;
if (epause->autoneg)
tg3_flag_set(tp, PAUSE_AUTONEG);
else
tg3_flag_clear(tp, PAUSE_AUTONEG);
if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
u32 oldadv = phydev->advertising &
(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
if (oldadv != newadv) {
phydev->advertising &=
~(ADVERTISED_Pause |
ADVERTISED_Asym_Pause);
phydev->advertising |= newadv;
if (phydev->autoneg) {
/*
* Always renegotiate the link to
* inform our link partner of our
* flow control settings, even if the
* flow control is forced. Let
* tg3_adjust_link() do the final
* flow control setup.
*/
return phy_start_aneg(phydev);
}
}
if (!epause->autoneg)
tg3_setup_flow_control(tp, 0, 0);
} else {
tp->link_config.advertising &=
~(ADVERTISED_Pause |
ADVERTISED_Asym_Pause);
tp->link_config.advertising |= newadv;
}
} else {
int irq_sync = 0;
if (netif_running(dev)) {
tg3_netif_stop(tp);
irq_sync = 1;
}
tg3_full_lock(tp, irq_sync);
if (epause->autoneg)
tg3_flag_set(tp, PAUSE_AUTONEG);
else
tg3_flag_clear(tp, PAUSE_AUTONEG);
if (epause->rx_pause)
tp->link_config.flowctrl |= FLOW_CTRL_RX;
else
tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
if (epause->tx_pause)
tp->link_config.flowctrl |= FLOW_CTRL_TX;
else
tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
if (netif_running(dev)) {
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
err = tg3_restart_hw(tp, 1);
if (!err)
tg3_netif_start(tp);
}
tg3_full_unlock(tp);
}
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,266 | static int tg3_set_phys_id(struct net_device *dev,
enum ethtool_phys_id_state state)
{
struct tg3 *tp = netdev_priv(dev);
if (!netif_running(tp->dev))
return -EAGAIN;
switch (state) {
case ETHTOOL_ID_ACTIVE:
return 1; /* cycle on/off once per second */
case ETHTOOL_ID_ON:
tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON |
LED_CTRL_100MBPS_ON |
LED_CTRL_10MBPS_ON |
LED_CTRL_TRAFFIC_OVERRIDE |
LED_CTRL_TRAFFIC_BLINK |
LED_CTRL_TRAFFIC_LED);
break;
case ETHTOOL_ID_OFF:
tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_TRAFFIC_OVERRIDE);
break;
case ETHTOOL_ID_INACTIVE:
tw32(MAC_LED_CTRL, tp->led_ctrl);
break;
}
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_phys_id(struct net_device *dev,
enum ethtool_phys_id_state state)
{
struct tg3 *tp = netdev_priv(dev);
if (!netif_running(tp->dev))
return -EAGAIN;
switch (state) {
case ETHTOOL_ID_ACTIVE:
return 1; /* cycle on/off once per second */
case ETHTOOL_ID_ON:
tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON |
LED_CTRL_100MBPS_ON |
LED_CTRL_10MBPS_ON |
LED_CTRL_TRAFFIC_OVERRIDE |
LED_CTRL_TRAFFIC_BLINK |
LED_CTRL_TRAFFIC_LED);
break;
case ETHTOOL_ID_OFF:
tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_TRAFFIC_OVERRIDE);
break;
case ETHTOOL_ID_INACTIVE:
tw32(MAC_LED_CTRL, tp->led_ctrl);
break;
}
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,267 | static void tg3_set_rx_mode(struct net_device *dev)
{
struct tg3 *tp = netdev_priv(dev);
if (!netif_running(dev))
return;
tg3_full_lock(tp, 0);
__tg3_set_rx_mode(dev);
tg3_full_unlock(tp);
}
| DoS Exec Code Overflow | 0 | static void tg3_set_rx_mode(struct net_device *dev)
{
struct tg3 *tp = netdev_priv(dev);
if (!netif_running(dev))
return;
tg3_full_lock(tp, 0);
__tg3_set_rx_mode(dev);
tg3_full_unlock(tp);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,268 | static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
{
struct tg3 *tp = netdev_priv(dev);
size_t i;
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
tp->rss_ind_tbl[i] = indir[i];
if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
return 0;
/* It is legal to write the indirection
* table while the device is running.
*/
tg3_full_lock(tp, 0);
tg3_rss_write_indir_tbl(tp);
tg3_full_unlock(tp);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
{
struct tg3 *tp = netdev_priv(dev);
size_t i;
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
tp->rss_ind_tbl[i] = indir[i];
if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
return 0;
/* It is legal to write the indirection
* table while the device is running.
*/
tg3_full_lock(tp, 0);
tg3_rss_write_indir_tbl(tp);
tg3_full_unlock(tp);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,269 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct tg3 *tp = netdev_priv(dev);
struct device *dp = &tp->pdev->dev;
if (wol->wolopts & ~WAKE_MAGIC)
return -EINVAL;
if ((wol->wolopts & WAKE_MAGIC) &&
!(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
return -EINVAL;
device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
spin_lock_bh(&tp->lock);
if (device_may_wakeup(dp))
tg3_flag_set(tp, WOL_ENABLE);
else
tg3_flag_clear(tp, WOL_ENABLE);
spin_unlock_bh(&tp->lock);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct tg3 *tp = netdev_priv(dev);
struct device *dp = &tp->pdev->dev;
if (wol->wolopts & ~WAKE_MAGIC)
return -EINVAL;
if ((wol->wolopts & WAKE_MAGIC) &&
!(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
return -EINVAL;
device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
spin_lock_bh(&tp->lock);
if (device_may_wakeup(dp))
tg3_flag_set(tp, WOL_ENABLE);
else
tg3_flag_clear(tp, WOL_ENABLE);
spin_unlock_bh(&tp->lock);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,270 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
{
int current_link_up;
u32 bmsr, val;
u32 lcl_adv, rmt_adv;
u16 current_speed;
u8 current_duplex;
int i, err;
tw32(MAC_EVENT, 0);
tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED |
MAC_STATUS_MI_COMPLETION |
MAC_STATUS_LNKSTATE_CHANGED));
udelay(40);
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
tw32_f(MAC_MI_MODE,
(tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
udelay(80);
}
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
/* Some third-party PHYs need to be reset on link going
* down.
*/
if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704 ||
tg3_asic_rev(tp) == ASIC_REV_5705) &&
tp->link_up) {
tg3_readphy(tp, MII_BMSR, &bmsr);
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
!(bmsr & BMSR_LSTATUS))
force_reset = 1;
}
if (force_reset)
tg3_phy_reset(tp);
if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
tg3_readphy(tp, MII_BMSR, &bmsr);
if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
!tg3_flag(tp, INIT_COMPLETE))
bmsr = 0;
if (!(bmsr & BMSR_LSTATUS)) {
err = tg3_init_5401phy_dsp(tp);
if (err)
return err;
tg3_readphy(tp, MII_BMSR, &bmsr);
for (i = 0; i < 1000; i++) {
udelay(10);
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
(bmsr & BMSR_LSTATUS)) {
udelay(40);
break;
}
}
if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
TG3_PHY_REV_BCM5401_B0 &&
!(bmsr & BMSR_LSTATUS) &&
tp->link_config.active_speed == SPEED_1000) {
err = tg3_phy_reset(tp);
if (!err)
err = tg3_init_5401phy_dsp(tp);
if (err)
return err;
}
}
} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
/* 5701 {A0,B0} CRC bug workaround */
tg3_writephy(tp, 0x15, 0x0a75);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
}
/* Clear pending interrupts... */
tg3_readphy(tp, MII_TG3_ISTAT, &val);
tg3_readphy(tp, MII_TG3_ISTAT, &val);
if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
tg3_writephy(tp, MII_TG3_IMASK, ~0);
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
tg3_writephy(tp, MII_TG3_EXT_CTRL,
MII_TG3_EXT_CTRL_LNK3_LED_MODE);
else
tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
}
current_link_up = 0;
current_speed = SPEED_UNKNOWN;
current_duplex = DUPLEX_UNKNOWN;
tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
tp->link_config.rmt_adv = 0;
if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
err = tg3_phy_auxctl_read(tp,
MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
&val);
if (!err && !(val & (1 << 10))) {
tg3_phy_auxctl_write(tp,
MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
val | (1 << 10));
goto relink;
}
}
bmsr = 0;
for (i = 0; i < 100; i++) {
tg3_readphy(tp, MII_BMSR, &bmsr);
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
(bmsr & BMSR_LSTATUS))
break;
udelay(40);
}
if (bmsr & BMSR_LSTATUS) {
u32 aux_stat, bmcr;
tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
for (i = 0; i < 2000; i++) {
udelay(10);
if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
aux_stat)
break;
}
tg3_aux_stat_to_speed_duplex(tp, aux_stat,
¤t_speed,
¤t_duplex);
bmcr = 0;
for (i = 0; i < 200; i++) {
tg3_readphy(tp, MII_BMCR, &bmcr);
if (tg3_readphy(tp, MII_BMCR, &bmcr))
continue;
if (bmcr && bmcr != 0x7fff)
break;
udelay(10);
}
lcl_adv = 0;
rmt_adv = 0;
tp->link_config.active_speed = current_speed;
tp->link_config.active_duplex = current_duplex;
if (tp->link_config.autoneg == AUTONEG_ENABLE) {
if ((bmcr & BMCR_ANENABLE) &&
tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
current_link_up = 1;
} else {
if (!(bmcr & BMCR_ANENABLE) &&
tp->link_config.speed == current_speed &&
tp->link_config.duplex == current_duplex &&
tp->link_config.flowctrl ==
tp->link_config.active_flowctrl) {
current_link_up = 1;
}
}
if (current_link_up == 1 &&
tp->link_config.active_duplex == DUPLEX_FULL) {
u32 reg, bit;
if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
reg = MII_TG3_FET_GEN_STAT;
bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
} else {
reg = MII_TG3_EXT_STAT;
bit = MII_TG3_EXT_STAT_MDIX;
}
if (!tg3_readphy(tp, reg, &val) && (val & bit))
tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
}
}
relink:
if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
tg3_phy_copper_begin(tp);
if (tg3_flag(tp, ROBOSWITCH)) {
current_link_up = 1;
/* FIXME: when BCM5325 switch is used use 100 MBit/s */
current_speed = SPEED_1000;
current_duplex = DUPLEX_FULL;
tp->link_config.active_speed = current_speed;
tp->link_config.active_duplex = current_duplex;
}
tg3_readphy(tp, MII_BMSR, &bmsr);
if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
current_link_up = 1;
}
tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
if (current_link_up == 1) {
if (tp->link_config.active_speed == SPEED_100 ||
tp->link_config.active_speed == SPEED_10)
tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
else
tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
} else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
else
tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
/* In order for the 5750 core in BCM4785 chip to work properly
* in RGMII mode, the Led Control Register must be set up.
*/
if (tg3_flag(tp, RGMII_MODE)) {
u32 led_ctrl = tr32(MAC_LED_CTRL);
led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
if (tp->link_config.active_speed == SPEED_10)
led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
else if (tp->link_config.active_speed == SPEED_100)
led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_100MBPS_ON);
else if (tp->link_config.active_speed == SPEED_1000)
led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON);
tw32(MAC_LED_CTRL, led_ctrl);
udelay(40);
}
tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
if (tp->link_config.active_duplex == DUPLEX_HALF)
tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
if (tg3_asic_rev(tp) == ASIC_REV_5700) {
if (current_link_up == 1 &&
tg3_5700_link_polarity(tp, tp->link_config.active_speed))
tp->mac_mode |= MAC_MODE_LINK_POLARITY;
else
tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
}
/* ??? Without this setting Netgear GA302T PHY does not
* ??? send/receive packets...
*/
if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
tw32_f(MAC_MI_MODE, tp->mi_mode);
udelay(80);
}
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
tg3_phy_eee_adjust(tp, current_link_up);
if (tg3_flag(tp, USE_LINKCHG_REG)) {
/* Polled via timer. */
tw32_f(MAC_EVENT, 0);
} else {
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
}
udelay(40);
if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
current_link_up == 1 &&
tp->link_config.active_speed == SPEED_1000 &&
(tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
udelay(120);
tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
udelay(40);
tg3_write_mem(tp,
NIC_SRAM_FIRMWARE_MBOX,
NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
}
/* Prevent send BD corruption. */
if (tg3_flag(tp, CLKREQ_BUG)) {
if (tp->link_config.active_speed == SPEED_100 ||
tp->link_config.active_speed == SPEED_10)
pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CLKREQ_EN);
else
pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CLKREQ_EN);
}
tg3_test_and_report_link_chg(tp, current_link_up);
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
{
int current_link_up;
u32 bmsr, val;
u32 lcl_adv, rmt_adv;
u16 current_speed;
u8 current_duplex;
int i, err;
tw32(MAC_EVENT, 0);
tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED |
MAC_STATUS_MI_COMPLETION |
MAC_STATUS_LNKSTATE_CHANGED));
udelay(40);
if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
tw32_f(MAC_MI_MODE,
(tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
udelay(80);
}
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
/* Some third-party PHYs need to be reset on link going
* down.
*/
if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704 ||
tg3_asic_rev(tp) == ASIC_REV_5705) &&
tp->link_up) {
tg3_readphy(tp, MII_BMSR, &bmsr);
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
!(bmsr & BMSR_LSTATUS))
force_reset = 1;
}
if (force_reset)
tg3_phy_reset(tp);
if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
tg3_readphy(tp, MII_BMSR, &bmsr);
if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
!tg3_flag(tp, INIT_COMPLETE))
bmsr = 0;
if (!(bmsr & BMSR_LSTATUS)) {
err = tg3_init_5401phy_dsp(tp);
if (err)
return err;
tg3_readphy(tp, MII_BMSR, &bmsr);
for (i = 0; i < 1000; i++) {
udelay(10);
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
(bmsr & BMSR_LSTATUS)) {
udelay(40);
break;
}
}
if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
TG3_PHY_REV_BCM5401_B0 &&
!(bmsr & BMSR_LSTATUS) &&
tp->link_config.active_speed == SPEED_1000) {
err = tg3_phy_reset(tp);
if (!err)
err = tg3_init_5401phy_dsp(tp);
if (err)
return err;
}
}
} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
/* 5701 {A0,B0} CRC bug workaround */
tg3_writephy(tp, 0x15, 0x0a75);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
}
/* Clear pending interrupts... */
tg3_readphy(tp, MII_TG3_ISTAT, &val);
tg3_readphy(tp, MII_TG3_ISTAT, &val);
if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
tg3_writephy(tp, MII_TG3_IMASK, ~0);
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
tg3_writephy(tp, MII_TG3_EXT_CTRL,
MII_TG3_EXT_CTRL_LNK3_LED_MODE);
else
tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
}
current_link_up = 0;
current_speed = SPEED_UNKNOWN;
current_duplex = DUPLEX_UNKNOWN;
tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
tp->link_config.rmt_adv = 0;
if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
err = tg3_phy_auxctl_read(tp,
MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
&val);
if (!err && !(val & (1 << 10))) {
tg3_phy_auxctl_write(tp,
MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
val | (1 << 10));
goto relink;
}
}
bmsr = 0;
for (i = 0; i < 100; i++) {
tg3_readphy(tp, MII_BMSR, &bmsr);
if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
(bmsr & BMSR_LSTATUS))
break;
udelay(40);
}
if (bmsr & BMSR_LSTATUS) {
u32 aux_stat, bmcr;
tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
for (i = 0; i < 2000; i++) {
udelay(10);
if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
aux_stat)
break;
}
tg3_aux_stat_to_speed_duplex(tp, aux_stat,
¤t_speed,
¤t_duplex);
bmcr = 0;
for (i = 0; i < 200; i++) {
tg3_readphy(tp, MII_BMCR, &bmcr);
if (tg3_readphy(tp, MII_BMCR, &bmcr))
continue;
if (bmcr && bmcr != 0x7fff)
break;
udelay(10);
}
lcl_adv = 0;
rmt_adv = 0;
tp->link_config.active_speed = current_speed;
tp->link_config.active_duplex = current_duplex;
if (tp->link_config.autoneg == AUTONEG_ENABLE) {
if ((bmcr & BMCR_ANENABLE) &&
tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
current_link_up = 1;
} else {
if (!(bmcr & BMCR_ANENABLE) &&
tp->link_config.speed == current_speed &&
tp->link_config.duplex == current_duplex &&
tp->link_config.flowctrl ==
tp->link_config.active_flowctrl) {
current_link_up = 1;
}
}
if (current_link_up == 1 &&
tp->link_config.active_duplex == DUPLEX_FULL) {
u32 reg, bit;
if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
reg = MII_TG3_FET_GEN_STAT;
bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
} else {
reg = MII_TG3_EXT_STAT;
bit = MII_TG3_EXT_STAT_MDIX;
}
if (!tg3_readphy(tp, reg, &val) && (val & bit))
tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
}
}
relink:
if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
tg3_phy_copper_begin(tp);
if (tg3_flag(tp, ROBOSWITCH)) {
current_link_up = 1;
/* FIXME: when BCM5325 switch is used use 100 MBit/s */
current_speed = SPEED_1000;
current_duplex = DUPLEX_FULL;
tp->link_config.active_speed = current_speed;
tp->link_config.active_duplex = current_duplex;
}
tg3_readphy(tp, MII_BMSR, &bmsr);
if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
current_link_up = 1;
}
tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
if (current_link_up == 1) {
if (tp->link_config.active_speed == SPEED_100 ||
tp->link_config.active_speed == SPEED_10)
tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
else
tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
} else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
else
tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
/* In order for the 5750 core in BCM4785 chip to work properly
* in RGMII mode, the Led Control Register must be set up.
*/
if (tg3_flag(tp, RGMII_MODE)) {
u32 led_ctrl = tr32(MAC_LED_CTRL);
led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
if (tp->link_config.active_speed == SPEED_10)
led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
else if (tp->link_config.active_speed == SPEED_100)
led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_100MBPS_ON);
else if (tp->link_config.active_speed == SPEED_1000)
led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON);
tw32(MAC_LED_CTRL, led_ctrl);
udelay(40);
}
tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
if (tp->link_config.active_duplex == DUPLEX_HALF)
tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
if (tg3_asic_rev(tp) == ASIC_REV_5700) {
if (current_link_up == 1 &&
tg3_5700_link_polarity(tp, tp->link_config.active_speed))
tp->mac_mode |= MAC_MODE_LINK_POLARITY;
else
tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
}
/* ??? Without this setting Netgear GA302T PHY does not
* ??? send/receive packets...
*/
if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
tw32_f(MAC_MI_MODE, tp->mi_mode);
udelay(80);
}
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
tg3_phy_eee_adjust(tp, current_link_up);
if (tg3_flag(tp, USE_LINKCHG_REG)) {
/* Polled via timer. */
tw32_f(MAC_EVENT, 0);
} else {
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
}
udelay(40);
if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
current_link_up == 1 &&
tp->link_config.active_speed == SPEED_1000 &&
(tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
udelay(120);
tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
udelay(40);
tg3_write_mem(tp,
NIC_SRAM_FIRMWARE_MBOX,
NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
}
/* Prevent send BD corruption. */
if (tg3_flag(tp, CLKREQ_BUG)) {
if (tp->link_config.active_speed == SPEED_100 ||
tp->link_config.active_speed == SPEED_10)
pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CLKREQ_EN);
else
pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_CLKREQ_EN);
}
tg3_test_and_report_link_chg(tp, current_link_up);
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,271 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
{
int current_link_up = 0;
if (!(mac_status & MAC_STATUS_PCS_SYNCED))
goto out;
if (tp->link_config.autoneg == AUTONEG_ENABLE) {
u32 txflags, rxflags;
int i;
if (fiber_autoneg(tp, &txflags, &rxflags)) {
u32 local_adv = 0, remote_adv = 0;
if (txflags & ANEG_CFG_PS1)
local_adv |= ADVERTISE_1000XPAUSE;
if (txflags & ANEG_CFG_PS2)
local_adv |= ADVERTISE_1000XPSE_ASYM;
if (rxflags & MR_LP_ADV_SYM_PAUSE)
remote_adv |= LPA_1000XPAUSE;
if (rxflags & MR_LP_ADV_ASYM_PAUSE)
remote_adv |= LPA_1000XPAUSE_ASYM;
tp->link_config.rmt_adv =
mii_adv_to_ethtool_adv_x(remote_adv);
tg3_setup_flow_control(tp, local_adv, remote_adv);
current_link_up = 1;
}
for (i = 0; i < 30; i++) {
udelay(20);
tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
udelay(40);
if ((tr32(MAC_STATUS) &
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED)) == 0)
break;
}
mac_status = tr32(MAC_STATUS);
if (current_link_up == 0 &&
(mac_status & MAC_STATUS_PCS_SYNCED) &&
!(mac_status & MAC_STATUS_RCVD_CFG))
current_link_up = 1;
} else {
tg3_setup_flow_control(tp, 0, 0);
/* Forcing 1000FD link up. */
current_link_up = 1;
tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
udelay(40);
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
}
out:
return current_link_up;
}
| DoS Exec Code Overflow | 0 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
{
int current_link_up = 0;
if (!(mac_status & MAC_STATUS_PCS_SYNCED))
goto out;
if (tp->link_config.autoneg == AUTONEG_ENABLE) {
u32 txflags, rxflags;
int i;
if (fiber_autoneg(tp, &txflags, &rxflags)) {
u32 local_adv = 0, remote_adv = 0;
if (txflags & ANEG_CFG_PS1)
local_adv |= ADVERTISE_1000XPAUSE;
if (txflags & ANEG_CFG_PS2)
local_adv |= ADVERTISE_1000XPSE_ASYM;
if (rxflags & MR_LP_ADV_SYM_PAUSE)
remote_adv |= LPA_1000XPAUSE;
if (rxflags & MR_LP_ADV_ASYM_PAUSE)
remote_adv |= LPA_1000XPAUSE_ASYM;
tp->link_config.rmt_adv =
mii_adv_to_ethtool_adv_x(remote_adv);
tg3_setup_flow_control(tp, local_adv, remote_adv);
current_link_up = 1;
}
for (i = 0; i < 30; i++) {
udelay(20);
tw32_f(MAC_STATUS,
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
udelay(40);
if ((tr32(MAC_STATUS) &
(MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED)) == 0)
break;
}
mac_status = tr32(MAC_STATUS);
if (current_link_up == 0 &&
(mac_status & MAC_STATUS_PCS_SYNCED) &&
!(mac_status & MAC_STATUS_RCVD_CFG))
current_link_up = 1;
} else {
tg3_setup_flow_control(tp, 0, 0);
/* Forcing 1000FD link up. */
current_link_up = 1;
tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
udelay(40);
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
}
out:
return current_link_up;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,272 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
{
u16 flowctrl;
u32 sg_dig_ctrl, sg_dig_status;
u32 serdes_cfg, expected_sg_dig_ctrl;
int workaround, port_a;
int current_link_up;
serdes_cfg = 0;
expected_sg_dig_ctrl = 0;
workaround = 0;
port_a = 1;
current_link_up = 0;
if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
workaround = 1;
if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
port_a = 0;
/* preserve bits 0-11,13,14 for signal pre-emphasis */
/* preserve bits 20-23 for voltage regulator */
serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
}
sg_dig_ctrl = tr32(SG_DIG_CTRL);
if (tp->link_config.autoneg != AUTONEG_ENABLE) {
if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
if (workaround) {
u32 val = serdes_cfg;
if (port_a)
val |= 0xc010000;
else
val |= 0x4010000;
tw32_f(MAC_SERDES_CFG, val);
}
tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
}
if (mac_status & MAC_STATUS_PCS_SYNCED) {
tg3_setup_flow_control(tp, 0, 0);
current_link_up = 1;
}
goto out;
}
/* Want auto-negotiation. */
expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
if (flowctrl & ADVERTISE_1000XPAUSE)
expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
if (flowctrl & ADVERTISE_1000XPSE_ASYM)
expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
if (sg_dig_ctrl != expected_sg_dig_ctrl) {
if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
tp->serdes_counter &&
((mac_status & (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_RCVD_CFG)) ==
MAC_STATUS_PCS_SYNCED)) {
tp->serdes_counter--;
current_link_up = 1;
goto out;
}
restart_autoneg:
if (workaround)
tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
udelay(5);
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
} else if (mac_status & (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_SIGNAL_DET)) {
sg_dig_status = tr32(SG_DIG_STATUS);
mac_status = tr32(MAC_STATUS);
if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
(mac_status & MAC_STATUS_PCS_SYNCED)) {
u32 local_adv = 0, remote_adv = 0;
if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
local_adv |= ADVERTISE_1000XPAUSE;
if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
local_adv |= ADVERTISE_1000XPSE_ASYM;
if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
remote_adv |= LPA_1000XPAUSE;
if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
remote_adv |= LPA_1000XPAUSE_ASYM;
tp->link_config.rmt_adv =
mii_adv_to_ethtool_adv_x(remote_adv);
tg3_setup_flow_control(tp, local_adv, remote_adv);
current_link_up = 1;
tp->serdes_counter = 0;
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
} else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
if (tp->serdes_counter)
tp->serdes_counter--;
else {
if (workaround) {
u32 val = serdes_cfg;
if (port_a)
val |= 0xc010000;
else
val |= 0x4010000;
tw32_f(MAC_SERDES_CFG, val);
}
tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
udelay(40);
/* Link parallel detection - link is up */
/* only if we have PCS_SYNC and not */
/* receiving config code words */
mac_status = tr32(MAC_STATUS);
if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
!(mac_status & MAC_STATUS_RCVD_CFG)) {
tg3_setup_flow_control(tp, 0, 0);
current_link_up = 1;
tp->phy_flags |=
TG3_PHYFLG_PARALLEL_DETECT;
tp->serdes_counter =
SERDES_PARALLEL_DET_TIMEOUT;
} else
goto restart_autoneg;
}
}
} else {
tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
}
out:
return current_link_up;
}
| DoS Exec Code Overflow | 0 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
{
u16 flowctrl;
u32 sg_dig_ctrl, sg_dig_status;
u32 serdes_cfg, expected_sg_dig_ctrl;
int workaround, port_a;
int current_link_up;
serdes_cfg = 0;
expected_sg_dig_ctrl = 0;
workaround = 0;
port_a = 1;
current_link_up = 0;
if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
workaround = 1;
if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
port_a = 0;
/* preserve bits 0-11,13,14 for signal pre-emphasis */
/* preserve bits 20-23 for voltage regulator */
serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
}
sg_dig_ctrl = tr32(SG_DIG_CTRL);
if (tp->link_config.autoneg != AUTONEG_ENABLE) {
if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
if (workaround) {
u32 val = serdes_cfg;
if (port_a)
val |= 0xc010000;
else
val |= 0x4010000;
tw32_f(MAC_SERDES_CFG, val);
}
tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
}
if (mac_status & MAC_STATUS_PCS_SYNCED) {
tg3_setup_flow_control(tp, 0, 0);
current_link_up = 1;
}
goto out;
}
/* Want auto-negotiation. */
expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
if (flowctrl & ADVERTISE_1000XPAUSE)
expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
if (flowctrl & ADVERTISE_1000XPSE_ASYM)
expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
if (sg_dig_ctrl != expected_sg_dig_ctrl) {
if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
tp->serdes_counter &&
((mac_status & (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_RCVD_CFG)) ==
MAC_STATUS_PCS_SYNCED)) {
tp->serdes_counter--;
current_link_up = 1;
goto out;
}
restart_autoneg:
if (workaround)
tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
udelay(5);
tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
} else if (mac_status & (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_SIGNAL_DET)) {
sg_dig_status = tr32(SG_DIG_STATUS);
mac_status = tr32(MAC_STATUS);
if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
(mac_status & MAC_STATUS_PCS_SYNCED)) {
u32 local_adv = 0, remote_adv = 0;
if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
local_adv |= ADVERTISE_1000XPAUSE;
if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
local_adv |= ADVERTISE_1000XPSE_ASYM;
if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
remote_adv |= LPA_1000XPAUSE;
if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
remote_adv |= LPA_1000XPAUSE_ASYM;
tp->link_config.rmt_adv =
mii_adv_to_ethtool_adv_x(remote_adv);
tg3_setup_flow_control(tp, local_adv, remote_adv);
current_link_up = 1;
tp->serdes_counter = 0;
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
} else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
if (tp->serdes_counter)
tp->serdes_counter--;
else {
if (workaround) {
u32 val = serdes_cfg;
if (port_a)
val |= 0xc010000;
else
val |= 0x4010000;
tw32_f(MAC_SERDES_CFG, val);
}
tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
udelay(40);
/* Link parallel detection - link is up */
/* only if we have PCS_SYNC and not */
/* receiving config code words */
mac_status = tr32(MAC_STATUS);
if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
!(mac_status & MAC_STATUS_RCVD_CFG)) {
tg3_setup_flow_control(tp, 0, 0);
current_link_up = 1;
tp->phy_flags |=
TG3_PHYFLG_PARALLEL_DETECT;
tp->serdes_counter =
SERDES_PARALLEL_DET_TIMEOUT;
} else
goto restart_autoneg;
}
}
} else {
tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
}
out:
return current_link_up;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,273 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
{
u32 orig_pause_cfg;
u16 orig_active_speed;
u8 orig_active_duplex;
u32 mac_status;
int current_link_up;
int i;
orig_pause_cfg = tp->link_config.active_flowctrl;
orig_active_speed = tp->link_config.active_speed;
orig_active_duplex = tp->link_config.active_duplex;
if (!tg3_flag(tp, HW_AUTONEG) &&
tp->link_up &&
tg3_flag(tp, INIT_COMPLETE)) {
mac_status = tr32(MAC_STATUS);
mac_status &= (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_SIGNAL_DET |
MAC_STATUS_CFG_CHANGED |
MAC_STATUS_RCVD_CFG);
if (mac_status == (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_SIGNAL_DET)) {
tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
return 0;
}
}
tw32_f(MAC_TX_AUTO_NEG, 0);
tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
if (tp->phy_id == TG3_PHY_ID_BCM8002)
tg3_init_bcm8002(tp);
/* Enable link change event even when serdes polling. */
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
udelay(40);
current_link_up = 0;
tp->link_config.rmt_adv = 0;
mac_status = tr32(MAC_STATUS);
if (tg3_flag(tp, HW_AUTONEG))
current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
else
current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
tp->napi[0].hw_status->status =
(SD_STATUS_UPDATED |
(tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
for (i = 0; i < 100; i++) {
tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
udelay(5);
if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED |
MAC_STATUS_LNKSTATE_CHANGED)) == 0)
break;
}
mac_status = tr32(MAC_STATUS);
if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
current_link_up = 0;
if (tp->link_config.autoneg == AUTONEG_ENABLE &&
tp->serdes_counter == 0) {
tw32_f(MAC_MODE, (tp->mac_mode |
MAC_MODE_SEND_CONFIGS));
udelay(1);
tw32_f(MAC_MODE, tp->mac_mode);
}
}
if (current_link_up == 1) {
tp->link_config.active_speed = SPEED_1000;
tp->link_config.active_duplex = DUPLEX_FULL;
tw32(MAC_LED_CTRL, (tp->led_ctrl |
LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON));
} else {
tp->link_config.active_speed = SPEED_UNKNOWN;
tp->link_config.active_duplex = DUPLEX_UNKNOWN;
tw32(MAC_LED_CTRL, (tp->led_ctrl |
LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_TRAFFIC_OVERRIDE));
}
if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
u32 now_pause_cfg = tp->link_config.active_flowctrl;
if (orig_pause_cfg != now_pause_cfg ||
orig_active_speed != tp->link_config.active_speed ||
orig_active_duplex != tp->link_config.active_duplex)
tg3_link_report(tp);
}
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
{
u32 orig_pause_cfg;
u16 orig_active_speed;
u8 orig_active_duplex;
u32 mac_status;
int current_link_up;
int i;
orig_pause_cfg = tp->link_config.active_flowctrl;
orig_active_speed = tp->link_config.active_speed;
orig_active_duplex = tp->link_config.active_duplex;
if (!tg3_flag(tp, HW_AUTONEG) &&
tp->link_up &&
tg3_flag(tp, INIT_COMPLETE)) {
mac_status = tr32(MAC_STATUS);
mac_status &= (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_SIGNAL_DET |
MAC_STATUS_CFG_CHANGED |
MAC_STATUS_RCVD_CFG);
if (mac_status == (MAC_STATUS_PCS_SYNCED |
MAC_STATUS_SIGNAL_DET)) {
tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
return 0;
}
}
tw32_f(MAC_TX_AUTO_NEG, 0);
tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
tw32_f(MAC_MODE, tp->mac_mode);
udelay(40);
if (tp->phy_id == TG3_PHY_ID_BCM8002)
tg3_init_bcm8002(tp);
/* Enable link change event even when serdes polling. */
tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
udelay(40);
current_link_up = 0;
tp->link_config.rmt_adv = 0;
mac_status = tr32(MAC_STATUS);
if (tg3_flag(tp, HW_AUTONEG))
current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
else
current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
tp->napi[0].hw_status->status =
(SD_STATUS_UPDATED |
(tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
for (i = 0; i < 100; i++) {
tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED));
udelay(5);
if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
MAC_STATUS_CFG_CHANGED |
MAC_STATUS_LNKSTATE_CHANGED)) == 0)
break;
}
mac_status = tr32(MAC_STATUS);
if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
current_link_up = 0;
if (tp->link_config.autoneg == AUTONEG_ENABLE &&
tp->serdes_counter == 0) {
tw32_f(MAC_MODE, (tp->mac_mode |
MAC_MODE_SEND_CONFIGS));
udelay(1);
tw32_f(MAC_MODE, tp->mac_mode);
}
}
if (current_link_up == 1) {
tp->link_config.active_speed = SPEED_1000;
tp->link_config.active_duplex = DUPLEX_FULL;
tw32(MAC_LED_CTRL, (tp->led_ctrl |
LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_1000MBPS_ON));
} else {
tp->link_config.active_speed = SPEED_UNKNOWN;
tp->link_config.active_duplex = DUPLEX_UNKNOWN;
tw32(MAC_LED_CTRL, (tp->led_ctrl |
LED_CTRL_LNKLED_OVERRIDE |
LED_CTRL_TRAFFIC_OVERRIDE));
}
if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
u32 now_pause_cfg = tp->link_config.active_flowctrl;
if (orig_pause_cfg != now_pause_cfg ||
orig_active_speed != tp->link_config.active_speed ||
orig_active_duplex != tp->link_config.active_duplex)
tg3_link_report(tp);
}
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,274 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
{
u8 autoneg;
u8 flowctrl = 0;
u32 old_rx_mode = tp->rx_mode;
u32 old_tx_mode = tp->tx_mode;
if (tg3_flag(tp, USE_PHYLIB))
autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
else
autoneg = tp->link_config.autoneg;
if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
else
flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
} else
flowctrl = tp->link_config.flowctrl;
tp->link_config.active_flowctrl = flowctrl;
if (flowctrl & FLOW_CTRL_RX)
tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
else
tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
if (old_rx_mode != tp->rx_mode)
tw32_f(MAC_RX_MODE, tp->rx_mode);
if (flowctrl & FLOW_CTRL_TX)
tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
else
tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
if (old_tx_mode != tp->tx_mode)
tw32_f(MAC_TX_MODE, tp->tx_mode);
}
| DoS Exec Code Overflow | 0 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
{
u8 autoneg;
u8 flowctrl = 0;
u32 old_rx_mode = tp->rx_mode;
u32 old_tx_mode = tp->tx_mode;
if (tg3_flag(tp, USE_PHYLIB))
autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
else
autoneg = tp->link_config.autoneg;
if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
else
flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
} else
flowctrl = tp->link_config.flowctrl;
tp->link_config.active_flowctrl = flowctrl;
if (flowctrl & FLOW_CTRL_RX)
tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
else
tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
if (old_rx_mode != tp->rx_mode)
tw32_f(MAC_RX_MODE, tp->rx_mode);
if (flowctrl & FLOW_CTRL_TX)
tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
else
tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
if (old_tx_mode != tp->tx_mode)
tw32_f(MAC_TX_MODE, tp->tx_mode);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,275 | static int tg3_setup_phy(struct tg3 *tp, int force_reset)
{
u32 val;
int err;
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
err = tg3_setup_fiber_phy(tp, force_reset);
else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
err = tg3_setup_fiber_mii_phy(tp, force_reset);
else
err = tg3_setup_copper_phy(tp, force_reset);
if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
u32 scale;
val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
scale = 65;
else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
scale = 6;
else
scale = 12;
val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
tw32(GRC_MISC_CFG, val);
}
val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT);
if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
tg3_asic_rev(tp) == ASIC_REV_5762)
val |= tr32(MAC_TX_LENGTHS) &
(TX_LENGTHS_JMB_FRM_LEN_MSK |
TX_LENGTHS_CNT_DWN_VAL_MSK);
if (tp->link_config.active_speed == SPEED_1000 &&
tp->link_config.active_duplex == DUPLEX_HALF)
tw32(MAC_TX_LENGTHS, val |
(0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
else
tw32(MAC_TX_LENGTHS, val |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT));
if (!tg3_flag(tp, 5705_PLUS)) {
if (tp->link_up) {
tw32(HOSTCC_STAT_COAL_TICKS,
tp->coal.stats_block_coalesce_usecs);
} else {
tw32(HOSTCC_STAT_COAL_TICKS, 0);
}
}
if (tg3_flag(tp, ASPM_WORKAROUND)) {
val = tr32(PCIE_PWR_MGMT_THRESH);
if (!tp->link_up)
val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
tp->pwrmgmt_thresh;
else
val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
tw32(PCIE_PWR_MGMT_THRESH, val);
}
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_setup_phy(struct tg3 *tp, int force_reset)
{
u32 val;
int err;
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
err = tg3_setup_fiber_phy(tp, force_reset);
else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
err = tg3_setup_fiber_mii_phy(tp, force_reset);
else
err = tg3_setup_copper_phy(tp, force_reset);
if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
u32 scale;
val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
scale = 65;
else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
scale = 6;
else
scale = 12;
val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
tw32(GRC_MISC_CFG, val);
}
val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT);
if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
tg3_asic_rev(tp) == ASIC_REV_5762)
val |= tr32(MAC_TX_LENGTHS) &
(TX_LENGTHS_JMB_FRM_LEN_MSK |
TX_LENGTHS_CNT_DWN_VAL_MSK);
if (tp->link_config.active_speed == SPEED_1000 &&
tp->link_config.active_duplex == DUPLEX_HALF)
tw32(MAC_TX_LENGTHS, val |
(0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
else
tw32(MAC_TX_LENGTHS, val |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT));
if (!tg3_flag(tp, 5705_PLUS)) {
if (tp->link_up) {
tw32(HOSTCC_STAT_COAL_TICKS,
tp->coal.stats_block_coalesce_usecs);
} else {
tw32(HOSTCC_STAT_COAL_TICKS, 0);
}
}
if (tg3_flag(tp, ASPM_WORKAROUND)) {
val = tr32(PCIE_PWR_MGMT_THRESH);
if (!tp->link_up)
val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
tp->pwrmgmt_thresh;
else
val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
tw32(PCIE_PWR_MGMT_THRESH, val);
}
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,276 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
{
u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
if (!tg3_flag(tp, 5750_PLUS) ||
tg3_flag(tp, 5780_CLASS) ||
tg3_asic_rev(tp) == ASIC_REV_5750 ||
tg3_asic_rev(tp) == ASIC_REV_5752 ||
tg3_flag(tp, 57765_PLUS))
bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
tg3_asic_rev(tp) == ASIC_REV_5787)
bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
else
bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
val = min(nic_rep_thresh, host_rep_thresh);
tw32(RCVBDI_STD_THRESH, val);
if (tg3_flag(tp, 57765_PLUS))
tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
return;
bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
val = min(bdcache_maxcnt / 2, host_rep_thresh);
tw32(RCVBDI_JUMBO_THRESH, val);
if (tg3_flag(tp, 57765_PLUS))
tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
}
| DoS Exec Code Overflow | 0 | static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
{
u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
if (!tg3_flag(tp, 5750_PLUS) ||
tg3_flag(tp, 5780_CLASS) ||
tg3_asic_rev(tp) == ASIC_REV_5750 ||
tg3_asic_rev(tp) == ASIC_REV_5752 ||
tg3_flag(tp, 57765_PLUS))
bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
tg3_asic_rev(tp) == ASIC_REV_5787)
bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
else
bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
val = min(nic_rep_thresh, host_rep_thresh);
tw32(RCVBDI_STD_THRESH, val);
if (tg3_flag(tp, 57765_PLUS))
tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
return;
bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
val = min(bdcache_maxcnt / 2, host_rep_thresh);
tw32(RCVBDI_JUMBO_THRESH, val);
if (tg3_flag(tp, 57765_PLUS))
tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,277 | static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
bool init)
{
struct net_device *dev = tp->dev;
int i, err;
/*
* Setup interrupts first so we know how
* many NAPI resources to allocate
*/
tg3_ints_init(tp);
tg3_rss_check_indir_tbl(tp);
/* The placement of this call is tied
* to the setup and use of Host TX descriptors.
*/
err = tg3_alloc_consistent(tp);
if (err)
goto err_out1;
tg3_napi_init(tp);
tg3_napi_enable(tp);
for (i = 0; i < tp->irq_cnt; i++) {
struct tg3_napi *tnapi = &tp->napi[i];
err = tg3_request_irq(tp, i);
if (err) {
for (i--; i >= 0; i--) {
tnapi = &tp->napi[i];
free_irq(tnapi->irq_vec, tnapi);
}
goto err_out2;
}
}
tg3_full_lock(tp, 0);
err = tg3_init_hw(tp, reset_phy);
if (err) {
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_free_rings(tp);
}
tg3_full_unlock(tp);
if (err)
goto err_out3;
if (test_irq && tg3_flag(tp, USING_MSI)) {
err = tg3_test_msi(tp);
if (err) {
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_free_rings(tp);
tg3_full_unlock(tp);
goto err_out2;
}
if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
u32 val = tr32(PCIE_TRANSACTION_CFG);
tw32(PCIE_TRANSACTION_CFG,
val | PCIE_TRANS_CFG_1SHOT_MSI);
}
}
tg3_phy_start(tp);
tg3_hwmon_open(tp);
tg3_full_lock(tp, 0);
tg3_timer_start(tp);
tg3_flag_set(tp, INIT_COMPLETE);
tg3_enable_ints(tp);
if (init)
tg3_ptp_init(tp);
else
tg3_ptp_resume(tp);
tg3_full_unlock(tp);
netif_tx_start_all_queues(dev);
/*
* Reset loopback feature if it was turned on while the device was down
* make sure that it's installed properly now.
*/
if (dev->features & NETIF_F_LOOPBACK)
tg3_set_loopback(dev, dev->features);
return 0;
err_out3:
for (i = tp->irq_cnt - 1; i >= 0; i--) {
struct tg3_napi *tnapi = &tp->napi[i];
free_irq(tnapi->irq_vec, tnapi);
}
err_out2:
tg3_napi_disable(tp);
tg3_napi_fini(tp);
tg3_free_consistent(tp);
err_out1:
tg3_ints_fini(tp);
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
bool init)
{
struct net_device *dev = tp->dev;
int i, err;
/*
* Setup interrupts first so we know how
* many NAPI resources to allocate
*/
tg3_ints_init(tp);
tg3_rss_check_indir_tbl(tp);
/* The placement of this call is tied
* to the setup and use of Host TX descriptors.
*/
err = tg3_alloc_consistent(tp);
if (err)
goto err_out1;
tg3_napi_init(tp);
tg3_napi_enable(tp);
for (i = 0; i < tp->irq_cnt; i++) {
struct tg3_napi *tnapi = &tp->napi[i];
err = tg3_request_irq(tp, i);
if (err) {
for (i--; i >= 0; i--) {
tnapi = &tp->napi[i];
free_irq(tnapi->irq_vec, tnapi);
}
goto err_out2;
}
}
tg3_full_lock(tp, 0);
err = tg3_init_hw(tp, reset_phy);
if (err) {
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_free_rings(tp);
}
tg3_full_unlock(tp);
if (err)
goto err_out3;
if (test_irq && tg3_flag(tp, USING_MSI)) {
err = tg3_test_msi(tp);
if (err) {
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_free_rings(tp);
tg3_full_unlock(tp);
goto err_out2;
}
if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
u32 val = tr32(PCIE_TRANSACTION_CFG);
tw32(PCIE_TRANSACTION_CFG,
val | PCIE_TRANS_CFG_1SHOT_MSI);
}
}
tg3_phy_start(tp);
tg3_hwmon_open(tp);
tg3_full_lock(tp, 0);
tg3_timer_start(tp);
tg3_flag_set(tp, INIT_COMPLETE);
tg3_enable_ints(tp);
if (init)
tg3_ptp_init(tp);
else
tg3_ptp_resume(tp);
tg3_full_unlock(tp);
netif_tx_start_all_queues(dev);
/*
* Reset loopback feature if it was turned on while the device was down
* make sure that it's installed properly now.
*/
if (dev->features & NETIF_F_LOOPBACK)
tg3_set_loopback(dev, dev->features);
return 0;
err_out3:
for (i = tp->irq_cnt - 1; i >= 0; i--) {
struct tg3_napi *tnapi = &tp->napi[i];
free_irq(tnapi->irq_vec, tnapi);
}
err_out2:
tg3_napi_disable(tp);
tg3_napi_fini(tp);
tg3_free_consistent(tp);
err_out1:
tg3_ints_fini(tp);
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,278 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct tg3 *tp = netdev_priv(dev);
u32 len, entry, base_flags, mss, vlan = 0;
u32 budget;
int i = -1, would_hit_hwbug;
dma_addr_t mapping;
struct tg3_napi *tnapi;
struct netdev_queue *txq;
unsigned int last;
txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
tnapi = &tp->napi[skb_get_queue_mapping(skb)];
if (tg3_flag(tp, ENABLE_TSS))
tnapi++;
budget = tg3_tx_avail(tnapi);
/* We are running in BH disabled context with netif_tx_lock
* and TX reclaim runs via tp->napi.poll inside of a software
* interrupt. Furthermore, IRQ processing runs lockless so we have
* no IRQ context deadlocks to worry about either. Rejoice!
*/
if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
if (!netif_tx_queue_stopped(txq)) {
netif_tx_stop_queue(txq);
/* This is a hard error, log it. */
netdev_err(dev,
"BUG! Tx Ring full when queue awake!\n");
}
return NETDEV_TX_BUSY;
}
entry = tnapi->tx_prod;
base_flags = 0;
if (skb->ip_summed == CHECKSUM_PARTIAL)
base_flags |= TXD_FLAG_TCPUDP_CSUM;
mss = skb_shinfo(skb)->gso_size;
if (mss) {
struct iphdr *iph;
u32 tcp_opt_len, hdr_len;
if (skb_header_cloned(skb) &&
pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
goto drop;
iph = ip_hdr(skb);
tcp_opt_len = tcp_optlen(skb);
hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
if (!skb_is_gso_v6(skb)) {
iph->check = 0;
iph->tot_len = htons(mss + hdr_len);
}
if (unlikely((ETH_HLEN + hdr_len) > 80) &&
tg3_flag(tp, TSO_BUG))
return tg3_tso_bug(tp, skb);
base_flags |= (TXD_FLAG_CPU_PRE_DMA |
TXD_FLAG_CPU_POST_DMA);
if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3)) {
tcp_hdr(skb)->check = 0;
base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
} else
tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
iph->daddr, 0,
IPPROTO_TCP,
0);
if (tg3_flag(tp, HW_TSO_3)) {
mss |= (hdr_len & 0xc) << 12;
if (hdr_len & 0x10)
base_flags |= 0x00000010;
base_flags |= (hdr_len & 0x3e0) << 5;
} else if (tg3_flag(tp, HW_TSO_2))
mss |= hdr_len << 9;
else if (tg3_flag(tp, HW_TSO_1) ||
tg3_asic_rev(tp) == ASIC_REV_5705) {
if (tcp_opt_len || iph->ihl > 5) {
int tsflags;
tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
mss |= (tsflags << 11);
}
} else {
if (tcp_opt_len || iph->ihl > 5) {
int tsflags;
tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
base_flags |= tsflags << 12;
}
}
}
if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
!mss && skb->len > VLAN_ETH_FRAME_LEN)
base_flags |= TXD_FLAG_JMB_PKT;
if (vlan_tx_tag_present(skb)) {
base_flags |= TXD_FLAG_VLAN;
vlan = vlan_tx_tag_get(skb);
}
if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
tg3_flag(tp, TX_TSTAMP_EN)) {
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
base_flags |= TXD_FLAG_HWTSTAMP;
}
len = skb_headlen(skb);
mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
if (pci_dma_mapping_error(tp->pdev, mapping))
goto drop;
tnapi->tx_buffers[entry].skb = skb;
dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
would_hit_hwbug = 0;
if (tg3_flag(tp, 5701_DMA_BUG))
would_hit_hwbug = 1;
if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
mss, vlan)) {
would_hit_hwbug = 1;
} else if (skb_shinfo(skb)->nr_frags > 0) {
u32 tmp_mss = mss;
if (!tg3_flag(tp, HW_TSO_1) &&
!tg3_flag(tp, HW_TSO_2) &&
!tg3_flag(tp, HW_TSO_3))
tmp_mss = 0;
/* Now loop through additional data
* fragments, and queue them.
*/
last = skb_shinfo(skb)->nr_frags - 1;
for (i = 0; i <= last; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
len = skb_frag_size(frag);
mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
len, DMA_TO_DEVICE);
tnapi->tx_buffers[entry].skb = NULL;
dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
mapping);
if (dma_mapping_error(&tp->pdev->dev, mapping))
goto dma_error;
if (!budget ||
tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
len, base_flags |
((i == last) ? TXD_FLAG_END : 0),
tmp_mss, vlan)) {
would_hit_hwbug = 1;
break;
}
}
}
if (would_hit_hwbug) {
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
/* If the workaround fails due to memory/mapping
* failure, silently drop this packet.
*/
entry = tnapi->tx_prod;
budget = tg3_tx_avail(tnapi);
if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
base_flags, mss, vlan))
goto drop_nofree;
}
skb_tx_timestamp(skb);
netdev_tx_sent_queue(txq, skb->len);
/* Sync BD data before updating mailbox */
wmb();
/* Packets are ready, update Tx producer idx local and on card. */
tw32_tx_mbox(tnapi->prodmbox, entry);
tnapi->tx_prod = entry;
if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
netif_tx_stop_queue(txq);
/* netif_tx_stop_queue() must be done before checking
* checking tx index in tg3_tx_avail() below, because in
* tg3_tx(), we update tx index before checking for
* netif_tx_queue_stopped().
*/
smp_mb();
if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
netif_tx_wake_queue(txq);
}
mmiowb();
return NETDEV_TX_OK;
dma_error:
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
drop:
dev_kfree_skb(skb);
drop_nofree:
tp->tx_dropped++;
return NETDEV_TX_OK;
}
| DoS Exec Code Overflow | 0 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct tg3 *tp = netdev_priv(dev);
u32 len, entry, base_flags, mss, vlan = 0;
u32 budget;
int i = -1, would_hit_hwbug;
dma_addr_t mapping;
struct tg3_napi *tnapi;
struct netdev_queue *txq;
unsigned int last;
txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
tnapi = &tp->napi[skb_get_queue_mapping(skb)];
if (tg3_flag(tp, ENABLE_TSS))
tnapi++;
budget = tg3_tx_avail(tnapi);
/* We are running in BH disabled context with netif_tx_lock
* and TX reclaim runs via tp->napi.poll inside of a software
* interrupt. Furthermore, IRQ processing runs lockless so we have
* no IRQ context deadlocks to worry about either. Rejoice!
*/
if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
if (!netif_tx_queue_stopped(txq)) {
netif_tx_stop_queue(txq);
/* This is a hard error, log it. */
netdev_err(dev,
"BUG! Tx Ring full when queue awake!\n");
}
return NETDEV_TX_BUSY;
}
entry = tnapi->tx_prod;
base_flags = 0;
if (skb->ip_summed == CHECKSUM_PARTIAL)
base_flags |= TXD_FLAG_TCPUDP_CSUM;
mss = skb_shinfo(skb)->gso_size;
if (mss) {
struct iphdr *iph;
u32 tcp_opt_len, hdr_len;
if (skb_header_cloned(skb) &&
pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
goto drop;
iph = ip_hdr(skb);
tcp_opt_len = tcp_optlen(skb);
hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
if (!skb_is_gso_v6(skb)) {
iph->check = 0;
iph->tot_len = htons(mss + hdr_len);
}
if (unlikely((ETH_HLEN + hdr_len) > 80) &&
tg3_flag(tp, TSO_BUG))
return tg3_tso_bug(tp, skb);
base_flags |= (TXD_FLAG_CPU_PRE_DMA |
TXD_FLAG_CPU_POST_DMA);
if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3)) {
tcp_hdr(skb)->check = 0;
base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
} else
tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
iph->daddr, 0,
IPPROTO_TCP,
0);
if (tg3_flag(tp, HW_TSO_3)) {
mss |= (hdr_len & 0xc) << 12;
if (hdr_len & 0x10)
base_flags |= 0x00000010;
base_flags |= (hdr_len & 0x3e0) << 5;
} else if (tg3_flag(tp, HW_TSO_2))
mss |= hdr_len << 9;
else if (tg3_flag(tp, HW_TSO_1) ||
tg3_asic_rev(tp) == ASIC_REV_5705) {
if (tcp_opt_len || iph->ihl > 5) {
int tsflags;
tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
mss |= (tsflags << 11);
}
} else {
if (tcp_opt_len || iph->ihl > 5) {
int tsflags;
tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
base_flags |= tsflags << 12;
}
}
}
if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
!mss && skb->len > VLAN_ETH_FRAME_LEN)
base_flags |= TXD_FLAG_JMB_PKT;
if (vlan_tx_tag_present(skb)) {
base_flags |= TXD_FLAG_VLAN;
vlan = vlan_tx_tag_get(skb);
}
if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
tg3_flag(tp, TX_TSTAMP_EN)) {
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
base_flags |= TXD_FLAG_HWTSTAMP;
}
len = skb_headlen(skb);
mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
if (pci_dma_mapping_error(tp->pdev, mapping))
goto drop;
tnapi->tx_buffers[entry].skb = skb;
dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
would_hit_hwbug = 0;
if (tg3_flag(tp, 5701_DMA_BUG))
would_hit_hwbug = 1;
if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
mss, vlan)) {
would_hit_hwbug = 1;
} else if (skb_shinfo(skb)->nr_frags > 0) {
u32 tmp_mss = mss;
if (!tg3_flag(tp, HW_TSO_1) &&
!tg3_flag(tp, HW_TSO_2) &&
!tg3_flag(tp, HW_TSO_3))
tmp_mss = 0;
/* Now loop through additional data
* fragments, and queue them.
*/
last = skb_shinfo(skb)->nr_frags - 1;
for (i = 0; i <= last; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
len = skb_frag_size(frag);
mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
len, DMA_TO_DEVICE);
tnapi->tx_buffers[entry].skb = NULL;
dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
mapping);
if (dma_mapping_error(&tp->pdev->dev, mapping))
goto dma_error;
if (!budget ||
tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
len, base_flags |
((i == last) ? TXD_FLAG_END : 0),
tmp_mss, vlan)) {
would_hit_hwbug = 1;
break;
}
}
}
if (would_hit_hwbug) {
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
/* If the workaround fails due to memory/mapping
* failure, silently drop this packet.
*/
entry = tnapi->tx_prod;
budget = tg3_tx_avail(tnapi);
if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
base_flags, mss, vlan))
goto drop_nofree;
}
skb_tx_timestamp(skb);
netdev_tx_sent_queue(txq, skb->len);
/* Sync BD data before updating mailbox */
wmb();
/* Packets are ready, update Tx producer idx local and on card. */
tw32_tx_mbox(tnapi->prodmbox, entry);
tnapi->tx_prod = entry;
if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
netif_tx_stop_queue(txq);
/* netif_tx_stop_queue() must be done before checking
* checking tx index in tg3_tx_avail() below, because in
* tg3_tx(), we update tx index before checking for
* netif_tx_queue_stopped().
*/
smp_mb();
if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
netif_tx_wake_queue(txq);
}
mmiowb();
return NETDEV_TX_OK;
dma_error:
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
drop:
dev_kfree_skb(skb);
drop_nofree:
tp->tx_dropped++;
return NETDEV_TX_OK;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,279 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
{
unsigned int i;
u32 val;
if (tg3_flag(tp, 5705_PLUS)) {
switch (ofs) {
case RCVLSC_MODE:
case DMAC_MODE:
case MBFREE_MODE:
case BUFMGR_MODE:
case MEMARB_MODE:
/* We can't enable/disable these bits of the
* 5705/5750, just say success.
*/
return 0;
default:
break;
}
}
val = tr32(ofs);
val &= ~enable_bit;
tw32_f(ofs, val);
for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100);
val = tr32(ofs);
if ((val & enable_bit) == 0)
break;
}
if (i == MAX_WAIT_CNT && !silent) {
dev_err(&tp->pdev->dev,
"tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
ofs, enable_bit);
return -ENODEV;
}
return 0;
}
| DoS Exec Code Overflow | 0 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
{
unsigned int i;
u32 val;
if (tg3_flag(tp, 5705_PLUS)) {
switch (ofs) {
case RCVLSC_MODE:
case DMAC_MODE:
case MBFREE_MODE:
case BUFMGR_MODE:
case MEMARB_MODE:
/* We can't enable/disable these bits of the
* 5705/5750, just say success.
*/
return 0;
default:
break;
}
}
val = tr32(ofs);
val &= ~enable_bit;
tw32_f(ofs, val);
for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100);
val = tr32(ofs);
if ((val & enable_bit) == 0)
break;
}
if (i == MAX_WAIT_CNT && !silent) {
dev_err(&tp->pdev->dev,
"tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
ofs, enable_bit);
return -ENODEV;
}
return 0;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,280 | static void tg3_stop_fw(struct tg3 *tp)
{
if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
/* Wait for RX cpu to ACK the previous event. */
tg3_wait_for_event_ack(tp);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
tg3_generate_fw_event(tp);
/* Wait for RX cpu to ACK this event. */
tg3_wait_for_event_ack(tp);
}
}
| DoS Exec Code Overflow | 0 | static void tg3_stop_fw(struct tg3 *tp)
{
if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
/* Wait for RX cpu to ACK the previous event. */
tg3_wait_for_event_ack(tp);
tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
tg3_generate_fw_event(tp);
/* Wait for RX cpu to ACK this event. */
tg3_wait_for_event_ack(tp);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,281 | static int tg3_suspend(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
struct net_device *dev = pci_get_drvdata(pdev);
struct tg3 *tp = netdev_priv(dev);
int err;
if (!netif_running(dev))
return 0;
tg3_reset_task_cancel(tp);
tg3_phy_stop(tp);
tg3_netif_stop(tp);
tg3_timer_stop(tp);
tg3_full_lock(tp, 1);
tg3_disable_ints(tp);
tg3_full_unlock(tp);
netif_device_detach(dev);
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_flag_clear(tp, INIT_COMPLETE);
tg3_full_unlock(tp);
err = tg3_power_down_prepare(tp);
if (err) {
int err2;
tg3_full_lock(tp, 0);
tg3_flag_set(tp, INIT_COMPLETE);
err2 = tg3_restart_hw(tp, 1);
if (err2)
goto out;
tg3_timer_start(tp);
netif_device_attach(dev);
tg3_netif_start(tp);
out:
tg3_full_unlock(tp);
if (!err2)
tg3_phy_start(tp);
}
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_suspend(struct device *device)
{
struct pci_dev *pdev = to_pci_dev(device);
struct net_device *dev = pci_get_drvdata(pdev);
struct tg3 *tp = netdev_priv(dev);
int err;
if (!netif_running(dev))
return 0;
tg3_reset_task_cancel(tp);
tg3_phy_stop(tp);
tg3_netif_stop(tp);
tg3_timer_stop(tp);
tg3_full_lock(tp, 1);
tg3_disable_ints(tp);
tg3_full_unlock(tp);
netif_device_detach(dev);
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_flag_clear(tp, INIT_COMPLETE);
tg3_full_unlock(tp);
err = tg3_power_down_prepare(tp);
if (err) {
int err2;
tg3_full_lock(tp, 0);
tg3_flag_set(tp, INIT_COMPLETE);
err2 = tg3_restart_hw(tp, 1);
if (err2)
goto out;
tg3_timer_start(tp);
netif_device_attach(dev);
tg3_netif_start(tp);
out:
tg3_full_unlock(tp);
if (!err2)
tg3_phy_start(tp);
}
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,282 | static void tg3_switch_clocks(struct tg3 *tp)
{
u32 clock_ctrl;
u32 orig_clock_ctrl;
if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
return;
clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
orig_clock_ctrl = clock_ctrl;
clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
CLOCK_CTRL_CLKRUN_OENABLE |
0x1f);
tp->pci_clock_ctrl = clock_ctrl;
if (tg3_flag(tp, 5705_PLUS)) {
if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
tw32_wait_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | CLOCK_CTRL_625_CORE, 40);
}
} else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
tw32_wait_f(TG3PCI_CLOCK_CTRL,
clock_ctrl |
(CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
40);
tw32_wait_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | (CLOCK_CTRL_ALTCLK),
40);
}
tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
}
| DoS Exec Code Overflow | 0 | static void tg3_switch_clocks(struct tg3 *tp)
{
u32 clock_ctrl;
u32 orig_clock_ctrl;
if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
return;
clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
orig_clock_ctrl = clock_ctrl;
clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
CLOCK_CTRL_CLKRUN_OENABLE |
0x1f);
tp->pci_clock_ctrl = clock_ctrl;
if (tg3_flag(tp, 5705_PLUS)) {
if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
tw32_wait_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | CLOCK_CTRL_625_CORE, 40);
}
} else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
tw32_wait_f(TG3PCI_CLOCK_CTRL,
clock_ctrl |
(CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
40);
tw32_wait_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | (CLOCK_CTRL_ALTCLK),
40);
}
tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,283 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
{
if (curr_link_up != tp->link_up) {
if (curr_link_up) {
netif_carrier_on(tp->dev);
} else {
netif_carrier_off(tp->dev);
if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
}
tg3_link_report(tp);
return true;
}
return false;
}
| DoS Exec Code Overflow | 0 | static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
{
if (curr_link_up != tp->link_up) {
if (curr_link_up) {
netif_carrier_on(tp->dev);
} else {
netif_carrier_off(tp->dev);
if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
}
tg3_link_report(tp);
return true;
}
return false;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,284 | static int tg3_test_dma(struct tg3 *tp)
{
dma_addr_t buf_dma;
u32 *buf, saved_dma_rwctrl;
int ret = 0;
buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
&buf_dma, GFP_KERNEL);
if (!buf) {
ret = -ENOMEM;
goto out_nofree;
}
tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
if (tg3_flag(tp, 57765_PLUS))
goto out;
if (tg3_flag(tp, PCI_EXPRESS)) {
/* DMA read watermark not used on PCIE */
tp->dma_rwctrl |= 0x00180000;
} else if (!tg3_flag(tp, PCIX_MODE)) {
if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
tg3_asic_rev(tp) == ASIC_REV_5750)
tp->dma_rwctrl |= 0x003f0000;
else
tp->dma_rwctrl |= 0x003f000f;
} else {
if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704) {
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
u32 read_water = 0x7;
/* If the 5704 is behind the EPB bridge, we can
* do the less restrictive ONE_DMA workaround for
* better performance.
*/
if (tg3_flag(tp, 40BIT_DMA_BUG) &&
tg3_asic_rev(tp) == ASIC_REV_5704)
tp->dma_rwctrl |= 0x8000;
else if (ccval == 0x6 || ccval == 0x7)
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
if (tg3_asic_rev(tp) == ASIC_REV_5703)
read_water = 4;
/* Set bit 23 to enable PCIX hw bug fix */
tp->dma_rwctrl |=
(read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(1 << 23);
} else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
/* 5780 always in PCIX mode */
tp->dma_rwctrl |= 0x00144000;
} else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
/* 5714 always in PCIX mode */
tp->dma_rwctrl |= 0x00148000;
} else {
tp->dma_rwctrl |= 0x001b000f;
}
}
if (tg3_flag(tp, ONE_DMA_AT_ONCE))
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704)
tp->dma_rwctrl &= 0xfffffff0;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
/* Remove this if it causes problems for some boards. */
tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
/* On 5700/5701 chips, we need to set this bit.
* Otherwise the chip will issue cacheline transactions
* to streamable DMA memory with not all the byte
* enables turned on. This is an error on several
* RISC PCI controllers, in particular sparc64.
*
* On 5703/5704 chips, this bit has been reassigned
* a different meaning. In particular, it is used
* on those chips to enable a PCI-X workaround.
*/
tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
}
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
#if 0
/* Unneeded, already done by tg3_get_invariants. */
tg3_switch_clocks(tp);
#endif
if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
tg3_asic_rev(tp) != ASIC_REV_5701)
goto out;
/* It is best to perform DMA test with maximum write burst size
* to expose the 5700/5701 write DMA bug.
*/
saved_dma_rwctrl = tp->dma_rwctrl;
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
while (1) {
u32 *p = buf, i;
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
p[i] = i;
/* Send the buffer to the chip. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
if (ret) {
dev_err(&tp->pdev->dev,
"%s: Buffer write failed. err = %d\n",
__func__, ret);
break;
}
#if 0
/* validate data reached card RAM correctly. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
u32 val;
tg3_read_mem(tp, 0x2100 + (i*4), &val);
if (le32_to_cpu(val) != p[i]) {
dev_err(&tp->pdev->dev,
"%s: Buffer corrupted on device! "
"(%d != %d)\n", __func__, val, i);
/* ret = -ENODEV here? */
}
p[i] = 0;
}
#endif
/* Now read it back. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
if (ret) {
dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
"err = %d\n", __func__, ret);
break;
}
/* Verify it. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
if (p[i] == i)
continue;
if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
DMA_RWCTRL_WRITE_BNDRY_16) {
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
break;
} else {
dev_err(&tp->pdev->dev,
"%s: Buffer corrupted on read back! "
"(%d != %d)\n", __func__, p[i], i);
ret = -ENODEV;
goto out;
}
}
if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
/* Success. */
ret = 0;
break;
}
}
if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
DMA_RWCTRL_WRITE_BNDRY_16) {
/* DMA test passed without adjusting DMA boundary,
* now look for chipsets that are known to expose the
* DMA bug without failing the test.
*/
if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
} else {
/* Safe to use the calculated DMA boundary. */
tp->dma_rwctrl = saved_dma_rwctrl;
}
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
}
out:
dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
out_nofree:
return ret;
}
| DoS Exec Code Overflow | 0 | static int tg3_test_dma(struct tg3 *tp)
{
dma_addr_t buf_dma;
u32 *buf, saved_dma_rwctrl;
int ret = 0;
buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
&buf_dma, GFP_KERNEL);
if (!buf) {
ret = -ENOMEM;
goto out_nofree;
}
tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
if (tg3_flag(tp, 57765_PLUS))
goto out;
if (tg3_flag(tp, PCI_EXPRESS)) {
/* DMA read watermark not used on PCIE */
tp->dma_rwctrl |= 0x00180000;
} else if (!tg3_flag(tp, PCIX_MODE)) {
if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
tg3_asic_rev(tp) == ASIC_REV_5750)
tp->dma_rwctrl |= 0x003f0000;
else
tp->dma_rwctrl |= 0x003f000f;
} else {
if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704) {
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
u32 read_water = 0x7;
/* If the 5704 is behind the EPB bridge, we can
* do the less restrictive ONE_DMA workaround for
* better performance.
*/
if (tg3_flag(tp, 40BIT_DMA_BUG) &&
tg3_asic_rev(tp) == ASIC_REV_5704)
tp->dma_rwctrl |= 0x8000;
else if (ccval == 0x6 || ccval == 0x7)
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
if (tg3_asic_rev(tp) == ASIC_REV_5703)
read_water = 4;
/* Set bit 23 to enable PCIX hw bug fix */
tp->dma_rwctrl |=
(read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(1 << 23);
} else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
/* 5780 always in PCIX mode */
tp->dma_rwctrl |= 0x00144000;
} else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
/* 5714 always in PCIX mode */
tp->dma_rwctrl |= 0x00148000;
} else {
tp->dma_rwctrl |= 0x001b000f;
}
}
if (tg3_flag(tp, ONE_DMA_AT_ONCE))
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704)
tp->dma_rwctrl &= 0xfffffff0;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) {
/* Remove this if it causes problems for some boards. */
tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
/* On 5700/5701 chips, we need to set this bit.
* Otherwise the chip will issue cacheline transactions
* to streamable DMA memory with not all the byte
* enables turned on. This is an error on several
* RISC PCI controllers, in particular sparc64.
*
* On 5703/5704 chips, this bit has been reassigned
* a different meaning. In particular, it is used
* on those chips to enable a PCI-X workaround.
*/
tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
}
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
#if 0
/* Unneeded, already done by tg3_get_invariants. */
tg3_switch_clocks(tp);
#endif
if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
tg3_asic_rev(tp) != ASIC_REV_5701)
goto out;
/* It is best to perform DMA test with maximum write burst size
* to expose the 5700/5701 write DMA bug.
*/
saved_dma_rwctrl = tp->dma_rwctrl;
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
while (1) {
u32 *p = buf, i;
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
p[i] = i;
/* Send the buffer to the chip. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
if (ret) {
dev_err(&tp->pdev->dev,
"%s: Buffer write failed. err = %d\n",
__func__, ret);
break;
}
#if 0
/* validate data reached card RAM correctly. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
u32 val;
tg3_read_mem(tp, 0x2100 + (i*4), &val);
if (le32_to_cpu(val) != p[i]) {
dev_err(&tp->pdev->dev,
"%s: Buffer corrupted on device! "
"(%d != %d)\n", __func__, val, i);
/* ret = -ENODEV here? */
}
p[i] = 0;
}
#endif
/* Now read it back. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
if (ret) {
dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
"err = %d\n", __func__, ret);
break;
}
/* Verify it. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
if (p[i] == i)
continue;
if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
DMA_RWCTRL_WRITE_BNDRY_16) {
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
break;
} else {
dev_err(&tp->pdev->dev,
"%s: Buffer corrupted on read back! "
"(%d != %d)\n", __func__, p[i], i);
ret = -ENODEV;
goto out;
}
}
if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
/* Success. */
ret = 0;
break;
}
}
if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
DMA_RWCTRL_WRITE_BNDRY_16) {
/* DMA test passed without adjusting DMA boundary,
* now look for chipsets that are known to expose the
* DMA bug without failing the test.
*/
if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
} else {
/* Safe to use the calculated DMA boundary. */
tp->dma_rwctrl = saved_dma_rwctrl;
}
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
}
out:
dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
out_nofree:
return ret;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,285 | static int tg3_test_interrupt(struct tg3 *tp)
{
struct tg3_napi *tnapi = &tp->napi[0];
struct net_device *dev = tp->dev;
int err, i, intr_ok = 0;
u32 val;
if (!netif_running(dev))
return -ENODEV;
tg3_disable_ints(tp);
free_irq(tnapi->irq_vec, tnapi);
/*
* Turn off MSI one shot mode. Otherwise this test has no
* observable way to know whether the interrupt was delivered.
*/
if (tg3_flag(tp, 57765_PLUS)) {
val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
}
err = request_irq(tnapi->irq_vec, tg3_test_isr,
IRQF_SHARED, dev->name, tnapi);
if (err)
return err;
tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
tg3_enable_ints(tp);
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
tnapi->coal_now);
for (i = 0; i < 5; i++) {
u32 int_mbox, misc_host_ctrl;
int_mbox = tr32_mailbox(tnapi->int_mbox);
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
if ((int_mbox != 0) ||
(misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
intr_ok = 1;
break;
}
if (tg3_flag(tp, 57765_PLUS) &&
tnapi->hw_status->status_tag != tnapi->last_tag)
tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
msleep(10);
}
tg3_disable_ints(tp);
free_irq(tnapi->irq_vec, tnapi);
err = tg3_request_irq(tp, 0);
if (err)
return err;
if (intr_ok) {
/* Reenable MSI one shot mode. */
if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
}
return 0;
}
return -EIO;
}
| DoS Exec Code Overflow | 0 | static int tg3_test_interrupt(struct tg3 *tp)
{
struct tg3_napi *tnapi = &tp->napi[0];
struct net_device *dev = tp->dev;
int err, i, intr_ok = 0;
u32 val;
if (!netif_running(dev))
return -ENODEV;
tg3_disable_ints(tp);
free_irq(tnapi->irq_vec, tnapi);
/*
* Turn off MSI one shot mode. Otherwise this test has no
* observable way to know whether the interrupt was delivered.
*/
if (tg3_flag(tp, 57765_PLUS)) {
val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
}
err = request_irq(tnapi->irq_vec, tg3_test_isr,
IRQF_SHARED, dev->name, tnapi);
if (err)
return err;
tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
tg3_enable_ints(tp);
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
tnapi->coal_now);
for (i = 0; i < 5; i++) {
u32 int_mbox, misc_host_ctrl;
int_mbox = tr32_mailbox(tnapi->int_mbox);
misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
if ((int_mbox != 0) ||
(misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
intr_ok = 1;
break;
}
if (tg3_flag(tp, 57765_PLUS) &&
tnapi->hw_status->status_tag != tnapi->last_tag)
tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
msleep(10);
}
tg3_disable_ints(tp);
free_irq(tnapi->irq_vec, tnapi);
err = tg3_request_irq(tp, 0);
if (err)
return err;
if (intr_ok) {
/* Reenable MSI one shot mode. */
if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
}
return 0;
}
return -EIO;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,286 | static irqreturn_t tg3_test_isr(int irq, void *dev_id)
{
struct tg3_napi *tnapi = dev_id;
struct tg3 *tp = tnapi->tp;
struct tg3_hw_status *sblk = tnapi->hw_status;
if ((sblk->status & SD_STATUS_UPDATED) ||
!(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
tg3_disable_ints(tp);
return IRQ_RETVAL(1);
}
return IRQ_RETVAL(0);
}
| DoS Exec Code Overflow | 0 | static irqreturn_t tg3_test_isr(int irq, void *dev_id)
{
struct tg3_napi *tnapi = dev_id;
struct tg3 *tp = tnapi->tp;
struct tg3_hw_status *sblk = tnapi->hw_status;
if ((sblk->status & SD_STATUS_UPDATED) ||
!(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
tg3_disable_ints(tp);
return IRQ_RETVAL(1);
}
return IRQ_RETVAL(0);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,287 | static int tg3_test_link(struct tg3 *tp)
{
int i, max;
if (!netif_running(tp->dev))
return -ENODEV;
if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
max = TG3_SERDES_TIMEOUT_SEC;
else
max = TG3_COPPER_TIMEOUT_SEC;
for (i = 0; i < max; i++) {
if (tp->link_up)
return 0;
if (msleep_interruptible(1000))
break;
}
return -EIO;
}
| DoS Exec Code Overflow | 0 | static int tg3_test_link(struct tg3 *tp)
{
int i, max;
if (!netif_running(tp->dev))
return -ENODEV;
if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
max = TG3_SERDES_TIMEOUT_SEC;
else
max = TG3_COPPER_TIMEOUT_SEC;
for (i = 0; i < max; i++) {
if (tp->link_up)
return 0;
if (msleep_interruptible(1000))
break;
}
return -EIO;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,288 | static int tg3_test_msi(struct tg3 *tp)
{
int err;
u16 pci_cmd;
if (!tg3_flag(tp, USING_MSI))
return 0;
/* Turn off SERR reporting in case MSI terminates with Master
* Abort.
*/
pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
pci_write_config_word(tp->pdev, PCI_COMMAND,
pci_cmd & ~PCI_COMMAND_SERR);
err = tg3_test_interrupt(tp);
pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
if (!err)
return 0;
/* other failures */
if (err != -EIO)
return err;
/* MSI test failed, go back to INTx mode */
netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
"to INTx mode. Please report this failure to the PCI "
"maintainer and include system chipset information\n");
free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
pci_disable_msi(tp->pdev);
tg3_flag_clear(tp, USING_MSI);
tp->napi[0].irq_vec = tp->pdev->irq;
err = tg3_request_irq(tp, 0);
if (err)
return err;
/* Need to reset the chip because the MSI cycle may have terminated
* with Master Abort.
*/
tg3_full_lock(tp, 1);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
err = tg3_init_hw(tp, 1);
tg3_full_unlock(tp);
if (err)
free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_test_msi(struct tg3 *tp)
{
int err;
u16 pci_cmd;
if (!tg3_flag(tp, USING_MSI))
return 0;
/* Turn off SERR reporting in case MSI terminates with Master
* Abort.
*/
pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
pci_write_config_word(tp->pdev, PCI_COMMAND,
pci_cmd & ~PCI_COMMAND_SERR);
err = tg3_test_interrupt(tp);
pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
if (!err)
return 0;
/* other failures */
if (err != -EIO)
return err;
/* MSI test failed, go back to INTx mode */
netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
"to INTx mode. Please report this failure to the PCI "
"maintainer and include system chipset information\n");
free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
pci_disable_msi(tp->pdev);
tg3_flag_clear(tp, USING_MSI);
tp->napi[0].irq_vec = tp->pdev->irq;
err = tg3_request_irq(tp, 0);
if (err)
return err;
/* Need to reset the chip because the MSI cycle may have terminated
* with Master Abort.
*/
tg3_full_lock(tp, 1);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
err = tg3_init_hw(tp, 1);
tg3_full_unlock(tp);
if (err)
free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,289 | static int tg3_test_nvram(struct tg3 *tp)
{
u32 csum, magic, len;
__be32 *buf;
int i, j, k, err = 0, size;
if (tg3_flag(tp, NO_NVRAM))
return 0;
if (tg3_nvram_read(tp, 0, &magic) != 0)
return -EIO;
if (magic == TG3_EEPROM_MAGIC)
size = NVRAM_TEST_SIZE;
else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
TG3_EEPROM_SB_FORMAT_1) {
switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
case TG3_EEPROM_SB_REVISION_0:
size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
break;
case TG3_EEPROM_SB_REVISION_2:
size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
break;
case TG3_EEPROM_SB_REVISION_3:
size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
break;
case TG3_EEPROM_SB_REVISION_4:
size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
break;
case TG3_EEPROM_SB_REVISION_5:
size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
break;
case TG3_EEPROM_SB_REVISION_6:
size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
break;
default:
return -EIO;
}
} else
return 0;
} else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
size = NVRAM_SELFBOOT_HW_SIZE;
else
return -EIO;
buf = kmalloc(size, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
err = -EIO;
for (i = 0, j = 0; i < size; i += 4, j++) {
err = tg3_nvram_read_be32(tp, i, &buf[j]);
if (err)
break;
}
if (i < size)
goto out;
/* Selfboot format */
magic = be32_to_cpu(buf[0]);
if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
TG3_EEPROM_MAGIC_FW) {
u8 *buf8 = (u8 *) buf, csum8 = 0;
if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
TG3_EEPROM_SB_REVISION_2) {
/* For rev 2, the csum doesn't include the MBA. */
for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
csum8 += buf8[i];
for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
csum8 += buf8[i];
} else {
for (i = 0; i < size; i++)
csum8 += buf8[i];
}
if (csum8 == 0) {
err = 0;
goto out;
}
err = -EIO;
goto out;
}
if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
TG3_EEPROM_MAGIC_HW) {
u8 data[NVRAM_SELFBOOT_DATA_SIZE];
u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
u8 *buf8 = (u8 *) buf;
/* Separate the parity bits and the data bytes. */
for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
if ((i == 0) || (i == 8)) {
int l;
u8 msk;
for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
} else if (i == 16) {
int l;
u8 msk;
for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
}
data[j++] = buf8[i];
}
err = -EIO;
for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
u8 hw8 = hweight8(data[i]);
if ((hw8 & 0x1) && parity[i])
goto out;
else if (!(hw8 & 0x1) && !parity[i])
goto out;
}
err = 0;
goto out;
}
err = -EIO;
/* Bootstrap checksum at offset 0x10 */
csum = calc_crc((unsigned char *) buf, 0x10);
if (csum != le32_to_cpu(buf[0x10/4]))
goto out;
/* Manufacturing block starts at offset 0x74, checksum at 0xfc */
csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
if (csum != le32_to_cpu(buf[0xfc/4]))
goto out;
kfree(buf);
buf = tg3_vpd_readblock(tp, &len);
if (!buf)
return -ENOMEM;
i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
if (i > 0) {
j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
if (j < 0)
goto out;
if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
goto out;
i += PCI_VPD_LRDT_TAG_SIZE;
j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
PCI_VPD_RO_KEYWORD_CHKSUM);
if (j > 0) {
u8 csum8 = 0;
j += PCI_VPD_INFO_FLD_HDR_SIZE;
for (i = 0; i <= j; i++)
csum8 += ((u8 *)buf)[i];
if (csum8)
goto out;
}
}
err = 0;
out:
kfree(buf);
return err;
}
| DoS Exec Code Overflow | 0 | static int tg3_test_nvram(struct tg3 *tp)
{
u32 csum, magic, len;
__be32 *buf;
int i, j, k, err = 0, size;
if (tg3_flag(tp, NO_NVRAM))
return 0;
if (tg3_nvram_read(tp, 0, &magic) != 0)
return -EIO;
if (magic == TG3_EEPROM_MAGIC)
size = NVRAM_TEST_SIZE;
else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
TG3_EEPROM_SB_FORMAT_1) {
switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
case TG3_EEPROM_SB_REVISION_0:
size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
break;
case TG3_EEPROM_SB_REVISION_2:
size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
break;
case TG3_EEPROM_SB_REVISION_3:
size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
break;
case TG3_EEPROM_SB_REVISION_4:
size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
break;
case TG3_EEPROM_SB_REVISION_5:
size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
break;
case TG3_EEPROM_SB_REVISION_6:
size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
break;
default:
return -EIO;
}
} else
return 0;
} else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
size = NVRAM_SELFBOOT_HW_SIZE;
else
return -EIO;
buf = kmalloc(size, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
err = -EIO;
for (i = 0, j = 0; i < size; i += 4, j++) {
err = tg3_nvram_read_be32(tp, i, &buf[j]);
if (err)
break;
}
if (i < size)
goto out;
/* Selfboot format */
magic = be32_to_cpu(buf[0]);
if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
TG3_EEPROM_MAGIC_FW) {
u8 *buf8 = (u8 *) buf, csum8 = 0;
if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
TG3_EEPROM_SB_REVISION_2) {
/* For rev 2, the csum doesn't include the MBA. */
for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
csum8 += buf8[i];
for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
csum8 += buf8[i];
} else {
for (i = 0; i < size; i++)
csum8 += buf8[i];
}
if (csum8 == 0) {
err = 0;
goto out;
}
err = -EIO;
goto out;
}
if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
TG3_EEPROM_MAGIC_HW) {
u8 data[NVRAM_SELFBOOT_DATA_SIZE];
u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
u8 *buf8 = (u8 *) buf;
/* Separate the parity bits and the data bytes. */
for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
if ((i == 0) || (i == 8)) {
int l;
u8 msk;
for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
} else if (i == 16) {
int l;
u8 msk;
for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
}
data[j++] = buf8[i];
}
err = -EIO;
for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
u8 hw8 = hweight8(data[i]);
if ((hw8 & 0x1) && parity[i])
goto out;
else if (!(hw8 & 0x1) && !parity[i])
goto out;
}
err = 0;
goto out;
}
err = -EIO;
/* Bootstrap checksum at offset 0x10 */
csum = calc_crc((unsigned char *) buf, 0x10);
if (csum != le32_to_cpu(buf[0x10/4]))
goto out;
/* Manufacturing block starts at offset 0x74, checksum at 0xfc */
csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
if (csum != le32_to_cpu(buf[0xfc/4]))
goto out;
kfree(buf);
buf = tg3_vpd_readblock(tp, &len);
if (!buf)
return -ENOMEM;
i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
if (i > 0) {
j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
if (j < 0)
goto out;
if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
goto out;
i += PCI_VPD_LRDT_TAG_SIZE;
j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
PCI_VPD_RO_KEYWORD_CHKSUM);
if (j > 0) {
u8 csum8 = 0;
j += PCI_VPD_INFO_FLD_HDR_SIZE;
for (i = 0; i <= j; i++)
csum8 += ((u8 *)buf)[i];
if (csum8)
goto out;
}
}
err = 0;
out:
kfree(buf);
return err;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,290 | static int tg3_test_registers(struct tg3 *tp)
{
int i, is_5705, is_5750;
u32 offset, read_mask, write_mask, val, save_val, read_val;
static struct {
u16 offset;
u16 flags;
#define TG3_FL_5705 0x1
#define TG3_FL_NOT_5705 0x2
#define TG3_FL_NOT_5788 0x4
#define TG3_FL_NOT_5750 0x8
u32 read_mask;
u32 write_mask;
} reg_tbl[] = {
/* MAC Control Registers */
{ MAC_MODE, TG3_FL_NOT_5705,
0x00000000, 0x00ef6f8c },
{ MAC_MODE, TG3_FL_5705,
0x00000000, 0x01ef6b8c },
{ MAC_STATUS, TG3_FL_NOT_5705,
0x03800107, 0x00000000 },
{ MAC_STATUS, TG3_FL_5705,
0x03800100, 0x00000000 },
{ MAC_ADDR_0_HIGH, 0x0000,
0x00000000, 0x0000ffff },
{ MAC_ADDR_0_LOW, 0x0000,
0x00000000, 0xffffffff },
{ MAC_RX_MTU_SIZE, 0x0000,
0x00000000, 0x0000ffff },
{ MAC_TX_MODE, 0x0000,
0x00000000, 0x00000070 },
{ MAC_TX_LENGTHS, 0x0000,
0x00000000, 0x00003fff },
{ MAC_RX_MODE, TG3_FL_NOT_5705,
0x00000000, 0x000007fc },
{ MAC_RX_MODE, TG3_FL_5705,
0x00000000, 0x000007dc },
{ MAC_HASH_REG_0, 0x0000,
0x00000000, 0xffffffff },
{ MAC_HASH_REG_1, 0x0000,
0x00000000, 0xffffffff },
{ MAC_HASH_REG_2, 0x0000,
0x00000000, 0xffffffff },
{ MAC_HASH_REG_3, 0x0000,
0x00000000, 0xffffffff },
/* Receive Data and Receive BD Initiator Control Registers. */
{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
0x00000000, 0x00000003 },
{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVDBDI_STD_BD+0, 0x0000,
0x00000000, 0xffffffff },
{ RCVDBDI_STD_BD+4, 0x0000,
0x00000000, 0xffffffff },
{ RCVDBDI_STD_BD+8, 0x0000,
0x00000000, 0xffff0002 },
{ RCVDBDI_STD_BD+0xc, 0x0000,
0x00000000, 0xffffffff },
/* Receive BD Initiator Control Registers. */
{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVBDI_STD_THRESH, TG3_FL_5705,
0x00000000, 0x000003ff },
{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
/* Host Coalescing Control Registers. */
{ HOSTCC_MODE, TG3_FL_NOT_5705,
0x00000000, 0x00000004 },
{ HOSTCC_MODE, TG3_FL_5705,
0x00000000, 0x000000f6 },
{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXCOL_TICKS, TG3_FL_5705,
0x00000000, 0x000003ff },
{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXCOL_TICKS, TG3_FL_5705,
0x00000000, 0x000003ff },
{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
0x00000000, 0xffffffff },
{ HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
0x00000000, 0xffffffff },
{ HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
0xffffffff, 0x00000000 },
{ HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
0xffffffff, 0x00000000 },
/* Buffer Manager Control Registers. */
{ BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
0x00000000, 0x007fff80 },
{ BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
0x00000000, 0x007fffff },
{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
0x00000000, 0x0000003f },
{ BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
0x00000000, 0x000001ff },
{ BUFMGR_MB_HIGH_WATER, 0x0000,
0x00000000, 0x000001ff },
{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
0xffffffff, 0x00000000 },
{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
0xffffffff, 0x00000000 },
/* Mailbox Registers */
{ GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
0x00000000, 0x000001ff },
{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
0x00000000, 0x000001ff },
{ GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
0x00000000, 0x000007ff },
{ GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
0x00000000, 0x000001ff },
{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
};
is_5705 = is_5750 = 0;
if (tg3_flag(tp, 5705_PLUS)) {
is_5705 = 1;
if (tg3_flag(tp, 5750_PLUS))
is_5750 = 1;
}
for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
continue;
if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
continue;
if (tg3_flag(tp, IS_5788) &&
(reg_tbl[i].flags & TG3_FL_NOT_5788))
continue;
if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
continue;
offset = (u32) reg_tbl[i].offset;
read_mask = reg_tbl[i].read_mask;
write_mask = reg_tbl[i].write_mask;
/* Save the original register content */
save_val = tr32(offset);
/* Determine the read-only value. */
read_val = save_val & read_mask;
/* Write zero to the register, then make sure the read-only bits
* are not changed and the read/write bits are all zeros.
*/
tw32(offset, 0);
val = tr32(offset);
/* Test the read-only and read/write bits. */
if (((val & read_mask) != read_val) || (val & write_mask))
goto out;
/* Write ones to all the bits defined by RdMask and WrMask, then
* make sure the read-only bits are not changed and the
* read/write bits are all ones.
*/
tw32(offset, read_mask | write_mask);
val = tr32(offset);
/* Test the read-only bits. */
if ((val & read_mask) != read_val)
goto out;
/* Test the read/write bits. */
if ((val & write_mask) != write_mask)
goto out;
tw32(offset, save_val);
}
return 0;
out:
if (netif_msg_hw(tp))
netdev_err(tp->dev,
"Register test failed at offset %x\n", offset);
tw32(offset, save_val);
return -EIO;
}
| DoS Exec Code Overflow | 0 | static int tg3_test_registers(struct tg3 *tp)
{
int i, is_5705, is_5750;
u32 offset, read_mask, write_mask, val, save_val, read_val;
static struct {
u16 offset;
u16 flags;
#define TG3_FL_5705 0x1
#define TG3_FL_NOT_5705 0x2
#define TG3_FL_NOT_5788 0x4
#define TG3_FL_NOT_5750 0x8
u32 read_mask;
u32 write_mask;
} reg_tbl[] = {
/* MAC Control Registers */
{ MAC_MODE, TG3_FL_NOT_5705,
0x00000000, 0x00ef6f8c },
{ MAC_MODE, TG3_FL_5705,
0x00000000, 0x01ef6b8c },
{ MAC_STATUS, TG3_FL_NOT_5705,
0x03800107, 0x00000000 },
{ MAC_STATUS, TG3_FL_5705,
0x03800100, 0x00000000 },
{ MAC_ADDR_0_HIGH, 0x0000,
0x00000000, 0x0000ffff },
{ MAC_ADDR_0_LOW, 0x0000,
0x00000000, 0xffffffff },
{ MAC_RX_MTU_SIZE, 0x0000,
0x00000000, 0x0000ffff },
{ MAC_TX_MODE, 0x0000,
0x00000000, 0x00000070 },
{ MAC_TX_LENGTHS, 0x0000,
0x00000000, 0x00003fff },
{ MAC_RX_MODE, TG3_FL_NOT_5705,
0x00000000, 0x000007fc },
{ MAC_RX_MODE, TG3_FL_5705,
0x00000000, 0x000007dc },
{ MAC_HASH_REG_0, 0x0000,
0x00000000, 0xffffffff },
{ MAC_HASH_REG_1, 0x0000,
0x00000000, 0xffffffff },
{ MAC_HASH_REG_2, 0x0000,
0x00000000, 0xffffffff },
{ MAC_HASH_REG_3, 0x0000,
0x00000000, 0xffffffff },
/* Receive Data and Receive BD Initiator Control Registers. */
{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
0x00000000, 0x00000003 },
{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVDBDI_STD_BD+0, 0x0000,
0x00000000, 0xffffffff },
{ RCVDBDI_STD_BD+4, 0x0000,
0x00000000, 0xffffffff },
{ RCVDBDI_STD_BD+8, 0x0000,
0x00000000, 0xffff0002 },
{ RCVDBDI_STD_BD+0xc, 0x0000,
0x00000000, 0xffffffff },
/* Receive BD Initiator Control Registers. */
{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ RCVBDI_STD_THRESH, TG3_FL_5705,
0x00000000, 0x000003ff },
{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
/* Host Coalescing Control Registers. */
{ HOSTCC_MODE, TG3_FL_NOT_5705,
0x00000000, 0x00000004 },
{ HOSTCC_MODE, TG3_FL_5705,
0x00000000, 0x000000f6 },
{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXCOL_TICKS, TG3_FL_5705,
0x00000000, 0x000003ff },
{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXCOL_TICKS, TG3_FL_5705,
0x00000000, 0x000003ff },
{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
0x00000000, 0x000000ff },
{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
0x00000000, 0xffffffff },
{ HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
0x00000000, 0xffffffff },
{ HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
0x00000000, 0xffffffff },
{ HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
0xffffffff, 0x00000000 },
{ HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
0xffffffff, 0x00000000 },
/* Buffer Manager Control Registers. */
{ BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
0x00000000, 0x007fff80 },
{ BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
0x00000000, 0x007fffff },
{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
0x00000000, 0x0000003f },
{ BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
0x00000000, 0x000001ff },
{ BUFMGR_MB_HIGH_WATER, 0x0000,
0x00000000, 0x000001ff },
{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
0xffffffff, 0x00000000 },
{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
0xffffffff, 0x00000000 },
/* Mailbox Registers */
{ GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
0x00000000, 0x000001ff },
{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
0x00000000, 0x000001ff },
{ GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
0x00000000, 0x000007ff },
{ GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
0x00000000, 0x000001ff },
{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
};
is_5705 = is_5750 = 0;
if (tg3_flag(tp, 5705_PLUS)) {
is_5705 = 1;
if (tg3_flag(tp, 5750_PLUS))
is_5750 = 1;
}
for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
continue;
if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
continue;
if (tg3_flag(tp, IS_5788) &&
(reg_tbl[i].flags & TG3_FL_NOT_5788))
continue;
if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
continue;
offset = (u32) reg_tbl[i].offset;
read_mask = reg_tbl[i].read_mask;
write_mask = reg_tbl[i].write_mask;
/* Save the original register content */
save_val = tr32(offset);
/* Determine the read-only value. */
read_val = save_val & read_mask;
/* Write zero to the register, then make sure the read-only bits
* are not changed and the read/write bits are all zeros.
*/
tw32(offset, 0);
val = tr32(offset);
/* Test the read-only and read/write bits. */
if (((val & read_mask) != read_val) || (val & write_mask))
goto out;
/* Write ones to all the bits defined by RdMask and WrMask, then
* make sure the read-only bits are not changed and the
* read/write bits are all ones.
*/
tw32(offset, read_mask | write_mask);
val = tr32(offset);
/* Test the read-only bits. */
if ((val & read_mask) != read_val)
goto out;
/* Test the read/write bits. */
if ((val & write_mask) != write_mask)
goto out;
tw32(offset, save_val);
}
return 0;
out:
if (netif_msg_hw(tp))
netdev_err(tp->dev,
"Register test failed at offset %x\n", offset);
tw32(offset, save_val);
return -EIO;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,291 | static void tg3_timer_init(struct tg3 *tp)
{
if (tg3_flag(tp, TAGGED_STATUS) &&
tg3_asic_rev(tp) != ASIC_REV_5717 &&
!tg3_flag(tp, 57765_CLASS))
tp->timer_offset = HZ;
else
tp->timer_offset = HZ / 10;
BUG_ON(tp->timer_offset > HZ);
tp->timer_multiplier = (HZ / tp->timer_offset);
tp->asf_multiplier = (HZ / tp->timer_offset) *
TG3_FW_UPDATE_FREQ_SEC;
init_timer(&tp->timer);
tp->timer.data = (unsigned long) tp;
tp->timer.function = tg3_timer;
}
| DoS Exec Code Overflow | 0 | static void tg3_timer_init(struct tg3 *tp)
{
if (tg3_flag(tp, TAGGED_STATUS) &&
tg3_asic_rev(tp) != ASIC_REV_5717 &&
!tg3_flag(tp, 57765_CLASS))
tp->timer_offset = HZ;
else
tp->timer_offset = HZ / 10;
BUG_ON(tp->timer_offset > HZ);
tp->timer_multiplier = (HZ / tp->timer_offset);
tp->asf_multiplier = (HZ / tp->timer_offset) *
TG3_FW_UPDATE_FREQ_SEC;
init_timer(&tp->timer);
tp->timer.data = (unsigned long) tp;
tp->timer.function = tg3_timer;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,292 | static void tg3_timer_start(struct tg3 *tp)
{
tp->asf_counter = tp->asf_multiplier;
tp->timer_counter = tp->timer_multiplier;
tp->timer.expires = jiffies + tp->timer_offset;
add_timer(&tp->timer);
}
| DoS Exec Code Overflow | 0 | static void tg3_timer_start(struct tg3 *tp)
{
tp->asf_counter = tp->asf_multiplier;
tp->timer_counter = tp->timer_multiplier;
tp->timer.expires = jiffies + tp->timer_offset;
add_timer(&tp->timer);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,293 | static void tg3_timer_stop(struct tg3 *tp)
{
del_timer_sync(&tp->timer);
}
| DoS Exec Code Overflow | 0 | static void tg3_timer_stop(struct tg3 *tp)
{
del_timer_sync(&tp->timer);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,294 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
{
struct sk_buff *segs, *nskb;
u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
/* Estimate the number of fragments in the worst case */
if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
netif_stop_queue(tp->dev);
/* netif_tx_stop_queue() must be done before checking
* checking tx index in tg3_tx_avail() below, because in
* tg3_tx(), we update tx index before checking for
* netif_tx_queue_stopped().
*/
smp_mb();
if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
return NETDEV_TX_BUSY;
netif_wake_queue(tp->dev);
}
segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
if (IS_ERR(segs))
goto tg3_tso_bug_end;
do {
nskb = segs;
segs = segs->next;
nskb->next = NULL;
tg3_start_xmit(nskb, tp->dev);
} while (segs);
tg3_tso_bug_end:
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
| DoS Exec Code Overflow | 0 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
{
struct sk_buff *segs, *nskb;
u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
/* Estimate the number of fragments in the worst case */
if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
netif_stop_queue(tp->dev);
/* netif_tx_stop_queue() must be done before checking
* checking tx index in tg3_tx_avail() below, because in
* tg3_tx(), we update tx index before checking for
* netif_tx_queue_stopped().
*/
smp_mb();
if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
return NETDEV_TX_BUSY;
netif_wake_queue(tp->dev);
}
segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
if (IS_ERR(segs))
goto tg3_tso_bug_end;
do {
nskb = segs;
segs = segs->next;
nskb->next = NULL;
tg3_start_xmit(nskb, tp->dev);
} while (segs);
tg3_tso_bug_end:
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,295 | static void tg3_tx(struct tg3_napi *tnapi)
{
struct tg3 *tp = tnapi->tp;
u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
u32 sw_idx = tnapi->tx_cons;
struct netdev_queue *txq;
int index = tnapi - tp->napi;
unsigned int pkts_compl = 0, bytes_compl = 0;
if (tg3_flag(tp, ENABLE_TSS))
index--;
txq = netdev_get_tx_queue(tp->dev, index);
while (sw_idx != hw_idx) {
struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
struct sk_buff *skb = ri->skb;
int i, tx_bug = 0;
if (unlikely(skb == NULL)) {
tg3_tx_recover(tp);
return;
}
if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
struct skb_shared_hwtstamps timestamp;
u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
skb_tstamp_tx(skb, ×tamp);
}
pci_unmap_single(tp->pdev,
dma_unmap_addr(ri, mapping),
skb_headlen(skb),
PCI_DMA_TODEVICE);
ri->skb = NULL;
while (ri->fragmented) {
ri->fragmented = false;
sw_idx = NEXT_TX(sw_idx);
ri = &tnapi->tx_buffers[sw_idx];
}
sw_idx = NEXT_TX(sw_idx);
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
ri = &tnapi->tx_buffers[sw_idx];
if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
tx_bug = 1;
pci_unmap_page(tp->pdev,
dma_unmap_addr(ri, mapping),
skb_frag_size(&skb_shinfo(skb)->frags[i]),
PCI_DMA_TODEVICE);
while (ri->fragmented) {
ri->fragmented = false;
sw_idx = NEXT_TX(sw_idx);
ri = &tnapi->tx_buffers[sw_idx];
}
sw_idx = NEXT_TX(sw_idx);
}
pkts_compl++;
bytes_compl += skb->len;
dev_kfree_skb(skb);
if (unlikely(tx_bug)) {
tg3_tx_recover(tp);
return;
}
}
netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
tnapi->tx_cons = sw_idx;
/* Need to make the tx_cons update visible to tg3_start_xmit()
* before checking for netif_queue_stopped(). Without the
* memory barrier, there is a small possibility that tg3_start_xmit()
* will miss it and cause the queue to be stopped forever.
*/
smp_mb();
if (unlikely(netif_tx_queue_stopped(txq) &&
(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
__netif_tx_lock(txq, smp_processor_id());
if (netif_tx_queue_stopped(txq) &&
(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
netif_tx_wake_queue(txq);
__netif_tx_unlock(txq);
}
}
| DoS Exec Code Overflow | 0 | static void tg3_tx(struct tg3_napi *tnapi)
{
struct tg3 *tp = tnapi->tp;
u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
u32 sw_idx = tnapi->tx_cons;
struct netdev_queue *txq;
int index = tnapi - tp->napi;
unsigned int pkts_compl = 0, bytes_compl = 0;
if (tg3_flag(tp, ENABLE_TSS))
index--;
txq = netdev_get_tx_queue(tp->dev, index);
while (sw_idx != hw_idx) {
struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
struct sk_buff *skb = ri->skb;
int i, tx_bug = 0;
if (unlikely(skb == NULL)) {
tg3_tx_recover(tp);
return;
}
if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
struct skb_shared_hwtstamps timestamp;
u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
skb_tstamp_tx(skb, ×tamp);
}
pci_unmap_single(tp->pdev,
dma_unmap_addr(ri, mapping),
skb_headlen(skb),
PCI_DMA_TODEVICE);
ri->skb = NULL;
while (ri->fragmented) {
ri->fragmented = false;
sw_idx = NEXT_TX(sw_idx);
ri = &tnapi->tx_buffers[sw_idx];
}
sw_idx = NEXT_TX(sw_idx);
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
ri = &tnapi->tx_buffers[sw_idx];
if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
tx_bug = 1;
pci_unmap_page(tp->pdev,
dma_unmap_addr(ri, mapping),
skb_frag_size(&skb_shinfo(skb)->frags[i]),
PCI_DMA_TODEVICE);
while (ri->fragmented) {
ri->fragmented = false;
sw_idx = NEXT_TX(sw_idx);
ri = &tnapi->tx_buffers[sw_idx];
}
sw_idx = NEXT_TX(sw_idx);
}
pkts_compl++;
bytes_compl += skb->len;
dev_kfree_skb(skb);
if (unlikely(tx_bug)) {
tg3_tx_recover(tp);
return;
}
}
netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
tnapi->tx_cons = sw_idx;
/* Need to make the tx_cons update visible to tg3_start_xmit()
* before checking for netif_queue_stopped(). Without the
* memory barrier, there is a small possibility that tg3_start_xmit()
* will miss it and cause the queue to be stopped forever.
*/
smp_mb();
if (unlikely(netif_tx_queue_stopped(txq) &&
(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
__netif_tx_lock(txq, smp_processor_id());
if (netif_tx_queue_stopped(txq) &&
(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
netif_tx_wake_queue(txq);
__netif_tx_unlock(txq);
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,296 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
{
/* Tell compiler to fetch tx indices from memory. */
barrier();
return tnapi->tx_pending -
((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
}
| DoS Exec Code Overflow | 0 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
{
/* Tell compiler to fetch tx indices from memory. */
barrier();
return tnapi->tx_pending -
((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,297 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
dma_addr_t map, u32 len, u32 flags,
u32 mss, u32 vlan)
{
struct tg3 *tp = tnapi->tp;
bool hwbug = false;
if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
hwbug = true;
if (tg3_4g_overflow_test(map, len))
hwbug = true;
if (tg3_40bit_overflow_test(tp, map, len))
hwbug = true;
if (tp->dma_limit) {
u32 prvidx = *entry;
u32 tmp_flag = flags & ~TXD_FLAG_END;
while (len > tp->dma_limit && *budget) {
u32 frag_len = tp->dma_limit;
len -= tp->dma_limit;
/* Avoid the 8byte DMA problem */
if (len <= 8) {
len += tp->dma_limit / 2;
frag_len = tp->dma_limit / 2;
}
tnapi->tx_buffers[*entry].fragmented = true;
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
frag_len, tmp_flag, mss, vlan);
*budget -= 1;
prvidx = *entry;
*entry = NEXT_TX(*entry);
map += frag_len;
}
if (len) {
if (*budget) {
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
len, flags, mss, vlan);
*budget -= 1;
*entry = NEXT_TX(*entry);
} else {
hwbug = true;
tnapi->tx_buffers[prvidx].fragmented = false;
}
}
} else {
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
len, flags, mss, vlan);
*entry = NEXT_TX(*entry);
}
return hwbug;
}
| DoS Exec Code Overflow | 0 | static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
dma_addr_t map, u32 len, u32 flags,
u32 mss, u32 vlan)
{
struct tg3 *tp = tnapi->tp;
bool hwbug = false;
if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
hwbug = true;
if (tg3_4g_overflow_test(map, len))
hwbug = true;
if (tg3_40bit_overflow_test(tp, map, len))
hwbug = true;
if (tp->dma_limit) {
u32 prvidx = *entry;
u32 tmp_flag = flags & ~TXD_FLAG_END;
while (len > tp->dma_limit && *budget) {
u32 frag_len = tp->dma_limit;
len -= tp->dma_limit;
/* Avoid the 8byte DMA problem */
if (len <= 8) {
len += tp->dma_limit / 2;
frag_len = tp->dma_limit / 2;
}
tnapi->tx_buffers[*entry].fragmented = true;
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
frag_len, tmp_flag, mss, vlan);
*budget -= 1;
prvidx = *entry;
*entry = NEXT_TX(*entry);
map += frag_len;
}
if (len) {
if (*budget) {
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
len, flags, mss, vlan);
*budget -= 1;
*entry = NEXT_TX(*entry);
} else {
hwbug = true;
tnapi->tx_buffers[prvidx].fragmented = false;
}
}
} else {
tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
len, flags, mss, vlan);
*entry = NEXT_TX(*entry);
}
return hwbug;
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,298 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
dma_addr_t mapping, u32 len, u32 flags,
u32 mss, u32 vlan)
{
txbd->addr_hi = ((u64) mapping >> 32);
txbd->addr_lo = ((u64) mapping & 0xffffffff);
txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
}
| DoS Exec Code Overflow | 0 | static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
dma_addr_t mapping, u32 len, u32 flags,
u32 mss, u32 vlan)
{
txbd->addr_hi = ((u64) mapping >> 32);
txbd->addr_lo = ((u64) mapping & 0xffffffff);
txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
26,299 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
{
int i;
struct sk_buff *skb;
struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
skb = txb->skb;
txb->skb = NULL;
pci_unmap_single(tnapi->tp->pdev,
dma_unmap_addr(txb, mapping),
skb_headlen(skb),
PCI_DMA_TODEVICE);
while (txb->fragmented) {
txb->fragmented = false;
entry = NEXT_TX(entry);
txb = &tnapi->tx_buffers[entry];
}
for (i = 0; i <= last; i++) {
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
entry = NEXT_TX(entry);
txb = &tnapi->tx_buffers[entry];
pci_unmap_page(tnapi->tp->pdev,
dma_unmap_addr(txb, mapping),
skb_frag_size(frag), PCI_DMA_TODEVICE);
while (txb->fragmented) {
txb->fragmented = false;
entry = NEXT_TX(entry);
txb = &tnapi->tx_buffers[entry];
}
}
}
| DoS Exec Code Overflow | 0 | static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
{
int i;
struct sk_buff *skb;
struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
skb = txb->skb;
txb->skb = NULL;
pci_unmap_single(tnapi->tp->pdev,
dma_unmap_addr(txb, mapping),
skb_headlen(skb),
PCI_DMA_TODEVICE);
while (txb->fragmented) {
txb->fragmented = false;
entry = NEXT_TX(entry);
txb = &tnapi->tx_buffers[entry];
}
for (i = 0; i <= last; i++) {
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
entry = NEXT_TX(entry);
txb = &tnapi->tx_buffers[entry];
pci_unmap_page(tnapi->tp->pdev,
dma_unmap_addr(txb, mapping),
skb_frag_size(frag), PCI_DMA_TODEVICE);
while (txb->fragmented) {
txb->fragmented = false;
entry = NEXT_TX(entry);
txb = &tnapi->tx_buffers[entry];
}
}
}
| @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
if (j + len > block_end)
goto partno;
- memcpy(tp->fw_ver, &vpd_data[j], len);
- strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+ if (len >= sizeof(tp->fw_ver))
+ len = sizeof(tp->fw_ver) - 1;
+ memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+ snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+ &vpd_data[j]);
}
partno: | CWE-119 | null | null |
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