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SAI_First_Level :=
VCO_Input * UInt32 (RCC_Periph.PLLI2SCFGR.PLLI2SN) /
UInt32 (RCC_Periph.PLLI2SCFGR.PLLI2SQ);
-- SAI frequency is SAI First level / PLLI2SDIVQ
return SAI_First_Level / UInt32 (RCC_Periph.DKCFGR1.PLLI2SDIV + 1);
end if;
end Get_Input_Clock;
------------------
-- Enable_Clock --
------------------
procedure Enable_Clock (This : in out SDMMC_Controller)
is
begin
if This.Periph.all'Address /= SDMMC_Base then
raise Unknown_Device;
end if;
RCC_Periph.APB2ENR.SDMMC1EN := True;
end Enable_Clock;
-----------
-- Reset --
-----------
procedure Reset (This : in out SDMMC_Controller)
is
begin
if This.Periph.all'Address /= SDMMC_Base then
raise Unknown_Device;
end if;
RCC_Periph.APB2RSTR.SDMMC1RST := True;
RCC_Periph.APB2RSTR.SDMMC1RST := False;
end Reset;
----------------------
-- Set_Clock_Source --
----------------------
procedure Set_Clock_Source
(This : in out SDMMC_Controller;
Src : SDMMC_Clock_Source)
is
begin
if This.Periph.all'Address /= SDMMC_Base then
raise Unknown_Device;
end if;
RCC_Periph.DKCFGR2.SDMMCSEL := Src = Src_Sysclk;
case Src is
when Src_Sysclk =>
STM32.SDMMC.Set_Clk_Src_Speed
(This, System_Clock_Frequencies.SYSCLK);
when Src_48Mhz =>
STM32.SDMMC.Set_Clk_Src_Speed
(This, 48_000_000);
end case;
end Set_Clock_Source;
------------------------------
-- System_Clock_Frequencies --
------------------------------
function System_Clock_Frequencies return RCC_System_Clocks
is
Source : constant UInt2 := RCC_Periph.CFGR.SWS;
Result : RCC_System_Clocks;
begin
Result.I2SCLK := 0;
case Source is
when 0 =>
-- HSI as source
Result.SYSCLK := HSI_VALUE;
when 1 =>
-- HSE as source
Result.SYSCLK := HSE_VALUE;
when 2 =>
-- PLL as source
declare
HSE_Source : constant Boolean := RCC_Periph.PLLCFGR.PLLSRC;
Pllm : constant UInt32 :=
UInt32 (RCC_Periph.PLLCFGR.PLLM);
Plln : constant UInt32 :=
UInt32 (RCC_Periph.PLLCFGR.PLLN);
Pllp : constant UInt32 :=
(UInt32 (RCC_Periph.PLLCFGR.PLLP) + 1) * 2;
Pllvco : UInt32;
begin
if not HSE_Source then
Pllvco := HSI_VALUE;
else
Pllvco := HSE_VALUE;
end if;
Pllvco := Pllvco / Pllm;