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Phase_High := 16#18#;
when 14 =>
Phase_High := 16#30#;
when 16 =>
Phase_High := 16#40#;
when 18 =>
Phase_High := 16#50#;
when others =>
Status := False;
return;
end case;
Write (This, REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
Phase_High, Status);
if not Status then
return;
end if;
Write (This, REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
UInt8'(16#08#), Status);
if not Status then
return;
end if;
Write (This, REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
Encoded, Status);
if not Status then
return;
end if;
-- Update the timeouts
Timeout_Mclks := To_Timeout_Mclks (Pre_Timeout, Period);
Write (This, REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
UInt16 (Timeout_Mclks), Status);
Timeout_Mclks := To_Timeout_Mclks (Msrc_Timeout, Period);
if Timeout_Mclks > 256 then
Timeout_Mclks := 255;
else
Timeout_Mclks := Timeout_Mclks - 1;
end if;
Write (This, REG_MSRC_CONFIG_TIMEOUT_MACROP,
UInt8 (Timeout_Mclks), Status);
when Final_Range =>
Pre_Timeout := Sequence_Step_Timeout
(This, Pre_Range, As_Mclks => True);
Final_Timeout := Sequence_Step_Timeout (This, Final_Range);
declare
Phase_High : UInt8;
Width : UInt8;
Cal_Timeout : UInt8;
Cal_Lim : UInt8;
begin
case Period is
when 8 =>
Phase_High := 16#10#;
Width := 16#02#;
Cal_Timeout := 16#0C#;
Cal_Lim := 16#30#;
when 10 =>
Phase_High := 16#28#;
Width := 16#03#;
Cal_Timeout := 16#09#;
Cal_Lim := 16#20#;
when 12 =>
Phase_High := 16#38#;
Width := 16#03#;
Cal_Timeout := 16#08#;
Cal_Lim := 16#20#;
when 14 =>
Phase_High := 16#48#;
Width := 16#03#;
Cal_Timeout := 16#07#;
Cal_Lim := 16#20#;
when others =>
return;
end case;
Write (This, REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
Phase_High, Status);
if not Status then
return;
end if;
Write (This, REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
UInt8'(16#08#), Status);
if not Status then
return;
end if;
Write (This, REG_GLOBAL_CONFIG_VCSEL_WIDTH,
Width, Status);
if not Status then
return;
end if;