module_content stringlengths 18 1.05M |
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module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red ... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(re... |
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = ... |
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = ... |
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = ... |
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
s... |
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
s... |
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes ... |
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes ... |
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes ... |
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes ... |
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; ou... |
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; ou... |
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; ou... |
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q =... |
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q =... |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
... |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VA... |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wir... |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
pa... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASS... |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG ... |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_... |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
... |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VA... |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wir... |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
pa... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASS... |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG ... |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_... |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
... |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VA... |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wir... |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
pa... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASS... |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG ... |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_... |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
... |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VA... |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wir... |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
pa... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASS... |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG ... |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_... |
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
... |
module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VA... |
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wir... |
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
pa... |
module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASS... |
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG ... |
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_... |
module dividerp1(input wire clk,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Co... |
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_inter... |
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_inter... |
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_inter... |
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges t... |
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges t... |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock... |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock... |
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock... |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output ... |
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output... |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
out... |
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
... |
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb... |
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
o... |
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
outpu... |
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
outpu... |
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
out... |
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
out... |
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
ou... |
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
ou... |
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output ... |
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output... |
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
out... |
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
... |
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb... |
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