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≻ y ∈ . (2.15)
(cid:26)H(M;x) q if M;x / H
n
≻ ∈
Nowsince boththe inputdataandthe programareencodedusing the same
alphabet, it is possible to write programs for the universal machine that takes
programsforotherTuringmachinesasinput. Considerthereforeanewmachine
D whichisa modificationofthe machineH andwhichtakesthe descriptionM
as input. It is defined by
D(M) ⊲ if H(M;M) q
D(M): ≻ ≻ y (2.16)
(cid:26)D(M) q if H(M;M) q
y n
≻ ≻
Under the assumption that H exists, this is a perfectly well defined compu-
tation. D can be explicitly defined by just adding a small set of instructions to
H(M;x) directing it to move right forever in the case that H(M;M) accepts
(which it does eventually by assumption), or directing it to accept if H(M;M)
accepts (which it also does eventually by assumption).
Let us spell out the definition of D explicitly. On given input M, D first
simulates the universalmachine H oninput M;M. Then, in the case where M
should have entered the accepting configuration q , D, which is reprogrammed
y
(as compared to H) to ’loop’, just continues to move forever right along the
tape. In the case where M should have entered the rejecting configuration q ,
n
D is reprogrammedto accept.
ButnowwecanaskhowDbehaveswhenitisrunwithadescriptionofitself
asinput,i.e. howdoesD(D)behave? ThedefinitionofD(D)immediatelygives
D(D) ⊲ if H(D;D) q
D(D): ≻ ≻ y . (2.17)
(cid:26)D(D) q if H(D;D) q
y n
≻ ≻
Let us analyze this. Does D(D) halt or not?
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Suppose it does not halt, i.e. D(D) ⊲. That case occurs when H accepts
≻
the input D;D. But then it follows from the assumption (2.15) about H that
D;D H. This, in its turn implies D(D) ⊲ using the definition (2.13) of the
∈ 6≻
language H.
On the other hand, suppose D(D) does halt. That case occurs when H
doesnotacceptthe input D;D. Butthen itfollowsfromthe assumption(2.15)
about H that D;D / H. Consequently, D(D) does not halt according to the
∈
definition (2.13) of the language H.
Both ways, we get a contradiction. The conclusion is that the universal
machine H deciding H does not exist.
Note, that this proof hinges on a delicate interplay between the definition
(2.13) of the halting language H, the assumed properties of the universal ma-
chine H purported to decide H and the derived properties of the ’diagonal’
reprogrammedmachine D.
2.4 The classical circuit model of computation
The circuit model of computation is based on the classical logical gates like
AND, OR and NOT. Since the 70’s these are implemented as physical devices
intheformofTTLorCMOStechnology. Inamicroprocessortherearemillions
ofgates,buttheyarealsopackagedincomponentscontainingafewgates,which
can be wired together on circuit boards using traditional soldering techniques.
The abstract logical values true,false are represented by voltage levels. In
{ }
this section we will review the circuit model as a theoretical model of compu-
tation, but everything in this model have a physical realizationin terms of real
world circuits and wires.
Acircuitismadeupofwiresandgates. Theinputsandoutputsofthegates
are bits, either represented by true,false or more conveniently by 0,1 . A
{ } { }
single gate might have any number of inputs and outputs, though in practice
the basic building blocks have just a few inputs and outputs.
A circuit with k inputs and l outputs corresponds to a function
f : 0,1 k 0,1 l.
{ } →{ }
f
inputs outputs
Figure 2.1: A general gate.
Bitsarecarriedfromonegatetoanotherthroughwires. Byconnectinggates
with wires a circuit is built. No loops or feedback are allowed in the circuit as
that generally leads to instabilities. Wires can be split into two or more wires,
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thus duplicating the bit they are carrying.13 All circuits canbe built using just
one type of logical gate, often chosen to be the 2-input gate NAND. NAND is
an AND gate followed by a NOT gate. The NAND gate is therefore said to be
universal for classical(non-reversible)computation. Circuits are often easierto
constructandunderstandifoneallowsoneselftousealargersetofgates: NOT,
AND, OR, NAND, XOR.
The basic circuit elements
x x x NOT x
"wire"
x x
x AND y x OR y
y y
x x
x XOR y x NAND y
y y
Figure 2.2: The basic circuit elements.
Input/output relations for the basic circuit elements
The outputs of these gates for different combinationsof inputs are givenby the
following table.
x y x AND y x OR y x XOR y x NAND y
0 0 0 0 0 1