xszheng2020/the_stack_dedup_python_hits_6 · Datasets at Hugging Face

7415e5c654a65332be95606d5f2dd9d37a5ad76a

153

py

Python

mrtopo/structures/networks/ring/ring.py

FaizChishtie/MrTopo

e6a674738d8b0a0c56edde2be0ae272ea9e62f1a

[ "MIT" ]

1

2021-01-26T11:01:32.000Z

mrtopo/structures/networks/ring/ring.py

FaizChishtie/MrTopo

e6a674738d8b0a0c56edde2be0ae272ea9e62f1a

[ "MIT" ]

null

mrtopo/structures/networks/ring/ring.py

FaizChishtie/MrTopo

e6a674738d8b0a0c56edde2be0ae272ea9e62f1a

[ "MIT" ]

1

2020-12-23T22:01:09.000Z

""" MrTopo Network - data structure repr Ring Topo """ from mininet.topo import Topo class RingTopo(Topo): def build(self): pass # TODO

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6

741f1a56d78060b5c2c3016e5f4813e2833b5c69

49

py

Python

wikidictparser/__init__.py

ls2716/wikidictparser_package

a1c6375bb84f2238aad09d46a753b2bde9490d85

[ "BSD-2-Clause" ]

null

wikidictparser/__init__.py

ls2716/wikidictparser_package

a1c6375bb84f2238aad09d46a753b2bde9490d85

[ "BSD-2-Clause" ]

2

2020-07-29T07:31:21.000Z

2021-03-31T19:48:02.000Z

wikidictparser/__init__.py

ls2716/wikidictparser_package

a1c6375bb84f2238aad09d46a753b2bde9490d85

[ "BSD-2-Clause" ]

null

from .router import get_parser, set_logging_level

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6

742f62c228db29ee09187d4fa834d870a7dd3cf0

193

py

Python

server/users/admin.py

FranciscoJavierMartin/iCard

13193a26aec4fc57351be522ebd68018cb79f927

[ "MIT" ]

null

server/users/admin.py

FranciscoJavierMartin/iCard

13193a26aec4fc57351be522ebd68018cb79f927

[ "MIT" ]

null

server/users/admin.py

FranciscoJavierMartin/iCard

13193a26aec4fc57351be522ebd68018cb79f927

[ "MIT" ]

null

from django.contrib import admin from django.contrib.auth.admin import UserAdmin as BaseUserAdmin from users.models import User @admin.register(User) class UserAdmin(BaseUserAdmin): pass

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6

747dcc5ba7e00991d583d3b8c503f5042fab0fb3

10,121

py

Python

api/resources_portal/test/views/test_attachment.py

AlexsLemonade/resources-portal

d91c6c8d6135461faccbc78ef2b0be3f9b358f21

[ "BSD-3-Clause" ]

null

api/resources_portal/test/views/test_attachment.py

AlexsLemonade/resources-portal

d91c6c8d6135461faccbc78ef2b0be3f9b358f21

[ "BSD-3-Clause" ]

536

2019-11-13T15:49:03.000Z

2022-03-28T20:17:24.000Z

api/resources_portal/test/views/test_attachment.py

AlexsLemonade/resources-portal

d91c6c8d6135461faccbc78ef2b0be3f9b358f21

[ "BSD-3-Clause" ]

1

2020-04-03T02:07:29.000Z

import os import shutil from django.forms.models import model_to_dict from django.urls import reverse from rest_framework import status from rest_framework.test import APITestCase from faker import Faker from resources_portal.models import Attachment from resources_portal.test.factories import AttachmentFactory, UserFactory from resources_portal.test.utils import clean_test_file_uploads fake = Faker() class TestAttachmentListTestCase(APITestCase): """ Tests /attachment list operations. """ def setUp(self): self.url = reverse("attachment-list") self.attachment = AttachmentFactory() self.attachment_data = model_to_dict(self.attachment) self.attachment_data.pop("id") self.user = UserFactory() self.admin = UserFactory() self.admin.is_staff = True clean_test_file_uploads() def test_list_request_from_admin_succeeds(self): self.client.force_authenticate(user=self.admin) response = self.client.get(self.url) self.assertEqual(response.status_code, status.HTTP_200_OK) def test_list_request_from_non_admin_fails(self): self.client.force_authenticate(user=self.user) response = self.client.get(self.url) self.assertEqual(response.status_code, status.HTTP_403_FORBIDDEN) def test_post_request_from_authenticated_succeeds(self): self.client.force_authenticate(user=self.user) with open("dev_data/nerd_sniping.png", "rb") as fp: data = {**self.attachment_data, "file": fp} data.pop("sequence_map_for") response = self.client.post(self.url, data, format="multipart") self.assertEqual(response.status_code, status.HTTP_201_CREATED) response = self.client.get(response.json()["download_url"]) self.assertEqual(response.status_code, status.HTTP_200_OK) self.assertEqual(len(response.content), 157844) def test_post_request_without_org_succeeds(self): self.client.force_authenticate(user=self.user) with open("dev_data/nerd_sniping.png", "rb") as fp: attachment_data = {"file": fp, "owned_by_user": self.user.id} response = self.client.post(self.url, attachment_data, format="multipart") self.assertEqual(response.status_code, status.HTTP_201_CREATED) def test_post_request_from_unauthenticated_user_fails(self): self.client.force_authenticate(user=None) with open("dev_data/nerd_sniping.png", "rb") as fp: data = {**self.attachment_data, "file": fp} data.pop("sequence_map_for") response = self.client.post(self.url, data, format="multipart") self.assertEqual(response.status_code, status.HTTP_401_UNAUTHORIZED) class TestSingleAttachmentTestCase(APITestCase): """ Tests /attachment detail operations. """ def setUp(self): self.attachment = AttachmentFactory() self.attachment_json = model_to_dict(self.attachment) self.attachment_json.pop("sequence_map_for") self.attachment_json.pop("owned_by_org") self.url = reverse("attachment-detail", args=[self.attachment.id]) self.organization = self.attachment.owned_by_org self.user = self.attachment.owned_by_user self.user_in_org = UserFactory() self.organization.members.add(self.user_in_org) self.organization.save() self.non_owner = UserFactory() self.admin = UserFactory() self.admin.is_staff = True self.admin.save() def test_get_request_from_owning_user_succeeds(self): self.client.force_authenticate(user=self.user) response = self.client.get(self.url) self.assertEqual(response.status_code, status.HTTP_200_OK) def test_get_request_from_member_of_owning_org_succeeds(self): self.client.force_authenticate(user=self.user_in_org) response = self.client.get(self.url) self.assertEqual(response.status_code, status.HTTP_200_OK) def test_get_request_from_non_owner_fails(self): self.client.force_authenticate(user=self.non_owner) response = self.client.get(self.url) self.assertEqual(response.status_code, status.HTTP_403_FORBIDDEN) def test_get_request_from_unauthenticated_fails(self): self.client.force_authenticate(user=None) response = self.client.get(self.url) self.assertEqual(response.status_code, status.HTTP_401_UNAUTHORIZED) def test_put_request_from_owning_user_succeeds(self): self.client.force_authenticate(user=self.user) description = "A different description." self.attachment_json["description"] = description response = self.client.put(self.url, self.attachment_json, format="multipart") self.assertEqual(response.status_code, status.HTTP_200_OK) self.attachment.refresh_from_db() self.assertEqual(description, self.attachment.description) def test_put_request_from_member_of_owning_org_succeeds(self): self.client.force_authenticate(user=self.user_in_org) description = "A different description." self.attachment_json["description"] = description response = self.client.put(self.url, self.attachment_json, format="multipart") self.assertEqual(response.status_code, status.HTTP_200_OK) self.attachment.refresh_from_db() self.assertEqual(description, self.attachment.description) def test_patch_request_from_member_of_owning_org_succeeds(self): self.client.force_authenticate(user=self.user_in_org) description = "A different description." self.attachment_json = {"description": description} response = self.client.patch(self.url, self.attachment_json, format="multipart") self.assertEqual(response.status_code, status.HTTP_200_OK) self.attachment.refresh_from_db() self.assertEqual(description, self.attachment.description) def test_put_request_from_user_not_in_organization_fails(self): self.client.force_authenticate(user=self.non_owner) attachment_json = self.client.get(self.url).json() filename = "new_filename" attachment_json["filename"] = filename response = self.client.put(self.url, attachment_json) self.assertEqual(response.status_code, status.HTTP_403_FORBIDDEN) def test_put_request_from_unauthenticated_fails(self): self.client.force_authenticate(user=None) attachment_json = self.client.get(self.url).json() filename = "new_filename" attachment_json["filename"] = filename response = self.client.put(self.url, attachment_json) self.assertEqual(response.status_code, status.HTTP_401_UNAUTHORIZED) def test_delete_request_from_admin_succeeds(self): self.client.force_authenticate(user=self.admin) attachment_id = self.attachment.id response = self.client.delete(self.url) self.assertEqual(response.status_code, status.HTTP_204_NO_CONTENT) self.assertEqual(Attachment.objects.filter(id=attachment_id).count(), 0) def test_delete_request_from_owning_user_succeeds(self): self.client.force_authenticate(user=self.user) response = self.client.delete(self.url) self.assertEqual(response.status_code, status.HTTP_204_NO_CONTENT) def test_delete_request_from_member_of_owning_org_succeeds(self): self.client.force_authenticate(user=self.user_in_org) response = self.client.delete(self.url) self.assertEqual(response.status_code, status.HTTP_204_NO_CONTENT) def test_delete_request_from_unauthorized_fails(self): self.client.force_authenticate(user=self.non_owner) response = self.client.delete(self.url) self.assertEqual(response.status_code, status.HTTP_403_FORBIDDEN) def test_delete_request_from_unauthenticated_fails(self): self.client.force_authenticate(user=None) response = self.client.delete(self.url) self.assertEqual(response.status_code, status.HTTP_401_UNAUTHORIZED) class TestCopyAttachment(APITestCase): """ Tests /attachment-copy operation. """ def setUp(self): clean_test_file_uploads() self.attachment = AttachmentFactory() self.attachment_json = model_to_dict(self.attachment) self.attachment_json.pop("sequence_map_for") self.attachment_json.pop("owned_by_org") shutil.rmtree(self.attachment.local_file_dir, ignore_errors=True) os.mkdir(self.attachment.local_file_dir) shutil.copyfile("dev_data/nerd_sniping.png", self.attachment.local_file_path) self.url = reverse("attachment-copy", args=[self.attachment.id]) self.organization = self.attachment.owned_by_org self.user = self.attachment.owned_by_user self.user_in_org = UserFactory() self.organization.members.add(self.user_in_org) self.organization.save() self.user_not_in_org = UserFactory() self.admin = UserFactory() self.admin.is_staff = True self.admin.save() def test_post_request_from_owning_user_succeeds(self): self.client.force_authenticate(user=self.user) response = self.client.post(self.url) self.assertEqual(response.status_code, status.HTTP_201_CREATED) new_attachment = Attachment.objects.get(pk=response.json()["id"]) self.assertEqual( os.path.getsize(new_attachment.local_file_path), os.path.getsize(self.attachment.local_file_path), ) def test_post_request_from_org_member_succeeds(self): self.client.force_authenticate(user=self.user_in_org) response = self.client.post(self.url) self.assertEqual(response.status_code, status.HTTP_201_CREATED) def test_post_request_from_non_owner_fails(self): self.client.force_authenticate(user=self.user_not_in_org) response = self.client.post(self.url) self.assertEqual(response.status_code, status.HTTP_403_FORBIDDEN)

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6

77cdc1ab145b10d7e6d7eb445132fbd57740370c

22

py

Python

elliot/recommender/graph_based/ngcf/__init__.py

gategill/elliot

113763ba6d595976e14ead2e3d460d9705cd882e

[ "Apache-2.0" ]

175

2021-03-04T15:46:25.000Z

2022-03-31T05:56:58.000Z

elliot/recommender/graph_based/ngcf/__init__.py

gategill/elliot

113763ba6d595976e14ead2e3d460d9705cd882e

[ "Apache-2.0" ]

15

2021-03-06T17:53:56.000Z

2022-03-24T17:02:07.000Z

elliot/recommender/graph_based/ngcf/__init__.py

gategill/elliot

113763ba6d595976e14ead2e3d460d9705cd882e

[ "Apache-2.0" ]

39

2021-03-04T15:46:26.000Z

2022-03-09T15:37:12.000Z

from .NGCF import NGCF

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0.818182

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4.5

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0.947368

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77e4285448d1d709e7a33331b14315be11d6791b

21

py

Python

lib/python-gflags/__init__.py

MiCHiLU/google_appengine_sdk

3da9f20d7e65e26c4938d2c4054bc4f39cbc5522

[ "Apache-2.0" ]

790

2015-01-03T02:13:39.000Z

2020-05-10T19:53:57.000Z

lib/python-gflags/__init__.py

MiCHiLU/google_appengine_sdk

3da9f20d7e65e26c4938d2c4054bc4f39cbc5522

[ "Apache-2.0" ]

1,361

2015-01-08T23:09:40.000Z

2020-04-14T00:03:04.000Z

lib/python-gflags/__init__.py

MiCHiLU/google_appengine_sdk

3da9f20d7e65e26c4938d2c4054bc4f39cbc5522

[ "Apache-2.0" ]

155

2015-01-08T22:59:31.000Z

2020-04-08T08:01:53.000Z

from gflags import *

10.5

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5.333333

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0.190476

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1

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0.941176

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6

77f068ae759fb07aff4020cf616599837c967ca2

123

py

Python

adonai/app/models.py

Egnod/adonai

b365d81c826fd7b626c9145154ee0136ea73fac1

[ "MIT" ]

6

2020-01-20T20:02:09.000Z

2020-02-24T08:40:23.000Z

adonai/app/models.py

Egnod/adonai

b365d81c826fd7b626c9145154ee0136ea73fac1

[ "MIT" ]

null

adonai/app/models.py

Egnod/adonai

b365d81c826fd7b626c9145154ee0136ea73fac1

[ "MIT" ]

null

from ..domain.models import * from ..permission.models import * from ..project.models import * from ..user.models import *

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123

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true

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null

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1

0

6

bb204f7b4d824eb681cd245206810d9706108932

29

py

Python

neurolab/optimization/sched/__init__.py

udday2014/HebbianLearning

e0d17e53e3db8ce54b8fdd901702d2d6e0633732

[ "MIT" ]

6

2020-01-08T05:36:09.000Z

2022-02-09T21:07:04.000Z

neurolab/optimization/sched/__init__.py

GabrieleLagani/HebbianPCA

2736bb3017fa30ad2c160c891d42361bc5894df5

[ "MIT" ]

null

neurolab/optimization/sched/__init__.py

GabrieleLagani/HebbianPCA

2736bb3017fa30ad2c160c891d42361bc5894df5

[ "MIT" ]

2

2022-03-04T08:28:44.000Z

2022-03-16T19:00:34.000Z

from .multistepsched import *

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bb373f7b11fded204a7f45c3455c7b54b88f1839

110

py

Python

example/task/__init__.py

crystina-z/profane

b467b0d45d37de856e02eb0afad9ff012d215a42

[ "Apache-2.0" ]

9

2020-06-05T15:12:01.000Z

2021-05-28T12:19:02.000Z

example/task/__init__.py

crystina-z/profane

b467b0d45d37de856e02eb0afad9ff012d215a42

[ "Apache-2.0" ]

7

2020-06-11T08:22:00.000Z

2022-01-28T09:32:20.000Z

example/task/__init__.py

crystina-z/profane

b467b0d45d37de856e02eb0afad9ff012d215a42

[ "Apache-2.0" ]

4

2020-06-10T23:12:16.000Z

2022-01-27T17:54:36.000Z

from profane import import_all_modules from task.base import Task import_all_modules(__file__, __package__)

18.333333

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bb3c9c9ad9c8f371d6758f487fa3863724d116e9

151

py

Python

ufdl-object-detection-app/src/ufdl/object_detection_app/models/__init__.py

waikato-ufdl/ufdl-backend

776fc906c61eba6c2f2e6324758e7b8a323e30d7

[ "Apache-2.0" ]

null

ufdl-object-detection-app/src/ufdl/object_detection_app/models/__init__.py

waikato-ufdl/ufdl-backend

776fc906c61eba6c2f2e6324758e7b8a323e30d7

[ "Apache-2.0" ]

85

2020-07-24T00:04:28.000Z

2022-02-10T10:35:15.000Z

ufdl-object-detection-app/src/ufdl/object_detection_app/models/__init__.py

waikato-ufdl/ufdl-backend

776fc906c61eba6c2f2e6324758e7b8a323e30d7

[ "Apache-2.0" ]

null

from ._Annotations import Annotations, AnnotationsQuerySet from ._ObjectDetectionDataset import ObjectDetectionDataset, ObjectDetectionDatasetQuerySet

50.333333

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bb495e03b6eb6d14afa26c71a0e2a517ba8bab26

145

py

Python

deep_utils/callbacks/torch/__init__.py

pooya-mohammadi/deep_utils

b589d8ab0a8d63f3d3b90c3bc0d4b1b648b8be37

[ "MIT" ]

36

2021-11-10T05:17:18.000Z

2022-03-27T18:25:10.000Z

deep_utils/callbacks/torch/__init__.py

pooya-mohammadi/deep_utils

b589d8ab0a8d63f3d3b90c3bc0d4b1b648b8be37

[ "MIT" ]

1

2021-12-03T07:07:18.000Z

2022-03-08T09:29:03.000Z

deep_utils/callbacks/torch/__init__.py

pooya-mohammadi/deep_utils

b589d8ab0a8d63f3d3b90c3bc0d4b1b648b8be37

[ "MIT" ]

4

2021-11-28T07:39:57.000Z

2022-03-30T05:46:10.000Z

from .torch_model_checkpoint import ModelCheckPointTorch from .torch_csv_logger import CSVLogger from .torch_tensorboard import TensorboardTorch

36.25

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145

7.352941

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145

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6

24890704544235d21f0b7c6fca71808a78126283

99

py

Python

10430.py

BACCHUS-S/Baekjoon

05edab8ea7c7205ca67ef8fe34bf0abd22726a0e

[ "MIT" ]

null

10430.py

BACCHUS-S/Baekjoon

05edab8ea7c7205ca67ef8fe34bf0abd22726a0e

[ "MIT" ]

null

10430.py

BACCHUS-S/Baekjoon

05edab8ea7c7205ca67ef8fe34bf0abd22726a0e

[ "MIT" ]

null

a,b,c=map(int,input().split()) print((a+b)%c) print((a%c+b%c)%c) print((a*b)%c) print((a%c*b%c)%c)

16.5

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0.555556

27

99

2.037037

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0.181818

0.163636

0.290909

0.654545

0

0.050505

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5

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true

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0

6

24a2301cc8e8f414aad472db39d81ed26c18ba2e

2,331

py

Python

tests/test_argparse.py

andreasgrv/mlconf

a1f2056cffb458ce3b845c5e4aab1a3a9e58a0c4

[ "BSD-3-Clause" ]

2

2019-08-29T12:59:28.000Z

2020-05-01T11:11:08.000Z

tests/test_argparse.py

andreasgrv/mlconf

a1f2056cffb458ce3b845c5e4aab1a3a9e58a0c4

[ "BSD-3-Clause" ]

null

tests/test_argparse.py

andreasgrv/mlconf

a1f2056cffb458ce3b845c5e4aab1a3a9e58a0c4

[ "BSD-3-Clause" ]

null

import mlconf import pytest def test_yaml_loader(): parser = mlconf.ArgumentParser() parser.add_argument('--value') parser.add_argument('--load_blueprint', action=mlconf.YAMLLoaderAction) bp = parser.parse_args(['--value', '5', '--load_blueprint', 'tests/data/example.yaml', '--foo.counter.b', '63']) assert(bp.value == '5') assert(bp.foo.counter.a == 5) assert(bp.foo.counter.b == 63) def test_yaml_loader_wrong_order(): parser = mlconf.ArgumentParser() parser.add_argument('--value') parser.add_argument('--load_blueprint', action=mlconf.YAMLLoaderAction) with pytest.raises(SystemExit): bp = parser.parse_args(['--load_blueprint', 'tests/data/example.yaml', '--value', '5']) def test_yaml_loader_override_default(): parser = mlconf.ArgumentParser() parser.add_argument('--value', default=29, type=int) parser.add_argument('--load_blueprint', action=mlconf.YAMLLoaderAction) bp = parser.parse_args(['--value', '8', '--load_blueprint', 'tests/data/example.yaml', '--foo.counter.b', '63']) assert(bp.value == 8) assert(bp.foo.counter.a == 5) assert(bp.foo.counter.b == 63) def test_yaml_loader_check_type(): parser = mlconf.ArgumentParser() parser.add_argument('--value', default=6) parser.add_argument('--load_blueprint', action=mlconf.YAMLLoaderAction) with pytest.raises(SystemExit): bp = parser.parse_args(['--load_blueprint', 'tests/data/example.yaml', '--foo.counter.b', 'a']) def test_yaml_loader_bools(): parser = mlconf.ArgumentParser() parser.add_argument('--value', default=6) parser.add_argument('--load_blueprint', action=mlconf.YAMLLoaderAction) bp = parser.parse_args(['--load_blueprint', 'tests/data/example.yaml', '--foo.boolstuff.a', 'false', '--foo.boolstuff.d', 'true']) assert(bp.foo.boolstuff.a == False) assert(bp.foo.boolstuff.b == True) assert(bp.foo.boolstuff.c == False) assert(bp.foo.boolstuff.d == True)

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0

6

24bd2e20c7bbad0be548b73aee51a4ec82030d0d

20

py

Python

xambda/s3_layer/__init__.py

xyla-io/lambda_io

a6e04a68a241880e573aa14f41dd19bfec37d73c

[ "MIT" ]

null

xambda/s3_layer/__init__.py

xyla-io/lambda_io

a6e04a68a241880e573aa14f41dd19bfec37d73c

[ "MIT" ]

null

xambda/s3_layer/__init__.py

xyla-io/lambda_io

a6e04a68a241880e573aa14f41dd19bfec37d73c

[ "MIT" ]

null

from .base import S3

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1

0

1

0

1

0

6

24ffde71409b719a80f121047beab73ccaf38677

1,609

py

Python

Code/tests/test_distances.py

robin-p-schmitt/conformance-checking

021e042bb026ef44f0d53d02f8cf8e1675066674

[ "MIT" ]

null

Code/tests/test_distances.py

robin-p-schmitt/conformance-checking

021e042bb026ef44f0d53d02f8cf8e1675066674

[ "MIT" ]

null

Code/tests/test_distances.py

robin-p-schmitt/conformance-checking

021e042bb026ef44f0d53d02f8cf8e1675066674

[ "MIT" ]

null

import pytest import numpy as np from conformance_checking.distances import calc_wmd, calc_ict, calc_euclidean, _calc_d def test_wmd(): """Is the wmd calculated correctly?""" model_embedding = [{0: 1, 1: 1}] real_embedding = [{1: 1}] context = np.array([[1, 4], [5, 1]]) # calculate Euclidean distance matrix distance_matrix = calc_euclidean(context) # calc d for embeddings vocab_len = len(context) d_model = _calc_d(model_embedding, vocab_len) d_real = _calc_d(real_embedding, vocab_len) assert calc_wmd(d_model[0], d_real[0], distance_matrix) == pytest.approx(2.5) def test_ict(): """Is the ict calculated correctly?""" model_embedding = [{0: 1, 1: 1}] real_embedding = [{1: 1}] context = np.array([[1, 4], [5, 1]]) # calculate Euclidean distance matrix distance_matrix = calc_euclidean(context) # calc d for embeddings vocab_len = len(context) d_model = _calc_d(model_embedding, vocab_len) d_real = _calc_d(real_embedding, vocab_len) assert calc_ict(d_model[0], d_real[0], distance_matrix) == pytest.approx(2.5) def test_ict2(): """Is the ict calculated correctly?""" model_embedding = [{0: 1}] real_embedding = [{1: 1}] context = np.array([[0, 4], [500, 4]]) # calculate Euclidean distance matrix distance_matrix = calc_euclidean(context) # calc d for embeddings vocab_len = len(context) d_model = _calc_d(model_embedding, vocab_len) d_real = _calc_d(real_embedding, vocab_len) assert calc_ict(d_model[0], d_real[0], distance_matrix) == pytest.approx(500)

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7029bec83423f275a443507bf4642cc66fa94866

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py

Python

plugins/figure-ref/__init__.py

mohnjahoney/website_source

edc86a869b90ae604f32e736d9d5ecd918088e6a

[ "MIT" ]

13

2020-01-27T09:02:25.000Z

2022-01-20T07:45:26.000Z

plugins/figure-ref/__init__.py

mohnjahoney/website_source

edc86a869b90ae604f32e736d9d5ecd918088e6a

[ "MIT" ]

29

2020-03-22T06:57:57.000Z

2022-01-24T22:46:42.000Z

plugins/figure-ref/__init__.py

mohnjahoney/website_source

edc86a869b90ae604f32e736d9d5ecd918088e6a

[ "MIT" ]

6

2020-07-10T00:13:30.000Z

2022-01-26T08:22:33.000Z

from .figure_ref import *

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6

708849058298473d2416788c38f8945810b63470

14,345

py

Python

leaqi/main.py

xkianteb/leaqi

924435590e74421ed16488429056f26747c99421

[ "MIT" ]

12

2020-05-25T16:50:05.000Z

2022-02-20T08:00:04.000Z

leaqi/main.py

chenyangh/leaqi

924435590e74421ed16488429056f26747c99421

[ "MIT" ]

null

leaqi/main.py

chenyangh/leaqi

924435590e74421ed16488429056f26747c99421

[ "MIT" ]

4

2020-05-28T18:25:01.000Z

2021-02-25T10:29:41.000Z

import pandas as pd from sklearn.metrics import accuracy_score from sklearn.metrics import confusion_matrix import gym from timeit import default_timer as timer from datetime import timedelta import torch import argparse import numpy as np import time from leaqi.src.util import TrainLog from leaqi.src.args import wso_args from leaqi.src.lts.leaqi import LEAQI from leaqi.src.lts.dagger import DAgger from leaqi.src.oracles import Reference, Annotator from leaqi.envs import gym_structured_prediction from leaqi.src.batch_evaluation import batch_evaluation use_cuda = torch.cuda.is_available() device = torch.device("cuda" if use_cuda else "cpu") def main(args, _print=False): env = None env = gym.make(args.env) if args.weak_feature: env.set_state(args=args) device = 'cuda' wrapper = None #TODO: Overwriting this method to meean reference ref = Reference(train=env.dataset.train_rlby, test=env.dataset.test_rlby,\ tag2idx=env.dataset.tag2idx, args=args) expert = Annotator(train=env.dataset.train_y, test=env.dataset.test_y,\ tag2idx=env.dataset.tag2idx, args=args) args.num_epochs = 100000000000 eval = 1000 trainlog = TrainLog(args=args, num_epoch=args.num_epochs) if args.alg == 'leaqi': agent = LEAQI(reference=ref, expert=expert, args=args, device=device,\ env=env, trainlog=trainlog) filename = f'{args.alg}' elif args.alg == 'dagger:strong': agent = DAgger(oracle_policy=expert, args=args, env=env,\ trainlog=trainlog, device=device) filename = f'{args.alg}_{args.query_strategy}' elif args.alg == 'dagger:weak': agent = DAgger(oracle_policy=ref, args=args, env=env,\ trainlog=trainlog, device=device) filename = f'{args.alg}_{args.query_strategy}' else: raise Exception("Unknown algoritm") num_steps = 0 num_fn = 0 data = [] try: nextupdatestart = timer() for traj in range(args.num_epochs): agent.reset(args.seed) state = env.reset() env.seed(args.seed) ep_reward = 0 trainstart = timer() allstart = timer() while True: num_steps +=1 action = agent(env, state) state, reward, done, info = env.step(action) ep_reward += reward if done: break agent.update() trainend = timer() if traj % eval == 0: [model_stats, diff_clf_stats] =\ batch_evaluation(agent, args, wrapper=wrapper, seed=args.seed, env= env) allend = timer() nextupdateend = timer() # Print Results stats = trainlog(traj, agent=agent, diff_clf=agent.diff_clf, loss=0) stats += f' traj: {traj}\n' stats += f' num_steps: {num_steps}\n' if args.alg == 'leaqi': stats += f' ****************\n' stats += f' Difference Classifier:\n' stats += f' Acuracy : {diff_clf_stats["acur"]}\n' stats += f' F1 macro : {diff_clf_stats["f1_macro"]}\n' stats += f' Miss rate: {diff_clf_stats["miss_rate"]}\n' stats += f' (tn, fp, fn, tp): {tuple(diff_clf_stats["con_mat"])}\n' stats += f' *****************\n' stats += f' Model Classifier:\n' stats += f' Acuracy : {model_stats["acur"]}\n' stats += f' F1 : {model_stats["f1"]}\n' stats += f' sklearnf1: {model_stats["sklearn_f1_macro"]}\n' stats += f' Train Reward: {ep_reward}\n' stats += f' Test Reward: {model_stats["avg_rtn"]}\n' stats += f' *****************\n' stats += f' Model Mistakes\n' stats += f' ref queries: {trainlog.weakoracle_counts}\n' stats += f' exp queries: {trainlog.strongoracle_counts}\n' stats += f' no queries: {trainlog.nocall_counts}\n' stats += f' ########################################\n' stats += f' queries: {agent.queries}\n' stats += f' unseen_mistakes : {agent.unseen_mistakes}\n' stats += f' model_mistakes: {agent.model_mistakes}\n' stats += f' seen mistakes: {agent.seen_mistakes}\n' stats += f' mistakes: {agent.mistakes}\n' stats += f' total: {agent.total_mistakes}\n' stats += f' Train/Update: {timedelta(seconds=trainend-trainstart)}\n' stats += f' Train/Update/Evaluate: {timedelta(seconds=allend-allstart)}\n' stats += f' Between Update: {timedelta(seconds=nextupdateend-nextupdatestart)}\n' stats += f'-----------------------------------' print(stats) # Log Results results ={'x': num_steps, 'train_accuracy':ep_reward,\ 'test_accuracy':reward,\ 'expert_queries':trainlog.strongoracle_counts,\ 'ref_queries': trainlog.weakoracle_counts,\ 'no_queries': trainlog.nocall_counts,\ 'diff_clf_acur': diff_clf_stats["acur"],\ 'tn': diff_clf_stats["con_mat"][0], 'fp': diff_clf_stats["con_mat"][1],\ 'fn': diff_clf_stats["con_mat"][2], 'tp': diff_clf_stats["con_mat"][3],\ 'diff_clf_f1':diff_clf_stats['f1_macro']} for idx in range(len(agent.random_queries)): results[f'mistake_{env.idx2tag[idx]}_agent_random_queries']= agent.random_queries[idx] results[f'mistake_{env.idx2tag[idx]}_agent_seen_mistakes']= agent.seen_mistakes[idx] results[f'mistake_{env.idx2tag[idx]}_agent_total_mistakes']= agent.total_mistakes[idx] results[f'mistake_{env.idx2tag[idx]}_agent_unseen_mistakes']=agent.unseen_mistakes[idx] results[f'mistake_{env.idx2tag[idx]}_agent_other_mistakes']= agent.other_mistakes[idx] results[f'mistake_{env.idx2tag[idx]}_queries']= agent.queries[idx] for key in model_stats.keys(): results[f'model_{key}'] = model_stats[key] for key in diff_clf_stats.keys(): results[f'diff_{key}'] = diff_clf_stats[key] data.append(results) filename = args.filename if args.filename != 'tmp' else filename pd.DataFrame(data).to_csv(f'{filename}_results.csv') nextupdatestart = timer() else: allend = timer() stats = f' traj: {traj}\n' stats += f' num_steps: {num_steps}\n' stats += f' *****************\n' stats += f' Model Mistakes\n' stats += f' ref queries: {trainlog.weakoracle_counts}\n' stats += f' exp queries: {trainlog.strongoracle_counts}\n' stats += f' no queries: {trainlog.nocall_counts}\n' stats += f' ########################################\n' stats += f' queries: {agent.queries}\n' stats += f' unseen_mistakes : {agent.unseen_mistakes}\n' stats += f' model_mistakes: {agent.model_mistakes}\n' stats += f' seen mistakes: {agent.seen_mistakes}\n' stats += f' mistakes: {agent.mistakes}\n' stats += f' total: {agent.total_mistakes}\n' stats += f' Train/Update: {timedelta(seconds=trainend-trainstart)}\n' stats += f' Train/Update/Evaluate: {timedelta(seconds=allend-allstart)}\n' stats += f'-----------------------------------' print(stats) if 'stopiteration' in info: if info['stopiteration']: break except KeyboardInterrupt: import pdb; pdb.set_trace() if __name__ == '__main__': parser = argparse.ArgumentParser() wso_args(parser) args = parser.parse_args() print(args.filename) main(args) # trainlog = TrainLog(args=args, num_epoch=args.num_epochs) # # if args.alg == 'leaqi': # agent = LEAQI(reference=ref, expert=expert, args=args, device=device,\ # env=env, trainlog=trainlog) # filename = f'{args.alg}_{args.no_apple_tasting}' # elif args.alg == 'dagger:strong': # agent = DAgger(oracle_policy=expert, args=args, env=env,\ # trainlog=trainlog, device=device) # filename = f'{args.alg}_{args.query_strategy}' # elif args.alg == 'dagger:weak': # agent = DAgger(oracle_policy=ref, args=args, env=env,\ # trainlog=trainlog, device=device) # filename = f'{args.alg}_{args.query_strategy}' # else: # raise Exception("Unknown algoritm") # # num_steps = 0 # num_fn = 0 # data = [] # try: # nextupdatestart = timer() # for traj in range(args.num_epochs): # agent.reset(args.seed) # state = env.reset() # env.seed(args.seed) # ep_reward = 0 # # trainstart = timer() # allstart = timer() # while True: # num_steps +=1 # info = (num_fn, traj) # action = agent(env, state, info) # state, reward, done, info = env.step(action) # ep_reward += reward # if done: # break # agent.update() # trainend = timer() # # if traj % eval == 0: # [model_stats, diff_clf_stats] =\ # batch_evaluation(agent, args, wrapper=wrapper, seed=args.seed, env= env) # allend = timer() # nextupdateend = timer() # # # Print Results # stats = trainlog(traj, agent=agent, diff_clf=agent.diff_clf, loss=0) # stats += f' traj: {traj}\n' # stats += f' num_steps: {num_steps}\n' # stats += f' ****************\n' # stats += f' Difference Classifier:\n' # stats += f' Acuracy : {diff_clf_stats["acur"]}\n' # stats += f' F1 macro : {diff_clf_stats["f1_macro"]}\n' # stats += f' Miss rate: {diff_clf_stats["miss_rate"]}\n' # stats += f' (tn, fp, fn, tp): {tuple(diff_clf_stats["con_mat"])}\n' # stats += f' *****************\n' # stats += f' Model Classifier:\n' # stats += f' Acuracy : {model_stats["acur"]}\n' # stats += f' F1 : {model_stats["f1"]}\n' # stats += f' sklearnf1: {model_stats["sklearn_f1_macro"]}\n' # stats += f' Train Reward: {ep_reward}\n' # stats += f' Test Reward: {model_stats["avg_rtn"]}\n' # stats += f' Train/Update: {timedelta(seconds=trainend-trainstart)}\n' # stats += f' Train/Update/Evaluate: {timedelta(seconds=allend-allstart)}\n' # stats += f' Between Update: {timedelta(seconds=nextupdateend-nextupdatestart)}\n' # stats += f'-----------------------------------' # print(stats) # # # Log Results # results ={'x': num_steps, 'train_accuracy':ep_reward,\ # 'test_accuracy':reward,\ # 'expert_queries':trainlog.strongoracle_counts,\ # 'ref_queries': trainlog.weakoracle_counts,\ # 'no_queries': trainlog.nocall_counts,\ # 'agent_random_queries': agent.random_queries,\ # 'agent_seen_mistakes': agent.seen_mistakes,\ # 'agent_total_mistakes': agent.total_mistakes,\ # 'agent_unseen_mistakes': agent.unseen_mistakes,\ # 'agent_other_mistakes': agent.other_mistakes,\ # 'diff_clf_acur': diff_clf_stats["acur"],\ # 'diff_clf_f1': diff_clf_stats['f1_macro'],\ # 'tn': diff_clf_stats["con_mat"][0], 'fp': diff_clf_stats["con_mat"][1],\ # 'fn': diff_clf_stats["con_mat"][2], 'tp': diff_clf_stats["con_mat"][3]} # for key in model_stats.keys(): # results[f'model_{key}'] = model_stats[key] # # if args.alg == 'leaqi': # for key in diff_clf_stats.keys(): # results[f'diff_{key}'] = diff_clf_stats[key] # # data.append(results) # filename = args.filename if args.filename != 'tmp' else filename # pd.DataFrame(data).to_csv(f'{filename}_results.csv') # nextupdatestart = timer() # else: # allend = timer() # stats = f' traj: {traj}\n' # stats += f' num_steps: {num_steps}\n' # stats += f' unseen_mistakes : {agent.unseen_mistakes}\n' # stats += f' model_mistakes: {agent.model_mistakes}\n' # stats += f' seen mistakes: {agent.seen_mistakes}\n' # stats += f' mistakes: {agent.mistakes}\n' # stats += f' total: {agent.total_mistakes}\n' # stats += f' Train/Update: {timedelta(seconds=trainend-trainstart)}\n' # stats += f' Train/Update/Evaluate: {timedelta(seconds=allend-allstart)}\n' # stats += f'-----------------------------------' # print(stats) # # # if 'stopiteration' in info: # if info['stopiteration']: # break # except KeyboardInterrupt: # import pdb; pdb.set_trace() # #if __name__ == '__main__': # parser = argparse.ArgumentParser() # wso_args(parser) # args = parser.parse_args() # print(args.filename) # main(args) #

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py

Python

usaspending_api/reporting/migrations/0004_auto_20210202_2234.py

ststuck/usaspending-api

b13bd5bcba0369ff8512f61a34745626c3969391

[ "CC0-1.0" ]

217

2016-11-03T17:09:53.000Z

2022-03-10T04:17:54.000Z

usaspending_api/reporting/migrations/0004_auto_20210202_2234.py

ststuck/usaspending-api

b13bd5bcba0369ff8512f61a34745626c3969391

[ "CC0-1.0" ]

622

2016-09-02T19:18:23.000Z

2022-03-29T17:11:01.000Z

usaspending_api/reporting/migrations/0004_auto_20210202_2234.py

ststuck/usaspending-api

b13bd5bcba0369ff8512f61a34745626c3969391

[ "CC0-1.0" ]

93

2016-09-07T20:28:57.000Z

2022-02-25T00:25:27.000Z

# Generated by Django 2.2.9 on 2021-02-02 22:34 from django.db import migrations, models class Migration(migrations.Migration): dependencies = [ ('reporting', '0003_auto_20201204_1531'), ] operations = [ migrations.AddField( model_name='reportingagencyoverview', name='unlinked_procurement_c_awards', field=models.IntegerField(default=0), ), migrations.AddField( model_name='reportingagencyoverview', name='unlinked_assistance_c_awards', field=models.IntegerField(default=0), ), migrations.AddField( model_name='reportingagencyoverview', name='unlinked_procurement_d_awards', field=models.IntegerField(default=0), ), migrations.AddField( model_name='reportingagencyoverview', name='unlinked_assistance_d_awards', field=models.IntegerField(default=0), ), migrations.AddField( model_name='reportingagencyoverview', name='linked_procurement_awards', field=models.IntegerField(default=0), ), migrations.AddField( model_name='reportingagencyoverview', name='linked_assistance_awards', field=models.IntegerField(default=0), ), ]

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563e283aff1f5c5f2d6b52b068e34fa3fa492fd5

276

py

Python

python/robot-name/robot_name.py

Victor-Chinewubeze/algorithms-exercism

34669348762eef69b68a2f43260ab10ac1c4eb2a

[ "MIT" ]

1

2020-04-16T23:06:33.000Z

python/robot-name/robot_name.py

Victor-Chinewubeze/algorithms-exercism

34669348762eef69b68a2f43260ab10ac1c4eb2a

[ "MIT" ]

7

2021-05-08T11:46:15.000Z

2021-05-10T19:31:11.000Z

python/robot-name/robot_name.py

Victor-Chinewubeze/algorithms-exercism

34669348762eef69b68a2f43260ab10ac1c4eb2a

[ "MIT" ]

1

2020-01-09T16:33:39.000Z

import random def rnd(seed=""): return chr(random.randint(65,90)) + chr(random.randint(65,90)) + str(random.randint(100,999)) class Robot(object): def __init__(self): self.name = rnd() def reset(self): self.name = rnd(chr(random.randint(65,90)))

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6

3b1f13044204afaafd0e6efc5c0ef6766a68ea0e

155

py

Python

pyvault/db/__init__.py

MattCCS/PyVault

c0e87a1bf731e0c7c800a599b0b33885e484b92b

[ "MIT" ]

null

pyvault/db/__init__.py

MattCCS/PyVault

c0e87a1bf731e0c7c800a599b0b33885e484b92b

[ "MIT" ]

null

pyvault/db/__init__.py

MattCCS/PyVault

c0e87a1bf731e0c7c800a599b0b33885e484b92b

[ "MIT" ]

null

""" """ from pyvault.db.table import TABLE from pyvault.db.key_manager import KEYMAN from pyvault.db.pwm import PWM __all__ = ['PWM', 'KEYMAN', 'TABLE']

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6

3b73c8fdf191a3dbb3944d82aff9c0a66783b2da

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py

Python

voice_similarity/lib/LPC/__init__.py

itanium-R/rcc_winter_hackathon_2020

cecd43d8b89d2d656e3b11ca5bdfb35965451d37

[ "MIT" ]

null

voice_similarity/lib/LPC/__init__.py

itanium-R/rcc_winter_hackathon_2020

cecd43d8b89d2d656e3b11ca5bdfb35965451d37

[ "MIT" ]

null

voice_similarity/lib/LPC/__init__.py

itanium-R/rcc_winter_hackathon_2020

cecd43d8b89d2d656e3b11ca5bdfb35965451d37

[ "MIT" ]

null

from .lpc import *

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0

1

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6

3b8168149c9ce5d91cd1377644dfd606fe93e353

158

py

Python

sesion_02/movies/admin.py

bernest/modulo-django-desarrollo-web-cdmx-20-05pt

33f971f032f7d3902a49a993d46e3ecefb21d59b

[ "MIT" ]

null

sesion_02/movies/admin.py

bernest/modulo-django-desarrollo-web-cdmx-20-05pt

33f971f032f7d3902a49a993d46e3ecefb21d59b

[ "MIT" ]

null

sesion_02/movies/admin.py

bernest/modulo-django-desarrollo-web-cdmx-20-05pt

33f971f032f7d3902a49a993d46e3ecefb21d59b

[ "MIT" ]

null

"""Movies app admin site""" from django.contrib import admin from .models import Movie, Director admin.site.register(Movie) admin.site.register(Director)

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8e6efd4d43d8d1fc921e1fe662bb48d5e06d653b

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py

Python

model/dialogue/__init__.py

NickSchoelkopf/SummerTime

9a89aab8e1544e3c52c043b9c47ab325e665e11e

[ "Apache-2.0" ]

178

2021-07-07T23:46:20.000Z

2022-03-26T17:47:21.000Z

model/dialogue/__init__.py

NickSchoelkopf/SummerTime

9a89aab8e1544e3c52c043b9c47ab325e665e11e

[ "Apache-2.0" ]

77

2021-06-18T21:44:53.000Z

2022-02-20T00:23:06.000Z

model/dialogue/__init__.py

NickSchoelkopf/SummerTime

9a89aab8e1544e3c52c043b9c47ab325e665e11e

[ "Apache-2.0" ]

19

2021-06-18T22:24:47.000Z

2022-03-16T12:53:50.000Z

from .hmnet_model import HMNetModel from .flatten_dialogue_model import FlattenDialogueModel

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8eafc05f177ce84e7d2aaa4c1cfbcc53a0ccf29d

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py

Python

homeworks/kirill_shevchuk/hw05/test_lvl3.py

tgrx/Z22

b2539682ff26c8b6d9f63a7670c8a9c6b614a8ff

[ "Apache-2.0" ]

null

homeworks/kirill_shevchuk/hw05/test_lvl3.py

tgrx/Z22

b2539682ff26c8b6d9f63a7670c8a9c6b614a8ff

[ "Apache-2.0" ]

8

2019-11-15T18:15:56.000Z

2020-02-03T18:05:05.000Z

homeworks/kirill_shevchuk/hw05/test_lvl3.py

tgrx/Z22

b2539682ff26c8b6d9f63a7670c8a9c6b614a8ff

[ "Apache-2.0" ]

null

from homeworks.kirill_shevchuk.hw05.level03 import good_phone def test_good_phone(): assert good_phone("+375172294660") assert good_phone("+375296648778") assert not good_phone("") assert not good_phone("+37517229466") assert not good_phone("+37517229466a") assert not good_phone("+791562655123") assert not good_phone("+3751722946601") assert not good_phone("2020327") assert not good_phone(None)

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8ebfcb01a0a7976ed37f77b03e151e6820c5bfb1

5,574

py

Python

Python/pygame/dijkstra.py

flmnv/Training

6070b8ddfb6e01c0f433c813265bf50d59a26ef4

[ "Unlicense" ]

null

Python/pygame/dijkstra.py

flmnv/Training

6070b8ddfb6e01c0f433c813265bf50d59a26ef4

[ "Unlicense" ]

null

Python/pygame/dijkstra.py

flmnv/Training

6070b8ddfb6e01c0f433c813265bf50d59a26ef4

[ "Unlicense" ]

null

from random import randint from math import inf class Vertex: def __init__(self, num, sizeX, sizeY, value = inf): self.isChecked = False self.value = value self.num = num self.n = [] for i in range(sizeX): temp = [] for j in range(sizeY): temp.append(inf) self.n.append(temp) i = num // sizeY j = num % sizeY self.n[i][j] = 0 if i - 1 >= 0: self.n[i - 1][j] = 1.0 if i + 1 < sizeX: self.n[i + 1][j] = 1.0 if j - 1 >= 0: self.n[i][j - 1] = 1.0 if j + 1 < sizeY: self.n[i][j + 1] = 1.0 if i - 1 >= 0 and j - 1 >= 0: self.n[i - 1][j - 1] = 1.41421 if i - 1 >= 0 and j + 1 < sizeY: self.n[i - 1][j + 1] = 1.41421 if i + 1 < sizeX and j - 1 >= 0: self.n[i + 1][j - 1] = 1.41421 if i + 1 < sizeX and j + 1 < sizeY: self.n[i + 1][j + 1] = 1.41421 def chgValue(self, value): self.value = value def checked(self): self.isChecked = True def vertCalc(vert, num, sizeX, sizeY): global recCount i = num // sizeY j = num % sizeY if i - 1 >= 0: if vert[i][j].value + vert[i][j].n[i - 1][j] < vert[i - 1][j].value and vert[i - 1][j].isChecked == False: vert[i - 1][j].value = round(vert[i][j].value + vert[i][j].n[i - 1][j], 5) if i + 1 < sizeX: if vert[i][j].value + vert[i][j].n[i + 1][j] < vert[i + 1][j].value and vert[i + 1][j].isChecked == False: vert[i + 1][j].value = round(vert[i][j].value + vert[i][j].n[i + 1][j], 5) if j - 1 >= 0: if vert[i][j].value + vert[i][j].n[i][j - 1] < vert[i][j - 1].value and vert[i][j - 1].isChecked == False: vert[i][j - 1].value = round(vert[i][j].value + vert[i][j].n[i][j - 1], 5) if j + 1 < sizeY: if vert[i][j].value + vert[i][j].n[i][j + 1] < vert[i][j + 1].value and vert[i][j + 1].isChecked == False: vert[i][j + 1].value = round(vert[i][j].value + vert[i][j].n[i][j + 1], 5) if i - 1 >= 0 and j - 1 >= 0: if vert[i][j].value + vert[i][j].n[i - 1][j - 1] < vert[i - 1][j - 1].value and vert[i - 1][j - 1].isChecked == False: vert[i - 1][j - 1].value = round(vert[i][j].value + vert[i][j].n[i - 1][j - 1], 5) if i - 1 >= 0 and j + 1 < sizeY: if vert[i][j].value + vert[i][j].n[i - 1][j + 1] < vert[i - 1][j + 1].value and vert[i - 1][j + 1].isChecked == False: vert[i - 1][j + 1].value = round(vert[i][j].value + vert[i][j].n[i - 1][j + 1], 5) if i + 1 < sizeX and j - 1 >= 0: if vert[i][j].value + vert[i][j].n[i + 1][j - 1] < vert[i + 1][j - 1].value and vert[i + 1][j - 1].isChecked == False: vert[i + 1][j - 1].value = round(vert[i][j].value + vert[i][j].n[i + 1][j - 1], 5) if i + 1 < sizeX and j + 1 < sizeY: if vert[i][j].value + vert[i][j].n[i + 1][j + 1] < vert[i + 1][j + 1].value and vert[i + 1][j + 1].isChecked == False: vert[i + 1][j + 1].value = round(vert[i][j].value + vert[i][j].n[i + 1][j + 1], 5) vert[i][j].isChecked = True if i - 1 >= 0: if vert[i - 1][j].isChecked == False: vertCalc(vert, (i - 1) * sizeY + j, sizeX, sizeY) if i + 1 < sizeX: if vert[i + 1][j].isChecked == False: vertCalc(vert, (i + 1) * sizeY + j, sizeX, sizeY) if j - 1 >= 0: if vert[i][j - 1].isChecked == False: vertCalc(vert, i * sizeY + j - 1, sizeX, sizeY) if j + 1 < sizeY: if vert[i][j + 1].isChecked == False: vertCalc(vert, i * sizeY + j + 1, sizeX, sizeY) if i - 1 >= 0 and j - 1 >= 0: if vert[i - 1][j - 1].isChecked == False: vertCalc(vert, (i - 1) * sizeY + j - 1, sizeX, sizeY) if i - 1 >= 0 and j + 1 < sizeY: if vert[i - 1][j + 1].isChecked == False: vertCalc(vert, (i - 1) * sizeY + j + 1, sizeX, sizeY) if i + 1 < sizeX and j - 1 >= 0: if vert[i + 1][j - 1].isChecked == False: vertCalc(vert, (i + 1) * sizeY + j - 1, sizeX, sizeY) if i + 1 < sizeX and j + 1 < sizeY: if vert[i + 1][j + 1].isChecked == False: vertCalc(vert, (i + 1) * sizeY + j + 1, sizeX, sizeY) def vertPath(vert, start, end, sizeX, sizeY, path = []): same = [] i = end // sizeY j = end % sizeY path.insert(0, i * sizeY + j) if i * sizeY + j == start: vert.clear() return path if i - 1 >= 0: if round(vert[i][j].value - vert[i][j].n[i - 1][j], 5) == vert[i - 1][j].value: same.append((i - 1) * sizeY + j) if i + 1 < sizeX: if round(vert[i][j].value - vert[i][j].n[i + 1][j], 5) == vert[i + 1][j].value: same.append((i + 1) * sizeY + j) if j - 1 >= 0: if round(vert[i][j].value - vert[i][j].n[i][j - 1], 5) == vert[i][j - 1].value: same.append(i * sizeY + j - 1) if j + 1 < sizeY: if round(vert[i][j].value - vert[i][j].n[i][j + 1], 5) == vert[i][j + 1].value: same.append(i * sizeY + j + 1) if i - 1 >= 0 and j - 1 >= 0: if round(vert[i][j].value - vert[i][j].n[i - 1][j - 1], 5) == vert[i - 1][j - 1].value: same.append((i - 1) * sizeY + j - 1) if i - 1 >= 0 and j + 1 < sizeY: if round(vert[i][j].value - vert[i][j].n[i - 1][j + 1], 5) == vert[i - 1][j + 1].value: same.append((i - 1) * sizeY + j + 1) if i + 1 < sizeX and j - 1 >= 0: if round(vert[i][j].value - vert[i][j].n[i + 1][j - 1], 5) == vert[i + 1][j - 1].value: same.append((i + 1) * sizeY + j - 1) if i + 1 < sizeX and j + 1 < sizeY: if round(vert[i][j].value - vert[i][j].n[i + 1][j + 1], 5) == vert[i + 1][j + 1].value: same.append((i + 1) * sizeY + j + 1) return vertPath(vert, start, same[randint(0, len(same)) - 1], sizeX, sizeY, path) def findPath(sizeX, sizeY, start, end): vert = [] for i in range(sizeX): temp = [] for j in range(sizeY): temp.append(Vertex(i * sizeY + j, sizeX, sizeY)) vert.append(temp) vert[start // sizeY][start % sizeY].value = 0 vertCalc(vert, start, sizeX, sizeY) return vertPath(vert, start, end, sizeX, sizeY)

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8ec065068a50a121692453a485b19d7ff6b8b458

182

py

Python

tests/test_mac_screencapture.py

jonringer/pyscreenshot

44cefded198b26fd162ab12c9e947704ec9dced0

[ "BSD-2-Clause" ]

416

2015-01-01T00:41:31.000Z

2022-03-31T10:15:53.000Z

tests/test_mac_screencapture.py

jonringer/pyscreenshot

44cefded198b26fd162ab12c9e947704ec9dced0

[ "BSD-2-Clause" ]

72

2015-02-23T20:12:17.000Z

2022-03-02T21:23:17.000Z

tests/test_mac_screencapture.py

jonringer/pyscreenshot

44cefded198b26fd162ab12c9e947704ec9dced0

[ "BSD-2-Clause" ]

88

2015-03-04T03:29:43.000Z

2021-10-04T06:37:00.000Z

from bt import backend_to_check from pyscreenshot.util import platform_is_osx if platform_is_osx(): def test_mac_screencapture(): backend_to_check("mac_screencapture")

22.75

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6

d9140dc93ea732c8c7456e1c9d2605d4e92f2106

30

py

Python

kornia/tracking/__init__.py

mfkiwl/kornia

df591b3b440de84c197f7e2ef91e1d3880e35ce1

[ "ECL-2.0", "Apache-2.0" ]

null

kornia/tracking/__init__.py

mfkiwl/kornia

df591b3b440de84c197f7e2ef91e1d3880e35ce1

[ "ECL-2.0", "Apache-2.0" ]

9

2021-12-12T09:15:33.000Z

2022-03-20T09:12:00.000Z

kornia/tracking/__init__.py

mfkiwl/kornia

df591b3b440de84c197f7e2ef91e1d3880e35ce1

[ "ECL-2.0", "Apache-2.0" ]

null

from .planar_tracker import *

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0

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1

0

1

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1

0

6

d9157cc197b84dec7d5282f1597f3dca44e779b1

106

py

Python

teerace/lib/context_processors.py

chaosk/teerace

16110c739eb12009d8e70fb3c3bfe8ed87112cfa

[ "BSD-3-Clause" ]

3

2016-06-10T03:45:19.000Z

2018-09-27T15:32:17.000Z

teerace/lib/context_processors.py

teerace/web

16110c739eb12009d8e70fb3c3bfe8ed87112cfa

[ "BSD-3-Clause" ]

26

2018-12-31T12:54:27.000Z

2019-04-08T02:34:44.000Z

teerace/lib/context_processors.py

teerace/web

16110c739eb12009d8e70fb3c3bfe8ed87112cfa

[ "BSD-3-Clause" ]

3

2017-01-08T14:59:18.000Z

2018-11-21T14:59:03.000Z

from django.conf import settings as _settings def settings(request): return {"settings": _settings}

17.666667

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6

d930d0cdd96f173459e9ffe25b58043a0210b8cb

12,597

py

Python

tests/tests_request_creators/tests_hitbtc/test_market_data.py

astsu-dev/exapi

1ef39ccdd77e9ddb60ec6eaa16a2cc26e1ac3e12

[ "MIT" ]

null

tests/tests_request_creators/tests_hitbtc/test_market_data.py

astsu-dev/exapi

1ef39ccdd77e9ddb60ec6eaa16a2cc26e1ac3e12

[ "MIT" ]

null

tests/tests_request_creators/tests_hitbtc/test_market_data.py

astsu-dev/exapi

1ef39ccdd77e9ddb60ec6eaa16a2cc26e1ac3e12

[ "MIT" ]

null

import pytest from yarl import URL from exapi.request_creators.hitbtc.market_data import \ HitbtcMarketDataRequestCreator from exapi.request_creators.request import Request @pytest.fixture(scope="module") def creator() -> HitbtcMarketDataRequestCreator: return HitbtcMarketDataRequestCreator() def test_create_get_currencies_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/currency") expected = Request( method="GET", url=url) assert creator.create_get_currencies_request() == expected url = url.with_query({"currencies": "BTC,ETH"}) expected = Request(method="GET", url=url) assert creator.create_get_currencies_request( ["BTC", "ETH"]) == expected def test_create_get_certain_currency_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/currency/BTC") expected = Request(method="GET", url=url) assert creator.create_get_certain_currency_request("BTC") == expected def test_create_get_symbols_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/symbol") expected = Request(method="GET", url=url) assert creator.create_get_symbols_request() == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD"}) expected = Request(method="GET", url=url) assert creator.create_get_symbols_request( ["ETHBTC", "BTCUSD"]) == expected def test_create_get_certain_symbol_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/symbol/BTCUSD") expected = Request(method="GET", url=url) assert creator.create_get_certain_symbol_request("BTCUSD") == expected def test_create_get_tickers_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/ticker") expected = Request(method="GET", url=url) assert creator.create_get_tickers_request() == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD"}) expected = Request(method="GET", url=url) assert creator.create_get_tickers_request( ["ETHBTC", "BTCUSD"]) == expected def test_create_get_certain_ticker_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/ticker/BTCUSD") expected = Request(method="GET", url=url) assert creator.create_get_certain_ticker_request("BTCUSD") == expected def test_create_get_trades_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/trades") expected = Request( method="GET", url=url) assert creator.create_get_trades_request() == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD"}) expected = Request(method="GET", url=url) assert creator.create_get_trades_request( symbols=["ETHBTC", "BTCUSD"]) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "sort": "ASC"}) expected = Request(method="GET", url=url) assert creator.create_get_trades_request( symbols=["ETHBTC", "BTCUSD"], sort="ASC") == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "sort": "ASC", "from": "150"}) expected = Request(method="GET", url=url) assert creator.create_get_trades_request( symbols=["ETHBTC", "BTCUSD"], sort="ASC", from_=150) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "sort": "ASC", "from": "150", "till": "160"}) expected = Request(method="GET", url=url) assert creator.create_get_trades_request( symbols=["ETHBTC", "BTCUSD"], sort="ASC", from_=150, till=160) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "sort": "ASC", "from": "150", "till": "160", "limit": "500"}) expected = Request(method="GET", url=url) assert creator.create_get_trades_request( symbols=["ETHBTC", "BTCUSD"], sort="ASC", from_=150, till=160, limit=500) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "sort": "ASC", "from": "150", "till": "160", "limit": "500", "offset": "100"}) expected = Request(method="GET", url=url) assert creator.create_get_trades_request( symbols=["ETHBTC", "BTCUSD"], sort="ASC", from_=150, till=160, limit=500, offset=100) == expected def test_create_get_certain_trades_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/trades/BTCUSD") expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request("BTCUSD") == expected url = url.with_query({"sort": "ASC"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request( symbol="BTCUSD", sort="ASC") == expected url = url.with_query({"sort": "ASC", "by": "timestamp"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request( symbol="BTCUSD", sort="ASC", by="timestamp") == expected url = url.with_query({"sort": "ASC", "by": "timestamp", "from": "150"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request( symbol="BTCUSD", sort="ASC", by="timestamp", from_=150) == expected url = url.with_query({"sort": "ASC", "by": "timestamp", "from": "150", "till": "160"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request( symbol="BTCUSD", sort="ASC", by="timestamp", from_=150, till=160) == expected url = url.with_query({"sort": "ASC", "by": "timestamp", "from": "150", "till": "160", "limit": "500"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request( symbol="BTCUSD", sort="ASC", by="timestamp", from_=150, till=160, limit=500) == expected url = url.with_query({"sort": "ASC", "by": "timestamp", "from": "150", "till": "160", "limit": "500", "offset": "100"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_trades_request( symbol="BTCUSD", sort="ASC", by="timestamp", from_=150, till=160, limit=500, offset=100) == expected def test_create_get_orderbooks_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/orderbook") expected = Request(method="GET", url=url) assert creator.create_get_orderbooks_request() == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD"}) expected = Request( method="GET", url=url) assert creator.create_get_orderbooks_request( ["ETHBTC", "BTCUSD"]) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "limit": "0"}) expected = Request(method="GET", url=url) assert creator.create_get_orderbooks_request( ["ETHBTC", "BTCUSD"], 0) == expected def test_create_get_certain_orderbook_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/orderbook/BTCUSD") expected = Request(method="GET", url=url) assert creator.create_get_certain_orderbook_request("BTCUSD") == expected url = url.with_query({"limit": "0", "volume": "15"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_orderbook_request( "BTCUSD", limit=0, volume=15) == expected url = url.with_query({"limit": "0"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_orderbook_request( "BTCUSD", 0) == expected def test_create_get_candles_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/candles") expected = Request( method="GET", url=url) assert creator.create_get_candles_request() == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"]) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "period": "1M"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"], period="1M") == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "period": "1M", "sort": "ASC"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"], period="1M", sort="ASC") == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "period": "1M", "sort": "ASC", "from": "150"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"], period="1M", sort="ASC", from_=150) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "period": "1M", "sort": "ASC", "from": "150", "till": "160"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"], period="1M", sort="ASC", from_=150, till=160) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "period": "1M", "sort": "ASC", "from": "150", "till": "160", "limit": "500"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"], period="1M", sort="ASC", from_=150, till=160, limit=500) == expected url = url.with_query({"symbols": "ETHBTC,BTCUSD", "period": "1M", "sort": "ASC", "from": "150", "till": "160", "limit": "500", "offset": "100"}) expected = Request(method="GET", url=url) assert creator.create_get_candles_request( symbols=["ETHBTC", "BTCUSD"], period="1M", sort="ASC", from_=150, till=160, limit=500, offset=100) == expected def test_create_get_certain_candles_request(creator: HitbtcMarketDataRequestCreator) -> None: url = URL("https://api.hitbtc.com/api/2/public/candles/BTCUSD") expected = Request( method="GET", url=url) assert creator.create_get_certain_candles_request("BTCUSD") == expected expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD") == expected url = url.with_query({"period": "1M"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD", period="1M") == expected url = url.with_query({"period": "1M", "sort": "ASC"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD", period="1M", sort="ASC") == expected url = url.with_query({"period": "1M", "sort": "ASC", "from": "150"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD", period="1M", sort="ASC", from_=150) == expected url = url.with_query({"period": "1M", "sort": "ASC", "from": "150", "till": "160"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD", period="1M", sort="ASC", from_=150, till=160) == expected url = url.with_query({"period": "1M", "sort": "ASC", "from": "150", "till": "160", "limit": "500"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD", period="1M", sort="ASC", from_=150, till=160, limit=500) == expected url = url.with_query({"period": "1M", "sort": "ASC", "from": "150", "till": "160", "limit": "500", "offset": "100"}) expected = Request(method="GET", url=url) assert creator.create_get_certain_candles_request( symbol="BTCUSD", period="1M", sort="ASC", from_=150, till=160, limit=500, offset=100) == expected

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797a0690301e70f01de0f5f46a51ddaa5f77a0da

37

py

Python

ModellingArch/__init__.py

MikaZeilstra/ModellingArch

71a8948f0e8feb086b291fa12d53a0a0adf50c3d

[ "MIT" ]

null

ModellingArch/__init__.py

MikaZeilstra/ModellingArch

71a8948f0e8feb086b291fa12d53a0a0adf50c3d

[ "MIT" ]

null

ModellingArch/__init__.py

MikaZeilstra/ModellingArch

71a8948f0e8feb086b291fa12d53a0a0adf50c3d

[ "MIT" ]

null

from ModellingArch.Model import Model

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1

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6

79ac20c94910683e931d38b82bfe2bcb6d880eb1

35

py

Python

ipynb/junix/__init__.py

tanyajainC137/flask-dashboard

88b908224ad6d748620a32debc0c9a662fd9e529

[ "MIT" ]

null

ipynb/junix/__init__.py

tanyajainC137/flask-dashboard

88b908224ad6d748620a32debc0c9a662fd9e529

[ "MIT" ]

null

ipynb/junix/__init__.py

tanyajainC137/flask-dashboard

88b908224ad6d748620a32debc0c9a662fd9e529

[ "MIT" ]

null

from .exporter import export_images

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1

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1

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6

8dff63840f16ab4199fd65d02aac2e5122ca9a0c

93

py

Python

test/test_metaL.py

ponyatov/metaLpy

96149313e8083536ade1c331825242f6996f05b3

[ "MIT" ]

null

test/test_metaL.py

ponyatov/metaLpy

96149313e8083536ade1c331825242f6996f05b3

[ "MIT" ]

null

test/test_metaL.py

ponyatov/metaLpy

96149313e8083536ade1c331825242f6996f05b3

[ "MIT" ]

null

## @file import pytest ## alwais `true` ## @ingroup test def test_empty(): assert True

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6

5c0a13a071297a64f17b775a20ba5d0313ab5bc7

74

py

Python

statsmodels/nonparametric/api.py

escheffel/statsmodels

bc70147c4c7ea00b6ac7256bbaf107902983c189

[ "BSD-3-Clause" ]

2

2017-01-05T22:44:37.000Z

2018-04-26T08:34:00.000Z

statsmodels/nonparametric/api.py

langmore/statsmodels

a29d0418436a9b38b11101f7741ce6cb35b9e2cd

[ "BSD-3-Clause" ]

null

statsmodels/nonparametric/api.py

langmore/statsmodels

a29d0418436a9b38b11101f7741ce6cb35b9e2cd

[ "BSD-3-Clause" ]

null

from kde import KDE from smoothers_lowess import lowess import bandwidths

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6

3089e2ece5579c4322c016b82e31d603866ad2b8

140

py

Python

conf/gunicorn_config.py

LASI-UFPI/back-end-datafriends

098b89486f98fabeba206703d32e969fc7992721

[ "MIT" ]

2

2021-05-24T14:44:47.000Z

2022-02-27T20:28:37.000Z

conf/gunicorn_config.py

LASI-UFPI/back-end-datafriends

098b89486f98fabeba206703d32e969fc7992721

[ "MIT" ]

2

2022-02-13T13:13:50.000Z

2022-03-04T23:41:53.000Z

conf/gunicorn_config.py

LASI-UFPI/back-end-datafriends

098b89486f98fabeba206703d32e969fc7992721

[ "MIT" ]

1

2021-05-24T14:44:50.000Z

command = '/opt/lasi/back-end-datafriends/venv/bin/gunicorn' pythonpath = '/opt/lasi/back-end-datafriends' bind = '0.0.0.0:8000' workers = 3

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1

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1

null

0

6

a518454b0e28ed5cb26c931568df41dede18afde

160

py

Python

funcs/__init__.py

farkon00/binarian

8ebe6247a8a4f709861432fc9d057b8aaeee2117

[ "MIT" ]

2

2022-02-23T21:24:47.000Z

2022-03-25T08:18:16.000Z

funcs/__init__.py

farkon00/binarian

8ebe6247a8a4f709861432fc9d057b8aaeee2117

[ "MIT" ]

null

funcs/__init__.py

farkon00/binarian

8ebe6247a8a4f709861432fc9d057b8aaeee2117

[ "MIT" ]

null

import sys sys.path.append(".") from binarian import * from . import exceptions from . import utils from . import code_preparer from . import brackets_parser

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1

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6

ebb92a644a0630b391f188a72d14906aa93018ce

35

py

Python

dkconfig/__init__.py

datakortet/dkconfig

9496bce00741f7c8839b6f86cb74388268bdbeb6

[ "MIT" ]

null

dkconfig/__init__.py

datakortet/dkconfig

9496bce00741f7c8839b6f86cb74388268bdbeb6

[ "MIT" ]

null

dkconfig/__init__.py

datakortet/dkconfig

9496bce00741f7c8839b6f86cb74388268bdbeb6

[ "MIT" ]

null

from .dkconfig import parser, main

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0

1

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1

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1

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6

ebc2b67804ab93b1fd58143725dcb389078c66ad

203

py

Python

factorial.py

rajat1401/Python-Thunder

76fcbc659070cfd92eeae4a68e485fe406949f16

[ "MIT" ]

null

factorial.py

rajat1401/Python-Thunder

76fcbc659070cfd92eeae4a68e485fe406949f16

[ "MIT" ]

null

factorial.py

rajat1401/Python-Thunder

76fcbc659070cfd92eeae4a68e485fe406949f16

[ "MIT" ]

null

''' Probem Task : This program will compute the factorial of a number Problem Link : https://edabit.com/challenge/PNbsQzmDR3CJ9JHkB ''' import math def factorial(n): return math.factorial(n)

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null

0

1

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1

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6

ccfd2febc56f42c375d3c307e4741721583dc898

133

py

Python

causal_world/evaluation/__init__.py

michaelfeil/CausalWorld

ff866159ef0ee9c407893ae204e93eb98dd68be2

[ "MIT" ]

2

2021-09-22T08:20:12.000Z

2021-11-16T14:20:45.000Z

causal_world/evaluation/__init__.py

michaelfeil/CausalWorld

ff866159ef0ee9c407893ae204e93eb98dd68be2

[ "MIT" ]

null

causal_world/evaluation/__init__.py

michaelfeil/CausalWorld

ff866159ef0ee9c407893ae204e93eb98dd68be2

[ "MIT" ]

null

from causal_world.evaluation.protocols.protocol import ProtocolBase from causal_world.evaluation.evaluation import EvaluationPipeline

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6

6942e417feb92b40005352a886f8f521e5b4b86a

41

py

Python

iopipe/contrib/logger/__init__.py

skeptycal/iopipe-python

f6afba36663751779cba55ce53c0e1f2042df0d7

[ "Apache-2.0" ]

74

2016-08-18T14:26:50.000Z

2021-11-21T10:58:32.000Z

iopipe/contrib/logger/__init__.py

vemel/iopipe-python

46c277f9447ddb00e544437ceaa7ba263a759c1d

[ "Apache-2.0" ]

198

2016-08-18T18:52:43.000Z

2021-05-09T10:01:14.000Z

iopipe/contrib/logger/__init__.py

vemel/iopipe-python

46c277f9447ddb00e544437ceaa7ba263a759c1d

[ "Apache-2.0" ]

23

2016-08-04T23:22:21.000Z

2020-01-20T13:54:27.000Z

from .plugin import LoggerPlugin # noqa

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null

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1

0

1

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1

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6

696d4174b7c92ef33969c7268439dd502c3d2b87

149

py

Python

cloudshell/firewall/paloalto/panos/flows/panos_state_flow.py

QualiSystems/cloudshell-firewall-panos

807f296b6960a6dc8fdc37ac332dcb72e3caa8e2

[ "Apache-2.0" ]

null

cloudshell/firewall/paloalto/panos/flows/panos_state_flow.py

QualiSystems/cloudshell-firewall-panos

807f296b6960a6dc8fdc37ac332dcb72e3caa8e2

[ "Apache-2.0" ]

1

2021-03-16T18:24:24.000Z

cloudshell/firewall/paloalto/panos/flows/panos_state_flow.py

QualiSystems/cloudshell-firewall-panos

807f296b6960a6dc8fdc37ac332dcb72e3caa8e2

[ "Apache-2.0" ]

null

#!/usr/bin/python # -*- coding: utf-8 -*- from cloudshell.shell.flows.state.basic_flow import StateFlow class PanOSStateFlow(StateFlow): pass

16.555556

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8

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true

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6

15c19b8b5ebc775bff2820c24048fe259a916c3c

51

py

Python

Models/__init__.py

AndresJejen/DashBoardTrocafoneDS4A

c58675192688a737972ce984ecf22d681246b7bc

[ "MIT" ]

1

2020-05-24T00:28:38.000Z

Models/__init__.py

AndresJejen/DashBoardTrocafoneDS4A

c58675192688a737972ce984ecf22d681246b7bc

[ "MIT" ]

null

Models/__init__.py

AndresJejen/DashBoardTrocafoneDS4A

c58675192688a737972ce984ecf22d681246b7bc

[ "MIT" ]

1

2020-05-24T01:27:01.000Z

from .LinearRegression import LinearRegressionModel

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15cd0ac59d86abb5fb51f3179e342f2b6f23a1c3

195

py

Python

zfit/dimension.py

donalrinho/zfit

9769ef7d56a6be9a5d438e47b80ea5a8f772bc24

[ "BSD-3-Clause" ]

null

zfit/dimension.py

donalrinho/zfit

9769ef7d56a6be9a5d438e47b80ea5a8f772bc24

[ "BSD-3-Clause" ]

null

zfit/dimension.py

donalrinho/zfit

9769ef7d56a6be9a5d438e47b80ea5a8f772bc24

[ "BSD-3-Clause" ]

null

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15de8961477fb58e446d86db6049c318d521c6de

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py

Python

pyfi/__init__.py

rlinguri/pyfi

08cccda7eab1119a2a82d265a015c95ba9bf4431

[ "MIT" ]

null

pyfi/__init__.py

rlinguri/pyfi

08cccda7eab1119a2a82d265a015c95ba9bf4431

[ "MIT" ]

null

pyfi/__init__.py

rlinguri/pyfi

08cccda7eab1119a2a82d265a015c95ba9bf4431

[ "MIT" ]

1

2019-01-12T17:02:01.000Z

#!/usr/bin/env python from pyfi.entity import * from pyfi.calendar import * from pyfi.yhapi import * __all__ = ['Entity', 'Calendar', 'Session', 'Tick', 'Result']

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c60b8918d4a54f76df084f23c8d4f9a2c0f51e55

36

py

Python

tests/test_general.py

Cloud-Atlas-BR/CloudAtlas

53b2b7859047fd8c98b548afdec9788334fe7b2f

[ "MIT" ]

null

tests/test_general.py

Cloud-Atlas-BR/CloudAtlas

53b2b7859047fd8c98b548afdec9788334fe7b2f

[ "MIT" ]

null

tests/test_general.py

Cloud-Atlas-BR/CloudAtlas

53b2b7859047fd8c98b548afdec9788334fe7b2f

[ "MIT" ]

null

def test_answer(): assert 2 == 2

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6

c619a0a7f1029b9312ddb12daf887420e80965c3

20

py

Python

src/wspc/__init__.py

shakedna1/wspc_rep

f4492af8cec25a3f7b00687c08d30754a1c0c91f

[ "MIT" ]

null

src/wspc/__init__.py

shakedna1/wspc_rep

f4492af8cec25a3f7b00687c08d30754a1c0c91f

[ "MIT" ]

null

src/wspc/__init__.py

shakedna1/wspc_rep

f4492af8cec25a3f7b00687c08d30754a1c0c91f

[ "MIT" ]

null

from .wspc import *

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6

c61c9e49e38f6232b0e59302c1905390097d4494

28

py

Python

authopenid/__init__.py

dairiki/authopenid-plugin

40dd4503221a0fcbbccfba530025496e0c1f7b1b

[ "BSD-3-Clause" ]

2

2015-01-06T03:21:55.000Z

2015-02-19T21:16:09.000Z

authopenid/__init__.py

trac-hacks/authopenid-plugin

40dd4503221a0fcbbccfba530025496e0c1f7b1b

[ "BSD-3-Clause" ]

8

2015-02-20T02:24:29.000Z

2020-07-23T18:48:13.000Z

authopenid/__init__.py

dairiki/authopenid-plugin

40dd4503221a0fcbbccfba530025496e0c1f7b1b

[ "BSD-3-Clause" ]

4

2015-04-08T17:55:38.000Z

2019-12-24T09:58:08.000Z

from authopenid import *

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2

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6

c6219b2d2bd435440fefd94846a5652afbb03691

5,710

py

Python

backend/api/migrations/0001_initial.py

rising-entropy/ADSL-4-Web-Portal

7ba596e0242cffb8affed47c360b52d97161d8ee

[ "MIT" ]

1

2022-02-24T05:35:19.000Z

backend/api/migrations/0001_initial.py

SayaliDesai4/StudentManegementPortal

84bdbcabde0f15db0e225ba76c03285dbeb93917

[ "MIT" ]

null

backend/api/migrations/0001_initial.py

SayaliDesai4/StudentManegementPortal

84bdbcabde0f15db0e225ba76c03285dbeb93917

[ "MIT" ]

1

2022-02-21T06:34:34.000Z

# Generated by Django 4.0.1 on 2022-02-13 06:42 from django.db import migrations, models import django.db.models.deletion class Migration(migrations.Migration): initial = True dependencies = [ ] operations = [ migrations.CreateModel( name='Classroom', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('building', models.CharField(max_length=300, unique=True)), ('room_number', models.CharField(max_length=300)), ('capacity', models.CharField(max_length=300)), ], ), migrations.CreateModel( name='Course', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('title', models.CharField(max_length=3)), ('credits', models.CharField(max_length=300)), ], ), migrations.CreateModel( name='Department', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('name', models.CharField(max_length=300, unique=True)), ('building', models.CharField(max_length=300)), ('budget', models.CharField(max_length=300)), ], ), migrations.CreateModel( name='Instructor', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('name', models.CharField(max_length=300)), ('salary', models.CharField(max_length=300)), ('department', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.department')), ], ), migrations.CreateModel( name='Section', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('semester', models.CharField(max_length=300)), ('year', models.CharField(max_length=300)), ('classroom', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.classroom')), ('course', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.course')), ], ), migrations.CreateModel( name='Student', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('name', models.CharField(max_length=300)), ('credits', models.CharField(max_length=300)), ('department', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.department')), ], ), migrations.CreateModel( name='TimeSlot', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('day', models.CharField(max_length=300)), ('startTime', models.CharField(max_length=300)), ('endTime', models.CharField(max_length=300)), ], ), migrations.CreateModel( name='StudentTakesSection', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('grade', models.CharField(max_length=300)), ('section', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.section')), ('student', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.student')), ], ), migrations.AddField( model_name='section', name='timeSlot', field=models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.timeslot'), ), migrations.CreateModel( name='Prerequisites', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('course', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, related_name='%(class)s_requests_created', to='api.course')), ('prereq', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.course')), ], ), migrations.CreateModel( name='InstructorTeachesSection', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('instructor', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.instructor')), ('section', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.section')), ], ), migrations.AddField( model_name='course', name='department', field=models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.department'), ), migrations.CreateModel( name='Advisor', fields=[ ('id', models.BigAutoField(auto_created=True, primary_key=True, serialize=False, verbose_name='ID')), ('instructor', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.instructor')), ('student', models.ForeignKey(on_delete=django.db.models.deletion.CASCADE, to='api.student')), ], ), ]

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6

c6318dad7a68979ccf0ad1dfb91c1e8c2d708af5

290

py

Python

site/projectLms/Aluno/views.py

GuiGusmao/LMSProjeto

2c1ffc302068c7d97a79a847b47640e0a6e3dde4

[ "Apache-2.0" ]

null

site/projectLms/Aluno/views.py

GuiGusmao/LMSProjeto

2c1ffc302068c7d97a79a847b47640e0a6e3dde4

[ "Apache-2.0" ]

null

site/projectLms/Aluno/views.py

GuiGusmao/LMSProjeto

2c1ffc302068c7d97a79a847b47640e0a6e3dde4

[ "Apache-2.0" ]

null

from django.shortcuts import render def notas(request): return render(request,'notas.html') def PortalHome(request): return render(request,'PortalHome.html') def contato(request): return render(request,'contato.html') def sugestao(request): return render(request,'sugestao.html')

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6

c639807e62bfa2b0f751bee1cb27c73f039d7e00

32

py

Python

python/scirpt.py

pection-zz/Allproject

25dd122cb4b30a360894aba0be4b4a62f465b68e

[ "MIT" ]

2

2020-09-19T04:22:52.000Z

2020-09-23T14:04:17.000Z

python/scirpt.py

pection/Allproject

25dd122cb4b30a360894aba0be4b4a62f465b68e

[ "MIT" ]

null

python/scirpt.py

pection/Allproject

25dd122cb4b30a360894aba0be4b4a62f465b68e

[ "MIT" ]

2

2020-09-13T03:47:22.000Z

2020-09-23T14:04:19.000Z

import a_module a_module.func()

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6

c63c110e04e5ad3e484613c3a0f15966391fbbba

9,355

py

Python

profiles/tests/test_gql_federation.py

City-of-Helsinki/opencity-profile

a430b562b9937f443d391475fabdc27068b95c49

[ "MIT" ]

5

2020-03-17T15:56:17.000Z

2022-01-31T13:43:31.000Z

profiles/tests/test_gql_federation.py

City-of-Helsinki/opencity-profile

a430b562b9937f443d391475fabdc27068b95c49

[ "MIT" ]

337

2018-05-21T08:35:05.000Z

2022-03-14T07:38:15.000Z

profiles/tests/test_gql_federation.py

City-of-Helsinki/opencity-profile

a430b562b9937f443d391475fabdc27068b95c49

[ "MIT" ]

10

2019-08-05T08:16:06.000Z

2021-08-06T15:08:44.000Z

import pytest from graphql_relay import to_global_id from guardian.shortcuts import assign_perm from open_city_profile.tests.asserts import assert_match_error_code from profiles.schema import AddressNode, ProfileNode from profiles.tests.factories import AddressFactory, ProfileFactory from services.tests.factories import ServiceConnectionFactory GRAPHQL_SDL_QUERY = """ query { _service { sdl } } """ ENTITY_QUERY = """ query ($_representations: [_Any!]!) { _entities(representations: $_representations) { ... on ProfileNode { id firstName } ... on AddressNode { id address postalCode } } } """ @pytest.mark.parametrize("schema_type", ["ProfileNode", "AddressNode"]) def test_node_exposes_key_for_federation_gateway(schema_type, anon_user_gql_client): executed = anon_user_gql_client.execute(GRAPHQL_SDL_QUERY) type_definition = f'type {schema_type} implements Node @key(fields: "id")' sdl = executed["data"]["_service"]["sdl"] assert type_definition in sdl def test_profile_connection_schema_matches_federated_schema(anon_user_gql_client): executed = anon_user_gql_client.execute(GRAPHQL_SDL_QUERY) assert ( "type ProfileNodeConnection { pageInfo: PageInfo! " "edges: [ProfileNodeEdge]! count: Int! totalCount: Int! }" in executed["data"]["_service"]["sdl"] ) def test_address_connection_schema_matches_federated_schema(anon_user_gql_client): executed = anon_user_gql_client.execute(GRAPHQL_SDL_QUERY) assert ( "type AddressNodeConnection { pageInfo: PageInfo! edges: [AddressNodeEdge]! }" in executed["data"]["_service"]["sdl"] ) def _create_profile_and_variables(with_serviceconnection, service, user=None): profile = ProfileFactory(user=user) if with_serviceconnection: ServiceConnectionFactory(profile=profile, service=service) profile._global_id = to_global_id(ProfileNode._meta.name, profile.id) variables = { "_representations": [ {"id": profile._global_id, "__typename": ProfileNode._meta.name} ] } return profile, variables def _create_address_and_variables(with_serviceconnection, service, user=None): profile = ProfileFactory(user=user) address = AddressFactory(profile=profile) if with_serviceconnection: ServiceConnectionFactory(profile=profile, service=service) address._global_id = to_global_id(AddressNode._meta.name, address.id) variables = { "_representations": [ {"id": address._global_id, "__typename": AddressNode._meta.name} ] } return address, variables @pytest.mark.parametrize("with_service", (True, False)) @pytest.mark.parametrize("with_serviceconnection", (True, False)) def test_anonymous_user_can_not_resolve_profile_entity( anon_user_gql_client, service, with_service, with_serviceconnection ): profile, variables = _create_profile_and_variables(with_serviceconnection, service) executed = anon_user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service if with_service else None, ) assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize("with_service", (True, False)) @pytest.mark.parametrize("with_serviceconnection", (True, False)) def test_owner_can_resolve_profile_entity( user_gql_client, service, with_service, with_serviceconnection ): profile, variables = _create_profile_and_variables( with_serviceconnection, service, user=user_gql_client.user ) expected_data = { "_entities": [{"id": profile._global_id, "firstName": profile.first_name}] } executed = user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service if with_service else None, ) if with_service and with_serviceconnection: assert executed["data"] == expected_data elif not with_service: assert_match_error_code(executed, "SERVICE_NOT_IDENTIFIED_ERROR") assert executed["data"]["_entities"] is None else: assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize("with_service", (True, False)) @pytest.mark.parametrize("with_serviceconnection", (True, False)) def test_non_owner_user_can_not_resolve_profile_entity( user_gql_client, service, with_service, with_serviceconnection ): profile, variables = _create_profile_and_variables(with_serviceconnection, service) executed = user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service if with_service else None, ) if not with_service: assert_match_error_code(executed, "SERVICE_NOT_IDENTIFIED_ERROR") assert executed["data"]["_entities"] is None else: assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize( "with_serviceconnection", (True, False), ) def test_staff_user_can_resolve_profile_entity( user_gql_client, group, service, with_serviceconnection ): profile, variables = _create_profile_and_variables(with_serviceconnection, service) user = user_gql_client.user user.groups.add(group) assign_perm("can_view_profiles", group, service) expected_data = { "_entities": [{"id": profile._global_id, "firstName": profile.first_name}] } executed = user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service, ) if with_serviceconnection: assert executed["data"] == expected_data else: assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize("with_service", (True, False)) @pytest.mark.parametrize("with_serviceconnection", (True, False)) def test_anonymous_user_can_not_resolve_address_entity( anon_user_gql_client, service, with_service, with_serviceconnection ): address, variables = _create_address_and_variables(with_serviceconnection, service) executed = anon_user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service if with_service else None, ) assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize("with_service", (True, False)) @pytest.mark.parametrize("with_serviceconnection", (True, False)) def test_owner_can_resolve_address_entity( user_gql_client, service, with_service, with_serviceconnection ): address, variables = _create_address_and_variables( with_serviceconnection, service, user=user_gql_client.user ) expected_data = { "_entities": [ { "id": address._global_id, "address": address.address, "postalCode": address.postal_code, } ] } executed = user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service if with_service else None, ) if with_service and with_serviceconnection: assert executed["data"] == expected_data elif not with_service: assert_match_error_code(executed, "SERVICE_NOT_IDENTIFIED_ERROR") assert executed["data"]["_entities"] is None else: assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize("with_service", (True, False)) @pytest.mark.parametrize("with_serviceconnection", (True, False)) def test_non_owner_user_can_not_resolve_address_entity( user_gql_client, service, with_service, with_serviceconnection ): address, variables = _create_address_and_variables(with_serviceconnection, service) executed = user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service if with_service else None, ) if not with_service: assert_match_error_code(executed, "SERVICE_NOT_IDENTIFIED_ERROR") assert executed["data"]["_entities"] is None else: assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None @pytest.mark.parametrize( "with_serviceconnection", (True, False), ) def test_staff_user_can_resolve_address_entity( user_gql_client, group, service, with_serviceconnection ): address, variables = _create_address_and_variables(with_serviceconnection, service) user = user_gql_client.user user.groups.add(group) assign_perm("can_view_profiles", group, service) expected_data = { "_entities": [ { "id": address._global_id, "address": address.address, "postalCode": address.postal_code, } ] } executed = user_gql_client.execute( ENTITY_QUERY, variables=variables, service=service, ) if with_serviceconnection: assert executed["data"] == expected_data else: assert_match_error_code(executed, "PERMISSION_DENIED_ERROR") assert executed["data"]["_entities"] is None

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null

0

1

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6

d699cf6a0abfd9944a570de426cbc2ae040e473a

3,831

py

Python

dlfairness/other/bias_metric_exp.py

lin-tan/fairness-variance

7f6aee23160707ffe78f429e5d960022ea1c9fe4

[ "BSD-3-Clause" ]

null

dlfairness/other/bias_metric_exp.py

lin-tan/fairness-variance

7f6aee23160707ffe78f429e5d960022ea1c9fe4

[ "BSD-3-Clause" ]

null

dlfairness/other/bias_metric_exp.py

lin-tan/fairness-variance

7f6aee23160707ffe78f429e5d960022ea1c9fe4

[ "BSD-3-Clause" ]

null

import numpy as np import sys arr = np.empty((2, 2, 2)) # GT, Pred, Group arr[0][0][0] = 80 arr[0][1][0] = 20 arr[1][0][0] = 10 arr[1][1][0] = 90 arr[0][0][1] = 60 arr[0][1][1] = 40 arr[1][0][1] = 70 arr[1][1][1] = 30 # SP, class 0 sp_f = arr[:, 0, :].sum() / arr.sum() sp_f_0 = arr[:, 0, 0].sum() / arr[:, :, 0].sum() sp_f_1 = arr[:, 0, 1].sum() / arr[:, :, 1].sum() bias_0 = abs(sp_f - sp_f_0) * (arr[:, :, 0].sum() / arr.sum()) + abs(sp_f - sp_f_1) * (arr[:, :, 1].sum() / arr.sum()) # class 1 sp_f = arr[:, 1, :].sum() / arr.sum() sp_f_0 = arr[:, 1, 0].sum() / arr[:, :, 0].sum() sp_f_1 = arr[:, 1, 1].sum() / arr[:, :, 1].sum() bias_1 = abs(sp_f - sp_f_0) * (arr[:, :, 0].sum() / arr.sum()) + abs(sp_f - sp_f_1) * (arr[:, :, 1].sum() / arr.sum()) bias = (bias_0 + bias_1) / 2 print("SP:", bias_0, bias_1, bias) # FP, class 0 fp_f = arr[0, 1, :].sum() / arr[0, :, :].sum() fp_f_0 = arr[0, 1, 0].sum() / arr[0, :, 0].sum() fp_f_1 = arr[0, 1, 1].sum() / arr[0, :, 1].sum() bias_0 = abs(fp_f - fp_f_0) * (arr[:, :, 0].sum() / arr.sum()) + abs(fp_f - fp_f_1) * (arr[:, :, 1].sum() / arr.sum()) # class 1 fp_f = arr[1, 0, :].sum() / arr[1, :, :].sum() fp_f_0 = arr[1, 0, 0].sum() / arr[1, :, 0].sum() fp_f_1 = arr[1, 0, 1].sum() / arr[1, :, 1].sum() bias_1 = abs(fp_f - fp_f_0) * (arr[:, :, 0].sum() / arr.sum()) + abs(fp_f - fp_f_1) * (arr[:, :, 1].sum() / arr.sum()) bias = (bias_0 + bias_1) / 2 print("FP:", bias_0, bias_1, bias) # DP, class 0 dp_0 = arr[:, 0, 0].sum() / arr[:, :, 0].sum() dp_1 = arr[:, 0, 1].sum() / arr[:, :, 1].sum() #print(dp_0, dp_1) bias_0 = abs(dp_0 - dp_1) dp_0 = arr[:, 1, 0].sum() / arr[:, :, 0].sum() dp_1 = arr[:, 1, 1].sum() / arr[:, :, 1].sum() bias_1 = abs(dp_0 - dp_1) bias = (bias_0 + bias_1) / 2 print("DP:", bias_0, bias_1, bias) # DI, class 0 di_0 = arr[:, 0, 0].sum() / arr[:, :, 0].sum() di_1 = arr[:, 0, 1].sum() / arr[:, :, 1].sum() bias_0 = 1.0 - min(di_0 / di_1, di_1 / di_0) di_0 = arr[:, 1, 0].sum() / arr[:, :, 0].sum() di_1 = arr[:, 1, 1].sum() / arr[:, :, 1].sum() bias_1 = 1.0 - min(di_0 / di_1, di_1 / di_0) bias = (bias_0 + bias_1) / 2 print("DI:", bias_0, bias_1, bias) # EO-TP, class 0 eo_0 = arr[0, 0, 0].sum() / arr[0, :, 0].sum() eo_1 = arr[0, 0, 1].sum() / arr[0, :, 1].sum() bias_0 = abs(eo_0 - eo_1) #print(eo_0, eo_1) eo_0 = arr[1, 1, 0].sum() / arr[1, :, 0].sum() eo_1 = arr[1, 1, 1].sum() / arr[1, :, 1].sum() bias_1 = abs(eo_0 - eo_1) bias = (bias_0 + bias_1) / 2 print("EO-TP:", bias_0, bias_1, bias) # EO-FP, class 0 eo_0 = arr[0, 1, 0].sum() / arr[0, :, 0].sum() eo_1 = arr[0, 1, 1].sum() / arr[0, :, 1].sum() bias_0 = abs(eo_0 - eo_1) #print(eo_0, eo_1) eo_0 = arr[1, 0, 0].sum() / arr[1, :, 0].sum() eo_1 = arr[1, 0, 1].sum() / arr[1, :, 1].sum() bias_1 = abs(eo_0 - eo_1) bias = (bias_0 + bias_1) / 2 print("EO-FP:", bias_0, bias_1, bias) # BA bs_0 = arr[0, :, 0].sum() / arr[0, :, :].sum() bs_1 = arr[0, :, 1].sum() / arr[0, :, :].sum() b_s_0 = bs_0 / (bs_0 + bs_1) b_s_1 = bs_1 / (bs_0 + bs_1) bt_0 = arr[:, 0, 0].sum() / arr[:, 0, :].sum() bt_1 = arr[:, 0, 1].sum() / arr[:, 0, :].sum() b_t_0 = bt_0 / (bt_0 + bt_1) b_t_1 = bt_1 / (bt_0 + bt_1) if b_s_0 > 0.5: bias_0 = abs(b_s_0 - b_t_0) elif b_s_1 > 0.5: bias_0 = abs(b_s_1 - b_t_1) else: bias_0 = abs(b_s_0 - b_t_0) # print(b_s_0, b_s_1) # print(b_t_0, b_t_1) bs_0 = arr[1, :, 0].sum() / arr[1, :, :].sum() bs_1 = arr[1, :, 1].sum() / arr[1, :, :].sum() b_s_0 = bs_0 / (bs_0 + bs_1) b_s_1 = bs_1 / (bs_0 + bs_1) bt_0 = arr[:, 1, 0].sum() / arr[:, 1, :].sum() bt_1 = arr[:, 1, 1].sum() / arr[:, 1, :].sum() b_t_0 = bt_0 / (bt_0 + bt_1) b_t_1 = bt_1 / (bt_0 + bt_1) if b_s_0 > 0.5: bias_1 = abs(b_s_0 - b_t_0) elif b_s_1 > 0.5: bias_1 = abs(b_s_1 - b_t_1) else: bias_1 = abs(b_s_0 - b_t_0) bias = (bias_0 + bias_1) / 2 print("BA:", bias_0, bias_1, bias)

29.244275

118

0.505612

870

3,831

1.973563

0.050575

0.153757

0.089691

0.081538

0.87187

0.822947

0.769948

0.737333

0.612114

0.525917

0

0.120836

0.200731

3,831

130

119

29.469231

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0

0.311828

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false

0

0.021505

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0

1

null

0

1

0

1

0

null

0

6

d69e3abbe3dcc09488cb886e46ff66cf611691bb

11,724

py

Python

tests/test_apigatewayv2/test_apigatewayv2.py

symroe/moto

4e106995af6f2820273528fca8a4e9ee288690a5

[ "Apache-2.0" ]

null

tests/test_apigatewayv2/test_apigatewayv2.py

symroe/moto

4e106995af6f2820273528fca8a4e9ee288690a5

[ "Apache-2.0" ]

1

2022-02-19T02:10:45.000Z

2022-02-19T02:15:52.000Z

tests/test_apigatewayv2/test_apigatewayv2.py

symroe/moto

4e106995af6f2820273528fca8a4e9ee288690a5

[ "Apache-2.0" ]

null

"""Unit tests for apigatewayv2-supported APIs.""" import boto3 import pytest import sure # noqa # pylint: disable=unused-import from botocore.exceptions import ClientError from moto import mock_apigatewayv2 # See our Development Tips on writing tests for hints on how to write good tests: # http://docs.getmoto.org/en/latest/docs/contributing/development_tips/tests.html @mock_apigatewayv2 def test_create_api_with_unknown_protocol_type(): client = boto3.client("apigatewayv2", region_name="eu-west-1") with pytest.raises(ClientError) as exc: client.create_api(Name="test-api", ProtocolType="?") err = exc.value.response["Error"] err["Code"].should.equal("BadRequestException") err["Message"].should.equal( "Invalid protocol specified. Must be one of [HTTP, WEBSOCKET]" ) @mock_apigatewayv2 def test_create_api_minimal(): client = boto3.client("apigatewayv2", region_name="eu-west-1") resp = client.create_api(Name="test-api", ProtocolType="HTTP") resp.should.have.key("ApiId") resp.should.have.key("ApiEndpoint").equals( f"https://{resp['ApiId']}.execute-api.eu-west-1.amazonaws.com" ) resp.should.have.key("ApiKeySelectionExpression").equals( "$request.header.x-api-key" ) resp.should.have.key("CreatedDate") resp.should.have.key("DisableExecuteApiEndpoint").equals(False) resp.should.have.key("Name").equals("test-api") resp.should.have.key("ProtocolType").equals("HTTP") resp.should.have.key("RouteSelectionExpression").equals( "$request.method $request.path" ) @mock_apigatewayv2 def test_create_api(): client = boto3.client("apigatewayv2", region_name="eu-west-1") resp = client.create_api( ApiKeySelectionExpression="s3l3ction", CorsConfiguration={ "AllowCredentials": True, "AllowHeaders": ["x-header1"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header1"], "MaxAge": 2, }, Description="my first api", DisableSchemaValidation=True, DisableExecuteApiEndpoint=True, Name="test-api", ProtocolType="HTTP", RouteSelectionExpression="route_s3l3ction", Version="1.0", ) resp.should.have.key("ApiId") resp.should.have.key("ApiEndpoint").equals( f"https://{resp['ApiId']}.execute-api.eu-west-1.amazonaws.com" ) resp.should.have.key("ApiKeySelectionExpression").equals("s3l3ction") resp.should.have.key("CreatedDate") resp.should.have.key("CorsConfiguration").equals( { "AllowCredentials": True, "AllowHeaders": ["x-header1"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header1"], "MaxAge": 2, } ) resp.should.have.key("Description").equals("my first api") resp.should.have.key("DisableExecuteApiEndpoint").equals(True) resp.should.have.key("DisableSchemaValidation").equals(True) resp.should.have.key("Name").equals("test-api") resp.should.have.key("ProtocolType").equals("HTTP") resp.should.have.key("RouteSelectionExpression").equals("route_s3l3ction") resp.should.have.key("Version").equals("1.0") @mock_apigatewayv2 def test_delete_api(): client = boto3.client("apigatewayv2", region_name="us-east-2") api_id = client.create_api(Name="t", ProtocolType="HTTP")["ApiId"] client.delete_api(ApiId=api_id) with pytest.raises(ClientError) as exc: client.get_api(ApiId=api_id) exc.value.response["Error"]["Code"].should.equal("NotFoundException") @mock_apigatewayv2 def test_delete_cors_configuration(): client = boto3.client("apigatewayv2", region_name="eu-west-1") api_id = client.create_api( ApiKeySelectionExpression="s3l3ction", CorsConfiguration={ "AllowCredentials": True, "AllowHeaders": ["x-header1"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header1"], "MaxAge": 2, }, Description="my first api", DisableSchemaValidation=True, DisableExecuteApiEndpoint=True, Name="test-api", ProtocolType="HTTP", RouteSelectionExpression="route_s3l3ction", Version="1.0", )["ApiId"] client.delete_cors_configuration(ApiId=api_id) resp = client.get_api(ApiId=api_id) resp.shouldnt.have.key("CorsConfiguration") resp.should.have.key("Description").equals("my first api") resp.should.have.key("Name").equals("test-api") @mock_apigatewayv2 def test_get_api_unknown(): client = boto3.client("apigatewayv2", region_name="ap-southeast-1") with pytest.raises(ClientError) as exc: client.get_api(ApiId="unknown") err = exc.value.response["Error"] err["Code"].should.equal("NotFoundException") err["Message"].should.equal("Invalid API identifier specified unknown") @mock_apigatewayv2 def test_get_api(): client = boto3.client("apigatewayv2", region_name="ap-southeast-1") api_id = client.create_api(Name="test-get-api", ProtocolType="WEBSOCKET")["ApiId"] resp = client.get_api(ApiId=api_id) resp.should.have.key("ApiId").equals(api_id) resp.should.have.key("ApiEndpoint").equals( f"https://{resp['ApiId']}.execute-api.ap-southeast-1.amazonaws.com" ) resp.should.have.key("ApiKeySelectionExpression").equals( "$request.header.x-api-key" ) resp.should.have.key("CreatedDate") resp.should.have.key("DisableExecuteApiEndpoint").equals(False) resp.should.have.key("Name").equals("test-get-api") resp.should.have.key("ProtocolType").equals("WEBSOCKET") resp.should.have.key("RouteSelectionExpression").equals( "$request.method $request.path" ) @mock_apigatewayv2 def test_get_apis(): client = boto3.client("apigatewayv2", region_name="ap-southeast-1") client.get_apis().should.have.key("Items").length_of(0) api_id_1 = client.create_api(Name="api1", ProtocolType="HTTP")["ApiId"] api_id_2 = client.create_api(Name="api2", ProtocolType="WEBSOCKET")["ApiId"] client.get_apis().should.have.key("Items").length_of(2) api_ids = [i["ApiId"] for i in client.get_apis()["Items"]] api_ids.should.contain(api_id_1) api_ids.should.contain(api_id_2) @mock_apigatewayv2 def test_update_api_minimal(): client = boto3.client("apigatewayv2", region_name="eu-west-1") api_id = client.create_api( ApiKeySelectionExpression="s3l3ction", CorsConfiguration={ "AllowCredentials": True, "AllowHeaders": ["x-header1"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header1"], "MaxAge": 2, }, Description="my first api", DisableSchemaValidation=True, DisableExecuteApiEndpoint=True, Name="test-api", ProtocolType="HTTP", RouteSelectionExpression="route_s3l3ction", Version="1.0", )["ApiId"] resp = client.update_api( ApiId=api_id, CorsConfiguration={ "AllowCredentials": False, "AllowHeaders": ["x-header2"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header2"], "MaxAge": 2, }, ) resp.should.have.key("ApiId") resp.should.have.key("ApiEndpoint").equals( f"https://{resp['ApiId']}.execute-api.eu-west-1.amazonaws.com" ) resp.should.have.key("ApiKeySelectionExpression").equals("s3l3ction") resp.should.have.key("CreatedDate") resp.should.have.key("CorsConfiguration").equals( { "AllowCredentials": False, "AllowHeaders": ["x-header2"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header2"], "MaxAge": 2, } ) resp.should.have.key("Description").equals("my first api") resp.should.have.key("DisableExecuteApiEndpoint").equals(True) resp.should.have.key("DisableSchemaValidation").equals(True) resp.should.have.key("Name").equals("test-api") resp.should.have.key("ProtocolType").equals("HTTP") resp.should.have.key("RouteSelectionExpression").equals("route_s3l3ction") resp.should.have.key("Version").equals("1.0") @mock_apigatewayv2 def test_update_api_empty_fields(): client = boto3.client("apigatewayv2", region_name="eu-west-1") api_id = client.create_api( ApiKeySelectionExpression="s3l3ction", CorsConfiguration={ "AllowCredentials": True, "AllowHeaders": ["x-header1"], "AllowMethods": ["GET", "PUT"], "AllowOrigins": ["google.com"], "ExposeHeaders": ["x-header1"], "MaxAge": 2, }, Description="my first api", DisableSchemaValidation=True, DisableExecuteApiEndpoint=True, Name="test-api", ProtocolType="HTTP", RouteSelectionExpression="route_s3l3ction", Version="1.0", )["ApiId"] resp = client.update_api(ApiId=api_id, Description="", Name="updated", Version="") resp.should.have.key("ApiId") resp.should.have.key("ApiEndpoint").equals( f"https://{resp['ApiId']}.execute-api.eu-west-1.amazonaws.com" ) resp.should.have.key("ApiKeySelectionExpression").equals("s3l3ction") resp.should.have.key("Description").equals("") resp.should.have.key("DisableExecuteApiEndpoint").equals(True) resp.should.have.key("DisableSchemaValidation").equals(True) resp.should.have.key("Name").equals("updated") resp.should.have.key("ProtocolType").equals("HTTP") resp.should.have.key("RouteSelectionExpression").equals("route_s3l3ction") resp.should.have.key("Version").equals("") @mock_apigatewayv2 def test_update_api(): client = boto3.client("apigatewayv2", region_name="us-east-2") api_id = client.create_api(Name="test-api", ProtocolType="HTTP")["ApiId"] resp = client.update_api( ApiId=api_id, ApiKeySelectionExpression="api_key_s3l3ction", CorsConfiguration={ "AllowCredentials": True, "AllowHeaders": ["X-Amz-Target"], "AllowMethods": ["GET"], }, CredentialsArn="credentials:arn", Description="updated API", DisableSchemaValidation=True, DisableExecuteApiEndpoint=True, Name="new name", RouteKey="route key", RouteSelectionExpression="route_s3l3ction", Target="updated target", Version="1.1", ) resp.should.have.key("ApiId") resp.should.have.key("ApiEndpoint").equals( f"https://{resp['ApiId']}.execute-api.us-east-2.amazonaws.com" ) resp.should.have.key("ApiKeySelectionExpression").equals("api_key_s3l3ction") resp.should.have.key("CorsConfiguration").equals( { "AllowCredentials": True, "AllowHeaders": ["X-Amz-Target"], "AllowMethods": ["GET"], } ) resp.should.have.key("CreatedDate") resp.should.have.key("Description").equals("updated API") resp.should.have.key("DisableSchemaValidation").equals(True) resp.should.have.key("DisableExecuteApiEndpoint").equals(True) resp.should.have.key("Name").equals("new name") resp.should.have.key("ProtocolType").equals("HTTP") resp.should.have.key("RouteSelectionExpression").equals("route_s3l3ction") resp.should.have.key("Version").equals("1.1")

35.96319

86

0.646196

1,271

11,724

5.86546

0.116444

0.062911

0.115091

0.145942

0.85285

0.837961

0.786586

0.772636

0.725687

0.671227

0

0.014141

0.191743

11,724

325

87

36.073846

0.772583

0.020471

0

0.681004

0

0.295251

0.051068

0

1

0.039427

false

0

0.017921

0

0.057348

0

null

0

1

0

null

0

6

d6df54eee7ede2f41d95836737f690f0ceb85810

42

py

Python

cloudman/__init__.py

aakashns/cloudman

5923152162151661397408de80783a80ffd8bb09

[ "MIT" ]

10

2019-07-06T08:49:41.000Z

2020-01-16T06:30:28.000Z

cloudman/__init__.py

aakashns/cloudman

5923152162151661397408de80783a80ffd8bb09

[ "MIT" ]

2

2019-11-12T11:53:27.000Z

2019-11-12T11:55:30.000Z

cloudman/__init__.py

aakashns/cloudman

5923152162151661397408de80783a80ffd8bb09

[ "MIT" ]

null

from cloudman._version import __version__

21

41

0.880952

5

42

6.4

0.8

0

0.095238

42

1

42

0.842105

0

1

0

true

0

1

0

1

0

1

0

null

0

1

0

null

0

1

0

1

0

1

0

6

ba9dbfcb61740474299dbdec881df5ead6bcd06d

45

py

Python

framework/framework/execute/__init__.py

StepaTa/vkbottle

3b04a5343380cbabe782151e7cb1c1645a9fa9ce

[ "MIT" ]

null

framework/framework/execute/__init__.py

StepaTa/vkbottle

3b04a5343380cbabe782151e7cb1c1645a9fa9ce

[ "MIT" ]

null

framework/framework/execute/__init__.py

StepaTa/vkbottle

3b04a5343380cbabe782151e7cb1c1645a9fa9ce

[ "MIT" ]

null

from .definitions import converter, vkscript

22.5

44

0.844444

5

45

7.6

1

0

0.111111

45

1

45

0.95

0

1

0

true

0

1

0

1

0

1

0

null

0

1

0

null

0

1

0

1

0

1

0

6

baaf7471c93dc4e4c3b5102d4ac16e244867fb72

536,768

py

Python

examples_obsolete/dataflow_fftN/test_dataflow_fftN.py

akmaru/veriloggen

74f998139e8cf613f7703fa4cffd571bbf069bbc

[ "Apache-2.0" ]

232

2015-09-01T16:07:48.000Z

2022-03-28T14:53:28.000Z

examples_obsolete/dataflow_fftN/test_dataflow_fftN.py

akmaru/veriloggen

74f998139e8cf613f7703fa4cffd571bbf069bbc

[ "Apache-2.0" ]

34

2015-08-21T09:13:03.000Z

2022-03-21T23:52:44.000Z

examples_obsolete/dataflow_fftN/test_dataflow_fftN.py

akmaru/veriloggen

74f998139e8cf613f7703fa4cffd571bbf069bbc

[ "Apache-2.0" ]

46

2015-09-24T14:39:57.000Z

2022-02-23T21:59:56.000Z

from __future__ import absolute_import from __future__ import print_function import veriloggen import dataflow_fftN expected_verilog = """ module test ( ); reg CLK; reg RST; reg signed [16-1:0] din0re; reg signed [16-1:0] din0im; reg signed [16-1:0] din1re; reg signed [16-1:0] din1im; reg signed [16-1:0] din2re; reg signed [16-1:0] din2im; reg signed [16-1:0] din3re; reg signed [16-1:0] din3im; reg signed [16-1:0] din4re; reg signed [16-1:0] din4im; reg signed [16-1:0] din5re; reg signed [16-1:0] din5im; reg signed [16-1:0] din6re; reg signed [16-1:0] din6im; reg signed [16-1:0] din7re; reg signed [16-1:0] din7im; reg signed [16-1:0] weight0re; reg signed [16-1:0] weight0im; reg signed [16-1:0] weight1re; reg signed [16-1:0] weight1im; reg signed [16-1:0] weight2re; reg signed [16-1:0] weight2im; reg signed [16-1:0] weight3re; reg signed [16-1:0] weight3im; reg signed [16-1:0] weight4re; reg signed [16-1:0] weight4im; reg signed [16-1:0] weight5re; reg signed [16-1:0] weight5im; reg signed [16-1:0] weight6re; reg signed [16-1:0] weight6im; reg signed [16-1:0] weight7re; reg signed [16-1:0] weight7im; reg signed [16-1:0] weight8re; reg signed [16-1:0] weight8im; reg signed [16-1:0] weight9re; reg signed [16-1:0] weight9im; reg signed [16-1:0] weight10re; reg signed [16-1:0] weight10im; reg signed [16-1:0] weight11re; reg signed [16-1:0] weight11im; wire signed [16-1:0] dout7re; wire signed [16-1:0] dout7im; wire signed [16-1:0] dout0re; wire signed [16-1:0] dout0im; wire signed [16-1:0] dout4re; wire signed [16-1:0] dout4im; wire signed [16-1:0] dout2re; wire signed [16-1:0] dout2im; wire signed [16-1:0] dout6re; wire signed [16-1:0] dout6im; wire signed [16-1:0] dout1re; wire signed [16-1:0] dout1im; wire signed [16-1:0] dout5re; wire signed [16-1:0] dout5im; wire signed [16-1:0] dout3re; wire signed [16-1:0] dout3im; wire signed [8-1:0] _din0re; wire signed [8-1:0] _din0im; wire signed [8-1:0] _din1re; wire signed [8-1:0] _din1im; wire signed [8-1:0] _din2re; wire signed [8-1:0] _din2im; wire signed [8-1:0] _din3re; wire signed [8-1:0] _din3im; wire signed [8-1:0] _din4re; wire signed [8-1:0] _din4im; wire signed [8-1:0] _din5re; wire signed [8-1:0] _din5im; wire signed [8-1:0] _din6re; wire signed [8-1:0] _din6im; wire signed [8-1:0] _din7re; wire signed [8-1:0] _din7im; wire signed [8-1:0] _dout0re; wire signed [8-1:0] _dout0im; wire signed [8-1:0] _dout1re; wire signed [8-1:0] _dout1im; wire signed [8-1:0] _dout2re; wire signed [8-1:0] _dout2im; wire signed [8-1:0] _dout3re; wire signed [8-1:0] _dout3im; wire signed [8-1:0] _dout4re; wire signed [8-1:0] _dout4im; wire signed [8-1:0] _dout5re; wire signed [8-1:0] _dout5im; wire signed [8-1:0] _dout6re; wire signed [8-1:0] _dout6im; wire signed [8-1:0] _dout7re; wire signed [8-1:0] _dout7im; wire signed [8-1:0] _weight0re; wire signed [8-1:0] _weight0im; wire signed [8-1:0] _weight1re; wire signed [8-1:0] _weight1im; wire signed [8-1:0] _weight2re; wire signed [8-1:0] _weight2im; wire signed [8-1:0] _weight3re; wire signed [8-1:0] _weight3im; wire signed [8-1:0] _weight4re; wire signed [8-1:0] _weight4im; wire signed [8-1:0] _weight5re; wire signed [8-1:0] _weight5im; wire signed [8-1:0] _weight6re; wire signed [8-1:0] _weight6im; wire signed [8-1:0] _weight7re; wire signed [8-1:0] _weight7im; wire signed [8-1:0] _weight8re; wire signed [8-1:0] _weight8im; wire signed [8-1:0] _weight9re; wire signed [8-1:0] _weight9im; wire signed [8-1:0] _weight10re; wire signed [8-1:0] _weight10im; wire signed [8-1:0] _weight11re; wire signed [8-1:0] _weight11im; assign _din0re = din0re >>> 8; assign _din0im = din0im >>> 8; assign _din1re = din1re >>> 8; assign _din1im = din1im >>> 8; assign _din2re = din2re >>> 8; assign _din2im = din2im >>> 8; assign _din3re = din3re >>> 8; assign _din3im = din3im >>> 8; assign _din4re = din4re >>> 8; assign _din4im = din4im >>> 8; assign _din5re = din5re >>> 8; assign _din5im = din5im >>> 8; assign _din6re = din6re >>> 8; assign _din6im = din6im >>> 8; assign _din7re = din7re >>> 8; assign _din7im = din7im >>> 8; assign _dout0re = dout0re >>> 8; assign _dout0im = dout0im >>> 8; assign _dout1re = dout1re >>> 8; assign _dout1im = dout1im >>> 8; assign _dout2re = dout2re >>> 8; assign _dout2im = dout2im >>> 8; assign _dout3re = dout3re >>> 8; assign _dout3im = dout3im >>> 8; assign _dout4re = dout4re >>> 8; assign _dout4im = dout4im >>> 8; assign _dout5re = dout5re >>> 8; assign _dout5im = dout5im >>> 8; assign _dout6re = dout6re >>> 8; assign _dout6im = dout6im >>> 8; assign _dout7re = dout7re >>> 8; assign _dout7im = dout7im >>> 8; assign _weight0re = weight0re >>> 8; assign _weight0im = weight0im >>> 8; assign _weight1re = weight1re >>> 8; assign _weight1im = weight1im >>> 8; assign _weight2re = weight2re >>> 8; assign _weight2im = weight2im >>> 8; assign _weight3re = weight3re >>> 8; assign _weight3im = weight3im >>> 8; assign _weight4re = weight4re >>> 8; assign _weight4im = weight4im >>> 8; assign _weight5re = weight5re >>> 8; assign _weight5im = weight5im >>> 8; assign _weight6re = weight6re >>> 8; assign _weight6im = weight6im >>> 8; assign _weight7re = weight7re >>> 8; assign _weight7im = weight7im >>> 8; assign _weight8re = weight8re >>> 8; assign _weight8im = weight8im >>> 8; assign _weight9re = weight9re >>> 8; assign _weight9im = weight9im >>> 8; assign _weight10re = weight10re >>> 8; assign _weight10im = weight10im >>> 8; assign _weight11re = weight11re >>> 8; assign _weight11im = weight11im >>> 8; fft uut ( .CLK(CLK), .RST(RST), .din0re(din0re), .din0im(din0im), .din1re(din1re), .din1im(din1im), .din2re(din2re), .din2im(din2im), .din3re(din3re), .din3im(din3im), .din4re(din4re), .din4im(din4im), .din5re(din5re), .din5im(din5im), .din6re(din6re), .din6im(din6im), .din7re(din7re), .din7im(din7im), .weight0re(weight0re), .weight0im(weight0im), .weight1re(weight1re), .weight1im(weight1im), .weight2re(weight2re), .weight2im(weight2im), .weight3re(weight3re), .weight3im(weight3im), .weight4re(weight4re), .weight4im(weight4im), .weight5re(weight5re), .weight5im(weight5im), .weight6re(weight6re), .weight6im(weight6im), .weight7re(weight7re), .weight7im(weight7im), .weight8re(weight8re), .weight8im(weight8im), .weight9re(weight9re), .weight9im(weight9im), .weight10re(weight10re), .weight10im(weight10im), .weight11re(weight11re), .weight11im(weight11im), .dout7re(dout7re), .dout7im(dout7im), .dout0re(dout0re), .dout0im(dout0im), .dout4re(dout4re), .dout4im(dout4im), .dout2re(dout2re), .dout2im(dout2im), .dout6re(dout6re), .dout6im(dout6im), .dout1re(dout1re), .dout1im(dout1im), .dout5re(dout5re), .dout5im(dout5im), .dout3re(dout3re), .dout3im(dout3im) ); reg reset_done; initial begin $dumpfile("uut.vcd"); $dumpvars(0, uut, _din0re, _din0im, _din1re, _din1im, _din2re, _din2im, _din3re, _din3im, _din4re, _din4im, _din5re, _din5im, _din6re, _din6im, _din7re, _din7im, _dout0re, _dout0im, _dout1re, _dout1im, _dout2re, _dout2im, _dout3re, _dout3im, _dout4re, _dout4im, _dout5re, _dout5im, _dout6re, _dout6im, _dout7re, _dout7im, _weight0re, _weight0im, _weight1re, _weight1im, _weight2re, _weight2im, _weight3re, _weight3im, _weight4re, _weight4im, _weight5re, _weight5im, _weight6re, _weight6im, _weight7re, _weight7im, _weight8re, _weight8im, _weight9re, _weight9im, _weight10re, _weight10im, _weight11re, _weight11im); end initial begin CLK = 0; forever begin #5 CLK = !CLK; end end initial begin RST = 0; reset_done = 0; din0re = 0; din0im = 0; din1re = 256; din1im = 256; din2re = 512; din2im = 512; din3re = 768; din3im = 768; din4re = 1024; din4im = 1024; din5re = 1280; din5im = 1280; din6re = 1536; din6im = 1536; din7re = 1792; din7im = 1792; weight0re = 256; weight0im = 0; weight1re = 181; weight1im = -181; weight2re = 0; weight2im = -256; weight3re = -181; weight3im = -181; weight4re = 256; weight4im = 0; weight5re = 0; weight5im = -256; weight6re = 256; weight6im = 0; weight7re = 0; weight7im = -256; weight8re = 256; weight8im = 0; weight9re = 256; weight9im = 0; weight10re = 256; weight10im = 0; weight11re = 256; weight11im = 0; #100; RST = 1; #100; RST = 0; #1000; reset_done = 1; @(posedge CLK); #1; #10000; $finish; end reg [32-1:0] send_fsm; localparam send_fsm_init = 0; localparam send_fsm_1 = 1; localparam send_fsm_2 = 2; localparam send_fsm_3 = 3; localparam send_fsm_4 = 4; localparam send_fsm_5 = 5; localparam send_fsm_6 = 6; localparam send_fsm_7 = 7; localparam send_fsm_8 = 8; localparam send_fsm_9 = 9; localparam send_fsm_10 = 10; localparam send_fsm_11 = 11; localparam send_fsm_12 = 12; localparam send_fsm_13 = 13; localparam send_fsm_14 = 14; localparam send_fsm_15 = 15; localparam send_fsm_16 = 16; localparam send_fsm_17 = 17; localparam send_fsm_18 = 18; localparam send_fsm_19 = 19; localparam send_fsm_20 = 20; localparam send_fsm_21 = 21; localparam send_fsm_22 = 22; localparam send_fsm_23 = 23; localparam send_fsm_24 = 24; localparam send_fsm_25 = 25; localparam send_fsm_26 = 26; localparam send_fsm_27 = 27; localparam send_fsm_28 = 28; localparam send_fsm_29 = 29; localparam send_fsm_30 = 30; localparam send_fsm_31 = 31; localparam send_fsm_32 = 32; localparam send_fsm_33 = 33; localparam send_fsm_34 = 34; localparam send_fsm_35 = 35; localparam send_fsm_36 = 36; localparam send_fsm_37 = 37; localparam send_fsm_38 = 38; localparam send_fsm_39 = 39; localparam send_fsm_40 = 40; localparam send_fsm_41 = 41; localparam send_fsm_42 = 42; localparam send_fsm_43 = 43; localparam send_fsm_44 = 44; localparam send_fsm_45 = 45; localparam send_fsm_46 = 46; localparam send_fsm_47 = 47; localparam send_fsm_48 = 48; localparam send_fsm_49 = 49; localparam send_fsm_50 = 50; localparam send_fsm_51 = 51; localparam send_fsm_52 = 52; localparam send_fsm_53 = 53; localparam send_fsm_54 = 54; localparam send_fsm_55 = 55; localparam send_fsm_56 = 56; localparam send_fsm_57 = 57; localparam send_fsm_58 = 58; localparam send_fsm_59 = 59; localparam send_fsm_60 = 60; localparam send_fsm_61 = 61; localparam send_fsm_62 = 62; localparam send_fsm_63 = 63; localparam send_fsm_64 = 64; localparam send_fsm_65 = 65; localparam send_fsm_66 = 66; localparam send_fsm_67 = 67; localparam send_fsm_68 = 68; localparam send_fsm_69 = 69; localparam send_fsm_70 = 70; localparam send_fsm_71 = 71; localparam send_fsm_72 = 72; localparam send_fsm_73 = 73; localparam send_fsm_74 = 74; localparam send_fsm_75 = 75; localparam send_fsm_76 = 76; localparam send_fsm_77 = 77; localparam send_fsm_78 = 78; localparam send_fsm_79 = 79; localparam send_fsm_80 = 80; localparam send_fsm_81 = 81; localparam send_fsm_82 = 82; localparam send_fsm_83 = 83; localparam send_fsm_84 = 84; localparam send_fsm_85 = 85; localparam send_fsm_86 = 86; localparam send_fsm_87 = 87; localparam send_fsm_88 = 88; localparam send_fsm_89 = 89; localparam send_fsm_90 = 90; localparam send_fsm_91 = 91; localparam send_fsm_92 = 92; localparam send_fsm_93 = 93; localparam send_fsm_94 = 94; localparam send_fsm_95 = 95; localparam send_fsm_96 = 96; localparam send_fsm_97 = 97; localparam send_fsm_98 = 98; localparam send_fsm_99 = 99; localparam send_fsm_100 = 100; localparam send_fsm_101 = 101; localparam send_fsm_102 = 102; localparam send_fsm_103 = 103; always @(posedge CLK) begin if(RST) begin send_fsm <= send_fsm_init; end else begin case(send_fsm) send_fsm_init: begin if(reset_done) begin send_fsm <= send_fsm_1; end end send_fsm_1: begin din0re <= 0; din0im <= 0; din1re <= 256; din1im <= 256; din2re <= 512; din2im <= 512; din3re <= 768; din3im <= 768; din4re <= 1024; din4im <= 1024; din5re <= 1280; din5im <= 1280; din6re <= 1536; din6im <= 1536; din7re <= 1792; din7im <= 1792; send_fsm <= send_fsm_2; end send_fsm_2: begin din0re <= 0; din0im <= 0; din1re <= 0; din1im <= 0; din2re <= 0; din2im <= 0; din3re <= 0; din3im <= 0; din4re <= 0; din4im <= 0; din5re <= 0; din5im <= 0; din6re <= 0; din6im <= 0; din7re <= 0; din7im <= 0; send_fsm <= send_fsm_3; end send_fsm_3: begin send_fsm <= send_fsm_4; end send_fsm_4: begin send_fsm <= send_fsm_5; end send_fsm_5: begin send_fsm <= send_fsm_6; end send_fsm_6: begin send_fsm <= send_fsm_7; end send_fsm_7: begin send_fsm <= send_fsm_8; end send_fsm_8: begin send_fsm <= send_fsm_9; end send_fsm_9: begin send_fsm <= send_fsm_10; end send_fsm_10: begin send_fsm <= send_fsm_11; end send_fsm_11: begin send_fsm <= send_fsm_12; end send_fsm_12: begin send_fsm <= send_fsm_13; end send_fsm_13: begin send_fsm <= send_fsm_14; end send_fsm_14: begin send_fsm <= send_fsm_15; end send_fsm_15: begin send_fsm <= send_fsm_16; end send_fsm_16: begin send_fsm <= send_fsm_17; end send_fsm_17: begin send_fsm <= send_fsm_18; end send_fsm_18: begin send_fsm <= send_fsm_19; end send_fsm_19: begin send_fsm <= send_fsm_20; end send_fsm_20: begin send_fsm <= send_fsm_21; end send_fsm_21: begin send_fsm <= send_fsm_22; end send_fsm_22: begin send_fsm <= send_fsm_23; end send_fsm_23: begin send_fsm <= send_fsm_24; end send_fsm_24: begin send_fsm <= send_fsm_25; end send_fsm_25: begin send_fsm <= send_fsm_26; end send_fsm_26: begin send_fsm <= send_fsm_27; end send_fsm_27: begin send_fsm <= send_fsm_28; end send_fsm_28: begin send_fsm <= send_fsm_29; end send_fsm_29: begin send_fsm <= send_fsm_30; end send_fsm_30: begin send_fsm <= send_fsm_31; end send_fsm_31: begin send_fsm <= send_fsm_32; end send_fsm_32: begin send_fsm <= send_fsm_33; end send_fsm_33: begin send_fsm <= send_fsm_34; end send_fsm_34: begin send_fsm <= send_fsm_35; end send_fsm_35: begin send_fsm <= send_fsm_36; end send_fsm_36: begin send_fsm <= send_fsm_37; end send_fsm_37: begin send_fsm <= send_fsm_38; end send_fsm_38: begin send_fsm <= send_fsm_39; end send_fsm_39: begin send_fsm <= send_fsm_40; end send_fsm_40: begin send_fsm <= send_fsm_41; end send_fsm_41: begin send_fsm <= send_fsm_42; end send_fsm_42: begin send_fsm <= send_fsm_43; end send_fsm_43: begin send_fsm <= send_fsm_44; end send_fsm_44: begin send_fsm <= send_fsm_45; end send_fsm_45: begin send_fsm <= send_fsm_46; end send_fsm_46: begin send_fsm <= send_fsm_47; end send_fsm_47: begin send_fsm <= send_fsm_48; end send_fsm_48: begin send_fsm <= send_fsm_49; end send_fsm_49: begin send_fsm <= send_fsm_50; end send_fsm_50: begin send_fsm <= send_fsm_51; end send_fsm_51: begin send_fsm <= send_fsm_52; end send_fsm_52: begin send_fsm <= send_fsm_53; end send_fsm_53: begin send_fsm <= send_fsm_54; end send_fsm_54: begin send_fsm <= send_fsm_55; end send_fsm_55: begin send_fsm <= send_fsm_56; end send_fsm_56: begin send_fsm <= send_fsm_57; end send_fsm_57: begin send_fsm <= send_fsm_58; end send_fsm_58: begin send_fsm <= send_fsm_59; end send_fsm_59: begin send_fsm <= send_fsm_60; end send_fsm_60: begin send_fsm <= send_fsm_61; end send_fsm_61: begin send_fsm <= send_fsm_62; end send_fsm_62: begin send_fsm <= send_fsm_63; end send_fsm_63: begin send_fsm <= send_fsm_64; end send_fsm_64: begin send_fsm <= send_fsm_65; end send_fsm_65: begin send_fsm <= send_fsm_66; end send_fsm_66: begin send_fsm <= send_fsm_67; end send_fsm_67: begin send_fsm <= send_fsm_68; end send_fsm_68: begin send_fsm <= send_fsm_69; end send_fsm_69: begin send_fsm <= send_fsm_70; end send_fsm_70: begin send_fsm <= send_fsm_71; end send_fsm_71: begin send_fsm <= send_fsm_72; end send_fsm_72: begin send_fsm <= send_fsm_73; end send_fsm_73: begin send_fsm <= send_fsm_74; end send_fsm_74: begin send_fsm <= send_fsm_75; end send_fsm_75: begin send_fsm <= send_fsm_76; end send_fsm_76: begin send_fsm <= send_fsm_77; end send_fsm_77: begin send_fsm <= send_fsm_78; end send_fsm_78: begin send_fsm <= send_fsm_79; end send_fsm_79: begin send_fsm <= send_fsm_80; end send_fsm_80: begin send_fsm <= send_fsm_81; end send_fsm_81: begin send_fsm <= send_fsm_82; end send_fsm_82: begin send_fsm <= send_fsm_83; end send_fsm_83: begin send_fsm <= send_fsm_84; end send_fsm_84: begin send_fsm <= send_fsm_85; end send_fsm_85: begin send_fsm <= send_fsm_86; end send_fsm_86: begin send_fsm <= send_fsm_87; end send_fsm_87: begin send_fsm <= send_fsm_88; end send_fsm_88: begin send_fsm <= send_fsm_89; end send_fsm_89: begin send_fsm <= send_fsm_90; end send_fsm_90: begin send_fsm <= send_fsm_91; end send_fsm_91: begin send_fsm <= send_fsm_92; end send_fsm_92: begin send_fsm <= send_fsm_93; end send_fsm_93: begin send_fsm <= send_fsm_94; end send_fsm_94: begin send_fsm <= send_fsm_95; end send_fsm_95: begin send_fsm <= send_fsm_96; end send_fsm_96: begin send_fsm <= send_fsm_97; end send_fsm_97: begin send_fsm <= send_fsm_98; end send_fsm_98: begin send_fsm <= send_fsm_99; end send_fsm_99: begin send_fsm <= send_fsm_100; end send_fsm_100: begin send_fsm <= send_fsm_101; end send_fsm_101: begin send_fsm <= send_fsm_102; end send_fsm_102: begin send_fsm <= send_fsm_103; end send_fsm_103: begin $finish; end endcase end end endmodule module fft ( input CLK, input RST, input signed [16-1:0] din0re, input signed [16-1:0] din0im, input signed [16-1:0] din1re, input signed [16-1:0] din1im, input signed [16-1:0] din2re, input signed [16-1:0] din2im, input signed [16-1:0] din3re, input signed [16-1:0] din3im, input signed [16-1:0] din4re, input signed [16-1:0] din4im, input signed [16-1:0] din5re, input signed [16-1:0] din5im, input signed [16-1:0] din6re, input signed [16-1:0] din6im, input signed [16-1:0] din7re, input signed [16-1:0] din7im, input signed [16-1:0] weight0re, input signed [16-1:0] weight0im, input signed [16-1:0] weight1re, input signed [16-1:0] weight1im, input signed [16-1:0] weight2re, input signed [16-1:0] weight2im, input signed [16-1:0] weight3re, input signed [16-1:0] weight3im, input signed [16-1:0] weight4re, input signed [16-1:0] weight4im, input signed [16-1:0] weight5re, input signed [16-1:0] weight5im, input signed [16-1:0] weight6re, input signed [16-1:0] weight6im, input signed [16-1:0] weight7re, input signed [16-1:0] weight7im, input signed [16-1:0] weight8re, input signed [16-1:0] weight8im, input signed [16-1:0] weight9re, input signed [16-1:0] weight9im, input signed [16-1:0] weight10re, input signed [16-1:0] weight10im, input signed [16-1:0] weight11re, input signed [16-1:0] weight11im, output signed [16-1:0] dout7re, output signed [16-1:0] dout7im, output signed [16-1:0] dout0re, output signed [16-1:0] dout0im, output signed [16-1:0] dout4re, output signed [16-1:0] dout4im, output signed [16-1:0] dout2re, output signed [16-1:0] dout2im, output signed [16-1:0] dout6re, output signed [16-1:0] dout6im, output signed [16-1:0] dout1re, output signed [16-1:0] dout1im, output signed [16-1:0] dout5re, output signed [16-1:0] dout5im, output signed [16-1:0] dout3re, output signed [16-1:0] dout3im ); reg signed [16-1:0] _dataflow_plus_data_40; reg _dataflow_plus_valid_40; wire _dataflow_plus_ready_40; reg signed [16-1:0] _dataflow_plus_data_41; reg _dataflow_plus_valid_41; wire _dataflow_plus_ready_41; reg signed [16-1:0] _dataflow_minus_data_42; reg _dataflow_minus_valid_42; wire _dataflow_minus_ready_42; reg signed [16-1:0] _dataflow_minus_data_43; reg _dataflow_minus_valid_43; wire _dataflow_minus_ready_43; reg signed [16-1:0] _dataflow_plus_data_50; reg _dataflow_plus_valid_50; wire _dataflow_plus_ready_50; reg signed [16-1:0] _dataflow_plus_data_51; reg _dataflow_plus_valid_51; wire _dataflow_plus_ready_51; reg signed [16-1:0] _dataflow_minus_data_52; reg _dataflow_minus_valid_52; wire _dataflow_minus_ready_52; reg signed [16-1:0] _dataflow_minus_data_53; reg _dataflow_minus_valid_53; wire _dataflow_minus_ready_53; reg signed [16-1:0] _dataflow_plus_data_60; reg _dataflow_plus_valid_60; wire _dataflow_plus_ready_60; reg signed [16-1:0] _dataflow_plus_data_61; reg _dataflow_plus_valid_61; wire _dataflow_plus_ready_61; reg signed [16-1:0] _dataflow_minus_data_62; reg _dataflow_minus_valid_62; wire _dataflow_minus_ready_62; reg signed [16-1:0] _dataflow_minus_data_63; reg _dataflow_minus_valid_63; wire _dataflow_minus_ready_63; reg signed [16-1:0] _dataflow_plus_data_70; reg _dataflow_plus_valid_70; wire _dataflow_plus_ready_70; reg signed [16-1:0] _dataflow_plus_data_71; reg _dataflow_plus_valid_71; wire _dataflow_plus_ready_71; reg signed [16-1:0] _dataflow_minus_data_72; reg _dataflow_minus_valid_72; wire _dataflow_minus_ready_72; reg signed [16-1:0] _dataflow_minus_data_73; reg _dataflow_minus_valid_73; wire _dataflow_minus_ready_73; reg signed [16-1:0] _dataflow__delay_data_160; reg _dataflow__delay_valid_160; wire _dataflow__delay_ready_160; reg signed [16-1:0] _dataflow__delay_data_163; reg _dataflow__delay_valid_163; wire _dataflow__delay_ready_163; reg signed [16-1:0] _dataflow__delay_data_166; reg _dataflow__delay_valid_166; wire _dataflow__delay_ready_166; reg signed [16-1:0] _dataflow__delay_data_168; reg _dataflow__delay_valid_168; wire _dataflow__delay_ready_168; reg signed [16-1:0] _dataflow__delay_data_170; reg _dataflow__delay_valid_170; wire _dataflow__delay_ready_170; reg signed [16-1:0] _dataflow__delay_data_172; reg _dataflow__delay_valid_172; wire _dataflow__delay_ready_172; reg signed [16-1:0] _dataflow__delay_data_174; reg _dataflow__delay_valid_174; wire _dataflow__delay_ready_174; reg signed [16-1:0] _dataflow__delay_data_185; reg _dataflow__delay_valid_185; wire _dataflow__delay_ready_185; reg signed [16-1:0] _dataflow__delay_data_196; reg _dataflow__delay_valid_196; wire _dataflow__delay_ready_196; reg signed [16-1:0] _dataflow__delay_data_197; reg _dataflow__delay_valid_197; wire _dataflow__delay_ready_197; reg signed [16-1:0] _dataflow__delay_data_198; reg _dataflow__delay_valid_198; wire _dataflow__delay_ready_198; reg signed [16-1:0] _dataflow__delay_data_199; reg _dataflow__delay_valid_199; wire _dataflow__delay_ready_199; reg signed [16-1:0] _dataflow__delay_data_200; reg _dataflow__delay_valid_200; wire _dataflow__delay_ready_200; reg signed [16-1:0] _dataflow__delay_data_201; reg _dataflow__delay_valid_201; wire _dataflow__delay_ready_201; reg signed [16-1:0] _dataflow__delay_data_202; reg _dataflow__delay_valid_202; wire _dataflow__delay_ready_202; reg signed [16-1:0] _dataflow__delay_data_203; reg _dataflow__delay_valid_203; wire _dataflow__delay_ready_203; reg signed [16-1:0] _dataflow__delay_data_204; reg _dataflow__delay_valid_204; wire _dataflow__delay_ready_204; reg signed [16-1:0] _dataflow__delay_data_215; reg _dataflow__delay_valid_215; wire _dataflow__delay_ready_215; reg signed [16-1:0] _dataflow__delay_data_226; reg _dataflow__delay_valid_226; wire _dataflow__delay_ready_226; reg signed [16-1:0] _dataflow__delay_data_236; reg _dataflow__delay_valid_236; wire _dataflow__delay_ready_236; reg signed [16-1:0] _dataflow__delay_data_246; reg _dataflow__delay_valid_246; wire _dataflow__delay_ready_246; reg signed [16-1:0] _dataflow__delay_data_256; reg _dataflow__delay_valid_256; wire _dataflow__delay_ready_256; reg signed [16-1:0] _dataflow__delay_data_266; reg _dataflow__delay_valid_266; wire _dataflow__delay_ready_266; reg signed [16-1:0] _dataflow__delay_data_285; reg _dataflow__delay_valid_285; wire _dataflow__delay_ready_285; wire signed [16-1:0] _dataflow_times_data_44; wire _dataflow_times_valid_44; wire _dataflow_times_ready_44; wire signed [32-1:0] _dataflow_times_mul_odata_44; reg signed [32-1:0] _dataflow_times_mul_odata_reg_44; assign _dataflow_times_data_44 = _dataflow_times_mul_odata_reg_44; wire _dataflow_times_mul_ovalid_44; reg _dataflow_times_mul_valid_reg_44; assign _dataflow_times_valid_44 = _dataflow_times_mul_valid_reg_44; wire _dataflow_times_mul_enable_44; wire _dataflow_times_mul_update_44; assign _dataflow_times_mul_enable_44 = (_dataflow_times_ready_44 || !_dataflow_times_valid_44) && (_dataflow_minus_ready_42 && _dataflow__delay_ready_196) && (_dataflow_minus_valid_42 && _dataflow__delay_valid_196); assign _dataflow_times_mul_update_44 = _dataflow_times_ready_44 || !_dataflow_times_valid_44; multiplier_0 _dataflow_times_mul_44 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_44), .enable(_dataflow_times_mul_enable_44), .valid(_dataflow_times_mul_ovalid_44), .a(_dataflow_minus_data_42), .b(_dataflow__delay_data_196), .c(_dataflow_times_mul_odata_44) ); wire signed [16-1:0] _dataflow_times_data_45; wire _dataflow_times_valid_45; wire _dataflow_times_ready_45; wire signed [32-1:0] _dataflow_times_mul_odata_45; reg signed [32-1:0] _dataflow_times_mul_odata_reg_45; assign _dataflow_times_data_45 = _dataflow_times_mul_odata_reg_45; wire _dataflow_times_mul_ovalid_45; reg _dataflow_times_mul_valid_reg_45; assign _dataflow_times_valid_45 = _dataflow_times_mul_valid_reg_45; wire _dataflow_times_mul_enable_45; wire _dataflow_times_mul_update_45; assign _dataflow_times_mul_enable_45 = (_dataflow_times_ready_45 || !_dataflow_times_valid_45) && (_dataflow_minus_ready_43 && _dataflow__delay_ready_197) && (_dataflow_minus_valid_43 && _dataflow__delay_valid_197); assign _dataflow_times_mul_update_45 = _dataflow_times_ready_45 || !_dataflow_times_valid_45; multiplier_1 _dataflow_times_mul_45 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_45), .enable(_dataflow_times_mul_enable_45), .valid(_dataflow_times_mul_ovalid_45), .a(_dataflow_minus_data_43), .b(_dataflow__delay_data_197), .c(_dataflow_times_mul_odata_45) ); wire signed [16-1:0] _dataflow_times_data_46; wire _dataflow_times_valid_46; wire _dataflow_times_ready_46; wire signed [32-1:0] _dataflow_times_mul_odata_46; reg signed [32-1:0] _dataflow_times_mul_odata_reg_46; assign _dataflow_times_data_46 = _dataflow_times_mul_odata_reg_46; wire _dataflow_times_mul_ovalid_46; reg _dataflow_times_mul_valid_reg_46; assign _dataflow_times_valid_46 = _dataflow_times_mul_valid_reg_46; wire _dataflow_times_mul_enable_46; wire _dataflow_times_mul_update_46; assign _dataflow_times_mul_enable_46 = (_dataflow_times_ready_46 || !_dataflow_times_valid_46) && (_dataflow_minus_ready_42 && _dataflow__delay_ready_197) && (_dataflow_minus_valid_42 && _dataflow__delay_valid_197); assign _dataflow_times_mul_update_46 = _dataflow_times_ready_46 || !_dataflow_times_valid_46; multiplier_2 _dataflow_times_mul_46 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_46), .enable(_dataflow_times_mul_enable_46), .valid(_dataflow_times_mul_ovalid_46), .a(_dataflow_minus_data_42), .b(_dataflow__delay_data_197), .c(_dataflow_times_mul_odata_46) ); assign _dataflow_minus_ready_42 = (_dataflow_times_ready_44 || !_dataflow_times_valid_44) && (_dataflow_minus_valid_42 && _dataflow__delay_valid_196) && ((_dataflow_times_ready_46 || !_dataflow_times_valid_46) && (_dataflow_minus_valid_42 && _dataflow__delay_valid_197)); assign _dataflow__delay_ready_197 = (_dataflow_times_ready_45 || !_dataflow_times_valid_45) && (_dataflow_minus_valid_43 && _dataflow__delay_valid_197) && ((_dataflow_times_ready_46 || !_dataflow_times_valid_46) && (_dataflow_minus_valid_42 && _dataflow__delay_valid_197)); wire signed [16-1:0] _dataflow_times_data_47; wire _dataflow_times_valid_47; wire _dataflow_times_ready_47; wire signed [32-1:0] _dataflow_times_mul_odata_47; reg signed [32-1:0] _dataflow_times_mul_odata_reg_47; assign _dataflow_times_data_47 = _dataflow_times_mul_odata_reg_47; wire _dataflow_times_mul_ovalid_47; reg _dataflow_times_mul_valid_reg_47; assign _dataflow_times_valid_47 = _dataflow_times_mul_valid_reg_47; wire _dataflow_times_mul_enable_47; wire _dataflow_times_mul_update_47; assign _dataflow_times_mul_enable_47 = (_dataflow_times_ready_47 || !_dataflow_times_valid_47) && (_dataflow_minus_ready_43 && _dataflow__delay_ready_196) && (_dataflow_minus_valid_43 && _dataflow__delay_valid_196); assign _dataflow_times_mul_update_47 = _dataflow_times_ready_47 || !_dataflow_times_valid_47; multiplier_3 _dataflow_times_mul_47 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_47), .enable(_dataflow_times_mul_enable_47), .valid(_dataflow_times_mul_ovalid_47), .a(_dataflow_minus_data_43), .b(_dataflow__delay_data_196), .c(_dataflow_times_mul_odata_47) ); assign _dataflow_minus_ready_43 = (_dataflow_times_ready_45 || !_dataflow_times_valid_45) && (_dataflow_minus_valid_43 && _dataflow__delay_valid_197) && ((_dataflow_times_ready_47 || !_dataflow_times_valid_47) && (_dataflow_minus_valid_43 && _dataflow__delay_valid_196)); assign _dataflow__delay_ready_196 = (_dataflow_times_ready_44 || !_dataflow_times_valid_44) && (_dataflow_minus_valid_42 && _dataflow__delay_valid_196) && ((_dataflow_times_ready_47 || !_dataflow_times_valid_47) && (_dataflow_minus_valid_43 && _dataflow__delay_valid_196)); wire signed [16-1:0] _dataflow_times_data_54; wire _dataflow_times_valid_54; wire _dataflow_times_ready_54; wire signed [32-1:0] _dataflow_times_mul_odata_54; reg signed [32-1:0] _dataflow_times_mul_odata_reg_54; assign _dataflow_times_data_54 = _dataflow_times_mul_odata_reg_54; wire _dataflow_times_mul_ovalid_54; reg _dataflow_times_mul_valid_reg_54; assign _dataflow_times_valid_54 = _dataflow_times_mul_valid_reg_54; wire _dataflow_times_mul_enable_54; wire _dataflow_times_mul_update_54; assign _dataflow_times_mul_enable_54 = (_dataflow_times_ready_54 || !_dataflow_times_valid_54) && (_dataflow_minus_ready_52 && _dataflow__delay_ready_200) && (_dataflow_minus_valid_52 && _dataflow__delay_valid_200); assign _dataflow_times_mul_update_54 = _dataflow_times_ready_54 || !_dataflow_times_valid_54; multiplier_4 _dataflow_times_mul_54 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_54), .enable(_dataflow_times_mul_enable_54), .valid(_dataflow_times_mul_ovalid_54), .a(_dataflow_minus_data_52), .b(_dataflow__delay_data_200), .c(_dataflow_times_mul_odata_54) ); wire signed [16-1:0] _dataflow_times_data_55; wire _dataflow_times_valid_55; wire _dataflow_times_ready_55; wire signed [32-1:0] _dataflow_times_mul_odata_55; reg signed [32-1:0] _dataflow_times_mul_odata_reg_55; assign _dataflow_times_data_55 = _dataflow_times_mul_odata_reg_55; wire _dataflow_times_mul_ovalid_55; reg _dataflow_times_mul_valid_reg_55; assign _dataflow_times_valid_55 = _dataflow_times_mul_valid_reg_55; wire _dataflow_times_mul_enable_55; wire _dataflow_times_mul_update_55; assign _dataflow_times_mul_enable_55 = (_dataflow_times_ready_55 || !_dataflow_times_valid_55) && (_dataflow_minus_ready_53 && _dataflow__delay_ready_201) && (_dataflow_minus_valid_53 && _dataflow__delay_valid_201); assign _dataflow_times_mul_update_55 = _dataflow_times_ready_55 || !_dataflow_times_valid_55; multiplier_5 _dataflow_times_mul_55 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_55), .enable(_dataflow_times_mul_enable_55), .valid(_dataflow_times_mul_ovalid_55), .a(_dataflow_minus_data_53), .b(_dataflow__delay_data_201), .c(_dataflow_times_mul_odata_55) ); wire signed [16-1:0] _dataflow_times_data_56; wire _dataflow_times_valid_56; wire _dataflow_times_ready_56; wire signed [32-1:0] _dataflow_times_mul_odata_56; reg signed [32-1:0] _dataflow_times_mul_odata_reg_56; assign _dataflow_times_data_56 = _dataflow_times_mul_odata_reg_56; wire _dataflow_times_mul_ovalid_56; reg _dataflow_times_mul_valid_reg_56; assign _dataflow_times_valid_56 = _dataflow_times_mul_valid_reg_56; wire _dataflow_times_mul_enable_56; wire _dataflow_times_mul_update_56; assign _dataflow_times_mul_enable_56 = (_dataflow_times_ready_56 || !_dataflow_times_valid_56) && (_dataflow_minus_ready_52 && _dataflow__delay_ready_201) && (_dataflow_minus_valid_52 && _dataflow__delay_valid_201); assign _dataflow_times_mul_update_56 = _dataflow_times_ready_56 || !_dataflow_times_valid_56; multiplier_6 _dataflow_times_mul_56 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_56), .enable(_dataflow_times_mul_enable_56), .valid(_dataflow_times_mul_ovalid_56), .a(_dataflow_minus_data_52), .b(_dataflow__delay_data_201), .c(_dataflow_times_mul_odata_56) ); assign _dataflow_minus_ready_52 = (_dataflow_times_ready_54 || !_dataflow_times_valid_54) && (_dataflow_minus_valid_52 && _dataflow__delay_valid_200) && ((_dataflow_times_ready_56 || !_dataflow_times_valid_56) && (_dataflow_minus_valid_52 && _dataflow__delay_valid_201)); assign _dataflow__delay_ready_201 = (_dataflow_times_ready_55 || !_dataflow_times_valid_55) && (_dataflow_minus_valid_53 && _dataflow__delay_valid_201) && ((_dataflow_times_ready_56 || !_dataflow_times_valid_56) && (_dataflow_minus_valid_52 && _dataflow__delay_valid_201)); wire signed [16-1:0] _dataflow_times_data_57; wire _dataflow_times_valid_57; wire _dataflow_times_ready_57; wire signed [32-1:0] _dataflow_times_mul_odata_57; reg signed [32-1:0] _dataflow_times_mul_odata_reg_57; assign _dataflow_times_data_57 = _dataflow_times_mul_odata_reg_57; wire _dataflow_times_mul_ovalid_57; reg _dataflow_times_mul_valid_reg_57; assign _dataflow_times_valid_57 = _dataflow_times_mul_valid_reg_57; wire _dataflow_times_mul_enable_57; wire _dataflow_times_mul_update_57; assign _dataflow_times_mul_enable_57 = (_dataflow_times_ready_57 || !_dataflow_times_valid_57) && (_dataflow_minus_ready_53 && _dataflow__delay_ready_200) && (_dataflow_minus_valid_53 && _dataflow__delay_valid_200); assign _dataflow_times_mul_update_57 = _dataflow_times_ready_57 || !_dataflow_times_valid_57; multiplier_7 _dataflow_times_mul_57 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_57), .enable(_dataflow_times_mul_enable_57), .valid(_dataflow_times_mul_ovalid_57), .a(_dataflow_minus_data_53), .b(_dataflow__delay_data_200), .c(_dataflow_times_mul_odata_57) ); assign _dataflow_minus_ready_53 = (_dataflow_times_ready_55 || !_dataflow_times_valid_55) && (_dataflow_minus_valid_53 && _dataflow__delay_valid_201) && ((_dataflow_times_ready_57 || !_dataflow_times_valid_57) && (_dataflow_minus_valid_53 && _dataflow__delay_valid_200)); assign _dataflow__delay_ready_200 = (_dataflow_times_ready_54 || !_dataflow_times_valid_54) && (_dataflow_minus_valid_52 && _dataflow__delay_valid_200) && ((_dataflow_times_ready_57 || !_dataflow_times_valid_57) && (_dataflow_minus_valid_53 && _dataflow__delay_valid_200)); wire signed [16-1:0] _dataflow_times_data_64; wire _dataflow_times_valid_64; wire _dataflow_times_ready_64; wire signed [32-1:0] _dataflow_times_mul_odata_64; reg signed [32-1:0] _dataflow_times_mul_odata_reg_64; assign _dataflow_times_data_64 = _dataflow_times_mul_odata_reg_64; wire _dataflow_times_mul_ovalid_64; reg _dataflow_times_mul_valid_reg_64; assign _dataflow_times_valid_64 = _dataflow_times_mul_valid_reg_64; wire _dataflow_times_mul_enable_64; wire _dataflow_times_mul_update_64; assign _dataflow_times_mul_enable_64 = (_dataflow_times_ready_64 || !_dataflow_times_valid_64) && (_dataflow_minus_ready_62 && _dataflow__delay_ready_198) && (_dataflow_minus_valid_62 && _dataflow__delay_valid_198); assign _dataflow_times_mul_update_64 = _dataflow_times_ready_64 || !_dataflow_times_valid_64; multiplier_8 _dataflow_times_mul_64 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_64), .enable(_dataflow_times_mul_enable_64), .valid(_dataflow_times_mul_ovalid_64), .a(_dataflow_minus_data_62), .b(_dataflow__delay_data_198), .c(_dataflow_times_mul_odata_64) ); wire signed [16-1:0] _dataflow_times_data_65; wire _dataflow_times_valid_65; wire _dataflow_times_ready_65; wire signed [32-1:0] _dataflow_times_mul_odata_65; reg signed [32-1:0] _dataflow_times_mul_odata_reg_65; assign _dataflow_times_data_65 = _dataflow_times_mul_odata_reg_65; wire _dataflow_times_mul_ovalid_65; reg _dataflow_times_mul_valid_reg_65; assign _dataflow_times_valid_65 = _dataflow_times_mul_valid_reg_65; wire _dataflow_times_mul_enable_65; wire _dataflow_times_mul_update_65; assign _dataflow_times_mul_enable_65 = (_dataflow_times_ready_65 || !_dataflow_times_valid_65) && (_dataflow_minus_ready_63 && _dataflow__delay_ready_199) && (_dataflow_minus_valid_63 && _dataflow__delay_valid_199); assign _dataflow_times_mul_update_65 = _dataflow_times_ready_65 || !_dataflow_times_valid_65; multiplier_9 _dataflow_times_mul_65 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_65), .enable(_dataflow_times_mul_enable_65), .valid(_dataflow_times_mul_ovalid_65), .a(_dataflow_minus_data_63), .b(_dataflow__delay_data_199), .c(_dataflow_times_mul_odata_65) ); wire signed [16-1:0] _dataflow_times_data_66; wire _dataflow_times_valid_66; wire _dataflow_times_ready_66; wire signed [32-1:0] _dataflow_times_mul_odata_66; reg signed [32-1:0] _dataflow_times_mul_odata_reg_66; assign _dataflow_times_data_66 = _dataflow_times_mul_odata_reg_66; wire _dataflow_times_mul_ovalid_66; reg _dataflow_times_mul_valid_reg_66; assign _dataflow_times_valid_66 = _dataflow_times_mul_valid_reg_66; wire _dataflow_times_mul_enable_66; wire _dataflow_times_mul_update_66; assign _dataflow_times_mul_enable_66 = (_dataflow_times_ready_66 || !_dataflow_times_valid_66) && (_dataflow_minus_ready_62 && _dataflow__delay_ready_199) && (_dataflow_minus_valid_62 && _dataflow__delay_valid_199); assign _dataflow_times_mul_update_66 = _dataflow_times_ready_66 || !_dataflow_times_valid_66; multiplier_10 _dataflow_times_mul_66 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_66), .enable(_dataflow_times_mul_enable_66), .valid(_dataflow_times_mul_ovalid_66), .a(_dataflow_minus_data_62), .b(_dataflow__delay_data_199), .c(_dataflow_times_mul_odata_66) ); assign _dataflow_minus_ready_62 = (_dataflow_times_ready_64 || !_dataflow_times_valid_64) && (_dataflow_minus_valid_62 && _dataflow__delay_valid_198) && ((_dataflow_times_ready_66 || !_dataflow_times_valid_66) && (_dataflow_minus_valid_62 && _dataflow__delay_valid_199)); assign _dataflow__delay_ready_199 = (_dataflow_times_ready_65 || !_dataflow_times_valid_65) && (_dataflow_minus_valid_63 && _dataflow__delay_valid_199) && ((_dataflow_times_ready_66 || !_dataflow_times_valid_66) && (_dataflow_minus_valid_62 && _dataflow__delay_valid_199)); wire signed [16-1:0] _dataflow_times_data_67; wire _dataflow_times_valid_67; wire _dataflow_times_ready_67; wire signed [32-1:0] _dataflow_times_mul_odata_67; reg signed [32-1:0] _dataflow_times_mul_odata_reg_67; assign _dataflow_times_data_67 = _dataflow_times_mul_odata_reg_67; wire _dataflow_times_mul_ovalid_67; reg _dataflow_times_mul_valid_reg_67; assign _dataflow_times_valid_67 = _dataflow_times_mul_valid_reg_67; wire _dataflow_times_mul_enable_67; wire _dataflow_times_mul_update_67; assign _dataflow_times_mul_enable_67 = (_dataflow_times_ready_67 || !_dataflow_times_valid_67) && (_dataflow_minus_ready_63 && _dataflow__delay_ready_198) && (_dataflow_minus_valid_63 && _dataflow__delay_valid_198); assign _dataflow_times_mul_update_67 = _dataflow_times_ready_67 || !_dataflow_times_valid_67; multiplier_11 _dataflow_times_mul_67 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_67), .enable(_dataflow_times_mul_enable_67), .valid(_dataflow_times_mul_ovalid_67), .a(_dataflow_minus_data_63), .b(_dataflow__delay_data_198), .c(_dataflow_times_mul_odata_67) ); assign _dataflow_minus_ready_63 = (_dataflow_times_ready_65 || !_dataflow_times_valid_65) && (_dataflow_minus_valid_63 && _dataflow__delay_valid_199) && ((_dataflow_times_ready_67 || !_dataflow_times_valid_67) && (_dataflow_minus_valid_63 && _dataflow__delay_valid_198)); assign _dataflow__delay_ready_198 = (_dataflow_times_ready_64 || !_dataflow_times_valid_64) && (_dataflow_minus_valid_62 && _dataflow__delay_valid_198) && ((_dataflow_times_ready_67 || !_dataflow_times_valid_67) && (_dataflow_minus_valid_63 && _dataflow__delay_valid_198)); wire signed [16-1:0] _dataflow_times_data_74; wire _dataflow_times_valid_74; wire _dataflow_times_ready_74; wire signed [32-1:0] _dataflow_times_mul_odata_74; reg signed [32-1:0] _dataflow_times_mul_odata_reg_74; assign _dataflow_times_data_74 = _dataflow_times_mul_odata_reg_74; wire _dataflow_times_mul_ovalid_74; reg _dataflow_times_mul_valid_reg_74; assign _dataflow_times_valid_74 = _dataflow_times_mul_valid_reg_74; wire _dataflow_times_mul_enable_74; wire _dataflow_times_mul_update_74; assign _dataflow_times_mul_enable_74 = (_dataflow_times_ready_74 || !_dataflow_times_valid_74) && (_dataflow_minus_ready_72 && _dataflow__delay_ready_202) && (_dataflow_minus_valid_72 && _dataflow__delay_valid_202); assign _dataflow_times_mul_update_74 = _dataflow_times_ready_74 || !_dataflow_times_valid_74; multiplier_12 _dataflow_times_mul_74 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_74), .enable(_dataflow_times_mul_enable_74), .valid(_dataflow_times_mul_ovalid_74), .a(_dataflow_minus_data_72), .b(_dataflow__delay_data_202), .c(_dataflow_times_mul_odata_74) ); wire signed [16-1:0] _dataflow_times_data_75; wire _dataflow_times_valid_75; wire _dataflow_times_ready_75; wire signed [32-1:0] _dataflow_times_mul_odata_75; reg signed [32-1:0] _dataflow_times_mul_odata_reg_75; assign _dataflow_times_data_75 = _dataflow_times_mul_odata_reg_75; wire _dataflow_times_mul_ovalid_75; reg _dataflow_times_mul_valid_reg_75; assign _dataflow_times_valid_75 = _dataflow_times_mul_valid_reg_75; wire _dataflow_times_mul_enable_75; wire _dataflow_times_mul_update_75; assign _dataflow_times_mul_enable_75 = (_dataflow_times_ready_75 || !_dataflow_times_valid_75) && (_dataflow_minus_ready_73 && _dataflow__delay_ready_203) && (_dataflow_minus_valid_73 && _dataflow__delay_valid_203); assign _dataflow_times_mul_update_75 = _dataflow_times_ready_75 || !_dataflow_times_valid_75; multiplier_13 _dataflow_times_mul_75 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_75), .enable(_dataflow_times_mul_enable_75), .valid(_dataflow_times_mul_ovalid_75), .a(_dataflow_minus_data_73), .b(_dataflow__delay_data_203), .c(_dataflow_times_mul_odata_75) ); wire signed [16-1:0] _dataflow_times_data_76; wire _dataflow_times_valid_76; wire _dataflow_times_ready_76; wire signed [32-1:0] _dataflow_times_mul_odata_76; reg signed [32-1:0] _dataflow_times_mul_odata_reg_76; assign _dataflow_times_data_76 = _dataflow_times_mul_odata_reg_76; wire _dataflow_times_mul_ovalid_76; reg _dataflow_times_mul_valid_reg_76; assign _dataflow_times_valid_76 = _dataflow_times_mul_valid_reg_76; wire _dataflow_times_mul_enable_76; wire _dataflow_times_mul_update_76; assign _dataflow_times_mul_enable_76 = (_dataflow_times_ready_76 || !_dataflow_times_valid_76) && (_dataflow_minus_ready_72 && _dataflow__delay_ready_203) && (_dataflow_minus_valid_72 && _dataflow__delay_valid_203); assign _dataflow_times_mul_update_76 = _dataflow_times_ready_76 || !_dataflow_times_valid_76; multiplier_14 _dataflow_times_mul_76 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_76), .enable(_dataflow_times_mul_enable_76), .valid(_dataflow_times_mul_ovalid_76), .a(_dataflow_minus_data_72), .b(_dataflow__delay_data_203), .c(_dataflow_times_mul_odata_76) ); assign _dataflow_minus_ready_72 = (_dataflow_times_ready_74 || !_dataflow_times_valid_74) && (_dataflow_minus_valid_72 && _dataflow__delay_valid_202) && ((_dataflow_times_ready_76 || !_dataflow_times_valid_76) && (_dataflow_minus_valid_72 && _dataflow__delay_valid_203)); assign _dataflow__delay_ready_203 = (_dataflow_times_ready_75 || !_dataflow_times_valid_75) && (_dataflow_minus_valid_73 && _dataflow__delay_valid_203) && ((_dataflow_times_ready_76 || !_dataflow_times_valid_76) && (_dataflow_minus_valid_72 && _dataflow__delay_valid_203)); wire signed [16-1:0] _dataflow_times_data_77; wire _dataflow_times_valid_77; wire _dataflow_times_ready_77; wire signed [32-1:0] _dataflow_times_mul_odata_77; reg signed [32-1:0] _dataflow_times_mul_odata_reg_77; assign _dataflow_times_data_77 = _dataflow_times_mul_odata_reg_77; wire _dataflow_times_mul_ovalid_77; reg _dataflow_times_mul_valid_reg_77; assign _dataflow_times_valid_77 = _dataflow_times_mul_valid_reg_77; wire _dataflow_times_mul_enable_77; wire _dataflow_times_mul_update_77; assign _dataflow_times_mul_enable_77 = (_dataflow_times_ready_77 || !_dataflow_times_valid_77) && (_dataflow_minus_ready_73 && _dataflow__delay_ready_202) && (_dataflow_minus_valid_73 && _dataflow__delay_valid_202); assign _dataflow_times_mul_update_77 = _dataflow_times_ready_77 || !_dataflow_times_valid_77; multiplier_15 _dataflow_times_mul_77 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_77), .enable(_dataflow_times_mul_enable_77), .valid(_dataflow_times_mul_ovalid_77), .a(_dataflow_minus_data_73), .b(_dataflow__delay_data_202), .c(_dataflow_times_mul_odata_77) ); assign _dataflow_minus_ready_73 = (_dataflow_times_ready_75 || !_dataflow_times_valid_75) && (_dataflow_minus_valid_73 && _dataflow__delay_valid_203) && ((_dataflow_times_ready_77 || !_dataflow_times_valid_77) && (_dataflow_minus_valid_73 && _dataflow__delay_valid_202)); assign _dataflow__delay_ready_202 = (_dataflow_times_ready_74 || !_dataflow_times_valid_74) && (_dataflow_minus_valid_72 && _dataflow__delay_valid_202) && ((_dataflow_times_ready_77 || !_dataflow_times_valid_77) && (_dataflow_minus_valid_73 && _dataflow__delay_valid_202)); reg signed [16-1:0] _dataflow_plus_data_80; reg _dataflow_plus_valid_80; wire _dataflow_plus_ready_80; reg signed [16-1:0] _dataflow_plus_data_81; reg _dataflow_plus_valid_81; wire _dataflow_plus_ready_81; reg signed [16-1:0] _dataflow_minus_data_82; reg _dataflow_minus_valid_82; wire _dataflow_minus_ready_82; assign _dataflow_plus_ready_40 = (_dataflow_plus_ready_80 || !_dataflow_plus_valid_80) && (_dataflow_plus_valid_40 && _dataflow_plus_valid_60) && ((_dataflow_minus_ready_82 || !_dataflow_minus_valid_82) && (_dataflow_plus_valid_40 && _dataflow_plus_valid_60)); assign _dataflow_plus_ready_60 = (_dataflow_plus_ready_80 || !_dataflow_plus_valid_80) && (_dataflow_plus_valid_40 && _dataflow_plus_valid_60) && ((_dataflow_minus_ready_82 || !_dataflow_minus_valid_82) && (_dataflow_plus_valid_40 && _dataflow_plus_valid_60)); reg signed [16-1:0] _dataflow_minus_data_83; reg _dataflow_minus_valid_83; wire _dataflow_minus_ready_83; assign _dataflow_plus_ready_41 = (_dataflow_plus_ready_81 || !_dataflow_plus_valid_81) && (_dataflow_plus_valid_41 && _dataflow_plus_valid_61) && ((_dataflow_minus_ready_83 || !_dataflow_minus_valid_83) && (_dataflow_plus_valid_41 && _dataflow_plus_valid_61)); assign _dataflow_plus_ready_61 = (_dataflow_plus_ready_81 || !_dataflow_plus_valid_81) && (_dataflow_plus_valid_41 && _dataflow_plus_valid_61) && ((_dataflow_minus_ready_83 || !_dataflow_minus_valid_83) && (_dataflow_plus_valid_41 && _dataflow_plus_valid_61)); reg signed [16-1:0] _dataflow_plus_data_90; reg _dataflow_plus_valid_90; wire _dataflow_plus_ready_90; reg signed [16-1:0] _dataflow_plus_data_91; reg _dataflow_plus_valid_91; wire _dataflow_plus_ready_91; reg signed [16-1:0] _dataflow_minus_data_92; reg _dataflow_minus_valid_92; wire _dataflow_minus_ready_92; assign _dataflow_plus_ready_50 = (_dataflow_plus_ready_90 || !_dataflow_plus_valid_90) && (_dataflow_plus_valid_50 && _dataflow_plus_valid_70) && ((_dataflow_minus_ready_92 || !_dataflow_minus_valid_92) && (_dataflow_plus_valid_50 && _dataflow_plus_valid_70)); assign _dataflow_plus_ready_70 = (_dataflow_plus_ready_90 || !_dataflow_plus_valid_90) && (_dataflow_plus_valid_50 && _dataflow_plus_valid_70) && ((_dataflow_minus_ready_92 || !_dataflow_minus_valid_92) && (_dataflow_plus_valid_50 && _dataflow_plus_valid_70)); reg signed [16-1:0] _dataflow_minus_data_93; reg _dataflow_minus_valid_93; wire _dataflow_minus_ready_93; assign _dataflow_plus_ready_51 = (_dataflow_plus_ready_91 || !_dataflow_plus_valid_91) && (_dataflow_plus_valid_51 && _dataflow_plus_valid_71) && ((_dataflow_minus_ready_93 || !_dataflow_minus_valid_93) && (_dataflow_plus_valid_51 && _dataflow_plus_valid_71)); assign _dataflow_plus_ready_71 = (_dataflow_plus_ready_91 || !_dataflow_plus_valid_91) && (_dataflow_plus_valid_51 && _dataflow_plus_valid_71) && ((_dataflow_minus_ready_93 || !_dataflow_minus_valid_93) && (_dataflow_plus_valid_51 && _dataflow_plus_valid_71)); reg signed [16-1:0] _dataflow__delay_data_161; reg _dataflow__delay_valid_161; wire _dataflow__delay_ready_161; assign _dataflow__delay_ready_160 = (_dataflow__delay_ready_161 || !_dataflow__delay_valid_161) && _dataflow__delay_valid_160; reg signed [16-1:0] _dataflow__delay_data_164; reg _dataflow__delay_valid_164; wire _dataflow__delay_ready_164; assign _dataflow__delay_ready_163 = (_dataflow__delay_ready_164 || !_dataflow__delay_valid_164) && _dataflow__delay_valid_163; reg signed [16-1:0] _dataflow__delay_data_167; reg _dataflow__delay_valid_167; wire _dataflow__delay_ready_167; assign _dataflow__delay_ready_166 = (_dataflow__delay_ready_167 || !_dataflow__delay_valid_167) && _dataflow__delay_valid_166; reg signed [16-1:0] _dataflow__delay_data_169; reg _dataflow__delay_valid_169; wire _dataflow__delay_ready_169; assign _dataflow__delay_ready_168 = (_dataflow__delay_ready_169 || !_dataflow__delay_valid_169) && _dataflow__delay_valid_168; reg signed [16-1:0] _dataflow__delay_data_171; reg _dataflow__delay_valid_171; wire _dataflow__delay_ready_171; assign _dataflow__delay_ready_170 = (_dataflow__delay_ready_171 || !_dataflow__delay_valid_171) && _dataflow__delay_valid_170; reg signed [16-1:0] _dataflow__delay_data_173; reg _dataflow__delay_valid_173; wire _dataflow__delay_ready_173; assign _dataflow__delay_ready_172 = (_dataflow__delay_ready_173 || !_dataflow__delay_valid_173) && _dataflow__delay_valid_172; reg signed [16-1:0] _dataflow__delay_data_175; reg _dataflow__delay_valid_175; wire _dataflow__delay_ready_175; assign _dataflow__delay_ready_174 = (_dataflow__delay_ready_175 || !_dataflow__delay_valid_175) && _dataflow__delay_valid_174; reg signed [16-1:0] _dataflow__delay_data_186; reg _dataflow__delay_valid_186; wire _dataflow__delay_ready_186; assign _dataflow__delay_ready_185 = (_dataflow__delay_ready_186 || !_dataflow__delay_valid_186) && _dataflow__delay_valid_185; reg signed [16-1:0] _dataflow__delay_data_205; reg _dataflow__delay_valid_205; wire _dataflow__delay_ready_205; assign _dataflow__delay_ready_204 = (_dataflow__delay_ready_205 || !_dataflow__delay_valid_205) && _dataflow__delay_valid_204; reg signed [16-1:0] _dataflow__delay_data_216; reg _dataflow__delay_valid_216; wire _dataflow__delay_ready_216; assign _dataflow__delay_ready_215 = (_dataflow__delay_ready_216 || !_dataflow__delay_valid_216) && _dataflow__delay_valid_215; reg signed [16-1:0] _dataflow__delay_data_227; reg _dataflow__delay_valid_227; wire _dataflow__delay_ready_227; assign _dataflow__delay_ready_226 = (_dataflow__delay_ready_227 || !_dataflow__delay_valid_227) && _dataflow__delay_valid_226; reg signed [16-1:0] _dataflow__delay_data_237; reg _dataflow__delay_valid_237; wire _dataflow__delay_ready_237; assign _dataflow__delay_ready_236 = (_dataflow__delay_ready_237 || !_dataflow__delay_valid_237) && _dataflow__delay_valid_236; reg signed [16-1:0] _dataflow__delay_data_247; reg _dataflow__delay_valid_247; wire _dataflow__delay_ready_247; assign _dataflow__delay_ready_246 = (_dataflow__delay_ready_247 || !_dataflow__delay_valid_247) && _dataflow__delay_valid_246; reg signed [16-1:0] _dataflow__delay_data_257; reg _dataflow__delay_valid_257; wire _dataflow__delay_ready_257; assign _dataflow__delay_ready_256 = (_dataflow__delay_ready_257 || !_dataflow__delay_valid_257) && _dataflow__delay_valid_256; reg signed [16-1:0] _dataflow__delay_data_267; reg _dataflow__delay_valid_267; wire _dataflow__delay_ready_267; assign _dataflow__delay_ready_266 = (_dataflow__delay_ready_267 || !_dataflow__delay_valid_267) && _dataflow__delay_valid_266; reg signed [16-1:0] _dataflow__delay_data_286; reg _dataflow__delay_valid_286; wire _dataflow__delay_ready_286; assign _dataflow__delay_ready_285 = (_dataflow__delay_ready_286 || !_dataflow__delay_valid_286) && _dataflow__delay_valid_285; wire signed [16-1:0] _dataflow_times_data_84; wire _dataflow_times_valid_84; wire _dataflow_times_ready_84; wire signed [32-1:0] _dataflow_times_mul_odata_84; reg signed [32-1:0] _dataflow_times_mul_odata_reg_84; assign _dataflow_times_data_84 = _dataflow_times_mul_odata_reg_84; wire _dataflow_times_mul_ovalid_84; reg _dataflow_times_mul_valid_reg_84; assign _dataflow_times_valid_84 = _dataflow_times_mul_valid_reg_84; wire _dataflow_times_mul_enable_84; wire _dataflow_times_mul_update_84; assign _dataflow_times_mul_enable_84 = (_dataflow_times_ready_84 || !_dataflow_times_valid_84) && (_dataflow_minus_ready_82 && _dataflow__delay_ready_167) && (_dataflow_minus_valid_82 && _dataflow__delay_valid_167); assign _dataflow_times_mul_update_84 = _dataflow_times_ready_84 || !_dataflow_times_valid_84; multiplier_16 _dataflow_times_mul_84 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_84), .enable(_dataflow_times_mul_enable_84), .valid(_dataflow_times_mul_ovalid_84), .a(_dataflow_minus_data_82), .b(_dataflow__delay_data_167), .c(_dataflow_times_mul_odata_84) ); wire signed [16-1:0] _dataflow_times_data_85; wire _dataflow_times_valid_85; wire _dataflow_times_ready_85; wire signed [32-1:0] _dataflow_times_mul_odata_85; reg signed [32-1:0] _dataflow_times_mul_odata_reg_85; assign _dataflow_times_data_85 = _dataflow_times_mul_odata_reg_85; wire _dataflow_times_mul_ovalid_85; reg _dataflow_times_mul_valid_reg_85; assign _dataflow_times_valid_85 = _dataflow_times_mul_valid_reg_85; wire _dataflow_times_mul_enable_85; wire _dataflow_times_mul_update_85; assign _dataflow_times_mul_enable_85 = (_dataflow_times_ready_85 || !_dataflow_times_valid_85) && (_dataflow_minus_ready_83 && _dataflow__delay_ready_169) && (_dataflow_minus_valid_83 && _dataflow__delay_valid_169); assign _dataflow_times_mul_update_85 = _dataflow_times_ready_85 || !_dataflow_times_valid_85; multiplier_17 _dataflow_times_mul_85 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_85), .enable(_dataflow_times_mul_enable_85), .valid(_dataflow_times_mul_ovalid_85), .a(_dataflow_minus_data_83), .b(_dataflow__delay_data_169), .c(_dataflow_times_mul_odata_85) ); wire signed [16-1:0] _dataflow_times_data_86; wire _dataflow_times_valid_86; wire _dataflow_times_ready_86; wire signed [32-1:0] _dataflow_times_mul_odata_86; reg signed [32-1:0] _dataflow_times_mul_odata_reg_86; assign _dataflow_times_data_86 = _dataflow_times_mul_odata_reg_86; wire _dataflow_times_mul_ovalid_86; reg _dataflow_times_mul_valid_reg_86; assign _dataflow_times_valid_86 = _dataflow_times_mul_valid_reg_86; wire _dataflow_times_mul_enable_86; wire _dataflow_times_mul_update_86; assign _dataflow_times_mul_enable_86 = (_dataflow_times_ready_86 || !_dataflow_times_valid_86) && (_dataflow_minus_ready_82 && _dataflow__delay_ready_169) && (_dataflow_minus_valid_82 && _dataflow__delay_valid_169); assign _dataflow_times_mul_update_86 = _dataflow_times_ready_86 || !_dataflow_times_valid_86; multiplier_18 _dataflow_times_mul_86 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_86), .enable(_dataflow_times_mul_enable_86), .valid(_dataflow_times_mul_ovalid_86), .a(_dataflow_minus_data_82), .b(_dataflow__delay_data_169), .c(_dataflow_times_mul_odata_86) ); assign _dataflow_minus_ready_82 = (_dataflow_times_ready_84 || !_dataflow_times_valid_84) && (_dataflow_minus_valid_82 && _dataflow__delay_valid_167) && ((_dataflow_times_ready_86 || !_dataflow_times_valid_86) && (_dataflow_minus_valid_82 && _dataflow__delay_valid_169)); assign _dataflow__delay_ready_169 = (_dataflow_times_ready_85 || !_dataflow_times_valid_85) && (_dataflow_minus_valid_83 && _dataflow__delay_valid_169) && ((_dataflow_times_ready_86 || !_dataflow_times_valid_86) && (_dataflow_minus_valid_82 && _dataflow__delay_valid_169)); wire signed [16-1:0] _dataflow_times_data_87; wire _dataflow_times_valid_87; wire _dataflow_times_ready_87; wire signed [32-1:0] _dataflow_times_mul_odata_87; reg signed [32-1:0] _dataflow_times_mul_odata_reg_87; assign _dataflow_times_data_87 = _dataflow_times_mul_odata_reg_87; wire _dataflow_times_mul_ovalid_87; reg _dataflow_times_mul_valid_reg_87; assign _dataflow_times_valid_87 = _dataflow_times_mul_valid_reg_87; wire _dataflow_times_mul_enable_87; wire _dataflow_times_mul_update_87; assign _dataflow_times_mul_enable_87 = (_dataflow_times_ready_87 || !_dataflow_times_valid_87) && (_dataflow_minus_ready_83 && _dataflow__delay_ready_167) && (_dataflow_minus_valid_83 && _dataflow__delay_valid_167); assign _dataflow_times_mul_update_87 = _dataflow_times_ready_87 || !_dataflow_times_valid_87; multiplier_19 _dataflow_times_mul_87 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_87), .enable(_dataflow_times_mul_enable_87), .valid(_dataflow_times_mul_ovalid_87), .a(_dataflow_minus_data_83), .b(_dataflow__delay_data_167), .c(_dataflow_times_mul_odata_87) ); assign _dataflow_minus_ready_83 = (_dataflow_times_ready_85 || !_dataflow_times_valid_85) && (_dataflow_minus_valid_83 && _dataflow__delay_valid_169) && ((_dataflow_times_ready_87 || !_dataflow_times_valid_87) && (_dataflow_minus_valid_83 && _dataflow__delay_valid_167)); assign _dataflow__delay_ready_167 = (_dataflow_times_ready_84 || !_dataflow_times_valid_84) && (_dataflow_minus_valid_82 && _dataflow__delay_valid_167) && ((_dataflow_times_ready_87 || !_dataflow_times_valid_87) && (_dataflow_minus_valid_83 && _dataflow__delay_valid_167)); wire signed [16-1:0] _dataflow_times_data_94; wire _dataflow_times_valid_94; wire _dataflow_times_ready_94; wire signed [32-1:0] _dataflow_times_mul_odata_94; reg signed [32-1:0] _dataflow_times_mul_odata_reg_94; assign _dataflow_times_data_94 = _dataflow_times_mul_odata_reg_94; wire _dataflow_times_mul_ovalid_94; reg _dataflow_times_mul_valid_reg_94; assign _dataflow_times_valid_94 = _dataflow_times_mul_valid_reg_94; wire _dataflow_times_mul_enable_94; wire _dataflow_times_mul_update_94; assign _dataflow_times_mul_enable_94 = (_dataflow_times_ready_94 || !_dataflow_times_valid_94) && (_dataflow_minus_ready_92 && _dataflow__delay_ready_171) && (_dataflow_minus_valid_92 && _dataflow__delay_valid_171); assign _dataflow_times_mul_update_94 = _dataflow_times_ready_94 || !_dataflow_times_valid_94; multiplier_20 _dataflow_times_mul_94 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_94), .enable(_dataflow_times_mul_enable_94), .valid(_dataflow_times_mul_ovalid_94), .a(_dataflow_minus_data_92), .b(_dataflow__delay_data_171), .c(_dataflow_times_mul_odata_94) ); wire signed [16-1:0] _dataflow_times_data_95; wire _dataflow_times_valid_95; wire _dataflow_times_ready_95; wire signed [32-1:0] _dataflow_times_mul_odata_95; reg signed [32-1:0] _dataflow_times_mul_odata_reg_95; assign _dataflow_times_data_95 = _dataflow_times_mul_odata_reg_95; wire _dataflow_times_mul_ovalid_95; reg _dataflow_times_mul_valid_reg_95; assign _dataflow_times_valid_95 = _dataflow_times_mul_valid_reg_95; wire _dataflow_times_mul_enable_95; wire _dataflow_times_mul_update_95; assign _dataflow_times_mul_enable_95 = (_dataflow_times_ready_95 || !_dataflow_times_valid_95) && (_dataflow_minus_ready_93 && _dataflow__delay_ready_173) && (_dataflow_minus_valid_93 && _dataflow__delay_valid_173); assign _dataflow_times_mul_update_95 = _dataflow_times_ready_95 || !_dataflow_times_valid_95; multiplier_21 _dataflow_times_mul_95 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_95), .enable(_dataflow_times_mul_enable_95), .valid(_dataflow_times_mul_ovalid_95), .a(_dataflow_minus_data_93), .b(_dataflow__delay_data_173), .c(_dataflow_times_mul_odata_95) ); wire signed [16-1:0] _dataflow_times_data_96; wire _dataflow_times_valid_96; wire _dataflow_times_ready_96; wire signed [32-1:0] _dataflow_times_mul_odata_96; reg signed [32-1:0] _dataflow_times_mul_odata_reg_96; assign _dataflow_times_data_96 = _dataflow_times_mul_odata_reg_96; wire _dataflow_times_mul_ovalid_96; reg _dataflow_times_mul_valid_reg_96; assign _dataflow_times_valid_96 = _dataflow_times_mul_valid_reg_96; wire _dataflow_times_mul_enable_96; wire _dataflow_times_mul_update_96; assign _dataflow_times_mul_enable_96 = (_dataflow_times_ready_96 || !_dataflow_times_valid_96) && (_dataflow_minus_ready_92 && _dataflow__delay_ready_173) && (_dataflow_minus_valid_92 && _dataflow__delay_valid_173); assign _dataflow_times_mul_update_96 = _dataflow_times_ready_96 || !_dataflow_times_valid_96; multiplier_22 _dataflow_times_mul_96 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_96), .enable(_dataflow_times_mul_enable_96), .valid(_dataflow_times_mul_ovalid_96), .a(_dataflow_minus_data_92), .b(_dataflow__delay_data_173), .c(_dataflow_times_mul_odata_96) ); assign _dataflow_minus_ready_92 = (_dataflow_times_ready_94 || !_dataflow_times_valid_94) && (_dataflow_minus_valid_92 && _dataflow__delay_valid_171) && ((_dataflow_times_ready_96 || !_dataflow_times_valid_96) && (_dataflow_minus_valid_92 && _dataflow__delay_valid_173)); assign _dataflow__delay_ready_173 = (_dataflow_times_ready_95 || !_dataflow_times_valid_95) && (_dataflow_minus_valid_93 && _dataflow__delay_valid_173) && ((_dataflow_times_ready_96 || !_dataflow_times_valid_96) && (_dataflow_minus_valid_92 && _dataflow__delay_valid_173)); wire signed [16-1:0] _dataflow_times_data_97; wire _dataflow_times_valid_97; wire _dataflow_times_ready_97; wire signed [32-1:0] _dataflow_times_mul_odata_97; reg signed [32-1:0] _dataflow_times_mul_odata_reg_97; assign _dataflow_times_data_97 = _dataflow_times_mul_odata_reg_97; wire _dataflow_times_mul_ovalid_97; reg _dataflow_times_mul_valid_reg_97; assign _dataflow_times_valid_97 = _dataflow_times_mul_valid_reg_97; wire _dataflow_times_mul_enable_97; wire _dataflow_times_mul_update_97; assign _dataflow_times_mul_enable_97 = (_dataflow_times_ready_97 || !_dataflow_times_valid_97) && (_dataflow_minus_ready_93 && _dataflow__delay_ready_171) && (_dataflow_minus_valid_93 && _dataflow__delay_valid_171); assign _dataflow_times_mul_update_97 = _dataflow_times_ready_97 || !_dataflow_times_valid_97; multiplier_23 _dataflow_times_mul_97 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_97), .enable(_dataflow_times_mul_enable_97), .valid(_dataflow_times_mul_ovalid_97), .a(_dataflow_minus_data_93), .b(_dataflow__delay_data_171), .c(_dataflow_times_mul_odata_97) ); assign _dataflow_minus_ready_93 = (_dataflow_times_ready_95 || !_dataflow_times_valid_95) && (_dataflow_minus_valid_93 && _dataflow__delay_valid_173) && ((_dataflow_times_ready_97 || !_dataflow_times_valid_97) && (_dataflow_minus_valid_93 && _dataflow__delay_valid_171)); assign _dataflow__delay_ready_171 = (_dataflow_times_ready_94 || !_dataflow_times_valid_94) && (_dataflow_minus_valid_92 && _dataflow__delay_valid_171) && ((_dataflow_times_ready_97 || !_dataflow_times_valid_97) && (_dataflow_minus_valid_93 && _dataflow__delay_valid_171)); reg signed [16-1:0] _dataflow_plus_data_120; reg _dataflow_plus_valid_120; wire _dataflow_plus_ready_120; reg signed [16-1:0] _dataflow_plus_data_121; reg _dataflow_plus_valid_121; wire _dataflow_plus_ready_121; reg signed [16-1:0] _dataflow_minus_data_122; reg _dataflow_minus_valid_122; wire _dataflow_minus_ready_122; assign _dataflow_plus_ready_80 = (_dataflow_plus_ready_120 || !_dataflow_plus_valid_120) && (_dataflow_plus_valid_80 && _dataflow_plus_valid_90) && ((_dataflow_minus_ready_122 || !_dataflow_minus_valid_122) && (_dataflow_plus_valid_80 && _dataflow_plus_valid_90)); assign _dataflow_plus_ready_90 = (_dataflow_plus_ready_120 || !_dataflow_plus_valid_120) && (_dataflow_plus_valid_80 && _dataflow_plus_valid_90) && ((_dataflow_minus_ready_122 || !_dataflow_minus_valid_122) && (_dataflow_plus_valid_80 && _dataflow_plus_valid_90)); reg signed [16-1:0] _dataflow_minus_data_123; reg _dataflow_minus_valid_123; wire _dataflow_minus_ready_123; assign _dataflow_plus_ready_81 = (_dataflow_plus_ready_121 || !_dataflow_plus_valid_121) && (_dataflow_plus_valid_81 && _dataflow_plus_valid_91) && ((_dataflow_minus_ready_123 || !_dataflow_minus_valid_123) && (_dataflow_plus_valid_81 && _dataflow_plus_valid_91)); assign _dataflow_plus_ready_91 = (_dataflow_plus_ready_121 || !_dataflow_plus_valid_121) && (_dataflow_plus_valid_81 && _dataflow_plus_valid_91) && ((_dataflow_minus_ready_123 || !_dataflow_minus_valid_123) && (_dataflow_plus_valid_81 && _dataflow_plus_valid_91)); reg signed [16-1:0] _dataflow__delay_data_162; reg _dataflow__delay_valid_162; wire _dataflow__delay_ready_162; assign _dataflow__delay_ready_161 = (_dataflow__delay_ready_162 || !_dataflow__delay_valid_162) && _dataflow__delay_valid_161; reg signed [16-1:0] _dataflow__delay_data_165; reg _dataflow__delay_valid_165; wire _dataflow__delay_ready_165; assign _dataflow__delay_ready_164 = (_dataflow__delay_ready_165 || !_dataflow__delay_valid_165) && _dataflow__delay_valid_164; reg signed [16-1:0] _dataflow__delay_data_176; reg _dataflow__delay_valid_176; wire _dataflow__delay_ready_176; assign _dataflow__delay_ready_175 = (_dataflow__delay_ready_176 || !_dataflow__delay_valid_176) && _dataflow__delay_valid_175; reg signed [16-1:0] _dataflow__delay_data_187; reg _dataflow__delay_valid_187; wire _dataflow__delay_ready_187; assign _dataflow__delay_ready_186 = (_dataflow__delay_ready_187 || !_dataflow__delay_valid_187) && _dataflow__delay_valid_186; reg signed [16-1:0] _dataflow__delay_data_206; reg _dataflow__delay_valid_206; wire _dataflow__delay_ready_206; assign _dataflow__delay_ready_205 = (_dataflow__delay_ready_206 || !_dataflow__delay_valid_206) && _dataflow__delay_valid_205; reg signed [16-1:0] _dataflow__delay_data_217; reg _dataflow__delay_valid_217; wire _dataflow__delay_ready_217; assign _dataflow__delay_ready_216 = (_dataflow__delay_ready_217 || !_dataflow__delay_valid_217) && _dataflow__delay_valid_216; reg signed [16-1:0] _dataflow__delay_data_228; reg _dataflow__delay_valid_228; wire _dataflow__delay_ready_228; assign _dataflow__delay_ready_227 = (_dataflow__delay_ready_228 || !_dataflow__delay_valid_228) && _dataflow__delay_valid_227; reg signed [16-1:0] _dataflow__delay_data_238; reg _dataflow__delay_valid_238; wire _dataflow__delay_ready_238; assign _dataflow__delay_ready_237 = (_dataflow__delay_ready_238 || !_dataflow__delay_valid_238) && _dataflow__delay_valid_237; reg signed [16-1:0] _dataflow__delay_data_248; reg _dataflow__delay_valid_248; wire _dataflow__delay_ready_248; assign _dataflow__delay_ready_247 = (_dataflow__delay_ready_248 || !_dataflow__delay_valid_248) && _dataflow__delay_valid_247; reg signed [16-1:0] _dataflow__delay_data_258; reg _dataflow__delay_valid_258; wire _dataflow__delay_ready_258; assign _dataflow__delay_ready_257 = (_dataflow__delay_ready_258 || !_dataflow__delay_valid_258) && _dataflow__delay_valid_257; reg signed [16-1:0] _dataflow__delay_data_268; reg _dataflow__delay_valid_268; wire _dataflow__delay_ready_268; assign _dataflow__delay_ready_267 = (_dataflow__delay_ready_268 || !_dataflow__delay_valid_268) && _dataflow__delay_valid_267; reg signed [16-1:0] _dataflow__delay_data_287; reg _dataflow__delay_valid_287; wire _dataflow__delay_ready_287; assign _dataflow__delay_ready_286 = (_dataflow__delay_ready_287 || !_dataflow__delay_valid_287) && _dataflow__delay_valid_286; wire signed [16-1:0] _dataflow_times_data_124; wire _dataflow_times_valid_124; wire _dataflow_times_ready_124; wire signed [32-1:0] _dataflow_times_mul_odata_124; reg signed [32-1:0] _dataflow_times_mul_odata_reg_124; assign _dataflow_times_data_124 = _dataflow_times_mul_odata_reg_124; wire _dataflow_times_mul_ovalid_124; reg _dataflow_times_mul_valid_reg_124; assign _dataflow_times_valid_124 = _dataflow_times_mul_valid_reg_124; wire _dataflow_times_mul_enable_124; wire _dataflow_times_mul_update_124; assign _dataflow_times_mul_enable_124 = (_dataflow_times_ready_124 || !_dataflow_times_valid_124) && (_dataflow_minus_ready_122 && _dataflow__delay_ready_162) && (_dataflow_minus_valid_122 && _dataflow__delay_valid_162); assign _dataflow_times_mul_update_124 = _dataflow_times_ready_124 || !_dataflow_times_valid_124; multiplier_24 _dataflow_times_mul_124 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_124), .enable(_dataflow_times_mul_enable_124), .valid(_dataflow_times_mul_ovalid_124), .a(_dataflow_minus_data_122), .b(_dataflow__delay_data_162), .c(_dataflow_times_mul_odata_124) ); wire signed [16-1:0] _dataflow_times_data_125; wire _dataflow_times_valid_125; wire _dataflow_times_ready_125; wire signed [32-1:0] _dataflow_times_mul_odata_125; reg signed [32-1:0] _dataflow_times_mul_odata_reg_125; assign _dataflow_times_data_125 = _dataflow_times_mul_odata_reg_125; wire _dataflow_times_mul_ovalid_125; reg _dataflow_times_mul_valid_reg_125; assign _dataflow_times_valid_125 = _dataflow_times_mul_valid_reg_125; wire _dataflow_times_mul_enable_125; wire _dataflow_times_mul_update_125; assign _dataflow_times_mul_enable_125 = (_dataflow_times_ready_125 || !_dataflow_times_valid_125) && (_dataflow_minus_ready_123 && _dataflow__delay_ready_165) && (_dataflow_minus_valid_123 && _dataflow__delay_valid_165); assign _dataflow_times_mul_update_125 = _dataflow_times_ready_125 || !_dataflow_times_valid_125; multiplier_25 _dataflow_times_mul_125 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_125), .enable(_dataflow_times_mul_enable_125), .valid(_dataflow_times_mul_ovalid_125), .a(_dataflow_minus_data_123), .b(_dataflow__delay_data_165), .c(_dataflow_times_mul_odata_125) ); wire signed [16-1:0] _dataflow_times_data_126; wire _dataflow_times_valid_126; wire _dataflow_times_ready_126; wire signed [32-1:0] _dataflow_times_mul_odata_126; reg signed [32-1:0] _dataflow_times_mul_odata_reg_126; assign _dataflow_times_data_126 = _dataflow_times_mul_odata_reg_126; wire _dataflow_times_mul_ovalid_126; reg _dataflow_times_mul_valid_reg_126; assign _dataflow_times_valid_126 = _dataflow_times_mul_valid_reg_126; wire _dataflow_times_mul_enable_126; wire _dataflow_times_mul_update_126; assign _dataflow_times_mul_enable_126 = (_dataflow_times_ready_126 || !_dataflow_times_valid_126) && (_dataflow_minus_ready_122 && _dataflow__delay_ready_165) && (_dataflow_minus_valid_122 && _dataflow__delay_valid_165); assign _dataflow_times_mul_update_126 = _dataflow_times_ready_126 || !_dataflow_times_valid_126; multiplier_26 _dataflow_times_mul_126 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_126), .enable(_dataflow_times_mul_enable_126), .valid(_dataflow_times_mul_ovalid_126), .a(_dataflow_minus_data_122), .b(_dataflow__delay_data_165), .c(_dataflow_times_mul_odata_126) ); assign _dataflow_minus_ready_122 = (_dataflow_times_ready_124 || !_dataflow_times_valid_124) && (_dataflow_minus_valid_122 && _dataflow__delay_valid_162) && ((_dataflow_times_ready_126 || !_dataflow_times_valid_126) && (_dataflow_minus_valid_122 && _dataflow__delay_valid_165)); assign _dataflow__delay_ready_165 = (_dataflow_times_ready_125 || !_dataflow_times_valid_125) && (_dataflow_minus_valid_123 && _dataflow__delay_valid_165) && ((_dataflow_times_ready_126 || !_dataflow_times_valid_126) && (_dataflow_minus_valid_122 && _dataflow__delay_valid_165)); wire signed [16-1:0] _dataflow_times_data_127; wire _dataflow_times_valid_127; wire _dataflow_times_ready_127; wire signed [32-1:0] _dataflow_times_mul_odata_127; reg signed [32-1:0] _dataflow_times_mul_odata_reg_127; assign _dataflow_times_data_127 = _dataflow_times_mul_odata_reg_127; wire _dataflow_times_mul_ovalid_127; reg _dataflow_times_mul_valid_reg_127; assign _dataflow_times_valid_127 = _dataflow_times_mul_valid_reg_127; wire _dataflow_times_mul_enable_127; wire _dataflow_times_mul_update_127; assign _dataflow_times_mul_enable_127 = (_dataflow_times_ready_127 || !_dataflow_times_valid_127) && (_dataflow_minus_ready_123 && _dataflow__delay_ready_162) && (_dataflow_minus_valid_123 && _dataflow__delay_valid_162); assign _dataflow_times_mul_update_127 = _dataflow_times_ready_127 || !_dataflow_times_valid_127; multiplier_27 _dataflow_times_mul_127 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_127), .enable(_dataflow_times_mul_enable_127), .valid(_dataflow_times_mul_ovalid_127), .a(_dataflow_minus_data_123), .b(_dataflow__delay_data_162), .c(_dataflow_times_mul_odata_127) ); assign _dataflow_minus_ready_123 = (_dataflow_times_ready_125 || !_dataflow_times_valid_125) && (_dataflow_minus_valid_123 && _dataflow__delay_valid_165) && ((_dataflow_times_ready_127 || !_dataflow_times_valid_127) && (_dataflow_minus_valid_123 && _dataflow__delay_valid_162)); assign _dataflow__delay_ready_162 = (_dataflow_times_ready_124 || !_dataflow_times_valid_124) && (_dataflow_minus_valid_122 && _dataflow__delay_valid_162) && ((_dataflow_times_ready_127 || !_dataflow_times_valid_127) && (_dataflow_minus_valid_123 && _dataflow__delay_valid_162)); reg signed [16-1:0] _dataflow__delay_data_177; reg _dataflow__delay_valid_177; wire _dataflow__delay_ready_177; assign _dataflow__delay_ready_176 = (_dataflow__delay_ready_177 || !_dataflow__delay_valid_177) && _dataflow__delay_valid_176; reg signed [16-1:0] _dataflow__delay_data_188; reg _dataflow__delay_valid_188; wire _dataflow__delay_ready_188; assign _dataflow__delay_ready_187 = (_dataflow__delay_ready_188 || !_dataflow__delay_valid_188) && _dataflow__delay_valid_187; reg signed [16-1:0] _dataflow__delay_data_207; reg _dataflow__delay_valid_207; wire _dataflow__delay_ready_207; assign _dataflow__delay_ready_206 = (_dataflow__delay_ready_207 || !_dataflow__delay_valid_207) && _dataflow__delay_valid_206; reg signed [16-1:0] _dataflow__delay_data_218; reg _dataflow__delay_valid_218; wire _dataflow__delay_ready_218; assign _dataflow__delay_ready_217 = (_dataflow__delay_ready_218 || !_dataflow__delay_valid_218) && _dataflow__delay_valid_217; reg signed [16-1:0] _dataflow__delay_data_229; reg _dataflow__delay_valid_229; wire _dataflow__delay_ready_229; assign _dataflow__delay_ready_228 = (_dataflow__delay_ready_229 || !_dataflow__delay_valid_229) && _dataflow__delay_valid_228; reg signed [16-1:0] _dataflow__delay_data_239; reg _dataflow__delay_valid_239; wire _dataflow__delay_ready_239; assign _dataflow__delay_ready_238 = (_dataflow__delay_ready_239 || !_dataflow__delay_valid_239) && _dataflow__delay_valid_238; reg signed [16-1:0] _dataflow__delay_data_249; reg _dataflow__delay_valid_249; wire _dataflow__delay_ready_249; assign _dataflow__delay_ready_248 = (_dataflow__delay_ready_249 || !_dataflow__delay_valid_249) && _dataflow__delay_valid_248; reg signed [16-1:0] _dataflow__delay_data_259; reg _dataflow__delay_valid_259; wire _dataflow__delay_ready_259; assign _dataflow__delay_ready_258 = (_dataflow__delay_ready_259 || !_dataflow__delay_valid_259) && _dataflow__delay_valid_258; reg signed [16-1:0] _dataflow__delay_data_269; reg _dataflow__delay_valid_269; wire _dataflow__delay_ready_269; assign _dataflow__delay_ready_268 = (_dataflow__delay_ready_269 || !_dataflow__delay_valid_269) && _dataflow__delay_valid_268; reg signed [16-1:0] _dataflow__delay_data_288; reg _dataflow__delay_valid_288; wire _dataflow__delay_ready_288; assign _dataflow__delay_ready_287 = (_dataflow__delay_ready_288 || !_dataflow__delay_valid_288) && _dataflow__delay_valid_287; reg signed [16-1:0] _dataflow__delay_data_304; reg _dataflow__delay_valid_304; wire _dataflow__delay_ready_304; assign _dataflow_plus_ready_120 = (_dataflow__delay_ready_304 || !_dataflow__delay_valid_304) && _dataflow_plus_valid_120; reg signed [16-1:0] _dataflow__delay_data_328; reg _dataflow__delay_valid_328; wire _dataflow__delay_ready_328; assign _dataflow_plus_ready_121 = (_dataflow__delay_ready_328 || !_dataflow__delay_valid_328) && _dataflow_plus_valid_121; reg signed [16-1:0] _dataflow__delay_data_178; reg _dataflow__delay_valid_178; wire _dataflow__delay_ready_178; assign _dataflow__delay_ready_177 = (_dataflow__delay_ready_178 || !_dataflow__delay_valid_178) && _dataflow__delay_valid_177; reg signed [16-1:0] _dataflow__delay_data_189; reg _dataflow__delay_valid_189; wire _dataflow__delay_ready_189; assign _dataflow__delay_ready_188 = (_dataflow__delay_ready_189 || !_dataflow__delay_valid_189) && _dataflow__delay_valid_188; reg signed [16-1:0] _dataflow__delay_data_208; reg _dataflow__delay_valid_208; wire _dataflow__delay_ready_208; assign _dataflow__delay_ready_207 = (_dataflow__delay_ready_208 || !_dataflow__delay_valid_208) && _dataflow__delay_valid_207; reg signed [16-1:0] _dataflow__delay_data_219; reg _dataflow__delay_valid_219; wire _dataflow__delay_ready_219; assign _dataflow__delay_ready_218 = (_dataflow__delay_ready_219 || !_dataflow__delay_valid_219) && _dataflow__delay_valid_218; reg signed [16-1:0] _dataflow__delay_data_230; reg _dataflow__delay_valid_230; wire _dataflow__delay_ready_230; assign _dataflow__delay_ready_229 = (_dataflow__delay_ready_230 || !_dataflow__delay_valid_230) && _dataflow__delay_valid_229; reg signed [16-1:0] _dataflow__delay_data_240; reg _dataflow__delay_valid_240; wire _dataflow__delay_ready_240; assign _dataflow__delay_ready_239 = (_dataflow__delay_ready_240 || !_dataflow__delay_valid_240) && _dataflow__delay_valid_239; reg signed [16-1:0] _dataflow__delay_data_250; reg _dataflow__delay_valid_250; wire _dataflow__delay_ready_250; assign _dataflow__delay_ready_249 = (_dataflow__delay_ready_250 || !_dataflow__delay_valid_250) && _dataflow__delay_valid_249; reg signed [16-1:0] _dataflow__delay_data_260; reg _dataflow__delay_valid_260; wire _dataflow__delay_ready_260; assign _dataflow__delay_ready_259 = (_dataflow__delay_ready_260 || !_dataflow__delay_valid_260) && _dataflow__delay_valid_259; reg signed [16-1:0] _dataflow__delay_data_270; reg _dataflow__delay_valid_270; wire _dataflow__delay_ready_270; assign _dataflow__delay_ready_269 = (_dataflow__delay_ready_270 || !_dataflow__delay_valid_270) && _dataflow__delay_valid_269; reg signed [16-1:0] _dataflow__delay_data_289; reg _dataflow__delay_valid_289; wire _dataflow__delay_ready_289; assign _dataflow__delay_ready_288 = (_dataflow__delay_ready_289 || !_dataflow__delay_valid_289) && _dataflow__delay_valid_288; reg signed [16-1:0] _dataflow__delay_data_305; reg _dataflow__delay_valid_305; wire _dataflow__delay_ready_305; assign _dataflow__delay_ready_304 = (_dataflow__delay_ready_305 || !_dataflow__delay_valid_305) && _dataflow__delay_valid_304; reg signed [16-1:0] _dataflow__delay_data_329; reg _dataflow__delay_valid_329; wire _dataflow__delay_ready_329; assign _dataflow__delay_ready_328 = (_dataflow__delay_ready_329 || !_dataflow__delay_valid_329) && _dataflow__delay_valid_328; reg signed [16-1:0] _dataflow__delay_data_179; reg _dataflow__delay_valid_179; wire _dataflow__delay_ready_179; assign _dataflow__delay_ready_178 = (_dataflow__delay_ready_179 || !_dataflow__delay_valid_179) && _dataflow__delay_valid_178; reg signed [16-1:0] _dataflow__delay_data_190; reg _dataflow__delay_valid_190; wire _dataflow__delay_ready_190; assign _dataflow__delay_ready_189 = (_dataflow__delay_ready_190 || !_dataflow__delay_valid_190) && _dataflow__delay_valid_189; reg signed [16-1:0] _dataflow__delay_data_209; reg _dataflow__delay_valid_209; wire _dataflow__delay_ready_209; assign _dataflow__delay_ready_208 = (_dataflow__delay_ready_209 || !_dataflow__delay_valid_209) && _dataflow__delay_valid_208; reg signed [16-1:0] _dataflow__delay_data_220; reg _dataflow__delay_valid_220; wire _dataflow__delay_ready_220; assign _dataflow__delay_ready_219 = (_dataflow__delay_ready_220 || !_dataflow__delay_valid_220) && _dataflow__delay_valid_219; reg signed [16-1:0] _dataflow__delay_data_231; reg _dataflow__delay_valid_231; wire _dataflow__delay_ready_231; assign _dataflow__delay_ready_230 = (_dataflow__delay_ready_231 || !_dataflow__delay_valid_231) && _dataflow__delay_valid_230; reg signed [16-1:0] _dataflow__delay_data_241; reg _dataflow__delay_valid_241; wire _dataflow__delay_ready_241; assign _dataflow__delay_ready_240 = (_dataflow__delay_ready_241 || !_dataflow__delay_valid_241) && _dataflow__delay_valid_240; reg signed [16-1:0] _dataflow__delay_data_251; reg _dataflow__delay_valid_251; wire _dataflow__delay_ready_251; assign _dataflow__delay_ready_250 = (_dataflow__delay_ready_251 || !_dataflow__delay_valid_251) && _dataflow__delay_valid_250; reg signed [16-1:0] _dataflow__delay_data_261; reg _dataflow__delay_valid_261; wire _dataflow__delay_ready_261; assign _dataflow__delay_ready_260 = (_dataflow__delay_ready_261 || !_dataflow__delay_valid_261) && _dataflow__delay_valid_260; reg signed [16-1:0] _dataflow__delay_data_271; reg _dataflow__delay_valid_271; wire _dataflow__delay_ready_271; assign _dataflow__delay_ready_270 = (_dataflow__delay_ready_271 || !_dataflow__delay_valid_271) && _dataflow__delay_valid_270; reg signed [16-1:0] _dataflow__delay_data_290; reg _dataflow__delay_valid_290; wire _dataflow__delay_ready_290; assign _dataflow__delay_ready_289 = (_dataflow__delay_ready_290 || !_dataflow__delay_valid_290) && _dataflow__delay_valid_289; reg signed [16-1:0] _dataflow__delay_data_306; reg _dataflow__delay_valid_306; wire _dataflow__delay_ready_306; assign _dataflow__delay_ready_305 = (_dataflow__delay_ready_306 || !_dataflow__delay_valid_306) && _dataflow__delay_valid_305; reg signed [16-1:0] _dataflow__delay_data_330; reg _dataflow__delay_valid_330; wire _dataflow__delay_ready_330; assign _dataflow__delay_ready_329 = (_dataflow__delay_ready_330 || !_dataflow__delay_valid_330) && _dataflow__delay_valid_329; reg signed [16-1:0] _dataflow__delay_data_180; reg _dataflow__delay_valid_180; wire _dataflow__delay_ready_180; assign _dataflow__delay_ready_179 = (_dataflow__delay_ready_180 || !_dataflow__delay_valid_180) && _dataflow__delay_valid_179; reg signed [16-1:0] _dataflow__delay_data_191; reg _dataflow__delay_valid_191; wire _dataflow__delay_ready_191; assign _dataflow__delay_ready_190 = (_dataflow__delay_ready_191 || !_dataflow__delay_valid_191) && _dataflow__delay_valid_190; reg signed [16-1:0] _dataflow__delay_data_210; reg _dataflow__delay_valid_210; wire _dataflow__delay_ready_210; assign _dataflow__delay_ready_209 = (_dataflow__delay_ready_210 || !_dataflow__delay_valid_210) && _dataflow__delay_valid_209; reg signed [16-1:0] _dataflow__delay_data_221; reg _dataflow__delay_valid_221; wire _dataflow__delay_ready_221; assign _dataflow__delay_ready_220 = (_dataflow__delay_ready_221 || !_dataflow__delay_valid_221) && _dataflow__delay_valid_220; reg signed [16-1:0] _dataflow__delay_data_232; reg _dataflow__delay_valid_232; wire _dataflow__delay_ready_232; assign _dataflow__delay_ready_231 = (_dataflow__delay_ready_232 || !_dataflow__delay_valid_232) && _dataflow__delay_valid_231; reg signed [16-1:0] _dataflow__delay_data_242; reg _dataflow__delay_valid_242; wire _dataflow__delay_ready_242; assign _dataflow__delay_ready_241 = (_dataflow__delay_ready_242 || !_dataflow__delay_valid_242) && _dataflow__delay_valid_241; reg signed [16-1:0] _dataflow__delay_data_252; reg _dataflow__delay_valid_252; wire _dataflow__delay_ready_252; assign _dataflow__delay_ready_251 = (_dataflow__delay_ready_252 || !_dataflow__delay_valid_252) && _dataflow__delay_valid_251; reg signed [16-1:0] _dataflow__delay_data_262; reg _dataflow__delay_valid_262; wire _dataflow__delay_ready_262; assign _dataflow__delay_ready_261 = (_dataflow__delay_ready_262 || !_dataflow__delay_valid_262) && _dataflow__delay_valid_261; reg signed [16-1:0] _dataflow__delay_data_272; reg _dataflow__delay_valid_272; wire _dataflow__delay_ready_272; assign _dataflow__delay_ready_271 = (_dataflow__delay_ready_272 || !_dataflow__delay_valid_272) && _dataflow__delay_valid_271; reg signed [16-1:0] _dataflow__delay_data_291; reg _dataflow__delay_valid_291; wire _dataflow__delay_ready_291; assign _dataflow__delay_ready_290 = (_dataflow__delay_ready_291 || !_dataflow__delay_valid_291) && _dataflow__delay_valid_290; reg signed [16-1:0] _dataflow__delay_data_307; reg _dataflow__delay_valid_307; wire _dataflow__delay_ready_307; assign _dataflow__delay_ready_306 = (_dataflow__delay_ready_307 || !_dataflow__delay_valid_307) && _dataflow__delay_valid_306; reg signed [16-1:0] _dataflow__delay_data_331; reg _dataflow__delay_valid_331; wire _dataflow__delay_ready_331; assign _dataflow__delay_ready_330 = (_dataflow__delay_ready_331 || !_dataflow__delay_valid_331) && _dataflow__delay_valid_330; reg signed [16-1:0] _dataflow__delay_data_181; reg _dataflow__delay_valid_181; wire _dataflow__delay_ready_181; assign _dataflow__delay_ready_180 = (_dataflow__delay_ready_181 || !_dataflow__delay_valid_181) && _dataflow__delay_valid_180; reg signed [16-1:0] _dataflow__delay_data_192; reg _dataflow__delay_valid_192; wire _dataflow__delay_ready_192; assign _dataflow__delay_ready_191 = (_dataflow__delay_ready_192 || !_dataflow__delay_valid_192) && _dataflow__delay_valid_191; reg signed [16-1:0] _dataflow__delay_data_211; reg _dataflow__delay_valid_211; wire _dataflow__delay_ready_211; assign _dataflow__delay_ready_210 = (_dataflow__delay_ready_211 || !_dataflow__delay_valid_211) && _dataflow__delay_valid_210; reg signed [16-1:0] _dataflow__delay_data_222; reg _dataflow__delay_valid_222; wire _dataflow__delay_ready_222; assign _dataflow__delay_ready_221 = (_dataflow__delay_ready_222 || !_dataflow__delay_valid_222) && _dataflow__delay_valid_221; reg signed [16-1:0] _dataflow__delay_data_233; reg _dataflow__delay_valid_233; wire _dataflow__delay_ready_233; assign _dataflow__delay_ready_232 = (_dataflow__delay_ready_233 || !_dataflow__delay_valid_233) && _dataflow__delay_valid_232; reg signed [16-1:0] _dataflow__delay_data_243; reg _dataflow__delay_valid_243; wire _dataflow__delay_ready_243; assign _dataflow__delay_ready_242 = (_dataflow__delay_ready_243 || !_dataflow__delay_valid_243) && _dataflow__delay_valid_242; reg signed [16-1:0] _dataflow__delay_data_253; reg _dataflow__delay_valid_253; wire _dataflow__delay_ready_253; assign _dataflow__delay_ready_252 = (_dataflow__delay_ready_253 || !_dataflow__delay_valid_253) && _dataflow__delay_valid_252; reg signed [16-1:0] _dataflow__delay_data_263; reg _dataflow__delay_valid_263; wire _dataflow__delay_ready_263; assign _dataflow__delay_ready_262 = (_dataflow__delay_ready_263 || !_dataflow__delay_valid_263) && _dataflow__delay_valid_262; reg signed [16-1:0] _dataflow__delay_data_273; reg _dataflow__delay_valid_273; wire _dataflow__delay_ready_273; assign _dataflow__delay_ready_272 = (_dataflow__delay_ready_273 || !_dataflow__delay_valid_273) && _dataflow__delay_valid_272; reg signed [16-1:0] _dataflow__delay_data_292; reg _dataflow__delay_valid_292; wire _dataflow__delay_ready_292; assign _dataflow__delay_ready_291 = (_dataflow__delay_ready_292 || !_dataflow__delay_valid_292) && _dataflow__delay_valid_291; reg signed [16-1:0] _dataflow__delay_data_308; reg _dataflow__delay_valid_308; wire _dataflow__delay_ready_308; assign _dataflow__delay_ready_307 = (_dataflow__delay_ready_308 || !_dataflow__delay_valid_308) && _dataflow__delay_valid_307; reg signed [16-1:0] _dataflow__delay_data_332; reg _dataflow__delay_valid_332; wire _dataflow__delay_ready_332; assign _dataflow__delay_ready_331 = (_dataflow__delay_ready_332 || !_dataflow__delay_valid_332) && _dataflow__delay_valid_331; reg signed [16-1:0] _dataflow_minus_data_48; reg _dataflow_minus_valid_48; wire _dataflow_minus_ready_48; assign _dataflow_times_ready_44 = (_dataflow_minus_ready_48 || !_dataflow_minus_valid_48) && (_dataflow_times_valid_44 && _dataflow_times_valid_45); assign _dataflow_times_ready_45 = (_dataflow_minus_ready_48 || !_dataflow_minus_valid_48) && (_dataflow_times_valid_44 && _dataflow_times_valid_45); reg signed [16-1:0] _dataflow_plus_data_49; reg _dataflow_plus_valid_49; wire _dataflow_plus_ready_49; assign _dataflow_times_ready_46 = (_dataflow_plus_ready_49 || !_dataflow_plus_valid_49) && (_dataflow_times_valid_46 && _dataflow_times_valid_47); assign _dataflow_times_ready_47 = (_dataflow_plus_ready_49 || !_dataflow_plus_valid_49) && (_dataflow_times_valid_46 && _dataflow_times_valid_47); reg signed [16-1:0] _dataflow_minus_data_58; reg _dataflow_minus_valid_58; wire _dataflow_minus_ready_58; assign _dataflow_times_ready_54 = (_dataflow_minus_ready_58 || !_dataflow_minus_valid_58) && (_dataflow_times_valid_54 && _dataflow_times_valid_55); assign _dataflow_times_ready_55 = (_dataflow_minus_ready_58 || !_dataflow_minus_valid_58) && (_dataflow_times_valid_54 && _dataflow_times_valid_55); reg signed [16-1:0] _dataflow_plus_data_59; reg _dataflow_plus_valid_59; wire _dataflow_plus_ready_59; assign _dataflow_times_ready_56 = (_dataflow_plus_ready_59 || !_dataflow_plus_valid_59) && (_dataflow_times_valid_56 && _dataflow_times_valid_57); assign _dataflow_times_ready_57 = (_dataflow_plus_ready_59 || !_dataflow_plus_valid_59) && (_dataflow_times_valid_56 && _dataflow_times_valid_57); reg signed [16-1:0] _dataflow_minus_data_68; reg _dataflow_minus_valid_68; wire _dataflow_minus_ready_68; assign _dataflow_times_ready_64 = (_dataflow_minus_ready_68 || !_dataflow_minus_valid_68) && (_dataflow_times_valid_64 && _dataflow_times_valid_65); assign _dataflow_times_ready_65 = (_dataflow_minus_ready_68 || !_dataflow_minus_valid_68) && (_dataflow_times_valid_64 && _dataflow_times_valid_65); reg signed [16-1:0] _dataflow_plus_data_69; reg _dataflow_plus_valid_69; wire _dataflow_plus_ready_69; assign _dataflow_times_ready_66 = (_dataflow_plus_ready_69 || !_dataflow_plus_valid_69) && (_dataflow_times_valid_66 && _dataflow_times_valid_67); assign _dataflow_times_ready_67 = (_dataflow_plus_ready_69 || !_dataflow_plus_valid_69) && (_dataflow_times_valid_66 && _dataflow_times_valid_67); reg signed [16-1:0] _dataflow_minus_data_78; reg _dataflow_minus_valid_78; wire _dataflow_minus_ready_78; assign _dataflow_times_ready_74 = (_dataflow_minus_ready_78 || !_dataflow_minus_valid_78) && (_dataflow_times_valid_74 && _dataflow_times_valid_75); assign _dataflow_times_ready_75 = (_dataflow_minus_ready_78 || !_dataflow_minus_valid_78) && (_dataflow_times_valid_74 && _dataflow_times_valid_75); reg signed [16-1:0] _dataflow_plus_data_79; reg _dataflow_plus_valid_79; wire _dataflow_plus_ready_79; assign _dataflow_times_ready_76 = (_dataflow_plus_ready_79 || !_dataflow_plus_valid_79) && (_dataflow_times_valid_76 && _dataflow_times_valid_77); assign _dataflow_times_ready_77 = (_dataflow_plus_ready_79 || !_dataflow_plus_valid_79) && (_dataflow_times_valid_76 && _dataflow_times_valid_77); reg signed [16-1:0] _dataflow__delay_data_182; reg _dataflow__delay_valid_182; wire _dataflow__delay_ready_182; assign _dataflow__delay_ready_181 = (_dataflow__delay_ready_182 || !_dataflow__delay_valid_182) && _dataflow__delay_valid_181; reg signed [16-1:0] _dataflow__delay_data_193; reg _dataflow__delay_valid_193; wire _dataflow__delay_ready_193; assign _dataflow__delay_ready_192 = (_dataflow__delay_ready_193 || !_dataflow__delay_valid_193) && _dataflow__delay_valid_192; reg signed [16-1:0] _dataflow__delay_data_212; reg _dataflow__delay_valid_212; wire _dataflow__delay_ready_212; assign _dataflow__delay_ready_211 = (_dataflow__delay_ready_212 || !_dataflow__delay_valid_212) && _dataflow__delay_valid_211; reg signed [16-1:0] _dataflow__delay_data_223; reg _dataflow__delay_valid_223; wire _dataflow__delay_ready_223; assign _dataflow__delay_ready_222 = (_dataflow__delay_ready_223 || !_dataflow__delay_valid_223) && _dataflow__delay_valid_222; reg signed [16-1:0] _dataflow__delay_data_234; reg _dataflow__delay_valid_234; wire _dataflow__delay_ready_234; assign _dataflow__delay_ready_233 = (_dataflow__delay_ready_234 || !_dataflow__delay_valid_234) && _dataflow__delay_valid_233; reg signed [16-1:0] _dataflow__delay_data_244; reg _dataflow__delay_valid_244; wire _dataflow__delay_ready_244; assign _dataflow__delay_ready_243 = (_dataflow__delay_ready_244 || !_dataflow__delay_valid_244) && _dataflow__delay_valid_243; reg signed [16-1:0] _dataflow__delay_data_254; reg _dataflow__delay_valid_254; wire _dataflow__delay_ready_254; assign _dataflow__delay_ready_253 = (_dataflow__delay_ready_254 || !_dataflow__delay_valid_254) && _dataflow__delay_valid_253; reg signed [16-1:0] _dataflow__delay_data_264; reg _dataflow__delay_valid_264; wire _dataflow__delay_ready_264; assign _dataflow__delay_ready_263 = (_dataflow__delay_ready_264 || !_dataflow__delay_valid_264) && _dataflow__delay_valid_263; reg signed [16-1:0] _dataflow__delay_data_274; reg _dataflow__delay_valid_274; wire _dataflow__delay_ready_274; assign _dataflow__delay_ready_273 = (_dataflow__delay_ready_274 || !_dataflow__delay_valid_274) && _dataflow__delay_valid_273; reg signed [16-1:0] _dataflow__delay_data_293; reg _dataflow__delay_valid_293; wire _dataflow__delay_ready_293; assign _dataflow__delay_ready_292 = (_dataflow__delay_ready_293 || !_dataflow__delay_valid_293) && _dataflow__delay_valid_292; reg signed [16-1:0] _dataflow__delay_data_309; reg _dataflow__delay_valid_309; wire _dataflow__delay_ready_309; assign _dataflow__delay_ready_308 = (_dataflow__delay_ready_309 || !_dataflow__delay_valid_309) && _dataflow__delay_valid_308; reg signed [16-1:0] _dataflow__delay_data_333; reg _dataflow__delay_valid_333; wire _dataflow__delay_ready_333; assign _dataflow__delay_ready_332 = (_dataflow__delay_ready_333 || !_dataflow__delay_valid_333) && _dataflow__delay_valid_332; reg signed [16-1:0] _dataflow_minus_data_88; reg _dataflow_minus_valid_88; wire _dataflow_minus_ready_88; assign _dataflow_times_ready_84 = (_dataflow_minus_ready_88 || !_dataflow_minus_valid_88) && (_dataflow_times_valid_84 && _dataflow_times_valid_85); assign _dataflow_times_ready_85 = (_dataflow_minus_ready_88 || !_dataflow_minus_valid_88) && (_dataflow_times_valid_84 && _dataflow_times_valid_85); reg signed [16-1:0] _dataflow_plus_data_89; reg _dataflow_plus_valid_89; wire _dataflow_plus_ready_89; assign _dataflow_times_ready_86 = (_dataflow_plus_ready_89 || !_dataflow_plus_valid_89) && (_dataflow_times_valid_86 && _dataflow_times_valid_87); assign _dataflow_times_ready_87 = (_dataflow_plus_ready_89 || !_dataflow_plus_valid_89) && (_dataflow_times_valid_86 && _dataflow_times_valid_87); reg signed [16-1:0] _dataflow_minus_data_98; reg _dataflow_minus_valid_98; wire _dataflow_minus_ready_98; assign _dataflow_times_ready_94 = (_dataflow_minus_ready_98 || !_dataflow_minus_valid_98) && (_dataflow_times_valid_94 && _dataflow_times_valid_95); assign _dataflow_times_ready_95 = (_dataflow_minus_ready_98 || !_dataflow_minus_valid_98) && (_dataflow_times_valid_94 && _dataflow_times_valid_95); reg signed [16-1:0] _dataflow_plus_data_99; reg _dataflow_plus_valid_99; wire _dataflow_plus_ready_99; assign _dataflow_times_ready_96 = (_dataflow_plus_ready_99 || !_dataflow_plus_valid_99) && (_dataflow_times_valid_96 && _dataflow_times_valid_97); assign _dataflow_times_ready_97 = (_dataflow_plus_ready_99 || !_dataflow_plus_valid_99) && (_dataflow_times_valid_96 && _dataflow_times_valid_97); reg signed [16-1:0] _dataflow_plus_data_100; reg _dataflow_plus_valid_100; wire _dataflow_plus_ready_100; reg signed [16-1:0] _dataflow_plus_data_101; reg _dataflow_plus_valid_101; wire _dataflow_plus_ready_101; reg signed [16-1:0] _dataflow_minus_data_102; reg _dataflow_minus_valid_102; wire _dataflow_minus_ready_102; assign _dataflow_minus_ready_48 = (_dataflow_plus_ready_100 || !_dataflow_plus_valid_100) && (_dataflow_minus_valid_48 && _dataflow_minus_valid_68) && ((_dataflow_minus_ready_102 || !_dataflow_minus_valid_102) && (_dataflow_minus_valid_48 && _dataflow_minus_valid_68)); assign _dataflow_minus_ready_68 = (_dataflow_plus_ready_100 || !_dataflow_plus_valid_100) && (_dataflow_minus_valid_48 && _dataflow_minus_valid_68) && ((_dataflow_minus_ready_102 || !_dataflow_minus_valid_102) && (_dataflow_minus_valid_48 && _dataflow_minus_valid_68)); reg signed [16-1:0] _dataflow_minus_data_103; reg _dataflow_minus_valid_103; wire _dataflow_minus_ready_103; assign _dataflow_plus_ready_49 = (_dataflow_plus_ready_101 || !_dataflow_plus_valid_101) && (_dataflow_plus_valid_49 && _dataflow_plus_valid_69) && ((_dataflow_minus_ready_103 || !_dataflow_minus_valid_103) && (_dataflow_plus_valid_49 && _dataflow_plus_valid_69)); assign _dataflow_plus_ready_69 = (_dataflow_plus_ready_101 || !_dataflow_plus_valid_101) && (_dataflow_plus_valid_49 && _dataflow_plus_valid_69) && ((_dataflow_minus_ready_103 || !_dataflow_minus_valid_103) && (_dataflow_plus_valid_49 && _dataflow_plus_valid_69)); reg signed [16-1:0] _dataflow_plus_data_110; reg _dataflow_plus_valid_110; wire _dataflow_plus_ready_110; reg signed [16-1:0] _dataflow_plus_data_111; reg _dataflow_plus_valid_111; wire _dataflow_plus_ready_111; reg signed [16-1:0] _dataflow_minus_data_112; reg _dataflow_minus_valid_112; wire _dataflow_minus_ready_112; assign _dataflow_minus_ready_58 = (_dataflow_plus_ready_110 || !_dataflow_plus_valid_110) && (_dataflow_minus_valid_58 && _dataflow_minus_valid_78) && ((_dataflow_minus_ready_112 || !_dataflow_minus_valid_112) && (_dataflow_minus_valid_58 && _dataflow_minus_valid_78)); assign _dataflow_minus_ready_78 = (_dataflow_plus_ready_110 || !_dataflow_plus_valid_110) && (_dataflow_minus_valid_58 && _dataflow_minus_valid_78) && ((_dataflow_minus_ready_112 || !_dataflow_minus_valid_112) && (_dataflow_minus_valid_58 && _dataflow_minus_valid_78)); reg signed [16-1:0] _dataflow_minus_data_113; reg _dataflow_minus_valid_113; wire _dataflow_minus_ready_113; assign _dataflow_plus_ready_59 = (_dataflow_plus_ready_111 || !_dataflow_plus_valid_111) && (_dataflow_plus_valid_59 && _dataflow_plus_valid_79) && ((_dataflow_minus_ready_113 || !_dataflow_minus_valid_113) && (_dataflow_plus_valid_59 && _dataflow_plus_valid_79)); assign _dataflow_plus_ready_79 = (_dataflow_plus_ready_111 || !_dataflow_plus_valid_111) && (_dataflow_plus_valid_59 && _dataflow_plus_valid_79) && ((_dataflow_minus_ready_113 || !_dataflow_minus_valid_113) && (_dataflow_plus_valid_59 && _dataflow_plus_valid_79)); reg signed [16-1:0] _dataflow__delay_data_183; reg _dataflow__delay_valid_183; wire _dataflow__delay_ready_183; assign _dataflow__delay_ready_182 = (_dataflow__delay_ready_183 || !_dataflow__delay_valid_183) && _dataflow__delay_valid_182; reg signed [16-1:0] _dataflow__delay_data_194; reg _dataflow__delay_valid_194; wire _dataflow__delay_ready_194; assign _dataflow__delay_ready_193 = (_dataflow__delay_ready_194 || !_dataflow__delay_valid_194) && _dataflow__delay_valid_193; reg signed [16-1:0] _dataflow__delay_data_213; reg _dataflow__delay_valid_213; wire _dataflow__delay_ready_213; assign _dataflow__delay_ready_212 = (_dataflow__delay_ready_213 || !_dataflow__delay_valid_213) && _dataflow__delay_valid_212; reg signed [16-1:0] _dataflow__delay_data_224; reg _dataflow__delay_valid_224; wire _dataflow__delay_ready_224; assign _dataflow__delay_ready_223 = (_dataflow__delay_ready_224 || !_dataflow__delay_valid_224) && _dataflow__delay_valid_223; reg signed [16-1:0] _dataflow__delay_data_235; reg _dataflow__delay_valid_235; wire _dataflow__delay_ready_235; assign _dataflow__delay_ready_234 = (_dataflow__delay_ready_235 || !_dataflow__delay_valid_235) && _dataflow__delay_valid_234; reg signed [16-1:0] _dataflow__delay_data_245; reg _dataflow__delay_valid_245; wire _dataflow__delay_ready_245; assign _dataflow__delay_ready_244 = (_dataflow__delay_ready_245 || !_dataflow__delay_valid_245) && _dataflow__delay_valid_244; reg signed [16-1:0] _dataflow__delay_data_255; reg _dataflow__delay_valid_255; wire _dataflow__delay_ready_255; assign _dataflow__delay_ready_254 = (_dataflow__delay_ready_255 || !_dataflow__delay_valid_255) && _dataflow__delay_valid_254; reg signed [16-1:0] _dataflow__delay_data_265; reg _dataflow__delay_valid_265; wire _dataflow__delay_ready_265; assign _dataflow__delay_ready_264 = (_dataflow__delay_ready_265 || !_dataflow__delay_valid_265) && _dataflow__delay_valid_264; reg signed [16-1:0] _dataflow__delay_data_275; reg _dataflow__delay_valid_275; wire _dataflow__delay_ready_275; assign _dataflow__delay_ready_274 = (_dataflow__delay_ready_275 || !_dataflow__delay_valid_275) && _dataflow__delay_valid_274; reg signed [16-1:0] _dataflow__delay_data_294; reg _dataflow__delay_valid_294; wire _dataflow__delay_ready_294; assign _dataflow__delay_ready_293 = (_dataflow__delay_ready_294 || !_dataflow__delay_valid_294) && _dataflow__delay_valid_293; reg signed [16-1:0] _dataflow__delay_data_310; reg _dataflow__delay_valid_310; wire _dataflow__delay_ready_310; assign _dataflow__delay_ready_309 = (_dataflow__delay_ready_310 || !_dataflow__delay_valid_310) && _dataflow__delay_valid_309; reg signed [16-1:0] _dataflow__delay_data_334; reg _dataflow__delay_valid_334; wire _dataflow__delay_ready_334; assign _dataflow__delay_ready_333 = (_dataflow__delay_ready_334 || !_dataflow__delay_valid_334) && _dataflow__delay_valid_333; wire signed [16-1:0] _dataflow_times_data_104; wire _dataflow_times_valid_104; wire _dataflow_times_ready_104; wire signed [32-1:0] _dataflow_times_mul_odata_104; reg signed [32-1:0] _dataflow_times_mul_odata_reg_104; assign _dataflow_times_data_104 = _dataflow_times_mul_odata_reg_104; wire _dataflow_times_mul_ovalid_104; reg _dataflow_times_mul_valid_reg_104; assign _dataflow_times_valid_104 = _dataflow_times_mul_valid_reg_104; wire _dataflow_times_mul_enable_104; wire _dataflow_times_mul_update_104; assign _dataflow_times_mul_enable_104 = (_dataflow_times_ready_104 || !_dataflow_times_valid_104) && (_dataflow_minus_ready_102 && _dataflow__delay_ready_235) && (_dataflow_minus_valid_102 && _dataflow__delay_valid_235); assign _dataflow_times_mul_update_104 = _dataflow_times_ready_104 || !_dataflow_times_valid_104; multiplier_28 _dataflow_times_mul_104 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_104), .enable(_dataflow_times_mul_enable_104), .valid(_dataflow_times_mul_ovalid_104), .a(_dataflow_minus_data_102), .b(_dataflow__delay_data_235), .c(_dataflow_times_mul_odata_104) ); wire signed [16-1:0] _dataflow_times_data_105; wire _dataflow_times_valid_105; wire _dataflow_times_ready_105; wire signed [32-1:0] _dataflow_times_mul_odata_105; reg signed [32-1:0] _dataflow_times_mul_odata_reg_105; assign _dataflow_times_data_105 = _dataflow_times_mul_odata_reg_105; wire _dataflow_times_mul_ovalid_105; reg _dataflow_times_mul_valid_reg_105; assign _dataflow_times_valid_105 = _dataflow_times_mul_valid_reg_105; wire _dataflow_times_mul_enable_105; wire _dataflow_times_mul_update_105; assign _dataflow_times_mul_enable_105 = (_dataflow_times_ready_105 || !_dataflow_times_valid_105) && (_dataflow_minus_ready_103 && _dataflow__delay_ready_245) && (_dataflow_minus_valid_103 && _dataflow__delay_valid_245); assign _dataflow_times_mul_update_105 = _dataflow_times_ready_105 || !_dataflow_times_valid_105; multiplier_29 _dataflow_times_mul_105 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_105), .enable(_dataflow_times_mul_enable_105), .valid(_dataflow_times_mul_ovalid_105), .a(_dataflow_minus_data_103), .b(_dataflow__delay_data_245), .c(_dataflow_times_mul_odata_105) ); wire signed [16-1:0] _dataflow_times_data_106; wire _dataflow_times_valid_106; wire _dataflow_times_ready_106; wire signed [32-1:0] _dataflow_times_mul_odata_106; reg signed [32-1:0] _dataflow_times_mul_odata_reg_106; assign _dataflow_times_data_106 = _dataflow_times_mul_odata_reg_106; wire _dataflow_times_mul_ovalid_106; reg _dataflow_times_mul_valid_reg_106; assign _dataflow_times_valid_106 = _dataflow_times_mul_valid_reg_106; wire _dataflow_times_mul_enable_106; wire _dataflow_times_mul_update_106; assign _dataflow_times_mul_enable_106 = (_dataflow_times_ready_106 || !_dataflow_times_valid_106) && (_dataflow_minus_ready_102 && _dataflow__delay_ready_245) && (_dataflow_minus_valid_102 && _dataflow__delay_valid_245); assign _dataflow_times_mul_update_106 = _dataflow_times_ready_106 || !_dataflow_times_valid_106; multiplier_30 _dataflow_times_mul_106 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_106), .enable(_dataflow_times_mul_enable_106), .valid(_dataflow_times_mul_ovalid_106), .a(_dataflow_minus_data_102), .b(_dataflow__delay_data_245), .c(_dataflow_times_mul_odata_106) ); assign _dataflow_minus_ready_102 = (_dataflow_times_ready_104 || !_dataflow_times_valid_104) && (_dataflow_minus_valid_102 && _dataflow__delay_valid_235) && ((_dataflow_times_ready_106 || !_dataflow_times_valid_106) && (_dataflow_minus_valid_102 && _dataflow__delay_valid_245)); assign _dataflow__delay_ready_245 = (_dataflow_times_ready_105 || !_dataflow_times_valid_105) && (_dataflow_minus_valid_103 && _dataflow__delay_valid_245) && ((_dataflow_times_ready_106 || !_dataflow_times_valid_106) && (_dataflow_minus_valid_102 && _dataflow__delay_valid_245)); wire signed [16-1:0] _dataflow_times_data_107; wire _dataflow_times_valid_107; wire _dataflow_times_ready_107; wire signed [32-1:0] _dataflow_times_mul_odata_107; reg signed [32-1:0] _dataflow_times_mul_odata_reg_107; assign _dataflow_times_data_107 = _dataflow_times_mul_odata_reg_107; wire _dataflow_times_mul_ovalid_107; reg _dataflow_times_mul_valid_reg_107; assign _dataflow_times_valid_107 = _dataflow_times_mul_valid_reg_107; wire _dataflow_times_mul_enable_107; wire _dataflow_times_mul_update_107; assign _dataflow_times_mul_enable_107 = (_dataflow_times_ready_107 || !_dataflow_times_valid_107) && (_dataflow_minus_ready_103 && _dataflow__delay_ready_235) && (_dataflow_minus_valid_103 && _dataflow__delay_valid_235); assign _dataflow_times_mul_update_107 = _dataflow_times_ready_107 || !_dataflow_times_valid_107; multiplier_31 _dataflow_times_mul_107 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_107), .enable(_dataflow_times_mul_enable_107), .valid(_dataflow_times_mul_ovalid_107), .a(_dataflow_minus_data_103), .b(_dataflow__delay_data_235), .c(_dataflow_times_mul_odata_107) ); assign _dataflow_minus_ready_103 = (_dataflow_times_ready_105 || !_dataflow_times_valid_105) && (_dataflow_minus_valid_103 && _dataflow__delay_valid_245) && ((_dataflow_times_ready_107 || !_dataflow_times_valid_107) && (_dataflow_minus_valid_103 && _dataflow__delay_valid_235)); assign _dataflow__delay_ready_235 = (_dataflow_times_ready_104 || !_dataflow_times_valid_104) && (_dataflow_minus_valid_102 && _dataflow__delay_valid_235) && ((_dataflow_times_ready_107 || !_dataflow_times_valid_107) && (_dataflow_minus_valid_103 && _dataflow__delay_valid_235)); wire signed [16-1:0] _dataflow_times_data_114; wire _dataflow_times_valid_114; wire _dataflow_times_ready_114; wire signed [32-1:0] _dataflow_times_mul_odata_114; reg signed [32-1:0] _dataflow_times_mul_odata_reg_114; assign _dataflow_times_data_114 = _dataflow_times_mul_odata_reg_114; wire _dataflow_times_mul_ovalid_114; reg _dataflow_times_mul_valid_reg_114; assign _dataflow_times_valid_114 = _dataflow_times_mul_valid_reg_114; wire _dataflow_times_mul_enable_114; wire _dataflow_times_mul_update_114; assign _dataflow_times_mul_enable_114 = (_dataflow_times_ready_114 || !_dataflow_times_valid_114) && (_dataflow_minus_ready_112 && _dataflow__delay_ready_255) && (_dataflow_minus_valid_112 && _dataflow__delay_valid_255); assign _dataflow_times_mul_update_114 = _dataflow_times_ready_114 || !_dataflow_times_valid_114; multiplier_32 _dataflow_times_mul_114 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_114), .enable(_dataflow_times_mul_enable_114), .valid(_dataflow_times_mul_ovalid_114), .a(_dataflow_minus_data_112), .b(_dataflow__delay_data_255), .c(_dataflow_times_mul_odata_114) ); wire signed [16-1:0] _dataflow_times_data_115; wire _dataflow_times_valid_115; wire _dataflow_times_ready_115; wire signed [32-1:0] _dataflow_times_mul_odata_115; reg signed [32-1:0] _dataflow_times_mul_odata_reg_115; assign _dataflow_times_data_115 = _dataflow_times_mul_odata_reg_115; wire _dataflow_times_mul_ovalid_115; reg _dataflow_times_mul_valid_reg_115; assign _dataflow_times_valid_115 = _dataflow_times_mul_valid_reg_115; wire _dataflow_times_mul_enable_115; wire _dataflow_times_mul_update_115; assign _dataflow_times_mul_enable_115 = (_dataflow_times_ready_115 || !_dataflow_times_valid_115) && (_dataflow_minus_ready_113 && _dataflow__delay_ready_265) && (_dataflow_minus_valid_113 && _dataflow__delay_valid_265); assign _dataflow_times_mul_update_115 = _dataflow_times_ready_115 || !_dataflow_times_valid_115; multiplier_33 _dataflow_times_mul_115 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_115), .enable(_dataflow_times_mul_enable_115), .valid(_dataflow_times_mul_ovalid_115), .a(_dataflow_minus_data_113), .b(_dataflow__delay_data_265), .c(_dataflow_times_mul_odata_115) ); wire signed [16-1:0] _dataflow_times_data_116; wire _dataflow_times_valid_116; wire _dataflow_times_ready_116; wire signed [32-1:0] _dataflow_times_mul_odata_116; reg signed [32-1:0] _dataflow_times_mul_odata_reg_116; assign _dataflow_times_data_116 = _dataflow_times_mul_odata_reg_116; wire _dataflow_times_mul_ovalid_116; reg _dataflow_times_mul_valid_reg_116; assign _dataflow_times_valid_116 = _dataflow_times_mul_valid_reg_116; wire _dataflow_times_mul_enable_116; wire _dataflow_times_mul_update_116; assign _dataflow_times_mul_enable_116 = (_dataflow_times_ready_116 || !_dataflow_times_valid_116) && (_dataflow_minus_ready_112 && _dataflow__delay_ready_265) && (_dataflow_minus_valid_112 && _dataflow__delay_valid_265); assign _dataflow_times_mul_update_116 = _dataflow_times_ready_116 || !_dataflow_times_valid_116; multiplier_34 _dataflow_times_mul_116 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_116), .enable(_dataflow_times_mul_enable_116), .valid(_dataflow_times_mul_ovalid_116), .a(_dataflow_minus_data_112), .b(_dataflow__delay_data_265), .c(_dataflow_times_mul_odata_116) ); assign _dataflow_minus_ready_112 = (_dataflow_times_ready_114 || !_dataflow_times_valid_114) && (_dataflow_minus_valid_112 && _dataflow__delay_valid_255) && ((_dataflow_times_ready_116 || !_dataflow_times_valid_116) && (_dataflow_minus_valid_112 && _dataflow__delay_valid_265)); assign _dataflow__delay_ready_265 = (_dataflow_times_ready_115 || !_dataflow_times_valid_115) && (_dataflow_minus_valid_113 && _dataflow__delay_valid_265) && ((_dataflow_times_ready_116 || !_dataflow_times_valid_116) && (_dataflow_minus_valid_112 && _dataflow__delay_valid_265)); wire signed [16-1:0] _dataflow_times_data_117; wire _dataflow_times_valid_117; wire _dataflow_times_ready_117; wire signed [32-1:0] _dataflow_times_mul_odata_117; reg signed [32-1:0] _dataflow_times_mul_odata_reg_117; assign _dataflow_times_data_117 = _dataflow_times_mul_odata_reg_117; wire _dataflow_times_mul_ovalid_117; reg _dataflow_times_mul_valid_reg_117; assign _dataflow_times_valid_117 = _dataflow_times_mul_valid_reg_117; wire _dataflow_times_mul_enable_117; wire _dataflow_times_mul_update_117; assign _dataflow_times_mul_enable_117 = (_dataflow_times_ready_117 || !_dataflow_times_valid_117) && (_dataflow_minus_ready_113 && _dataflow__delay_ready_255) && (_dataflow_minus_valid_113 && _dataflow__delay_valid_255); assign _dataflow_times_mul_update_117 = _dataflow_times_ready_117 || !_dataflow_times_valid_117; multiplier_35 _dataflow_times_mul_117 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_117), .enable(_dataflow_times_mul_enable_117), .valid(_dataflow_times_mul_ovalid_117), .a(_dataflow_minus_data_113), .b(_dataflow__delay_data_255), .c(_dataflow_times_mul_odata_117) ); assign _dataflow_minus_ready_113 = (_dataflow_times_ready_115 || !_dataflow_times_valid_115) && (_dataflow_minus_valid_113 && _dataflow__delay_valid_265) && ((_dataflow_times_ready_117 || !_dataflow_times_valid_117) && (_dataflow_minus_valid_113 && _dataflow__delay_valid_255)); assign _dataflow__delay_ready_255 = (_dataflow_times_ready_114 || !_dataflow_times_valid_114) && (_dataflow_minus_valid_112 && _dataflow__delay_valid_255) && ((_dataflow_times_ready_117 || !_dataflow_times_valid_117) && (_dataflow_minus_valid_113 && _dataflow__delay_valid_255)); reg signed [16-1:0] _dataflow_minus_data_128; reg _dataflow_minus_valid_128; wire _dataflow_minus_ready_128; assign _dataflow_times_ready_124 = (_dataflow_minus_ready_128 || !_dataflow_minus_valid_128) && (_dataflow_times_valid_124 && _dataflow_times_valid_125); assign _dataflow_times_ready_125 = (_dataflow_minus_ready_128 || !_dataflow_minus_valid_128) && (_dataflow_times_valid_124 && _dataflow_times_valid_125); reg signed [16-1:0] _dataflow_plus_data_129; reg _dataflow_plus_valid_129; wire _dataflow_plus_ready_129; assign _dataflow_times_ready_126 = (_dataflow_plus_ready_129 || !_dataflow_plus_valid_129) && (_dataflow_times_valid_126 && _dataflow_times_valid_127); assign _dataflow_times_ready_127 = (_dataflow_plus_ready_129 || !_dataflow_plus_valid_129) && (_dataflow_times_valid_126 && _dataflow_times_valid_127); reg signed [16-1:0] _dataflow_plus_data_130; reg _dataflow_plus_valid_130; wire _dataflow_plus_ready_130; reg signed [16-1:0] _dataflow_plus_data_131; reg _dataflow_plus_valid_131; wire _dataflow_plus_ready_131; reg signed [16-1:0] _dataflow_minus_data_132; reg _dataflow_minus_valid_132; wire _dataflow_minus_ready_132; assign _dataflow_minus_ready_88 = (_dataflow_plus_ready_130 || !_dataflow_plus_valid_130) && (_dataflow_minus_valid_88 && _dataflow_minus_valid_98) && ((_dataflow_minus_ready_132 || !_dataflow_minus_valid_132) && (_dataflow_minus_valid_88 && _dataflow_minus_valid_98)); assign _dataflow_minus_ready_98 = (_dataflow_plus_ready_130 || !_dataflow_plus_valid_130) && (_dataflow_minus_valid_88 && _dataflow_minus_valid_98) && ((_dataflow_minus_ready_132 || !_dataflow_minus_valid_132) && (_dataflow_minus_valid_88 && _dataflow_minus_valid_98)); reg signed [16-1:0] _dataflow_minus_data_133; reg _dataflow_minus_valid_133; wire _dataflow_minus_ready_133; assign _dataflow_plus_ready_89 = (_dataflow_plus_ready_131 || !_dataflow_plus_valid_131) && (_dataflow_plus_valid_89 && _dataflow_plus_valid_99) && ((_dataflow_minus_ready_133 || !_dataflow_minus_valid_133) && (_dataflow_plus_valid_89 && _dataflow_plus_valid_99)); assign _dataflow_plus_ready_99 = (_dataflow_plus_ready_131 || !_dataflow_plus_valid_131) && (_dataflow_plus_valid_89 && _dataflow_plus_valid_99) && ((_dataflow_minus_ready_133 || !_dataflow_minus_valid_133) && (_dataflow_plus_valid_89 && _dataflow_plus_valid_99)); reg signed [16-1:0] _dataflow_plus_data_140; reg _dataflow_plus_valid_140; wire _dataflow_plus_ready_140; reg signed [16-1:0] _dataflow_plus_data_141; reg _dataflow_plus_valid_141; wire _dataflow_plus_ready_141; reg signed [16-1:0] _dataflow_minus_data_142; reg _dataflow_minus_valid_142; wire _dataflow_minus_ready_142; assign _dataflow_plus_ready_100 = (_dataflow_plus_ready_140 || !_dataflow_plus_valid_140) && (_dataflow_plus_valid_100 && _dataflow_plus_valid_110) && ((_dataflow_minus_ready_142 || !_dataflow_minus_valid_142) && (_dataflow_plus_valid_100 && _dataflow_plus_valid_110)); assign _dataflow_plus_ready_110 = (_dataflow_plus_ready_140 || !_dataflow_plus_valid_140) && (_dataflow_plus_valid_100 && _dataflow_plus_valid_110) && ((_dataflow_minus_ready_142 || !_dataflow_minus_valid_142) && (_dataflow_plus_valid_100 && _dataflow_plus_valid_110)); reg signed [16-1:0] _dataflow_minus_data_143; reg _dataflow_minus_valid_143; wire _dataflow_minus_ready_143; assign _dataflow_plus_ready_101 = (_dataflow_plus_ready_141 || !_dataflow_plus_valid_141) && (_dataflow_plus_valid_101 && _dataflow_plus_valid_111) && ((_dataflow_minus_ready_143 || !_dataflow_minus_valid_143) && (_dataflow_plus_valid_101 && _dataflow_plus_valid_111)); assign _dataflow_plus_ready_111 = (_dataflow_plus_ready_141 || !_dataflow_plus_valid_141) && (_dataflow_plus_valid_101 && _dataflow_plus_valid_111) && ((_dataflow_minus_ready_143 || !_dataflow_minus_valid_143) && (_dataflow_plus_valid_101 && _dataflow_plus_valid_111)); reg signed [16-1:0] _dataflow__delay_data_184; reg _dataflow__delay_valid_184; wire _dataflow__delay_ready_184; assign _dataflow__delay_ready_183 = (_dataflow__delay_ready_184 || !_dataflow__delay_valid_184) && _dataflow__delay_valid_183; reg signed [16-1:0] _dataflow__delay_data_195; reg _dataflow__delay_valid_195; wire _dataflow__delay_ready_195; assign _dataflow__delay_ready_194 = (_dataflow__delay_ready_195 || !_dataflow__delay_valid_195) && _dataflow__delay_valid_194; reg signed [16-1:0] _dataflow__delay_data_214; reg _dataflow__delay_valid_214; wire _dataflow__delay_ready_214; assign _dataflow__delay_ready_213 = (_dataflow__delay_ready_214 || !_dataflow__delay_valid_214) && _dataflow__delay_valid_213; reg signed [16-1:0] _dataflow__delay_data_225; reg _dataflow__delay_valid_225; wire _dataflow__delay_ready_225; assign _dataflow__delay_ready_224 = (_dataflow__delay_ready_225 || !_dataflow__delay_valid_225) && _dataflow__delay_valid_224; reg signed [16-1:0] _dataflow__delay_data_276; reg _dataflow__delay_valid_276; wire _dataflow__delay_ready_276; assign _dataflow__delay_ready_275 = (_dataflow__delay_ready_276 || !_dataflow__delay_valid_276) && _dataflow__delay_valid_275; reg signed [16-1:0] _dataflow__delay_data_295; reg _dataflow__delay_valid_295; wire _dataflow__delay_ready_295; assign _dataflow__delay_ready_294 = (_dataflow__delay_ready_295 || !_dataflow__delay_valid_295) && _dataflow__delay_valid_294; reg signed [16-1:0] _dataflow__delay_data_311; reg _dataflow__delay_valid_311; wire _dataflow__delay_ready_311; assign _dataflow__delay_ready_310 = (_dataflow__delay_ready_311 || !_dataflow__delay_valid_311) && _dataflow__delay_valid_310; reg signed [16-1:0] _dataflow__delay_data_335; reg _dataflow__delay_valid_335; wire _dataflow__delay_ready_335; assign _dataflow__delay_ready_334 = (_dataflow__delay_ready_335 || !_dataflow__delay_valid_335) && _dataflow__delay_valid_334; wire signed [16-1:0] _dataflow_times_data_134; wire _dataflow_times_valid_134; wire _dataflow_times_ready_134; wire signed [32-1:0] _dataflow_times_mul_odata_134; reg signed [32-1:0] _dataflow_times_mul_odata_reg_134; assign _dataflow_times_data_134 = _dataflow_times_mul_odata_reg_134; wire _dataflow_times_mul_ovalid_134; reg _dataflow_times_mul_valid_reg_134; assign _dataflow_times_valid_134 = _dataflow_times_mul_valid_reg_134; wire _dataflow_times_mul_enable_134; wire _dataflow_times_mul_update_134; assign _dataflow_times_mul_enable_134 = (_dataflow_times_ready_134 || !_dataflow_times_valid_134) && (_dataflow_minus_ready_132 && _dataflow__delay_ready_184) && (_dataflow_minus_valid_132 && _dataflow__delay_valid_184); assign _dataflow_times_mul_update_134 = _dataflow_times_ready_134 || !_dataflow_times_valid_134; multiplier_36 _dataflow_times_mul_134 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_134), .enable(_dataflow_times_mul_enable_134), .valid(_dataflow_times_mul_ovalid_134), .a(_dataflow_minus_data_132), .b(_dataflow__delay_data_184), .c(_dataflow_times_mul_odata_134) ); wire signed [16-1:0] _dataflow_times_data_135; wire _dataflow_times_valid_135; wire _dataflow_times_ready_135; wire signed [32-1:0] _dataflow_times_mul_odata_135; reg signed [32-1:0] _dataflow_times_mul_odata_reg_135; assign _dataflow_times_data_135 = _dataflow_times_mul_odata_reg_135; wire _dataflow_times_mul_ovalid_135; reg _dataflow_times_mul_valid_reg_135; assign _dataflow_times_valid_135 = _dataflow_times_mul_valid_reg_135; wire _dataflow_times_mul_enable_135; wire _dataflow_times_mul_update_135; assign _dataflow_times_mul_enable_135 = (_dataflow_times_ready_135 || !_dataflow_times_valid_135) && (_dataflow_minus_ready_133 && _dataflow__delay_ready_195) && (_dataflow_minus_valid_133 && _dataflow__delay_valid_195); assign _dataflow_times_mul_update_135 = _dataflow_times_ready_135 || !_dataflow_times_valid_135; multiplier_37 _dataflow_times_mul_135 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_135), .enable(_dataflow_times_mul_enable_135), .valid(_dataflow_times_mul_ovalid_135), .a(_dataflow_minus_data_133), .b(_dataflow__delay_data_195), .c(_dataflow_times_mul_odata_135) ); wire signed [16-1:0] _dataflow_times_data_136; wire _dataflow_times_valid_136; wire _dataflow_times_ready_136; wire signed [32-1:0] _dataflow_times_mul_odata_136; reg signed [32-1:0] _dataflow_times_mul_odata_reg_136; assign _dataflow_times_data_136 = _dataflow_times_mul_odata_reg_136; wire _dataflow_times_mul_ovalid_136; reg _dataflow_times_mul_valid_reg_136; assign _dataflow_times_valid_136 = _dataflow_times_mul_valid_reg_136; wire _dataflow_times_mul_enable_136; wire _dataflow_times_mul_update_136; assign _dataflow_times_mul_enable_136 = (_dataflow_times_ready_136 || !_dataflow_times_valid_136) && (_dataflow_minus_ready_132 && _dataflow__delay_ready_195) && (_dataflow_minus_valid_132 && _dataflow__delay_valid_195); assign _dataflow_times_mul_update_136 = _dataflow_times_ready_136 || !_dataflow_times_valid_136; multiplier_38 _dataflow_times_mul_136 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_136), .enable(_dataflow_times_mul_enable_136), .valid(_dataflow_times_mul_ovalid_136), .a(_dataflow_minus_data_132), .b(_dataflow__delay_data_195), .c(_dataflow_times_mul_odata_136) ); assign _dataflow_minus_ready_132 = (_dataflow_times_ready_134 || !_dataflow_times_valid_134) && (_dataflow_minus_valid_132 && _dataflow__delay_valid_184) && ((_dataflow_times_ready_136 || !_dataflow_times_valid_136) && (_dataflow_minus_valid_132 && _dataflow__delay_valid_195)); assign _dataflow__delay_ready_195 = (_dataflow_times_ready_135 || !_dataflow_times_valid_135) && (_dataflow_minus_valid_133 && _dataflow__delay_valid_195) && ((_dataflow_times_ready_136 || !_dataflow_times_valid_136) && (_dataflow_minus_valid_132 && _dataflow__delay_valid_195)); wire signed [16-1:0] _dataflow_times_data_137; wire _dataflow_times_valid_137; wire _dataflow_times_ready_137; wire signed [32-1:0] _dataflow_times_mul_odata_137; reg signed [32-1:0] _dataflow_times_mul_odata_reg_137; assign _dataflow_times_data_137 = _dataflow_times_mul_odata_reg_137; wire _dataflow_times_mul_ovalid_137; reg _dataflow_times_mul_valid_reg_137; assign _dataflow_times_valid_137 = _dataflow_times_mul_valid_reg_137; wire _dataflow_times_mul_enable_137; wire _dataflow_times_mul_update_137; assign _dataflow_times_mul_enable_137 = (_dataflow_times_ready_137 || !_dataflow_times_valid_137) && (_dataflow_minus_ready_133 && _dataflow__delay_ready_184) && (_dataflow_minus_valid_133 && _dataflow__delay_valid_184); assign _dataflow_times_mul_update_137 = _dataflow_times_ready_137 || !_dataflow_times_valid_137; multiplier_39 _dataflow_times_mul_137 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_137), .enable(_dataflow_times_mul_enable_137), .valid(_dataflow_times_mul_ovalid_137), .a(_dataflow_minus_data_133), .b(_dataflow__delay_data_184), .c(_dataflow_times_mul_odata_137) ); assign _dataflow_minus_ready_133 = (_dataflow_times_ready_135 || !_dataflow_times_valid_135) && (_dataflow_minus_valid_133 && _dataflow__delay_valid_195) && ((_dataflow_times_ready_137 || !_dataflow_times_valid_137) && (_dataflow_minus_valid_133 && _dataflow__delay_valid_184)); assign _dataflow__delay_ready_184 = (_dataflow_times_ready_134 || !_dataflow_times_valid_134) && (_dataflow_minus_valid_132 && _dataflow__delay_valid_184) && ((_dataflow_times_ready_137 || !_dataflow_times_valid_137) && (_dataflow_minus_valid_133 && _dataflow__delay_valid_184)); wire signed [16-1:0] _dataflow_times_data_144; wire _dataflow_times_valid_144; wire _dataflow_times_ready_144; wire signed [32-1:0] _dataflow_times_mul_odata_144; reg signed [32-1:0] _dataflow_times_mul_odata_reg_144; assign _dataflow_times_data_144 = _dataflow_times_mul_odata_reg_144; wire _dataflow_times_mul_ovalid_144; reg _dataflow_times_mul_valid_reg_144; assign _dataflow_times_valid_144 = _dataflow_times_mul_valid_reg_144; wire _dataflow_times_mul_enable_144; wire _dataflow_times_mul_update_144; assign _dataflow_times_mul_enable_144 = (_dataflow_times_ready_144 || !_dataflow_times_valid_144) && (_dataflow_minus_ready_142 && _dataflow__delay_ready_214) && (_dataflow_minus_valid_142 && _dataflow__delay_valid_214); assign _dataflow_times_mul_update_144 = _dataflow_times_ready_144 || !_dataflow_times_valid_144; multiplier_40 _dataflow_times_mul_144 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_144), .enable(_dataflow_times_mul_enable_144), .valid(_dataflow_times_mul_ovalid_144), .a(_dataflow_minus_data_142), .b(_dataflow__delay_data_214), .c(_dataflow_times_mul_odata_144) ); wire signed [16-1:0] _dataflow_times_data_145; wire _dataflow_times_valid_145; wire _dataflow_times_ready_145; wire signed [32-1:0] _dataflow_times_mul_odata_145; reg signed [32-1:0] _dataflow_times_mul_odata_reg_145; assign _dataflow_times_data_145 = _dataflow_times_mul_odata_reg_145; wire _dataflow_times_mul_ovalid_145; reg _dataflow_times_mul_valid_reg_145; assign _dataflow_times_valid_145 = _dataflow_times_mul_valid_reg_145; wire _dataflow_times_mul_enable_145; wire _dataflow_times_mul_update_145; assign _dataflow_times_mul_enable_145 = (_dataflow_times_ready_145 || !_dataflow_times_valid_145) && (_dataflow_minus_ready_143 && _dataflow__delay_ready_225) && (_dataflow_minus_valid_143 && _dataflow__delay_valid_225); assign _dataflow_times_mul_update_145 = _dataflow_times_ready_145 || !_dataflow_times_valid_145; multiplier_41 _dataflow_times_mul_145 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_145), .enable(_dataflow_times_mul_enable_145), .valid(_dataflow_times_mul_ovalid_145), .a(_dataflow_minus_data_143), .b(_dataflow__delay_data_225), .c(_dataflow_times_mul_odata_145) ); wire signed [16-1:0] _dataflow_times_data_146; wire _dataflow_times_valid_146; wire _dataflow_times_ready_146; wire signed [32-1:0] _dataflow_times_mul_odata_146; reg signed [32-1:0] _dataflow_times_mul_odata_reg_146; assign _dataflow_times_data_146 = _dataflow_times_mul_odata_reg_146; wire _dataflow_times_mul_ovalid_146; reg _dataflow_times_mul_valid_reg_146; assign _dataflow_times_valid_146 = _dataflow_times_mul_valid_reg_146; wire _dataflow_times_mul_enable_146; wire _dataflow_times_mul_update_146; assign _dataflow_times_mul_enable_146 = (_dataflow_times_ready_146 || !_dataflow_times_valid_146) && (_dataflow_minus_ready_142 && _dataflow__delay_ready_225) && (_dataflow_minus_valid_142 && _dataflow__delay_valid_225); assign _dataflow_times_mul_update_146 = _dataflow_times_ready_146 || !_dataflow_times_valid_146; multiplier_42 _dataflow_times_mul_146 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_146), .enable(_dataflow_times_mul_enable_146), .valid(_dataflow_times_mul_ovalid_146), .a(_dataflow_minus_data_142), .b(_dataflow__delay_data_225), .c(_dataflow_times_mul_odata_146) ); assign _dataflow_minus_ready_142 = (_dataflow_times_ready_144 || !_dataflow_times_valid_144) && (_dataflow_minus_valid_142 && _dataflow__delay_valid_214) && ((_dataflow_times_ready_146 || !_dataflow_times_valid_146) && (_dataflow_minus_valid_142 && _dataflow__delay_valid_225)); assign _dataflow__delay_ready_225 = (_dataflow_times_ready_145 || !_dataflow_times_valid_145) && (_dataflow_minus_valid_143 && _dataflow__delay_valid_225) && ((_dataflow_times_ready_146 || !_dataflow_times_valid_146) && (_dataflow_minus_valid_142 && _dataflow__delay_valid_225)); wire signed [16-1:0] _dataflow_times_data_147; wire _dataflow_times_valid_147; wire _dataflow_times_ready_147; wire signed [32-1:0] _dataflow_times_mul_odata_147; reg signed [32-1:0] _dataflow_times_mul_odata_reg_147; assign _dataflow_times_data_147 = _dataflow_times_mul_odata_reg_147; wire _dataflow_times_mul_ovalid_147; reg _dataflow_times_mul_valid_reg_147; assign _dataflow_times_valid_147 = _dataflow_times_mul_valid_reg_147; wire _dataflow_times_mul_enable_147; wire _dataflow_times_mul_update_147; assign _dataflow_times_mul_enable_147 = (_dataflow_times_ready_147 || !_dataflow_times_valid_147) && (_dataflow_minus_ready_143 && _dataflow__delay_ready_214) && (_dataflow_minus_valid_143 && _dataflow__delay_valid_214); assign _dataflow_times_mul_update_147 = _dataflow_times_ready_147 || !_dataflow_times_valid_147; multiplier_43 _dataflow_times_mul_147 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_147), .enable(_dataflow_times_mul_enable_147), .valid(_dataflow_times_mul_ovalid_147), .a(_dataflow_minus_data_143), .b(_dataflow__delay_data_214), .c(_dataflow_times_mul_odata_147) ); assign _dataflow_minus_ready_143 = (_dataflow_times_ready_145 || !_dataflow_times_valid_145) && (_dataflow_minus_valid_143 && _dataflow__delay_valid_225) && ((_dataflow_times_ready_147 || !_dataflow_times_valid_147) && (_dataflow_minus_valid_143 && _dataflow__delay_valid_214)); assign _dataflow__delay_ready_214 = (_dataflow_times_ready_144 || !_dataflow_times_valid_144) && (_dataflow_minus_valid_142 && _dataflow__delay_valid_214) && ((_dataflow_times_ready_147 || !_dataflow_times_valid_147) && (_dataflow_minus_valid_143 && _dataflow__delay_valid_214)); reg signed [16-1:0] _dataflow__delay_data_277; reg _dataflow__delay_valid_277; wire _dataflow__delay_ready_277; assign _dataflow__delay_ready_276 = (_dataflow__delay_ready_277 || !_dataflow__delay_valid_277) && _dataflow__delay_valid_276; reg signed [16-1:0] _dataflow__delay_data_296; reg _dataflow__delay_valid_296; wire _dataflow__delay_ready_296; assign _dataflow__delay_ready_295 = (_dataflow__delay_ready_296 || !_dataflow__delay_valid_296) && _dataflow__delay_valid_295; reg signed [16-1:0] _dataflow__delay_data_312; reg _dataflow__delay_valid_312; wire _dataflow__delay_ready_312; assign _dataflow__delay_ready_311 = (_dataflow__delay_ready_312 || !_dataflow__delay_valid_312) && _dataflow__delay_valid_311; reg signed [16-1:0] _dataflow__delay_data_336; reg _dataflow__delay_valid_336; wire _dataflow__delay_ready_336; assign _dataflow__delay_ready_335 = (_dataflow__delay_ready_336 || !_dataflow__delay_valid_336) && _dataflow__delay_valid_335; reg signed [16-1:0] _dataflow__delay_data_352; reg _dataflow__delay_valid_352; wire _dataflow__delay_ready_352; assign _dataflow_minus_ready_128 = (_dataflow__delay_ready_352 || !_dataflow__delay_valid_352) && _dataflow_minus_valid_128; reg signed [16-1:0] _dataflow__delay_data_368; reg _dataflow__delay_valid_368; wire _dataflow__delay_ready_368; assign _dataflow_plus_ready_129 = (_dataflow__delay_ready_368 || !_dataflow__delay_valid_368) && _dataflow_plus_valid_129; reg signed [16-1:0] _dataflow__delay_data_384; reg _dataflow__delay_valid_384; wire _dataflow__delay_ready_384; assign _dataflow_plus_ready_130 = (_dataflow__delay_ready_384 || !_dataflow__delay_valid_384) && _dataflow_plus_valid_130; reg signed [16-1:0] _dataflow__delay_data_400; reg _dataflow__delay_valid_400; wire _dataflow__delay_ready_400; assign _dataflow_plus_ready_131 = (_dataflow__delay_ready_400 || !_dataflow__delay_valid_400) && _dataflow_plus_valid_131; reg signed [16-1:0] _dataflow__delay_data_432; reg _dataflow__delay_valid_432; wire _dataflow__delay_ready_432; assign _dataflow_plus_ready_140 = (_dataflow__delay_ready_432 || !_dataflow__delay_valid_432) && _dataflow_plus_valid_140; reg signed [16-1:0] _dataflow__delay_data_448; reg _dataflow__delay_valid_448; wire _dataflow__delay_ready_448; assign _dataflow_plus_ready_141 = (_dataflow__delay_ready_448 || !_dataflow__delay_valid_448) && _dataflow_plus_valid_141; reg signed [16-1:0] _dataflow__delay_data_278; reg _dataflow__delay_valid_278; wire _dataflow__delay_ready_278; assign _dataflow__delay_ready_277 = (_dataflow__delay_ready_278 || !_dataflow__delay_valid_278) && _dataflow__delay_valid_277; reg signed [16-1:0] _dataflow__delay_data_297; reg _dataflow__delay_valid_297; wire _dataflow__delay_ready_297; assign _dataflow__delay_ready_296 = (_dataflow__delay_ready_297 || !_dataflow__delay_valid_297) && _dataflow__delay_valid_296; reg signed [16-1:0] _dataflow__delay_data_313; reg _dataflow__delay_valid_313; wire _dataflow__delay_ready_313; assign _dataflow__delay_ready_312 = (_dataflow__delay_ready_313 || !_dataflow__delay_valid_313) && _dataflow__delay_valid_312; reg signed [16-1:0] _dataflow__delay_data_337; reg _dataflow__delay_valid_337; wire _dataflow__delay_ready_337; assign _dataflow__delay_ready_336 = (_dataflow__delay_ready_337 || !_dataflow__delay_valid_337) && _dataflow__delay_valid_336; reg signed [16-1:0] _dataflow__delay_data_353; reg _dataflow__delay_valid_353; wire _dataflow__delay_ready_353; assign _dataflow__delay_ready_352 = (_dataflow__delay_ready_353 || !_dataflow__delay_valid_353) && _dataflow__delay_valid_352; reg signed [16-1:0] _dataflow__delay_data_369; reg _dataflow__delay_valid_369; wire _dataflow__delay_ready_369; assign _dataflow__delay_ready_368 = (_dataflow__delay_ready_369 || !_dataflow__delay_valid_369) && _dataflow__delay_valid_368; reg signed [16-1:0] _dataflow__delay_data_385; reg _dataflow__delay_valid_385; wire _dataflow__delay_ready_385; assign _dataflow__delay_ready_384 = (_dataflow__delay_ready_385 || !_dataflow__delay_valid_385) && _dataflow__delay_valid_384; reg signed [16-1:0] _dataflow__delay_data_401; reg _dataflow__delay_valid_401; wire _dataflow__delay_ready_401; assign _dataflow__delay_ready_400 = (_dataflow__delay_ready_401 || !_dataflow__delay_valid_401) && _dataflow__delay_valid_400; reg signed [16-1:0] _dataflow__delay_data_433; reg _dataflow__delay_valid_433; wire _dataflow__delay_ready_433; assign _dataflow__delay_ready_432 = (_dataflow__delay_ready_433 || !_dataflow__delay_valid_433) && _dataflow__delay_valid_432; reg signed [16-1:0] _dataflow__delay_data_449; reg _dataflow__delay_valid_449; wire _dataflow__delay_ready_449; assign _dataflow__delay_ready_448 = (_dataflow__delay_ready_449 || !_dataflow__delay_valid_449) && _dataflow__delay_valid_448; reg signed [16-1:0] _dataflow__delay_data_279; reg _dataflow__delay_valid_279; wire _dataflow__delay_ready_279; assign _dataflow__delay_ready_278 = (_dataflow__delay_ready_279 || !_dataflow__delay_valid_279) && _dataflow__delay_valid_278; reg signed [16-1:0] _dataflow__delay_data_298; reg _dataflow__delay_valid_298; wire _dataflow__delay_ready_298; assign _dataflow__delay_ready_297 = (_dataflow__delay_ready_298 || !_dataflow__delay_valid_298) && _dataflow__delay_valid_297; reg signed [16-1:0] _dataflow__delay_data_314; reg _dataflow__delay_valid_314; wire _dataflow__delay_ready_314; assign _dataflow__delay_ready_313 = (_dataflow__delay_ready_314 || !_dataflow__delay_valid_314) && _dataflow__delay_valid_313; reg signed [16-1:0] _dataflow__delay_data_338; reg _dataflow__delay_valid_338; wire _dataflow__delay_ready_338; assign _dataflow__delay_ready_337 = (_dataflow__delay_ready_338 || !_dataflow__delay_valid_338) && _dataflow__delay_valid_337; reg signed [16-1:0] _dataflow__delay_data_354; reg _dataflow__delay_valid_354; wire _dataflow__delay_ready_354; assign _dataflow__delay_ready_353 = (_dataflow__delay_ready_354 || !_dataflow__delay_valid_354) && _dataflow__delay_valid_353; reg signed [16-1:0] _dataflow__delay_data_370; reg _dataflow__delay_valid_370; wire _dataflow__delay_ready_370; assign _dataflow__delay_ready_369 = (_dataflow__delay_ready_370 || !_dataflow__delay_valid_370) && _dataflow__delay_valid_369; reg signed [16-1:0] _dataflow__delay_data_386; reg _dataflow__delay_valid_386; wire _dataflow__delay_ready_386; assign _dataflow__delay_ready_385 = (_dataflow__delay_ready_386 || !_dataflow__delay_valid_386) && _dataflow__delay_valid_385; reg signed [16-1:0] _dataflow__delay_data_402; reg _dataflow__delay_valid_402; wire _dataflow__delay_ready_402; assign _dataflow__delay_ready_401 = (_dataflow__delay_ready_402 || !_dataflow__delay_valid_402) && _dataflow__delay_valid_401; reg signed [16-1:0] _dataflow__delay_data_434; reg _dataflow__delay_valid_434; wire _dataflow__delay_ready_434; assign _dataflow__delay_ready_433 = (_dataflow__delay_ready_434 || !_dataflow__delay_valid_434) && _dataflow__delay_valid_433; reg signed [16-1:0] _dataflow__delay_data_450; reg _dataflow__delay_valid_450; wire _dataflow__delay_ready_450; assign _dataflow__delay_ready_449 = (_dataflow__delay_ready_450 || !_dataflow__delay_valid_450) && _dataflow__delay_valid_449; reg signed [16-1:0] _dataflow__delay_data_280; reg _dataflow__delay_valid_280; wire _dataflow__delay_ready_280; assign _dataflow__delay_ready_279 = (_dataflow__delay_ready_280 || !_dataflow__delay_valid_280) && _dataflow__delay_valid_279; reg signed [16-1:0] _dataflow__delay_data_299; reg _dataflow__delay_valid_299; wire _dataflow__delay_ready_299; assign _dataflow__delay_ready_298 = (_dataflow__delay_ready_299 || !_dataflow__delay_valid_299) && _dataflow__delay_valid_298; reg signed [16-1:0] _dataflow__delay_data_315; reg _dataflow__delay_valid_315; wire _dataflow__delay_ready_315; assign _dataflow__delay_ready_314 = (_dataflow__delay_ready_315 || !_dataflow__delay_valid_315) && _dataflow__delay_valid_314; reg signed [16-1:0] _dataflow__delay_data_339; reg _dataflow__delay_valid_339; wire _dataflow__delay_ready_339; assign _dataflow__delay_ready_338 = (_dataflow__delay_ready_339 || !_dataflow__delay_valid_339) && _dataflow__delay_valid_338; reg signed [16-1:0] _dataflow__delay_data_355; reg _dataflow__delay_valid_355; wire _dataflow__delay_ready_355; assign _dataflow__delay_ready_354 = (_dataflow__delay_ready_355 || !_dataflow__delay_valid_355) && _dataflow__delay_valid_354; reg signed [16-1:0] _dataflow__delay_data_371; reg _dataflow__delay_valid_371; wire _dataflow__delay_ready_371; assign _dataflow__delay_ready_370 = (_dataflow__delay_ready_371 || !_dataflow__delay_valid_371) && _dataflow__delay_valid_370; reg signed [16-1:0] _dataflow__delay_data_387; reg _dataflow__delay_valid_387; wire _dataflow__delay_ready_387; assign _dataflow__delay_ready_386 = (_dataflow__delay_ready_387 || !_dataflow__delay_valid_387) && _dataflow__delay_valid_386; reg signed [16-1:0] _dataflow__delay_data_403; reg _dataflow__delay_valid_403; wire _dataflow__delay_ready_403; assign _dataflow__delay_ready_402 = (_dataflow__delay_ready_403 || !_dataflow__delay_valid_403) && _dataflow__delay_valid_402; reg signed [16-1:0] _dataflow__delay_data_435; reg _dataflow__delay_valid_435; wire _dataflow__delay_ready_435; assign _dataflow__delay_ready_434 = (_dataflow__delay_ready_435 || !_dataflow__delay_valid_435) && _dataflow__delay_valid_434; reg signed [16-1:0] _dataflow__delay_data_451; reg _dataflow__delay_valid_451; wire _dataflow__delay_ready_451; assign _dataflow__delay_ready_450 = (_dataflow__delay_ready_451 || !_dataflow__delay_valid_451) && _dataflow__delay_valid_450; reg signed [16-1:0] _dataflow__delay_data_281; reg _dataflow__delay_valid_281; wire _dataflow__delay_ready_281; assign _dataflow__delay_ready_280 = (_dataflow__delay_ready_281 || !_dataflow__delay_valid_281) && _dataflow__delay_valid_280; reg signed [16-1:0] _dataflow__delay_data_300; reg _dataflow__delay_valid_300; wire _dataflow__delay_ready_300; assign _dataflow__delay_ready_299 = (_dataflow__delay_ready_300 || !_dataflow__delay_valid_300) && _dataflow__delay_valid_299; reg signed [16-1:0] _dataflow__delay_data_316; reg _dataflow__delay_valid_316; wire _dataflow__delay_ready_316; assign _dataflow__delay_ready_315 = (_dataflow__delay_ready_316 || !_dataflow__delay_valid_316) && _dataflow__delay_valid_315; reg signed [16-1:0] _dataflow__delay_data_340; reg _dataflow__delay_valid_340; wire _dataflow__delay_ready_340; assign _dataflow__delay_ready_339 = (_dataflow__delay_ready_340 || !_dataflow__delay_valid_340) && _dataflow__delay_valid_339; reg signed [16-1:0] _dataflow__delay_data_356; reg _dataflow__delay_valid_356; wire _dataflow__delay_ready_356; assign _dataflow__delay_ready_355 = (_dataflow__delay_ready_356 || !_dataflow__delay_valid_356) && _dataflow__delay_valid_355; reg signed [16-1:0] _dataflow__delay_data_372; reg _dataflow__delay_valid_372; wire _dataflow__delay_ready_372; assign _dataflow__delay_ready_371 = (_dataflow__delay_ready_372 || !_dataflow__delay_valid_372) && _dataflow__delay_valid_371; reg signed [16-1:0] _dataflow__delay_data_388; reg _dataflow__delay_valid_388; wire _dataflow__delay_ready_388; assign _dataflow__delay_ready_387 = (_dataflow__delay_ready_388 || !_dataflow__delay_valid_388) && _dataflow__delay_valid_387; reg signed [16-1:0] _dataflow__delay_data_404; reg _dataflow__delay_valid_404; wire _dataflow__delay_ready_404; assign _dataflow__delay_ready_403 = (_dataflow__delay_ready_404 || !_dataflow__delay_valid_404) && _dataflow__delay_valid_403; reg signed [16-1:0] _dataflow__delay_data_436; reg _dataflow__delay_valid_436; wire _dataflow__delay_ready_436; assign _dataflow__delay_ready_435 = (_dataflow__delay_ready_436 || !_dataflow__delay_valid_436) && _dataflow__delay_valid_435; reg signed [16-1:0] _dataflow__delay_data_452; reg _dataflow__delay_valid_452; wire _dataflow__delay_ready_452; assign _dataflow__delay_ready_451 = (_dataflow__delay_ready_452 || !_dataflow__delay_valid_452) && _dataflow__delay_valid_451; reg signed [16-1:0] _dataflow__delay_data_282; reg _dataflow__delay_valid_282; wire _dataflow__delay_ready_282; assign _dataflow__delay_ready_281 = (_dataflow__delay_ready_282 || !_dataflow__delay_valid_282) && _dataflow__delay_valid_281; reg signed [16-1:0] _dataflow__delay_data_301; reg _dataflow__delay_valid_301; wire _dataflow__delay_ready_301; assign _dataflow__delay_ready_300 = (_dataflow__delay_ready_301 || !_dataflow__delay_valid_301) && _dataflow__delay_valid_300; reg signed [16-1:0] _dataflow__delay_data_317; reg _dataflow__delay_valid_317; wire _dataflow__delay_ready_317; assign _dataflow__delay_ready_316 = (_dataflow__delay_ready_317 || !_dataflow__delay_valid_317) && _dataflow__delay_valid_316; reg signed [16-1:0] _dataflow__delay_data_341; reg _dataflow__delay_valid_341; wire _dataflow__delay_ready_341; assign _dataflow__delay_ready_340 = (_dataflow__delay_ready_341 || !_dataflow__delay_valid_341) && _dataflow__delay_valid_340; reg signed [16-1:0] _dataflow__delay_data_357; reg _dataflow__delay_valid_357; wire _dataflow__delay_ready_357; assign _dataflow__delay_ready_356 = (_dataflow__delay_ready_357 || !_dataflow__delay_valid_357) && _dataflow__delay_valid_356; reg signed [16-1:0] _dataflow__delay_data_373; reg _dataflow__delay_valid_373; wire _dataflow__delay_ready_373; assign _dataflow__delay_ready_372 = (_dataflow__delay_ready_373 || !_dataflow__delay_valid_373) && _dataflow__delay_valid_372; reg signed [16-1:0] _dataflow__delay_data_389; reg _dataflow__delay_valid_389; wire _dataflow__delay_ready_389; assign _dataflow__delay_ready_388 = (_dataflow__delay_ready_389 || !_dataflow__delay_valid_389) && _dataflow__delay_valid_388; reg signed [16-1:0] _dataflow__delay_data_405; reg _dataflow__delay_valid_405; wire _dataflow__delay_ready_405; assign _dataflow__delay_ready_404 = (_dataflow__delay_ready_405 || !_dataflow__delay_valid_405) && _dataflow__delay_valid_404; reg signed [16-1:0] _dataflow__delay_data_437; reg _dataflow__delay_valid_437; wire _dataflow__delay_ready_437; assign _dataflow__delay_ready_436 = (_dataflow__delay_ready_437 || !_dataflow__delay_valid_437) && _dataflow__delay_valid_436; reg signed [16-1:0] _dataflow__delay_data_453; reg _dataflow__delay_valid_453; wire _dataflow__delay_ready_453; assign _dataflow__delay_ready_452 = (_dataflow__delay_ready_453 || !_dataflow__delay_valid_453) && _dataflow__delay_valid_452; reg signed [16-1:0] _dataflow_minus_data_108; reg _dataflow_minus_valid_108; wire _dataflow_minus_ready_108; assign _dataflow_times_ready_104 = (_dataflow_minus_ready_108 || !_dataflow_minus_valid_108) && (_dataflow_times_valid_104 && _dataflow_times_valid_105); assign _dataflow_times_ready_105 = (_dataflow_minus_ready_108 || !_dataflow_minus_valid_108) && (_dataflow_times_valid_104 && _dataflow_times_valid_105); reg signed [16-1:0] _dataflow_plus_data_109; reg _dataflow_plus_valid_109; wire _dataflow_plus_ready_109; assign _dataflow_times_ready_106 = (_dataflow_plus_ready_109 || !_dataflow_plus_valid_109) && (_dataflow_times_valid_106 && _dataflow_times_valid_107); assign _dataflow_times_ready_107 = (_dataflow_plus_ready_109 || !_dataflow_plus_valid_109) && (_dataflow_times_valid_106 && _dataflow_times_valid_107); reg signed [16-1:0] _dataflow_minus_data_118; reg _dataflow_minus_valid_118; wire _dataflow_minus_ready_118; assign _dataflow_times_ready_114 = (_dataflow_minus_ready_118 || !_dataflow_minus_valid_118) && (_dataflow_times_valid_114 && _dataflow_times_valid_115); assign _dataflow_times_ready_115 = (_dataflow_minus_ready_118 || !_dataflow_minus_valid_118) && (_dataflow_times_valid_114 && _dataflow_times_valid_115); reg signed [16-1:0] _dataflow_plus_data_119; reg _dataflow_plus_valid_119; wire _dataflow_plus_ready_119; assign _dataflow_times_ready_116 = (_dataflow_plus_ready_119 || !_dataflow_plus_valid_119) && (_dataflow_times_valid_116 && _dataflow_times_valid_117); assign _dataflow_times_ready_117 = (_dataflow_plus_ready_119 || !_dataflow_plus_valid_119) && (_dataflow_times_valid_116 && _dataflow_times_valid_117); reg signed [16-1:0] _dataflow__delay_data_283; reg _dataflow__delay_valid_283; wire _dataflow__delay_ready_283; assign _dataflow__delay_ready_282 = (_dataflow__delay_ready_283 || !_dataflow__delay_valid_283) && _dataflow__delay_valid_282; reg signed [16-1:0] _dataflow__delay_data_302; reg _dataflow__delay_valid_302; wire _dataflow__delay_ready_302; assign _dataflow__delay_ready_301 = (_dataflow__delay_ready_302 || !_dataflow__delay_valid_302) && _dataflow__delay_valid_301; reg signed [16-1:0] _dataflow__delay_data_318; reg _dataflow__delay_valid_318; wire _dataflow__delay_ready_318; assign _dataflow__delay_ready_317 = (_dataflow__delay_ready_318 || !_dataflow__delay_valid_318) && _dataflow__delay_valid_317; reg signed [16-1:0] _dataflow__delay_data_342; reg _dataflow__delay_valid_342; wire _dataflow__delay_ready_342; assign _dataflow__delay_ready_341 = (_dataflow__delay_ready_342 || !_dataflow__delay_valid_342) && _dataflow__delay_valid_341; reg signed [16-1:0] _dataflow__delay_data_358; reg _dataflow__delay_valid_358; wire _dataflow__delay_ready_358; assign _dataflow__delay_ready_357 = (_dataflow__delay_ready_358 || !_dataflow__delay_valid_358) && _dataflow__delay_valid_357; reg signed [16-1:0] _dataflow__delay_data_374; reg _dataflow__delay_valid_374; wire _dataflow__delay_ready_374; assign _dataflow__delay_ready_373 = (_dataflow__delay_ready_374 || !_dataflow__delay_valid_374) && _dataflow__delay_valid_373; reg signed [16-1:0] _dataflow__delay_data_390; reg _dataflow__delay_valid_390; wire _dataflow__delay_ready_390; assign _dataflow__delay_ready_389 = (_dataflow__delay_ready_390 || !_dataflow__delay_valid_390) && _dataflow__delay_valid_389; reg signed [16-1:0] _dataflow__delay_data_406; reg _dataflow__delay_valid_406; wire _dataflow__delay_ready_406; assign _dataflow__delay_ready_405 = (_dataflow__delay_ready_406 || !_dataflow__delay_valid_406) && _dataflow__delay_valid_405; reg signed [16-1:0] _dataflow__delay_data_438; reg _dataflow__delay_valid_438; wire _dataflow__delay_ready_438; assign _dataflow__delay_ready_437 = (_dataflow__delay_ready_438 || !_dataflow__delay_valid_438) && _dataflow__delay_valid_437; reg signed [16-1:0] _dataflow__delay_data_454; reg _dataflow__delay_valid_454; wire _dataflow__delay_ready_454; assign _dataflow__delay_ready_453 = (_dataflow__delay_ready_454 || !_dataflow__delay_valid_454) && _dataflow__delay_valid_453; reg signed [16-1:0] _dataflow_minus_data_138; reg _dataflow_minus_valid_138; wire _dataflow_minus_ready_138; assign _dataflow_times_ready_134 = (_dataflow_minus_ready_138 || !_dataflow_minus_valid_138) && (_dataflow_times_valid_134 && _dataflow_times_valid_135); assign _dataflow_times_ready_135 = (_dataflow_minus_ready_138 || !_dataflow_minus_valid_138) && (_dataflow_times_valid_134 && _dataflow_times_valid_135); reg signed [16-1:0] _dataflow_plus_data_139; reg _dataflow_plus_valid_139; wire _dataflow_plus_ready_139; assign _dataflow_times_ready_136 = (_dataflow_plus_ready_139 || !_dataflow_plus_valid_139) && (_dataflow_times_valid_136 && _dataflow_times_valid_137); assign _dataflow_times_ready_137 = (_dataflow_plus_ready_139 || !_dataflow_plus_valid_139) && (_dataflow_times_valid_136 && _dataflow_times_valid_137); reg signed [16-1:0] _dataflow_minus_data_148; reg _dataflow_minus_valid_148; wire _dataflow_minus_ready_148; assign _dataflow_times_ready_144 = (_dataflow_minus_ready_148 || !_dataflow_minus_valid_148) && (_dataflow_times_valid_144 && _dataflow_times_valid_145); assign _dataflow_times_ready_145 = (_dataflow_minus_ready_148 || !_dataflow_minus_valid_148) && (_dataflow_times_valid_144 && _dataflow_times_valid_145); reg signed [16-1:0] _dataflow_plus_data_149; reg _dataflow_plus_valid_149; wire _dataflow_plus_ready_149; assign _dataflow_times_ready_146 = (_dataflow_plus_ready_149 || !_dataflow_plus_valid_149) && (_dataflow_times_valid_146 && _dataflow_times_valid_147); assign _dataflow_times_ready_147 = (_dataflow_plus_ready_149 || !_dataflow_plus_valid_149) && (_dataflow_times_valid_146 && _dataflow_times_valid_147); reg signed [16-1:0] _dataflow_plus_data_150; reg _dataflow_plus_valid_150; wire _dataflow_plus_ready_150; reg signed [16-1:0] _dataflow_plus_data_151; reg _dataflow_plus_valid_151; wire _dataflow_plus_ready_151; reg signed [16-1:0] _dataflow_minus_data_152; reg _dataflow_minus_valid_152; wire _dataflow_minus_ready_152; assign _dataflow_minus_ready_108 = (_dataflow_plus_ready_150 || !_dataflow_plus_valid_150) && (_dataflow_minus_valid_108 && _dataflow_minus_valid_118) && ((_dataflow_minus_ready_152 || !_dataflow_minus_valid_152) && (_dataflow_minus_valid_108 && _dataflow_minus_valid_118)); assign _dataflow_minus_ready_118 = (_dataflow_plus_ready_150 || !_dataflow_plus_valid_150) && (_dataflow_minus_valid_108 && _dataflow_minus_valid_118) && ((_dataflow_minus_ready_152 || !_dataflow_minus_valid_152) && (_dataflow_minus_valid_108 && _dataflow_minus_valid_118)); reg signed [16-1:0] _dataflow_minus_data_153; reg _dataflow_minus_valid_153; wire _dataflow_minus_ready_153; assign _dataflow_plus_ready_109 = (_dataflow_plus_ready_151 || !_dataflow_plus_valid_151) && (_dataflow_plus_valid_109 && _dataflow_plus_valid_119) && ((_dataflow_minus_ready_153 || !_dataflow_minus_valid_153) && (_dataflow_plus_valid_109 && _dataflow_plus_valid_119)); assign _dataflow_plus_ready_119 = (_dataflow_plus_ready_151 || !_dataflow_plus_valid_151) && (_dataflow_plus_valid_109 && _dataflow_plus_valid_119) && ((_dataflow_minus_ready_153 || !_dataflow_minus_valid_153) && (_dataflow_plus_valid_109 && _dataflow_plus_valid_119)); reg signed [16-1:0] _dataflow__delay_data_284; reg _dataflow__delay_valid_284; wire _dataflow__delay_ready_284; assign _dataflow__delay_ready_283 = (_dataflow__delay_ready_284 || !_dataflow__delay_valid_284) && _dataflow__delay_valid_283; reg signed [16-1:0] _dataflow__delay_data_303; reg _dataflow__delay_valid_303; wire _dataflow__delay_ready_303; assign _dataflow__delay_ready_302 = (_dataflow__delay_ready_303 || !_dataflow__delay_valid_303) && _dataflow__delay_valid_302; reg signed [16-1:0] _dataflow__delay_data_319; reg _dataflow__delay_valid_319; wire _dataflow__delay_ready_319; assign _dataflow__delay_ready_318 = (_dataflow__delay_ready_319 || !_dataflow__delay_valid_319) && _dataflow__delay_valid_318; reg signed [16-1:0] _dataflow__delay_data_343; reg _dataflow__delay_valid_343; wire _dataflow__delay_ready_343; assign _dataflow__delay_ready_342 = (_dataflow__delay_ready_343 || !_dataflow__delay_valid_343) && _dataflow__delay_valid_342; reg signed [16-1:0] _dataflow__delay_data_359; reg _dataflow__delay_valid_359; wire _dataflow__delay_ready_359; assign _dataflow__delay_ready_358 = (_dataflow__delay_ready_359 || !_dataflow__delay_valid_359) && _dataflow__delay_valid_358; reg signed [16-1:0] _dataflow__delay_data_375; reg _dataflow__delay_valid_375; wire _dataflow__delay_ready_375; assign _dataflow__delay_ready_374 = (_dataflow__delay_ready_375 || !_dataflow__delay_valid_375) && _dataflow__delay_valid_374; reg signed [16-1:0] _dataflow__delay_data_391; reg _dataflow__delay_valid_391; wire _dataflow__delay_ready_391; assign _dataflow__delay_ready_390 = (_dataflow__delay_ready_391 || !_dataflow__delay_valid_391) && _dataflow__delay_valid_390; reg signed [16-1:0] _dataflow__delay_data_407; reg _dataflow__delay_valid_407; wire _dataflow__delay_ready_407; assign _dataflow__delay_ready_406 = (_dataflow__delay_ready_407 || !_dataflow__delay_valid_407) && _dataflow__delay_valid_406; reg signed [16-1:0] _dataflow__delay_data_439; reg _dataflow__delay_valid_439; wire _dataflow__delay_ready_439; assign _dataflow__delay_ready_438 = (_dataflow__delay_ready_439 || !_dataflow__delay_valid_439) && _dataflow__delay_valid_438; reg signed [16-1:0] _dataflow__delay_data_455; reg _dataflow__delay_valid_455; wire _dataflow__delay_ready_455; assign _dataflow__delay_ready_454 = (_dataflow__delay_ready_455 || !_dataflow__delay_valid_455) && _dataflow__delay_valid_454; wire signed [16-1:0] _dataflow_times_data_154; wire _dataflow_times_valid_154; wire _dataflow_times_ready_154; wire signed [32-1:0] _dataflow_times_mul_odata_154; reg signed [32-1:0] _dataflow_times_mul_odata_reg_154; assign _dataflow_times_data_154 = _dataflow_times_mul_odata_reg_154; wire _dataflow_times_mul_ovalid_154; reg _dataflow_times_mul_valid_reg_154; assign _dataflow_times_valid_154 = _dataflow_times_mul_valid_reg_154; wire _dataflow_times_mul_enable_154; wire _dataflow_times_mul_update_154; assign _dataflow_times_mul_enable_154 = (_dataflow_times_ready_154 || !_dataflow_times_valid_154) && (_dataflow_minus_ready_152 && _dataflow__delay_ready_284) && (_dataflow_minus_valid_152 && _dataflow__delay_valid_284); assign _dataflow_times_mul_update_154 = _dataflow_times_ready_154 || !_dataflow_times_valid_154; multiplier_44 _dataflow_times_mul_154 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_154), .enable(_dataflow_times_mul_enable_154), .valid(_dataflow_times_mul_ovalid_154), .a(_dataflow_minus_data_152), .b(_dataflow__delay_data_284), .c(_dataflow_times_mul_odata_154) ); wire signed [16-1:0] _dataflow_times_data_155; wire _dataflow_times_valid_155; wire _dataflow_times_ready_155; wire signed [32-1:0] _dataflow_times_mul_odata_155; reg signed [32-1:0] _dataflow_times_mul_odata_reg_155; assign _dataflow_times_data_155 = _dataflow_times_mul_odata_reg_155; wire _dataflow_times_mul_ovalid_155; reg _dataflow_times_mul_valid_reg_155; assign _dataflow_times_valid_155 = _dataflow_times_mul_valid_reg_155; wire _dataflow_times_mul_enable_155; wire _dataflow_times_mul_update_155; assign _dataflow_times_mul_enable_155 = (_dataflow_times_ready_155 || !_dataflow_times_valid_155) && (_dataflow_minus_ready_153 && _dataflow__delay_ready_303) && (_dataflow_minus_valid_153 && _dataflow__delay_valid_303); assign _dataflow_times_mul_update_155 = _dataflow_times_ready_155 || !_dataflow_times_valid_155; multiplier_45 _dataflow_times_mul_155 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_155), .enable(_dataflow_times_mul_enable_155), .valid(_dataflow_times_mul_ovalid_155), .a(_dataflow_minus_data_153), .b(_dataflow__delay_data_303), .c(_dataflow_times_mul_odata_155) ); wire signed [16-1:0] _dataflow_times_data_156; wire _dataflow_times_valid_156; wire _dataflow_times_ready_156; wire signed [32-1:0] _dataflow_times_mul_odata_156; reg signed [32-1:0] _dataflow_times_mul_odata_reg_156; assign _dataflow_times_data_156 = _dataflow_times_mul_odata_reg_156; wire _dataflow_times_mul_ovalid_156; reg _dataflow_times_mul_valid_reg_156; assign _dataflow_times_valid_156 = _dataflow_times_mul_valid_reg_156; wire _dataflow_times_mul_enable_156; wire _dataflow_times_mul_update_156; assign _dataflow_times_mul_enable_156 = (_dataflow_times_ready_156 || !_dataflow_times_valid_156) && (_dataflow_minus_ready_152 && _dataflow__delay_ready_303) && (_dataflow_minus_valid_152 && _dataflow__delay_valid_303); assign _dataflow_times_mul_update_156 = _dataflow_times_ready_156 || !_dataflow_times_valid_156; multiplier_46 _dataflow_times_mul_156 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_156), .enable(_dataflow_times_mul_enable_156), .valid(_dataflow_times_mul_ovalid_156), .a(_dataflow_minus_data_152), .b(_dataflow__delay_data_303), .c(_dataflow_times_mul_odata_156) ); assign _dataflow_minus_ready_152 = (_dataflow_times_ready_154 || !_dataflow_times_valid_154) && (_dataflow_minus_valid_152 && _dataflow__delay_valid_284) && ((_dataflow_times_ready_156 || !_dataflow_times_valid_156) && (_dataflow_minus_valid_152 && _dataflow__delay_valid_303)); assign _dataflow__delay_ready_303 = (_dataflow_times_ready_155 || !_dataflow_times_valid_155) && (_dataflow_minus_valid_153 && _dataflow__delay_valid_303) && ((_dataflow_times_ready_156 || !_dataflow_times_valid_156) && (_dataflow_minus_valid_152 && _dataflow__delay_valid_303)); wire signed [16-1:0] _dataflow_times_data_157; wire _dataflow_times_valid_157; wire _dataflow_times_ready_157; wire signed [32-1:0] _dataflow_times_mul_odata_157; reg signed [32-1:0] _dataflow_times_mul_odata_reg_157; assign _dataflow_times_data_157 = _dataflow_times_mul_odata_reg_157; wire _dataflow_times_mul_ovalid_157; reg _dataflow_times_mul_valid_reg_157; assign _dataflow_times_valid_157 = _dataflow_times_mul_valid_reg_157; wire _dataflow_times_mul_enable_157; wire _dataflow_times_mul_update_157; assign _dataflow_times_mul_enable_157 = (_dataflow_times_ready_157 || !_dataflow_times_valid_157) && (_dataflow_minus_ready_153 && _dataflow__delay_ready_284) && (_dataflow_minus_valid_153 && _dataflow__delay_valid_284); assign _dataflow_times_mul_update_157 = _dataflow_times_ready_157 || !_dataflow_times_valid_157; multiplier_47 _dataflow_times_mul_157 ( .CLK(CLK), .RST(RST), .update(_dataflow_times_mul_update_157), .enable(_dataflow_times_mul_enable_157), .valid(_dataflow_times_mul_ovalid_157), .a(_dataflow_minus_data_153), .b(_dataflow__delay_data_284), .c(_dataflow_times_mul_odata_157) ); assign _dataflow_minus_ready_153 = (_dataflow_times_ready_155 || !_dataflow_times_valid_155) && (_dataflow_minus_valid_153 && _dataflow__delay_valid_303) && ((_dataflow_times_ready_157 || !_dataflow_times_valid_157) && (_dataflow_minus_valid_153 && _dataflow__delay_valid_284)); assign _dataflow__delay_ready_284 = (_dataflow_times_ready_154 || !_dataflow_times_valid_154) && (_dataflow_minus_valid_152 && _dataflow__delay_valid_284) && ((_dataflow_times_ready_157 || !_dataflow_times_valid_157) && (_dataflow_minus_valid_153 && _dataflow__delay_valid_284)); reg signed [16-1:0] _dataflow__delay_data_320; reg _dataflow__delay_valid_320; wire _dataflow__delay_ready_320; assign _dataflow__delay_ready_319 = (_dataflow__delay_ready_320 || !_dataflow__delay_valid_320) && _dataflow__delay_valid_319; reg signed [16-1:0] _dataflow__delay_data_344; reg _dataflow__delay_valid_344; wire _dataflow__delay_ready_344; assign _dataflow__delay_ready_343 = (_dataflow__delay_ready_344 || !_dataflow__delay_valid_344) && _dataflow__delay_valid_343; reg signed [16-1:0] _dataflow__delay_data_360; reg _dataflow__delay_valid_360; wire _dataflow__delay_ready_360; assign _dataflow__delay_ready_359 = (_dataflow__delay_ready_360 || !_dataflow__delay_valid_360) && _dataflow__delay_valid_359; reg signed [16-1:0] _dataflow__delay_data_376; reg _dataflow__delay_valid_376; wire _dataflow__delay_ready_376; assign _dataflow__delay_ready_375 = (_dataflow__delay_ready_376 || !_dataflow__delay_valid_376) && _dataflow__delay_valid_375; reg signed [16-1:0] _dataflow__delay_data_392; reg _dataflow__delay_valid_392; wire _dataflow__delay_ready_392; assign _dataflow__delay_ready_391 = (_dataflow__delay_ready_392 || !_dataflow__delay_valid_392) && _dataflow__delay_valid_391; reg signed [16-1:0] _dataflow__delay_data_408; reg _dataflow__delay_valid_408; wire _dataflow__delay_ready_408; assign _dataflow__delay_ready_407 = (_dataflow__delay_ready_408 || !_dataflow__delay_valid_408) && _dataflow__delay_valid_407; reg signed [16-1:0] _dataflow__delay_data_416; reg _dataflow__delay_valid_416; wire _dataflow__delay_ready_416; assign _dataflow_minus_ready_138 = (_dataflow__delay_ready_416 || !_dataflow__delay_valid_416) && _dataflow_minus_valid_138; reg signed [16-1:0] _dataflow__delay_data_424; reg _dataflow__delay_valid_424; wire _dataflow__delay_ready_424; assign _dataflow_plus_ready_139 = (_dataflow__delay_ready_424 || !_dataflow__delay_valid_424) && _dataflow_plus_valid_139; reg signed [16-1:0] _dataflow__delay_data_440; reg _dataflow__delay_valid_440; wire _dataflow__delay_ready_440; assign _dataflow__delay_ready_439 = (_dataflow__delay_ready_440 || !_dataflow__delay_valid_440) && _dataflow__delay_valid_439; reg signed [16-1:0] _dataflow__delay_data_456; reg _dataflow__delay_valid_456; wire _dataflow__delay_ready_456; assign _dataflow__delay_ready_455 = (_dataflow__delay_ready_456 || !_dataflow__delay_valid_456) && _dataflow__delay_valid_455; reg signed [16-1:0] _dataflow__delay_data_464; reg _dataflow__delay_valid_464; wire _dataflow__delay_ready_464; assign _dataflow_minus_ready_148 = (_dataflow__delay_ready_464 || !_dataflow__delay_valid_464) && _dataflow_minus_valid_148; reg signed [16-1:0] _dataflow__delay_data_472; reg _dataflow__delay_valid_472; wire _dataflow__delay_ready_472; assign _dataflow_plus_ready_149 = (_dataflow__delay_ready_472 || !_dataflow__delay_valid_472) && _dataflow_plus_valid_149; reg signed [16-1:0] _dataflow__delay_data_480; reg _dataflow__delay_valid_480; wire _dataflow__delay_ready_480; assign _dataflow_plus_ready_150 = (_dataflow__delay_ready_480 || !_dataflow__delay_valid_480) && _dataflow_plus_valid_150; reg signed [16-1:0] _dataflow__delay_data_488; reg _dataflow__delay_valid_488; wire _dataflow__delay_ready_488; assign _dataflow_plus_ready_151 = (_dataflow__delay_ready_488 || !_dataflow__delay_valid_488) && _dataflow_plus_valid_151; reg signed [16-1:0] _dataflow__delay_data_321; reg _dataflow__delay_valid_321; wire _dataflow__delay_ready_321; assign _dataflow__delay_ready_320 = (_dataflow__delay_ready_321 || !_dataflow__delay_valid_321) && _dataflow__delay_valid_320; reg signed [16-1:0] _dataflow__delay_data_345; reg _dataflow__delay_valid_345; wire _dataflow__delay_ready_345; assign _dataflow__delay_ready_344 = (_dataflow__delay_ready_345 || !_dataflow__delay_valid_345) && _dataflow__delay_valid_344; reg signed [16-1:0] _dataflow__delay_data_361; reg _dataflow__delay_valid_361; wire _dataflow__delay_ready_361; assign _dataflow__delay_ready_360 = (_dataflow__delay_ready_361 || !_dataflow__delay_valid_361) && _dataflow__delay_valid_360; reg signed [16-1:0] _dataflow__delay_data_377; reg _dataflow__delay_valid_377; wire _dataflow__delay_ready_377; assign _dataflow__delay_ready_376 = (_dataflow__delay_ready_377 || !_dataflow__delay_valid_377) && _dataflow__delay_valid_376; reg signed [16-1:0] _dataflow__delay_data_393; reg _dataflow__delay_valid_393; wire _dataflow__delay_ready_393; assign _dataflow__delay_ready_392 = (_dataflow__delay_ready_393 || !_dataflow__delay_valid_393) && _dataflow__delay_valid_392; reg signed [16-1:0] _dataflow__delay_data_409; reg _dataflow__delay_valid_409; wire _dataflow__delay_ready_409; assign _dataflow__delay_ready_408 = (_dataflow__delay_ready_409 || !_dataflow__delay_valid_409) && _dataflow__delay_valid_408; reg signed [16-1:0] _dataflow__delay_data_417; reg _dataflow__delay_valid_417; wire _dataflow__delay_ready_417; assign _dataflow__delay_ready_416 = (_dataflow__delay_ready_417 || !_dataflow__delay_valid_417) && _dataflow__delay_valid_416; reg signed [16-1:0] _dataflow__delay_data_425; reg _dataflow__delay_valid_425; wire _dataflow__delay_ready_425; assign _dataflow__delay_ready_424 = (_dataflow__delay_ready_425 || !_dataflow__delay_valid_425) && _dataflow__delay_valid_424; reg signed [16-1:0] _dataflow__delay_data_441; reg _dataflow__delay_valid_441; wire _dataflow__delay_ready_441; assign _dataflow__delay_ready_440 = (_dataflow__delay_ready_441 || !_dataflow__delay_valid_441) && _dataflow__delay_valid_440; reg signed [16-1:0] _dataflow__delay_data_457; reg _dataflow__delay_valid_457; wire _dataflow__delay_ready_457; assign _dataflow__delay_ready_456 = (_dataflow__delay_ready_457 || !_dataflow__delay_valid_457) && _dataflow__delay_valid_456; reg signed [16-1:0] _dataflow__delay_data_465; reg _dataflow__delay_valid_465; wire _dataflow__delay_ready_465; assign _dataflow__delay_ready_464 = (_dataflow__delay_ready_465 || !_dataflow__delay_valid_465) && _dataflow__delay_valid_464; reg signed [16-1:0] _dataflow__delay_data_473; reg _dataflow__delay_valid_473; wire _dataflow__delay_ready_473; assign _dataflow__delay_ready_472 = (_dataflow__delay_ready_473 || !_dataflow__delay_valid_473) && _dataflow__delay_valid_472; reg signed [16-1:0] _dataflow__delay_data_481; reg _dataflow__delay_valid_481; wire _dataflow__delay_ready_481; assign _dataflow__delay_ready_480 = (_dataflow__delay_ready_481 || !_dataflow__delay_valid_481) && _dataflow__delay_valid_480; reg signed [16-1:0] _dataflow__delay_data_489; reg _dataflow__delay_valid_489; wire _dataflow__delay_ready_489; assign _dataflow__delay_ready_488 = (_dataflow__delay_ready_489 || !_dataflow__delay_valid_489) && _dataflow__delay_valid_488; reg signed [16-1:0] _dataflow__delay_data_322; reg _dataflow__delay_valid_322; wire _dataflow__delay_ready_322; assign _dataflow__delay_ready_321 = (_dataflow__delay_ready_322 || !_dataflow__delay_valid_322) && _dataflow__delay_valid_321; reg signed [16-1:0] _dataflow__delay_data_346; reg _dataflow__delay_valid_346; wire _dataflow__delay_ready_346; assign _dataflow__delay_ready_345 = (_dataflow__delay_ready_346 || !_dataflow__delay_valid_346) && _dataflow__delay_valid_345; reg signed [16-1:0] _dataflow__delay_data_362; reg _dataflow__delay_valid_362; wire _dataflow__delay_ready_362; assign _dataflow__delay_ready_361 = (_dataflow__delay_ready_362 || !_dataflow__delay_valid_362) && _dataflow__delay_valid_361; reg signed [16-1:0] _dataflow__delay_data_378; reg _dataflow__delay_valid_378; wire _dataflow__delay_ready_378; assign _dataflow__delay_ready_377 = (_dataflow__delay_ready_378 || !_dataflow__delay_valid_378) && _dataflow__delay_valid_377; reg signed [16-1:0] _dataflow__delay_data_394; reg _dataflow__delay_valid_394; wire _dataflow__delay_ready_394; assign _dataflow__delay_ready_393 = (_dataflow__delay_ready_394 || !_dataflow__delay_valid_394) && _dataflow__delay_valid_393; reg signed [16-1:0] _dataflow__delay_data_410; reg _dataflow__delay_valid_410; wire _dataflow__delay_ready_410; assign _dataflow__delay_ready_409 = (_dataflow__delay_ready_410 || !_dataflow__delay_valid_410) && _dataflow__delay_valid_409; reg signed [16-1:0] _dataflow__delay_data_418; reg _dataflow__delay_valid_418; wire _dataflow__delay_ready_418; assign _dataflow__delay_ready_417 = (_dataflow__delay_ready_418 || !_dataflow__delay_valid_418) && _dataflow__delay_valid_417; reg signed [16-1:0] _dataflow__delay_data_426; reg _dataflow__delay_valid_426; wire _dataflow__delay_ready_426; assign _dataflow__delay_ready_425 = (_dataflow__delay_ready_426 || !_dataflow__delay_valid_426) && _dataflow__delay_valid_425; reg signed [16-1:0] _dataflow__delay_data_442; reg _dataflow__delay_valid_442; wire _dataflow__delay_ready_442; assign _dataflow__delay_ready_441 = (_dataflow__delay_ready_442 || !_dataflow__delay_valid_442) && _dataflow__delay_valid_441; reg signed [16-1:0] _dataflow__delay_data_458; reg _dataflow__delay_valid_458; wire _dataflow__delay_ready_458; assign _dataflow__delay_ready_457 = (_dataflow__delay_ready_458 || !_dataflow__delay_valid_458) && _dataflow__delay_valid_457; reg signed [16-1:0] _dataflow__delay_data_466; reg _dataflow__delay_valid_466; wire _dataflow__delay_ready_466; assign _dataflow__delay_ready_465 = (_dataflow__delay_ready_466 || !_dataflow__delay_valid_466) && _dataflow__delay_valid_465; reg signed [16-1:0] _dataflow__delay_data_474; reg _dataflow__delay_valid_474; wire _dataflow__delay_ready_474; assign _dataflow__delay_ready_473 = (_dataflow__delay_ready_474 || !_dataflow__delay_valid_474) && _dataflow__delay_valid_473; reg signed [16-1:0] _dataflow__delay_data_482; reg _dataflow__delay_valid_482; wire _dataflow__delay_ready_482; assign _dataflow__delay_ready_481 = (_dataflow__delay_ready_482 || !_dataflow__delay_valid_482) && _dataflow__delay_valid_481; reg signed [16-1:0] _dataflow__delay_data_490; reg _dataflow__delay_valid_490; wire _dataflow__delay_ready_490; assign _dataflow__delay_ready_489 = (_dataflow__delay_ready_490 || !_dataflow__delay_valid_490) && _dataflow__delay_valid_489; reg signed [16-1:0] _dataflow__delay_data_323; reg _dataflow__delay_valid_323; wire _dataflow__delay_ready_323; assign _dataflow__delay_ready_322 = (_dataflow__delay_ready_323 || !_dataflow__delay_valid_323) && _dataflow__delay_valid_322; reg signed [16-1:0] _dataflow__delay_data_347; reg _dataflow__delay_valid_347; wire _dataflow__delay_ready_347; assign _dataflow__delay_ready_346 = (_dataflow__delay_ready_347 || !_dataflow__delay_valid_347) && _dataflow__delay_valid_346; reg signed [16-1:0] _dataflow__delay_data_363; reg _dataflow__delay_valid_363; wire _dataflow__delay_ready_363; assign _dataflow__delay_ready_362 = (_dataflow__delay_ready_363 || !_dataflow__delay_valid_363) && _dataflow__delay_valid_362; reg signed [16-1:0] _dataflow__delay_data_379; reg _dataflow__delay_valid_379; wire _dataflow__delay_ready_379; assign _dataflow__delay_ready_378 = (_dataflow__delay_ready_379 || !_dataflow__delay_valid_379) && _dataflow__delay_valid_378; reg signed [16-1:0] _dataflow__delay_data_395; reg _dataflow__delay_valid_395; wire _dataflow__delay_ready_395; assign _dataflow__delay_ready_394 = (_dataflow__delay_ready_395 || !_dataflow__delay_valid_395) && _dataflow__delay_valid_394; reg signed [16-1:0] _dataflow__delay_data_411; reg _dataflow__delay_valid_411; wire _dataflow__delay_ready_411; assign _dataflow__delay_ready_410 = (_dataflow__delay_ready_411 || !_dataflow__delay_valid_411) && _dataflow__delay_valid_410; reg signed [16-1:0] _dataflow__delay_data_419; reg _dataflow__delay_valid_419; wire _dataflow__delay_ready_419; assign _dataflow__delay_ready_418 = (_dataflow__delay_ready_419 || !_dataflow__delay_valid_419) && _dataflow__delay_valid_418; reg signed [16-1:0] _dataflow__delay_data_427; reg _dataflow__delay_valid_427; wire _dataflow__delay_ready_427; assign _dataflow__delay_ready_426 = (_dataflow__delay_ready_427 || !_dataflow__delay_valid_427) && _dataflow__delay_valid_426; reg signed [16-1:0] _dataflow__delay_data_443; reg _dataflow__delay_valid_443; wire _dataflow__delay_ready_443; assign _dataflow__delay_ready_442 = (_dataflow__delay_ready_443 || !_dataflow__delay_valid_443) && _dataflow__delay_valid_442; reg signed [16-1:0] _dataflow__delay_data_459; reg _dataflow__delay_valid_459; wire _dataflow__delay_ready_459; assign _dataflow__delay_ready_458 = (_dataflow__delay_ready_459 || !_dataflow__delay_valid_459) && _dataflow__delay_valid_458; reg signed [16-1:0] _dataflow__delay_data_467; reg _dataflow__delay_valid_467; wire _dataflow__delay_ready_467; assign _dataflow__delay_ready_466 = (_dataflow__delay_ready_467 || !_dataflow__delay_valid_467) && _dataflow__delay_valid_466; reg signed [16-1:0] _dataflow__delay_data_475; reg _dataflow__delay_valid_475; wire _dataflow__delay_ready_475; assign _dataflow__delay_ready_474 = (_dataflow__delay_ready_475 || !_dataflow__delay_valid_475) && _dataflow__delay_valid_474; reg signed [16-1:0] _dataflow__delay_data_483; reg _dataflow__delay_valid_483; wire _dataflow__delay_ready_483; assign _dataflow__delay_ready_482 = (_dataflow__delay_ready_483 || !_dataflow__delay_valid_483) && _dataflow__delay_valid_482; reg signed [16-1:0] _dataflow__delay_data_491; reg _dataflow__delay_valid_491; wire _dataflow__delay_ready_491; assign _dataflow__delay_ready_490 = (_dataflow__delay_ready_491 || !_dataflow__delay_valid_491) && _dataflow__delay_valid_490; reg signed [16-1:0] _dataflow__delay_data_324; reg _dataflow__delay_valid_324; wire _dataflow__delay_ready_324; assign _dataflow__delay_ready_323 = (_dataflow__delay_ready_324 || !_dataflow__delay_valid_324) && _dataflow__delay_valid_323; reg signed [16-1:0] _dataflow__delay_data_348; reg _dataflow__delay_valid_348; wire _dataflow__delay_ready_348; assign _dataflow__delay_ready_347 = (_dataflow__delay_ready_348 || !_dataflow__delay_valid_348) && _dataflow__delay_valid_347; reg signed [16-1:0] _dataflow__delay_data_364; reg _dataflow__delay_valid_364; wire _dataflow__delay_ready_364; assign _dataflow__delay_ready_363 = (_dataflow__delay_ready_364 || !_dataflow__delay_valid_364) && _dataflow__delay_valid_363; reg signed [16-1:0] _dataflow__delay_data_380; reg _dataflow__delay_valid_380; wire _dataflow__delay_ready_380; assign _dataflow__delay_ready_379 = (_dataflow__delay_ready_380 || !_dataflow__delay_valid_380) && _dataflow__delay_valid_379; reg signed [16-1:0] _dataflow__delay_data_396; reg _dataflow__delay_valid_396; wire _dataflow__delay_ready_396; assign _dataflow__delay_ready_395 = (_dataflow__delay_ready_396 || !_dataflow__delay_valid_396) && _dataflow__delay_valid_395; reg signed [16-1:0] _dataflow__delay_data_412; reg _dataflow__delay_valid_412; wire _dataflow__delay_ready_412; assign _dataflow__delay_ready_411 = (_dataflow__delay_ready_412 || !_dataflow__delay_valid_412) && _dataflow__delay_valid_411; reg signed [16-1:0] _dataflow__delay_data_420; reg _dataflow__delay_valid_420; wire _dataflow__delay_ready_420; assign _dataflow__delay_ready_419 = (_dataflow__delay_ready_420 || !_dataflow__delay_valid_420) && _dataflow__delay_valid_419; reg signed [16-1:0] _dataflow__delay_data_428; reg _dataflow__delay_valid_428; wire _dataflow__delay_ready_428; assign _dataflow__delay_ready_427 = (_dataflow__delay_ready_428 || !_dataflow__delay_valid_428) && _dataflow__delay_valid_427; reg signed [16-1:0] _dataflow__delay_data_444; reg _dataflow__delay_valid_444; wire _dataflow__delay_ready_444; assign _dataflow__delay_ready_443 = (_dataflow__delay_ready_444 || !_dataflow__delay_valid_444) && _dataflow__delay_valid_443; reg signed [16-1:0] _dataflow__delay_data_460; reg _dataflow__delay_valid_460; wire _dataflow__delay_ready_460; assign _dataflow__delay_ready_459 = (_dataflow__delay_ready_460 || !_dataflow__delay_valid_460) && _dataflow__delay_valid_459; reg signed [16-1:0] _dataflow__delay_data_468; reg _dataflow__delay_valid_468; wire _dataflow__delay_ready_468; assign _dataflow__delay_ready_467 = (_dataflow__delay_ready_468 || !_dataflow__delay_valid_468) && _dataflow__delay_valid_467; reg signed [16-1:0] _dataflow__delay_data_476; reg _dataflow__delay_valid_476; wire _dataflow__delay_ready_476; assign _dataflow__delay_ready_475 = (_dataflow__delay_ready_476 || !_dataflow__delay_valid_476) && _dataflow__delay_valid_475; reg signed [16-1:0] _dataflow__delay_data_484; reg _dataflow__delay_valid_484; wire _dataflow__delay_ready_484; assign _dataflow__delay_ready_483 = (_dataflow__delay_ready_484 || !_dataflow__delay_valid_484) && _dataflow__delay_valid_483; reg signed [16-1:0] _dataflow__delay_data_492; reg _dataflow__delay_valid_492; wire _dataflow__delay_ready_492; assign _dataflow__delay_ready_491 = (_dataflow__delay_ready_492 || !_dataflow__delay_valid_492) && _dataflow__delay_valid_491; reg signed [16-1:0] _dataflow__delay_data_325; reg _dataflow__delay_valid_325; wire _dataflow__delay_ready_325; assign _dataflow__delay_ready_324 = (_dataflow__delay_ready_325 || !_dataflow__delay_valid_325) && _dataflow__delay_valid_324; reg signed [16-1:0] _dataflow__delay_data_349; reg _dataflow__delay_valid_349; wire _dataflow__delay_ready_349; assign _dataflow__delay_ready_348 = (_dataflow__delay_ready_349 || !_dataflow__delay_valid_349) && _dataflow__delay_valid_348; reg signed [16-1:0] _dataflow__delay_data_365; reg _dataflow__delay_valid_365; wire _dataflow__delay_ready_365; assign _dataflow__delay_ready_364 = (_dataflow__delay_ready_365 || !_dataflow__delay_valid_365) && _dataflow__delay_valid_364; reg signed [16-1:0] _dataflow__delay_data_381; reg _dataflow__delay_valid_381; wire _dataflow__delay_ready_381; assign _dataflow__delay_ready_380 = (_dataflow__delay_ready_381 || !_dataflow__delay_valid_381) && _dataflow__delay_valid_380; reg signed [16-1:0] _dataflow__delay_data_397; reg _dataflow__delay_valid_397; wire _dataflow__delay_ready_397; assign _dataflow__delay_ready_396 = (_dataflow__delay_ready_397 || !_dataflow__delay_valid_397) && _dataflow__delay_valid_396; reg signed [16-1:0] _dataflow__delay_data_413; reg _dataflow__delay_valid_413; wire _dataflow__delay_ready_413; assign _dataflow__delay_ready_412 = (_dataflow__delay_ready_413 || !_dataflow__delay_valid_413) && _dataflow__delay_valid_412; reg signed [16-1:0] _dataflow__delay_data_421; reg _dataflow__delay_valid_421; wire _dataflow__delay_ready_421; assign _dataflow__delay_ready_420 = (_dataflow__delay_ready_421 || !_dataflow__delay_valid_421) && _dataflow__delay_valid_420; reg signed [16-1:0] _dataflow__delay_data_429; reg _dataflow__delay_valid_429; wire _dataflow__delay_ready_429; assign _dataflow__delay_ready_428 = (_dataflow__delay_ready_429 || !_dataflow__delay_valid_429) && _dataflow__delay_valid_428; reg signed [16-1:0] _dataflow__delay_data_445; reg _dataflow__delay_valid_445; wire _dataflow__delay_ready_445; assign _dataflow__delay_ready_444 = (_dataflow__delay_ready_445 || !_dataflow__delay_valid_445) && _dataflow__delay_valid_444; reg signed [16-1:0] _dataflow__delay_data_461; reg _dataflow__delay_valid_461; wire _dataflow__delay_ready_461; assign _dataflow__delay_ready_460 = (_dataflow__delay_ready_461 || !_dataflow__delay_valid_461) && _dataflow__delay_valid_460; reg signed [16-1:0] _dataflow__delay_data_469; reg _dataflow__delay_valid_469; wire _dataflow__delay_ready_469; assign _dataflow__delay_ready_468 = (_dataflow__delay_ready_469 || !_dataflow__delay_valid_469) && _dataflow__delay_valid_468; reg signed [16-1:0] _dataflow__delay_data_477; reg _dataflow__delay_valid_477; wire _dataflow__delay_ready_477; assign _dataflow__delay_ready_476 = (_dataflow__delay_ready_477 || !_dataflow__delay_valid_477) && _dataflow__delay_valid_476; reg signed [16-1:0] _dataflow__delay_data_485; reg _dataflow__delay_valid_485; wire _dataflow__delay_ready_485; assign _dataflow__delay_ready_484 = (_dataflow__delay_ready_485 || !_dataflow__delay_valid_485) && _dataflow__delay_valid_484; reg signed [16-1:0] _dataflow__delay_data_493; reg _dataflow__delay_valid_493; wire _dataflow__delay_ready_493; assign _dataflow__delay_ready_492 = (_dataflow__delay_ready_493 || !_dataflow__delay_valid_493) && _dataflow__delay_valid_492; reg signed [16-1:0] _dataflow__delay_data_326; reg _dataflow__delay_valid_326; wire _dataflow__delay_ready_326; assign _dataflow__delay_ready_325 = (_dataflow__delay_ready_326 || !_dataflow__delay_valid_326) && _dataflow__delay_valid_325; reg signed [16-1:0] _dataflow__delay_data_350; reg _dataflow__delay_valid_350; wire _dataflow__delay_ready_350; assign _dataflow__delay_ready_349 = (_dataflow__delay_ready_350 || !_dataflow__delay_valid_350) && _dataflow__delay_valid_349; reg signed [16-1:0] _dataflow__delay_data_366; reg _dataflow__delay_valid_366; wire _dataflow__delay_ready_366; assign _dataflow__delay_ready_365 = (_dataflow__delay_ready_366 || !_dataflow__delay_valid_366) && _dataflow__delay_valid_365; reg signed [16-1:0] _dataflow__delay_data_382; reg _dataflow__delay_valid_382; wire _dataflow__delay_ready_382; assign _dataflow__delay_ready_381 = (_dataflow__delay_ready_382 || !_dataflow__delay_valid_382) && _dataflow__delay_valid_381; reg signed [16-1:0] _dataflow__delay_data_398; reg _dataflow__delay_valid_398; wire _dataflow__delay_ready_398; assign _dataflow__delay_ready_397 = (_dataflow__delay_ready_398 || !_dataflow__delay_valid_398) && _dataflow__delay_valid_397; reg signed [16-1:0] _dataflow__delay_data_414; reg _dataflow__delay_valid_414; wire _dataflow__delay_ready_414; assign _dataflow__delay_ready_413 = (_dataflow__delay_ready_414 || !_dataflow__delay_valid_414) && _dataflow__delay_valid_413; reg signed [16-1:0] _dataflow__delay_data_422; reg _dataflow__delay_valid_422; wire _dataflow__delay_ready_422; assign _dataflow__delay_ready_421 = (_dataflow__delay_ready_422 || !_dataflow__delay_valid_422) && _dataflow__delay_valid_421; reg signed [16-1:0] _dataflow__delay_data_430; reg _dataflow__delay_valid_430; wire _dataflow__delay_ready_430; assign _dataflow__delay_ready_429 = (_dataflow__delay_ready_430 || !_dataflow__delay_valid_430) && _dataflow__delay_valid_429; reg signed [16-1:0] _dataflow__delay_data_446; reg _dataflow__delay_valid_446; wire _dataflow__delay_ready_446; assign _dataflow__delay_ready_445 = (_dataflow__delay_ready_446 || !_dataflow__delay_valid_446) && _dataflow__delay_valid_445; reg signed [16-1:0] _dataflow__delay_data_462; reg _dataflow__delay_valid_462; wire _dataflow__delay_ready_462; assign _dataflow__delay_ready_461 = (_dataflow__delay_ready_462 || !_dataflow__delay_valid_462) && _dataflow__delay_valid_461; reg signed [16-1:0] _dataflow__delay_data_470; reg _dataflow__delay_valid_470; wire _dataflow__delay_ready_470; assign _dataflow__delay_ready_469 = (_dataflow__delay_ready_470 || !_dataflow__delay_valid_470) && _dataflow__delay_valid_469; reg signed [16-1:0] _dataflow__delay_data_478; reg _dataflow__delay_valid_478; wire _dataflow__delay_ready_478; assign _dataflow__delay_ready_477 = (_dataflow__delay_ready_478 || !_dataflow__delay_valid_478) && _dataflow__delay_valid_477; reg signed [16-1:0] _dataflow__delay_data_486; reg _dataflow__delay_valid_486; wire _dataflow__delay_ready_486; assign _dataflow__delay_ready_485 = (_dataflow__delay_ready_486 || !_dataflow__delay_valid_486) && _dataflow__delay_valid_485; reg signed [16-1:0] _dataflow__delay_data_494; reg _dataflow__delay_valid_494; wire _dataflow__delay_ready_494; assign _dataflow__delay_ready_493 = (_dataflow__delay_ready_494 || !_dataflow__delay_valid_494) && _dataflow__delay_valid_493; reg signed [16-1:0] _dataflow_minus_data_158; reg _dataflow_minus_valid_158; wire _dataflow_minus_ready_158; assign _dataflow_times_ready_154 = (_dataflow_minus_ready_158 || !_dataflow_minus_valid_158) && (_dataflow_times_valid_154 && _dataflow_times_valid_155); assign _dataflow_times_ready_155 = (_dataflow_minus_ready_158 || !_dataflow_minus_valid_158) && (_dataflow_times_valid_154 && _dataflow_times_valid_155); reg signed [16-1:0] _dataflow_plus_data_159; reg _dataflow_plus_valid_159; wire _dataflow_plus_ready_159; assign _dataflow_times_ready_156 = (_dataflow_plus_ready_159 || !_dataflow_plus_valid_159) && (_dataflow_times_valid_156 && _dataflow_times_valid_157); assign _dataflow_times_ready_157 = (_dataflow_plus_ready_159 || !_dataflow_plus_valid_159) && (_dataflow_times_valid_156 && _dataflow_times_valid_157); reg signed [16-1:0] _dataflow__delay_data_327; reg _dataflow__delay_valid_327; wire _dataflow__delay_ready_327; assign _dataflow__delay_ready_326 = (_dataflow__delay_ready_327 || !_dataflow__delay_valid_327) && _dataflow__delay_valid_326; reg signed [16-1:0] _dataflow__delay_data_351; reg _dataflow__delay_valid_351; wire _dataflow__delay_ready_351; assign _dataflow__delay_ready_350 = (_dataflow__delay_ready_351 || !_dataflow__delay_valid_351) && _dataflow__delay_valid_350; reg signed [16-1:0] _dataflow__delay_data_367; reg _dataflow__delay_valid_367; wire _dataflow__delay_ready_367; assign _dataflow__delay_ready_366 = (_dataflow__delay_ready_367 || !_dataflow__delay_valid_367) && _dataflow__delay_valid_366; reg signed [16-1:0] _dataflow__delay_data_383; reg _dataflow__delay_valid_383; wire _dataflow__delay_ready_383; assign _dataflow__delay_ready_382 = (_dataflow__delay_ready_383 || !_dataflow__delay_valid_383) && _dataflow__delay_valid_382; reg signed [16-1:0] _dataflow__delay_data_399; reg _dataflow__delay_valid_399; wire _dataflow__delay_ready_399; assign _dataflow__delay_ready_398 = (_dataflow__delay_ready_399 || !_dataflow__delay_valid_399) && _dataflow__delay_valid_398; reg signed [16-1:0] _dataflow__delay_data_415; reg _dataflow__delay_valid_415; wire _dataflow__delay_ready_415; assign _dataflow__delay_ready_414 = (_dataflow__delay_ready_415 || !_dataflow__delay_valid_415) && _dataflow__delay_valid_414; reg signed [16-1:0] _dataflow__delay_data_423; reg _dataflow__delay_valid_423; wire _dataflow__delay_ready_423; assign _dataflow__delay_ready_422 = (_dataflow__delay_ready_423 || !_dataflow__delay_valid_423) && _dataflow__delay_valid_422; reg signed [16-1:0] _dataflow__delay_data_431; reg _dataflow__delay_valid_431; wire _dataflow__delay_ready_431; assign _dataflow__delay_ready_430 = (_dataflow__delay_ready_431 || !_dataflow__delay_valid_431) && _dataflow__delay_valid_430; reg signed [16-1:0] _dataflow__delay_data_447; reg _dataflow__delay_valid_447; wire _dataflow__delay_ready_447; assign _dataflow__delay_ready_446 = (_dataflow__delay_ready_447 || !_dataflow__delay_valid_447) && _dataflow__delay_valid_446; reg signed [16-1:0] _dataflow__delay_data_463; reg _dataflow__delay_valid_463; wire _dataflow__delay_ready_463; assign _dataflow__delay_ready_462 = (_dataflow__delay_ready_463 || !_dataflow__delay_valid_463) && _dataflow__delay_valid_462; reg signed [16-1:0] _dataflow__delay_data_471; reg _dataflow__delay_valid_471; wire _dataflow__delay_ready_471; assign _dataflow__delay_ready_470 = (_dataflow__delay_ready_471 || !_dataflow__delay_valid_471) && _dataflow__delay_valid_470; reg signed [16-1:0] _dataflow__delay_data_479; reg _dataflow__delay_valid_479; wire _dataflow__delay_ready_479; assign _dataflow__delay_ready_478 = (_dataflow__delay_ready_479 || !_dataflow__delay_valid_479) && _dataflow__delay_valid_478; reg signed [16-1:0] _dataflow__delay_data_487; reg _dataflow__delay_valid_487; wire _dataflow__delay_ready_487; assign _dataflow__delay_ready_486 = (_dataflow__delay_ready_487 || !_dataflow__delay_valid_487) && _dataflow__delay_valid_486; reg signed [16-1:0] _dataflow__delay_data_495; reg _dataflow__delay_valid_495; wire _dataflow__delay_ready_495; assign _dataflow__delay_ready_494 = (_dataflow__delay_ready_495 || !_dataflow__delay_valid_495) && _dataflow__delay_valid_494; assign dout7re = _dataflow_minus_data_158; assign _dataflow_minus_ready_158 = 1; assign dout7im = _dataflow_plus_data_159; assign _dataflow_plus_ready_159 = 1; assign dout0re = _dataflow__delay_data_327; assign _dataflow__delay_ready_327 = 1; assign dout0im = _dataflow__delay_data_351; assign _dataflow__delay_ready_351 = 1; assign dout4re = _dataflow__delay_data_367; assign _dataflow__delay_ready_367 = 1; assign dout4im = _dataflow__delay_data_383; assign _dataflow__delay_ready_383 = 1; assign dout2re = _dataflow__delay_data_399; assign _dataflow__delay_ready_399 = 1; assign dout2im = _dataflow__delay_data_415; assign _dataflow__delay_ready_415 = 1; assign dout6re = _dataflow__delay_data_423; assign _dataflow__delay_ready_423 = 1; assign dout6im = _dataflow__delay_data_431; assign _dataflow__delay_ready_431 = 1; assign dout1re = _dataflow__delay_data_447; assign _dataflow__delay_ready_447 = 1; assign dout1im = _dataflow__delay_data_463; assign _dataflow__delay_ready_463 = 1; assign dout5re = _dataflow__delay_data_471; assign _dataflow__delay_ready_471 = 1; assign dout5im = _dataflow__delay_data_479; assign _dataflow__delay_ready_479 = 1; assign dout3re = _dataflow__delay_data_487; assign _dataflow__delay_ready_487 = 1; assign dout3im = _dataflow__delay_data_495; assign _dataflow__delay_ready_495 = 1; always @(posedge CLK) begin if(RST) begin _dataflow_plus_data_40 <= 0; _dataflow_plus_valid_40 <= 0; _dataflow_plus_data_41 <= 0; _dataflow_plus_valid_41 <= 0; _dataflow_minus_data_42 <= 0; _dataflow_minus_valid_42 <= 0; _dataflow_minus_data_43 <= 0; _dataflow_minus_valid_43 <= 0; _dataflow_plus_data_50 <= 0; _dataflow_plus_valid_50 <= 0; _dataflow_plus_data_51 <= 0; _dataflow_plus_valid_51 <= 0; _dataflow_minus_data_52 <= 0; _dataflow_minus_valid_52 <= 0; _dataflow_minus_data_53 <= 0; _dataflow_minus_valid_53 <= 0; _dataflow_plus_data_60 <= 0; _dataflow_plus_valid_60 <= 0; _dataflow_plus_data_61 <= 0; _dataflow_plus_valid_61 <= 0; _dataflow_minus_data_62 <= 0; _dataflow_minus_valid_62 <= 0; _dataflow_minus_data_63 <= 0; _dataflow_minus_valid_63 <= 0; _dataflow_plus_data_70 <= 0; _dataflow_plus_valid_70 <= 0; _dataflow_plus_data_71 <= 0; _dataflow_plus_valid_71 <= 0; _dataflow_minus_data_72 <= 0; _dataflow_minus_valid_72 <= 0; _dataflow_minus_data_73 <= 0; _dataflow_minus_valid_73 <= 0; _dataflow__delay_data_160 <= 0; _dataflow__delay_valid_160 <= 0; _dataflow__delay_data_163 <= 0; _dataflow__delay_valid_163 <= 0; _dataflow__delay_data_166 <= 0; _dataflow__delay_valid_166 <= 0; _dataflow__delay_data_168 <= 0; _dataflow__delay_valid_168 <= 0; _dataflow__delay_data_170 <= 0; _dataflow__delay_valid_170 <= 0; _dataflow__delay_data_172 <= 0; _dataflow__delay_valid_172 <= 0; _dataflow__delay_data_174 <= 0; _dataflow__delay_valid_174 <= 0; _dataflow__delay_data_185 <= 0; _dataflow__delay_valid_185 <= 0; _dataflow__delay_data_196 <= 0; _dataflow__delay_valid_196 <= 0; _dataflow__delay_data_197 <= 0; _dataflow__delay_valid_197 <= 0; _dataflow__delay_data_198 <= 0; _dataflow__delay_valid_198 <= 0; _dataflow__delay_data_199 <= 0; _dataflow__delay_valid_199 <= 0; _dataflow__delay_data_200 <= 0; _dataflow__delay_valid_200 <= 0; _dataflow__delay_data_201 <= 0; _dataflow__delay_valid_201 <= 0; _dataflow__delay_data_202 <= 0; _dataflow__delay_valid_202 <= 0; _dataflow__delay_data_203 <= 0; _dataflow__delay_valid_203 <= 0; _dataflow__delay_data_204 <= 0; _dataflow__delay_valid_204 <= 0; _dataflow__delay_data_215 <= 0; _dataflow__delay_valid_215 <= 0; _dataflow__delay_data_226 <= 0; _dataflow__delay_valid_226 <= 0; _dataflow__delay_data_236 <= 0; _dataflow__delay_valid_236 <= 0; _dataflow__delay_data_246 <= 0; _dataflow__delay_valid_246 <= 0; _dataflow__delay_data_256 <= 0; _dataflow__delay_valid_256 <= 0; _dataflow__delay_data_266 <= 0; _dataflow__delay_valid_266 <= 0; _dataflow__delay_data_285 <= 0; _dataflow__delay_valid_285 <= 0; _dataflow_times_mul_odata_reg_44 <= 0; _dataflow_times_mul_valid_reg_44 <= 0; _dataflow_times_mul_odata_reg_45 <= 0; _dataflow_times_mul_valid_reg_45 <= 0; _dataflow_times_mul_odata_reg_46 <= 0; _dataflow_times_mul_valid_reg_46 <= 0; _dataflow_times_mul_odata_reg_47 <= 0; _dataflow_times_mul_valid_reg_47 <= 0; _dataflow_times_mul_odata_reg_54 <= 0; _dataflow_times_mul_valid_reg_54 <= 0; _dataflow_times_mul_odata_reg_55 <= 0; _dataflow_times_mul_valid_reg_55 <= 0; _dataflow_times_mul_odata_reg_56 <= 0; _dataflow_times_mul_valid_reg_56 <= 0; _dataflow_times_mul_odata_reg_57 <= 0; _dataflow_times_mul_valid_reg_57 <= 0; _dataflow_times_mul_odata_reg_64 <= 0; _dataflow_times_mul_valid_reg_64 <= 0; _dataflow_times_mul_odata_reg_65 <= 0; _dataflow_times_mul_valid_reg_65 <= 0; _dataflow_times_mul_odata_reg_66 <= 0; _dataflow_times_mul_valid_reg_66 <= 0; _dataflow_times_mul_odata_reg_67 <= 0; _dataflow_times_mul_valid_reg_67 <= 0; _dataflow_times_mul_odata_reg_74 <= 0; _dataflow_times_mul_valid_reg_74 <= 0; _dataflow_times_mul_odata_reg_75 <= 0; _dataflow_times_mul_valid_reg_75 <= 0; _dataflow_times_mul_odata_reg_76 <= 0; _dataflow_times_mul_valid_reg_76 <= 0; _dataflow_times_mul_odata_reg_77 <= 0; _dataflow_times_mul_valid_reg_77 <= 0; _dataflow_plus_data_80 <= 0; _dataflow_plus_valid_80 <= 0; _dataflow_plus_data_81 <= 0; _dataflow_plus_valid_81 <= 0; _dataflow_minus_data_82 <= 0; _dataflow_minus_valid_82 <= 0; _dataflow_minus_data_83 <= 0; _dataflow_minus_valid_83 <= 0; _dataflow_plus_data_90 <= 0; _dataflow_plus_valid_90 <= 0; _dataflow_plus_data_91 <= 0; _dataflow_plus_valid_91 <= 0; _dataflow_minus_data_92 <= 0; _dataflow_minus_valid_92 <= 0; _dataflow_minus_data_93 <= 0; _dataflow_minus_valid_93 <= 0; _dataflow__delay_data_161 <= 0; _dataflow__delay_valid_161 <= 0; _dataflow__delay_data_164 <= 0; _dataflow__delay_valid_164 <= 0; _dataflow__delay_data_167 <= 0; _dataflow__delay_valid_167 <= 0; _dataflow__delay_data_169 <= 0; _dataflow__delay_valid_169 <= 0; _dataflow__delay_data_171 <= 0; _dataflow__delay_valid_171 <= 0; _dataflow__delay_data_173 <= 0; _dataflow__delay_valid_173 <= 0; _dataflow__delay_data_175 <= 0; _dataflow__delay_valid_175 <= 0; _dataflow__delay_data_186 <= 0; _dataflow__delay_valid_186 <= 0; _dataflow__delay_data_205 <= 0; _dataflow__delay_valid_205 <= 0; _dataflow__delay_data_216 <= 0; _dataflow__delay_valid_216 <= 0; _dataflow__delay_data_227 <= 0; _dataflow__delay_valid_227 <= 0; _dataflow__delay_data_237 <= 0; _dataflow__delay_valid_237 <= 0; _dataflow__delay_data_247 <= 0; _dataflow__delay_valid_247 <= 0; _dataflow__delay_data_257 <= 0; _dataflow__delay_valid_257 <= 0; _dataflow__delay_data_267 <= 0; _dataflow__delay_valid_267 <= 0; _dataflow__delay_data_286 <= 0; _dataflow__delay_valid_286 <= 0; _dataflow_times_mul_odata_reg_84 <= 0; _dataflow_times_mul_valid_reg_84 <= 0; _dataflow_times_mul_odata_reg_85 <= 0; _dataflow_times_mul_valid_reg_85 <= 0; _dataflow_times_mul_odata_reg_86 <= 0; _dataflow_times_mul_valid_reg_86 <= 0; _dataflow_times_mul_odata_reg_87 <= 0; _dataflow_times_mul_valid_reg_87 <= 0; _dataflow_times_mul_odata_reg_94 <= 0; _dataflow_times_mul_valid_reg_94 <= 0; _dataflow_times_mul_odata_reg_95 <= 0; _dataflow_times_mul_valid_reg_95 <= 0; _dataflow_times_mul_odata_reg_96 <= 0; _dataflow_times_mul_valid_reg_96 <= 0; _dataflow_times_mul_odata_reg_97 <= 0; _dataflow_times_mul_valid_reg_97 <= 0; _dataflow_plus_data_120 <= 0; _dataflow_plus_valid_120 <= 0; _dataflow_plus_data_121 <= 0; _dataflow_plus_valid_121 <= 0; _dataflow_minus_data_122 <= 0; _dataflow_minus_valid_122 <= 0; _dataflow_minus_data_123 <= 0; _dataflow_minus_valid_123 <= 0; _dataflow__delay_data_162 <= 0; _dataflow__delay_valid_162 <= 0; _dataflow__delay_data_165 <= 0; _dataflow__delay_valid_165 <= 0; _dataflow__delay_data_176 <= 0; _dataflow__delay_valid_176 <= 0; _dataflow__delay_data_187 <= 0; _dataflow__delay_valid_187 <= 0; _dataflow__delay_data_206 <= 0; _dataflow__delay_valid_206 <= 0; _dataflow__delay_data_217 <= 0; _dataflow__delay_valid_217 <= 0; _dataflow__delay_data_228 <= 0; _dataflow__delay_valid_228 <= 0; _dataflow__delay_data_238 <= 0; _dataflow__delay_valid_238 <= 0; _dataflow__delay_data_248 <= 0; _dataflow__delay_valid_248 <= 0; _dataflow__delay_data_258 <= 0; _dataflow__delay_valid_258 <= 0; _dataflow__delay_data_268 <= 0; _dataflow__delay_valid_268 <= 0; _dataflow__delay_data_287 <= 0; _dataflow__delay_valid_287 <= 0; _dataflow_times_mul_odata_reg_124 <= 0; _dataflow_times_mul_valid_reg_124 <= 0; _dataflow_times_mul_odata_reg_125 <= 0; _dataflow_times_mul_valid_reg_125 <= 0; _dataflow_times_mul_odata_reg_126 <= 0; _dataflow_times_mul_valid_reg_126 <= 0; _dataflow_times_mul_odata_reg_127 <= 0; _dataflow_times_mul_valid_reg_127 <= 0; _dataflow__delay_data_177 <= 0; _dataflow__delay_valid_177 <= 0; _dataflow__delay_data_188 <= 0; _dataflow__delay_valid_188 <= 0; _dataflow__delay_data_207 <= 0; _dataflow__delay_valid_207 <= 0; _dataflow__delay_data_218 <= 0; _dataflow__delay_valid_218 <= 0; _dataflow__delay_data_229 <= 0; _dataflow__delay_valid_229 <= 0; _dataflow__delay_data_239 <= 0; _dataflow__delay_valid_239 <= 0; _dataflow__delay_data_249 <= 0; _dataflow__delay_valid_249 <= 0; _dataflow__delay_data_259 <= 0; _dataflow__delay_valid_259 <= 0; _dataflow__delay_data_269 <= 0; _dataflow__delay_valid_269 <= 0; _dataflow__delay_data_288 <= 0; _dataflow__delay_valid_288 <= 0; _dataflow__delay_data_304 <= 0; _dataflow__delay_valid_304 <= 0; _dataflow__delay_data_328 <= 0; _dataflow__delay_valid_328 <= 0; _dataflow__delay_data_178 <= 0; _dataflow__delay_valid_178 <= 0; _dataflow__delay_data_189 <= 0; _dataflow__delay_valid_189 <= 0; _dataflow__delay_data_208 <= 0; _dataflow__delay_valid_208 <= 0; _dataflow__delay_data_219 <= 0; _dataflow__delay_valid_219 <= 0; _dataflow__delay_data_230 <= 0; _dataflow__delay_valid_230 <= 0; _dataflow__delay_data_240 <= 0; _dataflow__delay_valid_240 <= 0; _dataflow__delay_data_250 <= 0; _dataflow__delay_valid_250 <= 0; _dataflow__delay_data_260 <= 0; _dataflow__delay_valid_260 <= 0; _dataflow__delay_data_270 <= 0; _dataflow__delay_valid_270 <= 0; _dataflow__delay_data_289 <= 0; _dataflow__delay_valid_289 <= 0; _dataflow__delay_data_305 <= 0; _dataflow__delay_valid_305 <= 0; _dataflow__delay_data_329 <= 0; _dataflow__delay_valid_329 <= 0; _dataflow__delay_data_179 <= 0; _dataflow__delay_valid_179 <= 0; _dataflow__delay_data_190 <= 0; _dataflow__delay_valid_190 <= 0; _dataflow__delay_data_209 <= 0; _dataflow__delay_valid_209 <= 0; _dataflow__delay_data_220 <= 0; _dataflow__delay_valid_220 <= 0; _dataflow__delay_data_231 <= 0; _dataflow__delay_valid_231 <= 0; _dataflow__delay_data_241 <= 0; _dataflow__delay_valid_241 <= 0; _dataflow__delay_data_251 <= 0; _dataflow__delay_valid_251 <= 0; _dataflow__delay_data_261 <= 0; _dataflow__delay_valid_261 <= 0; _dataflow__delay_data_271 <= 0; _dataflow__delay_valid_271 <= 0; _dataflow__delay_data_290 <= 0; _dataflow__delay_valid_290 <= 0; _dataflow__delay_data_306 <= 0; _dataflow__delay_valid_306 <= 0; _dataflow__delay_data_330 <= 0; _dataflow__delay_valid_330 <= 0; _dataflow__delay_data_180 <= 0; _dataflow__delay_valid_180 <= 0; _dataflow__delay_data_191 <= 0; _dataflow__delay_valid_191 <= 0; _dataflow__delay_data_210 <= 0; _dataflow__delay_valid_210 <= 0; _dataflow__delay_data_221 <= 0; _dataflow__delay_valid_221 <= 0; _dataflow__delay_data_232 <= 0; _dataflow__delay_valid_232 <= 0; _dataflow__delay_data_242 <= 0; _dataflow__delay_valid_242 <= 0; _dataflow__delay_data_252 <= 0; _dataflow__delay_valid_252 <= 0; _dataflow__delay_data_262 <= 0; _dataflow__delay_valid_262 <= 0; _dataflow__delay_data_272 <= 0; _dataflow__delay_valid_272 <= 0; _dataflow__delay_data_291 <= 0; _dataflow__delay_valid_291 <= 0; _dataflow__delay_data_307 <= 0; _dataflow__delay_valid_307 <= 0; _dataflow__delay_data_331 <= 0; _dataflow__delay_valid_331 <= 0; _dataflow__delay_data_181 <= 0; _dataflow__delay_valid_181 <= 0; _dataflow__delay_data_192 <= 0; _dataflow__delay_valid_192 <= 0; _dataflow__delay_data_211 <= 0; _dataflow__delay_valid_211 <= 0; _dataflow__delay_data_222 <= 0; _dataflow__delay_valid_222 <= 0; _dataflow__delay_data_233 <= 0; _dataflow__delay_valid_233 <= 0; _dataflow__delay_data_243 <= 0; _dataflow__delay_valid_243 <= 0; _dataflow__delay_data_253 <= 0; _dataflow__delay_valid_253 <= 0; _dataflow__delay_data_263 <= 0; _dataflow__delay_valid_263 <= 0; _dataflow__delay_data_273 <= 0; _dataflow__delay_valid_273 <= 0; _dataflow__delay_data_292 <= 0; _dataflow__delay_valid_292 <= 0; _dataflow__delay_data_308 <= 0; _dataflow__delay_valid_308 <= 0; _dataflow__delay_data_332 <= 0; _dataflow__delay_valid_332 <= 0; _dataflow_minus_data_48 <= 0; _dataflow_minus_valid_48 <= 0; _dataflow_plus_data_49 <= 0; _dataflow_plus_valid_49 <= 0; _dataflow_minus_data_58 <= 0; _dataflow_minus_valid_58 <= 0; _dataflow_plus_data_59 <= 0; _dataflow_plus_valid_59 <= 0; _dataflow_minus_data_68 <= 0; _dataflow_minus_valid_68 <= 0; _dataflow_plus_data_69 <= 0; _dataflow_plus_valid_69 <= 0; _dataflow_minus_data_78 <= 0; _dataflow_minus_valid_78 <= 0; _dataflow_plus_data_79 <= 0; _dataflow_plus_valid_79 <= 0; _dataflow__delay_data_182 <= 0; _dataflow__delay_valid_182 <= 0; _dataflow__delay_data_193 <= 0; _dataflow__delay_valid_193 <= 0; _dataflow__delay_data_212 <= 0; _dataflow__delay_valid_212 <= 0; _dataflow__delay_data_223 <= 0; _dataflow__delay_valid_223 <= 0; _dataflow__delay_data_234 <= 0; _dataflow__delay_valid_234 <= 0; _dataflow__delay_data_244 <= 0; _dataflow__delay_valid_244 <= 0; _dataflow__delay_data_254 <= 0; _dataflow__delay_valid_254 <= 0; _dataflow__delay_data_264 <= 0; _dataflow__delay_valid_264 <= 0; _dataflow__delay_data_274 <= 0; _dataflow__delay_valid_274 <= 0; _dataflow__delay_data_293 <= 0; _dataflow__delay_valid_293 <= 0; _dataflow__delay_data_309 <= 0; _dataflow__delay_valid_309 <= 0; _dataflow__delay_data_333 <= 0; _dataflow__delay_valid_333 <= 0; _dataflow_minus_data_88 <= 0; _dataflow_minus_valid_88 <= 0; _dataflow_plus_data_89 <= 0; _dataflow_plus_valid_89 <= 0; _dataflow_minus_data_98 <= 0; _dataflow_minus_valid_98 <= 0; _dataflow_plus_data_99 <= 0; _dataflow_plus_valid_99 <= 0; _dataflow_plus_data_100 <= 0; _dataflow_plus_valid_100 <= 0; _dataflow_plus_data_101 <= 0; _dataflow_plus_valid_101 <= 0; _dataflow_minus_data_102 <= 0; _dataflow_minus_valid_102 <= 0; _dataflow_minus_data_103 <= 0; _dataflow_minus_valid_103 <= 0; _dataflow_plus_data_110 <= 0; _dataflow_plus_valid_110 <= 0; _dataflow_plus_data_111 <= 0; _dataflow_plus_valid_111 <= 0; _dataflow_minus_data_112 <= 0; _dataflow_minus_valid_112 <= 0; _dataflow_minus_data_113 <= 0; _dataflow_minus_valid_113 <= 0; _dataflow__delay_data_183 <= 0; _dataflow__delay_valid_183 <= 0; _dataflow__delay_data_194 <= 0; _dataflow__delay_valid_194 <= 0; _dataflow__delay_data_213 <= 0; _dataflow__delay_valid_213 <= 0; _dataflow__delay_data_224 <= 0; _dataflow__delay_valid_224 <= 0; _dataflow__delay_data_235 <= 0; _dataflow__delay_valid_235 <= 0; _dataflow__delay_data_245 <= 0; _dataflow__delay_valid_245 <= 0; _dataflow__delay_data_255 <= 0; _dataflow__delay_valid_255 <= 0; _dataflow__delay_data_265 <= 0; _dataflow__delay_valid_265 <= 0; _dataflow__delay_data_275 <= 0; _dataflow__delay_valid_275 <= 0; _dataflow__delay_data_294 <= 0; _dataflow__delay_valid_294 <= 0; _dataflow__delay_data_310 <= 0; _dataflow__delay_valid_310 <= 0; _dataflow__delay_data_334 <= 0; _dataflow__delay_valid_334 <= 0; _dataflow_times_mul_odata_reg_104 <= 0; _dataflow_times_mul_valid_reg_104 <= 0; _dataflow_times_mul_odata_reg_105 <= 0; _dataflow_times_mul_valid_reg_105 <= 0; _dataflow_times_mul_odata_reg_106 <= 0; _dataflow_times_mul_valid_reg_106 <= 0; _dataflow_times_mul_odata_reg_107 <= 0; _dataflow_times_mul_valid_reg_107 <= 0; _dataflow_times_mul_odata_reg_114 <= 0; _dataflow_times_mul_valid_reg_114 <= 0; _dataflow_times_mul_odata_reg_115 <= 0; _dataflow_times_mul_valid_reg_115 <= 0; _dataflow_times_mul_odata_reg_116 <= 0; _dataflow_times_mul_valid_reg_116 <= 0; _dataflow_times_mul_odata_reg_117 <= 0; _dataflow_times_mul_valid_reg_117 <= 0; _dataflow_minus_data_128 <= 0; _dataflow_minus_valid_128 <= 0; _dataflow_plus_data_129 <= 0; _dataflow_plus_valid_129 <= 0; _dataflow_plus_data_130 <= 0; _dataflow_plus_valid_130 <= 0; _dataflow_plus_data_131 <= 0; _dataflow_plus_valid_131 <= 0; _dataflow_minus_data_132 <= 0; _dataflow_minus_valid_132 <= 0; _dataflow_minus_data_133 <= 0; _dataflow_minus_valid_133 <= 0; _dataflow_plus_data_140 <= 0; _dataflow_plus_valid_140 <= 0; _dataflow_plus_data_141 <= 0; _dataflow_plus_valid_141 <= 0; _dataflow_minus_data_142 <= 0; _dataflow_minus_valid_142 <= 0; _dataflow_minus_data_143 <= 0; _dataflow_minus_valid_143 <= 0; _dataflow__delay_data_184 <= 0; _dataflow__delay_valid_184 <= 0; _dataflow__delay_data_195 <= 0; _dataflow__delay_valid_195 <= 0; _dataflow__delay_data_214 <= 0; _dataflow__delay_valid_214 <= 0; _dataflow__delay_data_225 <= 0; _dataflow__delay_valid_225 <= 0; _dataflow__delay_data_276 <= 0; _dataflow__delay_valid_276 <= 0; _dataflow__delay_data_295 <= 0; _dataflow__delay_valid_295 <= 0; _dataflow__delay_data_311 <= 0; _dataflow__delay_valid_311 <= 0; _dataflow__delay_data_335 <= 0; _dataflow__delay_valid_335 <= 0; _dataflow_times_mul_odata_reg_134 <= 0; _dataflow_times_mul_valid_reg_134 <= 0; _dataflow_times_mul_odata_reg_135 <= 0; _dataflow_times_mul_valid_reg_135 <= 0; _dataflow_times_mul_odata_reg_136 <= 0; _dataflow_times_mul_valid_reg_136 <= 0; _dataflow_times_mul_odata_reg_137 <= 0; _dataflow_times_mul_valid_reg_137 <= 0; _dataflow_times_mul_odata_reg_144 <= 0; _dataflow_times_mul_valid_reg_144 <= 0; _dataflow_times_mul_odata_reg_145 <= 0; _dataflow_times_mul_valid_reg_145 <= 0; _dataflow_times_mul_odata_reg_146 <= 0; _dataflow_times_mul_valid_reg_146 <= 0; _dataflow_times_mul_odata_reg_147 <= 0; _dataflow_times_mul_valid_reg_147 <= 0; _dataflow__delay_data_277 <= 0; _dataflow__delay_valid_277 <= 0; _dataflow__delay_data_296 <= 0; _dataflow__delay_valid_296 <= 0; _dataflow__delay_data_312 <= 0; _dataflow__delay_valid_312 <= 0; _dataflow__delay_data_336 <= 0; _dataflow__delay_valid_336 <= 0; _dataflow__delay_data_352 <= 0; _dataflow__delay_valid_352 <= 0; _dataflow__delay_data_368 <= 0; _dataflow__delay_valid_368 <= 0; _dataflow__delay_data_384 <= 0; _dataflow__delay_valid_384 <= 0; _dataflow__delay_data_400 <= 0; _dataflow__delay_valid_400 <= 0; _dataflow__delay_data_432 <= 0; _dataflow__delay_valid_432 <= 0; _dataflow__delay_data_448 <= 0; _dataflow__delay_valid_448 <= 0; _dataflow__delay_data_278 <= 0; _dataflow__delay_valid_278 <= 0; _dataflow__delay_data_297 <= 0; _dataflow__delay_valid_297 <= 0; _dataflow__delay_data_313 <= 0; _dataflow__delay_valid_313 <= 0; _dataflow__delay_data_337 <= 0; _dataflow__delay_valid_337 <= 0; _dataflow__delay_data_353 <= 0; _dataflow__delay_valid_353 <= 0; _dataflow__delay_data_369 <= 0; _dataflow__delay_valid_369 <= 0; _dataflow__delay_data_385 <= 0; _dataflow__delay_valid_385 <= 0; _dataflow__delay_data_401 <= 0; _dataflow__delay_valid_401 <= 0; _dataflow__delay_data_433 <= 0; _dataflow__delay_valid_433 <= 0; _dataflow__delay_data_449 <= 0; _dataflow__delay_valid_449 <= 0; _dataflow__delay_data_279 <= 0; _dataflow__delay_valid_279 <= 0; _dataflow__delay_data_298 <= 0; _dataflow__delay_valid_298 <= 0; _dataflow__delay_data_314 <= 0; _dataflow__delay_valid_314 <= 0; _dataflow__delay_data_338 <= 0; _dataflow__delay_valid_338 <= 0; _dataflow__delay_data_354 <= 0; _dataflow__delay_valid_354 <= 0; _dataflow__delay_data_370 <= 0; _dataflow__delay_valid_370 <= 0; _dataflow__delay_data_386 <= 0; _dataflow__delay_valid_386 <= 0; _dataflow__delay_data_402 <= 0; _dataflow__delay_valid_402 <= 0; _dataflow__delay_data_434 <= 0; _dataflow__delay_valid_434 <= 0; _dataflow__delay_data_450 <= 0; _dataflow__delay_valid_450 <= 0; _dataflow__delay_data_280 <= 0; _dataflow__delay_valid_280 <= 0; _dataflow__delay_data_299 <= 0; _dataflow__delay_valid_299 <= 0; _dataflow__delay_data_315 <= 0; _dataflow__delay_valid_315 <= 0; _dataflow__delay_data_339 <= 0; _dataflow__delay_valid_339 <= 0; _dataflow__delay_data_355 <= 0; _dataflow__delay_valid_355 <= 0; _dataflow__delay_data_371 <= 0; _dataflow__delay_valid_371 <= 0; _dataflow__delay_data_387 <= 0; _dataflow__delay_valid_387 <= 0; _dataflow__delay_data_403 <= 0; _dataflow__delay_valid_403 <= 0; _dataflow__delay_data_435 <= 0; _dataflow__delay_valid_435 <= 0; _dataflow__delay_data_451 <= 0; _dataflow__delay_valid_451 <= 0; _dataflow__delay_data_281 <= 0; _dataflow__delay_valid_281 <= 0; _dataflow__delay_data_300 <= 0; _dataflow__delay_valid_300 <= 0; _dataflow__delay_data_316 <= 0; _dataflow__delay_valid_316 <= 0; _dataflow__delay_data_340 <= 0; _dataflow__delay_valid_340 <= 0; _dataflow__delay_data_356 <= 0; _dataflow__delay_valid_356 <= 0; _dataflow__delay_data_372 <= 0; _dataflow__delay_valid_372 <= 0; _dataflow__delay_data_388 <= 0; _dataflow__delay_valid_388 <= 0; _dataflow__delay_data_404 <= 0; _dataflow__delay_valid_404 <= 0; _dataflow__delay_data_436 <= 0; _dataflow__delay_valid_436 <= 0; _dataflow__delay_data_452 <= 0; _dataflow__delay_valid_452 <= 0; _dataflow__delay_data_282 <= 0; _dataflow__delay_valid_282 <= 0; _dataflow__delay_data_301 <= 0; _dataflow__delay_valid_301 <= 0; _dataflow__delay_data_317 <= 0; _dataflow__delay_valid_317 <= 0; _dataflow__delay_data_341 <= 0; _dataflow__delay_valid_341 <= 0; _dataflow__delay_data_357 <= 0; _dataflow__delay_valid_357 <= 0; _dataflow__delay_data_373 <= 0; _dataflow__delay_valid_373 <= 0; _dataflow__delay_data_389 <= 0; _dataflow__delay_valid_389 <= 0; _dataflow__delay_data_405 <= 0; _dataflow__delay_valid_405 <= 0; _dataflow__delay_data_437 <= 0; _dataflow__delay_valid_437 <= 0; _dataflow__delay_data_453 <= 0; _dataflow__delay_valid_453 <= 0; _dataflow_minus_data_108 <= 0; _dataflow_minus_valid_108 <= 0; _dataflow_plus_data_109 <= 0; _dataflow_plus_valid_109 <= 0; _dataflow_minus_data_118 <= 0; _dataflow_minus_valid_118 <= 0; _dataflow_plus_data_119 <= 0; _dataflow_plus_valid_119 <= 0; _dataflow__delay_data_283 <= 0; _dataflow__delay_valid_283 <= 0; _dataflow__delay_data_302 <= 0; _dataflow__delay_valid_302 <= 0; _dataflow__delay_data_318 <= 0; _dataflow__delay_valid_318 <= 0; _dataflow__delay_data_342 <= 0; _dataflow__delay_valid_342 <= 0; _dataflow__delay_data_358 <= 0; _dataflow__delay_valid_358 <= 0; _dataflow__delay_data_374 <= 0; _dataflow__delay_valid_374 <= 0; _dataflow__delay_data_390 <= 0; _dataflow__delay_valid_390 <= 0; _dataflow__delay_data_406 <= 0; _dataflow__delay_valid_406 <= 0; _dataflow__delay_data_438 <= 0; _dataflow__delay_valid_438 <= 0; _dataflow__delay_data_454 <= 0; _dataflow__delay_valid_454 <= 0; _dataflow_minus_data_138 <= 0; _dataflow_minus_valid_138 <= 0; _dataflow_plus_data_139 <= 0; _dataflow_plus_valid_139 <= 0; _dataflow_minus_data_148 <= 0; _dataflow_minus_valid_148 <= 0; _dataflow_plus_data_149 <= 0; _dataflow_plus_valid_149 <= 0; _dataflow_plus_data_150 <= 0; _dataflow_plus_valid_150 <= 0; _dataflow_plus_data_151 <= 0; _dataflow_plus_valid_151 <= 0; _dataflow_minus_data_152 <= 0; _dataflow_minus_valid_152 <= 0; _dataflow_minus_data_153 <= 0; _dataflow_minus_valid_153 <= 0; _dataflow__delay_data_284 <= 0; _dataflow__delay_valid_284 <= 0; _dataflow__delay_data_303 <= 0; _dataflow__delay_valid_303 <= 0; _dataflow__delay_data_319 <= 0; _dataflow__delay_valid_319 <= 0; _dataflow__delay_data_343 <= 0; _dataflow__delay_valid_343 <= 0; _dataflow__delay_data_359 <= 0; _dataflow__delay_valid_359 <= 0; _dataflow__delay_data_375 <= 0; _dataflow__delay_valid_375 <= 0; _dataflow__delay_data_391 <= 0; _dataflow__delay_valid_391 <= 0; _dataflow__delay_data_407 <= 0; _dataflow__delay_valid_407 <= 0; _dataflow__delay_data_439 <= 0; _dataflow__delay_valid_439 <= 0; _dataflow__delay_data_455 <= 0; _dataflow__delay_valid_455 <= 0; _dataflow_times_mul_odata_reg_154 <= 0; _dataflow_times_mul_valid_reg_154 <= 0; _dataflow_times_mul_odata_reg_155 <= 0; _dataflow_times_mul_valid_reg_155 <= 0; _dataflow_times_mul_odata_reg_156 <= 0; _dataflow_times_mul_valid_reg_156 <= 0; _dataflow_times_mul_odata_reg_157 <= 0; _dataflow_times_mul_valid_reg_157 <= 0; _dataflow__delay_data_320 <= 0; _dataflow__delay_valid_320 <= 0; _dataflow__delay_data_344 <= 0; _dataflow__delay_valid_344 <= 0; _dataflow__delay_data_360 <= 0; _dataflow__delay_valid_360 <= 0; _dataflow__delay_data_376 <= 0; _dataflow__delay_valid_376 <= 0; _dataflow__delay_data_392 <= 0; _dataflow__delay_valid_392 <= 0; _dataflow__delay_data_408 <= 0; _dataflow__delay_valid_408 <= 0; _dataflow__delay_data_416 <= 0; _dataflow__delay_valid_416 <= 0; _dataflow__delay_data_424 <= 0; _dataflow__delay_valid_424 <= 0; _dataflow__delay_data_440 <= 0; _dataflow__delay_valid_440 <= 0; _dataflow__delay_data_456 <= 0; _dataflow__delay_valid_456 <= 0; _dataflow__delay_data_464 <= 0; _dataflow__delay_valid_464 <= 0; _dataflow__delay_data_472 <= 0; _dataflow__delay_valid_472 <= 0; _dataflow__delay_data_480 <= 0; _dataflow__delay_valid_480 <= 0; _dataflow__delay_data_488 <= 0; _dataflow__delay_valid_488 <= 0; _dataflow__delay_data_321 <= 0; _dataflow__delay_valid_321 <= 0; _dataflow__delay_data_345 <= 0; _dataflow__delay_valid_345 <= 0; _dataflow__delay_data_361 <= 0; _dataflow__delay_valid_361 <= 0; _dataflow__delay_data_377 <= 0; _dataflow__delay_valid_377 <= 0; _dataflow__delay_data_393 <= 0; _dataflow__delay_valid_393 <= 0; _dataflow__delay_data_409 <= 0; _dataflow__delay_valid_409 <= 0; _dataflow__delay_data_417 <= 0; _dataflow__delay_valid_417 <= 0; _dataflow__delay_data_425 <= 0; _dataflow__delay_valid_425 <= 0; _dataflow__delay_data_441 <= 0; _dataflow__delay_valid_441 <= 0; _dataflow__delay_data_457 <= 0; _dataflow__delay_valid_457 <= 0; _dataflow__delay_data_465 <= 0; _dataflow__delay_valid_465 <= 0; _dataflow__delay_data_473 <= 0; _dataflow__delay_valid_473 <= 0; _dataflow__delay_data_481 <= 0; _dataflow__delay_valid_481 <= 0; _dataflow__delay_data_489 <= 0; _dataflow__delay_valid_489 <= 0; _dataflow__delay_data_322 <= 0; _dataflow__delay_valid_322 <= 0; _dataflow__delay_data_346 <= 0; _dataflow__delay_valid_346 <= 0; _dataflow__delay_data_362 <= 0; _dataflow__delay_valid_362 <= 0; _dataflow__delay_data_378 <= 0; _dataflow__delay_valid_378 <= 0; _dataflow__delay_data_394 <= 0; _dataflow__delay_valid_394 <= 0; _dataflow__delay_data_410 <= 0; _dataflow__delay_valid_410 <= 0; _dataflow__delay_data_418 <= 0; _dataflow__delay_valid_418 <= 0; _dataflow__delay_data_426 <= 0; _dataflow__delay_valid_426 <= 0; _dataflow__delay_data_442 <= 0; _dataflow__delay_valid_442 <= 0; _dataflow__delay_data_458 <= 0; _dataflow__delay_valid_458 <= 0; _dataflow__delay_data_466 <= 0; _dataflow__delay_valid_466 <= 0; _dataflow__delay_data_474 <= 0; _dataflow__delay_valid_474 <= 0; _dataflow__delay_data_482 <= 0; _dataflow__delay_valid_482 <= 0; _dataflow__delay_data_490 <= 0; _dataflow__delay_valid_490 <= 0; _dataflow__delay_data_323 <= 0; _dataflow__delay_valid_323 <= 0; _dataflow__delay_data_347 <= 0; _dataflow__delay_valid_347 <= 0; _dataflow__delay_data_363 <= 0; _dataflow__delay_valid_363 <= 0; _dataflow__delay_data_379 <= 0; _dataflow__delay_valid_379 <= 0; _dataflow__delay_data_395 <= 0; _dataflow__delay_valid_395 <= 0; _dataflow__delay_data_411 <= 0; _dataflow__delay_valid_411 <= 0; _dataflow__delay_data_419 <= 0; _dataflow__delay_valid_419 <= 0; _dataflow__delay_data_427 <= 0; _dataflow__delay_valid_427 <= 0; _dataflow__delay_data_443 <= 0; _dataflow__delay_valid_443 <= 0; _dataflow__delay_data_459 <= 0; _dataflow__delay_valid_459 <= 0; _dataflow__delay_data_467 <= 0; _dataflow__delay_valid_467 <= 0; _dataflow__delay_data_475 <= 0; _dataflow__delay_valid_475 <= 0; _dataflow__delay_data_483 <= 0; _dataflow__delay_valid_483 <= 0; _dataflow__delay_data_491 <= 0; _dataflow__delay_valid_491 <= 0; _dataflow__delay_data_324 <= 0; _dataflow__delay_valid_324 <= 0; _dataflow__delay_data_348 <= 0; _dataflow__delay_valid_348 <= 0; _dataflow__delay_data_364 <= 0; _dataflow__delay_valid_364 <= 0; _dataflow__delay_data_380 <= 0; _dataflow__delay_valid_380 <= 0; _dataflow__delay_data_396 <= 0; _dataflow__delay_valid_396 <= 0; _dataflow__delay_data_412 <= 0; _dataflow__delay_valid_412 <= 0; _dataflow__delay_data_420 <= 0; _dataflow__delay_valid_420 <= 0; _dataflow__delay_data_428 <= 0; _dataflow__delay_valid_428 <= 0; _dataflow__delay_data_444 <= 0; _dataflow__delay_valid_444 <= 0; _dataflow__delay_data_460 <= 0; _dataflow__delay_valid_460 <= 0; _dataflow__delay_data_468 <= 0; _dataflow__delay_valid_468 <= 0; _dataflow__delay_data_476 <= 0; _dataflow__delay_valid_476 <= 0; _dataflow__delay_data_484 <= 0; _dataflow__delay_valid_484 <= 0; _dataflow__delay_data_492 <= 0; _dataflow__delay_valid_492 <= 0; _dataflow__delay_data_325 <= 0; _dataflow__delay_valid_325 <= 0; _dataflow__delay_data_349 <= 0; _dataflow__delay_valid_349 <= 0; _dataflow__delay_data_365 <= 0; _dataflow__delay_valid_365 <= 0; _dataflow__delay_data_381 <= 0; _dataflow__delay_valid_381 <= 0; _dataflow__delay_data_397 <= 0; _dataflow__delay_valid_397 <= 0; _dataflow__delay_data_413 <= 0; _dataflow__delay_valid_413 <= 0; _dataflow__delay_data_421 <= 0; _dataflow__delay_valid_421 <= 0; _dataflow__delay_data_429 <= 0; _dataflow__delay_valid_429 <= 0; _dataflow__delay_data_445 <= 0; _dataflow__delay_valid_445 <= 0; _dataflow__delay_data_461 <= 0; _dataflow__delay_valid_461 <= 0; _dataflow__delay_data_469 <= 0; _dataflow__delay_valid_469 <= 0; _dataflow__delay_data_477 <= 0; _dataflow__delay_valid_477 <= 0; _dataflow__delay_data_485 <= 0; _dataflow__delay_valid_485 <= 0; _dataflow__delay_data_493 <= 0; _dataflow__delay_valid_493 <= 0; _dataflow__delay_data_326 <= 0; _dataflow__delay_valid_326 <= 0; _dataflow__delay_data_350 <= 0; _dataflow__delay_valid_350 <= 0; _dataflow__delay_data_366 <= 0; _dataflow__delay_valid_366 <= 0; _dataflow__delay_data_382 <= 0; _dataflow__delay_valid_382 <= 0; _dataflow__delay_data_398 <= 0; _dataflow__delay_valid_398 <= 0; _dataflow__delay_data_414 <= 0; _dataflow__delay_valid_414 <= 0; _dataflow__delay_data_422 <= 0; _dataflow__delay_valid_422 <= 0; _dataflow__delay_data_430 <= 0; _dataflow__delay_valid_430 <= 0; _dataflow__delay_data_446 <= 0; _dataflow__delay_valid_446 <= 0; _dataflow__delay_data_462 <= 0; _dataflow__delay_valid_462 <= 0; _dataflow__delay_data_470 <= 0; _dataflow__delay_valid_470 <= 0; _dataflow__delay_data_478 <= 0; _dataflow__delay_valid_478 <= 0; _dataflow__delay_data_486 <= 0; _dataflow__delay_valid_486 <= 0; _dataflow__delay_data_494 <= 0; _dataflow__delay_valid_494 <= 0; _dataflow_minus_data_158 <= 0; _dataflow_minus_valid_158 <= 0; _dataflow_plus_data_159 <= 0; _dataflow_plus_valid_159 <= 0; _dataflow__delay_data_327 <= 0; _dataflow__delay_valid_327 <= 0; _dataflow__delay_data_351 <= 0; _dataflow__delay_valid_351 <= 0; _dataflow__delay_data_367 <= 0; _dataflow__delay_valid_367 <= 0; _dataflow__delay_data_383 <= 0; _dataflow__delay_valid_383 <= 0; _dataflow__delay_data_399 <= 0; _dataflow__delay_valid_399 <= 0; _dataflow__delay_data_415 <= 0; _dataflow__delay_valid_415 <= 0; _dataflow__delay_data_423 <= 0; _dataflow__delay_valid_423 <= 0; _dataflow__delay_data_431 <= 0; _dataflow__delay_valid_431 <= 0; _dataflow__delay_data_447 <= 0; _dataflow__delay_valid_447 <= 0; _dataflow__delay_data_463 <= 0; _dataflow__delay_valid_463 <= 0; _dataflow__delay_data_471 <= 0; _dataflow__delay_valid_471 <= 0; _dataflow__delay_data_479 <= 0; _dataflow__delay_valid_479 <= 0; _dataflow__delay_data_487 <= 0; _dataflow__delay_valid_487 <= 0; _dataflow__delay_data_495 <= 0; _dataflow__delay_valid_495 <= 0; end else begin if((_dataflow_plus_ready_40 || !_dataflow_plus_valid_40) && 1 && 1) begin _dataflow_plus_data_40 <= din0re + din4re; end if(_dataflow_plus_valid_40 && _dataflow_plus_ready_40) begin _dataflow_plus_valid_40 <= 0; end if((_dataflow_plus_ready_40 || !_dataflow_plus_valid_40) && 1) begin _dataflow_plus_valid_40 <= 1; end if((_dataflow_plus_ready_41 || !_dataflow_plus_valid_41) && 1 && 1) begin _dataflow_plus_data_41 <= din0im + din4im; end if(_dataflow_plus_valid_41 && _dataflow_plus_ready_41) begin _dataflow_plus_valid_41 <= 0; end if((_dataflow_plus_ready_41 || !_dataflow_plus_valid_41) && 1) begin _dataflow_plus_valid_41 <= 1; end if((_dataflow_minus_ready_42 || !_dataflow_minus_valid_42) && 1 && 1) begin _dataflow_minus_data_42 <= din0re - din4re; end if(_dataflow_minus_valid_42 && _dataflow_minus_ready_42) begin _dataflow_minus_valid_42 <= 0; end if((_dataflow_minus_ready_42 || !_dataflow_minus_valid_42) && 1) begin _dataflow_minus_valid_42 <= 1; end if((_dataflow_minus_ready_43 || !_dataflow_minus_valid_43) && 1 && 1) begin _dataflow_minus_data_43 <= din0im - din4im; end if(_dataflow_minus_valid_43 && _dataflow_minus_ready_43) begin _dataflow_minus_valid_43 <= 0; end if((_dataflow_minus_ready_43 || !_dataflow_minus_valid_43) && 1) begin _dataflow_minus_valid_43 <= 1; end if((_dataflow_plus_ready_50 || !_dataflow_plus_valid_50) && 1 && 1) begin _dataflow_plus_data_50 <= din1re + din5re; end if(_dataflow_plus_valid_50 && _dataflow_plus_ready_50) begin _dataflow_plus_valid_50 <= 0; end if((_dataflow_plus_ready_50 || !_dataflow_plus_valid_50) && 1) begin _dataflow_plus_valid_50 <= 1; end if((_dataflow_plus_ready_51 || !_dataflow_plus_valid_51) && 1 && 1) begin _dataflow_plus_data_51 <= din1im + din5im; end if(_dataflow_plus_valid_51 && _dataflow_plus_ready_51) begin _dataflow_plus_valid_51 <= 0; end if((_dataflow_plus_ready_51 || !_dataflow_plus_valid_51) && 1) begin _dataflow_plus_valid_51 <= 1; end if((_dataflow_minus_ready_52 || !_dataflow_minus_valid_52) && 1 && 1) begin _dataflow_minus_data_52 <= din1re - din5re; end if(_dataflow_minus_valid_52 && _dataflow_minus_ready_52) begin _dataflow_minus_valid_52 <= 0; end if((_dataflow_minus_ready_52 || !_dataflow_minus_valid_52) && 1) begin _dataflow_minus_valid_52 <= 1; end if((_dataflow_minus_ready_53 || !_dataflow_minus_valid_53) && 1 && 1) begin _dataflow_minus_data_53 <= din1im - din5im; end if(_dataflow_minus_valid_53 && _dataflow_minus_ready_53) begin _dataflow_minus_valid_53 <= 0; end if((_dataflow_minus_ready_53 || !_dataflow_minus_valid_53) && 1) begin _dataflow_minus_valid_53 <= 1; end if((_dataflow_plus_ready_60 || !_dataflow_plus_valid_60) && 1 && 1) begin _dataflow_plus_data_60 <= din2re + din6re; end if(_dataflow_plus_valid_60 && _dataflow_plus_ready_60) begin _dataflow_plus_valid_60 <= 0; end if((_dataflow_plus_ready_60 || !_dataflow_plus_valid_60) && 1) begin _dataflow_plus_valid_60 <= 1; end if((_dataflow_plus_ready_61 || !_dataflow_plus_valid_61) && 1 && 1) begin _dataflow_plus_data_61 <= din2im + din6im; end if(_dataflow_plus_valid_61 && _dataflow_plus_ready_61) begin _dataflow_plus_valid_61 <= 0; end if((_dataflow_plus_ready_61 || !_dataflow_plus_valid_61) && 1) begin _dataflow_plus_valid_61 <= 1; end if((_dataflow_minus_ready_62 || !_dataflow_minus_valid_62) && 1 && 1) begin _dataflow_minus_data_62 <= din2re - din6re; end if(_dataflow_minus_valid_62 && _dataflow_minus_ready_62) begin _dataflow_minus_valid_62 <= 0; end if((_dataflow_minus_ready_62 || !_dataflow_minus_valid_62) && 1) begin _dataflow_minus_valid_62 <= 1; end if((_dataflow_minus_ready_63 || !_dataflow_minus_valid_63) && 1 && 1) begin _dataflow_minus_data_63 <= din2im - din6im; end if(_dataflow_minus_valid_63 && _dataflow_minus_ready_63) begin _dataflow_minus_valid_63 <= 0; end if((_dataflow_minus_ready_63 || !_dataflow_minus_valid_63) && 1) begin _dataflow_minus_valid_63 <= 1; end if((_dataflow_plus_ready_70 || !_dataflow_plus_valid_70) && 1 && 1) begin _dataflow_plus_data_70 <= din3re + din7re; end if(_dataflow_plus_valid_70 && _dataflow_plus_ready_70) begin _dataflow_plus_valid_70 <= 0; end if((_dataflow_plus_ready_70 || !_dataflow_plus_valid_70) && 1) begin _dataflow_plus_valid_70 <= 1; end if((_dataflow_plus_ready_71 || !_dataflow_plus_valid_71) && 1 && 1) begin _dataflow_plus_data_71 <= din3im + din7im; end if(_dataflow_plus_valid_71 && _dataflow_plus_ready_71) begin _dataflow_plus_valid_71 <= 0; end if((_dataflow_plus_ready_71 || !_dataflow_plus_valid_71) && 1) begin _dataflow_plus_valid_71 <= 1; end if((_dataflow_minus_ready_72 || !_dataflow_minus_valid_72) && 1 && 1) begin _dataflow_minus_data_72 <= din3re - din7re; end if(_dataflow_minus_valid_72 && _dataflow_minus_ready_72) begin _dataflow_minus_valid_72 <= 0; end if((_dataflow_minus_ready_72 || !_dataflow_minus_valid_72) && 1) begin _dataflow_minus_valid_72 <= 1; end if((_dataflow_minus_ready_73 || !_dataflow_minus_valid_73) && 1 && 1) begin _dataflow_minus_data_73 <= din3im - din7im; end if(_dataflow_minus_valid_73 && _dataflow_minus_ready_73) begin _dataflow_minus_valid_73 <= 0; end if((_dataflow_minus_ready_73 || !_dataflow_minus_valid_73) && 1) begin _dataflow_minus_valid_73 <= 1; end if((_dataflow__delay_ready_160 || !_dataflow__delay_valid_160) && 1 && 1) begin _dataflow__delay_data_160 <= weight8re; end if(_dataflow__delay_valid_160 && _dataflow__delay_ready_160) begin _dataflow__delay_valid_160 <= 0; end if((_dataflow__delay_ready_160 || !_dataflow__delay_valid_160) && 1) begin _dataflow__delay_valid_160 <= 1; end if((_dataflow__delay_ready_163 || !_dataflow__delay_valid_163) && 1 && 1) begin _dataflow__delay_data_163 <= weight8im; end if(_dataflow__delay_valid_163 && _dataflow__delay_ready_163) begin _dataflow__delay_valid_163 <= 0; end if((_dataflow__delay_ready_163 || !_dataflow__delay_valid_163) && 1) begin _dataflow__delay_valid_163 <= 1; end if((_dataflow__delay_ready_166 || !_dataflow__delay_valid_166) && 1 && 1) begin _dataflow__delay_data_166 <= weight4re; end if(_dataflow__delay_valid_166 && _dataflow__delay_ready_166) begin _dataflow__delay_valid_166 <= 0; end if((_dataflow__delay_ready_166 || !_dataflow__delay_valid_166) && 1) begin _dataflow__delay_valid_166 <= 1; end if((_dataflow__delay_ready_168 || !_dataflow__delay_valid_168) && 1 && 1) begin _dataflow__delay_data_168 <= weight4im; end if(_dataflow__delay_valid_168 && _dataflow__delay_ready_168) begin _dataflow__delay_valid_168 <= 0; end if((_dataflow__delay_ready_168 || !_dataflow__delay_valid_168) && 1) begin _dataflow__delay_valid_168 <= 1; end if((_dataflow__delay_ready_170 || !_dataflow__delay_valid_170) && 1 && 1) begin _dataflow__delay_data_170 <= weight5re; end if(_dataflow__delay_valid_170 && _dataflow__delay_ready_170) begin _dataflow__delay_valid_170 <= 0; end if((_dataflow__delay_ready_170 || !_dataflow__delay_valid_170) && 1) begin _dataflow__delay_valid_170 <= 1; end if((_dataflow__delay_ready_172 || !_dataflow__delay_valid_172) && 1 && 1) begin _dataflow__delay_data_172 <= weight5im; end if(_dataflow__delay_valid_172 && _dataflow__delay_ready_172) begin _dataflow__delay_valid_172 <= 0; end if((_dataflow__delay_ready_172 || !_dataflow__delay_valid_172) && 1) begin _dataflow__delay_valid_172 <= 1; end if((_dataflow__delay_ready_174 || !_dataflow__delay_valid_174) && 1 && 1) begin _dataflow__delay_data_174 <= weight9re; end if(_dataflow__delay_valid_174 && _dataflow__delay_ready_174) begin _dataflow__delay_valid_174 <= 0; end if((_dataflow__delay_ready_174 || !_dataflow__delay_valid_174) && 1) begin _dataflow__delay_valid_174 <= 1; end if((_dataflow__delay_ready_185 || !_dataflow__delay_valid_185) && 1 && 1) begin _dataflow__delay_data_185 <= weight9im; end if(_dataflow__delay_valid_185 && _dataflow__delay_ready_185) begin _dataflow__delay_valid_185 <= 0; end if((_dataflow__delay_ready_185 || !_dataflow__delay_valid_185) && 1) begin _dataflow__delay_valid_185 <= 1; end if((_dataflow__delay_ready_196 || !_dataflow__delay_valid_196) && 1 && 1) begin _dataflow__delay_data_196 <= weight0re; end if(_dataflow__delay_valid_196 && _dataflow__delay_ready_196) begin _dataflow__delay_valid_196 <= 0; end if((_dataflow__delay_ready_196 || !_dataflow__delay_valid_196) && 1) begin _dataflow__delay_valid_196 <= 1; end if((_dataflow__delay_ready_197 || !_dataflow__delay_valid_197) && 1 && 1) begin _dataflow__delay_data_197 <= weight0im; end if(_dataflow__delay_valid_197 && _dataflow__delay_ready_197) begin _dataflow__delay_valid_197 <= 0; end if((_dataflow__delay_ready_197 || !_dataflow__delay_valid_197) && 1) begin _dataflow__delay_valid_197 <= 1; end if((_dataflow__delay_ready_198 || !_dataflow__delay_valid_198) && 1 && 1) begin _dataflow__delay_data_198 <= weight2re; end if(_dataflow__delay_valid_198 && _dataflow__delay_ready_198) begin _dataflow__delay_valid_198 <= 0; end if((_dataflow__delay_ready_198 || !_dataflow__delay_valid_198) && 1) begin _dataflow__delay_valid_198 <= 1; end if((_dataflow__delay_ready_199 || !_dataflow__delay_valid_199) && 1 && 1) begin _dataflow__delay_data_199 <= weight2im; end if(_dataflow__delay_valid_199 && _dataflow__delay_ready_199) begin _dataflow__delay_valid_199 <= 0; end if((_dataflow__delay_ready_199 || !_dataflow__delay_valid_199) && 1) begin _dataflow__delay_valid_199 <= 1; end if((_dataflow__delay_ready_200 || !_dataflow__delay_valid_200) && 1 && 1) begin _dataflow__delay_data_200 <= weight1re; end if(_dataflow__delay_valid_200 && _dataflow__delay_ready_200) begin _dataflow__delay_valid_200 <= 0; end if((_dataflow__delay_ready_200 || !_dataflow__delay_valid_200) && 1) begin _dataflow__delay_valid_200 <= 1; end if((_dataflow__delay_ready_201 || !_dataflow__delay_valid_201) && 1 && 1) begin _dataflow__delay_data_201 <= weight1im; end if(_dataflow__delay_valid_201 && _dataflow__delay_ready_201) begin _dataflow__delay_valid_201 <= 0; end if((_dataflow__delay_ready_201 || !_dataflow__delay_valid_201) && 1) begin _dataflow__delay_valid_201 <= 1; end if((_dataflow__delay_ready_202 || !_dataflow__delay_valid_202) && 1 && 1) begin _dataflow__delay_data_202 <= weight3re; end if(_dataflow__delay_valid_202 && _dataflow__delay_ready_202) begin _dataflow__delay_valid_202 <= 0; end if((_dataflow__delay_ready_202 || !_dataflow__delay_valid_202) && 1) begin _dataflow__delay_valid_202 <= 1; end if((_dataflow__delay_ready_203 || !_dataflow__delay_valid_203) && 1 && 1) begin _dataflow__delay_data_203 <= weight3im; end if(_dataflow__delay_valid_203 && _dataflow__delay_ready_203) begin _dataflow__delay_valid_203 <= 0; end if((_dataflow__delay_ready_203 || !_dataflow__delay_valid_203) && 1) begin _dataflow__delay_valid_203 <= 1; end if((_dataflow__delay_ready_204 || !_dataflow__delay_valid_204) && 1 && 1) begin _dataflow__delay_data_204 <= weight10re; end if(_dataflow__delay_valid_204 && _dataflow__delay_ready_204) begin _dataflow__delay_valid_204 <= 0; end if((_dataflow__delay_ready_204 || !_dataflow__delay_valid_204) && 1) begin _dataflow__delay_valid_204 <= 1; end if((_dataflow__delay_ready_215 || !_dataflow__delay_valid_215) && 1 && 1) begin _dataflow__delay_data_215 <= weight10im; end if(_dataflow__delay_valid_215 && _dataflow__delay_ready_215) begin _dataflow__delay_valid_215 <= 0; end if((_dataflow__delay_ready_215 || !_dataflow__delay_valid_215) && 1) begin _dataflow__delay_valid_215 <= 1; end if((_dataflow__delay_ready_226 || !_dataflow__delay_valid_226) && 1 && 1) begin _dataflow__delay_data_226 <= weight6re; end if(_dataflow__delay_valid_226 && _dataflow__delay_ready_226) begin _dataflow__delay_valid_226 <= 0; end if((_dataflow__delay_ready_226 || !_dataflow__delay_valid_226) && 1) begin _dataflow__delay_valid_226 <= 1; end if((_dataflow__delay_ready_236 || !_dataflow__delay_valid_236) && 1 && 1) begin _dataflow__delay_data_236 <= weight6im; end if(_dataflow__delay_valid_236 && _dataflow__delay_ready_236) begin _dataflow__delay_valid_236 <= 0; end if((_dataflow__delay_ready_236 || !_dataflow__delay_valid_236) && 1) begin _dataflow__delay_valid_236 <= 1; end if((_dataflow__delay_ready_246 || !_dataflow__delay_valid_246) && 1 && 1) begin _dataflow__delay_data_246 <= weight7re; end if(_dataflow__delay_valid_246 && _dataflow__delay_ready_246) begin _dataflow__delay_valid_246 <= 0; end if((_dataflow__delay_ready_246 || !_dataflow__delay_valid_246) && 1) begin _dataflow__delay_valid_246 <= 1; end if((_dataflow__delay_ready_256 || !_dataflow__delay_valid_256) && 1 && 1) begin _dataflow__delay_data_256 <= weight7im; end if(_dataflow__delay_valid_256 && _dataflow__delay_ready_256) begin _dataflow__delay_valid_256 <= 0; end if((_dataflow__delay_ready_256 || !_dataflow__delay_valid_256) && 1) begin _dataflow__delay_valid_256 <= 1; end if((_dataflow__delay_ready_266 || !_dataflow__delay_valid_266) && 1 && 1) begin _dataflow__delay_data_266 <= weight11re; end if(_dataflow__delay_valid_266 && _dataflow__delay_ready_266) begin _dataflow__delay_valid_266 <= 0; end if((_dataflow__delay_ready_266 || !_dataflow__delay_valid_266) && 1) begin _dataflow__delay_valid_266 <= 1; end if((_dataflow__delay_ready_285 || !_dataflow__delay_valid_285) && 1 && 1) begin _dataflow__delay_data_285 <= weight11im; end if(_dataflow__delay_valid_285 && _dataflow__delay_ready_285) begin _dataflow__delay_valid_285 <= 0; end if((_dataflow__delay_ready_285 || !_dataflow__delay_valid_285) && 1) begin _dataflow__delay_valid_285 <= 1; end if(_dataflow_times_ready_44 || !_dataflow_times_valid_44) begin _dataflow_times_mul_odata_reg_44 <= _dataflow_times_mul_odata_44 >>> 8; end if(_dataflow_times_ready_44 || !_dataflow_times_valid_44) begin _dataflow_times_mul_valid_reg_44 <= _dataflow_times_mul_ovalid_44; end if(_dataflow_times_ready_45 || !_dataflow_times_valid_45) begin _dataflow_times_mul_odata_reg_45 <= _dataflow_times_mul_odata_45 >>> 8; end if(_dataflow_times_ready_45 || !_dataflow_times_valid_45) begin _dataflow_times_mul_valid_reg_45 <= _dataflow_times_mul_ovalid_45; end if(_dataflow_times_ready_46 || !_dataflow_times_valid_46) begin _dataflow_times_mul_odata_reg_46 <= _dataflow_times_mul_odata_46 >>> 8; end if(_dataflow_times_ready_46 || !_dataflow_times_valid_46) begin _dataflow_times_mul_valid_reg_46 <= _dataflow_times_mul_ovalid_46; end if(_dataflow_times_ready_47 || !_dataflow_times_valid_47) begin _dataflow_times_mul_odata_reg_47 <= _dataflow_times_mul_odata_47 >>> 8; end if(_dataflow_times_ready_47 || !_dataflow_times_valid_47) begin _dataflow_times_mul_valid_reg_47 <= _dataflow_times_mul_ovalid_47; end if(_dataflow_times_ready_54 || !_dataflow_times_valid_54) begin _dataflow_times_mul_odata_reg_54 <= _dataflow_times_mul_odata_54 >>> 8; end if(_dataflow_times_ready_54 || !_dataflow_times_valid_54) begin _dataflow_times_mul_valid_reg_54 <= _dataflow_times_mul_ovalid_54; end if(_dataflow_times_ready_55 || !_dataflow_times_valid_55) begin _dataflow_times_mul_odata_reg_55 <= _dataflow_times_mul_odata_55 >>> 8; end if(_dataflow_times_ready_55 || !_dataflow_times_valid_55) begin _dataflow_times_mul_valid_reg_55 <= _dataflow_times_mul_ovalid_55; end if(_dataflow_times_ready_56 || !_dataflow_times_valid_56) begin _dataflow_times_mul_odata_reg_56 <= _dataflow_times_mul_odata_56 >>> 8; end if(_dataflow_times_ready_56 || !_dataflow_times_valid_56) begin _dataflow_times_mul_valid_reg_56 <= _dataflow_times_mul_ovalid_56; end if(_dataflow_times_ready_57 || !_dataflow_times_valid_57) begin _dataflow_times_mul_odata_reg_57 <= _dataflow_times_mul_odata_57 >>> 8; end if(_dataflow_times_ready_57 || !_dataflow_times_valid_57) begin _dataflow_times_mul_valid_reg_57 <= _dataflow_times_mul_ovalid_57; end if(_dataflow_times_ready_64 || !_dataflow_times_valid_64) begin _dataflow_times_mul_odata_reg_64 <= _dataflow_times_mul_odata_64 >>> 8; end if(_dataflow_times_ready_64 || !_dataflow_times_valid_64) begin _dataflow_times_mul_valid_reg_64 <= _dataflow_times_mul_ovalid_64; end if(_dataflow_times_ready_65 || !_dataflow_times_valid_65) begin _dataflow_times_mul_odata_reg_65 <= _dataflow_times_mul_odata_65 >>> 8; end if(_dataflow_times_ready_65 || !_dataflow_times_valid_65) begin _dataflow_times_mul_valid_reg_65 <= _dataflow_times_mul_ovalid_65; end if(_dataflow_times_ready_66 || !_dataflow_times_valid_66) begin _dataflow_times_mul_odata_reg_66 <= _dataflow_times_mul_odata_66 >>> 8; end if(_dataflow_times_ready_66 || !_dataflow_times_valid_66) begin _dataflow_times_mul_valid_reg_66 <= _dataflow_times_mul_ovalid_66; end if(_dataflow_times_ready_67 || !_dataflow_times_valid_67) begin _dataflow_times_mul_odata_reg_67 <= _dataflow_times_mul_odata_67 >>> 8; end if(_dataflow_times_ready_67 || !_dataflow_times_valid_67) begin _dataflow_times_mul_valid_reg_67 <= _dataflow_times_mul_ovalid_67; end if(_dataflow_times_ready_74 || !_dataflow_times_valid_74) begin _dataflow_times_mul_odata_reg_74 <= _dataflow_times_mul_odata_74 >>> 8; end if(_dataflow_times_ready_74 || !_dataflow_times_valid_74) begin _dataflow_times_mul_valid_reg_74 <= _dataflow_times_mul_ovalid_74; end if(_dataflow_times_ready_75 || !_dataflow_times_valid_75) begin _dataflow_times_mul_odata_reg_75 <= _dataflow_times_mul_odata_75 >>> 8; end if(_dataflow_times_ready_75 || !_dataflow_times_valid_75) begin _dataflow_times_mul_valid_reg_75 <= _dataflow_times_mul_ovalid_75; end if(_dataflow_times_ready_76 || !_dataflow_times_valid_76) begin _dataflow_times_mul_odata_reg_76 <= _dataflow_times_mul_odata_76 >>> 8; end if(_dataflow_times_ready_76 || !_dataflow_times_valid_76) begin _dataflow_times_mul_valid_reg_76 <= _dataflow_times_mul_ovalid_76; end if(_dataflow_times_ready_77 || !_dataflow_times_valid_77) begin _dataflow_times_mul_odata_reg_77 <= _dataflow_times_mul_odata_77 >>> 8; end if(_dataflow_times_ready_77 || !_dataflow_times_valid_77) begin _dataflow_times_mul_valid_reg_77 <= _dataflow_times_mul_ovalid_77; end if((_dataflow_plus_ready_80 || !_dataflow_plus_valid_80) && (_dataflow_plus_ready_40 && _dataflow_plus_ready_60) && (_dataflow_plus_valid_40 && _dataflow_plus_valid_60)) begin _dataflow_plus_data_80 <= _dataflow_plus_data_40 + _dataflow_plus_data_60; end if(_dataflow_plus_valid_80 && _dataflow_plus_ready_80) begin _dataflow_plus_valid_80 <= 0; end if((_dataflow_plus_ready_80 || !_dataflow_plus_valid_80) && (_dataflow_plus_ready_40 && _dataflow_plus_ready_60)) begin _dataflow_plus_valid_80 <= _dataflow_plus_valid_40 && _dataflow_plus_valid_60; end if((_dataflow_plus_ready_81 || !_dataflow_plus_valid_81) && (_dataflow_plus_ready_41 && _dataflow_plus_ready_61) && (_dataflow_plus_valid_41 && _dataflow_plus_valid_61)) begin _dataflow_plus_data_81 <= _dataflow_plus_data_41 + _dataflow_plus_data_61; end if(_dataflow_plus_valid_81 && _dataflow_plus_ready_81) begin _dataflow_plus_valid_81 <= 0; end if((_dataflow_plus_ready_81 || !_dataflow_plus_valid_81) && (_dataflow_plus_ready_41 && _dataflow_plus_ready_61)) begin _dataflow_plus_valid_81 <= _dataflow_plus_valid_41 && _dataflow_plus_valid_61; end if((_dataflow_minus_ready_82 || !_dataflow_minus_valid_82) && (_dataflow_plus_ready_40 && _dataflow_plus_ready_60) && (_dataflow_plus_valid_40 && _dataflow_plus_valid_60)) begin _dataflow_minus_data_82 <= _dataflow_plus_data_40 - _dataflow_plus_data_60; end if(_dataflow_minus_valid_82 && _dataflow_minus_ready_82) begin _dataflow_minus_valid_82 <= 0; end if((_dataflow_minus_ready_82 || !_dataflow_minus_valid_82) && (_dataflow_plus_ready_40 && _dataflow_plus_ready_60)) begin _dataflow_minus_valid_82 <= _dataflow_plus_valid_40 && _dataflow_plus_valid_60; end if((_dataflow_minus_ready_83 || !_dataflow_minus_valid_83) && (_dataflow_plus_ready_41 && _dataflow_plus_ready_61) && (_dataflow_plus_valid_41 && _dataflow_plus_valid_61)) begin _dataflow_minus_data_83 <= _dataflow_plus_data_41 - _dataflow_plus_data_61; end if(_dataflow_minus_valid_83 && _dataflow_minus_ready_83) begin _dataflow_minus_valid_83 <= 0; end if((_dataflow_minus_ready_83 || !_dataflow_minus_valid_83) && (_dataflow_plus_ready_41 && _dataflow_plus_ready_61)) begin _dataflow_minus_valid_83 <= _dataflow_plus_valid_41 && _dataflow_plus_valid_61; end if((_dataflow_plus_ready_90 || !_dataflow_plus_valid_90) && (_dataflow_plus_ready_50 && _dataflow_plus_ready_70) && (_dataflow_plus_valid_50 && _dataflow_plus_valid_70)) begin _dataflow_plus_data_90 <= _dataflow_plus_data_50 + _dataflow_plus_data_70; end if(_dataflow_plus_valid_90 && _dataflow_plus_ready_90) begin _dataflow_plus_valid_90 <= 0; end if((_dataflow_plus_ready_90 || !_dataflow_plus_valid_90) && (_dataflow_plus_ready_50 && _dataflow_plus_ready_70)) begin _dataflow_plus_valid_90 <= _dataflow_plus_valid_50 && _dataflow_plus_valid_70; end if((_dataflow_plus_ready_91 || !_dataflow_plus_valid_91) && (_dataflow_plus_ready_51 && _dataflow_plus_ready_71) && (_dataflow_plus_valid_51 && _dataflow_plus_valid_71)) begin _dataflow_plus_data_91 <= _dataflow_plus_data_51 + _dataflow_plus_data_71; end if(_dataflow_plus_valid_91 && _dataflow_plus_ready_91) begin _dataflow_plus_valid_91 <= 0; end if((_dataflow_plus_ready_91 || !_dataflow_plus_valid_91) && (_dataflow_plus_ready_51 && _dataflow_plus_ready_71)) begin _dataflow_plus_valid_91 <= _dataflow_plus_valid_51 && _dataflow_plus_valid_71; end if((_dataflow_minus_ready_92 || !_dataflow_minus_valid_92) && (_dataflow_plus_ready_50 && _dataflow_plus_ready_70) && (_dataflow_plus_valid_50 && _dataflow_plus_valid_70)) begin _dataflow_minus_data_92 <= _dataflow_plus_data_50 - _dataflow_plus_data_70; end if(_dataflow_minus_valid_92 && _dataflow_minus_ready_92) begin _dataflow_minus_valid_92 <= 0; end if((_dataflow_minus_ready_92 || !_dataflow_minus_valid_92) && (_dataflow_plus_ready_50 && _dataflow_plus_ready_70)) begin _dataflow_minus_valid_92 <= _dataflow_plus_valid_50 && _dataflow_plus_valid_70; end if((_dataflow_minus_ready_93 || !_dataflow_minus_valid_93) && (_dataflow_plus_ready_51 && _dataflow_plus_ready_71) && (_dataflow_plus_valid_51 && _dataflow_plus_valid_71)) begin _dataflow_minus_data_93 <= _dataflow_plus_data_51 - _dataflow_plus_data_71; end if(_dataflow_minus_valid_93 && _dataflow_minus_ready_93) begin _dataflow_minus_valid_93 <= 0; end if((_dataflow_minus_ready_93 || !_dataflow_minus_valid_93) && (_dataflow_plus_ready_51 && _dataflow_plus_ready_71)) begin _dataflow_minus_valid_93 <= _dataflow_plus_valid_51 && _dataflow_plus_valid_71; end if((_dataflow__delay_ready_161 || !_dataflow__delay_valid_161) && _dataflow__delay_ready_160 && _dataflow__delay_valid_160) begin _dataflow__delay_data_161 <= _dataflow__delay_data_160; end if(_dataflow__delay_valid_161 && _dataflow__delay_ready_161) begin _dataflow__delay_valid_161 <= 0; end if((_dataflow__delay_ready_161 || !_dataflow__delay_valid_161) && _dataflow__delay_ready_160) begin _dataflow__delay_valid_161 <= _dataflow__delay_valid_160; end if((_dataflow__delay_ready_164 || !_dataflow__delay_valid_164) && _dataflow__delay_ready_163 && _dataflow__delay_valid_163) begin _dataflow__delay_data_164 <= _dataflow__delay_data_163; end if(_dataflow__delay_valid_164 && _dataflow__delay_ready_164) begin _dataflow__delay_valid_164 <= 0; end if((_dataflow__delay_ready_164 || !_dataflow__delay_valid_164) && _dataflow__delay_ready_163) begin _dataflow__delay_valid_164 <= _dataflow__delay_valid_163; end if((_dataflow__delay_ready_167 || !_dataflow__delay_valid_167) && _dataflow__delay_ready_166 && _dataflow__delay_valid_166) begin _dataflow__delay_data_167 <= _dataflow__delay_data_166; end if(_dataflow__delay_valid_167 && _dataflow__delay_ready_167) begin _dataflow__delay_valid_167 <= 0; end if((_dataflow__delay_ready_167 || !_dataflow__delay_valid_167) && _dataflow__delay_ready_166) begin _dataflow__delay_valid_167 <= _dataflow__delay_valid_166; end if((_dataflow__delay_ready_169 || !_dataflow__delay_valid_169) && _dataflow__delay_ready_168 && _dataflow__delay_valid_168) begin _dataflow__delay_data_169 <= _dataflow__delay_data_168; end if(_dataflow__delay_valid_169 && _dataflow__delay_ready_169) begin _dataflow__delay_valid_169 <= 0; end if((_dataflow__delay_ready_169 || !_dataflow__delay_valid_169) && _dataflow__delay_ready_168) begin _dataflow__delay_valid_169 <= _dataflow__delay_valid_168; end if((_dataflow__delay_ready_171 || !_dataflow__delay_valid_171) && _dataflow__delay_ready_170 && _dataflow__delay_valid_170) begin _dataflow__delay_data_171 <= _dataflow__delay_data_170; end if(_dataflow__delay_valid_171 && _dataflow__delay_ready_171) begin _dataflow__delay_valid_171 <= 0; end if((_dataflow__delay_ready_171 || !_dataflow__delay_valid_171) && _dataflow__delay_ready_170) begin _dataflow__delay_valid_171 <= _dataflow__delay_valid_170; end if((_dataflow__delay_ready_173 || !_dataflow__delay_valid_173) && _dataflow__delay_ready_172 && _dataflow__delay_valid_172) begin _dataflow__delay_data_173 <= _dataflow__delay_data_172; end if(_dataflow__delay_valid_173 && _dataflow__delay_ready_173) begin _dataflow__delay_valid_173 <= 0; end if((_dataflow__delay_ready_173 || !_dataflow__delay_valid_173) && _dataflow__delay_ready_172) begin _dataflow__delay_valid_173 <= _dataflow__delay_valid_172; end if((_dataflow__delay_ready_175 || !_dataflow__delay_valid_175) && _dataflow__delay_ready_174 && _dataflow__delay_valid_174) begin _dataflow__delay_data_175 <= _dataflow__delay_data_174; end if(_dataflow__delay_valid_175 && _dataflow__delay_ready_175) begin _dataflow__delay_valid_175 <= 0; end if((_dataflow__delay_ready_175 || !_dataflow__delay_valid_175) && _dataflow__delay_ready_174) begin _dataflow__delay_valid_175 <= _dataflow__delay_valid_174; end if((_dataflow__delay_ready_186 || !_dataflow__delay_valid_186) && _dataflow__delay_ready_185 && _dataflow__delay_valid_185) begin _dataflow__delay_data_186 <= _dataflow__delay_data_185; end if(_dataflow__delay_valid_186 && _dataflow__delay_ready_186) begin _dataflow__delay_valid_186 <= 0; end if((_dataflow__delay_ready_186 || !_dataflow__delay_valid_186) && _dataflow__delay_ready_185) begin _dataflow__delay_valid_186 <= _dataflow__delay_valid_185; end if((_dataflow__delay_ready_205 || !_dataflow__delay_valid_205) && _dataflow__delay_ready_204 && _dataflow__delay_valid_204) begin _dataflow__delay_data_205 <= _dataflow__delay_data_204; end if(_dataflow__delay_valid_205 && _dataflow__delay_ready_205) begin _dataflow__delay_valid_205 <= 0; end if((_dataflow__delay_ready_205 || !_dataflow__delay_valid_205) && _dataflow__delay_ready_204) begin _dataflow__delay_valid_205 <= _dataflow__delay_valid_204; end if((_dataflow__delay_ready_216 || !_dataflow__delay_valid_216) && _dataflow__delay_ready_215 && _dataflow__delay_valid_215) begin _dataflow__delay_data_216 <= _dataflow__delay_data_215; end if(_dataflow__delay_valid_216 && _dataflow__delay_ready_216) begin _dataflow__delay_valid_216 <= 0; end if((_dataflow__delay_ready_216 || !_dataflow__delay_valid_216) && _dataflow__delay_ready_215) begin _dataflow__delay_valid_216 <= _dataflow__delay_valid_215; end if((_dataflow__delay_ready_227 || !_dataflow__delay_valid_227) && _dataflow__delay_ready_226 && _dataflow__delay_valid_226) begin _dataflow__delay_data_227 <= _dataflow__delay_data_226; end if(_dataflow__delay_valid_227 && _dataflow__delay_ready_227) begin _dataflow__delay_valid_227 <= 0; end if((_dataflow__delay_ready_227 || !_dataflow__delay_valid_227) && _dataflow__delay_ready_226) begin _dataflow__delay_valid_227 <= _dataflow__delay_valid_226; end if((_dataflow__delay_ready_237 || !_dataflow__delay_valid_237) && _dataflow__delay_ready_236 && _dataflow__delay_valid_236) begin _dataflow__delay_data_237 <= _dataflow__delay_data_236; end if(_dataflow__delay_valid_237 && _dataflow__delay_ready_237) begin _dataflow__delay_valid_237 <= 0; end if((_dataflow__delay_ready_237 || !_dataflow__delay_valid_237) && _dataflow__delay_ready_236) begin _dataflow__delay_valid_237 <= _dataflow__delay_valid_236; end if((_dataflow__delay_ready_247 || !_dataflow__delay_valid_247) && _dataflow__delay_ready_246 && _dataflow__delay_valid_246) begin _dataflow__delay_data_247 <= _dataflow__delay_data_246; end if(_dataflow__delay_valid_247 && _dataflow__delay_ready_247) begin _dataflow__delay_valid_247 <= 0; end if((_dataflow__delay_ready_247 || !_dataflow__delay_valid_247) && _dataflow__delay_ready_246) begin _dataflow__delay_valid_247 <= _dataflow__delay_valid_246; end if((_dataflow__delay_ready_257 || !_dataflow__delay_valid_257) && _dataflow__delay_ready_256 && _dataflow__delay_valid_256) begin _dataflow__delay_data_257 <= _dataflow__delay_data_256; end if(_dataflow__delay_valid_257 && _dataflow__delay_ready_257) begin _dataflow__delay_valid_257 <= 0; end if((_dataflow__delay_ready_257 || !_dataflow__delay_valid_257) && _dataflow__delay_ready_256) begin _dataflow__delay_valid_257 <= _dataflow__delay_valid_256; end if((_dataflow__delay_ready_267 || !_dataflow__delay_valid_267) && _dataflow__delay_ready_266 && _dataflow__delay_valid_266) begin _dataflow__delay_data_267 <= _dataflow__delay_data_266; end if(_dataflow__delay_valid_267 && _dataflow__delay_ready_267) begin _dataflow__delay_valid_267 <= 0; end if((_dataflow__delay_ready_267 || !_dataflow__delay_valid_267) && _dataflow__delay_ready_266) begin _dataflow__delay_valid_267 <= _dataflow__delay_valid_266; end if((_dataflow__delay_ready_286 || !_dataflow__delay_valid_286) && _dataflow__delay_ready_285 && _dataflow__delay_valid_285) begin _dataflow__delay_data_286 <= _dataflow__delay_data_285; end if(_dataflow__delay_valid_286 && _dataflow__delay_ready_286) begin _dataflow__delay_valid_286 <= 0; end if((_dataflow__delay_ready_286 || !_dataflow__delay_valid_286) && _dataflow__delay_ready_285) begin _dataflow__delay_valid_286 <= _dataflow__delay_valid_285; end if(_dataflow_times_ready_84 || !_dataflow_times_valid_84) begin _dataflow_times_mul_odata_reg_84 <= _dataflow_times_mul_odata_84 >>> 8; end if(_dataflow_times_ready_84 || !_dataflow_times_valid_84) begin _dataflow_times_mul_valid_reg_84 <= _dataflow_times_mul_ovalid_84; end if(_dataflow_times_ready_85 || !_dataflow_times_valid_85) begin _dataflow_times_mul_odata_reg_85 <= _dataflow_times_mul_odata_85 >>> 8; end if(_dataflow_times_ready_85 || !_dataflow_times_valid_85) begin _dataflow_times_mul_valid_reg_85 <= _dataflow_times_mul_ovalid_85; end if(_dataflow_times_ready_86 || !_dataflow_times_valid_86) begin _dataflow_times_mul_odata_reg_86 <= _dataflow_times_mul_odata_86 >>> 8; end if(_dataflow_times_ready_86 || !_dataflow_times_valid_86) begin _dataflow_times_mul_valid_reg_86 <= _dataflow_times_mul_ovalid_86; end if(_dataflow_times_ready_87 || !_dataflow_times_valid_87) begin _dataflow_times_mul_odata_reg_87 <= _dataflow_times_mul_odata_87 >>> 8; end if(_dataflow_times_ready_87 || !_dataflow_times_valid_87) begin _dataflow_times_mul_valid_reg_87 <= _dataflow_times_mul_ovalid_87; end if(_dataflow_times_ready_94 || !_dataflow_times_valid_94) begin _dataflow_times_mul_odata_reg_94 <= _dataflow_times_mul_odata_94 >>> 8; end if(_dataflow_times_ready_94 || !_dataflow_times_valid_94) begin _dataflow_times_mul_valid_reg_94 <= _dataflow_times_mul_ovalid_94; end if(_dataflow_times_ready_95 || !_dataflow_times_valid_95) begin _dataflow_times_mul_odata_reg_95 <= _dataflow_times_mul_odata_95 >>> 8; end if(_dataflow_times_ready_95 || !_dataflow_times_valid_95) begin _dataflow_times_mul_valid_reg_95 <= _dataflow_times_mul_ovalid_95; end if(_dataflow_times_ready_96 || !_dataflow_times_valid_96) begin _dataflow_times_mul_odata_reg_96 <= _dataflow_times_mul_odata_96 >>> 8; end if(_dataflow_times_ready_96 || !_dataflow_times_valid_96) begin _dataflow_times_mul_valid_reg_96 <= _dataflow_times_mul_ovalid_96; end if(_dataflow_times_ready_97 || !_dataflow_times_valid_97) begin _dataflow_times_mul_odata_reg_97 <= _dataflow_times_mul_odata_97 >>> 8; end if(_dataflow_times_ready_97 || !_dataflow_times_valid_97) begin _dataflow_times_mul_valid_reg_97 <= _dataflow_times_mul_ovalid_97; end if((_dataflow_plus_ready_120 || !_dataflow_plus_valid_120) && (_dataflow_plus_ready_80 && _dataflow_plus_ready_90) && (_dataflow_plus_valid_80 && _dataflow_plus_valid_90)) begin _dataflow_plus_data_120 <= _dataflow_plus_data_80 + _dataflow_plus_data_90; end if(_dataflow_plus_valid_120 && _dataflow_plus_ready_120) begin _dataflow_plus_valid_120 <= 0; end if((_dataflow_plus_ready_120 || !_dataflow_plus_valid_120) && (_dataflow_plus_ready_80 && _dataflow_plus_ready_90)) begin _dataflow_plus_valid_120 <= _dataflow_plus_valid_80 && _dataflow_plus_valid_90; end if((_dataflow_plus_ready_121 || !_dataflow_plus_valid_121) && (_dataflow_plus_ready_81 && _dataflow_plus_ready_91) && (_dataflow_plus_valid_81 && _dataflow_plus_valid_91)) begin _dataflow_plus_data_121 <= _dataflow_plus_data_81 + _dataflow_plus_data_91; end if(_dataflow_plus_valid_121 && _dataflow_plus_ready_121) begin _dataflow_plus_valid_121 <= 0; end if((_dataflow_plus_ready_121 || !_dataflow_plus_valid_121) && (_dataflow_plus_ready_81 && _dataflow_plus_ready_91)) begin _dataflow_plus_valid_121 <= _dataflow_plus_valid_81 && _dataflow_plus_valid_91; end if((_dataflow_minus_ready_122 || !_dataflow_minus_valid_122) && (_dataflow_plus_ready_80 && _dataflow_plus_ready_90) && (_dataflow_plus_valid_80 && _dataflow_plus_valid_90)) begin _dataflow_minus_data_122 <= _dataflow_plus_data_80 - _dataflow_plus_data_90; end if(_dataflow_minus_valid_122 && _dataflow_minus_ready_122) begin _dataflow_minus_valid_122 <= 0; end if((_dataflow_minus_ready_122 || !_dataflow_minus_valid_122) && (_dataflow_plus_ready_80 && _dataflow_plus_ready_90)) begin _dataflow_minus_valid_122 <= _dataflow_plus_valid_80 && _dataflow_plus_valid_90; end if((_dataflow_minus_ready_123 || !_dataflow_minus_valid_123) && (_dataflow_plus_ready_81 && _dataflow_plus_ready_91) && (_dataflow_plus_valid_81 && _dataflow_plus_valid_91)) begin _dataflow_minus_data_123 <= _dataflow_plus_data_81 - _dataflow_plus_data_91; end if(_dataflow_minus_valid_123 && _dataflow_minus_ready_123) begin _dataflow_minus_valid_123 <= 0; end if((_dataflow_minus_ready_123 || !_dataflow_minus_valid_123) && (_dataflow_plus_ready_81 && _dataflow_plus_ready_91)) begin _dataflow_minus_valid_123 <= _dataflow_plus_valid_81 && _dataflow_plus_valid_91; end if((_dataflow__delay_ready_162 || !_dataflow__delay_valid_162) && _dataflow__delay_ready_161 && _dataflow__delay_valid_161) begin _dataflow__delay_data_162 <= _dataflow__delay_data_161; end if(_dataflow__delay_valid_162 && _dataflow__delay_ready_162) begin _dataflow__delay_valid_162 <= 0; end if((_dataflow__delay_ready_162 || !_dataflow__delay_valid_162) && _dataflow__delay_ready_161) begin _dataflow__delay_valid_162 <= _dataflow__delay_valid_161; end if((_dataflow__delay_ready_165 || !_dataflow__delay_valid_165) && _dataflow__delay_ready_164 && _dataflow__delay_valid_164) begin _dataflow__delay_data_165 <= _dataflow__delay_data_164; end if(_dataflow__delay_valid_165 && _dataflow__delay_ready_165) begin _dataflow__delay_valid_165 <= 0; end if((_dataflow__delay_ready_165 || !_dataflow__delay_valid_165) && _dataflow__delay_ready_164) begin _dataflow__delay_valid_165 <= _dataflow__delay_valid_164; end if((_dataflow__delay_ready_176 || !_dataflow__delay_valid_176) && _dataflow__delay_ready_175 && _dataflow__delay_valid_175) begin _dataflow__delay_data_176 <= _dataflow__delay_data_175; end if(_dataflow__delay_valid_176 && _dataflow__delay_ready_176) begin _dataflow__delay_valid_176 <= 0; end if((_dataflow__delay_ready_176 || !_dataflow__delay_valid_176) && _dataflow__delay_ready_175) begin _dataflow__delay_valid_176 <= _dataflow__delay_valid_175; end if((_dataflow__delay_ready_187 || !_dataflow__delay_valid_187) && _dataflow__delay_ready_186 && _dataflow__delay_valid_186) begin _dataflow__delay_data_187 <= _dataflow__delay_data_186; end if(_dataflow__delay_valid_187 && _dataflow__delay_ready_187) begin _dataflow__delay_valid_187 <= 0; end if((_dataflow__delay_ready_187 || !_dataflow__delay_valid_187) && _dataflow__delay_ready_186) begin _dataflow__delay_valid_187 <= _dataflow__delay_valid_186; end if((_dataflow__delay_ready_206 || !_dataflow__delay_valid_206) && _dataflow__delay_ready_205 && _dataflow__delay_valid_205) begin _dataflow__delay_data_206 <= _dataflow__delay_data_205; end if(_dataflow__delay_valid_206 && _dataflow__delay_ready_206) begin _dataflow__delay_valid_206 <= 0; end if((_dataflow__delay_ready_206 || !_dataflow__delay_valid_206) && _dataflow__delay_ready_205) begin _dataflow__delay_valid_206 <= _dataflow__delay_valid_205; end if((_dataflow__delay_ready_217 || !_dataflow__delay_valid_217) && _dataflow__delay_ready_216 && _dataflow__delay_valid_216) begin _dataflow__delay_data_217 <= _dataflow__delay_data_216; end if(_dataflow__delay_valid_217 && _dataflow__delay_ready_217) begin _dataflow__delay_valid_217 <= 0; end if((_dataflow__delay_ready_217 || !_dataflow__delay_valid_217) && _dataflow__delay_ready_216) begin _dataflow__delay_valid_217 <= _dataflow__delay_valid_216; end if((_dataflow__delay_ready_228 || !_dataflow__delay_valid_228) && _dataflow__delay_ready_227 && _dataflow__delay_valid_227) begin _dataflow__delay_data_228 <= _dataflow__delay_data_227; end if(_dataflow__delay_valid_228 && _dataflow__delay_ready_228) begin _dataflow__delay_valid_228 <= 0; end if((_dataflow__delay_ready_228 || !_dataflow__delay_valid_228) && _dataflow__delay_ready_227) begin _dataflow__delay_valid_228 <= _dataflow__delay_valid_227; end if((_dataflow__delay_ready_238 || !_dataflow__delay_valid_238) && _dataflow__delay_ready_237 && _dataflow__delay_valid_237) begin _dataflow__delay_data_238 <= _dataflow__delay_data_237; end if(_dataflow__delay_valid_238 && _dataflow__delay_ready_238) begin _dataflow__delay_valid_238 <= 0; end if((_dataflow__delay_ready_238 || !_dataflow__delay_valid_238) && _dataflow__delay_ready_237) begin _dataflow__delay_valid_238 <= _dataflow__delay_valid_237; end if((_dataflow__delay_ready_248 || !_dataflow__delay_valid_248) && _dataflow__delay_ready_247 && _dataflow__delay_valid_247) begin _dataflow__delay_data_248 <= _dataflow__delay_data_247; end if(_dataflow__delay_valid_248 && _dataflow__delay_ready_248) begin _dataflow__delay_valid_248 <= 0; end if((_dataflow__delay_ready_248 || !_dataflow__delay_valid_248) && _dataflow__delay_ready_247) begin _dataflow__delay_valid_248 <= _dataflow__delay_valid_247; end if((_dataflow__delay_ready_258 || !_dataflow__delay_valid_258) && _dataflow__delay_ready_257 && _dataflow__delay_valid_257) begin _dataflow__delay_data_258 <= _dataflow__delay_data_257; end if(_dataflow__delay_valid_258 && _dataflow__delay_ready_258) begin _dataflow__delay_valid_258 <= 0; end if((_dataflow__delay_ready_258 || !_dataflow__delay_valid_258) && _dataflow__delay_ready_257) begin _dataflow__delay_valid_258 <= _dataflow__delay_valid_257; end if((_dataflow__delay_ready_268 || !_dataflow__delay_valid_268) && _dataflow__delay_ready_267 && _dataflow__delay_valid_267) begin _dataflow__delay_data_268 <= _dataflow__delay_data_267; end if(_dataflow__delay_valid_268 && _dataflow__delay_ready_268) begin _dataflow__delay_valid_268 <= 0; end if((_dataflow__delay_ready_268 || !_dataflow__delay_valid_268) && _dataflow__delay_ready_267) begin _dataflow__delay_valid_268 <= _dataflow__delay_valid_267; end if((_dataflow__delay_ready_287 || !_dataflow__delay_valid_287) && _dataflow__delay_ready_286 && _dataflow__delay_valid_286) begin _dataflow__delay_data_287 <= _dataflow__delay_data_286; end if(_dataflow__delay_valid_287 && _dataflow__delay_ready_287) begin _dataflow__delay_valid_287 <= 0; end if((_dataflow__delay_ready_287 || !_dataflow__delay_valid_287) && _dataflow__delay_ready_286) begin _dataflow__delay_valid_287 <= _dataflow__delay_valid_286; end if(_dataflow_times_ready_124 || !_dataflow_times_valid_124) begin _dataflow_times_mul_odata_reg_124 <= _dataflow_times_mul_odata_124 >>> 8; end if(_dataflow_times_ready_124 || !_dataflow_times_valid_124) begin _dataflow_times_mul_valid_reg_124 <= _dataflow_times_mul_ovalid_124; end if(_dataflow_times_ready_125 || !_dataflow_times_valid_125) begin _dataflow_times_mul_odata_reg_125 <= _dataflow_times_mul_odata_125 >>> 8; end if(_dataflow_times_ready_125 || !_dataflow_times_valid_125) begin _dataflow_times_mul_valid_reg_125 <= _dataflow_times_mul_ovalid_125; end if(_dataflow_times_ready_126 || !_dataflow_times_valid_126) begin _dataflow_times_mul_odata_reg_126 <= _dataflow_times_mul_odata_126 >>> 8; end if(_dataflow_times_ready_126 || !_dataflow_times_valid_126) begin _dataflow_times_mul_valid_reg_126 <= _dataflow_times_mul_ovalid_126; end if(_dataflow_times_ready_127 || !_dataflow_times_valid_127) begin _dataflow_times_mul_odata_reg_127 <= _dataflow_times_mul_odata_127 >>> 8; end if(_dataflow_times_ready_127 || !_dataflow_times_valid_127) begin _dataflow_times_mul_valid_reg_127 <= _dataflow_times_mul_ovalid_127; end if((_dataflow__delay_ready_177 || !_dataflow__delay_valid_177) && _dataflow__delay_ready_176 && _dataflow__delay_valid_176) begin _dataflow__delay_data_177 <= _dataflow__delay_data_176; end if(_dataflow__delay_valid_177 && _dataflow__delay_ready_177) begin _dataflow__delay_valid_177 <= 0; end if((_dataflow__delay_ready_177 || !_dataflow__delay_valid_177) && _dataflow__delay_ready_176) begin _dataflow__delay_valid_177 <= _dataflow__delay_valid_176; end if((_dataflow__delay_ready_188 || !_dataflow__delay_valid_188) && _dataflow__delay_ready_187 && _dataflow__delay_valid_187) begin _dataflow__delay_data_188 <= _dataflow__delay_data_187; end if(_dataflow__delay_valid_188 && _dataflow__delay_ready_188) begin _dataflow__delay_valid_188 <= 0; end if((_dataflow__delay_ready_188 || !_dataflow__delay_valid_188) && _dataflow__delay_ready_187) begin _dataflow__delay_valid_188 <= _dataflow__delay_valid_187; end if((_dataflow__delay_ready_207 || !_dataflow__delay_valid_207) && _dataflow__delay_ready_206 && _dataflow__delay_valid_206) begin _dataflow__delay_data_207 <= _dataflow__delay_data_206; end if(_dataflow__delay_valid_207 && _dataflow__delay_ready_207) begin _dataflow__delay_valid_207 <= 0; end if((_dataflow__delay_ready_207 || !_dataflow__delay_valid_207) && _dataflow__delay_ready_206) begin _dataflow__delay_valid_207 <= _dataflow__delay_valid_206; end if((_dataflow__delay_ready_218 || !_dataflow__delay_valid_218) && _dataflow__delay_ready_217 && _dataflow__delay_valid_217) begin _dataflow__delay_data_218 <= _dataflow__delay_data_217; end if(_dataflow__delay_valid_218 && _dataflow__delay_ready_218) begin _dataflow__delay_valid_218 <= 0; end if((_dataflow__delay_ready_218 || !_dataflow__delay_valid_218) && _dataflow__delay_ready_217) begin _dataflow__delay_valid_218 <= _dataflow__delay_valid_217; end if((_dataflow__delay_ready_229 || !_dataflow__delay_valid_229) && _dataflow__delay_ready_228 && _dataflow__delay_valid_228) begin _dataflow__delay_data_229 <= _dataflow__delay_data_228; end if(_dataflow__delay_valid_229 && _dataflow__delay_ready_229) begin _dataflow__delay_valid_229 <= 0; end if((_dataflow__delay_ready_229 || !_dataflow__delay_valid_229) && _dataflow__delay_ready_228) begin _dataflow__delay_valid_229 <= _dataflow__delay_valid_228; end if((_dataflow__delay_ready_239 || !_dataflow__delay_valid_239) && _dataflow__delay_ready_238 && _dataflow__delay_valid_238) begin _dataflow__delay_data_239 <= _dataflow__delay_data_238; end if(_dataflow__delay_valid_239 && _dataflow__delay_ready_239) begin _dataflow__delay_valid_239 <= 0; end if((_dataflow__delay_ready_239 || !_dataflow__delay_valid_239) && _dataflow__delay_ready_238) begin _dataflow__delay_valid_239 <= _dataflow__delay_valid_238; end if((_dataflow__delay_ready_249 || !_dataflow__delay_valid_249) && _dataflow__delay_ready_248 && _dataflow__delay_valid_248) begin _dataflow__delay_data_249 <= _dataflow__delay_data_248; end if(_dataflow__delay_valid_249 && _dataflow__delay_ready_249) begin _dataflow__delay_valid_249 <= 0; end if((_dataflow__delay_ready_249 || !_dataflow__delay_valid_249) && _dataflow__delay_ready_248) begin _dataflow__delay_valid_249 <= _dataflow__delay_valid_248; end if((_dataflow__delay_ready_259 || !_dataflow__delay_valid_259) && _dataflow__delay_ready_258 && _dataflow__delay_valid_258) begin _dataflow__delay_data_259 <= _dataflow__delay_data_258; end if(_dataflow__delay_valid_259 && _dataflow__delay_ready_259) begin _dataflow__delay_valid_259 <= 0; end if((_dataflow__delay_ready_259 || !_dataflow__delay_valid_259) && _dataflow__delay_ready_258) begin _dataflow__delay_valid_259 <= _dataflow__delay_valid_258; end if((_dataflow__delay_ready_269 || !_dataflow__delay_valid_269) && _dataflow__delay_ready_268 && _dataflow__delay_valid_268) begin _dataflow__delay_data_269 <= _dataflow__delay_data_268; end if(_dataflow__delay_valid_269 && _dataflow__delay_ready_269) begin _dataflow__delay_valid_269 <= 0; end if((_dataflow__delay_ready_269 || !_dataflow__delay_valid_269) && _dataflow__delay_ready_268) begin _dataflow__delay_valid_269 <= _dataflow__delay_valid_268; end if((_dataflow__delay_ready_288 || !_dataflow__delay_valid_288) && _dataflow__delay_ready_287 && _dataflow__delay_valid_287) begin _dataflow__delay_data_288 <= _dataflow__delay_data_287; end if(_dataflow__delay_valid_288 && _dataflow__delay_ready_288) begin _dataflow__delay_valid_288 <= 0; end if((_dataflow__delay_ready_288 || !_dataflow__delay_valid_288) && _dataflow__delay_ready_287) begin _dataflow__delay_valid_288 <= _dataflow__delay_valid_287; end if((_dataflow__delay_ready_304 || !_dataflow__delay_valid_304) && _dataflow_plus_ready_120 && _dataflow_plus_valid_120) begin _dataflow__delay_data_304 <= _dataflow_plus_data_120; end if(_dataflow__delay_valid_304 && _dataflow__delay_ready_304) begin _dataflow__delay_valid_304 <= 0; end if((_dataflow__delay_ready_304 || !_dataflow__delay_valid_304) && _dataflow_plus_ready_120) begin _dataflow__delay_valid_304 <= _dataflow_plus_valid_120; end if((_dataflow__delay_ready_328 || !_dataflow__delay_valid_328) && _dataflow_plus_ready_121 && _dataflow_plus_valid_121) begin _dataflow__delay_data_328 <= _dataflow_plus_data_121; end if(_dataflow__delay_valid_328 && _dataflow__delay_ready_328) begin _dataflow__delay_valid_328 <= 0; end if((_dataflow__delay_ready_328 || !_dataflow__delay_valid_328) && _dataflow_plus_ready_121) begin _dataflow__delay_valid_328 <= _dataflow_plus_valid_121; end if((_dataflow__delay_ready_178 || !_dataflow__delay_valid_178) && _dataflow__delay_ready_177 && _dataflow__delay_valid_177) begin _dataflow__delay_data_178 <= _dataflow__delay_data_177; end if(_dataflow__delay_valid_178 && _dataflow__delay_ready_178) begin _dataflow__delay_valid_178 <= 0; end if((_dataflow__delay_ready_178 || !_dataflow__delay_valid_178) && _dataflow__delay_ready_177) begin _dataflow__delay_valid_178 <= _dataflow__delay_valid_177; end if((_dataflow__delay_ready_189 || !_dataflow__delay_valid_189) && _dataflow__delay_ready_188 && _dataflow__delay_valid_188) begin _dataflow__delay_data_189 <= _dataflow__delay_data_188; end if(_dataflow__delay_valid_189 && _dataflow__delay_ready_189) begin _dataflow__delay_valid_189 <= 0; end if((_dataflow__delay_ready_189 || !_dataflow__delay_valid_189) && _dataflow__delay_ready_188) begin _dataflow__delay_valid_189 <= _dataflow__delay_valid_188; end if((_dataflow__delay_ready_208 || !_dataflow__delay_valid_208) && _dataflow__delay_ready_207 && _dataflow__delay_valid_207) begin _dataflow__delay_data_208 <= _dataflow__delay_data_207; end if(_dataflow__delay_valid_208 && _dataflow__delay_ready_208) begin _dataflow__delay_valid_208 <= 0; end if((_dataflow__delay_ready_208 || !_dataflow__delay_valid_208) && _dataflow__delay_ready_207) begin _dataflow__delay_valid_208 <= _dataflow__delay_valid_207; end if((_dataflow__delay_ready_219 || !_dataflow__delay_valid_219) && _dataflow__delay_ready_218 && _dataflow__delay_valid_218) begin _dataflow__delay_data_219 <= _dataflow__delay_data_218; end if(_dataflow__delay_valid_219 && _dataflow__delay_ready_219) begin _dataflow__delay_valid_219 <= 0; end if((_dataflow__delay_ready_219 || !_dataflow__delay_valid_219) && _dataflow__delay_ready_218) begin _dataflow__delay_valid_219 <= _dataflow__delay_valid_218; end if((_dataflow__delay_ready_230 || !_dataflow__delay_valid_230) && _dataflow__delay_ready_229 && _dataflow__delay_valid_229) begin _dataflow__delay_data_230 <= _dataflow__delay_data_229; end if(_dataflow__delay_valid_230 && _dataflow__delay_ready_230) begin _dataflow__delay_valid_230 <= 0; end if((_dataflow__delay_ready_230 || !_dataflow__delay_valid_230) && _dataflow__delay_ready_229) begin _dataflow__delay_valid_230 <= _dataflow__delay_valid_229; end if((_dataflow__delay_ready_240 || !_dataflow__delay_valid_240) && _dataflow__delay_ready_239 && _dataflow__delay_valid_239) begin _dataflow__delay_data_240 <= _dataflow__delay_data_239; end if(_dataflow__delay_valid_240 && _dataflow__delay_ready_240) begin _dataflow__delay_valid_240 <= 0; end if((_dataflow__delay_ready_240 || !_dataflow__delay_valid_240) && _dataflow__delay_ready_239) begin _dataflow__delay_valid_240 <= _dataflow__delay_valid_239; end if((_dataflow__delay_ready_250 || !_dataflow__delay_valid_250) && _dataflow__delay_ready_249 && _dataflow__delay_valid_249) begin _dataflow__delay_data_250 <= _dataflow__delay_data_249; end if(_dataflow__delay_valid_250 && _dataflow__delay_ready_250) begin _dataflow__delay_valid_250 <= 0; end if((_dataflow__delay_ready_250 || !_dataflow__delay_valid_250) && _dataflow__delay_ready_249) begin _dataflow__delay_valid_250 <= _dataflow__delay_valid_249; end if((_dataflow__delay_ready_260 || !_dataflow__delay_valid_260) && _dataflow__delay_ready_259 && _dataflow__delay_valid_259) begin _dataflow__delay_data_260 <= _dataflow__delay_data_259; end if(_dataflow__delay_valid_260 && _dataflow__delay_ready_260) begin _dataflow__delay_valid_260 <= 0; end if((_dataflow__delay_ready_260 || !_dataflow__delay_valid_260) && _dataflow__delay_ready_259) begin _dataflow__delay_valid_260 <= _dataflow__delay_valid_259; end if((_dataflow__delay_ready_270 || !_dataflow__delay_valid_270) && _dataflow__delay_ready_269 && _dataflow__delay_valid_269) begin _dataflow__delay_data_270 <= _dataflow__delay_data_269; end if(_dataflow__delay_valid_270 && _dataflow__delay_ready_270) begin _dataflow__delay_valid_270 <= 0; end if((_dataflow__delay_ready_270 || !_dataflow__delay_valid_270) && _dataflow__delay_ready_269) begin _dataflow__delay_valid_270 <= _dataflow__delay_valid_269; end if((_dataflow__delay_ready_289 || !_dataflow__delay_valid_289) && _dataflow__delay_ready_288 && _dataflow__delay_valid_288) begin _dataflow__delay_data_289 <= _dataflow__delay_data_288; end if(_dataflow__delay_valid_289 && _dataflow__delay_ready_289) begin _dataflow__delay_valid_289 <= 0; end if((_dataflow__delay_ready_289 || !_dataflow__delay_valid_289) && _dataflow__delay_ready_288) begin _dataflow__delay_valid_289 <= _dataflow__delay_valid_288; end if((_dataflow__delay_ready_305 || !_dataflow__delay_valid_305) && _dataflow__delay_ready_304 && _dataflow__delay_valid_304) begin _dataflow__delay_data_305 <= _dataflow__delay_data_304; end if(_dataflow__delay_valid_305 && _dataflow__delay_ready_305) begin _dataflow__delay_valid_305 <= 0; end if((_dataflow__delay_ready_305 || !_dataflow__delay_valid_305) && _dataflow__delay_ready_304) begin _dataflow__delay_valid_305 <= _dataflow__delay_valid_304; end if((_dataflow__delay_ready_329 || !_dataflow__delay_valid_329) && _dataflow__delay_ready_328 && _dataflow__delay_valid_328) begin _dataflow__delay_data_329 <= _dataflow__delay_data_328; end if(_dataflow__delay_valid_329 && _dataflow__delay_ready_329) begin _dataflow__delay_valid_329 <= 0; end if((_dataflow__delay_ready_329 || !_dataflow__delay_valid_329) && _dataflow__delay_ready_328) begin _dataflow__delay_valid_329 <= _dataflow__delay_valid_328; end if((_dataflow__delay_ready_179 || !_dataflow__delay_valid_179) && _dataflow__delay_ready_178 && _dataflow__delay_valid_178) begin _dataflow__delay_data_179 <= _dataflow__delay_data_178; end if(_dataflow__delay_valid_179 && _dataflow__delay_ready_179) begin _dataflow__delay_valid_179 <= 0; end if((_dataflow__delay_ready_179 || !_dataflow__delay_valid_179) && _dataflow__delay_ready_178) begin _dataflow__delay_valid_179 <= _dataflow__delay_valid_178; end if((_dataflow__delay_ready_190 || !_dataflow__delay_valid_190) && _dataflow__delay_ready_189 && _dataflow__delay_valid_189) begin _dataflow__delay_data_190 <= _dataflow__delay_data_189; end if(_dataflow__delay_valid_190 && _dataflow__delay_ready_190) begin _dataflow__delay_valid_190 <= 0; end if((_dataflow__delay_ready_190 || !_dataflow__delay_valid_190) && _dataflow__delay_ready_189) begin _dataflow__delay_valid_190 <= _dataflow__delay_valid_189; end if((_dataflow__delay_ready_209 || !_dataflow__delay_valid_209) && _dataflow__delay_ready_208 && _dataflow__delay_valid_208) begin _dataflow__delay_data_209 <= _dataflow__delay_data_208; end if(_dataflow__delay_valid_209 && _dataflow__delay_ready_209) begin _dataflow__delay_valid_209 <= 0; end if((_dataflow__delay_ready_209 || !_dataflow__delay_valid_209) && _dataflow__delay_ready_208) begin _dataflow__delay_valid_209 <= _dataflow__delay_valid_208; end if((_dataflow__delay_ready_220 || !_dataflow__delay_valid_220) && _dataflow__delay_ready_219 && _dataflow__delay_valid_219) begin _dataflow__delay_data_220 <= _dataflow__delay_data_219; end if(_dataflow__delay_valid_220 && _dataflow__delay_ready_220) begin _dataflow__delay_valid_220 <= 0; end if((_dataflow__delay_ready_220 || !_dataflow__delay_valid_220) && _dataflow__delay_ready_219) begin _dataflow__delay_valid_220 <= _dataflow__delay_valid_219; end if((_dataflow__delay_ready_231 || !_dataflow__delay_valid_231) && _dataflow__delay_ready_230 && _dataflow__delay_valid_230) begin _dataflow__delay_data_231 <= _dataflow__delay_data_230; end if(_dataflow__delay_valid_231 && _dataflow__delay_ready_231) begin _dataflow__delay_valid_231 <= 0; end if((_dataflow__delay_ready_231 || !_dataflow__delay_valid_231) && _dataflow__delay_ready_230) begin _dataflow__delay_valid_231 <= _dataflow__delay_valid_230; end if((_dataflow__delay_ready_241 || !_dataflow__delay_valid_241) && _dataflow__delay_ready_240 && _dataflow__delay_valid_240) begin _dataflow__delay_data_241 <= _dataflow__delay_data_240; end if(_dataflow__delay_valid_241 && _dataflow__delay_ready_241) begin _dataflow__delay_valid_241 <= 0; end if((_dataflow__delay_ready_241 || !_dataflow__delay_valid_241) && _dataflow__delay_ready_240) begin _dataflow__delay_valid_241 <= _dataflow__delay_valid_240; end if((_dataflow__delay_ready_251 || !_dataflow__delay_valid_251) && _dataflow__delay_ready_250 && _dataflow__delay_valid_250) begin _dataflow__delay_data_251 <= _dataflow__delay_data_250; end if(_dataflow__delay_valid_251 && _dataflow__delay_ready_251) begin _dataflow__delay_valid_251 <= 0; end if((_dataflow__delay_ready_251 || !_dataflow__delay_valid_251) && _dataflow__delay_ready_250) begin _dataflow__delay_valid_251 <= _dataflow__delay_valid_250; end if((_dataflow__delay_ready_261 || !_dataflow__delay_valid_261) && _dataflow__delay_ready_260 && _dataflow__delay_valid_260) begin _dataflow__delay_data_261 <= _dataflow__delay_data_260; end if(_dataflow__delay_valid_261 && _dataflow__delay_ready_261) begin _dataflow__delay_valid_261 <= 0; end if((_dataflow__delay_ready_261 || !_dataflow__delay_valid_261) && _dataflow__delay_ready_260) begin _dataflow__delay_valid_261 <= _dataflow__delay_valid_260; end if((_dataflow__delay_ready_271 || !_dataflow__delay_valid_271) && _dataflow__delay_ready_270 && _dataflow__delay_valid_270) begin _dataflow__delay_data_271 <= _dataflow__delay_data_270; end if(_dataflow__delay_valid_271 && _dataflow__delay_ready_271) begin _dataflow__delay_valid_271 <= 0; end if((_dataflow__delay_ready_271 || !_dataflow__delay_valid_271) && _dataflow__delay_ready_270) begin _dataflow__delay_valid_271 <= _dataflow__delay_valid_270; end if((_dataflow__delay_ready_290 || !_dataflow__delay_valid_290) && _dataflow__delay_ready_289 && _dataflow__delay_valid_289) begin _dataflow__delay_data_290 <= _dataflow__delay_data_289; end if(_dataflow__delay_valid_290 && _dataflow__delay_ready_290) begin _dataflow__delay_valid_290 <= 0; end if((_dataflow__delay_ready_290 || !_dataflow__delay_valid_290) && _dataflow__delay_ready_289) begin _dataflow__delay_valid_290 <= _dataflow__delay_valid_289; end if((_dataflow__delay_ready_306 || !_dataflow__delay_valid_306) && _dataflow__delay_ready_305 && _dataflow__delay_valid_305) begin _dataflow__delay_data_306 <= _dataflow__delay_data_305; end if(_dataflow__delay_valid_306 && _dataflow__delay_ready_306) begin _dataflow__delay_valid_306 <= 0; end if((_dataflow__delay_ready_306 || !_dataflow__delay_valid_306) && _dataflow__delay_ready_305) begin _dataflow__delay_valid_306 <= _dataflow__delay_valid_305; end if((_dataflow__delay_ready_330 || !_dataflow__delay_valid_330) && _dataflow__delay_ready_329 && _dataflow__delay_valid_329) begin _dataflow__delay_data_330 <= _dataflow__delay_data_329; end if(_dataflow__delay_valid_330 && _dataflow__delay_ready_330) begin _dataflow__delay_valid_330 <= 0; end if((_dataflow__delay_ready_330 || !_dataflow__delay_valid_330) && _dataflow__delay_ready_329) begin _dataflow__delay_valid_330 <= _dataflow__delay_valid_329; end if((_dataflow__delay_ready_180 || !_dataflow__delay_valid_180) && _dataflow__delay_ready_179 && _dataflow__delay_valid_179) begin _dataflow__delay_data_180 <= _dataflow__delay_data_179; end if(_dataflow__delay_valid_180 && _dataflow__delay_ready_180) begin _dataflow__delay_valid_180 <= 0; end if((_dataflow__delay_ready_180 || !_dataflow__delay_valid_180) && _dataflow__delay_ready_179) begin _dataflow__delay_valid_180 <= _dataflow__delay_valid_179; end if((_dataflow__delay_ready_191 || !_dataflow__delay_valid_191) && _dataflow__delay_ready_190 && _dataflow__delay_valid_190) begin _dataflow__delay_data_191 <= _dataflow__delay_data_190; end if(_dataflow__delay_valid_191 && _dataflow__delay_ready_191) begin _dataflow__delay_valid_191 <= 0; end if((_dataflow__delay_ready_191 || !_dataflow__delay_valid_191) && _dataflow__delay_ready_190) begin _dataflow__delay_valid_191 <= _dataflow__delay_valid_190; end if((_dataflow__delay_ready_210 || !_dataflow__delay_valid_210) && _dataflow__delay_ready_209 && _dataflow__delay_valid_209) begin _dataflow__delay_data_210 <= _dataflow__delay_data_209; end if(_dataflow__delay_valid_210 && _dataflow__delay_ready_210) begin _dataflow__delay_valid_210 <= 0; end if((_dataflow__delay_ready_210 || !_dataflow__delay_valid_210) && _dataflow__delay_ready_209) begin _dataflow__delay_valid_210 <= _dataflow__delay_valid_209; end if((_dataflow__delay_ready_221 || !_dataflow__delay_valid_221) && _dataflow__delay_ready_220 && _dataflow__delay_valid_220) begin _dataflow__delay_data_221 <= _dataflow__delay_data_220; end if(_dataflow__delay_valid_221 && _dataflow__delay_ready_221) begin _dataflow__delay_valid_221 <= 0; end if((_dataflow__delay_ready_221 || !_dataflow__delay_valid_221) && _dataflow__delay_ready_220) begin _dataflow__delay_valid_221 <= _dataflow__delay_valid_220; end if((_dataflow__delay_ready_232 || !_dataflow__delay_valid_232) && _dataflow__delay_ready_231 && _dataflow__delay_valid_231) begin _dataflow__delay_data_232 <= _dataflow__delay_data_231; end if(_dataflow__delay_valid_232 && _dataflow__delay_ready_232) begin _dataflow__delay_valid_232 <= 0; end if((_dataflow__delay_ready_232 || !_dataflow__delay_valid_232) && _dataflow__delay_ready_231) begin _dataflow__delay_valid_232 <= _dataflow__delay_valid_231; end if((_dataflow__delay_ready_242 || !_dataflow__delay_valid_242) && _dataflow__delay_ready_241 && _dataflow__delay_valid_241) begin _dataflow__delay_data_242 <= _dataflow__delay_data_241; end if(_dataflow__delay_valid_242 && _dataflow__delay_ready_242) begin _dataflow__delay_valid_242 <= 0; end if((_dataflow__delay_ready_242 || !_dataflow__delay_valid_242) && _dataflow__delay_ready_241) begin _dataflow__delay_valid_242 <= _dataflow__delay_valid_241; end if((_dataflow__delay_ready_252 || !_dataflow__delay_valid_252) && _dataflow__delay_ready_251 && _dataflow__delay_valid_251) begin _dataflow__delay_data_252 <= _dataflow__delay_data_251; end if(_dataflow__delay_valid_252 && _dataflow__delay_ready_252) begin _dataflow__delay_valid_252 <= 0; end if((_dataflow__delay_ready_252 || !_dataflow__delay_valid_252) && _dataflow__delay_ready_251) begin _dataflow__delay_valid_252 <= _dataflow__delay_valid_251; end if((_dataflow__delay_ready_262 || !_dataflow__delay_valid_262) && _dataflow__delay_ready_261 && _dataflow__delay_valid_261) begin _dataflow__delay_data_262 <= _dataflow__delay_data_261; end if(_dataflow__delay_valid_262 && _dataflow__delay_ready_262) begin _dataflow__delay_valid_262 <= 0; end if((_dataflow__delay_ready_262 || !_dataflow__delay_valid_262) && _dataflow__delay_ready_261) begin _dataflow__delay_valid_262 <= _dataflow__delay_valid_261; end if((_dataflow__delay_ready_272 || !_dataflow__delay_valid_272) && _dataflow__delay_ready_271 && _dataflow__delay_valid_271) begin _dataflow__delay_data_272 <= _dataflow__delay_data_271; end if(_dataflow__delay_valid_272 && _dataflow__delay_ready_272) begin _dataflow__delay_valid_272 <= 0; end if((_dataflow__delay_ready_272 || !_dataflow__delay_valid_272) && _dataflow__delay_ready_271) begin _dataflow__delay_valid_272 <= _dataflow__delay_valid_271; end if((_dataflow__delay_ready_291 || !_dataflow__delay_valid_291) && _dataflow__delay_ready_290 && _dataflow__delay_valid_290) begin _dataflow__delay_data_291 <= _dataflow__delay_data_290; end if(_dataflow__delay_valid_291 && _dataflow__delay_ready_291) begin _dataflow__delay_valid_291 <= 0; end if((_dataflow__delay_ready_291 || !_dataflow__delay_valid_291) && _dataflow__delay_ready_290) begin _dataflow__delay_valid_291 <= _dataflow__delay_valid_290; end if((_dataflow__delay_ready_307 || !_dataflow__delay_valid_307) && _dataflow__delay_ready_306 && _dataflow__delay_valid_306) begin _dataflow__delay_data_307 <= _dataflow__delay_data_306; end if(_dataflow__delay_valid_307 && _dataflow__delay_ready_307) begin _dataflow__delay_valid_307 <= 0; end if((_dataflow__delay_ready_307 || !_dataflow__delay_valid_307) && _dataflow__delay_ready_306) begin _dataflow__delay_valid_307 <= _dataflow__delay_valid_306; end if((_dataflow__delay_ready_331 || !_dataflow__delay_valid_331) && _dataflow__delay_ready_330 && _dataflow__delay_valid_330) begin _dataflow__delay_data_331 <= _dataflow__delay_data_330; end if(_dataflow__delay_valid_331 && _dataflow__delay_ready_331) begin _dataflow__delay_valid_331 <= 0; end if((_dataflow__delay_ready_331 || !_dataflow__delay_valid_331) && _dataflow__delay_ready_330) begin _dataflow__delay_valid_331 <= _dataflow__delay_valid_330; end if((_dataflow__delay_ready_181 || !_dataflow__delay_valid_181) && _dataflow__delay_ready_180 && _dataflow__delay_valid_180) begin _dataflow__delay_data_181 <= _dataflow__delay_data_180; end if(_dataflow__delay_valid_181 && _dataflow__delay_ready_181) begin _dataflow__delay_valid_181 <= 0; end if((_dataflow__delay_ready_181 || !_dataflow__delay_valid_181) && _dataflow__delay_ready_180) begin _dataflow__delay_valid_181 <= _dataflow__delay_valid_180; end if((_dataflow__delay_ready_192 || !_dataflow__delay_valid_192) && _dataflow__delay_ready_191 && _dataflow__delay_valid_191) begin _dataflow__delay_data_192 <= _dataflow__delay_data_191; end if(_dataflow__delay_valid_192 && _dataflow__delay_ready_192) begin _dataflow__delay_valid_192 <= 0; end if((_dataflow__delay_ready_192 || !_dataflow__delay_valid_192) && _dataflow__delay_ready_191) begin _dataflow__delay_valid_192 <= _dataflow__delay_valid_191; end if((_dataflow__delay_ready_211 || !_dataflow__delay_valid_211) && _dataflow__delay_ready_210 && _dataflow__delay_valid_210) begin _dataflow__delay_data_211 <= _dataflow__delay_data_210; end if(_dataflow__delay_valid_211 && _dataflow__delay_ready_211) begin _dataflow__delay_valid_211 <= 0; end if((_dataflow__delay_ready_211 || !_dataflow__delay_valid_211) && _dataflow__delay_ready_210) begin _dataflow__delay_valid_211 <= _dataflow__delay_valid_210; end if((_dataflow__delay_ready_222 || !_dataflow__delay_valid_222) && _dataflow__delay_ready_221 && _dataflow__delay_valid_221) begin _dataflow__delay_data_222 <= _dataflow__delay_data_221; end if(_dataflow__delay_valid_222 && _dataflow__delay_ready_222) begin _dataflow__delay_valid_222 <= 0; end if((_dataflow__delay_ready_222 || !_dataflow__delay_valid_222) && _dataflow__delay_ready_221) begin _dataflow__delay_valid_222 <= _dataflow__delay_valid_221; end if((_dataflow__delay_ready_233 || !_dataflow__delay_valid_233) && _dataflow__delay_ready_232 && _dataflow__delay_valid_232) begin _dataflow__delay_data_233 <= _dataflow__delay_data_232; end if(_dataflow__delay_valid_233 && _dataflow__delay_ready_233) begin _dataflow__delay_valid_233 <= 0; end if((_dataflow__delay_ready_233 || !_dataflow__delay_valid_233) && _dataflow__delay_ready_232) begin _dataflow__delay_valid_233 <= _dataflow__delay_valid_232; end if((_dataflow__delay_ready_243 || !_dataflow__delay_valid_243) && _dataflow__delay_ready_242 && _dataflow__delay_valid_242) begin _dataflow__delay_data_243 <= _dataflow__delay_data_242; end if(_dataflow__delay_valid_243 && _dataflow__delay_ready_243) begin _dataflow__delay_valid_243 <= 0; end if((_dataflow__delay_ready_243 || !_dataflow__delay_valid_243) && _dataflow__delay_ready_242) begin _dataflow__delay_valid_243 <= _dataflow__delay_valid_242; end if((_dataflow__delay_ready_253 || !_dataflow__delay_valid_253) && _dataflow__delay_ready_252 && _dataflow__delay_valid_252) begin _dataflow__delay_data_253 <= _dataflow__delay_data_252; end if(_dataflow__delay_valid_253 && _dataflow__delay_ready_253) begin _dataflow__delay_valid_253 <= 0; end if((_dataflow__delay_ready_253 || !_dataflow__delay_valid_253) && _dataflow__delay_ready_252) begin _dataflow__delay_valid_253 <= _dataflow__delay_valid_252; end if((_dataflow__delay_ready_263 || !_dataflow__delay_valid_263) && _dataflow__delay_ready_262 && _dataflow__delay_valid_262) begin _dataflow__delay_data_263 <= _dataflow__delay_data_262; end if(_dataflow__delay_valid_263 && _dataflow__delay_ready_263) begin _dataflow__delay_valid_263 <= 0; end if((_dataflow__delay_ready_263 || !_dataflow__delay_valid_263) && _dataflow__delay_ready_262) begin _dataflow__delay_valid_263 <= _dataflow__delay_valid_262; end if((_dataflow__delay_ready_273 || !_dataflow__delay_valid_273) && _dataflow__delay_ready_272 && _dataflow__delay_valid_272) begin _dataflow__delay_data_273 <= _dataflow__delay_data_272; end if(_dataflow__delay_valid_273 && _dataflow__delay_ready_273) begin _dataflow__delay_valid_273 <= 0; end if((_dataflow__delay_ready_273 || !_dataflow__delay_valid_273) && _dataflow__delay_ready_272) begin _dataflow__delay_valid_273 <= _dataflow__delay_valid_272; end if((_dataflow__delay_ready_292 || !_dataflow__delay_valid_292) && _dataflow__delay_ready_291 && _dataflow__delay_valid_291) begin _dataflow__delay_data_292 <= _dataflow__delay_data_291; end if(_dataflow__delay_valid_292 && _dataflow__delay_ready_292) begin _dataflow__delay_valid_292 <= 0; end if((_dataflow__delay_ready_292 || !_dataflow__delay_valid_292) && _dataflow__delay_ready_291) begin _dataflow__delay_valid_292 <= _dataflow__delay_valid_291; end if((_dataflow__delay_ready_308 || !_dataflow__delay_valid_308) && _dataflow__delay_ready_307 && _dataflow__delay_valid_307) begin _dataflow__delay_data_308 <= _dataflow__delay_data_307; end if(_dataflow__delay_valid_308 && _dataflow__delay_ready_308) begin _dataflow__delay_valid_308 <= 0; end if((_dataflow__delay_ready_308 || !_dataflow__delay_valid_308) && _dataflow__delay_ready_307) begin _dataflow__delay_valid_308 <= _dataflow__delay_valid_307; end if((_dataflow__delay_ready_332 || !_dataflow__delay_valid_332) && _dataflow__delay_ready_331 && _dataflow__delay_valid_331) begin _dataflow__delay_data_332 <= _dataflow__delay_data_331; end if(_dataflow__delay_valid_332 && _dataflow__delay_ready_332) begin _dataflow__delay_valid_332 <= 0; end if((_dataflow__delay_ready_332 || !_dataflow__delay_valid_332) && _dataflow__delay_ready_331) begin _dataflow__delay_valid_332 <= _dataflow__delay_valid_331; end if((_dataflow_minus_ready_48 || !_dataflow_minus_valid_48) && (_dataflow_times_ready_44 && _dataflow_times_ready_45) && (_dataflow_times_valid_44 && _dataflow_times_valid_45)) begin _dataflow_minus_data_48 <= _dataflow_times_data_44 - _dataflow_times_data_45; end if(_dataflow_minus_valid_48 && _dataflow_minus_ready_48) begin _dataflow_minus_valid_48 <= 0; end if((_dataflow_minus_ready_48 || !_dataflow_minus_valid_48) && (_dataflow_times_ready_44 && _dataflow_times_ready_45)) begin _dataflow_minus_valid_48 <= _dataflow_times_valid_44 && _dataflow_times_valid_45; end if((_dataflow_plus_ready_49 || !_dataflow_plus_valid_49) && (_dataflow_times_ready_46 && _dataflow_times_ready_47) && (_dataflow_times_valid_46 && _dataflow_times_valid_47)) begin _dataflow_plus_data_49 <= _dataflow_times_data_46 + _dataflow_times_data_47; end if(_dataflow_plus_valid_49 && _dataflow_plus_ready_49) begin _dataflow_plus_valid_49 <= 0; end if((_dataflow_plus_ready_49 || !_dataflow_plus_valid_49) && (_dataflow_times_ready_46 && _dataflow_times_ready_47)) begin _dataflow_plus_valid_49 <= _dataflow_times_valid_46 && _dataflow_times_valid_47; end if((_dataflow_minus_ready_58 || !_dataflow_minus_valid_58) && (_dataflow_times_ready_54 && _dataflow_times_ready_55) && (_dataflow_times_valid_54 && _dataflow_times_valid_55)) begin _dataflow_minus_data_58 <= _dataflow_times_data_54 - _dataflow_times_data_55; end if(_dataflow_minus_valid_58 && _dataflow_minus_ready_58) begin _dataflow_minus_valid_58 <= 0; end if((_dataflow_minus_ready_58 || !_dataflow_minus_valid_58) && (_dataflow_times_ready_54 && _dataflow_times_ready_55)) begin _dataflow_minus_valid_58 <= _dataflow_times_valid_54 && _dataflow_times_valid_55; end if((_dataflow_plus_ready_59 || !_dataflow_plus_valid_59) && (_dataflow_times_ready_56 && _dataflow_times_ready_57) && (_dataflow_times_valid_56 && _dataflow_times_valid_57)) begin _dataflow_plus_data_59 <= _dataflow_times_data_56 + _dataflow_times_data_57; end if(_dataflow_plus_valid_59 && _dataflow_plus_ready_59) begin _dataflow_plus_valid_59 <= 0; end if((_dataflow_plus_ready_59 || !_dataflow_plus_valid_59) && (_dataflow_times_ready_56 && _dataflow_times_ready_57)) begin _dataflow_plus_valid_59 <= _dataflow_times_valid_56 && _dataflow_times_valid_57; end if((_dataflow_minus_ready_68 || !_dataflow_minus_valid_68) && (_dataflow_times_ready_64 && _dataflow_times_ready_65) && (_dataflow_times_valid_64 && _dataflow_times_valid_65)) begin _dataflow_minus_data_68 <= _dataflow_times_data_64 - _dataflow_times_data_65; end if(_dataflow_minus_valid_68 && _dataflow_minus_ready_68) begin _dataflow_minus_valid_68 <= 0; end if((_dataflow_minus_ready_68 || !_dataflow_minus_valid_68) && (_dataflow_times_ready_64 && _dataflow_times_ready_65)) begin _dataflow_minus_valid_68 <= _dataflow_times_valid_64 && _dataflow_times_valid_65; end if((_dataflow_plus_ready_69 || !_dataflow_plus_valid_69) && (_dataflow_times_ready_66 && _dataflow_times_ready_67) && (_dataflow_times_valid_66 && _dataflow_times_valid_67)) begin _dataflow_plus_data_69 <= _dataflow_times_data_66 + _dataflow_times_data_67; end if(_dataflow_plus_valid_69 && _dataflow_plus_ready_69) begin _dataflow_plus_valid_69 <= 0; end if((_dataflow_plus_ready_69 || !_dataflow_plus_valid_69) && (_dataflow_times_ready_66 && _dataflow_times_ready_67)) begin _dataflow_plus_valid_69 <= _dataflow_times_valid_66 && _dataflow_times_valid_67; end if((_dataflow_minus_ready_78 || !_dataflow_minus_valid_78) && (_dataflow_times_ready_74 && _dataflow_times_ready_75) && (_dataflow_times_valid_74 && _dataflow_times_valid_75)) begin _dataflow_minus_data_78 <= _dataflow_times_data_74 - _dataflow_times_data_75; end if(_dataflow_minus_valid_78 && _dataflow_minus_ready_78) begin _dataflow_minus_valid_78 <= 0; end if((_dataflow_minus_ready_78 || !_dataflow_minus_valid_78) && (_dataflow_times_ready_74 && _dataflow_times_ready_75)) begin _dataflow_minus_valid_78 <= _dataflow_times_valid_74 && _dataflow_times_valid_75; end if((_dataflow_plus_ready_79 || !_dataflow_plus_valid_79) && (_dataflow_times_ready_76 && _dataflow_times_ready_77) && (_dataflow_times_valid_76 && _dataflow_times_valid_77)) begin _dataflow_plus_data_79 <= _dataflow_times_data_76 + _dataflow_times_data_77; end if(_dataflow_plus_valid_79 && _dataflow_plus_ready_79) begin _dataflow_plus_valid_79 <= 0; end if((_dataflow_plus_ready_79 || !_dataflow_plus_valid_79) && (_dataflow_times_ready_76 && _dataflow_times_ready_77)) begin _dataflow_plus_valid_79 <= _dataflow_times_valid_76 && _dataflow_times_valid_77; end if((_dataflow__delay_ready_182 || !_dataflow__delay_valid_182) && _dataflow__delay_ready_181 && _dataflow__delay_valid_181) begin _dataflow__delay_data_182 <= _dataflow__delay_data_181; end if(_dataflow__delay_valid_182 && _dataflow__delay_ready_182) begin _dataflow__delay_valid_182 <= 0; end if((_dataflow__delay_ready_182 || !_dataflow__delay_valid_182) && _dataflow__delay_ready_181) begin _dataflow__delay_valid_182 <= _dataflow__delay_valid_181; end if((_dataflow__delay_ready_193 || !_dataflow__delay_valid_193) && _dataflow__delay_ready_192 && _dataflow__delay_valid_192) begin _dataflow__delay_data_193 <= _dataflow__delay_data_192; end if(_dataflow__delay_valid_193 && _dataflow__delay_ready_193) begin _dataflow__delay_valid_193 <= 0; end if((_dataflow__delay_ready_193 || !_dataflow__delay_valid_193) && _dataflow__delay_ready_192) begin _dataflow__delay_valid_193 <= _dataflow__delay_valid_192; end if((_dataflow__delay_ready_212 || !_dataflow__delay_valid_212) && _dataflow__delay_ready_211 && _dataflow__delay_valid_211) begin _dataflow__delay_data_212 <= _dataflow__delay_data_211; end if(_dataflow__delay_valid_212 && _dataflow__delay_ready_212) begin _dataflow__delay_valid_212 <= 0; end if((_dataflow__delay_ready_212 || !_dataflow__delay_valid_212) && _dataflow__delay_ready_211) begin _dataflow__delay_valid_212 <= _dataflow__delay_valid_211; end if((_dataflow__delay_ready_223 || !_dataflow__delay_valid_223) && _dataflow__delay_ready_222 && _dataflow__delay_valid_222) begin _dataflow__delay_data_223 <= _dataflow__delay_data_222; end if(_dataflow__delay_valid_223 && _dataflow__delay_ready_223) begin _dataflow__delay_valid_223 <= 0; end if((_dataflow__delay_ready_223 || !_dataflow__delay_valid_223) && _dataflow__delay_ready_222) begin _dataflow__delay_valid_223 <= _dataflow__delay_valid_222; end if((_dataflow__delay_ready_234 || !_dataflow__delay_valid_234) && _dataflow__delay_ready_233 && _dataflow__delay_valid_233) begin _dataflow__delay_data_234 <= _dataflow__delay_data_233; end if(_dataflow__delay_valid_234 && _dataflow__delay_ready_234) begin _dataflow__delay_valid_234 <= 0; end if((_dataflow__delay_ready_234 || !_dataflow__delay_valid_234) && _dataflow__delay_ready_233) begin _dataflow__delay_valid_234 <= _dataflow__delay_valid_233; end if((_dataflow__delay_ready_244 || !_dataflow__delay_valid_244) && _dataflow__delay_ready_243 && _dataflow__delay_valid_243) begin _dataflow__delay_data_244 <= _dataflow__delay_data_243; end if(_dataflow__delay_valid_244 && _dataflow__delay_ready_244) begin _dataflow__delay_valid_244 <= 0; end if((_dataflow__delay_ready_244 || !_dataflow__delay_valid_244) && _dataflow__delay_ready_243) begin _dataflow__delay_valid_244 <= _dataflow__delay_valid_243; end if((_dataflow__delay_ready_254 || !_dataflow__delay_valid_254) && _dataflow__delay_ready_253 && _dataflow__delay_valid_253) begin _dataflow__delay_data_254 <= _dataflow__delay_data_253; end if(_dataflow__delay_valid_254 && _dataflow__delay_ready_254) begin _dataflow__delay_valid_254 <= 0; end if((_dataflow__delay_ready_254 || !_dataflow__delay_valid_254) && _dataflow__delay_ready_253) begin _dataflow__delay_valid_254 <= _dataflow__delay_valid_253; end if((_dataflow__delay_ready_264 || !_dataflow__delay_valid_264) && _dataflow__delay_ready_263 && _dataflow__delay_valid_263) begin _dataflow__delay_data_264 <= _dataflow__delay_data_263; end if(_dataflow__delay_valid_264 && _dataflow__delay_ready_264) begin _dataflow__delay_valid_264 <= 0; end if((_dataflow__delay_ready_264 || !_dataflow__delay_valid_264) && _dataflow__delay_ready_263) begin _dataflow__delay_valid_264 <= _dataflow__delay_valid_263; end if((_dataflow__delay_ready_274 || !_dataflow__delay_valid_274) && _dataflow__delay_ready_273 && _dataflow__delay_valid_273) begin _dataflow__delay_data_274 <= _dataflow__delay_data_273; end if(_dataflow__delay_valid_274 && _dataflow__delay_ready_274) begin _dataflow__delay_valid_274 <= 0; end if((_dataflow__delay_ready_274 || !_dataflow__delay_valid_274) && _dataflow__delay_ready_273) begin _dataflow__delay_valid_274 <= _dataflow__delay_valid_273; end if((_dataflow__delay_ready_293 || !_dataflow__delay_valid_293) && _dataflow__delay_ready_292 && _dataflow__delay_valid_292) begin _dataflow__delay_data_293 <= _dataflow__delay_data_292; end if(_dataflow__delay_valid_293 && _dataflow__delay_ready_293) begin _dataflow__delay_valid_293 <= 0; end if((_dataflow__delay_ready_293 || !_dataflow__delay_valid_293) && _dataflow__delay_ready_292) begin _dataflow__delay_valid_293 <= _dataflow__delay_valid_292; end if((_dataflow__delay_ready_309 || !_dataflow__delay_valid_309) && _dataflow__delay_ready_308 && _dataflow__delay_valid_308) begin _dataflow__delay_data_309 <= _dataflow__delay_data_308; end if(_dataflow__delay_valid_309 && _dataflow__delay_ready_309) begin _dataflow__delay_valid_309 <= 0; end if((_dataflow__delay_ready_309 || !_dataflow__delay_valid_309) && _dataflow__delay_ready_308) begin _dataflow__delay_valid_309 <= _dataflow__delay_valid_308; end if((_dataflow__delay_ready_333 || !_dataflow__delay_valid_333) && _dataflow__delay_ready_332 && _dataflow__delay_valid_332) begin _dataflow__delay_data_333 <= _dataflow__delay_data_332; end if(_dataflow__delay_valid_333 && _dataflow__delay_ready_333) begin _dataflow__delay_valid_333 <= 0; end if((_dataflow__delay_ready_333 || !_dataflow__delay_valid_333) && _dataflow__delay_ready_332) begin _dataflow__delay_valid_333 <= _dataflow__delay_valid_332; end if((_dataflow_minus_ready_88 || !_dataflow_minus_valid_88) && (_dataflow_times_ready_84 && _dataflow_times_ready_85) && (_dataflow_times_valid_84 && _dataflow_times_valid_85)) begin _dataflow_minus_data_88 <= _dataflow_times_data_84 - _dataflow_times_data_85; end if(_dataflow_minus_valid_88 && _dataflow_minus_ready_88) begin _dataflow_minus_valid_88 <= 0; end if((_dataflow_minus_ready_88 || !_dataflow_minus_valid_88) && (_dataflow_times_ready_84 && _dataflow_times_ready_85)) begin _dataflow_minus_valid_88 <= _dataflow_times_valid_84 && _dataflow_times_valid_85; end if((_dataflow_plus_ready_89 || !_dataflow_plus_valid_89) && (_dataflow_times_ready_86 && _dataflow_times_ready_87) && (_dataflow_times_valid_86 && _dataflow_times_valid_87)) begin _dataflow_plus_data_89 <= _dataflow_times_data_86 + _dataflow_times_data_87; end if(_dataflow_plus_valid_89 && _dataflow_plus_ready_89) begin _dataflow_plus_valid_89 <= 0; end if((_dataflow_plus_ready_89 || !_dataflow_plus_valid_89) && (_dataflow_times_ready_86 && _dataflow_times_ready_87)) begin _dataflow_plus_valid_89 <= _dataflow_times_valid_86 && _dataflow_times_valid_87; end if((_dataflow_minus_ready_98 || !_dataflow_minus_valid_98) && (_dataflow_times_ready_94 && _dataflow_times_ready_95) && (_dataflow_times_valid_94 && _dataflow_times_valid_95)) begin _dataflow_minus_data_98 <= _dataflow_times_data_94 - _dataflow_times_data_95; end if(_dataflow_minus_valid_98 && _dataflow_minus_ready_98) begin _dataflow_minus_valid_98 <= 0; end if((_dataflow_minus_ready_98 || !_dataflow_minus_valid_98) && (_dataflow_times_ready_94 && _dataflow_times_ready_95)) begin _dataflow_minus_valid_98 <= _dataflow_times_valid_94 && _dataflow_times_valid_95; end if((_dataflow_plus_ready_99 || !_dataflow_plus_valid_99) && (_dataflow_times_ready_96 && _dataflow_times_ready_97) && (_dataflow_times_valid_96 && _dataflow_times_valid_97)) begin _dataflow_plus_data_99 <= _dataflow_times_data_96 + _dataflow_times_data_97; end if(_dataflow_plus_valid_99 && _dataflow_plus_ready_99) begin _dataflow_plus_valid_99 <= 0; end if((_dataflow_plus_ready_99 || !_dataflow_plus_valid_99) && (_dataflow_times_ready_96 && _dataflow_times_ready_97)) begin _dataflow_plus_valid_99 <= _dataflow_times_valid_96 && _dataflow_times_valid_97; end if((_dataflow_plus_ready_100 || !_dataflow_plus_valid_100) && (_dataflow_minus_ready_48 && _dataflow_minus_ready_68) && (_dataflow_minus_valid_48 && _dataflow_minus_valid_68)) begin _dataflow_plus_data_100 <= _dataflow_minus_data_48 + _dataflow_minus_data_68; end if(_dataflow_plus_valid_100 && _dataflow_plus_ready_100) begin _dataflow_plus_valid_100 <= 0; end if((_dataflow_plus_ready_100 || !_dataflow_plus_valid_100) && (_dataflow_minus_ready_48 && _dataflow_minus_ready_68)) begin _dataflow_plus_valid_100 <= _dataflow_minus_valid_48 && _dataflow_minus_valid_68; end if((_dataflow_plus_ready_101 || !_dataflow_plus_valid_101) && (_dataflow_plus_ready_49 && _dataflow_plus_ready_69) && (_dataflow_plus_valid_49 && _dataflow_plus_valid_69)) begin _dataflow_plus_data_101 <= _dataflow_plus_data_49 + _dataflow_plus_data_69; end if(_dataflow_plus_valid_101 && _dataflow_plus_ready_101) begin _dataflow_plus_valid_101 <= 0; end if((_dataflow_plus_ready_101 || !_dataflow_plus_valid_101) && (_dataflow_plus_ready_49 && _dataflow_plus_ready_69)) begin _dataflow_plus_valid_101 <= _dataflow_plus_valid_49 && _dataflow_plus_valid_69; end if((_dataflow_minus_ready_102 || !_dataflow_minus_valid_102) && (_dataflow_minus_ready_48 && _dataflow_minus_ready_68) && (_dataflow_minus_valid_48 && _dataflow_minus_valid_68)) begin _dataflow_minus_data_102 <= _dataflow_minus_data_48 - _dataflow_minus_data_68; end if(_dataflow_minus_valid_102 && _dataflow_minus_ready_102) begin _dataflow_minus_valid_102 <= 0; end if((_dataflow_minus_ready_102 || !_dataflow_minus_valid_102) && (_dataflow_minus_ready_48 && _dataflow_minus_ready_68)) begin _dataflow_minus_valid_102 <= _dataflow_minus_valid_48 && _dataflow_minus_valid_68; end if((_dataflow_minus_ready_103 || !_dataflow_minus_valid_103) && (_dataflow_plus_ready_49 && _dataflow_plus_ready_69) && (_dataflow_plus_valid_49 && _dataflow_plus_valid_69)) begin _dataflow_minus_data_103 <= _dataflow_plus_data_49 - _dataflow_plus_data_69; end if(_dataflow_minus_valid_103 && _dataflow_minus_ready_103) begin _dataflow_minus_valid_103 <= 0; end if((_dataflow_minus_ready_103 || !_dataflow_minus_valid_103) && (_dataflow_plus_ready_49 && _dataflow_plus_ready_69)) begin _dataflow_minus_valid_103 <= _dataflow_plus_valid_49 && _dataflow_plus_valid_69; end if((_dataflow_plus_ready_110 || !_dataflow_plus_valid_110) && (_dataflow_minus_ready_58 && _dataflow_minus_ready_78) && (_dataflow_minus_valid_58 && _dataflow_minus_valid_78)) begin _dataflow_plus_data_110 <= _dataflow_minus_data_58 + _dataflow_minus_data_78; end if(_dataflow_plus_valid_110 && _dataflow_plus_ready_110) begin _dataflow_plus_valid_110 <= 0; end if((_dataflow_plus_ready_110 || !_dataflow_plus_valid_110) && (_dataflow_minus_ready_58 && _dataflow_minus_ready_78)) begin _dataflow_plus_valid_110 <= _dataflow_minus_valid_58 && _dataflow_minus_valid_78; end if((_dataflow_plus_ready_111 || !_dataflow_plus_valid_111) && (_dataflow_plus_ready_59 && _dataflow_plus_ready_79) && (_dataflow_plus_valid_59 && _dataflow_plus_valid_79)) begin _dataflow_plus_data_111 <= _dataflow_plus_data_59 + _dataflow_plus_data_79; end if(_dataflow_plus_valid_111 && _dataflow_plus_ready_111) begin _dataflow_plus_valid_111 <= 0; end if((_dataflow_plus_ready_111 || !_dataflow_plus_valid_111) && (_dataflow_plus_ready_59 && _dataflow_plus_ready_79)) begin _dataflow_plus_valid_111 <= _dataflow_plus_valid_59 && _dataflow_plus_valid_79; end if((_dataflow_minus_ready_112 || !_dataflow_minus_valid_112) && (_dataflow_minus_ready_58 && _dataflow_minus_ready_78) && (_dataflow_minus_valid_58 && _dataflow_minus_valid_78)) begin _dataflow_minus_data_112 <= _dataflow_minus_data_58 - _dataflow_minus_data_78; end if(_dataflow_minus_valid_112 && _dataflow_minus_ready_112) begin _dataflow_minus_valid_112 <= 0; end if((_dataflow_minus_ready_112 || !_dataflow_minus_valid_112) && (_dataflow_minus_ready_58 && _dataflow_minus_ready_78)) begin _dataflow_minus_valid_112 <= _dataflow_minus_valid_58 && _dataflow_minus_valid_78; end if((_dataflow_minus_ready_113 || !_dataflow_minus_valid_113) && (_dataflow_plus_ready_59 && _dataflow_plus_ready_79) && (_dataflow_plus_valid_59 && _dataflow_plus_valid_79)) begin _dataflow_minus_data_113 <= _dataflow_plus_data_59 - _dataflow_plus_data_79; end if(_dataflow_minus_valid_113 && _dataflow_minus_ready_113) begin _dataflow_minus_valid_113 <= 0; end if((_dataflow_minus_ready_113 || !_dataflow_minus_valid_113) && (_dataflow_plus_ready_59 && _dataflow_plus_ready_79)) begin _dataflow_minus_valid_113 <= _dataflow_plus_valid_59 && _dataflow_plus_valid_79; end if((_dataflow__delay_ready_183 || !_dataflow__delay_valid_183) && _dataflow__delay_ready_182 && _dataflow__delay_valid_182) begin _dataflow__delay_data_183 <= _dataflow__delay_data_182; end if(_dataflow__delay_valid_183 && _dataflow__delay_ready_183) begin _dataflow__delay_valid_183 <= 0; end if((_dataflow__delay_ready_183 || !_dataflow__delay_valid_183) && _dataflow__delay_ready_182) begin _dataflow__delay_valid_183 <= _dataflow__delay_valid_182; end if((_dataflow__delay_ready_194 || !_dataflow__delay_valid_194) && _dataflow__delay_ready_193 && _dataflow__delay_valid_193) begin _dataflow__delay_data_194 <= _dataflow__delay_data_193; end if(_dataflow__delay_valid_194 && _dataflow__delay_ready_194) begin _dataflow__delay_valid_194 <= 0; end if((_dataflow__delay_ready_194 || !_dataflow__delay_valid_194) && _dataflow__delay_ready_193) begin _dataflow__delay_valid_194 <= _dataflow__delay_valid_193; end if((_dataflow__delay_ready_213 || !_dataflow__delay_valid_213) && _dataflow__delay_ready_212 && _dataflow__delay_valid_212) begin _dataflow__delay_data_213 <= _dataflow__delay_data_212; end if(_dataflow__delay_valid_213 && _dataflow__delay_ready_213) begin _dataflow__delay_valid_213 <= 0; end if((_dataflow__delay_ready_213 || !_dataflow__delay_valid_213) && _dataflow__delay_ready_212) begin _dataflow__delay_valid_213 <= _dataflow__delay_valid_212; end if((_dataflow__delay_ready_224 || !_dataflow__delay_valid_224) && _dataflow__delay_ready_223 && _dataflow__delay_valid_223) begin _dataflow__delay_data_224 <= _dataflow__delay_data_223; end if(_dataflow__delay_valid_224 && _dataflow__delay_ready_224) begin _dataflow__delay_valid_224 <= 0; end if((_dataflow__delay_ready_224 || !_dataflow__delay_valid_224) && _dataflow__delay_ready_223) begin _dataflow__delay_valid_224 <= _dataflow__delay_valid_223; end if((_dataflow__delay_ready_235 || !_dataflow__delay_valid_235) && _dataflow__delay_ready_234 && _dataflow__delay_valid_234) begin _dataflow__delay_data_235 <= _dataflow__delay_data_234; end if(_dataflow__delay_valid_235 && _dataflow__delay_ready_235) begin _dataflow__delay_valid_235 <= 0; end if((_dataflow__delay_ready_235 || !_dataflow__delay_valid_235) && _dataflow__delay_ready_234) begin _dataflow__delay_valid_235 <= _dataflow__delay_valid_234; end if((_dataflow__delay_ready_245 || !_dataflow__delay_valid_245) && _dataflow__delay_ready_244 && _dataflow__delay_valid_244) begin _dataflow__delay_data_245 <= _dataflow__delay_data_244; end if(_dataflow__delay_valid_245 && _dataflow__delay_ready_245) begin _dataflow__delay_valid_245 <= 0; end if((_dataflow__delay_ready_245 || !_dataflow__delay_valid_245) && _dataflow__delay_ready_244) begin _dataflow__delay_valid_245 <= _dataflow__delay_valid_244; end if((_dataflow__delay_ready_255 || !_dataflow__delay_valid_255) && _dataflow__delay_ready_254 && _dataflow__delay_valid_254) begin _dataflow__delay_data_255 <= _dataflow__delay_data_254; end if(_dataflow__delay_valid_255 && _dataflow__delay_ready_255) begin _dataflow__delay_valid_255 <= 0; end if((_dataflow__delay_ready_255 || !_dataflow__delay_valid_255) && _dataflow__delay_ready_254) begin _dataflow__delay_valid_255 <= _dataflow__delay_valid_254; end if((_dataflow__delay_ready_265 || !_dataflow__delay_valid_265) && _dataflow__delay_ready_264 && _dataflow__delay_valid_264) begin _dataflow__delay_data_265 <= _dataflow__delay_data_264; end if(_dataflow__delay_valid_265 && _dataflow__delay_ready_265) begin _dataflow__delay_valid_265 <= 0; end if((_dataflow__delay_ready_265 || !_dataflow__delay_valid_265) && _dataflow__delay_ready_264) begin _dataflow__delay_valid_265 <= _dataflow__delay_valid_264; end if((_dataflow__delay_ready_275 || !_dataflow__delay_valid_275) && _dataflow__delay_ready_274 && _dataflow__delay_valid_274) begin _dataflow__delay_data_275 <= _dataflow__delay_data_274; end if(_dataflow__delay_valid_275 && _dataflow__delay_ready_275) begin _dataflow__delay_valid_275 <= 0; end if((_dataflow__delay_ready_275 || !_dataflow__delay_valid_275) && _dataflow__delay_ready_274) begin _dataflow__delay_valid_275 <= _dataflow__delay_valid_274; end if((_dataflow__delay_ready_294 || !_dataflow__delay_valid_294) && _dataflow__delay_ready_293 && _dataflow__delay_valid_293) begin _dataflow__delay_data_294 <= _dataflow__delay_data_293; end if(_dataflow__delay_valid_294 && _dataflow__delay_ready_294) begin _dataflow__delay_valid_294 <= 0; end if((_dataflow__delay_ready_294 || !_dataflow__delay_valid_294) && _dataflow__delay_ready_293) begin _dataflow__delay_valid_294 <= _dataflow__delay_valid_293; end if((_dataflow__delay_ready_310 || !_dataflow__delay_valid_310) && _dataflow__delay_ready_309 && _dataflow__delay_valid_309) begin _dataflow__delay_data_310 <= _dataflow__delay_data_309; end if(_dataflow__delay_valid_310 && _dataflow__delay_ready_310) begin _dataflow__delay_valid_310 <= 0; end if((_dataflow__delay_ready_310 || !_dataflow__delay_valid_310) && _dataflow__delay_ready_309) begin _dataflow__delay_valid_310 <= _dataflow__delay_valid_309; end if((_dataflow__delay_ready_334 || !_dataflow__delay_valid_334) && _dataflow__delay_ready_333 && _dataflow__delay_valid_333) begin _dataflow__delay_data_334 <= _dataflow__delay_data_333; end if(_dataflow__delay_valid_334 && _dataflow__delay_ready_334) begin _dataflow__delay_valid_334 <= 0; end if((_dataflow__delay_ready_334 || !_dataflow__delay_valid_334) && _dataflow__delay_ready_333) begin _dataflow__delay_valid_334 <= _dataflow__delay_valid_333; end if(_dataflow_times_ready_104 || !_dataflow_times_valid_104) begin _dataflow_times_mul_odata_reg_104 <= _dataflow_times_mul_odata_104 >>> 8; end if(_dataflow_times_ready_104 || !_dataflow_times_valid_104) begin _dataflow_times_mul_valid_reg_104 <= _dataflow_times_mul_ovalid_104; end if(_dataflow_times_ready_105 || !_dataflow_times_valid_105) begin _dataflow_times_mul_odata_reg_105 <= _dataflow_times_mul_odata_105 >>> 8; end if(_dataflow_times_ready_105 || !_dataflow_times_valid_105) begin _dataflow_times_mul_valid_reg_105 <= _dataflow_times_mul_ovalid_105; end if(_dataflow_times_ready_106 || !_dataflow_times_valid_106) begin _dataflow_times_mul_odata_reg_106 <= _dataflow_times_mul_odata_106 >>> 8; end if(_dataflow_times_ready_106 || !_dataflow_times_valid_106) begin _dataflow_times_mul_valid_reg_106 <= _dataflow_times_mul_ovalid_106; end if(_dataflow_times_ready_107 || !_dataflow_times_valid_107) begin _dataflow_times_mul_odata_reg_107 <= _dataflow_times_mul_odata_107 >>> 8; end if(_dataflow_times_ready_107 || !_dataflow_times_valid_107) begin _dataflow_times_mul_valid_reg_107 <= _dataflow_times_mul_ovalid_107; end if(_dataflow_times_ready_114 || !_dataflow_times_valid_114) begin _dataflow_times_mul_odata_reg_114 <= _dataflow_times_mul_odata_114 >>> 8; end if(_dataflow_times_ready_114 || !_dataflow_times_valid_114) begin _dataflow_times_mul_valid_reg_114 <= _dataflow_times_mul_ovalid_114; end if(_dataflow_times_ready_115 || !_dataflow_times_valid_115) begin _dataflow_times_mul_odata_reg_115 <= _dataflow_times_mul_odata_115 >>> 8; end if(_dataflow_times_ready_115 || !_dataflow_times_valid_115) begin _dataflow_times_mul_valid_reg_115 <= _dataflow_times_mul_ovalid_115; end if(_dataflow_times_ready_116 || !_dataflow_times_valid_116) begin _dataflow_times_mul_odata_reg_116 <= _dataflow_times_mul_odata_116 >>> 8; end if(_dataflow_times_ready_116 || !_dataflow_times_valid_116) begin _dataflow_times_mul_valid_reg_116 <= _dataflow_times_mul_ovalid_116; end if(_dataflow_times_ready_117 || !_dataflow_times_valid_117) begin _dataflow_times_mul_odata_reg_117 <= _dataflow_times_mul_odata_117 >>> 8; end if(_dataflow_times_ready_117 || !_dataflow_times_valid_117) begin _dataflow_times_mul_valid_reg_117 <= _dataflow_times_mul_ovalid_117; end if((_dataflow_minus_ready_128 || !_dataflow_minus_valid_128) && (_dataflow_times_ready_124 && _dataflow_times_ready_125) && (_dataflow_times_valid_124 && _dataflow_times_valid_125)) begin _dataflow_minus_data_128 <= _dataflow_times_data_124 - _dataflow_times_data_125; end if(_dataflow_minus_valid_128 && _dataflow_minus_ready_128) begin _dataflow_minus_valid_128 <= 0; end if((_dataflow_minus_ready_128 || !_dataflow_minus_valid_128) && (_dataflow_times_ready_124 && _dataflow_times_ready_125)) begin _dataflow_minus_valid_128 <= _dataflow_times_valid_124 && _dataflow_times_valid_125; end if((_dataflow_plus_ready_129 || !_dataflow_plus_valid_129) && (_dataflow_times_ready_126 && _dataflow_times_ready_127) && (_dataflow_times_valid_126 && _dataflow_times_valid_127)) begin _dataflow_plus_data_129 <= _dataflow_times_data_126 + _dataflow_times_data_127; end if(_dataflow_plus_valid_129 && _dataflow_plus_ready_129) begin _dataflow_plus_valid_129 <= 0; end if((_dataflow_plus_ready_129 || !_dataflow_plus_valid_129) && (_dataflow_times_ready_126 && _dataflow_times_ready_127)) begin _dataflow_plus_valid_129 <= _dataflow_times_valid_126 && _dataflow_times_valid_127; end if((_dataflow_plus_ready_130 || !_dataflow_plus_valid_130) && (_dataflow_minus_ready_88 && _dataflow_minus_ready_98) && (_dataflow_minus_valid_88 && _dataflow_minus_valid_98)) begin _dataflow_plus_data_130 <= _dataflow_minus_data_88 + _dataflow_minus_data_98; end if(_dataflow_plus_valid_130 && _dataflow_plus_ready_130) begin _dataflow_plus_valid_130 <= 0; end if((_dataflow_plus_ready_130 || !_dataflow_plus_valid_130) && (_dataflow_minus_ready_88 && _dataflow_minus_ready_98)) begin _dataflow_plus_valid_130 <= _dataflow_minus_valid_88 && _dataflow_minus_valid_98; end if((_dataflow_plus_ready_131 || !_dataflow_plus_valid_131) && (_dataflow_plus_ready_89 && _dataflow_plus_ready_99) && (_dataflow_plus_valid_89 && _dataflow_plus_valid_99)) begin _dataflow_plus_data_131 <= _dataflow_plus_data_89 + _dataflow_plus_data_99; end if(_dataflow_plus_valid_131 && _dataflow_plus_ready_131) begin _dataflow_plus_valid_131 <= 0; end if((_dataflow_plus_ready_131 || !_dataflow_plus_valid_131) && (_dataflow_plus_ready_89 && _dataflow_plus_ready_99)) begin _dataflow_plus_valid_131 <= _dataflow_plus_valid_89 && _dataflow_plus_valid_99; end if((_dataflow_minus_ready_132 || !_dataflow_minus_valid_132) && (_dataflow_minus_ready_88 && _dataflow_minus_ready_98) && (_dataflow_minus_valid_88 && _dataflow_minus_valid_98)) begin _dataflow_minus_data_132 <= _dataflow_minus_data_88 - _dataflow_minus_data_98; end if(_dataflow_minus_valid_132 && _dataflow_minus_ready_132) begin _dataflow_minus_valid_132 <= 0; end if((_dataflow_minus_ready_132 || !_dataflow_minus_valid_132) && (_dataflow_minus_ready_88 && _dataflow_minus_ready_98)) begin _dataflow_minus_valid_132 <= _dataflow_minus_valid_88 && _dataflow_minus_valid_98; end if((_dataflow_minus_ready_133 || !_dataflow_minus_valid_133) && (_dataflow_plus_ready_89 && _dataflow_plus_ready_99) && (_dataflow_plus_valid_89 && _dataflow_plus_valid_99)) begin _dataflow_minus_data_133 <= _dataflow_plus_data_89 - _dataflow_plus_data_99; end if(_dataflow_minus_valid_133 && _dataflow_minus_ready_133) begin _dataflow_minus_valid_133 <= 0; end if((_dataflow_minus_ready_133 || !_dataflow_minus_valid_133) && (_dataflow_plus_ready_89 && _dataflow_plus_ready_99)) begin _dataflow_minus_valid_133 <= _dataflow_plus_valid_89 && _dataflow_plus_valid_99; end if((_dataflow_plus_ready_140 || !_dataflow_plus_valid_140) && (_dataflow_plus_ready_100 && _dataflow_plus_ready_110) && (_dataflow_plus_valid_100 && _dataflow_plus_valid_110)) begin _dataflow_plus_data_140 <= _dataflow_plus_data_100 + _dataflow_plus_data_110; end if(_dataflow_plus_valid_140 && _dataflow_plus_ready_140) begin _dataflow_plus_valid_140 <= 0; end if((_dataflow_plus_ready_140 || !_dataflow_plus_valid_140) && (_dataflow_plus_ready_100 && _dataflow_plus_ready_110)) begin _dataflow_plus_valid_140 <= _dataflow_plus_valid_100 && _dataflow_plus_valid_110; end if((_dataflow_plus_ready_141 || !_dataflow_plus_valid_141) && (_dataflow_plus_ready_101 && _dataflow_plus_ready_111) && (_dataflow_plus_valid_101 && _dataflow_plus_valid_111)) begin _dataflow_plus_data_141 <= _dataflow_plus_data_101 + _dataflow_plus_data_111; end if(_dataflow_plus_valid_141 && _dataflow_plus_ready_141) begin _dataflow_plus_valid_141 <= 0; end if((_dataflow_plus_ready_141 || !_dataflow_plus_valid_141) && (_dataflow_plus_ready_101 && _dataflow_plus_ready_111)) begin _dataflow_plus_valid_141 <= _dataflow_plus_valid_101 && _dataflow_plus_valid_111; end if((_dataflow_minus_ready_142 || !_dataflow_minus_valid_142) && (_dataflow_plus_ready_100 && _dataflow_plus_ready_110) && (_dataflow_plus_valid_100 && _dataflow_plus_valid_110)) begin _dataflow_minus_data_142 <= _dataflow_plus_data_100 - _dataflow_plus_data_110; end if(_dataflow_minus_valid_142 && _dataflow_minus_ready_142) begin _dataflow_minus_valid_142 <= 0; end if((_dataflow_minus_ready_142 || !_dataflow_minus_valid_142) && (_dataflow_plus_ready_100 && _dataflow_plus_ready_110)) begin _dataflow_minus_valid_142 <= _dataflow_plus_valid_100 && _dataflow_plus_valid_110; end if((_dataflow_minus_ready_143 || !_dataflow_minus_valid_143) && (_dataflow_plus_ready_101 && _dataflow_plus_ready_111) && (_dataflow_plus_valid_101 && _dataflow_plus_valid_111)) begin _dataflow_minus_data_143 <= _dataflow_plus_data_101 - _dataflow_plus_data_111; end if(_dataflow_minus_valid_143 && _dataflow_minus_ready_143) begin _dataflow_minus_valid_143 <= 0; end if((_dataflow_minus_ready_143 || !_dataflow_minus_valid_143) && (_dataflow_plus_ready_101 && _dataflow_plus_ready_111)) begin _dataflow_minus_valid_143 <= _dataflow_plus_valid_101 && _dataflow_plus_valid_111; end if((_dataflow__delay_ready_184 || !_dataflow__delay_valid_184) && _dataflow__delay_ready_183 && _dataflow__delay_valid_183) begin _dataflow__delay_data_184 <= _dataflow__delay_data_183; end if(_dataflow__delay_valid_184 && _dataflow__delay_ready_184) begin _dataflow__delay_valid_184 <= 0; end if((_dataflow__delay_ready_184 || !_dataflow__delay_valid_184) && _dataflow__delay_ready_183) begin _dataflow__delay_valid_184 <= _dataflow__delay_valid_183; end if((_dataflow__delay_ready_195 || !_dataflow__delay_valid_195) && _dataflow__delay_ready_194 && _dataflow__delay_valid_194) begin _dataflow__delay_data_195 <= _dataflow__delay_data_194; end if(_dataflow__delay_valid_195 && _dataflow__delay_ready_195) begin _dataflow__delay_valid_195 <= 0; end if((_dataflow__delay_ready_195 || !_dataflow__delay_valid_195) && _dataflow__delay_ready_194) begin _dataflow__delay_valid_195 <= _dataflow__delay_valid_194; end if((_dataflow__delay_ready_214 || !_dataflow__delay_valid_214) && _dataflow__delay_ready_213 && _dataflow__delay_valid_213) begin _dataflow__delay_data_214 <= _dataflow__delay_data_213; end if(_dataflow__delay_valid_214 && _dataflow__delay_ready_214) begin _dataflow__delay_valid_214 <= 0; end if((_dataflow__delay_ready_214 || !_dataflow__delay_valid_214) && _dataflow__delay_ready_213) begin _dataflow__delay_valid_214 <= _dataflow__delay_valid_213; end if((_dataflow__delay_ready_225 || !_dataflow__delay_valid_225) && _dataflow__delay_ready_224 && _dataflow__delay_valid_224) begin _dataflow__delay_data_225 <= _dataflow__delay_data_224; end if(_dataflow__delay_valid_225 && _dataflow__delay_ready_225) begin _dataflow__delay_valid_225 <= 0; end if((_dataflow__delay_ready_225 || !_dataflow__delay_valid_225) && _dataflow__delay_ready_224) begin _dataflow__delay_valid_225 <= _dataflow__delay_valid_224; end if((_dataflow__delay_ready_276 || !_dataflow__delay_valid_276) && _dataflow__delay_ready_275 && _dataflow__delay_valid_275) begin _dataflow__delay_data_276 <= _dataflow__delay_data_275; end if(_dataflow__delay_valid_276 && _dataflow__delay_ready_276) begin _dataflow__delay_valid_276 <= 0; end if((_dataflow__delay_ready_276 || !_dataflow__delay_valid_276) && _dataflow__delay_ready_275) begin _dataflow__delay_valid_276 <= _dataflow__delay_valid_275; end if((_dataflow__delay_ready_295 || !_dataflow__delay_valid_295) && _dataflow__delay_ready_294 && _dataflow__delay_valid_294) begin _dataflow__delay_data_295 <= _dataflow__delay_data_294; end if(_dataflow__delay_valid_295 && _dataflow__delay_ready_295) begin _dataflow__delay_valid_295 <= 0; end if((_dataflow__delay_ready_295 || !_dataflow__delay_valid_295) && _dataflow__delay_ready_294) begin _dataflow__delay_valid_295 <= _dataflow__delay_valid_294; end if((_dataflow__delay_ready_311 || !_dataflow__delay_valid_311) && _dataflow__delay_ready_310 && _dataflow__delay_valid_310) begin _dataflow__delay_data_311 <= _dataflow__delay_data_310; end if(_dataflow__delay_valid_311 && _dataflow__delay_ready_311) begin _dataflow__delay_valid_311 <= 0; end if((_dataflow__delay_ready_311 || !_dataflow__delay_valid_311) && _dataflow__delay_ready_310) begin _dataflow__delay_valid_311 <= _dataflow__delay_valid_310; end if((_dataflow__delay_ready_335 || !_dataflow__delay_valid_335) && _dataflow__delay_ready_334 && _dataflow__delay_valid_334) begin _dataflow__delay_data_335 <= _dataflow__delay_data_334; end if(_dataflow__delay_valid_335 && _dataflow__delay_ready_335) begin _dataflow__delay_valid_335 <= 0; end if((_dataflow__delay_ready_335 || !_dataflow__delay_valid_335) && _dataflow__delay_ready_334) begin _dataflow__delay_valid_335 <= _dataflow__delay_valid_334; end if(_dataflow_times_ready_134 || !_dataflow_times_valid_134) begin _dataflow_times_mul_odata_reg_134 <= _dataflow_times_mul_odata_134 >>> 8; end if(_dataflow_times_ready_134 || !_dataflow_times_valid_134) begin _dataflow_times_mul_valid_reg_134 <= _dataflow_times_mul_ovalid_134; end if(_dataflow_times_ready_135 || !_dataflow_times_valid_135) begin _dataflow_times_mul_odata_reg_135 <= _dataflow_times_mul_odata_135 >>> 8; end if(_dataflow_times_ready_135 || !_dataflow_times_valid_135) begin _dataflow_times_mul_valid_reg_135 <= _dataflow_times_mul_ovalid_135; end if(_dataflow_times_ready_136 || !_dataflow_times_valid_136) begin _dataflow_times_mul_odata_reg_136 <= _dataflow_times_mul_odata_136 >>> 8; end if(_dataflow_times_ready_136 || !_dataflow_times_valid_136) begin _dataflow_times_mul_valid_reg_136 <= _dataflow_times_mul_ovalid_136; end if(_dataflow_times_ready_137 || !_dataflow_times_valid_137) begin _dataflow_times_mul_odata_reg_137 <= _dataflow_times_mul_odata_137 >>> 8; end if(_dataflow_times_ready_137 || !_dataflow_times_valid_137) begin _dataflow_times_mul_valid_reg_137 <= _dataflow_times_mul_ovalid_137; end if(_dataflow_times_ready_144 || !_dataflow_times_valid_144) begin _dataflow_times_mul_odata_reg_144 <= _dataflow_times_mul_odata_144 >>> 8; end if(_dataflow_times_ready_144 || !_dataflow_times_valid_144) begin _dataflow_times_mul_valid_reg_144 <= _dataflow_times_mul_ovalid_144; end if(_dataflow_times_ready_145 || !_dataflow_times_valid_145) begin _dataflow_times_mul_odata_reg_145 <= _dataflow_times_mul_odata_145 >>> 8; end if(_dataflow_times_ready_145 || !_dataflow_times_valid_145) begin _dataflow_times_mul_valid_reg_145 <= _dataflow_times_mul_ovalid_145; end if(_dataflow_times_ready_146 || !_dataflow_times_valid_146) begin _dataflow_times_mul_odata_reg_146 <= _dataflow_times_mul_odata_146 >>> 8; end if(_dataflow_times_ready_146 || !_dataflow_times_valid_146) begin _dataflow_times_mul_valid_reg_146 <= _dataflow_times_mul_ovalid_146; end if(_dataflow_times_ready_147 || !_dataflow_times_valid_147) begin _dataflow_times_mul_odata_reg_147 <= _dataflow_times_mul_odata_147 >>> 8; end if(_dataflow_times_ready_147 || !_dataflow_times_valid_147) begin _dataflow_times_mul_valid_reg_147 <= _dataflow_times_mul_ovalid_147; end if((_dataflow__delay_ready_277 || !_dataflow__delay_valid_277) && _dataflow__delay_ready_276 && _dataflow__delay_valid_276) begin _dataflow__delay_data_277 <= _dataflow__delay_data_276; end if(_dataflow__delay_valid_277 && _dataflow__delay_ready_277) begin _dataflow__delay_valid_277 <= 0; end if((_dataflow__delay_ready_277 || !_dataflow__delay_valid_277) && _dataflow__delay_ready_276) begin _dataflow__delay_valid_277 <= _dataflow__delay_valid_276; end if((_dataflow__delay_ready_296 || !_dataflow__delay_valid_296) && _dataflow__delay_ready_295 && _dataflow__delay_valid_295) begin _dataflow__delay_data_296 <= _dataflow__delay_data_295; end if(_dataflow__delay_valid_296 && _dataflow__delay_ready_296) begin _dataflow__delay_valid_296 <= 0; end if((_dataflow__delay_ready_296 || !_dataflow__delay_valid_296) && _dataflow__delay_ready_295) begin _dataflow__delay_valid_296 <= _dataflow__delay_valid_295; end if((_dataflow__delay_ready_312 || !_dataflow__delay_valid_312) && _dataflow__delay_ready_311 && _dataflow__delay_valid_311) begin _dataflow__delay_data_312 <= _dataflow__delay_data_311; end if(_dataflow__delay_valid_312 && _dataflow__delay_ready_312) begin _dataflow__delay_valid_312 <= 0; end if((_dataflow__delay_ready_312 || !_dataflow__delay_valid_312) && _dataflow__delay_ready_311) begin _dataflow__delay_valid_312 <= _dataflow__delay_valid_311; end if((_dataflow__delay_ready_336 || !_dataflow__delay_valid_336) && _dataflow__delay_ready_335 && _dataflow__delay_valid_335) begin _dataflow__delay_data_336 <= _dataflow__delay_data_335; end if(_dataflow__delay_valid_336 && _dataflow__delay_ready_336) begin _dataflow__delay_valid_336 <= 0; end if((_dataflow__delay_ready_336 || !_dataflow__delay_valid_336) && _dataflow__delay_ready_335) begin _dataflow__delay_valid_336 <= _dataflow__delay_valid_335; end if((_dataflow__delay_ready_352 || !_dataflow__delay_valid_352) && _dataflow_minus_ready_128 && _dataflow_minus_valid_128) begin _dataflow__delay_data_352 <= _dataflow_minus_data_128; end if(_dataflow__delay_valid_352 && _dataflow__delay_ready_352) begin _dataflow__delay_valid_352 <= 0; end if((_dataflow__delay_ready_352 || !_dataflow__delay_valid_352) && _dataflow_minus_ready_128) begin _dataflow__delay_valid_352 <= _dataflow_minus_valid_128; end if((_dataflow__delay_ready_368 || !_dataflow__delay_valid_368) && _dataflow_plus_ready_129 && _dataflow_plus_valid_129) begin _dataflow__delay_data_368 <= _dataflow_plus_data_129; end if(_dataflow__delay_valid_368 && _dataflow__delay_ready_368) begin _dataflow__delay_valid_368 <= 0; end if((_dataflow__delay_ready_368 || !_dataflow__delay_valid_368) && _dataflow_plus_ready_129) begin _dataflow__delay_valid_368 <= _dataflow_plus_valid_129; end if((_dataflow__delay_ready_384 || !_dataflow__delay_valid_384) && _dataflow_plus_ready_130 && _dataflow_plus_valid_130) begin _dataflow__delay_data_384 <= _dataflow_plus_data_130; end if(_dataflow__delay_valid_384 && _dataflow__delay_ready_384) begin _dataflow__delay_valid_384 <= 0; end if((_dataflow__delay_ready_384 || !_dataflow__delay_valid_384) && _dataflow_plus_ready_130) begin _dataflow__delay_valid_384 <= _dataflow_plus_valid_130; end if((_dataflow__delay_ready_400 || !_dataflow__delay_valid_400) && _dataflow_plus_ready_131 && _dataflow_plus_valid_131) begin _dataflow__delay_data_400 <= _dataflow_plus_data_131; end if(_dataflow__delay_valid_400 && _dataflow__delay_ready_400) begin _dataflow__delay_valid_400 <= 0; end if((_dataflow__delay_ready_400 || !_dataflow__delay_valid_400) && _dataflow_plus_ready_131) begin _dataflow__delay_valid_400 <= _dataflow_plus_valid_131; end if((_dataflow__delay_ready_432 || !_dataflow__delay_valid_432) && _dataflow_plus_ready_140 && _dataflow_plus_valid_140) begin _dataflow__delay_data_432 <= _dataflow_plus_data_140; end if(_dataflow__delay_valid_432 && _dataflow__delay_ready_432) begin _dataflow__delay_valid_432 <= 0; end if((_dataflow__delay_ready_432 || !_dataflow__delay_valid_432) && _dataflow_plus_ready_140) begin _dataflow__delay_valid_432 <= _dataflow_plus_valid_140; end if((_dataflow__delay_ready_448 || !_dataflow__delay_valid_448) && _dataflow_plus_ready_141 && _dataflow_plus_valid_141) begin _dataflow__delay_data_448 <= _dataflow_plus_data_141; end if(_dataflow__delay_valid_448 && _dataflow__delay_ready_448) begin _dataflow__delay_valid_448 <= 0; end if((_dataflow__delay_ready_448 || !_dataflow__delay_valid_448) && _dataflow_plus_ready_141) begin _dataflow__delay_valid_448 <= _dataflow_plus_valid_141; end if((_dataflow__delay_ready_278 || !_dataflow__delay_valid_278) && _dataflow__delay_ready_277 && _dataflow__delay_valid_277) begin _dataflow__delay_data_278 <= _dataflow__delay_data_277; end if(_dataflow__delay_valid_278 && _dataflow__delay_ready_278) begin _dataflow__delay_valid_278 <= 0; end if((_dataflow__delay_ready_278 || !_dataflow__delay_valid_278) && _dataflow__delay_ready_277) begin _dataflow__delay_valid_278 <= _dataflow__delay_valid_277; end if((_dataflow__delay_ready_297 || !_dataflow__delay_valid_297) && _dataflow__delay_ready_296 && _dataflow__delay_valid_296) begin _dataflow__delay_data_297 <= _dataflow__delay_data_296; end if(_dataflow__delay_valid_297 && _dataflow__delay_ready_297) begin _dataflow__delay_valid_297 <= 0; end if((_dataflow__delay_ready_297 || !_dataflow__delay_valid_297) && _dataflow__delay_ready_296) begin _dataflow__delay_valid_297 <= _dataflow__delay_valid_296; end if((_dataflow__delay_ready_313 || !_dataflow__delay_valid_313) && _dataflow__delay_ready_312 && _dataflow__delay_valid_312) begin _dataflow__delay_data_313 <= _dataflow__delay_data_312; end if(_dataflow__delay_valid_313 && _dataflow__delay_ready_313) begin _dataflow__delay_valid_313 <= 0; end if((_dataflow__delay_ready_313 || !_dataflow__delay_valid_313) && _dataflow__delay_ready_312) begin _dataflow__delay_valid_313 <= _dataflow__delay_valid_312; end if((_dataflow__delay_ready_337 || !_dataflow__delay_valid_337) && _dataflow__delay_ready_336 && _dataflow__delay_valid_336) begin _dataflow__delay_data_337 <= _dataflow__delay_data_336; end if(_dataflow__delay_valid_337 && _dataflow__delay_ready_337) begin _dataflow__delay_valid_337 <= 0; end if((_dataflow__delay_ready_337 || !_dataflow__delay_valid_337) && _dataflow__delay_ready_336) begin _dataflow__delay_valid_337 <= _dataflow__delay_valid_336; end if((_dataflow__delay_ready_353 || !_dataflow__delay_valid_353) && _dataflow__delay_ready_352 && _dataflow__delay_valid_352) begin _dataflow__delay_data_353 <= _dataflow__delay_data_352; end if(_dataflow__delay_valid_353 && _dataflow__delay_ready_353) begin _dataflow__delay_valid_353 <= 0; end if((_dataflow__delay_ready_353 || !_dataflow__delay_valid_353) && _dataflow__delay_ready_352) begin _dataflow__delay_valid_353 <= _dataflow__delay_valid_352; end if((_dataflow__delay_ready_369 || !_dataflow__delay_valid_369) && _dataflow__delay_ready_368 && _dataflow__delay_valid_368) begin _dataflow__delay_data_369 <= _dataflow__delay_data_368; end if(_dataflow__delay_valid_369 && _dataflow__delay_ready_369) begin _dataflow__delay_valid_369 <= 0; end if((_dataflow__delay_ready_369 || !_dataflow__delay_valid_369) && _dataflow__delay_ready_368) begin _dataflow__delay_valid_369 <= _dataflow__delay_valid_368; end if((_dataflow__delay_ready_385 || !_dataflow__delay_valid_385) && _dataflow__delay_ready_384 && _dataflow__delay_valid_384) begin _dataflow__delay_data_385 <= _dataflow__delay_data_384; end if(_dataflow__delay_valid_385 && _dataflow__delay_ready_385) begin _dataflow__delay_valid_385 <= 0; end if((_dataflow__delay_ready_385 || !_dataflow__delay_valid_385) && _dataflow__delay_ready_384) begin _dataflow__delay_valid_385 <= _dataflow__delay_valid_384; end if((_dataflow__delay_ready_401 || !_dataflow__delay_valid_401) && _dataflow__delay_ready_400 && _dataflow__delay_valid_400) begin _dataflow__delay_data_401 <= _dataflow__delay_data_400; end if(_dataflow__delay_valid_401 && _dataflow__delay_ready_401) begin _dataflow__delay_valid_401 <= 0; end if((_dataflow__delay_ready_401 || !_dataflow__delay_valid_401) && _dataflow__delay_ready_400) begin _dataflow__delay_valid_401 <= _dataflow__delay_valid_400; end if((_dataflow__delay_ready_433 || !_dataflow__delay_valid_433) && _dataflow__delay_ready_432 && _dataflow__delay_valid_432) begin _dataflow__delay_data_433 <= _dataflow__delay_data_432; end if(_dataflow__delay_valid_433 && _dataflow__delay_ready_433) begin _dataflow__delay_valid_433 <= 0; end if((_dataflow__delay_ready_433 || !_dataflow__delay_valid_433) && _dataflow__delay_ready_432) begin _dataflow__delay_valid_433 <= _dataflow__delay_valid_432; end if((_dataflow__delay_ready_449 || !_dataflow__delay_valid_449) && _dataflow__delay_ready_448 && _dataflow__delay_valid_448) begin _dataflow__delay_data_449 <= _dataflow__delay_data_448; end if(_dataflow__delay_valid_449 && _dataflow__delay_ready_449) begin _dataflow__delay_valid_449 <= 0; end if((_dataflow__delay_ready_449 || !_dataflow__delay_valid_449) && _dataflow__delay_ready_448) begin _dataflow__delay_valid_449 <= _dataflow__delay_valid_448; end if((_dataflow__delay_ready_279 || !_dataflow__delay_valid_279) && _dataflow__delay_ready_278 && _dataflow__delay_valid_278) begin _dataflow__delay_data_279 <= _dataflow__delay_data_278; end if(_dataflow__delay_valid_279 && _dataflow__delay_ready_279) begin _dataflow__delay_valid_279 <= 0; end if((_dataflow__delay_ready_279 || !_dataflow__delay_valid_279) && _dataflow__delay_ready_278) begin _dataflow__delay_valid_279 <= _dataflow__delay_valid_278; end if((_dataflow__delay_ready_298 || !_dataflow__delay_valid_298) && _dataflow__delay_ready_297 && _dataflow__delay_valid_297) begin _dataflow__delay_data_298 <= _dataflow__delay_data_297; end if(_dataflow__delay_valid_298 && _dataflow__delay_ready_298) begin _dataflow__delay_valid_298 <= 0; end if((_dataflow__delay_ready_298 || !_dataflow__delay_valid_298) && _dataflow__delay_ready_297) begin _dataflow__delay_valid_298 <= _dataflow__delay_valid_297; end if((_dataflow__delay_ready_314 || !_dataflow__delay_valid_314) && _dataflow__delay_ready_313 && _dataflow__delay_valid_313) begin _dataflow__delay_data_314 <= _dataflow__delay_data_313; end if(_dataflow__delay_valid_314 && _dataflow__delay_ready_314) begin _dataflow__delay_valid_314 <= 0; end if((_dataflow__delay_ready_314 || !_dataflow__delay_valid_314) && _dataflow__delay_ready_313) begin _dataflow__delay_valid_314 <= _dataflow__delay_valid_313; end if((_dataflow__delay_ready_338 || !_dataflow__delay_valid_338) && _dataflow__delay_ready_337 && _dataflow__delay_valid_337) begin _dataflow__delay_data_338 <= _dataflow__delay_data_337; end if(_dataflow__delay_valid_338 && _dataflow__delay_ready_338) begin _dataflow__delay_valid_338 <= 0; end if((_dataflow__delay_ready_338 || !_dataflow__delay_valid_338) && _dataflow__delay_ready_337) begin _dataflow__delay_valid_338 <= _dataflow__delay_valid_337; end if((_dataflow__delay_ready_354 || !_dataflow__delay_valid_354) && _dataflow__delay_ready_353 && _dataflow__delay_valid_353) begin _dataflow__delay_data_354 <= _dataflow__delay_data_353; end if(_dataflow__delay_valid_354 && _dataflow__delay_ready_354) begin _dataflow__delay_valid_354 <= 0; end if((_dataflow__delay_ready_354 || !_dataflow__delay_valid_354) && _dataflow__delay_ready_353) begin _dataflow__delay_valid_354 <= _dataflow__delay_valid_353; end if((_dataflow__delay_ready_370 || !_dataflow__delay_valid_370) && _dataflow__delay_ready_369 && _dataflow__delay_valid_369) begin _dataflow__delay_data_370 <= _dataflow__delay_data_369; end if(_dataflow__delay_valid_370 && _dataflow__delay_ready_370) begin _dataflow__delay_valid_370 <= 0; end if((_dataflow__delay_ready_370 || !_dataflow__delay_valid_370) && _dataflow__delay_ready_369) begin _dataflow__delay_valid_370 <= _dataflow__delay_valid_369; end if((_dataflow__delay_ready_386 || !_dataflow__delay_valid_386) && _dataflow__delay_ready_385 && _dataflow__delay_valid_385) begin _dataflow__delay_data_386 <= _dataflow__delay_data_385; end if(_dataflow__delay_valid_386 && _dataflow__delay_ready_386) begin _dataflow__delay_valid_386 <= 0; end if((_dataflow__delay_ready_386 || !_dataflow__delay_valid_386) && _dataflow__delay_ready_385) begin _dataflow__delay_valid_386 <= _dataflow__delay_valid_385; end if((_dataflow__delay_ready_402 || !_dataflow__delay_valid_402) && _dataflow__delay_ready_401 && _dataflow__delay_valid_401) begin _dataflow__delay_data_402 <= _dataflow__delay_data_401; end if(_dataflow__delay_valid_402 && _dataflow__delay_ready_402) begin _dataflow__delay_valid_402 <= 0; end if((_dataflow__delay_ready_402 || !_dataflow__delay_valid_402) && _dataflow__delay_ready_401) begin _dataflow__delay_valid_402 <= _dataflow__delay_valid_401; end if((_dataflow__delay_ready_434 || !_dataflow__delay_valid_434) && _dataflow__delay_ready_433 && _dataflow__delay_valid_433) begin _dataflow__delay_data_434 <= _dataflow__delay_data_433; end if(_dataflow__delay_valid_434 && _dataflow__delay_ready_434) begin _dataflow__delay_valid_434 <= 0; end if((_dataflow__delay_ready_434 || !_dataflow__delay_valid_434) && _dataflow__delay_ready_433) begin _dataflow__delay_valid_434 <= _dataflow__delay_valid_433; end if((_dataflow__delay_ready_450 || !_dataflow__delay_valid_450) && _dataflow__delay_ready_449 && _dataflow__delay_valid_449) begin _dataflow__delay_data_450 <= _dataflow__delay_data_449; end if(_dataflow__delay_valid_450 && _dataflow__delay_ready_450) begin _dataflow__delay_valid_450 <= 0; end if((_dataflow__delay_ready_450 || !_dataflow__delay_valid_450) && _dataflow__delay_ready_449) begin _dataflow__delay_valid_450 <= _dataflow__delay_valid_449; end if((_dataflow__delay_ready_280 || !_dataflow__delay_valid_280) && _dataflow__delay_ready_279 && _dataflow__delay_valid_279) begin _dataflow__delay_data_280 <= _dataflow__delay_data_279; end if(_dataflow__delay_valid_280 && _dataflow__delay_ready_280) begin _dataflow__delay_valid_280 <= 0; end if((_dataflow__delay_ready_280 || !_dataflow__delay_valid_280) && _dataflow__delay_ready_279) begin _dataflow__delay_valid_280 <= _dataflow__delay_valid_279; end if((_dataflow__delay_ready_299 || !_dataflow__delay_valid_299) && _dataflow__delay_ready_298 && _dataflow__delay_valid_298) begin _dataflow__delay_data_299 <= _dataflow__delay_data_298; end if(_dataflow__delay_valid_299 && _dataflow__delay_ready_299) begin _dataflow__delay_valid_299 <= 0; end if((_dataflow__delay_ready_299 || !_dataflow__delay_valid_299) && _dataflow__delay_ready_298) begin _dataflow__delay_valid_299 <= _dataflow__delay_valid_298; end if((_dataflow__delay_ready_315 || !_dataflow__delay_valid_315) && _dataflow__delay_ready_314 && _dataflow__delay_valid_314) begin _dataflow__delay_data_315 <= _dataflow__delay_data_314; end if(_dataflow__delay_valid_315 && _dataflow__delay_ready_315) begin _dataflow__delay_valid_315 <= 0; end if((_dataflow__delay_ready_315 || !_dataflow__delay_valid_315) && _dataflow__delay_ready_314) begin _dataflow__delay_valid_315 <= _dataflow__delay_valid_314; end if((_dataflow__delay_ready_339 || !_dataflow__delay_valid_339) && _dataflow__delay_ready_338 && _dataflow__delay_valid_338) begin _dataflow__delay_data_339 <= _dataflow__delay_data_338; end if(_dataflow__delay_valid_339 && _dataflow__delay_ready_339) begin _dataflow__delay_valid_339 <= 0; end if((_dataflow__delay_ready_339 || !_dataflow__delay_valid_339) && _dataflow__delay_ready_338) begin _dataflow__delay_valid_339 <= _dataflow__delay_valid_338; end if((_dataflow__delay_ready_355 || !_dataflow__delay_valid_355) && _dataflow__delay_ready_354 && _dataflow__delay_valid_354) begin _dataflow__delay_data_355 <= _dataflow__delay_data_354; end if(_dataflow__delay_valid_355 && _dataflow__delay_ready_355) begin _dataflow__delay_valid_355 <= 0; end if((_dataflow__delay_ready_355 || !_dataflow__delay_valid_355) && _dataflow__delay_ready_354) begin _dataflow__delay_valid_355 <= _dataflow__delay_valid_354; end if((_dataflow__delay_ready_371 || !_dataflow__delay_valid_371) && _dataflow__delay_ready_370 && _dataflow__delay_valid_370) begin _dataflow__delay_data_371 <= _dataflow__delay_data_370; end if(_dataflow__delay_valid_371 && _dataflow__delay_ready_371) begin _dataflow__delay_valid_371 <= 0; end if((_dataflow__delay_ready_371 || !_dataflow__delay_valid_371) && _dataflow__delay_ready_370) begin _dataflow__delay_valid_371 <= _dataflow__delay_valid_370; end if((_dataflow__delay_ready_387 || !_dataflow__delay_valid_387) && _dataflow__delay_ready_386 && _dataflow__delay_valid_386) begin _dataflow__delay_data_387 <= _dataflow__delay_data_386; end if(_dataflow__delay_valid_387 && _dataflow__delay_ready_387) begin _dataflow__delay_valid_387 <= 0; end if((_dataflow__delay_ready_387 || !_dataflow__delay_valid_387) && _dataflow__delay_ready_386) begin _dataflow__delay_valid_387 <= _dataflow__delay_valid_386; end if((_dataflow__delay_ready_403 || !_dataflow__delay_valid_403) && _dataflow__delay_ready_402 && _dataflow__delay_valid_402) begin _dataflow__delay_data_403 <= _dataflow__delay_data_402; end if(_dataflow__delay_valid_403 && _dataflow__delay_ready_403) begin _dataflow__delay_valid_403 <= 0; end if((_dataflow__delay_ready_403 || !_dataflow__delay_valid_403) && _dataflow__delay_ready_402) begin _dataflow__delay_valid_403 <= _dataflow__delay_valid_402; end if((_dataflow__delay_ready_435 || !_dataflow__delay_valid_435) && _dataflow__delay_ready_434 && _dataflow__delay_valid_434) begin _dataflow__delay_data_435 <= _dataflow__delay_data_434; end if(_dataflow__delay_valid_435 && _dataflow__delay_ready_435) begin _dataflow__delay_valid_435 <= 0; end if((_dataflow__delay_ready_435 || !_dataflow__delay_valid_435) && _dataflow__delay_ready_434) begin _dataflow__delay_valid_435 <= _dataflow__delay_valid_434; end if((_dataflow__delay_ready_451 || !_dataflow__delay_valid_451) && _dataflow__delay_ready_450 && _dataflow__delay_valid_450) begin _dataflow__delay_data_451 <= _dataflow__delay_data_450; end if(_dataflow__delay_valid_451 && _dataflow__delay_ready_451) begin _dataflow__delay_valid_451 <= 0; end if((_dataflow__delay_ready_451 || !_dataflow__delay_valid_451) && _dataflow__delay_ready_450) begin _dataflow__delay_valid_451 <= _dataflow__delay_valid_450; end if((_dataflow__delay_ready_281 || !_dataflow__delay_valid_281) && _dataflow__delay_ready_280 && _dataflow__delay_valid_280) begin _dataflow__delay_data_281 <= _dataflow__delay_data_280; end if(_dataflow__delay_valid_281 && _dataflow__delay_ready_281) begin _dataflow__delay_valid_281 <= 0; end if((_dataflow__delay_ready_281 || !_dataflow__delay_valid_281) && _dataflow__delay_ready_280) begin _dataflow__delay_valid_281 <= _dataflow__delay_valid_280; end if((_dataflow__delay_ready_300 || !_dataflow__delay_valid_300) && _dataflow__delay_ready_299 && _dataflow__delay_valid_299) begin _dataflow__delay_data_300 <= _dataflow__delay_data_299; end if(_dataflow__delay_valid_300 && _dataflow__delay_ready_300) begin _dataflow__delay_valid_300 <= 0; end if((_dataflow__delay_ready_300 || !_dataflow__delay_valid_300) && _dataflow__delay_ready_299) begin _dataflow__delay_valid_300 <= _dataflow__delay_valid_299; end if((_dataflow__delay_ready_316 || !_dataflow__delay_valid_316) && _dataflow__delay_ready_315 && _dataflow__delay_valid_315) begin _dataflow__delay_data_316 <= _dataflow__delay_data_315; end if(_dataflow__delay_valid_316 && _dataflow__delay_ready_316) begin _dataflow__delay_valid_316 <= 0; end if((_dataflow__delay_ready_316 || !_dataflow__delay_valid_316) && _dataflow__delay_ready_315) begin _dataflow__delay_valid_316 <= _dataflow__delay_valid_315; end if((_dataflow__delay_ready_340 || !_dataflow__delay_valid_340) && _dataflow__delay_ready_339 && _dataflow__delay_valid_339) begin _dataflow__delay_data_340 <= _dataflow__delay_data_339; end if(_dataflow__delay_valid_340 && _dataflow__delay_ready_340) begin _dataflow__delay_valid_340 <= 0; end if((_dataflow__delay_ready_340 || !_dataflow__delay_valid_340) && _dataflow__delay_ready_339) begin _dataflow__delay_valid_340 <= _dataflow__delay_valid_339; end if((_dataflow__delay_ready_356 || !_dataflow__delay_valid_356) && _dataflow__delay_ready_355 && _dataflow__delay_valid_355) begin _dataflow__delay_data_356 <= _dataflow__delay_data_355; end if(_dataflow__delay_valid_356 && _dataflow__delay_ready_356) begin _dataflow__delay_valid_356 <= 0; end if((_dataflow__delay_ready_356 || !_dataflow__delay_valid_356) && _dataflow__delay_ready_355) begin _dataflow__delay_valid_356 <= _dataflow__delay_valid_355; end if((_dataflow__delay_ready_372 || !_dataflow__delay_valid_372) && _dataflow__delay_ready_371 && _dataflow__delay_valid_371) begin _dataflow__delay_data_372 <= _dataflow__delay_data_371; end if(_dataflow__delay_valid_372 && _dataflow__delay_ready_372) begin _dataflow__delay_valid_372 <= 0; end if((_dataflow__delay_ready_372 || !_dataflow__delay_valid_372) && _dataflow__delay_ready_371) begin _dataflow__delay_valid_372 <= _dataflow__delay_valid_371; end if((_dataflow__delay_ready_388 || !_dataflow__delay_valid_388) && _dataflow__delay_ready_387 && _dataflow__delay_valid_387) begin _dataflow__delay_data_388 <= _dataflow__delay_data_387; end if(_dataflow__delay_valid_388 && _dataflow__delay_ready_388) begin _dataflow__delay_valid_388 <= 0; end if((_dataflow__delay_ready_388 || !_dataflow__delay_valid_388) && _dataflow__delay_ready_387) begin _dataflow__delay_valid_388 <= _dataflow__delay_valid_387; end if((_dataflow__delay_ready_404 || !_dataflow__delay_valid_404) && _dataflow__delay_ready_403 && _dataflow__delay_valid_403) begin _dataflow__delay_data_404 <= _dataflow__delay_data_403; end if(_dataflow__delay_valid_404 && _dataflow__delay_ready_404) begin _dataflow__delay_valid_404 <= 0; end if((_dataflow__delay_ready_404 || !_dataflow__delay_valid_404) && _dataflow__delay_ready_403) begin _dataflow__delay_valid_404 <= _dataflow__delay_valid_403; end if((_dataflow__delay_ready_436 || !_dataflow__delay_valid_436) && _dataflow__delay_ready_435 && _dataflow__delay_valid_435) begin _dataflow__delay_data_436 <= _dataflow__delay_data_435; end if(_dataflow__delay_valid_436 && _dataflow__delay_ready_436) begin _dataflow__delay_valid_436 <= 0; end if((_dataflow__delay_ready_436 || !_dataflow__delay_valid_436) && _dataflow__delay_ready_435) begin _dataflow__delay_valid_436 <= _dataflow__delay_valid_435; end if((_dataflow__delay_ready_452 || !_dataflow__delay_valid_452) && _dataflow__delay_ready_451 && _dataflow__delay_valid_451) begin _dataflow__delay_data_452 <= _dataflow__delay_data_451; end if(_dataflow__delay_valid_452 && _dataflow__delay_ready_452) begin _dataflow__delay_valid_452 <= 0; end if((_dataflow__delay_ready_452 || !_dataflow__delay_valid_452) && _dataflow__delay_ready_451) begin _dataflow__delay_valid_452 <= _dataflow__delay_valid_451; end if((_dataflow__delay_ready_282 || !_dataflow__delay_valid_282) && _dataflow__delay_ready_281 && _dataflow__delay_valid_281) begin _dataflow__delay_data_282 <= _dataflow__delay_data_281; end if(_dataflow__delay_valid_282 && _dataflow__delay_ready_282) begin _dataflow__delay_valid_282 <= 0; end if((_dataflow__delay_ready_282 || !_dataflow__delay_valid_282) && _dataflow__delay_ready_281) begin _dataflow__delay_valid_282 <= _dataflow__delay_valid_281; end if((_dataflow__delay_ready_301 || !_dataflow__delay_valid_301) && _dataflow__delay_ready_300 && _dataflow__delay_valid_300) begin _dataflow__delay_data_301 <= _dataflow__delay_data_300; end if(_dataflow__delay_valid_301 && _dataflow__delay_ready_301) begin _dataflow__delay_valid_301 <= 0; end if((_dataflow__delay_ready_301 || !_dataflow__delay_valid_301) && _dataflow__delay_ready_300) begin _dataflow__delay_valid_301 <= _dataflow__delay_valid_300; end if((_dataflow__delay_ready_317 || !_dataflow__delay_valid_317) && _dataflow__delay_ready_316 && _dataflow__delay_valid_316) begin _dataflow__delay_data_317 <= _dataflow__delay_data_316; end if(_dataflow__delay_valid_317 && _dataflow__delay_ready_317) begin _dataflow__delay_valid_317 <= 0; end if((_dataflow__delay_ready_317 || !_dataflow__delay_valid_317) && _dataflow__delay_ready_316) begin _dataflow__delay_valid_317 <= _dataflow__delay_valid_316; end if((_dataflow__delay_ready_341 || !_dataflow__delay_valid_341) && _dataflow__delay_ready_340 && _dataflow__delay_valid_340) begin _dataflow__delay_data_341 <= _dataflow__delay_data_340; end if(_dataflow__delay_valid_341 && _dataflow__delay_ready_341) begin _dataflow__delay_valid_341 <= 0; end if((_dataflow__delay_ready_341 || !_dataflow__delay_valid_341) && _dataflow__delay_ready_340) begin _dataflow__delay_valid_341 <= _dataflow__delay_valid_340; end if((_dataflow__delay_ready_357 || !_dataflow__delay_valid_357) && _dataflow__delay_ready_356 && _dataflow__delay_valid_356) begin _dataflow__delay_data_357 <= _dataflow__delay_data_356; end if(_dataflow__delay_valid_357 && _dataflow__delay_ready_357) begin _dataflow__delay_valid_357 <= 0; end if((_dataflow__delay_ready_357 || !_dataflow__delay_valid_357) && _dataflow__delay_ready_356) begin _dataflow__delay_valid_357 <= _dataflow__delay_valid_356; end if((_dataflow__delay_ready_373 || !_dataflow__delay_valid_373) && _dataflow__delay_ready_372 && _dataflow__delay_valid_372) begin _dataflow__delay_data_373 <= _dataflow__delay_data_372; end if(_dataflow__delay_valid_373 && _dataflow__delay_ready_373) begin _dataflow__delay_valid_373 <= 0; end if((_dataflow__delay_ready_373 || !_dataflow__delay_valid_373) && _dataflow__delay_ready_372) begin _dataflow__delay_valid_373 <= _dataflow__delay_valid_372; end if((_dataflow__delay_ready_389 || !_dataflow__delay_valid_389) && _dataflow__delay_ready_388 && _dataflow__delay_valid_388) begin _dataflow__delay_data_389 <= _dataflow__delay_data_388; end if(_dataflow__delay_valid_389 && _dataflow__delay_ready_389) begin _dataflow__delay_valid_389 <= 0; end if((_dataflow__delay_ready_389 || !_dataflow__delay_valid_389) && _dataflow__delay_ready_388) begin _dataflow__delay_valid_389 <= _dataflow__delay_valid_388; end if((_dataflow__delay_ready_405 || !_dataflow__delay_valid_405) && _dataflow__delay_ready_404 && _dataflow__delay_valid_404) begin _dataflow__delay_data_405 <= _dataflow__delay_data_404; end if(_dataflow__delay_valid_405 && _dataflow__delay_ready_405) begin _dataflow__delay_valid_405 <= 0; end if((_dataflow__delay_ready_405 || !_dataflow__delay_valid_405) && _dataflow__delay_ready_404) begin _dataflow__delay_valid_405 <= _dataflow__delay_valid_404; end if((_dataflow__delay_ready_437 || !_dataflow__delay_valid_437) && _dataflow__delay_ready_436 && _dataflow__delay_valid_436) begin _dataflow__delay_data_437 <= _dataflow__delay_data_436; end if(_dataflow__delay_valid_437 && _dataflow__delay_ready_437) begin _dataflow__delay_valid_437 <= 0; end if((_dataflow__delay_ready_437 || !_dataflow__delay_valid_437) && _dataflow__delay_ready_436) begin _dataflow__delay_valid_437 <= _dataflow__delay_valid_436; end if((_dataflow__delay_ready_453 || !_dataflow__delay_valid_453) && _dataflow__delay_ready_452 && _dataflow__delay_valid_452) begin _dataflow__delay_data_453 <= _dataflow__delay_data_452; end if(_dataflow__delay_valid_453 && _dataflow__delay_ready_453) begin _dataflow__delay_valid_453 <= 0; end if((_dataflow__delay_ready_453 || !_dataflow__delay_valid_453) && _dataflow__delay_ready_452) begin _dataflow__delay_valid_453 <= _dataflow__delay_valid_452; end if((_dataflow_minus_ready_108 || !_dataflow_minus_valid_108) && (_dataflow_times_ready_104 && _dataflow_times_ready_105) && (_dataflow_times_valid_104 && _dataflow_times_valid_105)) begin _dataflow_minus_data_108 <= _dataflow_times_data_104 - _dataflow_times_data_105; end if(_dataflow_minus_valid_108 && _dataflow_minus_ready_108) begin _dataflow_minus_valid_108 <= 0; end if((_dataflow_minus_ready_108 || !_dataflow_minus_valid_108) && (_dataflow_times_ready_104 && _dataflow_times_ready_105)) begin _dataflow_minus_valid_108 <= _dataflow_times_valid_104 && _dataflow_times_valid_105; end if((_dataflow_plus_ready_109 || !_dataflow_plus_valid_109) && (_dataflow_times_ready_106 && _dataflow_times_ready_107) && (_dataflow_times_valid_106 && _dataflow_times_valid_107)) begin _dataflow_plus_data_109 <= _dataflow_times_data_106 + _dataflow_times_data_107; end if(_dataflow_plus_valid_109 && _dataflow_plus_ready_109) begin _dataflow_plus_valid_109 <= 0; end if((_dataflow_plus_ready_109 || !_dataflow_plus_valid_109) && (_dataflow_times_ready_106 && _dataflow_times_ready_107)) begin _dataflow_plus_valid_109 <= _dataflow_times_valid_106 && _dataflow_times_valid_107; end if((_dataflow_minus_ready_118 || !_dataflow_minus_valid_118) && (_dataflow_times_ready_114 && _dataflow_times_ready_115) && (_dataflow_times_valid_114 && _dataflow_times_valid_115)) begin _dataflow_minus_data_118 <= _dataflow_times_data_114 - _dataflow_times_data_115; end if(_dataflow_minus_valid_118 && _dataflow_minus_ready_118) begin _dataflow_minus_valid_118 <= 0; end if((_dataflow_minus_ready_118 || !_dataflow_minus_valid_118) && (_dataflow_times_ready_114 && _dataflow_times_ready_115)) begin _dataflow_minus_valid_118 <= _dataflow_times_valid_114 && _dataflow_times_valid_115; end if((_dataflow_plus_ready_119 || !_dataflow_plus_valid_119) && (_dataflow_times_ready_116 && _dataflow_times_ready_117) && (_dataflow_times_valid_116 && _dataflow_times_valid_117)) begin _dataflow_plus_data_119 <= _dataflow_times_data_116 + _dataflow_times_data_117; end if(_dataflow_plus_valid_119 && _dataflow_plus_ready_119) begin _dataflow_plus_valid_119 <= 0; end if((_dataflow_plus_ready_119 || !_dataflow_plus_valid_119) && (_dataflow_times_ready_116 && _dataflow_times_ready_117)) begin _dataflow_plus_valid_119 <= _dataflow_times_valid_116 && _dataflow_times_valid_117; end if((_dataflow__delay_ready_283 || !_dataflow__delay_valid_283) && _dataflow__delay_ready_282 && _dataflow__delay_valid_282) begin _dataflow__delay_data_283 <= _dataflow__delay_data_282; end if(_dataflow__delay_valid_283 && _dataflow__delay_ready_283) begin _dataflow__delay_valid_283 <= 0; end if((_dataflow__delay_ready_283 || !_dataflow__delay_valid_283) && _dataflow__delay_ready_282) begin _dataflow__delay_valid_283 <= _dataflow__delay_valid_282; end if((_dataflow__delay_ready_302 || !_dataflow__delay_valid_302) && _dataflow__delay_ready_301 && _dataflow__delay_valid_301) begin _dataflow__delay_data_302 <= _dataflow__delay_data_301; end if(_dataflow__delay_valid_302 && _dataflow__delay_ready_302) begin _dataflow__delay_valid_302 <= 0; end if((_dataflow__delay_ready_302 || !_dataflow__delay_valid_302) && _dataflow__delay_ready_301) begin _dataflow__delay_valid_302 <= _dataflow__delay_valid_301; end if((_dataflow__delay_ready_318 || !_dataflow__delay_valid_318) && _dataflow__delay_ready_317 && _dataflow__delay_valid_317) begin _dataflow__delay_data_318 <= _dataflow__delay_data_317; end if(_dataflow__delay_valid_318 && _dataflow__delay_ready_318) begin _dataflow__delay_valid_318 <= 0; end if((_dataflow__delay_ready_318 || !_dataflow__delay_valid_318) && _dataflow__delay_ready_317) begin _dataflow__delay_valid_318 <= _dataflow__delay_valid_317; end if((_dataflow__delay_ready_342 || !_dataflow__delay_valid_342) && _dataflow__delay_ready_341 && _dataflow__delay_valid_341) begin _dataflow__delay_data_342 <= _dataflow__delay_data_341; end if(_dataflow__delay_valid_342 && _dataflow__delay_ready_342) begin _dataflow__delay_valid_342 <= 0; end if((_dataflow__delay_ready_342 || !_dataflow__delay_valid_342) && _dataflow__delay_ready_341) begin _dataflow__delay_valid_342 <= _dataflow__delay_valid_341; end if((_dataflow__delay_ready_358 || !_dataflow__delay_valid_358) && _dataflow__delay_ready_357 && _dataflow__delay_valid_357) begin _dataflow__delay_data_358 <= _dataflow__delay_data_357; end if(_dataflow__delay_valid_358 && _dataflow__delay_ready_358) begin _dataflow__delay_valid_358 <= 0; end if((_dataflow__delay_ready_358 || !_dataflow__delay_valid_358) && _dataflow__delay_ready_357) begin _dataflow__delay_valid_358 <= _dataflow__delay_valid_357; end if((_dataflow__delay_ready_374 || !_dataflow__delay_valid_374) && _dataflow__delay_ready_373 && _dataflow__delay_valid_373) begin _dataflow__delay_data_374 <= _dataflow__delay_data_373; end if(_dataflow__delay_valid_374 && _dataflow__delay_ready_374) begin _dataflow__delay_valid_374 <= 0; end if((_dataflow__delay_ready_374 || !_dataflow__delay_valid_374) && _dataflow__delay_ready_373) begin _dataflow__delay_valid_374 <= _dataflow__delay_valid_373; end if((_dataflow__delay_ready_390 || !_dataflow__delay_valid_390) && _dataflow__delay_ready_389 && _dataflow__delay_valid_389) begin _dataflow__delay_data_390 <= _dataflow__delay_data_389; end if(_dataflow__delay_valid_390 && _dataflow__delay_ready_390) begin _dataflow__delay_valid_390 <= 0; end if((_dataflow__delay_ready_390 || !_dataflow__delay_valid_390) && _dataflow__delay_ready_389) begin _dataflow__delay_valid_390 <= _dataflow__delay_valid_389; end if((_dataflow__delay_ready_406 || !_dataflow__delay_valid_406) && _dataflow__delay_ready_405 && _dataflow__delay_valid_405) begin _dataflow__delay_data_406 <= _dataflow__delay_data_405; end if(_dataflow__delay_valid_406 && _dataflow__delay_ready_406) begin _dataflow__delay_valid_406 <= 0; end if((_dataflow__delay_ready_406 || !_dataflow__delay_valid_406) && _dataflow__delay_ready_405) begin _dataflow__delay_valid_406 <= _dataflow__delay_valid_405; end if((_dataflow__delay_ready_438 || !_dataflow__delay_valid_438) && _dataflow__delay_ready_437 && _dataflow__delay_valid_437) begin _dataflow__delay_data_438 <= _dataflow__delay_data_437; end if(_dataflow__delay_valid_438 && _dataflow__delay_ready_438) begin _dataflow__delay_valid_438 <= 0; end if((_dataflow__delay_ready_438 || !_dataflow__delay_valid_438) && _dataflow__delay_ready_437) begin _dataflow__delay_valid_438 <= _dataflow__delay_valid_437; end if((_dataflow__delay_ready_454 || !_dataflow__delay_valid_454) && _dataflow__delay_ready_453 && _dataflow__delay_valid_453) begin _dataflow__delay_data_454 <= _dataflow__delay_data_453; end if(_dataflow__delay_valid_454 && _dataflow__delay_ready_454) begin _dataflow__delay_valid_454 <= 0; end if((_dataflow__delay_ready_454 || !_dataflow__delay_valid_454) && _dataflow__delay_ready_453) begin _dataflow__delay_valid_454 <= _dataflow__delay_valid_453; end if((_dataflow_minus_ready_138 || !_dataflow_minus_valid_138) && (_dataflow_times_ready_134 && _dataflow_times_ready_135) && (_dataflow_times_valid_134 && _dataflow_times_valid_135)) begin _dataflow_minus_data_138 <= _dataflow_times_data_134 - _dataflow_times_data_135; end if(_dataflow_minus_valid_138 && _dataflow_minus_ready_138) begin _dataflow_minus_valid_138 <= 0; end if((_dataflow_minus_ready_138 || !_dataflow_minus_valid_138) && (_dataflow_times_ready_134 && _dataflow_times_ready_135)) begin _dataflow_minus_valid_138 <= _dataflow_times_valid_134 && _dataflow_times_valid_135; end if((_dataflow_plus_ready_139 || !_dataflow_plus_valid_139) && (_dataflow_times_ready_136 && _dataflow_times_ready_137) && (_dataflow_times_valid_136 && _dataflow_times_valid_137)) begin _dataflow_plus_data_139 <= _dataflow_times_data_136 + _dataflow_times_data_137; end if(_dataflow_plus_valid_139 && _dataflow_plus_ready_139) begin _dataflow_plus_valid_139 <= 0; end if((_dataflow_plus_ready_139 || !_dataflow_plus_valid_139) && (_dataflow_times_ready_136 && _dataflow_times_ready_137)) begin _dataflow_plus_valid_139 <= _dataflow_times_valid_136 && _dataflow_times_valid_137; end if((_dataflow_minus_ready_148 || !_dataflow_minus_valid_148) && (_dataflow_times_ready_144 && _dataflow_times_ready_145) && (_dataflow_times_valid_144 && _dataflow_times_valid_145)) begin _dataflow_minus_data_148 <= _dataflow_times_data_144 - _dataflow_times_data_145; end if(_dataflow_minus_valid_148 && _dataflow_minus_ready_148) begin _dataflow_minus_valid_148 <= 0; end if((_dataflow_minus_ready_148 || !_dataflow_minus_valid_148) && (_dataflow_times_ready_144 && _dataflow_times_ready_145)) begin _dataflow_minus_valid_148 <= _dataflow_times_valid_144 && _dataflow_times_valid_145; end if((_dataflow_plus_ready_149 || !_dataflow_plus_valid_149) && (_dataflow_times_ready_146 && _dataflow_times_ready_147) && (_dataflow_times_valid_146 && _dataflow_times_valid_147)) begin _dataflow_plus_data_149 <= _dataflow_times_data_146 + _dataflow_times_data_147; end if(_dataflow_plus_valid_149 && _dataflow_plus_ready_149) begin _dataflow_plus_valid_149 <= 0; end if((_dataflow_plus_ready_149 || !_dataflow_plus_valid_149) && (_dataflow_times_ready_146 && _dataflow_times_ready_147)) begin _dataflow_plus_valid_149 <= _dataflow_times_valid_146 && _dataflow_times_valid_147; end if((_dataflow_plus_ready_150 || !_dataflow_plus_valid_150) && (_dataflow_minus_ready_108 && _dataflow_minus_ready_118) && (_dataflow_minus_valid_108 && _dataflow_minus_valid_118)) begin _dataflow_plus_data_150 <= _dataflow_minus_data_108 + _dataflow_minus_data_118; end if(_dataflow_plus_valid_150 && _dataflow_plus_ready_150) begin _dataflow_plus_valid_150 <= 0; end if((_dataflow_plus_ready_150 || !_dataflow_plus_valid_150) && (_dataflow_minus_ready_108 && _dataflow_minus_ready_118)) begin _dataflow_plus_valid_150 <= _dataflow_minus_valid_108 && _dataflow_minus_valid_118; end if((_dataflow_plus_ready_151 || !_dataflow_plus_valid_151) && (_dataflow_plus_ready_109 && _dataflow_plus_ready_119) && (_dataflow_plus_valid_109 && _dataflow_plus_valid_119)) begin _dataflow_plus_data_151 <= _dataflow_plus_data_109 + _dataflow_plus_data_119; end if(_dataflow_plus_valid_151 && _dataflow_plus_ready_151) begin _dataflow_plus_valid_151 <= 0; end if((_dataflow_plus_ready_151 || !_dataflow_plus_valid_151) && (_dataflow_plus_ready_109 && _dataflow_plus_ready_119)) begin _dataflow_plus_valid_151 <= _dataflow_plus_valid_109 && _dataflow_plus_valid_119; end if((_dataflow_minus_ready_152 || !_dataflow_minus_valid_152) && (_dataflow_minus_ready_108 && _dataflow_minus_ready_118) && (_dataflow_minus_valid_108 && _dataflow_minus_valid_118)) begin _dataflow_minus_data_152 <= _dataflow_minus_data_108 - _dataflow_minus_data_118; end if(_dataflow_minus_valid_152 && _dataflow_minus_ready_152) begin _dataflow_minus_valid_152 <= 0; end if((_dataflow_minus_ready_152 || !_dataflow_minus_valid_152) && (_dataflow_minus_ready_108 && _dataflow_minus_ready_118)) begin _dataflow_minus_valid_152 <= _dataflow_minus_valid_108 && _dataflow_minus_valid_118; end if((_dataflow_minus_ready_153 || !_dataflow_minus_valid_153) && (_dataflow_plus_ready_109 && _dataflow_plus_ready_119) && (_dataflow_plus_valid_109 && _dataflow_plus_valid_119)) begin _dataflow_minus_data_153 <= _dataflow_plus_data_109 - _dataflow_plus_data_119; end if(_dataflow_minus_valid_153 && _dataflow_minus_ready_153) begin _dataflow_minus_valid_153 <= 0; end if((_dataflow_minus_ready_153 || !_dataflow_minus_valid_153) && (_dataflow_plus_ready_109 && _dataflow_plus_ready_119)) begin _dataflow_minus_valid_153 <= _dataflow_plus_valid_109 && _dataflow_plus_valid_119; end if((_dataflow__delay_ready_284 || !_dataflow__delay_valid_284) && _dataflow__delay_ready_283 && _dataflow__delay_valid_283) begin _dataflow__delay_data_284 <= _dataflow__delay_data_283; end if(_dataflow__delay_valid_284 && _dataflow__delay_ready_284) begin _dataflow__delay_valid_284 <= 0; end if((_dataflow__delay_ready_284 || !_dataflow__delay_valid_284) && _dataflow__delay_ready_283) begin _dataflow__delay_valid_284 <= _dataflow__delay_valid_283; end if((_dataflow__delay_ready_303 || !_dataflow__delay_valid_303) && _dataflow__delay_ready_302 && _dataflow__delay_valid_302) begin _dataflow__delay_data_303 <= _dataflow__delay_data_302; end if(_dataflow__delay_valid_303 && _dataflow__delay_ready_303) begin _dataflow__delay_valid_303 <= 0; end if((_dataflow__delay_ready_303 || !_dataflow__delay_valid_303) && _dataflow__delay_ready_302) begin _dataflow__delay_valid_303 <= _dataflow__delay_valid_302; end if((_dataflow__delay_ready_319 || !_dataflow__delay_valid_319) && _dataflow__delay_ready_318 && _dataflow__delay_valid_318) begin _dataflow__delay_data_319 <= _dataflow__delay_data_318; end if(_dataflow__delay_valid_319 && _dataflow__delay_ready_319) begin _dataflow__delay_valid_319 <= 0; end if((_dataflow__delay_ready_319 || !_dataflow__delay_valid_319) && _dataflow__delay_ready_318) begin _dataflow__delay_valid_319 <= _dataflow__delay_valid_318; end if((_dataflow__delay_ready_343 || !_dataflow__delay_valid_343) && _dataflow__delay_ready_342 && _dataflow__delay_valid_342) begin _dataflow__delay_data_343 <= _dataflow__delay_data_342; end if(_dataflow__delay_valid_343 && _dataflow__delay_ready_343) begin _dataflow__delay_valid_343 <= 0; end if((_dataflow__delay_ready_343 || !_dataflow__delay_valid_343) && _dataflow__delay_ready_342) begin _dataflow__delay_valid_343 <= _dataflow__delay_valid_342; end if((_dataflow__delay_ready_359 || !_dataflow__delay_valid_359) && _dataflow__delay_ready_358 && _dataflow__delay_valid_358) begin _dataflow__delay_data_359 <= _dataflow__delay_data_358; end if(_dataflow__delay_valid_359 && _dataflow__delay_ready_359) begin _dataflow__delay_valid_359 <= 0; end if((_dataflow__delay_ready_359 || !_dataflow__delay_valid_359) && _dataflow__delay_ready_358) begin _dataflow__delay_valid_359 <= _dataflow__delay_valid_358; end if((_dataflow__delay_ready_375 || !_dataflow__delay_valid_375) && _dataflow__delay_ready_374 && _dataflow__delay_valid_374) begin _dataflow__delay_data_375 <= _dataflow__delay_data_374; end if(_dataflow__delay_valid_375 && _dataflow__delay_ready_375) begin _dataflow__delay_valid_375 <= 0; end if((_dataflow__delay_ready_375 || !_dataflow__delay_valid_375) && _dataflow__delay_ready_374) begin _dataflow__delay_valid_375 <= _dataflow__delay_valid_374; end if((_dataflow__delay_ready_391 || !_dataflow__delay_valid_391) && _dataflow__delay_ready_390 && _dataflow__delay_valid_390) begin _dataflow__delay_data_391 <= _dataflow__delay_data_390; end if(_dataflow__delay_valid_391 && _dataflow__delay_ready_391) begin _dataflow__delay_valid_391 <= 0; end if((_dataflow__delay_ready_391 || !_dataflow__delay_valid_391) && _dataflow__delay_ready_390) begin _dataflow__delay_valid_391 <= _dataflow__delay_valid_390; end if((_dataflow__delay_ready_407 || !_dataflow__delay_valid_407) && _dataflow__delay_ready_406 && _dataflow__delay_valid_406) begin _dataflow__delay_data_407 <= _dataflow__delay_data_406; end if(_dataflow__delay_valid_407 && _dataflow__delay_ready_407) begin _dataflow__delay_valid_407 <= 0; end if((_dataflow__delay_ready_407 || !_dataflow__delay_valid_407) && _dataflow__delay_ready_406) begin _dataflow__delay_valid_407 <= _dataflow__delay_valid_406; end if((_dataflow__delay_ready_439 || !_dataflow__delay_valid_439) && _dataflow__delay_ready_438 && _dataflow__delay_valid_438) begin _dataflow__delay_data_439 <= _dataflow__delay_data_438; end if(_dataflow__delay_valid_439 && _dataflow__delay_ready_439) begin _dataflow__delay_valid_439 <= 0; end if((_dataflow__delay_ready_439 || !_dataflow__delay_valid_439) && _dataflow__delay_ready_438) begin _dataflow__delay_valid_439 <= _dataflow__delay_valid_438; end if((_dataflow__delay_ready_455 || !_dataflow__delay_valid_455) && _dataflow__delay_ready_454 && _dataflow__delay_valid_454) begin _dataflow__delay_data_455 <= _dataflow__delay_data_454; end if(_dataflow__delay_valid_455 && _dataflow__delay_ready_455) begin _dataflow__delay_valid_455 <= 0; end if((_dataflow__delay_ready_455 || !_dataflow__delay_valid_455) && _dataflow__delay_ready_454) begin _dataflow__delay_valid_455 <= _dataflow__delay_valid_454; end if(_dataflow_times_ready_154 || !_dataflow_times_valid_154) begin _dataflow_times_mul_odata_reg_154 <= _dataflow_times_mul_odata_154 >>> 8; end if(_dataflow_times_ready_154 || !_dataflow_times_valid_154) begin _dataflow_times_mul_valid_reg_154 <= _dataflow_times_mul_ovalid_154; end if(_dataflow_times_ready_155 || !_dataflow_times_valid_155) begin _dataflow_times_mul_odata_reg_155 <= _dataflow_times_mul_odata_155 >>> 8; end if(_dataflow_times_ready_155 || !_dataflow_times_valid_155) begin _dataflow_times_mul_valid_reg_155 <= _dataflow_times_mul_ovalid_155; end if(_dataflow_times_ready_156 || !_dataflow_times_valid_156) begin _dataflow_times_mul_odata_reg_156 <= _dataflow_times_mul_odata_156 >>> 8; end if(_dataflow_times_ready_156 || !_dataflow_times_valid_156) begin _dataflow_times_mul_valid_reg_156 <= _dataflow_times_mul_ovalid_156; end if(_dataflow_times_ready_157 || !_dataflow_times_valid_157) begin _dataflow_times_mul_odata_reg_157 <= _dataflow_times_mul_odata_157 >>> 8; end if(_dataflow_times_ready_157 || !_dataflow_times_valid_157) begin _dataflow_times_mul_valid_reg_157 <= _dataflow_times_mul_ovalid_157; end if((_dataflow__delay_ready_320 || !_dataflow__delay_valid_320) && _dataflow__delay_ready_319 && _dataflow__delay_valid_319) begin _dataflow__delay_data_320 <= _dataflow__delay_data_319; end if(_dataflow__delay_valid_320 && _dataflow__delay_ready_320) begin _dataflow__delay_valid_320 <= 0; end if((_dataflow__delay_ready_320 || !_dataflow__delay_valid_320) && _dataflow__delay_ready_319) begin _dataflow__delay_valid_320 <= _dataflow__delay_valid_319; end if((_dataflow__delay_ready_344 || !_dataflow__delay_valid_344) && _dataflow__delay_ready_343 && _dataflow__delay_valid_343) begin _dataflow__delay_data_344 <= _dataflow__delay_data_343; end if(_dataflow__delay_valid_344 && _dataflow__delay_ready_344) begin _dataflow__delay_valid_344 <= 0; end if((_dataflow__delay_ready_344 || !_dataflow__delay_valid_344) && _dataflow__delay_ready_343) begin _dataflow__delay_valid_344 <= _dataflow__delay_valid_343; end if((_dataflow__delay_ready_360 || !_dataflow__delay_valid_360) && _dataflow__delay_ready_359 && _dataflow__delay_valid_359) begin _dataflow__delay_data_360 <= _dataflow__delay_data_359; end if(_dataflow__delay_valid_360 && _dataflow__delay_ready_360) begin _dataflow__delay_valid_360 <= 0; end if((_dataflow__delay_ready_360 || !_dataflow__delay_valid_360) && _dataflow__delay_ready_359) begin _dataflow__delay_valid_360 <= _dataflow__delay_valid_359; end if((_dataflow__delay_ready_376 || !_dataflow__delay_valid_376) && _dataflow__delay_ready_375 && _dataflow__delay_valid_375) begin _dataflow__delay_data_376 <= _dataflow__delay_data_375; end if(_dataflow__delay_valid_376 && _dataflow__delay_ready_376) begin _dataflow__delay_valid_376 <= 0; end if((_dataflow__delay_ready_376 || !_dataflow__delay_valid_376) && _dataflow__delay_ready_375) begin _dataflow__delay_valid_376 <= _dataflow__delay_valid_375; end if((_dataflow__delay_ready_392 || !_dataflow__delay_valid_392) && _dataflow__delay_ready_391 && _dataflow__delay_valid_391) begin _dataflow__delay_data_392 <= _dataflow__delay_data_391; end if(_dataflow__delay_valid_392 && _dataflow__delay_ready_392) begin _dataflow__delay_valid_392 <= 0; end if((_dataflow__delay_ready_392 || !_dataflow__delay_valid_392) && _dataflow__delay_ready_391) begin _dataflow__delay_valid_392 <= _dataflow__delay_valid_391; end if((_dataflow__delay_ready_408 || !_dataflow__delay_valid_408) && _dataflow__delay_ready_407 && _dataflow__delay_valid_407) begin _dataflow__delay_data_408 <= _dataflow__delay_data_407; end if(_dataflow__delay_valid_408 && _dataflow__delay_ready_408) begin _dataflow__delay_valid_408 <= 0; end if((_dataflow__delay_ready_408 || !_dataflow__delay_valid_408) && _dataflow__delay_ready_407) begin _dataflow__delay_valid_408 <= _dataflow__delay_valid_407; end if((_dataflow__delay_ready_416 || !_dataflow__delay_valid_416) && _dataflow_minus_ready_138 && _dataflow_minus_valid_138) begin _dataflow__delay_data_416 <= _dataflow_minus_data_138; end if(_dataflow__delay_valid_416 && _dataflow__delay_ready_416) begin _dataflow__delay_valid_416 <= 0; end if((_dataflow__delay_ready_416 || !_dataflow__delay_valid_416) && _dataflow_minus_ready_138) begin _dataflow__delay_valid_416 <= _dataflow_minus_valid_138; end if((_dataflow__delay_ready_424 || !_dataflow__delay_valid_424) && _dataflow_plus_ready_139 && _dataflow_plus_valid_139) begin _dataflow__delay_data_424 <= _dataflow_plus_data_139; end if(_dataflow__delay_valid_424 && _dataflow__delay_ready_424) begin _dataflow__delay_valid_424 <= 0; end if((_dataflow__delay_ready_424 || !_dataflow__delay_valid_424) && _dataflow_plus_ready_139) begin _dataflow__delay_valid_424 <= _dataflow_plus_valid_139; end if((_dataflow__delay_ready_440 || !_dataflow__delay_valid_440) && _dataflow__delay_ready_439 && _dataflow__delay_valid_439) begin _dataflow__delay_data_440 <= _dataflow__delay_data_439; end if(_dataflow__delay_valid_440 && _dataflow__delay_ready_440) begin _dataflow__delay_valid_440 <= 0; end if((_dataflow__delay_ready_440 || !_dataflow__delay_valid_440) && _dataflow__delay_ready_439) begin _dataflow__delay_valid_440 <= _dataflow__delay_valid_439; end if((_dataflow__delay_ready_456 || !_dataflow__delay_valid_456) && _dataflow__delay_ready_455 && _dataflow__delay_valid_455) begin _dataflow__delay_data_456 <= _dataflow__delay_data_455; end if(_dataflow__delay_valid_456 && _dataflow__delay_ready_456) begin _dataflow__delay_valid_456 <= 0; end if((_dataflow__delay_ready_456 || !_dataflow__delay_valid_456) && _dataflow__delay_ready_455) begin _dataflow__delay_valid_456 <= _dataflow__delay_valid_455; end if((_dataflow__delay_ready_464 || !_dataflow__delay_valid_464) && _dataflow_minus_ready_148 && _dataflow_minus_valid_148) begin _dataflow__delay_data_464 <= _dataflow_minus_data_148; end if(_dataflow__delay_valid_464 && _dataflow__delay_ready_464) begin _dataflow__delay_valid_464 <= 0; end if((_dataflow__delay_ready_464 || !_dataflow__delay_valid_464) && _dataflow_minus_ready_148) begin _dataflow__delay_valid_464 <= _dataflow_minus_valid_148; end if((_dataflow__delay_ready_472 || !_dataflow__delay_valid_472) && _dataflow_plus_ready_149 && _dataflow_plus_valid_149) begin _dataflow__delay_data_472 <= _dataflow_plus_data_149; end if(_dataflow__delay_valid_472 && _dataflow__delay_ready_472) begin _dataflow__delay_valid_472 <= 0; end if((_dataflow__delay_ready_472 || !_dataflow__delay_valid_472) && _dataflow_plus_ready_149) begin _dataflow__delay_valid_472 <= _dataflow_plus_valid_149; end if((_dataflow__delay_ready_480 || !_dataflow__delay_valid_480) && _dataflow_plus_ready_150 && _dataflow_plus_valid_150) begin _dataflow__delay_data_480 <= _dataflow_plus_data_150; end if(_dataflow__delay_valid_480 && _dataflow__delay_ready_480) begin _dataflow__delay_valid_480 <= 0; end if((_dataflow__delay_ready_480 || !_dataflow__delay_valid_480) && _dataflow_plus_ready_150) begin _dataflow__delay_valid_480 <= _dataflow_plus_valid_150; end if((_dataflow__delay_ready_488 || !_dataflow__delay_valid_488) && _dataflow_plus_ready_151 && _dataflow_plus_valid_151) begin _dataflow__delay_data_488 <= _dataflow_plus_data_151; end if(_dataflow__delay_valid_488 && _dataflow__delay_ready_488) begin _dataflow__delay_valid_488 <= 0; end if((_dataflow__delay_ready_488 || !_dataflow__delay_valid_488) && _dataflow_plus_ready_151) begin _dataflow__delay_valid_488 <= _dataflow_plus_valid_151; end if((_dataflow__delay_ready_321 || !_dataflow__delay_valid_321) && _dataflow__delay_ready_320 && _dataflow__delay_valid_320) begin _dataflow__delay_data_321 <= _dataflow__delay_data_320; end if(_dataflow__delay_valid_321 && _dataflow__delay_ready_321) begin _dataflow__delay_valid_321 <= 0; end if((_dataflow__delay_ready_321 || !_dataflow__delay_valid_321) && _dataflow__delay_ready_320) begin _dataflow__delay_valid_321 <= _dataflow__delay_valid_320; end if((_dataflow__delay_ready_345 || !_dataflow__delay_valid_345) && _dataflow__delay_ready_344 && _dataflow__delay_valid_344) begin _dataflow__delay_data_345 <= _dataflow__delay_data_344; end if(_dataflow__delay_valid_345 && _dataflow__delay_ready_345) begin _dataflow__delay_valid_345 <= 0; end if((_dataflow__delay_ready_345 || !_dataflow__delay_valid_345) && _dataflow__delay_ready_344) begin _dataflow__delay_valid_345 <= _dataflow__delay_valid_344; end if((_dataflow__delay_ready_361 || !_dataflow__delay_valid_361) && _dataflow__delay_ready_360 && _dataflow__delay_valid_360) begin _dataflow__delay_data_361 <= _dataflow__delay_data_360; end if(_dataflow__delay_valid_361 && _dataflow__delay_ready_361) begin _dataflow__delay_valid_361 <= 0; end if((_dataflow__delay_ready_361 || !_dataflow__delay_valid_361) && _dataflow__delay_ready_360) begin _dataflow__delay_valid_361 <= _dataflow__delay_valid_360; end if((_dataflow__delay_ready_377 || !_dataflow__delay_valid_377) && _dataflow__delay_ready_376 && _dataflow__delay_valid_376) begin _dataflow__delay_data_377 <= _dataflow__delay_data_376; end if(_dataflow__delay_valid_377 && _dataflow__delay_ready_377) begin _dataflow__delay_valid_377 <= 0; end if((_dataflow__delay_ready_377 || !_dataflow__delay_valid_377) && _dataflow__delay_ready_376) begin _dataflow__delay_valid_377 <= _dataflow__delay_valid_376; end if((_dataflow__delay_ready_393 || !_dataflow__delay_valid_393) && _dataflow__delay_ready_392 && _dataflow__delay_valid_392) begin _dataflow__delay_data_393 <= _dataflow__delay_data_392; end if(_dataflow__delay_valid_393 && _dataflow__delay_ready_393) begin _dataflow__delay_valid_393 <= 0; end if((_dataflow__delay_ready_393 || !_dataflow__delay_valid_393) && _dataflow__delay_ready_392) begin _dataflow__delay_valid_393 <= _dataflow__delay_valid_392; end if((_dataflow__delay_ready_409 || !_dataflow__delay_valid_409) && _dataflow__delay_ready_408 && _dataflow__delay_valid_408) begin _dataflow__delay_data_409 <= _dataflow__delay_data_408; end if(_dataflow__delay_valid_409 && _dataflow__delay_ready_409) begin _dataflow__delay_valid_409 <= 0; end if((_dataflow__delay_ready_409 || !_dataflow__delay_valid_409) && _dataflow__delay_ready_408) begin _dataflow__delay_valid_409 <= _dataflow__delay_valid_408; end if((_dataflow__delay_ready_417 || !_dataflow__delay_valid_417) && _dataflow__delay_ready_416 && _dataflow__delay_valid_416) begin _dataflow__delay_data_417 <= _dataflow__delay_data_416; end if(_dataflow__delay_valid_417 && _dataflow__delay_ready_417) begin _dataflow__delay_valid_417 <= 0; end if((_dataflow__delay_ready_417 || !_dataflow__delay_valid_417) && _dataflow__delay_ready_416) begin _dataflow__delay_valid_417 <= _dataflow__delay_valid_416; end if((_dataflow__delay_ready_425 || !_dataflow__delay_valid_425) && _dataflow__delay_ready_424 && _dataflow__delay_valid_424) begin _dataflow__delay_data_425 <= _dataflow__delay_data_424; end if(_dataflow__delay_valid_425 && _dataflow__delay_ready_425) begin _dataflow__delay_valid_425 <= 0; end if((_dataflow__delay_ready_425 || !_dataflow__delay_valid_425) && _dataflow__delay_ready_424) begin _dataflow__delay_valid_425 <= _dataflow__delay_valid_424; end if((_dataflow__delay_ready_441 || !_dataflow__delay_valid_441) && _dataflow__delay_ready_440 && _dataflow__delay_valid_440) begin _dataflow__delay_data_441 <= _dataflow__delay_data_440; end if(_dataflow__delay_valid_441 && _dataflow__delay_ready_441) begin _dataflow__delay_valid_441 <= 0; end if((_dataflow__delay_ready_441 || !_dataflow__delay_valid_441) && _dataflow__delay_ready_440) begin _dataflow__delay_valid_441 <= _dataflow__delay_valid_440; end if((_dataflow__delay_ready_457 || !_dataflow__delay_valid_457) && _dataflow__delay_ready_456 && _dataflow__delay_valid_456) begin _dataflow__delay_data_457 <= _dataflow__delay_data_456; end if(_dataflow__delay_valid_457 && _dataflow__delay_ready_457) begin _dataflow__delay_valid_457 <= 0; end if((_dataflow__delay_ready_457 || !_dataflow__delay_valid_457) && _dataflow__delay_ready_456) begin _dataflow__delay_valid_457 <= _dataflow__delay_valid_456; end if((_dataflow__delay_ready_465 || !_dataflow__delay_valid_465) && _dataflow__delay_ready_464 && _dataflow__delay_valid_464) begin _dataflow__delay_data_465 <= _dataflow__delay_data_464; end if(_dataflow__delay_valid_465 && _dataflow__delay_ready_465) begin _dataflow__delay_valid_465 <= 0; end if((_dataflow__delay_ready_465 || !_dataflow__delay_valid_465) && _dataflow__delay_ready_464) begin _dataflow__delay_valid_465 <= _dataflow__delay_valid_464; end if((_dataflow__delay_ready_473 || !_dataflow__delay_valid_473) && _dataflow__delay_ready_472 && _dataflow__delay_valid_472) begin _dataflow__delay_data_473 <= _dataflow__delay_data_472; end if(_dataflow__delay_valid_473 && _dataflow__delay_ready_473) begin _dataflow__delay_valid_473 <= 0; end if((_dataflow__delay_ready_473 || !_dataflow__delay_valid_473) && _dataflow__delay_ready_472) begin _dataflow__delay_valid_473 <= _dataflow__delay_valid_472; end if((_dataflow__delay_ready_481 || !_dataflow__delay_valid_481) && _dataflow__delay_ready_480 && _dataflow__delay_valid_480) begin _dataflow__delay_data_481 <= _dataflow__delay_data_480; end if(_dataflow__delay_valid_481 && _dataflow__delay_ready_481) begin _dataflow__delay_valid_481 <= 0; end if((_dataflow__delay_ready_481 || !_dataflow__delay_valid_481) && _dataflow__delay_ready_480) begin _dataflow__delay_valid_481 <= _dataflow__delay_valid_480; end if((_dataflow__delay_ready_489 || !_dataflow__delay_valid_489) && _dataflow__delay_ready_488 && _dataflow__delay_valid_488) begin _dataflow__delay_data_489 <= _dataflow__delay_data_488; end if(_dataflow__delay_valid_489 && _dataflow__delay_ready_489) begin _dataflow__delay_valid_489 <= 0; end if((_dataflow__delay_ready_489 || !_dataflow__delay_valid_489) && _dataflow__delay_ready_488) begin _dataflow__delay_valid_489 <= _dataflow__delay_valid_488; end if((_dataflow__delay_ready_322 || !_dataflow__delay_valid_322) && _dataflow__delay_ready_321 && _dataflow__delay_valid_321) begin _dataflow__delay_data_322 <= _dataflow__delay_data_321; end if(_dataflow__delay_valid_322 && _dataflow__delay_ready_322) begin _dataflow__delay_valid_322 <= 0; end if((_dataflow__delay_ready_322 || !_dataflow__delay_valid_322) && _dataflow__delay_ready_321) begin _dataflow__delay_valid_322 <= _dataflow__delay_valid_321; end if((_dataflow__delay_ready_346 || !_dataflow__delay_valid_346) && _dataflow__delay_ready_345 && _dataflow__delay_valid_345) begin _dataflow__delay_data_346 <= _dataflow__delay_data_345; end if(_dataflow__delay_valid_346 && _dataflow__delay_ready_346) begin _dataflow__delay_valid_346 <= 0; end if((_dataflow__delay_ready_346 || !_dataflow__delay_valid_346) && _dataflow__delay_ready_345) begin _dataflow__delay_valid_346 <= _dataflow__delay_valid_345; end if((_dataflow__delay_ready_362 || !_dataflow__delay_valid_362) && _dataflow__delay_ready_361 && _dataflow__delay_valid_361) begin _dataflow__delay_data_362 <= _dataflow__delay_data_361; end if(_dataflow__delay_valid_362 && _dataflow__delay_ready_362) begin _dataflow__delay_valid_362 <= 0; end if((_dataflow__delay_ready_362 || !_dataflow__delay_valid_362) && _dataflow__delay_ready_361) begin _dataflow__delay_valid_362 <= _dataflow__delay_valid_361; end if((_dataflow__delay_ready_378 || !_dataflow__delay_valid_378) && _dataflow__delay_ready_377 && _dataflow__delay_valid_377) begin _dataflow__delay_data_378 <= _dataflow__delay_data_377; end if(_dataflow__delay_valid_378 && _dataflow__delay_ready_378) begin _dataflow__delay_valid_378 <= 0; end if((_dataflow__delay_ready_378 || !_dataflow__delay_valid_378) && _dataflow__delay_ready_377) begin _dataflow__delay_valid_378 <= _dataflow__delay_valid_377; end if((_dataflow__delay_ready_394 || !_dataflow__delay_valid_394) && _dataflow__delay_ready_393 && _dataflow__delay_valid_393) begin _dataflow__delay_data_394 <= _dataflow__delay_data_393; end if(_dataflow__delay_valid_394 && _dataflow__delay_ready_394) begin _dataflow__delay_valid_394 <= 0; end if((_dataflow__delay_ready_394 || !_dataflow__delay_valid_394) && _dataflow__delay_ready_393) begin _dataflow__delay_valid_394 <= _dataflow__delay_valid_393; end if((_dataflow__delay_ready_410 || !_dataflow__delay_valid_410) && _dataflow__delay_ready_409 && _dataflow__delay_valid_409) begin _dataflow__delay_data_410 <= _dataflow__delay_data_409; end if(_dataflow__delay_valid_410 && _dataflow__delay_ready_410) begin _dataflow__delay_valid_410 <= 0; end if((_dataflow__delay_ready_410 || !_dataflow__delay_valid_410) && _dataflow__delay_ready_409) begin _dataflow__delay_valid_410 <= _dataflow__delay_valid_409; end if((_dataflow__delay_ready_418 || !_dataflow__delay_valid_418) && _dataflow__delay_ready_417 && _dataflow__delay_valid_417) begin _dataflow__delay_data_418 <= _dataflow__delay_data_417; end if(_dataflow__delay_valid_418 && _dataflow__delay_ready_418) begin _dataflow__delay_valid_418 <= 0; end if((_dataflow__delay_ready_418 || !_dataflow__delay_valid_418) && _dataflow__delay_ready_417) begin _dataflow__delay_valid_418 <= _dataflow__delay_valid_417; end if((_dataflow__delay_ready_426 || !_dataflow__delay_valid_426) && _dataflow__delay_ready_425 && _dataflow__delay_valid_425) begin _dataflow__delay_data_426 <= _dataflow__delay_data_425; end if(_dataflow__delay_valid_426 && _dataflow__delay_ready_426) begin _dataflow__delay_valid_426 <= 0; end if((_dataflow__delay_ready_426 || !_dataflow__delay_valid_426) && _dataflow__delay_ready_425) begin _dataflow__delay_valid_426 <= _dataflow__delay_valid_425; end if((_dataflow__delay_ready_442 || !_dataflow__delay_valid_442) && _dataflow__delay_ready_441 && _dataflow__delay_valid_441) begin _dataflow__delay_data_442 <= _dataflow__delay_data_441; end if(_dataflow__delay_valid_442 && _dataflow__delay_ready_442) begin _dataflow__delay_valid_442 <= 0; end if((_dataflow__delay_ready_442 || !_dataflow__delay_valid_442) && _dataflow__delay_ready_441) begin _dataflow__delay_valid_442 <= _dataflow__delay_valid_441; end if((_dataflow__delay_ready_458 || !_dataflow__delay_valid_458) && _dataflow__delay_ready_457 && _dataflow__delay_valid_457) begin _dataflow__delay_data_458 <= _dataflow__delay_data_457; end if(_dataflow__delay_valid_458 && _dataflow__delay_ready_458) begin _dataflow__delay_valid_458 <= 0; end if((_dataflow__delay_ready_458 || !_dataflow__delay_valid_458) && _dataflow__delay_ready_457) begin _dataflow__delay_valid_458 <= _dataflow__delay_valid_457; end if((_dataflow__delay_ready_466 || !_dataflow__delay_valid_466) && _dataflow__delay_ready_465 && _dataflow__delay_valid_465) begin _dataflow__delay_data_466 <= _dataflow__delay_data_465; end if(_dataflow__delay_valid_466 && _dataflow__delay_ready_466) begin _dataflow__delay_valid_466 <= 0; end if((_dataflow__delay_ready_466 || !_dataflow__delay_valid_466) && _dataflow__delay_ready_465) begin _dataflow__delay_valid_466 <= _dataflow__delay_valid_465; end if((_dataflow__delay_ready_474 || !_dataflow__delay_valid_474) && _dataflow__delay_ready_473 && _dataflow__delay_valid_473) begin _dataflow__delay_data_474 <= _dataflow__delay_data_473; end if(_dataflow__delay_valid_474 && _dataflow__delay_ready_474) begin _dataflow__delay_valid_474 <= 0; end if((_dataflow__delay_ready_474 || !_dataflow__delay_valid_474) && _dataflow__delay_ready_473) begin _dataflow__delay_valid_474 <= _dataflow__delay_valid_473; end if((_dataflow__delay_ready_482 || !_dataflow__delay_valid_482) && _dataflow__delay_ready_481 && _dataflow__delay_valid_481) begin _dataflow__delay_data_482 <= _dataflow__delay_data_481; end if(_dataflow__delay_valid_482 && _dataflow__delay_ready_482) begin _dataflow__delay_valid_482 <= 0; end if((_dataflow__delay_ready_482 || !_dataflow__delay_valid_482) && _dataflow__delay_ready_481) begin _dataflow__delay_valid_482 <= _dataflow__delay_valid_481; end if((_dataflow__delay_ready_490 || !_dataflow__delay_valid_490) && _dataflow__delay_ready_489 && _dataflow__delay_valid_489) begin _dataflow__delay_data_490 <= _dataflow__delay_data_489; end if(_dataflow__delay_valid_490 && _dataflow__delay_ready_490) begin _dataflow__delay_valid_490 <= 0; end if((_dataflow__delay_ready_490 || !_dataflow__delay_valid_490) && _dataflow__delay_ready_489) begin _dataflow__delay_valid_490 <= _dataflow__delay_valid_489; end if((_dataflow__delay_ready_323 || !_dataflow__delay_valid_323) && _dataflow__delay_ready_322 && _dataflow__delay_valid_322) begin _dataflow__delay_data_323 <= _dataflow__delay_data_322; end if(_dataflow__delay_valid_323 && _dataflow__delay_ready_323) begin _dataflow__delay_valid_323 <= 0; end if((_dataflow__delay_ready_323 || !_dataflow__delay_valid_323) && _dataflow__delay_ready_322) begin _dataflow__delay_valid_323 <= _dataflow__delay_valid_322; end if((_dataflow__delay_ready_347 || !_dataflow__delay_valid_347) && _dataflow__delay_ready_346 && _dataflow__delay_valid_346) begin _dataflow__delay_data_347 <= _dataflow__delay_data_346; end if(_dataflow__delay_valid_347 && _dataflow__delay_ready_347) begin _dataflow__delay_valid_347 <= 0; end if((_dataflow__delay_ready_347 || !_dataflow__delay_valid_347) && _dataflow__delay_ready_346) begin _dataflow__delay_valid_347 <= _dataflow__delay_valid_346; end if((_dataflow__delay_ready_363 || !_dataflow__delay_valid_363) && _dataflow__delay_ready_362 && _dataflow__delay_valid_362) begin _dataflow__delay_data_363 <= _dataflow__delay_data_362; end if(_dataflow__delay_valid_363 && _dataflow__delay_ready_363) begin _dataflow__delay_valid_363 <= 0; end if((_dataflow__delay_ready_363 || !_dataflow__delay_valid_363) && _dataflow__delay_ready_362) begin _dataflow__delay_valid_363 <= _dataflow__delay_valid_362; end if((_dataflow__delay_ready_379 || !_dataflow__delay_valid_379) && _dataflow__delay_ready_378 && _dataflow__delay_valid_378) begin _dataflow__delay_data_379 <= _dataflow__delay_data_378; end if(_dataflow__delay_valid_379 && _dataflow__delay_ready_379) begin _dataflow__delay_valid_379 <= 0; end if((_dataflow__delay_ready_379 || !_dataflow__delay_valid_379) && _dataflow__delay_ready_378) begin _dataflow__delay_valid_379 <= _dataflow__delay_valid_378; end if((_dataflow__delay_ready_395 || !_dataflow__delay_valid_395) && _dataflow__delay_ready_394 && _dataflow__delay_valid_394) begin _dataflow__delay_data_395 <= _dataflow__delay_data_394; end if(_dataflow__delay_valid_395 && _dataflow__delay_ready_395) begin _dataflow__delay_valid_395 <= 0; end if((_dataflow__delay_ready_395 || !_dataflow__delay_valid_395) && _dataflow__delay_ready_394) begin _dataflow__delay_valid_395 <= _dataflow__delay_valid_394; end if((_dataflow__delay_ready_411 || !_dataflow__delay_valid_411) && _dataflow__delay_ready_410 && _dataflow__delay_valid_410) begin _dataflow__delay_data_411 <= _dataflow__delay_data_410; end if(_dataflow__delay_valid_411 && _dataflow__delay_ready_411) begin _dataflow__delay_valid_411 <= 0; end if((_dataflow__delay_ready_411 || !_dataflow__delay_valid_411) && _dataflow__delay_ready_410) begin _dataflow__delay_valid_411 <= _dataflow__delay_valid_410; end if((_dataflow__delay_ready_419 || !_dataflow__delay_valid_419) && _dataflow__delay_ready_418 && _dataflow__delay_valid_418) begin _dataflow__delay_data_419 <= _dataflow__delay_data_418; end if(_dataflow__delay_valid_419 && _dataflow__delay_ready_419) begin _dataflow__delay_valid_419 <= 0; end if((_dataflow__delay_ready_419 || !_dataflow__delay_valid_419) && _dataflow__delay_ready_418) begin _dataflow__delay_valid_419 <= _dataflow__delay_valid_418; end if((_dataflow__delay_ready_427 || !_dataflow__delay_valid_427) && _dataflow__delay_ready_426 && _dataflow__delay_valid_426) begin _dataflow__delay_data_427 <= _dataflow__delay_data_426; end if(_dataflow__delay_valid_427 && _dataflow__delay_ready_427) begin _dataflow__delay_valid_427 <= 0; end if((_dataflow__delay_ready_427 || !_dataflow__delay_valid_427) && _dataflow__delay_ready_426) begin _dataflow__delay_valid_427 <= _dataflow__delay_valid_426; end if((_dataflow__delay_ready_443 || !_dataflow__delay_valid_443) && _dataflow__delay_ready_442 && _dataflow__delay_valid_442) begin _dataflow__delay_data_443 <= _dataflow__delay_data_442; end if(_dataflow__delay_valid_443 && _dataflow__delay_ready_443) begin _dataflow__delay_valid_443 <= 0; end if((_dataflow__delay_ready_443 || !_dataflow__delay_valid_443) && _dataflow__delay_ready_442) begin _dataflow__delay_valid_443 <= _dataflow__delay_valid_442; end if((_dataflow__delay_ready_459 || !_dataflow__delay_valid_459) && _dataflow__delay_ready_458 && _dataflow__delay_valid_458) begin _dataflow__delay_data_459 <= _dataflow__delay_data_458; end if(_dataflow__delay_valid_459 && _dataflow__delay_ready_459) begin _dataflow__delay_valid_459 <= 0; end if((_dataflow__delay_ready_459 || !_dataflow__delay_valid_459) && _dataflow__delay_ready_458) begin _dataflow__delay_valid_459 <= _dataflow__delay_valid_458; end if((_dataflow__delay_ready_467 || !_dataflow__delay_valid_467) && _dataflow__delay_ready_466 && _dataflow__delay_valid_466) begin _dataflow__delay_data_467 <= _dataflow__delay_data_466; end if(_dataflow__delay_valid_467 && _dataflow__delay_ready_467) begin _dataflow__delay_valid_467 <= 0; end if((_dataflow__delay_ready_467 || !_dataflow__delay_valid_467) && _dataflow__delay_ready_466) begin _dataflow__delay_valid_467 <= _dataflow__delay_valid_466; end if((_dataflow__delay_ready_475 || !_dataflow__delay_valid_475) && _dataflow__delay_ready_474 && _dataflow__delay_valid_474) begin _dataflow__delay_data_475 <= _dataflow__delay_data_474; end if(_dataflow__delay_valid_475 && _dataflow__delay_ready_475) begin _dataflow__delay_valid_475 <= 0; end if((_dataflow__delay_ready_475 || !_dataflow__delay_valid_475) && _dataflow__delay_ready_474) begin _dataflow__delay_valid_475 <= _dataflow__delay_valid_474; end if((_dataflow__delay_ready_483 || !_dataflow__delay_valid_483) && _dataflow__delay_ready_482 && _dataflow__delay_valid_482) begin _dataflow__delay_data_483 <= _dataflow__delay_data_482; end if(_dataflow__delay_valid_483 && _dataflow__delay_ready_483) begin _dataflow__delay_valid_483 <= 0; end if((_dataflow__delay_ready_483 || !_dataflow__delay_valid_483) && _dataflow__delay_ready_482) begin _dataflow__delay_valid_483 <= _dataflow__delay_valid_482; end if((_dataflow__delay_ready_491 || !_dataflow__delay_valid_491) && _dataflow__delay_ready_490 && _dataflow__delay_valid_490) begin _dataflow__delay_data_491 <= _dataflow__delay_data_490; end if(_dataflow__delay_valid_491 && _dataflow__delay_ready_491) begin _dataflow__delay_valid_491 <= 0; end if((_dataflow__delay_ready_491 || !_dataflow__delay_valid_491) && _dataflow__delay_ready_490) begin _dataflow__delay_valid_491 <= _dataflow__delay_valid_490; end if((_dataflow__delay_ready_324 || !_dataflow__delay_valid_324) && _dataflow__delay_ready_323 && _dataflow__delay_valid_323) begin _dataflow__delay_data_324 <= _dataflow__delay_data_323; end if(_dataflow__delay_valid_324 && _dataflow__delay_ready_324) begin _dataflow__delay_valid_324 <= 0; end if((_dataflow__delay_ready_324 || !_dataflow__delay_valid_324) && _dataflow__delay_ready_323) begin _dataflow__delay_valid_324 <= _dataflow__delay_valid_323; end if((_dataflow__delay_ready_348 || !_dataflow__delay_valid_348) && _dataflow__delay_ready_347 && _dataflow__delay_valid_347) begin _dataflow__delay_data_348 <= _dataflow__delay_data_347; end if(_dataflow__delay_valid_348 && _dataflow__delay_ready_348) begin _dataflow__delay_valid_348 <= 0; end if((_dataflow__delay_ready_348 || !_dataflow__delay_valid_348) && _dataflow__delay_ready_347) begin _dataflow__delay_valid_348 <= _dataflow__delay_valid_347; end if((_dataflow__delay_ready_364 || !_dataflow__delay_valid_364) && _dataflow__delay_ready_363 && _dataflow__delay_valid_363) begin _dataflow__delay_data_364 <= _dataflow__delay_data_363; end if(_dataflow__delay_valid_364 && _dataflow__delay_ready_364) begin _dataflow__delay_valid_364 <= 0; end if((_dataflow__delay_ready_364 || !_dataflow__delay_valid_364) && _dataflow__delay_ready_363) begin _dataflow__delay_valid_364 <= _dataflow__delay_valid_363; end if((_dataflow__delay_ready_380 || !_dataflow__delay_valid_380) && _dataflow__delay_ready_379 && _dataflow__delay_valid_379) begin _dataflow__delay_data_380 <= _dataflow__delay_data_379; end if(_dataflow__delay_valid_380 && _dataflow__delay_ready_380) begin _dataflow__delay_valid_380 <= 0; end if((_dataflow__delay_ready_380 || !_dataflow__delay_valid_380) && _dataflow__delay_ready_379) begin _dataflow__delay_valid_380 <= _dataflow__delay_valid_379; end if((_dataflow__delay_ready_396 || !_dataflow__delay_valid_396) && _dataflow__delay_ready_395 && _dataflow__delay_valid_395) begin _dataflow__delay_data_396 <= _dataflow__delay_data_395; end if(_dataflow__delay_valid_396 && _dataflow__delay_ready_396) begin _dataflow__delay_valid_396 <= 0; end if((_dataflow__delay_ready_396 || !_dataflow__delay_valid_396) && _dataflow__delay_ready_395) begin _dataflow__delay_valid_396 <= _dataflow__delay_valid_395; end if((_dataflow__delay_ready_412 || !_dataflow__delay_valid_412) && _dataflow__delay_ready_411 && _dataflow__delay_valid_411) begin _dataflow__delay_data_412 <= _dataflow__delay_data_411; end if(_dataflow__delay_valid_412 && _dataflow__delay_ready_412) begin _dataflow__delay_valid_412 <= 0; end if((_dataflow__delay_ready_412 || !_dataflow__delay_valid_412) && _dataflow__delay_ready_411) begin _dataflow__delay_valid_412 <= _dataflow__delay_valid_411; end if((_dataflow__delay_ready_420 || !_dataflow__delay_valid_420) && _dataflow__delay_ready_419 && _dataflow__delay_valid_419) begin _dataflow__delay_data_420 <= _dataflow__delay_data_419; end if(_dataflow__delay_valid_420 && _dataflow__delay_ready_420) begin _dataflow__delay_valid_420 <= 0; end if((_dataflow__delay_ready_420 || !_dataflow__delay_valid_420) && _dataflow__delay_ready_419) begin _dataflow__delay_valid_420 <= _dataflow__delay_valid_419; end if((_dataflow__delay_ready_428 || !_dataflow__delay_valid_428) && _dataflow__delay_ready_427 && _dataflow__delay_valid_427) begin _dataflow__delay_data_428 <= _dataflow__delay_data_427; end if(_dataflow__delay_valid_428 && _dataflow__delay_ready_428) begin _dataflow__delay_valid_428 <= 0; end if((_dataflow__delay_ready_428 || !_dataflow__delay_valid_428) && _dataflow__delay_ready_427) begin _dataflow__delay_valid_428 <= _dataflow__delay_valid_427; end if((_dataflow__delay_ready_444 || !_dataflow__delay_valid_444) && _dataflow__delay_ready_443 && _dataflow__delay_valid_443) begin _dataflow__delay_data_444 <= _dataflow__delay_data_443; end if(_dataflow__delay_valid_444 && _dataflow__delay_ready_444) begin _dataflow__delay_valid_444 <= 0; end if((_dataflow__delay_ready_444 || !_dataflow__delay_valid_444) && _dataflow__delay_ready_443) begin _dataflow__delay_valid_444 <= _dataflow__delay_valid_443; end if((_dataflow__delay_ready_460 || !_dataflow__delay_valid_460) && _dataflow__delay_ready_459 && _dataflow__delay_valid_459) begin _dataflow__delay_data_460 <= _dataflow__delay_data_459; end if(_dataflow__delay_valid_460 && _dataflow__delay_ready_460) begin _dataflow__delay_valid_460 <= 0; end if((_dataflow__delay_ready_460 || !_dataflow__delay_valid_460) && _dataflow__delay_ready_459) begin _dataflow__delay_valid_460 <= _dataflow__delay_valid_459; end if((_dataflow__delay_ready_468 || !_dataflow__delay_valid_468) && _dataflow__delay_ready_467 && _dataflow__delay_valid_467) begin _dataflow__delay_data_468 <= _dataflow__delay_data_467; end if(_dataflow__delay_valid_468 && _dataflow__delay_ready_468) begin _dataflow__delay_valid_468 <= 0; end if((_dataflow__delay_ready_468 || !_dataflow__delay_valid_468) && _dataflow__delay_ready_467) begin _dataflow__delay_valid_468 <= _dataflow__delay_valid_467; end if((_dataflow__delay_ready_476 || !_dataflow__delay_valid_476) && _dataflow__delay_ready_475 && _dataflow__delay_valid_475) begin _dataflow__delay_data_476 <= _dataflow__delay_data_475; end if(_dataflow__delay_valid_476 && _dataflow__delay_ready_476) begin _dataflow__delay_valid_476 <= 0; end if((_dataflow__delay_ready_476 || !_dataflow__delay_valid_476) && _dataflow__delay_ready_475) begin _dataflow__delay_valid_476 <= _dataflow__delay_valid_475; end if((_dataflow__delay_ready_484 || !_dataflow__delay_valid_484) && _dataflow__delay_ready_483 && _dataflow__delay_valid_483) begin _dataflow__delay_data_484 <= _dataflow__delay_data_483; end if(_dataflow__delay_valid_484 && _dataflow__delay_ready_484) begin _dataflow__delay_valid_484 <= 0; end if((_dataflow__delay_ready_484 || !_dataflow__delay_valid_484) && _dataflow__delay_ready_483) begin _dataflow__delay_valid_484 <= _dataflow__delay_valid_483; end if((_dataflow__delay_ready_492 || !_dataflow__delay_valid_492) && _dataflow__delay_ready_491 && _dataflow__delay_valid_491) begin _dataflow__delay_data_492 <= _dataflow__delay_data_491; end if(_dataflow__delay_valid_492 && _dataflow__delay_ready_492) begin _dataflow__delay_valid_492 <= 0; end if((_dataflow__delay_ready_492 || !_dataflow__delay_valid_492) && _dataflow__delay_ready_491) begin _dataflow__delay_valid_492 <= _dataflow__delay_valid_491; end if((_dataflow__delay_ready_325 || !_dataflow__delay_valid_325) && _dataflow__delay_ready_324 && _dataflow__delay_valid_324) begin _dataflow__delay_data_325 <= _dataflow__delay_data_324; end if(_dataflow__delay_valid_325 && _dataflow__delay_ready_325) begin _dataflow__delay_valid_325 <= 0; end if((_dataflow__delay_ready_325 || !_dataflow__delay_valid_325) && _dataflow__delay_ready_324) begin _dataflow__delay_valid_325 <= _dataflow__delay_valid_324; end if((_dataflow__delay_ready_349 || !_dataflow__delay_valid_349) && _dataflow__delay_ready_348 && _dataflow__delay_valid_348) begin _dataflow__delay_data_349 <= _dataflow__delay_data_348; end if(_dataflow__delay_valid_349 && _dataflow__delay_ready_349) begin _dataflow__delay_valid_349 <= 0; end if((_dataflow__delay_ready_349 || !_dataflow__delay_valid_349) && _dataflow__delay_ready_348) begin _dataflow__delay_valid_349 <= _dataflow__delay_valid_348; end if((_dataflow__delay_ready_365 || !_dataflow__delay_valid_365) && _dataflow__delay_ready_364 && _dataflow__delay_valid_364) begin _dataflow__delay_data_365 <= _dataflow__delay_data_364; end if(_dataflow__delay_valid_365 && _dataflow__delay_ready_365) begin _dataflow__delay_valid_365 <= 0; end if((_dataflow__delay_ready_365 || !_dataflow__delay_valid_365) && _dataflow__delay_ready_364) begin _dataflow__delay_valid_365 <= _dataflow__delay_valid_364; end if((_dataflow__delay_ready_381 || !_dataflow__delay_valid_381) && _dataflow__delay_ready_380 && _dataflow__delay_valid_380) begin _dataflow__delay_data_381 <= _dataflow__delay_data_380; end if(_dataflow__delay_valid_381 && _dataflow__delay_ready_381) begin _dataflow__delay_valid_381 <= 0; end if((_dataflow__delay_ready_381 || !_dataflow__delay_valid_381) && _dataflow__delay_ready_380) begin _dataflow__delay_valid_381 <= _dataflow__delay_valid_380; end if((_dataflow__delay_ready_397 || !_dataflow__delay_valid_397) && _dataflow__delay_ready_396 && _dataflow__delay_valid_396) begin _dataflow__delay_data_397 <= _dataflow__delay_data_396; end if(_dataflow__delay_valid_397 && _dataflow__delay_ready_397) begin _dataflow__delay_valid_397 <= 0; end if((_dataflow__delay_ready_397 || !_dataflow__delay_valid_397) && _dataflow__delay_ready_396) begin _dataflow__delay_valid_397 <= _dataflow__delay_valid_396; end if((_dataflow__delay_ready_413 || !_dataflow__delay_valid_413) && _dataflow__delay_ready_412 && _dataflow__delay_valid_412) begin _dataflow__delay_data_413 <= _dataflow__delay_data_412; end if(_dataflow__delay_valid_413 && _dataflow__delay_ready_413) begin _dataflow__delay_valid_413 <= 0; end if((_dataflow__delay_ready_413 || !_dataflow__delay_valid_413) && _dataflow__delay_ready_412) begin _dataflow__delay_valid_413 <= _dataflow__delay_valid_412; end if((_dataflow__delay_ready_421 || !_dataflow__delay_valid_421) && _dataflow__delay_ready_420 && _dataflow__delay_valid_420) begin _dataflow__delay_data_421 <= _dataflow__delay_data_420; end if(_dataflow__delay_valid_421 && _dataflow__delay_ready_421) begin _dataflow__delay_valid_421 <= 0; end if((_dataflow__delay_ready_421 || !_dataflow__delay_valid_421) && _dataflow__delay_ready_420) begin _dataflow__delay_valid_421 <= _dataflow__delay_valid_420; end if((_dataflow__delay_ready_429 || !_dataflow__delay_valid_429) && _dataflow__delay_ready_428 && _dataflow__delay_valid_428) begin _dataflow__delay_data_429 <= _dataflow__delay_data_428; end if(_dataflow__delay_valid_429 && _dataflow__delay_ready_429) begin _dataflow__delay_valid_429 <= 0; end if((_dataflow__delay_ready_429 || !_dataflow__delay_valid_429) && _dataflow__delay_ready_428) begin _dataflow__delay_valid_429 <= _dataflow__delay_valid_428; end if((_dataflow__delay_ready_445 || !_dataflow__delay_valid_445) && _dataflow__delay_ready_444 && _dataflow__delay_valid_444) begin _dataflow__delay_data_445 <= _dataflow__delay_data_444; end if(_dataflow__delay_valid_445 && _dataflow__delay_ready_445) begin _dataflow__delay_valid_445 <= 0; end if((_dataflow__delay_ready_445 || !_dataflow__delay_valid_445) && _dataflow__delay_ready_444) begin _dataflow__delay_valid_445 <= _dataflow__delay_valid_444; end if((_dataflow__delay_ready_461 || !_dataflow__delay_valid_461) && _dataflow__delay_ready_460 && _dataflow__delay_valid_460) begin _dataflow__delay_data_461 <= _dataflow__delay_data_460; end if(_dataflow__delay_valid_461 && _dataflow__delay_ready_461) begin _dataflow__delay_valid_461 <= 0; end if((_dataflow__delay_ready_461 || !_dataflow__delay_valid_461) && _dataflow__delay_ready_460) begin _dataflow__delay_valid_461 <= _dataflow__delay_valid_460; end if((_dataflow__delay_ready_469 || !_dataflow__delay_valid_469) && _dataflow__delay_ready_468 && _dataflow__delay_valid_468) begin _dataflow__delay_data_469 <= _dataflow__delay_data_468; end if(_dataflow__delay_valid_469 && _dataflow__delay_ready_469) begin _dataflow__delay_valid_469 <= 0; end if((_dataflow__delay_ready_469 || !_dataflow__delay_valid_469) && _dataflow__delay_ready_468) begin _dataflow__delay_valid_469 <= _dataflow__delay_valid_468; end if((_dataflow__delay_ready_477 || !_dataflow__delay_valid_477) && _dataflow__delay_ready_476 && _dataflow__delay_valid_476) begin _dataflow__delay_data_477 <= _dataflow__delay_data_476; end if(_dataflow__delay_valid_477 && _dataflow__delay_ready_477) begin _dataflow__delay_valid_477 <= 0; end if((_dataflow__delay_ready_477 || !_dataflow__delay_valid_477) && _dataflow__delay_ready_476) begin _dataflow__delay_valid_477 <= _dataflow__delay_valid_476; end if((_dataflow__delay_ready_485 || !_dataflow__delay_valid_485) && _dataflow__delay_ready_484 && _dataflow__delay_valid_484) begin _dataflow__delay_data_485 <= _dataflow__delay_data_484; end if(_dataflow__delay_valid_485 && _dataflow__delay_ready_485) begin _dataflow__delay_valid_485 <= 0; end if((_dataflow__delay_ready_485 || !_dataflow__delay_valid_485) && _dataflow__delay_ready_484) begin _dataflow__delay_valid_485 <= _dataflow__delay_valid_484; end if((_dataflow__delay_ready_493 || !_dataflow__delay_valid_493) && _dataflow__delay_ready_492 && _dataflow__delay_valid_492) begin _dataflow__delay_data_493 <= _dataflow__delay_data_492; end if(_dataflow__delay_valid_493 && _dataflow__delay_ready_493) begin _dataflow__delay_valid_493 <= 0; end if((_dataflow__delay_ready_493 || !_dataflow__delay_valid_493) && _dataflow__delay_ready_492) begin _dataflow__delay_valid_493 <= _dataflow__delay_valid_492; end if((_dataflow__delay_ready_326 || !_dataflow__delay_valid_326) && _dataflow__delay_ready_325 && _dataflow__delay_valid_325) begin _dataflow__delay_data_326 <= _dataflow__delay_data_325; end if(_dataflow__delay_valid_326 && _dataflow__delay_ready_326) begin _dataflow__delay_valid_326 <= 0; end if((_dataflow__delay_ready_326 || !_dataflow__delay_valid_326) && _dataflow__delay_ready_325) begin _dataflow__delay_valid_326 <= _dataflow__delay_valid_325; end if((_dataflow__delay_ready_350 || !_dataflow__delay_valid_350) && _dataflow__delay_ready_349 && _dataflow__delay_valid_349) begin _dataflow__delay_data_350 <= _dataflow__delay_data_349; end if(_dataflow__delay_valid_350 && _dataflow__delay_ready_350) begin _dataflow__delay_valid_350 <= 0; end if((_dataflow__delay_ready_350 || !_dataflow__delay_valid_350) && _dataflow__delay_ready_349) begin _dataflow__delay_valid_350 <= _dataflow__delay_valid_349; end if((_dataflow__delay_ready_366 || !_dataflow__delay_valid_366) && _dataflow__delay_ready_365 && _dataflow__delay_valid_365) begin _dataflow__delay_data_366 <= _dataflow__delay_data_365; end if(_dataflow__delay_valid_366 && _dataflow__delay_ready_366) begin _dataflow__delay_valid_366 <= 0; end if((_dataflow__delay_ready_366 || !_dataflow__delay_valid_366) && _dataflow__delay_ready_365) begin _dataflow__delay_valid_366 <= _dataflow__delay_valid_365; end if((_dataflow__delay_ready_382 || !_dataflow__delay_valid_382) && _dataflow__delay_ready_381 && _dataflow__delay_valid_381) begin _dataflow__delay_data_382 <= _dataflow__delay_data_381; end if(_dataflow__delay_valid_382 && _dataflow__delay_ready_382) begin _dataflow__delay_valid_382 <= 0; end if((_dataflow__delay_ready_382 || !_dataflow__delay_valid_382) && _dataflow__delay_ready_381) begin _dataflow__delay_valid_382 <= _dataflow__delay_valid_381; end if((_dataflow__delay_ready_398 || !_dataflow__delay_valid_398) && _dataflow__delay_ready_397 && _dataflow__delay_valid_397) begin _dataflow__delay_data_398 <= _dataflow__delay_data_397; end if(_dataflow__delay_valid_398 && _dataflow__delay_ready_398) begin _dataflow__delay_valid_398 <= 0; end if((_dataflow__delay_ready_398 || !_dataflow__delay_valid_398) && _dataflow__delay_ready_397) begin _dataflow__delay_valid_398 <= _dataflow__delay_valid_397; end if((_dataflow__delay_ready_414 || !_dataflow__delay_valid_414) && _dataflow__delay_ready_413 && _dataflow__delay_valid_413) begin _dataflow__delay_data_414 <= _dataflow__delay_data_413; end if(_dataflow__delay_valid_414 && _dataflow__delay_ready_414) begin _dataflow__delay_valid_414 <= 0; end if((_dataflow__delay_ready_414 || !_dataflow__delay_valid_414) && _dataflow__delay_ready_413) begin _dataflow__delay_valid_414 <= _dataflow__delay_valid_413; end if((_dataflow__delay_ready_422 || !_dataflow__delay_valid_422) && _dataflow__delay_ready_421 && _dataflow__delay_valid_421) begin _dataflow__delay_data_422 <= _dataflow__delay_data_421; end if(_dataflow__delay_valid_422 && _dataflow__delay_ready_422) begin _dataflow__delay_valid_422 <= 0; end if((_dataflow__delay_ready_422 || !_dataflow__delay_valid_422) && _dataflow__delay_ready_421) begin _dataflow__delay_valid_422 <= _dataflow__delay_valid_421; end if((_dataflow__delay_ready_430 || !_dataflow__delay_valid_430) && _dataflow__delay_ready_429 && _dataflow__delay_valid_429) begin _dataflow__delay_data_430 <= _dataflow__delay_data_429; end if(_dataflow__delay_valid_430 && _dataflow__delay_ready_430) begin _dataflow__delay_valid_430 <= 0; end if((_dataflow__delay_ready_430 || !_dataflow__delay_valid_430) && _dataflow__delay_ready_429) begin _dataflow__delay_valid_430 <= _dataflow__delay_valid_429; end if((_dataflow__delay_ready_446 || !_dataflow__delay_valid_446) && _dataflow__delay_ready_445 && _dataflow__delay_valid_445) begin _dataflow__delay_data_446 <= _dataflow__delay_data_445; end if(_dataflow__delay_valid_446 && _dataflow__delay_ready_446) begin _dataflow__delay_valid_446 <= 0; end if((_dataflow__delay_ready_446 || !_dataflow__delay_valid_446) && _dataflow__delay_ready_445) begin _dataflow__delay_valid_446 <= _dataflow__delay_valid_445; end if((_dataflow__delay_ready_462 || !_dataflow__delay_valid_462) && _dataflow__delay_ready_461 && _dataflow__delay_valid_461) begin _dataflow__delay_data_462 <= _dataflow__delay_data_461; end if(_dataflow__delay_valid_462 && _dataflow__delay_ready_462) begin _dataflow__delay_valid_462 <= 0; end if((_dataflow__delay_ready_462 || !_dataflow__delay_valid_462) && _dataflow__delay_ready_461) begin _dataflow__delay_valid_462 <= _dataflow__delay_valid_461; end if((_dataflow__delay_ready_470 || !_dataflow__delay_valid_470) && _dataflow__delay_ready_469 && _dataflow__delay_valid_469) begin _dataflow__delay_data_470 <= _dataflow__delay_data_469; end if(_dataflow__delay_valid_470 && _dataflow__delay_ready_470) begin _dataflow__delay_valid_470 <= 0; end if((_dataflow__delay_ready_470 || !_dataflow__delay_valid_470) && _dataflow__delay_ready_469) begin _dataflow__delay_valid_470 <= _dataflow__delay_valid_469; end if((_dataflow__delay_ready_478 || !_dataflow__delay_valid_478) && _dataflow__delay_ready_477 && _dataflow__delay_valid_477) begin _dataflow__delay_data_478 <= _dataflow__delay_data_477; end if(_dataflow__delay_valid_478 && _dataflow__delay_ready_478) begin _dataflow__delay_valid_478 <= 0; end if((_dataflow__delay_ready_478 || !_dataflow__delay_valid_478) && _dataflow__delay_ready_477) begin _dataflow__delay_valid_478 <= _dataflow__delay_valid_477; end if((_dataflow__delay_ready_486 || !_dataflow__delay_valid_486) && _dataflow__delay_ready_485 && _dataflow__delay_valid_485) begin _dataflow__delay_data_486 <= _dataflow__delay_data_485; end if(_dataflow__delay_valid_486 && _dataflow__delay_ready_486) begin _dataflow__delay_valid_486 <= 0; end if((_dataflow__delay_ready_486 || !_dataflow__delay_valid_486) && _dataflow__delay_ready_485) begin _dataflow__delay_valid_486 <= _dataflow__delay_valid_485; end if((_dataflow__delay_ready_494 || !_dataflow__delay_valid_494) && _dataflow__delay_ready_493 && _dataflow__delay_valid_493) begin _dataflow__delay_data_494 <= _dataflow__delay_data_493; end if(_dataflow__delay_valid_494 && _dataflow__delay_ready_494) begin _dataflow__delay_valid_494 <= 0; end if((_dataflow__delay_ready_494 || !_dataflow__delay_valid_494) && _dataflow__delay_ready_493) begin _dataflow__delay_valid_494 <= _dataflow__delay_valid_493; end if((_dataflow_minus_ready_158 || !_dataflow_minus_valid_158) && (_dataflow_times_ready_154 && _dataflow_times_ready_155) && (_dataflow_times_valid_154 && _dataflow_times_valid_155)) begin _dataflow_minus_data_158 <= _dataflow_times_data_154 - _dataflow_times_data_155; end if(_dataflow_minus_valid_158 && _dataflow_minus_ready_158) begin _dataflow_minus_valid_158 <= 0; end if((_dataflow_minus_ready_158 || !_dataflow_minus_valid_158) && (_dataflow_times_ready_154 && _dataflow_times_ready_155)) begin _dataflow_minus_valid_158 <= _dataflow_times_valid_154 && _dataflow_times_valid_155; end if((_dataflow_plus_ready_159 || !_dataflow_plus_valid_159) && (_dataflow_times_ready_156 && _dataflow_times_ready_157) && (_dataflow_times_valid_156 && _dataflow_times_valid_157)) begin _dataflow_plus_data_159 <= _dataflow_times_data_156 + _dataflow_times_data_157; end if(_dataflow_plus_valid_159 && _dataflow_plus_ready_159) begin _dataflow_plus_valid_159 <= 0; end if((_dataflow_plus_ready_159 || !_dataflow_plus_valid_159) && (_dataflow_times_ready_156 && _dataflow_times_ready_157)) begin _dataflow_plus_valid_159 <= _dataflow_times_valid_156 && _dataflow_times_valid_157; end if((_dataflow__delay_ready_327 || !_dataflow__delay_valid_327) && _dataflow__delay_ready_326 && _dataflow__delay_valid_326) begin _dataflow__delay_data_327 <= _dataflow__delay_data_326; end if(_dataflow__delay_valid_327 && _dataflow__delay_ready_327) begin _dataflow__delay_valid_327 <= 0; end if((_dataflow__delay_ready_327 || !_dataflow__delay_valid_327) && _dataflow__delay_ready_326) begin _dataflow__delay_valid_327 <= _dataflow__delay_valid_326; end if((_dataflow__delay_ready_351 || !_dataflow__delay_valid_351) && _dataflow__delay_ready_350 && _dataflow__delay_valid_350) begin _dataflow__delay_data_351 <= _dataflow__delay_data_350; end if(_dataflow__delay_valid_351 && _dataflow__delay_ready_351) begin _dataflow__delay_valid_351 <= 0; end if((_dataflow__delay_ready_351 || !_dataflow__delay_valid_351) && _dataflow__delay_ready_350) begin _dataflow__delay_valid_351 <= _dataflow__delay_valid_350; end if((_dataflow__delay_ready_367 || !_dataflow__delay_valid_367) && _dataflow__delay_ready_366 && _dataflow__delay_valid_366) begin _dataflow__delay_data_367 <= _dataflow__delay_data_366; end if(_dataflow__delay_valid_367 && _dataflow__delay_ready_367) begin _dataflow__delay_valid_367 <= 0; end if((_dataflow__delay_ready_367 || !_dataflow__delay_valid_367) && _dataflow__delay_ready_366) begin _dataflow__delay_valid_367 <= _dataflow__delay_valid_366; end if((_dataflow__delay_ready_383 || !_dataflow__delay_valid_383) && _dataflow__delay_ready_382 && _dataflow__delay_valid_382) begin _dataflow__delay_data_383 <= _dataflow__delay_data_382; end if(_dataflow__delay_valid_383 && _dataflow__delay_ready_383) begin _dataflow__delay_valid_383 <= 0; end if((_dataflow__delay_ready_383 || !_dataflow__delay_valid_383) && _dataflow__delay_ready_382) begin _dataflow__delay_valid_383 <= _dataflow__delay_valid_382; end if((_dataflow__delay_ready_399 || !_dataflow__delay_valid_399) && _dataflow__delay_ready_398 && _dataflow__delay_valid_398) begin _dataflow__delay_data_399 <= _dataflow__delay_data_398; end if(_dataflow__delay_valid_399 && _dataflow__delay_ready_399) begin _dataflow__delay_valid_399 <= 0; end if((_dataflow__delay_ready_399 || !_dataflow__delay_valid_399) && _dataflow__delay_ready_398) begin _dataflow__delay_valid_399 <= _dataflow__delay_valid_398; end if((_dataflow__delay_ready_415 || !_dataflow__delay_valid_415) && _dataflow__delay_ready_414 && _dataflow__delay_valid_414) begin _dataflow__delay_data_415 <= _dataflow__delay_data_414; end if(_dataflow__delay_valid_415 && _dataflow__delay_ready_415) begin _dataflow__delay_valid_415 <= 0; end if((_dataflow__delay_ready_415 || !_dataflow__delay_valid_415) && _dataflow__delay_ready_414) begin _dataflow__delay_valid_415 <= _dataflow__delay_valid_414; end if((_dataflow__delay_ready_423 || !_dataflow__delay_valid_423) && _dataflow__delay_ready_422 && _dataflow__delay_valid_422) begin _dataflow__delay_data_423 <= _dataflow__delay_data_422; end if(_dataflow__delay_valid_423 && _dataflow__delay_ready_423) begin _dataflow__delay_valid_423 <= 0; end if((_dataflow__delay_ready_423 || !_dataflow__delay_valid_423) && _dataflow__delay_ready_422) begin _dataflow__delay_valid_423 <= _dataflow__delay_valid_422; end if((_dataflow__delay_ready_431 || !_dataflow__delay_valid_431) && _dataflow__delay_ready_430 && _dataflow__delay_valid_430) begin _dataflow__delay_data_431 <= _dataflow__delay_data_430; end if(_dataflow__delay_valid_431 && _dataflow__delay_ready_431) begin _dataflow__delay_valid_431 <= 0; end if((_dataflow__delay_ready_431 || !_dataflow__delay_valid_431) && _dataflow__delay_ready_430) begin _dataflow__delay_valid_431 <= _dataflow__delay_valid_430; end if((_dataflow__delay_ready_447 || !_dataflow__delay_valid_447) && _dataflow__delay_ready_446 && _dataflow__delay_valid_446) begin _dataflow__delay_data_447 <= _dataflow__delay_data_446; end if(_dataflow__delay_valid_447 && _dataflow__delay_ready_447) begin _dataflow__delay_valid_447 <= 0; end if((_dataflow__delay_ready_447 || !_dataflow__delay_valid_447) && _dataflow__delay_ready_446) begin _dataflow__delay_valid_447 <= _dataflow__delay_valid_446; end if((_dataflow__delay_ready_463 || !_dataflow__delay_valid_463) && _dataflow__delay_ready_462 && _dataflow__delay_valid_462) begin _dataflow__delay_data_463 <= _dataflow__delay_data_462; end if(_dataflow__delay_valid_463 && _dataflow__delay_ready_463) begin _dataflow__delay_valid_463 <= 0; end if((_dataflow__delay_ready_463 || !_dataflow__delay_valid_463) && _dataflow__delay_ready_462) begin _dataflow__delay_valid_463 <= _dataflow__delay_valid_462; end if((_dataflow__delay_ready_471 || !_dataflow__delay_valid_471) && _dataflow__delay_ready_470 && _dataflow__delay_valid_470) begin _dataflow__delay_data_471 <= _dataflow__delay_data_470; end if(_dataflow__delay_valid_471 && _dataflow__delay_ready_471) begin _dataflow__delay_valid_471 <= 0; end if((_dataflow__delay_ready_471 || !_dataflow__delay_valid_471) && _dataflow__delay_ready_470) begin _dataflow__delay_valid_471 <= _dataflow__delay_valid_470; end if((_dataflow__delay_ready_479 || !_dataflow__delay_valid_479) && _dataflow__delay_ready_478 && _dataflow__delay_valid_478) begin _dataflow__delay_data_479 <= _dataflow__delay_data_478; end if(_dataflow__delay_valid_479 && _dataflow__delay_ready_479) begin _dataflow__delay_valid_479 <= 0; end if((_dataflow__delay_ready_479 || !_dataflow__delay_valid_479) && _dataflow__delay_ready_478) begin _dataflow__delay_valid_479 <= _dataflow__delay_valid_478; end if((_dataflow__delay_ready_487 || !_dataflow__delay_valid_487) && _dataflow__delay_ready_486 && _dataflow__delay_valid_486) begin _dataflow__delay_data_487 <= _dataflow__delay_data_486; end if(_dataflow__delay_valid_487 && _dataflow__delay_ready_487) begin _dataflow__delay_valid_487 <= 0; end if((_dataflow__delay_ready_487 || !_dataflow__delay_valid_487) && _dataflow__delay_ready_486) begin _dataflow__delay_valid_487 <= _dataflow__delay_valid_486; end if((_dataflow__delay_ready_495 || !_dataflow__delay_valid_495) && _dataflow__delay_ready_494 && _dataflow__delay_valid_494) begin _dataflow__delay_data_495 <= _dataflow__delay_data_494; end if(_dataflow__delay_valid_495 && _dataflow__delay_ready_495) begin _dataflow__delay_valid_495 <= 0; end if((_dataflow__delay_ready_495 || !_dataflow__delay_valid_495) && _dataflow__delay_ready_494) begin _dataflow__delay_valid_495 <= _dataflow__delay_valid_494; end end end endmodule module multiplier_0 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_0 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_0 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_1 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_1 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_1 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_2 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_2 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_2 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_3 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_3 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_3 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_4 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_4 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_4 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_5 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_5 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_5 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_6 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_6 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_6 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_7 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_7 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_7 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_8 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_8 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_8 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_9 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_9 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_9 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_10 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_10 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_10 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_11 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_11 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_11 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_12 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_12 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_12 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_13 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_13 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_13 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_14 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_14 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_14 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_15 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_15 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_15 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_16 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_16 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_16 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_17 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_17 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_17 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_18 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_18 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_18 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_19 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_19 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_19 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_20 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_20 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_20 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_21 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_21 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_21 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_22 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_22 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_22 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_23 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_23 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_23 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_24 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_24 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_24 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_25 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_25 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_25 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_26 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_26 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_26 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_27 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_27 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_27 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_28 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_28 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_28 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_29 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_29 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_29 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_30 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_30 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_30 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_31 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_31 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_31 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_32 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_32 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_32 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_33 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_33 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_33 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_34 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_34 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_34 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_35 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_35 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_35 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_36 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_36 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_36 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_37 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_37 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_37 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_38 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_38 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_38 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_39 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_39 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_39 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_40 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_40 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_40 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_41 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_41 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_41 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_42 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_42 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_42 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_43 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_43 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_43 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_44 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_44 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_44 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_45 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_45 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_45 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_46 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_46 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_46 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule module multiplier_47 ( input CLK, input RST, input update, input enable, output valid, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg valid_reg0; reg valid_reg1; reg valid_reg2; reg valid_reg3; reg valid_reg4; reg valid_reg5; assign valid = valid_reg5; always @(posedge CLK) begin if(RST) begin valid_reg0 <= 0; valid_reg1 <= 0; valid_reg2 <= 0; valid_reg3 <= 0; valid_reg4 <= 0; valid_reg5 <= 0; end else begin if(update) begin valid_reg0 <= enable; valid_reg1 <= valid_reg0; valid_reg2 <= valid_reg1; valid_reg3 <= valid_reg2; valid_reg4 <= valid_reg3; valid_reg5 <= valid_reg4; end end end multiplier_core_47 mult ( .CLK(CLK), .update(update), .a(a), .b(b), .c(c) ); endmodule module multiplier_core_47 ( input CLK, input update, input [16-1:0] a, input [16-1:0] b, output [32-1:0] c ); reg signed [16-1:0] _a; reg signed [16-1:0] _b; wire signed [32-1:0] _mul; reg signed [32-1:0] _pipe_mul0; reg signed [32-1:0] _pipe_mul1; reg signed [32-1:0] _pipe_mul2; reg signed [32-1:0] _pipe_mul3; reg signed [32-1:0] _pipe_mul4; assign _mul = _a * _b; assign c = _pipe_mul4; always @(posedge CLK) begin if(update) begin _a <= a; _b <= b; _pipe_mul0 <= _mul; _pipe_mul1 <= _pipe_mul0; _pipe_mul2 <= _pipe_mul1; _pipe_mul3 <= _pipe_mul2; _pipe_mul4 <= _pipe_mul3; end end endmodule """ def test(): veriloggen.reset() test_module = dataflow_fftN.mkTest() code = test_module.to_verilog() from pyverilog.vparser.parser import VerilogParser from pyverilog.ast_code_generator.codegen import ASTCodeGenerator parser = VerilogParser() expected_ast = parser.parse(expected_verilog) codegen = ASTCodeGenerator() expected_code = codegen.visit(expected_ast) assert(expected_code == code)

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null

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6

bab4011c411d22e59ec3f3f81ea2a592e5cdec49

24

py

Python

DSTK/tests/__init__.py

jotterbach/dstk

d371262ca09527fb8279f066b564abf5a1fe28df

[ "MIT" ]

12

2017-01-10T19:50:32.000Z

2020-03-30T20:28:31.000Z

DSTK/tests/__init__.py

jotterbach/dstk

d371262ca09527fb8279f066b564abf5a1fe28df

[ "MIT" ]

7

2016-10-12T16:21:58.000Z

2016-12-01T00:34:54.000Z

DSTK/tests/__init__.py

jotterbach/dstk

d371262ca09527fb8279f066b564abf5a1fe28df

[ "MIT" ]

8

2016-08-22T11:23:12.000Z

2020-03-13T23:18:39.000Z

from tests_gam import *

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null

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1

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6

bac9812fd861e88bc5468eacd8098f231d403575

136

py

Python

object-detector/__init__.py

pedrooct/object-detector

4fe4671b8232ffae39834d0a5da783818ac40355

[ "MIT" ]

464

2015-07-07T05:19:20.000Z

2022-03-24T23:46:41.000Z

object-detector/__init__.py

pedrooct/object-detector

4fe4671b8232ffae39834d0a5da783818ac40355

[ "MIT" ]

31

2015-08-27T20:08:31.000Z

2021-09-21T07:43:40.000Z

object-detector/__init__.py

pedrooct/object-detector

4fe4671b8232ffae39834d0a5da783818ac40355

[ "MIT" ]

260

2015-07-08T13:40:27.000Z

2022-03-11T15:22:10.000Z

from .extract-features import * from .train-classifier import * from .test-classifier import * from .nms import * from .config import *

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baca81d9c723cf88a5ca9fb9a03c04646b7ed166

27

py

Python

test_pytrain/test_Apriori/__init__.py

pytrain/pytrain-shallow

c873a6f11f1dd940da12e7c9a3c961507d064d9a

[ "MIT" ]

20

2016-09-03T10:56:06.000Z

2020-08-21T01:43:47.000Z

test_pytrain/test_Apriori/__init__.py

pytrain/pytrain

c873a6f11f1dd940da12e7c9a3c961507d064d9a

[ "MIT" ]

8

2016-11-14T12:33:38.000Z

2017-07-14T15:43:53.000Z

test_pytrain/test_Apriori/__init__.py

pytrain/pytrain

c873a6f11f1dd940da12e7c9a3c961507d064d9a

[ "MIT" ]

7

2017-02-09T16:50:37.000Z

2022-01-02T01:18:56.000Z

from test_Apriori import *

13.5

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27

5.25

1

0

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27

1

27

0.913043

0

1

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1

0

1

0

1

0

null

0

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0

null

0

1

0

1

0

1

0

6

baf16ff1c899f41a7c0a6e2ad3de36b7758dd8b5

7,921

py

Python

tests/test_mediastore/test_mediastore.py

edisongustavo/moto

ae4d20610227b46590ad248535c021208b2bfaed

[ "Apache-2.0" ]

1

2019-10-18T16:10:01.000Z

tests/test_mediastore/test_mediastore.py

edisongustavo/moto

ae4d20610227b46590ad248535c021208b2bfaed

[ "Apache-2.0" ]

1

2021-03-08T09:45:17.000Z

tests/test_mediastore/test_mediastore.py

edisongustavo/moto

ae4d20610227b46590ad248535c021208b2bfaed

[ "Apache-2.0" ]

null

from __future__ import unicode_literals import boto3 import sure # noqa import pytest from moto import mock_mediastore from botocore.exceptions import ClientError region = "eu-west-1" @mock_mediastore def test_create_container_succeeds(): client = boto3.client("mediastore", region_name=region) response = client.create_container( ContainerName="Awesome container!", Tags=[{"Key": "customer"}] ) container = response["Container"] response["ResponseMetadata"]["HTTPStatusCode"].should.equal(200) container["ARN"].should.equal( "arn:aws:mediastore:container:{}".format(container["Name"]) ) container["Name"].should.equal("Awesome container!") container["Status"].should.equal("CREATING") @mock_mediastore def test_describe_container_succeeds(): client = boto3.client("mediastore", region_name=region) create_response = client.create_container( ContainerName="Awesome container!", Tags=[{"Key": "customer"}] ) container_name = create_response["Container"]["Name"] response = client.describe_container(ContainerName=container_name) response["ResponseMetadata"]["HTTPStatusCode"].should.equal(200) container = response["Container"] container["ARN"].should.equal( "arn:aws:mediastore:container:{}".format(container["Name"]) ) container["Name"].should.equal("Awesome container!") container["Status"].should.equal("ACTIVE") @mock_mediastore def test_list_containers_succeeds(): client = boto3.client("mediastore", region_name=region) client.create_container( ContainerName="Awesome container!", Tags=[{"Key": "customer"}] ) list_response = client.list_containers(NextToken="next-token", MaxResults=123) containers_list = list_response["Containers"] len(containers_list).should.equal(1) client.create_container( ContainerName="Awesome container2!", Tags=[{"Key": "customer"}] ) list_response = client.list_containers(NextToken="next-token", MaxResults=123) containers_list = list_response["Containers"] len(containers_list).should.equal(2) @mock_mediastore def test_describe_container_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.describe_container(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_put_lifecycle_policy_succeeds(): client = boto3.client("mediastore", region_name=region) container_response = client.create_container( ContainerName="container-name", Tags=[{"Key": "customer"}] ) container = container_response["Container"] client.put_lifecycle_policy( ContainerName=container["Name"], LifecyclePolicy="lifecycle-policy" ) response = client.get_lifecycle_policy(ContainerName=container["Name"]) response["ResponseMetadata"]["HTTPStatusCode"].should.equal(200) response["LifecyclePolicy"].should.equal("lifecycle-policy") @mock_mediastore def test_put_lifecycle_policy_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.put_lifecycle_policy( ContainerName="container-name", LifecyclePolicy="lifecycle-policy" ) ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_get_lifecycle_policy_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.get_lifecycle_policy(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_get_lifecycle_policy_raises_error_if_container_does_not_have_lifecycle_policy(): client = boto3.client("mediastore", region_name=region) client.create_container(ContainerName="container-name", Tags=[{"Key": "customer"}]) with pytest.raises(ClientError) as ex: client.get_lifecycle_policy(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("PolicyNotFoundException") @mock_mediastore def test_put_container_policy_succeeds(): client = boto3.client("mediastore", region_name=region) container_response = client.create_container( ContainerName="container-name", Tags=[{"Key": "customer"}] ) container = container_response["Container"] response = client.put_container_policy( ContainerName=container["Name"], Policy="container-policy" ) response = client.get_container_policy(ContainerName=container["Name"]) response["ResponseMetadata"]["HTTPStatusCode"].should.equal(200) response["Policy"].should.equal("container-policy") @mock_mediastore def test_put_container_policy_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.put_container_policy( ContainerName="container-name", Policy="container-policy" ) ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_get_container_policy_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.get_container_policy(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_get_container_policy_raises_error_if_container_does_not_have_container_policy(): client = boto3.client("mediastore", region_name=region) client.create_container(ContainerName="container-name", Tags=[{"Key": "customer"}]) with pytest.raises(ClientError) as ex: client.get_container_policy(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("PolicyNotFoundException") @mock_mediastore def test_put_metric_policy_succeeds(): client = boto3.client("mediastore", region_name=region) container_response = client.create_container( ContainerName="container-name", Tags=[{"Key": "customer"}] ) container = container_response["Container"] response = client.put_metric_policy( ContainerName=container["Name"], MetricPolicy={"ContainerLevelMetrics": "ENABLED"}, ) response = client.get_metric_policy(ContainerName=container["Name"]) response["ResponseMetadata"]["HTTPStatusCode"].should.equal(200) response["MetricPolicy"].should.equal({"ContainerLevelMetrics": "ENABLED"}) @mock_mediastore def test_put_metric_policy_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.put_metric_policy( ContainerName="container-name", MetricPolicy={"ContainerLevelMetrics": "ENABLED"}, ) ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_get_metric_policy_raises_error_if_container_does_not_exist(): client = boto3.client("mediastore", region_name=region) with pytest.raises(ClientError) as ex: client.get_metric_policy(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("ResourceNotFoundException") @mock_mediastore def test_get_metric_policy_raises_error_if_container_does_not_have_metric_policy(): client = boto3.client("mediastore", region_name=region) client.create_container(ContainerName="container-name", Tags=[{"Key": "customer"}]) with pytest.raises(ClientError) as ex: client.get_metric_policy(ContainerName="container-name") ex.value.response["Error"]["Code"].should.equal("PolicyNotFoundException")

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0.105282

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0

1

0.1

false

0

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0

0.1375

0

null

0

1

0

null

0

6

241a50d11ffa6fe4709126b40d28348799beaa06

8,355

py

Python

tests/test_watchdog.py

NiWaRe/deepee

98b5cd09f356f4a597fe204799a524c4d444dd2d

[ "Apache-2.0" ]

16

2021-03-24T09:50:32.000Z

2022-03-10T12:03:37.000Z

tests/test_watchdog.py

NiWaRe/deepee

98b5cd09f356f4a597fe204799a524c4d444dd2d

[ "Apache-2.0" ]

4

2021-03-27T09:36:20.000Z

2021-10-18T09:30:47.000Z

tests/test_watchdog.py

NiWaRe/deepee

98b5cd09f356f4a597fe204799a524c4d444dd2d

[ "Apache-2.0" ]

4

2021-06-24T08:30:47.000Z

2021-11-09T08:33:57.000Z

from deepee.watchdog import PrivacyBudgetExhausted from deepee import PrivacyWatchdog, UniformDataLoader, PrivacyWrapper from deepee.dataloader import UniformWORSubsampler from torch.utils.data import DataLoader, Dataset import torch import pytest from testfixtures import LogCapture class DS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 5 dl = DataLoader(DS()) udl = UniformDataLoader(DS(), 1) bsdl = DataLoader(DS(), batch_sampler=UniformWORSubsampler(DS(), 5)) def test_uniform_dl(): with LogCapture() as l: watchdog = PrivacyWatchdog(udl, target_delta=1e-5, target_epsilon=1.0) watchdog2 = PrivacyWatchdog(bsdl, target_delta=1e-5, target_epsilon=1.0) watchdog2 = PrivacyWatchdog(dl, target_delta=1e-5, target_epsilon=1.0) assert "CRITICAL" and "replacement" in str(l) def test_epsilon_delta_positive(): with pytest.raises(ValueError): watchdog = PrivacyWatchdog(udl, target_delta=1e-5, target_epsilon=None) with pytest.raises(ValueError): watchdog = PrivacyWatchdog(udl, target_delta=None, target_epsilon=1.0) with pytest.raises(ValueError): watchdog = PrivacyWatchdog(udl, target_delta=1.2, target_epsilon=1.0) with pytest.raises(ValueError): watchdog = PrivacyWatchdog(udl, target_delta=1.2, target_epsilon=1.0) with pytest.raises(ValueError): watchdog = PrivacyWatchdog(udl, target_delta=1e-5, target_epsilon=-4) def test_warn_without_save_or_path(): with LogCapture() as l: watchdog = PrivacyWatchdog( udl, target_delta=1e-5, target_epsilon=1.0, abort=False, save=True, ) assert "WARNING" and "ignored" in str(l) with LogCapture() as l: watchdog = PrivacyWatchdog( udl, target_delta=1e-5, target_epsilon=1.0, abort=False, save=False, path="somepath", ) assert "WARNING" and "ignored" in str(l) def test_save_fails_without_path(): """User asked for save without specifying path""" with pytest.raises(ValueError): watchdog = PrivacyWatchdog( udl, target_delta=1e-5, target_epsilon=1.0, abort=True, save=True, path=None ) def test_inform(): """Test reporting of epsilon""" class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, ) class FakeWrapper: noise_multiplier = 1.0 watchdog.wrapper = FakeWrapper with LogCapture() as l: watchdog.inform(1) assert "Privacy spent at 1 steps" in str(l) def test_orphan_watchdog(): """Watchdog not attached""" dl = UniformDataLoader(udl, batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, ) with pytest.raises(RuntimeError): watchdog.inform(1) def test_abort_training(): class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, abort=True ) class FakeWrapper: noise_multiplier = 1.0 watchdog.wrapper = FakeWrapper with pytest.raises(PrivacyBudgetExhausted): watchdog.inform(50000) def test_log_exhausted(): class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, abort=False ) class FakeWrapper: noise_multiplier = 1.0 watchdog.wrapper = FakeWrapper with LogCapture() as l: watchdog.inform(50000) assert "WARNING" and "exhausted" in str(l) def test_wrapper_returns_epsilon(): class MiniModel(torch.nn.Module): def __init__(self): super().__init__() self.lin = torch.nn.Linear(10, 1) def forward(self, x): return self.lin(x) class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, abort=False ) data = torch.randn(2, 1, 10) wrapped = PrivacyWrapper(MiniModel(), 2, 1.0, 1.0, watchdog=watchdog) epsila = [] # this one's for you @a1302z for _ in range(5): output = wrapped(data) loss = output.mean() loss.backward() wrapped.clip_and_accumulate() wrapped.noise_gradient() wrapped.prepare_next_batch() epsila.append(wrapped.current_epsilon) assert len(epsila) == 5 and None not in epsila def test_fallback_warning(): class MiniModel(torch.nn.Module): def __init__(self): super().__init__() self.lin = torch.nn.Linear(10, 1) def forward(self, x): return self.lin(x) class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) with LogCapture() as l: watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, abort=False, fallback_to_rdp=True, ) assert "CRITICAL" and "RDP" in str(l) def test_fallback_works(): class MiniModel(torch.nn.Module): def __init__(self): super().__init__() self.lin = torch.nn.Linear(10, 1) def forward(self, x): return self.lin(x) class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, abort=False, fallback_to_rdp=True, ) data = torch.randn(2, 1, 10) wrapped = PrivacyWrapper(MiniModel(), 2, 10, 0.001, watchdog=watchdog) epsila = [] # this one's for you @a1302z for _ in range(5): output = wrapped(data) loss = output.mean() loss.backward() wrapped.clip_and_accumulate() wrapped.noise_gradient() epsilon = wrapped.prepare_next_batch() epsila.append(epsilon) assert len(epsila) == 5 def test_no_fallback_crashes(): class MiniModel(torch.nn.Module): def __init__(self): super().__init__() self.lin = torch.nn.Linear(10, 1) def forward(self, x): return self.lin(x) class BigDS(Dataset): def __getitem__(self, idx): return torch.rand( 1, ) def __len__(self): return 50_000 dl = UniformDataLoader(BigDS(), batch_size=200) watchdog = PrivacyWatchdog( dl, report_every_n_steps=1, target_delta=1e-5, target_epsilon=1.0, abort=False, fallback_to_rdp=False, ) data = torch.randn(2, 1, 10) wrapped = PrivacyWrapper(MiniModel(), 2, 10, 0.001, watchdog=watchdog) with pytest.raises(RuntimeError): output = wrapped(data) loss = output.mean() loss.backward() wrapped.clip_and_accumulate() wrapped.noise_gradient() wrapped.prepare_next_batch()

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null

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6

244c12fcb46fcd868b6be755180aa9162f6650a5

48

py

Python

ezlog/__init__.py

eiva/ezlog

47aba57ebf69dd55b2c18d5f8a11396f59071ea0

[ "MIT" ]

null

ezlog/__init__.py

eiva/ezlog

47aba57ebf69dd55b2c18d5f8a11396f59071ea0

[ "MIT" ]

null

ezlog/__init__.py

eiva/ezlog

47aba57ebf69dd55b2c18d5f8a11396f59071ea0

[ "MIT" ]

null

from .wrappers import log_call, log_member_call

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6

246a50d8ac22a7e1ab54799c89a214b8e9a37bff

859

py

Python

ark_nlp/model/tc/bert/__init__.py

confstantine/nlp-task

cb152e885bc6f6f1243a12ad90b1c715eb548736

[ "Apache-2.0" ]

1

2021-12-27T04:48:40.000Z

ark_nlp/model/tc/bert/__init__.py

confstantine/nlp-task

cb152e885bc6f6f1243a12ad90b1c715eb548736

[ "Apache-2.0" ]

null

ark_nlp/model/tc/bert/__init__.py

confstantine/nlp-task

cb152e885bc6f6f1243a12ad90b1c715eb548736

[ "Apache-2.0" ]

1

2021-12-27T04:49:35.000Z

from ark_nlp.dataset import SentenceClassificationDataset as Dataset from ark_nlp.dataset import SentenceClassificationDataset as BertTCDataset from ark_nlp.processor.tokenizer.transfomer import SentenceTokenizer as Tokenizer from ark_nlp.processor.tokenizer.transfomer import SentenceTokenizer as BertTCTokenizer from ark_nlp.nn import BertConfig as BertConfig from ark_nlp.nn import Bert from ark_nlp.factory.optimizer import get_default_bert_optimizer as get_default_model_optimizer from ark_nlp.factory.optimizer import get_default_bert_optimizer as get_default_bert_optimizer from ark_nlp.factory.task import SequenceClassificationTask as Task from ark_nlp.factory.task import SequenceClassificationTask as BertTCTask from ark_nlp.factory.predictor import TCPredictor as Predictor from ark_nlp.factory.predictor import TCPredictor as BertTCPredictor

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6

03122c1caa10ce78558aac22cb7a375f52e24ce0

19,242

py

Python

mygrid/short_circuit/phase_components.py

grei-ufc/MyGrid

c42fe9d4e0838f253dd5b0716cbf0c892136d931

[ "MIT" ]

3

2018-03-02T11:18:51.000Z

2021-07-30T23:22:18.000Z

mygrid/short_circuit/phase_components.py

grei-ufc/MyGrid

c42fe9d4e0838f253dd5b0716cbf0c892136d931

[ "MIT" ]

8

2017-11-06T12:15:15.000Z

2019-04-29T13:41:27.000Z

mygrid/short_circuit/phase_components.py

grei-ufc/MyGrid

c42fe9d4e0838f253dd5b0716cbf0c892136d931

[ "MIT" ]

4

2019-03-20T11:26:04.000Z

2021-06-03T19:28:05.000Z

import numpy as np import copy from mygrid.grid import Section,TransformerModel, Auto_TransformerModel import pandas as pd """ This scripts allows the user to calculate the unbalanced short-circuits on radial distribution systems modeled on mygrid. """ def biphasic(distgrid, node_name, fs='Higher',Df=False, zc=0+0j): """ Calculates the two-phase short circuit Parameters ---------- distgrid: mygrid.grid.DistGrid node_name: str The name of node fault fs: str Designates which phases participate in the short circuit Options: 'Iab', 'Iac', 'Ibc' and 'Higher'. Df: bool Indicates whether the function returns a dataframe or a dictionary. If true the function returns a DataFrame. zc: complex Contact Impedance Returns: Dict or a DataFrame """ zz=dict() zus,zpus=upstream_area(distgrid, node_name) zds,zpds=downstream_area(distgrid, node_name) Xab=np.zeros((3,1), dtype=complex) Xac=np.zeros((3,1), dtype=complex) Xbc=np.zeros((3,1), dtype=complex) voltage_source=voltage(distgrid,node_name) zz.update(zpus) zz.update(zpds) l=0+0j for i in [zds, zus]: if type(i) != type(None): l += np.linalg.inv(i) l=np.linalg.inv(l)+zc C=calc_c(l) Cab=copy.copy(C) Cac=copy.copy(C) Cbc=copy.copy(C) Cab[3,3]=Cab[4,4]=1 Cab[6,0]=Cab[6,1]=Cab[5,2]=1 Cac[3,3]=Cac[5,5]=1 Cac[6,0]=Cac[6,2]=Cac[4,1]=1 Cbc[4,4]=Cbc[5,5]=1 Cbc[6,1]=Cbc[6,2]=Cbc[3,0]=1 IPS=np.zeros((7,1),dtype=complex) IPS[0:3,0:1]=np.linalg.inv(l).dot(voltage_source) Xab +=np.linalg.inv(Cab).dot(IPS)[0:3] Xac +=np.linalg.inv(Cac).dot(IPS)[0:3] Xbc +=np.linalg.inv(Cbc).dot(IPS)[0:3] If={'Fab': {'Ifa':Xab[0,0],'Ifb':Xab[1,0],'Ifc':Xab[2,0]}, 'Fac': {'Ifa':Xac[0,0],'Ifb':Xac[1,0],'Ifc':Xac[2,0]}, 'Fbc': {'Ifa':Xbc[0,0],'Ifb':Xbc[1,0],'Ifc':Xbc[2,0]}} If=pd.DataFrame(If) erase=None if fs =='Higher': fs=If.abs().max().idxmax() if fs=='Fac': Iz=If['Fac'] erase=[1] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) elif fs=='Fab': Iz=If['Fab'] erase=[2] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) elif fs == 'Fbc': Iz=If['Fbc'] erase=[0] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) if Df: ict=dict_to_DataFrame(ict) return ict def biphasic_to_ground(distgrid,node_name, fs='Higher',Df=False, zc=0+0j): """ Calculates the two-phase-grounded short circuit Parameters ---------- distgrid: mygrid.grid.DistGrid node_name: str The name of node fault fs: str Designates which phases participate in the short circuit Options: 'Iab', 'Iac', 'Ibc' and 'Higher'. Df: bool Indicates whether the function returns a dataframe or a dictionary. If true the function returns a DataFrame. zc: complex Contact Impedance Returns: Dict or a DataFrame """ zz=dict() zus,zpus=upstream_area(distgrid, node_name) zds,zpds=downstream_area(distgrid, node_name) zz.update(zpus) zz.update(zpds) Xab=np.zeros((3,1), dtype=complex) Xac=np.zeros((3,1), dtype=complex) Xbc=np.zeros((3,1), dtype=complex) voltage_source=voltage(distgrid,node_name) l=0+0j for i in [zds, zus]: if type(i) != type(None): l += np.linalg.inv(i) l=np.linalg.inv(l)+zc C=calc_c(l) Cab=copy.copy(C) Cac=copy.copy(C) Cbc=copy.copy(C) Cab[3,3]=Cab[4,4]=Cab[6,6]=1 Cab[5,2]=1 Cac[3,3]=Cac[5,5]=Cac[6,6]=1 Cac[4,1]=1 Cbc[4,4]=Cbc[5,5]=Cbc[6,6]=1 Cbc[3,0]=1 IPS=np.zeros((7,1),dtype=complex) IPS[0:3,0:1]=np.linalg.inv(l).dot(voltage_source) Xab +=np.linalg.inv(Cab).dot(IPS)[0:3] Xac +=np.linalg.inv(Cac).dot(IPS)[0:3] Xbc +=np.linalg.inv(Cbc).dot(IPS)[0:3] If={'Fabg': {'Ifa':Xab[0,0],'Ifb':Xab[1,0],'Ifc':Xab[2,0]}, 'Facg': {'Ifa':Xac[0,0],'Ifb':Xac[1,0],'Ifc':Xac[2,0]}, 'Fbcg': {'Ifa':Xbc[0,0],'Ifb':Xbc[1,0],'Ifc':Xbc[2,0]}} If=pd.DataFrame(If) if fs =='Higher': fs=If.abs().max().idxmax() if fs=='Facg': Iz=If['Facg'] erase=[1] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) elif fs=='Fabg': Iz=If['Fabg'] erase=[2] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) elif fs == 'Fbcg': Iz=If['Fbcg'] erase=[0] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) if Df: ict=dict_to_DataFrame(ict) return ict def three_phase_to_ground(distgrid,node_name,Df=False, zc=0+0j): """ Calculates the three-phase-grounded short circuit Parameters ---------- distgrid: mygrid.grid.DistGrid node_name: str The name of node fault fs: str Designates which phases participate in the short circuit Options: 'Iab', 'Iac', 'Ibc' and 'Higher'. Df: bool Indicates whether the function returns a dataframe or a dictionary. If true the function returns a DataFrame. zc: complex Contact Impedance Returns: Dict or a DataFrame """ zz=dict() zus,zpus=upstream_area(distgrid, node_name) zds, zpds=downstream_area(distgrid, node_name) zz.update(zpus) zz.update(zpds) X=np.zeros((3,1), dtype=complex) voltage_source=voltage(distgrid,node_name) l=0+0j for i in [zds, zus]: if type(i) != type(None): l += np.linalg.inv(i) l=np.linalg.inv(l)+zc C=calc_c(l) C[3,3]=C[4,4]=C[5,5]=C[6,6]=1 IPS=np.zeros((7,1),dtype=complex) IPS[0:3,0:1]=np.linalg.inv(l).dot(voltage_source) X +=np.linalg.inv(C).dot(IPS)[0:3] If={'Fabcg': {'Ifa':X[0,0],'Ifb':X[1,0],'Ifc':X[2,0]}} If=pd.DataFrame(If) ict=calc_contributions(zz,np.array(If).reshape(3,1),node_name,distgrid, ep=[]) if Df: ict=dict_to_DataFrame(ict) return ict def three_phase(distgrid,node_name,Df=False, zc=0+0j): """ Calculates the three-phase short circuit Parameters ---------- distgrid: mygrid.grid.DistGrid node_name: str The name of node fault Df: bool Indicates whether the function returns a dataframe or a dictionary. If true the function returns a DataFrame. zc: complex Contact Impedance Returns: Dict or a DataFrame """ zz=dict() zus,zpus=upstream_area(distgrid, node_name) zds,zpds=downstream_area(distgrid, node_name) zz.update(zpus) zz.update(zpds) X=np.zeros((3,1), dtype=complex) voltage_source=voltage(distgrid,node_name) l=0+0j for i in [zds, zus]: if type(i) != type(None): l += np.linalg.inv(i) l=np.linalg.inv(l)+zc C=calc_c(l) C[3,3]=C[4,4]=C[5,5]=1 C[6,0]=C[6,1]=C[6,2]=1 IPS=np.zeros((7,1),dtype=complex) IPS[0:3,0:1]=np.linalg.inv(l).dot(voltage_source) X +=np.linalg.inv(C).dot(IPS)[0:3] If={'Fabc': {'Ifa':X[0,0],'Ifb':X[1,0],'Ifc':X[2,0]}} If=pd.DataFrame(If) ict=calc_contributions(zz,np.array(If).reshape(3,1),node_name,distgrid,ep=[]) if Df: ict=dict_to_DataFrame(ict) return ict def mono_phase(distgrid,node_name,zf=0, fs='Higher',Df=False, zc=0+0j): """ Calculates the mono-phase short circuit Parameters ---------- distgrid: mygrid.grid.DistGrid node_name: str The name of node fault fs: str Designates which phases participate in the short circuit Options: 'Ia', 'Ia', 'Ib' and 'Higher'. Df: bool Indicates whether the function returns a dataframe or a dictionary. If true the function returns a DataFrame. zc: complex Contact Impedance Returns: Dict or a DataFrame """ zz=dict() zus,zpus=upstream_area(distgrid, node_name) zds,zpds=downstream_area(distgrid, node_name) zz.update(zpus) zz.update(zpds) Xa=np.zeros((3,1), dtype=complex) Xb=np.zeros((3,1), dtype=complex) Xc=np.zeros((3,1), dtype=complex) voltage_source=voltage(distgrid,node_name) l=0+0j for i in [zds, zus]: if type(i) != type(None): l += np.linalg.inv(i) l=np.linalg.inv(l)+zc C=calc_c(l) Ca=copy.copy(C) Cb=copy.copy(C) Cc=copy.copy(C) Ca[3,3]=Ca[6,6]=1 Ca[4,1]=Ca[5,2]=1 Cb[4,4]=Cb[6,6]=1 Cb[3,0]=Cb[5,2]=1 Cc[5,5]=Cc[6,6]=1 Cc[3,0]=Cc[4,1]=1 IPS=np.zeros((7,1),dtype=complex) IPS[0:3,0:1]=np.linalg.inv(l).dot(voltage_source) Xa+=np.linalg.inv(Ca).dot(IPS)[0:3] Xb+=np.linalg.inv(Cb).dot(IPS)[0:3] Xc+=np.linalg.inv(Cc).dot(IPS)[0:3] If={'Fag': {'Ifa':Xa[0,0],'Ifb':Xa[1,0],'Ifc':Xa[2,0]}, 'Fbg': {'Ifa':Xb[0,0],'Ifb':Xb[1,0],'Ifc':Xb[2,0]}, 'Fcg': {'Ifa':Xc[0,0],'Ifb':Xc[1,0],'Ifc':Xc[2,0]}} If=pd.DataFrame(If) if fs =='Higher': fs=If.abs().max().idxmax() if fs=='Fag': Iz=If['Fag'] erase=[1,2] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) elif fs=='Fbg': Iz=If['Fbg'] erase=[0,2] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) elif fs == 'Fcg': Iz=If['Fcg'] erase=[0,1] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid,ep=erase) if Df: ict=dict_to_DataFrame(ict) return ict def min_mono_phase(distgrid,node_name,zf=0, zt=40, fs='Higher',Df=False, zc=0+0j): """ Calculates the min-mono-phase short circuit Parameters ---------- distgrid: mygrid.grid.DistGrid node_name: str The name of node fault fs: str Designates which phases participate in the short circuit Options: 'Ia', 'Ia', 'Ib' and 'Higher'. Df: bool Indicates whether the function returns a dataframe or a dictionary. If true the function returns a DataFrame. zc: complex Contact Impedance Returns: Dict or a DataFrame """ zz=dict() zus,zpus=upstream_area(distgrid, node_name) zds,zpds=downstream_area(distgrid, node_name) zz.update(zpus) zz.update(zpds) Xa=np.zeros((3,1), dtype=complex) Xb=np.zeros((3,1), dtype=complex) Xc=np.zeros((3,1), dtype=complex) voltage_source=voltage(distgrid,node_name) l=0+0j for i in [zds, zus]: if type(i) != type(None): l += np.linalg.inv(i) l=np.linalg.inv(l+zc) C=calc_c(l+zt) Ca=copy.copy(C) Cb=copy.copy(C) Cc=copy.copy(C) Ca[3,3]=Ca[6,6]=1 Ca[4,1]=Ca[5,2]=1 Cb[4,4]=Cb[6,6]=1 Cb[3,0]=Cb[5,2]=1 Cc[5,5]=Cc[6,6]=1 Cc[3,0]=Cc[4,1]=1 IPS=np.zeros((7,1),dtype=complex) IPS[0:3,0:1]=np.linalg.inv(l).dot(voltage_source) Xa+=np.linalg.inv(Ca).dot(IPS)[0:3] Xb+=np.linalg.inv(Cb).dot(IPS)[0:3] Xc+=np.linalg.inv(Cc).dot(IPS)[0:3] If={'Fag_min': {'Ifa':Xa[0,0],'Ifb':Xa[1,0],'Ifc':Xa[2,0]}, 'Fbg_min': {'Ifa':Xb[0,0],'Ifb':Xb[1,0],'Ifc':Xb[2,0]}, 'Fcg_min': {'Ifa':Xc[0,0],'Ifb':Xc[1,0],'Ifc':Xc[2,0]}} If=pd.DataFrame(If) if fs =='Higher': fs=If.abs().max().idxmax() elif fs=='Fag_min': Iz=If['Fag_min'] erase=[1,2] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid ,ep=erase) elif fs=='Fbg_min': Iz=If['Fbg_min'] erase=[0,2] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid ,ep=erase) elif fs == 'Fcg_min': Iz=If['Fcg_min'] erase=[1,0] ict=calc_contributions(zz,np.array(Iz).reshape(3,1),node_name,distgrid ,ep=erase) if Df: ict=dict_to_DataFrame(ict) return ict def calc_c(l): C=np.zeros((7,7),dtype=complex) C[0,0]=C[1,1]=C[2,2]=1 l=np.linalg.inv(l) C[0:3,3:6]=l C[0,6]=np.sum(l[0,0:3]) C[1,6]=np.sum(l[1,0:3]) C[2,6]=np.sum(l[2,0:3]) return C def voltage(distgrid,node_name): loads=distgrid.load_nodes loads_path=distgrid.load_nodes_tree.node_to_root_path(node_name) voltage_source=loads[distgrid.load_nodes_tree.root].vp i=len(loads_path[0,0:])-1 while i >=1 : n1=loads[loads_path[1,i]] n2=loads[loads_path[1,i-1]] section=distgrid.sections_by_nodes[(n1,n2)] if isinstance(section.transformer, TransformerModel): voltage_source=section.A.dot(voltage_source) i-=1 return voltage_source def downstream_area(distgrid, node_name): tree=distgrid.load_nodes_tree.tree rnp=distgrid.load_nodes_tree.rnp.tolist() z, pp=resolve_downstream_area(distgrid, node_name, tree, rnp) return z,pp def upstream_area(distgrid, node_name): tree=distgrid.load_nodes_tree.tree rnp=distgrid.load_nodes_tree.rnp.tolist() z, pp=resolve_upstream_area(distgrid, node_name, tree, rnp) return z,pp def resolve_upstream_area(distgrid, n1, tree, rnp, nf=False): zpll=list() zp=dict() ds_neighbors=list() load_nodes=distgrid.load_nodes n1_depth=int(rnp[:][0][rnp[:][1].index(n1)]) n1=load_nodes[n1] for i in distgrid.load_nodes_tree.tree[n1.name]: if int(rnp[:][0][rnp[:][1].index(i)]) > n1_depth: ds_neighbors.append(load_nodes[i]) if len(ds_neighbors)!=0: if n1.generation != None: if type(n1.generation) == type(list()): for i in n1.generation: zpll.append(n1.generation.Z) zpll=inv_Z(zpll) zp[n1]=zpll else: zpll.append(n1.generation.Z) zp[n1]=n1.generation.Z for i in ds_neighbors: a, pp=resolve_upstream_area(distgrid, i.name, tree, rnp, nf=True) zp.update(pp) if type(a) == type(None): continue else: zeq=0 if (n1, i) in distgrid.sections_by_nodes.keys(): zeq = distgrid.sections_by_nodes[(n1, i)] if isinstance(zeq.transformer, TransformerModel): a= zeq.a.dot(a+zeq.transformer.z).dot(zeq.d) zpll.append(a) elif isinstance(zeq.transformer, Auto_TransformerModel): a= zeq.a.dot(a).dot(zeq.d) zpll.append(a) else: a=zeq.Z + a zpll.append(a) zp[n1,i] = a if len(zpll) == 0: return None, zp elif len(zpll) == 1 and n1.generation != None: zp[n1]=inv_Z(zpll) return zp[n1], zp else: return inv_Z(zpll), zp else: if n1.generation !=None: if type(n1.generation) == type(list()): for i in n1.generation: zpll.append(i.Z) zpll=inv_Z(zpll) zp[n1]=zpll return zpll, zp else: zp[n1]=n1.generation.Z return n1.generation.Z, zp else: return None, zp def inv_Z(zpll): zeq=0 if len(zpll) !=1: for i in zpll: if np.all(i==0): zeq=0 break else: zeq +=np.linalg.inv(i) if np.all(zeq == 0): return zeq else: zeq = np.linalg.inv(zeq) return zeq else: return zpll[0] def resolve_downstream_area(distgrid, n1, tree, rnp, n2=None, nf=False): zpll=list() zp=dict() up_neighbor=None ds_neighbors=list() load_nodes=distgrid.load_nodes n1_depth=int(rnp[:][0][rnp[:][1].index(n1)]) n1=load_nodes[n1] if n1_depth !=0: for i in distgrid.load_nodes_tree.tree[n1.name]: if int(rnp[:][0][rnp[:][1].index(i)]) < n1_depth: up_neighbor=load_nodes[i] break a, pp=resolve_downstream_area(distgrid, up_neighbor.name, tree, rnp, n2=n1.name, nf=True) zp.update(pp) if type(a) != type(None): zeq=0 if (up_neighbor, n1) in distgrid.sections_by_nodes.keys(): zeq = distgrid.sections_by_nodes[(up_neighbor, n1)] if isinstance(zeq.transformer, TransformerModel): a = zeq.A.dot(a).dot(zeq.d) + zeq.transformer.z zpll.append(a) elif isinstance(zeq.transformer, Auto_TransformerModel): a = zeq.A.dot(a).dot(zeq.d) + zeq.transformer.zz zpll.append(a) else: a=zeq.Z + a zpll.append(a) zp[up_neighbor, n1] = a if n1.generation != None and nf: if type(n1.generation) == type(list()): for i in n1.generation: zpll.append(i.Z) zp[n1]=zpll else: zpll.append(n1.generation.Z) zp[n1]=zpll if n1.external_grid != None: zpll.append(n1.external_grid.Z) zp[n1]=zpll if nf: for i in distgrid.load_nodes_tree.tree[n1.name]: if int(rnp[:][0][rnp[:][1].index(i)]) > n1_depth and (i != n2): ds_neighbors.append(load_nodes[i]) if len(ds_neighbors) !=0: for i in ds_neighbors: a,pp=resolve_upstream_area(distgrid, i.name, tree, rnp) zp.update(pp) if type(a) == type(None): continue else: zeq=0 if (n1, i) in distgrid.sections_by_nodes.keys(): zeq = distgrid.sections_by_nodes[(n1, i)] if isinstance(zeq.transformer, TransformerModel): a= zeq.a.dot(a+zeq.transformer.z).dot(zeq.d) zpll.append(a) elif isinstance(zeq.transformer, Auto_TransformerModel): a= zeq.a.dot(a + zeq.transformer.zz).dot(zeq.d) zpll.append(a) else: a=zeq.Z + a zpll.append(a) zp[n1,i] = a if len(zpll) == 0: return None, zp if len(zpll) == 1: return zpll[0], zp else: zeq=0 for i in zpll: if i.any()==0: zeq=i return zeq, zp zeq +=np.linalg.inv(i) zeq = np.linalg.inv(zeq) return zeq, zp def calc_contributions(zz,Iz,nodes,distgrid,ep): tree=distgrid.load_nodes_tree.tree ln=distgrid.load_nodes nodes=[ln[nodes]] ict=dict() visit_nodes=list() iz_nodes=dict() iz_nodes[nodes[0].name]=[Iz,ep] ict[nodes[0].name]=Iz root_name=distgrid.load_nodes_tree.root while len(nodes) !=0: next_nodes=list() for i in nodes: stop=False adjacent_nodes=[ln[x] for x in tree[i.name] if ln[x] not in visit_nodes] isl=dict() inv=np.zeros((3,3), dtype=complex) p=0 if i.generation !=None: if type(i.generation)==type(list()): ep_n=iz_nodes[i.name][1] for j in i. generation: p=np.linalg.inv(vectorize_zz(j.Z,iz_nodes[i.name][1])) isl[j.name]=[p,None] inv +=p else: ep_n=iz_nodes[i.name][1] p=np.linalg.inv(i.generation.Z) isl[i.generation.name]=[p,None] inv +=p if i.name==root_name: if i.external_grid.Z.all()==0: stop=True else: ep_n=iz_nodes[i.name][1] p=np.linalg.inv(i.external_grid.Z) isl[i.external_grid.name]=[p,None] inv +=p if not(stop): for j in adjacent_nodes: p=0 if (i, j) in zz.keys(): section=distgrid.sections_by_nodes[(i,j)] next_nodes.append(j) p=np.linalg.inv(vectorize_zz(zz[(i,j)].round(6), iz_nodes[i.name][1])) if isinstance(section.transformer,TransformerModel): ep_n = new_phase_erase(section.transformer.connection,iz_nodes[i.name][1]) isl[j.name] = [p, section.a] elif isinstance(section.transformer, Auto_TransformerModel): ep_n = new_phase_erase(section.transformer.connection,iz_nodes[i.name][1]) isl[j.name] = [p, section.a] else: ep_n=iz_nodes[i.name][1] isl[j.name] = [p, None] inv += p elif (j, i) in zz.keys(): section=distgrid.sections_by_nodes[(j,i)] next_nodes.append(j) p=np.linalg.inv(vectorize_zz(zz[(j,i)].round(6), ep)) if isinstance(section.transformer,TransformerModel): ep_n = new_phase_erase(section.transformer.connection,iz_nodes[i.name][1]) isl[j.name] = [p, section.d] elif isinstance(section.transformer, Auto_TransformerModel): ep_n = new_phase_erase(section.transformer.connection,iz_nodes[i.name][1]) isl[j.name] = [p, section.d] else: ep_n=iz_nodes[i.name][1] isl[j.name] = [p, None] inv += p if len(isl) !=0: z=np.linalg.inv(inv) for y in isl.keys(): izz=isl[y][0].dot(z).dot(iz_nodes[i.name][0]) if type(isl[y][1]) != type(None): izz=isl[y][1].dot(izz) if y[0]=="GD": iz_nodes[y] = [izz,ep_n] ict[y] = izz else: iz_nodes[y] = [izz, ep_n] ict[y] = izz visit_nodes.extend(nodes) nodes=next_nodes return ict def vectorize_zz(value,phase_erase=None): for i in phase_erase: value[:,i]=0 value[i,:]=0 value[i,i]=10e9 return value def dict_to_DataFrame(ict): for i in ict.keys(): ict[i]=ict[i].reshape(1,3,).tolist()[0] ict=pd.DataFrame(ict) return ict def new_phase_erase(tf_type,old_phase_erase): pr=[0,1,2] if tf_type == "Dyn": if len(old_phase_erase)==2: pr.remove(old_phase_erase[0]) pr.remove(old_phase_erase[1]) return pr elif len(old_phase_erase)==1: return [] else: return []

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0319bd2989808e5d20cd1adfecc9b7f82e942bd1

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py

Python

django/tests/bitcoin_monitor/test_tasks.py

chanhosuh/bitcoin-monitor

acecfcf020cf2debfdf3a2e8c446007d7412d8e1

[ "MIT" ]

1

2020-01-01T15:54:45.000Z

django/tests/bitcoin_monitor/test_tasks.py

chanhosuh/bitcoin-monitor

acecfcf020cf2debfdf3a2e8c446007d7412d8e1

[ "MIT" ]

13

2019-02-28T03:24:54.000Z

2021-09-22T17:50:00.000Z

django/tests/bitcoin_monitor/test_tasks.py

chanhosuh/bitcoin-monitor

acecfcf020cf2debfdf3a2e8c446007d7412d8e1

[ "MIT" ]

null

from django.test.testcases import TestCase class ProcessBlockchainTest(TestCase): pass

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034c5310cbe4c5b96dca0769da16ec02eba17fe9

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py

Python

utils/__init__.py

IST-DASLab/ACDC

ac53210b6adc1f2506ff909de08172ed9cad25d5

[ "Apache-2.0" ]

6

2021-11-26T01:21:03.000Z

2022-01-10T15:41:50.000Z

utils/__init__.py

IST-DASLab/ACDC

ac53210b6adc1f2506ff909de08172ed9cad25d5

[ "Apache-2.0" ]

1

2021-11-28T10:51:08.000Z

2021-11-30T01:30:29.000Z

utils/__init__.py

IST-DASLab/ACDC

ac53210b6adc1f2506ff909de08172ed9cad25d5

[ "Apache-2.0" ]

1

2021-12-21T13:25:43.000Z

from utils.utils import * from utils.parse_config import * from utils.masking_utils import * from utils.datasets import * from utils.checkpoints import * from utils.approximation import * from utils.auto_augmentation import * from utils.flop_utils import *

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036e8cd61cc156dded488b2f6b43cea5d9d146f6

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py

Python

src/core/settings/local.py

thibault/pomodoro_api

5ed4ecd8469f4ccf50246bdaa5421fa6c8042e66

[ "MIT" ]

null

src/core/settings/local.py

thibault/pomodoro_api

5ed4ecd8469f4ccf50246bdaa5421fa6c8042e66

[ "MIT" ]

null

src/core/settings/local.py

thibault/pomodoro_api

5ed4ecd8469f4ccf50246bdaa5421fa6c8042e66

[ "MIT" ]

null

from core.settings.base import * # noqa

20.5

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6

cee9fb9e2160fb5de225907dd20b5378aab8b769

2,487

py

Python

tests/test_itemloader.py

MIPT-Oulu/Collagen

0cbc4285d60e5c9fcc89f629fcf4321e80b7452c

[ "MIT" ]

4

2019-05-14T14:44:51.000Z

2020-03-13T08:37:48.000Z

tests/test_itemloader.py

MIPT-Oulu/Collagen

0cbc4285d60e5c9fcc89f629fcf4321e80b7452c

[ "MIT" ]

26

2019-04-21T20:35:22.000Z

2022-03-12T00:32:57.000Z

tests/test_itemloader.py

MIPT-Oulu/Collagen

0cbc4285d60e5c9fcc89f629fcf4321e80b7452c

[ "MIT" ]

1

2019-05-14T14:53:28.000Z

import itertools from collagen.data import ItemLoader from .fixtures import * @pytest.mark.parametrize('batch_size, n_samples', itertools.product([32, 11, 3], [1, 3, 6])) def test_loader_samples_batches(batch_size, n_samples, metadata_fname_target_5_classes, ones_image_parser, img_target_transformer): iterm_loader = ItemLoader(meta_data=metadata_fname_target_5_classes, root='/tmp/', batch_size=batch_size, parse_item_cb=ones_image_parser, transform=img_target_transformer, shuffle=True) samples = iterm_loader.sample(n_samples) assert len(samples) == n_samples assert samples[0]['img'].size(0) == batch_size assert samples[0]['target'].size(0) == batch_size @pytest.mark.parametrize('batch_size, n_samples', itertools.product([8], [5, 25])) def test_loader_endless_sampling_works(batch_size, n_samples, metadata_fname_target_5_classes, ones_image_parser, img_target_transformer): iterm_loader = ItemLoader(meta_data=metadata_fname_target_5_classes, root='/tmp/', batch_size=batch_size, parse_item_cb=ones_image_parser, transform=img_target_transformer, shuffle=True) for i in range(2 * len(iterm_loader)): samples = iterm_loader.sample(n_samples) assert len(samples) == n_samples assert samples[0]['img'].size(0) == batch_size assert samples[0]['target'].size(0) == batch_size @pytest.mark.parametrize('batch_size, n_samples, drop_last', itertools.product([3, 32], [1, 2], [True, False])) def test_loader_drop_last(batch_size, n_samples, metadata_fname_target_5_classes, ones_image_parser, img_target_transformer, drop_last): iterm_loader = ItemLoader(meta_data=metadata_fname_target_5_classes, root='/tmp/', batch_size=batch_size, parse_item_cb=ones_image_parser, transform=img_target_transformer, shuffle=True, drop_last=drop_last) if drop_last: assert len(iterm_loader) == metadata_fname_target_5_classes.shape[0] // batch_size else: if metadata_fname_target_5_classes.shape[0] % batch_size != 0: assert len(iterm_loader) == metadata_fname_target_5_classes.shape[0] // batch_size + 1 else: assert len(iterm_loader) == metadata_fname_target_5_classes.shape[0] // batch_size

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304e4d261ebda6206f6c2dda1a613c5f82c32929

204

py

Python

benchmarker/data/model/__init__.py

due-benchmark/baselines

2378c02238a04432c7e1401cbe471d57aaf26ff4

[ "MIT" ]

23

2021-12-07T01:56:02.000Z

2022-03-22T15:24:55.000Z

benchmarker/data/model/__init__.py

due-benchmark/baselines

2378c02238a04432c7e1401cbe471d57aaf26ff4

[ "MIT" ]

1

2022-01-13T10:00:23.000Z

2022-02-24T00:31:12.000Z

benchmarker/data/model/__init__.py

due-benchmark/baselines

2378c02238a04432c7e1401cbe471d57aaf26ff4

[ "MIT" ]

null

from benchmarker.data.model.example import Example from benchmarker.data.model.feature import Feature from benchmarker.data.model.span import Span __all__ = [ "Example", "Feature", "Span", ]

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6

3073156bf02e1e987900b0763ebcf68df7fab9e5

169

py

Python

src/confluence_secret_finder/core/secrets/plugins/base_plugin.py

gsoft-inc/confluence-secret-finder

3c342949f3ffbc3e50e1087e14855a87d94abf24

[ "Apache-2.0" ]

null

src/confluence_secret_finder/core/secrets/plugins/base_plugin.py

gsoft-inc/confluence-secret-finder

3c342949f3ffbc3e50e1087e14855a87d94abf24

[ "Apache-2.0" ]

null

src/confluence_secret_finder/core/secrets/plugins/base_plugin.py

gsoft-inc/confluence-secret-finder

3c342949f3ffbc3e50e1087e14855a87d94abf24

[ "Apache-2.0" ]

null

from abc import ABC, abstractmethod from typing import List class BasePlugin(ABC): @abstractmethod def find_secrets(self, lines: List[str]): return []

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null

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6

06a158906d92c598da33ba1946a32a264f08ad5e

3,869

py

Python

ir_measures/measures/nerr.py

claclark/ir_measures

0696f3cdf3d259d7f6713ef6e5cc4a6c2717d6de

[ "Apache-2.0" ]

17

2021-04-27T19:42:27.000Z

2022-03-13T10:57:16.000Z

ir_measures/measures/nerr.py

claclark/ir_measures

0696f3cdf3d259d7f6713ef6e5cc4a6c2717d6de

[ "Apache-2.0" ]

27

2021-04-23T19:33:22.000Z

2022-03-08T13:42:10.000Z

ir_measures/measures/nerr.py

claclark/ir_measures

0696f3cdf3d259d7f6713ef6e5cc4a6c2717d6de

[ "Apache-2.0" ]

3

2021-12-28T21:21:07.000Z

2022-01-26T15:38:40.000Z

from ir_measures import measures from .base import Measure, ParamInfo class _NERR8(measures.Measure): """ Version of the Not (but Nearly) Expected Reciprocal Rank (NERR) measure, version from Equation (8) of the the following paper. :: @inproceedings{Azzopardi:2021:ECE:3471158.3472239, author = {Azzopardi, Leif and Mackenzie, Joel and Moffat, Alistair}, title = {{ERR} is not {C/W/L}: Exploring the Relationship Between Expected Reciprocal Rank and Other Metrics}, booktitle = {ICTIR}, year = {2021}, url = {https://doi.org/10.1145/3471158.3472239} } """ __name__ = 'NERR8' NAME = __name__ SUPPORTED_PARAMS = { 'cutoff': measures.ParamInfo(dtype=int, required=True, desc='ranking cutoff threshold'), 'min_rel': measures.ParamInfo(dtype=int, default=0, desc='minimum relevance score'), 'max_rel': measures.ParamInfo(dtype=int, required=True, desc='maximum relevance score'), } class _NERR9(measures.Measure): """ Version of the Not (but Nearly) Expected Reciprocal Rank (NERR) measure, version from Equation (9) of the the following paper. :: @inproceedings{Azzopardi:2021:ECE:3471158.3472239, author = {Azzopardi, Leif and Mackenzie, Joel and Moffat, Alistair}, title = {{ERR} is not {C/W/L}: Exploring the Relationship Between Expected Reciprocal Rank and Other Metrics}, booktitle = {ICTIR}, year = {2021}, url = {https://doi.org/10.1145/3471158.3472239} } """ __name__ = 'NERR9' NAME = __name__ SUPPORTED_PARAMS = { 'cutoff': measures.ParamInfo(dtype=int, required=True, desc='ranking cutoff threshold'), 'min_rel': measures.ParamInfo(dtype=int, default=0, desc='minimum relevance score'), 'max_rel': measures.ParamInfo(dtype=int, required=True, desc='maximum relevance score'), } class _NERR10(measures.Measure): """ Version of the Not (but Nearly) Expected Reciprocal Rank (NERR) measure, version from Equation (10) of the the following paper. :: @inproceedings{Azzopardi:2021:ECE:3471158.3472239, author = {Azzopardi, Leif and Mackenzie, Joel and Moffat, Alistair}, title = {{ERR} is not {C/W/L}: Exploring the Relationship Between Expected Reciprocal Rank and Other Metrics}, booktitle = {ICTIR}, year = {2021}, url = {https://doi.org/10.1145/3471158.3472239} } """ __name__ = 'NERR10' NAME = __name__ SUPPORTED_PARAMS = { 'p': measures.ParamInfo(dtype=float, default=0.9, desc='persistence'), 'min_rel': measures.ParamInfo(dtype=int, default=0, desc='minimum relevance score'), 'max_rel': measures.ParamInfo(dtype=int, required=True, desc='maximum relevance score'), } class _NERR11(measures.Measure): """ Version of the Not (but Nearly) Expected Reciprocal Rank (NERR) measure, version from Equation (12) of the the following paper. :: @inproceedings{Azzopardi:2021:ECE:3471158.3472239, author = {Azzopardi, Leif and Mackenzie, Joel and Moffat, Alistair}, title = {{ERR} is not {C/W/L}: Exploring the Relationship Between Expected Reciprocal Rank and Other Metrics}, booktitle = {ICTIR}, year = {2021}, url = {https://doi.org/10.1145/3471158.3472239} } """ __name__ = 'NERR11' NAME = __name__ SUPPORTED_PARAMS = { 'T': measures.ParamInfo(dtype=float, default=1.0, desc='total desired gain (normalized)'), 'min_rel': measures.ParamInfo(dtype=int, default=0, desc='minimum relevance score'), 'max_rel': measures.ParamInfo(dtype=int, required=True, desc='maximum relevance score'), } NERR8 = _NERR8() measures.register(NERR8) NERR9 = _NERR9() measures.register(NERR9) NERR10 = _NERR10() measures.register(NERR10) NERR11 = _NERR11() measures.register(NERR11)

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231427b4d57a84ccf7bc21b23d0e3e9ccf181c46

202

py

Python

quiz/admin.py

arpitptl/quiz-up

e85329e799abe4da314021369990413225b34ae8

[ "MIT" ]

null

quiz/admin.py

arpitptl/quiz-up

e85329e799abe4da314021369990413225b34ae8

[ "MIT" ]

null

quiz/admin.py

arpitptl/quiz-up

e85329e799abe4da314021369990413225b34ae8

[ "MIT" ]

null

from django.contrib import admin from .models import Quiz, Question, Option, UserMarks admin.site.register(Quiz) admin.site.register(Question) admin.site.register(Option) admin.site.register(UserMarks)

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231851f25c7ebe3d166bcdcdd7e1410e4e55309e

152

py

Python

tests/test_capitalize.py

rblack42/TikzBuilder

ec69517db422ebda947c6e236c0b9ea597c3a934

[ "BSD-3-Clause" ]

null

tests/test_capitalize.py

rblack42/TikzBuilder

ec69517db422ebda947c6e236c0b9ea597c3a934

[ "BSD-3-Clause" ]

null

tests/test_capitalize.py

rblack42/TikzBuilder

ec69517db422ebda947c6e236c0b9ea597c3a934

[ "BSD-3-Clause" ]

null

# test the testing system def capital_case(x): return x.capitalize() def test_capital_case(): assert capital_case("something") == 'Something'

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py

Python

rosie/__init__.py

fmaida/rosie

3906d11231aadaf9095f00fde8a73bc186403660

[ "MIT" ]

null

rosie/__init__.py

fmaida/rosie

3906d11231aadaf9095f00fde8a73bc186403660

[ "MIT" ]

null

rosie/__init__.py

fmaida/rosie

3906d11231aadaf9095f00fde8a73bc186403660

[ "MIT" ]

null

# Rosie from rosie.utils import RelFile from rosie.exceptions import DocumentNotFound, NoDocuments from rosie.rosie import Rosie

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py

Python

schemaless/__init__.py

eklitzke/schemaless

eb2ca453a69e8af36980c53fcc66725116ae7971

[ "0BSD" ]

58

2015-04-30T07:36:45.000Z

2022-01-20T03:37:09.000Z

schemaless/__init__.py

eklitzke/schemaless

eb2ca453a69e8af36980c53fcc66725116ae7971

[ "0BSD" ]

1

2016-01-19T05:28:15.000Z

schemaless/__init__.py

eklitzke/schemaless

eb2ca453a69e8af36980c53fcc66725116ae7971

[ "0BSD" ]

14

2015-04-14T09:10:53.000Z

2020-05-09T01:53:17.000Z

from schemaless.guid import * from schemaless.column import Entity, c from schemaless.index import Index from schemaless.datastore import DataStore from schemaless.batch import IndexUpdater, main

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py

Python

networks.py

kenseii/landslide

597ddd0344a03811bcd1d246017b034a2c9c8030

[ "MIT" ]

40

2018-04-05T16:36:11.000Z

2022-03-05T08:29:50.000Z

networks.py

kenseii/landslide

597ddd0344a03811bcd1d246017b034a2c9c8030

[ "MIT" ]

4

2018-01-19T05:11:13.000Z

2021-05-06T13:16:55.000Z

networks.py

kenseii/landslide

597ddd0344a03811bcd1d246017b034a2c9c8030

[ "MIT" ]

28

2017-09-16T18:03:55.000Z

2021-05-06T13:15:00.000Z

from keras.layers import Activation, AvgPool2D, Conv2D, Dense, Dropout, Flatten, Input, MaxPool2D, merge from keras.models import Model, Sequential from utils import Maxout def get_convnet_landslide_all(args) -> Model: input_shape = (args.area_size, args.area_size, 14) model = Sequential() model.add(Conv2D(8, 3, 3, input_shape=input_shape, init='normal')) model.add(Activation('relu')) model.add(Conv2D(8, 3, 3, init='normal')) model.add(Activation('relu')) model.add(MaxPool2D((1, 1), strides=(1, 1))) model.add(Dropout(0.25)) model.add(Flatten(name="flatten")) # model.add(Dense(512, activation='relu', name='dense', init='normal')) model.add(Dropout(0.25)) model.add(Dense(1, name='last_layer')) model.add(Activation('sigmoid')) return model def get_test_model(args): y = x = Input(shape=(args.area_size, args.area_size, 14)) y = Conv2D(32, (5, 5))(y) y = Activation('relu')(y) y = AvgPool2D((3, 3), strides=(1, 1))(y) y = Flatten(name="flatten")(y) y = Dense(1, name='last_layer')(y) y = Activation('sigmoid')(y) return Model(x, y) def get_model_1(args): model = Sequential() model.add(Conv2D(32, (5, 5), input_shape=(args.area_size, args.area_size, 14))) model.add(Activation('relu')) model.add(Conv2D(16, (3, 3))) model.add(Activation('relu')) model.add(MaxPool2D((1, 1), strides=(1, 1))) model.add(Dropout(0.25)) # model.add(AvgPool2D((3, 3), strides=(1, 1))) model.add(Flatten(name="flatten")) # model.add(Dense(1, name='last_layer')) model.add(Activation('sigmoid')) return model def get_model_2(args): model = Sequential() model.add(Conv2D(32, (5, 1), padding="same", input_shape=(args.area_size, args.area_size, 14))) model.add(Activation('relu')) model.add(Conv2D(32, (1, 5), padding="same")) model.add(Maxout()) model.add(Conv2D(32, (5, 1), padding="same")) model.add(Activation('relu')) model.add(Conv2D(32, (1, 5), padding="same")) model.add(Maxout()) model.add(MaxPool2D(pool_size=(2, 2))) model.add(Dropout(0.25)) # model.add(Conv2D(16, (3, 1), padding="same")) model.add(Activation('relu')) model.add(Conv2D(16, (1, 3), padding="same")) model.add(Maxout()) model.add(Conv2D(16, (3, 1), padding="same")) model.add(Activation('relu')) model.add(Conv2D(16, (1, 3), padding="same")) model.add(Maxout()) model.add(MaxPool2D(pool_size=(2, 2))) model.add(Dropout(0.25)) # model.add(AvgPool2D((3, 3), strides=(1, 1))) model.add(Flatten(name="flatten")) # model.add(Dense(1, name='last_layer')) model.add(Activation('sigmoid')) return model def get_model_cifar(args): model = Sequential() model.add(Conv2D(32, (3, 3), padding='same', input_shape=(args.area_size, args.area_size, 14))) model.add(Activation('relu')) model.add(Conv2D(32, (3, 3))) model.add(Activation('relu')) model.add(MaxPool2D(pool_size=(2, 2))) model.add(Dropout(0.25)) model.add(Conv2D(64, (3, 3), padding='same')) model.add(Activation('relu')) model.add(Conv2D(64, (3, 3))) model.add(Activation('relu')) model.add(MaxPool2D(pool_size=(2, 2))) model.add(Dropout(0.25)) model.add(Flatten()) model.add(Dense(512)) model.add(Activation('relu')) model.add(Dropout(0.5)) model.add(Dense(1)) model.add(Activation('sigmoid')) return model def get_model_3(args): """First inception network implementation""" x = input_image = Input(shape=(args.area_size, args.area_size, 14)) tower_0 = Conv2D(64, (1, 1), border_mode='same', activation='relu')(x) tower_1 = Conv2D(64, (1, 1), border_mode='same', activation='relu')(x) tower_1 = Conv2D(64, (3, 3), border_mode='same', activation='relu')(tower_1) tower_2 = Conv2D(64, (1, 1), border_mode='same', activation='relu')(x) tower_2 = Conv2D(64, (5, 5), border_mode='same', activation='relu')(tower_2) tower_3 = MaxPool2D((3, 3), strides=(1, 1), border_mode='same')(x) tower_3 = Conv2D(64, (1, 1), border_mode='same', activation='relu')(tower_3) x = merge([tower_0, tower_1, tower_2, tower_3], mode='concat', concat_axis=3) x = Dropout(0.5)(x) tower_0 = Conv2D(32, (1, 1), border_mode='same', activation='relu')(x) tower_1 = Conv2D(32, (1, 1), border_mode='same', activation='relu')(x) tower_1 = Conv2D(32, (3, 3), border_mode='same', activation='relu')(tower_1) tower_2 = Conv2D(32, (1, 1), border_mode='same', activation='relu')(x) tower_2 = Conv2D(32, (5, 5), border_mode='same', activation='relu')(tower_2) tower_3 = MaxPool2D((3, 3), strides=(1, 1), border_mode='same')(x) tower_3 = Conv2D(32, (1, 1), border_mode='same', activation='relu')(tower_3) x = merge([tower_0, tower_1, tower_2, tower_3], mode='concat', concat_axis=3) x = Dropout(0.5)(x) x = AvgPool2D((3, 3), strides=(1, 1))(x) x = Flatten()(x) # model.add(Dropout(0.5)) x = Dense(1)(x) x = Activation('sigmoid')(x) return Model(input_image, x) def get_model_4(args): """First res network implementation""" x = input_image = Input(shape=(args.area_size, args.area_size, 14)) x = Conv2D(filters=64, kernel_size=(1, 1), border_mode='same')(x) y = Conv2D(filters=64, kernel_size=(3, 1), border_mode='same')(x) y = Activation('relu')(y) y = Conv2D(filters=64, kernel_size=(1, 3), border_mode='same')(y) y = Activation('relu')(y) y = Conv2D(filters=64, kernel_size=(3, 1), border_mode='same')(y) y = Activation('relu')(y) y = Conv2D(filters=64, kernel_size=(1, 3), border_mode='same')(y) # this returns x + y. x = merge([x, y], mode='sum') x = Activation('relu')(x) x = MaxPool2D(pool_size=(2, 2))(x) y = Conv2D(filters=64, kernel_size=(3, 1), border_mode='same')(x) y = Activation('relu')(y) y = Conv2D(filters=64, kernel_size=(1, 3), border_mode='same')(y) y = Activation('relu')(y) y = Conv2D(filters=64, kernel_size=(3, 1), border_mode='same')(y) y = Activation('relu')(y) y = Conv2D(filters=64, kernel_size=(1, 3), border_mode='same')(y) # this returns x + y. x = merge([x, y], mode='sum') x = Activation('relu')(x) x = Conv2D(filters=32, kernel_size=(1, 1), border_mode='same')(x) y = Conv2D(filters=32, kernel_size=(3, 1), border_mode='same')(x) y = Activation('relu')(y) y = Conv2D(filters=32, kernel_size=(1, 3), border_mode='same')(y) y = Activation('relu')(y) y = Conv2D(filters=32, kernel_size=(3, 1), border_mode='same')(y) y = Activation('relu')(y) y = Conv2D(filters=32, kernel_size=(1, 3), border_mode='same')(y) # this returns x + y. x = merge([x, y], mode='sum') x = Activation('relu')(x) x = MaxPool2D(pool_size=(2, 2))(x) x = AvgPool2D((3, 3), strides=(1, 1))(x) x = Flatten()(x) # model.add(Dropout(0.5)) x = Dense(1)(x) x = Activation('sigmoid')(x) return Model(input_image, x) model_pool = { "test" : get_test_model, "simple_conv" : get_model_1, "medium_maxout_conv": get_model_2, "inception_net" : get_model_3, "resnet" : get_model_4, "cifar" : get_model_cifar } def get_model_pool(): return model_pool def get_model_by_name(name): return model_pool[name]

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cc38465985c17d0379c8cd2d3021d73f3bad45ed

163

py

Python

ebenv/_compat.py

theY4Kman/ebenv

cc609303add9c71e95e5119dd8201a1b4d8bfaca

[ "BSD-3-Clause" ]

null

ebenv/_compat.py

theY4Kman/ebenv

cc609303add9c71e95e5119dd8201a1b4d8bfaca

[ "BSD-3-Clause" ]

null

ebenv/_compat.py

theY4Kman/ebenv

cc609303add9c71e95e5119dd8201a1b4d8bfaca

[ "BSD-3-Clause" ]

null

import sys IS_PY2 = sys.version_info < (3,) if IS_PY2: def iteritems(d): return d.iteritems() else: def iteritems(d): return d.items()

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24,788

py

Python

python/fdfault/analysis/write_scec.py

egdaub/fdfault

ec066f032ba109843164429aa7d9e7352485d735

[ "MIT" ]

12

2017-10-05T22:04:40.000Z

2020-08-31T08:32:17.000Z

python/fdfault/analysis/write_scec.py

jhsa26/fdfault

ec066f032ba109843164429aa7d9e7352485d735

[ "MIT" ]

3

2020-05-06T16:48:32.000Z

2020-09-18T11:41:41.000Z

python/fdfault/analysis/write_scec.py

jhsa26/fdfault

ec066f032ba109843164429aa7d9e7352485d735

[ "MIT" ]

12

2017-03-24T19:15:27.000Z

2020-08-31T08:32:18.000Z

""" The ``write_scec`` module contains several functions useful for converting binary output from a simulation to the text file format used by the SCEC Rupture Code Verification group. Functions are written for on fault, off fault, and front data types, and there are versions for both 2D and 3D problems. The functions take several common optional arguments, including ``depthsign`` (indicates whether depth is positive or negative), ``author`` (the person who is submitting the results), ``version`` (the code version used to run the simulation), ``grid_spacing`` (the resolution of the simulation, in the event you are submitting data for multiple grid spacings), ``datadir`` (directory where simulation files are written), and ``savepath`` (path where output text files will be written). Each function writes a text file in the current directory following the file naming convention used by the server for the Code Verification group. More information on the file outputs are given in the documentation for each function. """ import numpy as np import fdfault.analysis import datetime from scipy.integrate import cumtrapz from os.path import join def write_off_fault(problem, station, depthsign = 1., author = "", version = "", grid_spacing = "", datadir = None, savepath=None): """ Converts code output units for off-fault station from a 3D simulation into a formatted text file for SCEC website This function converts off fault data from binary (written by the C++ code) to ASCII text for a 3D benchmark simulation. Required inputs are the problem name (string) and station (tuple of strings in the format ``(across, strike, depth)``). Optional inputs include depthsign (1. by default, changes sign on depth coordinate if -1.), and author, verision, and grid spacing strings which will be inserted into the header of the output file. The text file is written to ``{problem}_body{across}st{strike}dp{depth}.txt`` in the specified directory. :param problem: Problem name to write to file :type problem: str :param station: Coordinates in 3D of output station (tuple of 3 strings) :type station: tuple :param depthsign: Sign of depth output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type depthsign: float :param author: Person who ran the simulation (optional, default is ``""``) :type author: str :param version: Code version used in simulation (optional, default is ``""``) :type version: str :param grid_spacing: Grid spacing used in simulation (optional, default is ``""``) :type grid_spacing: str :param datadir: Directory where data is stored (optional, default is current directory) :type datadir: str :param savepath: Path where files will be saved (optional, default is current directory) :type savepath: str :returns: None """ stationstr = 'body'+station[0]+'st'+station[1]+'dp'+station[2] h_vel = fdfault.analysis.output(problem,stationstr+'-h-vel', datadir) h_vel.load() n_vel = fdfault.analysis.output(problem,stationstr+'-n-vel', datadir) n_vel.load() v_vel = fdfault.analysis.output(problem,stationstr+'-v-vel', datadir) v_vel.load() assert(h_vel.nt == v_vel.nt) assert(h_vel.nt == n_vel.nt) assert(depthsign == 1. or depthsign == -1.) h_disp = cumtrapz(h_vel.vx, h_vel.t, initial=0.) n_disp = cumtrapz(n_vel.vy, n_vel.t, initial=0.) v_disp = cumtrapz(v_vel.vz, v_vel.t, initial=0.) if savepath is None: savepath = '' f = open(join(savepath,problem+'_'+stationstr+'.txt'),'w') f.write('# problem='+problem+'\n') f.write('# author='+author+'\n') f.write('# date='+datetime.date.today().strftime("%y/%m/%d")+"\n") f.write('# code=fdfault\n') f.write('# version='+version+'\n') f.write('# element_size='+grid_spacing+'\n') f.write('# time_step='+str(h_vel.t[1]-h_vel.t[0])+' s\n') f.write('# num_time_steps='+str(h_vel.nt)+'\n') f.write('# location='+str(float(station[1])/10.)+' km strike, '+str(float(station[0])/10.)+' km across, '+ str(depthsign*float(station[2])/10.)+' km depth\n') f.write('# Column #1 = Time (s)\n') f.write('# Column #2 = horizontal displacement (m)\n') f.write('# Column #3 = horizontal velocity (m/s)\n') f.write('# Column #4 = vertical displacement (m)\n') f.write('# Column #5 = vertical velocity (m/s)\n') f.write('# Column #6 = normal displacement (m)\n') f.write('# Column #7 = normal velocity (m/s)\n') f.write('#\n') f.write('t h-disp h-vel v-disp v-vel n-disp n-vel\n') f.write('#\n') for i in range(h_vel.nt): f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(h_vel.t[i], h_disp[i], h_vel.vx[i], depthsign*v_disp[i], depthsign*v_vel.vz[i], n_disp[i], n_vel.vy[i])) f.close() def write_off_fault_2d(problem, station, depthsign = 1., author = "", version = "", grid_spacing = "", datadir = None, savepath=None): """ Converts code output units for off-fault station into a formatted text file for SCEC website This function converts off fault data from binary (written by the C++ code) to ASCII text for a 3D benchmark simulation. Required inputs are the problem name (string) and station (tuple of strings in the format ``(across, strike, depth)``). Optional inputs include depthsign (1. by default, changes sign on depth coordinate if -1.), and author, verision, and grid spacing strings which will be inserted into the header of the output file. The text file is written to ``{problem}_body{across}st{strike}dp{depth}.txt`` in the selected directory. :param problem: Problem name to write to file :type problem: str :param station: Coordinates in 2D of output station (tuple of 3 strings, but ``strike`` should be ``'0'``) :type station: tuple :param depthsign: Sign of depth output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type depthsign: float :param author: Person who ran the simulation (optional, default is ``""``) :type author: str :param version: Code version used in simulation (optional, default is ``""``) :type version: str :param grid_spacing: Grid spacing used in simulation (optional, default is ``""``) :type grid_spacing: str :param datadir: Directory where data is stored (optional, default is current directory) :type datadir: str :param savepath: Path where files will be saved (optional, default is current directory) :type savepath: str :returns: None """ stationstr = 'body'+station[0]+'st'+station[1]+'dp'+station[2] n_vel = fdfault.analysis.output(problem,stationstr+'-n-vel', datadir) n_vel.load() v_vel = fdfault.analysis.output(problem,stationstr+'-v-vel', datadir) v_vel.load() assert(n_vel.nt == v_vel.nt) assert(depthsign == 1. or depthsign == -1.) n_disp = cumtrapz(n_vel.vx, n_vel.t, initial=0.) v_disp = cumtrapz(v_vel.vy, v_vel.t, initial=0.) if savepath is None: savepath = '' f = open(join(savepath,problem+'_'+stationstr+'.txt'),'w') f.write('# problem='+problem+'\n') f.write('# author='+author+'\n') f.write('# date='+datetime.date.today().strftime("%y/%m/%d")+"\n") f.write('# code=fdfault\n') f.write('# version='+version+'\n') f.write('# element_size='+grid_spacing+'\n') f.write('# time_step='+str(v_vel.t[1]-v_vel.t[0])+' s\n') f.write('# num_time_steps='+str(v_vel.nt)+'\n') f.write('# location='+str(float(station[1])/10.)+' km strike, '+str(float(station[0])/10.)+' km across, '+ str(depthsign*float(station[2])/10.)+' km depth\n') f.write('# Column #1 = Time (s)\n') f.write('# Column #2 = horizontal displacement (m)\n') f.write('# Column #3 = horizontal velocity (m/s)\n') f.write('# Column #4 = vertical displacement (m)\n') f.write('# Column #5 = vertical velocity (m/s)\n') f.write('# Column #6 = normal displacement (m)\n') f.write('# Column #7 = normal velocity (m/s)\n') f.write('#\n') f.write('t h-disp h-vel v-disp v-vel n-disp n-vel\n') f.write('#\n') for i in range(v_vel.nt): f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(v_vel.t[i], 0., 0., depthsign*v_disp[i], depthsign*v_vel.vy[i], n_disp[i], n_vel.vx[i])) f.close() def write_on_fault(problem, station, depthsign = 1., vertsign = 1., normal = True, faultstr = 'fault', author = "", version = "", grid_spacing = "", datadir = None, savepath=None): """ Converts code output units for on-fault station into a formatted text file for SCEC website This function converts on fault data from binary (written by the C++ code) to ASCII text for a 3D benchmark simulation. Required inputs are the problem name (string) and station (tuple of strings in the format ``(strike, depth)``). Optional inputs include depthsign (1. by default, changes sign on depth coordinate if -1.), and author, verision, and grid spacing strings which will be inserted into the header of the output file. The text file is written to ``{problem}_{faultstr}st{strike}dp{depth}.txt` in the selected directory. :param problem: Problem name to write to file :type problem: str :param station: Coordinates of output station (tuple of 2 strings for strike and depth coordinates) :type station: tuple :param depthsign: Sign of depth output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type depthsign: float :param vertsign: Sign of vertical component output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type vertsign: float :param normal: Boolean indicating if normal stress is to be written to file (default = ``True``) :type normal: bool :param faultstr: String denoting prefix to saved file (default = ``'fault'``) :type faultstr: str :param author: Person who ran the simulation (optional, default is ``""``) :type author: str :param version: Code version used in simulation (optional, default is ``""``) :type version: str :param grid_spacing: Grid spacing used in simulation (optional, default is ``""``) :type grid_spacing: str :param datadir: Directory where data is stored (optional, default is current directory) :type datadir: str :param savepath: Path where files will be saved (optional, default is current directory) :type savepath: str :returns: None """ stationstr = faultstr+'st'+station[0]+'dp'+station[1] h_slip = fdfault.analysis.output(problem,stationstr+'-h-slip', datadir) h_slip.load() h_slip_rate = fdfault.analysis.output(problem,stationstr+'-h-slip-rate', datadir) h_slip_rate.load() h_shear_stress = fdfault.analysis.output(problem,stationstr+'-h-shear-stress', datadir) h_shear_stress.load() v_slip = fdfault.analysis.output(problem,stationstr+'-v-slip', datadir) v_slip.load() v_slip_rate = fdfault.analysis.output(problem,stationstr+'-v-slip-rate', datadir) v_slip_rate.load() v_shear_stress = fdfault.analysis.output(problem,stationstr+'-v-shear-stress', datadir) v_shear_stress.load() assert(h_slip.nt == h_slip_rate.nt) assert(h_slip.nt == h_shear_stress.nt) assert(h_slip.nt == v_slip.nt) assert(h_slip.nt == v_slip_rate.nt) assert(h_slip.nt == v_shear_stress.nt) assert(depthsign == 1. or depthsign == -1.) assert(vertsign == 1. or vertsign == -1.) if normal: n_stress = fdfault.analysis.output(problem,stationstr+'-n-stress', datadir) n_stress.load() if savepath is None: savepath = '' f = open(join(savepath,problem+'_'+stationstr+'.txt'),'w') f.write('# problem='+problem+'\n') f.write('# author='+author+'\n') f.write('# date='+datetime.date.today().strftime("%y/%m/%d")+"\n") f.write('# code=fdfault\n') f.write('# version='+version+'\n') f.write('# element_size='+grid_spacing+'\n') f.write('# time_step='+str(h_slip.t[1]-h_slip.t[0])+' s\n') f.write('# num_time_steps='+str(h_slip.nt)+'\n') f.write('# location='+str(float(station[0])/10.)+' km strike, '+ str(depthsign*float(station[1])/10.)+' km depth\n') f.write('# Column #1 = Time (s)\n') f.write('# Column #2 = horizontal slip (m)\n') f.write('# Column #3 = horizontal slip rate (m/s)\n') f.write('# Column #4 = horizontal shear stress (MPa)\n') f.write('# Column #5 = vertical slip (m)\n') f.write('# Column #6 = vertical slip rate (m/s)\n') f.write('# Column #7 = vertical shear stress (MPa)\n') if normal: f.write('# Column #8 = normal stress (MPa)\n') f.write('#\n') if normal: f.write('t h-slip h-slip-rate h-shear-stress v-slip v-slip-rate v-shear-stress n-stress\n') else: f.write('t h-slip h-slip-rate h-shear-stress v-slip v-slip-rate v-shear-stress\n') f.write('#\n') for i in range(h_slip.nt): if normal: if faultstr == 'branch': f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(h_slip.t[i], h_slip.Uy[i], h_slip_rate.Vy[i], h_shear_stress.Sy[i], vertsign*v_slip.Uz[i], vertsign*v_slip_rate.Vz[i], vertsign*v_shear_stress.Sz[i], n_stress.Sn[i])) else: f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(h_slip.t[i], h_slip.Ux[i], h_slip_rate.Vx[i], h_shear_stress.Sx[i], vertsign*v_slip.Uz[i], vertsign*v_slip_rate.Vz[i], vertsign*v_shear_stress.Sz[i], n_stress.Sn[i])) else: if faultstr == 'branch': f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(h_slip.t[i], h_slip.Uy[i], h_slip_rate.Vy[i], h_shear_stress.Sy[i], vertsign*v_slip.Uz[i], vertsign*v_slip_rate.Vz[i], vertsign*v_shear_stress.Sz[i])) else: f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(h_slip.t[i], h_slip.Ux[i], h_slip_rate.Vx[i], h_shear_stress.Sx[i], vertsign*v_slip.Uz[i], vertsign*v_slip_rate.Vz[i], vertsign*v_shear_stress.Sz[i])) f.close() def write_on_fault_2d(problem, station, depthsign = 1., vertsign = 1., normal = True, faultstr = 'fault', author = "", version = "", grid_spacing = "", datadir = None, savepath=None): """ Converts code output units for on-fault station into a formatted text file for SCEC website This function converts on fault data from binary (written by the C++ code) to ASCII text for a 2D benchmark simulation. Required inputs are the problem name (string) and station (tuple of strings in the format ``(strike, depth)``, with values chosen appropriately for a 2D simulation). Optional inputs include depthsign (1. by default, changes sign on depth coordinate if -1.), and author, verision, and grid spacing strings which will be inserted into the header of the output file. The text file is written to ``{problem}_{faultstr}st{strike}dp{depth}.txt`` in the selected directory. :param problem: Problem name to write to file :type problem: str :param station: Coordinates of output station (tuple of 2 strings for strike and depth coordinates) :type station: tuple :param depthsign: Sign of depth output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type depthsign: float :param vertsign: Sign of vertical component output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type vertsign: float :param normal: Boolean indicating if normal stress is to be written to file (default = ``True``) :type normal: bool :param faultstr: String denoting prefix to saved file (default = ``'fault'``) :type faultstr: str :param author: Person who ran the simulation (optional, default is ``""``) :type author: str :param version: Code version used in simulation (optional, default is ``""``) :type version: str :param grid_spacing: Grid spacing used in simulation (optional, default is ``""``) :type grid_spacing: str :param datadir: Directory where data is stored (optional, default is current directory) :type datadir: str :param savepath: Path where files will be saved (optional, default is current directory) :type savepath: str :returns: None """ if branch: locstr = 'branch' else: locstr = 'fault' stationstr = locstr+'st'+station[0]+'dp'+station[1] v_slip = fdfault.analysis.output(problem,stationstr+'-v-slip', datadir) v_slip.load() v_slip_rate = fdfault.analysis.output(problem,stationstr+'-v-slip-rate', datadir) v_slip_rate.load() v_shear_stress = fdfault.analysis.output(problem,stationstr+'-v-shear-stress', datadir) v_shear_stress.load() assert(v_slip.nt == v_slip_rate.nt) assert(v_slip.nt == v_shear_stress.nt) assert(depthsign == 1. or depthsign == -1.) assert(vertsign == 1. or vertsign == -1.) if normal: n_stress = fdfault.analysis.output(problem,stationstr+'-n-stress', datadir) n_stress.load() if savepath is None: savepath = '' f = open(join(savepath,problem+'_'+stationstr+'.txt'),'w') f.write('# problem='+problem+'\n') f.write('# author='+author+'\n') f.write('# date='+datetime.date.today().strftime("%y/%m/%d")+"\n") f.write('# code=fdfault\n') f.write('# version='+version+'\n') f.write('# element_size='+grid_spacing+'\n') f.write('# time_step='+str(v_slip.t[1]-v_slip.t[0])+' s\n') f.write('# num_time_steps='+str(v_slip.nt)+'\n') f.write('# location='+str(float(station[0])/10.)+' km strike, '+ str(depthsign*float(station[1])/10.)+' km depth\n') f.write('# Column #1 = Time (s)\n') f.write('# Column #2 = horizontal slip (m)\n') f.write('# Column #3 = horizontal slip rate (m/s)\n') f.write('# Column #4 = horizontal shear stress (MPa)\n') f.write('# Column #5 = vertical slip (m)\n') f.write('# Column #6 = vertical slip rate (m/s)\n') f.write('# Column #7 = vertical shear stress (MPa)\n') if normal: f.write('# Column #8 = normal stress (MPa)\n') f.write('#\n') if normal: f.write('t h-slip h-slip-rate h-shear-stress v-slip v-slip-rate v-shear-stress n-stress\n') else: f.write('t h-slip h-slip-rate h-shear-stress v-slip v-slip-rate v-shear-stress\n') f.write('#\n') for i in range(v_slip.nt): if normal: if faultstr == 'branch': f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(v_slip.t[i], 0., 0., 0., depthsign*v_slip.Ux[i], depthsign*v_slip_rate.Vx[i], depthsign*v_shear_stress.Sx[i], n_stress.Sn[i])) else: f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(v_slip.t[i], 0., 0., 0., depthsign*v_slip.Uy[i], depthsign*v_slip_rate.Vy[i], depthsign*v_shear_stress.Sy[i], n_stress.Sn[i])) else: if faultstr == 'branch': f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(v_slip.t[i], 0., 0., 0., depthsign*v_slip.Ux[i], depthsign*v_slip_rate.Vx[i], depthsign*v_shear_stress.Sx[i])) else: f.write("{:.12E} {:E} {:E} {:E} {:E} {:E} {:E}\n".format(v_slip.t[i], 0., 0., 0., depthsign*v_slip.Uy[i], depthsign*v_slip_rate.Vy[i], depthsign*v_shear_stress.Sy[i])) f.close() def write_front(problem, iface = 0, depthsign = 1., faultstr = '', hscale = 1., vscale=1., author = "", version = "", grid_spacing = "", datadir = None, savepath=None): """ Converts code output units for rupture front times into a formatted text file for SCEC website This function converts rupture time data from binary (written by the C++ code) to ASCII text for a 3D benchmark simulation. Required inputs are the problem name (string). Optional inputs include the interface to write to file (default is ``0``), depthsign (1. by default, changes sign on depth coordinate if -1.), and author, verision, and grid spacing strings which will be inserted into the header of the output file. The text file is written to ``{problem}_cplot.txt`` or ``{problem}_cplot{faultstr}.txt`` in the current directory, where ``faultstr`` is an optional user-specified string that often indicates a branch fault. :param problem: Problem name to write to file :type problem: str :param iface: Interface to be written to file (default is ``0``). Can be an integer or a list of integers :type iface: int or list :param depthsign: Sign of depth output, must be ``1.`` or ``-1.`` (optional, default is ``1.``) :type depthsign: float :param faultstr: String will be appended to stem of output file (often used if the simulation contains a second fault or a fault branch, default is ``''``). If this string is ``'_branch'``, the code will adjust the spatial output locations appropriately for a branch fault. :type faultstr: str :param hscale: Scale factor for transforming horizontal coordinates (default is ``1.``) :type hscale: float :param vscale: Scale factor for transforming vertical coordinates (default is ``1.``) :type vscale: float :param author: Person who ran the simulation (optional, default is ``""``) :type author: str :param version: Code version used in simulation (optional, default is ``""``) :type version: str :param grid_spacing: Grid spacing used in simulation (optional, default is ``""``) :type grid_spacing: str :param datadir: Directory where data is stored (optional, default is current directory) :type datadir: str :param savepath: Path where files will be saved (optional, default is current directory) :type savepath: str :returns: None """ assert(depthsign == 1. or depthsign == -1.) if savepath is None: savepath = '' f = open(join(savepath,problem+'_cplot'+faultstr+'.txt'),'w') f.write('# problem='+problem+'\n') f.write('# author='+author+'\n') f.write('# date='+datetime.date.today().strftime("%y/%m/%d")+"\n") f.write('# code=fdfault\n') f.write('# version='+version+'\n') f.write('# element_size='+grid_spacing+'\n') f.write('# Column #1 = horizontal coordinate, distance along strike (m)\n') f.write('# Column #2 = vertical coordinate, distance down-dip (m)\n') f.write('# Column #3 = rupture time (s)\n') f.write('#\n') f.write('j k t\n') f.write('#\n') try: iface = list(iface) except: iface = [int(iface)] for ifaceitem in iface: frt = fdfault.analysis.front(problem, ifaceitem, datadir) frt.load() for i in range(frt.nx): for j in range(frt.ny): if (frt.t[i,j] < 0.): if faultstr == '_branch': f.write("{:E} {:E} {:E}\n".format(frt.y[i,j]*1000.*hscale, depthsign*frt.z[i,j]*1000.*vscale, 1.e9)) else: f.write("{:E} {:E} {:E}\n".format(frt.x[i,j]*1000.*hscale, depthsign*frt.z[i,j]*1000.*vscale, 1.e9)) else: if faultstr == '_branch': f.write("{:E} {:E} {:E}\n".format(frt.y[i,j]*1000.*hscale, depthsign*frt.z[i,j]*1000.*vscale, frt.t[i,j])) else: f.write("{:E} {:E} {:E}\n".format(frt.x[i,j]*1000.*hscale, depthsign*frt.z[i,j]*1000.*vscale, frt.t[i,j])) f.close()

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cc6bf5f9ee8ca256e37a2d20025ddfa0d5d111f9

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py

Python

tapiriik/services/TrainingPeaks/__init__.py

prohfesor/tapiriik

0c476f8bb6b3d51674f0117b054777405ff2ee0d

[ "Apache-2.0" ]

1,445

2015-01-01T21:43:31.000Z

2022-03-17T13:40:23.000Z

tapiriik/services/TrainingPeaks/__init__.py

prohfesor/tapiriik

0c476f8bb6b3d51674f0117b054777405ff2ee0d

[ "Apache-2.0" ]

441

2015-01-02T03:37:49.000Z

2022-03-31T18:18:03.000Z

tapiriik/services/TrainingPeaks/__init__.py

prohfesor/tapiriik

0c476f8bb6b3d51674f0117b054777405ff2ee0d

[ "Apache-2.0" ]

333

2015-01-06T12:14:15.000Z

2022-03-27T19:58:48.000Z

from .trainingpeaks import *

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py

Python

server/tasks/celery_worker.py

guigolab/biogenome-portal

a30557ea02cc94b863d646c5ff166fb593134974

[ "MIT" ]

1

2022-03-29T05:59:53.000Z

server/tasks/celery_worker.py

guigolab/biogenome-portal

a30557ea02cc94b863d646c5ff166fb593134974

[ "MIT" ]

null

server/tasks/celery_worker.py

guigolab/biogenome-portal

a30557ea02cc94b863d646c5ff166fb593134974

[ "MIT" ]

2

2022-03-03T15:05:57.000Z

2022-03-24T00:10:18.000Z

# from app import create_app # app = create_app() # app.app_context().push() # from tasks import celery

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1

0

1

0

null

0

1

0

6

4e2e1e08f59ce41b2f250b1764e9b9ed32e4cd87

98

py

Python

gary/integrate/cyintegrators/__init__.py

adrn/gary-old

065b371534baa03deeb860893640068d90ba5881

[ "MIT" ]

null

gary/integrate/cyintegrators/__init__.py

adrn/gary-old

065b371534baa03deeb860893640068d90ba5881

[ "MIT" ]

null

gary/integrate/cyintegrators/__init__.py

adrn/gary-old

065b371534baa03deeb860893640068d90ba5881

[ "MIT" ]

null

from .dop853 import dop853_integrate_potential from .leapfrog import leapfrog_integrate_potential

32.666667

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98

7

0.5

0.428571

0

0.066667

0.081633

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2

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49

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1

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1

0

null

0

1

0

1

0

1

0

6

4e3756ac9ee5e3aa611fb295f1091a9c8ba5610d

85

py

Python

vvsa/products/types/index_equity.py

goncalovf/security-analysis

72b80ea7c0c5c93b6fd80a4e347ecdb401b7667e

[ "MIT" ]

1

2021-09-16T13:36:13.000Z

vvsa/products/types/index_equity.py

goncalovf/security-analysis

72b80ea7c0c5c93b6fd80a4e347ecdb401b7667e

[ "MIT" ]

null

vvsa/products/types/index_equity.py

goncalovf/security-analysis

72b80ea7c0c5c93b6fd80a4e347ecdb401b7667e

[ "MIT" ]

null

from vvsa.abstracts.product_index import Index class Equity_Index(Index): pass

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null

0

1

0

1

0

6

9d7970a06681091a9f9a6d91fdfc4aff1ce517ab

43

py

Python

tarkov/inventory_dispatcher/inventory/__init__.py

JustEmuTarkov/jet_py

2f352b5e6f5d88594d08afc46e9458e919271788

[ "MIT" ]

14

2021-02-24T02:32:48.000Z

2022-01-03T05:51:45.000Z

tarkov/inventory_dispatcher/inventory/__init__.py

JustEmuTarkov/jet_py

2f352b5e6f5d88594d08afc46e9458e919271788

[ "MIT" ]

1

2021-03-08T09:02:29.000Z

tarkov/inventory_dispatcher/inventory/__init__.py

JustEmuTarkov/jet_py

2f352b5e6f5d88594d08afc46e9458e919271788

[ "MIT" ]

4

2021-04-14T01:47:01.000Z

2021-11-29T02:18:32.000Z

from .inventory import InventoryDispatcher

21.5

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1

0

1

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6

9d9570d0fed8b99661ca4af9c7d8193423e8c643

127

py

Python

app/model/Checklist.py

Marlysson/trackwork

149f977df468a97bb465fb8fd4f78c29a7517349

[ "MIT" ]

4

2020-07-23T20:19:12.000Z

2021-01-14T20:52:07.000Z

app/model/Checklist.py

Marlysson/trackwork

149f977df468a97bb465fb8fd4f78c29a7517349

[ "MIT" ]

2

2018-06-04T12:03:21.000Z

2018-09-03T13:38:38.000Z

app/model/Checklist.py

Marlysson/trackwork

149f977df468a97bb465fb8fd4f78c29a7517349

[ "MIT" ]

null

"""Checklist Model.""" from masoniteorm.models import Model class Checklist(Model): """Checklist Model.""" pass

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6.384615

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127

7

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0

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true

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null

1

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1

0

null

0

1

0

6

9dc159611951919e21b2eef186f0630a89740260

74

py

Python

dynamodb_meta_store/__init__.py

sergeymazin/dynamodb-meta-store

33757240fd823f830f1d36ef6f04c2a82ee88118

[ "Apache-2.0" ]

null

dynamodb_meta_store/__init__.py

sergeymazin/dynamodb-meta-store

33757240fd823f830f1d36ef6f04c2a82ee88118

[ "Apache-2.0" ]

null

dynamodb_meta_store/__init__.py

sergeymazin/dynamodb-meta-store

33757240fd823f830f1d36ef6f04c2a82ee88118

[ "Apache-2.0" ]

null

from dynamodb_meta_store.meta_store import DynamoDBMetaStore # noqa F401

37

73

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6.1

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1

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1

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6

d1b2160319349d236721a350fcc4e05e943889bd

69

py

Python

sciapp/util/__init__.py

dada1437903138/imagepy

65d9ce088894eef587054e04018f9d34ff65084f

[ "BSD-4-Clause" ]

1

2020-08-17T04:18:35.000Z

sciapp/util/__init__.py

saber-zero/imagepy

e37df0bfbce026101c815c928ddbd7066162c869

[ "BSD-4-Clause" ]

1

2021-06-20T08:50:20.000Z

sciapp/util/__init__.py

saber-zero/imagepy

e37df0bfbce026101c815c928ddbd7066162c869

[ "BSD-4-Clause" ]

1

2021-05-02T03:00:34.000Z

from .surfutil import * from .shputil import * from .imgutil import *

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6

d1c439f0ccf6f94b8b712348f7e450824ad5a8e9

24

py

Python

rosbuild_ws/src/behavior_manager/src/behavior_manager/msg/__init__.py

Boberito25/ButlerBot

959f961bbc8c43be0ccb533dd2e2af5c55b0cc2a

[ "BSD-3-Clause" ]

null

rosbuild_ws/src/behavior_manager/src/behavior_manager/msg/__init__.py

Boberito25/ButlerBot

959f961bbc8c43be0ccb533dd2e2af5c55b0cc2a

[ "BSD-3-Clause" ]

1

2015-06-08T19:55:40.000Z

rosbuild_ws/src/behavior_manager/src/behavior_manager/msg/__init__.py

Boberito25/ButlerBot

959f961bbc8c43be0ccb533dd2e2af5c55b0cc2a

[ "BSD-3-Clause" ]

null

from ._Startup import *

12

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1

0

6

ae4e2545d7d38e7e56c21eb946cab82de081df60

4,476

py

Python

helper_scripts/composing/list_libs_win.py

xorsnn/altexo

2587ecd66a970d6805cc40635a9ec19786b05dce

[ "MIT" ]

1

2018-09-06T15:37:19.000Z

helper_scripts/composing/list_libs_win.py

xorsnn/altexo

2587ecd66a970d6805cc40635a9ec19786b05dce

[ "MIT" ]

null

helper_scripts/composing/list_libs_win.py

xorsnn/altexo

2587ecd66a970d6805cc40635a9ec19786b05dce

[ "MIT" ]

null

import os import sys # walk_dir = sys.argv[1] walk_dir = "D:\\WORKSPACE\\webrtc\\src\\out\\Release" def ifExt(fileName): nameLen = len(fileName) ext = (fileName[(nameLen-4):(nameLen)]) # print(ext) if (ext.lower() == ".lib"): return True else: return False def composeDetails(): print('walk_dir = ' + walk_dir) libsList = [] fOut = open("res.cmake", "w") # If your current working directory may change during script execution, it's recommended to # immediately convert program arguments to an absolute path. Then the variable root below will # be an absolute path as well. Example: # walk_dir = os.path.abspath(walk_dir) print('walk_dir (absolute) = ' + os.path.abspath(walk_dir)) for root, subdirs, files in os.walk(walk_dir): for filename in files: file_path = os.path.join(root, filename) if ifExt(filename): print('\t- file %s (full path: %s)' % (filename, file_path)) libName = filename.split(".")[0].upper() fOut.write("ADD_LIBRARY(" + libName + " STATIC IMPORTED)\n") basePath = "D:\\WORKSPACE\\webrtc\\src\\out\\Release" resPath = file_path.replace(basePath, "${WEBRTCBUILD}") fOut.write("SET_TARGET_PROPERTIES(" + libName + " PROPERTIES IMPORTED_LOCATION " + resPath.replace("\\", "\\\\") + ")\n") libsList.append(libName) fOut.write("SET(WEBRTC_LIBS\n") for lib in libsList: fOut.write(" PUBLIC " + lib + "\n") fOut.write(")\n") fOut.close() def composeBrief(): print('walk_dir = ' + walk_dir) libsList = [] fOut = open("res.cmake", "w") # If your current working directory may change during script execution, it's recommended to # immediately convert program arguments to an absolute path. Then the variable root below will # be an absolute path as well. Example: # walk_dir = os.path.abspath(walk_dir) print('walk_dir (absolute) = ' + os.path.abspath(walk_dir)) for root, subdirs, files in os.walk(walk_dir): for filename in files: file_path = os.path.join(root, filename) if ifExt(filename): print('\t- file %s (full path: %s)' % (filename, file_path)) libName = filename.split(".")[0].upper() # fOut.write("ADD_LIBRARY(" + libName + " STATIC IMPORTED)\n") basePath = "D:\\WORKSPACE\\webrtc\\src\\out\\Release" resPath = file_path.replace(basePath, "${WEBRTCBUILD}") # fOut.write("SET_TARGET_PROPERTIES(" + libName + " PROPERTIES IMPORTED_LOCATION " + resPath.replace("\\", "\\\\") + ")\n") libsList.append(resPath.replace("\\", "\\\\") + "\n") fOut.write("SET(WEBRTC_LIBS\n") for lib in libsList: fOut.write(" " + lib) fOut.write(")\n") fOut.close() def composeComment(): print('walk_dir = ' + walk_dir) libsList = [] fOut = open("res.cmake", "w") # If your current working directory may change during script execution, it's recommended to # immediately convert program arguments to an absolute path. Then the variable root below will # be an absolute path as well. Example: # walk_dir = os.path.abspath(walk_dir) print('walk_dir (absolute) = ' + os.path.abspath(walk_dir)) for root, subdirs, files in os.walk(walk_dir): for filename in files: file_path = os.path.join(root, filename) if ifExt(filename): print('\t- file %s (full path: %s)' % (filename, file_path)) libName = filename.split(".")[0].upper() # fOut.write("ADD_LIBRARY(" + libName + " STATIC IMPORTED)\n") # basePath = "D:\\WORKSPACE\\webrtc\\src\\out\\Release" # resPath = file_path.replace(basePath, "${WEBRTCBUILD}") # fOut.write("SET_TARGET_PROPERTIES(" + libName + " PROPERTIES IMPORTED_LOCATION " + resPath.replace("\\", "\\\\") + ")\n") libsList.append(file_path.replace("\\", "\\\\")) for lib in libsList: fOut.write("#pragma comment (lib, \" " + lib + "\")\n") fOut.close() #pragma comment (lib, "d3d9.lib") def main(): # composeDetails() composeBrief() # composeComment() if __name__ == '__main__': main()

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null

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1

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0

6

8843f66069e0e2dba82c8b278cc26d56e383570e

68

py

Python

src/Arpspoofing/malarp.py

dhavall13/Python-Scripts

ebbf33fea976375ea7d4d5b604b352b797b41bda

[ "MIT" ]

null

src/Arpspoofing/malarp.py

dhavall13/Python-Scripts

ebbf33fea976375ea7d4d5b604b352b797b41bda

[ "MIT" ]

null

src/Arpspoofing/malarp.py

dhavall13/Python-Scripts

ebbf33fea976375ea7d4d5b604b352b797b41bda

[ "MIT" ]

null

from scapy.all import * broadcast = Ether(dst='ff:ff:ff:ff:ff:ff')

22.666667

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1

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6

8861646c989d1d54ee13a91094cb0b90faf27150

735

py

Python

Lib/site-packages/tensorflow/keras/mixed_precision/__init__.py

xorb813/Text-Mining

3dced9dd06fc9334d631ddf608b2ed96c2493276

[ "CNRI-Python-GPL-Compatible" ]

1

2021-05-24T10:08:51.000Z

Lib/site-packages/tensorflow/keras/mixed_precision/__init__.py

xorb813/Text-Mining

3dced9dd06fc9334d631ddf608b2ed96c2493276

[ "CNRI-Python-GPL-Compatible" ]

null

Lib/site-packages/tensorflow/keras/mixed_precision/__init__.py

xorb813/Text-Mining

3dced9dd06fc9334d631ddf608b2ed96c2493276

[ "CNRI-Python-GPL-Compatible" ]

null

# This file is MACHINE GENERATED! Do not edit. # Generated by: tensorflow/python/tools/api/generator/create_python_api.py script. """Keras mixed precision API. See [the mixed precision guide]( https://www.tensorflow.org/guide/keras/mixed_precision) to learn how to use the API. """ from __future__ import print_function as _print_function import sys as _sys from . import experimental from tensorflow.python.keras.mixed_precision.loss_scale_optimizer import LossScaleOptimizer from tensorflow.python.keras.mixed_precision.policy import Policy from tensorflow.python.keras.mixed_precision.policy import global_policy from tensorflow.python.keras.mixed_precision.policy import set_policy as set_global_policy del _print_function

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6

ee397e90d8da4443bf53214c79e54dc26c5e6cc9

5,649

py

Python

group_conv_op.py

wangxianliang/shufflenet_v2_tensorflow

919f25a1fb058215b614a4f3b6e5dd0190516812

[ "MIT" ]

4

2018-08-15T06:10:03.000Z

2019-02-18T12:16:43.000Z

group_conv_op.py

wangxianliang/shufflenet_v2_tensorflow

919f25a1fb058215b614a4f3b6e5dd0190516812

[ "MIT" ]

1

2019-02-18T12:15:20.000Z

2019-05-24T11:50:02.000Z

group_conv_op.py

wangxianliang/shufflenet_v2_tensorflow

919f25a1fb058215b614a4f3b6e5dd0190516812

[ "MIT" ]

4

2018-09-25T00:36:35.000Z

2020-07-23T07:48:58.000Z

# Tensorflow mandates these. from __future__ import absolute_import from __future__ import division from __future__ import print_function import tensorflow as tf slim = tf.contrib.slim @slim.add_arg_scope def group_conv2d_by_depthwise_conv(inputs, num_outputs, kernel_size, num_groups=1, stride=1, rate=1, padding='SAME', activation_fn=tf.nn.relu, normalizer_fn=None, normalizer_params=None, biases_initializer=tf.zeros_initializer(), scope=None): with tf.variable_scope(scope, 'group_conv2d', [inputs]) as sc: biases_initializer = biases_initializer if normalizer_fn is None else None if num_groups == 1: return slim.conv2d(inputs, num_outputs, kernel_size, stride=stride, rate=rate, padding=padding, activation_fn=activation_fn, normalizer_fn=normalizer_fn, normalizer_params=normalizer_params, biases_initializer=biases_initializer, scope=scope) else: depth_in = slim.utils.last_dimension(inputs.get_shape(), min_rank=4) assert num_outputs % num_groups == 0, ( "num_outputs=%d is not divisible by num_groups=%d" % (num_outputs, num_groups)) assert depth_in % num_groups == 0, ( "depth_in=%d is not divisible by num_groups=%d" % (depth_in, num_groups)) group_size_in = depth_in // num_groups group_size_out = num_outputs // num_groups # By passing filters=None # separable_conv2d produces only a depthwise convolution layer net = slim.separable_conv2d(inputs=inputs, num_outputs=None, kernel_size=kernel_size, depth_multiplier=group_size_out, stride=stride, padding=padding, rate=rate, activation_fn=None, normalizer_fn=None, biases_initializer=biases_initializer, scope=scope) net_shape = net.shape.as_list() net = tf.reshape(net, net_shape[:3] + [num_groups, group_size_in, group_size_out]) net = tf.reduce_sum(net, axis=4) net = tf.reshape(net, net_shape[:3] + [num_outputs]) if normalizer_fn is not None: normalizer_params = normalizer_params or {} net = normalizer_fn(net, **normalizer_params) if activation_fn is not None: net = activation_fn(net) return net @slim.add_arg_scope def group_conv2d(inputs, num_outputs, kernel_size, num_groups=1, stride=1, rate=1, padding='SAME', activation_fn=tf.nn.relu, normalizer_fn=None, normalizer_params=None, biases_initializer=tf.zeros_initializer(), scope=None): with tf.variable_scope(scope, 'group_conv2d', [inputs]) as sc: biases_initializer = biases_initializer if normalizer_fn is None else None if num_groups == 1: return slim.conv2d(inputs, num_outputs, kernel_size, stride=stride, rate=rate, padding=padding, activation_fn=activation_fn, normalizer_fn=normalizer_fn, normalizer_params=normalizer_params, biases_initializer=biases_initializer, scope=scope) else: depth_in = slim.utils.last_dimension(inputs.get_shape(), min_rank=4) assert num_outputs % num_groups == 0, ( "num_outputs=%d is not divisible by num_groups=%d" % (num_outputs, num_groups)) assert depth_in % num_groups == 0, ( "depth_in=%d is not divisible by num_groups=%d" % (depth_in, num_groups)) group_size_out = num_outputs // num_groups input_slices = tf.split(inputs, num_groups, axis=-1) output_slices = [slim.conv2d(inputs=input_slice, num_outputs=group_size_out, kernel_size=kernel_size, stride=stride, rate=rate, padding=padding, activation_fn=None, normalizer_fn=None, biases_initializer=biases_initializer, scope=scope + '/group%d' % idx) for idx, input_slice in enumerate(input_slices)] net = tf.concat(output_slices, axis=-1) if normalizer_fn is not None: normalizer_params = normalizer_params or {} net = normalizer_fn(net, **normalizer_params) if activation_fn is not None: net = activation_fn(net) return net

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6

ee3d4e59a59a7b3bf2279f63ce76abe9d59e62d7

47

py

Python

torch_lr_finder/__init__.py

AlexGrig/pytorch-lr-finder

b0b0ecd28c0578ad1d5ed06d2442f9a2c29c72e2

[ "MIT" ]

null

torch_lr_finder/__init__.py

AlexGrig/pytorch-lr-finder

b0b0ecd28c0578ad1d5ed06d2442f9a2c29c72e2

[ "MIT" ]

3

2020-05-25T20:40:01.000Z

2020-05-25T20:50:58.000Z

torch_lr_finder/__init__.py

AlexGrig/pytorch-lr-finder

b0b0ecd28c0578ad1d5ed06d2442f9a2c29c72e2

[ "MIT" ]

1

2020-05-25T20:25:19.000Z

from torch_lr_finder.lr_finder import LRFinder

23.5

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4.875

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null

0

1

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1

0

6

ee50cc62aef58d054e9691e112412cd9172f7ef6

6,448

py

Python

posts/views.py

aniruddha2000/foodfeeda

4dffbbe0310a1809c9743b3525e63bac8a8a0768

[ "Apache-2.0" ]

null

posts/views.py

aniruddha2000/foodfeeda

4dffbbe0310a1809c9743b3525e63bac8a8a0768

[ "Apache-2.0" ]

null

posts/views.py

aniruddha2000/foodfeeda

4dffbbe0310a1809c9743b3525e63bac8a8a0768

[ "Apache-2.0" ]

1

2022-03-17T12:47:40.000Z

from rest_framework import status from rest_framework.generics import ( ListAPIView, ListCreateAPIView, RetrieveUpdateDestroyAPIView) from rest_framework.permissions import IsAuthenticated from rest_framework.response import Response from rest_framework_simplejwt.authentication import JWTAuthentication from accounts.models import NGO, Donner from posts.models import FoodPost from posts.pagination import PostLimitOffsetPagination from posts.serializers import * class PostCreateAPIView(ListCreateAPIView): permission_classes = [ IsAuthenticated, ] authentication_classes = (JWTAuthentication,) queryset = FoodPost.objects.all() serializer_class = PostCreateSerializer pagination_class = PostLimitOffsetPagination def perform_create(self, serializer): return serializer.save(auther=Donner.objects.get(id=self.request.user.id)) def create(self, request, *args, **kwargs): serializer = self.get_serializer(data=request.data) serializer.is_valid(raise_exception=True) instance = self.perform_create(serializer) headers = self.get_success_headers(serializer.data) serializer = PostListSerializer(instance=instance, many=False) return Response(serializer.data, status=status.HTTP_201_CREATED, headers=headers) def post(self, request, *args, **kwargs): return self.create(request, *args, **kwargs) def list(self, request, *args, **kwargs): queryset = self.filter_queryset(self.get_queryset()) # page = self.paginate_queryset(queryset) # if page is not None: # serializer = self.get_serializer(page, many=True) # return self.get_paginated_response(serializer.data) serializer = PostListSerializer(queryset, many=True) return Response(serializer.data) def get_queryset(self): queryset = FoodPost.objects.filter( auther=Donner.objects.get(id=self.request.user.id)) return queryset class PostUpdateDeleteAPIView(RetrieveUpdateDestroyAPIView): permission_classes = [ IsAuthenticated, ] authentication_classes = (JWTAuthentication,) queryset = FoodPost.objects.all() serializer_class = PostCreateSerializer lookup_field = 'id' def retrieve(self, request, *args, **kwargs): instance = self.get_object() serializer = PostListSerializer(instance) return Response(serializer.data) def perform_update(self, serializer): return serializer.save() def update(self, request, *args, **kwargs): partial = kwargs.pop('partial', False) instance = self.get_object() serializer = self.get_serializer( instance, data=request.data, partial=partial) serializer.is_valid(raise_exception=True) self.perform_update(serializer) serializer = PostListSerializer(instance=instance, many=False) return Response(serializer.data) def perform_destroy(self, instance): instance.delete() return Response(status=status.HTTP_204_NO_CONTENT) class AllPostListRetrieveAPIView(ListAPIView): permission_classes = [ IsAuthenticated, ] authentication_classes = (JWTAuthentication,) queryset = FoodPost.objects.all() serializer_class = PostListSerializer pagination_class = PostLimitOffsetPagination def get_queryset(self): place = self.kwargs['place'] return FoodPost.objects.filter(place=place) class DonationPostCreateAPIView(ListCreateAPIView): permission_classes = [ IsAuthenticated, ] authentication_classes = (JWTAuthentication,) queryset = DonationPost.objects.all() serializer_class = DonationPostCreateSerializer pagination_class = PostLimitOffsetPagination def perform_create(self, serializer): return serializer.save(author=NGO.objects.get(id=self.request.user.id)) def create(self, request, *args, **kwargs): serializer = self.get_serializer(data=request.data) serializer.is_valid(raise_exception=True) instance = self.perform_create(serializer) headers = self.get_success_headers(serializer.data) serializer = DonationPostListSerializer(instance=instance, many=False) return Response(serializer.data, status=status.HTTP_201_CREATED, headers=headers) def post(self, request, *args, **kwargs): return self.create(request, *args, **kwargs) def list(self, request, *args, **kwargs): queryset = self.filter_queryset(self.get_queryset()) # page = self.paginate_queryset(queryset) # if page is not None: # serializer = self.get_serializer(page, many=True) # return self.get_paginated_response(serializer.data) serializer = DonationPostListSerializer(queryset, many=True) return Response(serializer.data) def get_queryset(self): queryset = DonationPost.objects.filter( author=NGO.objects.get(id=self.request.user.id)) return queryset class DonationPostUpdateAPIView(RetrieveUpdateDestroyAPIView): permission_classes = [ IsAuthenticated, ] authentication_classes = (JWTAuthentication,) queryset = DonationPost.objects.all() serializer_class = DonationPostCreateSerializer lookup_field = 'id' def retrieve(self, request, *args, **kwargs): instance = self.get_object() serializer = DonationPostListSerializer(instance) return Response(serializer.data) def perform_update(self, serializer): return serializer.save() def update(self, request, *args, **kwargs): partial = kwargs.pop('partial', False) instance = self.get_object() serializer = self.get_serializer( instance, data=request.data, partial=partial) serializer.is_valid(raise_exception=True) self.perform_update(serializer) serializer = DonationPostListSerializer(instance=instance, many=False) return Response(serializer.data) def perform_destroy(self, instance): instance.delete() class DonationAllPostListRetrieveAPIView(ListAPIView): permission_classes = [ IsAuthenticated, ] authentication_classes = (JWTAuthentication,) queryset = DonationPost.objects.filter(accepted=True) serializer_class = DonationPostListSerializer pagination_class = PostLimitOffsetPagination

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34.854054

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0

1

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1

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null

0

6

c99e5c02e72b3f1e2ca8ca3059d6a0fd583e003d

27

py

Python

music_metadata_extractor/sources/youtube/__init__.py

2000yeshu/metadata-extractor

e88932c736d4f69d459a752b10e4098f79343273

[ "MIT" ]

null

music_metadata_extractor/sources/youtube/__init__.py

2000yeshu/metadata-extractor

e88932c736d4f69d459a752b10e4098f79343273

[ "MIT" ]

null

music_metadata_extractor/sources/youtube/__init__.py

2000yeshu/metadata-extractor

e88932c736d4f69d459a752b10e4098f79343273

[ "MIT" ]

null

from .core import get_info

13.5

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null

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1

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1

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6

4e8ba3d6f513226a0d49da38014ac990085e9e78

9,337

py

Python

apps/System/handlers.py

swxs/home

652dab7c15ae9c2221c99405ce827be6ccaaccbb

[ "Apache-2.0" ]

1

2021-09-23T10:28:34.000Z

apps/System/handlers.py

swxs/home

652dab7c15ae9c2221c99405ce827be6ccaaccbb

[ "Apache-2.0" ]

null

apps/System/handlers.py

swxs/home

652dab7c15ae9c2221c99405ce827be6ccaaccbb

[ "Apache-2.0" ]

1

2021-09-23T10:28:36.000Z

# -*- coding: utf-8 -*- # @File : views.py # @AUTH : model import bson import json import logging from tornado.web import url from web import BaseHandler, BaseAuthedHanlder, SuccessData, render, undefined from commons.Helpers.Helper_pagenate import Page from .utils.User import User, user_schema from .utils.UserAuth import UserAuth, user_auth_schema logger = logging.getLogger("main.system.views") class UserHandler(BaseAuthedHanlder): async def add_tokens(self, params): return params @render async def get(self, user_id=None): if user_id: finds = await self.add_tokens({"id": user_id}) user = await User.find(finds) return SuccessData(data=await user.to_front()) else: use_pager = int(self.get_argument("use_pager", 1)) page = int(self.get_argument("page", 1)) items_per_page = int(self.get_argument("items_per_page", 20)) search = self.arguments.get('search', "") orderby = self.arguments.get("orderby", "") searches = await self.add_tokens(user_schema.load(self.arguments, partial=True).data) if search: searches.update({"search": search}) keys = [] for _order in orderby.split(";"): if _order: keys.append(_order) item_count = await User.count(searches) if use_pager: limit = items_per_page skip = (page - 1) * items_per_page else: limit = 0 skip = 0 user_cursor = User.search(searches, limit=limit, skip=skip).order_by(keys) data = [await user.to_front() async for user in user_cursor] pager = Page(data, use_pager=use_pager, page=page, items_per_page=items_per_page, item_count=item_count) return SuccessData(data=pager.items, info=pager.info) @render async def post(self, user_id=None): if user_id: finds = await self.add_tokens({"id": user_id}) copys = user_schema.load(self.arguments, partial=True).data user = await User.find_and_copy(finds, copys) return SuccessData(id=user.id) else: creates = await self.add_tokens(user_schema.load(self.arguments).data) user = await User.create(creates) return SuccessData(id=user.id) @render async def put(self, user_id=None): finds = await self.add_tokens({"id": user_id}) updates = user_schema.load(self.arguments, partial=True).data user = await User.find_and_update(finds, updates) return SuccessData(id=user.id) @render async def delete(self, user_id=None): finds = await self.add_tokens({"id": user_id}) count = await User.find_and_delete(finds) return SuccessData(count=count) @render async def patch(self, user_id=None): create_list = [] for __create in self.arguments.get("create", []): creates = await self.add_tokens(user_schema.load(__create).data) user = await User.create(creates) create_list.append(user.id) update_list = [] for __update in self.arguments.get("update", []): if "find" in __update: finds = await self.add_tokens(__update.pop("find", {})) updates = user_schema.load(__update, partial=True).data user = await User.find_and_update(finds, updates) update_list.append(user.id) elif "search" in __update: searches = await self.add_tokens(__update.pop("search", {})) updates = user_schema.load(__update, partial=True).data user_list = await User.search_and_update(searches, updates) update_list.append(user_list) delete_list = [] for __delete in self.arguments.get("delete", []): if "find" in __delete: finds = await self.add_tokens(__delete.pop("find", {})) count = await User.find_and_delete(finds) delete_list.append(count) elif "search" in __delete: searches = await self.add_tokens(__delete.pop("search", {})) count = await User.search_and_delete(searches) delete_list.append(count) return SuccessData( create_list=create_list, update_list=update_list, delete_list=delete_list, ) def set_default_headers(self): self._headers.add("version", "1") class UserAuthHandler(BaseAuthedHanlder): async def add_tokens(self, params): params['user_id'] = bson.ObjectId(self.tokens.get("user_id")) return params @render async def get(self, user_auth_id=None): if user_auth_id: finds = await self.add_tokens({"id": user_auth_id}) user_auth = await UserAuth.find(finds) return SuccessData(data=await user_auth.to_front()) else: use_pager = int(self.get_argument("use_pager", 1)) page = int(self.get_argument("page", 1)) items_per_page = int(self.get_argument("items_per_page", 20)) search = self.arguments.get('search', "") orderby = self.arguments.get("orderby", "") searches = await self.add_tokens(user_auth_schema.load(self.arguments, partial=True).data) if search: searches.update({"search": search}) keys = [] for _order in orderby.split(";"): if _order: keys.append(_order) item_count = await UserAuth.count(searches) if use_pager: limit = items_per_page skip = (page - 1) * items_per_page else: limit = 0 skip = 0 user_auth_cursor = UserAuth.search(searches, limit=limit, skip=skip).order_by(keys) data = [await user_auth.to_front() async for user_auth in user_auth_cursor] pager = Page(data, use_pager=use_pager, page=page, items_per_page=items_per_page, item_count=item_count) return SuccessData(data=pager.items, info=pager.info) @render async def post(self, user_auth_id=None): if user_auth_id: finds = await self.add_tokens({"id": user_auth_id}) copys = user_auth_schema.load(self.arguments, partial=True).data user_auth = await UserAuth.find_and_copy(finds, copys) return SuccessData(id=user_auth.id) else: creates = await self.add_tokens(user_auth_schema.load(self.arguments).data) user_auth = await UserAuth.create(creates) return SuccessData(id=user_auth.id) @render async def put(self, user_auth_id=None): finds = await self.add_tokens({"id": user_auth_id}) updates = user_auth_schema.load(self.arguments, partial=True).data user_auth = await UserAuth.find_and_update(finds, updates) return SuccessData(id=user_auth.id) @render async def delete(self, user_auth_id=None): finds = await self.add_tokens({"id": user_auth_id}) count = await UserAuth.find_and_delete(finds) return SuccessData(count=count) @render async def patch(self, user_auth_id=None): create_list = [] for __create in self.arguments.get("create", []): creates = await self.add_tokens(user_auth_schema.load(__create).data) user_auth = await UserAuth.create(creates) create_list.append(user_auth.id) update_list = [] for __update in self.arguments.get("update", []): if "find" in __update: finds = await self.add_tokens(__update.pop("find", {})) updates = user_auth_schema.load(__update, partial=True).data user_auth = await UserAuth.find_and_update(finds, updates) update_list.append(user_auth.id) elif "search" in __update: searches = await self.add_tokens(__update.pop("search", {})) updates = user_auth_schema.load(__update, partial=True).data user_auth_list = await UserAuth.search_and_update(searches, updates) update_list.append(user_auth_list) delete_list = [] for __delete in self.arguments.get("delete", []): if "find" in __delete: finds = await self.add_tokens(__delete.pop("find", {})) count = await UserAuth.find_and_delete(finds) delete_list.append(count) elif "search" in __delete: searches = await self.add_tokens(__delete.pop("search", {})) count = await UserAuth.search_and_delete(searches) delete_list.append(count) return SuccessData( create_list=create_list, update_list=update_list, delete_list=delete_list, ) def set_default_headers(self): self._headers.add("version", "1") URL_MAPPING_LIST = [ url(r"/api/system/user/(?:([a-zA-Z0-9&%\.~-]+)/)?", UserHandler), url(r"/api/system/user_auth/(?:([a-zA-Z0-9&%\.~-]+)/)?", UserAuthHandler), ]

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0.049466

0.074199

0.891887

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9,337

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1

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0.040816

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0.142857

0

null

0

1

0

null

0

6

4ed6c998b8bf0cad96ce086f1bc7cea1c9f5a1bf

163

py

Python

json2text/__init__.py

xrdavies/json2text

afa83f6f59f74317fb64d1508818106ab4c27aeb

[ "MIT" ]

null

json2text/__init__.py

xrdavies/json2text

afa83f6f59f74317fb64d1508818106ab4c27aeb

[ "MIT" ]

null

json2text/__init__.py

xrdavies/json2text

afa83f6f59f74317fb64d1508818106ab4c27aeb

[ "MIT" ]

null

__version__ = '0.0.1' import sys if sys.version_info[0] > 2: from .json2text import JSON2Text, Text2JSON else: from .json2text import JSON2Text, Text2JSON

23.285714

47

0.736196

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163

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0.521739

0.226087

0.330435

0.486957

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1

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1

0

null

0

1

0

6

14d8b9d1f92ee74e247c533723e0706f914064f8

18,521

py

Python

billingclient/v1/rating/gnocchi/shell.py

nubeliu/billingclient

f2539e211ca049f3ddc9ce5680932f8f5eff7434

[ "Apache-2.0" ]

1

2018-01-04T16:20:51.000Z

billingclient/v1/rating/gnocchi/shell.py

nubeliu/billingclient

f2539e211ca049f3ddc9ce5680932f8f5eff7434

[ "Apache-2.0" ]

null

billingclient/v1/rating/gnocchi/shell.py

nubeliu/billingclient

f2539e211ca049f3ddc9ce5680932f8f5eff7434

[ "Apache-2.0" ]

null

# NubeliU Billing SDK # @autor: Sergio Colinas import functools from oslo_utils import strutils from billingclient.common import utils from billingclient import exc _bool_strict = functools.partial(strutils.bool_from_string, strict=True) @utils.arg('-m', '--gnocchi-metric', help='Associated gnocchi metric', required=True) @utils.arg('-f', '--aggregation-function', help='Aggregation function to use for calculations', required=True) @utils.arg('-gu', '--gnocchi-unit', help='Gnocchi Unit', required=True) @utils.arg('-bu', '--billing-unit', help='Billing Unit', required=False) def do_rating_metric_rule_set_create(cc, args={}): """Create a metric rule set.""" arg_to_field_mapping = { 'gnocchi_metric': 'gnocchi_metric', 'aggregation_function': 'aggregation_function', 'gnocchi_unit': 'gnocchi_unit', 'billing_unit': 'billing_unit' } fields = {} for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: fields[arg_to_field_mapping.get(k, k)] = v out = cc.gnocchi.metric_rule_sets.create(**fields) utils.print_dict(out.to_dict()) def do_rating_metric_rule_set_list(cc, args={}): """List metric rule sets.""" try: metric_rule_sets = cc.gnocchi.metric_rule_sets.list() except exc.HTTPNotFound: raise exc.CommandError('Metric rule sets not found: %s' % args.counter_name) else: field_labels = ['Gnocchi Metric', 'Aggregation Function', 'Gnocchi Unit', 'Billing Unit', 'Id'] fields = ['gnocchi_metric', 'aggregation_function', 'gnocchi_unit', 'billing_unit', 'id'] utils.print_list(metric_rule_sets, fields, field_labels, sortby=0) @utils.arg('-s', '--id', help='Metric rule set uuid', required=True) def do_rating_metric_rule_set_get(cc, args={}): """Get a metric rule set.""" try: metric_rule_set = cc.gnocchi.metric_rule_sets.get( metric_rule_set_id=args.id) utils.print_dict(metric_rule_set.to_dict()) except exc.HTTPNotFound: raise exc.CommandError('Metric rule set not found: %s' % args.counter_name) @utils.arg('-s', '--id', help='Metric rule set uuid', required=True) def do_rating_metric_rule_set_delete(cc, args={}): """Delete a metric rule set.""" try: cc.gnocchi.metric_rule_sets.delete(metric_rule_set_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metric rule set not found: %s' % args.counter_name) @utils.arg('-n', '--name', help='Metadata rule set name', required=True) @utils.arg('-s', '--metric-rule-set-id', help='Metric rule set id', required=True) def do_rating_metadata_rule_set_create(cc, args={}): """Create a metadata rule set.""" arg_to_field_mapping = { 'name': 'name', 'metric_rule_set_id': 'metric_rule_set_id' } fields = {} for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: fields[arg_to_field_mapping.get(k, k)] = v out = cc.gnocchi.metadata_rule_sets.create(**fields) utils.print_dict(out.to_dict()) @utils.arg('-t', '--id', help='Metadata rule set uuid', required=True) def do_rating_metadata_rule_set_get(cc, args={}): """Get a metadata rule set.""" try: metadata_rule_set = cc.gnocchi.metadata_rule_sets.get( metadata_rule_set_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule set not found: %s' % args.id) utils.print_dict(metadata_rule_set.to_dict()) @utils.arg('-rs', '--metric-rule-set-id', help='Metric rule set id', required=True) def do_rating_metadata_rule_set_list(cc, args={}): """List metadata rule sets.""" try: created_metadata_rule_set = cc.gnocchi.metadata_rule_sets.list( metric_rule_set_id=args.metric_rule_set_id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule sets not found: %s' % args.counter_name) else: field_labels = ['Id', 'Name', 'Metadata rule set id'] fields = ['id', 'name', 'metric_rule_set_id'] utils.print_list(created_metadata_rule_set, fields, field_labels, sortby=0) @utils.arg('-m', '--id', help='Metadata rule set uuid', required=True) def do_rating_metadata_rule_set_delete(cc, args={}): """Delete a metadata rule set.""" try: cc.gnocchi.metadata_rule_sets.delete(metadata_rule_set_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule set not found: %s' % args.counter_name) @utils.arg('-c', '--cost', help='Metric rule cost', required=True) @utils.arg('-t', '--type', help='Metric rule type (flat, rate)', required=False) @utils.arg('-s', '--metric-rule-set-id', help='Metric rule set id', required=False) @utils.arg('-vs', '--valid-since', help='Metric rule valid since', required=False) @utils.arg('-vu', '--valid-until', help='Metric rule valid until', required=False) @utils.arg('-p', '--providers', help='Metric rule providers (openstack or vmware)', required=False) def do_rating_metric_rule_create(cc, args={}): """Create a metric rule.""" arg_to_field_mapping = { 'cost': 'cost', 'type': 'type', 'metric_rule_set_id': 'metric_rule_set_id', 'valid_since': 'valid_since', 'valid_until': 'valid_until', 'providers': 'providers', } fields = {} for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: fields[arg_to_field_mapping.get(k, k)] = v out = cc.gnocchi.metric_rules.create(**fields) utils.print_dict(out.to_dict()) @utils.arg('-c', '--cost', help='Metadata rule cost', required=True) @utils.arg('-v', '--value', help='Metadata rule value', required=False) @utils.arg('-d', '--display-value', help='Metadata rule display name', required=False) @utils.arg('-t', '--type', help='Metadata rule type (flat, rate)', required=False) @utils.arg('-s', '--metadata-rule-set-id', help='Metadata rule set id', required=False) @utils.arg('-vs', '--valid-since', help='Metadata rule valid since', required=False) @utils.arg('-vu', '--valid-until', help='Metadata rule valid until', required=False) @utils.arg('-p', '--providers', help='Metadata rule providers (openstack or vmware)', required=False) def do_rating_metadata_rule_create(cc, args={}): """Create a metadata rule.""" arg_to_field_mapping = { 'cost': 'cost', 'value': 'value', 'display_value': 'display_value', 'type': 'type', 'metadata_rule_id': 'metadata_rule_id', 'valid_since': 'valid_since', 'valid_until': 'valid_until', 'providers': 'providers', } fields = {} for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: fields[arg_to_field_mapping.get(k, k)] = v out = cc.gnocchi.metadata_rules.create(**fields) utils.print_dict(out.to_dict()) @utils.arg('-m', '--id', help='Metric rule id', required=True) @utils.arg('-c', '--cost', help='Metric rule cost', required=False) @utils.arg('-t', '--type', help='Metric rule type (flat, rate)', required=False) @utils.arg('-s', '--valid-since', help='Metric rule valid since', required=False) @utils.arg('-u', '--valid-until', help='Metric rule valid until', required=False) @utils.arg('-p', '--providers', help='Metric rule providers (openstack or vmware)', required=False) def do_rating_metric_rule_update(cc, args={}): """Update a metric rule.""" arg_to_field_mapping = { 'id': 'id', 'cost': 'cost', 'type': 'type', 'valid_since': 'valid_since', 'valid_until': 'valid_until', 'providers': 'providers', } try: metric_rule = cc.gnocchi.metric_rules.get(id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metric rule not found: %s' % args.counter_name) for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: if k == 'valid_since': setattr(metric_rule, k, None) else: setattr(metric_rule, k, v) cc.gnocchi.metric_rules.update(**metric_rule.dirty_fields) @utils.arg('-m', '--id', help='Metadata rule id', required=True) @utils.arg('-c', '--cost', help='Metadata rule cost', required=False) @utils.arg('-v', '--value', help='Metadata rule value', required=False) @utils.arg('-d', '--display-value', help='Metadata rule display value', required=False) @utils.arg('-t', '--type', help='Metadata rule type (flat, rate)', required=False) @utils.arg('-s', '--valid-since', help='Metadata rule valid since', required=False) @utils.arg('-u', '--valid-until', help='Metadata rule valid until', required=False) @utils.arg('-p', '--providers', help='Metadata rule providers', required=False) def do_rating_mapping_update(cc, args={}): """Update a metadata rule.""" arg_to_field_mapping = { 'id': 'id', 'cost': 'cost', 'value': 'value', 'display_value': 'display_value', 'type': 'type', 'valid_since': 'valid_since', 'valid_until': 'valid_until', 'providers': 'providers', } try: metadata_rule = cc.gnocchi.metadata_rules.get(id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule not found: %s' % args.counter_name) for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: if k == 'valid_since': setattr(metadata_rule, k, None) else: setattr(metadata_rule, k, v) cc.gnocchi.metadata_rules.update(**metadata_rule.dirty_fields) @utils.arg('-s', '--metric-rule-set-id', help='Metric rule set id', required=False) def do_rating_metric_rule_list(cc, args={}): """List metric rules.""" if args.metric_rule_set_id is None: raise exc.CommandError("Provide metric-rule-set-id") try: metric_rules = cc.gnocchi.metric_rules.list( metric_rule_set_id=args.metric_rule_set_id) except exc.HTTPNotFound: raise exc.CommandError('Metric rule not found: %s' % args.counter_name) else: field_labels = ['Id', 'Cost', 'Type', 'Metric rule set id', 'Valid Since', 'Valid Until', 'Providers'] fields = ['id', 'cost', 'type', 'metric_rule_set_id', 'valid_since', 'valid_until', 'providers'] utils.print_list(metric_rules, fields, field_labels, sortby=0) @utils.arg('-f', '--metadata-rule-set-id', help='Metadata rule set id', required=False) def do_rating_metadata_rule_list(cc, args={}): """List metadata rules.""" if args.metadata_rule_set_id is None: raise exc.CommandError("Provide metadata-rule-set-id") try: metadata_rules = cc.gnocchi.metadata_rules.list( metadata_rule_set_id=args.metadata_rule_set_id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule not found: %s' % args.counter_name) else: field_labels = ['Id', 'Value', 'Display name', 'Cost', 'Type', 'Metadata rule set id', 'Valid Since', 'Valid Until', 'Providers'] fields = ['id', 'value', 'display_value', 'cost', 'type', 'metadata_rule_set_id', 'valid_since', 'valid_until', 'providers'] utils.print_list(metadata_rules, fields, field_labels, sortby=0) @utils.arg('-m', '--id', help='Metric rule uuid', required=True) def do_rating_metric_rule_get(cc, args={}): """Get a metric rule.""" try: cc.gnocchi.metric_rules.get(metric_rule_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metric rule not found: %s' % args.id) @utils.arg('-m', '--id', help='Metadata rule uuid', required=True) def do_rating_metadata_rule_get(cc, args={}): """Get a metadata rule.""" try: cc.gnocchi.metadata_rules.get(metadata_rule_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule not found: %s' % args.id) @utils.arg('-m', '--id', help='Metric rule uuid', required=True) def do_rating_metric_rule_delete(cc, args={}): """Delete a metric rule.""" try: cc.gnocchi.metric_rules.delete(metric_rule_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metric rule not found: %s' % args.id) @utils.arg('-m', '--id', help='Metadata rule uuid', required=True) def do_rating_metadata_rule_delete(cc, args={}): """Delete a metadata rule.""" try: cc.gnocchi.metadata_rules.delete(metadata_rule_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Metadata rule not found: %s' % args.id) @utils.arg('-l', '--level', help='Threshold level', required=True) @utils.arg('-c', '--cost', help='Threshold cost', required=True) @utils.arg('-m', '--map-type', help='Threshold type (flat, rate)', required=False) @utils.arg('-s', '--metric-rule-set-id', help='Metric rule set id', required=False) @utils.arg('-vs', '--valid-since', help='Valid Since', required=False) @utils.arg('-vu', '--valid-until', help='Valid Until', required=False) @utils.arg('-p', '--providers', help='Providers', required=False) def do_rating_threshold_rule_create(cc, args={}): """Create a threshold rule.""" arg_to_field_mapping = { 'level': 'level', 'cost': 'cost', 'type': 'type', 'metric_rule_set_id': 'metric_rule_set_id', 'valid_since': 'valid_since', 'valid_until': 'valid_until', 'providers': 'providers', } fields = {} for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: fields[arg_to_field_mapping.get(k, k)] = v out = cc.gnocchi.threshold_rules.create(**fields) utils.print_dict(out.to_dict()) @utils.arg('-t', '--id', help='Threshold id', required=True) @utils.arg('-l', '--level', help='Threshold level', required=False) @utils.arg('-c', '--cost', help='Threshold cost', required=False) @utils.arg('-m', '--type', help='Threshold type (flat or rate)', required=False) @utils.arg('-vs', '--valid-since', help='Valid Since', required=False) @utils.arg('-vu', '--valid-until', help='Valid Until', required=False) @utils.arg('-p', '--providers', help='Providers', required=False) def do_rating_threshold_rule_update(cc, args={}): """Update a threshold rule.""" arg_to_field_mapping = { 'id': 'id', 'cost': 'cost', 'level': 'level', 'type': 'type', 'valid_since': 'valid_since', 'valid_until': 'valid_until', 'providers': 'providers', } try: threshold_rule = cc.gnocchi.threshold_rules.get(id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Modules not found: %s' % args.counter_name) for k, v in vars(args).items(): if k in arg_to_field_mapping: if v is not None: setattr(threshold_rule, k, v) cc.gnocchi.threshold_rules.update(**threshold_rule.dirty_fields) @utils.arg('-rs', '--metric-rule-set-id', help='Metric rule set id', required=False) def do_rating_threshold_rule_list(cc, args={}): """List threshold rules.""" if args.metric_rule_set_id is None: raise exc.CommandError("Provide metric-rule-set-id") try: threshold_rules = cc.gnocchi.threshold_rules.list( metric_rule_set_id=args.metric_rule_set_id) except exc.HTTPNotFound: raise exc.CommandError('Threshold rule not found: %s' % args.counter_name) else: field_labels = ['Id', 'Level', 'Cost', 'Type', 'Metric rule set id', 'Valid Since', 'Valid Until', 'Providers'] fields = ['id', 'level', 'cost', 'type', 'metric_rule_set_id', 'valid_since', 'valid_until', 'providers'] utils.print_list(threshold_rules, fields, field_labels, sortby=0) @utils.arg('-t', '--id', help='Threshold rule uuid', required=True) def do_rating_threshold_rule_delete(cc, args={}): """Delete a threshold rule.""" try: cc.gnocchi.threshold_rules.delete(threshold_rule_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Threshold rule not found: %s' % args.id) @utils.arg('-t', '--id', help='Threshold rule uuid', required=True) def do_rating_threshold_rule_get(cc, args={}): """Get a threshold rule.""" try: threshold_rule = cc.gnocchi.threshold_rules.get( threshold_rule_id=args.id) except exc.HTTPNotFound: raise exc.CommandError('Threshold rule not found: %s' % args.id) utils.print_dict(threshold_rule.to_dict())

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6

14ecf89a3ce6ef39e8aa28237f0ead0cc31afd0a

132

py

Python

pymtl3/stdlib/test/__init__.py

hsqforfun/pymtl3

05e06601cf262a663a95d1235cb99056ece84580

[ "BSD-3-Clause" ]

1

2019-11-12T12:26:01.000Z

pymtl3/stdlib/test/__init__.py

hsqforfun/pymtl3

05e06601cf262a663a95d1235cb99056ece84580

[ "BSD-3-Clause" ]

null

pymtl3/stdlib/test/__init__.py

hsqforfun/pymtl3

05e06601cf262a663a95d1235cb99056ece84580

[ "BSD-3-Clause" ]

null

from .test_sinks import TestSinkCL from .test_srcs import TestSrcCL from .test_utils import TestVectorSimulator, mk_test_case_table

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6

090d861a69194acff01f45da1b38433fa9ad0a19

30

py

Python

models/__init__.py

yifanfeng97/OS-MN40-Example

ca0e9b8017cdb95a2bf8dfdd6b8fbd284c8d97aa

[ "MIT" ]

11

2022-01-16T07:35:45.000Z

2022-03-04T02:55:41.000Z

models/__init__.py

yifanfeng97/OS-MN40-Example

ca0e9b8017cdb95a2bf8dfdd6b8fbd284c8d97aa

[ "MIT" ]

null

models/__init__.py

yifanfeng97/OS-MN40-Example

ca0e9b8017cdb95a2bf8dfdd6b8fbd284c8d97aa

[ "MIT" ]

null

from .combine import UniModel

15

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6

0921d7d5c4330f4ad16093a9b76e66ab2fbdadbc

149

py

Python

{{cookiecutter.project_slug}}/app/connection/db_instance.py

ActivandoIdeas/Cookiecutter-Flask-Microservice-SQLAlchemy

c002de1bf620eb57130c5ef6159a302afb6abcb2

[ "BSD-3-Clause" ]

null

{{cookiecutter.project_slug}}/app/connection/db_instance.py

ActivandoIdeas/Cookiecutter-Flask-Microservice-SQLAlchemy

c002de1bf620eb57130c5ef6159a302afb6abcb2

[ "BSD-3-Clause" ]

null

{{cookiecutter.project_slug}}/app/connection/db_instance.py

ActivandoIdeas/Cookiecutter-Flask-Microservice-SQLAlchemy

c002de1bf620eb57130c5ef6159a302afb6abcb2

[ "BSD-3-Clause" ]

null

"""Generate db instance for SQLAlchemy""" from flask_sqlalchemy import SQLAlchemy from .database import metadata db = SQLAlchemy(metadata=metadata)

24.833333

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1

0

6

092804802f17d92db033bf0dc07d5b6f25768639

6,496

py

Python

Piano.py

saransha/EasyElectric

7d2642accdd2b06572f9eda70feb0617cbb9785e

[ "MIT" ]

1

2020-03-19T16:31:52.000Z

Piano.py

saransha/EasyElectric

7d2642accdd2b06572f9eda70feb0617cbb9785e

[ "MIT" ]

null

Piano.py

saransha/EasyElectric

7d2642accdd2b06572f9eda70feb0617cbb9785e

[ "MIT" ]

null

import pygame pygame.init() class Piano(object): def __init__(self): self.A0=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A0.wav') self.A1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A1.wav') self.A2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A2.wav') self.A3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A3.wav') self.A4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A4.wav') self.A5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A5.wav') self.A6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A6.wav') self.A7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.A7.wav') self.Ab1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab1.wav') self.Ab2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab2.wav') self.Ab3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab3.wav') self.Ab4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab4.wav') self.Ab5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab5.wav') self.Ab6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab6.wav') self.Ab7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Ab7.wav') self.B0=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B0.wav') self.B1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B1.wav') self.B2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B2.wav') self.B3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B3.wav') self.B4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B4.wav') self.B5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B5.wav') self.B6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B6.wav') self.B7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.B7.wav') self.Bb0=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb0.wav') self.Bb1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb1.wav') self.Bb2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb2.wav') self.Bb3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb3.wav') self.Bb4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb4.wav') self.Bb5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb5.wav') self.Bb6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb6.wav') self.Bb7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Bb7.wav') self.C1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C1.wav') self.C2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C2.wav') self.C3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C3.wav') self.C4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C4.wav') self.C5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C5.wav') self.C6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C6.wav') self.C7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C7.wav') self.C8=pygame.mixer.Sound(file='Piano WAV/Piano.ff.C8.wav') self.D1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D1.wav') self.D2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D2.wav') self.D3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D3.wav') self.D4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D4.wav') self.D5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D5.wav') self.D6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D6.wav') self.D7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.D7.wav') self.Db1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db1.wav') self.Db2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db2.wav') self.Db3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db3.wav') self.Db4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db4.wav') self.Db5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db5.wav') self.Db6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db6.wav') self.Db7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Db7.wav') self.E1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E1.wav') self.E2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E2.wav') self.E3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E3.wav') self.E4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E4.wav') self.E5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E5.wav') self.E6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E6.wav') self.E7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.E7.wav') self.Eb1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb1.wav') self.Eb2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb2.wav') self.Eb3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb3.wav') self.Eb4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb4.wav') self.Eb5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb5.wav') self.Eb6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb6.wav') self.Eb7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Eb7.wav') self.F1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F1.wav') self.F2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F2.wav') self.F3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F3.wav') self.F4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F4.wav') self.F5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F5.wav') self.F6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F6.wav') self.F7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.F7.wav') self.G1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G1.wav') self.G2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G2.wav') self.G3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G3.wav') self.G4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G4.wav') self.G5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G5.wav') self.G6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G6.wav') self.G7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.G7.wav') self.Gb1=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb1.wav') self.Gb2=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb2.wav') self.Gb3=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb3.wav') self.Gb4=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb4.wav') self.Gb5=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb5.wav') self.Gb6=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb6.wav') self.Gb7=pygame.mixer.Sound(file='Piano WAV/Piano.ff.Gb7.wav') self.notes=[] self.hscrollDX=0 self.pianoGrid = pygame.image.load('Piano grid.png').convert_alpha() self.sx2,self.sx3=0,870 self.scrollGrid=(self.sx2,0,self.sx3,350) def __str__(self): return "self.piano"

61.283019

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0.666256

1,101

6,496

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0.224126

0.326001

0.407502

0.713128

0

0.034245

0.1504

6,496

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false

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