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AI4EDA-CASELAB

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https://github.com/NellyW8
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Nellyw888 
updated a collection 8 months ago

Verireason

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Dataset and Model for paper: "VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation" • 8 items • Updated 2 days ago • 2
Nellyw888 
authored 2 papers 9 months ago

SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning

Paper • 2504.10369 • Published Apr 14, 2025 • 2

VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Paper • 2505.11849 • Published May 17, 2025 • 2
Nellyw888 
updated a collection 9 months ago

Verireason

Collection
Dataset and Model for paper: "VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation" • 8 items • Updated 2 days ago • 2
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