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16bitupgrade.md

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-16-BIT TENSOR MANIFEST
-
-  ---
-  ARITHMETIC
-
-  ripplecarry16bit
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-  arithmetic.ripplecarry16bit.fa0.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa0.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa0.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa1.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa1.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa1.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa1.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa2.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa2.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa2.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa2.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa3.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa3.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa3.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa3.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa4.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa4.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa4.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa4.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa5.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa5.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa5.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa5.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa6.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa6.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa6.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa6.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa7.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa7.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa7.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa7.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa8.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa8.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa8.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa8.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa9.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa9.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa9.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa9.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa10.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa10.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa10.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa10.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa11.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa11.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa11.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa11.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa12.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa12.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa12.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa12.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa13.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa13.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa13.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa13.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa14.carry_or.bias [1]
-  arithmetic.ripplecarry16bit.fa14.carry_or.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa14.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa14.ha2.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa15.carry_or.bias [1]
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-  arithmetic.ripplecarry16bit.fa15.ha1.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha1.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha1.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha1.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha1.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha1.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha1.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha1.sum.layer2.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha2.carry.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha2.carry.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha2.sum.layer1.nand.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha2.sum.layer1.nand.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha2.sum.layer1.or.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha2.sum.layer1.or.weight [2]
-  arithmetic.ripplecarry16bit.fa15.ha2.sum.layer2.bias [1]
-  arithmetic.ripplecarry16bit.fa15.ha2.sum.layer2.weight [2]
-
-  16-bit comparators
-  arithmetic.greaterthan16bit.comparator [16]
-  arithmetic.lessthan16bit.comparator [16]
-
-  16x16 multiplier (14 stages, bits 0-30 per stage where applicable)
-
-  Stage 0: bits 0-16
-  Stage 1: bits 0-17
-  Stage 2: bits 0-18
-  ...
-  Stage 13: bits 0-30
-
-  Each bit position has the same full adder structure. Total enumeration:
-
-  arithmetic.multiplier16x16.stage0.bit0.carry_or.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.carry_or.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.carry.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.carry.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.sum.layer1.nand.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.sum.layer1.nand.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.sum.layer1.or.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.sum.layer1.or.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.sum.layer2.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha1.sum.layer2.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.carry.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.carry.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.sum.layer1.nand.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.sum.layer1.nand.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.sum.layer1.or.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.sum.layer1.or.weight [2]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.sum.layer2.bias [1]
-  arithmetic.multiplier16x16.stage0.bit0.ha2.sum.layer2.weight [2]
-
-  Pattern repeats for:
-  - stage0: bit0-bit16 (17 bits)
-  - stage1: bit0-bit17 (18 bits)
-  - stage2: bit0-bit18 (19 bits)
-  - stage3: bit0-bit19 (20 bits)
-  - stage4: bit0-bit20 (21 bits)
-  - stage5: bit0-bit21 (22 bits)
-  - stage6: bit0-bit22 (23 bits)
-  - stage7: bit0-bit23 (24 bits)
-  - stage8: bit0-bit24 (25 bits)
-  - stage9: bit0-bit25 (26 bits)
-  - stage10: bit0-bit26 (27 bits)
-  - stage11: bit0-bit27 (28 bits)
-  - stage12: bit0-bit28 (29 bits)
-  - stage13: bit0-bit29 (30 bits)
-
-  18 tensors per bit × (17+18+19+20+21+22+23+24+25+26+27+28+29+30) = 18 × 329 = 5922 tensors for multiplier stages.
-
-  Plus 256 AND gates for partial products (16×16):
-  arithmetic.multiplier16x16.partial.r0c0.bias [1]
-  arithmetic.multiplier16x16.partial.r0c0.weight [2]
-  ...through...
-  arithmetic.multiplier16x16.partial.r15c15.bias [1]
-  arithmetic.multiplier16x16.partial.r15c15.weight [2]
-  256 × 2 = 512 tensors for partial products.
-
-  ---
-  COMBINATIONAL
-
-  Barrel shifter 16-bit
-  combinational.barrelshifter16bit.shift [20]
-
-  Decoder 4-to-16
-  combinational.decoder4to16.out0.bias [1]
-  combinational.decoder4to16.out0.weight [4]
-  combinational.decoder4to16.out1.bias [1]
-  combinational.decoder4to16.out1.weight [4]
-  combinational.decoder4to16.out2.bias [1]
-  combinational.decoder4to16.out2.weight [4]
-  combinational.decoder4to16.out3.bias [1]
-  combinational.decoder4to16.out3.weight [4]
-  combinational.decoder4to16.out4.bias [1]
-  combinational.decoder4to16.out4.weight [4]
-  combinational.decoder4to16.out5.bias [1]
-  combinational.decoder4to16.out5.weight [4]
-  combinational.decoder4to16.out6.bias [1]
-  combinational.decoder4to16.out6.weight [4]
-  combinational.decoder4to16.out7.bias [1]
-  combinational.decoder4to16.out7.weight [4]
-  combinational.decoder4to16.out8.bias [1]
-  combinational.decoder4to16.out8.weight [4]
-  combinational.decoder4to16.out9.bias [1]
-  combinational.decoder4to16.out9.weight [4]
-  combinational.decoder4to16.out10.bias [1]
-  combinational.decoder4to16.out10.weight [4]
-  combinational.decoder4to16.out11.bias [1]
-  combinational.decoder4to16.out11.weight [4]
-  combinational.decoder4to16.out12.bias [1]
-  combinational.decoder4to16.out12.weight [4]
-  combinational.decoder4to16.out13.bias [1]
-  combinational.decoder4to16.out13.weight [4]
-  combinational.decoder4to16.out14.bias [1]
-  combinational.decoder4to16.out14.weight [4]
-  combinational.decoder4to16.out15.bias [1]
-  combinational.decoder4to16.out15.weight [4]
-
-  Encoder 16-to-4
-  combinational.encoder16to4.bit0.bias [1]
-  combinational.encoder16to4.bit0.weight [16]
-  combinational.encoder16to4.bit1.bias [1]
-  combinational.encoder16to4.bit1.weight [16]
-  combinational.encoder16to4.bit2.bias [1]
-  combinational.encoder16to4.bit2.weight [16]
-  combinational.encoder16to4.bit3.bias [1]
-  combinational.encoder16to4.bit3.weight [16]
-
-  Multiplexer 16-to-1
-  combinational.multiplexer16to1.select [20]
-
-  Demultiplexer 1-to-16
-  combinational.demultiplexer1to16.decode [5]
-
-  Priority encoder 16-bit
-  combinational.priorityencoder16bit.priority [16]
-
-  ---
-  CONTROL
-
-  Unconditional jump 16-bit
-  control.jump.bit0.bias [1]
-  control.jump.bit0.weight [1]
-  control.jump.bit1.bias [1]
-  control.jump.bit1.weight [1]
-  control.jump.bit2.bias [1]
-  control.jump.bit2.weight [1]
-  control.jump.bit3.bias [1]
-  control.jump.bit3.weight [1]
-  control.jump.bit4.bias [1]
-  control.jump.bit4.weight [1]
-  control.jump.bit5.bias [1]
-  control.jump.bit5.weight [1]
-  control.jump.bit6.bias [1]
-  control.jump.bit6.weight [1]
-  control.jump.bit7.bias [1]
-  control.jump.bit7.weight [1]
-  control.jump.bit8.bias [1]
-  control.jump.bit8.weight [1]
-  control.jump.bit9.bias [1]
-  control.jump.bit9.weight [1]
-  control.jump.bit10.bias [1]
-  control.jump.bit10.weight [1]
-  control.jump.bit11.bias [1]
-  control.jump.bit11.weight [1]
-  control.jump.bit12.bias [1]
-  control.jump.bit12.weight [1]
-  control.jump.bit13.bias [1]
-  control.jump.bit13.weight [1]
-  control.jump.bit14.bias [1]
-  control.jump.bit14.weight [1]
-  control.jump.bit15.bias [1]
-  control.jump.bit15.weight [1]
-
-  Conditional jump 16-bit (template for JZ, JNZ, JC, JNC, JN, JP, JV, JNV, and generic conditionaljump)
-
-  Each conditional jump type follows this pattern for bits 0-15:
-  control.{jtype}.bit{N}.and_a.bias [1]
-  control.{jtype}.bit{N}.and_a.weight [2]
-  control.{jtype}.bit{N}.and_b.bias [1]
-  control.{jtype}.bit{N}.and_b.weight [2]
-  control.{jtype}.bit{N}.not_sel.bias [1]
-  control.{jtype}.bit{N}.not_sel.weight [1]
-  control.{jtype}.bit{N}.or.bias [1]
-  control.{jtype}.bit{N}.or.weight [2]
-
-  Where {jtype} ∈ {conditionaljump, jz, jnz, jc, jnc, jn, jp, jv, jnv} and N ∈ {0..15}
-
-  Full expansion for control.jz (others follow same pattern):
-  control.jz.bit0.and_a.bias [1]
-  control.jz.bit0.and_a.weight [2]
-  control.jz.bit0.and_b.bias [1]
-  control.jz.bit0.and_b.weight [2]
-  control.jz.bit0.not_sel.bias [1]
-  control.jz.bit0.not_sel.weight [1]
-  control.jz.bit0.or.bias [1]
-  control.jz.bit0.or.weight [2]
-  control.jz.bit1.and_a.bias [1]
-  control.jz.bit1.and_a.weight [2]
-  control.jz.bit1.and_b.bias [1]
-  control.jz.bit1.and_b.weight [2]
-  control.jz.bit1.not_sel.bias [1]
-  control.jz.bit1.not_sel.weight [1]
-  control.jz.bit1.or.bias [1]
-  control.jz.bit1.or.weight [2]
-  control.jz.bit2.and_a.bias [1]
-  control.jz.bit2.and_a.weight [2]
-  control.jz.bit2.and_b.bias [1]
-  control.jz.bit2.and_b.weight [2]
-  control.jz.bit2.not_sel.bias [1]
-  control.jz.bit2.not_sel.weight [1]
-  control.jz.bit2.or.bias [1]
-  control.jz.bit2.or.weight [2]
-  control.jz.bit3.and_a.bias [1]
-  control.jz.bit3.and_a.weight [2]
-  control.jz.bit3.and_b.bias [1]
-  control.jz.bit3.and_b.weight [2]
-  control.jz.bit3.not_sel.bias [1]
-  control.jz.bit3.not_sel.weight [1]
-  control.jz.bit3.or.bias [1]
-  control.jz.bit3.or.weight [2]
-  control.jz.bit4.and_a.bias [1]
-  control.jz.bit4.and_a.weight [2]
-  control.jz.bit4.and_b.bias [1]
-  control.jz.bit4.and_b.weight [2]
-  control.jz.bit4.not_sel.bias [1]
-  control.jz.bit4.not_sel.weight [1]
-  control.jz.bit4.or.bias [1]
-  control.jz.bit4.or.weight [2]
-  control.jz.bit5.and_a.bias [1]
-  control.jz.bit5.and_a.weight [2]
-  control.jz.bit5.and_b.bias [1]
-  control.jz.bit5.and_b.weight [2]
-  control.jz.bit5.not_sel.bias [1]
-  control.jz.bit5.not_sel.weight [1]
-  control.jz.bit5.or.bias [1]
-  control.jz.bit5.or.weight [2]
-  control.jz.bit6.and_a.bias [1]
-  control.jz.bit6.and_a.weight [2]
-  control.jz.bit6.and_b.bias [1]
-  control.jz.bit6.and_b.weight [2]
-  control.jz.bit6.not_sel.bias [1]
-  control.jz.bit6.not_sel.weight [1]
-  control.jz.bit6.or.bias [1]
-  control.jz.bit6.or.weight [2]
-  control.jz.bit7.and_a.bias [1]
-  control.jz.bit7.and_a.weight [2]
-  control.jz.bit7.and_b.bias [1]
-  control.jz.bit7.and_b.weight [2]
-  control.jz.bit7.not_sel.bias [1]
-  control.jz.bit7.not_sel.weight [1]
-  control.jz.bit7.or.bias [1]
-  control.jz.bit7.or.weight [2]
-  control.jz.bit8.and_a.bias [1]
-  control.jz.bit8.and_a.weight [2]
-  control.jz.bit8.and_b.bias [1]
-  control.jz.bit8.and_b.weight [2]
-  control.jz.bit8.not_sel.bias [1]
-  control.jz.bit8.not_sel.weight [1]
-  control.jz.bit8.or.bias [1]
-  control.jz.bit8.or.weight [2]
-  control.jz.bit9.and_a.bias [1]
-  control.jz.bit9.and_a.weight [2]
-  control.jz.bit9.and_b.bias [1]
-  control.jz.bit9.and_b.weight [2]
-  control.jz.bit9.not_sel.bias [1]
-  control.jz.bit9.not_sel.weight [1]
-  control.jz.bit9.or.bias [1]
-  control.jz.bit9.or.weight [2]
-  control.jz.bit10.and_a.bias [1]
-  control.jz.bit10.and_a.weight [2]
-  control.jz.bit10.and_b.bias [1]
-  control.jz.bit10.and_b.weight [2]
-  control.jz.bit10.not_sel.bias [1]
-  control.jz.bit10.not_sel.weight [1]
-  control.jz.bit10.or.bias [1]
-  control.jz.bit10.or.weight [2]
-  control.jz.bit11.and_a.bias [1]
-  control.jz.bit11.and_a.weight [2]
-  control.jz.bit11.and_b.bias [1]
-  control.jz.bit11.and_b.weight [2]
-  control.jz.bit11.not_sel.bias [1]
-  control.jz.bit11.not_sel.weight [1]
-  control.jz.bit11.or.bias [1]
-  control.jz.bit11.or.weight [2]
-  control.jz.bit12.and_a.bias [1]
-  control.jz.bit12.and_a.weight [2]
-  control.jz.bit12.and_b.bias [1]
-  control.jz.bit12.and_b.weight [2]
-  control.jz.bit12.not_sel.bias [1]
-  control.jz.bit12.not_sel.weight [1]
-  control.jz.bit12.or.bias [1]
-  control.jz.bit12.or.weight [2]
-  control.jz.bit13.and_a.bias [1]
-  control.jz.bit13.and_a.weight [2]
-  control.jz.bit13.and_b.bias [1]
-  control.jz.bit13.and_b.weight [2]
-  control.jz.bit13.not_sel.bias [1]
-  control.jz.bit13.not_sel.weight [1]
-  control.jz.bit13.or.bias [1]
-  control.jz.bit13.or.weight [2]
-  control.jz.bit14.and_a.bias [1]
-  control.jz.bit14.and_a.weight [2]
-  control.jz.bit14.and_b.bias [1]
-  control.jz.bit14.and_b.weight [2]
-  control.jz.bit14.not_sel.bias [1]
-  control.jz.bit14.not_sel.weight [1]
-  control.jz.bit14.or.bias [1]
-  control.jz.bit14.or.weight [2]
-  control.jz.bit15.and_a.bias [1]
-  control.jz.bit15.and_a.weight [2]
-  control.jz.bit15.and_b.bias [1]
-  control.jz.bit15.and_b.weight [2]
-  control.jz.bit15.not_sel.bias [1]
-  control.jz.bit15.not_sel.weight [1]
-  control.jz.bit15.or.bias [1]
-  control.jz.bit15.or.weight [2]
-
-  Repeat above for: jnz, jc, jnc, jn, jp, jv, jnv, conditionaljump (9 types × 16 bits × 8 tensors = 1152 tensors)
-
-  Stack operations (unchanged)
-  control.call.jump [1]
-  control.call.push [1]
-  control.pop.load [1]
-  control.pop.sp_inc [1]
-  control.push.sp_dec [1]
-  control.push.store [1]
-  control.ret.jump [1]
-  control.ret.pop [1]
-  control.sp_dec.uses [1]
-  control.sp_inc.uses [1]
-
-  ---
-  ERROR DETECTION
-
-  Checksum 16-bit
-  error_detection.checksum16bit.sum.bias [1]
-  error_detection.checksum16bit.sum.weight [16]
-
-  Parity 16-bit
-  error_detection.evenparitychecker16bit.bias [1]
-  error_detection.evenparitychecker16bit.weight [16]
-  error_detection.oddparitychecker16bit.not.bias [1]
-  error_detection.oddparitychecker16bit.not.weight [1]
-  error_detection.oddparitychecker16bit.parity.bias [1]
-  error_detection.oddparitychecker16bit.parity.weight [16]
-
-  Parity checker/generator 16-bit (4 XOR stages instead of 3)
-  error_detection.paritychecker16bit.output.not.bias [1]
-  error_detection.paritychecker16bit.output.not.weight [1]
-  error_detection.paritychecker16bit.stage1.xor0.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor0.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor0.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor0.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor0.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor0.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor1.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor1.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor1.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor1.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor1.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor1.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor2.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor2.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor2.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor2.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor2.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor2.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor3.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor3.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor3.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor3.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor3.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor3.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor4.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor4.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor4.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor4.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor4.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor4.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor5.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor5.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor5.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor5.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor5.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor5.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor6.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor6.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor6.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor6.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor6.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor6.layer2.weight [2]
-  error_detection.paritychecker16bit.stage1.xor7.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage1.xor7.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage1.xor7.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage1.xor7.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage1.xor7.layer2.bias [1]
-  error_detection.paritychecker16bit.stage1.xor7.layer2.weight [2]
-  error_detection.paritychecker16bit.stage2.xor0.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage2.xor0.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage2.xor0.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage2.xor0.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage2.xor0.layer2.bias [1]
-  error_detection.paritychecker16bit.stage2.xor0.layer2.weight [2]
-  error_detection.paritychecker16bit.stage2.xor1.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage2.xor1.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage2.xor1.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage2.xor1.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage2.xor1.layer2.bias [1]
-  error_detection.paritychecker16bit.stage2.xor1.layer2.weight [2]
-  error_detection.paritychecker16bit.stage2.xor2.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage2.xor2.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage2.xor2.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage2.xor2.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage2.xor2.layer2.bias [1]
-  error_detection.paritychecker16bit.stage2.xor2.layer2.weight [2]
-  error_detection.paritychecker16bit.stage2.xor3.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage2.xor3.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage2.xor3.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage2.xor3.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage2.xor3.layer2.bias [1]
-  error_detection.paritychecker16bit.stage2.xor3.layer2.weight [2]
-  error_detection.paritychecker16bit.stage3.xor0.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage3.xor0.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage3.xor0.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage3.xor0.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage3.xor0.layer2.bias [1]
-  error_detection.paritychecker16bit.stage3.xor0.layer2.weight [2]
-  error_detection.paritychecker16bit.stage3.xor1.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage3.xor1.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage3.xor1.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage3.xor1.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage3.xor1.layer2.bias [1]
-  error_detection.paritychecker16bit.stage3.xor1.layer2.weight [2]
-  error_detection.paritychecker16bit.stage4.xor0.layer1.nand.bias [1]
-  error_detection.paritychecker16bit.stage4.xor0.layer1.nand.weight [2]
-  error_detection.paritychecker16bit.stage4.xor0.layer1.or.bias [1]
-  error_detection.paritychecker16bit.stage4.xor0.layer1.or.weight [2]
-  error_detection.paritychecker16bit.stage4.xor0.layer2.bias [1]
-  error_detection.paritychecker16bit.stage4.xor0.layer2.weight [2]
-
-  Identical structure for paritygenerator16bit.
-
-  CRC-16
-  error_detection.crc16.divisor [17]
-
-  Hamming (15,11) - 11 data bits, 4 parity bits
-  error_detection.hammingencode11bit.p0.weight [11]
-  error_detection.hammingencode11bit.p1.bias [1]
-  error_detection.hammingencode11bit.p1.weight [11]
-  error_detection.hammingencode11bit.p2.bias [1]
-  error_detection.hammingencode11bit.p2.weight [11]
-  error_detection.hammingencode11bit.p3.bias [1]
-  error_detection.hammingencode11bit.p3.weight [11]
-  error_detection.hammingencode11bit.p4.bias [1]
-  error_detection.hammingencode11bit.p4.weight [11]
-  error_detection.hammingdecode15bit.s1.bias [1]
-  error_detection.hammingdecode15bit.s1.weight [8]
-  error_detection.hammingdecode15bit.s2.bias [1]
-  error_detection.hammingdecode15bit.s2.weight [8]
-  error_detection.hammingdecode15bit.s3.bias [1]
-  error_detection.hammingdecode15bit.s3.weight [8]
-  error_detection.hammingdecode15bit.s4.bias [1]
-  error_detection.hammingdecode15bit.s4.weight [8]
-  error_detection.hammingsyndrome15bit.s1.weight [8]
-  error_detection.hammingsyndrome15bit.s2.weight [8]
-  error_detection.hammingsyndrome15bit.s3.weight [8]
-  error_detection.hammingsyndrome15bit.s4.weight [8]
-
-  Longitudinal parity 16-bit
-  error_detection.longitudinalparity16bit.col_parity [16]
-  error_detection.longitudinalparity16bit.row_parity [16]
-
-  ---
-  MODULAR
-
-  For 16-bit inputs, modular arithmetic requires detecting which of ceil(65536/N) ranges the input falls into. Structure per modulus:
-
-  mod2 (simple - just check LSB)
-  modular.mod2_16bit.bias [1]
-  modular.mod2_16bit.weight [16]
-
-  mod4 (check 2 LSBs)
-  modular.mod4_16bit.bias [1]
-  modular.mod4_16bit.weight [16]
-
-  mod8 (check 3 LSBs)
-  modular.mod8_16bit.bias [1]
-  modular.mod8_16bit.weight [16]
-
-  mod16 (check 4 LSBs)
-  modular.mod16_16bit.bias [1]
-  modular.mod16_16bit.weight [16]
-
-  For non-power-of-2 moduli (3, 5, 6, 7, 9, 10, 11, 12), use iterative subtraction circuit referencing the 16-bit subtractor and comparator, or expand the range-check approach:
-
-  mod3, mod5, mod6, mod7, mod9, mod10, mod11, mod12 (range-check approach, pattern):
-  modular.mod{N}_16bit.layer1.geq{K}.bias [1]
-  modular.mod{N}_16bit.layer1.geq{K}.weight [16]
-  modular.mod{N}_16bit.layer1.leq{K}.bias [1]
-  modular.mod{N}_16bit.layer1.leq{K}.weight [16]
-  modular.mod{N}_16bit.layer2.eq{K}.bias [1]
-  modular.mod{N}_16bit.layer2.eq{K}.weight [2]
-  modular.mod{N}_16bit.layer3.or.bias [1]
-  modular.mod{N}_16bit.layer3.or.weight [R]
-
-  Where R = number of ranges = ceil(65536/N).
-
-  ---
-  PATTERN RECOGNITION
-
-  pattern_recognition.popcount16bit.bias [1]
-  pattern_recognition.popcount16bit.weight [16]
-  pattern_recognition.allones16bit.bias [1]
-  pattern_recognition.allones16bit.weight [16]
-  pattern_recognition.allzeros16bit.bias [1]
-  pattern_recognition.allzeros16bit.weight [16]
-  pattern_recognition.alternating16bit.pattern1.weight [16]
-  pattern_recognition.alternating16bit.pattern2.weight [16]
-  pattern_recognition.hammingdistance16bit.popcount.weight [16]
-  pattern_recognition.hammingdistance16bit.xor.weight [32]
-  pattern_recognition.leadingones16bit.weight [16]
-  pattern_recognition.trailingones16bit.weight [16]
-  pattern_recognition.runlength16bit.weight [16]
-  pattern_recognition.onehotdetector16bit.and.bias [1]
-  pattern_recognition.onehotdetector16bit.and.weight [2]
-  pattern_recognition.onehotdetector16bit.atleast1.bias [1]
-  pattern_recognition.onehotdetector16bit.atleast1.weight [16]
-  pattern_recognition.onehotdetector16bit.atmost1.bias [1]
-  pattern_recognition.onehotdetector16bit.atmost1.weight [16]
-  pattern_recognition.symmetry16bit.and.bias [1]
-  pattern_recognition.symmetry16bit.and.weight [8]
-  pattern_recognition.symmetry16bit.xnor0.weight [2]
-  pattern_recognition.symmetry16bit.xnor1.weight [2]
-  pattern_recognition.symmetry16bit.xnor2.weight [2]
-  pattern_recognition.symmetry16bit.xnor3.weight [2]
-  pattern_recognition.symmetry16bit.xnor4.weight [2]
-  pattern_recognition.symmetry16bit.xnor5.weight [2]
-  pattern_recognition.symmetry16bit.xnor6.weight [2]
-  pattern_recognition.symmetry16bit.xnor7.weight [2]
-
-  ---
-  THRESHOLD
-
-  threshold.alloutof16.bias [1]
-  threshold.alloutof16.weight [16]
-  threshold.oneoutof16.bias [1]
-  threshold.oneoutof16.weight [16]
-  threshold.twooutof16.bias [1]
-  threshold.twooutof16.weight [16]
-  threshold.threeoutof16.bias [1]
-  threshold.threeoutof16.weight [16]
-  threshold.fouroutof16.bias [1]
-  threshold.fouroutof16.weight [16]
-  threshold.fiveoutof16.bias [1]
-  threshold.fiveoutof16.weight [16]
-  threshold.sixoutof16.bias [1]
-  threshold.sixoutof16.weight [16]
-  threshold.sevenoutof16.bias [1]
-  threshold.sevenoutof16.weight [16]
-  threshold.eightoutof16.bias [1]
-  threshold.eightoutof16.weight [16]
-  threshold.nineoutof16.bias [1]
-  threshold.nineoutof16.weight [16]
-  threshold.tenoutof16.bias [1]
-  threshold.tenoutof16.weight [16]
-  threshold.elevenoutof16.bias [1]
-  threshold.elevenoutof16.weight [16]
-  threshold.twelveoutof16.bias [1]
-  threshold.twelveoutof16.weight [16]
-  threshold.thirteenoutof16.bias [1]
-  threshold.thirteenoutof16.weight [16]
-  threshold.fourteenoutof16.bias [1]
-  threshold.fourteenoutof16.weight [16]
-  threshold.fifteenoutof16.bias [1]
-  threshold.fifteenoutof16.weight [16]
-  threshold.sixteenoutof16.bias [1]
-  threshold.sixteenoutof16.weight [16]
-  threshold.majority16.bias [1]
-  threshold.majority16.weight [16]
-  threshold.minority16.bias [1]
-  threshold.minority16.weight [16]
-  threshold.atleastk_8_16bit.bias [1]
-  threshold.atleastk_8_16bit.weight [16]
-  threshold.atmostk_8_16bit.bias [1]
-  threshold.atmostk_8_16bit.weight [16]
-  threshold.exactlyk_8_16bit.and.bias [1]
-  threshold.exactlyk_8_16bit.and.weight [2]
-  threshold.exactlyk_8_16bit.atleast.bias [1]
-  threshold.exactlyk_8_16bit.atleast.weight [16]
-  threshold.exactlyk_8_16bit.atmost.bias [1]
-  threshold.exactlyk_8_16bit.atmost.weight [16]
-
-  ---
-  MANIFEST
-
-  manifest.alu_operations [1]
-  manifest.flags [1]
-  manifest.instruction_width [1]
-  manifest.memory_bytes [1]
-  manifest.pc_width [1]
-  manifest.register_width [1]
-  manifest.registers [1]
-  manifest.turing_complete [1]
-  manifest.version [1]
-
-  Values change:
-  - register_width: 8 → 16
-  - pc_width: 8 → 16
-  - memory_bytes: 256 → 65536
-
-  ---
-  TOTAL NEW TENSOR COUNT
-
-  | Category                      | Count             |
-  |-------------------------------|-------------------|
-  | ripplecarry16bit              | 288               |
-  | 16-bit comparators            | 2                 |
-  | multiplier16x16               | ~6500             |
-  | combinational                 | 45                |
-  | control (jump + conditionals) | 1184              |
-  | error_detection               | ~200              |
-  | modular                       | ~600              |
-  | pattern_recognition           | 45                |
-  | threshold                     | 60                |
-  | manifest                      | 9                 |
-  | TOTAL                         | ~8900 new tensors |
-
-  Combined with existing 8-bit tensors retained for backwards compatibility or removed: final 16-bit model ~9000-17000 tensors depending on whether 8-bit components are kept.

todo.md

@@ -1,173 +1,173 @@
-# Threshold Logic Neural Turing Machine
-
-## Core Vision
-
-A self-contained, autonomous computational machine:
-- **Pure tensor computation**: State in, state out
-- **Frozen verified circuits**: Exhaustively tested, can't compute wrong
-- **ACT execution**: Internal loop until HALT
-- **No external orchestration**: One forward pass = complete program execution
-
-The machine runs. Callers just provide initial state and collect results.
-
-## Architecture
-
-```
-            ┌─────────────────────────────┐
-            │      Initial State          │
-            │  [PC|Regs|Flags|Memory...]  │
-            └─────────────┬───────────────┘
-                          ▼
-            ┌─────────────────────────────┐
-            │                             │
-            │   Threshold Circuit Layer   │
-            │                             │
-            │  ┌───────────────────────┐  │
-            │  │   Fetch: PC → Instr   │  │
-            │  ├───────────────────────┤  │
-            │  │   Decode: Opcode/Ops  │  │
-            │  ├───────────────────────┤  │
-            │  │   Execute: ALU/Mem    │  │
-            │  ├───────────────────────┤  │
-            │  │   Writeback: Results  │  │
-            │  ├───────────────────────┤  │
-            │  │   PC Update           │  │
-            │  └───────────┬───────────┘  │
-            │              │              │
-            │         ┌────▼────┐         │
-            │         │ HALTED? │         │
-            │         └────┬────┘         │
-            │              │              │
-            │         no ──┴── yes        │
-            │          │       │          │
-            │          ▼       ▼          │
-            │       [loop]   [exit]       │
-            │                             │
-            └─────────────┬───────────────┘
-                          ▼
-            ┌─────────────────────────────┐
-            │       Final State           │
-            │  [PC|Regs|Flags|Memory...]  │
-            └─────────────────────────────┘
-```
-
-## Memory Architecture
-
-### State Tensor Layout
-```
-┌────────┬──────────┬───────┬────────┬─────────────────────┐
-│ PC [8] │ Regs[32] │Flags[4│Ctrl[4] │ Memory [N × 8]      │
-└────────┴──────────┴───────┴────────┴─────────────────────┘
-    8    +   32     +   4   +   4    +   N × 8   bits
-```
-
-### Memory Hierarchy
-| Level | Size | Tensors | Access |
-|-------|------|---------|--------|
-| Registers | 4 × 8-bit | Direct wiring | Immediate |
-| Hot cache | 256 bytes | ~6,400 | 8-bit addressed |
-| Cold bank | 64KB | ~1.6M | 16-bit addressed |
-
-### Full 64KB Configuration
-- Address space: 0x0000 - 0xFFFF
-- Routing circuits: ~1.64M tensors
-- State tensor: 48 + 524,288 = 524,336 bits per instance
-
-## Phase 1: Memory Infrastructure
-
-| Component | Description | Tensors | Status |
-|-----------|-------------|---------|--------|
-| Address Decoder 8-bit | 8-bit → 256 one-hot | ~520 | Pending |
-| Address Decoder 16-bit | 16-bit → 65536 one-hot | ~65,600 | Pending |
-| Memory Read MUX 256 | 256-to-1 × 8 bits | ~2,048 | Pending |
-| Memory Read MUX 64K | 65536-to-1 × 8 bits | ~524,288 | Pending |
-| Memory Write Demux | Route write to address | ~524,288 | Pending |
-| Memory Cell Logic | Conditional update | ~524,288 | Pending |
-
-## Phase 2: Execution Engine
-
-| Component | Description | Status |
-|-----------|-------------|--------|
-| Instruction Fetch | PC → Memory → IR | Pending |
-| Operand Fetch | Decode → Register/Memory Read | Pending |
-| ALU Dispatch | Opcode → Operation Select | Pending |
-| Result Writeback | Route to destination | Pending |
-| Flag Update | Compute Z/N/C/V | Partial |
-| PC Advance | Increment or Jump | Done |
-| Halt Detection | HALT opcode → stop | Done |
-
-## Phase 3: ACT Integration
-
-| Component | Description | Status |
-|-----------|-------------|--------|
-| Cycle Block | All Phase 2 as single layer | Pending |
-| Recurrence Wrapper | Loop until halt signal | Pending |
-| Max Cycles Guard | Prevent infinite loops | Pending |
-| State I/O | Pack/unpack state tensor | Pending |
-
-## Instruction Set
-
-| Opcode | Mnemonic | Operation | Status |
-|--------|----------|-----------|--------|
-| 0x0 | ADD | R[d] = R[a] + R[b] | Done |
-| 0x1 | SUB | R[d] = R[a] - R[b] | Done |
-| 0x2 | AND | R[d] = R[a] & R[b] | Done |
-| 0x3 | OR | R[d] = R[a] \| R[b] | Done |
-| 0x4 | XOR | R[d] = R[a] ^ R[b] | Done |
-| 0x5 | SHL | R[d] = R[a] << 1 | Done |
-| 0x6 | SHR | R[d] = R[a] >> 1 | Done |
-| 0x7 | MUL | R[d] = R[a] * R[b] | Done |
-| 0x8 | DIV | R[d] = R[a] / R[b] | Done |
-| 0x9 | CMP | flags = R[a] - R[b] | Done |
-| 0xA | LOAD | R[d] = M[addr] | Pending |
-| 0xB | STORE | M[addr] = R[s] | Pending |
-| 0xC | JMP | PC = addr | Partial |
-| 0xD | JZ/JNZ | PC = addr if flag | Done |
-| 0xE | CALL | push PC; PC = addr | Partial |
-| 0xF | HALT | stop execution | Done |
-
-## Completed Circuits
-
-### Arithmetic (2,756 tensors)
-- ADD, SUB, MUL, DIV, NEG
-- ADC, SBC (with carry)
-- CMP (compare, sets flags)
-
-### Bit Operations (62 tensors)
-- ASR (arithmetic shift right)
-- ROL, ROR (rotate through carry)
-- SHL, SHR (from original)
-
-### Control (306 tensors)
-- NOP, HALT
-- PC Increment, PC Load MUX
-- Register MUX 4-to-1
-- Instruction Decoder 4-to-16
-
-### Original Model (~3,100 tensors)
-- Boolean gates (AND, OR, XOR, NOT, NAND, NOR)
-- Ripple carry adders (2/4/8-bit)
-- 8×8 multiplier
-- Comparators, threshold gates
-- Conditional jumps
-
-**Current: 6,184 tensors**
-**Projected: ~1.65M tensors (with 64KB memory)**
-
-## Applications
-
-The machine is general-purpose. Possible callers:
-
-1. **Direct invocation**: Load state, call forward(), read result
-2. **LLM coprocessor**: Embedded layer for exact computation
-3. **Neuromorphic deployment**: Map to spiking hardware
-4. **Verified computation**: Provably correct execution
-5. **Educational**: Transparent, inspectable CPU
-
-## Design Principles
-
-1. **Autonomy**: Machine runs without external logic
-2. **Purity**: forward(state) → state', no side effects
-3. **Verification**: Every circuit exhaustively tested
-4. **Transparency**: All weights inspectable, all operations traceable
-5. **Universality**: Turing complete, runs arbitrary programs
+# Threshold Logic Neural Turing Machine
+
+## Core Vision
+
+A self-contained, autonomous computational machine:
+- **Pure tensor computation**: State in, state out
+- **Frozen verified circuits**: Exhaustively tested, can't compute wrong
+- **ACT execution**: Internal loop until HALT
+- **No external orchestration**: One forward pass = complete program execution
+
+The machine runs. Callers just provide initial state and collect results.
+
+## Architecture
+
+```
+            ┌─────────────────────────────┐
+            │      Initial State          │
+            │  [PC|Regs|Flags|Memory...]  │
+            └─────────────┬───────────────┘
+                          ▼
+            ┌─────────────────────────────┐
+            │                             │
+            │   Threshold Circuit Layer   │
+            │                             │
+            │  ┌───────────────────────┐  │
+            │  │   Fetch: PC → Instr   │  │
+            │  ├───────────────────────┤  │
+            │  │   Decode: Opcode/Ops  │  │
+            │  ├───────────────────────┤  │
+            │  │   Execute: ALU/Mem    │  │
+            │  ├───────────────────────┤  │
+            │  │   Writeback: Results  │  │
+            │  ├───────────────────────┤  │
+            │  │   PC Update           │  │
+            │  └───────────┬───────────┘  │
+            │              │              │
+            │         ┌────▼────┐         │
+            │         │ HALTED? │         │
+            │         └────┬────┘         │
+            │              │              │
+            │         no ──┴── yes        │
+            │          │       │          │
+            │          ▼       ▼          │
+            │       [loop]   [exit]       │
+            │                             │
+            └─────────────┬───────────────┘
+                          ▼
+            ┌─────────────────────────────┐
+            │       Final State           │
+            │  [PC|Regs|Flags|Memory...]  │
+            └─────────────────────────────┘
+```
+
+## Memory Architecture
+
+### State Tensor Layout
+```
+┌────────┬──────────┬───────┬────────┬─────────────────────┐
+│ PC [8] │ Regs[32] │Flags[4│Ctrl[4] │ Memory [N × 8]      │
+└────────┴──────────┴───────┴────────┴─────────────────────┘
+    8    +   32     +   4   +   4    +   N × 8   bits
+```
+
+### Memory Hierarchy
+| Level | Size | Tensors | Access |
+|-------|------|---------|--------|
+| Registers | 4 × 8-bit | Direct wiring | Immediate |
+| Hot cache | 256 bytes | ~6,400 | 8-bit addressed |
+| Cold bank | 64KB | ~1.6M | 16-bit addressed |
+
+### Full 64KB Configuration
+- Address space: 0x0000 - 0xFFFF
+- Routing circuits: ~1.64M tensors
+- State tensor: 48 + 524,288 = 524,336 bits per instance
+
+## Phase 1: Memory Infrastructure
+
+| Component | Description | Tensors | Status |
+|-----------|-------------|---------|--------|
+| Address Decoder 8-bit | 8-bit → 256 one-hot | ~520 | Pending |
+| Address Decoder 16-bit | 16-bit → 65536 one-hot | ~65,600 | Pending |
+| Memory Read MUX 256 | 256-to-1 × 8 bits | ~2,048 | Pending |
+| Memory Read MUX 64K | 65536-to-1 × 8 bits | ~524,288 | Pending |
+| Memory Write Demux | Route write to address | ~524,288 | Pending |
+| Memory Cell Logic | Conditional update | ~524,288 | Pending |
+
+## Phase 2: Execution Engine
+
+| Component | Description | Status |
+|-----------|-------------|--------|
+| Instruction Fetch | PC → Memory → IR | Pending |
+| Operand Fetch | Decode → Register/Memory Read | Pending |
+| ALU Dispatch | Opcode → Operation Select | Pending |
+| Result Writeback | Route to destination | Pending |
+| Flag Update | Compute Z/N/C/V | Partial |
+| PC Advance | Increment or Jump | Done |
+| Halt Detection | HALT opcode → stop | Done |
+
+## Phase 3: ACT Integration
+
+| Component | Description | Status |
+|-----------|-------------|--------|
+| Cycle Block | All Phase 2 as single layer | Pending |
+| Recurrence Wrapper | Loop until halt signal | Pending |
+| Max Cycles Guard | Prevent infinite loops | Pending |
+| State I/O | Pack/unpack state tensor | Pending |
+
+## Instruction Set
+
+| Opcode | Mnemonic | Operation | Status |
+|--------|----------|-----------|--------|
+| 0x0 | ADD | R[d] = R[a] + R[b] | Done |
+| 0x1 | SUB | R[d] = R[a] - R[b] | Done |
+| 0x2 | AND | R[d] = R[a] & R[b] | Done |
+| 0x3 | OR | R[d] = R[a] \| R[b] | Done |
+| 0x4 | XOR | R[d] = R[a] ^ R[b] | Done |
+| 0x5 | SHL | R[d] = R[a] << 1 | Done |
+| 0x6 | SHR | R[d] = R[a] >> 1 | Done |
+| 0x7 | MUL | R[d] = R[a] * R[b] | Done |
+| 0x8 | DIV | R[d] = R[a] / R[b] | Done |
+| 0x9 | CMP | flags = R[a] - R[b] | Done |
+| 0xA | LOAD | R[d] = M[addr] | Pending |
+| 0xB | STORE | M[addr] = R[s] | Pending |
+| 0xC | JMP | PC = addr | Partial |
+| 0xD | JZ/JNZ | PC = addr if flag | Done |
+| 0xE | CALL | push PC; PC = addr | Partial |
+| 0xF | HALT | stop execution | Done |
+
+## Completed Circuits
+
+### Arithmetic (2,756 tensors)
+- ADD, SUB, MUL, DIV, NEG
+- ADC, SBC (with carry)
+- CMP (compare, sets flags)
+
+### Bit Operations (62 tensors)
+- ASR (arithmetic shift right)
+- ROL, ROR (rotate through carry)
+- SHL, SHR (from original)
+
+### Control (306 tensors)
+- NOP, HALT
+- PC Increment, PC Load MUX
+- Register MUX 4-to-1
+- Instruction Decoder 4-to-16
+
+### Original Model (~3,100 tensors)
+- Boolean gates (AND, OR, XOR, NOT, NAND, NOR)
+- Ripple carry adders (2/4/8-bit)
+- 8×8 multiplier
+- Comparators, threshold gates
+- Conditional jumps
+
+**Current: 6,184 tensors**
+**Projected: ~1.65M tensors (with 64KB memory)**
+
+## Applications
+
+The machine is general-purpose. Possible callers:
+
+1. **Direct invocation**: Load state, call forward(), read result
+2. **LLM coprocessor**: Embedded layer for exact computation
+3. **Neuromorphic deployment**: Map to spiking hardware
+4. **Verified computation**: Provably correct execution
+5. **Educational**: Transparent, inspectable CPU
+
+## Design Principles
+
+1. **Autonomy**: Machine runs without external logic
+2. **Purity**: forward(state) → state', no side effects
+3. **Verification**: Every circuit exhaustively tested
+4. **Transparency**: All weights inspectable, all operations traceable
+5. **Universality**: Turing complete, runs arbitrary programs