Add Instruction Decoder - 44 tensors, 16/16 tests pass

neural_computer.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:1d4d6d5a39d660390c5156d33b6ad3d5a2f49538a89ce0f2fcbb74e4c4ccb07a
-size 679380
+oid sha256:6c5e11ab199ce8548681595ff4a417a6634f62c2189749ef0d6a4cdb4a384a59
+size 683804

tensors.txt

@@ -1,5 +1,5 @@
 # Tensor Manifest
-# Total: 6140 tensors
+# Total: 6184 tensors
 
 alu.alu8bit.add.bias: shape=[1], values=[0.0]
 alu.alu8bit.add.weight: shape=[16], values=[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]
@@ -5021,6 +5021,50 @@ control.conditionaljump.bit7.not_sel.bias: shape=[1], values=[0.0]
 control.conditionaljump.bit7.not_sel.weight: shape=[1], values=[-1.0]
 control.conditionaljump.bit7.or.bias: shape=[1], values=[-1.0]
 control.conditionaljump.bit7.or.weight: shape=[2], values=[1.0, 1.0]
+control.decoder.decode0.bias: shape=[1], values=[-4.0]
+control.decoder.decode0.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode1.bias: shape=[1], values=[-4.0]
+control.decoder.decode1.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode10.bias: shape=[1], values=[-4.0]
+control.decoder.decode10.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode11.bias: shape=[1], values=[-4.0]
+control.decoder.decode11.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode12.bias: shape=[1], values=[-4.0]
+control.decoder.decode12.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode13.bias: shape=[1], values=[-4.0]
+control.decoder.decode13.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode14.bias: shape=[1], values=[-4.0]
+control.decoder.decode14.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode15.bias: shape=[1], values=[-4.0]
+control.decoder.decode15.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode2.bias: shape=[1], values=[-4.0]
+control.decoder.decode2.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode3.bias: shape=[1], values=[-4.0]
+control.decoder.decode3.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode4.bias: shape=[1], values=[-4.0]
+control.decoder.decode4.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode5.bias: shape=[1], values=[-4.0]
+control.decoder.decode5.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode6.bias: shape=[1], values=[-4.0]
+control.decoder.decode6.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode7.bias: shape=[1], values=[-4.0]
+control.decoder.decode7.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode8.bias: shape=[1], values=[-4.0]
+control.decoder.decode8.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.decode9.bias: shape=[1], values=[-4.0]
+control.decoder.decode9.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+control.decoder.is_alu.bias: shape=[1], values=[-1.0]
+control.decoder.is_alu.weight: shape=[16], values=[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0]
+control.decoder.is_control.bias: shape=[1], values=[-1.0]
+control.decoder.is_control.weight: shape=[16], values=[0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]
+control.decoder.not_op0.bias: shape=[1], values=[0.0]
+control.decoder.not_op0.weight: shape=[1], values=[-1.0]
+control.decoder.not_op1.bias: shape=[1], values=[0.0]
+control.decoder.not_op1.weight: shape=[1], values=[-1.0]
+control.decoder.not_op2.bias: shape=[1], values=[0.0]
+control.decoder.not_op2.weight: shape=[1], values=[-1.0]
+control.decoder.not_op3.bias: shape=[1], values=[0.0]
+control.decoder.not_op3.weight: shape=[1], values=[-1.0]
 control.halt.flag_c.bias: shape=[1], values=[-0.5]
 control.halt.flag_c.weight: shape=[1], values=[1.0]
 control.halt.flag_n.bias: shape=[1], values=[-0.5]

todo.md

@@ -15,7 +15,7 @@
 | Memory Data Register    | MDR latch                   | Missing                        |
 | Memory Read/Write       | R/W enable signals          | Missing                        |
 | Instruction Register    | IR latch                    | Missing                        |
-| Instruction Decoder     | Opcode → microops           | Missing                        |
+| Instruction Decoder     | 4-bit → 16 one-hot          | DONE - 44 tensors, 16/16 tests pass |
 | Sequencer FSM           | Fetch/Decode/Execute states | Missing                        |
 
 ## Extended Operations