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README.md

@@ -4,137 +4,341 @@ tags:
 - threshold-logic
 - neuromorphic
 - computer-architecture
+- formal-verification
 - coq
 - turing-complete
+- loihi
+- truenorth
+- akida
 ---
 
 # 8bit-threshold-computer
 
-A complete 8-bit computer implemented entirely in threshold logic neurons. All computation uses weighted sums with Heaviside step activation - no traditional logic gates.
+A complete **Turing-complete 8-bit computer** implemented entirely in threshold logic neurons. No traditional logic gates - every operation uses weighted sums with Heaviside step activation.
 
-## Architecture
+**Tested**: Rock-Paper-Scissors, FizzBuzz, countdown loops, and ALU operations all execute correctly using only threshold neuron computations.
+
+## System Architecture
 
 | Component | Specification |
 |-----------|---------------|
-| Registers | 4 × 8-bit (R0, R1, R2, R3) |
+| Registers | 4 x 8-bit (R0, R1, R2, R3) |
 | Memory | 256 bytes |
 | Program Counter | 8-bit |
 | Instruction Width | 16-bit |
 | ALU Operations | 16 |
-| Status Flags | Z, N, C, V |
-| Circuits | 93 verified |
-| Parameters | 2,377 |
+| Status Flags | Z (Zero), N (Negative), C (Carry), V (Overflow) |
+| **Total Circuits** | **93** |
+| **Total Tensors** | **1,193** |
+| **Total Parameters** | **2,386** |
+
+## Quick Start
+
+```python
+import torch
+from safetensors.torch import load_file
+
+weights = load_file("neural_computer.safetensors")
+
+def heaviside(x):
+    """Threshold activation: fires if x >= 0"""
+    return (x >= 0).int()
+
+def threshold_neuron(inputs, weight, bias):
+    """Single threshold neuron computation"""
+    weighted_sum = (inputs.float() * weight.float()).sum() + bias.float()
+    return heaviside(weighted_sum)
+
+# Example: AND gate
+and_w = weights['boolean.and.weight']  # [1.0, 1.0]
+and_b = weights['boolean.and.bias']    # [-2.0]
+
+for a in [0, 1]:
+    for b in [0, 1]:
+        result = threshold_neuron(torch.tensor([a, b]), and_w, and_b)
+        print(f"AND({a}, {b}) = {result.item()}")
+```
 
 ## Instruction Set
 
-### ALU Operations (opcode 0-12)
-| Op | Mnemonic | Operation |
-|----|----------|-----------|
-| 0 | ADD | dest = src1 + src2 |
-| 1 | SUB | dest = src1 - src2 |
-| 2 | AND | dest = src1 & src2 |
-| 3 | OR | dest = src1 \| src2 |
-| 4 | XOR | dest = src1 ^ src2 |
-| 5 | NOT | dest = ~src1 |
-| 6 | SHL | dest = src1 << 1 |
-| 7 | SHR | dest = src1 >> 1 |
-| 8 | INC | dest = src1 + 1 |
-| 9 | DEC | dest = src1 - 1 |
-| 10 | CMP | flags = src1 - src2 |
-| 11 | NEG | dest = -src1 |
-| 12 | MOV | dest = src1 |
-| 13 | LDI | dest = immediate |
-
-### Control Flow (opcode 14)
+### ALU Operations (Opcodes 0-15)
+
+| Op | Mnemonic | Operation | Opcode |
+|----|----------|-----------|--------|
+| 0 | ADD | dest = src1 + src2 | 0000 |
+| 1 | SUB | dest = src1 - src2 | 0001 |
+| 2 | AND | dest = src1 & src2 | 0010 |
+| 3 | OR | dest = src1 \| src2 | 0011 |
+| 4 | XOR | dest = src1 ^ src2 | 0100 |
+| 5 | NOT | dest = ~src1 | 0101 |
+| 6 | SHL | dest = src1 << 1 | 0110 |
+| 7 | SHR | dest = src1 >> 1 | 0111 |
+| 8 | INC | dest = src1 + 1 | 1000 |
+| 9 | DEC | dest = src1 - 1 | 1001 |
+| 10 | CMP | flags = src1 - src2 | 1010 |
+| 11 | NEG | dest = -src1 | 1011 |
+| 12 | PASS | dest = src1 | 1100 |
+| 13 | ZERO | dest = 0 | 1101 |
+| 14 | ONES | dest = 0xFF | 1110 |
+| 15 | NOP | no operation | 1111 |
+
+### Control Flow
+
 | Cond | Mnemonic | Condition |
 |------|----------|-----------|
 | 0 | JMP | unconditional |
-| 1 | JZ | Z = 1 |
-| 2 | JNZ | Z = 0 |
-| 3 | JC | C = 1 |
-| 4 | JNC | C = 0 |
-| 5 | JN | N = 1 |
-| 6 | JP | N = 0 |
-| 7 | JV | V = 1 |
-
-### Extended Operations (opcode 15)
-| Sub | Mnemonic | Operation |
-|-----|----------|-----------|
-| 0 | NOP | no operation |
-| 1 | LD | load from memory |
-| 2 | ST | store to memory |
-| 3 | PUSH | push to stack |
-| 4 | POP | pop from stack |
-| 5 | CALL | call subroutine |
-| 6 | RET | return |
-
-## Usage
+| 1 | JZ | Z = 1 (zero) |
+| 2 | JNZ | Z = 0 (not zero) |
+| 3 | JC | C = 1 (carry) |
+| 4 | JNC | C = 0 (no carry) |
+| 5 | JN | N = 1 (negative) |
+| 6 | JP | N = 0 (positive) |
+| 7 | JV | V = 1 (overflow) |
+
+### Stack & Memory
+
+| Mnemonic | Operation |
+|----------|-----------|
+| LD | Load from memory |
+| ST | Store to memory |
+| PUSH | Push to stack |
+| POP | Pop from stack |
+| CALL | Call subroutine |
+| RET | Return from subroutine |
+
+## Complete Circuit Inventory
+
+### ALU (3 circuits, 305 params)
+
+| Circuit | Tensors | Parameters | Description |
+|---------|---------|------------|-------------|
+| alu8bit | 17 | 201 | Complete 8-bit ALU with 16 operations |
+| alucontrol | 32 | 80 | 4-bit opcode decoder |
+| aluflags | 8 | 24 | Z, N, C, V flag computation |
+
+### Boolean (9 circuits, 44 params)
+
+| Circuit | Tensors | Parameters | Weights | Bias |
+|---------|---------|------------|---------|------|
+| and | 2 | 3 | [1, 1] | -2 |
+| or | 2 | 3 | [1, 1] | -1 |
+| not | 2 | 2 | [-1] | 0 |
+| nand | 2 | 3 | [-1, -1] | 1 |
+| nor | 2 | 3 | [-1, -1] | 0 |
+| xor | 6 | 9 | 2-layer network |
+| xnor | 6 | 9 | 2-layer network |
+| implies | 2 | 3 | [-1, 1] | 0 |
+| biimplies | 6 | 9 | 2-layer network |
+
+### Arithmetic (16 circuits, 612 params)
+
+| Circuit | Tensors | Parameters | Description |
+|---------|---------|------------|-------------|
+| halfadder | 8 | 12 | 1-bit half adder |
+| fulladder | 18 | 27 | 1-bit full adder |
+| ripplecarry2bit | 36 | 54 | 2-bit ripple carry adder |
+| ripplecarry4bit | 72 | 108 | 4-bit ripple carry adder |
+| ripplecarry8bit | 144 | 216 | 8-bit ripple carry adder |
+| incrementer8bit | 2 | 16 | 8-bit increment |
+| decrementer8bit | 2 | 16 | 8-bit decrement |
+| equality8bit | 50 | 81 | 8-bit equality comparison |
+| greaterthan8bit | 1 | 8 | 8-bit greater than |
+| greaterorequal8bit | 1 | 8 | 8-bit greater or equal |
+| lessthan8bit | 1 | 8 | 8-bit less than |
+| lessorequal8bit | 1 | 8 | 8-bit less or equal |
+| absolutedifference8bit | 1 | 16 | 8-bit absolute difference |
+| max8bit | 1 | 16 | 8-bit maximum |
+| min8bit | 1 | 16 | 8-bit minimum |
+| multiplier2x2 | 8 | 12 | 2x2 bit multiplier |
+
+### Combinational (10 circuits, 119 params)
+
+| Circuit | Tensors | Parameters | Description |
+|---------|---------|------------|-------------|
+| multiplexer2to1 | 8 | 11 | 2:1 MUX |
+| multiplexer4to1 | 1 | 6 | 4:1 MUX |
+| multiplexer8to1 | 1 | 11 | 8:1 MUX |
+| demultiplexer1to2 | 4 | 6 | 1:2 DEMUX |
+| demultiplexer1to4 | 1 | 3 | 1:4 DEMUX |
+| demultiplexer1to8 | 1 | 4 | 1:8 DEMUX |
+| encoder8to3 | 6 | 27 | 8:3 priority encoder |
+| decoder3to8 | 16 | 32 | 3:8 decoder |
+| priorityencoder8bit | 1 | 8 | 8-bit priority encoder |
+| barrelshifter8bit | 1 | 11 | 8-bit barrel shifter |
+
+### Control (16 circuits, 806 params)
+
+| Circuit | Tensors | Parameters | Description |
+|---------|---------|------------|-------------|
+| jump | 16 | 16 | Unconditional jump |
+| jz | 64 | 88 | Jump if zero |
+| jnz | 64 | 88 | Jump if not zero |
+| jc | 64 | 88 | Jump if carry |
+| jnc | 64 | 88 | Jump if no carry |
+| jn | 64 | 88 | Jump if negative |
+| jp | 64 | 88 | Jump if positive |
+| jv | 64 | 88 | Jump if overflow |
+| jnv | 64 | 88 | Jump if no overflow |
+| conditionaljump | 64 | 88 | Generic conditional |
+| push | 2 | 2 | Push to stack |
+| pop | 2 | 2 | Pop from stack |
+| call | 2 | 2 | Call subroutine |
+| ret | 2 | 2 | Return |
+| sp_inc | 1 | 1 | Increment stack pointer |
+| sp_dec | 1 | 1 | Decrement stack pointer |
+
+### Error Detection (11 circuits, 116 params)
+
+| Circuit | Tensors | Parameters | Description |
+|---------|---------|------------|-------------|
+| paritychecker8bit | 2 | 9 | 8-bit parity checker |
+| paritygenerator8bit | 2 | 9 | 8-bit parity generator |
+| evenparitychecker | 2 | 9 | Even parity |
+| oddparitychecker | 4 | 11 | Odd parity |
+| checksum8bit | 2 | 9 | 8-bit checksum |
+| crc4 | 1 | 5 | CRC-4 |
+| crc8 | 1 | 9 | CRC-8 |
+| hammingencode4bit | 6 | 12 | Hamming(7,4) encoder |
+| hammingdecode7bit | 6 | 15 | Hamming(7,4) decoder |
+| hammingsyndrome | 3 | 12 | Hamming syndrome |
+| longitudinalparity | 2 | 16 | Longitudinal parity |
+
+### Modular Arithmetic (11 circuits, 99 params)
+
+| Circuit | Tensors | Parameters | Weights |
+|---------|---------|------------|---------|
+| mod2 | 2 | 9 | [1, -1, 1, -1, 1, -1, 1, -1] |
+| mod3 | 2 | 9 | [1, 1, -2, 1, 1, -2, 1, 1] |
+| mod4 | 2 | 9 | [1, 1, 1, -3, 1, 1, 1, -3] |
+| mod5 | 2 | 9 | [1, 1, 1, 1, -4, 1, 1, 1] |
+| mod6 | 2 | 9 | [1, 1, 1, 1, 1, -5, 1, 1] |
+| mod7 | 2 | 9 | [1, 1, 1, 1, 1, 1, -6, 1] |
+| mod8 | 2 | 9 | [1, 1, 1, 1, 1, 1, 1, -7] |
+| mod9 | 2 | 9 | [1, 1, 1, 1, 1, 1, 1, 1] |
+| mod10 | 2 | 9 | [1, 1, 1, 1, 1, 1, 1, 1] |
+| mod11 | 2 | 9 | [1, 1, 1, 1, 1, 1, 1, 1] |
+| mod12 | 2 | 9 | [1, 1, 1, 1, 1, 1, 1, 1] |
+
+### Pattern Recognition (10 circuits, 125 params)
+
+| Circuit | Tensors | Parameters | Description |
+|---------|---------|------------|-------------|
+| popcount | 2 | 9 | Population count (Hamming weight) |
+| allones | 2 | 9 | Detect all 1s |
+| allzeros | 2 | 9 | Detect all 0s |
+| alternating8bit | 2 | 16 | Detect alternating pattern |
+| hammingdistance8bit | 2 | 24 | Hamming distance |
+| leadingones | 1 | 8 | Count leading ones |
+| trailingones | 1 | 8 | Count trailing ones |
+| symmetry8bit | 6 | 13 | Detect palindrome pattern |
+| runlength | 1 | 8 | Run length encoding |
+| onehotdetector | 6 | 21 | Detect one-hot encoding |
+
+### Threshold (13 circuits, 117 params)
+
+| Circuit | Tensors | Parameters | Weights | Bias | Fires when |
+|---------|---------|------------|---------|------|------------|
+| oneoutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -1 | >= 1 of 8 |
+| twooutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -2 | >= 2 of 8 |
+| threeoutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -3 | >= 3 of 8 |
+| fouroutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -4 | >= 4 of 8 |
+| fiveoutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -5 | >= 5 of 8 |
+| sixoutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -6 | >= 6 of 8 |
+| sevenoutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -7 | >= 7 of 8 |
+| alloutof8 | 2 | 9 | [1,1,1,1,1,1,1,1] | -8 | = 8 of 8 |
+| majority | 2 | 9 | [1,1,1,1,1,1,1,1] | -5 | > 50% |
+| minority | 2 | 9 | [-1,-1,-1,-1,-1,-1,-1,-1] | 3 | <= 37.5% |
+| atleastk_4 | 2 | 9 | [1,1,1,1,1,1,1,1] | -4 | >= k |
+| atmostk_4 | 2 | 9 | [-1,-1,-1,-1,-1,-1,-1,-1] | 4 | <= k |
+| exactlyk_4 | 6 | 21 | 2-layer network | | = k |
+
+## Example Programs
+
+### FizzBuzz
 
 ```python
-from safetensors.torch import load_file
+mod3_w = weights['modular.mod3.weight']  # [1, 1, -2, 1, 1, -2, 1, 1]
+mod5_w = weights['modular.mod5.weight']  # [1, 1, 1, 1, -4, 1, 1, 1]
 
-weights = load_file("neural_computer.safetensors")
+for n in range(1, 16):
+    bits = int_to_bits(n)
+    div3 = (weighted_sum(bits, mod3_w, 0) % 3) == 0
+    div5 = (weighted_sum(bits, mod5_w, 0) % 5) == 0
 
-# All operations use threshold neurons:
-#   output = 1 if sum(weight * input) + bias >= 0 else 0
+    if div3 and div5: print("FizzBuzz")
+    elif div3: print("Fizz")
+    elif div5: print("Buzz")
+    else: print(n)
 ```
 
-## Example Programs
+### Rock-Paper-Scissors
 
-**Sum 1 to 10:**
-```asm
-LDI R0, 0      ; sum = 0
-LDI R1, 10     ; counter = 10
-ADD R0, R0, R1 ; sum += counter
-DEC R1, R1     ; counter--
-JNZ 4          ; loop if counter > 0
-; Result: R0 = 55
+```python
+def play_round(player, computer):
+    xor_result = alu_xor(player, computer)
+    if bits_to_int(xor_result) == 0:
+        return "Draw"
+    diff = alu_sub(player, computer)
+    return "Player wins" if (diff + 3) % 3 == 1 else "Computer wins"
 ```
 
-**Fibonacci:**
-```asm
-LDI R0, 1      ; fib(n-2)
-LDI R1, 1      ; fib(n-1)
-LDI R2, 6      ; iterations
-ADD R3, R0, R1 ; fib(n) = fib(n-2) + fib(n-1)
-MOV R0, R1
-MOV R1, R3
-DEC R2, R2
-JNZ 6
-; Result: R1 = 21 (fib(8))
+### Sum 1 to N
+
+```assembly
+    LDI R0, 0      ; sum = 0
+    LDI R1, 10     ; n = 10
+loop:
+    ADD R0, R0, R1 ; sum += n
+    DEC R1, R1     ; n--
+    JNZ loop       ; if n != 0, continue
+    ; Result: R0 = 55
 ```
 
-## Verification
+### Fibonacci
 
-Circuit weights derived from Coq proofs. Each circuit proven correct using:
-1. **Exhaustive verification** - all inputs tested
-2. **Universal quantification** - symbolic proofs
-3. **Algebraic characterization** - weight pattern correctness
+```assembly
+    LDI R0, 1      ; fib(n-2) = 1
+    LDI R1, 1      ; fib(n-1) = 1
+    LDI R2, 6      ; iterations
+loop:
+    ADD R3, R0, R1 ; fib(n) = fib(n-2) + fib(n-1)
+    MOV R0, R1
+    MOV R1, R3
+    DEC R2, R2
+    JNZ loop
+    ; Result: R1 = 21 (fib(8))
+```
 
-Note: The extraction from Coq to weights is not itself formally verified. The proofs establish correctness of the circuit specifications; the weights are a faithful transcription.
+## Hardware Compatibility
 
-## Circuit Categories
+All weights are integers. All activations are Heaviside step function. Designed for direct deployment on:
 
-| Category | Count | Examples |
-|----------|-------|----------|
-| Boolean | 9 | AND, OR, XOR, NAND, NOR |
-| Modular | 11 | MOD-2 through MOD-12 |
-| Threshold | 13 | Majority, k-out-of-n |
-| Arithmetic | 17 | Adders, comparators |
-| Error | 11 | Parity, Hamming, CRC |
-| Pattern | 10 | PopCount, symmetry |
-| Combinational | 10 | Mux, encoder, decoder |
-| ALU | 3 | Flags, control, ALU8Bit |
-| Control | 9 | Jump, conditional, stack |
+- **Intel Loihi** - Neuromorphic research chip
+- **IBM TrueNorth** - 1M neuron chip
+- **BrainChip Akida** - Edge neuromorphic processor
 
-## Hardware Compatibility
+## Verification
 
-Designed for neuromorphic processors:
-- Intel Loihi
-- IBM TrueNorth
-- BrainChip Akida
+Circuit weights derived from axiom-free Coq proofs:
 
-All weights are integers. All activations are Heaviside step.
+1. **Exhaustive verification** - All inputs tested
+2. **Universal quantification** - Symbolic proofs over all boolean combinations
+3. **Algebraic characterization** - Weight patterns proven correct
+
+Full Coq proofs: [github.com/CharlesCNorton/coq-circuits](https://github.com/CharlesCNorton/coq-circuits)
+
+## Tensor Naming Convention
+
+```
+{category}.{circuit}.{layer}.{component}.{weight|bias}
+
+Examples:
+  boolean.and.weight
+  boolean.xor.layer1.or.weight
+  alu.alu8bit.xor.layer2.bias
+  control.jz.mux.bit0.weight
+  arithmetic.ripplecarry8bit.fa7.sum.layer1.or.weight
+```
 
 ## Citation
 
@@ -143,7 +347,8 @@ All weights are integers. All activations are Heaviside step.
   title={8bit-threshold-computer: Turing-Complete Threshold Logic Computer},
   author={Norton, Charles},
   url={https://huggingface.co/phanerozoic/8bit-threshold-computer},
-  year={2025}
+  year={2025},
+  note={93 verified circuits, 2386 parameters}
 }
 ```
 
@@ -151,3 +356,4 @@ All weights are integers. All activations are Heaviside step.
 
 - [GitHub Repository](https://github.com/CharlesCNorton/coq-circuits)
 - [Coq Proofs](https://github.com/CharlesCNorton/coq-circuits/tree/main/coq)
+- [Individual Circuit Models](https://huggingface.co/phanerozoic)