Update roadmap: self-contained tensor CPU architecture

todo.md

@@ -1,42 +1,101 @@
-# Missing CPU Components
-
-## Core CPU Components
-
-| Component               | Description                 | Status                         |
-|-------------------------|-----------------------------|--------------------------------|
-| SUB                     | Subtraction circuit         | DONE - 162 tensors, 65536/65536 tests pass |
-| DIV                     | Division circuit            | DONE - 1984 tensors, 65280/65280 tests pass |
-| NEG                     | Two's complement negate     | DONE - 76 tensors, 256/256 tests pass |
-| Program Counter         | PC incrementer              | DONE - 62 tensors, 256/256 tests pass |
-| PC Load                 | 2-to-1 MUX for PC/jump      | DONE - 50 tensors, 1536/1536 tests pass |
-| Register File MUX       | Select 1-of-4 GPRs          | DONE - 84 tensors, 1036/1036 tests pass |
-| Register Write Enable   | Write back to register      | Missing                        |
-| Memory Address Register | MAR latch                   | Missing                        |
-| Memory Data Register    | MDR latch                   | Missing                        |
-| Memory Read/Write       | R/W enable signals          | Missing                        |
-| Instruction Register    | IR latch                    | Missing                        |
-| Instruction Decoder     | 4-bit → 16 one-hot          | DONE - 44 tensors, 16/16 tests pass |
-| Sequencer FSM           | Fetch/Decode/Execute states | Missing                        |
-
-## Extended Operations
-
-| Component | Description                          | Status                                              |
-|-----------|--------------------------------------|-----------------------------------------------------|
-| ROL       | Rotate left through carry            | DONE - 18 tensors, 512/512 tests pass               |
-| ROR       | Rotate right through carry           | DONE - 18 tensors, 512/512 tests pass               |
-| ASR       | Arithmetic shift right (sign-extend) | DONE - 26 tensors, 256/256 tests pass               |
-| ADC       | Add with carry input                 | DONE - 144 tensors, 131072/131072 tests pass        |
-| SBC       | Subtract with borrow                 | DONE - 160 tensors, 131072/131072 tests pass        |
-| CMP       | Compare (SUB without writeback)      | DONE - 168 tensors, 65536/65536 tests pass          |
-
-## System
-
-| Component              | Description      | Status  |
-|------------------------|------------------|---------|
-| Interrupt Controller   | IRQ/NMI handling | Missing |
-| Interrupt Vector Table | Jump addresses   | Missing |
-| Interrupt Enable Flag  | Global IE bit    | Missing |
-| I/O Ports              | IN/OUT data path | Missing |
-| HALT                   | Stop execution   | DONE - 42 tensors, 24576/24576 tests pass |
-| NOP                    | No operation     | DONE - 24 tensors, 4096/4096 tests pass |
-| Watchdog Timer         | Reset on timeout | Missing |
+# Self-Contained Tensor CPU Roadmap
+
+## Vision
+A fully self-contained CPU where:
+- All computation is threshold circuits (frozen weights)
+- Memory is a tensor partition (data flows through)
+- Stepper logic is encoded as circuits (no external orchestration)
+- One forward pass = one clock tick
+
+## Architecture
+
+```
+Input State Tensor:
+┌────────┬───────────┬───────┬─────────────────┐
+│ PC [8] │ Regs [32] │ Flags │ Memory [N×8]    │
+└────────┴───────────┴───────┴─────────────────┘
+                    ↓
+           Threshold Circuits
+         (fetch/decode/execute)
+                    ↓
+Output State Tensor:
+┌─────────┬───────────┬────────┬─────────────────┐
+│ PC' [8] │ Regs' [32]│ Flags' │ Memory' [N×8]   │
+└─────────┴───────────┴────────┴─────────────────┘
+```
+
+## Phase 1: Memory Infrastructure
+
+| Component | Description | Status |
+|-----------|-------------|--------|
+| Memory Address Decoder | 8-bit address → 256 one-hot select | Pending |
+| Memory Read MUX | 256-to-1 mux, select byte by address | Pending |
+| Memory Write Demux | Route write data to addressed location | Pending |
+| Memory Cell Logic | Conditional update: new or keep old | Pending |
+
+## Phase 2: Instruction Fetch
+
+| Component | Description | Status |
+|-----------|-------------|--------|
+| PC → Memory Read | Fetch instruction at PC address | Pending |
+| Instruction Split | Separate opcode from operands | Pending |
+| Operand Decode | Extract src/dst register indices | Pending |
+
+## Phase 3: Execute Cycle
+
+| Component | Description | Status |
+|-----------|-------------|--------|
+| Register Read MUX | Select source register(s) | Done (regmux4to1) |
+| ALU Dispatch | Route to correct operation circuit | Pending |
+| Result MUX | Select ALU output | Pending |
+| Writeback Logic | Route result to register or memory | Pending |
+| PC Update | Increment or load jump target | Done (pc_inc, pc_load) |
+
+## Phase 4: Full Integration
+
+| Component | Description | Status |
+|-----------|-------------|--------|
+| State Packer | Combine all outputs into state tensor | Pending |
+| State Unpacker | Split input state into components | Pending |
+| Single-Pass Execute | One forward pass = one instruction | Pending |
+
+## Completed Building Blocks
+
+These circuits are ready to use:
+
+### Arithmetic
+- NEG (76 tensors)
+- SUB (162 tensors)
+- ADC (144 tensors)
+- SBC (160 tensors)
+- DIV (1984 tensors)
+- ADD, MUL (from original model)
+
+### Comparison & Logic
+- CMP (168 tensors)
+- ASR, ROL, ROR (62 tensors total)
+- All boolean gates (from original model)
+
+### Control
+- NOP (24 tensors)
+- HALT (42 tensors)
+- PC Incrementer (62 tensors)
+- PC Load MUX (50 tensors)
+- Instruction Decoder (44 tensors)
+- Register File MUX (84 tensors)
+- Conditional jumps (from original model)
+
+## Memory Size Options
+
+| Size | Bytes | Bit-Tensors | Use Case |
+|------|-------|-------------|----------|
+| Tiny | 256 | ~2K | Proof of concept |
+| Small | 4KB | ~32K | Simple programs |
+| Medium | 64KB | ~512K | Full 8-bit address space |
+
+## Notes
+
+- Memory is DATA flowing through, not stored in weights
+- Weights remain frozen - only input/output tensors change
+- "Stepper" = calling forward() repeatedly
+- No Python logic in the loop - just tensor→forward→tensor