Add INC, DEC, NEG, ROL, ROR, stack ops, barrel shifter, priority encoder

New circuits:
- INC/DEC: half adder chain with carry/borrow (72 gates)
- NEG: NOT + INC (40 gates)
- ROL/ROR: rotate with carry wraparound (16 gates)
- PUSH/POP/RET: SP increment/decrement + address buffers (144 gates)
- Barrel shifter: 3-stage log shifter (96 gates)
- Priority encoder: find highest set bit (28 gates)

Tensors: 10,399 -> 11,581
Parameters: 8,288,256 -> 8,290,134
Fitness: 1.000000

README.md

@@ -17,8 +17,8 @@ tags:
 Every logic gate is a threshold neuron: `output = 1 if (Σ wᵢxᵢ + b) ≥ 0 else 0`
 
 ```
-Tensors:    10,399
-Parameters: 8,288,256
+Tensors:    11,581
+Parameters: 8,290,134
 ```
 
 ---
@@ -477,7 +477,7 @@ The interface generalizes to **all** 65,536 8-bit additions once trained—no me
 
 | File | Description |
 |------|-------------|
-| `neural_computer.safetensors` | 10,399 tensors, 8,288,256 parameters |
+| `neural_computer.safetensors` | 11,581 tensors, 8,290,134 parameters |
 | `threshold_cpu.py` | CPU state, reference cycle, threshold runtime |
 | `eval.py` | Unified evaluation suite (5,884 tests, GPU-batched) |
 | `build.py` | Build tools for memory, ALU, and .inputs tensors |

build.py

@@ -301,6 +301,170 @@ def add_div(tensors: Dict[str, torch.Tensor]) -> None:
             add_gate(tensors, f"alu.alu8bit.div.stage{stage}.mux.bit{bit}.or", [1.0, 1.0], [-1.0])
 
 
+def add_inc_dec(tensors: Dict[str, torch.Tensor]) -> None:
+    """Add INC and DEC circuits.
+
+    INC: A + 1 using half adders with carry chain
+    DEC: A - 1 using borrow chain (A + 255, two's complement of 1)
+
+    For INC, we add 1 to the LSB and propagate carry.
+    For DEC, we add 0xFF (two's complement of 1) or use borrow logic.
+    """
+    # INC: half adder chain starting with carry_in = 1
+    # bit 7 (LSB): XOR with 1, carry = bit[7]
+    # bit 6: XOR with carry, new_carry = bit[6] AND old_carry
+    # ...
+    for bit in range(8):
+        # XOR for sum (two-layer)
+        add_gate(tensors, f"alu.alu8bit.inc.bit{bit}.xor.layer1.or", [1.0, 1.0], [-1.0])
+        add_gate(tensors, f"alu.alu8bit.inc.bit{bit}.xor.layer1.nand", [-1.0, -1.0], [1.0])
+        add_gate(tensors, f"alu.alu8bit.inc.bit{bit}.xor.layer2", [1.0, 1.0], [-2.0])
+        # AND for carry propagation
+        add_gate(tensors, f"alu.alu8bit.inc.bit{bit}.carry", [1.0, 1.0], [-2.0])
+
+    # DEC: similar but with borrow logic
+    # Equivalent to adding 0xFF with carry_in = 0
+    # Or: NOT each bit, propagate borrow
+    for bit in range(8):
+        # XOR for difference
+        add_gate(tensors, f"alu.alu8bit.dec.bit{bit}.xor.layer1.or", [1.0, 1.0], [-1.0])
+        add_gate(tensors, f"alu.alu8bit.dec.bit{bit}.xor.layer1.nand", [-1.0, -1.0], [1.0])
+        add_gate(tensors, f"alu.alu8bit.dec.bit{bit}.xor.layer2", [1.0, 1.0], [-2.0])
+        # Borrow: NOT(A) AND borrow_in, equivalent to (NOT A) when borrow_in=1
+        add_gate(tensors, f"alu.alu8bit.dec.bit{bit}.not_a", [-1.0], [0.0])
+        add_gate(tensors, f"alu.alu8bit.dec.bit{bit}.borrow", [1.0, 1.0], [-2.0])
+
+
+def add_neg(tensors: Dict[str, torch.Tensor]) -> None:
+    """Add NEG circuit (two's complement negation).
+
+    NEG(A) = NOT(A) + 1 = ~A + 1
+
+    Structure: NOT gates followed by INC-style adder.
+    """
+    for bit in range(8):
+        # NOT gate for each bit
+        add_gate(tensors, f"alu.alu8bit.neg.not.bit{bit}", [-1.0], [0.0])
+        # Then add 1 using half adder chain
+        add_gate(tensors, f"alu.alu8bit.neg.inc.bit{bit}.xor.layer1.or", [1.0, 1.0], [-1.0])
+        add_gate(tensors, f"alu.alu8bit.neg.inc.bit{bit}.xor.layer1.nand", [-1.0, -1.0], [1.0])
+        add_gate(tensors, f"alu.alu8bit.neg.inc.bit{bit}.xor.layer2", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"alu.alu8bit.neg.inc.bit{bit}.carry", [1.0, 1.0], [-2.0])
+
+
+def add_rol_ror(tensors: Dict[str, torch.Tensor]) -> None:
+    """Add ROL and ROR circuits (rotate left/right).
+
+    ROL: out[i] = in[i+1] for i<7, out[7] = in[0] (MSB wraps to LSB)
+    ROR: out[0] = in[7], out[i] = in[i-1] for i>0 (LSB wraps to MSB)
+
+    Identity gates with circular wiring.
+    """
+    # ROL: rotate left (toward MSB)
+    for bit in range(8):
+        src = (bit + 1) % 8  # Circular: bit 7 gets bit 0
+        add_gate(tensors, f"alu.alu8bit.rol.bit{bit}", [2.0], [-1.0])
+
+    # ROR: rotate right (toward LSB)
+    for bit in range(8):
+        src = (bit - 1) % 8  # Circular: bit 0 gets bit 7
+        add_gate(tensors, f"alu.alu8bit.ror.bit{bit}", [2.0], [-1.0])
+
+
+def add_stack_ops(tensors: Dict[str, torch.Tensor]) -> None:
+    """Add RET, PUSH, POP circuit components.
+
+    These are higher-level operations that use memory read/write.
+    We create the control logic gates.
+
+    RET: Pop return address from stack, jump to it
+    PUSH: Decrement SP, write value to [SP]
+    POP: Read value from [SP], increment SP
+    """
+    # SP decrement for PUSH (16-bit)
+    for bit in range(16):
+        add_gate(tensors, f"control.push.sp_dec.bit{bit}.xor.layer1.or", [1.0, 1.0], [-1.0])
+        add_gate(tensors, f"control.push.sp_dec.bit{bit}.xor.layer1.nand", [-1.0, -1.0], [1.0])
+        add_gate(tensors, f"control.push.sp_dec.bit{bit}.xor.layer2", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"control.push.sp_dec.bit{bit}.borrow", [1.0, 1.0], [-2.0])
+
+    # SP increment for POP (16-bit)
+    for bit in range(16):
+        add_gate(tensors, f"control.pop.sp_inc.bit{bit}.xor.layer1.or", [1.0, 1.0], [-1.0])
+        add_gate(tensors, f"control.pop.sp_inc.bit{bit}.xor.layer1.nand", [-1.0, -1.0], [1.0])
+        add_gate(tensors, f"control.pop.sp_inc.bit{bit}.xor.layer2", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"control.pop.sp_inc.bit{bit}.carry", [1.0, 1.0], [-2.0])
+
+    # RET uses POP twice (for 16-bit address) then jumps
+    # Buffer gates for return address
+    for bit in range(16):
+        add_gate(tensors, f"control.ret.addr.bit{bit}", [2.0], [-1.0])
+
+
+def add_barrel_shifter(tensors: Dict[str, torch.Tensor]) -> None:
+    """Add barrel shifter circuit.
+
+    Shifts input by 0-7 positions based on 3-bit shift amount.
+    Uses layers of 2:1 muxes controlled by shift amount bits.
+
+    Layer 0: shift by 0 or 1 (controlled by shift[2], LSB)
+    Layer 1: shift by 0 or 2 (controlled by shift[1])
+    Layer 2: shift by 0 or 4 (controlled by shift[0], MSB)
+    """
+    # 3 layers of muxes, 8 bits each
+    for layer in range(3):
+        shift_amount = 1 << (2 - layer)  # 4, 2, 1 for layers 0, 1, 2
+        for bit in range(8):
+            # 2:1 mux: if sel then shifted else original
+            # NOT for inverting select
+            add_gate(tensors, f"combinational.barrelshifter.layer{layer}.bit{bit}.not_sel", [-1.0], [0.0])
+            # AND gates
+            add_gate(tensors, f"combinational.barrelshifter.layer{layer}.bit{bit}.and_a", [1.0, 1.0], [-2.0])
+            add_gate(tensors, f"combinational.barrelshifter.layer{layer}.bit{bit}.and_b", [1.0, 1.0], [-2.0])
+            # OR gate
+            add_gate(tensors, f"combinational.barrelshifter.layer{layer}.bit{bit}.or", [1.0, 1.0], [-1.0])
+
+
+def add_priority_encoder(tensors: Dict[str, torch.Tensor]) -> None:
+    """Add priority encoder circuit.
+
+    Finds the position of the highest set bit (0-7).
+    Output is 3-bit index + valid flag.
+
+    Uses cascaded comparisons: check bit 7 first, then 6, etc.
+    """
+    # Check each bit position (8 OR gates to detect any bit set at or above position)
+    for pos in range(8):
+        # OR of bits pos through 7
+        num_inputs = 8 - pos
+        weights = [1.0] * num_inputs
+        add_gate(tensors, f"combinational.priorityencoder.any_ge{pos}",
+                weights, [-1.0])
+
+    # Priority logic: pos N is highest if bit N is set AND no higher bit is set
+    for pos in range(8):
+        # bit[pos] AND NOT(any bit > pos)
+        add_gate(tensors, f"combinational.priorityencoder.is_highest{pos}.not_higher", [-1.0], [0.0])
+        add_gate(tensors, f"combinational.priorityencoder.is_highest{pos}.and", [1.0, 1.0], [-2.0])
+
+    # Encode position to 3-bit output
+    # out[0] (LSB): positions 1,3,5,7
+    # out[1]: positions 2,3,6,7
+    # out[2] (MSB): positions 4,5,6,7
+    for out_bit in range(3):
+        weights = []
+        for pos in range(8):
+            if (pos >> out_bit) & 1:
+                weights.append(1.0)
+        if weights:
+            add_gate(tensors, f"combinational.priorityencoder.out{out_bit}",
+                    weights, [-1.0])
+
+    # Valid flag: any bit set
+    add_gate(tensors, f"combinational.priorityencoder.valid",
+            [1.0] * 8, [-1.0])
+
+
 def add_comparators(tensors: Dict[str, torch.Tensor]) -> None:
     """Add 8-bit comparator circuits (GT, LT, GE, LE, EQ).
 
@@ -647,6 +811,79 @@ def infer_alu_inputs(gate: str, reg: SignalRegistry) -> List[int]:
                 if '.or' in gate:
                     return [reg.register(f"{prefix}.mux.bit{bit}.and_a"), reg.register(f"{prefix}.mux.bit{bit}.and_b")]
         return [reg.get_id(f"$a[{i}]") for i in range(8)] + [reg.get_id(f"$b[{i}]") for i in range(8)]
+    if '.inc.bit' in gate:
+        m = re.search(r'bit(\d+)', gate)
+        if m:
+            bit = int(m.group(1))
+            prefix = f"alu.alu8bit.inc.bit{bit}"
+            if 'layer1' in gate:
+                if bit == 7:
+                    return [reg.get_id(f"$a[{bit}]"), reg.get_id("#1")]
+                else:
+                    return [reg.get_id(f"$a[{bit}]"), reg.register(f"alu.alu8bit.inc.bit{bit+1}.carry")]
+            if 'layer2' in gate:
+                return [reg.register(f"{prefix}.xor.layer1.or"), reg.register(f"{prefix}.xor.layer1.nand")]
+            if '.carry' in gate:
+                if bit == 7:
+                    return [reg.get_id(f"$a[{bit}]"), reg.get_id("#1")]
+                else:
+                    return [reg.get_id(f"$a[{bit}]"), reg.register(f"alu.alu8bit.inc.bit{bit+1}.carry")]
+        return [reg.get_id(f"$a[{i}]") for i in range(8)]
+    if '.dec.bit' in gate:
+        m = re.search(r'bit(\d+)', gate)
+        if m:
+            bit = int(m.group(1))
+            prefix = f"alu.alu8bit.dec.bit{bit}"
+            if '.not_a' in gate:
+                return [reg.get_id(f"$a[{bit}]")]
+            if 'layer1' in gate:
+                if bit == 7:
+                    return [reg.get_id(f"$a[{bit}]"), reg.get_id("#1")]
+                else:
+                    return [reg.get_id(f"$a[{bit}]"), reg.register(f"alu.alu8bit.dec.bit{bit+1}.borrow")]
+            if 'layer2' in gate:
+                return [reg.register(f"{prefix}.xor.layer1.or"), reg.register(f"{prefix}.xor.layer1.nand")]
+            if '.borrow' in gate:
+                if bit == 7:
+                    return [reg.register(f"{prefix}.not_a"), reg.get_id("#1")]
+                else:
+                    return [reg.register(f"{prefix}.not_a"), reg.register(f"alu.alu8bit.dec.bit{bit+1}.borrow")]
+        return [reg.get_id(f"$a[{i}]") for i in range(8)]
+    if '.neg.' in gate:
+        m = re.search(r'bit(\d+)', gate)
+        if m:
+            bit = int(m.group(1))
+            if '.not.bit' in gate:
+                return [reg.get_id(f"$a[{bit}]")]
+            prefix = f"alu.alu8bit.neg.inc.bit{bit}"
+            not_bit = f"alu.alu8bit.neg.not.bit{bit}"
+            if 'layer1' in gate:
+                if bit == 7:
+                    return [reg.register(not_bit), reg.get_id("#1")]
+                else:
+                    return [reg.register(not_bit), reg.register(f"alu.alu8bit.neg.inc.bit{bit+1}.carry")]
+            if 'layer2' in gate:
+                return [reg.register(f"{prefix}.xor.layer1.or"), reg.register(f"{prefix}.xor.layer1.nand")]
+            if '.carry' in gate:
+                if bit == 7:
+                    return [reg.register(not_bit), reg.get_id("#1")]
+                else:
+                    return [reg.register(not_bit), reg.register(f"alu.alu8bit.neg.inc.bit{bit+1}.carry")]
+        return [reg.get_id(f"$a[{i}]") for i in range(8)]
+    if '.rol.bit' in gate:
+        m = re.search(r'bit(\d+)', gate)
+        if m:
+            bit = int(m.group(1))
+            src = (bit + 1) % 8
+            return [reg.get_id(f"$a[{src}]")]
+        return [reg.get_id(f"$a[{i}]") for i in range(8)]
+    if '.ror.bit' in gate:
+        m = re.search(r'bit(\d+)', gate)
+        if m:
+            bit = int(m.group(1))
+            src = (bit - 1) % 8
+            return [reg.get_id(f"$a[{src}]")]
+        return [reg.get_id(f"$a[{i}]") for i in range(8)]
     if '.and' in gate or '.or' in gate or '.xor' in gate:
         m = re.search(r'bit(\d+)', gate)
         if m:
@@ -757,9 +994,64 @@ def infer_combinational_inputs(gate: str, reg: SignalRegistry) -> List[int]:
             if '.or' in gate:
                 return [reg.register(f"combinational.regmux4to1.bit{bit}.and{i}") for i in range(4)]
         return []
-    if 'barrelshifter' in gate or 'priorityencoder' in gate:
+    if 'barrelshifter' in gate:
+        for i in range(8):
+            reg.register(f"$x[{i}]")
+        for i in range(3):
+            reg.register(f"$shift[{i}]")
+        m = re.search(r'layer(\d+)\.bit(\d+)', gate)
+        if m:
+            layer, bit = int(m.group(1)), int(m.group(2))
+            shift_amount = 1 << (2 - layer)
+            prefix = f"combinational.barrelshifter.layer{layer}.bit{bit}"
+            if '.not_sel' in gate:
+                return [reg.get_id(f"$shift[{2 - layer}]")]
+            if '.and_a' in gate:
+                if layer == 0:
+                    return [reg.get_id(f"$x[{bit}]"), reg.register(f"{prefix}.not_sel")]
+                else:
+                    prev_prefix = f"combinational.barrelshifter.layer{layer-1}.bit{bit}"
+                    return [reg.register(f"{prev_prefix}.or"), reg.register(f"{prefix}.not_sel")]
+            if '.and_b' in gate:
+                src = (bit + shift_amount) % 8
+                if layer == 0:
+                    return [reg.get_id(f"$x[{src}]"), reg.get_id(f"$shift[{2 - layer}]")]
+                else:
+                    prev_prefix = f"combinational.barrelshifter.layer{layer-1}.bit{src}"
+                    return [reg.register(f"{prev_prefix}.or"), reg.get_id(f"$shift[{2 - layer}]")]
+            if '.or' in gate:
+                return [reg.register(f"{prefix}.and_a"), reg.register(f"{prefix}.and_b")]
+        return [reg.get_id(f"$x[{i}]") for i in range(8)]
+    if 'priorityencoder' in gate:
         for i in range(8):
             reg.register(f"$x[{i}]")
+        if '.any_ge' in gate:
+            m = re.search(r'any_ge(\d+)', gate)
+            if m:
+                pos = int(m.group(1))
+                return [reg.get_id(f"$x[{i}]") for i in range(pos, 8)]
+        if '.is_highest' in gate:
+            m = re.search(r'is_highest(\d+)', gate)
+            if m:
+                pos = int(m.group(1))
+                if '.not_higher' in gate:
+                    if pos == 0:
+                        return [reg.get_id("#0")]
+                    else:
+                        return [reg.register(f"combinational.priorityencoder.any_ge{pos-1}")]
+                if '.and' in gate:
+                    return [reg.get_id(f"$x[{pos}]"), reg.register(f"combinational.priorityencoder.is_highest{pos}.not_higher")]
+        if '.out' in gate:
+            m = re.search(r'out(\d+)', gate)
+            if m:
+                out_bit = int(m.group(1))
+                inputs = []
+                for pos in range(8):
+                    if (pos >> out_bit) & 1:
+                        inputs.append(reg.register(f"combinational.priorityencoder.is_highest{pos}.and"))
+                return inputs
+        if '.valid' in gate:
+            return [reg.get_id(f"$x[{i}]") for i in range(8)]
         return [reg.get_id(f"$x[{i}]") for i in range(8)]
     return []
 
@@ -814,6 +1106,35 @@ def infer_inputs_for_gate(gate: str, reg: SignalRegistry, tensors: Dict[str, tor
             return infer_control_jump_inputs(gate, prefix, reg)
         if any(b in gate for b in ['fetch', 'load', 'store', 'mem_addr']):
             return infer_buffer_inputs(gate, reg)
+        if 'push.sp_dec' in gate or 'pop.sp_inc' in gate:
+            for i in range(16):
+                reg.register(f"$sp[{i}]")
+            m = re.search(r'bit(\d+)', gate)
+            if m:
+                bit = int(m.group(1))
+                op = 'push.sp_dec' if 'push' in gate else 'pop.sp_inc'
+                prefix = f"control.{op}.bit{bit}"
+                if 'layer1' in gate:
+                    if bit == 15:
+                        return [reg.get_id(f"$sp[{bit}]"), reg.get_id("#1")]
+                    else:
+                        carry_name = 'borrow' if 'push' in gate else 'carry'
+                        return [reg.get_id(f"$sp[{bit}]"), reg.register(f"control.{op}.bit{bit+1}.{carry_name}")]
+                if 'layer2' in gate:
+                    return [reg.register(f"{prefix}.xor.layer1.or"), reg.register(f"{prefix}.xor.layer1.nand")]
+                if '.borrow' in gate or '.carry' in gate:
+                    if bit == 15:
+                        return [reg.get_id(f"$sp[{bit}]"), reg.get_id("#1")]
+                    else:
+                        carry_name = 'borrow' if 'push' in gate else 'carry'
+                        return [reg.get_id(f"$sp[{bit}]"), reg.register(f"control.{op}.bit{bit+1}.{carry_name}")]
+            return [reg.get_id(f"$sp[{i}]") for i in range(16)]
+        if 'ret.addr' in gate:
+            m = re.search(r'bit(\d+)', gate)
+            if m:
+                bit = int(m.group(1))
+                return [reg.register(f"$ret_addr[{bit}]")]
+            return [reg.register(f"$ret_addr[{i}]") for i in range(16)]
         return [reg.register("$ctrl")]
     if gate.startswith('memory.'):
         return infer_memory_inputs(gate, reg)
@@ -931,9 +1252,13 @@ def cmd_alu(args) -> None:
     drop_prefixes(tensors, [
         "alu.alu8bit.shl.", "alu.alu8bit.shr.",
         "alu.alu8bit.mul.", "alu.alu8bit.div.",
+        "alu.alu8bit.inc.", "alu.alu8bit.dec.",
+        "alu.alu8bit.neg.", "alu.alu8bit.rol.", "alu.alu8bit.ror.",
         "arithmetic.greaterthan8bit.", "arithmetic.lessthan8bit.",
         "arithmetic.greaterorequal8bit.", "arithmetic.lessorequal8bit.",
         "arithmetic.equality8bit.",
+        "control.push.", "control.pop.", "control.ret.",
+        "combinational.barrelshifter.", "combinational.priorityencoder.",
     ])
     print(f"  Now {len(tensors)} tensors")
     print("\nGenerating SHL/SHR circuits...")
@@ -954,6 +1279,42 @@ def cmd_alu(args) -> None:
         print("  Added DIV (8 stages x comparison + mux)")
     except ValueError as e:
         print(f"  DIV already exists: {e}")
+    print("\nGenerating INC/DEC circuits...")
+    try:
+        add_inc_dec(tensors)
+        print("  Added INC (32 gates), DEC (40 gates)")
+    except ValueError as e:
+        print(f"  INC/DEC already exist: {e}")
+    print("\nGenerating NEG circuit...")
+    try:
+        add_neg(tensors)
+        print("  Added NEG (40 gates)")
+    except ValueError as e:
+        print(f"  NEG already exists: {e}")
+    print("\nGenerating ROL/ROR circuits...")
+    try:
+        add_rol_ror(tensors)
+        print("  Added ROL (8 gates), ROR (8 gates)")
+    except ValueError as e:
+        print(f"  ROL/ROR already exist: {e}")
+    print("\nGenerating stack operation circuits...")
+    try:
+        add_stack_ops(tensors)
+        print("  Added PUSH/POP/RET (144 gates)")
+    except ValueError as e:
+        print(f"  Stack ops already exist: {e}")
+    print("\nGenerating barrel shifter...")
+    try:
+        add_barrel_shifter(tensors)
+        print("  Added barrel shifter (96 gates)")
+    except ValueError as e:
+        print(f"  Barrel shifter already exists: {e}")
+    print("\nGenerating priority encoder...")
+    try:
+        add_priority_encoder(tensors)
+        print("  Added priority encoder (28 gates)")
+    except ValueError as e:
+        print(f"  Priority encoder already exists: {e}")
     print("\nGenerating comparator circuits...")
     try:
         add_comparators(tensors)

neural_computer.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:68c76f0ec6822e071d2532c4ca40a216d959d5344e617990371bbc856134c4a0
-size 34342684
+oid sha256:d8f97c127018647da3a788ee40cbe498ee583d2031bbec04e9347894b1fb5c19
+size 34491396