Sync local state

Remove pycache files

Remove tracked pycache files

Sync packed memory + 16-bit addressing

Add packed memory routing and 16-bit addressing

Add memory circuits and CPU state layout

Add memory circuits and CPU state layout

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Add comprehensive evaluator with 97% tensor coverage

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Update roadmap

Roadmap: Threshold Logic Neural Turing Machine with 64KB memory + LLM integration

Update roadmap: self-contained tensor CPU architecture

Add Instruction Decoder - 44 tensors, 16/16 tests pass

Add PC Load MUX - 50 tensors, 1536/1536 tests pass

Add PC Incrementer - 62 tensors, 256/256 tests pass

Add Register File MUX - 84 tensors, 1036/1036 tests pass

Add HALT circuit - 42 tensors, 24576/24576 tests pass

Add NOP circuit - 24 tensors, 4096/4096 tests pass

Add DIV circuit (8-bit division) - 1984 tensors, 65280/65280 tests pass

Add ROR circuit (rotate right through carry) - 18 tensors, 512/512 tests pass

Add ROL circuit (rotate left through carry) - 18 tensors, 512/512 tests pass

Add ASR circuit (arithmetic shift right) - 26 tensors, 256/256 tests pass

Add CMP circuit (compare with flags) - 168 tensors, 65536/65536 tests pass

Add SBC circuit (subtract with borrow) - 160 tensors, 131072/131072 tests pass

Add ADC circuit (add with carry) - 144 tensors, 131072/131072 tests pass

Add SUB circuit (subtraction) - 162 tensors, 65536/65536 tests pass

Add NEG circuit (two's complement negate) - 76 tensors, 256/256 tests pass

Add missing CPU components todo

Remove tests/test_all.py - merged into eval/iron_eval.py

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Create 16bitupgrade.md

Clean up: remove duplicates, pycache, and misplaced files

Remove old individual test files

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Create todo.md

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