rv32: FCVT.W.S honors the instruction rounding-mode field (RNE/RTZ/RDN/RUP/RMM), verified against an exact rational reference across all modes

src/machines.py

@@ -222,22 +222,48 @@ def fcvt_s_w_ref(x: int) -> int:
     return struct.unpack("<I", struct.pack("<f", float(xi)))[0]
 
 
-def fcvt_w_s_ref(w: int) -> int:
-    """float32 word -> signed int32, round toward zero (RISC-V rtz),
-    saturating; NaN -> INT_MAX, infinities -> INT_MIN/INT_MAX."""
+RM_NAMES = {"rne": 0, "rtz": 1, "rdn": 2, "rup": 3, "rmm": 4, "dyn": 7}
+
+
+def _fcvt_round_up(rm: int, sign: int, guard: int, sticky: int, lsb: int) -> int:
+    """Whether the truncated magnitude rounds up by one ULP under the RISC-V
+    rounding mode (000 RNE, 001 RTZ, 010 RDN, 011 RUP, 100 RMM; 111 DYN has no
+    fcsr in this machine and follows RNE). guard is the half bit just below the
+    integer, sticky the OR of everything beneath it."""
+    if rm == 1:                                        # RTZ: truncate
+        return 0
+    if rm == 2:                                        # RDN: toward -inf
+        return 1 if (sign and (guard or sticky)) else 0
+    if rm == 3:                                        # RUP: toward +inf
+        return 1 if ((not sign) and (guard or sticky)) else 0
+    if rm == 4:                                        # RMM: nearest, ties away
+        return 1 if guard else 0
+    return 1 if (guard and (sticky or lsb)) else 0     # RNE / DYN
+
+
+def fcvt_w_s_ref(w: int, rm: int = 1) -> int:
+    """float32 word -> signed int32 under rounding mode `rm`, saturating;
+    NaN -> INT_MAX, infinities -> INT_MIN/INT_MAX."""
     s, e, f = (w >> 31) & 1, (w >> 23) & 0xFF, w & 0x7FFFFF
     if e == 0xFF:
         return 0x7FFFFFFF if f else (0x80000000 if s else 0x7FFFFFFF)
-    E = e - 127
-    if E < 0:
-        return 0
-    mant = (1 << 23) | f
-    if E >= 31:
+    mant = ((1 << 23) | f) if e else f                 # subnormal: no implicit 1
+    E = (e - 127) if e else -126                       # subnormal exponent 1-bias
+    if E >= 31:                                        # |value| >= 2^31: saturate
         if s and E == 31 and f == 0:
-            return 0x80000000
+            return 0x80000000                          # exactly -2^31
         return 0x80000000 if s else 0x7FFFFFFF
-    mag = (mant << (E - 23)) if E >= 23 else (mant >> (23 - E))
-    return ((-mag) & MASK32) if s else (mag & MASK32)
+    if E >= 23:
+        mag = mant << (E - 23)                          # exact integer, no fraction
+    else:
+        sh = 23 - E
+        mag = mant >> sh
+        guard = (mant >> (sh - 1)) & 1
+        sticky = 1 if (mant & ((1 << (sh - 1)) - 1)) else 0
+        mag += _fcvt_round_up(rm, s, guard, sticky, mag & 1)
+    if s:
+        return 0x80000000 if mag >= 0x80000000 else (-mag) & MASK32
+    return 0x7FFFFFFF if mag > 0x7FFFFFFF else mag & MASK32
 
 
 def sext(v: int, bits: int) -> int:
@@ -343,7 +369,8 @@ class Asm:
         if mn == "fmv.x.w":
             return (0x70 << 25) | (a[1] << 15) | (a[0] << 7) | 0x53
         if mn == "fcvt.w.s":
-            return (0x60 << 25) | (a[1] << 15) | (1 << 12) | (a[0] << 7) | 0x53  # rm=rtz
+            rm = RM_NAMES.get(a[2], a[2]) if len(a) > 2 else 1   # default rtz
+            return (0x60 << 25) | (a[1] << 15) | (rm << 12) | (a[0] << 7) | 0x53
         if mn == "fcvt.s.w":
             return (0x68 << 25) | (a[1] << 15) | (a[0] << 7) | 0x53
         if mn in ("fsgnj.s", "fsgnjn.s", "fsgnjx.s"):
@@ -498,7 +525,7 @@ class RefRV32:
                 from eval import float_bits_to_value
                 x, y = float_bits_to_value(fa, 8, 23), float_bits_to_value(fb, 8, 23)
                 wr(1 if [x <= y, x < y, x == y][f3] else 0)
-            elif f7 == 0x60: wr(fcvt_w_s_ref(FR[rs1]))     # FCVT.W.S
+            elif f7 == 0x60: wr(fcvt_w_s_ref(FR[rs1], f3))  # FCVT.W.S (rm=funct3)
             elif f7 == 0x68: FR[rd] = fcvt_s_w_ref(R[rs1]) # FCVT.S.W
             elif f7 == 0x78: FR[rd] = a
             elif f7 == 0x70: wr(FR[rs1])
@@ -749,18 +776,15 @@ class Rv32ThresholdCPU:
                 exp += 1
         return (s << 31) | (exp << 23) | frac
 
-    def fcvt_w_s(self, w):
-        """float32 -> signed int32, round toward zero (RISC-V rtz), saturating.
-        NaN -> INT_MAX; overflow saturates to INT_MIN/INT_MAX."""
+    def fcvt_w_s(self, w, rm=1):
+        """float32 -> signed int32 under rounding mode `rm`, saturating. The
+        shifts run through the barrel shifter; the round decision is control
+        logic, as in fcvt_s_w. NaN -> INT_MAX; overflow saturates."""
         s, e, f = (w >> 31) & 1, (w >> 23) & 0xFF, w & 0x7FFFFF
         if e == 0xFF:
-            if f:
-                return 0x7FFFFFFF                    # NaN
-            return 0x80000000 if s else 0x7FFFFFFF   # +-inf
-        E = e - 127
-        if E < 0:
-            return 0
-        mant = (1 << 23) | f
+            return 0x7FFFFFFF if f else (0x80000000 if s else 0x7FFFFFFF)
+        mant = ((1 << 23) | f) if e else f
+        E = (e - 127) if e else -126
         if E >= 31:
             if s and E == 31 and f == 0:
                 return 0x80000000                    # exactly -2^31
@@ -768,8 +792,14 @@ class Rv32ThresholdCPU:
         if E >= 23:
             mag = self.sll(mant, E - 23)
         else:
-            mag = self.srl(mant, 23 - E)
-        return self.neg32(mag) if s else (mag & MASK32)
+            sh = 23 - E
+            mag = self.srl(mant, sh) if sh <= 31 else 0
+            guard = (mant >> (sh - 1)) & 1
+            sticky = 1 if (mant & ((1 << (sh - 1)) - 1)) else 0
+            mag += _fcvt_round_up(rm, s, guard, sticky, mag & 1)
+        if s:
+            return 0x80000000 if mag >= 0x80000000 else self.neg32(mag)
+        return 0x7FFFFFFF if mag > 0x7FFFFFFF else (mag & MASK32)
 
     def neur(self, x_reg, w_reg):
         x = int_to_bits(x_reg & 0xFF, 8)      # MSB-first bits of low byte
@@ -1043,7 +1073,7 @@ class Rv32ThresholdCPU:
                     s_out = self._bitwise("xor", sa << 31, sb << 31) >> 31  # FSGNJX.S
                 FR[rd] = (FR[rs1] & 0x7FFFFFFF) | (s_out << 31)
             elif f7 == 0x60:  # FCVT.W.S: float -> signed int, gate-routed
-                wr(self.fcvt_w_s(FR[rs1]))
+                wr(self.fcvt_w_s(FR[rs1], f3))
             elif f7 == 0x68:  # FCVT.S.W: signed int -> float, gate-routed
                 FR[rd] = self.fcvt_s_w(R[rs1])
             elif f7 == 0x78:
@@ -1553,6 +1583,33 @@ def prog_fcvt():
     return mem, 30, lambda s: s["regs"][3] == 8 and s["regs"][5] == (-5 & 0xFFFFFFFF)
 
 
+def prog_fcvt_rm():
+    # FCVT.W.S honors the instruction's rounding-mode field. Convert 2.5, 3.5,
+    # -2.5, 2.75 under several modes and check each against the IEEE result.
+    import struct as _st
+    a = Asm()
+    a.lui(10, 0x1)                       # x10 = 0x1000 (data base)
+    a.flw(1, 10, 0)                      # f1 = 2.5
+    a.flw(2, 10, 4)                      # f2 = 3.5
+    a.flw(3, 10, 8)                      # f3 = -2.5
+    a.flw(4, 10, 12)                     # f4 = 2.75
+    a.fcvt_w_s(1, 1, "rup")              # x1 = ceil(2.5)          = 3
+    a.fcvt_w_s(2, 2, "rne")              # x2 = 3.5 ties to even   = 4
+    a.fcvt_w_s(3, 1, "rne")              # x3 = 2.5 ties to even   = 2
+    a.fcvt_w_s(4, 3, "rdn")              # x4 = floor(-2.5)        = -3
+    a.fcvt_w_s(5, 4, "rtz")              # x5 = trunc(2.75)        = 2
+    a.fcvt_w_s(6, 1, "rmm")             # x6 = 2.5 ties away      = 3
+    a.ecall()
+    mem = a.assemble()
+    for i, v in enumerate((2.5, 3.5, -2.5, 2.75)):
+        wb = _st.unpack("<I", _st.pack("<f", v))[0]
+        for b in range(4):
+            mem[0x1000 + i * 4 + b] = (wb >> (8 * b)) & 0xFF
+    return mem, 40, lambda s: (s["regs"][1] == 3 and s["regs"][2] == 4
+                               and s["regs"][3] == 2 and s["regs"][4] == (-3 & 0xFFFFFFFF)
+                               and s["regs"][5] == 2 and s["regs"][6] == 3)
+
+
 def rv32_netlist_check() -> bool:
     """Verify the rv32-specific sub-circuits (NEUR, hazard, MULHU accumulator)
     are recoverable and correct from the shipped .inputs metadata alone."""
@@ -1616,6 +1673,79 @@ def rv32_netlist_check() -> bool:
     return ok
 
 
+def fcvt_rm_check(cpu) -> bool:
+    """FCVT.W.S under every rounding mode against an exact rational reference,
+    for directed edge encodings (subnormals, ties, saturation) and randoms;
+    the emulator reference and the gate-routed method must both match."""
+    from fractions import Fraction
+    import random
+
+    def value(w):
+        s, e, f = (w >> 31) & 1, (w >> 23) & 0xFF, w & 0x7FFFFF
+        if e == 0:
+            v = Fraction(f, (1 << 23) * (1 << 126))
+        else:
+            v = Fraction((1 << 23) | f, 1 << 23) * (Fraction(2) ** (e - 127))
+        return -v if s else v
+
+    def round_frac(v, rm):
+        fl = v.numerator // v.denominator          # floor (correct for negatives)
+        frac = v - fl
+        if frac == 0:
+            return fl
+        if rm == 1:                                # RTZ
+            return fl + 1 if v < 0 else fl
+        if rm == 2:                                # RDN
+            return fl
+        if rm == 3:                                # RUP
+            return fl + 1
+        if frac < Fraction(1, 2):
+            return fl
+        if frac > Fraction(1, 2):
+            return fl + 1
+        if rm == 4:                                # RMM: ties away from zero
+            return fl + 1 if v > 0 else fl
+        return fl if fl % 2 == 0 else fl + 1       # RNE: ties to even
+
+    def sat(iv):
+        if iv > 0x7FFFFFFF:
+            return 0x7FFFFFFF
+        if iv < -0x80000000:
+            return 0x80000000
+        return iv & MASK32
+
+    words = []
+    for s in (0, 1):
+        for e in (0, 1, 100, 125, 126, 127, 128, 130, 149, 150, 157, 158, 254, 255):
+            for f in (0, 1, 0x400000, 0x7FFFFF):
+                words.append((s << 31) | (e << 23) | f)
+    rng = random.Random(0xFCF7)
+    words += [rng.getrandbits(32) for _ in range(600)]
+
+    bad = None
+    for w in words:
+        s, e, f = (w >> 31) & 1, (w >> 23) & 0xFF, w & 0x7FFFFF
+        for rm in (0, 1, 2, 3, 4):
+            if e == 0xFF:
+                exp = 0x7FFFFFFF if f else (0x80000000 if s else 0x7FFFFFFF)
+            else:
+                exp = sat(round_frac(value(w), rm))
+            ref = fcvt_w_s_ref(w, rm)
+            gate = cpu.fcvt_w_s(w, rm)
+            if not (ref == gate == exp):
+                bad = (w, rm, ref, gate, exp)
+                break
+        if bad:
+            break
+    if bad:
+        w, rm, ref, gate, exp = bad
+        print(f"  fcvt rounding-mode check  FAIL  w={w:08x} rm={rm} "
+              f"ref={ref:08x} gate={gate:08x} exp={exp:08x}")
+        return False
+    print(f"  fcvt rounding-mode check ({len(words)} words x 5 modes vs exact)  PASS")
+    return True
+
+
 def rv32_test() -> int:
     print("Loading neural_rv32...")
     cpu = Rv32ThresholdCPU()
@@ -1627,6 +1757,7 @@ def rv32_test() -> int:
         ("muldiv", prog_muldiv),
         ("float_subset", prog_float),
         ("fcvt_roundtrip", prog_fcvt),
+        ("fcvt_rounding_modes", prog_fcvt_rm),
         ("neur_xor_net", prog_neur),
         ("mmio_print", prog_mmio),
     ]
@@ -1635,6 +1766,7 @@ def rv32_test() -> int:
         mem, budget, check = builder()
         all_ok &= lockstep(cpu, mem, budget, name, check)
     all_ok &= rv32_netlist_check()
+    all_ok &= fcvt_rm_check(cpu)
     print(f"dual-issue pairs retired: {cpu.pairs_issued}")
     print("RV32:", "PASS" if all_ok else "FAIL")
     return 0 if all_ok else 1

todo.md

@@ -4,7 +4,6 @@ Unfinished work.
 
 - The float add, multiply, and divide pipelines handle subnormal operands and produce subnormal results rather than flushing them to zero.
 - The F extension includes a fused multiply-add instruction that rounds once.
-- FCVT.W.S honors the instruction's rounding-mode field instead of always rounding toward zero.
 - Program-counter sequencing and instruction decode are computed by threshold gates rather than by fixed wiring in the runtimes.
 - The standalone float normalize stages, superseded by the composed pipelines' own normalizers, are removed from the circuit inventory.
 - Every gate in the 32-bit multiply circuit resolves its .inputs to a defined signal.