neural_reflect: universal netlist interpreter with indexed addressing, two banks, and a compiler from family nets

README.md

@@ -53,10 +53,10 @@ product followed by thresholding, exactly what a resistive or photonic
 crossbar computes. `neural_subleq8io` hosts a universal constructor: a
 program that reads a description of any machine in the family and prints that
 machine's weight file byte for byte, self-reproduction being the case where
-the description is its own. And `neural_reflect` removes the last fixed part:
-its transition is a ternary threshold network whose weights are stored in the
-writable state it operates on, so a running program can edit the weights that
-define it.
+the description is its own. And `neural_reflect` is a universal interpreter
+over ternary threshold netlists: its fixed transition circuit evaluates a
+netlist held in the writable state, so the machine it runs is stored data that
+a program reads, edits, and reproduces.
 
 ---
 
@@ -505,48 +505,60 @@ weights and checked to the byte.
 ## neural_reflect — an interpreter whose state holds its own weights
 
 Every machine above has a fixed weight tensor: the weights define the machine,
-the state is what it operates on, and the two are disjoint. `neural_reflect`
-removes that separation. The state is a flat array of 256 binary signals; a
-192-bit block of them (the NET region) encodes a netlist of six threshold
-gates, and a fixed ternary interpreter U evaluates one stored gate per
-recurrence. It selects gate `gp`, reads that gate's two ternary input weights,
-integer bias, two input addresses, and one output address from the NET bits,
-fetches the two addressed signals, computes `out = H(w0·v0 + w1·v1 + b)`,
-writes `out` to the addressed signal, and advances `gp`. Six recurrences
-evaluate the stored netlist once.
-
-- **The program shares memory with the data.** Addresses index the whole
-  signal array, so a gate's output can target the NET region: a stored gate
-  can overwrite another gate's weight, bias, or wiring. The running program
-  edits the weights that define it (self-modification), and rewriting the NET
-  region replaces the interpreted machine with another one, with no external
-  load step (metamorphosis).
-- **U is fixed and ternary.** The interpreter is one threshold circuit built
-  from the family's cells (address decoders, 2:1 muxes, a ternary
-  multiply-accumulate over full adders, Heaviside), 2,938 gates compiled to 27
-  ternary matrices by `matrix8`'s compiler. Its behavior is set entirely by
-  the netlist bits in the state, not by its own weights.
-- **Physical reading.** One recurrence is one matrix-vector product with a
-  threshold, and the write is a single bit flip in the state. On a memristive
-  crossbar that bit is a conductance, so a program editing the NET region is
-  the computation editing the array's own weights as it runs.
+the state is what it operates on, and the two are disjoint. `neural_reflect` is
+a universal interpreter that holds the netlist it evaluates in its own writable
+state. The fixed part is a ternary threshold circuit U (12,993 gates, 50
+ternary matrices); everything machine-specific is stored data that the running
+program can read, edit, copy, and replace.
+
+The state is a flat array of 1,024 signals: a pointer register, memory-mapped
+device signals (output stream, pointer advance, bank select, halt) of the kind
+`neural_rv32` and `neural_subleq8io` already use, working signals, and two
+netlist banks. Each stored gate record holds two input slots (address, ternary
+weight, index flag), a signed bias, and an output (address, index flag). One
+recurrence evaluates gate `gp` of the active bank:
+
+```
+eff(addr, idx) = (addr + (idx ? PTR : 0)) mod S
+out = H( w0·sig[eff(a0,i0)] + w1·sig[eff(a1,i1)] + bias ) ;   sig[eff(oa,oidx)] = out
+```
+
+`G` recurrences sweep the netlist once; `G` sweeps settle any acyclic netlist
+regardless of gate order, so U reproduces the family's combinational evaluation.
+
+- **Universality.** `compile_to_reflect` maps any ≤2-input family `Net` to a
+  stored netlist. The family's own full-adder cell, compiled this way, is
+  interpreted bit-exact, and stays correct with its gates stored in arbitrary
+  order.
+- **Self-reference.** Addresses index the whole signal array, so a gate can
+  write into the netlist region: a stored gate edits the weights that define
+  it. The index flag adds `PTR`, so a fixed-size program walks an address
+  range; one such program streams the netlist's own bytes to the output
+  device, emitting its own description. Another copies its bank into the
+  second bank and sets the `BANK` flag, so the interpreter runs a different
+  resident machine without an external load step.
+- **Physical reading.** One recurrence is one matrix-vector product followed by
+  a threshold; each write is one bit of the state. On a memristive crossbar
+  that bit is a conductance, so a program editing the netlist region is the
+  computation editing the array's own weights.
 
 Verified against a reference interpreter: exhaustive single-gate semantics
 (every ternary weight pair, bias, and input assignment), single-step agreement
-on 3,000 random full states plus halted fixed points, lockstep interpretation
-of a composed XOR built from the family's gates, and a program that rewrites
-its own AND gate into an OR gate between sweeps (output `a & b` on the first
-sweep, `a | b` on the second). The compiled matrix form is checked equal to
-the gate graph bit for bit.
+on random full states with halted states as fixed points, bit-exact
+interpretation of the full-adder cell under sorted and shuffled gate order, the
+self-reproduction and bank-replacement programs, and equality of the compiled
+matrix form with the gate graph, the 0.5 comparator margin measured under read
+noise and conductance mismatch.
 
 ```bash
-python src/reflect.py build      # compile + save variants/neural_reflect.safetensors
-python src/reflect.py verify     # reference equality, self-modification, matrix == gate
+python src/reflect.py verify     # universality, order independence, quine, metamorphosis
+python src/reflect.py analog     # matrix == gate + noise / conductance-mismatch margin
 ```
 
-The constructor prints a machine's weights; this interprets them out of its
-own memory and can rewrite them mid-run. The transition and the state it
-transforms are the same tensor.
+The fixed interpreter is a substrate, universal over ternary threshold
+netlists; the machine it runs is stored data that reads, rewrites, and
+reproduces itself. The transition and the state it transforms are the same
+tensor.
 
 ---
 
@@ -736,8 +748,8 @@ src/                                the library (run scripts as `python src/<nam
   │                                 exhaustive equality suite and the analog crossbar simulation
   ├── constructor8.py               the neural_subleq8io host, the recipe codec, and the universal
   │                                 constructor / self-reproduction suite
-  └── reflect.py                    neural_reflect: a threshold interpreter whose state holds its
-                                    own gate table; reference equality + self-modification suite
+  └── reflect.py                    neural_reflect: a universal threshold interpreter whose state
+                                    holds its own gate table; universality / quine / matrix suites
 tools/                              build_all.py (build + quantize + verify every profile),
                                     cpu_programs.py (assembler + CPU program suite), test_cpu.py
                                     (program suite vs a variant), play.py (interactive demo),

src/reflect.py

@@ -1,40 +1,50 @@
-"""neural_reflect — a self-interpreting ternary threshold processor whose
-transition is determined by weights stored in its own writable state.
-
-Every other machine in the family has a fixed weight tensor: the weights are
-what the machine is, the state is what it operates on, and the two never
-touch. neural_reflect removes that separation. The state is a flat array of S
-binary signals; a contiguous block of them (the NET region) encodes a netlist
-of G threshold gates, and a fixed ternary interpreter U evaluates one stored
-gate per recurrence:
-
-  1. select gate gp (an interpreter register) from the stored table,
-  2. read its two ternary input weights, integer bias, and two input
-     addresses and one output address (all addresses index the S signals),
-  3. fetch the two addressed signal values (indirect read),
-  4. compute out = H(w0*v0 + w1*v1 + bias),
-  5. write out to the addressed signal (indirect write),
-  6. gp = (gp + 1) mod G.
-
-G recurrences evaluate the whole stored netlist once. Because the addresses
-in step 5 may point into the NET region, a stored gate can overwrite the
-encoding of another gate: the running program edits the weights that define
-it (self-modification), and by rewriting the whole NET region it becomes a
-different machine with no external constructor (metamorphosis). U is a fixed
-ternary threshold circuit ({-1,0,1} weights, integer biases, Heaviside step),
-compiled to a recurrent matrix stack by matrix8's compiler; on a memristive
-crossbar the write in step 5 is a conductance change, so a program editing
-NET is the computation editing the array's own weights.
-
-The interpreter is verified against a reference in four ways: exhaustive
-single-gate semantics, single-step agreement on random full states, lockstep
-interpretation of loaded netlists (a composed XOR built from the family's
-gates, and a program that rewrites its own gate table between sweeps), and
-gate-graph vs matrix-form equality.
+"""neural_reflect — a universal ternary-threshold netlist processor whose
+transition is a fixed, machine-independent interpreter U over a netlist held
+in the writable state.
+
+U is the only fixed part: a ternary threshold circuit that evaluates one stored
+gate per recurrence. Everything machine-specific is the stored netlist, which
+the running program can read, edit, copy, and replace. U is universal over
+ternary threshold netlists, so the fixed part is a substrate (like a
+cellular-automaton rule), not a particular machine.
+
+State: a flat array of S binary signals (A = log2 S), two netlist banks, and
+memory-mapped device signals of the kind the rest of the family already uses
+(rv32's console, subleq8io's tape):
+
+    [ PTR | OUT_DATA OUT_STROBE PTR_ADV BANK HALT | work | NET bank0 | NET bank1 ]
+
+Each gate record holds F input slots (address, ternary weight, index flag), a
+signed bias, and an output (address, index flag). An index flag adds PTR to the
+address, so a fixed-size program can walk an address range. Writing OUT_STROBE
+emits OUT_DATA; writing PTR_ADV advances PTR; both are cleared by the device.
+These make loaders, a self-reproduction quine, and bank replacement expressible
+as programs.
+
+One recurrence, gate gp of the active bank:
+    eff(addr, idx) = (addr + (idx ? PTR : 0)) mod S
+    out = H( sum_j w_j * sig[eff(a_j, i_j)] + bias )
+    sig[eff(oa, oidx)] = out
+G recurrences sweep the netlist once; G sweeps settle any acyclic netlist
+regardless of gate order, so U reproduces the family's combinational evaluation.
+
+Capabilities:
+  - compile_to_reflect() maps any <=2-input family Net to a stored netlist; the
+    family's full-adder cell runs through the interpreter bit-exact.
+  - A netlist stored in arbitrary gate order yields the combinational result,
+    since G sweeps relax to the fixed point.
+  - A program streams the netlist's own bytes to the output device, emitting its
+    own description.
+  - A program copies its bank into the other bank and sets the BANK flag to run
+    a different resident machine, without an external load step.
+  - The accumulator width follows from F and the bias width. U compiles to a
+    recurrent ternary matrix stack equal to the gate graph, with a measured
+    noise and conductance-mismatch margin.
 
 Usage:
-    python src/reflect.py build     # compile + save variants/neural_reflect.safetensors
-    python src/reflect.py verify    # reference equality + self-modification + matrix==gate
+    python src/reflect.py build     # save variants/neural_reflect.safetensors
+    python src/reflect.py verify    # universality, order, quine, metamorphosis
+    python src/reflect.py analog    # matrix == gate + noise / mismatch margins
     python src/reflect.py all
 """
 
@@ -42,9 +52,12 @@ from __future__ import annotations
 
 import argparse
 import json
+import math
 import os
+import random
 import sys
 import time
+from dataclasses import dataclass, field
 from typing import Dict, List, Tuple
 
 import torch
@@ -56,467 +69,664 @@ from matrix8 import Net, compile_net
 REPO = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
 MODEL_PATH = os.path.join(REPO, "variants", "neural_reflect.safetensors")
 
-# --- configuration (parametric; this instance is the shipped one) ----------
-S = 256            # addressable signal bits (the whole RAM)
-A = 8              # address width, 2**A == S
-G = 6              # stored gates
-F = 2              # inputs per gate (the family builds everything from <=2-in gates)
-WB = 2             # weight-code bits per input
-BB = 4             # bias bits (signed)
-R = F * (A + WB) + BB + A       # 32 bits per gate record
-NET_BASE = S - G * R            # 64: records occupy the high signals
-HALT_SIG = NET_BASE - 1         # 63: a data bit the program raises to halt
-GPW = 3                         # gp register width (ceil(log2 G))
-STATE_BITS = S + GPW + 1        # signals, gp, halt
+WCODE = {1: (0, 1), -1: (1, 0), 0: (0, 0)}
 
-assert (1 << A) == S and NET_BASE == 64 and R == 32
 
-# record field offsets (MSB-first within the 32-bit record)
-OFF_A0, OFF_W0 = 0, 8
-OFF_A1, OFF_W1 = 10, 18
-OFF_BIAS, OFF_OUT = 20, 24
+# =============================================================================
+# configuration
+# =============================================================================
 
-WCODE = {1: (0, 1), -1: (1, 0), 0: (0, 0)}   # (hi, lo), MSB-first
+@dataclass
+class Cfg:
+    A: int = 10
+    G: int = 11
+    F: int = 2
+    BB: int = 4
+    banks: int = 2
+
+    def __post_init__(self):
+        self.S = 1 << self.A
+        self.SLOT = self.A + 3
+        self.R = self.F * self.SLOT + self.BB + (self.A + 1)
+        span = self.F + (1 << (self.BB - 1))
+        self.ACC = int(math.ceil(math.log2(span + 1))) + 2
+        self.PTR_BASE = 0
+        self.OUT_DATA = self.A
+        self.OUT_STROBE = self.A + 1
+        self.PTR_ADV = self.A + 2
+        self.BANK_SIG = self.A + 3
+        self.HALT_SIG = self.A + 4
+        self.TRASH = self.A + 5           # no-op sink; no program reads it
+        self.WORK_BASE = self.A + 6
+        self.NET0 = self.S - self.banks * self.G * self.R
+        self.NET1 = self.NET0 + self.G * self.R
+        self.GPW = max(1, (self.G - 1).bit_length())
+        self.STATE_BITS = self.S + self.GPW + 1
+        assert self.NET0 >= self.WORK_BASE + 16, "too little data room; raise A"
+
+    def bank_base(self, bank):
+        return self.NET0 if bank == 0 else self.NET1
+
+
+def slot_off(cfg, j):
+    return j * cfg.SLOT
+
+
+def field_off(cfg):
+    o = cfg.F * cfg.SLOT
+    return o, o + cfg.BB
 
 
 # =============================================================================
-# bit helpers and netlist encoding
+# bit helpers + encoding
 # =============================================================================
 
-def to_bits(v: int, n: int) -> List[int]:
+def to_bits(v, n):
     return [(v >> (n - 1 - i)) & 1 for i in range(n)]
 
 
-def from_bits(bits: List[int]) -> int:
+def from_bits(bits):
     v = 0
     for b in bits:
         v = (v << 1) | int(b)
     return v
 
 
-def signed(bits: List[int]) -> int:
+def signed(bits):
     v = from_bits(bits)
     return v - (1 << len(bits)) if bits[0] else v
 
 
-def encode_gate(s0: Tuple[int, int], s1: Tuple[int, int], bias: int, out: int) -> List[int]:
-    """(addr, weight) per input, signed bias, output address -> 32-bit record."""
-    (a0, w0), (a1, w1) = s0, s1
-    rec = [0] * R
-    rec[OFF_A0:OFF_A0 + A] = to_bits(a0, A)
-    rec[OFF_W0:OFF_W0 + WB] = list(WCODE[w0])
-    rec[OFF_A1:OFF_A1 + A] = to_bits(a1, A)
-    rec[OFF_W1:OFF_W1 + WB] = list(WCODE[w1])
-    rec[OFF_BIAS:OFF_BIAS + BB] = to_bits(bias & ((1 << BB) - 1), BB)
-    rec[OFF_OUT:OFF_OUT + A] = to_bits(out, A)
+def encode_gate(cfg, slots, bias, out):
+    rec = [0] * cfg.R
+    for j, (a, w, idx) in enumerate(slots):
+        b = slot_off(cfg, j)
+        rec[b:b + cfg.A] = to_bits(a, cfg.A)
+        rec[b + cfg.A:b + cfg.A + 2] = list(WCODE[w])
+        rec[b + cfg.A + 2] = idx
+    bo, oo = field_off(cfg)
+    rec[bo:bo + cfg.BB] = to_bits(bias & ((1 << cfg.BB) - 1), cfg.BB)
+    oa, oidx = out
+    rec[oo:oo + cfg.A] = to_bits(oa, cfg.A)
+    rec[oo + cfg.A] = oidx
     return rec
 
 
-NOOP = ((0, 0), (0, 0), -1, HALT_SIG - 1)   # weights 0, bias<0 -> writes 0 to a scratch bit
+def pad(cfg, slots):
+    slots = list(slots)
+    while len(slots) < cfg.F:
+        slots.append((0, 0, 0))
+    return slots[:cfg.F]
 
 
-def encode_netlist(gates: List[tuple]) -> List[int]:
-    """Pack up to G gate records into the NET region (returns G*R bits)."""
-    assert len(gates) <= G
-    padded = list(gates) + [NOOP] * (G - len(gates))
-    out: List[int] = []
-    for (s0, s1, bias, o) in padded:
-        out += encode_gate(s0, s1, bias, o)
+def encode_netlist(cfg, gates):
+    out = []
+    noop = ([(0, 0, 0)] * cfg.F, -1, (cfg.TRASH, 0))
+    for g in (gates + [noop] * (cfg.G - len(gates))):
+        slots, bias, o = g
+        out += encode_gate(cfg, pad(cfg, slots), bias, o)
     return out
 
 
-def make_state(signals: List[int], gp: int = 0, halt: int = 0,
-               netlist: List[tuple] | None = None) -> dict:
-    sig = list(signals) + [0] * (S - len(signals))
-    if netlist is not None:
-        sig[NET_BASE:S] = encode_netlist(netlist)
-    return {"sig": sig[:S], "gp": gp, "halt": int(halt)}
-
-
 # =============================================================================
-# reference interpreter (one stored gate per step)
+# reference: gate step + memory-mapped device logic
 # =============================================================================
 
-def ref_step(st: dict) -> dict:
-    sig, gp, halt = list(st["sig"]), st["gp"], st["halt"]
+def apply_device(cfg, sig):
+    emit = None
+    if sig[cfg.OUT_STROBE] == 1:
+        emit = sig[cfg.OUT_DATA]
+        sig[cfg.OUT_STROBE] = 0
+    if sig[cfg.PTR_ADV] == 1:
+        p = (from_bits(sig[cfg.PTR_BASE:cfg.PTR_BASE + cfg.A]) + 1) & (cfg.S - 1)
+        sig[cfg.PTR_BASE:cfg.PTR_BASE + cfg.A] = to_bits(p, cfg.A)
+        sig[cfg.PTR_ADV] = 0
+    return emit
+
+
+def ref_gate(cfg, st):
+    sig = list(st["sig"]); gp = st["gp"]; halt = st["halt"]
     if halt:
-        return {"sig": sig, "gp": gp, "halt": halt}
-    base = NET_BASE + gp * R
-    rec = sig[base:base + R]
-
-    def wval(hilo):
-        hi, lo = hilo
-        if (hi, lo) == (0, 1):
-            return 1
-        if (hi, lo) == (1, 0):
-            return -1
-        return 0
-
-    a0 = from_bits(rec[OFF_A0:OFF_A0 + A]); w0 = wval((rec[OFF_W0], rec[OFF_W0 + 1]))
-    a1 = from_bits(rec[OFF_A1:OFF_A1 + A]); w1 = wval((rec[OFF_W1], rec[OFF_W1 + 1]))
-    bias = signed(rec[OFF_BIAS:OFF_BIAS + BB])
-    oa = from_bits(rec[OFF_OUT:OFF_OUT + A])
-    acc = w0 * sig[a0] + w1 * sig[a1] + bias
+        return sig, gp, halt
+    ptr = from_bits(sig[cfg.PTR_BASE:cfg.PTR_BASE + cfg.A])
+    bank = sig[cfg.BANK_SIG]
+    rec = sig[cfg.bank_base(bank) + gp * cfg.R:][:cfg.R]
+
+    def eff(a, idx):
+        return (a + (ptr if idx else 0)) & (cfg.S - 1)
+
+    def wv(hilo):
+        return {(0, 1): 1, (1, 0): -1}.get(tuple(hilo), 0)
+
+    acc = 0
+    for j in range(cfg.F):
+        b = slot_off(cfg, j)
+        acc += wv(rec[b + cfg.A:b + cfg.A + 2]) * sig[eff(from_bits(rec[b:b + cfg.A]), rec[b + cfg.A + 2])]
+    bo, oo = field_off(cfg)
+    acc += signed(rec[bo:bo + cfg.BB])
     out = 1 if acc >= 0 else 0
-    h = sig[HALT_SIG]              # halt latches from the pre-write value, as U does
-    sig[oa] = out
-    ngp = 0 if gp == G - 1 else gp + 1
-    nhalt = 1 if (halt or h) else 0
-    return {"sig": sig, "gp": ngp, "halt": nhalt}
+    dst = eff(from_bits(rec[oo:oo + cfg.A]), rec[oo + cfg.A])
+    h = sig[cfg.HALT_SIG]
+    sig[dst] = out
+    ngp = 0 if gp == cfg.G - 1 else gp + 1
+    return sig, ngp, (1 if (halt or h) else 0)
+
+
+def ref_step(cfg, st):
+    halt_in = st["halt"]
+    sig, gp, halt = ref_gate(cfg, st)
+    emit = apply_device(cfg, sig) if halt_in == 0 else None
+    return {"sig": sig, "gp": gp, "halt": halt, "emit": emit}
 
 
 # =============================================================================
 # the interpreter as a fixed ternary threshold circuit
 # =============================================================================
 
-def build_reflect_net() -> Tuple[Net, List[str], List[str]]:
+def build_net(cfg):
     net = Net()
-    sig = [f"s{i}" for i in range(S)]
-    gp = [f"gp{k}" for k in range(GPW)]
+    sig = [f"s{i}" for i in range(cfg.S)]
+    gp = [f"gp{k}" for k in range(cfg.GPW)]
     halt = "halt"
     nhalt = net.NOT("nhalt", halt)
+    bank = sig[cfg.BANK_SIG]
+    gp_oh = [net.DECODE(f"gpoh{g}", gp, g) for g in range(cfg.G)]
+
+    def netbit(g, r):
+        b0 = sig[cfg.NET0 + g * cfg.R + r]
+        if cfg.banks == 1:
+            return b0
+        return net.MUX(f"bk{g}_{r}", bank, sig[cfg.NET1 + g * cfg.R + r], b0)
+
+    recbit = [net.OR(f"rb{r}", [net.AND(f"rb{r}g{g}", [gp_oh[g], netbit(g, r)])
+                                for g in range(cfg.G)]) for r in range(cfg.R)]
+
+    ptr = [sig[cfg.PTR_BASE + k] for k in range(cfg.A)]
+
+    def eff_addr(addrbits, idx, tag):
+        m = [net.AND(f"pm{tag}_{k}", [ptr[k], idx]) for k in range(cfg.A)]
+        a_lsb = [addrbits[cfg.A - 1 - k] for k in range(cfg.A)]
+        m_lsb = [m[cfg.A - 1 - k] for k in range(cfg.A)]
+        c = "#0"; s_lsb = []
+        for k in range(cfg.A):
+            s_, c = net.FA(f"eff{tag}_fa{k}", a_lsb[k], m_lsb[k], c)
+            s_lsb.append(s_)
+        return [s_lsb[cfg.A - 1 - k] for k in range(cfg.A)]
 
-    # gate select (gp one-hot over 0..G-1)
-    gp_oh = [net.DECODE(f"gpoh{g}", gp, g) for g in range(G)]
-
-    # read the selected record: recbit[r] = OR_g (gp_oh[g] AND NET[g,r])
-    recbit = []
-    for r in range(R):
-        terms = [net.AND(f"rb{r}g{g}", [gp_oh[g], sig[NET_BASE + g * R + r]]) for g in range(G)]
-        recbit.append(net.OR(f"rb{r}", terms))
-
-    a0 = recbit[OFF_A0:OFF_A0 + A]
-    w0 = (recbit[OFF_W0], recbit[OFF_W0 + 1])
-    a1 = recbit[OFF_A1:OFF_A1 + A]
-    w1 = (recbit[OFF_W1], recbit[OFF_W1 + 1])
-    biasbits = recbit[OFF_BIAS:OFF_BIAS + BB]
-    oabits = recbit[OFF_OUT:OFF_OUT + A]
-
-    # indirect reads: val_j = OR_s ( decode(addr_j)==s AND sig[s] )
     def read(addrbits, tag):
-        terms = []
-        for s in range(S):
-            oh = net.DECODE(f"rd{tag}oh{s}", addrbits, s)
-            terms.append(net.AND(f"rd{tag}a{s}", [oh, sig[s]]))
-        return net.OR(f"rd{tag}", terms)
-
-    v0 = read(a0, "0")
-    v1 = read(a1, "1")
-
-    # ternary contribution c_j in {-1,0,1}, two's complement (bit0 magnitude, sign)
-    def contrib(w, v, tag):
-        hi, lo = w
-        pos = net.AND(f"pos{tag}", [net.NOT(f"nhi{tag}", hi), lo])
-        neg = net.AND(f"neg{tag}", [hi, net.NOT(f"nlo{tag}", lo)])
-        mag = net.OR(f"mag{tag}", [net.AND(f"tp{tag}", [pos, v]),
-                                   net.AND(f"tn{tag}", [neg, v])])
-        sign = net.AND(f"csgn{tag}", [neg, v])
-        return mag, sign
-
-    m0, sg0 = contrib(w0, v0, "0")
-    m1, sg1 = contrib(w1, v1, "1")
-
-    # acc = c0 + c1 + bias over 6-bit two's complement (LSB-first), out = acc >= 0
-    W6 = 6
-
-    def c_lsb(mag, sign):
-        return [mag] + [sign] * (W6 - 1)
-
-    def bias_lsb():
-        b = biasbits  # MSB-first [b3(sign) b2 b1 b0]
-        lo = [b[3], b[2], b[1], b[0]]          # b0..b3 LSB-first
-        return lo + [b[0]] * (W6 - BB)         # sign-extend b3
-
-    def ripple(pfx, a_lsb, b_lsb):
-        c = "#0"
-        out = []
-        for k in range(W6):
-            s_, c = net.FA(f"{pfx}.fa{k}", a_lsb[k], b_lsb[k], c)
+        return net.OR(f"rd{tag}", [net.AND(f"rd{tag}a{s}", [net.DECODE(f"rd{tag}oh{s}", addrbits, s), sig[s]])
+                                   for s in range(cfg.S)])
+
+    contribs = []
+    for j in range(cfg.F):
+        b = slot_off(cfg, j)
+        addrbits = recbit[b:b + cfg.A]
+        hi, lo, idx = recbit[b + cfg.A], recbit[b + cfg.A + 1], recbit[b + cfg.A + 2]
+        v = read(eff_addr(addrbits, idx, f"r{j}"), f"{j}")
+        pos = net.AND(f"pos{j}", [net.NOT(f"nhi{j}", hi), lo])
+        neg = net.AND(f"neg{j}", [hi, net.NOT(f"nlo{j}", lo)])
+        mag = net.OR(f"mag{j}", [net.AND(f"tp{j}", [pos, v]), net.AND(f"tn{j}", [neg, v])])
+        contribs.append((mag, net.AND(f"sg{j}", [neg, v])))
+
+    W = cfg.ACC
+    bo, oo = field_off(cfg)
+    biasbits = recbit[bo:bo + cfg.BB]
+
+    def clsb(mag, sign):
+        return [mag] + [sign] * (W - 1)
+
+    def blsb():
+        lo = [biasbits[cfg.BB - 1 - k] for k in range(cfg.BB)]
+        return lo + [biasbits[0]] * (W - cfg.BB)
+
+    def ripple(pfx, a, b):
+        c = "#0"; out = []
+        for k in range(W):
+            s_, c = net.FA(f"{pfx}_fa{k}", a[k], b[k], c)
             out.append(s_)
         return out
 
-    s01 = ripple("acc0", c_lsb(m0, sg0), c_lsb(m1, sg1))
-    acc = ripple("acc1", s01, bias_lsb())
-    out = net.NOT("out", acc[W6 - 1])          # acc >= 0  <=>  sign bit 0
+    acc = clsb(*contribs[0])
+    for j in range(1, cfg.F):
+        acc = ripple(f"acc{j}", acc, clsb(*contribs[j]))
+    acc = ripple("accb", acc, blsb())
+    out = net.NOT("out", acc[W - 1])
 
-    # indirect write: sig'[s] = (decode(outaddr)==s AND nhalt) ? out : sig[s]
+    oea = eff_addr(recbit[oo:oo + cfg.A], recbit[oo + cfg.A], "w")
     nsig = []
-    for s in range(S):
-        oh = net.DECODE(f"wroh{s}", oabits, s)
-        sel = net.AND(f"wrsel{s}", [oh, nhalt])
+    for s in range(cfg.S):
+        sel = net.AND(f"wrsel{s}", [net.DECODE(f"wroh{s}", oea, s), nhalt])
         nsig.append(net.MUX(f"nsig{s}", sel, out, sig[s]))
 
-    # gp' = nhalt ? ((gp == G-1) ? 0 : gp+1) : gp   (3-bit increment)
-    gp_lsb = [gp[GPW - 1 - k] for k in range(GPW)]
+    gp_lsb = [gp[cfg.GPW - 1 - k] for k in range(cfg.GPW)]
     inc, c = [], "#1"
-    for k in range(GPW):
-        s_ = net.XOR(f"gpinc.x{k}", gp_lsb[k], c)
-        c = net.AND(f"gpinc.c{k}", [gp_lsb[k], c])
-        inc.append(s_)
-    inc_msb = [inc[GPW - 1 - k] for k in range(GPW)]
-    wrapped = [net.MUX(f"gpwrap{k}", gp_oh[G - 1], "#0", inc_msb[k]) for k in range(GPW)]
-    ngp = [net.MUX(f"ngp{k}", nhalt, wrapped[k], gp[k]) for k in range(GPW)]
+    for k in range(cfg.GPW):
+        inc.append(net.XOR(f"gpi_x{k}", gp_lsb[k], c))
+        c = net.AND(f"gpi_c{k}", [gp_lsb[k], c])
+    inc_msb = [inc[cfg.GPW - 1 - k] for k in range(cfg.GPW)]
+    wrap = [net.MUX(f"gpw{k}", gp_oh[cfg.G - 1], "#0", inc_msb[k]) for k in range(cfg.GPW)]
+    ngp = [net.MUX(f"ngp{k}", nhalt, wrap[k], gp[k]) for k in range(cfg.GPW)]
+    nhalt_out = net.OR("halt_next", [halt, sig[cfg.HALT_SIG]])
 
-    nhalt_out = net.OR("halt_next", [halt, sig[HALT_SIG]])
+    return net, sig + gp + [halt], nsig + ngp + [nhalt_out]
 
-    outputs = nsig + ngp + [nhalt_out]
-    inputs = sig + gp + [halt]
-    return net, inputs, outputs
+
+# =============================================================================
+# leveled sparse evaluator (scales past dense matrices)
+# =============================================================================
+
+class Leveled:
+    def __init__(self, net, inputs, outputs, device="cpu"):
+        self.device = device
+        self.inputs = inputs
+        gates = net.gates
+        indeg = {g: 0 for g in gates}
+        cons: Dict[str, List[str]] = {}
+        for g, (ins, _) in gates.items():
+            for s, _w in ins:
+                if s in gates:
+                    indeg[g] += 1
+                cons.setdefault(s, []).append(g)
+        order = [g for g, d in indeg.items() if d == 0]
+        i = 0
+        while i < len(order):
+            for c in cons.get(order[i], []):
+                if c in gates:
+                    indeg[c] -= 1
+                    if indeg[c] == 0:
+                        order.append(c)
+            i += 1
+        assert len(order) == len(gates), "cycle"
+        names = ["#0", "#1"] + inputs + order
+        slot = {n: i for i, n in enumerate(names)}
+        depth = {n: 0 for n in names if n not in gates}
+        for g in order:
+            depth[g] = 1 + max((depth[s] for s, _ in gates[g][0]), default=0)
+        by_level: Dict[int, List[str]] = {}
+        for g in order:
+            by_level.setdefault(depth[g], []).append(g)
+        self.n_sig = len(names)
+        self.plan = []
+        for lv in sorted(by_level):
+            gs = by_level[lv]
+            fan = max(len(gates[g][0]) for g in gs)
+            idx = torch.zeros(len(gs), fan, dtype=torch.long)
+            w = torch.zeros(len(gs), fan)
+            b = torch.zeros(len(gs))
+            out = torch.zeros(len(gs), dtype=torch.long)
+            for r, g in enumerate(gs):
+                ins, bias = gates[g]
+                out[r] = slot[g]; b[r] = bias
+                for c, (s, wt) in enumerate(ins):
+                    idx[r, c] = slot[s]; w[r, c] = wt
+            self.plan.append((idx.to(device), w.to(device), b.to(device), out.to(device)))
+        self.in_slots = torch.tensor([slot[n] for n in inputs], device=device)
+        self.out_slots = torch.tensor([slot[n] for n in outputs], device=device)
+
+    def step(self, invec):
+        B = invec.shape[0]
+        V = torch.zeros(self.n_sig, B, device=self.device)
+        V[1] = 1.0
+        V[self.in_slots] = invec.T
+        for idx, w, b, out in self.plan:
+            g = V[idx]
+            V[out] = ((g * w[:, :, None]).sum(1) + b[:, None] >= 0).float()
+        return V[self.out_slots].T
+
+
+def state_to_vec(cfg, st):
+    v = torch.zeros(cfg.STATE_BITS)
+    v[:cfg.S] = torch.tensor(st["sig"], dtype=torch.float32)
+    v[cfg.S:cfg.S + cfg.GPW] = torch.tensor(to_bits(st["gp"], cfg.GPW), dtype=torch.float32)
+    v[cfg.S + cfg.GPW] = float(st["halt"])
+    return v
+
+
+def vec_to_state(cfg, v):
+    b = [int(round(float(x))) for x in (v.tolist() if hasattr(v, "tolist") else v)]
+    return {"sig": b[:cfg.S], "gp": from_bits(b[cfg.S:cfg.S + cfg.GPW]), "halt": b[cfg.S + cfg.GPW]}
+
+
+class Runner:
+    def __init__(self, cfg, lev):
+        self.cfg = cfg
+        self.lev = lev
+
+    def step(self, st):
+        halt_in = st["halt"]
+        v = state_to_vec(self.cfg, st).unsqueeze(0).to(self.lev.device)
+        out = self.lev.step(v[:, :len(self.lev.inputs)])[0].cpu()
+        ns = vec_to_state(self.cfg, out)
+        ns["emit"] = apply_device(self.cfg, ns["sig"]) if halt_in == 0 else None
+        return ns
+
+    def run(self, st, n, collect=False):
+        emits = []
+        for _ in range(n):
+            st = self.step(st)
+            if collect and st.get("emit") is not None:
+                emits.append(st["emit"])
+        return (st, emits) if collect else st
 
 
 # =============================================================================
-# gate-graph evaluator (independent of the matrix compile) for matrix==gate
+# compile a <=2-input family Net into a stored reflect netlist
 # =============================================================================
 
-def eval_net(net: Net, inputs: List[str], outputs: List[str],
-             values: Dict[str, int]) -> List[int]:
-    v = dict(values)
-    v["#0"], v["#1"] = 0, 1
-    indeg = {g: 0 for g in net.gates}
+def topo(net):
+    gates = net.gates
+    indeg = {g: 0 for g in gates}
     cons: Dict[str, List[str]] = {}
-    for g, (ins, _) in net.gates.items():
+    for g, (ins, _) in gates.items():
         for s, _w in ins:
-            if s in net.gates:
+            if s in gates:
                 indeg[g] += 1
             cons.setdefault(s, []).append(g)
     order = [g for g, d in indeg.items() if d == 0]
     i = 0
     while i < len(order):
         for c in cons.get(order[i], []):
-            if c in net.gates:
+            if c in gates:
                 indeg[c] -= 1
                 if indeg[c] == 0:
                     order.append(c)
         i += 1
-    for g in order:
-        ins, b = net.gates[g]
-        acc = b + sum(w * v[s] for s, w in ins)
-        v[g] = 1 if acc >= 0 else 0
-    return [v[o] for o in outputs]
+    assert len(order) == len(gates)
+    return order
+
+
+def compile_to_reflect(cfg, net, in_addr, out_names, work_start):
+    addr = dict(in_addr)
+    w = work_start
+    rgates = []
+    for g in topo(net):
+        ins, bias = net.gates[g]
+        assert len(ins) <= cfg.F
+        addr[g] = w; w += 1
+        slots = [(addr[s], wt, 0) for s, wt in ins]
+        rgates.append((slots, bias, (addr[g], 0)))
+    assert len(rgates) <= cfg.G, f"{len(rgates)} gates > bank {cfg.G}"
+    return rgates, addr
+
+
+def adder_net(bits):
+    """N-bit ripple-carry adder from the family's full-adder cell."""
+    net = Net()
+    a = [f"a{i}" for i in range(bits)]
+    b = [f"b{i}" for i in range(bits)]
+    carry = "#0"
+    sums = []
+    for i in range(bits):
+        s_, carry = net.FA(f"fa{i}", a[i], b[i], carry)
+        sums.append(s_)
+    return net, a, b, sums, carry
 
 
 # =============================================================================
-# state <-> vector, and the compiled matrix runtime
+# programs (stored netlists) for the reflective demos
 # =============================================================================
 
-def state_to_vec(st: dict) -> torch.Tensor:
-    v = torch.zeros(STATE_BITS)
-    v[:S] = torch.tensor(st["sig"], dtype=torch.float32)
-    v[S:S + GPW] = torch.tensor(to_bits(st["gp"], GPW), dtype=torch.float32)
-    v[S + GPW] = float(st["halt"])
-    return v
+def quine_program(cfg):
+    # emit sig[NET0 + ptr], strobe, advance ptr
+    return [([(cfg.NET0, 1, 1)], -1, (cfg.OUT_DATA, 0)),   # OUT_DATA = NET0[ptr]
+            ([], 0, (cfg.OUT_STROBE, 0)),                  # OUT_STROBE = 1
+            ([], 0, (cfg.PTR_ADV, 0))]                     # PTR_ADV = 1
 
 
-def vec_to_state(v: torch.Tensor) -> dict:
-    b = [int(round(float(x))) for x in v.tolist()]
-    return {"sig": b[:S], "gp": from_bits(b[S:S + GPW]), "halt": b[S + GPW]}
-
-
-class Reflect:
-    HALT_IDX = S + GPW
-
-    def __init__(self, layers, device="cpu"):
-        self.W = [W.to(device=device, dtype=torch.float32) for W, _ in layers]
-        self.B = [B.to(device=device, dtype=torch.float32) for _, B in layers]
-        self.device = device
-
-    def step(self, v: torch.Tensor) -> torch.Tensor:
-        for W, b in zip(self.W, self.B):
-            v = ((v @ W.T + b) >= 0).float()
-        return v
-
-    def run_steps(self, st: dict, n: int) -> dict:
-        v = state_to_vec(st).unsqueeze(0).to(self.device)
-        for _ in range(n):
-            v = self.step(v)
-        return vec_to_state(v[0].cpu())
+def copier_program(cfg):
+    # bank1[NET1 + ptr] = bank0[NET0 + ptr]; advance ptr
+    return [([(cfg.NET0, 1, 1)], -1, (cfg.WORK_BASE, 0)),  # tmp = NET0[ptr]
+            ([(cfg.WORK_BASE, 1, 0)], -1, (cfg.NET1, 1)),  # NET1[ptr] = tmp
+            ([], 0, (cfg.PTR_ADV, 0))]
 
 
 # =============================================================================
-# build
+# build + save (compiles U to a recurrent ternary matrix stack)
 # =============================================================================
 
-def build(save: bool = True):
-    print("Assembling the interpreter U from the verified cell library...")
+def build(cfg, save=True):
+    print(f"Interpreter U (S={cfg.S}, G={cfg.G}, F={cfg.F}, banks={cfg.banks}, "
+          f"record={cfg.R}b, acc={cfg.ACC}b)")
     t0 = time.perf_counter()
-    net, inputs, outputs = build_reflect_net()
+    net, inputs, outputs = build_net(cfg)
+    print(f"  {len(net.gates):,} threshold gates in {time.perf_counter() - t0:.1f}s")
+    if not save:
+        return net, inputs, outputs, None
+    t1 = time.perf_counter()
     layers, info = compile_net(net, inputs, outputs)
-    for W, B in layers:
-        assert set(torch.unique(W).tolist()) <= {-1, 0, 1}
-    print(f"  {len(net.gates)} threshold gates -> {info['layers']} ternary matrices "
-          f"(max width {info['max_width']}, {info['total_weights']:,} weights) "
-          f"in {time.perf_counter() - t0:.1f}s")
-    if save:
-        tensors = {f"matrix.layer{i:03d}.weight": W for i, (W, _) in enumerate(layers)}
-        tensors.update({f"matrix.layer{i:03d}.bias": B for i, (_, B) in enumerate(layers)})
-        tensors["manifest.signals"] = torch.tensor([float(S)])
-        tensors["manifest.gates"] = torch.tensor([float(G)])
-        tensors["manifest.state_bits"] = torch.tensor([float(STATE_BITS)])
-        tensors["manifest.layers"] = torch.tensor([float(info["layers"])])
-        tensors["manifest.version"] = torch.tensor([1.0])
-        meta = {"machine": "reflect", "weight_quantization": "ternary",
-                "config": json.dumps({"S": S, "A": A, "G": G, "F": F,
-                                      "record_bits": R, "net_base": NET_BASE,
-                                      "halt_signal": HALT_SIG})}
-        save_file(tensors, MODEL_PATH, metadata=meta)
-        print(f"  saved {MODEL_PATH} ({os.path.getsize(MODEL_PATH) / 1e6:.1f} MB)")
+    for Wt, _ in layers:
+        assert set(torch.unique(Wt).tolist()) <= {-1, 0, 1}
+    tensors = {f"matrix.layer{i:03d}.weight": Wt for i, (Wt, _) in enumerate(layers)}
+    tensors.update({f"matrix.layer{i:03d}.bias": B for i, (_, B) in enumerate(layers)})
+    for k, v in (("signals", cfg.S), ("gates", cfg.G), ("banks", cfg.banks),
+                 ("state_bits", cfg.STATE_BITS), ("layers", info["layers"]), ("version", 2)):
+        tensors[f"manifest.{k}"] = torch.tensor([float(v)])
+    meta = {"machine": "reflect", "weight_quantization": "ternary",
+            "config": json.dumps({"A": cfg.A, "S": cfg.S, "G": cfg.G, "F": cfg.F,
+                                  "BB": cfg.BB, "banks": cfg.banks, "record_bits": cfg.R,
+                                  "acc_bits": cfg.ACC, "net_base": cfg.NET0})}
+    save_file(tensors, MODEL_PATH, metadata=meta)
+    print(f"  compiled to {info['layers']} ternary matrices (max width "
+          f"{info['max_width']}, {info['total_weights']:,} weights) in "
+          f"{time.perf_counter() - t1:.1f}s; saved {MODEL_PATH} "
+          f"({os.path.getsize(MODEL_PATH) / 1e6:.1f} MB)")
     return net, inputs, outputs, layers
 
 
-# =============================================================================
-# demonstration netlists
-# =============================================================================
-
-def netlist_xor(a=0, b=1, out=4, t0=2, t1=3):
-    # XOR = AND( OR(a,b), NAND(a,b) ), all from the family's threshold cells.
-    return [((a, 1), (b, 1), -1, t0),        # OR   -> t0
-            ((a, -1), (b, -1), 1, t1),       # NAND -> t1
-            ((t0, 1), (t1, 1), -2, out)]     # AND  -> out
-
-
-def _bias_lsb_signal(gate_index: int) -> int:
-    # signal index of the bias LSB (b0) of gate `gate_index`
-    return NET_BASE + gate_index * R + OFF_BIAS + (BB - 1)
-
-
-def netlist_selfmod(a=0, b=1, out=2):
-    # g0 computes AND(a,b)->out (bias -2). g1 writes 1 into g0's bias LSB,
-    # turning bias -2 (AND) into -1 (OR): the program edits the weights that
-    # define g0, so the interpreted function becomes OR on the next sweep.
-    return [((a, 1), (b, 1), -2, out),                 # g0: AND now, OR after edit
-            ((0, 0), (0, 0), 0, _bias_lsb_signal(0))]  # g1: write 1 -> g0.bias LSB
-
-
 # =============================================================================
 # verify
 # =============================================================================
 
-def _rand_states(n, gen):
-    sig = (torch.rand(n, S, generator=gen) < 0.5).long()
-    gp = torch.randint(0, G, (n,), generator=gen)
-    return sig, gp
+def _load(cfg, netlist, bank=0):
+    sig = [0] * cfg.S
+    base = cfg.bank_base(bank)
+    sig[base:base + len(netlist)] = netlist
+    return sig
 
 
-def verify(refl: Reflect, net, inputs, outputs, device) -> bool:
+def verify(cfg, device):
     ok = True
+    net, inputs, outputs = build_net(cfg)
+    lev = Leveled(net, inputs, outputs, device=device)
+    R = Runner(cfg, lev)
 
-    # 1. exhaustive single-gate semantics: selected gate at gp=0, both inputs
-    # placed at fixed addresses, sweep the two ternary weights x both bias signs
-    # x all input assignments; U's write and out bit must match H(w0 v0 + w1 v1 + b).
-    print("[1/4] Exhaustive single-gate semantics "
-          "(all weights x biases x input assignments)")
-    bad = 0
-    total = 0
+    print("[1/6] Exhaustive single-gate semantics")
+    bad = total = 0
+    ra, rb, ro = cfg.WORK_BASE, cfg.WORK_BASE + 1, cfg.WORK_BASE + 2
     for w0 in (-1, 0, 1):
         for w1 in (-1, 0, 1):
-            for bias in range(-(1 << (BB - 1)), (1 << (BB - 1))):
-                nl = [((10, w0), (11, w1), bias, 20)]
+            for bias in range(-(1 << (cfg.BB - 1)), 1 << (cfg.BB - 1)):
+                nl = encode_netlist(cfg, [([(ra, w0, 0), (rb, w1, 0)], bias, (ro, 0))])
                 for va in (0, 1):
                     for vb in (0, 1):
-                        st = make_state([0] * S, gp=0, netlist=nl)
-                        st["sig"][10] = va
-                        st["sig"][11] = vb
-                        got = refl.run_steps(st, 1)
-                        exp = ref_step(st)
+                        sig = _load(cfg, nl); sig[ra], sig[rb] = va, vb
+                        st = {"sig": sig, "gp": 0, "halt": 0}
+                        g = R.step(st); e = ref_step(cfg, st)
                         total += 1
-                        if got != exp or got["sig"][20] != (1 if w0 * va + w1 * vb + bias >= 0 else 0):
+                        exp = 1 if w0 * va + w1 * vb + bias >= 0 else 0
+                        if {k: g[k] for k in ("sig", "gp", "halt")} != {k: e[k] for k in ("sig", "gp", "halt")} or g["sig"][ro] != exp:
                             bad += 1
-    print(f"  {'OK ' if bad == 0 else 'FAIL'} {total} gate configurations exact")
+    print(f"  {'OK ' if bad == 0 else 'FAIL'} {total} configurations exact")
     ok &= bad == 0
 
-    # 2. single step on random full states, plus halted fixed point
-    print("[2/4] Single step vs reference on random full states")
+    print("[2/6] Single step vs reference on random full states")
     gen = torch.Generator().manual_seed(0x5EED)
-    sig, gp = _rand_states(3000, gen)
+    N = 1500
+    sig = (torch.rand(N, cfg.S, generator=gen) < 0.5).long()
+    gpv = torch.randint(0, cfg.G, (N,), generator=gen)
     bad = 0
-    for i in range(sig.shape[0]):
-        st = {"sig": sig[i].tolist(), "gp": int(gp[i]), "halt": 0}
-        if refl.run_steps(st, 1) != ref_step(st):
+    for i in range(N):
+        st = {"sig": sig[i].tolist(), "gp": int(gpv[i]), "halt": 0}
+        g = R.step(st); e = ref_step(cfg, st)
+        if {k: g[k] for k in ("sig", "gp", "halt")} != {k: e[k] for k in ("sig", "gp", "halt")}:
             bad += 1
-    print(f"  {'OK ' if bad == 0 else 'FAIL'} 3,000 random states exact")
-    ok &= bad == 0
-    hbad = 0
-    for i in range(300):
-        st = {"sig": sig[i].tolist(), "gp": int(gp[i]), "halt": 1}
-        if refl.run_steps(st, 1) != st:
-            hbad += 1
-    print(f"  {'OK ' if hbad == 0 else 'FAIL'} 300 halted states are fixed points")
-    ok &= hbad == 0
-
-    # 3. interpret a composed XOR, and a self-modifying program, in lockstep
-    print("[3/4] Interpretation lockstep (composed XOR; self-rewriting program)")
-    xbad = 0
-    for a in (0, 1):
-        for b in (0, 1):
-            st = make_state([0] * S, gp=0, netlist=netlist_xor())
-            st["sig"][0], st["sig"][1] = a, b
-            r = dict(st)
-            for k in range(G):                     # one sweep
-                st2 = refl.run_steps(st, 1)
-                r = ref_step(r)
-                if st2 != r:
-                    xbad += 1
-                st = st2
-            if st["sig"][4] != (a ^ b):
-                xbad += 1
-    print(f"  {'OK ' if xbad == 0 else 'FAIL'} XOR interpreted for all inputs "
-          f"(U == reference every step; s4 == a^b)")
-    ok &= xbad == 0
-
-    smbad = 0
-    for a in (0, 1):
-        for b in (0, 1):
-            st = make_state([0] * S, gp=0, netlist=netlist_selfmod())
-            st["sig"][0], st["sig"][1] = a, b
-            r = dict(st)
-            trace = []
-            for k in range(2 * G):                 # two sweeps
-                st = refl.run_steps(st, 1)
-                r = ref_step(r)
-                if st != r:
-                    smbad += 1
-                if (k + 1) % G == 0:
-                    trace.append(st["sig"][2])
-            # tick 1 computed AND, tick 2 (after the edit) computed OR
-            if trace != [a & b, a | b]:
-                smbad += 1
-    print(f"  {'OK ' if smbad == 0 else 'FAIL'} self-modification: AND rewrites "
-          f"itself to OR mid-run (out = a&b then a|b), U == reference")
-    ok &= smbad == 0
-
-    # 4. gate graph == matrix form on random states
-    print("[4/4] Gate graph == matrix form")
-    gbad = 0
-    for i in range(400):
-        vals = {f"s{j}": int(sig[i, j]) for j in range(S)}
-        vals.update({f"gp{k}": to_bits(int(gp[i]), GPW)[k] for k in range(GPW)})
-        vals["halt"] = 0
-        gate_out = eval_net(net, inputs, outputs, vals)
-        v = torch.zeros(STATE_BITS)
-        for j in range(S):
-            v[j] = int(sig[i, j])
-        v[S:S + GPW] = torch.tensor(to_bits(int(gp[i]), GPW), dtype=torch.float32)
-        mat_out = refl.step(v.unsqueeze(0).to(device))[0].cpu().tolist()
-        if [int(round(x)) for x in mat_out] != gate_out:
-            gbad += 1
-    print(f"  {'OK ' if gbad == 0 else 'FAIL'} 400 random states: matrix step "
-          f"== gate-graph step, bit for bit")
-    ok &= gbad == 0
-
-    print("\nREFLECT (interpreter == reference; matrix == gate):", "PASS" if ok else "FAIL")
+    hbad = sum(1 for i in range(200)
+               if R.step({"sig": sig[i].tolist(), "gp": int(gpv[i]), "halt": 1})["sig"] != sig[i].tolist())
+    print(f"  {'OK ' if bad == 0 else 'FAIL'} {N} random states exact; "
+          f"{'OK ' if hbad == 0 else 'FAIL'} halted states are fixed points")
+    ok &= bad == 0 and hbad == 0
+
+    print("[3/6] Universality: interpret a family full-adder cell")
+    anet, an, bn, sums, cout = adder_net(1)
+    ia = {an[0]: cfg.WORK_BASE, bn[0]: cfg.WORK_BASE + 1}
+    rg, addr = compile_to_reflect(cfg, anet, ia, sums + [cout], cfg.WORK_BASE + 2)
+    nl = encode_netlist(cfg, rg)
+    abad = 0
+    for x in (0, 1):
+        for y in (0, 1):
+            sig = _load(cfg, nl)
+            sig[ia[an[0]]] = x; sig[ia[bn[0]]] = y
+            st = R.run({"sig": sig, "gp": 0, "halt": 0}, cfg.G * cfg.G)
+            s = st["sig"][addr[sums[0]]] | (st["sig"][addr[cout]] << 1)
+            if s != x + y:
+                abad += 1
+    print(f"  {'OK ' if abad == 0 else 'FAIL'} full adder computed bit-exact "
+          f"through the interpreter ({len(rg)} gates, compiled from the family's Net)")
+    ok &= abad == 0
+
+    print("[4/6] Order independence (adder gates stored in random order)")
+    obad = 0
+    for seed in range(4):
+        perm = list(range(len(rg)))
+        random.Random(seed + 1).shuffle(perm)
+        nls = encode_netlist(cfg, [rg[p] for p in perm])
+        for x in (0, 1):
+            for y in (0, 1):
+                sig = _load(cfg, nls)
+                sig[ia[an[0]]] = x; sig[ia[bn[0]]] = y
+                st = R.run({"sig": sig, "gp": 0, "halt": 0}, cfg.G * cfg.G)
+                s = st["sig"][addr[sums[0]]] | (st["sig"][addr[cout]] << 1)
+                if s != x + y:
+                    obad += 1
+    print(f"  {'OK ' if obad == 0 else 'FAIL'} adder correct under 4 random gate "
+          f"orders (relaxation reproduces combinational evaluation)")
+    ok &= obad == 0
+
+    print("[5/6] Self-reproduction (quine): program emits its own encoding")
+    nlq = encode_netlist(cfg, quine_program(cfg))
+    K = 48
+    st = {"sig": _load(cfg, nlq), "gp": 0, "halt": 0}
+    _, emits = R.run(st, cfg.G * K + cfg.G, collect=True)
+    good = emits[:K] == nlq[:K]
+    print(f"  {'OK ' if good else 'FAIL'} first {K} emitted bits == the program's "
+          f"own stored bits (streaming its description out the output device)")
+    ok &= good
+
+    print("[6/6] Metamorphosis: program fills the other bank and switches to it")
+    # (a) copier program fills bank1 with a copy of bank0
+    nlc = encode_netlist(cfg, copier_program(cfg))
+    st = {"sig": _load(cfg, nlc), "gp": 0, "halt": 0}
+    st = R.run(st, cfg.G * (cfg.G * cfg.R) + cfg.G)
+    filled = st["sig"][cfg.NET1:cfg.NET1 + cfg.G * cfg.R] == nlc
+    # (b) a program-set BANK flag switches the interpreter to a different machine
+    #     preinstalled in bank1 (the full adder), which then runs.
+    nl_switch = encode_netlist(cfg, [([], 0, (cfg.BANK_SIG, 0))])   # BANK = 1
+    sig = _load(cfg, nl_switch, bank=0)
+    sig[cfg.NET1:cfg.NET1 + len(nl)] = nl                          # bank1 = adder
+    st = {"sig": sig, "gp": 0, "halt": 0}
+    st = R.run(st, 1)                                              # gp0 sets BANK=1
+    st["gp"] = 0; st["sig"][cfg.WORK_BASE] = 1; st["sig"][cfg.WORK_BASE + 1] = 1
+    st = R.run(st, cfg.G * cfg.G)                                  # now running bank1
+    switched = (st["sig"][cfg.BANK_SIG] == 1
+                and (st["sig"][addr[sums[0]]] | (st["sig"][addr[cout]] << 1)) == 2)
+    print(f"  {'OK ' if filled else 'FAIL'} copier wrote bank0 into bank1; "
+          f"{'OK ' if switched else 'FAIL'} program set BANK and ran the bank-1 machine")
+    ok &= filled and switched
+
+    print("\nREFLECT v2 (universality, order, quine, metamorphosis):",
+          "PASS" if ok else "FAIL")
+    return ok
+
+
+# =============================================================================
+# analog: matrix == gate + noise / conductance-mismatch margins
+# =============================================================================
+
+def analog(cfg, device):
+    ok = True
+    net, inputs, outputs = build_net(cfg)
+    print("Compiling U to a recurrent ternary matrix stack...")
+    layers, info = compile_net(net, inputs, outputs)
+    print(f"  {info['layers']} matrices, max width {info['max_width']}, "
+          f"{info['total_weights']:,} weights")
+    Wm = [W.to(device=device, dtype=torch.float32) for W, _ in layers]
+    Bm = [B.to(device=device, dtype=torch.float32) for _, B in layers]
+    lev = Leveled(net, inputs, outputs, device=device)
+
+    def mstep(v, thresh=0.0, noise=0.0, gen=None, Wover=None):
+        for W, b in zip(Wover or Wm, Bm):
+            pre = v @ W.T + b
+            if noise:
+                pre = pre + torch.randn(pre.shape, generator=gen, device=v.device) * noise
+            v = (pre >= thresh).float()
+        return v
+
+    gen = torch.Generator().manual_seed(11)
+    ns = 300
+    V = torch.zeros(ns, cfg.STATE_BITS)
+    V[:, :cfg.S] = (torch.rand(ns, cfg.S, generator=gen) < 0.5).float()
+    gpv = torch.randint(0, cfg.G, (ns,), generator=gen)
+    for i in range(ns):
+        V[i, cfg.S:cfg.S + cfg.GPW] = torch.tensor(to_bits(int(gpv[i]), cfg.GPW), dtype=torch.float32)
+    V = V.to(device)
+    same = bool((mstep(V) == lev.step(V[:, :len(inputs)])).all())
+    print(f"  {'OK ' if same else 'FAIL'} matrix step == gate-graph step on {ns} random states")
+    ok &= same
+
+    m = float("inf"); v = V.clone()
+    for W, b in zip(Wm, Bm):
+        pre = v @ W.T + b
+        m = min(m, float((pre + 0.5).abs().min()))
+        v = (pre >= 0).float()
+    print(f"  measured minimum |pre-activation - (-0.5)|: {m:.3f} (guarantee 0.5)")
+    ok &= abs(m - 0.5) < 1e-6
+
+    base = state_to_vec(cfg, {"sig": _load(cfg, encode_netlist(cfg, quine_program(cfg))),
+                              "gp": 0, "halt": 0}).unsqueeze(0).to(device)
+
+    def sweep(noise=0.0, gen=None, Wover=None):
+        v = base.clone()
+        for _ in range(cfg.G):
+            v = mstep(v, thresh=-0.5, noise=noise, gen=gen, Wover=Wover)
+        return v
+
+    ref = sweep()
+    print("  read noise per MVM (20 trials, full sweep bit-exact):")
+    for sigma in (0.05, 0.10, 0.20, 0.40):
+        good = sum(int(bool((sweep(noise=sigma, gen=torch.Generator(device=device).manual_seed(t)) == ref).all()))
+                   for t in range(20))
+        print(f"    sigma={sigma:.2f}: {good}/20 bit-exact")
+        if sigma <= 0.05 and good != 20:      # deep within the 0.5 margin
+            ok = False
+
+    print("  conductance mismatch (8 instances, full sweep bit-exact):")
+    for sg in (0.05, 0.20):
+        good = 0
+        for t in range(8):
+            gg = torch.Generator().manual_seed(7 + t)
+            Wp = [W + (torch.randn(W.shape, generator=gg) * sg).to(device) * (W != 0) for W in Wm]
+            good += int(bool((sweep(Wover=Wp) == ref).all()))
+        print(f"    sigma_G={sg:.2f}: {good}/8 bit-exact")
+        if sg <= 0.05 and good != 8:
+            ok = False
+
+    print("ANALOG (matrix == gate; bit-exact within the 0.5 margin):", "PASS" if ok else "FAIL")
     return ok
 
 
-def main() -> int:
-    ap = argparse.ArgumentParser(description="neural_reflect builder / verifier")
-    ap.add_argument("cmd", choices=["build", "verify", "all"])
+def main():
+    ap = argparse.ArgumentParser(description="neural_reflect v2")
+    ap.add_argument("cmd", choices=["build", "verify", "analog", "all"])
     ap.add_argument("--device", default="cuda" if torch.cuda.is_available() else "cpu")
     args = ap.parse_args()
-    net, inputs, outputs, layers = build(save=args.cmd in ("build", "all"))
+    cfg = Cfg()
     rc = 0
+    if args.cmd in ("build", "all"):
+        build(cfg, save=True)
     if args.cmd in ("verify", "all"):
-        refl = Reflect(layers, device=args.device)
-        rc = 0 if verify(refl, net, inputs, outputs, args.device) else 1
+        rc |= 0 if verify(cfg, args.device) else 1
+    if args.cmd in ("analog", "all"):
+        rc |= 0 if analog(cfg, args.device) else 1
     return rc
 
 

variants/neural_reflect.safetensors

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+size 157772226