neural_reflect: host a complete SUBLEQ machine (32-byte memory, fetch-execute loop) inside the interpreter, its memory accessed through indexed addressing

README.md

@@ -536,6 +536,15 @@ regardless of gate order, so U reproduces the family's combinational evaluation.
   addressed span stays small as the gate count grows, so U holds a circuit far
   larger than its wire space. The 156-gate SUBLEQ datapath is interpreted with
   a 272-signal addressed span.
+- **A complete machine hosted inside the interpreter.** A stored microprogram
+  holds a whole SUBLEQ machine: its 32-byte memory lives in signals, and the
+  interpreter's own indexed addressing (set `PTR` to a byte address, read or
+  write the eight bit-planes) serves as the machine's memory-access hardware.
+  266 stored gates fetch three operand bytes, read two data bytes, subtract,
+  write the result back, and branch, one instruction per sweep; the memory and
+  program counter carry across sweeps. One instruction is exact over 4,096
+  random `(memory, PC)` states, and a stored countdown program runs a loop to a
+  halt with its final memory matching the reference emulator.
 - **Self-reference.** When the netlist is address-reachable, a gate can write
   into it: a stored gate edits the weights that define it. The index flag adds
   `PTR`, so a fixed-size program walks an address range; one such program
@@ -554,13 +563,15 @@ Verified against a reference interpreter: exhaustive single-gate semantics
 (every ternary weight pair, bias, and input assignment), single-step agreement
 on random full states with halted states as fixed points, bit-exact
 interpretation of the ripple-carry adder and the SUBLEQ datapath (all 65,536
-pairs) under sorted and shuffled gate order, the self-reproduction, self-rewrite,
-and bank-switch programs, the counter holding state through feedback, and
-equality of the compiled matrix form with the gate graph, the 0.5 comparator
-margin measured under read noise and conductance mismatch.
+pairs) under sorted and shuffled gate order, one hosted SUBLEQ instruction over
+4,096 random memory states and a stored program run to a halt, the
+self-reproduction, self-rewrite, and bank-switch programs, the counter holding
+state through feedback, and equality of the compiled matrix form with the gate
+graph, the 0.5 comparator margin measured under read noise and conductance
+mismatch.
 
 ```bash
-python src/reflect.py verify     # universality, order independence, quine, metamorphosis
+python src/reflect.py verify     # universality, a hosted SUBLEQ machine, quine, metamorphosis
 python src/reflect.py analog     # matrix == gate + noise / conductance-mismatch margin
 ```
 

src/reflect.py

@@ -457,18 +457,25 @@ def record_bit(cfg, bank, gate, off):
     return cfg.bank_base(bank) + gate * cfg.R + off
 
 
-def compile_to_reflect(cfg, net, in_addr, out_names, work_start):
+def compile_to_reflect(cfg, net, in_addr, out_names, work_start, fixed=None):
+    """Lay a <=2-input acyclic Net out as reflect gate records in topological
+    order. Primary inputs sit at in_addr; gate outputs get fresh work signals
+    from work_start up, except those named in `fixed` (gate -> signal), which
+    are placed at the given signal. Returns (records, address map, next work)."""
+    fixed = fixed or {}
     addr = dict(in_addr)
     w = work_start
     rgates = []
     for g in topo(net):
         ins, bias = net.gates[g]
         assert len(ins) <= cfg.F
-        addr[g] = w; w += 1
+        if g in fixed:
+            addr[g] = fixed[g]
+        else:
+            addr[g] = w; w += 1
         slots = [(addr[s], wt, 0) for s, wt in ins]
         rgates.append((slots, bias, (addr[g], 0)))
-    assert len(rgates) <= cfg.G, f"{len(rgates)} gates > bank {cfg.G}"
-    return rgates, addr
+    return rgates, addr, w
 
 
 def adder_net(bits):
@@ -614,7 +621,7 @@ def verify(cfg, device):
     print("[3/7] Universality: interpret a family full-adder cell")
     anet, an, bn, sums, cout = adder_net(1)
     ia = {an[0]: cfg.WORK_BASE, bn[0]: cfg.WORK_BASE + 1}
-    rg, addr = compile_to_reflect(cfg, anet, ia, sums + [cout], cfg.WORK_BASE + 2)
+    rg, addr, _ = compile_to_reflect(cfg,anet, ia, sums + [cout], cfg.WORK_BASE + 2)
     nl = encode_netlist(cfg, rg)
     abad = 0
     for x in (0, 1):
@@ -727,7 +734,7 @@ def verify_scale(device):
     for i in range(W):
         ia[an[i]] = cfg.WORK_BASE + i
         ia[bn[i]] = cfg.WORK_BASE + W + i
-    rg, addr = compile_to_reflect(cfg, anet, ia, sums + [cout], cfg.WORK_BASE + 2 * W)
+    rg, addr, _ = compile_to_reflect(cfg,anet, ia, sums + [cout], cfg.WORK_BASE + 2 * W)
     nl = encode_netlist(cfg, rg)
     print(f"  compiled adder netlist: {len(rg)} gates")
 
@@ -784,7 +791,7 @@ def verify_subleq(device):
         in_addr[b[k]] = base + 8 + k
         in_addr[pc[k]] = base + 16 + k
         in_addr[c[k]] = base + 24 + k
-    rg, addr = compile_to_reflect(cfg, net, in_addr, r + [leq] + pcm, base + 32)
+    rg, addr, _ = compile_to_reflect(cfg,net, in_addr, r + [leq] + pcm, base + 32)
     nl = encode_netlist(cfg, rg)
     print(f"  compiled datapath netlist: {len(rg)} gates; interpreting all "
           f"65,536 (M[A], M[B]) pairs")
@@ -823,6 +830,189 @@ def verify_subleq(device):
     return good
 
 
+# =============================================================================
+# a complete stored machine (SUBLEQ, 32-byte memory) hosted in the interpreter
+# =============================================================================
+
+def _subtract_net():
+    net = Net()
+    x = [f"x{k}" for k in range(8)]; y = [f"y{k}" for k in range(8)]
+    nx = [net.NOT(f"nx{k}", x[k]) for k in range(8)]
+    carry = "#1"; r = []
+    for k in range(8):
+        s_, carry = net.FA(f"sb{k}", y[k], nx[k], carry)
+        r.append(s_)
+    ot = r[0]
+    for k in range(1, 8):
+        ot = net.OR(f"zo{k}", [ot, r[k]])
+    leq = net.OR("leq", [r[7], net.NOT("z", ot)])
+    return net, x, y, r, leq
+
+
+def _incr_net():                          # 5-bit address arithmetic (mod 32)
+    net = Net()
+    pc = [f"p{k}" for k in range(5)]
+
+    def addc(tag, cst):
+        carry = "#0"; out = []
+        for k in range(5):
+            s_, carry = net.FA(f"{tag}{k}", pc[k], "#1" if (cst >> k) & 1 else "#0", carry)
+            out.append(s_)
+        return out
+    return net, pc, addc("i1", 1), addc("i2", 2), addc("i3", 3)
+
+
+def _branch_net():
+    net = Net()
+    c = [f"c{k}" for k in range(5)]; q = [f"q{k}" for k in range(5)]
+    npc = [net.MUX(f"nb{k}", "leq", c[k], q[k]) for k in range(5)]
+    halt = npc[0]
+    for k in range(1, 5):
+        halt = net.AND(f"hb{k}", [halt, npc[k]])
+    return net, c, q, npc, halt
+
+
+MEMB = 32
+MEM = 416
+
+
+def build_subleq_machine(cfg):
+    """A stored microprogram implementing one SUBLEQ instruction per sweep over
+    a 32-byte memory held in signals [MEM, MEM+8*32). Data-dependent memory
+    access is the interpreter's own indexed addressing: set PTR to a byte
+    address, then read/write the eight bit-planes at MEM + b*32 + PTR."""
+    WB = cfg.WORK_BASE
+    reg = lambda o: [WB + o + k for k in range(8)]
+    PC, A_, B_, C_ = reg(0), reg(8), reg(16), reg(24)
+    X, Y, Rr = reg(32), reg(40), reg(48)
+    P1, P2, P3, NPC = reg(56), reg(64), reg(72), reg(80)
+    leqs = WB + 88
+    workc = WB + 96
+
+    def zero_hi():                                     # PTR high bits = 0 (once)
+        return [([], -1, (cfg.PTR_BASE + (cfg.A - 1 - k), 0)) for k in range(5, cfg.A)]
+
+    def ptr_set(r8):                                   # PTR low 5 = addr; high stays 0
+        return [([(r8[k], 1, 0)], -1, (cfg.PTR_BASE + (cfg.A - 1 - k), 0)) for k in range(5)]
+
+    def read_byte(dst):
+        return [([(MEM + b * MEMB, 1, 1)], -1, (dst[b], 0)) for b in range(8)]
+
+    def write_byte(src):
+        return [([(src[b], 1, 0)], -1, (MEM + b * MEMB, 1)) for b in range(8)]
+
+    inet, pin, p1, p2, p3 = _incr_net()
+    irec, _, workc = compile_to_reflect(cfg, inet, {pin[k]: PC[k] for k in range(5)}, [],
+                                        workc, fixed={**{p1[k]: P1[k] for k in range(5)},
+                                                       **{p2[k]: P2[k] for k in range(5)},
+                                                       **{p3[k]: P3[k] for k in range(5)}})
+    snet, sx, sy, sr, sleq = _subtract_net()
+    srec, _, workc = compile_to_reflect(
+        cfg, snet, {**{sx[k]: X[k] for k in range(8)}, **{sy[k]: Y[k] for k in range(8)}},
+        [], workc, fixed={**{sr[k]: Rr[k] for k in range(8)}, sleq: leqs})
+    bnet, bc, bq, bnpc, bhalt = _branch_net()
+    brec, _, workc = compile_to_reflect(
+        cfg, bnet, {**{bc[k]: C_[k] for k in range(5)}, **{bq[k]: P3[k] for k in range(5)}, "leq": leqs},
+        [], workc, fixed={**{bnpc[k]: NPC[k] for k in range(5)}, bhalt: cfg.HALT_SIG})
+    assert workc < MEM, "compiled internals collide with memory"
+
+    prog = zero_hi() + list(irec)
+    prog += ptr_set(PC) + read_byte(A_)
+    prog += ptr_set(P1) + read_byte(B_)
+    prog += ptr_set(P2) + read_byte(C_)
+    prog += ptr_set(A_) + read_byte(X)
+    prog += ptr_set(B_) + read_byte(Y)
+    prog += srec
+    prog += ptr_set(B_) + write_byte(Rr)
+    prog += brec
+    prog += [([(NPC[k], 1, 0)], -1, (PC[k], 0)) for k in range(5)]     # PC = NPC (low 5)
+    return prog, {"PC": PC}
+
+
+def subleq32_step(mem, pc):
+    A, B, C = mem[pc], mem[(pc + 1) & 31], mem[(pc + 2) & 31]
+    x, y = mem[A & 31], mem[B & 31]
+    r = (y - x) & 0xFF
+    m2 = list(mem); m2[B & 31] = r
+    npc = (C & 31) if (r == 0 or r >= 128) else (pc + 3) & 31
+    return m2, npc
+
+
+def verify_hosted(device):
+    cfg = Cfg(A=14, G=296, banks=1, self_mod=False)
+    prog, lay = build_subleq_machine(cfg)
+    print(f"\nHosted machine: SUBLEQ with a 32-byte memory, one instruction per "
+          f"sweep\n  microprogram: {len(prog)} gates; interpreter U:", end=" ")
+    inet, ii, io = build_net(cfg)
+    print(f"{len(inet.gates):,} gates (addressed span {cfg.span})")
+    lev = Leveled(inet, ii, io, device=device)
+    nl = encode_netlist(cfg, prog)
+    sig0 = [0] * cfg.S
+    sig0[cfg.NET0:cfg.NET0 + len(nl)] = nl
+    base = state_to_vec(cfg, {"sig": sig0, "gp": 0, "halt": 0}).to(device)
+    PC = lay["PC"]
+
+    def set_mem(V, mems):
+        for i in range(32):
+            for b in range(8):
+                V[:, MEM + b * MEMB + i] = ((mems[:, i] >> b) & 1).float().to(device)
+
+    def get_mem(Vc):
+        return sum(Vc[:, MEM + b * MEMB: MEM + b * MEMB + 32].long() << b for b in range(8))
+
+    # one instruction vs reference over random (memory, PC) states, batched
+    gen = torch.Generator().manual_seed(1)
+    B = 4096
+    mems = torch.randint(0, 256, (B, 32), generator=gen)
+    pcs = torch.randint(0, 30, (B,), generator=gen)          # avoid the halt cell
+    V = base.unsqueeze(0).repeat(B, 1)
+    set_mem(V, mems)
+    for k in range(8):
+        V[:, PC[k]] = ((pcs >> k) & 1).float().to(device)
+    for _ in range(cfg.G):
+        V = lev.step(V)
+    Vc = V.cpu()
+    got_mem = get_mem(Vc)
+    got_pc = sum(Vc[:, PC[k]].long() << k for k in range(8)) & 31
+    exp_mem = torch.zeros_like(got_mem); exp_pc = torch.zeros_like(got_pc)
+    for i in range(B):
+        m2, np_ = subleq32_step(mems[i].tolist(), int(pcs[i]))
+        exp_mem[i] = torch.tensor(m2); exp_pc[i] = np_
+    mask = exp_pc != 31                                # halting instr freezes PC
+    ok1 = bool((got_mem == exp_mem).all()) and bool((got_pc[mask] == exp_pc[mask]).all())
+    print(f"  {'OK ' if ok1 else 'FAIL'} one instruction exact for {B} random "
+          f"(memory, PC) states (result, writeback, and branch)")
+
+    # run a stored program to a halt: count M[21] (=3) down to 0 through a loop
+    prog_mem = [0] * 32
+    prog_mem[0:3] = [20, 21, 6]         # loop:  subleq one, n, done
+    prog_mem[3:6] = [22, 22, 0]         #        subleq z, z, 0   (jump back to loop)
+    prog_mem[6:9] = [31, 31, 31]        # done:  branch to the halt cell
+    prog_mem[20], prog_mem[21], prog_mem[22] = 1, 3, 0
+    V = base.unsqueeze(0).repeat(1, 1)
+    set_mem(V, torch.tensor(prog_mem).unsqueeze(0))
+    halted = False
+    steps = 0
+    for _ in range(24):
+        for _ in range(cfg.G):
+            V = lev.step(V)
+        steps += 1
+        if int(V[0, cfg.S + cfg.GPW]) == 1:            # interpreter halt latched
+            halted = True
+            break
+    got = get_mem(V.cpu())[0].tolist()
+    ref_mem, ref_pc = list(prog_mem), 0
+    while ref_pc != 31:
+        ref_mem, ref_pc = subleq32_step(ref_mem, ref_pc)
+    ok2 = halted and got == ref_mem and got[21] == 0
+    print(f"  {'OK ' if ok2 else 'FAIL'} stored countdown program ran to a halt in "
+          f"{steps} instructions; final memory matches the emulator (M[21] = {got[21]})")
+
+    good = ok1 and ok2
+    print("HOSTED MACHINE:", "PASS" if good else "FAIL")
+    return good
+
+
 # =============================================================================
 # analog: matrix == gate + noise / conductance-mismatch margins
 # =============================================================================
@@ -912,6 +1102,7 @@ def main():
         rc |= 0 if verify(cfg, args.device) else 1
         rc |= 0 if verify_scale(args.device) else 1
         rc |= 0 if verify_subleq(args.device) else 1
+        rc |= 0 if verify_hosted(args.device) else 1
     if args.cmd in ("analog", "all"):
         rc |= 0 if analog(cfg, args.device) else 1
     return rc