neural_reflect: interpret the SUBLEQ datapath from stored gates; index-read scaling, a compiler from family nets, self-reproduction, self-rewrite, and sequential-state programs

README.md

@@ -527,16 +527,24 @@ out = H( w0·sig[eff(a0,i0)] + w1·sig[eff(a1,i1)] + bias ) ;   sig[eff(oa,oidx)
 regardless of gate order, so U reproduces the family's combinational evaluation.
 
 - **Universality.** `compile_to_reflect` maps any ≤2-input family `Net` to a
-  stored netlist. The family's own full-adder cell, compiled this way, is
-  interpreted bit-exact, and stays correct with its gates stored in arbitrary
-  order.
-- **Self-reference.** Addresses index the whole signal array, so a gate can
-  write into the netlist region: a stored gate edits the weights that define
-  it. The index flag adds `PTR`, so a fixed-size program walks an address
-  range; one such program streams the netlist's own bytes to the output
-  device, emitting its own description. Another copies its bank into the
-  second bank and sets the `BANK` flag, so the interpreter runs a different
-  resident machine without an external load step.
+  stored netlist. Compiled this way, a ripple-carry adder and the SUBLEQ
+  machine's datapath, the family's own subtract-and-branch logic, run through
+  the interpreter bit-exact; the datapath is checked against the reference over
+  all 65,536 `(M[A], M[B])` operand pairs. Results do not depend on the order
+  the gates are stored in.
+- **Scale.** When the netlist is read by gate index rather than by address, the
+  addressed span stays small as the gate count grows, so U holds a circuit far
+  larger than its wire space. The 156-gate SUBLEQ datapath is interpreted with
+  a 272-signal addressed span.
+- **Self-reference.** When the netlist is address-reachable, a gate can write
+  into it: a stored gate edits the weights that define it. The index flag adds
+  `PTR`, so a fixed-size program walks an address range; one such program
+  streams the netlist's own bytes to the output device, emitting its own
+  description. A single program computes `a & b` and then edits its own gate so
+  the next sweep computes `a & ~b`, and a program-set `BANK` flag switches the
+  interpreter to a different resident machine without an external load step.
+- **State.** A stored netlist with feedback holds state across sweeps: a 2-bit
+  counter advances `0, 1, 2, 3, 0` as U is iterated.
 - **Physical reading.** One recurrence is one matrix-vector product followed by
   a threshold; each write is one bit of the state. On a memristive crossbar
   that bit is a conductance, so a program editing the netlist region is the
@@ -545,10 +553,11 @@ regardless of gate order, so U reproduces the family's combinational evaluation.
 Verified against a reference interpreter: exhaustive single-gate semantics
 (every ternary weight pair, bias, and input assignment), single-step agreement
 on random full states with halted states as fixed points, bit-exact
-interpretation of the full-adder cell under sorted and shuffled gate order, the
-self-reproduction and bank-replacement programs, and equality of the compiled
-matrix form with the gate graph, the 0.5 comparator margin measured under read
-noise and conductance mismatch.
+interpretation of the ripple-carry adder and the SUBLEQ datapath (all 65,536
+pairs) under sorted and shuffled gate order, the self-reproduction, self-rewrite,
+and bank-switch programs, the counter holding state through feedback, and
+equality of the compiled matrix form with the gate graph, the 0.5 comparator
+margin measured under read noise and conductance mismatch.
 
 ```bash
 python src/reflect.py verify     # universality, order independence, quine, metamorphosis

src/reflect.py

@@ -83,13 +83,16 @@ class Cfg:
     F: int = 2
     BB: int = 4
     banks: int = 2
+    self_mod: bool = True     # True: netlist is address-reachable (editable);
+                              # False: netlist read only by gate index -> the
+                              # addressed span stays small as G grows.
 
     def __post_init__(self):
         self.S = 1 << self.A
         self.SLOT = self.A + 3
         self.R = self.F * self.SLOT + self.BB + (self.A + 1)
-        span = self.F + (1 << (self.BB - 1))
-        self.ACC = int(math.ceil(math.log2(span + 1))) + 2
+        rng = self.F + (1 << (self.BB - 1))
+        self.ACC = int(math.ceil(math.log2(rng + 1))) + 2
         self.PTR_BASE = 0
         self.OUT_DATA = self.A
         self.OUT_STROBE = self.A + 1
@@ -100,6 +103,7 @@ class Cfg:
         self.WORK_BASE = self.A + 6
         self.NET0 = self.S - self.banks * self.G * self.R
         self.NET1 = self.NET0 + self.G * self.R
+        self.span = self.S if self.self_mod else self.NET0   # indirect coverage
         self.GPW = max(1, (self.G - 1).bit_length())
         self.STATE_BITS = self.S + self.GPW + 1
         assert self.NET0 >= self.WORK_BASE + 16, "too little data room; raise A"
@@ -201,13 +205,15 @@ def ref_gate(cfg, st):
     acc = 0
     for j in range(cfg.F):
         b = slot_off(cfg, j)
-        acc += wv(rec[b + cfg.A:b + cfg.A + 2]) * sig[eff(from_bits(rec[b:b + cfg.A]), rec[b + cfg.A + 2])]
+        e = eff(from_bits(rec[b:b + cfg.A]), rec[b + cfg.A + 2])
+        acc += wv(rec[b + cfg.A:b + cfg.A + 2]) * (sig[e] if e < cfg.span else 0)
     bo, oo = field_off(cfg)
     acc += signed(rec[bo:bo + cfg.BB])
     out = 1 if acc >= 0 else 0
     dst = eff(from_bits(rec[oo:oo + cfg.A]), rec[oo + cfg.A])
     h = sig[cfg.HALT_SIG]
-    sig[dst] = out
+    if dst < cfg.span:
+        sig[dst] = out
     ngp = 0 if gp == cfg.G - 1 else gp + 1
     return sig, ngp, (1 if (halt or h) else 0)
 
@@ -255,7 +261,7 @@ def build_net(cfg):
 
     def read(addrbits, tag):
         return net.OR(f"rd{tag}", [net.AND(f"rd{tag}a{s}", [net.DECODE(f"rd{tag}oh{s}", addrbits, s), sig[s]])
-                                   for s in range(cfg.S)])
+                                   for s in range(cfg.span)])
 
     contribs = []
     for j in range(cfg.F):
@@ -295,8 +301,11 @@ def build_net(cfg):
     oea = eff_addr(recbit[oo:oo + cfg.A], recbit[oo + cfg.A], "w")
     nsig = []
     for s in range(cfg.S):
-        sel = net.AND(f"wrsel{s}", [net.DECODE(f"wroh{s}", oea, s), nhalt])
-        nsig.append(net.MUX(f"nsig{s}", sel, out, sig[s]))
+        if s < cfg.span:              # only the addressed span is writable
+            sel = net.AND(f"wrsel{s}", [net.DECODE(f"wroh{s}", oea, s), nhalt])
+            nsig.append(net.MUX(f"nsig{s}", sel, out, sig[s]))
+        else:                         # netlist (index-read only) passes through
+            nsig.append(sig[s])
 
     gp_lsb = [gp[cfg.GPW - 1 - k] for k in range(cfg.GPW)]
     inc, c = [], "#1"
@@ -435,6 +444,19 @@ def topo(net):
     return order
 
 
+def eval_family_net(net, input_vals):
+    """Evaluate a matrix8.Net directly (the family's own gate semantics)."""
+    v = dict(input_vals); v["#0"], v["#1"] = 0, 1
+    for g in topo(net):
+        ins, b = net.gates[g]
+        v[g] = 1 if b + sum(w * v[s] for s, w in ins) >= 0 else 0
+    return v
+
+
+def record_bit(cfg, bank, gate, off):
+    return cfg.bank_base(bank) + gate * cfg.R + off
+
+
 def compile_to_reflect(cfg, net, in_addr, out_names, work_start):
     addr = dict(in_addr)
     w = work_start
@@ -462,6 +484,36 @@ def adder_net(bits):
     return net, a, b, sums, carry
 
 
+def subleq_datapath_net():
+    """The SUBLEQ machine's datapath as <=2-input threshold gates: result =
+    M[B] - M[A], the branch decision leq = (result <= 0), and next PC =
+    leq ? C : PC + 3. All inputs LSB-first. (This is the combinational core the
+    family verifies exhaustively; the 256-byte packed memory is not included.)"""
+    net = Net()
+    a = [f"a{k}" for k in range(8)]
+    b = [f"b{k}" for k in range(8)]
+    pc = [f"pc{k}" for k in range(8)]
+    c = [f"c{k}" for k in range(8)]
+    nota = [net.NOT(f"nota{k}", a[k]) for k in range(8)]
+    carry = "#1"                                     # two's-complement subtract
+    r = []
+    for k in range(8):
+        s_, carry = net.FA(f"sub{k}", b[k], nota[k], carry)
+        r.append(s_)
+    ortree = r[0]                                    # NOR-8 as an OR-tree + NOT
+    for k in range(1, 8):
+        ortree = net.OR(f"zor{k}", [ortree, r[k]])
+    zero = net.NOT("zero", ortree)
+    leq = net.OR("leq", [r[7], zero])                # sign OR zero
+    carry = "#0"
+    p3 = []
+    for k in range(8):
+        s_, carry = net.FA(f"pci{k}", pc[k], "#1" if k in (0, 1) else "#0", carry)
+        p3.append(s_)
+    pcm = [net.MUX(f"pcm{k}", leq, c[k], p3[k]) for k in range(8)]
+    return net, a, b, pc, c, r, leq, pcm
+
+
 # =============================================================================
 # programs (stored netlists) for the reflective demos
 # =============================================================================
@@ -473,13 +525,6 @@ def quine_program(cfg):
             ([], 0, (cfg.PTR_ADV, 0))]                     # PTR_ADV = 1
 
 
-def copier_program(cfg):
-    # bank1[NET1 + ptr] = bank0[NET0 + ptr]; advance ptr
-    return [([(cfg.NET0, 1, 1)], -1, (cfg.WORK_BASE, 0)),  # tmp = NET0[ptr]
-            ([(cfg.WORK_BASE, 1, 0)], -1, (cfg.NET1, 1)),  # NET1[ptr] = tmp
-            ([], 0, (cfg.PTR_ADV, 0))]
-
-
 # =============================================================================
 # build + save (compiles U to a recurrent ternary matrix stack)
 # =============================================================================
@@ -530,7 +575,7 @@ def verify(cfg, device):
     lev = Leveled(net, inputs, outputs, device=device)
     R = Runner(cfg, lev)
 
-    print("[1/6] Exhaustive single-gate semantics")
+    print("[1/7] Exhaustive single-gate semantics")
     bad = total = 0
     ra, rb, ro = cfg.WORK_BASE, cfg.WORK_BASE + 1, cfg.WORK_BASE + 2
     for w0 in (-1, 0, 1):
@@ -549,7 +594,7 @@ def verify(cfg, device):
     print(f"  {'OK ' if bad == 0 else 'FAIL'} {total} configurations exact")
     ok &= bad == 0
 
-    print("[2/6] Single step vs reference on random full states")
+    print("[2/7] Single step vs reference on random full states")
     gen = torch.Generator().manual_seed(0x5EED)
     N = 1500
     sig = (torch.rand(N, cfg.S, generator=gen) < 0.5).long()
@@ -566,7 +611,7 @@ def verify(cfg, device):
           f"{'OK ' if hbad == 0 else 'FAIL'} halted states are fixed points")
     ok &= bad == 0 and hbad == 0
 
-    print("[3/6] Universality: interpret a family full-adder cell")
+    print("[3/7] Universality: interpret a family full-adder cell")
     anet, an, bn, sums, cout = adder_net(1)
     ia = {an[0]: cfg.WORK_BASE, bn[0]: cfg.WORK_BASE + 1}
     rg, addr = compile_to_reflect(cfg, anet, ia, sums + [cout], cfg.WORK_BASE + 2)
@@ -577,14 +622,16 @@ def verify(cfg, device):
             sig = _load(cfg, nl)
             sig[ia[an[0]]] = x; sig[ia[bn[0]]] = y
             st = R.run({"sig": sig, "gp": 0, "halt": 0}, cfg.G * cfg.G)
-            s = st["sig"][addr[sums[0]]] | (st["sig"][addr[cout]] << 1)
-            if s != x + y:
+            fam = eval_family_net(anet, {an[0]: x, bn[0]: y})
+            got = {g: st["sig"][addr[g]] for g in [sums[0], cout]}
+            s = got[sums[0]] | (got[cout] << 1)
+            if s != x + y or got[sums[0]] != fam[sums[0]] or got[cout] != fam[cout]:
                 abad += 1
-    print(f"  {'OK ' if abad == 0 else 'FAIL'} full adder computed bit-exact "
-          f"through the interpreter ({len(rg)} gates, compiled from the family's Net)")
+    print(f"  {'OK ' if abad == 0 else 'FAIL'} full adder ({len(rg)} gates, compiled "
+          f"from the family's Net) matches arithmetic and the family's own evaluator")
     ok &= abad == 0
 
-    print("[4/6] Order independence (adder gates stored in random order)")
+    print("[4/7] Order independence (adder gates stored in random order)")
     obad = 0
     for seed in range(4):
         perm = list(range(len(rg)))
@@ -602,42 +649,180 @@ def verify(cfg, device):
           f"orders (relaxation reproduces combinational evaluation)")
     ok &= obad == 0
 
-    print("[5/6] Self-reproduction (quine): program emits its own encoding")
+    print("[5/7] Self-reproduction (quine): program emits its whole encoding")
     nlq = encode_netlist(cfg, quine_program(cfg))
-    K = 48
+    K = len(nlq)
     st = {"sig": _load(cfg, nlq), "gp": 0, "halt": 0}
     _, emits = R.run(st, cfg.G * K + cfg.G, collect=True)
-    good = emits[:K] == nlq[:K]
-    print(f"  {'OK ' if good else 'FAIL'} first {K} emitted bits == the program's "
-          f"own stored bits (streaming its description out the output device)")
+    good = emits[:K] == nlq
+    print(f"  {'OK ' if good else 'FAIL'} all {K} emitted bits == the program's own "
+          f"stored encoding (streaming its full description out the output device)")
     ok &= good
 
-    print("[6/6] Metamorphosis: program fills the other bank and switches to it")
-    # (a) copier program fills bank1 with a copy of bank0
-    nlc = encode_netlist(cfg, copier_program(cfg))
-    st = {"sig": _load(cfg, nlc), "gp": 0, "halt": 0}
-    st = R.run(st, cfg.G * (cfg.G * cfg.R) + cfg.G)
-    filled = st["sig"][cfg.NET1:cfg.NET1 + cfg.G * cfg.R] == nlc
-    # (b) a program-set BANK flag switches the interpreter to a different machine
-    #     preinstalled in bank1 (the full adder), which then runs.
-    nl_switch = encode_netlist(cfg, [([], 0, (cfg.BANK_SIG, 0))])   # BANK = 1
-    sig = _load(cfg, nl_switch, bank=0)
-    sig[cfg.NET1:cfg.NET1 + len(nl)] = nl                          # bank1 = adder
-    st = {"sig": sig, "gp": 0, "halt": 0}
-    st = R.run(st, 1)                                              # gp0 sets BANK=1
-    st["gp"] = 0; st["sig"][cfg.WORK_BASE] = 1; st["sig"][cfg.WORK_BASE + 1] = 1
-    st = R.run(st, cfg.G * cfg.G)                                  # now running bank1
-    switched = (st["sig"][cfg.BANK_SIG] == 1
-                and (st["sig"][addr[sums[0]]] | (st["sig"][addr[cout]] << 1)) == 2)
-    print(f"  {'OK ' if filled else 'FAIL'} copier wrote bank0 into bank1; "
-          f"{'OK ' if switched else 'FAIL'} program set BANK and ran the bank-1 machine")
-    ok &= filled and switched
-
-    print("\nREFLECT v2 (universality, order, quine, metamorphosis):",
+    print("[6/7] Metamorphosis: a program rewrites its own function, and bank-switches")
+    IA, IB, OUT = cfg.WORK_BASE, cfg.WORK_BASE + 1, cfg.WORK_BASE + 2
+    w1hi = slot_off(cfg, 1) + cfg.A
+    bo, _ = field_off(cfg)
+    prog = [([(IA, 1, 0), (IB, 1, 0)], -2, (OUT, 0)),                 # AND(a, b)
+            ([], 0, (record_bit(cfg, 0, 0, w1hi), 0)),                # slot1 weight hi = 1
+            ([], -1, (record_bit(cfg, 0, 0, w1hi + 1), 0)),           # slot1 weight lo = 0
+            ([], 0, (record_bit(cfg, 0, 0, bo + cfg.BB - 1), 0))]     # bias lsb = 1 (-2 -> -1)
+    nlm = encode_netlist(cfg, prog)
+    mbad = 0
+    for a in (0, 1):
+        for b in (0, 1):
+            sig = _load(cfg, nlm); sig[IA] = a; sig[IB] = b
+            st = R.run({"sig": sig, "gp": 0, "halt": 0}, cfg.G)       # sweep 1: AND
+            f = st["sig"][OUT]
+            st = R.run(st, cfg.G)                                     # sweep 2: rewritten
+            g = st["sig"][OUT]
+            if f != (a & b) or g != (a & (1 - b)):
+                mbad += 1
+    # program-set BANK flag switches the interpreter to a different bank-1 machine
+    nl_sw = encode_netlist(cfg, [([], 0, (cfg.BANK_SIG, 0))])
+    Bnl = encode_netlist(cfg, [([(IA, 1, 0), (IB, 1, 0)], -2, (OUT, 0))])   # bank1 = AND
+    sig = _load(cfg, nl_sw, bank=0); sig[cfg.NET1:cfg.NET1 + len(Bnl)] = Bnl
+    st = R.run({"sig": sig, "gp": 0, "halt": 0}, 1)                   # gp0 sets BANK=1
+    st["gp"] = 0; st["sig"][IA] = 1; st["sig"][IB] = 1
+    st = R.run(st, cfg.G)                                             # now running bank1
+    switched = st["sig"][cfg.BANK_SIG] == 1 and st["sig"][OUT] == 1
+    print(f"  {'OK ' if mbad == 0 else 'FAIL'} one program computes a&b, then edits its "
+          f"own gate so the next sweep computes a&~b; "
+          f"{'OK ' if switched else 'FAIL'} program-set BANK runs the bank-1 machine")
+    ok &= mbad == 0 and switched
+
+    print("[7/7] Sequential state: interpret a 2-bit counter with feedback")
+    C0, C1, T, OR_, NAND_ = (cfg.WORK_BASE, cfg.WORK_BASE + 1, cfg.WORK_BASE + 2,
+                             cfg.WORK_BASE + 3, cfg.WORK_BASE + 4)
+    counter = [([(C0, 1, 0)], -1, (T, 0)),                      # T = c0 (old)
+               ([(C1, 1, 0), (T, 1, 0)], -1, (OR_, 0)),         # c1 OR T
+               ([(C1, -1, 0), (T, -1, 0)], 1, (NAND_, 0)),      # c1 NAND T
+               ([(OR_, 1, 0), (NAND_, 1, 0)], -2, (C1, 0)),     # c1' = c1 XOR c0
+               ([(C0, -1, 0)], 0, (C0, 0))]                     # c0' = NOT c0
+    nlk = encode_netlist(cfg, counter)
+    st = {"sig": _load(cfg, nlk), "gp": 0, "halt": 0}
+    seq = []
+    for _ in range(5):                                         # 5 ticks (5 sweeps)
+        st = R.run(st, cfg.G)
+        seq.append(st["sig"][C1] * 2 + st["sig"][C0])
+    kgood = seq == [1, 2, 3, 0, 1]
+    print(f"  {'OK ' if kgood else 'FAIL'} register advances 0->1->2->3->0 across sweeps "
+          f"(a stored machine holding state through feedback): {seq}")
+    ok &= kgood
+
+    print("\nREFLECT v2 (universality, order, quine, metamorphosis, sequential state):",
           "PASS" if ok else "FAIL")
     return ok
 
 
+def verify_scale(device):
+    cfg = Cfg(A=11, G=40, banks=1)
+    print(f"\nScale: interpret a 4-bit ripple-carry adder (S={cfg.S}, G={cfg.G})")
+    net, inputs, outputs = build_net(cfg)
+    print(f"  interpreter U: {len(net.gates):,} gates")
+    R = Runner(cfg, Leveled(net, inputs, outputs, device=device))
+    W = 4
+    anet, an, bn, sums, cout = adder_net(W)
+    ia = {}
+    for i in range(W):
+        ia[an[i]] = cfg.WORK_BASE + i
+        ia[bn[i]] = cfg.WORK_BASE + W + i
+    rg, addr = compile_to_reflect(cfg, anet, ia, sums + [cout], cfg.WORK_BASE + 2 * W)
+    nl = encode_netlist(cfg, rg)
+    print(f"  compiled adder netlist: {len(rg)} gates")
+
+    def result(st):
+        return sum(st["sig"][addr[sums[i]]] << i for i in range(W)) | (st["sig"][addr[cout]] << W)
+
+    bad = 0
+    pairs = [(x, y) for x in range(1 << W) for y in range(1 << W)]
+    for (x, y) in pairs:
+        sig = _load(cfg, nl)
+        for i in range(W):
+            sig[ia[an[i]]] = (x >> i) & 1
+            sig[ia[bn[i]]] = (y >> i) & 1
+        st = R.run({"sig": sig, "gp": 0, "halt": 0}, cfg.G)     # one sweep (topo order)
+        fam = eval_family_net(anet, {an[i]: (x >> i) & 1 for i in range(W)}
+                              | {bn[i]: (y >> i) & 1 for i in range(W)})
+        famres = sum(fam[sums[i]] << i for i in range(W)) | (fam[cout] << W)
+        if result(st) != x + y or result(st) != famres:
+            bad += 1
+    print(f"  {'OK ' if bad == 0 else 'FAIL'} all {len(pairs)} input pairs match "
+          f"arithmetic and the family's own evaluator")
+
+    obad = 0
+    for seed in range(2):
+        perm = list(range(len(rg)))
+        random.Random(seed + 1).shuffle(perm)
+        nls = encode_netlist(cfg, [rg[p] for p in perm])
+        for (x, y) in [(7, 9), (15, 15), (10, 6)]:
+            sig = _load(cfg, nls)
+            for i in range(W):
+                sig[ia[an[i]]] = (x >> i) & 1
+                sig[ia[bn[i]]] = (y >> i) & 1
+            st = R.run({"sig": sig, "gp": 0, "halt": 0}, cfg.G * cfg.G)
+            if result(st) != x + y:
+                obad += 1
+    print(f"  {'OK ' if obad == 0 else 'FAIL'} correct under 2 random gate orders (relaxation)")
+    good = bad == 0 and obad == 0
+    print("SCALE:", "PASS" if good else "FAIL")
+    return good
+
+
+def verify_subleq(device):
+    cfg = Cfg(A=14, G=304, banks=1, self_mod=False)
+    net, a, b, pc, c, r, leq, pcm = subleq_datapath_net()
+    print(f"\nFamily machine: interpret the SUBLEQ datapath "
+          f"(S={cfg.S}, addressed span={cfg.span}, G={cfg.G})")
+    inet, ii, io = build_net(cfg)
+    print(f"  interpreter U: {len(inet.gates):,} gates")
+    lev = Leveled(inet, ii, io, device=device)
+    base = cfg.WORK_BASE
+    in_addr = {}
+    for k in range(8):
+        in_addr[a[k]] = base + k
+        in_addr[b[k]] = base + 8 + k
+        in_addr[pc[k]] = base + 16 + k
+        in_addr[c[k]] = base + 24 + k
+    rg, addr = compile_to_reflect(cfg, net, in_addr, r + [leq] + pcm, base + 32)
+    nl = encode_netlist(cfg, rg)
+    print(f"  compiled datapath netlist: {len(rg)} gates; interpreting all "
+          f"65,536 (M[A], M[B]) pairs")
+    sig0 = [0] * cfg.S
+    sig0[cfg.NET0:cfg.NET0 + len(nl)] = nl
+    base_vec = state_to_vec(cfg, {"sig": sig0, "gp": 0, "halt": 0}).to(device)
+    PC, C = 0x42, 0x99
+
+    bad = 0
+    t0 = time.perf_counter()
+    for lo in range(0, 65536, 8192):
+        xs = torch.arange(lo, lo + 8192) % 256          # M[A]
+        ys = torch.arange(lo, lo + 8192) // 256         # M[B]
+        B = xs.shape[0]
+        V = base_vec.unsqueeze(0).repeat(B, 1)
+        for k in range(8):
+            V[:, in_addr[a[k]]] = ((xs >> k) & 1).float().to(device)
+            V[:, in_addr[b[k]]] = ((ys >> k) & 1).float().to(device)
+            V[:, in_addr[pc[k]]] = float((PC >> k) & 1)
+            V[:, in_addr[c[k]]] = float((C >> k) & 1)
+        for _ in range(cfg.G):
+            V = lev.step(V)
+        Vc = V.cpu()
+        rr = sum(Vc[:, addr[r[k]]].long() << k for k in range(8))
+        lq = Vc[:, addr[leq]].long()
+        npc = sum(Vc[:, addr[pcm[k]]].long() << k for k in range(8))
+        exp_r = (ys - xs) & 0xFF
+        exp_lq = ((exp_r == 0) | (exp_r >= 128)).long()
+        exp_np = torch.where(exp_lq.bool(), torch.full_like(xs, C), (PC + 3) & 0xFF)
+        bad += int((rr != exp_r).sum() + (lq != exp_lq).sum() + (npc != exp_np).sum())
+    dt = time.perf_counter() - t0
+    good = bad == 0
+    print(f"  {'OK ' if good else 'FAIL'} result, branch decision, and next-PC exact "
+          f"for all 65,536 pairs ({dt:.0f}s)")
+    print("SUBLEQ DATAPATH:", "PASS" if good else "FAIL")
+    return good
+
+
 # =============================================================================
 # analog: matrix == gate + noise / conductance-mismatch margins
 # =============================================================================
@@ -725,6 +910,8 @@ def main():
         build(cfg, save=True)
     if args.cmd in ("verify", "all"):
         rc |= 0 if verify(cfg, args.device) else 1
+        rc |= 0 if verify_scale(args.device) else 1
+        rc |= 0 if verify_subleq(args.device) else 1
     if args.cmd in ("analog", "all"):
         rc |= 0 if analog(cfg, args.device) else 1
     return rc

variants/neural_reflect.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:3a9c8eda3eef586ea00b4ff32e511223f54bff3ab6b4e151c69b5318cb106db2
+oid sha256:d653009bb03b30bf2ce2cc7a30e48c3cf284d722750c9a3aad0a51ce59fb4691
 size 157772226