8-bit computer decode and PC sequencing as threshold gates: a 4-to-16 opcode one-hot decoder and a next-PC network (PC+2/PC+4 increment chains plus a priority mux over PC+2, PC+4, the conditional-jump mux, and the direct target). The runtime dispatches on the gate one-hots and takes the next PC from the mux instead of Python slicing and PC+2. Full 10/10 CPU suite passes; all variants rebuilt. Completes decode/PC-as-gates across every runtime (rv32, subleq, 8-bit computer).

README.md

@@ -123,9 +123,10 @@ Every datapath operation runs through threshold gates: ALU arithmetic
 (ADD/SUB via ripple-carry, MUL via partial-product AND gates and shift-add,
 DIV via per-stage bit-cascade comparators), bitwise logic, shifts,
 comparisons, conditional-jump PC muxing, stack-pointer stepping, and all
-memory reads and writes. Instruction decode (bit-field selection), PC
-sequencing, and the bit complements feeding negated-condition selects are
-fixed wiring in the runtimes — structural routing, not gates.
+memory reads and writes. Instruction decode (a 4-to-16 opcode one-hot
+decoder) and PC sequencing (the PC+2/PC+4 increment chains and the next-PC
+mux) are also threshold gates now; register-field indexing and the bit
+complements feeding negated-condition selects remain structural routing.
 
 ```
             ┌─────────────────────────────┐
@@ -383,7 +384,7 @@ The most capable member: a RISC-V CPU whose entire datapath is ternary threshold
 - **Dual issue**: two adjacent OP/OP-IMM/LUI/AUIPC instructions retire in one cycle when the gate-level hazard comparators (`rv32.hazard.*`) clear RAW and WAW dependences.
 - **MMIO**: stores to `0xFF00` append a character to the console.
 
-Signed comparisons ride the unsigned bit-cascade with sign bits complemented through NOT gates; SLL uses the barrel shifter, SRL is bit-reversal wiring over it, SRA a gate mux over the complement form. Instruction decode, immediate extraction, register-file indexing, and PC sequencing are fixed wiring, per the family convention.
+Signed comparisons ride the unsigned bit-cascade with sign bits complemented through NOT gates; SLL uses the barrel shifter, SRL is bit-reversal wiring over it, SRA a gate mux over the complement form. Instruction decode (opcode-class detectors and the I/S/B/U/J immediate mux) and PC sequencing (the next-PC mux over PC+4, PC+imm, and (rs1+imm)&~1) are threshold gates; register-field indexing remains fixed wiring.
 
 ```bash
 python src/build.py --apply rv32                            # build the file
@@ -604,7 +605,7 @@ Modern neuromorphic processors implement large arrays of configurable threshold-
 
 Published work on these platforms has focused on neural network inference, sensory processing, and pattern recognition. A 2024 paper demonstrated basic logic gates, adders, and decoders on SpiNNaker and Dynap-SE1 and described that work as "a first step toward the construction of a spiking computer"; that implementation lacked instruction fetch, a program counter, memory, and control logic.
 
-The weights in this repository implement a complete CPU: registers, ALU with 16 operations, status flags, conditional branching, subroutine calls, stack operations, and memory access. Every logic component is a threshold neuron with integer weights; instruction decode and PC sequencing are fixed wiring between them.
+The weights in this repository implement a complete CPU: registers, ALU with 16 operations, status flags, conditional branching, subroutine calls, stack operations, and memory access. Every logic component is a threshold neuron with integer weights; opcode decode and PC sequencing run through threshold gates as well, leaving only register-field indexing as structural wiring.
 
 ---
 

neural_computer.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:9257c5519edac4fb5f76724389d6950590c83b8fa6e5a5e48bb2eda41e208c08
-size 45921927
+oid sha256:1555742a28aea9f00affacd90ee88b68760e09d9ca82dbeebc57ae746a99f1b8
+size 46044315

src/build.py

@@ -674,6 +674,38 @@ def add_conditional_jumps(tensors: Dict[str, torch.Tensor], addr_bits: int) -> N
             add_gate(tensors, f"{prefix}.or", [1.0, 1.0], [-1.0])
 
 
+def add_computer_decode(tensors: Dict[str, torch.Tensor]) -> None:
+    """Instruction decode for the 8-bit computer as threshold gates: a 4-to-16
+    opcode one-hot decoder (exact match on the instruction's opcode nibble). The
+    runtime reads these one-hots to dispatch instead of slicing the word."""
+    for opc in range(16):
+        w = [1.0 if (opc >> j) & 1 else -1.0 for j in range(4)]
+        add_gate(tensors, f"control.decode.op{opc}", w, [-float(bin(opc).count("1"))])
+
+
+def add_computer_pcnext(tensors: Dict[str, torch.Tensor], addr_bits: int) -> None:
+    """PC sequencing for the 8-bit computer as threshold gates: PC+2 / PC+4
+    increment chains and a priority mux selecting the next PC among PC+2 (ALU),
+    PC+4 (load/store), the conditional-jump mux, and the direct target
+    (JMP/CALL). Replaces the runtime's Python PC+2/PC+4 and jump wiring."""
+    for name, start in (("pc2", 1), ("pc4", 2)):
+        for bit in range(addr_bits):
+            if bit < start:
+                add_gate(tensors, f"control.pcnext.{name}.bit{bit}", [1.0], [-1.0])
+            else:
+                add_gate(tensors, f"control.pcnext.{name}.bit{bit}.xor.layer1.or", [1.0, 1.0], [-1.0])
+                add_gate(tensors, f"control.pcnext.{name}.bit{bit}.xor.layer1.nand", [-1.0, -1.0], [1.0])
+                add_gate(tensors, f"control.pcnext.{name}.bit{bit}.xor.layer2", [1.0, 1.0], [-2.0])
+                add_gate(tensors, f"control.pcnext.{name}.bit{bit}.carry", [1.0, 1.0], [-2.0])
+    # priority mux: next = use_addr ? addr : (use_jcc ? jcc : (use_pc4 ? pc4 : pc2))
+    for lvl in ("m_pc4", "m_jcc", "m_addr"):
+        for bit in range(addr_bits):
+            add_gate(tensors, f"control.pcnext.{lvl}.bit{bit}.not_sel", [-1.0], [0.0])
+            add_gate(tensors, f"control.pcnext.{lvl}.bit{bit}.and_a", [1.0, 1.0], [-2.0])
+            add_gate(tensors, f"control.pcnext.{lvl}.bit{bit}.and_b", [1.0, 1.0], [-2.0])
+            add_gate(tensors, f"control.pcnext.{lvl}.bit{bit}.or", [1.0, 1.0], [-1.0])
+
+
 def add_status_flags(tensors: Dict[str, torch.Tensor], data_bits: int) -> None:
     """Add status flag computation circuits (Z, N, C, V).
 
@@ -5472,7 +5504,8 @@ def infer_inputs_for_gate(gate: str, reg: SignalRegistry, tensors: Dict[str, tor
     if gate.startswith('modular.'):
         return infer_modular_inputs(gate, reg)
     if gate.startswith('control.'):
-        if any(j in gate for j in ['jz', 'jc', 'jn', 'jv', 'jp', 'jnz', 'jnc', 'jnv', 'conditionaljump']):
+        if ('pcnext' not in gate and 'decode' not in gate
+                and any(j in gate for j in ['jz', 'jc', 'jn', 'jv', 'jp', 'jnz', 'jnc', 'jnv', 'conditionaljump'])):
             prefix = gate.split('.bit')[0] if '.bit' in gate else gate.rsplit('.', 1)[0]
             return infer_control_jump_inputs(gate, prefix, reg)
         if any(b in gate for b in ['fetch', 'load', 'store', 'mem_addr']):
@@ -5506,6 +5539,58 @@ def infer_inputs_for_gate(gate: str, reg: SignalRegistry, tensors: Dict[str, tor
                 bit = int(m.group(1))
                 return [reg.register(f"$ret_addr[{bit}]")]
             return [reg.register(f"$ret_addr[{i}]") for i in range(16)]
+        if 'decode.op' in gate:
+            for i in range(4):
+                reg.register(f"$comp_op[{i}]")
+            return [reg.get_id(f"$comp_op[{i}]") for i in range(4)]
+        if 'pcnext.' in gate:
+            for i in range(16):
+                reg.register(f"$comp_pc[{i}]")
+                reg.register(f"$comp_addr[{i}]")
+                reg.register(f"$comp_jcc[{i}]")
+            for nm in ("$comp_use_pc4", "$comp_use_jcc", "$comp_use_addr"):
+                reg.register(nm)
+
+            def _inc_out(name, k):
+                start = 1 if name == "pc2" else 2
+                return reg.register(f"control.pcnext.{name}.bit{k}"
+                                    if k < start else f"control.pcnext.{name}.bit{k}.xor.layer2")
+
+            mm = re.match(r"^control\.pcnext\.(pc2|pc4)\.bit(\d+)(?:\.(.+))?$", gate)
+            if mm:
+                name, k, sub = mm.group(1), int(mm.group(2)), mm.group(3)
+                start = 1 if name == "pc2" else 2
+                if sub is None:
+                    return [reg.get_id(f"$comp_pc[{k}]")]
+                cin = reg.get_id("#1") if k == start else reg.register(f"control.pcnext.{name}.bit{k - 1}.carry")
+                pcb = reg.get_id(f"$comp_pc[{k}]")
+                if sub in ("xor.layer1.or", "xor.layer1.nand", "carry"):
+                    return [pcb, cin]
+                if sub == "xor.layer2":
+                    return [reg.register(f"control.pcnext.{name}.bit{k}.xor.layer1.or"),
+                            reg.register(f"control.pcnext.{name}.bit{k}.xor.layer1.nand")]
+            mm = re.match(r"^control\.pcnext\.(m_pc4|m_jcc|m_addr)\.bit(\d+)\.(not_sel|and_a|and_b|or)$", gate)
+            if mm:
+                lvl, k, kind = mm.group(1), int(mm.group(2)), mm.group(3)
+                sel = {"m_pc4": "$comp_use_pc4", "m_jcc": "$comp_use_jcc", "m_addr": "$comp_use_addr"}[lvl]
+                if kind == "not_sel":
+                    return [reg.get_id(sel)]
+                if kind == "and_a":
+                    if lvl == "m_pc4":
+                        a_src = _inc_out("pc2", k)
+                    else:
+                        a_src = reg.register(f"control.pcnext.{'m_pc4' if lvl == 'm_jcc' else 'm_jcc'}.bit{k}.or")
+                    return [a_src, reg.register(f"control.pcnext.{lvl}.bit{k}.not_sel")]
+                if kind == "and_b":
+                    if lvl == "m_pc4":
+                        b_src = _inc_out("pc4", k)
+                    elif lvl == "m_jcc":
+                        b_src = reg.get_id(f"$comp_jcc[{k}]")
+                    else:
+                        b_src = reg.get_id(f"$comp_addr[{k}]")
+                    return [b_src, reg.get_id(sel)]
+                return [reg.register(f"control.pcnext.{lvl}.bit{k}.and_a"),
+                        reg.register(f"control.pcnext.{lvl}.bit{k}.and_b")]
         return [reg.register("$ctrl")]
     if gate.startswith('memory.'):
         return infer_memory_inputs(gate, reg, tensors)
@@ -5671,6 +5756,14 @@ def cmd_memory(args) -> None:
         except ValueError as e:
             print(f"  Conditional jumps already exist: {e}")
 
+        print("\nGenerating instruction-decode and PC-sequencing circuits...")
+        try:
+            add_computer_decode(tensors)
+            add_computer_pcnext(tensors, addr_bits)
+            print(f"  Added opcode decoder (4->16) and next-PC mux ({addr_bits}-bit)")
+        except ValueError as e:
+            print(f"  Decode/PC circuits already exist: {e}")
+
         print("\nGenerating status flag circuits...")
         try:
             add_status_flags(tensors, args.bits)

src/eval_all.py

@@ -414,6 +414,52 @@ class GenericThresholdCPU:
             borrow = self.alu._g(f"{bp}.borrow", [float(1 - bits[bit]), float(borrow)])
         return bits_to_int(out)
 
+    def _decode_op(self, opcode):
+        """4-to-16 opcode one-hot through the gate decoder."""
+        ob = [float((opcode >> j) & 1) for j in range(4)]
+        return [self.alu._g(f"control.decode.op{n}", ob) for n in range(16)]
+
+    def _inc(self, pc, name, start):
+        """PC + 2^start through the gate increment chain (LSB-first)."""
+        ab = self.addr_bits
+        pcb = [(pc >> k) & 1 for k in range(ab)]
+        out = [0] * ab
+        carry = 0
+        for k in range(ab):
+            if k < start:
+                out[k] = self.alu._g(f"control.pcnext.{name}.bit{k}", [float(pcb[k])])
+            else:
+                cin = 1 if k == start else carry
+                o = self.alu._g(f"control.pcnext.{name}.bit{k}.xor.layer1.or", [float(pcb[k]), float(cin)])
+                nd = self.alu._g(f"control.pcnext.{name}.bit{k}.xor.layer1.nand", [float(pcb[k]), float(cin)])
+                out[k] = self.alu._g(f"control.pcnext.{name}.bit{k}.xor.layer2", [o, nd])
+                carry = self.alu._g(f"control.pcnext.{name}.bit{k}.carry", [float(pcb[k]), float(cin)])
+        return sum(out[k] << k for k in range(ab))
+
+    def _pcnext(self, pc2, pc4, addr, jcc, use_pc4, use_addr, use_jcc):
+        """Next-PC priority mux through the gates: use_addr ? addr :
+        (use_jcc ? jcc : (use_pc4 ? pc4 : pc2))."""
+        ab = self.addr_bits
+        p2 = [(pc2 >> k) & 1 for k in range(ab)]
+        p4 = [(pc4 >> k) & 1 for k in range(ab)]
+        aB = [(addr >> k) & 1 for k in range(ab)]
+        jB = [(jcc >> k) & 1 for k in range(ab)]
+        out = [0] * ab
+        for k in range(ab):
+            ns = self.alu._g(f"control.pcnext.m_pc4.bit{k}.not_sel", [float(use_pc4)])
+            aa = self.alu._g(f"control.pcnext.m_pc4.bit{k}.and_a", [float(p2[k]), ns])
+            bb = self.alu._g(f"control.pcnext.m_pc4.bit{k}.and_b", [float(p4[k]), float(use_pc4)])
+            m1 = self.alu._g(f"control.pcnext.m_pc4.bit{k}.or", [aa, bb])
+            ns = self.alu._g(f"control.pcnext.m_jcc.bit{k}.not_sel", [float(use_jcc)])
+            aa = self.alu._g(f"control.pcnext.m_jcc.bit{k}.and_a", [float(m1), ns])
+            bb = self.alu._g(f"control.pcnext.m_jcc.bit{k}.and_b", [float(jB[k]), float(use_jcc)])
+            m2 = self.alu._g(f"control.pcnext.m_jcc.bit{k}.or", [aa, bb])
+            ns = self.alu._g(f"control.pcnext.m_addr.bit{k}.not_sel", [float(use_addr)])
+            aa = self.alu._g(f"control.pcnext.m_addr.bit{k}.and_a", [float(m2), ns])
+            bb = self.alu._g(f"control.pcnext.m_addr.bit{k}.and_b", [float(aB[k]), float(use_addr)])
+            out[k] = self.alu._g(f"control.pcnext.m_addr.bit{k}.or", [aa, bb])
+        return sum(out[k] << k for k in range(ab))
+
     def step(self, state):
         if state["halted"]:
             return state
@@ -427,88 +473,88 @@ class GenericThresholdCPU:
         lo = self.mem_read(s["mem"], (pc + 1) & addr_mask)
         ir = ((hi & 0xFF) << 8) | (lo & 0xFF)
         opcode = (ir >> 12) & 0xF
+        oh = self._decode_op(opcode)                 # gate opcode decode (one-hots)
         rd = (ir >> 10) & 0x3
         rs = (ir >> 8) & 0x3
         imm = ir & 0xFF
-        next_pc = (pc + 2) & addr_mask
-        addr_full = None
-        if opcode in (0xA, 0xB, 0xC, 0xD, 0xE):
-            ah = self.mem_read(s["mem"], next_pc)
-            al = self.mem_read(s["mem"], (next_pc + 1) & addr_mask)
-            addr_full = ((ah & 0xFF) << 8) | (al & 0xFF)
-            next_pc = (next_pc + 2) & addr_mask
-        addr = (addr_full & addr_mask) if addr_full is not None else None
+        addr = None
+        if oh[0xA] or oh[0xB] or oh[0xC] or oh[0xD] or oh[0xE]:
+            ah = self.mem_read(s["mem"], (pc + 2) & addr_mask)
+            al = self.mem_read(s["mem"], (pc + 3) & addr_mask)
+            addr = (((ah & 0xFF) << 8) | (al & 0xFF)) & addr_mask
+        pc2 = self._inc(pc, "pc2", 1)                # PC+2 through the gate chain
+        pc4 = self._inc(pc, "pc4", 2)                # PC+4 through the gate chain
         a = s["regs"][rd]
         b = s["regs"][rs]
         result = a
         carry = 0
         overflow = 0
         write_result = True
-        if opcode == 0x0:
+        jcc_val = 0
+        if oh[0x0]:
             result, carry = self.alu.add8(a, b)
             overflow = 1 if (((a ^ result) & (b ^ result)) & 0x80) else 0
-        elif opcode == 0x1:
+        elif oh[0x1]:
             result, carry = self.alu.sub8(a, b)
             overflow = 1 if (((a ^ b) & (a ^ result)) & 0x80) else 0
-        elif opcode == 0x2:  # AND
+        elif oh[0x2]:
             result = self.alu.and8(a, b)
-        elif opcode == 0x3:  # OR
+        elif oh[0x3]:
             result = self.alu.or8(a, b)
-        elif opcode == 0x4:  # XOR
+        elif oh[0x4]:
             result = self.alu.xor8(a, b)
-        elif opcode == 0x5:  # SHL by 1 (8-bit)
+        elif oh[0x5]:
             result = self.alu.shl8(a)
-        elif opcode == 0x6:  # SHR by 1
+        elif oh[0x6]:
             result = self.alu.shr8(a)
-        elif opcode == 0x7:
+        elif oh[0x7]:
             result = self.alu.mul8(a, b)
-        elif opcode == 0x8:  # DIV (sets R[d] = R[d] / R[s]; 0xFF on divide by zero)
+        elif oh[0x8]:
             result, _ = self.alu.div8(a, b)
-        elif opcode == 0x9:
+        elif oh[0x9]:                                # CMP: set flags only
             r2, carry = self.alu.sub8(a, b)
             z = 1 if r2 == 0 else 0
             n = 1 if (r2 & 0x80) else 0
             v = 1 if (((a ^ b) & (a ^ r2)) & 0x80) else 0
             s["flags"] = [z, n, carry, v]
             write_result = False
-        elif opcode == 0xA:
+        elif oh[0xA]:                                # LOAD
             result = self.mem_read(s["mem"], addr)
-        elif opcode == 0xB:
+        elif oh[0xB]:                                # STORE
             s["mem"] = self.mem_write(s["mem"], addr, b & 0xFF)
             write_result = False
-        elif opcode == 0xC:
-            s["pc"] = addr
-            return s
-        elif opcode == 0xD:
+        elif oh[0xC]:                                # JMP (PC = addr via pcnext)
+            write_result = False
+        elif oh[0xD]:                                # JCC (PC via jcc mux + pcnext)
             cond = imm & 0x7
             circuit, flag_idx = self._JCC[cond]
             flag = s["flags"][flag_idx]
             sel = flag if cond % 2 == 0 else 1 - flag
-            s["pc"] = self._jcc_pc(circuit, next_pc, addr, sel)
-            return s
-        elif opcode == 0xE:  # CALL: push return address (next_pc), set PC = addr
-            ret_addr = next_pc & 0xFFFF
+            jcc_val = self._jcc_pc(circuit, pc4, addr, sel)
+            write_result = False
+        elif oh[0xE]:                                # CALL: push PC+4, PC = addr
+            ret_addr = pc4 & 0xFFFF
             sp = s.get("sp", addr_mask)
             sp = self._sp_dec(sp)
             s["mem"] = self.mem_write(s["mem"], sp, (ret_addr >> 8) & 0xFF)
             sp = self._sp_dec(sp)
             s["mem"] = self.mem_write(s["mem"], sp, ret_addr & 0xFF)
             s["sp"] = sp
-            s["pc"] = addr
-            return s
-        elif opcode == 0xF:
+            write_result = False
+        elif oh[0xF]:                                # HALT
             s["halted"] = True
             return s
 
-        if write_result and opcode != 0x9:
+        if write_result:
             s["regs"][rd] = result & 0xFF
-        # Flag policy: ADD, SUB, MUL (and CMP, handled in its branch) write
-        # Z/N/C/V; MUL clears C and V. All other opcodes leave FLAGS unchanged.
-        if opcode in (0x0, 0x1, 0x7):
+        if oh[0x0] or oh[0x1] or oh[0x7]:
             z = 1 if (result & 0xFF) == 0 else 0
             n = 1 if (result & 0x80) else 0
             s["flags"] = [z, n, carry, overflow]
-        s["pc"] = next_pc
+        # PC sequencing through the gate mux.
+        use_pc4 = 1 if (oh[0xA] or oh[0xB]) else 0
+        use_addr = 1 if (oh[0xC] or oh[0xE]) else 0
+        s["pc"] = self._pcnext(pc2, pc4, addr or 0, jcc_val, use_pc4, use_addr, oh[0xD])
         return s
 
     def run(self, state, max_cycles=200):

todo.md

@@ -2,5 +2,4 @@
 
 Unfinished work.
 
-1. Program-counter sequencing and instruction decode are computed by threshold gates rather than by fixed wiring in the runtimes.
-2. A machine-checked correctness proof relates the shipped weights to the ISA.
+1. A machine-checked correctness proof relates the shipped weights to the ISA.

variants/neural_alu32.safetensors

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variants/neural_alu8.safetensors

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variants/neural_computer16.safetensors

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+size 47686556

variants/neural_computer16_reduced.safetensors

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variants/neural_computer16_registers.safetensors

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variants/neural_computer16_scratchpad.safetensors

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+size 39286906

variants/neural_computer16_small.safetensors

@@ -1,3 +1,3 @@
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