rv32 decode and PC sequencing as threshold gates: an opcode-class detector network (exact 7-bit match per class), sign-extended immediate generation muxed over the I/S/B/U/J formats, and a next-PC mux (PC+4 / PC+imm / (rs1+imm)&~1). The threshold CPU reads these gate outputs for dispatch, immediates, and the next PC instead of slicing the instruction word in Python; verified in isolation and by the full RV32 lockstep suite plus randomized programs.

src/build.py

@@ -5166,6 +5166,48 @@ def infer_rv32_inputs(gate: str, reg: SignalRegistry) -> Optional[List[int]]:
         pair = m.group(1)
         return [R(f"rv32.hazard.{pair}.bit{k}.eq") for k in range(5)]
 
+    # Instruction decode: opcode-class detectors, format-select, active immediate.
+    m = re.match(r"^rv32\.decode\.is_(\w+)$", gate)
+    if m:
+        name = m.group(1)
+        if name == "fma":
+            return [R(f"$rv32_instr[{j}]") for j in (0, 1, 4, 5, 6)]
+        return [R(f"$rv32_instr[{j}]") for j in range(7)]
+    m = re.match(r"^rv32\.decode\.use_([ISBUJ])$", gate)
+    if m:
+        return [R(f"rv32.decode.is_{cls}") for cls in RV32_USE[m.group(1)]]
+    m = re.match(r"^rv32\.decode\.imm\.bit(\d+)\.and_([ISBUJ])$", gate)
+    if m:
+        k, fmt = int(m.group(1)), m.group(2)
+        return [R(f"rv32.decode.use_{fmt}"), R(f"$rv32_instr[{_rv32_imm_src(fmt, k)}]")]
+    m = re.match(r"^rv32\.decode\.imm\.bit(\d+)$", gate)
+    if m:
+        k = int(m.group(1))
+        terms = [fmt for fmt in RV32_IMM_FMTS if _rv32_imm_src(fmt, k) is not None]
+        return [R(f"rv32.decode.imm.bit{k}.and_{fmt}") for fmt in terms] if terms else [zero]
+
+    # PC sequencing: next-PC mux (pc4 / pc+imm / (rs1+imm)&~1).
+    m = re.match(r"^rv32\.pcnext\.m1\.bit(\d+)\.(not_sel|and_a|and_b|or)$", gate)
+    if m:
+        k, kind = int(m.group(1)), m.group(2)
+        if kind == "not_sel":
+            return [R("$rv32_sel_target")]
+        if kind == "and_a":
+            return [R(f"$rv32_pc4[{k}]"), R(f"rv32.pcnext.m1.bit{k}.not_sel")]
+        if kind == "and_b":
+            return [R(f"$rv32_pcimm[{k}]"), R("$rv32_sel_target")]
+        return [R(f"rv32.pcnext.m1.bit{k}.and_a"), R(f"rv32.pcnext.m1.bit{k}.and_b")]
+    m = re.match(r"^rv32\.pcnext\.bit(\d+)\.(not_sel|and_a|and_b|or)$", gate)
+    if m:
+        k, kind = int(m.group(1)), m.group(2)
+        if kind == "not_sel":
+            return [R("$rv32_sel_jalr")]
+        if kind == "and_a":
+            return [R(f"rv32.pcnext.m1.bit{k}.or"), R(f"rv32.pcnext.bit{k}.not_sel")]
+        if kind == "and_b":
+            return [R(f"$rv32_jalr[{k}]"), R("$rv32_sel_jalr")]
+        return [R(f"rv32.pcnext.bit{k}.and_a"), R(f"rv32.pcnext.bit{k}.and_b")]
+
     return None
 
 
@@ -6056,6 +6098,86 @@ def add_rv32_extras(tensors: Dict[str, torch.Tensor]) -> None:
         add_gate(tensors, f"rv32.hazard.{pair}.all", [1.0] * 5, [-5.0])
 
 
+# Opcode -> class name for the instruction-decode network.
+RV32_OPCLASS = {0x33: "op", 0x13: "op_imm", 0x03: "load", 0x23: "store",
+                0x63: "branch", 0x37: "lui", 0x17: "auipc", 0x6F: "jal",
+                0x67: "jalr", 0x73: "system", 0x53: "fp", 0x07: "flw", 0x27: "fsw"}
+# Which opcode classes select each immediate format.
+RV32_USE = {"I": ["op_imm", "load", "jalr", "flw"], "S": ["store", "fsw"],
+            "B": ["branch"], "U": ["lui", "auipc"], "J": ["jal"]}
+RV32_IMM_FMTS = ("I", "S", "B", "U", "J")
+
+
+def _rv32_imm_src(fmt: str, k: int):
+    """Instruction bit that supplies immediate bit k for a format, or None (0)."""
+    if fmt == "I":
+        return (20 + k) if k <= 11 else 31
+    if fmt == "S":
+        if k <= 4:
+            return 7 + k
+        return (20 + k) if k <= 11 else 31
+    if fmt == "B":
+        if k == 0:
+            return None
+        if k <= 4:
+            return 7 + k
+        if k <= 10:
+            return 20 + k
+        if k == 11:
+            return 7
+        return 31
+    if fmt == "U":
+        return None if k < 12 else k
+    if fmt == "J":
+        if k == 0:
+            return None
+        if k <= 10:
+            return 20 + k
+        if k == 11:
+            return 20
+        if k <= 19:
+            return k
+        return 31
+    return None
+
+
+def add_rv32_decode(tensors: Dict[str, torch.Tensor]) -> None:
+    """Instruction decode as threshold gates: opcode-class one-hots (an exact
+    7-bit match on the instruction's opcode field) and the sign-extended
+    immediate for the active format, muxed from the raw instruction word. The
+    runtime reads these gate outputs instead of slicing the word in Python."""
+    for opc, name in RV32_OPCLASS.items():
+        w = [1.0 if (opc >> j) & 1 else -1.0 for j in range(7)]
+        add_gate(tensors, f"rv32.decode.is_{name}", w, [-float(bin(opc).count("1"))])
+    # FMADD/FMSUB/FNMADD/FNMSUB share the mask 100xx11 (instr bits 6,1,0 set; 5,4 clear).
+    add_gate(tensors, "rv32.decode.is_fma", [1.0, 1.0, -1.0, -1.0, 1.0], [-3.0])
+    for u, cls in RV32_USE.items():
+        add_gate(tensors, f"rv32.decode.use_{u}", [1.0] * len(cls), [-1.0])
+    for k in range(32):
+        terms = [fmt for fmt in RV32_IMM_FMTS if _rv32_imm_src(fmt, k) is not None]
+        for fmt in terms:
+            add_gate(tensors, f"rv32.decode.imm.bit{k}.and_{fmt}", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"rv32.decode.imm.bit{k}", [1.0] * max(1, len(terms)), [-1.0])
+
+
+def add_rv32_pcnext(tensors: Dict[str, torch.Tensor]) -> None:
+    """PC sequencing as threshold gates: a two-level mux selecting the next PC
+    among PC+4, PC+imm (branch/jal), and (rs1+imm)&~1 (jalr). The three
+    candidates are the gate adder's outputs; this network chooses between them
+    from the decode's control signals rather than a Python if/elif."""
+    for k in range(32):
+        # m1 = sel_target ? pcimm : pc4
+        add_gate(tensors, f"rv32.pcnext.m1.bit{k}.not_sel", [-1.0], [0.0])
+        add_gate(tensors, f"rv32.pcnext.m1.bit{k}.and_a", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"rv32.pcnext.m1.bit{k}.and_b", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"rv32.pcnext.m1.bit{k}.or", [1.0, 1.0], [-1.0])
+        # pcnext = sel_jalr ? jalr : m1
+        add_gate(tensors, f"rv32.pcnext.bit{k}.not_sel", [-1.0], [0.0])
+        add_gate(tensors, f"rv32.pcnext.bit{k}.and_a", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"rv32.pcnext.bit{k}.and_b", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"rv32.pcnext.bit{k}.or", [1.0, 1.0], [-1.0])
+
+
 def cmd_rv32(args) -> None:
     """Build the standalone RV32 threshold processor file from scratch:
     64 KB packed memory, the shared 32-bit circuit families, the composed
@@ -6083,6 +6205,8 @@ def cmd_rv32(args) -> None:
     add_float_fma(tensors, "float32", 8, 23)
     add_float32_cmp(tensors)
     add_rv32_extras(tensors)
+    add_rv32_decode(tensors)
+    add_rv32_pcnext(tensors)
     tensors["manifest.data_bits"] = torch.tensor([32.0], dtype=torch.float32)
     tensors["manifest.addr_bits"] = torch.tensor([16.0], dtype=torch.float32)
     tensors["manifest.memory_bytes"] = torch.tensor([65536.0], dtype=torch.float32)

src/machines.py

@@ -573,6 +573,8 @@ def rv_state(mem):
 # =============================================================================
 
 PAIRABLE = (0x33, 0x13, 0x37, 0x17)
+DECODE_CLASSES = ("op", "op_imm", "load", "store", "branch", "lui", "auipc",
+                  "jal", "jalr", "system", "fp", "flw", "fsw", "fma")
 
 
 class Rv32ThresholdCPU:
@@ -585,6 +587,8 @@ class Rv32ThresholdCPU:
         self.alu = GenericThresholdALU(self.T, 32)
         self.fpu = {op: NetlistEvaluator(self.T, self.registry, f"float32.{op}")
                     for op in ("add", "mul", "div", "cmp", "fma")}
+        self.decode = NetlistEvaluator(self.T, self.registry, "rv32.decode")
+        self.pcseq = NetlistEvaluator(self.T, self.registry, "rv32.pcnext")
         self.pairs_issued = 0
 
     # ---- gate helpers -------------------------------------------------
@@ -926,13 +930,15 @@ class Rv32ThresholdCPU:
         f7 = w >> 25
         R = s["regs"]
         a = R[rs1]
+        if op in (0x37, 0x17, 0x13):
+            _, imm_g = self._decode(w)            # gate-decoded immediate
         if op == 0x37:
-            return rd, w & 0xFFFFF000
+            return rd, imm_g
         if op == 0x17:
-            return rd, self.add32(pc, w & 0xFFFFF000)
+            return rd, self.add32(pc, imm_g)
         if op == 0x13:
-            b = u32(sext(w >> 20, 12))
-            sh = (w >> 20) & 31
+            b = imm_g
+            sh = imm_g & 31
             imm_mode = True
         else:
             b = R[rs2]
@@ -1001,7 +1007,9 @@ class Rv32ThresholdCPU:
         R = s["regs"]
         FR = s["fregs"]
         a, b = R[rs1], R[rs2]
-        nxt = (pc + 4) & MASK32
+        cls, imm_g = self._decode(w)              # gate decode: classes + immediate
+        pc4 = self.add32(pc, 4)                    # PC+4 through the gate adder
+        branch_taken = 0
 
         def wr(v):
             if rd:
@@ -1011,7 +1019,7 @@ class Rv32ThresholdCPU:
             d, v = self._exec_alu_class(s, pc, w)
             if d:
                 R[d] = u32(v)
-        if op == 0x33 and f7 == 1:
+        if cls["op"] and f7 == 1:
             if f3 == 0:
                 wr(self.alu.mul_n(a, b, 32))
             elif f3 == 1:
@@ -1028,40 +1036,29 @@ class Rv32ThresholdCPU:
                 wr(self.divs(a, b)[1])
             elif f3 == 7:
                 wr(self.divu(a, b)[1])
-        elif op == 0x6F:
-            imm = sext((((w >> 31) & 1) << 20) | (((w >> 12) & 0xFF) << 12)
-                       | (((w >> 20) & 1) << 11) | (((w >> 21) & 0x3FF) << 1), 21)
-            wr(nxt)
-            nxt = self.add32(pc, u32(imm))
-        elif op == 0x67:
-            t = self.add32(a, u32(sext(w >> 20, 12))) & ~1
-            wr(nxt)
-            nxt = t
-        elif op == 0x63:
-            imm = sext((((w >> 31) & 1) << 12) | (((w >> 7) & 1) << 11)
-                       | (((w >> 25) & 0x3F) << 5) | (((w >> 8) & 0xF) << 1), 13)
+        elif cls["jal"]:
+            wr(pc4)                               # return address
+        elif cls["jalr"]:
+            wr(pc4)
+        elif cls["branch"]:
             eq = self.ucmp(a, b, "eq")
             sl = self.scmp_lt(a, b)
             ul = self.ucmp(a, b, "lessthan")
-            take = [eq, 1 - eq, 0, 0, sl, 1 - sl, ul, 1 - ul][f3]
-            if take:
-                nxt = self.add32(pc, u32(imm))
-        elif op == 0x03:
-            addr = self.add32(a, u32(sext(w >> 20, 12))) & 0xFFFF
+            branch_taken = [eq, 1 - eq, 0, 0, sl, 1 - sl, ul, 1 - ul][f3]
+        elif cls["load"]:
+            addr = self.add32(a, imm_g) & 0xFFFF
             width = [1, 2, 4, 0, 1, 2][f3]
             wr(self._load(s, addr, width, f3 < 3))
-        elif op == 0x23:
-            imm = sext(((w >> 25) << 5) | ((w >> 7) & 31), 12)
-            addr = self.add32(a, u32(imm)) & 0xFFFF
+        elif cls["store"]:
+            addr = self.add32(a, imm_g) & 0xFFFF
             self._store(s, addr, b, [1, 2, 4][f3])
-        elif op == 0x07:
-            addr = self.add32(a, u32(sext(w >> 20, 12))) & 0xFFFF
+        elif cls["flw"]:
+            addr = self.add32(a, imm_g) & 0xFFFF
             FR[rd] = self._load(s, addr, 4, False)
-        elif op == 0x27:
-            imm = sext(((w >> 25) << 5) | ((w >> 7) & 31), 12)
-            addr = self.add32(a, u32(imm)) & 0xFFFF
+        elif cls["fsw"]:
+            addr = self.add32(a, imm_g) & 0xFFFF
             self._store(s, addr, FR[rs2], 4)
-        elif op == 0x53:
+        elif cls["fp"]:
             fa, fb = FR[rs1], FR[rs2]
             if f7 in (0x00, 0x04, 0x08, 0x0C):
                 circ = {0x00: "add", 0x04: "add", 0x08: "mul", 0x0C: "div"}[f7]
@@ -1090,7 +1087,7 @@ class Rv32ThresholdCPU:
                 FR[rd] = a
             elif f7 == 0x70:
                 wr(FR[rs1])
-        elif op in (0x43, 0x47, 0x4b, 0x4f):     # FMADD/FMSUB/FNMSUB/FNMADD.S
+        elif cls["fma"]:                          # FMADD/FMSUB/FNMSUB/FNMADD.S
             rs3 = (w >> 27) & 0x1F
             fa, fb, fc = FR[rs1], FR[rs2], FR[rs3]
             if op in (0x4b, 0x4f):               # negate the product
@@ -1100,13 +1097,17 @@ class Rv32ThresholdCPU:
             FR[rd] = self._fpu_word3(fa, fb, fc)
         elif op == 0x0B:
             wr(self.neur(a, b))
-        elif op == 0x73:
+        elif cls["system"]:
             s["halted"] = True
         elif op == 0x0F:
             pass
         elif op not in PAIRABLE:
             raise ValueError(f"illegal instruction {w:#010x} at {pc:#06x}")
-        s["pc"] = nxt
+        # PC sequencing through the gate mux: pc4 / pc+imm (branch,jal) / (rs1+imm)&~1 (jalr).
+        pcimm = self.add32(pc, imm_g)
+        jalr_t = self.add32(a, imm_g) & ~1
+        sel_target = 1 if (branch_taken or cls["jal"]) else 0
+        s["pc"] = self._pcnext(pc4, pcimm, jalr_t, sel_target, cls["jalr"])
         return s
 
     def _fpu_ext(self, fa, fb):
@@ -1144,6 +1145,30 @@ class Rv32ThresholdCPU:
             v |= int(out[f"{p}.frac_out.bit{k}"][0, 0].item()) << k
         return v
 
+    def _decode(self, w):
+        """Instruction decode through the gate network: opcode-class one-hots
+        and the sign-extended immediate for the active format."""
+        ext = {f"$rv32_instr[{k}]": (w >> k) & 1 for k in range(32)}
+        out = self.decode.run(ext)
+        cls = {n: int(out[f"rv32.decode.is_{n}"][0, 0].item()) for n in DECODE_CLASSES}
+        imm = 0
+        for k in range(32):
+            imm |= int(out[f"rv32.decode.imm.bit{k}"][0, 0].item()) << k
+        return cls, imm
+
+    def _pcnext(self, pc4, pcimm, jalr, sel_target, sel_jalr):
+        """Next-PC selection through the gate mux (pc4 / pc+imm / (rs1+imm)&~1)."""
+        ext = {"$rv32_sel_target": sel_target, "$rv32_sel_jalr": sel_jalr}
+        for k in range(32):
+            ext[f"$rv32_pc4[{k}]"] = (pc4 >> k) & 1
+            ext[f"$rv32_pcimm[{k}]"] = (pcimm >> k) & 1
+            ext[f"$rv32_jalr[{k}]"] = (jalr >> k) & 1
+        out = self.pcseq.run(ext)
+        v = 0
+        for k in range(32):
+            v |= int(out[f"rv32.pcnext.bit{k}.or"][0, 0].item()) << k
+        return v
+
     def run(self, state, max_cycles=400):
         s = dict(state)
         s["_mem_bits"] = torch.tensor(

variants/neural_rv32.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:d329a8aedbf8e993be78df458f26044ace482b4ee146e0dee86612c12d5a345a
-size 43277092
+oid sha256:1947dab2cf586de70c3f799538eda4f129106d77ead404944df060349ff1380e
+size 43429657