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firmware/ap_types/ap_common.h

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+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_COMMON_H__
+#define __AP_COMMON_H__
+
+// ----------------------------------------------------------------------
+
+// Forward declaration of all AP types.
+#include <ap_decl.h>
+
+
+#ifdef __SYNTHESIS__
+#error "The open-source version of AP types does not support synthesis."
+#endif // ifdef __SYNTHESIS__
+#define _AP_ENABLE_HALF_ 0
+
+
+#if _AP_ENABLE_HALF_ == 1
+// Before ap_private definition.
+#ifdef __SYNTHESIS__
+#define _HLS_HALF_DEFINED_
+typedef __fp16 half;
+#else
+class half;
+#endif // __SYNTHESIS__
+#endif // _AP_ENABLE_HALF_
+
+// ----------------------------------------------------------------------
+
+// Macro functions
+#define AP_MAX(a, b) ((a) > (b) ? (a) : (b))
+#define AP_MIN(a, b) ((a) < (b) ? (a) : (b))
+#define AP_ABS(a) ((a) >= 0 ? (a) : -(a))
+
+#ifndef AP_ASSERT
+#ifndef __SYNTHESIS__
+#include <assert.h>
+#define AP_ASSERT(cond, msg) assert((cond) && (msg))
+#else
+#define AP_ASSERT(cond, msg)
+#endif // ifndef __SYNTHESIS__
+#endif // ifndef AP_ASSERT
+
+#ifndef __SYNTHESIS__
+// for fprintf messages.
+#include <stdio.h>
+// for exit on error.
+#include <stdlib.h>
+#endif
+
+// same disable condition as assert.
+#if !defined(__SYNTHESIS__) && !defined(NDEBUG)
+
+#define _AP_DEBUG(cond, ...)                  \
+  do {                                        \
+    if ((cond)) {                             \
+      fprintf(stderr, "DEBUG: " __VA_ARGS__); \
+      fprintf(stderr, "\n");                  \
+    }                                         \
+  } while (0)
+#define _AP_WARNING(cond, ...)                  \
+  do {                                          \
+    if ((cond)) {                               \
+      fprintf(stderr, "WARNING: " __VA_ARGS__); \
+      fprintf(stderr, "\n");                    \
+    }                                           \
+  } while (0)
+#define _AP_ERROR(cond, ...)                  \
+  do {                                        \
+    if ((cond)) {                             \
+      fprintf(stderr, "ERROR: " __VA_ARGS__); \
+      fprintf(stderr, "\n");                  \
+      abort();                                \
+    }                                         \
+  } while (0)
+
+#else // if !defined(__SYNTHESIS__) && !defined(NDEBUG)
+
+#define __AP_VOID_CAST static_cast<void>
+#define _AP_DEBUG(cond, ...) (__AP_VOID_CAST(0))
+#define _AP_WARNING(cond, ...) (__AP_VOID_CAST(0))
+#define _AP_ERROR(cond, ...) (__AP_VOID_CAST(0))
+
+#endif // if !defined(__SYNTHESIS__) && !defined(NDEBUG) else
+
+// ----------------------------------------------------------------------
+
+// Attribute only for synthesis
+#ifdef __SYNTHESIS__
+#define INLINE inline __attribute__((always_inline))
+//#define INLINE inline __attribute__((noinline))
+#else
+#define INLINE inline
+#endif
+
+#define AP_WEAK
+// __attribute__((weak))
+
+#ifndef AP_INT_MAX_W
+#define AP_INT_MAX_W 1024
+#endif
+
+#define BIT_WIDTH_UPPER_LIMIT (1 << 15)
+#if AP_INT_MAX_W > BIT_WIDTH_UPPER_LIMIT
+#error "Bitwidth exceeds 32768 (1 << 15), the maximum allowed value"
+#endif
+
+#define MAX_MODE(BITS) ((BITS + 1023) / 1024)
+
+// ----------------------------------------------------------------------
+
+// XXX apcc cannot handle global std::ios_base::Init() brought in by <iostream>
+#ifndef AP_AUTOCC
+#ifndef __SYNTHESIS__
+// for overload operator<<
+#include <iostream>
+#endif
+#endif // ifndef AP_AUTOCC
+
+#ifndef __SYNTHESIS__
+// for string format.
+#include <sstream>
+// for string.
+#include <string>
+#endif
+
+// for detecting if char is signed.
+enum { CHAR_IS_SIGNED = (char)-1 < 0 };
+
+// TODO we have similar traits in x_hls_utils.h, should consider unify.
+namespace _ap_type {
+template <typename _Tp>
+struct is_signed {
+  static const bool value = _Tp(-1) < _Tp(1);
+};
+
+template <typename _Tp>
+struct is_integral {
+  static const bool value = false;
+};
+#define DEF_IS_INTEGRAL(CTYPE)      \
+  template <>                       \
+  struct is_integral<CTYPE> {       \
+    static const bool value = true; \
+  };
+DEF_IS_INTEGRAL(bool)
+DEF_IS_INTEGRAL(char)
+DEF_IS_INTEGRAL(signed char)
+DEF_IS_INTEGRAL(unsigned char)
+DEF_IS_INTEGRAL(short)
+DEF_IS_INTEGRAL(unsigned short)
+DEF_IS_INTEGRAL(int)
+DEF_IS_INTEGRAL(unsigned int)
+DEF_IS_INTEGRAL(long)
+DEF_IS_INTEGRAL(unsigned long)
+DEF_IS_INTEGRAL(ap_slong)
+DEF_IS_INTEGRAL(ap_ulong)
+#undef DEF_IS_INTEGRAL
+
+template <bool, typename _Tp = void>
+struct enable_if {};
+// partial specialization for true
+template <typename _Tp>
+struct enable_if<true, _Tp> {
+  typedef _Tp type;
+};
+
+template <typename _Tp>
+struct remove_const {
+  typedef _Tp type;
+};
+
+template <typename _Tp>
+struct remove_const<_Tp const> {
+  typedef _Tp type;
+};
+} // namespace _ap_type
+
+// ----------------------------------------------------------------------
+
+// Define ssdm_int and _ssdm_op.
+// XXX deleted in open-source version
+
+#ifndef NON_C99STRING
+#define _AP_C99 true
+#else
+#define _AP_C99 false
+#endif
+
+static inline unsigned char guess_radix(const char* s) {
+  unsigned char rd = 10; ///< default radix
+  const char* p = s;
+  // skip neg sign if it exists
+  if (p[0] == '-' || p[0] == '+') ++p;
+  // guess based on following two bits.
+  if (p[0] == '0') {
+    if (p[1] == 'b' || p[1] == 'B') {
+      rd = 2;
+    } else if (p[1] == 'o' || p[1] == 'O') {
+      rd = 8;
+    } else if (p[1] == 'x' || p[1] == 'X') {
+      rd = 16;
+    } else if (p[1] == 'd' || p[1] == 'D') {
+      rd = 10;
+    }
+  }
+  return rd;
+}
+
+// ----------------------------------------------------------------------
+
+// Basic integral struct upon which ap_int and ap_fixed are defined.
+#ifdef __SYNTHESIS__
+// Use ssdm_int, a compiler dependent, attribute constrained integeral type as
+// basic data type.
+#define _AP_ROOT_TYPE ssdm_int
+// Basic ops.
+#define _AP_ROOT_op_concat(Ret, X, Y) _ssdm_op_concat(Ret, X, Y)
+#define _AP_ROOT_op_get_bit(Val, Bit) _ssdm_op_get_bit(Val, Bit)
+#define _AP_ROOT_op_set_bit(Val, Bit, Repl) _ssdm_op_set_bit(Val, Bit, Repl)
+#define _AP_ROOT_op_get_range(Val, Lo, Hi) _ssdm_op_get_range(Val, Lo, Hi)
+#define _AP_ROOT_op_set_range(Val, Lo, Hi, Repl) \
+  _ssdm_op_set_range(Val, Lo, Hi, Repl)
+#define _AP_ROOT_op_reduce(Op, Val) _ssdm_op_reduce(Op, Val)
+#else // ifdef __SYNTHESIS__
+// Use ap_private for compiler-independent basic data type
+template <int _AP_W, bool _AP_S, bool _AP_C = _AP_W <= 64>
+class ap_private;
+/// model ssdm_int in standard C++ for simulation.
+template <int _AP_W, bool _AP_S>
+struct ssdm_int_sim {
+  /// integral type with template-specified width and signedness.
+  ap_private<_AP_W, _AP_S> V;
+  ssdm_int_sim() {}
+};
+#define _AP_ROOT_TYPE ssdm_int_sim
+// private's ref uses _AP_ROOT_TYPE.
+#include <etc/ap_private.h>
+// XXX The C-sim model cannot use GCC-extension
+// Basic ops. Ret and Val are ap_private.
+template <typename _Tp1, typename _Tp2, typename _Tp3>
+inline _Tp1 _AP_ROOT_op_concat(const _Tp1& Ret, const _Tp2& X, const _Tp3& Y) {
+  _Tp1 r = (X).operator,(Y);
+  return r;
+}
+#define _AP_ROOT_op_get_bit(Val, Bit) (Val).get_bit((Bit))
+template <typename _Tp1, typename _Tp2, typename _Tp3>
+inline _Tp1& _AP_ROOT_op_set_bit(_Tp1& Val, const _Tp2& Bit, const _Tp3& Repl) {
+  (Val).set_bit((Bit), (Repl));
+  return Val;
+}
+// notice the order of high and low index is different in ssdm call and
+// ap_private.range()...
+#define _AP_ROOT_op_get_range(Val, Lo, Hi) (Val).range((Hi), (Lo))
+template <typename _Tp1, typename _Tp2, typename _Tp3, typename _Tp4>
+inline _Tp1& _AP_ROOT_op_set_range(_Tp1& Val, const _Tp2& Lo, const _Tp3& Hi,
+                                   const _Tp4& Repl) {
+  (Val).range((Hi), (Lo)) = Repl;
+  return (Val);
+}
+#define _AP_ROOT_op_and_reduce(Val) (Val).and_reduce()
+#define _AP_ROOT_op_nand_reduce(Val) (Val).nand_reduce()
+#define _AP_ROOT_op_or_reduce(Val) (Val).or_reduce()
+#define _AP_ROOT_op_xor_reduce(Val) (Val).xor_reduce()
+// ## is the concatenation in preprocessor:
+#define _AP_ROOT_op_reduce(Op, Val) _AP_ROOT_op_##Op##_reduce(Val)
+#endif // ifdef __SYNTHESIS__ else
+
+// ----------------------------------------------------------------------
+
+// Constants for half, single, double pricision floating points
+#define HALF_MAN 10
+#define FLOAT_MAN 23
+#define DOUBLE_MAN 52
+
+#define HALF_EXP 5
+#define FLOAT_EXP 8
+#define DOUBLE_EXP 11
+
+#define BIAS(e) ((1L << (e - 1L)) - 1L)
+#define HALF_BIAS BIAS(HALF_EXP)
+#define FLOAT_BIAS BIAS(FLOAT_EXP)
+#define DOUBLE_BIAS BIAS(DOUBLE_EXP)
+
+#define APFX_IEEE_DOUBLE_E_MAX DOUBLE_BIAS
+#define APFX_IEEE_DOUBLE_E_MIN (-DOUBLE_BIAS + 1)
+
+INLINE ap_ulong doubleToRawBits(double pf) {
+  union {
+    ap_ulong __L;
+    double __D;
+  } LD;
+  LD.__D = pf;
+  return LD.__L;
+}
+
+INLINE unsigned int floatToRawBits(float pf) {
+  union {
+    unsigned int __L;
+    float __D;
+  } LD;
+  LD.__D = pf;
+  return LD.__L;
+}
+
+#if _AP_ENABLE_HALF_ == 1
+INLINE unsigned short halfToRawBits(half pf) {
+#ifdef __SYNTHESIS__
+  union {
+    unsigned short __L;
+    half __D;
+  } LD;
+  LD.__D = pf;
+  return LD.__L;
+#else
+  return pf.get_bits();
+#endif
+}
+#endif
+
+// usigned long long is at least 64-bit
+INLINE double rawBitsToDouble(ap_ulong pi) {
+  union {
+    ap_ulong __L;
+    double __D;
+  } LD;
+  LD.__L = pi;
+  return LD.__D;
+}
+
+// long is at least 32-bit
+INLINE float rawBitsToFloat(unsigned long pi) {
+  union {
+    unsigned int __L;
+    float __D;
+  } LD;
+  LD.__L = pi;
+  return LD.__D;
+}
+
+#if _AP_ENABLE_HALF_ == 1
+// short is at least 16-bit
+INLINE half rawBitsToHalf(unsigned short pi) {
+#ifdef __SYNTHESIS__
+  union {
+    unsigned short __L;
+    half __D;
+  } LD;
+  LD.__L = pi;
+  return LD.__D;
+#else
+  // sim model of half has a non-trivial constructor
+  half __D;
+  __D.set_bits(pi);
+  return __D;
+#endif
+}
+#endif
+
+#endif // ifndef __AP_COMMON_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_decl.h

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+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_DECL_H__
+#define __AP_DECL_H__
+
+// ----------------------------------------------------------------------
+
+#if !defined(__AP_FIXED_H__) && !defined(__AP_INT_H__) && !defined(__AUTOPILOT_CBE_H__) && !defined(__HLS_HALF_H__)
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+// Test __SYNTHESIS__ only for mode
+#if !defined(__SYNTHESIS__) && (defined(AESL_SYN) || defined(__HLS_SYN__))
+//#pragma message "AESL_SYN and __HLS_SYN__ should be replaced by __SYNTHESIS__"
+#define __SYNTHESIS__
+#endif
+
+/* for safety*/
+#if (defined(_AP_N) || defined(_AP_C))
+#error One or more of the following is defined: _AP_N, _AP_C. Definition conflicts with their usage as template parameters.
+#endif
+
+/* for safety*/
+#if (defined(_AP_W) || defined(_AP_I) || defined(_AP_S) || defined(_AP_Q) || \
+     defined(_AP_O) || defined(_AP_W2) || defined(_AP_I2) ||                 \
+     defined(_AP_S2) || defined(_AP_Q2) || defined(_AP_O2) ||                \
+     defined(_AP_N) || defined(_AP_N2))
+#error \
+    "One or more of the following is defined: _AP_W, _AP_I, _AP_S, _AP_Q, _AP_O,  _AP_N, _AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2. Definition conflicts with their usage as template parameters."
+#endif
+
+/*for safety*/
+#if (defined(_AP_W3) || defined(_AP_S3) || defined(_AP_W4) || defined(_AP_S4))
+#error \
+    "One or more of the following is defined: _AP_W3, _AP_S3, _AP_W4,_AP_S4. Definition conflicts with their usage as template parameters."
+#endif
+
+#if (defined(_AP_W1) || defined(_AP_S1) || defined(_AP_T) || \
+     defined(_AP_T1) || defined(_AP_T2) || defined(_AP_T3) || defined(_AP_T4))
+#error \
+    "One or more of the following is defined: _AP_W1, _AP_S1, _AP_T,  _AP_T1, _AP_T2, _AP_T3, _AP_T4. Definition conflicts with their usage as template parameters."
+#endif
+
+#ifndef __cplusplus
+#error "AP data type can only be used in C++"
+#endif
+
+// ----------------------------------------------------------------------
+
+#ifndef __SC_COMPATIBLE__
+/// ap_fixed quantification mode
+enum ap_q_mode {
+  AP_RND,         //< rounding to plus infinity
+  AP_RND_ZERO,    //< rounding to zero
+  AP_RND_MIN_INF, //< rounding to minus infinity
+  AP_RND_INF,     //< rounding to infinity
+  AP_RND_CONV,    //< convergent rounding
+  AP_TRN,         //< truncation
+  AP_TRN_ZERO,    //< truncation to zero
+};
+
+// FIXME for legacy code
+#ifndef SYSTEMC_INCLUDED
+#define SC_RND AP_RND
+#define SC_RND_ZERO AP_RND_ZERO
+#define SC_RND_MIN_INF AP_RND_MIN_INF
+#define SC_RND_INF AP_RND_INF
+#define SC_RND_CONV AP_RND_CONV
+#define SC_TRN AP_TRN
+#define SC_TRN_ZERO AP_TRN_ZERO
+#endif // !defined(SYSTEMC_INCLUDED)
+
+/// ap_fixed saturation mode
+enum ap_o_mode {
+  AP_SAT,      //< saturation
+  AP_SAT_ZERO, //< saturation to zero
+  AP_SAT_SYM,  //< symmetrical saturation
+  AP_WRAP,     //< wrap-around (*)
+  AP_WRAP_SM,  //< sign magnitude wrap-around (*)
+};
+
+// FIXME for legacy code
+#ifndef SYSTEMC_INCLUDED
+#define SC_SAT AP_SAT
+#define SC_SAT_ZERO AP_SAT_ZERO
+#define SC_SAT_SYM AP_SAT_SYM
+#define SC_WRAP AP_WRAP
+#define SC_WRAP_SM AP_WRAP_SM
+#endif // !defined(SYSTEMC_INCLUDED)
+
+#else // defined(__SC_COMPATIBLE__)
+
+// There will not be sc_fxdefs.h, and the emu should be defined by ap_fixed.
+
+/// ap_fixed quantification mode
+enum ap_q_mode {
+  SC_RND,         //< rounding to plus infinity
+  SC_RND_ZERO,    //< rounding to zero
+  SC_RND_MIN_INF, //< rounding to minus infinity
+  SC_RND_INF,     //< rounding to infinity
+  SC_RND_CONV,    //< convergent rounding
+  SC_TRN,         //< truncation
+  SC_TRN_ZERO,    //< truncation to zero
+};
+
+#define AP_RND SC_RND
+#define AP_RND_ZERO SC_RND_ZERO
+#define AP_RND_MIN_INF SC_RND_MIN_INF
+#define AP_RND_INF SC_RND_INF
+#define AP_RND_CONV SC_RND_CONV
+#define AP_TRN SC_TRN
+#define AP_TRN_ZERO SC_TRN_ZERO
+
+/// ap_fixed saturation mode
+enum ap_o_mode {
+  SC_SAT,      //< saturation
+  SC_SAT_ZERO, //< saturation to zero
+  SC_SAT_SYM,  //< symmetrical saturation
+  SC_WRAP,     //< wrap-around (*)
+  SC_WRAP_SM,  //< sign magnitude wrap-around (*)
+};
+
+#define AP_SAT SC_SAT
+#define AP_SAT_ZERO SC_SAT_ZERO
+#define AP_SAT_SYM SC_SAT_SYM
+#define AP_WRAP SC_WRAP
+#define AP_WRAP_SM SC_WRAP_SM
+
+#endif // defined(__SC_COMPATIBLE__)
+
+template <int _AP_W, bool _AP_S>
+struct ap_int_base;
+
+template <int _AP_W>
+struct ap_int;
+
+template <int _AP_W>
+struct ap_uint;
+
+template <int _AP_W, bool _AP_S>
+struct ap_range_ref;
+
+template <int _AP_W, bool _AP_S>
+struct ap_bit_ref;
+
+template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2>
+struct ap_concat_ref;
+
+template <int _AP_W, int _AP_I, bool _AP_S = true, ap_q_mode _AP_Q = AP_TRN,
+          ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+struct ap_fixed_base;
+
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q = AP_TRN,
+          ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+struct ap_fixed;
+
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q = AP_TRN,
+          ap_o_mode _AP_O = AP_WRAP, int _AP_N = 0>
+struct ap_ufixed;
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+struct af_range_ref;
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+struct af_bit_ref;
+
+/// string base mode
+enum BaseMode { AP_BIN = 2, AP_OCT = 8, AP_DEC = 10, AP_HEX = 16 };
+
+#ifndef SYSTEMC_INCLUDED
+#define SC_BIN 2
+#define SC_OCT 8
+#define SC_DEC 10
+#define SC_HEX 16
+#endif // !defined(SYSTEMC_INCLUDED)
+
+// Alias C data types
+#ifdef _MSC_VER
+typedef signed __int64 ap_slong;
+typedef unsigned __int64 ap_ulong;
+#else  // !defined(_MSC_VER)
+typedef signed long long ap_slong;
+typedef unsigned long long ap_ulong;
+#endif // !defined(_MSC_VER)
+
+enum {
+  _AP_SIZE_char = 8,
+  _AP_SIZE_short = sizeof(short) * 8,
+  _AP_SIZE_int = sizeof(int) * 8,
+  _AP_SIZE_long = sizeof(long) * 8,
+  _AP_SIZE_ap_slong = sizeof(ap_slong) * 8
+};
+
+#endif // !defined(__AP_DECL_H__)
+
+// -*- cpp -*-

firmware/ap_types/ap_fixed.h

@@ -0,0 +1,360 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_FIXED_H__
+#define __AP_FIXED_H__
+
+#include <ap_common.h>
+#include <ap_fixed_base.h>
+#include <ap_fixed_ref.h>
+
+//---------------------------------------------------------------
+
+/// Signed Arbitrary Precision Fixed-Point Type.
+// default for _AP_Q, _AP_O and _AP_N set in ap_decl.h
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+struct ap_fixed : ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> {
+  typedef ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> Base;
+  // Constructor
+  /// default ctor
+  INLINE ap_fixed() : Base() {}
+
+  /// default copy ctor
+  INLINE ap_fixed(const ap_fixed& op) { Base::V = op.V; }
+
+  /// copy ctor from ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+                                      _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed(const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+                                               _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  //// from ap_fixed
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_fixed(
+  //    const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_fixed(
+  //    const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+  //// from ap_ufixed.
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_fixed(
+  //    const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) {
+  //}
+
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_fixed(
+  //    const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) {
+  //}
+
+  /// copy ctor from ap_int_base.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed(const ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed(const volatile ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  //// from ap_int.
+  //template <int _AP_W2>
+  //INLINE ap_fixed(const ap_int<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, true>(op)) {}
+
+  //template <int _AP_W2>
+  //INLINE ap_fixed(const volatile ap_int<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, true>(op)) {}
+
+  //// from ap_uint.
+  //template <int _AP_W2>
+  //INLINE ap_fixed(const ap_uint<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, false>(op)) {}
+
+  //template <int _AP_W2>
+  //INLINE ap_fixed(const volatile ap_uint<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, false>(op)) {}
+
+  // from ap_bit_ref.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed(const ap_bit_ref<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  // from ap_range_ref.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed(const ap_range_ref<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  // from ap_concat_ref.
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_fixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op)
+      : Base(op) {}
+
+  // from af_bit_ref.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  // from af_range_ref.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+// from c types.
+#define CTOR(TYPE) \
+  INLINE ap_fixed(TYPE v) : Base(v) {}
+
+  CTOR(bool)
+  CTOR(char)
+  CTOR(signed char)
+  CTOR(unsigned char)
+  CTOR(short)
+  CTOR(unsigned short)
+  CTOR(int)
+  CTOR(unsigned int)
+  CTOR(long)
+  CTOR(unsigned long)
+  CTOR(ap_slong)
+  CTOR(ap_ulong)
+#if _AP_ENABLE_HALF_ == 1
+  CTOR(half)
+#endif
+  CTOR(float)
+  CTOR(double)
+#undef CTOR
+
+  INLINE ap_fixed(const char* s) : Base(s) {}
+
+  INLINE ap_fixed(const char* s, signed char rd) : Base(s, rd) {}
+
+  // Assignment
+  // The assignment operator is technically inherited; however, it is always
+  // hidden by an explicitly or implicitly defined assignment operator for the
+  // derived class.
+  /* XXX ctor will be used when right is not of proper type. */
+  INLINE ap_fixed& operator=(
+      const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) {
+    Base::V = op.V;
+    return *this;
+  }
+
+  INLINE void operator=(
+      const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) volatile {
+    Base::V = op.V;
+  }
+
+  INLINE ap_fixed& operator=(
+      const volatile ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) {
+    Base::V = op.V;
+    return *this;
+  }
+
+  INLINE void operator=(
+      const volatile ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) volatile {
+    Base::V = op.V;
+  }
+}; // struct ap_fixed.
+
+//-------------------------------------------------------------------
+
+// Unsigned Arbitrary Precision Fixed-Point Type.
+// default for _AP_Q, _AP_O and _AP_N set in ap_decl.h
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+struct ap_ufixed : ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> {
+  typedef ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N> Base;
+  // Constructor
+  /// default ctor
+  INLINE ap_ufixed() : Base() {}
+
+  /// default copy ctor
+  INLINE ap_ufixed(const ap_ufixed& op) { Base::V = op.V; }
+
+  /// copy ctor from ap_fixed_base
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_ufixed(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+                                       _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  /// copy ctor from ap_fixed_base
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_ufixed(const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2,
+                                                _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_ufixed(
+  //    const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_ufixed(
+  //    const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>(op)) {}
+
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_ufixed(
+  //    const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) {
+  //}
+
+  //template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+  //          int _AP_N2>
+  //INLINE ap_ufixed(
+  //    const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+  //    : Base(ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>(op)) {
+  //}
+
+  /// copy ctor from ap_int_base.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_ufixed(const ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_ufixed(const volatile ap_int_base<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  //template <int _AP_W2>
+  //INLINE ap_ufixed(const ap_int<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, true>(op)) {}
+
+  //template <int _AP_W2>
+  //INLINE ap_ufixed(const volatile ap_int<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, true>(op)) {}
+
+  //template <int _AP_W2>
+  //INLINE ap_ufixed(const ap_uint<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, false>(op)) {}
+
+  //template <int _AP_W2>
+  //INLINE ap_ufixed(const volatile ap_uint<_AP_W2>& op)
+  //    : Base(ap_int_base<_AP_W2, false>(op)) {}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_ufixed(const ap_bit_ref<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_ufixed(const ap_range_ref<_AP_W2, _AP_S2>& op) : Base(op) {}
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_ufixed(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_ufixed(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_ufixed(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+#define CTOR(TYPE) \
+  INLINE ap_ufixed(TYPE v) : Base(v) {}
+
+  CTOR(bool)
+  CTOR(char)
+  CTOR(signed char)
+  CTOR(unsigned char)
+  CTOR(short)
+  CTOR(unsigned short)
+  CTOR(int)
+  CTOR(unsigned int)
+  CTOR(long)
+  CTOR(unsigned long)
+  CTOR(ap_slong)
+  CTOR(ap_ulong)
+#if _AP_ENABLE_HALF_ == 1
+  CTOR(half)
+#endif
+  CTOR(float)
+  CTOR(double)
+#undef CTOR
+
+  INLINE ap_ufixed(const char* s) : Base(s) {}
+
+  INLINE ap_ufixed(const char* s, signed char rd) : Base(s, rd) {}
+
+  // Assignment
+  INLINE ap_ufixed& operator=(
+      const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) {
+    Base::V = op.V;
+    return *this;
+  }
+
+  INLINE void operator=(
+      const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) volatile {
+    Base::V = op.V;
+  }
+
+  INLINE ap_ufixed& operator=(
+      const volatile ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op) {
+    Base::V = op.V;
+    return *this;
+  }
+
+  INLINE void operator=(const volatile ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O,
+                                                 _AP_N>& op) volatile {
+    Base::V = op.V;
+  }
+}; // struct ap_ufixed
+
+
+#if !defined(__SYNTHESIS__) && (defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED))
+// XXX sc_trace overload for ap_fixed is already included in
+// "ap_sysc/ap_sc_extras.h", so do not define in synthesis.
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void sc_trace(sc_core::sc_trace_file* tf,
+                     const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op,
+                     const std::string& name) {
+  tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE void sc_trace(sc_core::sc_trace_file* tf,
+                     const ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>& op,
+                     const std::string& name) {
+  tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+#endif // System C sim
+
+// Specialization of std containers, so that std::complex<ap_fixed> can have its
+// image part automatically zero-initialized when only real part is provided.
+#include <ap_fixed_special.h>
+
+#endif // ifndef __AP_FIXED_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_fixed_base.h

@@ -0,0 +1,2354 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_FIXED_BASE_H__
+#define __AP_FIXED_BASE_H__
+
+#ifndef __AP_FIXED_H__
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+// for ap_int_base and its reference types.
+#include <ap_int.h>
+#ifndef __SYNTHESIS__
+#if _AP_ENABLE_HALF_ == 1
+// for half type
+#include <hls_half.h>
+#endif
+// for std io
+#include <iostream>
+#endif
+
+#ifndef __cplusplus
+#error "C++ is required to include this header file"
+#else // __cplusplus
+
+// for warning on unsupported rounding mode in conversion to float/double.
+#if !defined(__SYNTHESIS__) && __cplusplus >= 201103L && \
+    (defined(__gnu_linux__) || defined(_WIN32))
+#define AP_FIXED_ENABLE_CPP_FENV 1
+#include <cfenv>
+#endif
+
+// ----------------------------------------------------------------------
+
+/* Major TODO
+  long double support: constructor, assign and other operators.
+  binary operators with ap_fixed_base and const char*.
+  return ap_fixed/ap_ufixed when result signedness is known.
+*/
+
+// Helper function in conversion to floating point types.
+
+#ifdef __SYNTHESIS__
+#define _AP_ctype_op_get_bit(var, index) _AP_ROOT_op_get_bit(var, index)
+#define _AP_ctype_op_set_bit(var, index, x) _AP_ROOT_op_set_bit(var, index, x)
+#define _AP_ctype_op_get_range(var, low, high) \
+  _AP_ROOT_op_get_range(var, low, high)
+#define _AP_ctype_op_set_range(var, low, high, x) \
+  _AP_ROOT_op_set_range(var, low, high, x)
+#else // ifdef __SYNTHESIS__
+template <typename _Tp1, typename _Tp2>
+inline bool _AP_ctype_op_get_bit(_Tp1& var, const _Tp2& index) {
+  return !!(var & (1ull << (index)));
+}
+template <typename _Tp1, typename _Tp2, typename _Tp3>
+inline _Tp1 _AP_ctype_op_set_bit(_Tp1& var, const _Tp2& index, const _Tp3& x) {
+  var |= (((x) ? 1ull : 0ull) << (index));
+  return var;
+}
+template <typename _Tp1, typename _Tp2, typename _Tp3>
+inline _Tp1 _AP_ctype_op_get_range(_Tp1& var, const _Tp2& low,
+                                   const _Tp3& high) {
+  _Tp1 r = var;
+  ap_ulong mask = -1ll;
+  mask >>= (sizeof(_Tp1) * 8 - ((high) - (low) + 1));
+  r >>= (low);
+  r &= mask;
+  return r;
+}
+template <typename _Tp1, typename _Tp2, typename _Tp3, typename _Tp4>
+inline _Tp1 _AP_ctype_op_set_range(_Tp1& var, const _Tp2& low, const _Tp3& high,
+                                   const _Tp4& x) {
+  ap_ulong mask = -1ll;
+  mask >>= (_AP_SIZE_ap_slong - ((high) - (low) + 1));
+  var &= ~(mask << (low));
+  var |= ((mask & x) << (low));
+  return var;
+}
+#endif // ifdef __SYNTHESIS__
+
+
+// trait for letting base class to return derived class.
+// Notice that derived class template is incomplete, and we cannot use
+// the member of the derived class.
+template <int _AP_W2, int _AP_I2, bool _AP_S2>
+struct _ap_fixed_factory;
+template <int _AP_W2, int _AP_I2>
+struct _ap_fixed_factory<_AP_W2, _AP_I2, true> {
+  typedef ap_fixed<_AP_W2, _AP_I2> type;
+};
+template <int _AP_W2, int _AP_I2>
+struct _ap_fixed_factory<_AP_W2, _AP_I2, false> {
+  typedef ap_ufixed<_AP_W2, _AP_I2> type;
+};
+
+/// ap_fixed_base: AutoPilot fixed point.
+/** partial specialization of signed.
+  @tparam _AP_W width.
+  @tparam _AP_I integral part width.
+  @tparam _AP_S signed.
+  @tparam _AP_Q quantization mode. Default is AP_TRN.
+  @tparam _AP_O saturation mode. Default is AP_WRAP.
+  @tparam _AP_N saturation wrap value. Default is 0.
+ */
+// default for _AP_Q, _AP_O and _AP_N set in ap_decl.h
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+struct ap_fixed_base : _AP_ROOT_TYPE<_AP_W, _AP_S> {
+ public:
+  typedef _AP_ROOT_TYPE<_AP_W, _AP_S> Base;
+  static const int width = _AP_W;
+  static const int iwidth = _AP_I;
+  static const ap_q_mode qmode = _AP_Q;
+  static const ap_o_mode omode = _AP_O;
+
+  /// Return type trait.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2>
+  struct RType {
+    enum {
+      _AP_F = _AP_W - _AP_I,
+      F2 = _AP_W2 - _AP_I2,
+      mult_w = _AP_W + _AP_W2,
+      mult_i = _AP_I + _AP_I2,
+      mult_s = _AP_S || _AP_S2,
+      plus_w = AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) +
+               1 + AP_MAX(_AP_F, F2),
+      plus_i =
+          AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + 1,
+      plus_s = _AP_S || _AP_S2,
+      minus_w =
+          AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + 1 +
+          AP_MAX(_AP_F, F2),
+      minus_i =
+          AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) + 1,
+      minus_s = true,
+#ifndef __SC_COMPATIBLE__
+      div_w = _AP_S2 + _AP_W + AP_MAX(F2, 0),
+#else
+      div_w = _AP_S2 + _AP_W + AP_MAX(F2, 0) + AP_MAX(_AP_I2, 0),
+#endif
+      div_i = _AP_S2 + _AP_I + F2,
+      div_s = _AP_S || _AP_S2,
+      logic_w =
+          AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)) +
+          AP_MAX(_AP_F, F2),
+      logic_i = AP_MAX(_AP_I + (_AP_S2 && !_AP_S), _AP_I2 + (_AP_S && !_AP_S2)),
+      logic_s = _AP_S || _AP_S2
+    };
+
+    typedef ap_fixed_base<_AP_W, _AP_I, _AP_S> lhs;
+    typedef ap_fixed_base<_AP_W2, _AP_I2, _AP_S2> rhs;
+
+    typedef ap_fixed_base<mult_w, mult_i, mult_s> mult_base;
+    typedef ap_fixed_base<plus_w, plus_i, plus_s> plus_base;
+    typedef ap_fixed_base<minus_w, minus_i, minus_s> minus_base;
+    typedef ap_fixed_base<logic_w, logic_i, logic_s> logic_base;
+    typedef ap_fixed_base<div_w, div_i, div_s> div_base;
+    typedef ap_fixed_base<_AP_W, _AP_I, _AP_S> arg1_base;
+
+    typedef typename _ap_fixed_factory<mult_w, mult_i, mult_s>::type mult;
+    typedef typename _ap_fixed_factory<plus_w, plus_i, plus_s>::type plus;
+    typedef typename _ap_fixed_factory<minus_w, minus_i, minus_s>::type minus;
+    typedef typename _ap_fixed_factory<logic_w, logic_i, logic_s>::type logic;
+    typedef typename _ap_fixed_factory<div_w, div_i, div_s>::type div;
+    typedef typename _ap_fixed_factory<_AP_W, _AP_I, _AP_S>::type arg1;
+  };
+
+ private:
+#ifndef __SYNTHESIS__
+  // This cannot handle hex float format string.
+  void fromString(const std::string& val, unsigned char radix) {
+    _AP_ERROR(!(radix == 2 || radix == 8 || radix == 10 || radix == 16),
+              "ap_fixed_base::fromString(%s, %d)", val.c_str(), radix);
+
+    Base::V = 0;
+    int startPos = 0;
+    int endPos = val.length();
+    int decPos = val.find(".");
+    if (decPos == -1) decPos = endPos;
+
+    // handle sign
+    bool isNegative = false;
+    if (val[0] == '-') {
+      isNegative = true;
+      ++startPos;
+    } else if (val[0] == '+')
+      ++startPos;
+
+    // If there are no integer bits, e.g.:
+    // .0000XXXX, then keep at least one bit.
+    // If the width is greater than the number of integer bits, e.g.:
+    // XXXX.XXXX, then we keep the integer bits
+    // if the number of integer bits is greater than the width, e.g.:
+    // XXX000 then we keep the integer bits.
+    // Always keep one bit.
+    ap_fixed_base<AP_MAX(_AP_I, 4) + 4, AP_MAX(_AP_I, 4) + 4, false>
+        integer_bits = 0;
+
+    // Figure out if we can shift instead of multiply
+    unsigned shift = (radix == 16 ? 4 : radix == 8 ? 3 : radix == 2 ? 1 : 0);
+
+    //std::cout << "\n\n" << val << "\n";
+    //std::cout << startPos << " " << decPos << " " << endPos << "\n";
+
+    bool sticky_int = false;
+
+    // Traverse the integer digits from the MSD, multiplying by radix as we go.
+    for (int i = startPos; i < decPos; i++) {
+      // Get a digit
+      char cdigit = val[i];
+      if (cdigit == '\0') continue;
+      unsigned digit = ap_private_ops::decode_digit(cdigit, radix);
+
+      sticky_int |= integer_bits[AP_MAX(_AP_I, 4) + 4 - 1] |
+                    integer_bits[AP_MAX(_AP_I, 4) + 4 - 2] |
+                    integer_bits[AP_MAX(_AP_I, 4) + 4 - 3] |
+                    integer_bits[AP_MAX(_AP_I, 4) + 4 - 4];
+      // Shift or multiply the value by the radix
+      if (shift)
+        integer_bits <<= shift;
+      else
+        integer_bits *= radix;
+
+      // Add in the digit we just interpreted
+      integer_bits += digit;
+      //std::cout << "idigit = " << digit << " " << integer_bits.to_string()
+      //    << "  " << sticky_int <<  "\n";
+    }
+    integer_bits[AP_MAX(_AP_I, 4) + 4 - 3] =
+        integer_bits[AP_MAX(_AP_I, 4) + 4 - 3] | sticky_int;
+
+    ap_fixed_base<AP_MAX(_AP_W - _AP_I, 0) + 4 + 4, 4, false> fractional_bits = 0;
+    bool sticky = false;
+
+    // Traverse the fractional digits from the LSD, dividing by radix as we go.
+    for (int i = endPos - 1; i >= decPos + 1; i--) {
+      // Get a digit
+      char cdigit = val[i];
+      if (cdigit == '\0') continue;
+      unsigned digit = ap_private_ops::decode_digit(cdigit, radix);
+      // Add in the digit we just interpreted
+      fractional_bits += digit;
+
+      sticky |= fractional_bits[0] | fractional_bits[1] | fractional_bits[2] |
+                fractional_bits[3];
+      // Shift or divide the value by the radix
+      if (shift)
+        fractional_bits >>= shift;
+      else
+        fractional_bits /= radix;
+
+      //std::cout << "fdigit = " << digit << " " << fractional_bits.to_string()
+      //    << " " << sticky << "\n";
+    }
+
+    //std::cout << "Int =" << integer_bits.to_string() << " " <<
+    //    fractional_bits.to_string() << "\n";
+
+    fractional_bits[0] = fractional_bits[0] | sticky;
+
+    if (isNegative)
+      *this = -(integer_bits + fractional_bits);
+    else
+      *this = integer_bits + fractional_bits;
+
+    //std::cout << "end = " << this->to_string(16) << "\n";
+  }
+
+  /// report invalid constrction of ap_fixed_base
+  INLINE void report() {
+    if (!_AP_S && _AP_O == AP_WRAP_SM) {
+      fprintf(stderr, "ap_ufxied<...> cannot support AP_WRAP_SM.\n");
+      exit(1);
+    }
+    if (_AP_W > MAX_MODE(AP_INT_MAX_W) * 1024) {
+      fprintf(stderr,
+              "[E] ap_%sfixed<%d, ...>: Bitwidth exceeds the "
+              "default max value %d. Please use macro "
+              "AP_INT_MAX_W to set a larger max value.\n",
+              _AP_S ? "" : "u", _AP_W, MAX_MODE(AP_INT_MAX_W) * 1024);
+      exit(1);
+    }
+  }
+#else
+  INLINE void report() {}
+#endif // ifdef __SYNTHESIS__
+
+  /// @name helper functions.
+  //  @{
+  INLINE void overflow_adjust(bool underflow, bool overflow, bool lD,
+                              bool sign) {
+    if (!underflow && !overflow) return;
+    if (_AP_O == AP_WRAP) {
+      if (_AP_N == 0) return;
+      if (_AP_S) {
+        // signed AP_WRAP
+        // n_bits == 1
+        Base::V = _AP_ROOT_op_set_bit(Base::V, _AP_W - 1, sign);
+        if (_AP_N > 1) {
+          // n_bits > 1
+          ap_int_base<_AP_W, false> mask(-1);
+          if (sign) mask.V = 0;
+          Base::V =
+              _AP_ROOT_op_set_range(Base::V, _AP_W - _AP_N, _AP_W - 2, mask.V);
+        }
+      } else {
+        // unsigned AP_WRAP
+        ap_int_base<_AP_W, false> mask(-1);
+        Base::V =
+            _AP_ROOT_op_set_range(Base::V, _AP_W - _AP_N, _AP_W - 1, mask.V);
+      }
+    } else if (_AP_O == AP_SAT_ZERO) {
+      Base::V = 0;
+    } else if (_AP_O == AP_WRAP_SM && _AP_S) {
+      bool Ro = _AP_ROOT_op_get_bit(Base::V, _AP_W - 1);
+      if (_AP_N == 0) {
+        if (lD != Ro) {
+          Base::V = ~Base::V;
+          Base::V = _AP_ROOT_op_set_bit(Base::V, _AP_W - 1, lD);
+        }
+      } else {
+        if (_AP_N == 1 && sign != Ro) {
+          Base::V = ~Base::V;
+        } else if (_AP_N > 1) {
+          bool lNo = _AP_ROOT_op_get_bit(Base::V, _AP_W - _AP_N);
+          if (lNo == sign) Base::V = ~Base::V;
+          ap_int_base<_AP_W, false> mask(-1);
+          if (sign) mask.V = 0;
+          Base::V =
+              _AP_ROOT_op_set_range(Base::V, _AP_W - _AP_N, _AP_W - 2, mask.V);
+        }
+        Base::V = _AP_ROOT_op_set_bit(Base::V, _AP_W - 1, sign);
+      }
+    } else {
+      if (_AP_S) {
+        if (overflow) {
+          Base::V = 1;
+          Base::V <<= _AP_W - 1;
+          Base::V = ~Base::V;
+        } else if (underflow) {
+          Base::V = 1;
+          Base::V <<= _AP_W - 1;
+          if (_AP_O == AP_SAT_SYM) Base::V |= 1;
+        }
+      } else {
+        if (overflow)
+          Base::V = ~(ap_int_base<_AP_W, false>(0).V);
+        else if (underflow)
+          Base::V = 0;
+      }
+    }
+  }
+
+  INLINE bool quantization_adjust(bool qb, bool r, bool s) {
+    bool carry = (bool)_AP_ROOT_op_get_bit(Base::V, _AP_W - 1);
+    if (_AP_Q == AP_TRN) return false;
+    if (_AP_Q == AP_RND_ZERO)
+      qb &= s || r;
+    else if (_AP_Q == AP_RND_MIN_INF)
+      qb &= r;
+    else if (_AP_Q == AP_RND_INF)
+      qb &= !s || r;
+    else if (_AP_Q == AP_RND_CONV)
+      qb &= _AP_ROOT_op_get_bit(Base::V, 0) || r;
+    else if (_AP_Q == AP_TRN_ZERO)
+      qb = s && (qb || r);
+    Base::V += qb;
+    return carry && (!(bool)_AP_ROOT_op_get_bit(Base::V, _AP_W - 1));
+  }
+  //  @}
+
+ public:
+  /// @name constructors.
+  //  @{
+  /// default ctor.
+  INLINE ap_fixed_base() {}
+
+  /// copy ctor.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    operator=(op);
+    report();
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base(
+      const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    operator=(op);
+    report();
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed_base(const ap_int_base<_AP_W2, _AP_S2>& op) {
+    ap_fixed_base<_AP_W2, _AP_W2, _AP_S2> tmp;
+    tmp.V = op.V;
+    operator=(tmp);
+    report();
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed_base(const volatile ap_int_base<_AP_W2, _AP_S2>& op) {
+    ap_fixed_base<_AP_W2, _AP_W2, _AP_S2> tmp;
+    tmp.V = op.V;
+    operator=(tmp);
+    report();
+  }
+
+#ifndef __SYNTHESIS__
+#ifndef NON_C99STRING
+  INLINE ap_fixed_base(const char* s, signed char rd = 0) {
+    unsigned char radix = rd;
+    std::string str = ap_private_ops::parseString(s, radix); // will guess rd, default 10
+    _AP_ERROR(radix == 0, "ap_fixed_base(const char* \"%s\", %d), str=%s, radix = %d",
+              s, rd, str.c_str(), radix); // TODO remove this check
+    fromString(str, radix);
+  }
+#else
+  INLINE ap_fixed_base(const char* s, signed char rd = 10) {
+    ap_int_base<_AP_W, _AP_S> t(s, rd);
+    Base::V = t.V;
+  }
+#endif // ifndef NON_C99STRING
+#else // ifndef __SYNTHESIS__
+  // XXX _ssdm_string2bits only takes const string and const radix.
+  // It seems XFORM will do compile time processing of the string.
+  INLINE ap_fixed_base(const char* s) {
+    typeof(Base::V) t;
+    _ssdm_string2bits((void*)(&t), (const char*)(s), 10, _AP_I, _AP_S, _AP_Q,
+                      _AP_O, _AP_N, _AP_C99);
+    Base::V = t;
+  }
+  INLINE ap_fixed_base(const char* s, signed char rd) {
+    typeof(Base::V) t;
+    _ssdm_string2bits((void*)(&t), (const char*)(s), rd, _AP_I, _AP_S, _AP_Q,
+                      _AP_O, _AP_N, _AP_C99);
+    Base::V = t;
+  }
+#endif // ifndef __SYNTHESIS__ else
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed_base(const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+    *this = ((bool)op);
+    report();
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed_base(const ap_range_ref<_AP_W2, _AP_S2>& op) {
+    *this = (ap_int_base<_AP_W2, false>(op));
+    report();
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_fixed_base(
+      const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op) {
+    *this = (ap_int_base<_AP_W2 + _AP_W3, false>(op));
+    report();
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    *this = (bool(op));
+    report();
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    *this = (ap_int_base<_AP_W2, false>(op));
+    report();
+  }
+
+  // ctors from c types.
+  // make a temp ap_fixed_base first, and use ap_fixed_base.operator=
+#define CTOR_FROM_INT(C_TYPE, _AP_W2, _AP_S2)        \
+  INLINE ap_fixed_base(const C_TYPE x) {             \
+    ap_fixed_base<(_AP_W2), (_AP_W2), (_AP_S2)> tmp; \
+    tmp.V = x;                                       \
+    *this = tmp;                                     \
+  }
+
+  CTOR_FROM_INT(bool, 1, false)
+  CTOR_FROM_INT(char, 8, CHAR_IS_SIGNED)
+  CTOR_FROM_INT(signed char, 8, true)
+  CTOR_FROM_INT(unsigned char, 8, false)
+  CTOR_FROM_INT(short, _AP_SIZE_short, true)
+  CTOR_FROM_INT(unsigned short, _AP_SIZE_short, false)
+  CTOR_FROM_INT(int, _AP_SIZE_int, true)
+  CTOR_FROM_INT(unsigned int, _AP_SIZE_int, false)
+  CTOR_FROM_INT(long, _AP_SIZE_long, true)
+  CTOR_FROM_INT(unsigned long, _AP_SIZE_long, false)
+  CTOR_FROM_INT(ap_slong, _AP_SIZE_ap_slong, true)
+  CTOR_FROM_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+#undef CTOR_FROM_INT
+/*
+ * TODO:
+ *Theere used to be several funtions which were AP_WEAK.
+ *Now they're all INLINE expect ap_fixed_base(double d)
+ *Maybe we can use '#pragma HLS inline' instead of INLINE.
+ */
+  AP_WEAK ap_fixed_base(double d) {
+    ap_int_base<64, false> ireg;
+    ireg.V = doubleToRawBits(d);
+    bool isneg = _AP_ROOT_op_get_bit(ireg.V, 63);
+
+    ap_int_base<DOUBLE_EXP + 1, true> exp;
+    ap_int_base<DOUBLE_EXP, false> exp_tmp;
+    exp_tmp.V =
+        _AP_ROOT_op_get_range(ireg.V, DOUBLE_MAN, DOUBLE_MAN + DOUBLE_EXP - 1);
+    exp = exp_tmp - DOUBLE_BIAS;
+    ap_int_base<DOUBLE_MAN + 2, true> man;
+    man.V = _AP_ROOT_op_get_range(ireg.V, 0, DOUBLE_MAN - 1);
+    // do not support NaN
+    _AP_WARNING(exp == APFX_IEEE_DOUBLE_E_MAX + 1 && man.V != 0,
+                "assign NaN to fixed point value");
+    man.V = _AP_ROOT_op_set_bit(man.V, DOUBLE_MAN, 1);
+    if (isneg) man = -man;
+    if ((ireg.V & 0x7fffffffffffffffLL) == 0) {
+      Base::V = 0;
+    } else {
+      int _AP_W2 = DOUBLE_MAN + 2, _AP_I2 = exp.V + 2, _AP_F = _AP_W - _AP_I,
+          F2 = _AP_W2 - _AP_I2;
+      bool _AP_S2 = true,
+           QUAN_INC = F2 > _AP_F &&
+                      !(_AP_Q == AP_TRN || (_AP_Q == AP_TRN_ZERO && !_AP_S2));
+      bool carry = false;
+      // handle quantization
+      unsigned sh_amt = (F2 > _AP_F) ? F2 - _AP_F : _AP_F - F2;
+      if (F2 == _AP_F)
+        Base::V = man.V;
+      else if (F2 > _AP_F) {
+        if (sh_amt < DOUBLE_MAN + 2)
+          Base::V = man.V >> sh_amt;
+        else {
+          Base::V = isneg ? -1 : 0;
+        }
+        if ((_AP_Q != AP_TRN) && !((_AP_Q == AP_TRN_ZERO) && !_AP_S2)) {
+          bool qb = (F2 - _AP_F > _AP_W2) ? isneg : (bool)_AP_ROOT_op_get_bit(
+                                                        man.V, F2 - _AP_F - 1);
+          bool r =
+              (F2 > _AP_F + 1)
+                  ? _AP_ROOT_op_get_range(man.V, 0, (F2 - _AP_F - 2 < _AP_W2)
+                                                        ? (F2 - _AP_F - 2)
+                                                        : (_AP_W2 - 1)) != 0
+                  : false;
+          carry = quantization_adjust(qb, r, isneg);
+        }
+      } else { // no quantization
+        Base::V = man.V;
+        if (sh_amt < _AP_W)
+          Base::V = Base::V << sh_amt;
+        else
+          Base::V = 0;
+      }
+      // handle overflow/underflow
+      if ((_AP_O != AP_WRAP || _AP_N != 0) &&
+          ((!_AP_S && _AP_S2) ||
+           _AP_I - _AP_S <
+               _AP_I2 - _AP_S2 +
+                   (QUAN_INC ||
+                    (_AP_S2 && (_AP_O == AP_SAT_SYM))))) { // saturation
+        bool deleted_zeros = _AP_S2 ? true : !carry, deleted_ones = true;
+        bool neg_src = isneg;
+        bool lD = false;
+        int pos1 = F2 - _AP_F + _AP_W;
+        int pos2 = F2 - _AP_F + _AP_W + 1;
+        bool newsignbit = _AP_ROOT_op_get_bit(Base::V, _AP_W - 1);
+        if (pos1 < _AP_W2 && pos1 >= 0)
+          // lD = _AP_ROOT_op_get_bit(man.V, pos1);
+          lD = (man.V >> pos1) & 1;
+        if (pos1 < _AP_W2) {
+          bool Range1_all_ones = true;
+          bool Range1_all_zeros = true;
+          bool Range2_all_ones = true;
+          ap_int_base<DOUBLE_MAN + 2, false> Range2;
+          ap_int_base<DOUBLE_MAN + 2, false> all_ones(-1);
+
+          if (pos2 >= 0 && pos2 < _AP_W2) {
+            // Range2.V = _AP_ROOT_op_get_range(man.V,
+            //                        pos2, _AP_W2 - 1);
+            Range2.V = man.V;
+            Range2.V >>= pos2;
+            Range2_all_ones = Range2 == (all_ones >> pos2);
+          } else if (pos2 < 0)
+            Range2_all_ones = false;
+          if (pos1 >= 0 && pos2 < _AP_W2) {
+            Range1_all_ones = Range2_all_ones && lD;
+            Range1_all_zeros = !Range2.V && !lD;
+          } else if (pos2 == _AP_W2) {
+            Range1_all_ones = lD;
+            Range1_all_zeros = !lD;
+          } else if (pos1 < 0) {
+            Range1_all_zeros = !man.V;
+            Range1_all_ones = false;
+          }
+
+          deleted_zeros =
+              deleted_zeros && (carry ? Range1_all_ones : Range1_all_zeros);
+          deleted_ones =
+              carry ? Range2_all_ones && (pos1 < 0 || !lD) : Range1_all_ones;
+          neg_src = isneg && !(carry && Range1_all_ones);
+        } else
+          neg_src = isneg && newsignbit;
+        bool neg_trg = _AP_S && newsignbit;
+        bool overflow = (neg_trg || !deleted_zeros) && !isneg;
+        bool underflow = (!neg_trg || !deleted_ones) && neg_src;
+        if ((_AP_O == AP_SAT_SYM) && _AP_S2 && _AP_S)
+          underflow |=
+              neg_src &&
+              (_AP_W > 1 ? _AP_ROOT_op_get_range(Base::V, 0, _AP_W - 2) == 0
+                         : true);
+        overflow_adjust(underflow, overflow, lD, neg_src);
+      }
+    }
+    report();
+  }
+
+  // TODO more optimized implementation.
+  INLINE ap_fixed_base(float d) { *this = ap_fixed_base(double(d)); }
+
+#if _AP_ENABLE_HALF_ == 1
+  // TODO more optimized implementation.
+  INLINE ap_fixed_base(half d) { *this = ap_fixed_base(double(d)); }
+#endif
+  //  @}
+
+  /// @name assign operator
+  /// assign, using another ap_fixed_base of same template parameters.
+  /*
+  INLINE ap_fixed_base& operator=(
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {
+    Base::V = op.V;
+    return *this;
+  }
+  */
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base& operator=(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+
+    const int _AP_F = _AP_W - _AP_I;
+    const int F2 = _AP_W2 - _AP_I2;
+    const int QUAN_INC =
+          F2 > _AP_F && !(_AP_Q == AP_TRN || (_AP_Q == AP_TRN_ZERO && !_AP_S2));
+
+    if (!op) Base::V = 0;
+    bool carry = false;
+    bool signbit = _AP_ROOT_op_get_bit(op.V, _AP_W2 - 1);
+    bool isneg = signbit && _AP_S2;
+    if (F2 == _AP_F)
+      Base::V = op.V;
+    else if (F2 > _AP_F) {
+      unsigned int sh_amt = F2 - _AP_F;
+      //  moves bits right, handle quantization.
+      if (sh_amt < _AP_W2) {
+        Base::V = op.V >> sh_amt;
+      } else {
+        Base::V = isneg ? -1 : 0;
+      }
+      if (_AP_Q != AP_TRN && !(_AP_Q == AP_TRN_ZERO && !_AP_S2)) {
+        bool qbit = _AP_ROOT_op_get_bit(op.V, F2 - _AP_F - 1);
+        // bit after LSB.
+        bool qb = (F2 - _AP_F > _AP_W2) ? _AP_S2 && signbit : qbit;
+        enum { hi = ((F2 - _AP_F - 2) < _AP_W2) ? (F2 - _AP_F - 2) : (_AP_W2 - 1) };
+        // bits after qb.
+        bool r = (F2 > _AP_F + 1) ? (_AP_ROOT_op_get_range(op.V, 0, hi) != 0) : false;
+        carry = quantization_adjust(qb, r, isneg);
+      }
+    } else {
+      unsigned  sh_amt = _AP_F - F2;
+      // moves bits left, no quantization
+      if (sh_amt < _AP_W) {
+        if (_AP_W > _AP_W2) {
+          // extend and then shift, avoid losing bits.
+          Base::V = op.V;
+          Base::V <<= sh_amt;
+        } else {
+          // shift and truncate.
+          Base::V = op.V << sh_amt;
+        }
+      } else {
+        Base::V = 0;
+      }
+    }
+    // handle overflow/underflow
+    if ((_AP_O != AP_WRAP || _AP_N != 0) &&
+        ((!_AP_S && _AP_S2) ||
+         _AP_I - _AP_S <
+             _AP_I2 - _AP_S2 +
+                 (QUAN_INC || (_AP_S2 && _AP_O == AP_SAT_SYM)))) { // saturation
+      bool deleted_zeros = _AP_S2 ? true : !carry;
+      bool deleted_ones = true;
+      bool neg_src = isneg;
+      bool newsignbit = _AP_ROOT_op_get_bit(Base::V, _AP_W - 1);
+      enum { pos1 = F2 - _AP_F + _AP_W, pos2 = F2 - _AP_F + _AP_W + 1 };
+      bool lD = (pos1 < _AP_W2 && pos1 >= 0) ? _AP_ROOT_op_get_bit(op.V, pos1)
+                                             : false;
+      if (pos1 < _AP_W2) {
+        bool Range1_all_ones = true;
+        bool Range1_all_zeros = true;
+        bool Range2_all_ones = true;
+        ap_int_base<_AP_W2, false> all_ones(-1);
+
+        if (pos2 < _AP_W2 && pos2 >= 0) {
+          ap_int_base<_AP_W2, false> Range2;
+          Range2.V = _AP_ROOT_op_get_range(op.V, pos2, _AP_W2 - 1);
+          Range2_all_ones = Range2 == (all_ones >> pos2);
+        } else if (pos2 < 0) {
+          Range2_all_ones = false;
+        }
+
+        if (pos1 >= 0 && pos2 < _AP_W2) {
+          ap_int_base<_AP_W2, false> Range1;
+          Range1.V = _AP_ROOT_op_get_range(op.V, pos1, _AP_W2 - 1);
+          Range1_all_ones = Range1 == (all_ones >> pos1);
+          Range1_all_zeros = !Range1.V;
+        } else if (pos2 == _AP_W2) {
+          Range1_all_ones = lD;
+          Range1_all_zeros = !lD;
+        } else if (pos1 < 0) {
+          Range1_all_zeros = !op.V;
+          Range1_all_ones = false;
+        }
+
+        deleted_zeros =
+            deleted_zeros && (carry ? Range1_all_ones : Range1_all_zeros);
+        deleted_ones =
+            carry ? Range2_all_ones && (pos1 < 0 || !lD) : Range1_all_ones;
+        neg_src = isneg && !(carry && Range1_all_ones);
+      } else
+        neg_src = isneg && newsignbit;
+      bool neg_trg = _AP_S && newsignbit;
+      bool overflow = (neg_trg || !deleted_zeros) && !isneg;
+      bool underflow = (!neg_trg || !deleted_ones) && neg_src;
+      if ((_AP_O == AP_SAT_SYM) && _AP_S2 && _AP_S)
+        underflow |=
+            neg_src &&
+            (_AP_W > 1 ? _AP_ROOT_op_get_range(Base::V, 0, _AP_W - 2) == 0
+                       : true);
+
+      overflow_adjust(underflow, overflow, lD, neg_src);
+    }
+    return *this;
+  } // operator= 
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base& operator=(
+      const volatile ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    operator=(const_cast<const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(op));
+    return *this;
+  }
+
+  /// Set this ap_fixed_base with ULL.
+  INLINE ap_fixed_base& setBits(ap_ulong bv) {
+    // TODO when ull is not be long enough...
+    Base::V = bv;
+    return *this;
+  }
+
+  /// Return a ap_fixed_base object whose this->V is assigned by bv.
+  static INLINE ap_fixed_base bitsToFixed(ap_ulong bv) {
+    // TODO fix when ull is not be long enough...
+    ap_fixed_base t;
+#ifdef __SYNTHESIS__
+    t.V = bv;
+#else
+    t.V.set_bits(bv);
+#endif
+    return t;
+  }
+
+  // Explicit conversion functions to ap_int_base.
+  /** Captures all integer bits, in truncate mode.
+   *  @param[in] Cnative follow conversion from double to int.
+   */
+  INLINE ap_int_base<AP_MAX(_AP_I, 1), _AP_S> to_ap_int_base(
+      bool Cnative = true) const {
+    ap_int_base<AP_MAX(_AP_I, 1), _AP_S> ret;
+    if (_AP_I == 0) {
+      ret.V = 0;
+    } else if (_AP_I > 0 && _AP_I <= _AP_W) {
+      ret.V = _AP_ROOT_op_get_range(Base::V, _AP_W - _AP_I, _AP_W - 1);
+    } else if (_AP_I > _AP_W) {
+      ret.V = _AP_ROOT_op_get_range(Base::V, 0, _AP_W - 1);
+      ret.V <<= (_AP_I - _AP_W);
+    }
+    /* Consider the following case
+     *   float f = -7.5f;
+     *   ap_fixed<8,4> t = f;  // -8 0 0 0 . 0.5
+     *   int i = t.to_int();
+     * the result should be -7 instead of -8.
+     * Therefore, after truncation, the value should be increated by 1.
+     * For (-1, 0), carry to MSB will happen, but result 0 is still correct.
+     */
+    if (Cnative && _AP_I < _AP_W) {
+      // Follow C native data type, conversion from double to int
+      if (_AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1) && (_AP_I < _AP_W) &&
+          (_AP_ROOT_op_get_range(
+               Base::V, 0, _AP_I < 0 ? _AP_W - 1 : _AP_W - _AP_I - 1) != 0))
+        ++ret;
+    } else {
+      // Follow OSCI library, conversion from sc_fixed to sc_int
+    }
+    return ret;
+  };
+
+ public:
+  template <int _AP_W2, bool _AP_S2>
+  INLINE operator ap_int_base<_AP_W2, _AP_S2>() const {
+    return ap_int_base<_AP_W2, _AP_S2>(to_ap_int_base());
+  }
+
+  // Explicit conversion function to C built-in integral type.
+  INLINE char to_char() const { return to_ap_int_base().to_char(); }
+
+  INLINE int to_int() const { return to_ap_int_base().to_int(); }
+
+  INLINE unsigned to_uint() const { return to_ap_int_base().to_uint(); }
+
+  INLINE ap_slong to_int64() const { return to_ap_int_base().to_int64(); }
+
+  INLINE ap_ulong to_uint64() const { return to_ap_int_base().to_uint64(); }
+
+  /// covert function to double.
+  /** only round-half-to-even mode supported, does not obey FE env. */
+  INLINE double to_double() const {
+#if defined(AP_FIXED_ENABLE_CPP_FENV)
+    _AP_WARNING(std::fegetround() != FE_TONEAREST,
+                "Only FE_TONEAREST is supported");
+#endif
+    enum { BITS = DOUBLE_MAN + DOUBLE_EXP + 1 };
+    if (!Base::V) return 0.0f;
+    bool s = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); ///< sign.
+    ap_int_base<_AP_W, false> tmp;
+    if (s)
+      tmp.V = -Base::V; // may truncate one bit extra from neg in sim.
+    else
+      tmp.V = Base::V;
+    int l = tmp.countLeadingZeros(); ///< number of leading zeros.
+    int e = _AP_I - l - 1 + DOUBLE_BIAS; ///< exponent
+    int lsb_index = _AP_W - l - 1 - DOUBLE_MAN;
+    // more than 0.5?
+    bool a = (lsb_index >=2) ?
+        (_AP_ROOT_op_get_range(tmp.V, 0, lsb_index - 2) != 0) : 0;
+    // round to even
+    a |= (lsb_index >=0) ? _AP_ROOT_op_get_bit(tmp.V, lsb_index) : 0;
+    // ull is at least 64-bit
+    ap_ulong m;
+    // may actually left shift, ensure buffer is wide enough.
+    if (_AP_W > BITS) {
+      m = (lsb_index >= 1) ? (ap_ulong)(tmp.V >> (lsb_index - 1))
+                           : (ap_ulong)(tmp.V << (1 - lsb_index));
+    } else {
+      m = (ap_ulong)tmp.V;
+      m = (lsb_index >= 1) ? (m >> (lsb_index - 1))
+                           : (m << (1 - lsb_index));
+    }
+    m += a;
+    m >>= 1;
+    //std::cout << '\n' << std::hex << m << '\n'; // TODO delete this
+    // carry to MSB, increase exponent
+    if (_AP_ctype_op_get_bit(m, DOUBLE_MAN + 1)) {
+      e += 1;
+    }
+    // set sign and exponent
+    m = _AP_ctype_op_set_bit(m, BITS - 1, s);
+    //std::cout << m << '\n'; // TODO delete this
+    m = _AP_ctype_op_set_range(m, DOUBLE_MAN, DOUBLE_MAN + DOUBLE_EXP - 1, e);
+    //std::cout << std::hex << m << std::dec << std::endl; // TODO delete this
+    // cast to fp
+    return rawBitsToDouble(m);
+  }
+
+  /// convert function to float.
+  /** only round-half-to-even mode supported, does not obey FE env. */
+  INLINE float to_float() const {
+#if defined(AP_FIXED_ENABLE_CPP_FENV)
+    _AP_WARNING(std::fegetround() != FE_TONEAREST,
+                "Only FE_TONEAREST is supported");
+#endif
+    enum { BITS = FLOAT_MAN + FLOAT_EXP + 1 };
+    if (!Base::V) return 0.0f;
+    bool s = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); ///< sign.
+    ap_int_base<_AP_W, false> tmp;
+    if (s)
+      tmp.V = -Base::V; // may truncate one bit extra from neg in sim.
+    else
+      tmp.V = Base::V;
+    int l = tmp.countLeadingZeros();  ///< number of leading zeros.
+    int e = _AP_I - l - 1 + FLOAT_BIAS; ///< exponent
+    int lsb_index = _AP_W - l - 1 - FLOAT_MAN;
+    // more than 0.5?
+    bool a = (lsb_index >=2) ?
+        (_AP_ROOT_op_get_range(tmp.V, 0, lsb_index - 2) != 0) : 0;
+    // round to even
+    a |= (lsb_index >=0) ? _AP_ROOT_op_get_bit(tmp.V, lsb_index) : 0;
+    // ul is at least 32-bit
+    unsigned long m;
+    // may actually left shift, ensure buffer is wide enough.
+    if (_AP_W > BITS) {
+      m = (lsb_index >= 1) ? (unsigned long)(tmp.V >> (lsb_index - 1))
+                           : (unsigned long)(tmp.V << (1 - lsb_index));
+    } else {
+      m = (unsigned long)tmp.V;
+      m = (lsb_index >= 1) ? (m >> (lsb_index - 1))
+                           : (m << (1 - lsb_index));
+    }
+    m += a;
+    m >>= 1;
+    // carry to MSB, increase exponent
+    if (_AP_ctype_op_get_bit(m, FLOAT_MAN + 1)) {
+      e += 1;
+    }
+    // set sign and exponent
+    m = _AP_ctype_op_set_bit(m, BITS - 1, s);
+    m = _AP_ctype_op_set_range(m, FLOAT_MAN, FLOAT_MAN + FLOAT_EXP - 1, e);
+    // cast to fp
+    return rawBitsToFloat(m);
+  }
+
+#if _AP_ENABLE_HALF_ == 1
+  /// convert function to half.
+  /** only round-half-to-even mode supported, does not obey FE env. */
+  INLINE half to_half() const {
+#if defined(AP_FIXED_ENABLE_CPP_FENV)
+    _AP_WARNING(std::fegetround() != FE_TONEAREST,
+                "Only FE_TONEAREST is supported");
+#endif
+    enum { BITS = HALF_MAN + HALF_EXP + 1 };
+    if (!Base::V) return 0.0f;
+    bool s = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1); ///< sign.
+    ap_int_base<_AP_W, false> tmp;
+    if (s)
+      tmp.V = -Base::V; // may truncate one bit extra from neg in sim.
+    else
+      tmp.V = Base::V;
+    int l = tmp.countLeadingZeros();  ///< number of leading zeros.
+    int e = _AP_I - l - 1 + HALF_BIAS; ///< exponent
+    int lsb_index = _AP_W - l - 1 - HALF_MAN;
+    // more than 0.5?
+    bool a = (lsb_index >=2) ?
+        (_AP_ROOT_op_get_range(tmp.V, 0, lsb_index - 2) != 0) : 0;
+    // round to even
+    a |= (lsb_index >=0) ? _AP_ROOT_op_get_bit(tmp.V, lsb_index) : 0;
+    // short is at least 16-bit
+    unsigned short m;
+    // may actually left shift, ensure buffer is wide enough.
+    if (_AP_W > BITS) {
+      m = (lsb_index >= 1) ? (unsigned short)(tmp.V >> (lsb_index - 1))
+                           : (unsigned short)(tmp.V << (1 - lsb_index));
+    } else {
+      m = (unsigned short)tmp.V;
+      m = (lsb_index >= 1) ? (m >> (lsb_index - 1))
+                           : (m << (1 - lsb_index));
+    }
+    m += a;
+    m >>= 1;
+    // carry to MSB, increase exponent
+    if (_AP_ctype_op_get_bit(m, HALF_MAN + 1)) {
+      e += 1;
+    }
+    // set sign and exponent
+    m = _AP_ctype_op_set_bit(m, BITS - 1, s);
+    m = _AP_ctype_op_set_range(m, HALF_MAN, HALF_MAN + HALF_EXP - 1, e);
+    // cast to fp
+    return rawBitsToHalf(m);
+  }
+#endif
+
+  // FIXME inherited from old code, this may loose precision!
+  INLINE operator long double() const { return (long double)to_double(); }
+
+  INLINE operator double() const { return to_double(); }
+
+  INLINE operator float() const { return to_float(); }
+
+#if _AP_ENABLE_HALF_ == 1
+  INLINE operator half() const { return to_half(); }
+#endif
+
+  INLINE operator bool() const { return (bool)Base::V != 0; }
+
+  INLINE operator char() const { return (char)to_int(); }
+
+  INLINE operator signed char() const { return (signed char)to_int(); }
+
+  INLINE operator unsigned char() const { return (unsigned char)to_uint(); }
+
+  INLINE operator short() const { return (short)to_int(); }
+
+  INLINE operator unsigned short() const { return (unsigned short)to_uint(); }
+
+  INLINE operator int() const { return to_int(); }
+
+  INLINE operator unsigned int() const { return to_uint(); }
+
+// FIXME don't assume data width...
+#ifdef __x86_64__
+  INLINE operator long() const { return (long)to_int64(); }
+
+  INLINE operator unsigned long() const { return (unsigned long)to_uint64(); }
+#else
+  INLINE operator long() const { return (long)to_int(); }
+
+  INLINE operator unsigned long() const { return (unsigned long)to_uint(); }
+#endif // ifdef __x86_64__ else
+
+  INLINE operator ap_ulong() const { return to_uint64(); }
+
+  INLINE operator ap_slong() const { return to_int64(); }
+
+  INLINE int length() const { return _AP_W; };
+
+  // bits_to_int64 deleted.
+#ifndef __SYNTHESIS__
+  // Used in autowrap, when _AP_W < 64.
+  INLINE ap_ulong bits_to_uint64() const {
+    return (Base::V).to_uint64();
+  }
+#endif
+
+  // Count the number of zeros from the most significant bit
+  // to the first one bit. Note this is only for ap_fixed_base whose
+  // _AP_W <= 64, otherwise will incur assertion.
+  INLINE int countLeadingZeros() {
+#ifdef __SYNTHESIS__
+    // TODO: used llvm.ctlz intrinsic ?
+    if (_AP_W <= 32) {
+      ap_int_base<32, false> t(-1ULL);
+      t.range(_AP_W - 1, 0) = this->range(0, _AP_W - 1);
+      return __builtin_ctz(t.V);
+    } else if (_AP_W <= 64) {
+      ap_int_base<64, false> t(-1ULL);
+      t.range(_AP_W - 1, 0) = this->range(0, _AP_W - 1);
+      return __builtin_ctzll(t.V);
+    } else {
+      enum {__N = (_AP_W + 63) / 64};
+      int NZeros = 0;
+      int i = 0;
+      bool hitNonZero = false;
+      for (i = 0; i < __N - 1; ++i) {
+        ap_int_base<64, false> t;
+        t.range(0, 63) = this->range(_AP_W - i * 64 - 64, _AP_W - i * 64 - 1);
+        NZeros += hitNonZero ? 0 : __builtin_clzll(t.V);
+        hitNonZero |= (t != 0);
+      }
+      if (!hitNonZero) {
+        ap_int_base<64, false> t(-1ULL);
+        t.range(63 - (_AP_W - 1) % 64, 63) = this->range(0, (_AP_W - 1) % 64);
+        NZeros += __builtin_clzll(t.V);
+      }
+      return NZeros;
+    }
+#else
+    return Base::V.countLeadingZeros();
+#endif
+  }
+
+  // Arithmetic : Binary
+  // -------------------------------------------------------------------------
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE typename RType<_AP_W2, _AP_I2, _AP_S2>::mult operator*(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2)
+      const {
+    typename RType<_AP_W2, _AP_I2, _AP_S2>::mult_base r, t;
+    r.V = Base::V;
+    t.V = op2.V;
+    r.V *= op2.V;
+    return r;
+  }
+
+  // multiply function deleted.
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE typename RType<_AP_W2, _AP_I2, _AP_S2>::div operator/(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2)
+      const {
+    typename RType<_AP_W2, _AP_I2, _AP_S2>::div_base r;
+#ifndef __SYNTHESIS__
+    enum {F2 = _AP_W2-_AP_I2,
+              _W1=AP_MAX(_AP_W + AP_MAX(F2, 0) + ((_AP_S2 && !_AP_S) ? 1 : 0), _AP_W2 + ((_AP_S && !_AP_S2) ? 1 : 0))};
+    ap_int_base<_W1,_AP_S||_AP_S2> dividend,divisior;
+    ap_int_base<_W1,_AP_S> tmp1;
+    ap_int_base<_W1,_AP_S2> tmp2;
+    tmp1.V = Base::V;
+    tmp1.V <<= AP_MAX(F2,0);
+    tmp2.V = op2.V;
+    dividend = tmp1;
+    divisior = tmp2;
+    r.V = ((_AP_S||_AP_S2) ? dividend.V.sdiv(divisior.V): dividend.V.udiv(divisior.V));
+#else
+    #ifndef __SC_COMPATIBLE__
+        ap_fixed_base<_AP_W + AP_MAX(_AP_W2 - _AP_I2, 0),_AP_I, _AP_S> t(*this);
+    #else
+        ap_fixed_base<_AP_W + AP_MAX(_AP_W2 - _AP_I2, 0) + AP_MAX(_AP_I2, 0),_AP_I, _AP_S> t(*this);
+    #endif
+        r.V = t.V / op2.V;
+#endif
+/*
+    enum {
+      F2 = _AP_W2 - _AP_I2,
+      shl = AP_MAX(F2, 0) + AP_MAX(_AP_I2, 0),
+#ifndef __SC_COMPATIBLE__
+      shr = AP_MAX(_AP_I2, 0),
+#else
+      shr = 0,
+#endif
+      W3 = _AP_S2 + _AP_W + shl,
+      S3 = _AP_S || _AP_S2,
+    };
+    ap_int_base<W3, S3> dividend, t;
+    dividend.V = Base::V;
+    // multiply both by (1 << F2), and than do integer division.
+    dividend.V <<= (int) shl;
+#ifdef __SYNTHESIS__
+    // .V's have right signedness, and will have right extending.
+    t.V = dividend.V / op2.V;
+#else
+    // XXX op2 may be wider than dividend, and sdiv and udiv takes the same with
+    // as left hand operand, so data might be truncated by mistake if not
+    // handled here.
+    t.V = S3 ? dividend.V.sdiv(op2.V) : dividend.V.udiv(op2.V);
+#endif
+    r.V = t.V >> (int) shr;
+*/
+    return r;
+  }
+
+#define OP_BIN_AF(Sym, Rty)                                                \
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,         \
+            ap_o_mode _AP_O2, int _AP_N2>                                  \
+  INLINE typename RType<_AP_W2, _AP_I2, _AP_S2>::Rty operator Sym(         \
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& \
+          op2) const {                                                     \
+    typename RType<_AP_W2, _AP_I2, _AP_S2>::Rty##_base ret, lhs(*this),    \
+        rhs(op2);                                                          \
+    ret.V = lhs.V Sym rhs.V;                                               \
+    return ret;                                                            \
+  }
+
+  OP_BIN_AF(+, plus)
+  OP_BIN_AF(-, minus)
+  OP_BIN_AF(&, logic)
+  OP_BIN_AF(|, logic)
+  OP_BIN_AF(^, logic)
+
+// Arithmetic : assign
+// -------------------------------------------------------------------------
+#define OP_ASSIGN_AF(Sym)                                                  \
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,         \
+            ap_o_mode _AP_O2, int _AP_N2>                                  \
+  INLINE ap_fixed_base& operator Sym##=(                                   \
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& \
+          op2) {                                                           \
+    *this = operator Sym(op2);                                             \
+    return *this;                                                          \
+  }
+
+  OP_ASSIGN_AF(*)
+  OP_ASSIGN_AF(/)
+  OP_ASSIGN_AF(+)
+  OP_ASSIGN_AF(-)
+  OP_ASSIGN_AF(&)
+  OP_ASSIGN_AF(|)
+  OP_ASSIGN_AF(^)
+
+  // Prefix and postfix increment and decrement.
+  // -------------------------------------------------------------------------
+
+  /// Prefix increment
+  INLINE ap_fixed_base& operator++() {
+    operator+=(ap_fixed_base<_AP_W - _AP_I + 1, 1, false>(1));
+    return *this;
+  }
+
+  /// Prefix decrement.
+  INLINE ap_fixed_base& operator--() {
+    operator-=(ap_fixed_base<_AP_W - _AP_I + 1, 1, false>(1));
+    return *this;
+  }
+
+  /// Postfix increment
+  INLINE const ap_fixed_base operator++(int) {
+    ap_fixed_base r(*this);
+    operator++();
+    return r;
+  }
+
+  /// Postfix decrement
+  INLINE const ap_fixed_base operator--(int) {
+    ap_fixed_base r(*this);
+    operator--();
+    return r;
+  }
+
+  // Unary arithmetic.
+  // -------------------------------------------------------------------------
+  INLINE ap_fixed_base operator+() { return *this; }
+
+  INLINE ap_fixed_base<_AP_W + 1, _AP_I + 1, true> operator-() const {
+    ap_fixed_base<_AP_W + 1, _AP_I + 1, true> r(*this);
+    r.V = -r.V;
+    return r;
+  }
+
+  INLINE ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> getNeg() {
+    ap_fixed_base<_AP_W, _AP_I, true, _AP_Q, _AP_O, _AP_N> r(*this);
+    r.V = -r.V;
+    return r;
+  }
+
+  // Not (!)
+  // -------------------------------------------------------------------------
+  INLINE bool operator!() const { return Base::V == 0; }
+
+  // Bitwise complement
+  // -------------------------------------------------------------------------
+  // XXX different from Mentor's ac_fixed.
+  INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S> operator~() const {
+    ap_fixed_base<_AP_W, _AP_I, _AP_S> r;
+    r.V = ~Base::V;
+    return r;
+  }
+
+  // Shift
+  // -------------------------------------------------------------------------
+  // left shift is the same as moving point right, i.e. increate I.
+  template <int _AP_SHIFT>
+  INLINE ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> lshift() const {
+    ap_fixed_base<_AP_W, _AP_I + _AP_SHIFT, _AP_S> r;
+    r.V = Base::V;
+    return r;
+  }
+
+  template <int _AP_SHIFT>
+  INLINE ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> rshift() const {
+    ap_fixed_base<_AP_W, _AP_I - _AP_SHIFT, _AP_S> r;
+    r.V = Base::V;
+    return r;
+  }
+
+  // Because the return type is the type of the the first operand, shift assign
+  // operators do not carry out any quantization or overflow
+  // While systemc, shift assigns for sc_fixed/sc_ufixed will result in
+  // quantization or overflow (depending on the mode of the first operand)
+  INLINE ap_fixed_base operator<<(unsigned int sh) const {
+    ap_fixed_base r;
+    r.V = Base::V << sh;
+// TODO check shift overflow?
+#ifdef __SC_COMPATIBLE__
+    if (sh == 0) return r;
+    if (_AP_O != AP_WRAP || _AP_N != 0) {
+      bool neg_src = _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1);
+      bool allones, allzeros;
+      ap_int_base<_AP_W, false> ones(-1);
+      if (sh <= _AP_W) {
+        ap_int_base<_AP_W, false> range1;
+        range1.V = _AP_ROOT_op_get_range(
+            const_cast<ap_fixed_base*>(this)->Base::V, _AP_W - sh, _AP_W - 1);
+        allones = range1 == (ones >> (_AP_W - sh));
+        allzeros = range1 == 0;
+      } else {
+        allones = false;
+        allzeros = Base::V == 0;
+      }
+      bool overflow = !allzeros && !neg_src;
+      bool underflow = !allones && neg_src;
+      if ((_AP_O == AP_SAT_SYM) && _AP_S)
+        underflow |=
+            neg_src &&
+            (_AP_W > 1 ? _AP_ROOT_op_get_range(r.V, 0, _AP_W - 2) == 0 : true);
+      bool lD = false;
+      if (sh < _AP_W) lD = _AP_ROOT_op_get_bit(Base::V, _AP_W - sh - 1);
+      r.overflow_adjust(underflow, overflow, lD, neg_src);
+    }
+#endif
+    return r;
+  }
+
+  INLINE ap_fixed_base operator>>(unsigned int sh) const {
+    ap_fixed_base r;
+    r.V = Base::V >> sh;
+// TODO check shift overflow?
+#ifdef __SC_COMPATIBLE__
+    if (sh == 0) return r;
+    if (_AP_Q != AP_TRN) {
+      bool qb = false;
+      if (sh <= _AP_W) qb = _AP_ROOT_op_get_bit(Base::V, sh - 1);
+      bool rb = false;
+      if (sh > 1 && sh <= _AP_W)
+        rb = _AP_ROOT_op_get_range(const_cast<ap_fixed_base*>(this)->Base::V, 0,
+                                   sh - 2) != 0;
+      else if (sh > _AP_W)
+        rb = Base::V != 0;
+      r.quantization_adjust(qb, rb,
+                            _AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1));
+    }
+#endif
+    return r;
+  }
+
+  // left and right shift for int
+  INLINE ap_fixed_base operator<<(int sh) const {
+    ap_fixed_base r;
+    bool isNeg = sh < 0;
+    unsigned int ush = isNeg ? -sh : sh;
+    if (isNeg) {
+      return operator>>(ush);
+    } else {
+      return operator<<(ush);
+    }
+  }
+
+  INLINE ap_fixed_base operator>>(int sh) const {
+    bool isNeg = sh < 0;
+    unsigned int ush = isNeg ? -sh : sh;
+    if (isNeg) {
+      return operator<<(ush);
+    } else {
+      return operator>>(ush);
+    }
+  }
+
+  // left and right shift for ap_int.
+  template <int _AP_W2>
+  INLINE ap_fixed_base operator<<(const ap_int_base<_AP_W2, true>& op2) const {
+    // TODO the code seems not optimal. ap_fixed<8,8> << ap_int<2> needs only a
+    // small mux, but integer need a big one!
+    int sh = op2.to_int();
+    return operator<<(sh);
+  }
+
+  template <int _AP_W2>
+  INLINE ap_fixed_base operator>>(const ap_int_base<_AP_W2, true>& op2) const {
+    int sh = op2.to_int();
+    return operator>>(sh);
+  }
+
+  // left and right shift for ap_uint.
+  template <int _AP_W2>
+  INLINE ap_fixed_base operator<<(const ap_int_base<_AP_W2, false>& op2) const {
+    unsigned int sh = op2.to_uint();
+    return operator<<(sh);
+  }
+
+  template <int _AP_W2>
+  INLINE ap_fixed_base operator>>(const ap_int_base<_AP_W2, false>& op2) const {
+    unsigned int sh = op2.to_uint();
+    return operator>>(sh);
+  }
+
+  // left and right shift for ap_fixed
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base operator<<(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&
+          op2) {
+    return operator<<(op2.to_ap_int_base());
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base operator>>(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&
+          op2) {
+    return operator>>(op2.to_ap_int_base());
+  }
+
+  // Shift assign.
+  // -------------------------------------------------------------------------
+
+  // left shift assign.
+  INLINE ap_fixed_base& operator<<=(const int sh) {
+    *this = operator<<(sh);
+    return *this;
+  }
+
+  INLINE ap_fixed_base& operator<<=(const unsigned int sh) {
+    *this = operator<<(sh);
+    return *this;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed_base& operator<<=(const ap_int_base<_AP_W2, _AP_S2>& sh) {
+    *this = operator<<(sh.to_int());
+    return *this;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base& operator<<=(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&
+          sh) {
+    *this = operator<<(sh.to_int());
+    return *this;
+  }
+
+  // right shift assign.
+  INLINE ap_fixed_base& operator>>=(const int sh) {
+    *this = operator>>(sh);
+    return *this;
+  }
+
+  INLINE ap_fixed_base& operator>>=(const unsigned int sh) {
+    *this = operator>>(sh);
+    return *this;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_fixed_base& operator>>=(const ap_int_base<_AP_W2, _AP_S2>& sh) {
+    *this = operator>>(sh.to_int());
+    return *this;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_fixed_base& operator>>=(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&
+          sh) {
+    *this = operator>>(sh.to_int());
+    return *this;
+  }
+
+// Comparisons.
+// -------------------------------------------------------------------------
+#define OP_CMP_AF(Sym)                                                         \
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,             \
+            ap_o_mode _AP_O2, int _AP_N2>                                      \
+  INLINE bool operator Sym(const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, \
+                                               _AP_O2, _AP_N2>& op2) const {   \
+    enum { _AP_F = _AP_W - _AP_I, F2 = _AP_W2 - _AP_I2 };                      \
+    if (_AP_F == F2)                                                           \
+      return Base::V Sym op2.V;                                                \
+    else if (_AP_F > F2)                                                       \
+      return Base::V Sym ap_fixed_base<AP_MAX(_AP_W2 + _AP_F - F2, 1), _AP_I2, \
+                                       _AP_S2, _AP_Q2, _AP_O2, _AP_N2>(op2).V; \
+    else                                                                       \
+      return ap_fixed_base<AP_MAX(_AP_W + F2 - _AP_F + 1, 1), _AP_I + 1,       \
+                           _AP_S, _AP_Q, _AP_O, _AP_N>(*this).V Sym op2.V;     \
+    return false;                                                              \
+  }
+
+  OP_CMP_AF(>)
+  OP_CMP_AF(<)
+  OP_CMP_AF(>=)
+  OP_CMP_AF(<=)
+  OP_CMP_AF(==)
+  OP_CMP_AF(!=)
+// FIXME: Move compare with double out of struct ap_fixed_base defination
+//        and combine it with compare operator(double, ap_fixed_base)
+#define DOUBLE_CMP_AF(Sym) \
+  INLINE bool operator Sym(double d) const { return to_double() Sym d; }
+
+  DOUBLE_CMP_AF(>)
+  DOUBLE_CMP_AF(<)
+  DOUBLE_CMP_AF(>=)
+  DOUBLE_CMP_AF(<=)
+  DOUBLE_CMP_AF(==)
+  DOUBLE_CMP_AF(!=)
+
+  // Bit and Slice Select
+  INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator[](
+      unsigned index) {
+    _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB");
+    return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, index);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator[](
+      const ap_int_base<_AP_W2, _AP_S2>& index) {
+    _AP_WARNING(index < 0, "Attempting to read bit with negative index");
+    _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB");
+    return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this,
+                                                                index.to_int());
+  }
+
+  INLINE bool operator[](unsigned index) const {
+    _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB");
+    return _AP_ROOT_op_get_bit(const_cast<ap_fixed_base*>(this)->V, index);
+  }
+
+  INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> bit(
+      unsigned index) {
+    _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB");
+    return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, index);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> bit(
+      const ap_int_base<_AP_W2, _AP_S2>& index) {
+    _AP_WARNING(index < 0, "Attempting to read bit with negative index");
+    _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB");
+    return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this,
+                                                                index.to_int());
+  }
+
+  INLINE bool bit(unsigned index) const {
+    _AP_WARNING(index >= _AP_W, "Attempting to read bit beyond MSB");
+    return _AP_ROOT_op_get_bit(const_cast<ap_fixed_base*>(this)->V, index);
+  }
+
+  template <int _AP_W2>
+  INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> get_bit(
+      const ap_int_base<_AP_W2, true>& index) {
+    _AP_WARNING(index < _AP_I - _AP_W,
+                "Attempting to read bit with negative index");
+    _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB");
+    return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(
+        this, index.to_int() + _AP_W - _AP_I);
+  }
+
+  INLINE bool get_bit(int index) const {
+    _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB");
+    _AP_WARNING(index < _AP_I - _AP_W, "Attempting to read bit beyond MSB");
+    return _AP_ROOT_op_get_bit(const_cast<ap_fixed_base*>(this)->V,
+                               index + _AP_W - _AP_I);
+  }
+#if 0
+  INLINE af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> get_bit(
+      int index) {
+    _AP_WARNING(index < _AP_I - _AP_W,
+              "Attempting to read bit with negative index");
+    _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB");
+    return af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(
+        this, index + _AP_W - _AP_I);
+  }
+#endif
+
+  template <int _AP_W2>
+  INLINE bool get_bit(const ap_int_base<_AP_W2, true>& index) const {
+    _AP_WARNING(index >= _AP_I, "Attempting to read bit beyond MSB");
+    _AP_WARNING(index < _AP_I - _AP_W, "Attempting to read bit beyond MSB");
+    return _AP_ROOT_op_get_bit(const_cast<ap_fixed_base*>(this)->V,
+                               index.to_int() + _AP_W - _AP_I);
+  }
+
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range(int Hi,
+                                                                      int Lo) {
+    _AP_WARNING((Hi >= _AP_W) || (Lo >= _AP_W), "Out of bounds in range()");
+    return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(this, Hi, Lo);
+  }
+
+  // This is a must to strip constness to produce reference type.
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range(
+      int Hi, int Lo) const {
+    _AP_WARNING((Hi >= _AP_W) || (Lo >= _AP_W), "Out of bounds in range()");
+    return af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(
+        const_cast<ap_fixed_base*>(this), Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range() {
+    return this->range(_AP_W - 1, 0);
+  }
+
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> range() const {
+    return this->range(_AP_W - 1, 0);
+  }
+
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()(
+      int Hi, int Lo) {
+    return this->range(Hi, Lo);
+  }
+
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()(
+      int Hi, int Lo) const {
+    return this->range(Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> operator()(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  INLINE bool is_zero() const { return Base::V == 0; }
+
+  INLINE bool is_neg() const {
+    if (_AP_S && _AP_ROOT_op_get_bit(Base::V, _AP_W - 1)) return true;
+    return false;
+  }
+
+  INLINE int wl() const { return _AP_W; }
+
+  INLINE int iwl() const { return _AP_I; }
+
+  INLINE ap_q_mode q_mode() const { return _AP_Q; }
+
+  INLINE ap_o_mode o_mode() const { return _AP_O; }
+
+  INLINE int n_bits() const { return _AP_N; }
+
+  // print a string representation of this number in the given radix.
+  // Radix support is 2, 8, 10, or 16.
+  // The result will include a prefix indicating the radix, except for decimal,
+  // where no prefix is needed.  The default is to output a signed representation
+  // of signed numbers, or an unsigned representation  of unsigned numbers.  For
+  // non-decimal formats, this can be changed by the 'sign' argument.
+#ifndef __SYNTHESIS__
+  std::string to_string(unsigned char radix = 2, bool sign = _AP_S) const {
+    // XXX in autosim/autowrap.tcl "(${name}).to_string(2).c_str()" is used to
+    // initialize sc_lv, which seems incapable of handling format "-0b".
+    if (radix == 2) sign = false;
+
+    std::string str;
+    str.clear();
+    char step = 0;
+    bool isNeg = sign && (Base::V < 0);
+
+    // Extend to take care of the -MAX case.
+    ap_fixed_base<_AP_W + 1, _AP_I + 1> tmp(*this);
+    if (isNeg) {
+      tmp = -tmp;
+      str += '-';
+    }
+    std::string prefix;
+    switch (radix) {
+      case 2:
+        prefix = "0b";
+        step = 1;
+        break;
+      case 8:
+        prefix = "0o";
+        step = 3;
+        break;
+      case 16:
+        prefix = "0x";
+        step = 4;
+        break;
+      default:
+        break;
+    }
+
+    if (_AP_I > 0) {
+      // Note we drop the quantization and rounding flags here.  The
+      // integer part is always in range, and the fractional part we
+      // want to drop.  Also, the number is always positive, because
+      // of the absolute value above.
+      ap_int_base<AP_MAX(_AP_I + 1, 1), false> int_part;
+      //   [1] [ I ] d [ W - I ]
+      //    |     |            |
+      //    |    W-I           0
+      //    W
+      int_part.V = _AP_ROOT_op_get_range(
+          tmp.V, _AP_W - _AP_I, _AP_W);
+      str += int_part.to_string(radix, false);
+    } else {
+      str += prefix;
+      str += '0';
+    }
+
+    ap_fixed_base<AP_MAX(_AP_W - _AP_I, 1), 0, false> frac_part = tmp;
+
+    if (radix == 10) {
+      if (frac_part != 0) {
+        str += ".";
+        while (frac_part != 0) {
+          char digit = (frac_part * radix).to_char();
+          str += static_cast<char>(digit + '0');
+          frac_part *= radix;
+        }
+      }
+    } else {
+      if (frac_part != 0) {
+        str += ".";
+        for (signed i = _AP_W - _AP_I - 1; i >= 0; i -= step) {
+          char digit = frac_part.range(i, AP_MAX(0, i - step + 1)).to_char();
+          // If we have a partial bit pattern at the end, then we need
+          // to put it in the high-order bits of 'digit'.
+          int offset = AP_MIN(0, i - step + 1);
+          digit <<= -offset;
+          str += digit < 10 ? static_cast<char>(digit + '0')
+                            : static_cast<char>(digit - 10 + 'a');
+        }
+        if (radix == 16)
+          str += "p0"; // C99 Hex constants are required to have an exponent.
+      }
+    }
+    return str;
+  }
+#else
+  // XXX HLS will delete this in synthesis
+  INLINE char* to_string(unsigned char radix = 2, bool sign = _AP_S) const {
+    return 0;
+  }
+#endif
+}; // struct ap_fixed_base.
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE void b_not(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {
+  ret.V = ~op.V;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE void b_and(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  ret.V = op1.V & op2.V;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE void b_or(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  ret.V = op1.V | op2.V;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE void b_xor(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  ret.V = op1.V ^ op2.V;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+          ap_o_mode _AP_O2, int _AP_N2>
+INLINE void neg(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+  ap_fixed_base<_AP_W2 + !_AP_S2, _AP_I2 + !_AP_S2, true, _AP_Q2, _AP_O2,
+                _AP_N2>
+      t;
+  t.V = -op.V;
+  ret = t;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+          ap_o_mode _AP_O2, int _AP_N2>
+INLINE void lshift(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op,
+    int i) {
+  enum {
+    F2 = _AP_W2 - _AP_I2,
+    _AP_I3 = AP_MAX(_AP_I, _AP_I2),
+    _AP_W3 = _AP_I3 + F2,
+  };
+  // wide buffer
+  ap_fixed_base<_AP_W3, _AP_I3, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> t;
+  t.V = op.V;
+  t.V <<= i; // FIXME overflow?
+  // handle quantization and overflow
+  ret = t;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N, int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+          ap_o_mode _AP_O2, int _AP_N2>
+INLINE void rshift(
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ret,
+    const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op,
+    int i) {
+  enum {
+    F = _AP_W - _AP_I,
+    F2 = _AP_W2 - _AP_I2,
+    F3 = AP_MAX(F, F2),
+    _AP_W3 = _AP_I2 + F3,
+    sh = F - F2,
+  };
+  // wide buffer
+  ap_fixed_base<_AP_W3, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> t;
+  t.V = op.V;
+  if (sh >= 0)
+    t.V <<= (int) sh;
+  t.V >>= i;
+  // handle quantization and overflow
+  ret = t;
+}
+
+//// FIXME
+//// These partial specialization ctors allow code like
+////   char c = 'a';
+////   ap_fixed_base<8, 8, true> x(c);
+//// but what bout ap_fixed_base<9, 9, true> y(c) ?
+//
+
+#ifndef __SYNTHESIS__
+INLINE std::string scientificFormat(std::string& input) {
+  if (input.length() == 0) return input;
+
+  size_t decPosition = input.find('.');
+  if (decPosition == std::string::npos) decPosition = input.length();
+
+  size_t firstNonZeroPos = 0;
+  for (; input[firstNonZeroPos] > '9' || input[firstNonZeroPos] < '1';
+       firstNonZeroPos++)
+    ;
+
+  int exp;
+  if (firstNonZeroPos > decPosition)
+    exp = decPosition - firstNonZeroPos;
+  else
+    exp = decPosition - firstNonZeroPos - 1;
+  std::string expString = "";
+  if (exp == 0)
+    ;
+  else if (exp < 0) {
+    expString += "e-";
+    exp = -exp;
+  } else
+    expString += "e+";
+
+  if (exp < 10 && exp > 0) {
+    expString += '0';
+    expString += (char)('0' + exp);
+  } else if (exp != 0) {
+    std::string tmp;
+
+    std::ostringstream oss;
+    oss << exp;
+
+    tmp = oss.str();
+    expString += tmp;
+  }
+
+  int lastNonZeroPos = (int)(input.length() - 1);
+  for (; lastNonZeroPos >= 0; --lastNonZeroPos)
+    if (input[lastNonZeroPos] <= '9' && input[lastNonZeroPos] > '0') break;
+
+  std::string ans = "";
+  ans += input[firstNonZeroPos];
+  if (firstNonZeroPos != (size_t)lastNonZeroPos) {
+    ans += '.';
+    for (int i = firstNonZeroPos + 1; i <= lastNonZeroPos; i++)
+      if (input[i] != '.') ans += input[i];
+  }
+
+  ans += expString;
+  return ans;
+}
+
+INLINE std::string reduceToPrecision(std::string& input, int precision) {
+  bool isZero = true;
+  size_t inputLen = input.length();
+  for (size_t i = 0; i < inputLen && isZero; i++)
+    if (input[i] != '.' && input[i] != '0') isZero = false;
+  if (isZero) return "0";
+
+  // Find the first valid number, skip '-'
+  int FirstNonZeroPos = 0;
+  int LastNonZeroPos = (int)inputLen - 1;
+  int truncBitPosition = 0;
+  size_t decPosition = input.find('.');
+  for (; input[FirstNonZeroPos] < '1' || input[FirstNonZeroPos] > '9';
+       FirstNonZeroPos++)
+    ;
+
+  for (; input[LastNonZeroPos] < '1' || input[LastNonZeroPos] > '9';
+       LastNonZeroPos--)
+    ;
+
+  if (decPosition == std::string::npos) decPosition = inputLen;
+  // Count the valid number, to decide whether we need to truncate
+  if ((int)decPosition > LastNonZeroPos) {
+    if (LastNonZeroPos - FirstNonZeroPos + 1 <= precision) return input;
+    truncBitPosition = FirstNonZeroPos + precision;
+  } else if ((int)decPosition < FirstNonZeroPos) { // This is pure decimal
+    if (LastNonZeroPos - FirstNonZeroPos + 1 <= precision) {
+      if (FirstNonZeroPos - decPosition - 1 < 4) {
+        return input;
+      } else {
+        if (input[0] == '-') {
+          std::string tmp = input.substr(1, inputLen - 1);
+          return std::string("-") + scientificFormat(tmp);
+        } else
+          return scientificFormat(input);
+      }
+    }
+    truncBitPosition = FirstNonZeroPos + precision;
+  } else {
+    if (LastNonZeroPos - FirstNonZeroPos <= precision) return input;
+    truncBitPosition = FirstNonZeroPos + precision + 1;
+  }
+
+  // duplicate the input string, we want to add "0" before the valid numbers
+  // This is easy for quantization, since we may change 9999 to 10000
+  std::string ans = "";
+  std::string dupInput = "0";
+  if (input[0] == '-') {
+    ans += '-';
+    dupInput += input.substr(1, inputLen - 1);
+  } else {
+    dupInput += input.substr(0, inputLen);
+    ++truncBitPosition;
+  }
+
+  // Add 'carry' after truncation, if necessary
+  bool carry = dupInput[truncBitPosition] > '4';
+  for (int i = truncBitPosition - 1; i >= 0 && carry; i--) {
+    if (dupInput[i] == '.') continue;
+    if (dupInput[i] == '9')
+      dupInput[i] = '0';
+    else {
+      ++dupInput[i];
+      carry = false;
+    }
+  }
+
+  // bits outside precision range should be set to 0
+  if (dupInput[0] == '1')
+    FirstNonZeroPos = 0;
+  else {
+    FirstNonZeroPos = 0;
+    while (dupInput[FirstNonZeroPos] < '1' || dupInput[FirstNonZeroPos] > '9')
+      ++FirstNonZeroPos;
+  }
+
+  unsigned it = FirstNonZeroPos;
+  int NValidNumber = 0;
+  while (it < dupInput.length()) {
+    if (dupInput[it] == '.') {
+      ++it;
+      continue;
+    }
+    ++NValidNumber;
+    if (NValidNumber > precision) dupInput[it] = '0';
+    ++it;
+  }
+
+  // Here we wanted to adjust the truncate position and the value
+  decPosition = dupInput.find('.');
+  if (decPosition == std::string::npos) // When this is integer
+    truncBitPosition = (int)dupInput.length();
+  else
+    for (truncBitPosition = (int)(dupInput.length() - 1); truncBitPosition >= 0;
+         --truncBitPosition) {
+      if (dupInput[truncBitPosition] == '.') break;
+      if (dupInput[truncBitPosition] != '0') {
+        truncBitPosition++;
+        break;
+      }
+    }
+
+  if (dupInput[0] == '1')
+    dupInput = dupInput.substr(0, truncBitPosition);
+  else
+    dupInput = dupInput.substr(1, truncBitPosition - 1);
+
+  decPosition = dupInput.find('.');
+  if (decPosition != std::string::npos) {
+    size_t it = 0;
+    for (it = decPosition + 1; dupInput[it] == '0'; it++)
+      ;
+    if (it - decPosition - 1 < 4) {
+      ans += dupInput;
+      return ans;
+    } else {
+      ans += scientificFormat(dupInput);
+      return ans;
+    }
+  } else if ((int)(dupInput.length()) <= precision) {
+    ans += dupInput;
+    return ans;
+  }
+
+  ans += scientificFormat(dupInput);
+  return ans;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE void print(
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) {
+  if (_AP_I > 0) {
+    ap_int_base<_AP_I, _AP_S> p1;
+    p1.V = x.V >> (_AP_W - _AP_I);
+    print(p1.V); // print overlaod for .V should exit
+  } else {
+    printf("0");
+  }
+  printf(".");
+  if (_AP_I < _AP_W) {
+    ap_int_base<_AP_W - _AP_I, false> p2;
+    p2.V = _AP_ROOT_op_get_range(x.V, 0, _AP_W - _AP_I);
+    print(p2.V, false); // print overlaod for .V should exit
+  }
+}
+#endif // ifndef __SYNTHESIS__
+
+// XXX the following two functions have to exist in synthesis,
+// as some old HLS Video Library code uses the ostream overload,
+// although HLS will later delete I/O function call.
+
+/// Output streaming
+//-----------------------------------------------------------------------------
+// XXX apcc cannot handle global std::ios_base::Init() brought in by <iostream>
+#ifndef AP_AUTOCC
+#ifndef __SYNTHESIS__
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE std::ostream& operator<<(
+    std::ostream& out,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) {
+  // TODO support std::ios_base::fmtflags
+  unsigned width = out.width();
+  unsigned precision = out.precision();
+  char fill = out.fill();
+  std::string str = x.to_string(10, _AP_S);
+  str = reduceToPrecision(str, precision);
+  if (width > str.length()) {
+    for (unsigned i = 0; i < width - str.length(); ++i)
+      out << fill;
+  }
+  out << str;
+  return out;
+}
+#endif // ifndef __SYNTHESIS__
+
+/// Input streaming
+// -----------------------------------------------------------------------------
+#ifndef __SYNTHESIS__
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE std::istream& operator>>(
+    std::istream& in,
+    ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) {
+  double d;
+  in >> d;
+  x = ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>(d);
+  return in;
+}
+#endif
+#endif // ifndef AP_AUTOCC
+
+/// Operators mixing Integers with ap_fixed_base
+// -----------------------------------------------------------------------------
+#define AF_BIN_OP_WITH_INT_SF(BIN_OP, C_TYPE, _AP_W2, _AP_S2, RTYPE)     \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,           \
+            ap_o_mode _AP_O, int _AP_N>                                  \
+  INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType<    \
+      _AP_W2, _AP_W2, _AP_S2>::RTYPE                                     \
+  operator BIN_OP(                                                       \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op, \
+      C_TYPE i_op) {                                                     \
+    return op.operator BIN_OP(ap_int_base<_AP_W2, _AP_S2>(i_op));        \
+  }
+
+#define AF_BIN_OP_WITH_INT(BIN_OP, C_TYPE, _AP_W2, _AP_S2, RTYPE)           \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType<       \
+      _AP_W2, _AP_W2, _AP_S2>::RTYPE                                        \
+  operator BIN_OP(                                                          \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,    \
+      C_TYPE i_op) {                                                        \
+    return op.operator BIN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \
+  }                                                                         \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType<       \
+      _AP_W2, _AP_W2, _AP_S2>::RTYPE                                        \
+  operator BIN_OP(                                                          \
+      C_TYPE i_op,                                                          \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {  \
+    return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator BIN_OP(op); \
+  }
+
+#define AF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)                  \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE bool operator REL_OP(                                              \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,    \
+      C_TYPE i_op) {                                                        \
+    return op.operator REL_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \
+  }                                                                         \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE bool operator REL_OP(                                              \
+      C_TYPE i_op,                                                          \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {  \
+    return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator REL_OP(op); \
+  }
+
+#define AF_ASSIGN_OP_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)               \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,                 \
+            ap_o_mode _AP_O, int _AP_N>                                        \
+  INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&              \
+  operator ASSIGN_OP(                                                          \
+      ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,             \
+      C_TYPE i_op) {                                                           \
+    return op.operator ASSIGN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \
+  }
+
+#define AF_ASSIGN_OP_WITH_INT_SF(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)  \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,       \
+            ap_o_mode _AP_O, int _AP_N>                              \
+  INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&    \
+  operator ASSIGN_OP(                                                \
+      ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,   \
+      C_TYPE i_op) {                                                 \
+    return op.operator ASSIGN_OP(ap_int_base<_AP_W2, _AP_S2>(i_op)); \
+  }
+
+#define ALL_AF_OP_WITH_INT(C_TYPE, BITS, SIGN)               \
+  AF_BIN_OP_WITH_INT(+, C_TYPE, (BITS), (SIGN), plus)     \
+  AF_BIN_OP_WITH_INT(-, C_TYPE, (BITS), (SIGN), minus)    \
+  AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult)     \
+  AF_BIN_OP_WITH_INT(/, C_TYPE, (BITS), (SIGN), div)      \
+  AF_BIN_OP_WITH_INT(&, C_TYPE, (BITS), (SIGN), logic)    \
+  AF_BIN_OP_WITH_INT(|, C_TYPE, (BITS), (SIGN), logic)    \
+  AF_BIN_OP_WITH_INT(^, C_TYPE, (BITS), (SIGN), logic)    \
+  AF_BIN_OP_WITH_INT_SF(>>, C_TYPE, (BITS), (SIGN), lhs)  \
+  AF_BIN_OP_WITH_INT_SF(<<, C_TYPE, (BITS), (SIGN), lhs)  \
+                                                          \
+  AF_ASSIGN_OP_WITH_INT(+=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT(-=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT(*=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT(/=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT(&=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT(|=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT(^=, C_TYPE, (BITS), (SIGN))     \
+  AF_ASSIGN_OP_WITH_INT_SF(>>=, C_TYPE, (BITS), (SIGN)) \
+  AF_ASSIGN_OP_WITH_INT_SF(<<=, C_TYPE, (BITS), (SIGN)) \
+                                                          \
+  AF_REL_OP_WITH_INT(>, C_TYPE, (BITS), (SIGN))           \
+  AF_REL_OP_WITH_INT(<, C_TYPE, (BITS), (SIGN))           \
+  AF_REL_OP_WITH_INT(>=, C_TYPE, (BITS), (SIGN))          \
+  AF_REL_OP_WITH_INT(<=, C_TYPE, (BITS), (SIGN))          \
+  AF_REL_OP_WITH_INT(==, C_TYPE, (BITS), (SIGN))          \
+  AF_REL_OP_WITH_INT(!=, C_TYPE, (BITS), (SIGN))
+
+ALL_AF_OP_WITH_INT(bool, 1, false)
+ALL_AF_OP_WITH_INT(char, 8, CHAR_IS_SIGNED)
+ALL_AF_OP_WITH_INT(signed char, 8, true)
+ALL_AF_OP_WITH_INT(unsigned char, 8, false)
+ALL_AF_OP_WITH_INT(short, _AP_SIZE_short, true)
+ALL_AF_OP_WITH_INT(unsigned short, _AP_SIZE_short, false)
+ALL_AF_OP_WITH_INT(int, _AP_SIZE_int, true)
+ALL_AF_OP_WITH_INT(unsigned int, _AP_SIZE_int, false)
+ALL_AF_OP_WITH_INT(long, _AP_SIZE_long, true)
+ALL_AF_OP_WITH_INT(unsigned long, _AP_SIZE_long, false)
+ALL_AF_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+ALL_AF_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef ALL_AF_OP_WITH_INT
+#undef AF_BIN_OP_WITH_INT
+#undef AF_BIN_OP_WITH_INT_SF
+#undef AF_ASSIGN_OP_WITH_INT
+#undef AF_ASSIGN_OP_WITH_INT_SF
+#undef AF_REL_OP_WITH_INT
+
+/*
+ * **********************************************************************
+ * TODO
+ * There is no operator defined with float/double/long double, so that
+ * code like
+ *   ap_fixed<8,4> a = 1.5f;
+ *   a += 0.5f;
+ * will fail in compilation.
+ * Operator with warning about conversion might be wanted.
+ * **********************************************************************
+ */
+
+#define AF_BIN_OP_WITH_AP_INT(BIN_OP, RTYPE)                                \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>            \
+  INLINE typename ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>::template RType<    \
+      _AP_W, _AP_I, _AP_S>::RTYPE                                           \
+  operator BIN_OP(                                                          \
+      const ap_int_base<_AP_W2, _AP_S2>& i_op,                              \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {  \
+    return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator BIN_OP(op); \
+  }                                                                         \
+                                                                            \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>            \
+  INLINE typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::template RType<       \
+      _AP_W2, _AP_W2, _AP_S2>::RTYPE                                        \
+  operator BIN_OP(                                                          \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,    \
+      const ap_int_base<_AP_W2, _AP_S2>& i_op) {                            \
+    return op.operator BIN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \
+  }
+
+#define AF_REL_OP_WITH_AP_INT(REL_OP)                                       \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>            \
+  INLINE bool operator REL_OP(                                              \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,    \
+      const ap_int_base<_AP_W2, _AP_S2>& i_op) {                            \
+    return op.operator REL_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \
+  }                                                                         \
+                                                                            \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>            \
+  INLINE bool operator REL_OP(                                              \
+      const ap_int_base<_AP_W2, _AP_S2>& i_op,                              \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {  \
+    return ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op).operator REL_OP(op); \
+  }
+
+#define AF_ASSIGN_OP_WITH_AP_INT(ASSIGN_OP)                                    \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,                 \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>               \
+  INLINE ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&              \
+  operator ASSIGN_OP(                                                          \
+      ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,             \
+      const ap_int_base<_AP_W2, _AP_S2>& i_op) {                               \
+    return op.operator ASSIGN_OP(ap_fixed_base<_AP_W2, _AP_W2, _AP_S2>(i_op)); \
+  }                                                                            \
+                                                                               \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,                 \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>               \
+  INLINE ap_int_base<_AP_W2, _AP_S2>& operator ASSIGN_OP(                      \
+      ap_int_base<_AP_W2, _AP_S2>& i_op,                                       \
+      const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {     \
+    return i_op.operator ASSIGN_OP(op.to_ap_int_base());                       \
+  }
+
+AF_BIN_OP_WITH_AP_INT(+, plus)
+AF_BIN_OP_WITH_AP_INT(-, minus)
+AF_BIN_OP_WITH_AP_INT(*, mult)
+AF_BIN_OP_WITH_AP_INT(/, div)
+AF_BIN_OP_WITH_AP_INT(&, logic)
+AF_BIN_OP_WITH_AP_INT(|, logic)
+AF_BIN_OP_WITH_AP_INT(^, logic)
+
+#undef AF_BIN_OP_WITH_AP_INT
+
+AF_ASSIGN_OP_WITH_AP_INT(+=)
+AF_ASSIGN_OP_WITH_AP_INT(-=)
+AF_ASSIGN_OP_WITH_AP_INT(*=)
+AF_ASSIGN_OP_WITH_AP_INT(/=)
+AF_ASSIGN_OP_WITH_AP_INT(&=)
+AF_ASSIGN_OP_WITH_AP_INT(|=)
+AF_ASSIGN_OP_WITH_AP_INT(^=)
+
+#undef AF_ASSIGN_OP_WITH_AP_INT
+
+AF_REL_OP_WITH_AP_INT(==)
+AF_REL_OP_WITH_AP_INT(!=)
+AF_REL_OP_WITH_AP_INT(>)
+AF_REL_OP_WITH_AP_INT(>=)
+AF_REL_OP_WITH_AP_INT(<)
+AF_REL_OP_WITH_AP_INT(<=)
+
+#undef AF_REL_OP_WITH_AP_INT
+
+// Relational Operators with double
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE bool operator==(
+    double op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  return op2.operator==(op1);
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE bool operator!=(
+    double op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  return op2.operator!=(op1);
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE bool operator>(
+    double op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  return op2.operator<(op1);
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE bool operator>=(
+    double op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  return op2.operator<=(op1);
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE bool operator<(
+    double op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  return op2.operator>(op1);
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE bool operator<=(
+    double op1,
+    const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op2) {
+  return op2.operator>=(op1);
+}
+
+#endif // ifndef __cplusplus else
+
+#endif // ifndef __AP_FIXED_BASE_H__ else
+
+// -*- cpp -*-

firmware/ap_types/ap_fixed_ref.h

@@ -0,0 +1,718 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_FIXED_REF_H__
+#define __AP_FIXED_REF_H__
+
+#ifndef __AP_FIXED_H__
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+#ifndef __cplusplus
+#error "C++ is required to include this header file"
+
+#else
+#ifndef __SYNTHESIS__
+#include <iostream>
+#endif
+/// Proxy class, which allows bit selection  to be used as both rvalue (for
+/// reading) and lvalue (for writing)
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+struct af_bit_ref {
+#ifdef _MSC_VER
+#pragma warning(disable : 4521 4522)
+#endif
+  typedef ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> ref_type;
+  ref_type& d_bv;
+  int d_index;
+
+ public:
+  INLINE af_bit_ref(
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ref)
+      : d_bv(ref.d_bv), d_index(ref.d_index) {
+#ifndef __SYNTHESIS__
+    _AP_WARNING(d_index < 0, "Index of bit vector  (%d) cannot be negative.",
+                d_index);
+    _AP_WARNING(d_index >= _AP_W, "Index of bit vector (%d) out of range (%d).",
+                d_index, _AP_W);
+#endif
+  }
+
+  INLINE af_bit_ref(ref_type* bv, int index = 0) : d_bv(*bv), d_index(index) {}
+
+  INLINE af_bit_ref(const ref_type* bv, int index = 0)
+      : d_bv(*const_cast<ref_type*>(bv)), d_index(index) {}
+
+  /// convert operators.
+  INLINE operator bool() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); }
+
+  /// @name assign operators
+  //  @{
+  INLINE af_bit_ref& operator=(bool val) {
+    d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index, val);
+    return *this;
+  }
+
+  // Be explicit to prevent it from being deleted, as field d_bv
+  // is of reference type.
+  INLINE af_bit_ref& operator=(const af_bit_ref& val) {
+    return operator=(bool(val));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE af_bit_ref& operator=(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    return operator=(bool(val));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_bit_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) {
+    return operator=(bool(val));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_bit_ref& operator=(const ap_int_base<_AP_W2, _AP_S2>& val) {
+    return operator=(val != 0);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_bit_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) {
+    return operator=(ap_int_base<_AP_W2, false>(val));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE af_bit_ref& operator=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    return operator=(ap_int_base<_AP_W2, false>(val));
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE af_bit_ref& operator=(
+      const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+    return operator=(ap_int_base<_AP_W2 + _AP_W3, false>(val));
+  }
+  //  @}
+
+  /// @name concatenate operators
+  //  @{
+  template <int _AP_W2, int _AP_S2>
+  INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(ap_int_base<_AP_W2, _AP_S2> &op) {
+    return ap_concat_ref<1, af_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >(
+        *this, op);
+  }
+
+  template <int _AP_W2, int _AP_S2>
+  INLINE ap_concat_ref<1, af_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> > operator,(
+      const ap_bit_ref<_AP_W2, _AP_S2> &op) {
+    return ap_concat_ref<1, af_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >(*this,
+                                                                        op);
+  }
+
+  template <int _AP_W2, int _AP_S2>
+  INLINE ap_concat_ref<1, af_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+  operator,(const ap_range_ref<_AP_W2, _AP_S2> &op) {
+    return ap_concat_ref<1, af_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >(
+        *this, op);
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+  operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) {
+    return ap_concat_ref<1, af_bit_ref, _AP_W2 + _AP_W3,
+                         ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                                                                         op);
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<
+      1, af_bit_ref, _AP_W2,
+      af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &op) {
+    return ap_concat_ref<
+        1, af_bit_ref, _AP_W2,
+        af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                                                                       op);
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<1, af_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                                    _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &op) {
+    return ap_concat_ref<1, af_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                                      _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(
+            op));
+  }
+  //  @}
+
+  /// @name comparison
+  //  @{
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator==(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    return get() == op.get();
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator!=(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    return get() != op.get();
+  }
+  //  @}
+
+  INLINE bool operator~() const {
+    bool bit = _AP_ROOT_op_get_bit(d_bv.V, d_index);
+    return bit ? false : true;
+  }
+
+  INLINE bool get() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); }
+
+  INLINE int length() const { return 1; }
+
+#ifndef __SYNTHESIS__
+  std::string to_string() const { return get() ? "1" : "0"; }
+#else
+  // XXX HLS will delete this in synthesis
+  INLINE char* to_string() const { return 0; }
+#endif
+}; // struct af_bit_ref
+
+// XXX apcc cannot handle global std::ios_base::Init() brought in by <iostream>
+#ifndef AP_AUTOCC
+#ifndef __SYNTHESIS__
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE std::ostream& operator<<(
+    std::ostream& os,
+    const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) {
+  os << x.to_string();
+  return os;
+}
+#endif // ifndef __SYNTHESIS__
+#endif // ifndef AP_AUTOCC
+
+/// Range (slice) reference.
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+struct af_range_ref {
+#ifdef _MSC_VER
+#pragma warning(disable : 4521 4522)
+#endif
+  typedef ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> ref_type;
+  ref_type& d_bv;
+  int l_index;
+  int h_index;
+
+ public:
+  /// copy ctor
+  INLINE af_range_ref(
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& ref)
+      : d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {}
+
+  /// ctor from ap_fixed_base, higher and lower bound.
+  /** if h is less than l, the bits selected will be returned in reverse order.
+   */
+  INLINE af_range_ref(ref_type* bv, int h, int l)
+      : d_bv(*bv), l_index(l), h_index(h) {
+#ifndef __SYNTHESIS__
+    _AP_WARNING(h < 0 || l < 0,
+                "Higher bound(%d) and lower(%d) bound cannot be negative.", h,
+                l);
+    _AP_WARNING(h >= _AP_W || l >= _AP_W,
+                "Higher bound(%d) or lower(%d) bound out of range.", h, l);
+    _AP_WARNING(h < l, "The bits selected will be returned in reverse order.");
+#endif
+  }
+
+  INLINE af_range_ref(const ref_type* bv, int h, int l)
+      : d_bv(*const_cast<ref_type*>(bv)), l_index(l), h_index(h) {
+#ifndef __SYNTHESIS__
+    _AP_WARNING(h < 0 || l < 0,
+                "Higher bound(%d) and lower(%d) bound cannot be negative.", h,
+                l);
+    _AP_WARNING(h >= _AP_W || l >= _AP_W,
+                "Higher bound(%d) or lower(%d) bound out of range.", h, l);
+    _AP_WARNING(h < l, "The bits selected will be returned in reverse order.");
+#endif
+  }
+
+  /// @name assign operators
+  //  @{
+
+#define ASSIGN_CTYPE_TO_AF_RANGE(DATA_TYPE)                          \
+  INLINE af_range_ref& operator=(const DATA_TYPE val) {              \
+    ap_int_base<_AP_W, false> loc(val);                              \
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, loc.V); \
+    return *this;                                                    \
+  }
+
+  ASSIGN_CTYPE_TO_AF_RANGE(bool)
+  ASSIGN_CTYPE_TO_AF_RANGE(char)
+  ASSIGN_CTYPE_TO_AF_RANGE(signed char)
+  ASSIGN_CTYPE_TO_AF_RANGE(unsigned char)
+  ASSIGN_CTYPE_TO_AF_RANGE(short)
+  ASSIGN_CTYPE_TO_AF_RANGE(unsigned short)
+  ASSIGN_CTYPE_TO_AF_RANGE(int)
+  ASSIGN_CTYPE_TO_AF_RANGE(unsigned int)
+  ASSIGN_CTYPE_TO_AF_RANGE(long)
+  ASSIGN_CTYPE_TO_AF_RANGE(unsigned long)
+  ASSIGN_CTYPE_TO_AF_RANGE(ap_slong)
+  ASSIGN_CTYPE_TO_AF_RANGE(ap_ulong)
+#if _AP_ENABLE_HALF_ == 1
+  ASSIGN_CTYPE_TO_AF_RANGE(half)
+#endif
+  ASSIGN_CTYPE_TO_AF_RANGE(float)
+  ASSIGN_CTYPE_TO_AF_RANGE(double)
+#undef ASSIGN_CTYPE_TO_AF_RANGE
+
+  /// assgin using a string. XXX crucial for cosim.
+  INLINE af_range_ref& operator=(const char* val) {
+    const ap_int_base<_AP_W, false> tmp(val); // XXX figure out radix
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V);
+    return *this;
+  }
+
+  /// assign from ap_int_base.
+  // NOTE Base of other assgin operators.
+  template <int _AP_W3, bool _AP_S3>
+  INLINE af_range_ref& operator=(const ap_int_base<_AP_W3, _AP_S3>& val) {
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V);
+    return *this;
+  }
+
+  /// assign from range reference to ap_int_base.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_range_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) {
+    const ap_int_base<_AP_W2, false> tmp(val);
+    return operator=(tmp);
+  }
+
+  /// assign from bit reference to ap_int_base..
+  template <int _AP_W2, bool _AP_S2>
+  INLINE af_range_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) {
+    const ap_int_base<1, false> tmp((bool)val);
+    return operator=(tmp);
+  }
+
+  /// assgin from ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE af_range_ref& operator=(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&
+          val) {
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V);
+    return *this;
+  }
+
+  /// copy assgin.
+  // XXX This has to be explicit, otherwise it will be deleted, as d_bv is
+  // of reference type.
+  INLINE af_range_ref& operator=(const af_range_ref& val) {
+    ap_int_base<_AP_W, false> tmp(val);
+    return operator=(tmp);
+  }
+
+  /// assign from range reference to ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE af_range_ref& operator=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    ap_int_base<_AP_W2, false> tmp(val);
+    return operator=(tmp);
+  }
+
+  /// assign from bit reference to ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE af_range_ref& operator=(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    ap_int_base<1, false> tmp((bool)val);
+    return operator=(tmp);
+  }
+
+  /// assign from compound reference.
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE af_range_ref& operator=(
+      const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+    const ap_int_base<_AP_W2 + _AP_W3, false> tmp(val);
+    return operator=(tmp);
+  }
+  //  @}
+
+  /// @name comparison operators with ap_range_ref.
+  //  @{
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator==(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> rop(op2);
+    return lop == rop;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator!=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return !(operator==(op2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator<(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> rop(op2);
+    return lop < rop;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator>(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> rop(op2);
+    return lop > rop;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator<=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return !(operator>(op2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator>=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return !(operator<(op2));
+  }
+  //  @}
+
+  /// @name comparison operators with af_range_ref.
+  //  @{
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator==(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> rop(op2);
+    return lop == rop;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator!=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+    return !(operator==(op2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator<(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> rop(op2);
+    return lop < rop;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator>(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> rop(op2);
+    return lop > rop;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator<=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+    return !(operator>(op2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE bool operator>=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op2) {
+    return !(operator<(op2));
+  }
+  //  @}
+
+  /// @name concatenate operators.
+  /// @{
+  /// concatenate with ap_int_base.
+  template <int _AP_W2, int _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+      operator,(ap_int_base<_AP_W2, _AP_S2> &op) {
+    return ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(*this, op);
+  }
+
+  /// concatenate with ap_bit_ref.
+  template <int _AP_W2, int _AP_S2>
+  INLINE ap_concat_ref<_AP_W, af_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+  operator,(const ap_bit_ref<_AP_W2, _AP_S2> &op) {
+    return ap_concat_ref<_AP_W, af_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_bit_ref<_AP_W2, _AP_S2>&>(op));
+  }
+
+  /// concatenate with ap_bit_ref.
+  template <int _AP_W2, int _AP_S2>
+  INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+  operator,(const ap_range_ref<_AP_W2, _AP_S2> &op) {
+    return ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+                         ap_range_ref<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_range_ref<_AP_W2, _AP_S2>&>(op));
+  }
+
+  /// concatenate with ap_concat_ref.
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+  operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &op) {
+    return ap_concat_ref<_AP_W, af_range_ref, _AP_W2 + _AP_W3,
+                         ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(
+        *this, const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>&>(op));
+  }
+
+  /// concatenate with another af_range_ref.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE
+      ap_concat_ref<_AP_W, af_range_ref, _AP_W2,
+                    af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+      operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>
+                    &op) {
+    return ap_concat_ref<
+        _AP_W, af_range_ref, _AP_W2,
+        af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(
+            op));
+  }
+
+  /// concatenate with another af_bit_ref.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE
+      ap_concat_ref<_AP_W, af_range_ref, 1,
+                    af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+      operator,(
+          const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &op) {
+    return ap_concat_ref<
+        _AP_W, af_range_ref, 1,
+        af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(
+            op));
+  }
+  //  @}
+
+  INLINE operator ap_ulong() const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret.to_uint64();
+  }
+
+  INLINE operator ap_int_base<_AP_W, false>() const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret;
+  }
+
+  INLINE ap_int_base<_AP_W, false> to_ap_int_base() const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret;
+  }
+
+  // used in ap_fixed_base::to_string()
+  INLINE char to_char() const {
+    return (char)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE int to_int() const {
+    return (int)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE unsigned to_uint() const {
+    return (unsigned)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE long to_long() const {
+    return (long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE unsigned long to_ulong() const {
+    return (unsigned long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE ap_slong to_int64() const {
+    return (ap_slong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE ap_ulong to_uint64() const {
+    return (ap_ulong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE ap_int_base<_AP_W, false> get() const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret;
+  }
+
+  template <int _AP_W2>
+  INLINE void set(const ap_int_base<_AP_W2, false>& val) {
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V);
+  }
+
+  INLINE int length() const {
+    return h_index >= l_index ? h_index - l_index + 1 : l_index - h_index + 1;
+  }
+
+#ifndef __SYNTHESIS__
+  std::string to_string(signed char rd = 2) const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret.to_string(rd);
+  }
+#else
+  // XXX HLS will delete this in synthesis
+  INLINE char* to_string(signed char rd = 2) const {
+    return 0;
+  }
+#endif
+}; // struct af_range_ref
+
+// XXX apcc cannot handle global std::ios_base::Init() brought in by <iostream>
+#ifndef AP_AUTOCC
+#ifndef __SYNTHESIS__
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O,
+          int _AP_N>
+INLINE std::ostream& operator<<(
+    std::ostream& os,
+    const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& x) {
+  os << x.to_string();
+  return os;
+}
+#endif
+#endif // ifndef AP_AUTOCC
+
+#define AF_REF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)            \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N>                                   \
+  INLINE bool operator REL_OP(                                            \
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,   \
+      C_TYPE op2) {                                                       \
+    return ap_int_base<_AP_W, false>(op)                                  \
+        REL_OP ap_int_base<_AP_W2, _AP_S2>(op2);                          \
+  }                                                                       \
+                                                                          \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N>                                   \
+  INLINE bool operator REL_OP(                                            \
+      C_TYPE op2,                                                         \
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \
+    return ap_int_base<_AP_W2, _AP_S2>(op2)                               \
+        REL_OP ap_int_base<_AP_W, false>(op);                             \
+  }                                                                       \
+                                                                          \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N>                                   \
+  INLINE bool operator REL_OP(                                            \
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,     \
+      C_TYPE op2) {                                                       \
+    return bool(op) REL_OP op2;                                           \
+  }                                                                       \
+                                                                          \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N>                                   \
+  INLINE bool operator REL_OP(                                            \
+      C_TYPE op2,                                                         \
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {   \
+    return op2 REL_OP bool(op);                                           \
+  }
+
+#define AF_REF_REL_OPS_WITH_INT(C_TYPE, _AP_W2, _AP_S2)  \
+  AF_REF_REL_OP_WITH_INT(>, C_TYPE, (_AP_W2), (_AP_S2))  \
+  AF_REF_REL_OP_WITH_INT(<, C_TYPE, (_AP_W2), (_AP_S2))  \
+  AF_REF_REL_OP_WITH_INT(>=, C_TYPE, (_AP_W2), (_AP_S2)) \
+  AF_REF_REL_OP_WITH_INT(<=, C_TYPE, (_AP_W2), (_AP_S2)) \
+  AF_REF_REL_OP_WITH_INT(==, C_TYPE, (_AP_W2), (_AP_S2)) \
+  AF_REF_REL_OP_WITH_INT(!=, C_TYPE, (_AP_W2), (_AP_S2))
+
+AF_REF_REL_OPS_WITH_INT(bool, 1, false)
+AF_REF_REL_OPS_WITH_INT(char, 8, CHAR_IS_SIGNED)
+AF_REF_REL_OPS_WITH_INT(signed char, 8, true)
+AF_REF_REL_OPS_WITH_INT(unsigned char, 8, false)
+AF_REF_REL_OPS_WITH_INT(short, _AP_SIZE_short, true)
+AF_REF_REL_OPS_WITH_INT(unsigned short, _AP_SIZE_short, false)
+AF_REF_REL_OPS_WITH_INT(int, _AP_SIZE_int, true)
+AF_REF_REL_OPS_WITH_INT(unsigned int, _AP_SIZE_int, false)
+AF_REF_REL_OPS_WITH_INT(long, _AP_SIZE_long, true)
+AF_REF_REL_OPS_WITH_INT(unsigned long, _AP_SIZE_long, false)
+AF_REF_REL_OPS_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+AF_REF_REL_OPS_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef AF_REF_REL_OP_INT
+#undef AF_REF_REL_OPS_WITH_INT
+
+#define AF_REF_REL_OP_WITH_AP_INT(REL_OP)                                 \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>          \
+  INLINE bool operator REL_OP(                                            \
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,   \
+      const ap_int_base<_AP_W2, _AP_S>& op2) {                            \
+    return ap_int_base<_AP_W, false>(op) REL_OP op2;                      \
+  }                                                                       \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>          \
+  INLINE bool operator REL_OP(                                            \
+      const ap_int_base<_AP_W2, _AP_S2>& op2,                             \
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) { \
+    return op2 REL_OP ap_int_base<_AP_W, false>(op);                      \
+  }                                                                       \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>          \
+  INLINE bool operator REL_OP(                                            \
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op,     \
+      const ap_int_base<_AP_W2, _AP_S2>& op2) {                           \
+    return ap_int_base<1, false>(op) REL_OP op2;                          \
+  }                                                                       \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,            \
+            ap_o_mode _AP_O, int _AP_N, int _AP_W2, bool _AP_S2>          \
+  INLINE bool operator REL_OP(                                            \
+      const ap_int_base<_AP_W2, _AP_S2>& op2,                             \
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>& op) {   \
+    return op2 REL_OP ap_int_base<1, false>(op);                          \
+  }
+
+AF_REF_REL_OP_WITH_AP_INT(>)
+AF_REF_REL_OP_WITH_AP_INT(<)
+AF_REF_REL_OP_WITH_AP_INT(>=)
+AF_REF_REL_OP_WITH_AP_INT(<=)
+AF_REF_REL_OP_WITH_AP_INT(==)
+AF_REF_REL_OP_WITH_AP_INT(!=)
+
+#endif // ifndef __cplusplus
+
+#endif // ifndef __AP_FIXED_REF_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_fixed_special.h

@@ -0,0 +1,230 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_FIXED_SPECIAL_H__
+#define __AP_FIXED_SPECIAL_H__
+
+#ifndef __AP_FIXED_H__
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+#ifndef __SYNTHESIS__
+#include <cstdio>
+#include <cstdlib>
+#endif
+// FIXME AP_AUTOCC cannot handle many standard headers, so declare instead of
+// include.
+// #include <complex>
+namespace std {
+template<typename _Tp> class complex;
+}
+
+/*
+  TODO: Modernize the code using C++11/C++14
+  1. constexpr http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0415r0.html
+  2. move constructor
+*/
+
+namespace std {
+/*
+   Specialize std::complex<ap_fixed> to zero initialization ap_fixed.
+
+   To reduce the area cost, ap_fixed is not zero initialized, just like basic
+   types float or double. However, libstdc++ provides specialization for float,
+   double and long double, initializing image part to 0 when not specified.
+
+   This has become a difficulty in switching legacy code from these C types to
+   ap_fixed. To ease the tranform of legacy code, we have to implement
+   specialization of std::complex<> for our type.
+
+   As ap_fixed is a template, it is impossible to specialize only the methods
+   that causes default initialization of value type in std::complex<>. An
+   explicit full specialization of the template class has to be done, covering
+   all the member functions and operators of std::complex<> as specified
+   in standard 26.2.4 and 26.2.5.
+*/
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+class complex<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> > {
+ public:
+  typedef ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> _Tp;
+  typedef _Tp value_type;
+
+  // 26.2.4/1
+  // Constructor without argument
+  // Default initialize, so that in dataflow, the variable is only written once.
+  complex() : _M_real(_Tp()), _M_imag(_Tp()) {}
+  // Constructor with ap_fixed.
+  // Zero initialize image part when not specified, so that `C(1) == C(1,0)`
+  complex(const _Tp &__r, const _Tp &__i = _Tp(0))
+      : _M_real(__r), _M_imag(__i) {}
+
+  // Constructor with another complex number
+  template <typename _Up>
+  complex(const complex<_Up> &__z) : _M_real(__z.real()), _M_imag(__z.imag()) {}
+
+#if __cplusplus >= 201103L
+  const _Tp& real() const { return _M_real; }
+  const _Tp& imag() const { return _M_imag; }
+#else
+  _Tp& real() { return _M_real; }
+  const _Tp& real() const { return _M_real; }
+  _Tp& imag() { return _M_imag; }
+  const _Tp& imag() const { return _M_imag; }
+#endif
+ 
+  void real(_Tp __val) { _M_real = __val; }
+
+  void imag(_Tp __val) { _M_imag = __val; }
+
+  // Assign this complex number with ap_fixed.
+  // Zero initialize image poarrt, so that `C c; c = 1; c == C(1,0);`
+  complex<_Tp> &operator=(const _Tp __t) {
+    _M_real = __t;
+    _M_imag = _Tp(0);
+    return *this;
+  }
+
+  // 26.2.5/1
+  // Add ap_fixed to this complex number.
+  complex<_Tp> &operator+=(const _Tp &__t) {
+    _M_real += __t;
+    return *this;
+  }
+
+  // 26.2.5/3
+  // Subtract ap_fixed from this complex number.
+  complex<_Tp> &operator-=(const _Tp &__t) {
+    _M_real -= __t;
+    return *this;
+  }
+
+  // 26.2.5/5
+  // Multiply this complex number by ap_fixed.
+  complex<_Tp> &operator*=(const _Tp &__t) {
+    _M_real *= __t;
+    _M_imag *= __t;
+    return *this;
+  }
+
+  // 26.2.5/7
+  // Divide this complex number by ap_fixed.
+  complex<_Tp> &operator/=(const _Tp &__t) {
+    _M_real /= __t;
+    _M_imag /= __t;
+    return *this;
+  }
+
+  // Assign complex number to this complex number.
+  template <typename _Up>
+  complex<_Tp> &operator=(const complex<_Up> &__z) {
+    _M_real = __z.real();
+    _M_imag = __z.imag();
+    return *this;
+  }
+
+  // 26.2.5/9
+  // Add complex number to this.
+  template <typename _Up>
+  complex<_Tp> &operator+=(const complex<_Up> &__z) {
+    _M_real += __z.real();
+    _M_imag += __z.imag();
+    return *this;
+  }
+
+  // 26.2.5/11
+  // Subtract complex number from this.
+  template <typename _Up>
+  complex<_Tp> &operator-=(const complex<_Up> &__z) {
+    _M_real -= __z.real();
+    _M_imag -= __z.imag();
+    return *this;
+  }
+
+  // 26.2.5/13
+  // Multiply this by complex number.
+  template <typename _Up>
+  complex<_Tp> &operator*=(const complex<_Up> &__z) {
+    const _Tp __r = _M_real * __z.real() - _M_imag * __z.imag();
+    _M_imag = _M_real * __z.imag() + _M_imag * __z.real();
+    _M_real = __r;
+    return *this;
+  }
+
+  // 26.2.5/15
+  // Divide this by complex number.
+  template <typename _Up>
+  complex<_Tp> &operator/=(const complex<_Up> &__z) {
+    complex<_Tp> cj (__z.real(), -__z.imag());
+    complex<_Tp> a = (*this) * cj;
+    complex<_Tp> b = cj * __z;
+    _M_real = a.real() / b.real();
+    _M_imag = a.imag() / b.real();
+    return *this;
+  }
+
+ private:
+  _Tp _M_real;
+  _Tp _M_imag;
+
+}; // class complex<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> >
+
+/*
+   Non-member operations
+   These operations are not required by standard in 26.2.6, but libstdc++
+   defines them for
+   float, double or long double's specialization.
+*/
+// Compare complex number with ap_fixed.
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+inline bool operator==(
+    const complex<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> > &__x,
+    const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__y) {
+  return __x.real() == __y &&
+         __x.imag() == 0;
+}
+
+// Compare ap_fixed with complex number.
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+inline bool operator==(
+    const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__x,
+    const complex<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> > &__y) {
+  return __x == __y.real() &&
+         0 == __y.imag();
+}
+
+// Compare complex number with ap_fixed.
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+inline bool operator!=(
+    const complex<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> > &__x,
+    const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__y) {
+  return __x.real() != __y ||
+         __x.imag() != 0;
+}
+
+// Compare ap_fixed with complex number.
+template <int _AP_W, int _AP_I, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+inline bool operator!=(
+    const ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> &__x,
+    const complex<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N> > &__y) {
+  return __x != __y.real() ||
+         0 != __y.imag();
+}
+
+}  // namespace std
+
+#endif  // ifndef __AP_FIXED_SPECIAL_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_float.h

@@ -0,0 +1,186 @@
+#ifndef __AP_FLOAT_H__
+#define __AP_FLOAT_H__
+
+#define __AP_FLOAT_H_MAX(a, b) ((a) > (b) ? (a) : (b))
+
+constexpr int ceillog2(int x) { return (x <= 2) ? 1 : 1 + ceillog2((x + 1) / 2); }
+
+#include "ap_fixed.h"
+#include <cassert>
+#include <cmath>
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE ap_fixed_base<_AP_W, _AP_I, false, _AP_Q, _AP_O, _AP_N>
+abs(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) {
+    if (value > 0) {
+        return value;
+    } else {
+        return -value;
+    }
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE ap_uint<ceillog2(_AP_W)> msb_loc(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) {
+    auto buf = abs(value);
+    ap_uint<ceillog2(_AP_W)> msb = 0;
+    for (int i = 0; i < _AP_W; i++) {
+#pragma HLS UNROLL
+        if (buf[i] && msb < i) {
+            msb = i;
+        }
+    }
+    return msb;
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE auto rt_floorlog2(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value)
+    -> ap_int_base<ceillog2(__AP_FLOAT_H_MAX(_AP_I - _AP_S, _AP_W - _AP_I + 1)) + (_AP_W - _AP_I > 0), (_AP_W - _AP_I > 0)> {
+    // Runtime floorlog2 for fixed point numbers
+    auto msb = msb_loc(value);
+    ap_int_base<6, 1> r = msb;
+    return r - (_AP_W - _AP_I);
+}
+
+template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+INLINE auto rt_ceillog2(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) -> decltype(rt_floorlog2(value)) {
+    // Runtime ceillog2 for fixed point numbers
+    auto msb = msb_loc(value);
+    ap_ufixed<_AP_W, _AP_I> buf;
+    if (value > 0) {
+        buf = value;
+    } else {
+        buf = -value;
+    }
+    bool is_pow2 = buf << (_AP_W - msb) == 0;
+    return msb + !is_pow2 - (_AP_W - _AP_I);
+}
+
+template <int M, int E, int E0, int W, int I> INLINE bool cond_minimal_normal(ap_ufixed<W, I> abs_value) {
+    bool is_normal = true;
+    for (int i = 0; i < M + 1; ++i) {
+#pragma HLS UNROLL
+        is_normal &= abs_value[W - I - (1 << (E - 1)) + E0 - i];
+    }
+    return is_normal;
+}
+
+template <int M, int E, int E0 = 0> struct ap_float {
+
+    bool is_negative;
+    typedef ap_ufixed<M, 0, AP_RND_CONV, AP_SAT> mantissa_t;
+    typedef ap_fixed<E, E, AP_TRN, AP_SAT> exponent_t;
+    typedef ap_ufixed<M + 1, 1> opr_mantissa_t;
+    typedef ap_ufixed<M + 1, 1 + E0> opr_mantissa2_t;
+    mantissa_t mantissa;
+    exponent_t exponent;
+    INLINE ap_float() {}
+    INLINE ap_float(mantissa_t mantissa, exponent_t exponent) : mantissa(mantissa), exponent(exponent) {}
+
+    template <typename T> INLINE ap_float(T value) { *this = ap_fixed<32, 16>(value); }
+
+    template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+    INLINE int operator=(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> value) {
+        is_negative = value < 0;
+        ap_ufixed<M + 1, 1, AP_RND_CONV, AP_SAT> _mantissa;
+        ap_ufixed<_AP_W - _AP_S, _AP_I - _AP_S> abs_value = abs(value);
+        exponent = rt_floorlog2(abs_value) - E0; // E0 is the offset
+
+        // std::cout << "cond=" << (abs_value >> (-(1 << (E - 1)) + E0)).to_float() << std::endl;
+        if (exponent != -(1 << (E - 1))) {
+            // Normal
+            _mantissa = (abs_value >> (ap_int<E>(exponent) + E0)) - 1;
+        } else {
+            // Subnormal
+            _mantissa = (abs_value >> (ap_int<E>(exponent + 1) + E0));
+        }
+        if (_mantissa >= 1 && exponent != (1 << (E - 1)) - 1) {
+            exponent = exponent + 1;
+            _mantissa = 0;
+        }
+        mantissa = _mantissa;
+
+        return 0;
+    }
+
+    INLINE ap_fixed<M + (1 << E) + 1, 1 + (1 << (E - 1)) + E0> to_ap_fixed() const {
+
+        ap_ufixed<M + (1 << E), (1 << (E - 1))> _result;
+        int shift = exponent;
+        if (exponent == -(1 << (E - 1))) {
+            shift += 1;
+            _result = mantissa;
+        } else {
+            _result = mantissa + 1;
+        }
+
+        ap_ufixed<M + (1 << E), (1 << (E - 1)) + E0> result;
+
+        _result = _result << shift;
+        result.range() = _result.range();
+        if (is_negative)
+            return -result;
+        else
+            return result;
+    }
+
+    INLINE double to_float() const { return to_ap_fixed().to_float(); }
+    INLINE operator float() const { return to_float(); }
+    INLINE operator double() const { return to_float(); }
+
+    template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+    auto operator*(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> other)
+        -> ap_fixed<M + (1 << E) - 1 + _AP_W + (!_AP_S), 1 + (1 << (E - 1)) - 1 + E0 + _AP_I + (!_AP_S)> {
+
+        int shift = exponent;
+        opr_mantissa_t mantissa;
+        if (exponent == -(1 << (E - 1))) {
+            shift += 1;
+            mantissa = this->mantissa;
+        } else {
+            mantissa = this->mantissa + 1;
+        }
+        opr_mantissa2_t mantissa2;
+        mantissa2.range() = mantissa.range();
+
+        constexpr int E_max = (1 << (E - 1)) - 1 + E0;
+        constexpr int E_min = -(1 << (E - 1)) + E0;
+        constexpr int I = 1 + E_max + _AP_I + (!_AP_S);
+        constexpr int W = M + 1 + _AP_W + E_max - E_min + 1 + (!_AP_S);
+        // std::cout << "W=" << W << std::endl;
+        // std::cout << "I=" << I << std::endl;
+        // std::cout << "E_max=" << E_max << std::endl;
+        // std::cout << "E_min=" << E_min << std::endl;
+        ap_fixed<W, I> result_fixed = mantissa2 * other;
+
+        if (is_negative) {
+            result_fixed = -result_fixed;
+        }
+        result_fixed <<= shift;
+        return result_fixed;
+    }
+
+    template <int _M, int _E, int _E0> ap_float<_M, _E, _E0> operator*(ap_float<_M, _E, _E0> other) {
+        assert(0); // ap_float can only be multiplied by ap_fixed
+    }
+};
+
+template <int M, int E, int E0, int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q, ap_o_mode _AP_O, int _AP_N>
+auto operator*(ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> a, ap_float<M, E, E0> b) -> decltype(b * a) {
+    return b * a;
+}
+
+#ifndef __SYNTHESIS__
+template <int M, int E, int E0> int operator>>(std::istringstream s, ap_float<M, E, E0> &b) {
+    std::string str;
+    s >> str;
+    b = std::stof(str);
+    return 0;
+}
+
+template <int M, int E, int E0> std::ostream &operator<<(std::ostream &os, const ap_float<M, E, E0> &b) {
+    os << b.to_float();
+    return os;
+}
+#endif
+
+#endif

firmware/ap_types/ap_int.h

@@ -0,0 +1,330 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_INT_H__
+#define __AP_INT_H__
+
+#include <ap_common.h>
+#include <ap_int_base.h>
+#include <ap_int_ref.h>
+
+//---------------------------------------------------------------
+
+/// Sign Arbitrary Precision Type.
+template <int _AP_W>
+struct ap_int : ap_int_base<_AP_W, true> {
+  typedef ap_int_base<_AP_W, true> Base;
+  // Constructor
+  INLINE ap_int() : Base() {}
+
+  // Copy ctor
+  INLINE ap_int(const ap_int& op) { Base::V = op.V; }
+
+  template <int _AP_W2>
+  INLINE ap_int(const ap_int<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_int(const volatile ap_int<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_int(const ap_uint<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_int(const volatile ap_uint<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int(const ap_range_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int(const ap_bit_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {}
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_int(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref)
+      : Base(ref) {}
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_int(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {}
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_int(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) {
+  }
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_int(
+      const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {}
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_int(
+      const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) {
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int(const ap_int_base<_AP_W2, _AP_S2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+#define CTOR(TYPE) \
+  INLINE ap_int(TYPE val) { Base::V = val; }
+  CTOR(bool)
+  CTOR(char)
+  CTOR(signed char)
+  CTOR(unsigned char)
+  CTOR(short)
+  CTOR(unsigned short)
+  CTOR(int)
+  CTOR(unsigned int)
+  CTOR(long)
+  CTOR(unsigned long)
+  CTOR(ap_slong)
+  CTOR(ap_ulong)
+#undef CTOR
+  ap_int(double val) : Base(val) {}
+  ap_int(float val) : Base(val) {}
+#if _AP_ENABLE_HALF_ == 1
+  ap_int(half val) : Base(val) {}
+#endif
+
+  // ap_int_base will guess radix if radix is not provided.
+  INLINE ap_int(const char* s) : Base(s) {}
+
+  INLINE ap_int(const char* s, signed char rd) : Base(s, rd) {}
+
+  // Assignment
+  /* ctor will be used when right is not of proper type. */
+
+  INLINE ap_int& operator=(const ap_int<_AP_W>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  /* cannot bind volatile reference to non-volatile type. */
+  INLINE ap_int& operator=(const volatile ap_int<_AP_W>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  /* cannot return volatile *this. */
+  INLINE void operator=(const ap_int<_AP_W>& op2) volatile { Base::V = op2.V; }
+
+  INLINE void operator=(const volatile ap_int<_AP_W>& op2) volatile {
+    Base::V = op2.V;
+  }
+
+}; // struct ap_int.
+
+//---------------------------------------------------------------
+
+/// Unsigned Arbitrary Precision Type.
+template <int _AP_W>
+struct ap_uint : ap_int_base<_AP_W, false> {
+  typedef ap_int_base<_AP_W, false> Base;
+  // Constructor
+  INLINE ap_uint() : Base() {}
+
+  // Copy ctor
+  INLINE ap_uint(const ap_uint& op) { Base::V = op.V; }
+
+  template <int _AP_W2>
+  INLINE ap_uint(const ap_uint<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_uint(const ap_int<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_uint(const volatile ap_uint<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_uint(const volatile ap_int<_AP_W2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_uint(const ap_range_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_uint(const ap_bit_ref<_AP_W2, _AP_S2>& ref) : Base(ref) {}
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_uint(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref)
+      : Base(ref) {}
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_uint(const ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {}
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_uint(const ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) {
+  }
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_uint(
+      const volatile ap_fixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, true, _AP_Q2, _AP_O2, _AP_N2>)op) {}
+
+  template <int _AP_W2, int _AP_I2, ap_q_mode _AP_Q2, ap_o_mode _AP_O2,
+            int _AP_N2>
+  INLINE ap_uint(
+      const volatile ap_ufixed<_AP_W2, _AP_I2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base((ap_fixed_base<_AP_W2, _AP_I2, false, _AP_Q2, _AP_O2, _AP_N2>)op) {
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_uint(const ap_int_base<_AP_W2, _AP_S2>& op) {
+    Base::V = op.V;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_uint(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_uint(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_uint(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op)
+      : Base(op) {}
+
+#define CTOR(TYPE) \
+  INLINE ap_uint(TYPE val) { Base::V = val; }
+  CTOR(bool)
+  CTOR(char)
+  CTOR(signed char)
+  CTOR(unsigned char)
+  CTOR(short)
+  CTOR(unsigned short)
+  CTOR(int)
+  CTOR(unsigned int)
+  CTOR(long)
+  CTOR(unsigned long)
+  CTOR(ap_slong)
+  CTOR(ap_ulong)
+#undef CTOR
+  ap_uint(double val) : Base(val) {}
+  ap_uint(float val) : Base(val) {}
+#if _AP_ENABLE_HALF_ == 1
+  ap_uint(half val) : Base(val) {}
+#endif
+
+  // ap_int_base will guess radix if radix is not provided.
+  INLINE ap_uint(const char* s) : Base(s) {}
+
+  INLINE ap_uint(const char* s, signed char rd) : Base(s, rd) {}
+
+  // Assignment
+  /* XXX ctor will be used when right is not of proper type. */
+
+  INLINE ap_uint& operator=(const ap_uint<_AP_W>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  /* cannot bind volatile reference to non-volatile type. */
+  INLINE ap_uint& operator=(const volatile ap_uint<_AP_W>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  /* cannot return volatile *this. */
+  INLINE void operator=(const ap_uint<_AP_W>& op2) volatile { Base::V = op2.V; }
+
+  INLINE void operator=(const volatile ap_uint<_AP_W>& op2) volatile {
+    Base::V = op2.V;
+  }
+
+}; // struct ap_uint.
+
+#define ap_bigint ap_int
+#define ap_biguint ap_uint
+
+#if !defined(__SYNTHESIS__) && (defined(SYSTEMC_H) || defined(SYSTEMC_INCLUDED))
+// XXX sc_trace overload for ap_fixed is already included in
+// "ap_sysc/ap_sc_extras.h", so do not define in synthesis.
+template <int _AP_W>
+INLINE void sc_trace(sc_core::sc_trace_file* tf, const ap_int<_AP_W>& op,
+                     const std::string& name) {
+  if (tf) tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+
+template <int _AP_W>
+INLINE void sc_trace(sc_core::sc_trace_file* tf, const ap_uint<_AP_W>& op,
+                     const std::string& name) {
+  if (tf) tf->trace(sc_dt::sc_lv<_AP_W>(op.to_string(2).c_str()), name);
+}
+#endif // System C sim
+
+#include <ap_int_special.h>
+
+#endif // ifndef __AP_INT_H__ else
+
+// FIXME user should include ap_fixed.h when using ap_fixed.
+// to avoid circular inclusion, must check whether this is required by
+// ap_fixed.h
+#ifndef __AP_FIXED_H__
+#include <ap_fixed.h>
+#endif
+
+// -*- cpp -*-

firmware/ap_types/ap_int_base.h

@@ -0,0 +1,1885 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_INT_BASE_H__
+#define __AP_INT_BASE_H__
+
+#ifndef __AP_INT_H__
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+#ifndef __cplusplus
+#error "C++ is required to include this header file"
+#else
+
+#include <ap_common.h>
+#ifndef __SYNTHESIS__
+#if _AP_ENABLE_HALF_ == 1
+#include <hls_half.h>
+#endif
+#include <iostream>
+#include <string.h>
+#endif
+
+/* ----------------------------------------------------------------
+ * ap_int_base: AutoPilot integer/Arbitrary precision integer.
+ * ----------------------------------------------------------------
+ */
+
+/* helper trait. Selecting the smallest C type that can hold the value,
+ * return 64 bit C type if not possible.
+ */
+template <int _AP_N, bool _AP_S>
+struct retval;
+
+// at least 64 bit
+template <int _AP_N>
+struct retval<_AP_N, true> {
+  typedef ap_slong Type;
+};
+
+template <int _AP_N>
+struct retval<_AP_N, false> {
+  typedef ap_ulong Type;
+};
+
+// at least 8 bit
+template <>
+struct retval<1, true> {
+  typedef signed char Type;
+};
+
+template <>
+struct retval<1, false> {
+  typedef unsigned char Type;
+};
+
+// at least 16 bit
+template <>
+struct retval<2, true> {
+  typedef short Type;
+};
+
+template <>
+struct retval<2, false> {
+  typedef unsigned short Type;
+};
+
+// at least 32 bit
+template <>
+struct retval<3, true> {
+  typedef long Type;
+};
+
+template <>
+struct retval<3, false> {
+  typedef unsigned long Type;
+};
+
+template <>
+struct retval<4, true> {
+  typedef long Type;
+};
+
+template <>
+struct retval<4, false> {
+  typedef unsigned long Type;
+};
+
+// trait for letting base class to return derived class.
+// Notice that derived class template is incomplete, and we cannot use
+// the member of the derived class.
+template <int _AP_W2, bool _AP_S2>
+struct _ap_int_factory;
+template <int _AP_W2>
+struct _ap_int_factory<_AP_W2,true> { typedef ap_int<_AP_W2> type; };
+template <int _AP_W2>
+struct _ap_int_factory<_AP_W2,false> { typedef ap_uint<_AP_W2> type; };
+
+template <int _AP_W, bool _AP_S>
+struct ap_int_base : public _AP_ROOT_TYPE<_AP_W, _AP_S> {
+ public:
+  typedef _AP_ROOT_TYPE<_AP_W, _AP_S> Base;
+
+  /* ap_int_base<_AP_W, _AP_S, true>
+   * typedef typename retval<(_AP_W + 7) / 8, _AP_S>::Type RetType;
+   *
+   * ap_int_base<_AP_W, _AP_S, false>
+   * typedef typename retval<8, _AP_S>::Type RetType;
+   */
+  typedef typename retval<AP_MAX((_AP_W + 7) / 8, 8), _AP_S>::Type RetType;
+
+  static const int width = _AP_W;
+
+  template <int _AP_W2, bool _AP_S2>
+  struct RType {
+    enum {
+      mult_w = _AP_W + _AP_W2,
+      mult_s = _AP_S || _AP_S2,
+      plus_w =
+          AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1,
+      plus_s = _AP_S || _AP_S2,
+      minus_w =
+          AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)) + 1,
+      minus_s = true,
+      div_w = _AP_W + _AP_S2,
+      div_s = _AP_S || _AP_S2,
+      mod_w = AP_MIN(_AP_W, _AP_W2 + (!_AP_S2 && _AP_S)),
+      mod_s = _AP_S,
+      logic_w = AP_MAX(_AP_W + (_AP_S2 && !_AP_S), _AP_W2 + (_AP_S && !_AP_S2)),
+      logic_s = _AP_S || _AP_S2
+    };
+
+
+    typedef ap_int_base<mult_w, mult_s> mult_base;
+    typedef ap_int_base<plus_w, plus_s> plus_base;
+    typedef ap_int_base<minus_w, minus_s> minus_base;
+    typedef ap_int_base<logic_w, logic_s> logic_base;
+    typedef ap_int_base<div_w, div_s> div_base;
+    typedef ap_int_base<mod_w, mod_s> mod_base;
+    typedef ap_int_base<_AP_W, _AP_S> arg1_base;
+
+    typedef typename _ap_int_factory<mult_w, mult_s>::type mult;
+    typedef typename _ap_int_factory<plus_w, plus_s>::type plus;
+    typedef typename _ap_int_factory<minus_w, minus_s>::type minus;
+    typedef typename _ap_int_factory<logic_w, logic_s>::type logic;
+    typedef typename _ap_int_factory<div_w, div_s>::type div;
+    typedef typename _ap_int_factory<mod_w, mod_s>::type mod;
+    typedef typename _ap_int_factory<_AP_W, _AP_S>::type arg1;
+    typedef bool reduce;
+  };
+
+  /* Constructors.
+   * ----------------------------------------------------------------
+   */
+  /// default ctor
+  INLINE ap_int_base() {
+    /*
+      #ifdef __SC_COMPATIBLE__
+      Base::V = 0;
+      #endif
+    */
+  }
+
+  /// copy ctor
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base(const ap_int_base<_AP_W2, _AP_S2>& op) {
+    Base::V = op.V;
+  }
+
+  /// volatile copy ctor
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base(const volatile ap_int_base<_AP_W2, _AP_S2>& op) {
+    Base::V = op.V;
+  }
+
+// XXX C++11 feature.
+// The explicit specifier specifies that a constructor or conversion function
+// (since C++11) doesn't allow implicit conversions or copy-initialization.
+//   ap_int_base<W,S> x = 1;
+//   ap_int_base<W,S> foo() { return 1; }
+// but allows
+//   ap_int_base<W,S> x(1);
+//   ap_int_base<W,S> y {1};
+
+/// from all c types.
+#define CTOR_FROM_INT(Type, Size, Signed) \
+  INLINE ap_int_base(const Type op) { Base::V = op; }
+
+  CTOR_FROM_INT(bool, 1, false)
+  CTOR_FROM_INT(char, 8, CHAR_IS_SIGNED)
+  CTOR_FROM_INT(signed char, 8, true)
+  CTOR_FROM_INT(unsigned char, 8, false)
+  CTOR_FROM_INT(short, _AP_SIZE_short, true)
+  CTOR_FROM_INT(unsigned short, _AP_SIZE_short, false)
+  CTOR_FROM_INT(int, _AP_SIZE_int, true)
+  CTOR_FROM_INT(unsigned int, _AP_SIZE_int, false)
+  CTOR_FROM_INT(long, _AP_SIZE_long, true)
+  CTOR_FROM_INT(unsigned long, _AP_SIZE_long, false)
+  CTOR_FROM_INT(ap_slong, _AP_SIZE_ap_slong, true)
+  CTOR_FROM_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+#undef CTOR_FROM_INT
+
+#if _AP_ENABLE_HALF_ == 1
+  /// ctor from half.
+  //  TODO optimize
+  INLINE ap_int_base(half op) {
+    ap_int_base<_AP_W, _AP_S> t((float)op);
+    Base::V = t.V;
+  }
+#endif
+
+  /// ctor from float.
+  INLINE ap_int_base(float op) {
+    const int BITS = FLOAT_MAN + FLOAT_EXP + 1;
+    ap_int_base<BITS, false> reg;
+    reg.V = floatToRawBits(op);
+    bool is_neg = _AP_ROOT_op_get_bit(reg.V, BITS - 1);
+
+    ap_int_base<FLOAT_EXP + 1, true> exp = 0;
+    exp.V = _AP_ROOT_op_get_range(reg.V, FLOAT_MAN, BITS - 2);
+    exp = exp - FLOAT_BIAS;
+
+    ap_int_base<FLOAT_MAN + 2, true> man;
+    man.V = _AP_ROOT_op_get_range(reg.V, 0, FLOAT_MAN - 1);
+    // check for NaN
+    _AP_WARNING(exp == ((unsigned char)(FLOAT_BIAS + 1)) && man.V != 0,
+                "assign NaN to ap integer value");
+    // set leading 1.
+    man.V = _AP_ROOT_op_set_bit(man.V, FLOAT_MAN, 1);
+    //if (is_neg) man = -man;
+
+    if ((reg.V & 0x7ffffffful) == 0) {
+      Base::V = 0;
+    } else {
+      int sh_amt = FLOAT_MAN - exp.V;
+      if (sh_amt == 0) {
+        Base::V = man.V;
+      } else if (sh_amt > 0) {
+        if (sh_amt < FLOAT_MAN + 2) {
+          Base::V = man.V >> sh_amt;
+        } else {
+          if (is_neg)
+            Base::V = -1;
+          else
+            Base::V = 0;
+        }
+      } else {
+        sh_amt = -sh_amt;
+        if (sh_amt < _AP_W) {
+          Base::V = man.V;
+          Base::V <<= sh_amt;
+        } else {
+          Base::V = 0;
+        }
+      }
+    }
+    if (is_neg) *this = -(*this);
+  }
+
+  /// ctor from double.
+  INLINE ap_int_base(double op) {
+    const int BITS = DOUBLE_MAN + DOUBLE_EXP + 1;
+    ap_int_base<BITS, false> reg;
+    reg.V = doubleToRawBits(op);
+    bool is_neg = _AP_ROOT_op_get_bit(reg.V, BITS - 1);
+
+    ap_int_base<DOUBLE_EXP + 1, true> exp = 0;
+    exp.V = _AP_ROOT_op_get_range(reg.V, DOUBLE_MAN, BITS - 2);
+    exp = exp - DOUBLE_BIAS;
+
+    ap_int_base<DOUBLE_MAN + 2, true> man;
+    man.V = _AP_ROOT_op_get_range(reg.V, 0, DOUBLE_MAN - 1);
+    // check for NaN
+    _AP_WARNING(exp == ((unsigned char)(DOUBLE_BIAS + 1)) && man.V != 0,
+                "assign NaN to ap integer value");
+    // set leading 1.
+    man.V = _AP_ROOT_op_set_bit(man.V, DOUBLE_MAN, 1);
+    //if (is_neg) man = -man;
+
+    if ((reg.V & 0x7fffffffffffffffull) == 0) {
+      Base::V = 0;
+    } else {
+      int sh_amt = DOUBLE_MAN - exp.V;
+      if (sh_amt == 0) {
+        Base::V = man.V;
+      } else if (sh_amt > 0) {
+        if (sh_amt < DOUBLE_MAN + 2) {
+          Base::V = man.V >> sh_amt;
+        } else {
+          if (is_neg)
+            Base::V = -1;
+          else
+            Base::V = 0;
+        }
+      } else {
+        sh_amt = -sh_amt;
+        if (sh_amt < _AP_W) {
+          Base::V = man.V;
+          Base::V <<= sh_amt;
+        } else {
+          Base::V = 0;
+        }
+      }
+    }
+    if (is_neg) *this = -(*this);
+  }
+
+  /// from higer rank type.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int_base(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    Base::V = op.to_ap_int_base().V;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base(const ap_range_ref<_AP_W2, _AP_S2>& ref) {
+    Base::V = (ref.get()).V;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base(const ap_bit_ref<_AP_W2, _AP_S2>& ref) {
+    Base::V = ref.operator bool();
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_int_base(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& ref) {
+    const ap_int_base<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>::_AP_WR,
+                      false>
+        tmp = ref.get();
+    Base::V = tmp.V;
+  }
+
+  /* radix has default value in set */
+
+#ifndef __SYNTHESIS__
+  INLINE ap_int_base(const char* s, signed char rd = 0) {
+    if (rd == 0)
+      rd = guess_radix(s);
+    unsigned int length = strlen(s);
+    Base::V.fromString(s, length, rd);
+  }
+#else
+  // XXX __builtin_bit_from_string(...) requires const C string and radix.
+  INLINE ap_int_base(const char* s) {
+    typeof(Base::V) t;
+    _ssdm_string2bits((void*)(&t), (const char*)(s), 10, _AP_W, _AP_S,
+                      AP_TRN, AP_WRAP, 0, _AP_C99);
+    Base::V = t;
+  }
+  INLINE ap_int_base(const char* s, signed char rd) {
+    typeof(Base::V) t;
+    _ssdm_string2bits((void*)(&t), (const char*)(s), rd, _AP_W, _AP_S,
+                      AP_TRN, AP_WRAP, 0, _AP_C99);
+    Base::V = t;
+  }
+#endif
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int_base(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    Base::V = (val.get()).V;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int_base(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    Base::V = val.operator bool();
+  }
+
+  INLINE ap_int_base read() volatile {
+    /*AP_DEBUG(printf("call read %d\n", Base::V););*/
+    ap_int_base ret;
+    ret.V = Base::V;
+    return ret;
+  }
+
+  INLINE void write(const ap_int_base<_AP_W, _AP_S>& op2) volatile {
+    /*AP_DEBUG(printf("call write %d\n", op2.V););*/
+    Base::V = op2.V;
+  }
+
+  /* Another form of "write".*/
+  template <int _AP_W2, bool _AP_S2>
+  INLINE void operator=(
+      const volatile ap_int_base<_AP_W2, _AP_S2>& op2) volatile {
+    Base::V = op2.V;
+  }
+
+  INLINE void operator=(
+      const volatile ap_int_base<_AP_W, _AP_S>& op2) volatile {
+    Base::V = op2.V;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE void operator=(const ap_int_base<_AP_W2, _AP_S2>& op2) volatile {
+    Base::V = op2.V;
+  }
+
+  INLINE void operator=(const ap_int_base<_AP_W, _AP_S>& op2) volatile {
+    Base::V = op2.V;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base& operator=(
+      const volatile ap_int_base<_AP_W2, _AP_S2>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base& operator=(const ap_int_base<_AP_W2, _AP_S2>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  INLINE ap_int_base& operator=(const volatile ap_int_base<_AP_W, _AP_S>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+  INLINE ap_int_base& operator=(const ap_int_base<_AP_W, _AP_S>& op2) {
+    Base::V = op2.V;
+    return *this;
+  }
+
+
+#define ASSIGN_OP_FROM_INT(Type, Size, Signed) \
+  INLINE ap_int_base& operator=(Type op) {     \
+    Base::V = op;                              \
+    return *this;                              \
+  }
+
+  ASSIGN_OP_FROM_INT(bool, 1, false)
+  ASSIGN_OP_FROM_INT(char, 8, CHAR_IS_SIGNED)
+  ASSIGN_OP_FROM_INT(signed char, 8, true)
+  ASSIGN_OP_FROM_INT(unsigned char, 8, false)
+  ASSIGN_OP_FROM_INT(short, _AP_SIZE_short, true)
+  ASSIGN_OP_FROM_INT(unsigned short, _AP_SIZE_short, false)
+  ASSIGN_OP_FROM_INT(int, _AP_SIZE_int, true)
+  ASSIGN_OP_FROM_INT(unsigned int, _AP_SIZE_int, false)
+  ASSIGN_OP_FROM_INT(long, _AP_SIZE_long, true)
+  ASSIGN_OP_FROM_INT(unsigned long, _AP_SIZE_long, false)
+  ASSIGN_OP_FROM_INT(ap_slong, _AP_SIZE_ap_slong, true)
+  ASSIGN_OP_FROM_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef ASSIGN_OP_FROM_INT
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& op2) {
+    Base::V = (bool)op2;
+    return *this;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base& operator=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    Base::V = (ap_int_base<_AP_W2, false>(op2)).V;
+    return *this;
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_int_base& operator=(
+      const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& op2) {
+    Base::V = op2.get().V;
+    return *this;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int_base& operator=(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    Base::V = op.to_ap_int_base().V;
+    return *this;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int_base& operator=(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    Base::V = (bool)op;
+    return *this;
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_int_base& operator=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& op) {
+    Base::V = ((const ap_int_base<_AP_W2, false>)(op)).V;
+    return *this;
+  }
+
+  // FIXME: UG902 has clearly required user to use to_int() to convert to built-in
+  // types, but this implicit conversion is relied on in hls_cordic.h and hls_rsr.h.
+  // For example:
+  //     int d_exp = fps_x.exp - fps_y.exp;
+  INLINE operator RetType() const { return (RetType)(Base::V); }
+
+  /* Explicit conversions to C types.
+   * ----------------------------------------------------------------
+   */
+  INLINE bool to_bool() const { return (bool)(Base::V); }
+  INLINE char to_char() const { return (char)(Base::V); }
+  INLINE signed char to_schar() const { return (signed char)(Base::V); }
+  INLINE unsigned char to_uchar() const { return (unsigned char)(Base::V); }
+  INLINE short to_short() const { return (short)(Base::V); }
+  INLINE unsigned short to_ushort() const { return (unsigned short)(Base::V); }
+  INLINE int to_int() const { return (int)(Base::V); }
+  INLINE unsigned to_uint() const { return (unsigned)(Base::V); }
+  INLINE long to_long() const { return (long)(Base::V); }
+  INLINE unsigned long to_ulong() const { return (unsigned long)(Base::V); }
+  INLINE ap_slong to_int64() const { return (ap_slong)(Base::V); }
+  INLINE ap_ulong to_uint64() const { return (ap_ulong)(Base::V); }
+  INLINE float to_float() const { return (float)(Base::V); }
+  INLINE double to_double() const { return (double)(Base::V); }
+
+  // TODO decide if user-defined conversion should be provided.
+#if 0
+  INLINE operator char() const { return (char)(Base::V); }
+  INLINE operator signed char() const { return (signed char)(Base::V); }
+  INLINE operator unsigned char() const { return (unsigned char)(Base::V); }
+  INLINE operator short() const { return (short)(Base::V); }
+  INLINE operator unsigned short() const { return (unsigned short)(Base::V); }
+  INLINE operator int() const { return (int)(Base::V); }
+  INLINE operator unsigned int () const { return (unsigned)(Base::V); }
+  INLINE operator long () const { return (long)(Base::V); }
+  INLINE operator unsigned long () const { return (unsigned long)(Base::V); }
+  INLINE operator ap_slong () { return (ap_slong)(Base::V); }
+  INLINE operator ap_ulong () { return (ap_ulong)(Base::V); }
+#endif
+
+  /* Helper methods.
+     ----------------------------------------------------------------
+  */
+  /* we cannot call a non-volatile function on a volatile instance.
+   * but calling a volatile function is ok.
+   * XXX deleted non-volatile version.
+   */
+  INLINE int length() const volatile { return _AP_W; }
+
+  /*Return true if the value of ap_int_base instance is zero*/
+  INLINE bool iszero() const { return Base::V == 0; }
+
+  /*Return true if the value of ap_int_base instance is zero*/
+  INLINE bool is_zero() const { return Base::V == 0; }
+
+  /* x < 0 */
+  INLINE bool sign() const {
+    if (_AP_S &&
+        _AP_ROOT_op_get_bit(Base::V, _AP_W - 1))
+      return true;
+    else
+      return false;
+  }
+
+  /* x[i] = 0 */
+  INLINE void clear(int i) {
+    AP_ASSERT(i >= 0 && i < _AP_W, "position out of range");
+    Base::V = _AP_ROOT_op_set_bit(Base::V, i, 0);
+  }
+
+  /* x[i] = !x[i]*/
+  INLINE void invert(int i) {
+    AP_ASSERT(i >= 0 && i < _AP_W, "position out of range");
+    bool val = _AP_ROOT_op_get_bit(Base::V, i);
+    if (val)
+      Base::V = _AP_ROOT_op_set_bit(Base::V, i, 0);
+    else
+      Base::V = _AP_ROOT_op_set_bit(Base::V, i, 1);
+  }
+
+  INLINE bool test(int i) const {
+    AP_ASSERT(i >= 0 && i < _AP_W, "position out of range");
+    return _AP_ROOT_op_get_bit(Base::V, i);
+  }
+
+  // Get self. For ap_concat_ref expansion.
+  INLINE ap_int_base& get() { return *this; }
+
+  // Set the ith bit into 1
+  INLINE void set(int i) {
+    AP_ASSERT(i >= 0 && i < _AP_W, "position out of range");
+    Base::V = _AP_ROOT_op_set_bit(Base::V, i, 1);
+  }
+
+  // Set the ith bit into v
+  INLINE void set(int i, bool v) {
+    AP_ASSERT(i >= 0 && i < _AP_W, "position out of range");
+    Base::V = _AP_ROOT_op_set_bit(Base::V, i, v);
+  }
+
+  // This is used for sc_lv and sc_bv, which is implemented by sc_uint
+  // Rotate an ap_int_base object n places to the left
+  INLINE ap_int_base& lrotate(int n) {
+    AP_ASSERT(n >= 0 && n < _AP_W, "shift value out of range");
+    // TODO unify this.
+#ifdef __SYNTHESIS__
+    typeof(Base::V) l_p = Base::V << n;
+    typeof(Base::V) r_p = Base::V >> (_AP_W - n);
+    Base::V = l_p | r_p;
+#else
+    Base::V.lrotate(n);
+#endif
+    return *this;
+  }
+
+  // This is used for sc_lv and sc_bv, which is implemented by sc_uint
+  // Rotate an ap_int_base object n places to the right
+  INLINE ap_int_base& rrotate(int n) {
+    AP_ASSERT(n >= 0 && n < _AP_W, "shift value out of range");
+    // TODO unify this.
+#ifdef __SYNTHESIS__
+    typeof(Base::V) l_p = Base::V << (_AP_W - n);
+    typeof(Base::V) r_p = Base::V >> n;
+    Base::V = l_p | r_p;
+#else
+    Base::V.rrotate(n);
+#endif
+    return *this;
+  }
+
+  // Reverse the contents of ap_int_base instance.
+  // I.e. LSB becomes MSB and vise versa.
+  INLINE ap_int_base& reverse() {
+    Base::V = _AP_ROOT_op_get_range(Base::V, _AP_W - 1, 0);
+    return *this;
+  }
+
+  // Set the ith bit into v
+  INLINE void set_bit(int i, bool v) {
+    Base::V = _AP_ROOT_op_set_bit(Base::V, i, v);
+  }
+
+  // Get the value of ith bit
+  INLINE bool get_bit(int i) const {
+    return (bool)_AP_ROOT_op_get_bit(Base::V, i);
+  }
+
+  // complements every bit
+  INLINE void b_not() { Base::V = ~Base::V; }
+
+#define OP_ASSIGN_AP(Sym)                                                    \
+  template <int _AP_W2, bool _AP_S2>                                         \
+  INLINE ap_int_base& operator Sym(const ap_int_base<_AP_W2, _AP_S2>& op2) { \
+    Base::V Sym op2.V;                                                       \
+    return *this;                                                            \
+  }
+
+  /* Arithmetic assign.
+   * ----------------------------------------------------------------
+   */
+  OP_ASSIGN_AP(*=)
+  OP_ASSIGN_AP(+=)
+  OP_ASSIGN_AP(-=)
+  OP_ASSIGN_AP(/=)
+  OP_ASSIGN_AP(%=)
+#undef OP_ASSIGN_AP
+
+  /* Bitwise assign: and, or, xor.
+   * ----------------------------------------------------------------
+   */
+#define OP_ASSIGN_AP_CHK(Sym)                                                \
+  template <int _AP_W2, bool _AP_S2>                                         \
+  INLINE ap_int_base& operator Sym(const ap_int_base<_AP_W2, _AP_S2>& op2) { \
+    _AP_WARNING((_AP_W != _AP_W2),                                           \
+                "Bitsize mismatch for ap_[u]int" #Sym "ap_[u]int.");         \
+    Base::V Sym op2.V;                                                       \
+    return *this;                                                            \
+  }
+  OP_ASSIGN_AP_CHK(&=)
+  OP_ASSIGN_AP_CHK(|=)
+  OP_ASSIGN_AP_CHK(^=)
+#undef OP_ASSIGN_AP_CHK
+
+  /* Prefix increment, decrement.
+   * ----------------------------------------------------------------
+   */
+  INLINE ap_int_base& operator++() {
+    operator+=((ap_int_base<1, false>)1);
+    return *this;
+  }
+  INLINE ap_int_base& operator--() {
+    operator-=((ap_int_base<1, false>)1);
+    return *this;
+  }
+
+  /* Postfix increment, decrement
+   * ----------------------------------------------------------------
+   */
+  INLINE const typename RType<_AP_W,_AP_S>::arg1 operator++(int) {
+    ap_int_base t = *this;
+    operator+=((ap_int_base<1, false>)1);
+    return t;
+  }
+  INLINE const typename RType<_AP_W,_AP_S>::arg1 operator--(int) {
+    ap_int_base t = *this;
+    operator-=((ap_int_base<1, false>)1);
+    return t;
+  }
+
+  /* Unary arithmetic.
+   * ----------------------------------------------------------------
+   */
+  INLINE typename RType<_AP_W,_AP_S>::arg1 operator+() const { return *this; }
+
+  // TODO used to be W>64 only... need check.
+  INLINE typename RType<1, false>::minus operator-() const {
+    return ap_int_base<1, false>(0) - *this;
+  }
+
+  /* Not (!)
+   * ----------------------------------------------------------------
+   */
+  INLINE bool operator!() const { return Base::V == 0; }
+
+  /* Bitwise (arithmetic) unary: complement
+     ----------------------------------------------------------------
+  */
+  // XXX different from Mentor's ac_int!
+  INLINE typename RType<_AP_W,_AP_S>::arg1 operator~() const {
+    ap_int_base<_AP_W, _AP_S> r;
+    r.V = ~Base::V;
+    return r;
+  }
+
+  /* Shift (result constrained by left operand).
+   * ----------------------------------------------------------------
+   */
+  template <int _AP_W2>
+  INLINE typename RType<_AP_W,_AP_S>::arg1 operator<<(const ap_int_base<_AP_W2, true>& op2) const {
+    bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1);
+    ap_int_base<_AP_W2, false> sh = op2;
+    if (isNeg) {
+      sh = -op2;
+      return operator>>(sh);
+    } else
+      return operator<<(sh);
+  }
+
+  template <int _AP_W2>
+  INLINE typename RType<_AP_W,_AP_S>::arg1 operator<<(const ap_int_base<_AP_W2, false>& op2) const {
+    ap_int_base r;
+    r.V = Base::V << op2.to_uint();
+    return r;
+  }
+
+  template <int _AP_W2>
+  INLINE typename RType<_AP_W,_AP_S>::arg1 operator>>(const ap_int_base<_AP_W2, true>& op2) const {
+    bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1);
+    ap_int_base<_AP_W2, false> sh = op2;
+    if (isNeg) {
+      sh = -op2;
+      return operator<<(sh);
+    }
+    return operator>>(sh);
+  }
+
+  template <int _AP_W2>
+  INLINE typename RType<_AP_W,_AP_S>::arg1 operator>>(const ap_int_base<_AP_W2, false>& op2) const {
+    ap_int_base r;
+    r.V = Base::V >> op2.to_uint();
+    return r;
+  }
+
+  // FIXME we standalone operator>> for ap_int_base and ap_range_ref.
+#if 0
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base operator<<(const ap_range_ref<_AP_W2, _AP_S2>& op2) const {
+    return *this << (op2.operator ap_int_base<_AP_W2, false>());
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base operator>>(const ap_range_ref<_AP_W2, _AP_S2>& op2) const {
+    return *this >> (op2.operator ap_int_base<_AP_W2, false>());
+  }
+#endif
+
+  /* Shift assign
+   * ----------------------------------------------------------------
+   */
+  template <int _AP_W2>
+  INLINE ap_int_base& operator<<=(const ap_int_base<_AP_W2, true>& op2) {
+    bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1);
+    ap_int_base<_AP_W2, false> sh = op2;
+    if (isNeg) {
+      sh = -op2;
+      return operator>>=(sh);
+    } else
+      return operator<<=(sh);
+  }
+
+  template <int _AP_W2>
+  INLINE ap_int_base& operator<<=(const ap_int_base<_AP_W2, false>& op2) {
+    Base::V <<= op2.to_uint();
+    return *this;
+  }
+
+  template <int _AP_W2>
+  INLINE ap_int_base& operator>>=(const ap_int_base<_AP_W2, true>& op2) {
+    bool isNeg = _AP_ROOT_op_get_bit(op2.V, _AP_W2 - 1);
+    ap_int_base<_AP_W2, false> sh = op2;
+    if (isNeg) {
+      sh = -op2;
+      return operator<<=(sh);
+    }
+    return operator>>=(sh);
+  }
+
+  template <int _AP_W2>
+  INLINE ap_int_base& operator>>=(const ap_int_base<_AP_W2, false>& op2) {
+    Base::V >>= op2.to_uint();
+    return *this;
+  }
+
+  // FIXME we standalone operator>> for ap_int_base and ap_range_ref.
+#if 0
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base& operator<<=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return *this <<= (op2.operator ap_int_base<_AP_W2, false>());
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_int_base& operator>>=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return *this >>= (op2.operator ap_int_base<_AP_W2, false>());
+  }
+#endif
+
+  /* Equality and Relational.
+   * ----------------------------------------------------------------
+   */
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator==(const ap_int_base<_AP_W2, _AP_S2>& op2) const {
+    return Base::V == op2.V;
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator!=(const ap_int_base<_AP_W2, _AP_S2>& op2) const {
+    return !(Base::V == op2.V);
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator<(const ap_int_base<_AP_W2, _AP_S2>& op2) const {
+    return Base::V < op2.V;
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator>=(const ap_int_base<_AP_W2, _AP_S2>& op2) const {
+    return Base::V >= op2.V;
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator>(const ap_int_base<_AP_W2, _AP_S2>& op2) const {
+    return Base::V > op2.V;
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator<=(const ap_int_base<_AP_W2, _AP_S2>& op2) const {
+    return Base::V <= op2.V;
+  }
+
+  /* Bit and Part Select
+   * ----------------------------------------------------------------
+   */
+  INLINE ap_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) {
+    _AP_ERROR(Hi >= _AP_W, "Hi(%d)out of bound(%d) in range()", Hi, _AP_W);
+    _AP_ERROR(Lo >= _AP_W, "Lo(%d)out of bound(%d) in range()", Lo, _AP_W);
+    return ap_range_ref<_AP_W, _AP_S>(this, Hi, Lo);
+  }
+
+  // This is a must to strip constness to produce reference type.
+  INLINE ap_range_ref<_AP_W, _AP_S> range(int Hi, int Lo) const {
+    _AP_ERROR(Hi >= _AP_W, "Hi(%d)out of bound(%d) in range()", Hi, _AP_W);
+    _AP_ERROR(Lo >= _AP_W, "Lo(%d)out of bound(%d) in range()", Lo, _AP_W);
+    return ap_range_ref<_AP_W, _AP_S>(const_cast<ap_int_base*>(this), Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE ap_range_ref<_AP_W, _AP_S> range(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE ap_range_ref<_AP_W, _AP_S> range(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  INLINE ap_range_ref<_AP_W, _AP_S> range() {
+    return this->range(_AP_W - 1, 0);
+  }
+
+  INLINE ap_range_ref<_AP_W, _AP_S> range() const {
+    return this->range(_AP_W - 1, 0);
+  }
+
+  INLINE ap_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) {
+    return this->range(Hi, Lo);
+  }
+
+  INLINE ap_range_ref<_AP_W, _AP_S> operator()(int Hi, int Lo) const {
+    return this->range(Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE ap_range_ref<_AP_W, _AP_S> operator()(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+  template <int _AP_W2, bool _AP_S2, int _AP_W3, bool _AP_S3>
+  INLINE ap_range_ref<_AP_W, _AP_S> operator()(
+      const ap_int_base<_AP_W2, _AP_S2>& HiIdx,
+      const ap_int_base<_AP_W3, _AP_S3>& LoIdx) const {
+    int Hi = HiIdx.to_int();
+    int Lo = LoIdx.to_int();
+    return this->range(Hi, Lo);
+  }
+
+#if 0
+  template<int Hi, int Lo>
+  INLINE ap_int_base<Hi-Lo+1, false> slice() const {
+    AP_ASSERT(Hi >= Lo && Hi < _AP_W && Lo < _AP_W, "Out of bounds in slice()");
+    ap_int_base<Hi-Lo+1, false> tmp ;
+    tmp.V = _AP_ROOT_op_get_range(Base::V, Lo, Hi);
+    return tmp;
+  }
+
+  INLINE ap_bit_ref<_AP_W,_AP_S> operator [] ( unsigned int uindex) {
+    AP_ASSERT(uindex < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W,_AP_S> bvh( this, uindex );
+    return bvh;
+  }
+#endif
+
+  INLINE ap_bit_ref<_AP_W, _AP_S> operator[](int index) {
+    AP_ASSERT(index >= 0, "Attempting to read bit with negative index");
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> bvh(this, index);
+    return bvh;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_bit_ref<_AP_W, _AP_S> operator[](
+      const ap_int_base<_AP_W2, _AP_S2>& index) {
+    AP_ASSERT(index >= 0, "Attempting to read bit with negative index");
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> bvh(this, index.to_int());
+    return bvh;
+  }
+
+  INLINE bool operator[](int index) const {
+    AP_ASSERT(index >= 0, "Attempting to read bit with negative index");
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> br(this, index);
+    return br.to_bool();
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator[](const ap_int_base<_AP_W2, _AP_S2>& index) const {
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> br(this, index.to_int());
+    return br.to_bool();
+  }
+
+  INLINE ap_bit_ref<_AP_W, _AP_S> bit(int index) {
+    AP_ASSERT(index >= 0, "Attempting to read bit with negative index");
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> bvh(this, index);
+    return bvh;
+  }
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_bit_ref<_AP_W, _AP_S> bit(
+      const ap_int_base<_AP_W2, _AP_S2>& index) {
+    AP_ASSERT(index >= 0, "Attempting to read bit with negative index");
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> bvh(this, index.to_int());
+    return bvh;
+  }
+
+  INLINE bool bit(int index) const {
+    AP_ASSERT(index >= 0, "Attempting to read bit with negative index");
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W, _AP_S> br(this, index);
+    return br.to_bool();
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool bit(const ap_int_base<_AP_W2, _AP_S2>& index) const {
+    return bit(index.to_int());
+  }
+
+#if 0
+  template<typename _AP_T>
+  INLINE bool operator[](_AP_T index) const {
+    AP_ASSERT(index < _AP_W, "Attempting to read bit beyond MSB");
+    ap_bit_ref<_AP_W,_AP_S> br = operator[](index);
+    return br.to_bool();
+  }
+#endif
+
+  // Count the number of zeros from the most significant bit
+  // to the first one bit.
+  INLINE int countLeadingZeros() {
+#ifdef __SYNTHESIS__
+    if (_AP_W <= 32) {
+      ap_int_base<32, false> t(-1UL), x;
+      x.V = _AP_ROOT_op_get_range(this->V, _AP_W - 1, 0); // reverse
+      t.V = _AP_ROOT_op_set_range(t.V, 0, _AP_W - 1, x.V);
+      return __builtin_ctz(t.V); // count trailing zeros.
+    } else if (_AP_W <= 64) {
+      ap_int_base<64, false> t(-1ULL);
+      ap_int_base<64, false> x;
+      x.V = _AP_ROOT_op_get_range(this->V, _AP_W - 1, 0); // reverse
+      t.V = _AP_ROOT_op_set_range(t.V, 0, _AP_W - 1, x.V);
+      return __builtin_ctzll(t.V); // count trailing zeros.
+    } else {
+      enum { __N = (_AP_W + 63) / 64 };
+      int NZeros = 0;
+      int i = 0;
+      bool hitNonZero = false;
+      for (i = 0; i < __N - 1; ++i) {
+        ap_int_base<64, false> t;
+        t.V = _AP_ROOT_op_get_range(this->V, _AP_W - i * 64 - 64, _AP_W - i * 64 - 1);
+        NZeros += hitNonZero ? 0 : __builtin_clzll(t.V); // count leading zeros.
+        hitNonZero |= (t.V != 0);
+      }
+      if (!hitNonZero) {
+        ap_int_base<64, false> t(-1ULL);
+        enum { REST = (_AP_W - 1) % 64 };
+        ap_int_base<64, false> x;
+        x.V = _AP_ROOT_op_get_range(this->V, 0, REST);
+        t.V = _AP_ROOT_op_set_range(t.V, 63 - REST, 63, x.V);
+        NZeros += __builtin_clzll(t.V);
+      }
+      return NZeros;
+    }
+#else
+    return (Base::V).countLeadingZeros();
+#endif
+  } // countLeadingZeros
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  concat(const ap_int_base<_AP_W2, _AP_S2>& a2) const {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  concat(ap_int_base<_AP_W2, _AP_S2>& a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(*this, a2);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+      operator,(const ap_range_ref<_AP_W2, _AP_S2> &a2) const {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_range_ref<_AP_W2, _AP_S2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<ap_range_ref<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+      operator,(ap_range_ref<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_range_ref<_AP_W2, _AP_S2> >(*this, a2);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(ap_int_base<_AP_W2, _AP_S2> &a2) const {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this), a2);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) const {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(*this, a2);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+  operator,(const ap_bit_ref<_AP_W2, _AP_S2> &a2) const {
+    return ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<ap_bit_ref<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+  operator,(ap_bit_ref<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, 1, ap_bit_ref<_AP_W2, _AP_S2> >(
+        *this, a2);
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+  operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3,
+                         ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>&>(a2));
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+  operator,(ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) {
+    return ap_concat_ref<_AP_W, ap_int_base, _AP_W2 + _AP_W3,
+                         ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(*this,
+                                                                         a2);
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<
+      _AP_W, ap_int_base, _AP_W2,
+      af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>
+                &a2) const {
+    return ap_concat_ref<
+        _AP_W, ap_int_base, _AP_W2,
+        af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<
+            af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<
+      _AP_W, ap_int_base, _AP_W2,
+      af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) {
+    return ap_concat_ref<
+        _AP_W, ap_int_base, _AP_W2,
+        af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this,
+                                                                       a2);
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_int_base, 1,
+                    af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+      operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>
+                    &a2) const {
+    return ap_concat_ref<
+        _AP_W, ap_int_base, 1,
+        af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        const_cast<ap_int_base<_AP_W, _AP_S>&>(*this),
+        const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(
+            a2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_int_base, 1,
+                    af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+      operator,(
+          af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) {
+    return ap_concat_ref<
+        _AP_W, ap_int_base, 1,
+        af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(*this, a2);
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_int_base<AP_MAX(_AP_W2 + _AP_W3, _AP_W), _AP_S> operator&(
+      const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) {
+    return *this & a2.get();
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_int_base<AP_MAX(_AP_W2 + _AP_W3, _AP_W), _AP_S> operator|(
+      const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) {
+    return *this | a2.get();
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_int_base<AP_MAX(_AP_W2 + _AP_W3, _AP_W), _AP_S> operator^(
+      const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>& a2) {
+    return *this ^ a2.get();
+  }
+
+  template <int _AP_W3>
+  INLINE void set(const ap_int_base<_AP_W3, false>& val) {
+    Base::V = val.V;
+  }
+
+  /* Reduce operations.
+   * ----------------------------------------------------------------
+   */
+  // XXX non-const version deleted.
+  INLINE bool and_reduce() const { return _AP_ROOT_op_reduce(and, Base::V); }
+  INLINE bool nand_reduce() const { return _AP_ROOT_op_reduce(nand, Base::V); }
+  INLINE bool or_reduce() const { return _AP_ROOT_op_reduce(or, Base::V); }
+  INLINE bool nor_reduce() const { return !(_AP_ROOT_op_reduce(or, Base::V)); }
+  INLINE bool xor_reduce() const { return _AP_ROOT_op_reduce (xor, Base::V); }
+  INLINE bool xnor_reduce() const {
+    return !(_AP_ROOT_op_reduce (xor, Base::V));
+  }
+
+  /* Output as a string.
+   * ----------------------------------------------------------------
+   */
+#ifndef __SYNTHESIS__
+  std::string to_string(signed char rd = 2, bool sign = _AP_S) const {
+    // XXX in autosim/autowrap.tcl "(${name}).to_string(2).c_str()" is used to
+    // initialize sc_lv, which seems incapable of handling format "-0b".
+    if (rd == 2) sign = false;
+    return (Base::V).to_string(rd, sign);
+  }
+#else
+  INLINE char* to_string(signed char rd = 2, bool sign = _AP_S) const {
+    return 0;
+  }
+#endif
+}; // struct ap_int_base
+
+// XXX apcc cannot handle global std::ios_base::Init() brought in by <iostream>
+#ifndef AP_AUTOCC
+#ifndef __SYNTHESIS__
+template <int _AP_W, bool _AP_S>
+INLINE std::ostream& operator<<(std::ostream& os,
+                                const ap_int_base<_AP_W, _AP_S>& x) {
+  std::ios_base::fmtflags ff = std::cout.flags();
+  if (ff & std::cout.hex) {
+    os << x.to_string(16); // don't print sign
+  } else if (ff & std::cout.oct) {
+    os << x.to_string(8); // don't print sign
+  } else {
+    os << x.to_string(10);
+  }
+  return os;
+}
+#endif // ifndef __SYNTHESIS__
+
+#ifndef __SYNTHESIS__
+template <int _AP_W, bool _AP_S>
+INLINE std::istream& operator>>(std::istream& in,
+                                ap_int_base<_AP_W, _AP_S>& op) {
+  std::string str;
+  in >> str;
+  const std::ios_base::fmtflags basefield = in.flags() & std::ios_base::basefield;
+  unsigned radix = (basefield == std::ios_base::dec) ? 0 : (
+                     (basefield == std::ios_base::oct) ? 8 : (
+                       (basefield == std::ios_base::hex) ? 16 : 0));
+  op = ap_int_base<_AP_W, _AP_S>(str.c_str(), radix);
+  return in;
+}
+#endif // ifndef __SYNTHESIS__
+#endif // ifndef AP_AUTOCC
+
+/* Operators with another ap_int_base.
+ * ----------------------------------------------------------------
+ */
+#define OP_BIN_AP(Sym, Rty)                                                   \
+  template <int _AP_W, bool _AP_S, int _AP_W2, bool _AP_S2>                   \
+  INLINE                                                                      \
+      typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2, _AP_S2>::Rty \
+      operator Sym(const ap_int_base<_AP_W, _AP_S>& op,                       \
+                   const ap_int_base<_AP_W2, _AP_S2>& op2) {                  \
+    typename ap_int_base<_AP_W, _AP_S>::template RType<                       \
+        _AP_W2, _AP_S2>::Rty##_base lhs(op);                                  \
+    typename ap_int_base<_AP_W, _AP_S>::template RType<                       \
+        _AP_W2, _AP_S2>::Rty##_base rhs(op2);                                 \
+    typename ap_int_base<_AP_W, _AP_S>::template RType<                       \
+        _AP_W2, _AP_S2>::Rty##_base ret;                                      \
+    ret.V = lhs.V Sym rhs.V;                                                  \
+    return ret;                                                               \
+  }
+
+OP_BIN_AP(*, mult)
+OP_BIN_AP(+, plus)
+OP_BIN_AP(-, minus)
+OP_BIN_AP(&, logic)
+OP_BIN_AP(|, logic)
+OP_BIN_AP(^, logic)
+
+#define OP_BIN_AP2(Sym, Rty)                                                  \
+  template <int _AP_W, bool _AP_S, int _AP_W2, bool _AP_S2>                   \
+  INLINE                                                                      \
+      typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2, _AP_S2>::Rty \
+      operator Sym(const ap_int_base<_AP_W, _AP_S>& op,                       \
+                   const ap_int_base<_AP_W2, _AP_S2>& op2) {                  \
+    typename ap_int_base<_AP_W, _AP_S>::template RType<                       \
+        _AP_W2, _AP_S2>::Rty##_base ret;                                      \
+    ret.V = op.V Sym op2.V;                                                   \
+    return ret;                                                               \
+  }
+
+OP_BIN_AP2(/, div)
+OP_BIN_AP2(%, mod)
+
+// shift operators are defined inside class.
+// compound assignment operators are defined inside class.
+
+/* Operators with a pointer type.
+ * ----------------------------------------------------------------
+ *   char a[100];
+ *   char* ptr = a;
+ *   ap_int<2> n = 3;
+ *   char* ptr2 = ptr + n*2;
+ * avoid ambiguous errors.
+ */
+#define OP_BIN_WITH_PTR(BIN_OP)                                           \
+  template <typename PTR_TYPE, int _AP_W, bool _AP_S>                     \
+  INLINE PTR_TYPE* operator BIN_OP(PTR_TYPE* i_op,                        \
+                                   const ap_int_base<_AP_W, _AP_S>& op) { \
+    ap_slong op2 = op.to_int64(); /* Not all implementation */            \
+    return i_op BIN_OP op2;                                               \
+  }                                                                       \
+  template <typename PTR_TYPE, int _AP_W, bool _AP_S>                     \
+  INLINE PTR_TYPE* operator BIN_OP(const ap_int_base<_AP_W, _AP_S>& op,   \
+                                   PTR_TYPE* i_op) {                      \
+    ap_slong op2 = op.to_int64(); /* Not all implementation */            \
+    return op2 BIN_OP i_op;                                               \
+  }
+
+OP_BIN_WITH_PTR(+)
+OP_BIN_WITH_PTR(-)
+
+/* Operators with a native floating point types.
+ * ----------------------------------------------------------------
+ */
+// float OP ap_int
+// when ap_int<wa>'s width > 64, then trunc ap_int<w> to ap_int<64>
+#define OP_BIN_WITH_FLOAT(BIN_OP, C_TYPE)                              \
+  template <int _AP_W, bool _AP_S>                                     \
+  INLINE C_TYPE operator BIN_OP(C_TYPE i_op,                           \
+                                const ap_int_base<_AP_W, _AP_S>& op) { \
+    typename ap_int_base<_AP_W, _AP_S>::RetType op2 = op;              \
+    return i_op BIN_OP op2;                                            \
+  }                                                                    \
+  template <int _AP_W, bool _AP_S>                                     \
+  INLINE C_TYPE operator BIN_OP(const ap_int_base<_AP_W, _AP_S>& op,   \
+                                C_TYPE i_op) {                         \
+    typename ap_int_base<_AP_W, _AP_S>::RetType op2 = op;              \
+    return op2 BIN_OP i_op;                                            \
+  }
+
+#define ALL_OP_WITH_FLOAT(C_TYPE) \
+  OP_BIN_WITH_FLOAT(*, C_TYPE) \
+  OP_BIN_WITH_FLOAT(/, C_TYPE) \
+  OP_BIN_WITH_FLOAT(+, C_TYPE) \
+  OP_BIN_WITH_FLOAT(-, C_TYPE)
+
+#if _AP_ENABLE_HALF_ == 1
+ALL_OP_WITH_FLOAT(half)
+#endif
+ALL_OP_WITH_FLOAT(float)
+ALL_OP_WITH_FLOAT(double)
+
+// TODO no shift?
+
+/* Operators with a native integral types.
+ * ----------------------------------------------------------------
+ */
+// arithmetic and bitwise operators.
+#define OP_BIN_WITH_INT(BIN_OP, C_TYPE, _AP_W2, _AP_S2, RTYPE)             \
+  template <int _AP_W, bool _AP_S>                                         \
+  INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2,        \
+                                                            _AP_S2>::RTYPE \
+  operator BIN_OP(C_TYPE i_op, const ap_int_base<_AP_W, _AP_S>& op) {      \
+    return ap_int_base<_AP_W2, _AP_S2>(i_op) BIN_OP(op);                   \
+  }                                                                        \
+  template <int _AP_W, bool _AP_S>                                         \
+  INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W2,        \
+                                                            _AP_S2>::RTYPE \
+  operator BIN_OP(const ap_int_base<_AP_W, _AP_S>& op, C_TYPE i_op) {      \
+    return op BIN_OP ap_int_base<_AP_W2, _AP_S2>(i_op);                    \
+  }
+
+#define ALL_OP_BIN_WITH_INT(C_TYPE, _AP_W2, _AP_S2)    \
+  OP_BIN_WITH_INT(*, C_TYPE, _AP_W2, _AP_S2, mult)  \
+  OP_BIN_WITH_INT(+, C_TYPE, _AP_W2, _AP_S2, plus)  \
+  OP_BIN_WITH_INT(-, C_TYPE, _AP_W2, _AP_S2, minus) \
+  OP_BIN_WITH_INT(/, C_TYPE, _AP_W2, _AP_S2, div)   \
+  OP_BIN_WITH_INT(%, C_TYPE, _AP_W2, _AP_S2, mod)   \
+  OP_BIN_WITH_INT(&, C_TYPE, _AP_W2, _AP_S2, logic) \
+  OP_BIN_WITH_INT(|, C_TYPE, _AP_W2, _AP_S2, logic) \
+  OP_BIN_WITH_INT(^, C_TYPE, _AP_W2, _AP_S2, logic)
+
+ALL_OP_BIN_WITH_INT(bool, 1, false)
+ALL_OP_BIN_WITH_INT(char, 8, CHAR_IS_SIGNED)
+ALL_OP_BIN_WITH_INT(signed char, 8, true)
+ALL_OP_BIN_WITH_INT(unsigned char, 8, false)
+ALL_OP_BIN_WITH_INT(short, _AP_SIZE_short, true)
+ALL_OP_BIN_WITH_INT(unsigned short, _AP_SIZE_short, false)
+ALL_OP_BIN_WITH_INT(int, _AP_SIZE_int, true)
+ALL_OP_BIN_WITH_INT(unsigned int, _AP_SIZE_int, false)
+ALL_OP_BIN_WITH_INT(long, _AP_SIZE_long, true)
+ALL_OP_BIN_WITH_INT(unsigned long, _AP_SIZE_long, false)
+ALL_OP_BIN_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+ALL_OP_BIN_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef OP_BIN_WITH_INT
+#undef ALL_OP_BIN_WITH_INT
+
+// shift operators.
+#define ALL_OP_SHIFT_WITH_INT(C_TYPE, _AP_W2, _AP_S2)    \
+  template <int _AP_W, bool _AP_S>                       \
+  INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator<<(           \
+      const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \
+    ap_int_base<_AP_W, _AP_S> r;                         \
+    if (_AP_S2)                                          \
+      r.V = op2 >= 0 ? (op.V << op2) : (op.V >> (-op2)); \
+    else                                                 \
+      r.V = op.V << op2;                                 \
+    return r;                                            \
+  }                                                      \
+  template <int _AP_W, bool _AP_S>                       \
+  INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator>>(           \
+      const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \
+    ap_int_base<_AP_W, _AP_S> r;                         \
+    if (_AP_S2)                                          \
+      r.V = op2 >= 0 ? (op.V >> op2) : (op.V << (-op2)); \
+    else                                                 \
+      r.V = op.V >> op2;                                 \
+    return r;                                            \
+  }
+
+ALL_OP_SHIFT_WITH_INT(char, 8, CHAR_IS_SIGNED)
+ALL_OP_SHIFT_WITH_INT(signed char, 8, true)
+ALL_OP_SHIFT_WITH_INT(short, _AP_SIZE_short, true)
+ALL_OP_SHIFT_WITH_INT(int, _AP_SIZE_int, true)
+ALL_OP_SHIFT_WITH_INT(long, _AP_SIZE_long, true)
+ALL_OP_SHIFT_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+
+#undef ALL_OP_SHIFT_WITH_INT
+
+#define ALL_OP_SHIFT_WITH_INT(C_TYPE, _AP_W2, _AP_S2)    \
+  template <int _AP_W, bool _AP_S>                       \
+  INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator<<(           \
+      const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \
+    ap_int_base<_AP_W, _AP_S> r;                         \
+    r.V = op.V << op2;                                   \
+    return r;                                            \
+  }                                                      \
+  template <int _AP_W, bool _AP_S>                       \
+  INLINE typename ap_int_base<_AP_W, _AP_S>::template RType<_AP_W,_AP_S>::arg1 operator>>(           \
+      const ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) { \
+    ap_int_base<_AP_W, _AP_S> r;                         \
+    r.V = op.V >> op2;                                   \
+    return r;                                            \
+  }
+ALL_OP_SHIFT_WITH_INT(bool, 1, false)
+ALL_OP_SHIFT_WITH_INT(unsigned char, 8, false)
+ALL_OP_SHIFT_WITH_INT(unsigned short, _AP_SIZE_short, false)
+ALL_OP_SHIFT_WITH_INT(unsigned int, _AP_SIZE_int, false)
+ALL_OP_SHIFT_WITH_INT(unsigned long, _AP_SIZE_long, false)
+ALL_OP_SHIFT_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef ALL_OP_SHIFT_WITH_INT
+
+// compound assign operators.
+#define OP_ASSIGN_WITH_INT(ASSIGN_OP, C_TYPE, _AP_W2, _AP_S2)       \
+  template <int _AP_W, bool _AP_S>                                  \
+  INLINE ap_int_base<_AP_W, _AP_S>& operator ASSIGN_OP(             \
+      ap_int_base<_AP_W, _AP_S>& op, C_TYPE op2) {                  \
+    return op ASSIGN_OP ap_int_base<_AP_W2, _AP_S2>(op2);           \
+  }
+
+// TODO int a; ap_int<16> b; a += b;
+
+#define ALL_OP_ASSIGN_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \
+  OP_ASSIGN_WITH_INT(+=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(-=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(*=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(/=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(%=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(&=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(|=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(^=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_ASSIGN_WITH_INT(>>=, C_TYPE, _AP_W2, _AP_S2)      \
+  OP_ASSIGN_WITH_INT(<<=, C_TYPE, _AP_W2, _AP_S2)
+
+ALL_OP_ASSIGN_WITH_INT(bool, 1, false)
+ALL_OP_ASSIGN_WITH_INT(char, 8, CHAR_IS_SIGNED)
+ALL_OP_ASSIGN_WITH_INT(signed char, 8, true)
+ALL_OP_ASSIGN_WITH_INT(unsigned char, 8, false)
+ALL_OP_ASSIGN_WITH_INT(short, _AP_SIZE_short, true)
+ALL_OP_ASSIGN_WITH_INT(unsigned short, _AP_SIZE_short, false)
+ALL_OP_ASSIGN_WITH_INT(int, _AP_SIZE_int, true)
+ALL_OP_ASSIGN_WITH_INT(unsigned int, _AP_SIZE_int, false)
+ALL_OP_ASSIGN_WITH_INT(long, _AP_SIZE_long, true)
+ALL_OP_ASSIGN_WITH_INT(unsigned long, _AP_SIZE_long, false)
+ALL_OP_ASSIGN_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+ALL_OP_ASSIGN_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef OP_ASSIGN_WITH_INT
+#undef ALL_OP_ASSIGN_WITH_INT
+
+// equality and relational operators.
+#define OP_REL_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)              \
+  template <int _AP_W, bool _AP_S>                                   \
+  INLINE bool operator REL_OP(C_TYPE i_op,                           \
+                              const ap_int_base<_AP_W, _AP_S>& op) { \
+    return ap_int_base<_AP_W2, _AP_S2>(i_op) REL_OP op;              \
+  }                                                                  \
+  template <int _AP_W, bool _AP_S>                                   \
+  INLINE bool operator REL_OP(const ap_int_base<_AP_W, _AP_S>& op,   \
+                              C_TYPE op2) {                          \
+    return op REL_OP ap_int_base<_AP_W2, _AP_S2>(op2);               \
+  }
+
+#define ALL_OP_REL_WITH_INT(C_TYPE, _AP_W2, _AP_S2) \
+  OP_REL_WITH_INT(>, C_TYPE, _AP_W2, _AP_S2)        \
+  OP_REL_WITH_INT(<, C_TYPE, _AP_W2, _AP_S2)        \
+  OP_REL_WITH_INT(>=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_REL_WITH_INT(<=, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_REL_WITH_INT(==, C_TYPE, _AP_W2, _AP_S2)       \
+  OP_REL_WITH_INT(!=, C_TYPE, _AP_W2, _AP_S2)
+
+ALL_OP_REL_WITH_INT(bool, 1, false)
+ALL_OP_REL_WITH_INT(char, 8, CHAR_IS_SIGNED)
+ALL_OP_REL_WITH_INT(signed char, 8, true)
+ALL_OP_REL_WITH_INT(unsigned char, 8, false)
+ALL_OP_REL_WITH_INT(short, _AP_SIZE_short, true)
+ALL_OP_REL_WITH_INT(unsigned short, _AP_SIZE_short, false)
+ALL_OP_REL_WITH_INT(int, _AP_SIZE_int, true)
+ALL_OP_REL_WITH_INT(unsigned int, _AP_SIZE_int, false)
+ALL_OP_REL_WITH_INT(long, _AP_SIZE_long, true)
+ALL_OP_REL_WITH_INT(unsigned long, _AP_SIZE_long, false)
+ALL_OP_REL_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+ALL_OP_REL_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef OP_REL_WITH_INT
+#undef ALL_OP_BIN_WITH_INT
+
+#define OP_REL_WITH_DOUBLE_OR_FLOAT(Sym)                            \
+  template <int _AP_W, bool _AP_S>                                  \
+  INLINE bool operator Sym(const ap_int_base<_AP_W, _AP_S>& op1,    \
+                           double op2) {                            \
+    return op1.to_double() Sym op2 ;                                \
+  }                                                                 \
+  template <int _AP_W, bool _AP_S>                                  \
+  INLINE bool operator Sym(double op1,                              \
+                           const ap_int_base<_AP_W, _AP_S>& op2) {  \
+    return op1 Sym op2.to_double() ;                                \
+  }                                                                 \
+  template <int _AP_W, bool _AP_S>                                  \
+  INLINE bool operator Sym(const ap_int_base<_AP_W, _AP_S>& op1,    \
+                           float op2) {                             \
+    return op1.to_double() Sym op2 ;                                \
+  }                                                                 \
+  template <int _AP_W, bool _AP_S>                                  \
+  INLINE bool operator Sym(float op1,                               \
+                           const ap_int_base<_AP_W, _AP_S>& op2) {  \
+    return op1 Sym op2.to_double() ;                                \
+  }
+  OP_REL_WITH_DOUBLE_OR_FLOAT(>)
+  OP_REL_WITH_DOUBLE_OR_FLOAT(<)
+  OP_REL_WITH_DOUBLE_OR_FLOAT(>=)
+  OP_REL_WITH_DOUBLE_OR_FLOAT(<=)
+  OP_REL_WITH_DOUBLE_OR_FLOAT(==)
+  OP_REL_WITH_DOUBLE_OR_FLOAT(!=)
+
+#undef OP_REL_WITH_DOUBLE_OR_FLOAT
+
+
+/* Operators with ap_bit_ref.
+ * ------------------------------------------------------------
+ */
+// arithmetic, bitwise and shift operators.
+#define OP_BIN_WITH_RANGE(BIN_OP, RTYPE)                                     \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>                \
+  INLINE typename ap_int_base<_AP_W1, _AP_S1>::template RType<_AP_W2,        \
+                                                              _AP_S2>::RTYPE \
+  operator BIN_OP(const ap_range_ref<_AP_W1, _AP_S1>& op1,                   \
+                  const ap_int_base<_AP_W2, _AP_S2>& op2) {                  \
+    return ap_int_base<_AP_W1, false>(op1) BIN_OP op2;                       \
+  }                                                                          \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>                \
+  INLINE typename ap_int_base<_AP_W1, _AP_S1>::template RType<_AP_W2,        \
+                                                              _AP_S2>::RTYPE \
+  operator BIN_OP(const ap_int_base<_AP_W1, _AP_S1>& op1,                    \
+                  const ap_range_ref<_AP_W2, _AP_S2>& op2) {                 \
+    return op1 BIN_OP ap_int_base<_AP_W2, false>(op2);                       \
+  }
+
+OP_BIN_WITH_RANGE(+, plus)
+OP_BIN_WITH_RANGE(-, minus)
+OP_BIN_WITH_RANGE(*, mult)
+OP_BIN_WITH_RANGE(/, div)
+OP_BIN_WITH_RANGE(%, mod)
+OP_BIN_WITH_RANGE(&, logic)
+OP_BIN_WITH_RANGE(|, logic)
+OP_BIN_WITH_RANGE(^, logic)
+OP_BIN_WITH_RANGE(>>, arg1)
+OP_BIN_WITH_RANGE(<<, arg1)
+
+#undef OP_BIN_WITH_RANGE
+
+// compound assignment operators.
+#define OP_ASSIGN_WITH_RANGE(ASSIGN_OP)                                      \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>                \
+  INLINE ap_int_base<_AP_W1, _AP_S1>& operator ASSIGN_OP(                    \
+      ap_int_base<_AP_W1, _AP_S1>& op1, ap_range_ref<_AP_W2, _AP_S2>& op2) { \
+    return op1 ASSIGN_OP ap_int_base<_AP_W2, false>(op2);                    \
+  }                                                                          \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>                \
+  INLINE ap_range_ref<_AP_W1, _AP_S1>& operator ASSIGN_OP(                   \
+      ap_range_ref<_AP_W1, _AP_S1>& op1, ap_int_base<_AP_W2, _AP_S2>& op2) { \
+    ap_int_base<_AP_W1, false> tmp(op1);                                     \
+    tmp ASSIGN_OP op2;                                                       \
+    op1 = tmp;                                                               \
+    return op1;                                                              \
+  }
+
+OP_ASSIGN_WITH_RANGE(+=)
+OP_ASSIGN_WITH_RANGE(-=)
+OP_ASSIGN_WITH_RANGE(*=)
+OP_ASSIGN_WITH_RANGE(/=)
+OP_ASSIGN_WITH_RANGE(%=)
+OP_ASSIGN_WITH_RANGE(&=)
+OP_ASSIGN_WITH_RANGE(|=)
+OP_ASSIGN_WITH_RANGE(^=)
+OP_ASSIGN_WITH_RANGE(>>=)
+OP_ASSIGN_WITH_RANGE(<<=)
+
+#undef OP_ASSIGN_WITH_RANGE
+
+// equality and relational operators
+#define OP_REL_WITH_RANGE(REL_OP)                                          \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>              \
+  INLINE bool operator REL_OP(const ap_range_ref<_AP_W1, _AP_S1>& op1,     \
+                              const ap_int_base<_AP_W2, _AP_S2>& op2) {    \
+    return ap_int_base<_AP_W1, false>(op1).operator REL_OP(op2);           \
+  }                                                                        \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>              \
+  INLINE bool operator REL_OP(const ap_int_base<_AP_W1, _AP_S1>& op1,      \
+                              const ap_range_ref<_AP_W2, _AP_S2>& op2) {   \
+    return op1.operator REL_OP(op2.operator ap_int_base<_AP_W2, false>()); \
+  }
+
+OP_REL_WITH_RANGE(==)
+OP_REL_WITH_RANGE(!=)
+OP_REL_WITH_RANGE(>)
+OP_REL_WITH_RANGE(>=)
+OP_REL_WITH_RANGE(<)
+OP_REL_WITH_RANGE(<=)
+
+#undef OP_REL_WITH_RANGE
+
+/* Operators with ap_bit_ref.
+ * ------------------------------------------------------------
+ */
+// arithmetic, bitwise and shift operators.
+#define OP_BIN_WITH_BIT(BIN_OP, RTYPE)                                         \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>                  \
+  INLINE typename ap_int_base<_AP_W1, _AP_S1>::template RType<1, false>::RTYPE \
+  operator BIN_OP(const ap_int_base<_AP_W1, _AP_S1>& op1,                      \
+                  const ap_bit_ref<_AP_W2, _AP_S2>& op2) {                     \
+    return op1 BIN_OP ap_int_base<1, false>(op2);                              \
+  }                                                                            \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>                  \
+  INLINE typename ap_int_base<1, false>::template RType<_AP_W2, _AP_S2>::RTYPE \
+  operator BIN_OP(const ap_bit_ref<_AP_W1, _AP_S1>& op1,                       \
+                  const ap_int_base<_AP_W2, _AP_S2>& op2) {                    \
+    return ap_int_base<1, false>(op1) BIN_OP op2;                              \
+  }
+
+OP_BIN_WITH_BIT(+, plus)
+OP_BIN_WITH_BIT(-, minus)
+OP_BIN_WITH_BIT(*, mult)
+OP_BIN_WITH_BIT(/, div)
+OP_BIN_WITH_BIT(%, mod)
+OP_BIN_WITH_BIT(&, logic)
+OP_BIN_WITH_BIT(|, logic)
+OP_BIN_WITH_BIT(^, logic)
+OP_BIN_WITH_BIT(>>, arg1)
+OP_BIN_WITH_BIT(<<, arg1)
+
+#undef OP_BIN_WITH_BIT
+
+// compound assignment operators.
+#define OP_ASSIGN_WITH_BIT(ASSIGN_OP)                                      \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>              \
+  INLINE ap_int_base<_AP_W1, _AP_S1>& operator ASSIGN_OP(                  \
+      ap_int_base<_AP_W1, _AP_S1>& op1, ap_bit_ref<_AP_W2, _AP_S2>& op2) { \
+    return op1 ASSIGN_OP ap_int_base<1, false>(op2);                       \
+  }                                                                        \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>              \
+  INLINE ap_bit_ref<_AP_W1, _AP_S1>& operator ASSIGN_OP(                   \
+      ap_bit_ref<_AP_W1, _AP_S1>& op1, ap_int_base<_AP_W2, _AP_S2>& op2) { \
+    ap_int_base<1, false> tmp(op1);                                        \
+    tmp ASSIGN_OP op2;                                                     \
+    op1 = tmp;                                                             \
+    return op1;                                                            \
+  }
+
+OP_ASSIGN_WITH_BIT(+=)
+OP_ASSIGN_WITH_BIT(-=)
+OP_ASSIGN_WITH_BIT(*=)
+OP_ASSIGN_WITH_BIT(/=)
+OP_ASSIGN_WITH_BIT(%=)
+OP_ASSIGN_WITH_BIT(&=)
+OP_ASSIGN_WITH_BIT(|=)
+OP_ASSIGN_WITH_BIT(^=)
+OP_ASSIGN_WITH_BIT(>>=)
+OP_ASSIGN_WITH_BIT(<<=)
+
+#undef OP_ASSIGN_WITH_BIT
+
+// equality and relational operators.
+#define OP_REL_WITH_BIT(REL_OP)                                         \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>           \
+  INLINE bool operator REL_OP(const ap_int_base<_AP_W1, _AP_S1>& op1,   \
+                              const ap_bit_ref<_AP_W2, _AP_S2>& op2) {  \
+    return op1 REL_OP ap_int_base<1, false>(op2);                       \
+  }                                                                     \
+  template <int _AP_W1, bool _AP_S1, int _AP_W2, bool _AP_S2>           \
+  INLINE bool operator REL_OP(const ap_bit_ref<_AP_W1, _AP_S1>& op1,    \
+                              const ap_int_base<_AP_W2, _AP_S2>& op2) { \
+    return ap_int_base<1, false>(op1) REL_OP op2;                       \
+  }
+
+OP_REL_WITH_BIT(==)
+OP_REL_WITH_BIT(!=)
+OP_REL_WITH_BIT(>)
+OP_REL_WITH_BIT(>=)
+OP_REL_WITH_BIT(<)
+OP_REL_WITH_BIT(<=)
+
+#undef OP_REL_WITH_BIT
+
+
+/* Operators with ap_concat_ref.
+ * ------------------------------------------------------------
+ */
+// arithmetic, bitwise and shift operators.
+// bitwise operators are defined in struct.
+// TODO specify whether to define arithmetic and bitwise operators.
+#if 0
+#define OP_BIN_WITH_CONCAT(BIN_OP, RTYPE)                                      \
+  template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2,          \
+            int _AP_W3, bool _AP_S3>                                           \
+  INLINE typename ap_int_base<_AP_W3, _AP_S3>::template RType<_AP_W1 + _AP_W2, \
+                                                              false>::RTYPE    \
+  operator BIN_OP(const ap_int_base<_AP_W3, _AP_S3>& op1,                      \
+                  const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op2) {  \
+    /* convert ap_concat_ref to ap_int_base */                                 \
+    return op1 BIN_OP op2.get();                                               \
+  }                                                                            \
+  template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2,          \
+            int _AP_W3, bool _AP_S3>                                           \
+  INLINE typename ap_int_base<_AP_W1 + _AP_W2,                                 \
+                              false>::template RType<_AP_W3, _AP_S3>::RTYPE    \
+  operator BIN_OP(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op1,    \
+                  const ap_int_base<_AP_W3, _AP_S3>& op2) {                    \
+    /* convert ap_concat_ref to ap_int_base */                                 \
+    return op1.get() BIN_OP op2;                                               \
+  }
+
+OP_BIN_WITH_CONCAT(+, plus)
+OP_BIN_WITH_CONCAT(-, minus)
+OP_BIN_WITH_CONCAT(*, mult)
+OP_BIN_WITH_CONCAT(/, div)
+OP_BIN_WITH_CONCAT(%, mod)
+OP_BIN_WITH_CONCAT(&, logic)
+OP_BIN_WITH_CONCAT(|, logic)
+OP_BIN_WITH_CONCAT(^, logic)
+OP_BIN_WITH_CONCAT(>>, arg1)
+OP_BIN_WITH_CONCAT(<<, arg1)
+
+#undef OP_BIN_WITH_CONCAT
+
+// compound assignment operators.
+#define OP_ASSIGN_WITH_CONCAT(ASSIGN_OP)                                       \
+  template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2,          \
+            int _AP_W3, bool _AP_S3>                                           \
+  INLINE typename ap_int_base<_AP_W3, _AP_S3>::template RType<_AP_W1 + _AP_W2, \
+                                                              false>::RTYPE    \
+  operator ASSIGN_OP(                                                          \
+      const ap_int_base<_AP_W3, _AP_S3>& op1,                                  \
+      const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op2) {              \
+    /* convert ap_concat_ref to ap_int_base */                                 \
+    return op1 ASSIGN_OP op2.get();                                            \
+  }                                                                            \
+  template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2,          \
+            int _AP_W3, bool _AP_S3>                                           \
+  INLINE typename ap_int_base<_AP_W1 + _AP_W2,                                 \
+                              false>::template RType<_AP_W3, _AP_S3>::RTYPE    \
+  operator ASSIGN_OP(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op1, \
+                     const ap_int_base<_AP_W3, _AP_S3>& op2) {                 \
+    /* convert ap_concat_ref to ap_int_base */                                 \
+    ap_int_base<_AP_W1 + _AP_W2, false> tmp = op1.get();                       \
+    tmp ASSIGN_OP op2;                                                         \
+    op1 = tmp;                                                                 \
+    return op1;                                                                \
+  }
+
+OP_ASSIGN_WITH_CONCAT(+=)
+OP_ASSIGN_WITH_CONCAT(-=)
+OP_ASSIGN_WITH_CONCAT(*=)
+OP_ASSIGN_WITH_CONCAT(/=)
+OP_ASSIGN_WITH_CONCAT(%=)
+OP_ASSIGN_WITH_CONCAT(&=)
+OP_ASSIGN_WITH_CONCAT(|=)
+OP_ASSIGN_WITH_CONCAT(^=)
+OP_ASSIGN_WITH_CONCAT(>>=)
+OP_ASSIGN_WITH_CONCAT(<<=)
+
+#undef OP_ASSIGN_WITH_CONCAT
+#endif
+
+// equality and relational operators.
+#define OP_REL_WITH_CONCAT(REL_OP)                                    \
+  template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2, \
+            int _AP_W3, bool _AP_S3>                                  \
+  INLINE bool operator REL_OP(                                        \
+      const ap_int_base<_AP_W3, _AP_S3>& op1,                         \
+      const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op2) {     \
+    /* convert ap_concat_ref to ap_int_base */                        \
+    return op1 REL_OP op2.get();                                      \
+  }                                                                   \
+  template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2, \
+            int _AP_W3, bool _AP_S3>                                  \
+  INLINE bool operator REL_OP(                                        \
+      const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& op1,       \
+      const ap_int_base<_AP_W3, _AP_S3>& op2) {                       \
+    /* convert ap_concat_ref to ap_int_base */                        \
+    return op1.get() REL_OP op2;                                      \
+  }
+
+OP_REL_WITH_CONCAT(==)
+OP_REL_WITH_CONCAT(!=)
+OP_REL_WITH_CONCAT(>)
+OP_REL_WITH_CONCAT(>=)
+OP_REL_WITH_CONCAT(<)
+OP_REL_WITH_CONCAT(<=)
+
+#undef OP_REL_WITH_CONCAT
+
+#endif // ifndef __cplusplus
+#endif // ifndef __AP_INT_BASE_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_int_ref.h

@@ -0,0 +1,1346 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_INT_REF_H__
+#define __AP_INT_REF_H__
+
+#ifndef __AP_INT_H__
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+#ifndef __cplusplus
+#error "C++ is required to include this header file"
+
+#else
+
+#ifndef __SYNTHESIS__
+#include <iostream>
+#endif
+
+/* Concatination reference.
+   ----------------------------------------------------------------
+*/
+template <int _AP_W1, typename _AP_T1, int _AP_W2, typename _AP_T2>
+struct ap_concat_ref {
+  enum {
+    _AP_WR = _AP_W1 + _AP_W2,
+  };
+
+  _AP_T1& mbv1;
+  _AP_T2& mbv2;
+
+  INLINE ap_concat_ref(const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& ref)
+      : mbv1(ref.mbv1), mbv2(ref.mbv2) {}
+
+  INLINE ap_concat_ref(_AP_T1& bv1, _AP_T2& bv2) : mbv1(bv1), mbv2(bv2) {}
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_concat_ref& operator=(const ap_int_base<_AP_W3, _AP_S3>& val) {
+    ap_int_base<_AP_W1 + _AP_W2, false> vval(val);
+    int W_ref1 = mbv1.length();
+    int W_ref2 = mbv2.length();
+    ap_int_base<_AP_W1, false> Part1;
+    Part1.V = _AP_ROOT_op_get_range(vval.V, W_ref2, W_ref1 + W_ref2 - 1);
+    mbv1.set(Part1);
+    ap_int_base<_AP_W2, false> Part2;
+    Part2.V = _AP_ROOT_op_get_range(vval.V, 0, W_ref2 - 1);
+    mbv2.set(Part2);
+    return *this;
+  }
+
+  // assign op from hls supported C integral types.
+  // FIXME disabled to support legacy code directly assign from sc_signal<T>
+  //template <typename T>
+  //INLINE typename _ap_type::enable_if<_ap_type::is_integral<T>::value,
+  //                                    ap_concat_ref&>::type
+  //operator=(T val) {
+  //  ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val);
+  //  return operator=(tmpVal);
+  //}
+#define ASSIGN_WITH_CTYPE(_Tp)                       \
+  INLINE ap_concat_ref& operator=(_Tp val) {         \
+    ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val); \
+    return operator=(tmpVal);                        \
+  }
+
+  ASSIGN_WITH_CTYPE(bool)
+  ASSIGN_WITH_CTYPE(char)
+  ASSIGN_WITH_CTYPE(signed char)
+  ASSIGN_WITH_CTYPE(unsigned char)
+  ASSIGN_WITH_CTYPE(short)
+  ASSIGN_WITH_CTYPE(unsigned short)
+  ASSIGN_WITH_CTYPE(int)
+  ASSIGN_WITH_CTYPE(unsigned int)
+  ASSIGN_WITH_CTYPE(long)
+  ASSIGN_WITH_CTYPE(unsigned long)
+  ASSIGN_WITH_CTYPE(ap_slong)
+  ASSIGN_WITH_CTYPE(ap_ulong)
+#if _AP_ENABLE_HALF_ == 1
+  ASSIGN_WITH_CTYPE(half)
+#endif
+  ASSIGN_WITH_CTYPE(float)
+  ASSIGN_WITH_CTYPE(double)
+
+#undef ASSIGN_WITH_CTYPE
+
+  // Be explicit to prevent it from being deleted, as field d_bv
+  // is of reference type.
+  INLINE ap_concat_ref& operator=(
+      const ap_concat_ref<_AP_W1, _AP_T1, _AP_W2, _AP_T2>& val) {
+    ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val);
+    return operator=(tmpVal);
+  }
+
+  template <int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+  INLINE ap_concat_ref& operator=(
+      const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4>& val) {
+    ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val);
+    return operator=(tmpVal);
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_concat_ref& operator=(const ap_bit_ref<_AP_W3, _AP_S3>& val) {
+    ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val);
+    return operator=(tmpVal);
+  }
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_concat_ref& operator=(const ap_range_ref<_AP_W3, _AP_S3>& val) {
+    ap_int_base<_AP_W1 + _AP_W2, false> tmpVal(val);
+    return operator=(tmpVal);
+  }
+
+  template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3,
+            ap_o_mode _AP_O3, int _AP_N3>
+  INLINE ap_concat_ref& operator=(
+      const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& val) {
+    return operator=((const ap_int_base<_AP_W3, false>)(val));
+  }
+
+  template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3,
+            ap_o_mode _AP_O3, int _AP_N3>
+  INLINE ap_concat_ref& operator=(
+      const ap_fixed_base<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>&
+          val) {
+    return operator=(val.to_ap_int_base());
+  }
+
+  template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3,
+            ap_o_mode _AP_O3, int _AP_N3>
+  INLINE ap_concat_ref& operator=(
+      const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>& val) {
+    return operator=((ap_ulong)(bool)(val));
+  }
+
+  INLINE operator ap_int_base<_AP_WR, false>() const { return get(); }
+
+  INLINE operator ap_ulong() const { return get().to_uint64(); }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3,
+                       ap_range_ref<_AP_W3, _AP_S3> >
+  operator,(const ap_range_ref<_AP_W3, _AP_S3> &a2) {
+    return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3,
+                         ap_range_ref<_AP_W3, _AP_S3> >(
+        *this, const_cast<ap_range_ref<_AP_W3, _AP_S3>&>(a2));
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE
+      ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> >
+      operator,(ap_int_base<_AP_W3, _AP_S3> &a2) {
+    return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3,
+                         ap_int_base<_AP_W3, _AP_S3> >(*this, a2);
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE
+      ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> >
+      operator,(volatile ap_int_base<_AP_W3, _AP_S3> &a2) {
+    return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3,
+                         ap_int_base<_AP_W3, _AP_S3> >(
+        *this, const_cast<ap_int_base<_AP_W3, _AP_S3>&>(a2));
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE
+      ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> >
+      operator,(const ap_int_base<_AP_W3, _AP_S3> &a2) {
+    return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3,
+                         ap_int_base<_AP_W3, _AP_S3> >(
+        *this, const_cast<ap_int_base<_AP_W3, _AP_S3>&>(a2));
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE
+      ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3, ap_int_base<_AP_W3, _AP_S3> >
+      operator,(const volatile ap_int_base<_AP_W3, _AP_S3> &a2) {
+    // FIXME op's life does not seem long enough
+    ap_int_base<_AP_W3, _AP_S3> op(a2);
+    return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3,
+                         ap_int_base<_AP_W3, _AP_S3> >(
+        *this, const_cast<ap_int_base<_AP_W3, _AP_S3>&>(op));
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_concat_ref<_AP_WR, ap_concat_ref, 1, ap_bit_ref<_AP_W3, _AP_S3> >
+  operator,(const ap_bit_ref<_AP_W3, _AP_S3> &a2) {
+    return ap_concat_ref<_AP_WR, ap_concat_ref, 1, ap_bit_ref<_AP_W3, _AP_S3> >(
+        *this, const_cast<ap_bit_ref<_AP_W3, _AP_S3>&>(a2));
+  }
+
+  template <int _AP_W3, typename _AP_T3, int _AP_W4, typename _AP_T4>
+  INLINE ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3 + _AP_W4,
+                       ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> >
+  operator,(const ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> &a2) {
+    return ap_concat_ref<_AP_WR, ap_concat_ref, _AP_W3 + _AP_W4,
+                         ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4> >(
+        *this, const_cast<ap_concat_ref<_AP_W3, _AP_T3, _AP_W4, _AP_T4>&>(a2));
+  }
+
+  template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3,
+            ap_o_mode _AP_O3, int _AP_N3>
+  INLINE ap_concat_ref<
+      _AP_WR, ap_concat_ref, _AP_W3,
+      af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >
+  operator,(
+      const af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> &a2) {
+    return ap_concat_ref<
+        _AP_WR, ap_concat_ref, _AP_W3,
+        af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >(
+        *this,
+        const_cast<
+            af_range_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>&>(a2));
+  }
+
+  template <int _AP_W3, int _AP_I3, bool _AP_S3, ap_q_mode _AP_Q3,
+            ap_o_mode _AP_O3, int _AP_N3>
+  INLINE
+      ap_concat_ref<_AP_WR, ap_concat_ref, 1,
+                    af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >
+      operator,(const af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>
+                    &a2) {
+    return ap_concat_ref<
+        _AP_WR, ap_concat_ref, 1,
+        af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3> >(
+        *this,
+        const_cast<af_bit_ref<_AP_W3, _AP_I3, _AP_S3, _AP_Q3, _AP_O3, _AP_N3>&>(
+            a2));
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_int_base<AP_MAX(_AP_WR, _AP_W3), _AP_S3> operator&(
+      const ap_int_base<_AP_W3, _AP_S3>& a2) {
+    return get() & a2;
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_int_base<AP_MAX(_AP_WR, _AP_W3), _AP_S3> operator|(
+      const ap_int_base<_AP_W3, _AP_S3>& a2) {
+    return get() | a2;
+  }
+
+  template <int _AP_W3, bool _AP_S3>
+  INLINE ap_int_base<AP_MAX(_AP_WR, _AP_W3), _AP_S3> operator^(
+      const ap_int_base<_AP_W3, _AP_S3>& a2) {
+    return get() ^ a2;
+  }
+
+#if 0
+  template<int Hi, int Lo>
+  INLINE ap_int_base<Hi-Lo+1, false> slice() {
+    ap_int_base<_AP_WR, false> bv = get();
+    return bv.slice<Hi,Lo>();
+  }
+#endif
+
+  INLINE ap_int_base<_AP_WR, false> get() const {
+    ap_int_base<_AP_WR, false> tmpVal(0);
+    int W_ref1 = mbv1.length();
+    int W_ref2 = mbv2.length();
+    ap_int_base<_AP_W2, false> v2(mbv2);
+    ap_int_base<_AP_W1, false> v1(mbv1);
+    tmpVal.V = _AP_ROOT_op_set_range(tmpVal.V, 0, W_ref2 - 1, v2.V);
+    tmpVal.V =
+        _AP_ROOT_op_set_range(tmpVal.V, W_ref2, W_ref1 + W_ref2 - 1, v1.V);
+    return tmpVal;
+  }
+
+  template <int _AP_W3>
+  INLINE void set(const ap_int_base<_AP_W3, false>& val) {
+    ap_int_base<_AP_W1 + _AP_W2, false> vval(val);
+    int W_ref1 = mbv1.length();
+    int W_ref2 = mbv2.length();
+    ap_int_base<_AP_W1, false> tmpVal1;
+    tmpVal1.V = _AP_ROOT_op_get_range(vval.V, W_ref2, W_ref1 + W_ref2 - 1);
+    mbv1.set(tmpVal1);
+    ap_int_base<_AP_W2, false> tmpVal2;
+    tmpVal2.V = _AP_ROOT_op_get_range(vval.V, 0, W_ref2 - 1);
+    mbv2.set(tmpVal2);
+  }
+
+  INLINE int length() const { return mbv1.length() + mbv2.length(); }
+}; // struct ap_concat_ref
+
+/* Range (slice) reference.
+   ----------------------------------------------------------------
+*/
+template <int _AP_W, bool _AP_S>
+struct ap_range_ref {
+  // struct ssdm_int or its sim model.
+  // TODO make it possible to reference to ap_fixed_base/ap_fixed/ap_ufixed
+  //      and then we can retire af_range_ref.
+  typedef ap_int_base<_AP_W, _AP_S> ref_type;
+  ref_type& d_bv;
+  int l_index;
+  int h_index;
+
+ public:
+  INLINE ap_range_ref(const ap_range_ref<_AP_W, _AP_S>& ref)
+      : d_bv(ref.d_bv), l_index(ref.l_index), h_index(ref.h_index) {}
+
+  INLINE ap_range_ref(ref_type* bv, int h, int l)
+      : d_bv(*bv), l_index(l), h_index(h) {}
+
+  INLINE ap_range_ref(const ref_type* bv, int h, int l)
+      : d_bv(*const_cast<ref_type*>(bv)), l_index(l), h_index(h) {}
+
+  INLINE operator ap_int_base<_AP_W, false>() const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret;
+  }
+
+  INLINE operator ap_ulong() const { return to_uint64(); }
+
+  /// @name assign operators
+  //  @{
+
+  // FIXME disabled to work-around lagacy code assigning from sc_signal<T>,
+  // which dependes on implicit type conversion.
+  //
+  //   /// assign from hls supported C integral types.
+  //   template <typename T>
+  //   INLINE typename _ap_type::enable_if<_ap_type::is_integral<T>::value,
+  //                                       ap_range_ref&>::type
+  //   operator=(T val) {
+  //     ap_int_base<_AP_W, false> tmp(val);
+  //     d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V);
+  //     return *this;
+  //   }
+#define ASSIGN_WITH_CTYPE(_Tp)                                       \
+  INLINE ap_range_ref& operator=(_Tp val) {                          \
+    ap_int_base<_AP_W, false> tmp(val);                              \
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V); \
+    return *this;                                                    \
+  }
+
+  ASSIGN_WITH_CTYPE(bool)
+  ASSIGN_WITH_CTYPE(char)
+  ASSIGN_WITH_CTYPE(signed char)
+  ASSIGN_WITH_CTYPE(unsigned char)
+  ASSIGN_WITH_CTYPE(short)
+  ASSIGN_WITH_CTYPE(unsigned short)
+  ASSIGN_WITH_CTYPE(int)
+  ASSIGN_WITH_CTYPE(unsigned int)
+  ASSIGN_WITH_CTYPE(long)
+  ASSIGN_WITH_CTYPE(unsigned long)
+  ASSIGN_WITH_CTYPE(ap_slong)
+  ASSIGN_WITH_CTYPE(ap_ulong)
+#if _AP_ENABLE_HALF_ == 1
+  ASSIGN_WITH_CTYPE(half)
+#endif
+  ASSIGN_WITH_CTYPE(float)
+  ASSIGN_WITH_CTYPE(double)
+
+#undef ASSIGN_WITH_CTYPE
+
+  /// assign using string. XXX crucial for cosim.
+  INLINE ap_range_ref& operator=(const char* val) {
+    const ap_int_base<_AP_W, false> tmp(val); // XXX figure out radix
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V);
+    return *this;
+  }
+
+  /// assign from ap_int_base.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref& operator=(const ap_int_base<_AP_W2, _AP_S2>& val) {
+    ap_int_base<_AP_W, false> tmp(val);
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, tmp.V);
+    return *this;
+  }
+
+  /// copy assign operator
+  // XXX Be explicit to prevent it from being deleted, as field d_bv
+  // is of reference type.
+  INLINE ap_range_ref& operator=(const ap_range_ref& val) {
+    return operator=((const ap_int_base<_AP_W, false>)val);
+  }
+
+  /// assign from range reference to ap_int_base.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) {
+    return operator=((const ap_int_base<_AP_W2, false>)val);
+  }
+
+  /// assign from bit reference to ap_int_base.
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) {
+    return operator=((ap_ulong)(bool)(val));
+  }
+
+  /// assign from ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_range_ref& operator=(
+      const ap_fixed_base<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&
+          val) {
+    return operator=(val.to_ap_int_base());
+  }
+
+  /// assign from range reference to ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_range_ref& operator=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    return operator=((const ap_int_base<_AP_W2, false>)val);
+  }
+
+  /// assign from bit reference to ap_fixed_base.
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_range_ref& operator=(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    return operator=((ap_ulong)(bool)(val));
+  }
+
+  /// assign from compound reference.
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_range_ref& operator=(
+      const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+    return operator=((const ap_int_base<_AP_W2 + _AP_W3, false>)(val));
+  }
+  //  @}
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+      operator,(const ap_range_ref<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                         ap_range_ref<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_range_ref<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+      operator,(ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(*this, a2);
+  }
+
+  INLINE
+  ap_concat_ref<_AP_W, ap_range_ref, _AP_W, ap_int_base<_AP_W, _AP_S> >
+  operator,(ap_int_base<_AP_W, _AP_S>& a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W,
+                         ap_int_base<_AP_W, _AP_S> >(*this, a2);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+      operator,(volatile ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+      operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_range_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+      operator,(const volatile ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2,
+                         ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<_AP_W, ap_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >
+  operator,(const ap_bit_ref<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_bit_ref<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_concat_ref<_AP_W, ap_range_ref, _AP_W2 + _AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+  operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) {
+    return ap_concat_ref<_AP_W, ap_range_ref, _AP_W2 + _AP_W3,
+                         ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(
+        *this, const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>&>(a2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<
+      _AP_W, ap_range_ref, _AP_W2,
+      af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> a2) {
+    return ap_concat_ref<
+        _AP_W, ap_range_ref, _AP_W2,
+        af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<
+            af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE
+      ap_concat_ref<_AP_W, ap_range_ref, 1,
+                    af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+      operator,(const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>
+                    &a2) {
+    return ap_concat_ref<
+        _AP_W, ap_range_ref, 1,
+        af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(
+            a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator==(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> hop(op2);
+    return lop == hop;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator!=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return !(operator==(op2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator<(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> hop(op2);
+    return lop < hop;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator<=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    ap_int_base<_AP_W, false> lop(*this);
+    ap_int_base<_AP_W2, false> hop(op2);
+    return lop <= hop;
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator>(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return !(operator<=(op2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator>=(const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    return !(operator<(op2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref<_AP_W, _AP_S>& operator|=(
+      const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    (this->d_bv).V |= (op2.d_bv).V;
+    return *this;
+  };
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref<_AP_W, _AP_S>& operator|=(
+      const ap_int_base<_AP_W2, _AP_S2>& op2) {
+    (this->d_bv).V |= op2.V;
+    return *this;
+  };
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref<_AP_W, _AP_S>& operator&=(
+      const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    (this->d_bv).V &= (op2.d_bv).V;
+    return *this;
+  };
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref<_AP_W, _AP_S>& operator&=(
+      const ap_int_base<_AP_W2, _AP_S2>& op2) {
+    (this->d_bv).V &= op2.V;
+    return *this;
+  };
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref<_AP_W, _AP_S>& operator^=(
+      const ap_range_ref<_AP_W2, _AP_S2>& op2) {
+    (this->d_bv).V ^= (op2.d_bv).V;
+    return *this;
+  };
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_range_ref<_AP_W, _AP_S>& operator^=(
+      const ap_int_base<_AP_W2, _AP_S2>& op2) {
+    (this->d_bv).V ^= op2.V;
+    return *this;
+  };
+
+  INLINE ap_int_base<_AP_W, false> get() const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret;
+  }
+
+  template <int _AP_W2>
+  INLINE void set(const ap_int_base<_AP_W2, false>& val) {
+    d_bv.V = _AP_ROOT_op_set_range(d_bv.V, l_index, h_index, val.V);
+  }
+
+  INLINE int length() const {
+    return h_index >= l_index ? h_index - l_index + 1 : l_index - h_index + 1;
+  }
+
+  INLINE int to_int() const {
+    return (int)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE unsigned to_uint() const {
+    return (unsigned)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE long to_long() const {
+    return (long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE unsigned long to_ulong() const {
+    return (unsigned long)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE ap_slong to_int64() const {
+    return (ap_slong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE ap_ulong to_uint64() const {
+    return (ap_ulong)(_AP_ROOT_op_get_range(d_bv.V, l_index, h_index));
+  }
+
+  INLINE bool and_reduce() const {
+    bool ret = true;
+    bool reverse = l_index > h_index;
+    unsigned low = reverse ? h_index : l_index;
+    unsigned high = reverse ? l_index : h_index;
+    for (unsigned i = low; i != high; ++i) {
+#ifdef __SYNTHESIS__
+#pragma HLS unroll
+#endif
+      ret &= _AP_ROOT_op_get_bit(d_bv.V, i);
+    }
+    return ret;
+  }
+
+  INLINE bool or_reduce() const {
+    bool ret = false;
+    bool reverse = l_index > h_index;
+    unsigned low = reverse ? h_index : l_index;
+    unsigned high = reverse ? l_index : h_index;
+    for (unsigned i = low; i != high; ++i) {
+#ifdef __SYNTHESIS__
+#pragma HLS unroll
+#endif
+      ret |= _AP_ROOT_op_get_bit(d_bv.V, i);
+    }
+    return ret;
+  }
+
+  INLINE bool xor_reduce() const {
+    bool ret = false;
+    bool reverse = l_index > h_index;
+    unsigned low = reverse ? h_index : l_index;
+    unsigned high = reverse ? l_index : h_index;
+    for (unsigned i = low; i != high; ++i) {
+#ifdef __SYNTHESIS__
+#pragma HLS unroll
+#endif
+      ret ^= _AP_ROOT_op_get_bit(d_bv.V, i);
+    }
+    return ret;
+  }
+#ifndef __SYNTHESIS__
+  std::string to_string(signed char radix = 2) const {
+    ap_int_base<_AP_W, false> ret;
+    ret.V = _AP_ROOT_op_get_range(d_bv.V, l_index, h_index);
+    return ret.to_string(radix);
+  }
+#else
+  // XXX HLS will delete this in synthesis
+  INLINE char* to_string(signed char radix = 2) const {
+    return 0;
+  }
+#endif
+}; // struct ap_range_ref
+
+// XXX apcc cannot handle global std::ios_base::Init() brought in by <iostream>
+#ifndef AP_AUTOCC
+#ifndef __SYNTHESIS__
+template <int _AP_W, bool _AP_S>
+INLINE std::ostream& operator<<(std::ostream& os,
+                                const ap_range_ref<_AP_W, _AP_S>& x) {
+  std::ios_base::fmtflags ff = std::cout.flags();
+  if (ff & std::cout.hex) {
+    os << x.to_string(16); // don't print sign
+  } else if (ff & std::cout.oct) {
+    os << x.to_string(8); // don't print sign
+  } else {
+    os << x.to_string(10);
+  }
+  return os;
+}
+#endif // ifndef __SYNTHESIS__
+
+#ifndef __SYNTHESIS__
+template <int _AP_W, bool _AP_S>
+INLINE std::istream& operator>>(std::istream& in,
+                                ap_range_ref<_AP_W, _AP_S>& op) {
+  std::string str;
+  in >> str;
+  op = ap_int_base<_AP_W, _AP_S>(str.c_str());
+  return in;
+}
+#endif // ifndef __SYNTHESIS__
+#endif // ifndef AP_AUTOCC
+
+/* Bit reference.
+   ----------------------------------------------------------------
+*/
+template <int _AP_W, bool _AP_S>
+struct ap_bit_ref {
+  // struct ssdm_int or its sim model.
+  // TODO make it possible to reference to ap_fixed_base/ap_fixed/ap_ufixed
+  //      and then we can retire af_bit_ref.
+  typedef ap_int_base<_AP_W, _AP_S> ref_type;
+  ref_type& d_bv;
+  int d_index;
+
+ public:
+  // copy ctor
+  INLINE ap_bit_ref(const ap_bit_ref<_AP_W, _AP_S>& ref)
+      : d_bv(ref.d_bv), d_index(ref.d_index) {}
+
+  INLINE ap_bit_ref(ref_type* bv, int index = 0) : d_bv(*bv), d_index(index) {}
+
+  INLINE ap_bit_ref(const ref_type* bv, int index = 0)
+      : d_bv(*const_cast<ref_type*>(bv)), d_index(index) {}
+
+  INLINE operator bool() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); }
+  INLINE bool to_bool() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); }
+
+  // assign op from hls supported C integral types.
+  // FIXME disabled to support sc_signal<bool>.
+  // NOTE this used to be unsigned long long.
+  //template <typename T>
+  //INLINE typename _ap_type::enable_if<_ap_type::is_integral<T>::value,
+  //                                    ap_bit_ref&>::type
+  //operator=(T val) {
+  //  d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index, val);
+  //  return *this;
+  //}
+#define ASSIGN_WITH_CTYPE(_Tp)                          \
+  INLINE ap_bit_ref& operator=(_Tp val) {               \
+    d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index, val); \
+    return *this;                                       \
+  }
+
+  ASSIGN_WITH_CTYPE(bool)
+  ASSIGN_WITH_CTYPE(char)
+  ASSIGN_WITH_CTYPE(signed char)
+  ASSIGN_WITH_CTYPE(unsigned char)
+  ASSIGN_WITH_CTYPE(short)
+  ASSIGN_WITH_CTYPE(unsigned short)
+  ASSIGN_WITH_CTYPE(int)
+  ASSIGN_WITH_CTYPE(unsigned int)
+  ASSIGN_WITH_CTYPE(long)
+  ASSIGN_WITH_CTYPE(unsigned long)
+  ASSIGN_WITH_CTYPE(ap_slong)
+  ASSIGN_WITH_CTYPE(ap_ulong)
+
+#undef ASSIGN_WITH_CTYPE
+
+#define ASSIGN_WITH_CTYPE_FP(_Tp)                           \
+  INLINE ap_bit_ref& operator=(_Tp val) {                   \
+    bool tmp_val = val;                                     \
+    d_bv.V = _AP_ROOT_op_set_bit(d_bv.V, d_index,tmp_val);  \
+    return *this;                                           \
+  }
+
+#if _AP_ENABLE_HALF_ == 1
+  ASSIGN_WITH_CTYPE_FP(half)
+#endif
+  ASSIGN_WITH_CTYPE_FP(float)
+  ASSIGN_WITH_CTYPE_FP(double)
+
+#undef ASSIGN_WITH_CTYPE_FP
+
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_bit_ref& operator=(const ap_int_base<_AP_W2, _AP_S2>& val) {
+    return operator=((ap_ulong)(val.V != 0));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_bit_ref& operator=(const ap_range_ref<_AP_W2, _AP_S2>& val) {
+    return operator=((ap_int_base<_AP_W2, false>)val);
+  }
+
+  // Be explicit to prevent it from being deleted, as field d_bv
+  // is of reference type.
+  INLINE ap_bit_ref& operator=(const ap_bit_ref& val) {
+    return operator=((ap_ulong)(bool)val);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_bit_ref& operator=(const ap_bit_ref<_AP_W2, _AP_S2>& val) {
+    return operator=((ap_ulong)(bool)val);
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_bit_ref& operator=(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    return operator=((const ap_int_base<_AP_W2, false>)val);
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_bit_ref& operator=(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>& val) {
+    return operator=((ap_ulong)(bool)val);
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_bit_ref& operator=(
+      const ap_concat_ref<_AP_W2, _AP_T3, _AP_W3, _AP_T3>& val) {
+    return operator=((const ap_int_base<_AP_W2 + _AP_W3, false>)val);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >(
+        *this, a2);
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(volatile ap_int_base<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(const ap_int_base<_AP_W2, _AP_S2> &a2) {
+    ap_int_base<_AP_W2, _AP_S2> op(a2);
+    return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(op));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >
+  operator,(const volatile ap_int_base<_AP_W2, _AP_S2> &a2) {
+    ap_int_base<_AP_W2, _AP_S2> op(a2);
+    return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_int_base<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_int_base<_AP_W2, _AP_S2>&>(op));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >
+  operator,(const ap_range_ref<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<1, ap_bit_ref, _AP_W2, ap_range_ref<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_range_ref<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> > operator,(
+      const ap_bit_ref<_AP_W2, _AP_S2> &a2) {
+    return ap_concat_ref<1, ap_bit_ref, 1, ap_bit_ref<_AP_W2, _AP_S2> >(
+        *this, const_cast<ap_bit_ref<_AP_W2, _AP_S2>&>(a2));
+  }
+
+  template <int _AP_W2, typename _AP_T2, int _AP_W3, typename _AP_T3>
+  INLINE ap_concat_ref<1, ap_bit_ref, _AP_W2 + _AP_W3,
+                       ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >
+  operator,(const ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> &a2) {
+    return ap_concat_ref<1, ap_bit_ref, _AP_W2 + _AP_W3,
+                         ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3> >(
+        *this, const_cast<ap_concat_ref<_AP_W2, _AP_T2, _AP_W3, _AP_T3>&>(a2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<
+      1, ap_bit_ref, _AP_W2,
+      af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(
+      const af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) {
+    return ap_concat_ref<
+        1, ap_bit_ref, _AP_W2,
+        af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<
+            af_range_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(a2));
+  }
+
+  template <int _AP_W2, int _AP_I2, bool _AP_S2, ap_q_mode _AP_Q2,
+            ap_o_mode _AP_O2, int _AP_N2>
+  INLINE ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                                    _AP_Q2, _AP_O2, _AP_N2> >
+  operator,(
+      const af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2> &a2) {
+    return ap_concat_ref<1, ap_bit_ref, 1, af_bit_ref<_AP_W2, _AP_I2, _AP_S2,
+                                                      _AP_Q2, _AP_O2, _AP_N2> >(
+        *this,
+        const_cast<af_bit_ref<_AP_W2, _AP_I2, _AP_S2, _AP_Q2, _AP_O2, _AP_N2>&>(
+            a2));
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator==(const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+    return get() == op.get();
+  }
+
+  template <int _AP_W2, bool _AP_S2>
+  INLINE bool operator!=(const ap_bit_ref<_AP_W2, _AP_S2>& op) {
+    return get() != op.get();
+  }
+
+  INLINE bool get() const { return _AP_ROOT_op_get_bit(d_bv.V, d_index); }
+
+  INLINE bool get() { return _AP_ROOT_op_get_bit(d_bv.V, d_index); }
+
+  template <int _AP_W3>
+  INLINE void set(const ap_int_base<_AP_W3, false>& val) {
+    operator=(val);
+  }
+
+  INLINE bool operator~() const {
+    bool bit = _AP_ROOT_op_get_bit(d_bv.V, d_index);
+    return bit ? false : true;
+  }
+
+  INLINE int length() const { return 1; }
+
+#ifndef __SYNTHESIS__
+  std::string to_string() const { return get() ? "1" : "0"; }
+#else
+  // XXX HLS will delete this in synthesis
+  INLINE char* to_string() const { return 0; }
+#endif
+}; // struct ap_bit_ref
+
+/* ap_range_ref with int.
+ * ------------------------------------------------------------
+ */
+// equality and relational operators.
+#define REF_REL_OP_WITH_INT(REL_OP, C_TYPE, _AP_W2, _AP_S2)                \
+  template <int _AP_W, bool _AP_S>                                         \
+  INLINE bool operator REL_OP(const ap_range_ref<_AP_W, _AP_S>& op,        \
+                              C_TYPE op2) {                                \
+    return ap_int_base<_AP_W, false>(op)                                   \
+        REL_OP ap_int_base<_AP_W2, _AP_S2>(op2);                           \
+  }                                                                        \
+  template <int _AP_W, bool _AP_S>                                         \
+  INLINE bool operator REL_OP(const ap_bit_ref<_AP_W, _AP_S>& op,          \
+                              C_TYPE op2) {                                \
+    return bool(op) REL_OP op2;                                            \
+  }                                                                        \
+  template <int _AP_W, bool _AP_S>                                         \
+  INLINE bool operator REL_OP(C_TYPE op2,                                  \
+                              const ap_bit_ref<_AP_W, _AP_S>& op) {        \
+    return op2 REL_OP bool(op);                                            \
+  }                                                                        \
+  template <int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>        \
+  INLINE bool operator REL_OP(                                             \
+      const ap_concat_ref<_AP_W, _AP_T, _AP_W1, _AP_T1>& op, C_TYPE op2) { \
+    return ap_int_base<_AP_W + _AP_W1, false>(op)                          \
+        REL_OP ap_int_base<_AP_W2, _AP_S2>(op2);                           \
+  }
+
+// Make the line shorter than 5000 chars
+#define REF_REL_WITH_INT_1(C_TYPE, _AP_WI, _AP_SI) \
+  REF_REL_OP_WITH_INT(>, C_TYPE, _AP_WI, _AP_SI)   \
+  REF_REL_OP_WITH_INT(<, C_TYPE, _AP_WI, _AP_SI)   \
+  REF_REL_OP_WITH_INT(>=, C_TYPE, _AP_WI, _AP_SI)  \
+  REF_REL_OP_WITH_INT(<=, C_TYPE, _AP_WI, _AP_SI)
+
+REF_REL_WITH_INT_1(bool, 1, false)
+REF_REL_WITH_INT_1(char, 8, CHAR_IS_SIGNED)
+REF_REL_WITH_INT_1(signed char, 8, true)
+REF_REL_WITH_INT_1(unsigned char, 8, false)
+REF_REL_WITH_INT_1(short, _AP_SIZE_short, true)
+REF_REL_WITH_INT_1(unsigned short, _AP_SIZE_short, false)
+REF_REL_WITH_INT_1(int, _AP_SIZE_int, true)
+REF_REL_WITH_INT_1(unsigned int, _AP_SIZE_int, false)
+REF_REL_WITH_INT_1(long, _AP_SIZE_long, true)
+REF_REL_WITH_INT_1(unsigned long, _AP_SIZE_long, false)
+REF_REL_WITH_INT_1(ap_slong, _AP_SIZE_ap_slong, true)
+REF_REL_WITH_INT_1(ap_ulong, _AP_SIZE_ap_slong, false)
+
+// Make the line shorter than 5000 chars
+#define REF_REL_WITH_INT_2(C_TYPE, _AP_WI, _AP_SI) \
+  REF_REL_OP_WITH_INT(==, C_TYPE, _AP_WI, _AP_SI)  \
+  REF_REL_OP_WITH_INT(!=, C_TYPE, _AP_WI, _AP_SI)
+
+REF_REL_WITH_INT_2(bool, 1, false)
+REF_REL_WITH_INT_2(char, 8, CHAR_IS_SIGNED)
+REF_REL_WITH_INT_2(signed char, 8, true)
+REF_REL_WITH_INT_2(unsigned char, 8, false)
+REF_REL_WITH_INT_2(short, _AP_SIZE_short, true)
+REF_REL_WITH_INT_2(unsigned short, _AP_SIZE_short, false)
+REF_REL_WITH_INT_2(int, _AP_SIZE_int, true)
+REF_REL_WITH_INT_2(unsigned int, _AP_SIZE_int, false)
+REF_REL_WITH_INT_2(long, _AP_SIZE_long, true)
+REF_REL_WITH_INT_2(unsigned long, _AP_SIZE_long, false)
+REF_REL_WITH_INT_2(ap_slong, _AP_SIZE_ap_slong, true)
+REF_REL_WITH_INT_2(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef REF_REL_OP_WITH_INT
+#undef REF_REL_WITH_INT_1
+#undef REF_REL_WITH_INT_2
+
+#define REF_BIN_OP_WITH_INT(BIN_OP, RTYPE, C_TYPE, _AP_W2, _AP_S2)          \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE typename ap_int_base<_AP_W, false>::template RType<_AP_W2,         \
+                                                            _AP_S2>::RTYPE  \
+  operator BIN_OP(const ap_range_ref<_AP_W, _AP_S>& op, C_TYPE op2) {       \
+    return ap_int_base<_AP_W, false>(op)                                    \
+        BIN_OP ap_int_base<_AP_W2, _AP_S2>(op2);                            \
+  }                                                                         \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE typename ap_int_base<_AP_W2, _AP_S2>::template RType<_AP_W,        \
+                                                              false>::RTYPE \
+  operator BIN_OP(C_TYPE op2, const ap_range_ref<_AP_W, _AP_S>& op) {       \
+    return ap_int_base<_AP_W2, _AP_S2>(op2)                                 \
+        BIN_OP ap_int_base<_AP_W, false>(op);                               \
+  }
+
+// arithmetic operators.
+#define REF_BIN_OP_WITH_INT_ARITH(C_TYPE, _AP_W2, _AP_S2)   \
+  REF_BIN_OP_WITH_INT(+, plus, C_TYPE, (_AP_W2), (_AP_S2))  \
+  REF_BIN_OP_WITH_INT(-, minus, C_TYPE, (_AP_W2), (_AP_S2)) \
+  REF_BIN_OP_WITH_INT(*, mult, C_TYPE, (_AP_W2), (_AP_S2))  \
+  REF_BIN_OP_WITH_INT(/, div, C_TYPE, (_AP_W2), (_AP_S2))   \
+  REF_BIN_OP_WITH_INT(%, mod, C_TYPE, (_AP_W2), (_AP_S2))
+
+REF_BIN_OP_WITH_INT_ARITH(bool, 1, false)
+REF_BIN_OP_WITH_INT_ARITH(char, 8, CHAR_IS_SIGNED)
+REF_BIN_OP_WITH_INT_ARITH(signed char, 8, true)
+REF_BIN_OP_WITH_INT_ARITH(unsigned char, 8, false)
+REF_BIN_OP_WITH_INT_ARITH(short, _AP_SIZE_short, true)
+REF_BIN_OP_WITH_INT_ARITH(unsigned short, _AP_SIZE_short, false)
+REF_BIN_OP_WITH_INT_ARITH(int, _AP_SIZE_int, true)
+REF_BIN_OP_WITH_INT_ARITH(unsigned int, _AP_SIZE_int, false)
+REF_BIN_OP_WITH_INT_ARITH(long, _AP_SIZE_long, true)
+REF_BIN_OP_WITH_INT_ARITH(unsigned long, _AP_SIZE_long, false)
+REF_BIN_OP_WITH_INT_ARITH(ap_slong, _AP_SIZE_ap_slong, true)
+REF_BIN_OP_WITH_INT_ARITH(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef REF_BIN_OP_WITH_INT_ARITH
+
+// bitwise and shift operators
+#define REF_BIN_OP_WITH_INT_BITS(C_TYPE, _AP_W2, _AP_S2)     \
+  REF_BIN_OP_WITH_INT(&, logic, C_TYPE, (_AP_W2), (_AP_S2))  \
+  REF_BIN_OP_WITH_INT(|, logic, C_TYPE, (_AP_W2), (_AP_S2))  \
+  REF_BIN_OP_WITH_INT(^, logic, C_TYPE, (_AP_W2), (_AP_S2)) \
+  REF_BIN_OP_WITH_INT(>>, arg1, C_TYPE, (_AP_W2), (_AP_S2))  \
+  REF_BIN_OP_WITH_INT(<<, arg1, C_TYPE, (_AP_W2), (_AP_S2))
+
+REF_BIN_OP_WITH_INT_BITS(bool, 1, false)
+REF_BIN_OP_WITH_INT_BITS(char, 8, CHAR_IS_SIGNED)
+REF_BIN_OP_WITH_INT_BITS(signed char, 8, true)
+REF_BIN_OP_WITH_INT_BITS(unsigned char, 8, false)
+REF_BIN_OP_WITH_INT_BITS(short, _AP_SIZE_short, true)
+REF_BIN_OP_WITH_INT_BITS(unsigned short, _AP_SIZE_short, false)
+REF_BIN_OP_WITH_INT_BITS(int, _AP_SIZE_int, true)
+REF_BIN_OP_WITH_INT_BITS(unsigned int, _AP_SIZE_int, false)
+REF_BIN_OP_WITH_INT_BITS(long, _AP_SIZE_long, true)
+REF_BIN_OP_WITH_INT_BITS(unsigned long, _AP_SIZE_long, false)
+REF_BIN_OP_WITH_INT_BITS(ap_slong, _AP_SIZE_ap_slong, true)
+REF_BIN_OP_WITH_INT_BITS(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef REF_BIN_OP_WITH_INT_BITS
+
+/* ap_range_ref with ap_range_ref
+ *  ------------------------------------------------------------
+ */
+#define REF_BIN_OP(BIN_OP, RTYPE)                                              \
+  template <int _AP_W, bool _AP_S, int _AP_W2, bool _AP_S2>                    \
+  INLINE                                                                       \
+      typename ap_int_base<_AP_W, false>::template RType<_AP_W2, false>::RTYPE \
+      operator BIN_OP(const ap_range_ref<_AP_W, _AP_S>& lhs,                   \
+                      const ap_range_ref<_AP_W2, _AP_S2>& rhs) {               \
+    return (lhs.operator ap_int_base<_AP_W, false>())BIN_OP(                   \
+        rhs.operator ap_int_base<_AP_W2, false>());                            \
+  }
+
+REF_BIN_OP(+, plus)
+REF_BIN_OP(-, minus)
+REF_BIN_OP(*, mult)
+REF_BIN_OP(/, div)
+REF_BIN_OP(%, mod)
+REF_BIN_OP(&, logic)
+REF_BIN_OP(|, logic)
+REF_BIN_OP(^, logic)
+REF_BIN_OP(>>, arg1)
+REF_BIN_OP(<<, arg1)
+
+/* ap_concat_ref with ap_concat_ref.
+ *  ------------------------------------------------------------
+ */
+
+//************************************************************************
+//  Implement
+//      ap_int_base<M+N> = ap_concat_ref<M> OP ap_concat_ref<N>
+//  for operators  +, -, *, /, %, >>, <<, &, |, ^
+//  Without these operators the operands are converted to int64 and
+//  larger results lose informations (higher order bits).
+//
+//                       operand OP
+//                      /          |
+//              left-concat         right-concat
+//                /     |            /         |
+//         <LW1,LT1>  <LW2,LT2>   <RW1,RT1>    <RW2,RT2>
+//
+//      _AP_LW1, _AP_LT1 (width and type of left-concat's left side)
+//      _AP_LW2, _AP_LT2 (width and type of left-concat's right side)
+//  Similarly for RHS of operand OP: _AP_RW1, AP_RW2, _AP_RT1, _AP_RT2
+//
+//  In Verilog 2001 result of concatenation is always unsigned even
+//  when both sides are signed.
+//************************************************************************
+
+#undef SYN_CONCAT_REF_BIN_OP
+
+#define SYN_CONCAT_REF_BIN_OP(BIN_OP, RTYPE)                              \
+  template <int _AP_LW1, typename _AP_LT1, int _AP_LW2, typename _AP_LT2, \
+            int _AP_RW1, typename _AP_RT1, int _AP_RW2, typename _AP_RT2> \
+  INLINE typename ap_int_base<_AP_LW1 + _AP_LW2, false>::template RType<  \
+      _AP_RW1 + _AP_RW2, false>::RTYPE                                    \
+  operator BIN_OP(                                                        \
+      const ap_concat_ref<_AP_LW1, _AP_LT1, _AP_LW2, _AP_LT2>& lhs,       \
+      const ap_concat_ref<_AP_RW1, _AP_RT1, _AP_RW2, _AP_RT2>& rhs) {     \
+    return lhs.get() BIN_OP rhs.get();                                    \
+  }
+
+SYN_CONCAT_REF_BIN_OP(+, plus)
+SYN_CONCAT_REF_BIN_OP(-, minus)
+SYN_CONCAT_REF_BIN_OP(*, mult)
+SYN_CONCAT_REF_BIN_OP(/, div)
+SYN_CONCAT_REF_BIN_OP(%, mod)
+SYN_CONCAT_REF_BIN_OP(&, logic)
+SYN_CONCAT_REF_BIN_OP(|, logic)
+SYN_CONCAT_REF_BIN_OP(^, logic)
+SYN_CONCAT_REF_BIN_OP(>>, arg1)
+SYN_CONCAT_REF_BIN_OP(<<, arg1)
+
+#undef SYN_CONCAT_REF_BIN_OP
+
+#define CONCAT_OP_WITH_INT(C_TYPE, _AP_WI, _AP_SI)                          \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE ap_int_base<_AP_W + _AP_WI, false> operator,(                      \
+      const ap_int_base<_AP_W, _AP_S> &op1, C_TYPE op2) {                   \
+    ap_int_base<_AP_WI + _AP_W, false> val(op2);                            \
+    ap_int_base<_AP_WI + _AP_W, false> ret(op1);                            \
+    ret <<= _AP_WI;                                                         \
+    if (_AP_SI) {                                                           \
+      val <<= _AP_W;                                                        \
+      val >>= _AP_W;                                                        \
+    }                                                                       \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE ap_int_base<_AP_W + _AP_WI, false> operator,(                      \
+      C_TYPE op1, const ap_int_base<_AP_W, _AP_S> &op2) {                   \
+    ap_int_base<_AP_WI + _AP_W, false> val(op1);                            \
+    ap_int_base<_AP_WI + _AP_W, false> ret(op2);                            \
+    if (_AP_S) {                                                            \
+      ret <<= _AP_WI;                                                       \
+      ret >>= _AP_WI;                                                       \
+    }                                                                       \
+    ret |= val << _AP_W;                                                    \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE ap_int_base<_AP_W + _AP_WI, false> operator,(                      \
+      const ap_range_ref<_AP_W, _AP_S> &op1, C_TYPE op2) {                  \
+    ap_int_base<_AP_WI + _AP_W, false> val(op2);                            \
+    ap_int_base<_AP_WI + _AP_W, false> ret(op1);                            \
+    ret <<= _AP_WI;                                                         \
+    if (_AP_SI) {                                                           \
+      val <<= _AP_W;                                                        \
+      val >>= _AP_W;                                                        \
+    }                                                                       \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE ap_int_base<_AP_W + _AP_WI, false> operator,(                      \
+      C_TYPE op1, const ap_range_ref<_AP_W, _AP_S> &op2) {                  \
+    ap_int_base<_AP_WI + _AP_W, false> val(op1);                            \
+    ap_int_base<_AP_WI + _AP_W, false> ret(op2);                            \
+    int len = op2.length();                                                 \
+    val <<= len;                                                            \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE ap_int_base<_AP_WI + 1, false> operator,(                          \
+      const ap_bit_ref<_AP_W, _AP_S> &op1, C_TYPE op2) {                    \
+    ap_int_base<_AP_WI + 1, false> val(op2);                                \
+    val[_AP_WI] = op1;                                                      \
+    return val;                                                             \
+  }                                                                         \
+  template <int _AP_W, bool _AP_S>                                          \
+  INLINE ap_int_base<_AP_WI + 1, false> operator,(                          \
+      C_TYPE op1, const ap_bit_ref<_AP_W, _AP_S> &op2) {                    \
+    ap_int_base<_AP_WI + 1, false> val(op1);                                \
+    val <<= 1;                                                              \
+    val[0] = op2;                                                           \
+    return val;                                                             \
+  }                                                                         \
+  template <int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2>         \
+  INLINE ap_int_base<_AP_W + _AP_W2 + _AP_WI, false> operator,(             \
+      const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op1, C_TYPE op2) { \
+    ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op2);                  \
+    ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op1);                  \
+    if (_AP_SI) {                                                           \
+      val <<= _AP_W + _AP_W2;                                               \
+      val >>= _AP_W + _AP_W2;                                               \
+    }                                                                       \
+    ret <<= _AP_WI;                                                         \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, typename _AP_T, int _AP_W2, typename _AP_T2>         \
+  INLINE ap_int_base<_AP_W + _AP_W2 + _AP_WI, false> operator,(             \
+      C_TYPE op1, const ap_concat_ref<_AP_W, _AP_T, _AP_W2, _AP_T2> &op2) { \
+    ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> val(op1);                  \
+    ap_int_base<_AP_WI + _AP_W + _AP_W2, _AP_SI> ret(op2);                  \
+    int len = op2.length();                                                 \
+    val <<= len;                                                            \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE ap_int_base<_AP_W + _AP_WI, false> operator,(                      \
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1,    \
+      C_TYPE op2) {                                                         \
+    ap_int_base<_AP_WI + _AP_W, false> val(op2);                            \
+    ap_int_base<_AP_WI + _AP_W, false> ret(op1);                            \
+    if (_AP_SI) {                                                           \
+      val <<= _AP_W;                                                        \
+      val >>= _AP_W;                                                        \
+    }                                                                       \
+    ret <<= _AP_WI;                                                         \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE ap_int_base<_AP_W + _AP_WI, false> operator,(                      \
+      C_TYPE op1,                                                           \
+      const af_range_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) {  \
+    ap_int_base<_AP_WI + _AP_W, false> val(op1);                            \
+    ap_int_base<_AP_WI + _AP_W, false> ret(op2);                            \
+    int len = op2.length();                                                 \
+    val <<= len;                                                            \
+    ret |= val;                                                             \
+    return ret;                                                             \
+  }                                                                         \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE ap_int_base<1 + _AP_WI, false> operator,(                          \
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op1,      \
+      C_TYPE op2) {                                                         \
+    ap_int_base<_AP_WI + 1, _AP_SI> val(op2);                               \
+    val[_AP_WI] = op1;                                                      \
+    return val;                                                             \
+  }                                                                         \
+  template <int _AP_W, int _AP_I, bool _AP_S, ap_q_mode _AP_Q,              \
+            ap_o_mode _AP_O, int _AP_N>                                     \
+  INLINE ap_int_base<1 + _AP_WI, false> operator,(                          \
+      C_TYPE op1,                                                           \
+      const af_bit_ref<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N> &op2) {    \
+    ap_int_base<_AP_WI + 1, _AP_SI> val(op1);                               \
+    val <<= 1;                                                              \
+    val[0] = op2;                                                           \
+    return val;                                                             \
+  }
+
+CONCAT_OP_WITH_INT(bool, 1, false)
+CONCAT_OP_WITH_INT(char, 8, CHAR_IS_SIGNED)
+CONCAT_OP_WITH_INT(signed char, 8, true)
+CONCAT_OP_WITH_INT(unsigned char, 8, false)
+CONCAT_OP_WITH_INT(short, _AP_SIZE_short, true)
+CONCAT_OP_WITH_INT(unsigned short, _AP_SIZE_short, false)
+CONCAT_OP_WITH_INT(int, _AP_SIZE_int, true)
+CONCAT_OP_WITH_INT(unsigned int, _AP_SIZE_int, false)
+CONCAT_OP_WITH_INT(long, _AP_SIZE_long, true)
+CONCAT_OP_WITH_INT(unsigned long, _AP_SIZE_long, false)
+CONCAT_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true)
+CONCAT_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false)
+
+#undef CONCAT_OP_WITH_INT
+
+#define CONCAT_SHIFT_WITH_INT(C_TYPE, OP)                                  \
+  template <int _AP_W, typename _AP_T, int _AP_W1, typename _AP_T1>        \
+  INLINE ap_uint<_AP_W + _AP_W1> operator OP(                              \
+      const ap_concat_ref<_AP_W, _AP_T, _AP_W1, _AP_T1> lhs, C_TYPE rhs) { \
+    return ap_uint<_AP_W + _AP_W1>(lhs).get() OP int(rhs);                 \
+  }
+
+// FIXME int(rhs) may loose precision.
+
+CONCAT_SHIFT_WITH_INT(int, <<)
+CONCAT_SHIFT_WITH_INT(unsigned int, <<)
+CONCAT_SHIFT_WITH_INT(long, <<)
+CONCAT_SHIFT_WITH_INT(unsigned long, <<)
+CONCAT_SHIFT_WITH_INT(ap_slong, <<)
+CONCAT_SHIFT_WITH_INT(ap_ulong, <<)
+
+CONCAT_SHIFT_WITH_INT(int, >>)
+CONCAT_SHIFT_WITH_INT(unsigned int, >>)
+CONCAT_SHIFT_WITH_INT(long, >>)
+CONCAT_SHIFT_WITH_INT(unsigned long, >>)
+CONCAT_SHIFT_WITH_INT(ap_slong, >>)
+CONCAT_SHIFT_WITH_INT(ap_ulong, >>)
+
+#endif // ifndef __cplusplus
+#endif // ifndef __AP_INT_REF_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_int_special.h

@@ -0,0 +1,223 @@
+/*
+ * Copyright 2011-2019 Xilinx, Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AP_INT_SPECIAL_H__
+#define __AP_INT_SPECIAL_H__
+
+#ifndef __AP_INT_H__
+#error "Only ap_fixed.h and ap_int.h can be included directly in user code."
+#endif
+
+#ifndef __SYNTHESIS__
+#include <cstdio>
+#include <cstdlib>
+#endif
+// FIXME AP_AUTOCC cannot handle many standard headers, so declare instead of
+// include.
+// #include <complex>
+namespace std {
+template<typename _Tp> class complex;
+}
+
+/*
+  TODO: Modernize the code using C++11/C++14
+  1. constexpr http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0415r0.html
+  2. move constructor
+*/
+
+namespace std {
+/*
+   Specialize std::complex<ap_int> to zero initialization ap_int.
+
+   To reduce the area cost, ap_int is not zero initialized, just like basic
+   types float or double. However, libstdc++ provides specialization for float,
+   double and long double, initializing image part to 0 when not specified.
+
+   This has become a difficulty in switching legacy code from these C types to
+   ap_int. To ease the tranform of legacy code, we have to implement
+   specialization of std::complex<> for our type.
+
+   As ap_int is a template, it is impossible to specialize only the methods
+   that causes default initialization of value type in std::complex<>. An
+   explicit full specialization of the template class has to be done, covering
+   all the member functions and operators of std::complex<> as specified
+   in standard 26.2.4 and 26.2.5.
+*/
+template <int _AP_W>
+class complex<ap_int<_AP_W> > {
+ public:
+  typedef ap_int<_AP_W> _Tp;
+  typedef _Tp value_type;
+
+  // 26.2.4/1
+  // Constructor without argument
+  // Default initialize, so that in dataflow, the variable is only written once.
+  complex() : _M_real(_Tp()), _M_imag(_Tp()) {}
+  // Constructor with ap_int.
+  // Zero initialize image part when not specified, so that `C(1) == C(1,0)`
+  complex(const _Tp &__r, const _Tp &__i = _Tp(0))
+      : _M_real(__r), _M_imag(__i) {}
+
+  // Constructor with another complex number
+  template <typename _Up>
+  complex(const complex<_Up> &__z) : _M_real(__z.real()), _M_imag(__z.imag()) {}
+
+#if __cplusplus >= 201103L
+  const _Tp& real() const { return _M_real; }
+  const _Tp& imag() const { return _M_imag; }
+#else
+  _Tp& real() { return _M_real; }
+  const _Tp& real() const { return _M_real; }
+  _Tp& imag() { return _M_imag; }
+  const _Tp& imag() const { return _M_imag; }
+#endif
+
+  void real(_Tp __val) { _M_real = __val; }
+
+  void imag(_Tp __val) { _M_imag = __val; }
+
+  // Assign this complex number with ap_int.
+  // Zero initialize image poarrt, so that `C c; c = 1; c == C(1,0);`
+  complex<_Tp> &operator=(const _Tp __t) {
+    _M_real = __t;
+    _M_imag = _Tp(0);
+    return *this;
+  }
+
+  // 26.2.5/1
+  // Add ap_int to this complex number.
+  complex<_Tp> &operator+=(const _Tp &__t) {
+    _M_real += __t;
+    return *this;
+  }
+
+  // 26.2.5/3
+  // Subtract ap_int from this complex number.
+  complex<_Tp> &operator-=(const _Tp &__t) {
+    _M_real -= __t;
+    return *this;
+  }
+
+  // 26.2.5/5
+  // Multiply this complex number by ap_int.
+  complex<_Tp> &operator*=(const _Tp &__t) {
+    _M_real *= __t;
+    _M_imag *= __t;
+    return *this;
+  }
+
+  // 26.2.5/7
+  // Divide this complex number by ap_int.
+  complex<_Tp> &operator/=(const _Tp &__t) {
+    _M_real /= __t;
+    _M_imag /= __t;
+    return *this;
+  }
+
+  // Assign complex number to this complex number.
+  template <typename _Up>
+  complex<_Tp> &operator=(const complex<_Up> &__z) {
+    _M_real = __z.real();
+    _M_imag = __z.imag();
+    return *this;
+  }
+
+  // 26.2.5/9
+  // Add complex number to this.
+  template <typename _Up>
+  complex<_Tp> &operator+=(const complex<_Up> &__z) {
+    _M_real += __z.real();
+    _M_imag += __z.imag();
+    return *this;
+  }
+
+  // 26.2.5/11
+  // Subtract complex number from this.
+  template <typename _Up>
+  complex<_Tp> &operator-=(const complex<_Up> &__z) {
+    _M_real -= __z.real();
+    _M_imag -= __z.imag();
+    return *this;
+  }
+
+  // 26.2.5/13
+  // Multiply this by complex number.
+  template <typename _Up>
+  complex<_Tp> &operator*=(const complex<_Up> &__z) {
+    const _Tp __r = _M_real * __z.real() - _M_imag * __z.imag();
+    _M_imag = _M_real * __z.imag() + _M_imag * __z.real();
+    _M_real = __r;
+    return *this;
+  }
+
+  // 26.2.5/15
+  // Divide this by complex number.
+  template <typename _Up>
+  complex<_Tp> &operator/=(const complex<_Up> &__z) {
+    complex<_Tp> cj (__z.real(), -__z.imag());
+    complex<_Tp> a = (*this) * cj;
+    complex<_Tp> b = cj * __z;
+    _M_real = a.real() / b.real();
+    _M_imag = a.imag() / b.real();
+    return *this;
+  }
+
+ private:
+  _Tp _M_real;
+  _Tp _M_imag;
+
+}; // class complex<ap_int<_AP_W> >
+
+
+/*
+   Non-member operations
+   These operations are not required by standard in 26.2.6, but libstdc++
+   defines them for
+   float, double or long double's specialization.
+*/
+// Compare complex number with ap_int.
+template <int _AP_W>
+inline bool operator==(const complex<ap_int<_AP_W> > &__x, const ap_int<_AP_W> &__y) {
+  return __x.real() == __y &&
+         __x.imag() == 0;
+}
+
+// Compare ap_int with complex number.
+template <int _AP_W>
+inline bool operator==(const ap_int<_AP_W> &__x, const complex<ap_int<_AP_W> > &__y) {
+  return __x == __y.real() &&
+         0 == __y.imag();
+}
+
+// Compare complex number with ap_int.
+template <int _AP_W>
+inline bool operator!=(const complex<ap_int<_AP_W> > &__x, const ap_int<_AP_W> &__y) {
+  return __x.real() != __y ||
+         __x.imag() != 0;
+}
+
+// Compare ap_int with complex number.
+template <int _AP_W>
+inline bool operator!=(const ap_int<_AP_W> &__x, const complex<ap_int<_AP_W> > &__y) {
+  return __x != __y.real() ||
+         0 != __y.imag();
+}
+
+}  // namespace std
+
+#endif  // ifndef __AP_INT_SPECIAL_H__
+
+// -*- cpp -*-

firmware/ap_types/ap_shift_reg.h

@@ -0,0 +1,138 @@
+/*
+#-  (c) Copyright 2011-2019 Xilinx, Inc. All rights reserved.
+#-
+#-  This file contains confidential and proprietary information
+#-  of Xilinx, Inc. and is protected under U.S. and
+#-  international copyright and other intellectual property
+#-  laws.
+#-
+#-  DISCLAIMER
+#-  This disclaimer is not a license and does not grant any
+#-  rights to the materials distributed herewith. Except as
+#-  otherwise provided in a valid license issued to you by
+#-  Xilinx, and to the maximum extent permitted by applicable
+#-  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+#-  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+#-  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+#-  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+#-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+#-  (2) Xilinx shall not be liable (whether in contract or tort,
+#-  including negligence, or under any other theory of
+#-  liability) for any loss or damage of any kind or nature
+#-  related to, arising under or in connection with these
+#-  materials, including for any direct, or any indirect,
+#-  special, incidental, or consequential loss or damage
+#-  (including loss of data, profits, goodwill, or any type of
+#-  loss or damage suffered as a result of any action brought
+#-  by a third party) even if such damage or loss was
+#-  reasonably foreseeable or Xilinx had been advised of the
+#-  possibility of the same.
+#-
+#-  CRITICAL APPLICATIONS
+#-  Xilinx products are not designed or intended to be fail-
+#-  safe, or for use in any application requiring fail-safe
+#-  performance, such as life-support or safety devices or
+#-  systems, Class III medical devices, nuclear facilities,
+#-  applications related to the deployment of airbags, or any
+#-  other applications that could lead to death, personal
+#-  injury, or severe property or environmental damage
+#-  (individually and collectively, "Critical
+#-  Applications"). Customer assumes the sole risk and
+#-  liability of any use of Xilinx products in Critical
+#-  Applications, subject only to applicable laws and
+#-  regulations governing limitations on product liability.
+#-
+#-  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+#-  PART OF THIS FILE AT ALL TIMES. 
+#- ************************************************************************
+
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+*/
+
+#ifndef __SIM_AP_SHIFT_REG_H__
+#define __SIM_AP_SHIFT_REG_H__
+
+
+/*
+ * This file contains a C++ model of shift register.
+ * It defines C level simulation model.
+ */
+#ifndef __cplusplus
+#error C++ is required to include this header file
+#else
+
+#include <cassert>
+
+//////////////////////////////////////////////
+// C level simulation model for ap_shift_reg
+//////////////////////////////////////////////
+template<typename __SHIFT_T__, unsigned int __SHIFT_DEPTH__ = 32>
+class ap_shift_reg
+{
+  public:
+    /// Constructors
+    ap_shift_reg() { }
+    ap_shift_reg(const char* name) { }
+    /// Destructor
+    virtual ~ap_shift_reg() { }
+
+  private:
+    /// Make copy constructor and assignment operator private
+    ap_shift_reg(const ap_shift_reg< __SHIFT_T__, __SHIFT_DEPTH__ >& shreg)
+    {
+        for (unsigned i = 0; i < __SHIFT_DEPTH__; ++i)
+            Array[i] = shreg.Array[i];
+    }
+
+    ap_shift_reg& operator = (const ap_shift_reg< __SHIFT_T__,
+        __SHIFT_DEPTH__ >& shreg)
+    {
+        for (unsigned i = 0; i < __SHIFT_DEPTH__; ++i)
+            Array[i] = shreg.Array[i];
+        return *this;
+    }
+
+  public:
+    // Shift the queue, push to back and read from a given address.
+    __SHIFT_T__ shift(__SHIFT_T__ DataIn,
+        unsigned int Addr = __SHIFT_DEPTH__ - 1, bool Enable = true)
+    {
+        assert(Addr < __SHIFT_DEPTH__ &&
+            "Out-of-bound shift is found in ap_shift_reg.");
+        __SHIFT_T__ ret = Array[Addr];
+        if (Enable) {
+            for (unsigned int i = __SHIFT_DEPTH__ - 1; i > 0; --i)
+                Array[i] = Array[i-1];
+            Array[0] = DataIn;
+        }
+        return ret;
+    }
+
+    // Read from a given address.
+    __SHIFT_T__ read(unsigned int Addr = __SHIFT_DEPTH__ - 1) const
+    {
+        assert(Addr < __SHIFT_DEPTH__ &&
+            "Out-of-bound read is found in ap_shift_reg.");
+        return Array[Addr];
+    }
+
+  protected:
+    __SHIFT_T__ Array[__SHIFT_DEPTH__];
+};
+
+#endif //__cplusplus
+
+#endif //__SIM_AP_SHIFT_REG_H__
+
+

firmware/ap_types/hls_math.h

@@ -0,0 +1,27 @@
+#ifndef X_HLS_MATH_H
+#define X_HLS_MATH_H
+
+#include <cmath>
+#include "ap_fixed.h"
+
+namespace hls {
+
+template<class T>
+static T exp(const T x) {
+  return (T) std::exp(x.to_double());
+}
+
+template <typename T> T sin(T x) { return (T) std::sin(x.to_double()); };
+
+template <typename T> T cos(T x) { return (T) std::cos(x.to_double()); };
+
+template <typename T> T asin(T x) { return (T) std::asin(x.to_double()); };
+
+template <typename T> T acos(T x) { return (T) std::acos(x.to_double()); };
+
+template <typename T> T atan(T x) { return (T) std::atan(x.to_double()); };
+
+template <typename T> T atan2(T x, T y) { return (T) hls::atan2(x.to_double(), y.to_double()); };
+
+}
+#endif

firmware/ap_types/hls_stream.h

@@ -0,0 +1,263 @@
+/*
+#-  (c) Copyright 2011-2018 Xilinx, Inc. All rights reserved.
+#-
+#-  This file contains confidential and proprietary information
+#-  of Xilinx, Inc. and is protected under U.S. and
+#-  international copyright and other intellectual property
+#-  laws.
+#-
+#-  DISCLAIMER
+#-  This disclaimer is not a license and does not grant any
+#-  rights to the materials distributed herewith. Except as
+#-  otherwise provided in a valid license issued to you by
+#-  Xilinx, and to the maximum extent permitted by applicable
+#-  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+#-  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+#-  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+#-  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+#-  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+#-  (2) Xilinx shall not be liable (whether in contract or tort,
+#-  including negligence, or under any other theory of
+#-  liability) for any loss or damage of any kind or nature
+#-  related to, arising under or in connection with these
+#-  materials, including for any direct, or any indirect,
+#-  special, incidental, or consequential loss or damage
+#-  (including loss of data, profits, goodwill, or any type of
+#-  loss or damage suffered as a result of any action brought
+#-  by a third party) even if such damage or loss was
+#-  reasonably foreseeable or Xilinx had been advised of the
+#-  possibility of the same.
+#-
+#-  CRITICAL APPLICATIONS
+#-  Xilinx products are not designed or intended to be fail-
+#-  safe, or for use in any application requiring fail-safe
+#-  performance, such as life-support or safety devices or
+#-  systems, Class III medical devices, nuclear facilities,
+#-  applications related to the deployment of airbags, or any
+#-  other applications that could lead to death, personal
+#-  injury, or severe property or environmental damage
+#-  (individually and collectively, "Critical
+#-  Applications"). Customer assumes the sole risk and
+#-  liability of any use of Xilinx products in Critical
+#-  Applications, subject only to applicable laws and
+#-  regulations governing limitations on product liability.
+#-
+#-  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+#-  PART OF THIS FILE AT ALL TIMES. 
+#- ************************************************************************
+
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+*/
+
+#ifndef X_HLS_STREAM_SIM_H
+#define X_HLS_STREAM_SIM_H
+
+/*
+ * This file contains a C++ model of hls::stream.
+ * It defines C simulation model.
+ */
+#ifndef __cplusplus
+
+#error C++ is required to include this header file
+
+#else
+
+//////////////////////////////////////////////
+// C level simulation models for hls::stream
+//////////////////////////////////////////////
+#include <queue>
+#include <iostream>
+#include <typeinfo>
+#include <string>
+#include <sstream>
+
+#ifdef HLS_STREAM_THREAD_SAFE
+#include <mutex>
+#include <condition_variable>
+#endif
+
+#ifndef _MSC_VER
+#include <cxxabi.h>
+#include <stdlib.h>
+#endif
+
+namespace hls {
+
+template<typename __STREAM_T__>
+class stream
+{
+  protected:
+    std::string _name;
+    std::deque<__STREAM_T__> _data; // container for the elements
+#ifdef HLS_STREAM_THREAD_SAFE
+    std::mutex _mutex;
+    std::condition_variable _condition_var;
+#endif    
+
+  public:
+    /// Constructors
+    // Keep consistent with the synthesis model's constructors
+    stream() {
+        static unsigned _counter = 1;
+        std::stringstream ss;
+#ifndef _MSC_VER
+        char* _demangle_name = abi::__cxa_demangle(typeid(*this).name(), 0, 0, 0);
+        if (_demangle_name) {
+            _name = _demangle_name;
+            free(_demangle_name);
+        }
+        else {
+            _name = "hls_stream";
+        }
+#else
+        _name = typeid(*this).name();
+#endif
+
+        ss << _counter++;
+        _name += "." + ss.str();
+    }
+
+    stream(const std::string name) {
+    // default constructor,
+    // capacity set to predefined maximum
+        _name = name;
+    }
+
+  /// Make copy constructor and assignment operator private
+  private:
+    stream(const stream< __STREAM_T__ >& chn):
+        _name(chn._name), _data(chn._data) {
+    }
+
+    stream& operator = (const stream< __STREAM_T__ >& chn) {
+        _name = chn._name;
+        _data = chn._data;
+        return *this;
+    }
+
+  public:
+    /// Overload >> and << operators to implement read() and write()
+    void operator >> (__STREAM_T__& rdata) {
+        read(rdata);
+    }
+
+    void operator << (const __STREAM_T__& wdata) {
+        write(wdata);
+    }
+
+
+  public:
+    /// Destructor
+    /// Check status of the queue
+    virtual ~stream() {
+        if (!_data.empty())
+        {
+            std::cout << "WARNING: Hls::stream '" 
+                      << _name 
+                      << "' contains leftover data,"
+                      << " which may result in RTL simulation hanging."
+                      << std::endl;
+        }
+    }
+
+    /// Status of the queue
+    bool empty() {
+#ifdef HLS_STREAM_THREAD_SAFE
+        std::lock_guard<std::mutex> lg(_mutex);
+#endif
+        return _data.empty();
+    }    
+
+    bool full() const { return false; }
+
+    /// Blocking read
+    void read(__STREAM_T__& head) {
+        head = read();
+    }
+
+#ifdef HLS_STREAM_THREAD_SAFE
+    __STREAM_T__ read() {
+        std::unique_lock<std::mutex> ul(_mutex);
+        while (_data.empty()) {
+            _condition_var.wait(ul);
+        }
+
+        __STREAM_T__ elem;
+        elem = _data.front();
+        _data.pop_front();
+        return elem;
+    }
+#else
+    __STREAM_T__ read() {
+        __STREAM_T__ elem;
+        if (_data.empty()) {
+            std::cout << "WARNING: Hls::stream '"
+                      << _name 
+                      << "' is read while empty,"
+                      << " which may result in RTL simulation hanging."
+                      << std::endl;
+            elem = __STREAM_T__();
+        } else {
+            elem = _data.front();
+            _data.pop_front();
+        }
+        return elem;
+    }
+#endif
+
+    /// Blocking write
+    void write(const __STREAM_T__& tail) { 
+#ifdef HLS_STREAM_THREAD_SAFE
+        std::unique_lock<std::mutex> ul(_mutex);
+#endif
+        _data.push_back(tail);
+#ifdef HLS_STREAM_THREAD_SAFE
+        _condition_var.notify_one();
+#endif
+    }
+
+    /// Nonblocking read
+    bool read_nb(__STREAM_T__& head) {
+#ifdef HLS_STREAM_THREAD_SAFE
+        std::lock_guard<std::mutex> lg(_mutex);
+#endif    
+        bool is_empty = _data.empty();
+        if (is_empty) {
+            head = __STREAM_T__();
+        } else {
+            __STREAM_T__ elem(_data.front());
+            _data.pop_front();
+            head = elem;
+        }
+        return !is_empty;
+    }
+
+    /// Nonblocking write
+    bool write_nb(const __STREAM_T__& tail) {
+        bool is_full = full();
+        write(tail);
+        return !is_full;
+    }
+
+    /// Fifo size
+    size_t size() {
+        return _data.size();
+    }
+};
+
+} // namespace hls
+
+#endif // __cplusplus
+#endif  // X_HLS_STREAM_SIM_H
+

firmware/ap_types/utils/x_hls_utils.h

@@ -0,0 +1,80 @@
+#ifndef X_HLS_UTILS_H
+#define X_HLS_UTILS_H
+#include "ap_fixed.h"
+#include <limits>
+
+namespace hls {
+
+    template<typename T>
+    class numeric_limits {
+    public:
+        static T max()     { return std::numeric_limits<T>::max(); }
+        static T min()     { return std::numeric_limits<T>::min(); }
+        static T epsilon() { return std::numeric_limits<T>::epsilon(); }
+    };
+
+    template <int W, int I, ap_q_mode Q, ap_o_mode O>
+    class numeric_limits<ap_fixed<W,I,Q,O> > {
+    public:
+        static ap_fixed<W,I,Q,O> max() {
+            ap_int<W> m = ::hls::numeric_limits<ap_int<W> >::max();
+            ap_fixed<W,I,Q,O> x;
+            x(W-1,0) = m(W-1,0);
+            return x;
+        }
+        static ap_fixed<W,I,Q,O> min() {
+            ap_int<W> m = ::hls::numeric_limits<ap_int<W> >::min();
+            ap_fixed<W,I,Q,O> x;
+            x(W-1,0) = m(W-1,0);
+            return x;
+        }
+        static ap_fixed<W,I,Q,O> epsilon() {
+          ap_fixed<W,I,Q,O> x = 0;
+          x[0] = 1;
+          return x;
+        }
+    };
+
+    template <int W, int I, ap_q_mode Q, ap_o_mode O>
+    class numeric_limits<ap_ufixed<W,I,Q,O> > {
+    public:
+        static ap_ufixed<W,I,Q,O> max() {
+            ap_uint<W> m = ::hls::numeric_limits<ap_uint<W> >::max();
+            ap_ufixed<W,I,Q,O> x;
+            x(W-1,0) = m(W-1,0);
+            return x;
+        }
+        static ap_ufixed<W,I,Q,O> min() { return 0; }
+        static ap_ufixed<W,I,Q,O> epsilon() {
+          ap_ufixed<W,I,Q,O> x = 0;
+          x[0] = 1;
+          return x;
+        }
+    };
+
+    template <int W>
+    class numeric_limits<ap_int<W> > {
+    public:
+        static ap_int<W> max() { ap_int<W> m = min(); return ~m; }
+        static ap_int<W> min() { ap_int<W> m = 0; m[W-1] = 1; return m; }
+        static ap_int<W> epsilon() {
+          ap_int<W> x = 0;
+          x[0] = 1;
+          return x;
+        }
+    };
+
+    template <int W>
+    class numeric_limits<ap_uint<W> > {
+    public:
+        static ap_uint<W> max() { ap_uint<W> zero = 0; return ~zero; }
+        static ap_uint<W> min() { return 0; }
+        static ap_uint<W> epsilon() {
+          ap_uint<W> x = 0;
+          x[0] = 1;
+          return x;
+        }
+    };
+}
+
+#endif

firmware/nnet_utils/nnet_code_gen.h

@@ -0,0 +1,28 @@
+#ifndef NNET_INSTR_GEN_H_
+#define NNET_INSTR_GEN_H_
+
+#include "nnet_conv1d_latency.h"
+#include "nnet_helpers.h"
+
+#include "hls_stream.h"
+#include "nnet_common.h"
+#include "nnet_function_stubs.h"
+#include "nnet_mult.h"
+
+namespace nnet {
+
+template <class data_T, class res_T, typename CONFIG_T> class PointwiseConv1D {
+  public:
+    static void pointwise_conv(data_T data[CONFIG_T::in_width * CONFIG_T::n_chan],
+                               res_T res[CONFIG_T::out_width * CONFIG_T::n_filt],
+                               typename CONFIG_T::weight_t weights[CONFIG_T::n_chan * CONFIG_T::n_filt],
+                               typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) {
+        // To be implemented in subclasses
+    }
+};
+
+// hls4ml insert code
+
+} // namespace nnet
+
+#endif

firmware/nnet_utils/nnet_conv1d_stream.h

@@ -0,0 +1,37 @@
+#ifndef NNET_CONV1D_STREAM_H_
+#define NNET_CONV1D_STREAM_H_
+
+#include "hls_stream.h"
+#include "nnet_common.h"
+#include "nnet_conv_stream.h"
+#include <cassert>
+
+namespace nnet {
+
+template <class data_T, class res_T, typename CONFIG_T>
+void conv_1d_cl(hls::stream<data_T> &data, hls::stream<res_T> &res,
+                typename CONFIG_T::weight_t weights[CONFIG_T::filt_width * CONFIG_T::n_chan * CONFIG_T::n_filt],
+                typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) {
+    assert(CONFIG_T::implementation == conv_implementation::linebuffer &&
+           "Only \"linebuffer\" implementation is supported in Vitis HLS.");
+
+    assert(CONFIG_T::pad_left == 0 && CONFIG_T::pad_right == 0);
+
+    if (CONFIG_T::strategy == nnet::latency || CONFIG_T::strategy == nnet::distributed_arithmetic) {
+    ReadInputWidth:
+        for (unsigned i_iw = 0; i_iw < CONFIG_T::in_width; i_iw++) {
+            #pragma HLS PIPELINE II=CONFIG_T::reuse_factor
+            compute_output_buffer_1d<data_T, res_T, CONFIG_T>(data.read(), res, weights, biases);
+        }
+    } else if (CONFIG_T::strategy == nnet::resource || CONFIG_T::strategy == nnet::resource_unrolled) {
+    ReadInputWidthSerial:
+        for (unsigned i_iw = 0; i_iw < CONFIG_T::in_width; i_iw++) {
+            compute_output_buffer_1d<data_T, res_T, CONFIG_T>(data.read(), res, weights, biases);
+        }
+    } else {
+        assert(false && "Unsupported strategy for conv_1d_cl");
+    }
+}
+
+} // namespace nnet
+#endif

firmware/nnet_utils/nnet_conv2d_latency.h

@@ -0,0 +1,90 @@
+#ifndef NNET_CONV2D_LATENCY_H_
+#define NNET_CONV2D_LATENCY_H_
+
+#include "nnet_common.h"
+#include "nnet_mult.h"
+#include <cstdlib>
+
+namespace nnet {
+
+template <class data_T, class res_T, typename CONFIG_T>
+void conv_2d_latency_cl(
+    data_T data[CONFIG_T::in_height * CONFIG_T::in_width * CONFIG_T::n_chan],
+    res_T res[CONFIG_T::out_height * CONFIG_T::out_width * CONFIG_T::n_filt],
+    typename CONFIG_T::weight_t weights[CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan * CONFIG_T::n_filt],
+    typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) {
+    constexpr unsigned mult_n_in = CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan;
+    constexpr unsigned mult_n_out = CONFIG_T::n_filt;
+
+    data_T data_buf[CONFIG_T::n_pixels][mult_n_in];
+    #pragma HLS ARRAY_PARTITION variable=data_buf complete dim=0
+
+    typename CONFIG_T::accum_t mult[mult_n_in * mult_n_out];
+    #pragma HLS ARRAY_PARTITION variable=mult complete
+
+    typename CONFIG_T::accum_t acc[mult_n_out];
+    #pragma HLS ARRAY_PARTITION variable=acc complete
+
+    #pragma HLS ARRAY_PARTITION variable=weights complete
+    #pragma HLS ARRAY_PARTITION variable=biases complete
+
+    // Limit multipliers to control parallelization
+    #pragma HLS ALLOCATION operation instances=mul limit=CONFIG_T::mult_config::multiplier_limit
+
+PartitionLoop:
+    for (int i_part = 0; i_part < CONFIG_T::n_partitions; i_part++) {
+        #pragma HLS PIPELINE II=CONFIG_T::reuse_factor rewind
+
+        CONFIG_T::template fill_buffer<data_T, CONFIG_T>::fill_buffer(data, data_buf, i_part);
+
+    PixelLoop:
+        for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) {
+            #pragma HLS UNROLL
+
+            data_T cache;
+
+        // Do the matrix-multiply
+        Product1:
+            for (int i_in = 0; i_in < mult_n_in; i_in++) {
+                #pragma HLS UNROLL
+                cache = data_buf[i_pxl][i_in];
+            Product2:
+                for (int i_out = 0; i_out < mult_n_out; i_out++) {
+                    #pragma HLS UNROLL
+                    mult[i_in * mult_n_out + i_out] =
+                        CONFIG_T::mult_config::template product<data_T, typename CONFIG_T::mult_config::weight_t>::product(
+                            cache, weights[i_in * mult_n_out + i_out]);
+                }
+            }
+
+        // Initialize accumulator with input biases
+        ResetAccum:
+            for (int i_acc = 0; i_acc < mult_n_out; i_acc++) {
+                #pragma HLS UNROLL
+                acc[i_acc] = (typename CONFIG_T::accum_t)biases[i_acc];
+            }
+
+        // Accumulate multiplication result
+        Accum1:
+            for (int i_in = 0; i_in < mult_n_in; i_in++) {
+                #pragma HLS UNROLL
+            Accum2:
+                for (int i_out = 0; i_out < mult_n_out; i_out++) {
+                    #pragma HLS UNROLL
+                    acc[i_out] += mult[i_in * mult_n_out + i_out];
+                }
+            }
+
+        // Cast to "res_t" type
+        Result:
+            for (int i_res = 0; i_res < mult_n_out; i_res++) {
+                #pragma HLS UNROLL
+                res[i_part * CONFIG_T::n_pixels * mult_n_out + i_pxl * mult_n_out + i_res] =
+                    cast<data_T, res_T, typename CONFIG_T::mult_config>(acc[i_res]);
+            }
+        }
+    }
+}
+
+} // namespace nnet
+#endif

firmware/nnet_utils/nnet_conv2d_resource.h

@@ -0,0 +1,108 @@
+#ifndef NNET_CONV2D_RESOURCE_H_
+#define NNET_CONV2D_RESOURCE_H_
+
+#include "nnet_common.h"
+#include "nnet_dense.h"
+
+namespace nnet {
+
+template <class data_T, class res_T, typename CONFIG_T>
+void conv_2d_resource_cl(
+    data_T data[CONFIG_T::in_height * CONFIG_T::in_width * CONFIG_T::n_chan],
+    res_T res[CONFIG_T::out_height * CONFIG_T::out_width * CONFIG_T::n_filt],
+    typename CONFIG_T::weight_t weights[CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan * CONFIG_T::n_filt],
+    typename CONFIG_T::bias_t biases[CONFIG_T::n_filt]) {
+    constexpr unsigned mult_n_in = CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan;
+    constexpr unsigned mult_n_out = CONFIG_T::n_filt;
+    constexpr unsigned block_factor = DIV_ROUNDUP(mult_n_in * mult_n_out, CONFIG_T::reuse_factor);
+
+    constexpr unsigned multiplier_limit = DIV_ROUNDUP(mult_n_in * mult_n_out, CONFIG_T::reuse_factor);
+    constexpr unsigned multscale = multiplier_limit / mult_n_out;
+
+    assert((multiplier_limit % mult_n_out == 0 || CONFIG_T::reuse_factor >= mult_n_in) &&
+           "The current Reuse Factor is not allowed");
+    assert((multiplier_limit == block_factor) &&
+           "This function is correct only for RF <= FILT_HEIGHT * FILT_WIDTH * N_CHAN");
+
+    // Treating weights as 2d is required to make sure Vitis doesn't use urem cores to calculate indices.
+    // Also, we don't apply ARRAY_RESHAPE pragma as Vitis figures this out on its own.
+    typename CONFIG_T::weight_t(*weights_2d)[CONFIG_T::reuse_factor] =
+        (typename CONFIG_T::weight_t(*)[CONFIG_T::reuse_factor])weights;
+
+    data_T data_buf[CONFIG_T::n_pixels][mult_n_in];
+    #pragma HLS ARRAY_PARTITION variable=data_buf complete dim=0
+
+    #pragma HLS ARRAY_PARTITION variable=biases complete
+
+    typename CONFIG_T::accum_t acc[CONFIG_T::n_pixels][mult_n_out];
+    #pragma HLS ARRAY_PARTITION variable=acc complete dim=0
+
+PartitionLoop:
+    for (unsigned i_part = 0; i_part < CONFIG_T::n_partitions; i_part++) {
+        //#pragma HLS UNROLL // We don't want this loop unrolled
+
+        CONFIG_T::template fill_buffer<data_T, CONFIG_T>::fill_buffer(data, data_buf, i_part);
+
+    PixelInitAccumLoop:
+        for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) {
+            #pragma HLS UNROLL
+
+        InitAccumLoop:
+            for (unsigned i_acc = 0; i_acc < mult_n_out; i_acc++) {
+                #pragma HLS UNROLL
+                acc[i_pxl][i_acc] = (typename CONFIG_T::accum_t)biases[i_acc];
+            }
+        }
+
+    ReuseLoop:
+        for (unsigned i_rf = 0; i_rf < CONFIG_T::reuse_factor; i_rf++) {
+            #pragma HLS PIPELINE II=1 rewind
+
+            unsigned i_in = i_rf;
+            unsigned i_out = 0;
+            unsigned i_acc = 0;
+
+        MultLoop:
+            for (unsigned i_blk = 0; i_blk < block_factor; i_blk++) {
+                #pragma HLS UNROLL
+
+            PixelMultLoop:
+                for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) {
+                    #pragma HLS UNROLL
+
+                    acc[i_pxl][i_out] += static_cast<typename CONFIG_T::accum_t>(
+                        CONFIG_T::mult_config::template product<data_T, typename CONFIG_T::mult_config::weight_t>::product(
+                            data_buf[i_pxl][i_in], weights_2d[i_blk][i_rf]));
+                }
+
+                // Increment i_in
+                i_in += CONFIG_T::reuse_factor;
+                if (i_in >= mult_n_in) {
+                    i_in = i_rf;
+                }
+                // Increment i_out
+                if (i_acc + 1 >= multscale) {
+                    i_acc = 0;
+                    i_out++;
+                } else {
+                    i_acc++;
+                }
+            }
+        }
+
+    PixelResultLoop:
+        for (unsigned i_pxl = 0; i_pxl < CONFIG_T::n_pixels; i_pxl++) {
+        #pragma HLS UNROLL
+        // Cast to "res_t" type
+        ResultLoop:
+            for (unsigned i_res = 0; i_res < mult_n_out; i_res++) {
+                #pragma HLS UNROLL
+                res[i_part * CONFIG_T::n_pixels * mult_n_out + i_pxl * mult_n_out + i_res] =
+                    cast<data_T, res_T, typename CONFIG_T::mult_config>(acc[i_pxl][i_res]);
+            }
+        }
+    }
+}
+
+} // namespace nnet
+#endif

firmware/nnet_utils/nnet_embed_stream.h

@@ -0,0 +1,33 @@
+#ifndef NNET_EMBED_STREAM_H_
+#define NNET_EMBED_STREAM_H_
+
+#include "hls_stream.h"
+#include "nnet_common.h"
+#include "nnet_helpers.h"
+
+namespace nnet {
+
+template <class data_T, class res_T, typename CONFIG_T>
+void embedding(hls::stream<data_T> &data, hls::stream<res_T> &res,
+               typename CONFIG_T::embeddings_t embeddings[CONFIG_T::vocab_size * CONFIG_T::n_out]) {
+    data_T in_data = data.read();
+
+InputSequence:
+    for (int j = 0; j < data_T::size; j++) {
+        #pragma HLS PIPELINE II=CONFIG_T::reuse_factor
+
+        res_T res_pack;
+        PRAGMA_DATA_PACK(res_pack)
+
+    DenseEmbedding:
+        for (int i = 0; i < CONFIG_T::n_out; i++) {
+            #pragma HLS UNROLL
+            res_pack[i] = embeddings[in_data[j] * CONFIG_T::n_out + i];
+        }
+        res.write(res_pack);
+    }
+}
+
+} // namespace nnet
+
+#endif

firmware/nnet_utils/nnet_helpers.h

@@ -0,0 +1,382 @@
+#ifndef NNET_HELPERS_H
+#define NNET_HELPERS_H
+
+#include "hls_stream.h"
+#include <algorithm>
+#include <fstream>
+#include <iostream>
+#include <map>
+#include <math.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <vector>
+
+namespace nnet {
+
+#ifndef __SYNTHESIS__
+
+#ifndef WEIGHTS_DIR
+#define WEIGHTS_DIR "weights"
+#endif
+
+template <class T, size_t SIZE> void load_weights_from_txt(T *w, const char *fname) {
+
+    std::string full_path = std::string(WEIGHTS_DIR) + "/" + std::string(fname);
+    std::ifstream infile(full_path.c_str(), std::ios::binary);
+
+    if (infile.fail()) {
+        std::cerr << "ERROR: file " << std::string(full_path) << " does not exist" << std::endl;
+        exit(1);
+    }
+
+    std::string line;
+    if (std::getline(infile, line)) {
+        std::istringstream iss(line);
+        std::string token;
+
+        size_t i = 0;
+        while (std::getline(iss, token, ',')) {
+            std::istringstream(token) >> w[i];
+            i++;
+        }
+
+        if (SIZE != i) {
+            std::cerr << "ERROR: Expected " << SIZE << " values";
+            std::cerr << " but read only " << i << " values" << std::endl;
+        }
+    }
+}
+
+template <class T, size_t SIZE> void load_compressed_weights_from_txt(T *w, const char *fname) {
+
+    std::string full_path = std::string(WEIGHTS_DIR) + "/" + std::string(fname);
+    std::ifstream infile(full_path.c_str(), std::ios::binary);
+
+    if (infile.fail()) {
+        std::cerr << "ERROR: file " << std::string(fname) << " does not exist" << std::endl;
+        exit(1);
+    }
+
+    std::string line;
+    if (std::getline(infile, line)) {
+        std::istringstream iss(line);
+        std::string token;
+        std::string extra_chars = "} ";
+
+        size_t i = 0;
+        while (std::getline(iss, token, '{')) {
+            if (token.length() == 0) {
+                continue;
+            }
+            for (char c : extra_chars) {
+                token.erase(std::remove(token.begin(), token.end(), c), token.end());
+            }
+            if (token.back() == ',') {
+                token.erase(token.end() - 1);
+            }
+
+            std::replace(token.begin(), token.end(), ',', ' ');
+            std::istringstream structss(token);
+
+            if (!(structss >> w[i].row_index >> w[i].col_index >> w[i].weight)) {
+                std::cerr << "ERROR: Unable to parse file " << std::string(fname);
+                exit(1);
+            }
+            i++;
+        }
+
+        if (SIZE != i) {
+            std::cerr << "ERROR: Expected " << SIZE << " values";
+            std::cerr << " but read only " << i << " values" << std::endl;
+        }
+    }
+}
+
+template <class T, size_t SIZE> void load_exponent_weights_from_txt(T *w, const char *fname) {
+
+    std::string full_path = std::string(WEIGHTS_DIR) + "/" + std::string(fname);
+    std::ifstream infile(full_path.c_str(), std::ios::binary);
+
+    if (infile.fail()) {
+        std::cerr << "ERROR: file " << std::string(fname) << " does not exist" << std::endl;
+        exit(1);
+    }
+
+    std::string line;
+    if (std::getline(infile, line)) {
+        std::istringstream iss(line);
+        std::string token;
+        std::string extra_chars = "} ";
+
+        size_t i = 0;
+        while (std::getline(iss, token, '{')) {
+            if (token.length() == 0) {
+                continue;
+            }
+            for (char c : extra_chars) {
+                token.erase(std::remove(token.begin(), token.end(), c), token.end());
+            }
+            if (token.back() == ',') {
+                token.erase(token.end() - 1);
+            }
+
+            std::replace(token.begin(), token.end(), ',', ' ');
+            std::istringstream structss(token);
+
+            if (!(structss >> w[i].sign >> w[i].weight)) {
+                std::cerr << "ERROR: Unable to parse file " << std::string(fname);
+                exit(1);
+            }
+            i++;
+        }
+
+        if (SIZE != i) {
+            std::cerr << "ERROR: Expected " << SIZE << " values";
+            std::cerr << " but read only " << i << " values" << std::endl;
+        }
+    }
+}
+template <class srcType, class dstType, size_t SIZE> void convert_data(srcType *src, dstType *dst) {
+    for (size_t i = 0; i < SIZE; i++) {
+        dst[i] = dstType(src[i]);
+    }
+}
+
+template <class srcType, class dstType, size_t SIZE> void convert_data(srcType *src, hls::stream<dstType> &dst) {
+    for (size_t i = 0; i < SIZE / dstType::size; i++) {
+        dstType ctype;
+        for (size_t j = 0; j < dstType::size; j++) {
+            ctype[j] = typename dstType::value_type(src[i * dstType::size + j]);
+        }
+        dst.write(ctype);
+    }
+}
+
+template <class srcType, class dstType, size_t SIZE> void convert_data(hls::stream<srcType> &src, dstType *dst) {
+    for (size_t i = 0; i < SIZE / srcType::size; i++) {
+        srcType ctype = src.read();
+        for (size_t j = 0; j < srcType::size; j++) {
+            dst[i * srcType::size + j] = dstType(ctype[j]);
+        }
+    }
+}
+
+extern bool trace_enabled;
+extern std::map<std::string, void *> *trace_outputs;
+extern size_t trace_type_size;
+
+template <class data_T, class save_T> void save_output_array(data_T *data, save_T *ptr, size_t layer_size) {
+    for (int i = 0; i < layer_size; i++) {
+        ptr[i] = save_T(data[i]);
+    }
+}
+
+template <class data_T, class save_T> void save_output_array(hls::stream<data_T> &data, save_T *ptr, size_t layer_size) {
+    for (size_t i = 0; i < layer_size / data_T::size; i++) {
+        data_T ctype = data.read();
+        for (size_t j = 0; j < data_T::size; j++) {
+            ptr[i * data_T::size + j] = save_T(ctype[j]);
+        }
+        data.write(ctype);
+    }
+}
+
+// We don't want to include save_T in this function because it will be inserted into myproject.cpp
+// so a workaround with element size is used
+template <class data_T> void save_layer_output(data_T *data, const char *layer_name, size_t layer_size) {
+    if (!trace_enabled)
+        return;
+
+    if (trace_outputs) {
+        if (trace_outputs->count(layer_name) > 0) {
+            if (trace_type_size == 4) {
+                save_output_array<data_T, float>(data, (float *)(*trace_outputs)[layer_name], layer_size);
+            } else if (trace_type_size == 8) {
+                save_output_array<data_T, double>(data, (double *)(*trace_outputs)[layer_name], layer_size);
+            } else {
+                std::cout << "Unknown trace type!" << std::endl;
+            }
+        } else {
+            std::cout << "Layer name: " << layer_name << " not found in debug storage!" << std::endl;
+        }
+    } else {
+        std::ostringstream filename;
+        filename << "./tb_data/" << layer_name << "_output.log"; // TODO if run as a shared lib, path should be ../tb_data
+        std::fstream out;
+        out.open(filename.str(), std::ios::app);
+        assert(out.is_open());
+        for (int i = 0; i < layer_size; i++) {
+            out << float(data[i]) << " "; // We don't care about precision in text files
+        }
+        out << std::endl;
+        out.close();
+    }
+}
+
+template <class data_T> void save_layer_output(hls::stream<data_T> &data, const char *layer_name, size_t layer_size) {
+    if (!trace_enabled)
+        return;
+
+    if (trace_outputs) {
+        if (trace_outputs->count(layer_name) > 0) {
+            if (trace_type_size == 4) {
+                save_output_array<data_T, float>(data, (float *)(*trace_outputs)[layer_name], layer_size);
+            } else if (trace_type_size == 8) {
+                save_output_array<data_T, double>(data, (double *)(*trace_outputs)[layer_name], layer_size);
+            } else {
+                std::cout << "Unknown trace type!" << std::endl;
+            }
+        } else {
+            std::cout << "Layer name: " << layer_name << " not found in debug storage!" << std::endl;
+        }
+    } else {
+        std::ostringstream filename;
+        filename << "./tb_data/" << layer_name << "_output.log"; // TODO if run as a shared lib, path should be ../tb_data
+        std::fstream out;
+        out.open(filename.str(), std::ios::app);
+        assert(out.is_open());
+        for (size_t i = 0; i < layer_size / data_T::size; i++) {
+            data_T ctype = data.read();
+            for (size_t j = 0; j < data_T::size; j++) {
+                out << float(ctype[j]) << " "; // We don't care about precision in text files
+            }
+            data.write(ctype);
+        }
+        out << std::endl;
+        out.close();
+    }
+}
+
+#endif
+
+template <class src_T, class dst_T, size_t OFFSET, size_t SIZE> void copy_data(std::vector<src_T> src, dst_T dst[SIZE]) {
+    typename std::vector<src_T>::const_iterator in_begin = src.cbegin() + OFFSET;
+    typename std::vector<src_T>::const_iterator in_end = in_begin + SIZE;
+    std::copy(in_begin, in_end, dst);
+}
+
+template <class src_T, class dst_T, size_t OFFSET, size_t SIZE>
+void copy_data(std::vector<src_T> src, hls::stream<dst_T> &dst) {
+    typename std::vector<src_T>::const_iterator in_begin = src.cbegin() + OFFSET;
+    typename std::vector<src_T>::const_iterator in_end = in_begin + SIZE;
+
+    size_t i_pack = 0;
+    dst_T dst_pack;
+    for (typename std::vector<src_T>::const_iterator i = in_begin; i != in_end; ++i) {
+        dst_pack[i_pack++] = typename dst_T::value_type(*i);
+        if (i_pack == dst_T::size) {
+            i_pack = 0;
+            dst.write(dst_pack);
+        }
+    }
+}
+
+template <class src_T, class dst_T, size_t OFFSET, size_t SIZE> void copy_data_axi(std::vector<src_T> src, dst_T dst[SIZE]) {
+    for (auto i = 0; i < SIZE; i++)
+        if (i == SIZE - 1) {
+            dst[i].data = src[i];
+            dst[i].last = 1;
+        } else {
+            dst[i].data = src[i];
+            dst[i].last = 0;
+        }
+}
+
+template <class res_T, size_t SIZE> void print_result(res_T result[SIZE], std::ostream &out, bool keep = false) {
+    for (int i = 0; i < SIZE; i++) {
+        out << result[i] << " ";
+    }
+    out << std::endl;
+}
+
+template <class res_T, size_t SIZE> void print_result(hls::stream<res_T> &result, std::ostream &out, bool keep = false) {
+    for (int i = 0; i < SIZE / res_T::size; i++) {
+        res_T res_pack = result.read();
+        for (int j = 0; j < res_T::size; j++) {
+            out << res_pack[j] << " ";
+        }
+        if (keep)
+            result.write(res_pack);
+    }
+    out << std::endl;
+}
+
+template <class data_T, size_t SIZE> void fill_zero(data_T data[SIZE]) { std::fill_n(data, SIZE, 0.); }
+
+template <class data_T, size_t SIZE> void fill_zero(hls::stream<data_T> &data) {
+    for (int i = 0; i < SIZE / data_T::size; i++) {
+        data_T data_pack;
+        for (int j = 0; j < data_T::size; j++) {
+            data_pack[j] = 0.;
+        }
+        data.write(data_pack);
+    }
+}
+
+template <class dataType, unsigned int nrows> int read_file_1D(const char *filename, dataType data[nrows]) {
+    FILE *fp;
+    fp = fopen(filename, "r");
+    if (fp == 0) {
+        return -1;
+    }
+    // Read data from file
+    float newval;
+    for (int ii = 0; ii < nrows; ii++) {
+        if (fscanf(fp, "%f\n", &newval) != 0) {
+            data[ii] = newval;
+        } else {
+            return -2;
+        }
+    }
+    fclose(fp);
+    return 0;
+}
+
+template <class dataType, unsigned int nrows, unsigned int ncols>
+int read_file_2D(const char *filename, dataType data[nrows][ncols]) {
+    FILE *fp;
+    fp = fopen(filename, "r");
+    if (fp == 0) {
+        return -1;
+    }
+    // Read data from file
+    float newval;
+    for (int ii = 0; ii < nrows; ii++) {
+        for (int jj = 0; jj < ncols; jj++) {
+            if (fscanf(fp, "%f\n", &newval) != 0) {
+                data[ii][jj] = newval;
+            } else {
+                return -2;
+            }
+        }
+    }
+    fclose(fp);
+    return 0;
+}
+
+template <class in_T, class out_T, int N_IN> void change_type(hls::stream<in_T> &in, hls::stream<out_T> &out) {
+    in_T datareg;
+    hls::stream<out_T> input_trunc;
+    for (int ii = 0; ii < N_IN; ii++) {
+        out << (out_T)in.read();
+    }
+}
+
+template <class data_T, int N_IN> void hls_stream_debug(hls::stream<data_T> &data, hls::stream<data_T> &res) {
+    data_T datareg;
+    for (int ii = 0; ii < N_IN; ii++) {
+        datareg = data.read();
+        std::cout << "[" << ii << "]: " << datareg << std::endl;
+        res << datareg;
+    }
+}
+
+constexpr int ceillog2(int x) { return (x <= 2) ? 1 : 1 + ceillog2((x + 1) / 2); }
+
+constexpr int floorlog2(int x) { return (x < 2) ? 0 : 1 + floorlog2(x / 2); }
+
+constexpr int pow2(int x) { return x == 0 ? 1 : 2 * pow2(x - 1); }
+
+} // namespace nnet
+
+#endif

firmware/nnet_utils/nnet_sepconv2d.h

@@ -0,0 +1,51 @@
+#ifndef NNET_SEPARABLE_CONV2D_H_
+#define NNET_SEPARABLE_CONV2D_H_
+
+#include "nnet_common.h"
+#include "nnet_conv2d.h"
+#include "nnet_sepconv2d_latency.h"
+//#include "nnet_sepconv2d_resource.h"
+#include <cstdlib>
+
+namespace nnet {
+
+template <class data_T, class res_T, typename CONFIG_T>
+void depthwise_conv_2d_cl(
+    data_T data[CONFIG_T::in_height * CONFIG_T::in_width * CONFIG_T::n_chan],
+    res_T res[CONFIG_T::out_height * CONFIG_T::out_width * CONFIG_T::n_filt],
+    typename CONFIG_T::weight_t weights[CONFIG_T::filt_height * CONFIG_T::filt_width * CONFIG_T::n_chan],
+    typename CONFIG_T::bias_t biases[CONFIG_T::n_chan]) {
+    #pragma HLS INLINE recursive
+    if (CONFIG_T::strategy == nnet::latency || CONFIG_T::strategy == nnet::distributed_arithmetic) {
+        depthwise_conv_2d_latency_cl<data_T, res_T, CONFIG_T>(data, res, weights, biases);
+    } else {
+        assert("Resource strategy for DepthwiseConv2D is not supported." && false);
+    }
+}
+
+template <class data_T, class dw_res_T, class res_T, typename CONFIG_T>
+void separable_conv_2d_cl(data_T data[CONFIG_T::depthwise_config::in_height * CONFIG_T::depthwise_config::in_width *
+                                      CONFIG_T::depthwise_config::n_chan],
+                          res_T res[CONFIG_T::pointwise_config::out_height * CONFIG_T::pointwise_config::out_width *
+                                    CONFIG_T::pointwise_config::n_filt],
+                          typename CONFIG_T::depthwise_config::weight_t
+                              depthwise_weights[CONFIG_T::depthwise_config::filt_height *
+                                                CONFIG_T::depthwise_config::filt_width * CONFIG_T::depthwise_config::n_chan],
+                          typename CONFIG_T::pointwise_config::weight_t
+                              pointwise_weights[CONFIG_T::pointwise_config::n_chan * CONFIG_T::pointwise_config::n_filt],
+                          typename CONFIG_T::depthwise_config::bias_t depthwise_biases[CONFIG_T::depthwise_config::n_chan],
+                          typename CONFIG_T::pointwise_config::bias_t pointwise_biases[CONFIG_T::pointwise_config::n_filt]) {
+    #pragma HLS INLINE recursive
+
+    dw_res_T depthwise_res[CONFIG_T::depthwise_config::out_height * CONFIG_T::depthwise_config::out_width *
+                           CONFIG_T::depthwise_config::n_filt];
+
+    depthwise_conv_2d_cl<data_T, dw_res_T, typename CONFIG_T::depthwise_config>(data, depthwise_res, depthwise_weights,
+                                                                                depthwise_biases);
+    pointwise_conv_2d_cl<dw_res_T, res_T, typename CONFIG_T::pointwise_config>(depthwise_res, res, pointwise_weights,
+                                                                               pointwise_biases);
+}
+
+} // namespace nnet
+
+#endif

firmware/nnet_utils/nnet_transpose.h

@@ -0,0 +1,39 @@
+#ifndef NNET_PERMUTE_H_
+#define NNET_PERMUTE_H_
+
+namespace nnet {
+
+struct transpose_config {
+    static const unsigned dims;
+    static const unsigned N;
+    // vivado/vitis hls can't index constexpr array for some reason
+    // and vivado hls don't like template recursion either (vitis is fine)
+    // thus this appears to be the only workaround (or overkill it with codegen)
+    static const unsigned *const from_shape;
+    static const unsigned *const to_shape;
+    static const unsigned *const perm;
+    static const unsigned *const perm_strides;
+};
+
+template <typename CONFIG_T> unsigned transfer_idx(int index) {
+    // Given output idx in c-order flat array, return input idx
+    int idx = 0;
+    for (int i = CONFIG_T::dims - 1; i >= 0; i--) {
+        idx += (index % CONFIG_T::to_shape[i]) * CONFIG_T::perm_strides[i];
+        index /= CONFIG_T::to_shape[i];
+    }
+    return idx;
+}
+
+template <typename data_T, typename res_T, typename CONFIG_T>
+void transpose(const data_T data[CONFIG_T::N], res_T res[CONFIG_T::N]) {
+    for (int i = 0; i < CONFIG_T::N; i++) {
+        #pragma HLS UNROLL
+        int idx = transfer_idx<CONFIG_T>(i);
+        res[i] = data[idx];
+    }
+}
+
+} // namespace nnet
+
+#endif

firmware/nnet_utils/nnet_types.h

@@ -0,0 +1,80 @@
+#ifndef NNET_TYPES_H_
+#define NNET_TYPES_H_
+
+#include <assert.h>
+#include <cstddef>
+#include <cstdio>
+
+namespace nnet {
+
+// Fixed-size array
+template <typename T, unsigned N> struct array {
+    typedef T value_type;
+    static const unsigned size = N;
+
+    T data[N];
+
+    T &operator[](size_t pos) { return data[pos]; }
+
+    const T &operator[](size_t pos) const { return data[pos]; }
+
+    array &operator=(const array &other) {
+        if (&other == this)
+            return *this;
+
+        assert(N == other.size && "Array sizes must match.");
+
+        for (unsigned i = 0; i < N; i++) {
+            #pragma HLS UNROLL
+            data[i] = other[i];
+        }
+        return *this;
+    }
+
+    bool operator==(const array &other) const {
+        if (N != other.size) {
+            return false;
+        }
+
+        for (unsigned i = 0; i < N; i++) {
+            if (data[i] != other[i]) {
+                return false;
+            }
+        }
+
+        return true;
+    }
+
+    bool operator!=(const array &other) const { return !(*this == other); }
+};
+
+// Generic lookup-table implementation, for use in approximations of math functions
+template <typename T, unsigned N, T (*func)(T)> class lookup_table {
+  public:
+    lookup_table(T from, T to) : range_start(from), range_end(to), base_div(ap_uint<16>(N) / T(to - from)) {
+        T step = (range_end - range_start) / ap_uint<16>(N);
+        for (size_t i = 0; i < N; i++) {
+            T num = range_start + ap_uint<16>(i) * step;
+            T sample = func(num);
+            samples[i] = sample;
+        }
+    }
+
+    T operator()(T n) const {
+        int index = (n - range_start) * base_div;
+        if (index < 0)
+            index = 0;
+        else if (index > N - 1)
+            index = N - 1;
+        return samples[index];
+    }
+
+  private:
+    T samples[N];
+    const T range_start, range_end;
+    ap_fixed<20, 16> base_div;
+};
+
+} // namespace nnet
+
+#endif

logs/hls_run_tcl_20622.backup.log

@@ -0,0 +1,170 @@
+INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet
+
+****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit)
+  **** SW Build 5069499 on May 21 2024
+  **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+  **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+  **** Start of session at: Mon Mar 30 15:20:26 2026
+    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace
+INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Mon Mar 30 15:20:28 UTC 2026
+INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS
+INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet'
+Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl'
+INFO: [HLS 200-1510] Running: open_project myproject_prj 
+INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'.
+INFO: [HLS 200-1510] Running: set_top myproject 
+INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x 
+INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project
+INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x 
+INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project
+INFO: [HLS 200-1510] Running: add_files -tb firmware/weights 
+INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project
+INFO: [HLS 200-1510] Running: add_files -tb tb_data 
+INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project
+INFO: [HLS 200-1510] Running: open_solution solution1 
+INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'.
+INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns.
+INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns.
+INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e'
+INFO: [HLS 200-1505] Using flow_target 'vivado'
+Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html
+INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0
+INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096
+INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096.
+INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 
+ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'.
+ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'.
+SYNTAX 
+  config_array_partition [OPTIONS]
+    -auto_partition_threshold <uint:*4*> *** DEPRECATED***
+    -auto_promotion_threshold <uint:*64*> *** DEPRECATED***
+    -complete_threshold <uint:*4*> 
+    -throughput_driven <off|auto|aggressive|*on*>
+
+SEE ALSO
+  INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven
+  docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html
+
+INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e 
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false 
+INFO: [HLS 200-1510] Running: create_clock -period 5 -name default 
+INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default 
+***** C/RTL SYNTHESIS *****
+INFO: [HLS 200-1510] Running: csynth_design 
+INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 276.859 MB.
+INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... 
+WARNING: [HLS 207-5570] unexpected pragma argument 'softmax', expects function/operation (firmware/nnet_utils/nnet_activation.h:402:36)
+WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:33:9)
+WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:107:9)
+WARNING: [HLS 207-5538] 'Resource pragma' is deprecated, use 'bind_op/bind_storage pragma' instead (firmware/nnet_utils/nnet_dense_resource.h:189:9)
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:85)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:242:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:85)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:248:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:85)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:258:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:85)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:264:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:87)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:274:92)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:87)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:280:92)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:87)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:290:92)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:87)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:296:92)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:306:94)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:312:94)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:322:94)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:328:94)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:338:94)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:89)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:344:94)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:100)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 214-113] Either use an argument of the function or declare the variable inside the dataflow loop body (firmware/myproject.cpp:348:105)
+Resolution: For help on HLS 214-113 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=214-113.html
+WARNING: [HLS 200-471] Dataflow form checks found 30 issue(s) in file firmware/myproject.cpp
+Resolution: For help on HLS 200-471 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-471.html
+WARNING: [HLS 207-5292] unused parameter 'keep' (firmware/nnet_utils/nnet_helpers.h:285:99)
+WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:14:36)
+WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:15:36)
+WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:16:44)
+WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:24:24)
+WARNING: [HLS 207-5292] unused parameter 'buffer' (firmware/nnet_utils/nnet_function_stubs.h:25:24)
+WARNING: [HLS 207-5292] unused parameter 'partition' (firmware/nnet_utils/nnet_function_stubs.h:26:32)
+WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:33:30)
+WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:33:58)
+WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:34:51)
+WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:35:49)
+WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:42:30)
+WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:42:58)
+WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:43:51)
+WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:44:49)
+WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_function_stubs.h:51:29)
+WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_function_stubs.h:51:80)
+WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_function_stubs.h:52:50)
+WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_function_stubs.h:53:48)
+WARNING: [HLS 207-5292] unused parameter 'data' (firmware/nnet_utils/nnet_code_gen.h:16:39)
+WARNING: [HLS 207-5292] unused parameter 'res' (firmware/nnet_utils/nnet_code_gen.h:17:38)
+WARNING: [HLS 207-5292] unused parameter 'weights' (firmware/nnet_utils/nnet_code_gen.h:18:60)
+WARNING: [HLS 207-5292] unused parameter 'biases' (firmware/nnet_utils/nnet_code_gen.h:19:58)
+WARNING: [HLS 207-5584] there are more than one pragma inline in the function scope, ignore the pragma  (/opt/Xilinx/Vitis_HLS/2024.1/common/technology/autopilot/ap_shift_reg.h:47:9)
+INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 36.43 seconds. CPU system time: 2.15 seconds. Elapsed time: 38.64 seconds; current allocated memory: 287.945 MB.
+INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
+INFO: [HLS 200-1995] There were 28,390 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+WARNING: [HLS 200-1995] There were 282,347 instructions in the design after the 'Unroll/Inline' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+WARNING: [HLS 200-1995] There were 127,448 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+WARNING: [HLS 200-1995] There were 102,013 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+INFO: [HLS 200-1995] There were 53,117 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+INFO: [HLS 200-1995] There were 69,335 instructions in the design after the 'Array/Struct' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+INFO: [HLS 200-1995] There were 50,968 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+INFO: [HLS 200-1995] There were 51,867 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+WARNING: [HLS 200-1995] There were 106,651 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+INFO: [HLS 200-1995] There were 97,860 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt
+INFO: [HLS 200-1995] There were 99,568 instructions in the design after the 'Performance' phase of compilation. See the Design Size Report for more details: /home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1/syn/report/csynth_design_size.rpt

logs/hls_run_tcl_21278.backup.log

@@ -0,0 +1,104 @@
+INFO: [vitis-run 82-31] Launching vitis_hls: vitis_hls -nolog -run tcl -f /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl -work_dir /home/ubuntu/lithobench/hls4ml_mini_unet
+
+****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit)
+  **** SW Build 5069499 on May 21 2024
+  **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+  **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+  **** Start of session at: Mon Mar 30 15:35:30 2026
+    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source /opt/Xilinx/Vitis_HLS/2024.1/scripts/vitis_hls/hls.tcl -notrace
+INFO: [HLS 200-10] For user 'ubuntu' on host 'ip-172-31-42-252.ec2.internal' (Linux_x86_64 version 5.15.0-1084-aws) on Mon Mar 30 15:35:32 UTC 2026
+INFO: [HLS 200-10] On os Ubuntu 20.04.6 LTS
+INFO: [HLS 200-10] In directory '/home/ubuntu/lithobench/hls4ml_mini_unet'
+Sourcing Tcl script '/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl'
+INFO: [HLS 200-1510] Running: open_project myproject_prj 
+INFO: [HLS 200-10] Opening project '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj'.
+INFO: [HLS 200-1510] Running: set_top myproject 
+INFO: [HLS 200-1510] Running: add_files firmware/myproject.cpp -cflags -std=c++0x 
+INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project
+INFO: [HLS 200-1510] Running: add_files -tb myproject_test.cpp -cflags -std=c++0x 
+INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project
+INFO: [HLS 200-1510] Running: add_files -tb firmware/weights 
+INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project
+INFO: [HLS 200-1510] Running: add_files -tb tb_data 
+INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project
+INFO: [HLS 200-1510] Running: open_solution solution1 
+INFO: [HLS 200-10] Opening solution '/home/ubuntu/lithobench/hls4ml_mini_unet/myproject_prj/solution1'.
+INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns.
+INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.35ns.
+INFO: [HLS 200-1611] Setting target device to 'xcvu47p-fsvh2892-2L-e'
+INFO: [HLS 200-1505] Using flow_target 'vivado'
+Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html
+INFO: [HLS 200-1464] Running solution command: config_compile -name_max_length=80
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1464] Running solution command: config_compile -complex-mul-dsp=0
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1464] Running solution command: config_compile -unsafe_math_optimizations=0
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1464] Running solution command: config_schedule -enable_dsp_full_reg=0
+INFO: [HLS 200-1464] Running solution command: config_array_partition -complete_threshold=4096
+INFO: [XFORM 203-102] Size-based automatic array partition enabled: cut-off elements per dimension is 4096.
+INFO: [HLS 200-1510] Running: config_array_partition -maximum_size 4096 
+ERROR: [HLS 200-101] config_array_partition: Unknown option '-maximum_size'.
+ERROR: [HLS 200-101] config_array_partition: Unknown option '4096'.
+SYNTAX 
+  config_array_partition [OPTIONS]
+    -auto_partition_threshold <uint:*4*> *** DEPRECATED***
+    -auto_promotion_threshold <uint:*64*> *** DEPRECATED***
+    -complete_threshold <uint:*4*> 
+    -throughput_driven <off|auto|aggressive|*on*>
+
+SEE ALSO
+  INI: syn.array_partition.complete_threshold syn.array_partition.throughput_driven
+  docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html
+
+INFO: [HLS 200-1510] Running: config_compile -name_max_length 80 
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1510] Running: set_part xcvu47p-fsvh2892-2L-e 
+INFO: [XFORM 203-1161] The maximum of name length is set to 80.
+INFO: [HLS 200-1510] Running: config_schedule -enable_dsp_full_reg=false 
+INFO: [HLS 200-1510] Running: create_clock -period 5 -name default 
+INFO: [HLS 200-1510] Running: set_clock_uncertainty 27% default 
+***** C/RTL SYNTHESIS *****
+INFO: [HLS 200-1510] Running: config_compile -expression_balance off 
+ERROR: [HLS 200-101] config_compile: Unknown option '-expression_balance'.
+ERROR: [HLS 200-101] config_compile: Unknown option 'off'.
+SYNTAX 
+  config_compile [OPTIONS]
+    -design_size_maximum_warning <int:*100000*> 
+    -enable_auto_rewind [=false|*true*]
+    -ignore_long_run_time [=true|*false*]
+    -name_max_length <uint:*80*> 
+    -no_signed_zeros [=true|*false*]
+    -pipeline_flush_in_task <always|never|*ii1*>
+    -pipeline_loops <uint:*64*> 
+    -pipeline_style <stp|flp|frp|*auto*>
+    -pragma_strict_mode [=true|*false*]
+    -pre_tcl <string> 
+    -unsafe_math_optimizations [=true|*false*]
+
+SEE ALSO
+  INI: syn.compile.*
+  docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.1%20English&url=ug1399-vitis-hls&resourceid=vyw1583260160301.html
+
+
+    invoked from within
+"config_compile -expression_balance off"
+    invoked from within
+"if {$opt(synth)} {
+    puts "***** C/RTL SYNTHESIS *****"
+
+    set time_start [clock clicks -milliseconds]
+    config_compile -expression_balance off
+..."
+    (file "/home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl" line 165)
+    invoked from within
+"source /home/ubuntu/lithobench/hls4ml_mini_unet/build_prj.tcl"
+    ("uplevel" body line 1)
+    invoked from within
+"uplevel \#0 [list source $tclfile] "
+
+INFO: [HLS 200-112] Total CPU user time: 2.3 seconds. Total CPU system time: 0.34 seconds. Total elapsed time: 2.46 seconds; peak allocated memory: 276.859 MB.
+INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid.

myproject_prj/hls.app

@@ -0,0 +1,12 @@
+<AutoPilot:project xmlns:AutoPilot="com.autoesl.autopilot.project" projectType="C/C++" name="myproject_prj" ideType="classic" top="myproject">
+    <files>
+        <file name="firmware/myproject.cpp" sc="0" tb="false" cflags="-std=c++0x" csimflags="" blackbox="false"/>
+        <file name="../../tb_data" sc="0" tb="1" cflags="-Wno-unknown-pragmas" csimflags="" blackbox="false"/>
+        <file name="../../firmware/weights" sc="0" tb="1" cflags="-Wno-unknown-pragmas" csimflags="" blackbox="false"/>
+        <file name="../../myproject_test.cpp" sc="0" tb="1" cflags="-std=c++0x -Wno-unknown-pragmas" csimflags="" blackbox="false"/>
+    </files>
+    <solutions>
+        <solution name="solution1" status=""/>
+    </solutions>
+</AutoPilot:project>
+

myproject_prj/solution1/solution1.aps

@@ -0,0 +1,24 @@
+<AutoPilot:solution xmlns:AutoPilot="com.autoesl.autopilot.solution">
+    <config>
+        <config_compile name_max_length="80" complex-mul-dsp="0" unsafe_math_optimizations="0"/>
+        <config_schedule enable_dsp_full_reg="0"/>
+        <config_array_partition complete_threshold="4096"/>
+    </config>
+    <name>
+        <value string="solution1"/>
+    </name>
+    <project>
+        <value string="myproject_prj"/>
+    </project>
+    <flowTarget value="vivado"/>
+    <targetInfo>
+        <TargetInfo value="xcvu47p:-fsvh2892:-2L-e"/>
+    </targetInfo>
+    <libraryList>
+        <library value="xilinx/virtexuplus/virtexuplus" name="DefaultPlatform"/>
+    </libraryList>
+    <clockList>
+        <clock default="false" name="default" uncertainty="27%" period="4"/>
+    </clockList>
+</AutoPilot:solution>
+

myproject_prj/solution1/solution1.directive

@@ -0,0 +1,10 @@
+<AutoPilot:ProjectResources xmlns:AutoPilot="com.autoesl.autopilot.ui.directiveView">
+    <sourceFile name="">
+        <directive functionName="myproject" label="" functionLabel="">
+            <pragma name="TOP">
+                <option name="name" value="myproject"/>
+            </pragma>
+        </directive>
+    </sourceFile>
+</AutoPilot:ProjectResources>
+

myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s_csynth.xml

@@ -0,0 +1,356 @@
+<profile>
+
+<ReportVersion>
+<Version>2024.1</Version>
+</ReportVersion>
+
+<UserAssignments>
+<unit>ns</unit>
+<ProductFamily>virtexuplusHBM</ProductFamily>
+<Part>xcvu47p-fsvh2892-2L-e</Part>
+<TopModelName>clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s</TopModelName>
+<TargetClockPeriod>4.00</TargetClockPeriod>
+<ClockUncertainty>1.35</ClockUncertainty>
+<FlowTarget>vivado</FlowTarget>
+</UserAssignments>
+
+<PerformanceEstimates>
+<PipelineType>loop auto-rewind stp(delay=0 clock cycles(s))</PipelineType>
+<SummaryOfTimingAnalysis>
+<unit>ns</unit>
+<EstimatedClockPeriod>2.590</EstimatedClockPeriod>
+</SummaryOfTimingAnalysis>
+<SummaryOfOverallLatency>
+<unit>clock cycles</unit>
+<Best-caseLatency>257</Best-caseLatency>
+<Average-caseLatency>257</Average-caseLatency>
+<Worst-caseLatency>257</Worst-caseLatency>
+<Best-caseRealTimeLatency>1.028 us</Best-caseRealTimeLatency>
+<Average-caseRealTimeLatency>1.028 us</Average-caseRealTimeLatency>
+<Worst-caseRealTimeLatency>1.028 us</Worst-caseRealTimeLatency>
+<Interval-min>256</Interval-min>
+<Interval-max>256</Interval-max>
+</SummaryOfOverallLatency>
+<SummaryOfLoopLatency>
+<CloneLoop>
+<Slack>2.65</Slack>
+<TripCount>256</TripCount>
+<Latency>255</Latency>
+<AbsoluteTimeLatency>1020</AbsoluteTimeLatency>
+<PipelineII>1</PipelineII>
+<PipelineDepth>1</PipelineDepth>
+<InstanceList>
+</InstanceList>
+</CloneLoop>
+</SummaryOfLoopLatency>
+<SummaryOfViolations>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_stream.h:22</SourceLocation>
+<SummaryOfLoopViolations>
+<CloneLoop>
+<Name>CloneLoop</Name>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_stream.h:22</SourceLocation>
+</CloneLoop>
+</SummaryOfLoopViolations>
+</SummaryOfViolations>
+</PerformanceEstimates>
+
+<AreaEstimates>
+<Resources>
+<FF>11</FF>
+<LUT>95</LUT>
+<BRAM_18K>0</BRAM_18K>
+<DSP>0</DSP>
+<URAM>0</URAM>
+</Resources>
+<AvailableResources>
+<BRAM_18K>4032</BRAM_18K>
+<DSP>9024</DSP>
+<FF>2607360</FF>
+<LUT>1303680</LUT>
+<URAM>960</URAM>
+</AvailableResources>
+</AreaEstimates>
+
+<InterfaceSummary>
+<RtlPorts>
+<name>ap_clk</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_rst</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_start</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>start_full_n</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_done</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_continue</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_idle</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_ready</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>start_out</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>start_write</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,32u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,32u&gt;,8192&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer15_out_dout</name>
+<Object>layer15_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>512</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer15_out_num_data_valid</name>
+<Object>layer15_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>9</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer15_out_fifo_cap</name>
+<Object>layer15_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>9</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer15_out_empty_n</name>
+<Object>layer15_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer15_out_read</name>
+<Object>layer15_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy1_din</name>
+<Object>layer43_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>512</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy1_num_data_valid</name>
+<Object>layer43_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>9</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy1_fifo_cap</name>
+<Object>layer43_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>9</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy1_full_n</name>
+<Object>layer43_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy1_write</name>
+<Object>layer43_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy2_din</name>
+<Object>layer43_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>512</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy2_num_data_valid</name>
+<Object>layer43_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>9</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy2_fifo_cap</name>
+<Object>layer43_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>9</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy2_full_n</name>
+<Object>layer43_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer43_cpy2_write</name>
+<Object>layer43_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+</InterfaceSummary>
+
+</profile>

myproject_prj/solution1/syn/report/clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s_csynth.xml

@@ -0,0 +1,356 @@
+<profile>
+
+<ReportVersion>
+<Version>2024.1</Version>
+</ReportVersion>
+
+<UserAssignments>
+<unit>ns</unit>
+<ProductFamily>virtexuplusHBM</ProductFamily>
+<Part>xcvu47p-fsvh2892-2L-e</Part>
+<TopModelName>clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s</TopModelName>
+<TargetClockPeriod>4.00</TargetClockPeriod>
+<ClockUncertainty>1.35</ClockUncertainty>
+<FlowTarget>vivado</FlowTarget>
+</UserAssignments>
+
+<PerformanceEstimates>
+<PipelineType>loop auto-rewind stp(delay=0 clock cycles(s))</PipelineType>
+<SummaryOfTimingAnalysis>
+<unit>ns</unit>
+<EstimatedClockPeriod>2.448</EstimatedClockPeriod>
+</SummaryOfTimingAnalysis>
+<SummaryOfOverallLatency>
+<unit>clock cycles</unit>
+<Best-caseLatency>4097</Best-caseLatency>
+<Average-caseLatency>4097</Average-caseLatency>
+<Worst-caseLatency>4097</Worst-caseLatency>
+<Best-caseRealTimeLatency>16.388 us</Best-caseRealTimeLatency>
+<Average-caseRealTimeLatency>16.388 us</Average-caseRealTimeLatency>
+<Worst-caseRealTimeLatency>16.388 us</Worst-caseRealTimeLatency>
+<Interval-min>4096</Interval-min>
+<Interval-max>4096</Interval-max>
+</SummaryOfOverallLatency>
+<SummaryOfLoopLatency>
+<CloneLoop>
+<Slack>2.65</Slack>
+<TripCount>4096</TripCount>
+<Latency>4095</Latency>
+<AbsoluteTimeLatency>16380</AbsoluteTimeLatency>
+<PipelineII>1</PipelineII>
+<PipelineDepth>1</PipelineDepth>
+<InstanceList>
+</InstanceList>
+</CloneLoop>
+</SummaryOfLoopLatency>
+<SummaryOfViolations>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_stream.h:22</SourceLocation>
+<SummaryOfLoopViolations>
+<CloneLoop>
+<Name>CloneLoop</Name>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_stream.h:22</SourceLocation>
+</CloneLoop>
+</SummaryOfLoopViolations>
+</SummaryOfViolations>
+</PerformanceEstimates>
+
+<AreaEstimates>
+<Resources>
+<FF>15</FF>
+<LUT>103</LUT>
+<BRAM_18K>0</BRAM_18K>
+<DSP>0</DSP>
+<URAM>0</URAM>
+</Resources>
+<AvailableResources>
+<BRAM_18K>4032</BRAM_18K>
+<DSP>9024</DSP>
+<FF>2607360</FF>
+<LUT>1303680</LUT>
+<URAM>960</URAM>
+</AvailableResources>
+</AreaEstimates>
+
+<InterfaceSummary>
+<RtlPorts>
+<name>ap_clk</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_rst</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_start</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>start_full_n</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_done</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_continue</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_idle</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_ready</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>start_out</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>start_write</name>
+<Object>clone_stream&lt;array&lt;ap_fixed,8u&gt;,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,8u&gt;,32768&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer5_out_dout</name>
+<Object>layer5_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>128</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer5_out_num_data_valid</name>
+<Object>layer5_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer5_out_fifo_cap</name>
+<Object>layer5_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer5_out_empty_n</name>
+<Object>layer5_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer5_out_read</name>
+<Object>layer5_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy1_din</name>
+<Object>layer41_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>128</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy1_num_data_valid</name>
+<Object>layer41_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy1_fifo_cap</name>
+<Object>layer41_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy1_full_n</name>
+<Object>layer41_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy1_write</name>
+<Object>layer41_cpy1</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_din</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>128</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_num_data_valid</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_fifo_cap</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_full_n</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_write</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+</InterfaceSummary>
+
+</profile>

myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_csynth.rpt

@@ -0,0 +1,335 @@
+
+
+================================================================
+== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s'
+================================================================
+* Date:           Sun Apr  5 21:47:00 2026
+
+* Version:        2024.1 (Build 5069499 on May 21 2024)
+* Project:        myproject_prj
+* Solution:       solution1 (Vivado IP Flow Target)
+* Product family: virtexuplusHBM
+* Target device:  xcvu47p-fsvh2892-2L-e
+
+
+================================================================
+== Performance Estimates
+================================================================
++ Timing: 
+    * Summary: 
+    +--------+---------+----------+------------+
+    |  Clock |  Target | Estimated| Uncertainty|
+    +--------+---------+----------+------------+
+    |ap_clk  |  4.00 ns|  4.437 ns|     1.35 ns|
+    +--------+---------+----------+------------+
+
++ Latency: 
+    * Summary: 
+    +---------+---------+----------+----------+-----+-----+---------+
+    |  Latency (cycles) |  Latency (absolute) |  Interval | Pipeline|
+    |   min   |   max   |    min   |    max   | min | max |   Type  |
+    +---------+---------+----------+----------+-----+-----+---------+
+    |        2|      581|  8.873 ns|  2.578 us|    2|  581|       no|
+    +---------+---------+----------+----------+-----+-----+---------+
+
+    + Detail: 
+        * Instance: 
+        +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+        |                                                                              |                                                                 |  Latency (cycles) |  Latency (absolute) |  Interval |                 Pipeline                 |
+        |                                   Instance                                   |                              Module                             |   min   |   max   |    min   |    max   | min | max |                   Type                   |
+        +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+        |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543  |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s       |        0|        0|      0 ns|      0 ns|    1|    1|                                       yes|
+        |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931    |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s  |      578|      579|  2.564 us|  2.569 us|  576|  576|  loop rewind stp(delay=0 clock cycles(s))|
+        +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+
+        * Loop: 
+        N/A
+
+
+
+================================================================
+== Utilization Estimates
+================================================================
+* Summary: 
++---------------------+---------+------+---------+---------+-----+
+|         Name        | BRAM_18K|  DSP |    FF   |   LUT   | URAM|
++---------------------+---------+------+---------+---------+-----+
+|DSP                  |        -|     -|        -|        -|    -|
+|Expression           |        -|     -|        0|      505|    -|
+|FIFO                 |        -|     -|        -|        -|    -|
+|Instance             |        8|     8|     9548|     9887|    -|
+|Memory               |        -|     -|        -|        -|    -|
+|Multiplexer          |        -|     -|        0|       70|    -|
+|Register             |        -|     -|     2438|        -|    -|
++---------------------+---------+------+---------+---------+-----+
+|Total                |        8|     8|    11986|    10462|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available SLR        |     1344|  3008|   869120|   434560|  320|
++---------------------+---------+------+---------+---------+-----+
+|Utilization SLR (%)  |       ~0|    ~0|        1|        2|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available            |     4032|  9024|  2607360|  1303680|  960|
++---------------------+---------+------+---------+---------+-----+
+|Utilization (%)      |       ~0|    ~0|       ~0|       ~0|    0|
++---------------------+---------+------+---------+---------+-----+
+
++ Detail: 
+    * Instance: 
+    +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+
+    |                                   Instance                                   |                              Module                             | BRAM_18K| DSP|  FF  |  LUT | URAM|
+    +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+
+    |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931    |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s  |        8|   8|  7499|  7999|    0|
+    |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543  |shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s       |        0|   0|  2049|  1888|    0|
+    +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+
+    |Total                                                                         |                                                                 |        8|   8|  9548|  9887|    0|
+    +------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+------+-----+
+
+    * DSP: 
+    N/A
+
+    * Memory: 
+    N/A
+
+    * FIFO: 
+    N/A
+
+    * Expression: 
+    +---------------------------------+----------+----+---+----+------------+------------+
+    |          Variable Name          | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+    +---------------------------------+----------+----+---+----+------------+------------+
+    |add_ln303_fu_1496_p2             |         +|   0|  0|  39|          32|           1|
+    |add_ln307_fu_1543_p2             |         +|   0|  0|  39|          32|           1|
+    |add_ln313_fu_1565_p2             |         +|   0|  0|  39|          32|           1|
+    |add_ln318_fu_1513_p2             |         +|   0|  0|  39|          32|           1|
+    |and_ln284_7_fu_1293_p2           |       and|   0|  0|   2|           1|           1|
+    |and_ln284_fu_1287_p2             |       and|   0|  0|   2|           1|           1|
+    |ap_block_state3                  |       and|   0|  0|   2|           1|           1|
+    |ap_block_state3_on_subcall_done  |       and|   0|  0|   2|           1|           1|
+    |ap_condition_1153                |       and|   0|  0|   2|           1|           1|
+    |ap_condition_822                 |       and|   0|  0|   2|           1|           1|
+    |ap_predicate_op37_call_state3    |       and|   0|  0|   2|           1|           1|
+    |icmp_ln284_19_fu_1249_p2         |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln284_20_fu_1265_p2         |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_21_fu_1281_p2         |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_fu_1231_p2            |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln303_fu_1501_p2            |      icmp|   0|  0|  39|          32|           5|
+    |icmp_ln307_fu_1548_p2            |      icmp|   0|  0|  39|          32|           5|
+    |icmp_ln313_fu_1560_p2            |      icmp|   0|  0|  39|          32|           2|
+    |select_ln313_fu_1570_p3          |    select|   0|  0|  32|           1|           2|
+    |select_ln318_fu_1518_p3          |    select|   0|  0|  32|           1|           2|
+    +---------------------------------+----------+----+---+----+------------+------------+
+    |Total                            |          |   0|  0| 505|         359|          33|
+    +---------------------------------+----------+----+---+----+------------+------------+
+
+    * Multiplexer: 
+    +-------------------------------------+----+-----------+-----+-----------+
+    |                 Name                | LUT| Input Size| Bits| Total Bits|
+    +-------------------------------------+----+-----------+-----+-----------+
+    |ap_NS_fsm                            |  20|          4|    1|          4|
+    |ap_phi_mux_storemerge_phi_fu_536_p4  |  14|          3|   32|         96|
+    |layer12_out_blk_n                    |   9|          2|    1|          2|
+    |pX_8                                 |   9|          2|   32|         64|
+    |pY_8                                 |   9|          2|   32|         64|
+    |sX_8                                 |   9|          2|   32|         64|
+    +-------------------------------------+----+-----------+-----+-----------+
+    |Total                                |  70|         15|  130|        294|
+    +-------------------------------------+----+-----------+-----+-----------+
+
+    * Register: 
+    +-----------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |                                           Name                                          | FF | LUT| Bits| Const Bits|
+    +-----------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |and_ln284_7_reg_1608                                                                     |   1|   0|    1|          0|
+    |ap_CS_fsm                                                                                |   3|   0|    3|          0|
+    |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931_ap_start_reg  |   1|   0|    1|          0|
+    |icmp_ln284_reg_1594                                                                      |   1|   0|    1|          0|
+    |pX_8                                                                                     |  32|   0|   32|          0|
+    |pY_8                                                                                     |  32|   0|   32|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4416   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4417   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4419   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4420   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4421   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4422   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4423   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4424   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4425   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4426   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4427   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4428   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4430   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4431   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4432   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4433   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4434   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4435   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4436   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4437   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4438   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4439   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4441   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4442   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4443   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4444   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4445   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4446   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4447   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4448   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4449   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4450   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4452   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4453   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4454   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4455   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4456   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4457   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4458   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4459   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4460   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4461   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4463   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4464   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4465   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4466   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4467   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4468   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4469   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4470   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4471   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4472   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4474   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4475   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4476   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4477   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4478   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4479   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4480   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4481   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4482   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4483   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4485   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4486   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4487   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4488   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4489   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4490   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4491   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4492   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4493   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4494   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4496   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4497   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4498   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4499   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4500   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4501   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4502   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4503   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4504   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4505   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4507   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4508   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4509   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4510   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4511   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4512   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4513   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4514   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4515   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4516   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4518   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4519   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4520   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4521   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4522   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4523   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4524   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4525   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4526   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4527   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4529   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4530   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4531   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4532   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4533   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4534   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4535   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4536   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4537   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4538   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4540   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4541   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4542   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4543   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4544   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4545   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4546   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4547   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4548   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4549   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4551   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4552   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4553   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4554   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4555   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4556   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4557   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4558   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4559   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4560   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4562   |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4563   |  16|   0|   16|          0|
+    |sX_8                                                                                     |  32|   0|   32|          0|
+    |sY_8                                                                                     |  32|   0|   32|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_158            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_159            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_160            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_161            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_162            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_163            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_164            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_165            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_166            |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_167            |  16|   0|   16|          0|
+    +-----------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |Total                                                                                    |2438|   0| 2438|          0|
+    +-----------------------------------------------------------------------------------------+----+----+-----+-----------+
+
+
+
+================================================================
+== Interface
+================================================================
+* Summary: 
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+|          RTL Ports         | Dir | Bits |  Protocol  |                               Source Object                               |    C Type    |
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+|ap_clk                      |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,32u>,config12>|  return value|
+|ap_rst                      |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,32u>,config12>|  return value|
+|ap_start                    |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,32u>,config12>|  return value|
+|ap_done                     |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,32u>,config12>|  return value|
+|ap_idle                     |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,32u>,config12>|  return value|
+|ap_ready                    |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,32u>,config12>|  return value|
+|p_read                      |   in|    16|     ap_none|                                                                     p_read|        scalar|
+|p_read1                     |   in|    16|     ap_none|                                                                    p_read1|        scalar|
+|p_read2                     |   in|    16|     ap_none|                                                                    p_read2|        scalar|
+|p_read3                     |   in|    16|     ap_none|                                                                    p_read3|        scalar|
+|p_read4                     |   in|    16|     ap_none|                                                                    p_read4|        scalar|
+|p_read5                     |   in|    16|     ap_none|                                                                    p_read5|        scalar|
+|p_read6                     |   in|    16|     ap_none|                                                                    p_read6|        scalar|
+|p_read7                     |   in|    16|     ap_none|                                                                    p_read7|        scalar|
+|p_read8                     |   in|    16|     ap_none|                                                                    p_read8|        scalar|
+|p_read9                     |   in|    16|     ap_none|                                                                    p_read9|        scalar|
+|p_read10                    |   in|    16|     ap_none|                                                                   p_read10|        scalar|
+|p_read11                    |   in|    16|     ap_none|                                                                   p_read11|        scalar|
+|p_read12                    |   in|    16|     ap_none|                                                                   p_read12|        scalar|
+|p_read13                    |   in|    16|     ap_none|                                                                   p_read13|        scalar|
+|p_read14                    |   in|    16|     ap_none|                                                                   p_read14|        scalar|
+|p_read15                    |   in|    16|     ap_none|                                                                   p_read15|        scalar|
+|layer12_out_din             |  out|  1312|     ap_fifo|                                                                layer12_out|       pointer|
+|layer12_out_num_data_valid  |   in|     9|     ap_fifo|                                                                layer12_out|       pointer|
+|layer12_out_fifo_cap        |   in|     9|     ap_fifo|                                                                layer12_out|       pointer|
+|layer12_out_full_n          |   in|     1|     ap_fifo|                                                                layer12_out|       pointer|
+|layer12_out_write           |  out|     1|     ap_fifo|                                                                layer12_out|       pointer|
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+

myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_csynth.rpt

@@ -0,0 +1,421 @@
+
+
+================================================================
+== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s'
+================================================================
+* Date:           Sun Apr  5 21:50:35 2026
+
+* Version:        2024.1 (Build 5069499 on May 21 2024)
+* Project:        myproject_prj
+* Solution:       solution1 (Vivado IP Flow Target)
+* Product family: virtexuplusHBM
+* Target device:  xcvu47p-fsvh2892-2L-e
+
+
+================================================================
+== Performance Estimates
+================================================================
++ Timing: 
+    * Summary: 
+    +--------+---------+----------+------------+
+    |  Clock |  Target | Estimated| Uncertainty|
+    +--------+---------+----------+------------+
+    |ap_clk  |  4.00 ns|  2.533 ns|     1.35 ns|
+    +--------+---------+----------+------------+
+
++ Latency: 
+    * Summary: 
+    +---------+---------+----------+----------+-----+-----+---------+
+    |  Latency (cycles) |  Latency (absolute) |  Interval | Pipeline|
+    |   min   |   max   |    min   |    max   | min | max |   Type  |
+    +---------+---------+----------+----------+-----+-----+---------+
+    |        2|      221|  8.000 ns|  0.884 us|    2|  221|       no|
+    +---------+---------+----------+----------+-----+-----+---------+
+
+    + Detail: 
+        * Instance: 
+        +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+        |                                                                                     |                                                                         |  Latency (cycles) |  Latency (absolute) |  Interval |                 Pipeline                 |
+        |                                       Instance                                      |                                  Module                                 |   min   |   max   |    min   |    max   | min | max |                   Type                   |
+        +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+        |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781         |shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s               |        0|        0|      0 ns|      0 ns|    1|    1|                                       yes|
+        |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361  |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s  |      217|      218|  0.868 us|  0.872 us|  216|  216|  loop rewind stp(delay=0 clock cycles(s))|
+        +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+
+        * Loop: 
+        N/A
+
+
+
+================================================================
+== Utilization Estimates
+================================================================
+* Summary: 
++---------------------+---------+------+---------+---------+-----+
+|         Name        | BRAM_18K|  DSP |    FF   |   LUT   | URAM|
++---------------------+---------+------+---------+---------+-----+
+|DSP                  |        -|     -|        -|        -|    -|
+|Expression           |        -|     -|        0|      501|    -|
+|FIFO                 |        -|     -|        -|        -|    -|
+|Instance             |        4|     8|    10784|    10117|    -|
+|Memory               |        -|     -|        -|        -|    -|
+|Multiplexer          |        -|     -|        0|       76|    -|
+|Register             |        -|     -|     3919|        -|    -|
++---------------------+---------+------+---------+---------+-----+
+|Total                |        4|     8|    14703|    10694|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available SLR        |     1344|  3008|   869120|   434560|  320|
++---------------------+---------+------+---------+---------+-----+
+|Utilization SLR (%)  |       ~0|    ~0|        1|        2|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available            |     4032|  9024|  2607360|  1303680|  960|
++---------------------+---------+------+---------+---------+-----+
+|Utilization (%)      |       ~0|    ~0|       ~0|       ~0|    0|
++---------------------+---------+------+---------+---------+-----+
+
++ Detail: 
+    * Instance: 
+    +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+
+    |                                       Instance                                      |                                  Module                                 | BRAM_18K| DSP|  FF  |  LUT | URAM|
+    +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+
+    |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361  |dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s  |        4|   8|  7711|  7285|    0|
+    |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781         |shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s               |        0|   0|  3073|  2832|    0|
+    +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+
+    |Total                                                                                |                                                                         |        4|   8| 10784| 10117|    0|
+    +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+---------+----+------+------+-----+
+
+    * DSP: 
+    N/A
+
+    * Memory: 
+    N/A
+
+    * FIFO: 
+    N/A
+
+    * Expression: 
+    +--------------------------------+----------+----+---+----+------------+------------+
+    |          Variable Name         | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+    +--------------------------------+----------+----+---+----+------------+------------+
+    |add_ln303_fu_1916_p2            |         +|   0|  0|  39|          32|           1|
+    |add_ln307_fu_1963_p2            |         +|   0|  0|  39|          32|           1|
+    |add_ln313_fu_1985_p2            |         +|   0|  0|  39|          32|           1|
+    |add_ln318_fu_1933_p2            |         +|   0|  0|  39|          32|           1|
+    |and_ln284_6_fu_1865_p2          |       and|   0|  0|   2|           1|           1|
+    |and_ln284_fu_1859_p2            |       and|   0|  0|   2|           1|           1|
+    |ap_block_state4                 |       and|   0|  0|   2|           1|           1|
+    |ap_condition_1647               |       and|   0|  0|   2|           1|           1|
+    |ap_predicate_op56_write_state4  |       and|   0|  0|   2|           1|           1|
+    |icmp_ln284_16_fu_1821_p2        |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln284_17_fu_1837_p2        |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_18_fu_1853_p2        |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_fu_1803_p2           |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln303_fu_1921_p2           |      icmp|   0|  0|  39|          32|           7|
+    |icmp_ln307_fu_1968_p2           |      icmp|   0|  0|  39|          32|           7|
+    |icmp_ln313_fu_1980_p2           |      icmp|   0|  0|  39|          32|           2|
+    |select_ln313_fu_1990_p3         |    select|   0|  0|  32|           1|           2|
+    |select_ln318_fu_1938_p3         |    select|   0|  0|  32|           1|           2|
+    +--------------------------------+----------+----+---+----+------------+------------+
+    |Total                           |          |   0|  0| 501|         357|          35|
+    +--------------------------------+----------+----+---+----+------------+------------+
+
+    * Multiplexer: 
+    +-------------------------------------+----+-----------+-----+-----------+
+    |                 Name                | LUT| Input Size| Bits| Total Bits|
+    +-------------------------------------+----+-----------+-----+-----------+
+    |ap_NS_fsm                            |  26|          5|    1|          5|
+    |ap_phi_mux_storemerge_phi_fu_774_p4  |  14|          3|   32|         96|
+    |layer35_out_blk_n                    |   9|          2|    1|          2|
+    |pX_6                                 |   9|          2|   32|         64|
+    |pY_6                                 |   9|          2|   32|         64|
+    |sX_6                                 |   9|          2|   32|         64|
+    +-------------------------------------+----+-----------+-----+-----------+
+    |Total                                |  76|         16|  130|        295|
+    +-------------------------------------+----+-----------+-----+-----------+
+
+    * Register: 
+    +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |                                               Name                                               | FF | LUT| Bits| Const Bits|
+    +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |and_ln284_6_reg_2028                                                                              |   1|   0|    1|          0|
+    |ap_CS_fsm                                                                                         |   4|   0|    4|          0|
+    |grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361_ap_start_reg  |   1|   0|    1|          0|
+    |icmp_ln284_reg_2014                                                                               |   1|   0|    1|          0|
+    |pX_6                                                                                              |  32|   0|   32|          0|
+    |pY_6                                                                                              |  32|   0|   32|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4564            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4565            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4566            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4567            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4568            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4569            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4570            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4571            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4573            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4574            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4575            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4576            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4577            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4578            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4579            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4580            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4581            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4582            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4584            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4585            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4586            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4587            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4588            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4589            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4590            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4591            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4592            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4593            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4595            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4596            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4597            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4598            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4599            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4600            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4601            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4602            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4603            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4604            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4606            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4607            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4608            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4609            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4610            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4611            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4612            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4613            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4614            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4615            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4617            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4618            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4619            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4620            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4621            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4622            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4623            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4624            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4625            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4626            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4628            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4629            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4630            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4631            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4632            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4633            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4634            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4635            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4636            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4637            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4639            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4640            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4641            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4642            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4643            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4644            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4645            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4646            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4647            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4648            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4650            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4651            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4652            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4653            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4654            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4655            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4656            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4657            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4658            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4659            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4661            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4662            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4663            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4664            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4665            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4666            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4667            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4668            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4669            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4670            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4672            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4673            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4674            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4675            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4676            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4677            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4678            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4679            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4680            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4681            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4683            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4684            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4685            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4686            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4687            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4688            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4689            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4690            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4691            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4692            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4694            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4695            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4696            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4697            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4698            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4699            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4700            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4701            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4702            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4703            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4705            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4706            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4707            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4708            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4709            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4710            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4711            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4712            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4713            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4714            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4716            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4717            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4718            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4719            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4720            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4721            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4722            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4723            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4724            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4725            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4727            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4728            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4729            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4730            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4731            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4732            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4733            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4734            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4735            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4736            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4738            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4739            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4740            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4741            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4742            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4743            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4744            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4745            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4746            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4747            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4749            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4750            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4751            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4752            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4753            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4754            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4755            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4756            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4757            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4758            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4760            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4761            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4762            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4763            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4764            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4765            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4766            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4767            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4768            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4769            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4771            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4772            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4773            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4774            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4775            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4776            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4777            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4778            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4779            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4780            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4782            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4783            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4784            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4785            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4786            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4787            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4788            |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4789            |  16|   0|   16|          0|
+    |res_out_1_reg_2037                                                                                |  41|   0|   41|          0|
+    |res_out_2_reg_2042                                                                                |  41|   0|   41|          0|
+    |res_out_3_reg_2047                                                                                |  41|   0|   41|          0|
+    |res_out_4_reg_2052                                                                                |  41|   0|   41|          0|
+    |res_out_5_reg_2057                                                                                |  41|   0|   41|          0|
+    |res_out_6_reg_2062                                                                                |  41|   0|   41|          0|
+    |res_out_7_reg_2067                                                                                |  41|   0|   41|          0|
+    |res_out_reg_2032                                                                                  |  41|   0|   41|          0|
+    |sX_6                                                                                              |  32|   0|   32|          0|
+    |sY_6                                                                                              |  32|   0|   32|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_90                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_91                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_92                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_93                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_94                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_95                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_96                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_97                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_98                      |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_99                      |  16|   0|   16|          0|
+    +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |Total                                                                                             |3919|   0| 3919|          0|
+    +--------------------------------------------------------------------------------------------------+----+----+-----+-----------+
+
+
+
+================================================================
+== Interface
+================================================================
+* Summary: 
++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+
+|          RTL Ports         | Dir | Bits|  Protocol  |                               Source Object                              |    C Type    |
++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+
+|ap_clk                      |   in|    1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,8u>,config35>|  return value|
+|ap_rst                      |   in|    1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,8u>,config35>|  return value|
+|ap_start                    |   in|    1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,8u>,config35>|  return value|
+|ap_done                     |  out|    1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,8u>,config35>|  return value|
+|ap_idle                     |  out|    1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,8u>,config35>|  return value|
+|ap_ready                    |  out|    1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<41,21,5,3,0>,8u>,config35>|  return value|
+|p_read                      |   in|   16|     ap_none|                                                                    p_read|        scalar|
+|p_read1                     |   in|   16|     ap_none|                                                                   p_read1|        scalar|
+|p_read2                     |   in|   16|     ap_none|                                                                   p_read2|        scalar|
+|p_read3                     |   in|   16|     ap_none|                                                                   p_read3|        scalar|
+|p_read4                     |   in|   16|     ap_none|                                                                   p_read4|        scalar|
+|p_read5                     |   in|   16|     ap_none|                                                                   p_read5|        scalar|
+|p_read6                     |   in|   16|     ap_none|                                                                   p_read6|        scalar|
+|p_read7                     |   in|   16|     ap_none|                                                                   p_read7|        scalar|
+|p_read8                     |   in|   16|     ap_none|                                                                   p_read8|        scalar|
+|p_read9                     |   in|   16|     ap_none|                                                                   p_read9|        scalar|
+|p_read10                    |   in|   16|     ap_none|                                                                  p_read10|        scalar|
+|p_read11                    |   in|   16|     ap_none|                                                                  p_read11|        scalar|
+|p_read12                    |   in|   16|     ap_none|                                                                  p_read12|        scalar|
+|p_read13                    |   in|   16|     ap_none|                                                                  p_read13|        scalar|
+|p_read14                    |   in|   16|     ap_none|                                                                  p_read14|        scalar|
+|p_read15                    |   in|   16|     ap_none|                                                                  p_read15|        scalar|
+|p_read16                    |   in|   16|     ap_none|                                                                  p_read16|        scalar|
+|p_read17                    |   in|   16|     ap_none|                                                                  p_read17|        scalar|
+|p_read18                    |   in|   16|     ap_none|                                                                  p_read18|        scalar|
+|p_read19                    |   in|   16|     ap_none|                                                                  p_read19|        scalar|
+|p_read20                    |   in|   16|     ap_none|                                                                  p_read20|        scalar|
+|p_read21                    |   in|   16|     ap_none|                                                                  p_read21|        scalar|
+|p_read22                    |   in|   16|     ap_none|                                                                  p_read22|        scalar|
+|p_read23                    |   in|   16|     ap_none|                                                                  p_read23|        scalar|
+|layer35_out_din             |  out|  328|     ap_fifo|                                                               layer35_out|       pointer|
+|layer35_out_num_data_valid  |   in|   13|     ap_fifo|                                                               layer35_out|       pointer|
+|layer35_out_fifo_cap        |   in|   13|     ap_fifo|                                                               layer35_out|       pointer|
+|layer35_out_full_n          |   in|    1|     ap_fifo|                                                               layer35_out|       pointer|
+|layer35_out_write           |  out|    1|     ap_fifo|                                                               layer35_out|       pointer|
++----------------------------+-----+-----+------------+--------------------------------------------------------------------------+--------------+
+

myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_csynth.xml

@@ -0,0 +1,710 @@
+<profile>
+
+<ReportVersion>
+<Version>2024.1</Version>
+</ReportVersion>
+
+<UserAssignments>
+<unit>ns</unit>
+<ProductFamily>virtexuplusHBM</ProductFamily>
+<Part>xcvu47p-fsvh2892-2L-e</Part>
+<TopModelName>compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s</TopModelName>
+<TargetClockPeriod>4.00</TargetClockPeriod>
+<ClockUncertainty>1.35</ClockUncertainty>
+<FlowTarget>vivado</FlowTarget>
+</UserAssignments>
+
+<PerformanceEstimates>
+<PipelineType>no</PipelineType>
+<SummaryOfTimingAnalysis>
+<unit>ns</unit>
+<EstimatedClockPeriod>2.533</EstimatedClockPeriod>
+</SummaryOfTimingAnalysis>
+<SummaryOfOverallLatency>
+<unit>clock cycles</unit>
+<Best-caseLatency>2</Best-caseLatency>
+<Average-caseLatency>147</Average-caseLatency>
+<Worst-caseLatency>437</Worst-caseLatency>
+<Best-caseRealTimeLatency>8.000 ns</Best-caseRealTimeLatency>
+<Average-caseRealTimeLatency>0.588 us</Average-caseRealTimeLatency>
+<Worst-caseRealTimeLatency>1.748 us</Worst-caseRealTimeLatency>
+<Interval-min>2</Interval-min>
+<Interval-max>437</Interval-max>
+</SummaryOfOverallLatency>
+<SummaryOfViolations>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_conv_stream.h:281</SourceLocation>
+</SummaryOfViolations>
+</PerformanceEstimates>
+
+<AreaEstimates>
+<Resources>
+<BRAM_18K>8</BRAM_18K>
+<DSP>16</DSP>
+<FF>29287</FF>
+<LUT>20707</LUT>
+<URAM>0</URAM>
+</Resources>
+<AvailableResources>
+<BRAM_18K>4032</BRAM_18K>
+<DSP>9024</DSP>
+<FF>2607360</FF>
+<LUT>1303680</LUT>
+<URAM>960</URAM>
+</AvailableResources>
+</AreaEstimates>
+
+<InterfaceSummary>
+<RtlPorts>
+<name>ap_clk</name>
+<Object>compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_rst</name>
+<Object>compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_start</name>
+<Object>compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_done</name>
+<Object>compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_idle</name>
+<Object>compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_ready</name>
+<Object>compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read</name>
+<Object>p_read</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read1</name>
+<Object>p_read1</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read2</name>
+<Object>p_read2</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read3</name>
+<Object>p_read3</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read4</name>
+<Object>p_read4</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read5</name>
+<Object>p_read5</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read6</name>
+<Object>p_read6</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read7</name>
+<Object>p_read7</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read8</name>
+<Object>p_read8</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read9</name>
+<Object>p_read9</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read10</name>
+<Object>p_read10</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read11</name>
+<Object>p_read11</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read12</name>
+<Object>p_read12</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read13</name>
+<Object>p_read13</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read14</name>
+<Object>p_read14</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read15</name>
+<Object>p_read15</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read16</name>
+<Object>p_read16</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read17</name>
+<Object>p_read17</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read18</name>
+<Object>p_read18</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read19</name>
+<Object>p_read19</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read20</name>
+<Object>p_read20</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read21</name>
+<Object>p_read21</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read22</name>
+<Object>p_read22</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read23</name>
+<Object>p_read23</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read24</name>
+<Object>p_read24</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read25</name>
+<Object>p_read25</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read26</name>
+<Object>p_read26</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read27</name>
+<Object>p_read27</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read28</name>
+<Object>p_read28</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read29</name>
+<Object>p_read29</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read30</name>
+<Object>p_read30</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read31</name>
+<Object>p_read31</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read32</name>
+<Object>p_read32</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read33</name>
+<Object>p_read33</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read34</name>
+<Object>p_read34</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read35</name>
+<Object>p_read35</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read36</name>
+<Object>p_read36</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read37</name>
+<Object>p_read37</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read38</name>
+<Object>p_read38</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read39</name>
+<Object>p_read39</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read40</name>
+<Object>p_read40</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read41</name>
+<Object>p_read41</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read42</name>
+<Object>p_read42</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read43</name>
+<Object>p_read43</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read44</name>
+<Object>p_read44</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read45</name>
+<Object>p_read45</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read46</name>
+<Object>p_read46</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>p_read47</name>
+<Object>p_read47</Object>
+<Type>scalar</Type>
+<Scope></Scope>
+<IOProtocol>ap_none</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>16</Bits>
+<Attribute>data</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer29_out_din</name>
+<Object>layer29_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>672</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer29_out_num_data_valid</name>
+<Object>layer29_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>11</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer29_out_fifo_cap</name>
+<Object>layer29_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>11</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer29_out_full_n</name>
+<Object>layer29_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer29_out_write</name>
+<Object>layer29_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+</InterfaceSummary>
+
+</profile>

myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_csynth.rpt

@@ -0,0 +1,525 @@
+
+
+================================================================
+== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s'
+================================================================
+* Date:           Sun Apr  5 21:47:13 2026
+
+* Version:        2024.1 (Build 5069499 on May 21 2024)
+* Project:        myproject_prj
+* Solution:       solution1 (Vivado IP Flow Target)
+* Product family: virtexuplusHBM
+* Target device:  xcvu47p-fsvh2892-2L-e
+
+
+================================================================
+== Performance Estimates
+================================================================
++ Timing: 
+    * Summary: 
+    +--------+---------+----------+------------+
+    |  Clock |  Target | Estimated| Uncertainty|
+    +--------+---------+----------+------------+
+    |ap_clk  |  4.00 ns|  4.118 ns|     1.35 ns|
+    +--------+---------+----------+------------+
+
++ Latency: 
+    * Summary: 
+    +---------+---------+----------+----------+-----+-----+---------+
+    |  Latency (cycles) |  Latency (absolute) |  Interval | Pipeline|
+    |   min   |   max   |    min   |    max   | min | max |   Type  |
+    +---------+---------+----------+----------+-----+-----+---------+
+    |        2|      581|  8.236 ns|  2.393 us|    2|  581|       no|
+    +---------+---------+----------+----------+-----+-----+---------+
+
+    + Detail: 
+        * Instance: 
+        +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+        |                                                                               |                                                                 |  Latency (cycles) |  Latency (absolute) |  Interval |                 Pipeline                 |
+        |                                    Instance                                   |                              Module                             |   min   |   max   |    min   |    max   | min | max |                   Type                   |
+        +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+        |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023  |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s       |        0|        0|      0 ns|      0 ns|    1|    1|                                       yes|
+        |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795    |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s  |      577|      578|  2.376 us|  2.380 us|  576|  576|  loop rewind stp(delay=0 clock cycles(s))|
+        +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+-----+-----+------------------------------------------+
+
+        * Loop: 
+        N/A
+
+
+
+================================================================
+== Utilization Estimates
+================================================================
+* Summary: 
++---------------------+---------+------+---------+---------+-----+
+|         Name        | BRAM_18K|  DSP |    FF   |   LUT   | URAM|
++---------------------+---------+------+---------+---------+-----+
+|DSP                  |        -|     -|        -|        -|    -|
+|Expression           |        -|     -|        0|      501|    -|
+|FIFO                 |        -|     -|        -|        -|    -|
+|Instance             |       15|    16|    11522|    19870|    -|
+|Memory               |        -|     -|        -|        -|    -|
+|Multiplexer          |        -|     -|        0|       76|    -|
+|Register             |        -|     -|     6087|        -|    -|
++---------------------+---------+------+---------+---------+-----+
+|Total                |       15|    16|    17609|    20447|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available SLR        |     1344|  3008|   869120|   434560|  320|
++---------------------+---------+------+---------+---------+-----+
+|Utilization SLR (%)  |        1|    ~0|        2|        4|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available            |     4032|  9024|  2607360|  1303680|  960|
++---------------------+---------+------+---------+---------+-----+
+|Utilization (%)      |       ~0|    ~0|       ~0|        1|    0|
++---------------------+---------+------+---------+---------+-----+
+
++ Detail: 
+    * Instance: 
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+
+    |                                    Instance                                   |                              Module                             | BRAM_18K| DSP|  FF  |  LUT  | URAM|
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+
+    |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795    |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s  |       15|  16|  7425|  16094|    0|
+    |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023  |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s       |        0|   0|  4097|   3776|    0|
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+
+    |Total                                                                          |                                                                 |       15|  16| 11522|  19870|    0|
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+------+-------+-----+
+
+    * DSP: 
+    N/A
+
+    * Memory: 
+    N/A
+
+    * FIFO: 
+    N/A
+
+    * Expression: 
+    +--------------------------------+----------+----+---+----+------------+------------+
+    |          Variable Name         | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+    +--------------------------------+----------+----+---+----+------------+------------+
+    |add_ln303_fu_2616_p2            |         +|   0|  0|  39|          32|           1|
+    |add_ln307_fu_2663_p2            |         +|   0|  0|  39|          32|           1|
+    |add_ln313_fu_2685_p2            |         +|   0|  0|  39|          32|           1|
+    |add_ln318_fu_2633_p2            |         +|   0|  0|  39|          32|           1|
+    |and_ln284_4_fu_2445_p2          |       and|   0|  0|   2|           1|           1|
+    |and_ln284_fu_2439_p2            |       and|   0|  0|   2|           1|           1|
+    |ap_block_state4                 |       and|   0|  0|   2|           1|           1|
+    |ap_condition_2223               |       and|   0|  0|   2|           1|           1|
+    |ap_predicate_op88_write_state4  |       and|   0|  0|   2|           1|           1|
+    |icmp_ln284_10_fu_2401_p2        |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln284_11_fu_2417_p2        |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_12_fu_2433_p2        |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_fu_2383_p2           |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln303_fu_2621_p2           |      icmp|   0|  0|  39|          32|           5|
+    |icmp_ln307_fu_2668_p2           |      icmp|   0|  0|  39|          32|           5|
+    |icmp_ln313_fu_2680_p2           |      icmp|   0|  0|  39|          32|           2|
+    |select_ln313_fu_2690_p3         |    select|   0|  0|  32|           1|           2|
+    |select_ln318_fu_2638_p3         |    select|   0|  0|  32|           1|           2|
+    +--------------------------------+----------+----+---+----+------------+------------+
+    |Total                           |          |   0|  0| 501|         357|          31|
+    +--------------------------------+----------+----+---+----+------------+------------+
+
+    * Multiplexer: 
+    +--------------------------------------+----+-----------+-----+-----------+
+    |                 Name                 | LUT| Input Size| Bits| Total Bits|
+    +--------------------------------------+----+-----------+-----+-----------+
+    |ap_NS_fsm                             |  26|          5|    1|          5|
+    |ap_phi_mux_storemerge_phi_fu_1016_p4  |  14|          3|   32|         96|
+    |layer14_out_blk_n                     |   9|          2|    1|          2|
+    |pX_5                                  |   9|          2|   32|         64|
+    |pY_5                                  |   9|          2|   32|         64|
+    |sX_5                                  |   9|          2|   32|         64|
+    +--------------------------------------+----+-----------+-----+-----------+
+    |Total                                 |  76|         16|  130|        295|
+    +--------------------------------------+----+-----------+-----+-----------+
+
+    * Register: 
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |                                           Name                                           | FF | LUT| Bits| Const Bits|
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |and_ln284_4_reg_2728                                                                      |   1|   0|    1|          0|
+    |ap_CS_fsm                                                                                 |   4|   0|    4|          0|
+    |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795_ap_start_reg  |   1|   0|    1|          0|
+    |icmp_ln284_reg_2714                                                                       |   1|   0|    1|          0|
+    |pX_5                                                                                      |  32|   0|   32|          0|
+    |pY_5                                                                                      |  32|   0|   32|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4790    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4791    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4793    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4794    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4795    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4796    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4797    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4798    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4799    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4800    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4801    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4802    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4804    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4805    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4806    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4807    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4808    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4809    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4810    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4811    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4812    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4813    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4815    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4816    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4817    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4818    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4819    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4820    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4821    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4822    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4823    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4824    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4826    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4827    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4828    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4829    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4830    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4831    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4832    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4833    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4834    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4835    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4837    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4838    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4839    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4840    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4841    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4842    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4843    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4844    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4845    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4846    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4848    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4849    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4850    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4851    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4852    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4853    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4854    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4855    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4856    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4857    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4859    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4860    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4861    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4862    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4863    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4864    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4865    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4866    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4867    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4868    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4870    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4871    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4872    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4873    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4874    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4875    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4876    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4877    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4878    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4879    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4881    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4882    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4883    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4884    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4885    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4886    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4887    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4888    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4889    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4890    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4892    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4893    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4894    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4895    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4896    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4897    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4898    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4899    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4900    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4901    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4903    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4904    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4905    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4906    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4907    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4908    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4909    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4910    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4911    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4912    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4914    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4915    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4916    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4917    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4918    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4919    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4920    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4921    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4922    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4923    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4925    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4926    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4927    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4928    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4929    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4930    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4931    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4932    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4933    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4934    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4936    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4937    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4938    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4939    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4940    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4941    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4942    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4943    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4944    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4945    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4947    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4948    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4949    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4950    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4951    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4952    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4953    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4954    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4955    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4956    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4958    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4959    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4960    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4961    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4962    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4963    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4964    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4965    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4966    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4967    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4969    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4970    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4971    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4972    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4973    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4974    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4975    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4976    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4977    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4978    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4980    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4981    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4982    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4983    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4984    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4985    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4986    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4987    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4988    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4989    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4991    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4992    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4993    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4994    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4995    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4996    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4997    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4998    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_4999    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5000    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5002    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5003    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5004    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5005    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5006    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5007    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5008    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5009    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5010    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5011    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5013    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5014    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5015    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5016    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5017    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5018    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5019    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5020    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5021    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5022    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5024    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5025    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5026    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5027    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5028    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5029    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5030    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5031    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5032    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5033    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5035    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5036    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5037    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5038    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5039    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5040    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5041    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5042    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5043    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5044    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5046    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5047    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5048    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5049    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5050    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5051    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5052    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5053    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5054    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5055    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5057    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5058    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5059    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5060    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5061    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5062    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5063    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5064    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5065    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5066    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5068    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5069    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5070    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5071    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5072    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5073    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5074    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5075    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5076    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5077    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5079    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5080    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5081    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5082    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5083    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5084    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5085    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5086    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5087    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5088    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5090    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5091    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5092    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5093    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5094    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5095    |  16|   0|   16|          0|
+    |res_out_162_reg_2782                                                                      |  42|   0|   42|          0|
+    |res_out_163_reg_2787                                                                      |  42|   0|   42|          0|
+    |res_out_164_reg_2792                                                                      |  42|   0|   42|          0|
+    |res_out_165_reg_2797                                                                      |  42|   0|   42|          0|
+    |res_out_166_reg_2802                                                                      |  42|   0|   42|          0|
+    |res_out_167_reg_2807                                                                      |  42|   0|   42|          0|
+    |res_out_168_reg_2812                                                                      |  42|   0|   42|          0|
+    |res_out_169_reg_2817                                                                      |  42|   0|   42|          0|
+    |res_out_170_reg_2822                                                                      |  42|   0|   42|          0|
+    |res_out_171_reg_2827                                                                      |  42|   0|   42|          0|
+    |res_out_172_reg_2832                                                                      |  42|   0|   42|          0|
+    |res_out_173_reg_2837                                                                      |  42|   0|   42|          0|
+    |res_out_174_reg_2842                                                                      |  42|   0|   42|          0|
+    |res_out_175_reg_2847                                                                      |  42|   0|   42|          0|
+    |res_out_176_reg_2852                                                                      |  42|   0|   42|          0|
+    |res_out_177_reg_2857                                                                      |  42|   0|   42|          0|
+    |res_out_178_reg_2862                                                                      |  42|   0|   42|          0|
+    |res_out_179_reg_2867                                                                      |  42|   0|   42|          0|
+    |res_out_180_reg_2872                                                                      |  42|   0|   42|          0|
+    |res_out_181_reg_2877                                                                      |  42|   0|   42|          0|
+    |res_out_182_reg_2882                                                                      |  42|   0|   42|          0|
+    |res_out_183_reg_2887                                                                      |  42|   0|   42|          0|
+    |res_out_1_reg_2737                                                                        |  42|   0|   42|          0|
+    |res_out_2_reg_2742                                                                        |  42|   0|   42|          0|
+    |res_out_3_reg_2747                                                                        |  42|   0|   42|          0|
+    |res_out_4_reg_2752                                                                        |  42|   0|   42|          0|
+    |res_out_5_reg_2757                                                                        |  42|   0|   42|          0|
+    |res_out_6_reg_2762                                                                        |  42|   0|   42|          0|
+    |res_out_7_reg_2767                                                                        |  42|   0|   42|          0|
+    |res_out_8_reg_2772                                                                        |  42|   0|   42|          0|
+    |res_out_9_reg_2777                                                                        |  42|   0|   42|          0|
+    |res_out_reg_2732                                                                          |  42|   0|   42|          0|
+    |sX_5                                                                                      |  32|   0|   32|          0|
+    |sY_5                                                                                      |  32|   0|   32|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_80              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_81              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_82              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_83              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_84              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_85              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_86              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_87              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_88              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_89              |  16|   0|   16|          0|
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |Total                                                                                     |6087|   0| 6087|          0|
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+
+
+
+================================================================
+== Interface
+================================================================
+* Summary: 
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+|          RTL Ports         | Dir | Bits |  Protocol  |                               Source Object                               |    C Type    |
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+|ap_clk                      |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config14>|  return value|
+|ap_rst                      |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config14>|  return value|
+|ap_start                    |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config14>|  return value|
+|ap_done                     |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config14>|  return value|
+|ap_idle                     |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config14>|  return value|
+|ap_ready                    |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config14>|  return value|
+|p_read                      |   in|    16|     ap_none|                                                                     p_read|        scalar|
+|p_read1                     |   in|    16|     ap_none|                                                                    p_read1|        scalar|
+|p_read2                     |   in|    16|     ap_none|                                                                    p_read2|        scalar|
+|p_read3                     |   in|    16|     ap_none|                                                                    p_read3|        scalar|
+|p_read4                     |   in|    16|     ap_none|                                                                    p_read4|        scalar|
+|p_read5                     |   in|    16|     ap_none|                                                                    p_read5|        scalar|
+|p_read6                     |   in|    16|     ap_none|                                                                    p_read6|        scalar|
+|p_read7                     |   in|    16|     ap_none|                                                                    p_read7|        scalar|
+|p_read8                     |   in|    16|     ap_none|                                                                    p_read8|        scalar|
+|p_read9                     |   in|    16|     ap_none|                                                                    p_read9|        scalar|
+|p_read10                    |   in|    16|     ap_none|                                                                   p_read10|        scalar|
+|p_read11                    |   in|    16|     ap_none|                                                                   p_read11|        scalar|
+|p_read12                    |   in|    16|     ap_none|                                                                   p_read12|        scalar|
+|p_read13                    |   in|    16|     ap_none|                                                                   p_read13|        scalar|
+|p_read14                    |   in|    16|     ap_none|                                                                   p_read14|        scalar|
+|p_read15                    |   in|    16|     ap_none|                                                                   p_read15|        scalar|
+|p_read16                    |   in|    16|     ap_none|                                                                   p_read16|        scalar|
+|p_read17                    |   in|    16|     ap_none|                                                                   p_read17|        scalar|
+|p_read18                    |   in|    16|     ap_none|                                                                   p_read18|        scalar|
+|p_read19                    |   in|    16|     ap_none|                                                                   p_read19|        scalar|
+|p_read20                    |   in|    16|     ap_none|                                                                   p_read20|        scalar|
+|p_read21                    |   in|    16|     ap_none|                                                                   p_read21|        scalar|
+|p_read22                    |   in|    16|     ap_none|                                                                   p_read22|        scalar|
+|p_read23                    |   in|    16|     ap_none|                                                                   p_read23|        scalar|
+|p_read24                    |   in|    16|     ap_none|                                                                   p_read24|        scalar|
+|p_read25                    |   in|    16|     ap_none|                                                                   p_read25|        scalar|
+|p_read26                    |   in|    16|     ap_none|                                                                   p_read26|        scalar|
+|p_read27                    |   in|    16|     ap_none|                                                                   p_read27|        scalar|
+|p_read28                    |   in|    16|     ap_none|                                                                   p_read28|        scalar|
+|p_read29                    |   in|    16|     ap_none|                                                                   p_read29|        scalar|
+|p_read30                    |   in|    16|     ap_none|                                                                   p_read30|        scalar|
+|p_read31                    |   in|    16|     ap_none|                                                                   p_read31|        scalar|
+|layer14_out_din             |  out|  1344|     ap_fifo|                                                                layer14_out|       pointer|
+|layer14_out_num_data_valid  |   in|     9|     ap_fifo|                                                                layer14_out|       pointer|
+|layer14_out_fifo_cap        |   in|     9|     ap_fifo|                                                                layer14_out|       pointer|
+|layer14_out_full_n          |   in|     1|     ap_fifo|                                                                layer14_out|       pointer|
+|layer14_out_write           |  out|     1|     ap_fifo|                                                                layer14_out|       pointer|
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+

myproject_prj/solution1/syn/report/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_csynth.rpt

@@ -0,0 +1,495 @@
+
+
+================================================================
+== Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s'
+================================================================
+* Date:           Sun Apr  5 21:49:26 2026
+
+* Version:        2024.1 (Build 5069499 on May 21 2024)
+* Project:        myproject_prj
+* Solution:       solution1 (Vivado IP Flow Target)
+* Product family: virtexuplusHBM
+* Target device:  xcvu47p-fsvh2892-2L-e
+
+
+================================================================
+== Performance Estimates
+================================================================
++ Timing: 
+    * Summary: 
+    +--------+---------+----------+------------+
+    |  Clock |  Target | Estimated| Uncertainty|
+    +--------+---------+----------+------------+
+    |ap_clk  |  4.00 ns|  4.449 ns|     1.35 ns|
+    +--------+---------+----------+------------+
+
++ Latency: 
+    * Summary: 
+    +---------+---------+----------+----------+-----+------+---------+
+    |  Latency (cycles) |  Latency (absolute) |  Interval  | Pipeline|
+    |   min   |   max   |    min   |    max   | min |  max |   Type  |
+    +---------+---------+----------+----------+-----+------+---------+
+    |        2|     1157|  8.899 ns|  5.148 us|    2|  1157|       no|
+    +---------+---------+----------+----------+-----+------+---------+
+
+    + Detail: 
+        * Instance: 
+        +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+------+------+------------------------------------------+
+        |                                                                               |                                                                 |  Latency (cycles) |  Latency (absolute) |   Interval  |                 Pipeline                 |
+        |                                    Instance                                   |                              Module                             |   min   |   max   |    min   |    max   |  min |  max |                   Type                   |
+        +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+------+------+------------------------------------------+
+        |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023  |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s       |        0|        0|      0 ns|      0 ns|     1|     1|                                       yes|
+        |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795    |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s  |     1154|     1155|  5.135 us|  5.139 us|  1152|  1152|  loop rewind stp(delay=0 clock cycles(s))|
+        +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+---------+----------+----------+------+------+------------------------------------------+
+
+        * Loop: 
+        N/A
+
+
+
+================================================================
+== Utilization Estimates
+================================================================
+* Summary: 
++---------------------+---------+------+---------+---------+-----+
+|         Name        | BRAM_18K|  DSP |    FF   |   LUT   | URAM|
++---------------------+---------+------+---------+---------+-----+
+|DSP                  |        -|     -|        -|        -|    -|
+|Expression           |        -|     -|        0|      505|    -|
+|FIFO                 |        -|     -|        -|        -|    -|
+|Instance             |       16|     8|    16268|    16447|    -|
+|Memory               |        -|     -|        -|        -|    -|
+|Multiplexer          |        -|     -|        0|       70|    -|
+|Register             |        -|     -|     4742|        -|    -|
++---------------------+---------+------+---------+---------+-----+
+|Total                |       16|     8|    21010|    17022|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available SLR        |     1344|  3008|   869120|   434560|  320|
++---------------------+---------+------+---------+---------+-----+
+|Utilization SLR (%)  |        1|    ~0|        2|        3|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available            |     4032|  9024|  2607360|  1303680|  960|
++---------------------+---------+------+---------+---------+-----+
+|Utilization (%)      |       ~0|    ~0|       ~0|        1|    0|
++---------------------+---------+------+---------+---------+-----+
+
++ Detail: 
+    * Instance: 
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+
+    |                                    Instance                                   |                              Module                             | BRAM_18K| DSP|   FF  |  LUT  | URAM|
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+
+    |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795    |dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s  |       16|   8|  12171|  12671|    0|
+    |call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023  |shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s       |        0|   0|   4097|   3776|    0|
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+
+    |Total                                                                          |                                                                 |       16|   8|  16268|  16447|    0|
+    +-------------------------------------------------------------------------------+-----------------------------------------------------------------+---------+----+-------+-------+-----+
+
+    * DSP: 
+    N/A
+
+    * Memory: 
+    N/A
+
+    * FIFO: 
+    N/A
+
+    * Expression: 
+    +---------------------------------+----------+----+---+----+------------+------------+
+    |          Variable Name          | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+    +---------------------------------+----------+----+---+----+------------+------------+
+    |add_ln303_fu_2648_p2             |         +|   0|  0|  39|          32|           1|
+    |add_ln307_fu_2695_p2             |         +|   0|  0|  39|          32|           1|
+    |add_ln313_fu_2717_p2             |         +|   0|  0|  39|          32|           1|
+    |add_ln318_fu_2665_p2             |         +|   0|  0|  39|          32|           1|
+    |and_ln284_3_fu_2445_p2           |       and|   0|  0|   2|           1|           1|
+    |and_ln284_fu_2439_p2             |       and|   0|  0|   2|           1|           1|
+    |ap_block_state3                  |       and|   0|  0|   2|           1|           1|
+    |ap_block_state3_on_subcall_done  |       and|   0|  0|   2|           1|           1|
+    |ap_condition_1526                |       and|   0|  0|   2|           1|           1|
+    |ap_condition_2161                |       and|   0|  0|   2|           1|           1|
+    |ap_predicate_op53_call_state3    |       and|   0|  0|   2|           1|           1|
+    |icmp_ln284_7_fu_2401_p2          |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln284_8_fu_2417_p2          |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_9_fu_2433_p2          |      icmp|   0|  0|  38|          31|           1|
+    |icmp_ln284_fu_2383_p2            |      icmp|   0|  0|  39|          32|           2|
+    |icmp_ln303_fu_2653_p2            |      icmp|   0|  0|  39|          32|           5|
+    |icmp_ln307_fu_2700_p2            |      icmp|   0|  0|  39|          32|           5|
+    |icmp_ln313_fu_2712_p2            |      icmp|   0|  0|  39|          32|           2|
+    |select_ln313_fu_2722_p3          |    select|   0|  0|  32|           1|           2|
+    |select_ln318_fu_2670_p3          |    select|   0|  0|  32|           1|           2|
+    +---------------------------------+----------+----+---+----+------------+------------+
+    |Total                            |          |   0|  0| 505|         359|          33|
+    +---------------------------------+----------+----+---+----+------------+------------+
+
+    * Multiplexer: 
+    +--------------------------------------+----+-----------+-----+-----------+
+    |                 Name                 | LUT| Input Size| Bits| Total Bits|
+    +--------------------------------------+----+-----------+-----+-----------+
+    |ap_NS_fsm                             |  20|          4|    1|          4|
+    |ap_phi_mux_storemerge_phi_fu_1016_p4  |  14|          3|   32|         96|
+    |layer25_out_blk_n                     |   9|          2|    1|          2|
+    |pX_4                                  |   9|          2|   32|         64|
+    |pY_4                                  |   9|          2|   32|         64|
+    |sX_4                                  |   9|          2|   32|         64|
+    +--------------------------------------+----+-----------+-----+-----------+
+    |Total                                 |  70|         15|  130|        294|
+    +--------------------------------------+----+-----------+-----+-----------+
+
+    * Register: 
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |                                           Name                                           | FF | LUT| Bits| Const Bits|
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |and_ln284_3_reg_2760                                                                      |   1|   0|    1|          0|
+    |ap_CS_fsm                                                                                 |   3|   0|    3|          0|
+    |grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795_ap_start_reg  |   1|   0|    1|          0|
+    |icmp_ln284_reg_2746                                                                       |   1|   0|    1|          0|
+    |pX_4                                                                                      |  32|   0|   32|          0|
+    |pY_4                                                                                      |  32|   0|   32|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5096    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5097    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5098    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5099    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5101    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5102    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5103    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5104    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5105    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5106    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5107    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5108    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5109    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5110    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5112    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5113    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5114    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5115    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5116    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5117    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5118    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5119    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5120    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5121    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5123    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5124    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5125    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5126    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5127    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5128    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5129    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5130    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5131    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5132    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5134    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5135    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5136    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5137    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5138    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5139    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5140    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5141    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5142    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5143    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5145    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5146    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5147    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5148    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5149    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5150    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5151    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5152    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5153    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5154    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5156    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5157    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5158    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5159    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5160    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5161    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5162    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5163    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5164    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5165    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5167    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5168    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5169    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5170    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5171    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5172    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5173    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5174    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5175    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5176    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5178    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5179    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5180    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5181    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5182    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5183    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5184    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5185    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5186    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5187    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5189    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5190    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5191    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5192    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5193    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5194    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5195    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5196    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5197    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5198    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5200    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5201    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5202    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5203    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5204    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5205    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5206    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5207    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5208    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5209    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5211    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5212    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5213    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5214    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5215    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5216    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5217    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5218    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5219    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5220    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5222    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5223    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5224    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5225    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5226    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5227    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5228    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5229    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5230    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5231    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5233    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5234    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5235    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5236    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5237    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5238    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5239    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5240    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5241    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5242    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5244    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5245    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5246    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5247    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5248    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5249    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5250    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5251    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5252    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5253    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5255    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5256    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5257    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5258    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5259    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5260    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5261    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5262    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5263    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5264    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5266    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5267    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5268    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5269    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5270    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5271    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5272    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5273    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5274    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5275    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5277    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5278    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5279    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5280    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5281    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5282    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5283    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5284    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5285    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5286    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5288    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5289    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5290    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5291    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5292    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5293    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5294    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5295    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5296    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5297    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5299    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5300    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5301    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5302    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5303    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5304    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5305    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5306    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5307    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5308    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5310    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5311    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5312    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5313    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5314    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5315    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5316    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5317    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5318    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5319    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5321    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5322    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5323    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5324    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5325    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5326    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5327    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5328    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5329    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5330    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5332    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5333    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5334    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5335    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5336    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5337    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5338    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5339    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5340    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5341    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5343    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5344    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5345    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5346    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5347    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5348    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5349    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5350    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5351    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5352    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5354    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5355    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5356    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5357    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5358    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5359    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5360    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5361    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5362    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5363    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5365    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5366    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5367    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5368    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5369    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5370    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5371    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5372    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5373    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5374    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5376    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5377    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5378    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5379    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5380    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5381    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5382    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5383    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5384    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5385    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5387    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5388    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5389    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5390    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5391    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5392    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5393    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5394    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5395    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5396    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5398    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5399    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5400    |  16|   0|   16|          0|
+    |p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_5401    |  16|   0|   16|          0|
+    |sX_4                                                                                      |  32|   0|   32|          0|
+    |sY_4                                                                                      |  32|   0|   32|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_70              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_71              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_72              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_73              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_74              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_75              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_76              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_77              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_78              |  16|   0|   16|          0|
+    |void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_79              |  16|   0|   16|          0|
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+    |Total                                                                                     |4742|   0| 4742|          0|
+    +------------------------------------------------------------------------------------------+----+----+-----+-----------+
+
+
+
+================================================================
+== Interface
+================================================================
+* Summary: 
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+|          RTL Ports         | Dir | Bits |  Protocol  |                               Source Object                               |    C Type    |
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+|ap_clk                      |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config25>|  return value|
+|ap_rst                      |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config25>|  return value|
+|ap_start                    |   in|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config25>|  return value|
+|ap_done                     |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config25>|  return value|
+|ap_idle                     |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config25>|  return value|
+|ap_ready                    |  out|     1|  ap_ctrl_hs|  compute_output_buffer_2d<array,array<ap_fixed<42,22,5,3,0>,32u>,config25>|  return value|
+|p_read                      |   in|    16|     ap_none|                                                                     p_read|        scalar|
+|p_read1                     |   in|    16|     ap_none|                                                                    p_read1|        scalar|
+|p_read2                     |   in|    16|     ap_none|                                                                    p_read2|        scalar|
+|p_read3                     |   in|    16|     ap_none|                                                                    p_read3|        scalar|
+|p_read4                     |   in|    16|     ap_none|                                                                    p_read4|        scalar|
+|p_read5                     |   in|    16|     ap_none|                                                                    p_read5|        scalar|
+|p_read6                     |   in|    16|     ap_none|                                                                    p_read6|        scalar|
+|p_read7                     |   in|    16|     ap_none|                                                                    p_read7|        scalar|
+|p_read8                     |   in|    16|     ap_none|                                                                    p_read8|        scalar|
+|p_read9                     |   in|    16|     ap_none|                                                                    p_read9|        scalar|
+|p_read10                    |   in|    16|     ap_none|                                                                   p_read10|        scalar|
+|p_read11                    |   in|    16|     ap_none|                                                                   p_read11|        scalar|
+|p_read12                    |   in|    16|     ap_none|                                                                   p_read12|        scalar|
+|p_read13                    |   in|    16|     ap_none|                                                                   p_read13|        scalar|
+|p_read14                    |   in|    16|     ap_none|                                                                   p_read14|        scalar|
+|p_read15                    |   in|    16|     ap_none|                                                                   p_read15|        scalar|
+|p_read16                    |   in|    16|     ap_none|                                                                   p_read16|        scalar|
+|p_read17                    |   in|    16|     ap_none|                                                                   p_read17|        scalar|
+|p_read18                    |   in|    16|     ap_none|                                                                   p_read18|        scalar|
+|p_read19                    |   in|    16|     ap_none|                                                                   p_read19|        scalar|
+|p_read20                    |   in|    16|     ap_none|                                                                   p_read20|        scalar|
+|p_read21                    |   in|    16|     ap_none|                                                                   p_read21|        scalar|
+|p_read22                    |   in|    16|     ap_none|                                                                   p_read22|        scalar|
+|p_read23                    |   in|    16|     ap_none|                                                                   p_read23|        scalar|
+|p_read24                    |   in|    16|     ap_none|                                                                   p_read24|        scalar|
+|p_read25                    |   in|    16|     ap_none|                                                                   p_read25|        scalar|
+|p_read26                    |   in|    16|     ap_none|                                                                   p_read26|        scalar|
+|p_read27                    |   in|    16|     ap_none|                                                                   p_read27|        scalar|
+|p_read28                    |   in|    16|     ap_none|                                                                   p_read28|        scalar|
+|p_read29                    |   in|    16|     ap_none|                                                                   p_read29|        scalar|
+|p_read30                    |   in|    16|     ap_none|                                                                   p_read30|        scalar|
+|p_read31                    |   in|    16|     ap_none|                                                                   p_read31|        scalar|
+|layer25_out_din             |  out|  1344|     ap_fifo|                                                                layer25_out|       pointer|
+|layer25_out_num_data_valid  |   in|     9|     ap_fifo|                                                                layer25_out|       pointer|
+|layer25_out_fifo_cap        |   in|     9|     ap_fifo|                                                                layer25_out|       pointer|
+|layer25_out_full_n          |   in|     1|     ap_fifo|                                                                layer25_out|       pointer|
+|layer25_out_write           |  out|     1|     ap_fifo|                                                                layer25_out|       pointer|
++----------------------------+-----+------+------------+---------------------------------------------------------------------------+--------------+
+

myproject_prj/solution1/syn/report/concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_csynth.xml

@@ -0,0 +1,312 @@
+<profile>
+
+<ReportVersion>
+<Version>2024.1</Version>
+</ReportVersion>
+
+<UserAssignments>
+<unit>ns</unit>
+<ProductFamily>virtexuplusHBM</ProductFamily>
+<Part>xcvu47p-fsvh2892-2L-e</Part>
+<TopModelName>concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s</TopModelName>
+<TargetClockPeriod>4.00</TargetClockPeriod>
+<ClockUncertainty>1.35</ClockUncertainty>
+<FlowTarget>vivado</FlowTarget>
+</UserAssignments>
+
+<PerformanceEstimates>
+<PipelineType>loop auto-rewind stp(delay=0 clock cycles(s))</PipelineType>
+<SummaryOfTimingAnalysis>
+<unit>ns</unit>
+<EstimatedClockPeriod>2.460</EstimatedClockPeriod>
+</SummaryOfTimingAnalysis>
+<SummaryOfOverallLatency>
+<unit>clock cycles</unit>
+<Best-caseLatency>4098</Best-caseLatency>
+<Average-caseLatency>4098</Average-caseLatency>
+<Worst-caseLatency>4098</Worst-caseLatency>
+<Best-caseRealTimeLatency>16.392 us</Best-caseRealTimeLatency>
+<Average-caseRealTimeLatency>16.392 us</Average-caseRealTimeLatency>
+<Worst-caseRealTimeLatency>16.392 us</Worst-caseRealTimeLatency>
+<Interval-min>4097</Interval-min>
+<Interval-max>4097</Interval-max>
+</SummaryOfOverallLatency>
+<SummaryOfLoopLatency>
+<ConcatLoopHeight_ConcatLoopWidth>
+<Slack>2.65</Slack>
+<TripCount>4096</TripCount>
+<Latency>4096</Latency>
+<AbsoluteTimeLatency>16384</AbsoluteTimeLatency>
+<PipelineII>1</PipelineII>
+<PipelineDepth>2</PipelineDepth>
+<InstanceList>
+</InstanceList>
+</ConcatLoopHeight_ConcatLoopWidth>
+</SummaryOfLoopLatency>
+<SummaryOfViolations>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_merge_stream.h:234</SourceLocation>
+<SummaryOfLoopViolations>
+<ConcatLoopHeight_ConcatLoopWidth>
+<Name>ConcatLoopHeight_ConcatLoopWidth</Name>
+<IssueType>-</IssueType>
+<ViolationType>-</ViolationType>
+<SourceLocation>firmware/nnet_utils/nnet_merge_stream.h:234</SourceLocation>
+</ConcatLoopHeight_ConcatLoopWidth>
+</SummaryOfLoopViolations>
+</SummaryOfViolations>
+</PerformanceEstimates>
+
+<AreaEstimates>
+<Resources>
+<FF>16</FF>
+<LUT>110</LUT>
+<BRAM_18K>0</BRAM_18K>
+<DSP>0</DSP>
+<URAM>0</URAM>
+</Resources>
+<AvailableResources>
+<BRAM_18K>4032</BRAM_18K>
+<DSP>9024</DSP>
+<FF>2607360</FF>
+<LUT>1303680</LUT>
+<URAM>960</URAM>
+</AvailableResources>
+</AreaEstimates>
+
+<InterfaceSummary>
+<RtlPorts>
+<name>ap_clk</name>
+<Object>concatenate3d_2&lt;array,array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config34&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_rst</name>
+<Object>concatenate3d_2&lt;array,array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config34&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_start</name>
+<Object>concatenate3d_2&lt;array,array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config34&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_done</name>
+<Object>concatenate3d_2&lt;array,array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config34&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_idle</name>
+<Object>concatenate3d_2&lt;array,array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config34&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>ap_ready</name>
+<Object>concatenate3d_2&lt;array,array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config34&gt;</Object>
+<Type>return value</Type>
+<Scope></Scope>
+<IOProtocol>ap_ctrl_hs</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer33_out_dout</name>
+<Object>layer33_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>256</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer33_out_num_data_valid</name>
+<Object>layer33_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer33_out_fifo_cap</name>
+<Object>layer33_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer33_out_empty_n</name>
+<Object>layer33_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer33_out_read</name>
+<Object>layer33_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_dout</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>128</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_num_data_valid</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_fifo_cap</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_empty_n</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer41_cpy2_read</name>
+<Object>layer41_cpy2</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer34_out_din</name>
+<Object>layer34_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>384</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer34_out_num_data_valid</name>
+<Object>layer34_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer34_out_fifo_cap</name>
+<Object>layer34_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>13</Bits>
+<Attribute>unknown</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer34_out_full_n</name>
+<Object>layer34_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>in</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+<RtlPorts>
+<name>layer34_out_write</name>
+<Object>layer34_out</Object>
+<Type>pointer</Type>
+<Scope></Scope>
+<IOProtocol>ap_fifo</IOProtocol>
+<IOConfig></IOConfig>
+<Dir>out</Dir>
+<Bits>1</Bits>
+<Attribute>control</Attribute>
+</RtlPorts>
+</InterfaceSummary>
+
+</profile>