cs/overview.md

001 — STACK OVERVIEW

Primordial Compute Stack v0.1

Created and Developed by Collin D. Weber

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The Central Claim

Autonomy is allowed only when HIR resonance remains stable under pressure. — README_OSF.md, Primordial OS HIR Runtime Prototype v0.1

The Primordial Compute Stack is a layered architecture for bounded autonomy governance — a system in which every computational action must pass through Honesty, Integrity, and Respect evaluation before it is permitted. The stack defines not just processing logic, but the memory, governance, and security layers that make bounded autonomy physically and computationally enforceable.

This overview describes the layers as they currently exist. It does not collapse the distinction between what is running code, what is a hardware specification, and what is a forward-looking architectural proposal. Those distinctions are explicit in each layer entry below.

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Layer Map

┌─────────────────────────────────────────────────────────────────────────────┐
│  LAYER IV — Resonant Access Memory (RAM)                        [PROVISIONAL]│
│  Primordial_RAM_Architecture_v0.1_Collin_D_Weber                            │
│  HIR-gated provenance-bound memory · 5-layer stack · Write Gate equation    │
│  Status: architectural specification. Not yet prototyped.                   │
├─────────────────────────────────────────────────────────────────────────────┤
│  LAYER III — GPU Parallel Compute Mapping                       [ARCH-MAP]  │
│  Primordial_HIR_SPU_GPU_Map.html                                            │
│  SIMT gate parallelism · warp-level H/I/R · Tensor core batch               │
│  Status: architectural translation of Layer II onto GPU compute model.      │
│  Not an implementation. No CUDA code produced.                              │
├─────────────────────────────────────────────────────────────────────────────┤
│  LAYER II — HIR Security Processing Unit (HIR-SPU / CPU)   [HARDWARE-SPEC] │
│  Primordial_HIR_SPU_Architecture_v0.1_Collin_D_Weber.zip                   │
│  Deterministic governance coprocessor · FPGA prototype spec                 │
│  SystemVerilog RTL · 30-register file · 14-instruction set                 │
│  Status: hardware architecture specification. Not fabricated.               │
│  FPGA implementation path defined; not yet executed.                        │
├─────────────────────────────────────────────────────────────────────────────┤
│  LAYER I-B — CyberSec Suite                                     [RUNNABLE]  │
│  Primordial_CyberSec_Suite_v0.1_Collin_D_Weber.zip                         │
│  Process/network/file-integrity collectors · HIR bridge                    │
│  Triage rules · Windows/Linux/macOS evidence collection                    │
│  Status: runnable Python prototype. Evidence bridge to HIR kernel.          │
├─────────────────────────────────────────────────────────────────────────────┤
│  LAYER I-A — OS HIR Runtime Prototype                           [RUNNABLE]  │
│  Primordial_OS_HIR_Runtime_Prototype_v0.1_Collin_D_Weber.zip               │
│  HIR Kernel · Diamond gates · Equation datapath · Audit log                │
│  24/24 tests passing · GREEN/YELLOW/RED routing verified                   │
│  Status: runnable Python prototype. Primary canonical artifact.             │
└─────────────────────────────────────────────────────────────────────────────┘
       ↑
  Foundation

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Layer Descriptions

Layer I-A — OS HIR Runtime Prototype [RUNNABLE] [CANONICAL]

The primary artifact. A runnable Python governance-kernel implementing the HIR equation stack as defined in the Primordial Calculus framework.

What it contains:

• hir/kernel.py — the central operating loop (§12 of the instruction set)
• hir/equations.py — the full equation datapath: B, P, S, U, Ξ, C, Θ, ΔD, D, Fidelity, Cohesion, Resonance
• gates/diamond.py — H, I, R gate evaluation (scores [0,1], hard-zero failure paths)
• gates/action.py — action packet schema
• audit/log.py — append-only SHA-256 hash-chained audit log
• hir/failure_modes.py — §18 failure mode detection (8 modes)
• Test suite: 24/24 passing, GREEN/YELLOW/RED routing confirmed

What it is not: a bootable OS, production infrastructure, or security-certified runtime.

Canonical source: OSF release package, SHA-256 85b9fdf9... (inner runtime zip)

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Layer I-B — CyberSec Suite [RUNNABLE]

A runnable cybersecurity evidence collection and HIR governance bridge.

What it contains:

• Host evidence collectors: process, network, file integrity, audit
• hir_bridge.py — translates security findings into HIR action packets
• triage_rules.json — rule class / severity mappings
• Windows (PowerShell), Linux, macOS collection scripts

What it is not: a production EDR, SIEM replacement, or certified security tool.

Relationship to Layer I-A: The CyberSec Suite produces normalized evidence packets that are consumed by the HIR Kernel. It is the host-side evidence layer; the HIR Kernel provides the governance layer. They are coupled through hir_bridge.py.

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Layer II — HIR-SPU Architecture [HARDWARE-SPEC]

A hardware architecture specification for a deterministic governance coprocessor.

What it contains:

• ARCHITECTURE_HIR_SPU_v0.1.md — complete architecture document
• specs/REGISTER_MAP.md — 30-register memory-mapped interface (0x00–0x74)
• specs/INSTRUCTION_SET.md — 14-instruction command set
• specs/FUNCTIONAL_SPEC.md, SAFETY_INVARIANTS.md, FIXED_POINT_PROFILE.md
• rtl/hir_spu_top.sv — SystemVerilog RTL scaffold (Q16.16 fixed-point arithmetic)
• rtl/hir_spu_pkg.sv — package definitions
• sim/test_vectors.json — simulation test vectors
• specs/PACKET_SCHEMAS.json, RULE_CLASS_MAP.json

What it is not: fabricated silicon. The RTL is a scaffold — architecture-verified, not manufacturing-verified. The FPGA implementation path is defined; not yet executed.

Relationship to Layer I-A: The HIR-SPU hardware specification is derived from the OS Runtime's Python kernel. The always_comb block in hir_spu_top.sv is a direct hardware translation of the evaluate_diamond() and equation functions in equations.py. The register file maps 1:1 to the kernel's input/output contract.

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Layer III — GPU Parallel Compute Mapping [ARCH-MAP]

An architectural translation of the HIR-SPU compute graph onto GPU/SIMT execution model.

What it contains:

• Primordial_HIR_SPU_GPU_Map.html — interactive architecture diagram

Key architectural finding: H, I, and R gates are fully independent (zero cross-dependency proven in the RTL always_comb block). The Pressure field P has zero dependency on gate results. This creates a natural 4-warp parallel front-end. The Resonance emergence chain (F → Cₑₘ → Rn) maps to 3 sequential SFU (Special Function Unit) sqrt operations.

What it is not: a CUDA implementation, a PTX program, or executable GPU code. This is an architectural mapping only. No GPU code has been written.

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Layer IV — Resonant Access Memory (RAM) [PROVISIONAL]

A forward-looking architectural specification for a HIR-gated, provenance-bound memory system.

What it contains:

• Primordial_RAM_Architecture_v0_1.html — interactive architecture diagram
• Primordial_RAM_Architecture_v0_1_Collin_D_Weber.docx — OSF-format specification document

Core architectural proposal:

• 5-layer memory stack: Working, Episodic, Semantic, Procedural, Integrity/Provenance
• Write Gate: W_i = Q_i × P_i × H_i × I_i × R_i (multiplicative, hard-zero on any axis failure)
• Memory Strength: M_{i,t+1} = M_{i,t} + α(U_i × Rel_i × Rn_i) − β(D_i + X_i)
• Recall Score: Recall_i(q) = Sim(q,i) × M_i × Rec_i × Trust_i
• 7-stage lifecycle: Capture → Normalize → HIR Gate → Weighting → Consolidation → Recall → Repair/Quarantine
• 8 safety invariants (MEM-INV-1 through MEM-INV-8)

What it is not: a running implementation. No Python prototype exists for this layer. The equations are proposed; they have not been computationally verified against a running system. The schema is defined; no datastore implements it.

Status: provisional. This layer is the forward-looking next step, not a completed artifact.

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Canonical Upstream Documents

Inside docs_canonical/:

Document	Status	Description
README_OSF.md	[CANONICAL]	Primary OSF release statement for the runtime prototype
HIR_Architecture_Specification_v1.0_Collin_D_Weber.md	[CANONICAL]	HIR framework applied as engineering specification
Primordial_OS_Baseline_Instruction_Set_v1.0_Collin_D_Weber.md	[CANONICAL]	Baseline instruction set; HIR/OAM boundary definition

These documents are upstream canonical source. They define the framework from which all hardware specifications and forward-looking layers are derived. Nothing in this bundle supersedes or modifies them.

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What The Stack Does Not Yet Have

For completeness, the following are identified in this overview as absent from v0.1:

• Fabricated hardware. The HIR-SPU RTL has not been synthesized to an FPGA or ASIC.
• GPU code. The GPU mapping is architectural; no CUDA/PTX implementation exists.
• RAM prototype. The memory architecture is specified; no running implementation exists.
• Formal verification. No formal proofs of the safety invariants have been produced.
• Cross-layer integration test. No test exercises all four layers end-to-end.
• Signed configuration loading. Defined in v1.0 roadmaps; not yet implemented.