docs/PROMPT_TEMPLATE_FOR_UI.txt

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 PROMPT TEMPLATE FOR GRADIO UI - Copy and Paste This
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📋 COPY THIS ENTIRE TEXT BLOCK BELOW:
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You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

User:
Generate a synchronous FIFO with 8-bit data width, depth 4, write_enable, read_enable, full flag, empty flag.

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📝 HOW TO USE IN GRADIO UI:
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1. Open: https://3833be2ce50507322f.gradio.live

2. Navigate to: "🧪 Test Inference" tab

3. Model Selection:
   - Model Source: Local Model
   - Model: /workspace/ftt/semicon-finetuning-scripts/mistral-finetuned-fifo1

4. Paste the prompt above into the "Prompt" textbox

5. Settings:
   - Max Length: 1024
   - Temperature: 0.7

6. Click: "🔄 Run Inference"

7. Wait ~5-10 seconds

8. View your generated Verilog code!


🎯 OTHER EXAMPLES YOU CAN TRY:
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Replace the "User:" line with any of these:

Example 1 (16-bit FIFO):
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You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

User:
Generate a synchronous FIFO with 16-bit data width, depth 16, write_enable, read_enable, full flag, empty flag.
────────────────────────────────────────────────────────────────────


Example 2 (32-bit FIFO):
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You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

User:
Generate a synchronous FIFO with 32-bit data width, depth 32, write_enable, read_enable, full flag, empty flag.
────────────────────────────────────────────────────────────────────


Example 3 (Custom FIFO):
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You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements.

User:
Generate a synchronous FIFO with 64-bit data width, depth 8, write_enable, read_enable, full flag, empty flag, almost_full flag, almost_empty flag.
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💡 QUICK TIPS:
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✓ ALWAYS include the full system instruction (the "You are Elinnos..." part)
✓ Keep the format: System instruction → "User:" → Your request
✓ For best results, use temperature 0.3-0.7
✓ Set max_length to 1024 for complete code generation
✓ The model was trained on this exact format, so stick to it!


⚙️ PARAMETER GUIDE:
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Temperature Settings:
  0.1 - 0.3  = Very deterministic, consistent output
  0.4 - 0.6  = Balanced between consistency and variety
  0.7 - 0.9  = More creative, varied outputs
  
Max Length:
  512   = Quick tests, short modules
  1024  = Standard FIFO modules (RECOMMENDED)
  2048  = Complex modules with multiple features
  4096  = Very large designs


🎉 YOU'RE READY TO GO!
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Your fine-tuned model is loaded and ready. Just copy the prompt
above, paste it into the Gradio UI, and click "Run Inference"!

Access: https://3833be2ce50507322f.gradio.live