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d8ff16a | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 | // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vsim.h for the primary calling header
#ifndef VERILATED_VSIM___024ROOT_H_
#define VERILATED_VSIM___024ROOT_H_ // guard
#include "verilated.h"
#include "verilated_timing.h"
class Vsim__Syms;
class alignas(VL_CACHE_LINE_BYTES) Vsim___024root final {
public:
// DESIGN SPECIFIC STATE
CData/*0:0*/ tb_full_adder__DOT__a;
CData/*0:0*/ tb_full_adder__DOT__b;
CData/*0:0*/ tb_full_adder__DOT__cin;
CData/*0:0*/ tb_full_adder__DOT__uut__DOT__sum;
CData/*0:0*/ tb_full_adder__DOT__uut__DOT__cout;
CData/*0:0*/ __VstlFirstIteration;
CData/*0:0*/ __VstlPhaseResult;
CData/*0:0*/ __VactPhaseResult;
CData/*0:0*/ __VinactPhaseResult;
CData/*0:0*/ __VnbaPhaseResult;
IData/*31:0*/ __VactIterCount;
IData/*31:0*/ __VinactIterCount;
IData/*31:0*/ __Vi;
VlUnpacked<QData/*63:0*/, 1> __VstlTriggered;
VlUnpacked<QData/*63:0*/, 1> __VactTriggered;
VlUnpacked<QData/*63:0*/, 1> __VactTriggeredAcc;
VlUnpacked<QData/*63:0*/, 1> __VnbaTriggered;
VlUnpacked<CData/*0:0*/, 3> __Vm_traceActivity;
VlDelayScheduler __VdlySched;
// INTERNAL VARIABLES
Vsim__Syms* vlSymsp;
const char* vlNamep;
// CONSTRUCTORS
Vsim___024root(Vsim__Syms* symsp, const char* namep);
~Vsim___024root();
VL_UNCOPYABLE(Vsim___024root);
// INTERNAL METHODS
void __Vconfigure(bool first);
};
#endif // guard
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