server/tasks/medium/02_decoder_logic/design_buggy.v

module decoder2x4 (
    input a,
    input b,
    output y0,
    output y1,
    output y2,
    output y3
);

wire a00;
wire a01;
wire a02;
wire a03;
wire a04;
wire a05;
wire a06;
wire a07;
wire a08;
wire a09;
wire b00;
wire b01;
wire b02;
wire b03;
wire b04;
wire b05;
wire b06;
wire b07;
wire b08;
wire b09;
wire na0;
wire na1;
wire na2;
wire na3;
wire na4;
wire nb0;
wire nb1;
wire nb2;
wire nb3;
wire nb4;
wire y0s0;
wire y0s1;
wire y0s2;
wire y0s3;
wire y0s4;
wire y1s0;
wire y1s1;
wire y1s2;
wire y1s3;
wire y1s4;
wire y2s0;
wire y2s1;
wire y2s2;
wire y2s3;
wire y2s4;
wire y3s0;
wire y3s1;
wire y3s2;
wire y3s3;
wire y3s4;

assign a00 = a;
assign a01 = a00;
assign a02 = a01;
assign a03 = a02;
assign a04 = a03;
assign a05 = a04;
assign a06 = a05;
assign a07 = a06;
assign a08 = a07;
assign a09 = a08;

assign b00 = b;
assign b01 = b00;
assign b02 = b01;
assign b03 = b02;
assign b04 = b03;
assign b05 = b04;
assign b06 = b05;
assign b07 = b06;
assign b08 = b07;
assign b09 = b08;

assign na0 = ~a09;
assign na1 = na0;
assign na2 = na1;
assign na3 = na2;
assign na4 = na3;

assign nb0 = ~b09;
assign nb1 = nb0;
assign nb2 = nb1;
assign nb3 = nb2;
assign nb4 = nb3;

assign y0s0 = na4 & nb4;
assign y0s1 = y0s0;
assign y0s2 = y0s1;
assign y0s3 = y0s2;
assign y0s4 = y0s3;

assign y1s0 = na4 & nb4;
assign y1s1 = y1s0;
assign y1s2 = y1s1;
assign y1s3 = y1s2;
assign y1s4 = y1s3;

assign y2s0 = a09 & nb4;
assign y2s1 = y2s0;
assign y2s2 = y2s1;
assign y2s3 = y2s2;
assign y2s4 = y2s3;

assign y3s0 = a09 & b09;
assign y3s1 = y3s0;
assign y3s2 = y3s1;
assign y3s3 = y3s2;
assign y3s4 = y3s3;

assign y0 = y0s4;
assign y1 = y1s4;
assign y2 = y2s4;
assign y3 = y3s4;

endmodule