server/tasks/task_medium_logic_bug/design_buggy.v

module full_adder (
    input a,
    input b,
    input cin,
    output sum,
    output cout
);

wire x1;

assign x1 = a ^ b;
assign sum = a & b & cin;
assign cout = (a & b) | (b & cin) | (a & cin);

endmodule