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| <section class="text-center py-16"> |
| <h1 class="text-5xl font-bold mb-6">HSPA Core Explorer</h1> |
| <p class="text-xl max-w-2xl mx-auto mb-10">Dive into the next-generation Probabilistic Semantic Processing Architecture</p> |
| <div class="flex justify-center gap-4"> |
| <a href="#architecture" class="bg-blue-600 hover:bg-blue-700 text-white font-bold py-3 px-6 rounded-lg transition duration-300">Explore Architecture</a> |
| <a href="#prototype" class="bg-purple-600 hover:bg-purple-700 text-white font-bold py-3 px-6 rounded-lg transition duration-300">View Prototype</a> |
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| <section id="architecture" class="py-16"> |
| <h2 class="text-3xl font-bold mb-8 text-center">System Architecture</h2> |
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| <i data-feather="cpu" class="w-12 h-12 mb-4 text-blue-400"></i> |
| <h3 class="text-xl font-bold mb-2">PMCU</h3> |
| <p>Probabilistic Microcontroller Unit with Bayesian scheduling</p> |
| </div> |
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| <h3 class="text-xl font-bold mb-2">RLC Fabric</h3> |
| <p>Reconfigurable Logic Cell array for parallel execution</p> |
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| <h3 class="text-xl font-bold mb-2">SEG Memory</h3> |
| <p>Semantic Execution Graph storage and management</p> |
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| <i data-feather="layers" class="w-12 h-12 mb-4 text-red-400"></i> |
| <h3 class="text-xl font-bold mb-2">UML</h3> |
| <p>Unified Memory Lattice with semantic tagging</p> |
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| <div class="bg-gray-800 bg-opacity-70 p-6 rounded-xl backdrop-blur-sm"> |
| <i data-feather="trending-up" class="w-12 h-12 mb-4 text-purple-400"></i> |
| <h3 class="text-xl font-bold mb-2">SOML</h3> |
| <p>Self-Optimizing Microcode Layer for adaptive performance</p> |
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| <h3 class="text-xl font-bold mb-2">MIT</h3> |
| <p>Meta-ISA Translator for legacy compatibility</p> |
| </div> |
| </div> |
| </section> |
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| <section id="prototype" class="py-16"> |
| <h2 class="text-3xl font-bold mb-8 text-center">Verilog Prototype</h2> |
| <div class="bg-gray-800 bg-opacity-70 rounded-xl p-8 backdrop-blur-sm"> |
| <div class="flex flex-wrap gap-4 mb-6"> |
| <button class="prototype-tab active" data-file="seg_memory.v">seg_memory.v</button> |
| <button class="prototype-tab" data-file="pmcu.v">pmcu.v</button> |
| <button class="prototype-tab" data-file="rlc.v">rlc.v</button> |
| <button class="prototype-tab" data-file="uml.v">uml.v</button> |
| <button class="prototype-tab" data-file="soml.v">soml.v</button> |
| <button class="prototype-tab" data-file="mit_translator.v">mit_translator.v</button> |
| <button class="prototype-tab" data-file="top.v">top.v</button> |
| </div> |
| <pre id="prototype-code" class="bg-gray-900 p-4 rounded-lg overflow-x-auto text-sm max-h-96"><code>// Loading prototype code...</code></pre> |
| </div> |
| </section> |
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| <section class="py-16"> |
| <h2 class="text-3xl font-bold mb-8 text-center">FPGA Carrier Board</h2> |
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| <div class="grid grid-cols-1 md:grid-cols-2 gap-8"> |
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| <h3 class="text-xl font-bold mb-4">Key Specifications</h3> |
| <ul class="space-y-2"> |
| <li class="flex items-center"> |
| <i data-feather="check-circle" class="w-5 h-5 mr-2 text-green-400"></i> |
| Xilinx Zynq UltraScale+ MPSoC ZU9EG |
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| <li class="flex items-center"> |
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| 2x 72-bit DDR4 ECC banks (up to 4GB) |
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| PCIe Gen3 x8 edge connector |
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| <li class="flex items-center"> |
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| 2x SFP+ cages (10GbE) |
| </li> |
| <li class="flex items-center"> |
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| FMC HPC connector for expansion |
| </li> |
| </ul> |
| </div> |
| <div> |
| <h3 class="text-xl font-bold mb-4">Features</h3> |
| <ul class="space-y-2"> |
| <li class="flex items-center"> |
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| Partial reconfiguration support |
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| PMBus power management |
| </li> |
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| Si5345 clock generation |
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| <li class="flex items-center"> |
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| Thermal management with fan control |
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| JTAG/UART debugging interface |
| </li> |
| </ul> |
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| </div> |
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