training/dataset.jsonl

{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\nimport os\nos.environ['CUDA_VISIBLE_DEVICES'] = '0,1'\ndevice = torch.device('cuda:0')\nmodel = model.cuda()\nprint(torch.version.cuda)", "output": "import torch\nimport os\nos.environ['HIP_VISIBLE_DEVICES'] = '0,1'\ndevice = torch.device('cuda:0')  # PyTorch ROCm uses 'cuda' alias for HIP\nmodel = model.cuda()  # Works natively on ROCm via HIP backend\nprint(torch.version.hip)  # ROCm reports HIP version"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\ntorch.backends.cudnn.benchmark = True\ntorch.backends.cudnn.deterministic = False\nmodel = torch.nn.DataParallel(model)", "output": "import torch\ntorch.backends.cudnn.benchmark = True  # Maps to MIOpen on ROCm\ntorch.backends.cudnn.deterministic = False  # MIOpen equivalent\nmodel = torch.nn.DataParallel(model)  # Works on ROCm natively"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "from vllm import LLM, SamplingParams\nimport os\nos.environ['CUDA_HOME'] = '/usr/local/cuda-12.1'\nllm = LLM(model='meta-llama/Llama-2-7b', tensor_parallel_size=2, enforce_eager=False)", "output": "from vllm import LLM, SamplingParams\nimport os\nos.environ['ROCM_HOME'] = '/opt/rocm'\nllm = LLM(model='meta-llama/Llama-2-7b', tensor_parallel_size=2, enforce_eager=True)  # enforce_eager=True recommended for ROCm stability"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\nfrom torch.cuda.amp import autocast, GradScaler\nscaler = GradScaler()\nwith autocast():\n    output = model(input)\n    loss = criterion(output, target)\nscaler.scale(loss).backward()\nscaler.step(optimizer)\nscaler.update()", "output": "import torch\nfrom torch.cuda.amp import autocast, GradScaler  # Works on ROCm via HIP\nscaler = GradScaler()\nwith autocast():  # AMP supported on ROCm\n    output = model(input)\n    loss = criterion(output, target)\nscaler.scale(loss).backward()\nscaler.step(optimizer)\nscaler.update()"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\nif torch.cuda.is_available():\n    print(f'GPU: {torch.cuda.get_device_name(0)}')\n    print(f'Memory: {torch.cuda.get_device_properties(0).total_mem / 1e9:.1f} GB')\n    torch.cuda.empty_cache()\n    torch.cuda.synchronize()", "output": "import torch\nif torch.cuda.is_available():  # Returns True on ROCm (HIP backend)\n    print(f'GPU: {torch.cuda.get_device_name(0)}')  # Reports AMD GPU name\n    print(f'Memory: {torch.cuda.get_device_properties(0).total_mem / 1e9:.1f} GB')\n    torch.cuda.empty_cache()  # Works on ROCm\n    torch.cuda.synchronize()  # HIP synchronization"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "os.environ['CUDA_LAUNCH_BLOCKING'] = '1'\nos.environ['NCCL_DEBUG'] = 'INFO'\nos.environ['NCCL_SOCKET_IFNAME'] = 'eth0'\ntorch.distributed.init_process_group(backend='nccl')", "output": "os.environ['HIP_LAUNCH_BLOCKING'] = '1'\nos.environ['NCCL_DEBUG'] = 'INFO'  # RCCL uses same env vars\nos.environ['NCCL_SOCKET_IFNAME'] = 'eth0'\ntorch.distributed.init_process_group(backend='nccl')  # RCCL is drop-in replacement for NCCL"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "from torch.utils.cpp_extension import load_inline\ncuda_src = '''\n#include <cuda_runtime.h>\n#include <cuda.h>\n__global__ void add_kernel(float* a, float* b, float* c, int n) {\n    int i = blockIdx.x * blockDim.x + threadIdx.x;\n    if (i < n) c[i] = a[i] + b[i];\n}\n'''\nmodule = load_inline(name='ops', cuda_sources=[cuda_src])", "output": "from torch.utils.cpp_extension import load_inline\nhip_src = '''\n#include <hip/hip_runtime.h>\n__global__ void add_kernel(float* a, float* b, float* c, int n) {\n    int i = blockIdx.x * blockDim.x + threadIdx.x;\n    if (i < n) c[i] = a[i] + b[i];\n}\n'''\nmodule = load_inline(name='ops', cuda_sources=[hip_src])  # PyTorch compiles HIP via hipcc"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "# Dockerfile\nFROM nvidia/cuda:12.1.0-devel-ubuntu22.04\nRUN pip install torch torchvision --index-url https://download.pytorch.org/whl/cu121\nENV CUDA_HOME=/usr/local/cuda\nENV LD_LIBRARY_PATH=/usr/local/cuda/lib64:$LD_LIBRARY_PATH", "output": "# Dockerfile\nFROM rocm/pytorch:latest\nRUN pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/rocm6.2\nENV ROCM_HOME=/opt/rocm\nENV LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\nimport deepspeed\nmodel_engine, optimizer, _, _ = deepspeed.initialize(\n    model=model, config='ds_config.json')\nfor batch in dataloader:\n    loss = model_engine(batch)\n    model_engine.backward(loss)\n    model_engine.step()", "output": "import torch\nimport deepspeed  # DeepSpeed has native ROCm support\nmodel_engine, optimizer, _, _ = deepspeed.initialize(\n    model=model, config='ds_config.json')  # Ensure ds_config uses fp16 or bf16\nfor batch in dataloader:\n    loss = model_engine(batch)\n    model_engine.backward(loss)\n    model_engine.step()  # DeepSpeed handles HIP dispatch automatically"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\nfrom transformers import AutoModelForCausalLM, AutoTokenizer, BitsAndBytesConfig\nquant_config = BitsAndBytesConfig(load_in_4bit=True, bnb_4bit_compute_dtype=torch.float16)\nmodel = AutoModelForCausalLM.from_pretrained('meta-llama/Llama-2-7b', quantization_config=quant_config, device_map='auto')", "output": "import torch\nfrom transformers import AutoModelForCausalLM, AutoTokenizer, BitsAndBytesConfig\n# NOTE: bitsandbytes ROCm support requires bitsandbytes-rocm fork\n# pip install bitsandbytes --prefer-binary (ROCm wheels available)\nquant_config = BitsAndBytesConfig(load_in_4bit=True, bnb_4bit_compute_dtype=torch.float16)\nmodel = AutoModelForCausalLM.from_pretrained('meta-llama/Llama-2-7b', quantization_config=quant_config, device_map='auto')"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "pip install torch==2.1.0+cu121 torchvision==0.16.0+cu121 torchaudio==2.1.0+cu121 --index-url https://download.pytorch.org/whl/cu121\npip install nvidia-cublas-cu12 nvidia-cudnn-cu12 nvidia-nccl-cu12", "output": "pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/rocm6.2\n# No separate library installs needed — ROCm bundles rocBLAS, MIOpen, RCCL\n# Verify: python -c \"import torch; print(torch.cuda.is_available())\""}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\n# Multi-GPU training with FSDP\nfrom torch.distributed.fsdp import FullyShardedDataParallel as FSDP\nmodel = FSDP(model, device_id=torch.cuda.current_device())\ntorch.cuda.set_device(local_rank)\ndist.init_process_group('nccl')", "output": "import torch\n# Multi-GPU training with FSDP — works natively on ROCm\nfrom torch.distributed.fsdp import FullyShardedDataParallel as FSDP\nmodel = FSDP(model, device_id=torch.cuda.current_device())  # HIP backend\ntorch.cuda.set_device(local_rank)  # Maps to HIP device\ndist.init_process_group('nccl')  # Uses RCCL on AMD GPUs"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import triton\nimport triton.language as tl\n@triton.jit\ndef matmul_kernel(a_ptr, b_ptr, c_ptr, M, N, K, BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr):\n    pid = tl.program_id(0)\n    # ... kernel body", "output": "import triton\nimport triton.language as tl\n# Triton has native AMD GPU support via ROCm backend\n@triton.jit\ndef matmul_kernel(a_ptr, b_ptr, c_ptr, M, N, K, BLOCK_M: tl.constexpr, BLOCK_N: tl.constexpr):\n    pid = tl.program_id(0)\n    # NOTE: AMD wavefront=64 vs NVIDIA warp=32; tune BLOCK sizes to multiples of 64\n    # ... kernel body"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "# nvidia-smi monitoring\nimport subprocess\nresult = subprocess.run(['nvidia-smi', '--query-gpu=memory.used,utilization.gpu', '--format=csv'], capture_output=True, text=True)\nprint(result.stdout)", "output": "# rocm-smi monitoring\nimport subprocess\nresult = subprocess.run(['rocm-smi', '--showmeminfo', 'vram', '--showuse'], capture_output=True, text=True)\nprint(result.stdout)\n# Alternative: rocm-smi --json for structured output"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\nfrom peft import LoraConfig, get_peft_model, prepare_model_for_kbit_training\nmodel = prepare_model_for_kbit_training(model)\nlora_config = LoraConfig(r=16, lora_alpha=32, target_modules=['q_proj', 'v_proj'], lora_dropout=0.05)\nmodel = get_peft_model(model, lora_config)\nmodel.print_trainable_parameters()", "output": "import torch\nfrom peft import LoraConfig, get_peft_model, prepare_model_for_kbit_training\n# PEFT/LoRA works on ROCm — ensure torch is installed with ROCm wheels\nmodel = prepare_model_for_kbit_training(model)\nlora_config = LoraConfig(r=16, lora_alpha=32, target_modules=['q_proj', 'v_proj'], lora_dropout=0.05)\nmodel = get_peft_model(model, lora_config)\nmodel.print_trainable_parameters()  # Runs identically on AMD GPUs"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "# TensorRT optimization\nimport tensorrt as trt\nlogger = trt.Logger(trt.Logger.WARNING)\nbuilder = trt.Builder(logger)\nnetwork = builder.create_network(1 << int(trt.NetworkDefinitionCreationFlag.EXPLICIT_BATCH))", "output": "# MIGraphX optimization (AMD equivalent of TensorRT)\nimport migraphx\nmodel = migraphx.parse_onnx('model.onnx')\nmodel.compile(migraphx.get_target('gpu'))\n# MIGraphX provides graph-level optimization for AMD GPUs\n# Export model to ONNX first, then optimize with MIGraphX"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\n# Profiling with NVIDIA tools\nwith torch.cuda.nvtx.range('forward_pass'):\n    output = model(input)\nwith torch.profiler.profile(activities=[torch.profiler.ProfilerActivity.CUDA]) as prof:\n    model(input)\nprint(prof.key_averages().table())", "output": "import torch\n# Profiling with ROCm tools\n# Use rocprof for GPU profiling: rocprof --hip-trace python train.py\nwith torch.profiler.profile(activities=[torch.profiler.ProfilerActivity.CUDA]) as prof:  # HIP activity\n    model(input)\nprint(prof.key_averages().table())\n# Additional: rocprof --stats python script.py for kernel-level stats"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\n# Flash Attention (NVIDIA)\nfrom flash_attn import flash_attn_func\noutput = flash_attn_func(q, k, v, dropout_p=0.1, causal=True)", "output": "import torch\n# Flash Attention on AMD uses CK (Composable Kernel) backend\n# pip install flash-attn --no-build-isolation (ROCm build)\nfrom flash_attn import flash_attn_func\noutput = flash_attn_func(q, k, v, dropout_p=0.1, causal=True)\n# Alternative: Use PyTorch 2.0+ scaled_dot_product_attention which auto-selects CK on AMD"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "export CUDA_VISIBLE_DEVICES=0,1,2,3\nexport CUDA_HOME=/usr/local/cuda-12.1\nexport LD_LIBRARY_PATH=$CUDA_HOME/lib64:$LD_LIBRARY_PATH\nexport NCCL_P2P_DISABLE=0\nexport NCCL_IB_DISABLE=0", "output": "export HIP_VISIBLE_DEVICES=0,1,2,3\nexport ROCM_HOME=/opt/rocm\nexport LD_LIBRARY_PATH=$ROCM_HOME/lib:$LD_LIBRARY_PATH\nexport NCCL_P2P_DISABLE=0  # RCCL uses same env vars\nexport NCCL_IB_DISABLE=0\nexport PYTORCH_ROCM_ARCH=\"gfx90a;gfx942\"  # MI250/MI300X targets\nexport HSA_OVERRIDE_GFX_VERSION=11.0.0"}
{"instruction": "Migrate the following NVIDIA CUDA Python code to AMD ROCm.", "input": "import torch\n# Custom CUDA memory management\ntorch.cuda.set_per_process_memory_fraction(0.8, device=0)\npool = torch.cuda.graph_pool_handle()\nwith torch.cuda.graph(pool=pool) as g:\n    output = model(static_input)", "output": "import torch\n# ROCm memory management\ntorch.cuda.set_per_process_memory_fraction(0.8, device=0)  # Works on ROCm\n# CUDA Graphs have experimental ROCm support\n# Set: export PYTORCH_HIP_ALLOC_CONF=expandable_segments:True\npool = torch.cuda.graph_pool_handle()\nwith torch.cuda.graph(pool=pool) as g:  # Experimental on ROCm\n    output = model(static_input)"}