chore: remove obsolete files and directories from the repository

POSTER_CONTENT.md

@@ -1,97 +0,0 @@
-# Research Poster Content: AgentIC & Defense Challenges
-
-## Title
-**AgentIC: Autonomous Sovereign Silicon Design Framework for Defense Applications**
-
-## Abstract
-Modern defense systems are critically dependent on advanced semiconductors. However, reliance on foreign EDA tools and fabrication supply chains introduces severe risks, including Hardware Trojans, backdoors, and strategic denial of technology. Validating the "Trust" in hardware is expensive and time-consuming. **AgentIC** is a novel, AI-driven "Text-to-Silicon" framework designed to democratize and accelerate the design of secure, sovereign silicon. By leveraging specialized coding Large Language Models (LLMs) like **Qwen Coder** and open-source EDA tools (OpenLane), AgentIC automates the RTL-to-GDSII flow, ensuring design secrecy and reducing the "Time-to-Tactical-Edge" for custom hardware solutions.
-
----
-
-## 1. Problem Statement: The Defense Silicon Gap
-
-### A. Supply Chain Vulnerability
-*   **Dependency:** Over 90% of advanced chips and EDA tools are controlled by non-domestic entities.
-*   **Risk:** In conflict scenarios, access to critical components can be cut off (Sanctions/Blockades).
-
-### B. Hardware Security Threats
-*   **Trojans:** Malicious logic inserted during design or fabrication (e.g., "Kill Switches" or data exfiltration backdoors).
-*   **Opaque IP:** Using closed-source "Black Box" IP cores makes it impossible to verify full security coverage.
-
-### C. Obsolescence & Agility
-*   **Legacy Systems:** Maintaining aging military hardware requires obsolete chips that are no longer manufactured.
-*   **Slow Development:** Traditional ASIC design cycles take 18-24 months, too slow for evolving asymmetric threats.
-
----
-
-## 2. Proposed Solution: The AgentIC Framework
-
-AgentIC serves as a **Sovereign Design Companion**, allowing defense engineers to generate verified, physically layout-ready silicon from high-level natural language specifications.
-
-### Key Pillars:
-1.  **AI-Agent Crew:** Specialized AI agents act as the Design Team (Architect, RTL Coder, Verification Engineer).
-2.  **Self-Correction:** Closed-loop feedback mechanism where agents fix their own compilation and simulation errors.
-3.  **Local & Resilient:** Support for on-premises LLM deployment (e.g., Qwen Coder on air-gapped servers) with **Robust Fallback** (Cloud → Local) to ensure operational continuity.
-4.  **Open Source Flow:** output is compatible with the OpenLane/SkyWater 130nm PDK, ensuring a fully auditable toolchain.
-
----
-
-## 3. Methodology & Architecture
-
-### The Workflow
-1.  **Prompt:** User inputs specs (e.g., *"Design a secure AES-256 accelerator with side-channel attack masking"*).
-2.  **Design Agent:** Generates SystemVerilog RTL.
-3.  **Verification Agent:** Generates a self-checking testbench (randomized stimuli + assertion checking).
-4.  **Simulation & Loop:** 
-    *   Runs `iverilog` simulation.
-    *   If fail: Agents read logs -> Patch Code -> Re-run.
-    *   If pass: Proceed to hardening.
-5.  **Physical Design:** Automates OpenLane scripts to generate GDSII.
-
-### Sovereign Tech Stack
-*   **Logic:** Custom AI Agents powered by **Qwen Coder** (Primary) / Llama 3 (Backup)
-*   **Simulation:** Icarus Verilog (Open Source)
-*   **Layout:** OpenLane (Open Source)
-*   **PDK:** SkyWater 130nm (Open Google/SkyWater)
-
----
-
-## 4. Addressing Defense Challenges (Analysis)
-
-| Challenge | AgentIC Solution |
-| :--- | :--- |
-| **IP Theft / Secrecy** | **Local Inference:** Prompts run on secure, air-gapped servers. No cloud APIs required. |
-| **Trojan Insertion** | **Auditable Code:** AI generates human-readable SystemVerilog, not binary blobs. Easier to review. |
-| **Rapid Field Deployment** | **Speed:** Reduces design-to-layout time from months to days for auxiliary chips. |
-| **Talent Shortage** | **Force Multiplier:** Allows non-expert systems engineers to create functional hardware blocks. |
-
----
-
-## 5. Case Study: Secure Processor Recovery
-
-**Experiment:** 
-We tasked AgentIC to design a "Secure Lockout Mechanism" for a processor (a common need for tamper-proof hardware).
-
-*   **Input:** "Create a state machine that locks the system after 3 failed 4-digit PIN attempts."
-*   **Result:**
-    1.  Agent generated an FSM (Finite State Machine) correctly handling transitions.
-    2.  Initial bug: Reset logic was inverted.
-    3.  **Auto-Fix:** Verification agent caught the timeout error, and the Designer agent corrected the polarity in `always_ff`.
-    4.  **Final Output:** Clean, LVS-clean GDSII layout ready for fabrication.
-
----
-
-## 6. Conclusion & Future Work
-
-AgentIC demonstrates that Generative AI can bridge the gap between secure requirements and physical silicon. By keeping the "Brain" of the design process local and using open tools, India can achieve true **Atmanirbhar** status in the strategic semiconductor sector. 
-
-**Future Roadmap:**
-*   Integration with formal verification tools for mathematical security proofs.
-*   Support for FPGA bitstream generation for rapid field updates.
-
----
-
-## References
-1.  *The OpenLane Project Documentation*
-2.  *Qwen Coder / Llama 3 Technical Reports*
-3.  *Defense Advanced Research Projects Agency (DARPA) POSH Program*

WEB_APP_GUIDE.md

@@ -1,439 +0,0 @@
-# AgentIC Web App — Complete Guide
-
-> **How the premium chip design web interface was built and how every piece fits together.**
-
----
-
-## Table of Contents
-
-1. [What Was Built](#what-was-built)
-2. [Architecture Overview](#architecture-overview)
-3. [Backend — `server/api.py`](#backend--serverapipy)
-4. [Orchestrator Hook — `src/agentic/orchestrator.py`](#orchestrator-hook--srcagenticorchestratorpy)
-5. [Frontend — `web/src/`](#frontend--websrc)
-6. [LLM Selection](#llm-selection)
-7. [Where Data Is Saved](#where-data-is-saved)
-8. [Training Data Auto-Export](#training-data-auto-export)
-9. [Cancel a Build](#cancel-a-build)
-10. [Running the App](#running-the-app)
-11. [API Reference](#api-reference)
-
----
-
-## What Was Built
-
-The original AgentIC was a **CLI-only tool**: you typed a command and watched logs scroll by. We transformed it into a full-stack web application with:
-
-| Feature | Description |
-|---|---|
-| **NLP Prompt UI** | Type a chip description in plain English, hit Launch |
-| **Live Build Monitor** | See every stage of the build pipeline in real-time as it runs |
-| **Cancel Button** | Stop a running build from the browser |
-| **Chip Summary** | After completion, view die area, WNS, power, gate count, RTL preview |
-| **Browser Notifications** | Get a popup when the build finishes, even if you've switched tabs |
-| **Training Auto-Export** | Every build is appended to a JSONL file for fine-tuning VeriReason |
-| **Claude-style Theme** | Warm off-white (#F7F4EF), terracotta accent (#C96442), zero neon |
-
----
-
-## Architecture Overview
-
-```
-┌─────────────────────┐         HTTP / SSE         ┌──────────────────────┐
-│  Browser (Vite UI)  │ ◄────────────────────────► │  FastAPI Backend      │
-│  localhost:5173     │                             │  localhost:8000       │
-│                     │                             │                       │
-│  DesignStudio.tsx   │  POST /build                │  _run_agentic_build() │
-│  BuildMonitor.tsx   │  GET  /build/stream/{id}    │  (background thread)  │
-│  ChipSummary.tsx    │  POST /build/cancel/{id}    │                       │
-│                     │  GET  /build/result/{id}    │  BuildOrchestrator    │
-└─────────────────────┘                             │  (orchestrator.py)    │
-                                                    └──────────────────────┘
-                                                             │
-                                                             ▼
-                                                    ~/OpenLane/designs/<name>/
-                                                    training/agentic_sft_data.jsonl
-```
-
-**Key concept: Server-Sent Events (SSE)**  
-Instead of the frontend constantly asking "are we done yet?", the backend *pushes* updates to the browser the moment they happen. This is called SSE (Server-Sent Events) — it's like a one-way live stream from server → browser over a normal HTTP connection.
-
----
-
-## Backend — `server/api.py`
-
-### The Job Store
-
-```python
-JOB_STORE: Dict[str, Dict[str, Any]] = {}
-```
-
-This is an **in-memory dictionary** that holds the state of every build job. Each entry looks like:
-
-```python
-{
-  "status": "running",          # queued | running | cancelling | done | failed | cancelled
-  "design_name": "my_counter",
-  "current_state": "RTL_GEN",  # current orchestrator stage
-  "events": [...],              # list of all events emitted so far
-  "result": {...},              # filled in at the end
-  "cancelled": False,           # cancel flag checked by the build thread
-  "created_at": 1709123456,
-}
-```
-
-> ⚠️ **The Job Store is in RAM only.** It resets when the server restarts. The actual chip files (RTL, GDSII, logs) are on disk in `~/OpenLane/designs/` and persist permanently.
-
----
-
-### `_get_llm()` — Smart LLM Selection
-
-```python
-def _get_llm():
-    configs = [
-        ("NVIDIA Nemotron Cloud", NEMOTRON_CONFIG),  # tries first
-        ("Backup GLM5 Cloud",     GLM5_CONFIG),       # second
-        ("VeriReason Local",      LOCAL_CONFIG),       # last resort
-    ]
-    for name, cfg in configs:
-        # skip cloud if no API key
-        # try to instantiate LLM
-        # return first one that works
-```
-
-This mirrors the exact same logic as the CLI's `get_llm()`. So when you click **Launch** in the browser, it uses **the same LLM priority** as running `python main.py build` from the terminal.
-
-With your `.env` file having `NVIDIA_API_KEY` set → it always picks **Nemotron Cloud first**.
-
----
-
-### `_emit_event()` — Pushing Events
-
-```python
-def _emit_event(job_id, event_type, state, message, step=0):
-    event = {"type": ..., "state": ..., "message": ..., "timestamp": ...}
-    JOB_STORE[job_id]["events"].append(event)
-```
-
-Every time something happens in the build (a state change, a log message, an error), this function is called. It appends a structured event to the job's event list. The SSE stream then picks these up and sends them to the browser.
-
-**Event types:**
-- `checkpoint` — an important milestone (e.g. "Starting RTL generation")
-- `transition` — the orchestrator moved to a new state (e.g. `RTL_GEN → VERIFICATION`)  
-- `log` — a regular log message
-- `error` — something went wrong
-- `done` / `stream_end` — build finished
-
----
-
-### `_run_agentic_build()` — Background Thread
-
-```python
-def _run_agentic_build(job_id, design_name, description, ...):
-    llm, llm_name = _get_llm()
-
-    def event_sink(event: dict):
-        # receives events from the orchestrator
-        _emit_event(job_id, ...)
-
-    orchestrator = BuildOrchestrator(
-        ...,
-        event_sink=event_sink,   # the live hook
-    )
-    orchestrator.run()
-
-    # after build finishes:
-    result = _build_result_summary(orchestrator, ...)
-    _export_training_record(...)  # save to JSONL
-```
-
-This runs in a **separate Python thread** (via `threading.Thread`) so the API doesn't block. When you call `POST /build`, it starts this thread immediately and returns `job_id` to the browser — the browser then connects to the SSE stream to receive live updates.
-
----
-
-### SSE Stream — `GET /build/stream/{job_id}`
-
-```python
-async def event_generator():
-    sent_index = 0
-    while True:
-        events = JOB_STORE[job_id]["events"]
-        while sent_index < len(events):
-            yield f"data: {json.dumps(events[sent_index])}\n\n"
-            sent_index += 1
-        if job["status"] in ("done", "failed", "cancelled"):
-            yield f"data: {json.dumps({'type': 'stream_end', ...})}\n\n"
-            break
-        await asyncio.sleep(0.4)   # poll every 400ms
-```
-
-The browser holds this connection open. Every 400ms the server checks if there are new events and sends them. When the build finishes, it sends a `stream_end` event and closes the connection.
-
----
-
-### Training Export — `_export_training_record()`
-
-```python
-record = {
-    "instruction": "Design a digital chip: <your prompt>",
-    "input": "<architecture spec>",        # chip spec written by the LLM
-    "output": "<RTL verilog code>",        # generated RTL
-    "success": True/False,
-    "metrics": {"wns": ..., "area": ...},
-    "build_log_excerpt": "...",            # first 8000 chars of build log
-    "source": "agentic_web_build",
-}
-# appended to: training/agentic_sft_data.jsonl
-```
-
-Every completed build (success or failure) is saved as one line in `training/agentic_sft_data.jsonl`. This is **SFT (Supervised Fine-Tuning) format** — exactly what `training/generate_reasoning.py` expects. You can use it to fine-tune VeriReason to get better at the kinds of chips you build.
-
----
-
-## Orchestrator Hook — `src/agentic/orchestrator.py`
-
-### What Changed
-
-Only **3 things** were added (all backward-compatible — the CLI is unaffected):
-
-**1. New `event_sink` parameter in `__init__`:**
-```python
-def __init__(self, ..., event_sink=None):
-    self.event_sink = event_sink  # None when called from CLI
-```
-
-**2. In `log()` — fires on every log message:**
-```python
-def log(self, message, refined=False):
-    # ... existing logging ...
-    if self.event_sink is not None:
-        self.event_sink({"type": "checkpoint" if refined else "log",
-                         "state": self.state.name, "message": message})
-```
-
-**3. In `transition()` — fires on every state change:**
-```python
-def transition(self, new_state):
-    # ... existing logic ...
-    if self.event_sink is not None:
-        self.event_sink({"type": "transition",
-                         "state": new_state.name, "message": f"▶ {new_state.value}"})
-```
-
-**Why this approach?** The orchestrator has 3000+ lines. Instead of rewriting it, we added a single "callback hook". When the orchestrator calls `self.log(...)` or `self.transition(...)`, the hook fires and sends the event to the web backend. The CLI never passes `event_sink`, so it gets `None` and nothing changes for existing CLI users.
-
----
-
-## Frontend — `web/src/`
-
-### Three-Phase Flow
-
-The UI works as a **state machine with 3 phases**:
-
-```
-Phase 1: prompt  ──►  Phase 2: building  ──►  Phase 3: done
-  (type desc)           (watch build)           (see results)
-```
-
-All managed in `DesignStudio.tsx` with a single `phase` state variable.
-
----
-
-### `DesignStudio.tsx` — The Controller
-
-This is the **parent component** that owns all state and coordinates the 3 phases.
-
-**Key state variables:**
-```typescript
-const [phase, setPhase] = useState('prompt');    // which screen to show
-const [jobId, setJobId] = useState('');          // the server-side job ID
-const [events, setEvents] = useState([]);        // all SSE events received
-const [jobStatus, setJobStatus] = useState('queued');
-const [result, setResult] = useState(null);      // final chip data
-```
-
-**How the SSE connection works:**
-```typescript
-const es = new EventSource(`http://localhost:8000/build/stream/${jobId}`);
-es.onmessage = (evt) => {
-    const data = JSON.parse(evt.data);
-    if (data.type === 'stream_end') {
-        // build finished — fetch full result
-        fetchResult(jobId, data.status);
-    } else {
-        setEvents(prev => [...prev, data]);  // add to the timeline
-    }
-};
-```
-
-`EventSource` is a **built-in browser API** — no extra library needed. It automatically reconnects if the connection drops.
-
----
-
-### `BuildMonitor.tsx` — The Live View
-
-Shows the **checkpoint timeline** (pipeline stages) and the **live terminal log**.
-
-**Checkpoint timeline logic:**
-- Loops through all 14 pipeline stages (INIT → SUCCESS)
-- If `state < currentState` → show green checkmark (done)
-- If `state === currentState` → show spinning ring (active)
-- If `state > currentState` → show empty circle (pending)
-
-**Cancel button:**
-```typescript
-const handleCancel = async () => {
-    await axios.post(`http://localhost:8000/build/cancel/${jobId}`);
-};
-```
-Sends a POST request to the backend, which sets `JOB_STORE[job_id]["cancelled"] = True`. The build thread checks this flag between orchestrator steps and exits gracefully.
-
-> **Note:** Python threads can't be killed mid-operation. The cancel takes effect **after the current step finishes**. If the LLM is in the middle of generating RTL, it will finish that generation, then stop before the next step.
-
----
-
-### `ChipSummary.tsx` — The Results Page
-
-Displays after the build completes:
-- **Silicon metrics** (WNS, die area, power, gate count) from `~/OpenLane/designs/<name>/runs/.../metrics.csv`
-- **Architecture spec** — the text spec the LLM wrote for your chip
-- **RTL preview** — first 1200 chars of the generated Verilog
-- **Convergence table** — WNS/TNS/congestion across OpenLane iterations
-- **Error details** — if the build failed
-
----
-
-### `index.css` — Claude-Inspired Theme
-
-The design tokens mirror Claude.ai's visual language:
-
-```css
-:root {
-  --bg:      #F7F4EF;   /* warm off-white parchment */
-  --accent:  #C96442;   /* Claude's terracotta orange */
-  --text:    #1A1817;   /* near-black ink */
-  --border:  #E2DDD7;   /* warm light grey */
-}
-```
-
-No neon, no glassmorphism, no glows. Cards have a 1px warm border and a soft `box-shadow`. Typography is Inter (same as Claude). The terminal inside the Build Monitor uses the dark theme (`var(--text)` background with `#D4CFC8` text) as a deliberate contrast island.
-
----
-
-## LLM Selection
-
-```
-Browser clicks "Launch"
-       │
-       ▼
-POST /build
-       │
-       ▼
-_get_llm() tries in order:
-  1. NVIDIA Nemotron  (if NVIDIA_API_KEY is set in .env)  ← your setup uses this
-  2. GLM5 Cloud       (if above fails)
-  3. VeriReason Local (last resort — Ollama at localhost:11434)
-       │
-       ▼
-BuildOrchestrator(llm=<chosen llm>, event_sink=...)
-```
-
-The first log line in the Build Monitor terminal will always say which LLM was selected:
-```
-🤖 LLM selected: NVIDIA Nemotron Cloud
-```
-
----
-
-## Where Data Is Saved
-
-| Data | Location | Persists after restart? |
-|---|---|---|
-| Job status & events | RAM (`JOB_STORE`) | ❌ No |
-| Chip RTL code | `~/OpenLane/designs/<name>/src/<name>.v` | ✅ Yes |
-| Testbench | `~/OpenLane/designs/<name>/src/<name>_tb.v` | ✅ Yes |
-| Build log | `~/OpenLane/designs/<name>/<name>.log` | ✅ Yes |
-| GDSII layout | `~/OpenLane/designs/<name>/runs/<run>/results/final/` | ✅ Yes |
-| Metrics CSV | `~/OpenLane/designs/<name>/runs/<run>/reports/metrics.csv` | ✅ Yes |
-| **Training JSONL** | `AgentIC/training/agentic_sft_data.jsonl` | ✅ Yes, appended |
-
----
-
-## Training Data Auto-Export
-
-After every build (success **or** failure), this record is appended to `training/agentic_sft_data.jsonl`:
-
-```jsonl
-{
-  "instruction": "Design a digital chip: 8-bit counter with synchronous reset",
-  "input": "# Architecture Spec\n## Module: counter\n...",
-  "output": "module counter (\n  input clk, rst_n, en,\n...",
-  "success": true,
-  "metrics": {"wns": "0.12", "area": "0.003 mm²", ...},
-  "build_log_excerpt": "[INIT] Initializing workspace\n[SPEC] ...",
-  "source": "agentic_web_build"
-}
-```
-
-**How to use it for fine-tuning VeriReason:**
-```bash
-# Existing script — reads training/agentic_sft_data.jsonl automatically
-python training/generate_reasoning.py
-
-# Then fine-tune
-python training/train_verireason.py
-```
-
-The format is **Alpaca-style SFT**: `instruction` + `input` + `output`. This is the standard format used by Unsloth, LLaMA-Factory, and most fine-tuning frameworks.
-
----
-
-## Cancel a Build
-
-**From the browser:** Click the **✕ Cancel** button in the Build Monitor header.
-
-**From the terminal:**
-```bash
-curl -X POST http://localhost:8000/build/cancel/<job_id>
-```
-
-**What happens:**
-1. Backend sets `JOB_STORE[job_id]["cancelled"] = True`
-2. The build thread checks this flag after each orchestrator step
-3. The thread exits, logs `"🛑 Build cancelled by user."`
-4. The SSE stream closes, the UI transitions to Phase 3 (results page) showing cancellation
-
----
-
-## Running the App
-
-**Backend** (port 8000):
-```bash
-source .venv-agentic/bin/activate
-python -m uvicorn server.api:app --host 0.0.0.0 --port 8000 --reload
-```
-
-**Frontend** (port 5173):
-```bash
-cd web
-node node_modules/vite/bin/vite.js --host 0.0.0.0 --port 5173
-```
-
-Open **http://localhost:5173** → you land directly on the Design Studio.
-
----
-
-## API Reference
-
-| Method | Endpoint | What it does |
-|---|---|---|
-| `POST` | `/build` | Start a build. Body: `{design_name, description, skip_openlane, full_signoff}`. Returns `{job_id}` |
-| `GET` | `/build/stream/{job_id}` | SSE stream of live build events |
-| `GET` | `/build/status/{job_id}` | Poll current status + all events |
-| `GET` | `/build/result/{job_id}` | Get final chip summary (only when done/failed) |
-| `POST` | `/build/cancel/{job_id}` | Request graceful cancellation |
-| `GET` | `/jobs` | List all jobs in the current session |
-| `GET` | `/designs` | List all chip designs on disk |
-| `GET` | `/signoff/{name}` | Run signoff check on an existing design |
-| `GET` | `/metrics/{name}` | Get OpenLane metrics for a design |
-| `GET` | `/` | Health check |

designs/simple_counter/config.tcl

@@ -1,27 +0,0 @@
-set ::env(DESIGN_NAME) "simple_counter"
-set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/simple_counter.v"
-
-# Die size 200um x 200um
-set ::env(DIE_AREA) "0 0 200 200"
-set ::env(FP_SIZING) absolute
-
-# Core utilization
-set ::env(FP_CORE_UTIL) 20
-set ::env(PL_TARGET_DENSITY) 0.3
-
-# Power Grid Settings
-set ::env(FP_PDN_VPITCH) 50
-set ::env(FP_PDN_HPITCH) 50
-set ::env(FP_PDN_VOFFSET) 5
-set ::env(FP_PDN_HOFFSET) 5
-
-# Power Pins / Voltage Sources
-set ::env(VDD_NETS) [list {vccd1}]
-set ::env(GND_NETS) [list {vssd1}]
-set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
-
-# Technology Setup
-set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
-set ::env(CLOCK_PORT) "clk"
-set ::env(CLOCK_PERIOD) "10.0"

designs/simple_counter/src/simple_counter.v

@@ -1,16 +0,0 @@
-module simple_counter (
-    input wire clk,
-    input wire rst_n,
-    input wire enable,
-    output reg [7:0] count
-);
-
-    always @(posedge clk or negedge rst_n) begin
-        if (!rst_n) begin
-            count <= 8'b0;
-        end else if (enable) begin
-            count <= count + 1'b1;
-        end
-    end
-
-endmodule

designs/simple_counter/src/simple_counter_tb.v

@@ -1,63 +0,0 @@
-`timescale 1ns / 1ps
-
-module simple_counter_tb;
-
-    // Inputs
-    reg clk;
-    reg rst_n;
-    reg enable;
-
-    // Outputs
-    wire [7:0] count;
-
-    // Instantiate the Unit Under Test (UUT)
-    simple_counter uut (
-        .clk(clk),
-        .rst_n(rst_n),
-        .enable(enable),
-        .count(count)
-    );
-
-    // Clock generation
-    initial begin
-        clk = 0;
-        forever #5 clk = ~clk; // 100MHz clock
-    end
-
-    // Test Sequence
-    initial begin
-        // Initialize Inputs
-        rst_n = 0;
-        enable = 0;
-
-        // Monitoring
-        $monitor("Time=%0t | rst_n=%b | enable=%b | count=%d", $time, rst_n, enable, count);
-
-        // Reset
-        #20;
-        rst_n = 1;
-        #20;
-
-        // Enable Counter
-        enable = 1;
-        #200;
-
-        // Disable Counter
-        enable = 0;
-        #50;
-
-        // Reset again
-        rst_n = 0;
-        #20;
-        
-        $display("TEST PASSED");
-        $finish;
-    end
-    
-    // Waveform dump for GTKWave
-    initial begin
-        $dumpfile("simple_counter.vcd");
-        $dumpvars(0, simple_counter_tb);
-    end
-
-endmodule

smart_nic_prompt.txt

@@ -1,13 +0,0 @@
-Design a high-performance networking chip for a smart NIC (Network Interface Card) with the following features:
-
-1. Packet Parser: Hardware module to parse Ethernet, IPv4/IPv6, TCP/UDP headers, and extract fields (src/dst MAC, IP, ports, protocol, flags, etc.) at line rate (≥100Gbps). Support programmable parsing rules for custom protocols.
-2. QoS Engine: Implement multi-queue packet scheduling with strict priority and weighted fair queuing (WFQ). Support per-flow rate limiting, traffic shaping, and dynamic queue mapping based on parsed header fields. Provide statistics counters for each queue and flow.
-3. Crypto Accelerator: Integrate a hardware crypto engine supporting AES-GCM (128/256), ChaCha20-Poly1305, and SHA-2 hashing. Enable inline encryption/decryption and authentication for selected flows, with key/context management and low-latency operation.
-4. AXI/PCIe Interface: Expose a high-bandwidth AXI or PCIe interface for DMA to host memory. Support descriptor-based packet I/O and interrupt coalescing.
-5. Control/Status: Provide a register interface for configuration (parsing rules, QoS policies, crypto keys), status monitoring, and error reporting.
-
-Constraints:
-- Target 28nm or 14nm process, area < 10mm², power < 2W.
-- Verilog RTL, synthesizable, with testbenches for all modules.
-- Formal verification for packet parser and crypto engine.
-- VCD waveform output for key scenarios.

tests/test_reliability_contracts.py

@@ -1,123 +0,0 @@
-import sys
-import contextlib
-import unittest
-from unittest import mock
-from pathlib import Path
-
-REPO_ROOT = Path(__file__).resolve().parents[1]
-SRC_ROOT = REPO_ROOT / "src"
-if str(SRC_ROOT) not in sys.path:
-    sys.path.insert(0, str(SRC_ROOT))
-
-from agentic.contracts import FailureClass, extract_json_object, infer_failure_class, validate_agent_payload
-from agentic.orchestrator import BuildOrchestrator, BuildState
-
-
-class ReliabilityContractsTest(unittest.TestCase):
-    def _make_orchestrator(self) -> BuildOrchestrator:
-        orch = BuildOrchestrator(
-            name="demo",
-            desc="demo design",
-            llm=object(),
-            verbose=False,
-        )
-        orch.logger = mock.Mock()
-        orch.state = BuildState.VERIFICATION
-        orch.artifacts["rtl_code"] = (
-            "module demo(input logic clk, input logic rst_n, output logic y);\n"
-            "assign y = clk;\n"
-            "endmodule\n"
-        )
-        orch.artifacts["rtl_path"] = "/tmp/demo.v"
-        return orch
-
-    def test_extract_json_object_from_fenced_text(self):
-        raw = 'noise\n```json\n{"class":"B","root_cause":"bad"}\n```\n'
-        parsed = extract_json_object(raw)
-        self.assertEqual(parsed, {"class": "B", "root_cause": "bad"})
-
-    def test_validate_agent_payload_missing_keys(self):
-        errors = validate_agent_payload({"class": "A"}, ["class", "root_cause"])
-        self.assertEqual(errors, ["Missing required key 'root_cause'."])
-
-    def test_infer_failure_class(self):
-        cls = infer_failure_class(
-            producer="llm_fixer",
-            raw_output="This is not valid json",
-            diagnostics=["Missing required key 'root_cause'."],
-        )
-        self.assertEqual(cls, FailureClass.LLM_FORMAT_ERROR)
-
-    def test_transition_resets_retry_count(self):
-        orch = self._make_orchestrator()
-        orch.retry_count = 3
-        orch.transition(BuildState.FORMAL_VERIFY)
-        self.assertEqual(orch.retry_count, 0)
-
-    def test_required_artifact_handoff_raises(self):
-        orch = self._make_orchestrator()
-        with self.assertRaises(RuntimeError):
-            orch._consume_handoff("tb_regen_context", consumer="VERIFICATION", required=True)
-
-    def test_parse_structured_agent_json_rejects_prose(self):
-        orch = self._make_orchestrator()
-        result = orch._parse_structured_agent_json(
-            agent_name="VerificationAnalyst",
-            raw_output="The issue is likely in the RTL.",
-            required_keys=["class", "root_cause"],
-        )
-        self.assertFalse(result.ok)
-        self.assertEqual(result.failure_class, FailureClass.LLM_FORMAT_ERROR)
-
-    def test_validate_rtl_candidate_rejects_hierarchy_rewrite(self):
-        orch = self._make_orchestrator()
-        previous = (
-            "module demo(input logic clk, output logic y); assign y = clk; endmodule\n"
-            "module demo_helper(input logic a, output logic b); assign b = a; endmodule\n"
-        )
-        candidate = "module demo(input logic clk, output logic y); assign y = clk; endmodule\n"
-        issues = orch._validate_rtl_candidate(candidate, previous)
-        self.assertTrue(any("module inventory" in issue for issue in issues))
-
-    def test_validate_tb_candidate_requires_waveform_and_name(self):
-        orch = self._make_orchestrator()
-        issues = orch._validate_tb_candidate("module wrong_tb; initial begin $finish; end endmodule")
-        self.assertTrue(any("TB module name" in issue for issue in issues))
-        self.assertTrue(any("dumpfile" in issue for issue in issues))
-
-    def test_tb_regen_context_bypasses_golden_tb(self):
-        orch = self._make_orchestrator()
-        orch.artifacts["golden_tb"] = "module counter_tb; endmodule"
-        orch.artifacts["golden_template"] = "counter"
-        orch._set_artifact(
-            "tb_regen_context",
-            '{"issue":"pin mismatch"}',
-            producer="test",
-            consumer="VERIFICATION",
-            required=True,
-            blocking=True,
-        )
-        generated_tb = """module demo_tb;
-initial begin
-    $dumpfile("demo_wave.vcd");
-    $dumpvars(0, demo_tb);
-    $display("TEST FAILED");
-    $display("TEST PASSED");
-    $finish;
-end
-endmodule
-"""
-
-        with mock.patch("agentic.orchestrator.get_testbench_agent", return_value=object()), \
-             mock.patch("agentic.orchestrator.Task", side_effect=lambda **kwargs: kwargs), \
-             mock.patch.object(orch, "_kickoff_with_timeout", return_value=generated_tb) as kickoff, \
-             mock.patch("agentic.orchestrator.console.status", return_value=contextlib.nullcontext()), \
-             mock.patch("agentic.orchestrator.write_verilog", return_value="/tmp/demo_tb.v"), \
-             mock.patch("agentic.orchestrator.run_tb_static_contract_check", side_effect=RuntimeError("stop_after_generation")):
-            with self.assertRaisesRegex(RuntimeError, "stop_after_generation"):
-                orch.do_verification()
-        self.assertTrue(kickoff.called)
-
-
-if __name__ == "__main__":
-    unittest.main()

tests/test_vlsi_tools_temp_paths.py

@@ -1,83 +0,0 @@
-import os
-import subprocess
-import sys
-import tempfile
-import unittest
-from pathlib import Path
-from unittest import mock
-
-
-REPO_ROOT = Path(__file__).resolve().parents[1]
-SRC_ROOT = REPO_ROOT / "src"
-if str(SRC_ROOT) not in sys.path:
-    sys.path.insert(0, str(SRC_ROOT))
-
-from agentic.tools import vlsi_tools
-
-
-class TempPathRewriteTests(unittest.TestCase):
-    def test_rewrite_temp_paths_replaces_absolute_and_basename_forms(self):
-        original = "/workspace/designs/counter8/src/counter8.v"
-        staged = "/tmp/tmpabc/counter8.v"
-        staged_map = {original: staged}
-
-        rewritten_abs = vlsi_tools._rewrite_temp_paths(
-            f"%Error: {staged}:12:3: syntax error",
-            staged_map,
-        )
-        rewritten_base = vlsi_tools._rewrite_temp_paths(
-            "%Error: counter8.v:12:3: syntax error",
-            staged_map,
-        )
-
-        self.assertIn(original, rewritten_abs)
-        self.assertIn(original, rewritten_base)
-        self.assertNotIn("/tmp/tmpabc", rewritten_abs)
-        self.assertNotIn("/tmp/tmpabc", rewritten_base)
-
-    def test_rewrite_result_paths_sanitizes_all_text_fields(self):
-        original = "/workspace/designs/counter8/src/counter8.v"
-        staged = "/tmp/tmpxyz/counter8.v"
-        staged_map = {original: staged}
-        payload = {
-            "stdout": f"warning in {staged}:4:1",
-            "stderr": "counter8.v:7:2: syntax error",
-            "diagnostics": [
-                f"%Error: {staged}:9:9: bad token",
-                "counter8.v:10:11: width warning",
-            ],
-        }
-
-        sanitized = vlsi_tools._rewrite_result_paths(payload, staged_map)
-
-        for text in [sanitized["stdout"], sanitized["stderr"], *sanitized["diagnostics"]]:
-            self.assertIn(original, text)
-            self.assertNotIn("/tmp/tmpxyz", text)
-
-    def test_run_syntax_check_returns_original_path_in_legacy_message(self):
-        with tempfile.TemporaryDirectory() as src_dir:
-            rtl_path = os.path.join(src_dir, "counter8.v")
-            with open(rtl_path, "w", encoding="utf-8") as f:
-                f.write("module counter8; endmodule\n")
-
-            seen = {}
-
-            def fake_run(cmd, capture_output, text, timeout, cwd=None):
-                seen["cwd"] = cwd
-                return subprocess.CompletedProcess(
-                    cmd,
-                    1,
-                    stdout="",
-                    stderr=f"%Error: {cwd}/counter8.v:12:3: syntax error\n",
-                )
-
-            with mock.patch("agentic.tools.vlsi_tools.subprocess.run", side_effect=fake_run):
-                ok, message = vlsi_tools.run_syntax_check(rtl_path)
-
-        self.assertFalse(ok)
-        self.assertIn(rtl_path, message)
-        self.assertNotIn(seen["cwd"], message)
-
-
-if __name__ == "__main__":
-    unittest.main()

verify_fixes.py

@@ -1,90 +0,0 @@
-import re
-import os
-import sys
-
-# Add src to path
-sys.path.append(os.path.abspath("src"))
-
-from agentic.tools import vlsi_tools
-
-def check_duplicates(file_path):
-    print(f"Checking for duplicates in {file_path}...")
-    with open(file_path, 'r') as f:
-        content = f.read()
-    
-    # Find all function definitions
-    funcs = re.findall(r'^def\s+(\w+)\s*\(', content, re.MULTILINE)
-    seen = set()
-    dupes = []
-    for f in funcs:
-        if f in seen:
-            dupes.append(f)
-        seen.add(f)
-    
-    if dupes:
-        print(f"FAILED: Found duplicate functions: {dupes}")
-        return False
-    print("PASSED: No duplicate functions found.")
-    return True
-
-def test_validate_rtl():
-    print("\nTesting validate_rtl_for_synthesis logic...")
-    
-    # Sample RTL with undriven signals (active high and low)
-    rtl = """
-    module test_module (
-        input clk,
-        input rst_n
-    );
-        reg [7:0] data_reg;
-        wire valid_signal;
-        wire [3:0] active_low_b;
-        wire enable_n;
-        
-        always @(posedge clk) begin
-            if (enable_n) begin
-                 data_reg <= 8'h00;
-            end
-        end
-        
-        assign valid_signal = 1'b1; // Driven
-        
-        // active_low_b is used in expression but not driven
-        wire check = &active_low_b; 
-    endmodule
-    """
-    
-    # Write to temp file
-    test_file = "temp_test.v"
-    with open(test_file, 'w') as f:
-        f.write(rtl)
-        
-    try:
-        fixed, report = vlsi_tools.validate_rtl_for_synthesis(test_file)
-        
-        with open(test_file, 'r') as f:
-            fixed_rtl = f.read()
-            
-        print(f"Report:\n{report}")
-        
-        # Checks
-        if "active_low_b = {4{1'b1}}" in fixed_rtl:
-            print("PASSED: active_low_b tied to 1s")
-        else:
-            print(f"FAILED: active_low_b fix incorrect. Content:\n{fixed_rtl}")
-            
-        if "enable_n = 1'b1" in fixed_rtl:
-            print("PASSED: enable_n tied to 1")
-        else:
-             print(f"FAILED: enable_n fix incorrect. Content:\n{fixed_rtl}")
-
-    finally:
-        if os.path.exists(test_file):
-            os.remove(test_file)
-
-if __name__ == "__main__":
-    vlsi_path = "src/agentic/tools/vlsi_tools.py"
-    if check_duplicates(vlsi_path):
-        test_validate_rtl()
-    else:
-        sys.exit(1)

web/README.md

@@ -1,73 +0,0 @@
-# React + TypeScript + Vite
-
-This template provides a minimal setup to get React working in Vite with HMR and some ESLint rules.
-
-Currently, two official plugins are available:
-
-- [@vitejs/plugin-react](https://github.com/vitejs/vite-plugin-react/blob/main/packages/plugin-react) uses [Babel](https://babeljs.io/) (or [oxc](https://oxc.rs) when used in [rolldown-vite](https://vite.dev/guide/rolldown)) for Fast Refresh
-- [@vitejs/plugin-react-swc](https://github.com/vitejs/vite-plugin-react/blob/main/packages/plugin-react-swc) uses [SWC](https://swc.rs/) for Fast Refresh
-
-## React Compiler
-
-The React Compiler is not enabled on this template because of its impact on dev & build performances. To add it, see [this documentation](https://react.dev/learn/react-compiler/installation).
-
-## Expanding the ESLint configuration
-
-If you are developing a production application, we recommend updating the configuration to enable type-aware lint rules:
-
-```js
-export default defineConfig([
-  globalIgnores(['dist']),
-  {
-    files: ['**/*.{ts,tsx}'],
-    extends: [
-      // Other configs...
-
-      // Remove tseslint.configs.recommended and replace with this
-      tseslint.configs.recommendedTypeChecked,
-      // Alternatively, use this for stricter rules
-      tseslint.configs.strictTypeChecked,
-      // Optionally, add this for stylistic rules
-      tseslint.configs.stylisticTypeChecked,
-
-      // Other configs...
-    ],
-    languageOptions: {
-      parserOptions: {
-        project: ['./tsconfig.node.json', './tsconfig.app.json'],
-        tsconfigRootDir: import.meta.dirname,
-      },
-      // other options...
-    },
-  },
-])
-```
-
-You can also install [eslint-plugin-react-x](https://github.com/Rel1cx/eslint-react/tree/main/packages/plugins/eslint-plugin-react-x) and [eslint-plugin-react-dom](https://github.com/Rel1cx/eslint-react/tree/main/packages/plugins/eslint-plugin-react-dom) for React-specific lint rules:
-
-```js
-// eslint.config.js
-import reactX from 'eslint-plugin-react-x'
-import reactDom from 'eslint-plugin-react-dom'
-
-export default defineConfig([
-  globalIgnores(['dist']),
-  {
-    files: ['**/*.{ts,tsx}'],
-    extends: [
-      // Other configs...
-      // Enable lint rules for React
-      reactX.configs['recommended-typescript'],
-      // Enable lint rules for React DOM
-      reactDom.configs.recommended,
-    ],
-    languageOptions: {
-      parserOptions: {
-        project: ['./tsconfig.node.json', './tsconfig.app.json'],
-        tsconfigRootDir: import.meta.dirname,
-      },
-      // other options...
-    },
-  },
-])
-```