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--- |
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model_name: AIDE-Chip-Surrogates |
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license: cc-by-nc-sa-4.0 |
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library_name: xgboost |
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pipeline_tag: tabular-regression |
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tags: |
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- computer-architecture |
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- gem5 |
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- cache |
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- surrogate-model |
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- explainable-ai |
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- shap |
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- monotonic-constraints |
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- systems-ml |
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datasets: |
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- uralstech/AIDE-Chip-15K-gem5-Sims |
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--- |
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# AIDE Chip Surrogates |
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This is a collection of physics-aware, monotonicity-constrained XGBoost models that replace expensive gem5 cache simulations during design-space exploration. |
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Each model predicts either IPC or L2 miss rate for a specific workload, using only cache configuration parameters as input. The models are interpretable via SHAP and enforce microarchitectural monotonicity where physically justified. |
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This model release accompanies the paper: |
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> Udayshankar Ravikumar . Fast, Explainable Surrogate Models for gem5 Cache Design Space Exploration. Authorea. January 14, 2026. |
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> <https://doi.org/10.22541/au.176843174.46109183/v1> |
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## Model Architecture |
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* Algorithm: XGBoost Regressor |
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* Targets: |
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* IPC |
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* L2 miss rate |
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* Features: |
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* Log₂ cache sizes & associativities |
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* Set-count proxies |
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* Cache hierarchy ratios |
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* Constraints: |
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* Monotonic constraints encoding cache physics |
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* Selective relaxation for latency-sensitive workloads |
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## Available Models |
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| Workload | IPC Model | L2 Miss Model | |
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| ---------- | --------- | ------------- | |
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| crc32 | ✔ | ✔ | |
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| dijkstra | ✔ | ✔ | |
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| fft | ✔ | ✔ | |
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| matrix_mul | ✔ | ✔ | |
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| qsort | ✔ | ✔ | |
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| sha | ✔ | ✔ | |
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Total models: **12** |
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## Performance |
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* Test set accuracy: **R² ≈ 0.999** |
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* OOD validation: |
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* 26 unseen cache configurations |
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* **~817× critical-path speedup** |
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* Low absolute error even when R² is unstable |
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## Explainability |
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Each model is uploaded with its SHAP summary plot. They confirm: |
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* Cache sizes dominate IPC & miss behavior |
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* Associativity effects are workload-dependent |
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* Learned relationships align with microarchitectural intuition |
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## Intended Use |
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* Architecture research |
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* Design-space exploration |
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* Educational use |
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* Explainable systems ML |
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**Not for commercial deployment** without separate licensing. |
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## Limitations |
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* Single-core, single-thread models |
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* Cache hierarchy only (no pipeline, prefetcher, or multicore effects) |
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* Accuracy depends on training coverage; extreme OOD configs are flagged |
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## Patent Notice |
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The models uploaded here implement techniques described in an accompanying research paper. |
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The author has filed a pending patent application that may cover broader |
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design-space exploration workflows beyond these specific model implementations. |
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The open-source license (CC BY-NC-SA 4.0) governs use of these models. |
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This notice is informational only. |
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