README.md

metadata

pipeline_tag: text-generation
library_name: transformers
license: apache-2.0
tags:
  - code-generation
  - verilog

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

This repository contains the SALV-Qwen2.5-Coder-7B-Instruct model, an advanced model for Verilog code generation presented in the paper QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation.

QiMeng-SALV introduces a novel framework for Verilog code generation that shifts reinforcement learning optimization from module-level to signal-level rewards. By leveraging Abstract Syntax Tree (AST) analysis and signal-aware verification, it extracts functionally correct code segments from partially incorrect modules, enabling more effective RL training. This method addresses the issue of insufficient functional rewards and achieves state-of-the-art performance on VerilogEval and RTLLM.

Resources

• Paper: https://huggingface.co/papers/2510.19296
• Project Page: https://zy1xxx.github.io/SALV
• Code: https://github.com/zy1xxx/SALV
• Dataset: https://huggingface.co/datasets/TabCanNotTab/SALV-dataset

Usage

You can use this model with the transformers library:

from transformers import AutoModelForCausalLM, AutoTokenizer
import torch
import re

model_name = "TabCanNotTab/SALV-Qwen2.5-Coder-7B-Instruct"
model = AutoModelForCausalLM.from_pretrained(
    model_name,
    torch_dtype=torch.bfloat16,
    device_map="auto",
)
tokenizer = AutoTokenizer.from_pretrained(model_name)

prompt = """
Please act as a professional verilog designer.

Implement a module of an 8-bit adder with multiple bit-level adders in combinational logic. 

Module name:  
    adder_8bit               
Input ports:
    a[7:0]: 8-bit input operand A.
    b[7:0]: 8-bit input operand B.
    cin: Carry-in input.
Output ports:
    sum[7:0]: 8-bit output representing the sum of A and B.
    cout: Carry-out output.

Implementation:
The module utilizes a series of bit-level adders (full adders) to perform the addition operation.

Give me the complete code.
"""

messages = [
    {"role": "system", "content": "You are a helpful assistant."},
    {"role": "user", "content": prompt}
]

text = tokenizer.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
model_inputs = tokenizer(text, return_tensors="pt").to(model.device)

# inference
outputs = model.generate(
    **model_inputs,
    max_new_tokens=2048,
    do_sample=True,
    temperature=0.5,
    top_p=0.95
)

# get response text
input_length = model_inputs.input_ids.shape[1]
generated_tokens = outputs[0][input_length:]
response = tokenizer.decode(generated_tokens, skip_special_tokens=True)

# get code text
pattern = r"```verilog\s*(.*?)\s*```"
matches = re.findall(pattern, response, re.DOTALL)
if matches:
    code=matches[-1]
    print(code)
else:
    print("No Verilog code found in the response!")

Citation

If you find QiMeng-SALV useful, please cite our paper:

@misc{zhang2025qimengsalvsignalawarelearningverilog,
  title={QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation}, 
  author={Yang Zhang and Rui Zhang and Jiaming Guo and Lei Huang and Di Huang and Yunpu Zhao and Shuyao Cheng and Pengwei Jin and Chongxiao Li and Zidong Du and Xing Hu and Qi Guo and Yunji Chen},
  year={2025},
  eprint={2510.19296},
  archivePrefix={arXiv},
  primaryClass={cs.LG},
  url={https://arxiv.org/abs/2510.19296}, 
}