repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
jakubcabal/pipemania-fpga-game | source/comp/video/cell_ctrl.vhd | 1 | 15927 | --------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: CELL_CTRL
-- AUTHORS: Jakub Cabal <xcabal05@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please read LI... | mit |
jeffmagina/ECE368 | Lab1/ALU/alu_arithmetic_unit.vhd | 1 | 1599 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool version... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/DEBUG_CONTROLLER.vhd | 2 | 2079 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:26:35 02/25/2015
-- Design Name:
-- Module Name: DEBUG_CONTROLLER - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... | mit |
gustavogarciautp/Procesador | Entrega 1/OMUXT.vhd | 3 | 434 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OMUXT is
Port ( Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
SEUimm: in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
oper2 : out STD_LOGIC_VECTOR (31 downto 0));
end OMUXT;
architecture Behavioral of OMUXT is
begin
process(... | mit |
KPU-RISC/KPU | VHDL/InstructionDecoder.vhd | 1 | 69353 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/23/2015 03:41:27 PM
-- Design Name:
-- Module Name: InstructionDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
--... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG_for lab/alu_shift_unit.vhd | 3 | 1193 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions:... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG_for lab/keyboard_controller.vhd | 8 | 2793 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/keyboard_controller.vhd | 8 | 2793 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keyboard Controller
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E... | mit |
gustavogarciautp/Procesador | Entrega 2/OMUXT_tb.vhd | 2 | 1427 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 dow... | mit |
KPU-RISC/KPU | VHDL/EnableCircuit.vhd | 1 | 1457 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 06:01:15 PM
-- Design Name:
-- Module Name: EnableCircuit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revi... | mit |
jeffmagina/ECE368 | Project1/EXECUTE/ALU/alu_toplevel.vhd | 1 | 2586 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xil... | mit |
gustavogarciautp/Procesador | Entrega 2/SEU.vhd | 3 | 389 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
SEUimm : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process(imm13)
begin
if imm13(12)='1' then
SEUimm<="1111111111111111111"&imm13;
else
SEUimm<=... | mit |
gustavogarciautp/Procesador | Entrega 3/SEU_tb.vhd | 2 | 914 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEU_tb IS
END SEU_tb;
ARCHITECTURE behavior OF SEU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)... | mit |
jeffmagina/ECE368 | Lab2/VGA Part 1/clk_tb.vhd | 1 | 2570 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/alu_toplevel.vhd | 3 | 2604 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versi... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG_for lab/alu_toplevel.vhd | 3 | 2604 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versi... | mit |
jeffmagina/ECE368 | Lab1/CounterTest/clk4Hz.vhd | 1 | 1421 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: ... | mit |
gustavogarciautp/Procesador | Entrega 2/ALU_tb.vhd | 1 | 7455 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
... | mit |
gustavogarciautp/Procesador | Entrega 1/OMUXT_tb.vhd | 1 | 1440 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 dow... | mit |
jeffmagina/ECE368 | Project1/RISC_MACHINE/RISC_MACHINE_tbd.vhd | 1 | 2471 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:46:18 04/07/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/RISC_MACHINE/RISC_MACHINE_tbd.vhd
-- Project Name: RISC_MACHINE
-- Target Device... | mit |
gustavogarciautp/Procesador | Entrega 2/PSRModifier.vhd | 1 | 1710 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSRModifier is
Port ( ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
NZVC : out ST... | mit |
gustavogarciautp/Procesador | Entrega 1/InstructionMemory.vhd | 1 | 3187 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is... | mit |
jeffmagina/ECE368 | Project1/RISC_MACHINE/RISC_MACHINE.vhd | 1 | 3308 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:23:34 03/25/2015
-- Design Name:
-- Module Name: RISC_MACHINE - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... | mit |
jeffmagina/ECE368 | Lab2/RISC Machine SSEG/load_store_unit.vhd | 3 | 1320 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions:... | mit |
laurivosandi/hdl | primitives/src/sr_latch_testbench.vhd | 1 | 717 | library ieee;
use ieee.std_logic_1164.all;
entity sr_latch_testbench is end sr_latch_testbench;
architecture behavioral of sr_latch_testbench IS
component sr_latch
port (
s : in std_logic;
r : in std_logic;
q_n : inout std_logic;
q : inou... | mit |
rodrigoazs/-7-5-Reed-Solomon | code/full_adder.vhd | 1 | 1029 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity fa is
Port ( a : in std... | mit |
rodrigoazs/-7-5-Reed-Solomon | code/symbol_multiplier.vhd | 1 | 2678 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolMultiplier is
port( u... | mit |
rodrigoazs/-7-5-Reed-Solomon | code/symbol_power_encoder.vhd | 1 | 819 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolPowerEncoder is
Po... | mit |
laurivosandi/hdl | zynq/src/bcd_segment_driver.vhd | 1 | 754 | library ieee;
use ieee.std_logic_1164.all;
entity bcd_segment_driver is
port (
bcd : in std_logic_vector(3 downto 0);
segments : out std_logic_vector(6 downto 0));
end;
architecture behavioral of bcd_segment_driver is
begin
segments <=
"1111110" when bcd = "0000" else -- 0
... | mit |
rajvinjamuri/ECE385_VHDL | reg_11.vhd | 1 | 2105 | ---------------------------------------------------------------------------
-- reg_11.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- ... | mit |
laurivosandi/hdl | zynq/src/ov7670_axi_stream_capture/ov7670_axi_stream_capture.vhd | 1 | 3774 | ----------------------------------------------------------------------------------
-- Authors: Mike Field <hamster@snap.net.nz>
-- Lauir Vosandi <lauri.vosandi@gmail.com>
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numer... | mit |
rajvinjamuri/ECE385_VHDL | game_handler.vhd | 1 | 2877 | ---------------------------------------------------------------------------
-- game_handler.vhd --
-- Raj Vinjamuri --
-- 4-13 --
-- --
... | mit |
rodrigoazs/-7-5-Reed-Solomon | code/reedsolomon.vhd | 1 | 5367 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomon is
end ReedSolo... | mit |
vhdlnerd/classicHp | src/classic.vhd | 1 | 38653 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... | mit |
vhdlnerd/classicHp | src/ps2_keyboard_pack.vhd | 1 | 18206 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... | mit |
vhdlnerd/classicHp | src/interface_ps2.vhd | 1 | 7858 | -- Hi Emacs, this is -*- mode: vhdl -*-
----------------------------------------------------------------------------------
-- Unidirectional PS2 Interface (device -> host)
-- For connect mouse/keyboard
--
-- The PS/2 mouse and keyboard implement a bidirectional synchronous serial
-- protocol. The bus is "idle" when b... | mit |
vhdlnerd/classicHp | src/ps2_keyboard.vhd | 1 | 5880 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... | mit |
vhdlnerd/classicHp | src/rom_pack.vhd | 1 | 172536 | ----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in... | mit |
Umesh8Joshi/VHDL-programs | Mux.vhdl | 1 | 600 | LIBRARY IEEE;
USE IEEE.std_logic_1164ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN std_logic;
PORT (q : OUT std_logic);
END mux;
ARCHITECTURE better OF mux IS
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
VARIABLE muxval : INTEGER;
BEGIN
muxval := 0;
IF (a = ‘1’) THEN
muxval := muxval + 1;
END IF;
IF ... | mit |
pkerling/Chips-Demo | source/reset_generator.vhd | 1 | 851 | library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic(
-- 20 ms at 125 MHz clock
-- Minimum 88E1111 reset pulse width: 10 ms
RESET_DELAY : positive := 2500000
);
port(
clock_i : in std_ulogic;
locked_i : in std_ulogic;
reset_o : out std_ulogic
);
end entity;
architecture rtl... | mit |
pkerling/Chips-Demo | source/chips_mac_adaptor.vhd | 1 | 5004 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ethernet_mac;
use ethernet_mac.ethernet_types.all;
use ethernet_mac.framing_common.all;
entity chips_mac_adaptor is
port(
-- Common clock for MAC and chips
clock_i : in std_ulogic;
reset_i : in std_ulogic;
-- MAC FI... | mit |
ssabogal/nocturnal | ip_repo/router/src/fifo.vhd | 2 | 2327 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
FIFO_WIDTH : positive := 10;
DATA_WIDTH : positive := 32
);
port (
-- clock and reset
CLOCK : in std_logic;
RESET : in std_logic;
-- fifo input interface
DAT_I : in std_logic_vector(D... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_0_0/sim/sys_router_0_0.vhd | 1 | 7447 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | ip_repo/nic_1.0/src/nic_v1_0_S00_AXI.vhd | 2 | 19933 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nic_v1_0_S00_AXI is
generic (
-- Users to add parameters here
USE_1K_NOT_4K_FIFO_DEPTH : boolean := true;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : in... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/bd/sys/hdl/sys.vhd | 1 | 297432 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Apr 15 17:28:28 2017
--Host : work running 64-bit Ubuntu 16.04.2 LTS
--... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_0/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_0_1/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_1/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_00_0/src/FIFO_32x1Kr/synth/FIFO_32x1Kr.vhd | 9 | 39107 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
kauecano/eel5105 | vhds/Cont_desc.vhd | 1 | 606 | library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
use IEEE.Std_Logic_arith.all;
entity Cont_desc is
port ( CLK1, rst, en: in std_logic;
S: out std_logic_vector(9 downto 0)
);
end Cont_desc;
architecture Cont_desc_estr of Cont_desc is
signal cont: std_logic_vector(9 downto 0):="111110... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/hdl/sys_wrapper.vhd | 1 | 3399 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Apr 15 18:53:53 2017
--Host : work running 64-bit Ubuntu 16.04.2 LTS
--... | mit |
kauecano/eel5105 | vhds/topo_reg.vhd | 1 | 876 | library ieee;
use ieee.std_logic_1164.all;
entity topo_reg is
port ( BTN0, C3, C2, C1, C0, CLOCK_50: IN STD_LOGIC;
REG: IN STD_LOGIC_VECTOR(19 downto 0);
SEQ_3, SEQ_2, SEQ_1, SEQ_0 : OUT STD_LOGIC_VECTOR(4 downto 0)
);
end topo_reg;
architecture topo_reg_arch of topo_reg is
component reg_5bits
port (
EN, CL... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_20_0/sim/sys_axi_nic_20_0.vhd | 1 | 9209 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd | 15 | 22231 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_00_0/synth/sys_axi_nic_00_0.vhd | 1 | 9482 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
kauecano/eel5105 | vhds/reg_5bits.vhd | 1 | 486 | library ieee;
use ieee.std_logic_1164.all;
entity reg_5bits is
port (EN, CLK, RST: in std_logic;
D: in std_logic_vector(4 downto 0);
Q: out std_logic_vector(4 downto 0)
);
end reg_5bits;
architecture bhv of reg_5bits is
begin
process(CLK, D)
begin
if RST = '0' then--reset assíncrono do registrador.
Q <... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd | 32 | 49938 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Us... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_20_0/src/FIFO_32x1K/synth/FIFO_32x1K.vhd | 9 | 39096 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_0/sim/sys_router_10_0.vhd | 1 | 9079 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ress/VHDL-Pong | Pong.vhd | 1 | 17042 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:18:30 07/14/2009
-- Design Name:
-- Module Name: Pong - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... | mit |
Tech-Curriculums/FPGA-101---Introduction-to-Verilog | digilent.adept.sdk_2.3.1/samples/depp/DeppDemo/logic/dpimref.vhd | 1 | 13748 | ----------------------------------------------------------------------------
-- DPIMREF.VHD -- Digilent Parallel Interface Module Reference Design
----------------------------------------------------------------------------
-- Author: Gene Apperson
-- Copyright 2004 Digilent, Inc.
----------------------------... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ipshared/9293/src/struct_out.vhd | 2 | 8698 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_out is
generic (
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(... | mit |
BerkeleyTrue/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_0_1/sim/sys_router_0_1.vhd | 1 | 8260 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_00_1/src/FIFO_32x4K/synth/FIFO_32x4K.vhd | 9 | 39096 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
briannkym/583final | Breakout/DCM.vhd | 1 | 2645 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... | mit |
rccoder/CPU-Summer-Term-HIT | chapter3/sreg.vhd | 1 | 1190 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:56 07/16/2015
-- Design Name:
-- Module Name: sreg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: ... | mit |
Beck-Sisyphus/EE471 | Lab4/simulation/modelsim/rtl_work/@instru@memory/_primary.vhd | 1 | 720 | library verilog;
use verilog.vl_types.all;
entity InstruMemory is
generic(
DATA_WIDTH : integer := 32;
DATA_LENGTH : integer := 128;
ADX_LENGTH : integer := 7
);
port(
clk : in vl_logic;
adx : in vl_logic_vector;
W... | mit |
rccoder/CPU-Summer-Term-HIT | chapter3/count4.vhd | 1 | 1226 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:39:15 07/16/2015
-- Design Name:
-- Module Name: count4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... | mit |
briannkym/583final | Breakout/src/Digit.vhd | 1 | 4689 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:31:01 11/18/2013
-- Design Name:
-- Module Name: Digit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... | mit |
rccoder/CPU-Summer-Term-HIT | CPU/clock.vhd | 1 | 1448 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:37:09 07/24/2015
-- Design Name:
-- Module Name: clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:... | mit |
Beck-Sisyphus/EE471 | Lab4/simulation/modelsim/rtl_work/addition/_primary.vhd | 1 | 453 | library verilog;
use verilog.vl_types.all;
entity addition is
port(
busADD : out vl_logic_vector(31 downto 0);
busA : in vl_logic_vector(31 downto 0);
busB : in vl_logic_vector(31 downto 0);
zADD : out vl_logic;
oADD ... | mit |
Beck-Sisyphus/EE471 | Lab4/work/mux2_1_testbench/_primary.vhd | 3 | 92 | library verilog;
use verilog.vl_types.all;
entity mux2_1_testbench is
end mux2_1_testbench;
| mit |
OgliariNatan/projetointegrador_II | D_7SEG/sevenSeg_decoder.vhd | 1 | 767 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sevenSeg_decoder IS
PORT
(
BCD_DATA: IN INTEGER;
SEG7_DATA: BUFFER STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevenSeg_decoder;
ARCHITECTURE behavior OF sevenSeg_decoder IS
BEGIN
PROCESS(BCD_DATA)
BEGIN
CASE (BCD_DATA) IS
WHEN 0 => SEG7_DATA <= "00... | mit |
briannkym/583final | Breakout/src/Sync.vhd | 1 | 1576 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Sync is
Port(
clk: in std_logic;
R_in, G_in, B_in : in std_logic_vector(3 downto 0);
x, y : out std_logic_vector(11 downto 0);
HSync, VSync: out std_logic;
R, G, B : out std_logic_vector(3 downto 0)
);
end Sync;
Architecture behavioral of Sy... | mit |
Beck-Sisyphus/EE471 | Lab4/simulation/modelsim/rtl_work/@instruc@decoder/_primary.vhd | 1 | 2132 | library verilog;
use verilog.vl_types.all;
entity InstrucDecoder is
generic(
nop : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi1, Hi1, Hi0, Hi0);
add : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, Hi0, Hi0, Hi0);
sub : vl_logic_vector(0 to 5) := (Hi1, Hi0, Hi0, ... | mit |
rccoder/CPU-Summer-Term-HIT | chapter3/serial.vhd | 1 | 2580 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:50 07/16/2015
-- Design Name:
-- Module Name: serial - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision... | mit |
rccoder/CPU-Summer-Term-HIT | CPU/write_back.vhd | 1 | 2544 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:34:39 07/28/2015
-- Design Name:
-- Module Name: write_back - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... | mit |
maikmerten/riscv-tomthumb | boards/de0-nano/vhdl/wizpll/wizpll_vga.vhd | 1 | 14872 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll_vga.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ========================================... | mit |
maikmerten/riscv-tomthumb | src/vhdl/spi/spirom_wb8.vhd | 1 | 2506 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spirom_wb8 is
Port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_O: out std_logic_vector(7 dow... | mit |
maikmerten/riscv-tomthumb | src/vhdl/spi/spiromram_wb8.vhd | 1 | 4621 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spiromram_wb8 is
generic(
ADDRLEN: integer := 12
);
port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_lo... | mit |
maikmerten/riscv-tomthumb | src/vhdl/attic/ram_init.vhd | 1 | 537 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package ram_init is
constant ADDRLEN : integer := 12; -- bits for number of 32 bit words in memory
type store_t is array(0 to (2**ADDRLEN)-1) of std_logic_vector(31 downto 0);
constant RAM_INIT : store_t := (
-- slow binary LED counter loop.s
X"b... | mit |
jpcofr/PDUAMaude | PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/pdua.vhdl | 1 | 5038 | -- *******************************************************
-- ** PDUA **
-- ** PROCESADOR DIDACTICO **
-- ** Arquitectura y Diseno de Sistemas Digitales **
-- ** UNIVERSIDAD DE LOS ANDES **
-- **********************... | mit |
maikmerten/riscv-tomthumb | src/vhdl/cpu/bus_wb8_tb.vhd | 1 | 4670 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_wb8_tb is
end bus_wb8_tb;
architecture Behavior of bus_wb8_tb is
component bus_wb8
Port(
I_en: in std_logic;
I_op: in busops_t; -- memory opcodes
I_addr: in std_logic_vector(31 downto 0)... | mit |
maikmerten/riscv-tomthumb | src/vhdl/ram/bus_ram_toplevel_tb.vhd | 1 | 3335 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_ram_toplevel_tb is
end bus_ram_toplevel_tb;
architecture Behavior of bus_ram_toplevel_tb is
component bus_ram_toplevel
Port(
I_clk: in std_logic;
I_reset: in std_logic;
I_en: in std_logi... | mit |
maikmerten/riscv-tomthumb | src/vhdl/cpu/registers.vhd | 1 | 1437 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity registers is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_op: in regops_t;
I_selS1: in std_logic_vector(4 downto 0);
I_selS2: in std_logic_vector(4 downto 0);
I_selD: in std_logic_vector(... | mit |
maikmerten/riscv-tomthumb | src/vhdl/cpu/bus_wb8.vhd | 1 | 4822 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_wb8 is
Port(
-- wired to CPU core
I_en: in std_logic;
I_op: in busops_t; -- bus opcodes
I_addr: in std_logic_vector(31 downto 0); -- address
I_data: in std_logic_vector(31 downto 0); -- dat... | mit |
miree/vhdl_cores | fifo/fifo_passive_out/testbench.vhd | 2 | 3978 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- package with component to test on this testbench
use work.fifo_pkg.all;
use work.guarded_fifo_pkg.all;
entity testbench is
end entity;
architecture simulation of testbench is
-- clock generation
constant clk_period : time := 5 ns;
-- sig... | mit |
miree/vhdl_cores | wishbone/wbp_mux.vhd | 1 | 8381 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S S
-- |/
-- M
entity wbp_2s1m is
port (
clk_i : in std_logic;
slaves_i : in t_wbp_slave_in_array(0 to 1);
slaves_o : out t_wbp_slave_out_array(0 to 1);
master_o : out t_wbp_master_out;
master_i : in t_wbp... | mit |
miree/vhdl_cores | uart/uart.vhd | 1 | 8780 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pkg is
type t_uart_parallel is record
dat : std_logic_vector(7 downto 0);
stb : std_logic;
stall : std_logic;
end record;
constant c_uart_parallel_init : t_uart_parallel := ((others => '0'), others => '0');
end package;
pac... | mit |
jpcofr/PDUAMaude | PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/ALU.vhdl | 1 | 2643 | -- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: ALU **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- AL... | mit |
rbaummer/UART | mixed_clock_fifo_regbased.vhd | 1 | 6039 | --------------------------------------------------------------------------------
--
-- File: Mixed-Clock FIFO - Register Based
-- Author: Rob Baummer
--
-- Description: A mixed clock FIFO using registers targeting small FIFOs. Based
-- on T. Chelcea, S. Nowick, A Low-Latency FIFO for Mixed-Clock Systems.
-- NOTE: Ra... | mit |
notti/schaltungstechnik_vertiefung | Assignement/Task2/uart_receive.vhd | 1 | 3562 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:34 10/01/2013
-- Design Name:
-- Module Name: uart_receive - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... | mit |
notti/schaltungstechnik_vertiefung | Assignement/Task5/clk_res_gen.vhd | 2 | 907 |
library ieee;
use ieee.std_logic_1164.all;
entity clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end entity clk_res_gen;
architecture RTL of clk_res_gen is
begin
-- This process generates a 50MHz clock signal
p_clk_generate : process
begin
while TRUE loop
clk_50 <= '0';
wai... | mit |
notti/schaltungstechnik_vertiefung | Assignement/Task2/uart_transmit.vhd | 1 | 2568 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:53 10/01/2013
-- Design Name:
-- Module Name: uart_transmit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... | mit |
notti/schaltungstechnik_vertiefung | Assignement/Task2/clock_gen.vhd | 1 | 3186 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:04:12 10/01/2013
-- Design Name:
-- Module Name: clock_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... | mit |
notti/schaltungstechnik_vertiefung | Assignement/Task4/toplevel.vhd | 1 | 5449 | library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port(
-- input pins
IN_clk_50 : in std_logic;
IN_rst : in std_logic;
IN_RotA : in std_logic;
IN_RotB : in std_logic;
IN_RotPush : in std_logic;
-- output pins
OUT_LED_ch0 : out std_logic := '0';
OUT_LED_ch1 : out st... | mit |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais | PBL_3/A.vhd | 1 | 4757 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: A.vhd
-- Megafunction Name(s):
-- altaccumulate
--
-- Simulation Library Files(s):
-- altera_mf
-- ================... | mit |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais | PBL_3/Comparador17.vhd | 1 | 4810 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: Comparador17.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- =============================... | mit |
mwpastore/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
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