repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
notti/schaltungstechnik_vertiefung | Assignement/Task1/enable.vhd | 1 | 1248 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
e... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/benchmark/pwm.vhd | 15 | 1069 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/svga_hello_world/serial_out.vhd | 23 | 3390 | --------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/knight_rider/serial_out.vhd | 23 | 3390 | --------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
---------... | mit |
dawsonjon/Chips-Demo | demo/bsp/nexys_4/bsp.vhd | 15 | 24719 | -------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
---------------------------... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/seven_segment/bsp.vhd | 15 | 24719 | -------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
---------------------------... | mit |
dawsonjon/Chips-Demo | demo/bsp/atlys/bsp.vhd | 1 | 21809 | --------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- BSP for Digilent Atlys
---
---------... | mit |
HSCD-SS16/HSCD-SS16 | VHDL/FDSx2.vhd | 1 | 775 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FDSx2 IS
PORT(D : IN std_ulogic; -- data input
Q : OUT std_ulogic; -- data output
S : IN std_ulogic; -- preset, high active
C : IN std_ulogic); -- clock, rising edge active
END FDSx2;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
ARCHIT... | mit |
HSCD-SS16/HSCD-SS16 | Aufgabe1/software/ROM_form.vhd | 6 | 12443 | ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/temperature/serial_in.vhd | 20 | 4970 | --------------------------------------------------------------------------------
---
--- SERIAL INPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Component
---
-----------... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/knight_rider/svga_timing_gen.vhd | 15 | 5488 | -- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/image_processor/svga_timing_gen.vhd | 15 | 5488 | -- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- *****************************************************... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/svga_hello_world/pwm_audio.vhd | 15 | 1817 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/raw_ethernet/pwm_audio.vhd | 15 | 1817 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/raw_ethernet/rmii_ethernet.vhd | 15 | 25834 | --------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: chips@jondawson.org.uk
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
---------------------... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/temperature/svga_core.vhd | 15 | 4875 | -- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/tri_color/svga_core.vhd | 15 | 4875 | -- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/image_processor/svga_core.vhd | 15 | 4875 | -- ****************************************************************************
-- Filename :svga_core.vhd
-- Project :VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ********************************************************************... | mit |
dawsonjon/Chips-Demo | demo/bsp/atlys/keyboard.vhd | 16 | 2713 | -- ****************************************************************************
-- Filename :keyboard.vhd
-- Project :Wishbone SOC
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2006-04-14
-- *****************************************************************... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/svga_hello_world/keyboard.vhd | 16 | 2713 | -- ****************************************************************************
-- Filename :keyboard.vhd
-- Project :Wishbone SOC
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2006-04-14
-- *****************************************************************... | mit |
HSCD-SS16/HSCD-SS16 | Aufgabe3/VHDL/insertsort.vhd | 1 | 3241 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY insertsort IS
GENERIC(RSTDEF: std_logic := '1');
PORT(rst: IN std_logic; -- reset, RSTDEF active
clk: IN std_logic; -- clock, rising edge active
-- interface to PicoBlaze
rsel: IN std_logic_vector(7 DOWNTO 0); -- registe... | mit |
onkelthomas/HW_SW_LU_Gr3_2015 | template/template/vhdl/common/synchronizer/sync.vhd | 2 | 782 | library ieee;
use ieee.std_logic_1164.all;
entity sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end entity sync;... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/hello_world/bram.vhd | 15 | 847 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out ... | mit |
onkelthomas/HW_SW_LU_Gr3_2015 | template/template/vhdl/textmode_controller/font_rom_beh.vhd | 2 | 2047 | ----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Thomas Polzer --
-- ... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/keyboard/i2c.vhd | 15 | 8318 | --- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 =... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/enigma_machine/i2c.vhd | 15 | 8318 | --- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 =... | mit |
dawsonjon/Chips-Demo | synthesis/nexys_4/benchmark/i2c.vhd | 15 | 8318 | --- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 =... | mit |
mikeek/FIT | INC/proj_1/fsm.vhd | 1 | 8367 | -- fsm.vhd: Finite State Machine
-- Author(s):
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity fsm is
port(
... | mit |
16-bit-risc/16-bit-risc | vhdl/dcd3x8.vhd | 4 | 539 | -- DCD3x8
-- 3-to-8 decoder
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity dcd3x8 is
port(en : in std_logic_vector(2 downto 0);
de : out std_logic_vector(7 downto 0)
);
end dcd3x8;
architecture logic of dcd3x8 is
begin
with en select de <= "00000001" when "000",
"0... | mit |
glenux/contrib-linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
16-bit-risc/16-bit-risc | vhdl/sgnext6x16.vhd | 4 | 341 | library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity sgnext6x16 is
port (DIN : in std_logic_vector(5 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end sgnext6x16;
architecture Logic of sgnext6x16 is
begin
DOUT<=DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DIN(5)&DI... | mit |
0a-/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
agural/AVR-Processor | src/AVR/opcodes.vhd | 1 | 7639 | -----------------------------------------------------------------------------
--
-- AVR opcode package
--
-- This package defines opcode constants for the complete AVR instruction
-- set. Not all variants of the AVR implement all instructions.
--
-- Revision History
-- 4/27/98 Glen George initial revision
... | mit |
AndyMcC0/UVVM_All | uvvm_vvc_framework/src/ti_data_stack_pkg.vhd | 3 | 8489 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | bitvis_irqc/src/irqc.vhd | 3 | 3092 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | uvvm_util/src/types_pkg.vhd | 1 | 6000 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | bitvis_irqc/tb/irqc_tb.vhd | 1 | 20216 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | uvvm_util/src/hierarchy_linked_list_pkg.vhd | 1 | 41905 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | uvvm_util/src/uvvm_util_context.vhd | 1 | 1596 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
Wynjones1/gbvhdl | src/common.vhd | 1 | 4491 | library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use work.types.all;
package common is
-- impure function init_mem(input_file : in string) return
function r_table(input : std_logic_vector(2 downto 0)) return register_t;
function d_table(input : std_logic_vector(1 downto 0)) return register_t;... | mit |
AndyMcC0/UVVM_All | bitvis_vip_uart/src/uart_rx_vvc.vhd | 1 | 16486 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit |
JackyRen/vimrc | template/vhdl/basic.vhd | 1 | 304 | LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE work.GlobalDefines.ALL;
entity <name> is
port(
);
end <name>;
architecture bhv of <name> is
component <bla> is
port(
);
end component;
begin
end bhv;
| mit |
kiwih/subleq-vhdl | clk_div.vhd | 1 | 580 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_div is
generic(
CLOCK_DIVIDE : integer := 5000000
);
port (
CLK_50: in std_logic;
CLK_SLOW: out std_logic
);
end entity clk_div;
architecture beh of clk_div is
begin
-- clk_out <= clk_in;
process (CLK_50)
variable count: integer... | mit |
AndyMcC0/UVVM_All | uvvm_util/src/methods_pkg.vhd | 1 | 237364 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit |
AndyMcC0/UVVM_All | bitvis_vip_spi/src/vvc_cmd_pkg.vhd | 1 | 7098 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | bitvis_vip_sbi/src/sbi_bfm_pkg.vhd | 1 | 32317 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... | mit |
AndyMcC0/UVVM_All | bitvis_uart/src/uart_core.vhd | 1 | 13866 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <supp... | mit |
elainemielas/CVUT_BI-PNO | cvika/had/decoder.vhd | 1 | 670 | library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER is
port (
BIN_VALUE : in std_logic_vector (2 downto 0);
ONE_HOT : out std_logic_vector (7 downto 0)
);
end entity DECODER;
architecture DECODER_BODY of DECODER is
begin
DECODE : process (BIN_VALUE)
begin
case BIN_VALUE is
when "000" => ONE_H... | mit |
Wynjones1/gbvhdl | scripts/out.vhd | 1 | 4142 | elsif mem_dout = "00000000" then -- NOP
elsif mem_dout = "00000111" then -- RLCA
elsif mem_dout = "00001111" then -- RRCA
elsif mem_dout = "00010000" then -- STOP
elsif mem_dout = "00010111" then -- RLA
elsif mem_dout = "00011000" then -- JR r8
elsif mem_dout = "00011111" then -- RRA
elsif mem_dout = ... | mit |
elainemielas/CVUT_BI-PNO | cvika/scit1/CONTROLLER.vhd | 2 | 1208 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CONTROLLER is
port(
CLK : in std_logic;
RESET : in std_logic;
TOP : in std_logic;
BOTTOM : in std_logic;
UP : out std_logic
);
end CONTROLLER;
architecture CONTROLLER_BODY of CONTROLLER is
type TYP_STAV is (NAHORU, DOLU);
signal STAV, D... | mit |
elainemielas/CVUT_THESIS | Spartan-3E/led_controller.vhd | 1 | 2156 | ----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 14:34:10 05/08/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: led_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-... | mit |
elainemielas/CVUT_THESIS | Spartan-3E/rate_generator.vhd | 1 | 1715 | ----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 15:21:19 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: rate_generator - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- ... | mit |
dtysky/LD3320_AXI | src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd | 2 | 66283 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
touilleMan/scrips | instmemory.vhd | 1 | 12315 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:35 05/08/2012
-- Design Name:
-- Module Name: instmemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Re... | mit |
dtysky/LD3320_AXI | src/LIST/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_fsm.vhd | 2 | 83900 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_wb_controller.vhd | 1 | 10257 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit |
touilleMan/scrips | control_bench.vhd | 1 | 2967 | -- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/control.sch - Thu Jun 7 17:34:08 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends t... | mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_reset_unit.vhd | 1 | 39205 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/nf/nf_transmitter.vhd | 1 | 3866 | -------------------------------------------------------------------------------
--! @file nf_transmitter.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-23
--! @brief NanoFIP transmitter.
--------------------------------------------------------... | mit |
touilleMan/scrips | datamemory.vhd | 1 | 3243 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:55:03 05/08/2012
-- Design Name:
-- Module Name: datamemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Re... | mit |
wltr/cern-fgclite | critical_fpga/src/rtl/cf/fetch_page/fetch_page_ow.vhd | 1 | 5203 | -------------------------------------------------------------------------------
--! @file fetch_page_ow.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare one-wire page for NanoFIP communication.
-----------------------------... | mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_prod_data_lgth_calc.vhd | 1 | 13111 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit |
touilleMan/scrips | sign_extend_bench.vhd | 1 | 1757 | -- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/sign_extend.sch - Thu Jun 7 17:52:26 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommend... | mit |
touilleMan/scrips | ALU_bench.vhd | 1 | 2756 | -- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_v2/ALU.sch - Fri Jun 8 12:08:08 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that ... | mit |
wltr/cern-fgclite | nanofip_fpga/src/rtl/nanofip/wf_status_bytes_gen.vhd | 1 | 26557 | --_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- ... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/Synthesize/DataPath/Vhdl/c_adder.vhd | 1 | 952 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_adder is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_adder;
architecture behavior of c_adder is
function bi... | mit |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/meu_projeto.vhd | 1 | 1818 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:20:16 11/04/2014
-- Design Name:
-- Module Name: meu_projeto - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies... | mit |
marceloboeira/vhdl-examples | 008-state-machine-calculator/_example/disp7segx4.vhd | 1 | 2430 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:01 06/13/2012
-- Design Name:
-- Module Name: disp7segx4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_tb.vhd | 1 | 1598 | ---------------------------------------------------------------------
--
-- Inputs: a, b, c, d, e, f, g, h
-- Output(s): i
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_nor.vhd | 2 | 568 | library ieee;
use ieee.std_logic_1164.all;
entity c_nor is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_nor;
architecture behavior of c_nor is
begin
... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample/input_dp.vhd | 1 | 14195 | ---------------------------------------------------------------------
-- --
-- This file is generated automatically by AUDI (AUtomatic --
-- Design Instantiation) system, a behavioral synthesis system, --
-- developed at the University of South Florida. This project --
-- is supported... | mit |
Abeergit/UART | UART_TX.vhd | 1 | 4351 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
generic(
DBIT: integer := 8; -- Anzahl Datenbits
PARITY_EN: std_logic := '1'; -- Parity bit (1 = enable, 0 = disable)
SB_TICK: integer := 16 -- Anzahl s_tick f stopbbit
);
port(
clk,... | mit |
marceloboeira/vhdl-examples | 008-state-machine-calculator/seven_segment_display_mux.vhd | 1 | 1839 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity SevenSegmentDisplayMux is
Port (entrada: in STD_LOGIC_VECTOR (15 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
output_h: out STD_LOGIC_VECTOR (7 downto 0);
... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | docs/sample2/input_des.vhd | 1 | 2075 | ---------------------------------------------------------------------
--
-- Inputs: a, b, c, d, e, f, g, h
-- Output(s): i
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_or.vhd | 2 | 564 | library ieee;
use ieee.std_logic_1164.all;
entity c_or is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_or;
architecture behavior of c_or is
begin
P0... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/c_signal.vhd | 1 | 1482 | library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_signal is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
store, update, clear, clock : in std_logic;
output : out std_logic_vector((width + 1) downto 0)
);
end c_signal;
architect... | mit |
CyAScott/CIS4930.DatapathSynthesisTool | src/components/test_shiftreg.vhd | 1 | 2541 | use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_shiftreg is end;
architecture test_shiftreg of test_shiftreg is
component shift_reg
generic (width : INTEGER := 4);
port (input : in std_logic_vector((width - 1) downto 0);
control:in std_logic_vector(1 downto 0);
Clear :... | mit |
skrasser/papilio_synth | hdl/dac.vhd | 1 | 530 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
port (pulse : out STD_LOGIC;
data : in STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC
);
end dac;
architecture behavioral of dac is
signal sum : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
begi... | mit |
jamesots/learnfpga | midi/tb/shift_out_tb.vhdl | 1 | 2508 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:32:19 01/31/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/midi/tb/shift_out_tb.vhdl
-- Project Name: midi
-- Target Device:
-- Tool versions:
-- Description: ... | mit |
gustapp/labdig | exp4/transmissão/unidade_controle_transmissao.vhd | 1 | 1906 | library ieee;
use ieee.std_logic_1164.all;
entity unidade_controle_transmissao is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
DTR : out std_logic;
RTS : out std_logic;... | mit |
gustapp/labdig | Exp4/FD_receptor.vhd | 1 | 343 | library IEEE;
use IEEE.std_logic_1164.all;
entity FD_receptor is
port(
CD, RD, enable_recepcao : in std_logic;
temDadoRecebido, DadoRecebido : out std_logic
);
end FD_receptor;
architecture fluxo_dados of FD_receptor is
begin
temDadoRecebido <= CD;
DadoRecebido <= enable_recepcao an... | mit |
jamesots/learnfpga | oscilloscope/vhdl/shift_in.vhdl | 2 | 720 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- shifts data into the LSB
entity shift_in is
generic (
width : positive
);
port (
reset : in std_logic;
clk : in std_logic;
ce : in std_logic;
ser_in : in std_logic;
par_out : out std_logic_vector(width - 1 downto 0)
... | mit |
jamesots/learnfpga | drum1/vhdl/clock_divider.vhdl | 1 | 810 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
generic (
divisor : positive
);
Port (
clk_in : in std_logic;
clk_out : out std_logic;
reset : in std_logic
);
end clock_divider;
architecture behavioral of clock_divider is
begin
process(clk_in)
variable t : std_logic :=... | mit |
gustapp/labdig | Exp5/cronometro/contador_min_seg_bcd.vhd | 1 | 2259 | -- contador_min_seg_bcd.vhd
-- contador de minutos e segundos com saida bcd
-- com suporte a sinal de tick enable
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.alL;
entity contador_min_seg_bcd is
port ... | mit |
jamesots/learnfpga | analogue2/vhdl/analogue2.vhdl | 1 | 2208 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity analogue2 is
Port (
clk50 : in STD_LOGIC;
ad_dout : in STD_LOGIC;
ad_din : out STD_LOGIC;
ad_cs : out STD_LOGIC;
ad_sclk : out STD_LOGIC;
leds : out STD_LOGIC_VECTOR(7 downto 0)
);
end analogue2;
architecture Behav... | mit |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/Miscellaneous/kcpsm6_without_slice_packing_attributes.vhd | 2 | 109641 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... | mit |
bravo95/SecondProcessor | register.vhd | 1 | 974 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity regis is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC := '0' ;
datain : in STD_LOGIC_VECTOR (31 downto 0) := x"00000000" ;
dataout : out STD_LOGIC_VECTOR (31 downto 0... | mit |
gustapp/labdig | Exp4/InterfaceModem.vhd | 1 | 1581 | library IEEE;
use IEEE.std_logic_1164.all;
entity InterfaceModem is
port (CLOCK, RESET, LIGA, DadoSerial, CD, RD, CTS : in std_logic;
Enviar : in std_logic;
DTR, RTS, TD, temDadoRecebido, DadoRecebido : out std_logic;
envioOK ... | mit |
bravo95/SecondProcessor | PSR_modifier_tb.vhd | 1 | 2122 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
ENTITY PSR_modifier_tb IS
END PSR_modifier_tb;
ARCHITECTURE behavior OF PSR_modifier_tb IS
COMPONENT PSR_modifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
RESULT : IN std_l... | mit |
jamesots/learnfpga | midi2/tb/midi2_tb.vhdl | 1 | 2109 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:40 01/31/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/midi/tb/midi_tb.vhdl
-- Project Name: midi
-- Target Device:
-- Tool versions:
-- Description:
--... | mit |
bravo95/SecondProcessor | SEU.vhd | 1 | 470 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
seuout : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process( imm13)
begin
if(imm13(12)... | mit |
bravo95/SecondProcessor | InstruccionMemory.vhd | 1 | 1526 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
--int k = 6
entity InstruccionMemory is
Port ( address : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstruccionMemory;... | mit |
bravo95/SecondProcessor | Processor_tb.vhd | 1 | 1108 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Processor_tb IS
END Processor_tb;
ARCHITECTURE behavior OF Processor_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Processor
PORT(
CLK : IN std_logic;
RST : IN std_logic;
ALURESULT : OUT std... | mit |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/ROM_form_templates/ROM_form_7S_2K_with_error_detection_14March13.vhd | 1 | 52574 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... | mit |
jamesots/learnfpga | analogue2/vhdl/adc.vhdl | 1 | 2255 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity adc is
port (
ad_port : in std_logic_vector (2 downto 0);
ad_value : out std_logic_vector (11 downto 0);
ad_newvalue : out std_logic := '0';
clk : in std_logic;
ad_dout : in std_logic;
ad_din : out std_logic := '0';
... | mit |
JavierRizzoA/Sacagawea | sources/DECODIFICADOR.vhd | 1 | 1494 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:18:59 06/05/2016
-- Design Name:
-- Module Name: DECODIFICADOR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenci... | mit |
masaruohashi/tic-tac-toe | interface_jogo/contador_tabuleiro.vhd | 1 | 844 | -- VHDL de um contador para a impressao do tabuleiro
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_tabuleiro is
port(
clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(6 do... | mit |
masaruohashi/tic-tac-toe | uart/registrador_dado_recebido.vhd | 1 | 705 | -- VHDL de um Registrador de dados para a recepcao
library ieee;
use ieee.std_logic_1164.all;
entity registrador_dado_recebido is
port(
clock: in std_logic;
enable: in std_logic;
clear: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end ... | mit |
JavierRizzoA/Sacagawea | sources/RAM.vhd | 1 | 1054 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port (
clk : in std_logic;
write_read : in std_logic; -- write = 1 read = 0
ram_enable : in std_logic;
direccion : in std_logic_vector(9 downto 0);
ram_datos_escritura : out std_logic_vector(7 do... | mit |
masaruohashi/tic-tac-toe | uart/gerador_tick.vhd | 1 | 737 | -- gerador_tick.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gerador_tick is
generic(
M: integer := 454545 -- para transmissao de 110 bauds
);
port(
clock, reset: in std_logic;
tick: out std_logic
);
end gerador_tick;
architecture arch of gerador_ti... | mit |
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