repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Wishbone_Peripherals/papilio_stepper.vhd | 13 | 7399 | --**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/papilio_stepper.vhd | 13 | 7399 | --**********************************************************************************************
-- Stepper Controller Peripheral for the AVR Core
-- Version 0.1
-- Designed by Girish Pundlik and Jack Gassett.
--
--
-- License Creative Commons Attribution
-- Please give attribution to the original author and Gadget ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/Papilio_Default_Wing_Pinout.vhd | 13 | 13006 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/Papilio_Default_Wing_Pinout.vhd | 13 | 13006 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd | 13 | 8035 | --
-- UART for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/rle.vhd | 13 | 7423 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either vers... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/rle.vhd | 13 | 7423 | ----------------------------------------------------------------------------------
-- rle_enc.vhd
--
-- Copyright (C) 2011 Kinsa
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either vers... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_pokey.vhd | 13 | 19476 | --
-- A simulation model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/AUDIO_zpuino_wb_pokey.vhd | 13 | 19476 | --
-- A simulation model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/wb_rom_ram_hyperion.vhd | 13 | 6196 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram_hyperion is
generic (
maxbit: integer := maxAddrBit
);
port... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/zpuino_gpio.vhd | 13 | 8192 | --
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/zpuino_gpio.vhd | 13 | 8192 | --
-- GPIO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/shifter.vhd | 14 | 3771 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lshifter is
generic (
stages: integer := 3
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
done: out std_logic;
inputA: in std_logic_vector(31 downto 0);
inputB: in std_logic_vector(31 ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/board_Papilio_One_250k/prom-generic-dp-32.vhd | 13 | 102419 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity prom_generic_dualport is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(13 d... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_One_500k/zpu_config.vhd | 13 | 2676 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/clk_32to800_pll.vhd | 13 | 5860 | -- file: clk_32to800_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to800_pll.vhd | 13 | 5860 | -- file: clk_32to800_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer i... | mit |
sinkswim/DLX-Pro | DLX_simulation_cfg/a.b-DataPath.core/a.b.c-execute.core/a.b.c.f-mux21.vhd | 1 | 398 | library ieee;
use ieee.std_logic_1164.all;
-- a goes through with s = '1', b with s = '0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
a: in std_logic_vector(NBIT - 1 downto 0);
b: in std_logic_vector(NBIT - 1 downto 0);
s: in std_logic;
y: out std_logic_vector(NBIT - 1 downto 0)
);
end mu... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/lsu.vhd | 13 | 2970 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/Benchy/BRAM8k36bit.vhd | 13 | 2520 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of sou... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/BRAM8k36bit.vhd | 13 | 2520 | --
-- Generic dual-port RAM (symmetric)
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of sou... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_i2c.vhd | 13 | 15356 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/controller.vhd | 13 | 6873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Benchy/controller.vhd | 13 | 6873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/controller.vhd | 13 | 6873 | ----------------------------------------------------------------------------------
-- controller.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/board_Papilio_One_250k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen.vhd | 26 | 7843 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_One_500k/stack.vhd | 13 | 1500 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/MegaWing_Logicstart/Libraries/ZPUino_1/board_Papilio_One_500k/stack.vhd | 13 | 1500 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/board_Papilio_One_250k/zpu_config.vhd | 13 | 2676 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain t... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_Pro/bootloader.vhd | 13 | 13706 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bootloader_dp_32 is
port (
CLK: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(11 downto... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/zpu_core_extreme_hyperion.vhd | 13 | 42758 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are me... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/wb_rom_ram.vhd | 13 | 6124 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/wb_rom_ram.vhd | 13 | 6124 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: ... | mit |
chcbaram/FPGA | zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/wb_rom_ram.vhd | 13 | 6124 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
entity wb_rom_ram is
generic (
maxbit: integer := maxAddrBit
);
port (
ram_wb_clk_i: ... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_rsft32x5.vhd | 10 | 4329 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulat... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_normus64.vhd | 10 | 4503 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_castytof.vhd | 10 | 3181 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_expnornd.vhd | 10 | 4802 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... | mit |
LorhanSohaky/UFSCar | 2017/lab_cd/aula4/Segmentos7/simulation/qsim/work/@etapa1_vlg_vec_tst/_primary.vhd | 1 | 96 | library verilog;
use verilog.vl_types.all;
entity Etapa1_vlg_vec_tst is
end Etapa1_vlg_vec_tst;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_sin_s5.vhd | 10 | 431526 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/hcc_divrnd.vhd | 10 | 5592 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fp_clz36x6.vhd | 10 | 2148 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... | mit |
boztalay/OZ-3 | FPGA/OZ-3_System/Output_Extender_TB.vhd | 2 | 2582 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:49 06/12/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/OZ-3_System/Output_Extender_TB.vhd
-- Project Name: ... | mit |
LorhanSohaky/UFSCar | 2017/lab_cd/aula7/Verilog/simulation/modelsim/rtl_work/decodificador_@t@b/_primary.vhd | 1 | 92 | library verilog;
use verilog.vl_types.all;
entity decodificador_TB is
end decodificador_TB;
| mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_invsqr_core.vhd | 10 | 8541 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/fp_cordic_m1_fused.vhd | 10 | 14306 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulati... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/hcc_implementation.vhd | 10 | 516240 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... | mit |
boztalay/OZ-3 | FPGA/OZ-3_System/four_dig_7seg.vhd | 3 | 3099 | ----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--
--Module Title: 4dig_7seg
--Module Description:
-- This is a 4-digit, 7-segment display decoder. It outputs in 16-bit values
-- on the Digilent Nexys 2 board's 4-digit display in hexadecimal. Simply
... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/dp_lnrndpipe.vhd | 10 | 6310 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... | mit |
satputeaditya/vernier-ring-oscillator-tdc | coincidence_detector.vhd | 1 | 1249 | -- coincidence_detector.vhd
--**********************************************************************
-- Program to detect if STOP pulse is leading and lagging edge wrt START
--**********************************************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic... | mit |
SLongofono/Senior_Design_Capstone | hdl/Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp/ipcore_dir/ddr/example_design/rtl/example_top.vhd | 1 | 65422 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual prope... | mit |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.vhd | 1 | 111054 | --*****************************************************************************
-- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... | mit |
fabioperez/space-invaders-vhdl | lib/pc.vhd | 1 | 3176 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- PLAYER CONTROLLER
--------------------------------------------------------------------------------
-- TODO:
-- Remove o... | mit |
SLongofono/Senior_Design_Capstone | hdl/system_top.vhd | 1 | 9545 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 04/21/2018 01:23:15 PM
-- Module Name: system_top - Behavioral
-- Description: System-level wrapper for processor components
--
-- Additional Comments: "Death must be so beautiful. To lie in... | mit |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ram2ddrxadc.vhd | 2 | 19856 | -------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
----------------------------------------------... | mit |
WebWorkDeveloper/SQL-editor | public/src/libs/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
... | mit |
SLongofono/Senior_Design_Capstone | StupidCore/UART_TX_CTRL.vhd | 1 | 4747 | ----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
-----------------------------------------... | mit |
fabioperez/space-invaders-vhdl | lib/io/keyboard.vhd | 1 | 2172 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data, clock_25Mhz ,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
... | mit |
SLongofono/Senior_Design_Capstone | hdl/decode.vhd | 2 | 22081 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/06/2017 10:33:06 AM
-- Module Name: decode - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
--... | mit |
SLongofono/Senior_Design_Capstone | StupidCore/RAM.vhd | 1 | 7870 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
done: out STD_LOGIC... | mit |
SLongofono/Senior_Design_Capstone | hdl/ROM_Controller.vhd | 1 | 10896 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
-- so, acc, hold: in STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
... | mit |
tcsiwula/java_code | classes/cs345/code_examples/antlr_github_copy/grammars/vhdl/examples/signed.vhd | 5 | 10990 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- ... | mit |
akshayp/college-projects | vhdl/pong/bat.vhd | 1 | 2926 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bat IS
PORT ( clr, CLKBAT : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : IN std_logic;
read : OUT std_logic;
paddle_1, paddle_2 : OUT INTEGER RANGE 0 to 48);
END ... | mit |
inmagik/html-map-designer | lib/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
... | mit |
AmitThakur/vhdl | mealy/mealy1.vhd | 2 | 772 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END mealy ;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, ... | mit |
shamoons/linguist-samples | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
hamsternz/FPGA_Webserver | hdl/tx/tx_interface.vhd | 1 | 8508 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tx_interface - Behavioral
--
-- Description: To send data streams out to an Ethernet PHY over RGMII
--
----------------------------------------------------------------... | mit |
xiehuiqi220/package-json-editor | bower_components/ace/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
... | mit |
hamsternz/FPGA_Webserver | testbenches/tb_main_design_arp.vhd | 1 | 10234 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.05.2016 21:14:53
-- Design Name:
-- Module Name: tb_main_design - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
... | mit |
hamsternz/FPGA_Webserver | hdl/arp/arp_request.vhd | 1 | 7048 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: rx_arp_request - Behavioral
--
-- Description: Receive ARP packets and decode them
--
-----------------------------------------------------------------------------------... | mit |
hamsternz/FPGA_Webserver | hdl/arp/arp_tx_fifo.vhd | 1 | 3511 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: my_fifo - Behavioral
--
-- Description: A 32 entry FIFO using inferred storage
--
-----------------------------------------------------------------------------------... | mit |
hamsternz/FPGA_Webserver | hdl/icmp/icmp_build_reply.vhd | 1 | 11819 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: icmp_build_reply - Behavioral
--
-- Description: Build the ICMP reply packet by adding headers to the data.
--
---------------------------------------------------------... | mit |
Remillard/VHDL-Mode | Test/beautify_test.vhd | 1 | 26841 | -------------------------------------------------------------------------------
-- Last update : Fri Jun 14 13:31:50 2019
-- Project : VHDL Mode for Sublime Text
-------------------------------------------------------------------------------
-- Description: This VHDL file is intended as a test of scope and beau... | mit |
hamsternz/FPGA_Webserver | hdl/transport/transport_commit_buffer.vhd | 1 | 7231 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: transport_commit_buffer - Behavioral
--
-- Description: Somewhere to hold the data outbound packet while waiting to
-- be granted access to the TX interface.... | mit |
hamsternz/FPGA_Webserver | hdl/arp/arp_handler.vhd | 1 | 13243 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: arp_handler - Behavioral
--
-- Description: Processing for ARP packets.
--
------------------------------------------------------------------------------------
-- FPGA_... | mit |
hamsternz/FPGA_Webserver | hdl/tcp_engine/tcp_engine_seq_generator.vhd | 1 | 2264 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_seq_generator - Behavioral
--
-- Description: A very bad random SYN number generator
--
-----------------------------------------------------------------------... | mit |
wifidar/wifidar_fpga | src/uart_minibuf.vhd | 2 | 2698 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity uart_minibuf is
generic(
num_samples: integer range 0 to 20000 := 20;
sample_length_bits: integer range 0 to 32 := 14
);
port(
data_in: in std_logic_vector (sample_length_bits -1 downto 0);
data_out: out s... | mit |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_5/a3d4f4cf/src/TMDS_Clocking.vhd | 14 | 11908 | -------------------------------------------------------------------------------
--
-- File: TMDS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 10 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright D... | mit |
carlosrd/DAS | P4/Parte C (Opcional 2)/binToSeg.vhd | 5 | 1631 | ----------------------------------------------------------------------------------
-- ESQUEMA LEDS 8 SEGMENTOS:
--
-- A
-- ---
-- F | | B
-- -G-
-- E | | C
-- --- . DP
-- D
----------------------------------------------------------------------------------
library IEEE;
us... | mit |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_5/a3d4f4cf/src/dvi2rgb.vhd | 1 | 11028 | -------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent I... | mit |
es17m014/vhdl-counter | src/vhdl/bin2bcd_.vhd | 1 | 1073 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : bin2bcd_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
... | mit |
es17m014/vhdl-counter | src/old/vhdl/debounce_.vhd | 1 | 1117 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : debounce_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems... | mit |
TheMassController/VHDL_experimenting | project/complete_system/test/two_brams_tb.vhd | 1 | 6382 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library tb;
use tb.bus_tb_pkg.all;
use tb.depp_tb_pkg.all;
library src;
use src.bus_pkg.all;
use src.depp_pkg.all;
entity two_brams_tb is
generic (
runne... | mit |
digital-sound-antiques/vm2413 | PhaseGenerator.vhd | 2 | 3829 | --
-- PhaseGenerator.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseGenerator is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
... | mit |
es17m014/vhdl-counter | src/vhdl/x7seg.vhd | 1 | 2369 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : x7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- ... | mit |
es17m014/vhdl-counter | src/old/tb/tb_debouncer.vhd | 1 | 2250 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_debounce.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Syste... | mit |
LucasMahieu/TP_secu | code/AES/vhd/vhd/l_barrel.vhd | 2 | 1058 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------
-- Entity implementing shiftrow operation.
-- amount<0> controls rotation by one byte to the left
-- amount<1> controls rotation by two bytes
-- Input size configurable through ge... | mit |
es17m014/vhdl-counter | src/vhdl/io_ctrl_.vhd | 1 | 1670 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : io_ctrl_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
... | mit |
digital-sound-antiques/vm2413 | vm2413.vhd | 2 | 10377 | --
-- VM2413.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package VM2413 is
constant MAXCH : integer := 9;
constant MAXSLOT : integer := MAXCH * 2;
subtype CH_TYPE is integer range 0 to MAXCH-1;
subtype SLOT_TYPE is integer range 0 to MAXSLOT-1;
subty... | mit |
es17m014/vhdl-counter | src/old/vhdl/cntr_.vhd | 1 | 1719 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- ... | mit |
LucasMahieu/TP_secu | code/AES/vhd/DDR_reg.vhd | 2 | 1065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
... | mit |
LucasMahieu/TP_secu | code/AES/vhd/Sbox.vhd | 2 | 4859 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-- Component Declaration
entity sbox is port (
b_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
clock, reset : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end ... | mit |
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