repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
values |
|---|---|---|---|---|---|
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_reset_in/pr_region_default_reset_in_inst.vhd | 1 | 472 | component pr_region_default_reset_in is
port (
clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_reset : out std_logic -- reset
);
end component pr_region_default_reset_in;
u0 : component pr_region_default_reset_in
port map (
clk => CONNECTED_TO_... | mit |
pdt/ttask | test/ghdl/lib/my_lib/sim/and_gate_test.vhdl | 3 | 989 | --
-- and_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
library my_lib;
use work.tbmsgs.all;
entity and_gate_test is
end entity;
architecture sim of and_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity my_lib.and_gate port ... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/road/simulation/road_tb.vhd | 1 | 4331 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | mit |
capitanov/Stupid_watch | src/top/top_xc3s500e_ex.vhd | 1 | 14017 | --------------------------------------------------------------------------------
--
-- Title : top_xc3s500e_ex.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description ... | mit |
laurocruz/snakes_vhdl | src/snake_lib/make_map.vhd | 1 | 2607 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
-- controlador do mapa do jogo
ENTITY make_map IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
-- clock do jogo
PORT (clock ... | mit |
IamVNIE/Hardware-Security | Interfaces/UART_Version_3/Uart_working/des_decrypt_wit_out - Copy.vhd | 2 | 15062 | ------------------------------------------
--------------PACKET----------------------
----MSB--- EN G1 G2 G3 G6 G7 ---LSB-------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DISPLA... | mit |
pdt/ttask | test/fpga-sim/lib/my_lib/sim/or_gate_test.vhdl | 3 | 984 | --
-- or_gate_test.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
library my_lib;
use work.tbmsgs.all;
entity or_gate_test is
end entity;
architecture sim of or_gate_test is
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic;
begin
uut : entity my_lib.or_gate port map ... | mit |
capitanov/Stupid_watch | src/rtl/chips/cl_lcd_data.vhd | 1 | 3302 | -------------------------------------------------------------------------------
--
-- Title : cl_lcd_data
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : kapitanov@insys.ru
--
-- Version : 1.0
--
----------------------------------------------------------------------... | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/roundfunc.vhd | 2 | 2695 | ----------------------------------------------------------------------------------
-- Company: Hardware Security
-- Designer: Vinayaka Jyothi
--
-- Create Date: 18:42:44 11/28/2016
-- Design Name: DES Round Function
-- Module Name: des_roundfunc - Structural
-- Project Name: DES Crypto Core
-- Target Devices: ANY... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/startBtn/simulation/bmg_stim_gen.vhd | 1 | 12585 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/background/simulation/addr_gen.vhd | 101 | 4409 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/side/example_design/side_exdes.vhd | 1 | 4312 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/explosion/example_design/explosion_exdes.vhd | 1 | 4342 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | mit |
capitanov/Stupid_watch | src/rtl/game_cores/ctrl_rounds_rom.vhd | 1 | 7130 | --------------------------------------------------------------------------------
--
-- Title : ctrl_rounds_rom
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Description : ROM generator for new rounds
--
-- Rules for ROM generator:
-- 1) 0-6 - number of mines, 7 - a mine; 8-9 - ... | mit |
Yuriu5/MiniBlaze | src/hw1/ALU_pkg.vhd | 1 | 5786 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : ALU_pkg
-- Date : 07/07/2016
--
-- Description : Arithmetic Logic Unit Package
--
-- ---------------------------... | mit |
Luisda199824/ProcesadorMonociclo | SignExtender.vhd | 1 | 471 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SignExtender is
Port ( A : in STD_LOGIC_VECTOR (12 downto 0);
SEOut : out STD_LOGIC_VECTOR (31 downto 0));
end SignExtender;
architecture Behavioral of SignExtender is
begin
process(A)
... | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/keysched.vhd | 2 | 5134 | --******************************************************************************
-- Copyright (c) 2017 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the ... | mit |
IamVNIE/Hardware-Security | RC5 CryptoCore/Rc5 Codes/RC5encryptAllSteps.vhd | 2 | 6997 | Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_enc Is
Port
(
clr : in std_logic;
clk : in std_logic;
din : in std_logic_vector(63 downto 0);
di_vld : in std_logic;
key_rdy : in std_logic;
skey : in rom;
dout : out std_logic_vecto... | mit |
Yuriu5/MiniBlaze | src/hw1/ALU.vhd | 1 | 8041 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : ALU
-- Date : 07/07/2016
--
-- Description : Arithmetic Logic Unit
--
-- ---------------------------------------... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/police/simulation/police_tb.vhd | 1 | 4343 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/s2.vhd | 2 | 3979 | library ieee;
use ieee.std_logic_1164.all;
entity s2 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s2;
architecture behaviour of s2 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "000010"=> so<=... | mit |
laurocruz/snakes_vhdl | src/snake_lib/snake_pack.vhd | 1 | 2402 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.math_real.all;
PACKAGE snake_pack IS
--TYPE int_s IS INTEGER RANGE -20 TO 255;
TYPE int_array IS array (0 to 127) OF INTEGER RANGE -20 TO 255;
COMPONENT conv_7seg IS
PORT (digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
seg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_stub.vhdl | 1 | 2560 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:54 2017
-- Host : DarkCube running 64-bit major re... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/vhdl/convolve_kernel.vhd | 1 | 39161 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 16 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 16 | 94635 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/DEL.vhd | 1 | 311 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DEL is port(
D : in std_logic;
E : in std_logic;
Q : out std_logic
);
end DEL;
architecture behavior of DEL is
signal S : std_logic;
begin
Main : process (D, E)
begin
if(E='1') then
S <= D;
end if;
end process;
Q <= S;
end behavior;
| mit |
nathdwek/vhdltree | test/dummy_project/long_component_name5678.vhd | 1 | 94 | long_ent17y_n4m3_with_numbers4567: entity lib.deep.E4
2numbers_should_not_start: entity comp
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_stub.vhdl | 1 | 1970 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major re... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/Zeroes/ZeroCounter.vhd | 1 | 2760 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity ZeroCounter is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end ZeroCounter;
architecture Beh of ZeroCounter is
component MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_1/synth/design_1_axi_bram_ctrl_0_1.vhd | 1 | 17300 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_sim_netlist.vhdl | 1 | 3912778 | null | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_auto_pc_0/led_controller_design_auto_pc_0_sim_netlist.vhdl | 1 | 510749 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:20:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/prim/NOR2.vhd | 1 | 185 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2 is port(
a,b: in std_logic;
z: out std_logic
);
end NOR2;
--
architecture NOR2 of NOR2 is
begin
z <= not (a or b);
end NOR2; | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel_fcud.vhd | 2 | 3077 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/zqynq_lab_1_design_axi_gpio_1_1_sim_netlist.vhdl | 1 | 111722 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:33 2017
-- Host : DarkCube running 64-bit major releas... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 7 | 143167 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_ser.vhd | 3 | 4421 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisio... | mit |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/lfsr.vhd | 3 | 643 | library ieee;
use ieee.std_logic_1164.all;
entity lfsr is
generic(
init : in std_logic_vector(63 downto 0) := X"0000000000000001"
);
port(
clk : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end entity lfsr;
architecture rtl of lfsr is
signal shifter : std_logic_vector(63 downto 0) ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/sim/zqynq_lab_1_design_axi_bram_ctrl_0_0.vhd | 1 | 16949 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 7 | 103702 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/6d8f288943408fbb/zynq_design_1_rst_ps7_0_100M_1_stub.vhdl | 1 | 1958 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:40 2017
-- Host : DarkCube running 64-bit major re... | mit |
MarkBlanco/FPGA_Sandbox | VHDL_funcs_and_procs/VHDL_func_and_procs.vhd | 1 | 1453 | -- Based on tutorial here:
-- https://www.youtube.com/watch?v=j2lAPIjpF1w&t=309s
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library sevseg_package;
use sevseg_package.my.all;
ENTITY SEVSEG is
PORT(
SW: IN STD_LOGIC_VECTOR(9 downto 0);
HEX0: OUT STD_LOGIC_VECTOR(6 downto 0);
HEX1: OUT STD_L... | mit |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/fifo.vhd | 3 | 1952 | library ieee;
use ieee.std_logic_1164.all;
entity fifo is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width-1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output : out std_logic_vector(... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab2/fir_prj/solution1/impl/ip/hdl/vhdl/fir_shift_reg.vhd | 10 | 3079 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab1/fir_prj/solution1/syn/vhdl/fir_shift_reg.vhd | 10 | 3079 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/b32f033de8d0536c/ip_design_zed_audio_ctrl_0_0_stub.vhdl | 1 | 2512 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-5/src/Task4_TB/Task4_tb3.vhd | 2 | 6048 | -------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\s... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution1/impl/vhdl/fir.vhd | 9 | 14661 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab1/fir_prj/solution1/syn/vhdl/fir.vhd | 9 | 14661 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... | mit |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/TestBench/mrom_TB.vhd | 1 | 1381 | library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component m... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 330319 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:41 2017
-- Host : DarkCube running 64-bit major releas... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_3_full_dsp_32/synth/convolve_kernel_ap_fadd_3_full_dsp_32.vhd | 3 | 12845 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_4/syn/vhdl/convolve_kernel_fcud.vhd | 1 | 3077 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/747b0ef18f7ea24b/ip_design_lms_pcore_0_0_stub.vhdl | 1 | 2608 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:37 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_12_no_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 16 | 103154 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/841f5df448bf42bc/zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl | 1 | 533334 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major... | mit |
kloboves/sicxe | vhdl/debouncer.vhd | 1 | 3491 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debouncer is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
output_o : out std_logic;
change_on_o : out std_logic;
change_off_o : out std_logic
);
end debouncer;
architecture ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xlconcat_0_1/zqynq_lab_1_design_xlconcat_0_1_stub.vhdl | 1 | 1473 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:52 2017
-- Host : EffulgentTome running 64-bit maj... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_2_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 16 | 292080 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 16 | 292080 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 16 | 292080 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_0/zynq_design_1_axi_gpio_0_0_sim_netlist.vhdl | 1 | 51912 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major releas... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_sim_netlist.vhdl | 1 | 66664 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:28 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 16 | 142619 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/DELAR.vhd | 1 | 380 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DELAR is port(
D : in std_logic;
E : in std_logic;
CLR : in std_logic;
Q : out std_logic
);
end DELAR;
architecture behavior of DELAR is
signal S : std_logic;
begin
Main : process (D, E, CLR)
begin
if(CLR = '1') then
S <= '0';
elsif(E='1') then
... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/213bdb6c5f83bd6a/zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 197463 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:29:07 2017
-- Host : EffulgentTome running 64-bit major r... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/hdl/vhdl/convolve_kernel_fbkb.vhd | 4 | 3597 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ie... | mit |
dsaves/dsaves-hdl | primitives/lut6.vhd | 1 | 2095 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modi... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/38a92fb39758d0fa/ip_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 35666 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:12 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/axi_utils_v2_0_vh_rfs.vhd | 7 | 292628 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect k... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl | 1 | 719637 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:59 2017
-- Host : DarkCube running 64-bit major releas... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl | 1 | 29735 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:33 2017
-- Host : DarkCube running 64-bit major releas... | mit |
dsaves/dsaves-hdl | primitives/buffer.vhd | 1 | 1474 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modi... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/Max/MaxFinder.vhd | 1 | 2754 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity MaxFinder is
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end MaxFinder;
architecture Beh of MaxFinder is
component MROM is
port (
RE: in std_logic;
ADR: in std_logic_vector(5 downto 0);
DOUT: out st... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/b73b442e1fb83bed/ip_design_nco_0_0_sim_netlist.vhdl | 1 | 97040 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:10 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/structure/Var5.vhd | 1 | 1482 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Var5 is port(
W,X,Y,Z: in std_logic;
F: out std_logic
);
end Var5;
--
architecture structual of Var5 is
signal nW : std_logic;
signal nY : std_logic;
signal nWX : std_logic;
signal nWXY : std_logic;
signal WXY : std_logic;
signal T : std_logic;
signal... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c47de30114c88d53/ip_design_rst_ps7_0_100M_0_stub.vhdl | 1 | 1907 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu ... | mit |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/LIFO.vhd | 1 | 2389 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
entity LIFO is
generic(
-- address bus
m: integer := 5;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;... | mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/VGA_play.vhd | 2 | 6134 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 17:12:10 11/26/2013
-- Design Name:
-- Module Name: VGA_play - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd | 19 | 32006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd | 19 | 32006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/Keyboard.vhd | 1 | 3036 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZLX
--
-- Create Date: 15:22:18 11/06/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revis... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd | 19 | 13156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_blk_mem_gen_0_0/blk_mem_gen_v8_1/blk_mem_axi_write_fsm.vhd | 27 | 61464 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/coregen_comp_defs.vhd | 1 | 13913 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *****************... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/or_gate.vhd | 15 | 9199 | -------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
--------------------------------------------------------... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/blk_mem_gen_v8_1/simulation/blk_mem_gen_v8_1.vhd | 14 | 211393 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd | 19 | 31831 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_status_flags_ss.vhd | 19 | 23791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy_f.vhd | 15 | 12722 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
-... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy_f.vhd | 15 | 12722 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
-... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd | 19 | 9156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/rd_logic_pkt_fifo.vhd | 19 | 44022 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/fifo_generator_v11_0.vhd | 19 | 89172 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo2.vhd | 15 | 14428 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
------------------------------------------------------... | mit |
IamVNIE/Hardware-Security | DES CryptoCore/src/s1.vhd | 2 | 3979 | library ieee;
use ieee.std_logic_1164.all;
entity s1 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s1;
architecture behaviour of s1 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "000010"=> so<=... | mit |
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