repo_name stringlengths 6 79 | path stringlengths 5 236 | copies stringclasses 54
values | size stringlengths 1 8 | content stringlengths 0 1.04M ⌀ | license stringclasses 15
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|---|---|---|---|---|---|
es17m014/vhdl-counter | src/vhdl/ancode.vhd | 1 | 1112 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : ancode.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
--... | mit |
TheMassController/VHDL_experimenting | project/deppSlave/test/depp_slave_controller_tb.vhd | 1 | 18940 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
use src.depp_pkg.all;
library tb;
use tb.depp_tb_pkg.all;
entity depp_slave_controller_tb is
generic (
runner_cfg : str... | mit |
LucasMahieu/TP_secu | code/bench/test_core_glob.vhd | 1 | 4047 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_aes;
use lib_aes.all;
------------------------------------------------------------------------
-- This test bench is configured with two different data sets (selectable with
-- <seltest>). Each test can be run... | mit |
LucasMahieu/TP_secu | code/AES/vhd/MixColumn0.vhd | 2 | 1657 |
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity mixcolumn0 is port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
ctrl_dec : in T_ENCDEC;
b_out : out std_logic_vector (7 downto 0) ) ;
end mixcolumn0;
architecture a_mixcolumn0 of mixcolumn0 i... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/reports/Gray_Binarization/Gray_Binarization_example.vhd | 1 | 2480 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization_example is
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC... | mit |
Nic30/hwtLib | hwtLib/examples/SimpleComentedUnit.vhd | 1 | 444 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- This is comment for SimpleComentedUnit entity, it will be rendered before entity as comment.
-- Do not forget that class inheritance does apply for docstring as well.
--
ENTITY SimpleComentedUnit IS
PORT(
a : IN STD_LOGIC;
... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/altera_lnsim/common_28nm_mlab_cell_pulse_generator/_primary.vhd | 5 | 322 | library verilog;
use verilog.vl_types.all;
entity common_28nm_mlab_cell_pulse_generator is
port(
clk : in vl_logic;
ena : in vl_logic;
pulse : out vl_logic;
cycle : out vl_logic
);
end common_28nm_mlab_cell_pulse_generator... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_cast_GNLF52SJQ3.vhd | 4 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLF52SJQ3 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_cast_GNJGR7GQ2L.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNJGR7GQ2L is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
VladisM/MARK_II | VHDL/src/cpu/id.vhd | 1 | 47743 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity id is
port(
clk: in std_logic;
res: in std_logic;
instr_opcode: in std_logic_vector(7 downto 0);
flag: in std_logic;
ack: in std_logic;
int: in std_logic;
swirq: out std_logic;
... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_bus_concat_GNIIOZRPJD.vhd | 12 | 653 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic ( widthB : natural := 8;
widthA : natural := 8);
po... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_testbench_salt_GN7Z4SHGOK.vhd | 17 | 1749 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string :=... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/Gray_Binarization.vhd | 2 | 2769 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_multiplexer_GNCALBUTDR.vhd | 12 | 1253 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNCALBUTDR is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_ho... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_decoder_GNM4LOIHXZ.vhd | 14 | 901 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNM4LOIHXZ is
generic ( decode : string := "01";
pipeline : natural := 1;
w... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_sMultAltr.vhd | 12 | 3026 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_multiplexer.vhd | 10 | 658 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... | mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_cmp_lt/fp_cmp_lt.vhd | 1 | 5883 | -- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_cmp_lt.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_cmp_lt is
port (
clk : in std_logic := '0'; -- clk.clk
areset : i... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_port_GNOC3SGKQJ.vhd | 20 | 489 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_log... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_port_GN37ALZBS4.vhd | 20 | 449 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/altera_lnsim/altera_mult_add_rtl/_primary.vhd | 5 | 43770 | library verilog;
use verilog.vl_types.all;
entity altera_mult_add_rtl is
generic(
extra_latency : integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
selected_device_family: string := "Stratix V";
lpm_type : strin... | mit |
Nic30/hwtLib | hwtLib/tests/serialization/TmpVarSignCast.vhd | 1 | 1093 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarSignCast IS
PORT(
a : IN STD_LOGIC;
b : IN UNSIGNED(0 DOWNTO 0);
c : OUT UNSIGNED(0 DOWNTO 0);
d : OUT UNSIGNED(0 DOWNTO 0);
e : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
i : IN STD_LOGIC;
... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module.vhd | 2 | 9927 | -- Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module_Binarization_Module is... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_cast_GN7IAAYCSZ.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN7IAAYCSZ is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_decoder.vhd | 7 | 1660 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_testbench_capture.vhd | 10 | 676 | -- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instant... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/db/alt_dspbuilder_BarrelShiftAltr.vhd | 8 | 7592 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/altera_lnsim/altera_arriav_pll/_primary.vhd | 5 | 70296 | library verilog;
use verilog.vl_types.all;
entity altera_arriav_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: st... | mit |
Nic30/hwtLib | hwtLib/examples/showcase0.vhd | 1 | 5141 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
--
-- .. hwt-autodoc::
--
ENTITY Showcase0 IS
PORT(
a : IN UNSIGNED(31 DOWNTO 0);
b : IN SIGNED(31 DOWNTO 0);
c : OUT ... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_barrelshifter.vhd | 4 | 2271 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_delay_GND2PGZRBZ.vhd | 3 | 1088 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GND2PGZRBZ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
us... | mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_div/fp_div_sim/fp_div.vhd | 1 | 86872 | -- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of In... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_sMuxAltr.vhd | 20 | 3446 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
VladisM/MARK_II | VHDL/src/uart/reciever.vhd | 1 | 9255 | -- Reciever
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reciever is
port(
en: in std_logic;
... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_port_GN6TDLHAW6.vhd | 13 | 487 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN6TDLHAW6 is
port(
input : in std_logic_vector(1 downto 0);
output : out std_logi... | mit |
Nic30/hwtLib | hwtLib/tests/serialization/TmpVarExample1.vhd | 1 | 661 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarExample1 IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarExample1 IS
BEGIN
assig_process_b: PROCESS(a)
VARIABLE tmpTypeConv... | mit |
Nic30/hwtLib | hwtLib/examples/statements/FsmExample.vhd | 1 | 1852 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY FsmExample IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
clk : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECT... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_constant_GNZEH3JAKA.vhd | 20 | 592 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : ... | mit |
Given-Jiang/Gray_Binarization | Gray_Binarization_dspbuilder/hdl/alt_dspbuilder_vecseq.vhd | 20 | 2951 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
Nic30/hwtLib | hwtLib/tests/serialization/SimpleUnitReanamedPort1.vhd | 1 | 528 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleUnitReanamedPort1 IS
PORT(
a_in_hdl_data : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
a_in_hdl_rd : OUT STD_LOGIC;
a_in_hdl_vld : IN STD_LOGIC;
b_data : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
b_rd : IN STD_L... | mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_addsub/fp_addsub_sim/dspba_library_package.vhd | 12 | 2231 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... | mit |
VladisM/MARK_II | VHDL/src/cpu/qip/fp_cmp_gt/fp_cmp_gt_sim/dspba_library.vhd | 12 | 11603 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentati... | mit |
VladisM/MARK_II | VHDL/src/systimer/systim.vhd | 1 | 3467 | -- System timer for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity systim is
generic(
BASE_ADDRE... | mit |
Nic30/hwtLib | hwtLib/tests/serialization/AssignToASliceOfReg3a.vhd | 1 | 2417 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Something not assigned by index at the end and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3a IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGI... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_delay.vhd | 1 | 4983 | -- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/db/alt_dspbuilder_cast_GN6OMCQQS7.vhd | 8 | 877 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN6OMCQQS7 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... | mit |
Given-Jiang/Gray_Binarization | tb_Gray_Binarization/hdl/alt_dspbuilder_sAltrBitPropagate.vhd | 20 | 1572 | --------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions ... | mit |
capitanov/MinesweeperFPGA | src/game_cores/cl_square.vhd | 1 | 3602 | --------------------------------------------------------------------------------
--
-- Title : cl_square.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game blo... | mit |
Wynjones1/VHDL-Tests | simu/memory_tb.vhd | 1 | 1737 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
entity memory_tb is
end memory_tb ;
architecture rtl of memory_tb is
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal address : std_logic_vector(15 downto 0);
signal we : std_logic := '0'... | mit |
laurivosandi/vhdl-exercise | carry_ripple_adder.vhd | 1 | 946 | library ieee;
use ieee.std_logic_1164.all;
-- This file corresponds to 4-bit carry ripple adder
entity carry_ripple_adder is
port (
a : in std_logic_vector (3 downto 0); -- First operand
b : in std_logic_vector (3 downto 0); -- Second operand
ci : in std_logic; ... | mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_dverif.vhd | 11 | 5803 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
Mafus1/bluetooth-receiver | source/infrastructure.vhd | 1 | 812 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY infrastructure IS
PORT(
clk : IN std_logic;
reset_n : IN std_logic;
serdata_in : IN std_logic;
serdata_out : OUT std_logic
);
END infrastructure;
-- Architecture Declaration
ARCHITECTURE rtl OF inf... | mit |
kevintownsend/R3 | coregen/fifo_69x512_hf/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... | mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... | mit |
TMU-VHDL-team2/sqrt | components/mdr.vhd | 2 | 886 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;... | mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_top.vhd | 2 | 5679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
TMU-VHDL-team2/sqrt | components/old_data/pr_32.vhd | 1 | 626 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pr is
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(31 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end pr;
architecture BEHAVIOR of pr is
signal rst : std_logic_vector(15 downto 0... | mit |
dugagjinll/MIPS | MIPS/registerFile.vhd | 1 | 1976 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY registerFile IS
GENERIC (
B : INTEGER := 32; --number of bits
W : INTEGER := 5 --number of address bits
);
PORT (
readRegister1 : IN std_logic_vector (W - 1 DOWNTO 0);
readRegister2 : IN std_logic_vector (W - 1 DOWNTO 0);
writeRegi... | mit |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_pkg.vhd | 1 | 11255 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_synth.vhd | 1 | 9659 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
kevintownsend/R3 | coregen/fifo_138x512/example_design/fifo_138x512_top_wrapper.vhd | 1 | 19002 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... | mit |
kevintownsend/R3 | coregen/fifo_96x512/simulation/fg_tb_dgen.vhd | 11 | 4510 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
kevintownsend/R3 | coregen/fifo_fwft_64x512/simulation/fg_tb_synth.vhd | 1 | 9294 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
kevintownsend/R3 | coregen/fifo_36x512_hf/example_design/fifo_36x512_hf_top_wrapper.vhd | 1 | 19220 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... | mit |
kevintownsend/R3 | coregen/fifo_64x512_hf/example_design/fifo_64x512_hf_top_wrapper.vhd | 1 | 19220 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... | mit |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_pctrl.vhd | 10 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... | mit |
TMU-VHDL-team2/sqrt | fpga/M9K_RAM.vhd | 1 | 7140 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: M9K_RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ==============================... | mit |
TMU-VHDL-team2/sqrt | components/old_data/inst_32.vhd | 1 | 687 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity inst is
port(
clock : in std_logic;
busA : in std_logic_vector(31 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0)
);
end inst;
architecture BEHAVIOR ... | mit |
TMU-VHDL-team2/sqrt | components/old_data/alu_32.vhd | 1 | 8160 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(31 downto 0);
busB : in std_logic_vector(31 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO :... | mit |
TMU-VHDL-team2/sqrt | components/old_data/busA_32.vhd | 1 | 742 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
---SI=[MDR,GR,ADDRESS]
entity busA is
port(
clock: in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(31 downto 0);
ADDR : in std_logic_vector( 7 downto 0);
SI : in s... | mit |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11323 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... | mit |
Madh93/scpu | work/mux1/_primary.vhd | 1 | 446 | library verilog;
use verilog.vl_types.all;
entity mux1 is
generic(
WIDTH : integer := 10
);
port(
d0 : in vl_logic_vector;
d1 : in vl_logic_vector;
s : in vl_logic;
y : out vl_logic_vector
... | mit |
alifazel/16-bit-risc | vhdl/mux2x16.vhd | 4 | 382 | library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x16 is
port(S : in std_logic;
X,Y : in std_logic_vector(15 downto 0);
O : out std_logic_vector(15 downto 0));
end mux2x16;
architecture Logic of mux2x16 is
begin
with S select O <= X when '0',
Y when '1',
... | mit |
mjl152/usmt_uarch | smt_full_adder.vhd | 1 | 1908 | -- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to us... | mit |
airlog/vhdl-rc4 | src/rc4_key_loader.vhd | 1 | 2542 | --
-- rc4_key_loader
-- urz¹dzenie ³aduj¹ce kolejne bajty klucza do pamiêci
--
-- TODO: opis dzialania
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.ALL;
entity rc4_key_loader is
generic (
width: integer := 8; -- ilosc bitow na wartosci
key_width: integer := 8 -- ilosc bit... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19382 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19382 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
------------------------------------... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
------------------------------------... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
------------------------------------... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/wr_pf_as.vhd | 19 | 27402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
fupolarbear/THU-Class-CO-makecomputer | src/CPU/ipcore_dir/char_mem/simulation/bmg_tb_pkg.vhd | 101 | 6006 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/dynshreg_i_f.vhd | 15 | 20708 | -------------------------------------------------------------------------------
-- $Id: dynshreg_i_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg_i_f - entity / architecture pair
------------------------------------------------... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/rd_pe_ss.vhd | 19 | 28350 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth.vhd | 27 | 68532 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/clk_x_pntrs_builtin.vhd | 19 | 43418 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/bd/BD_PR_3/hdl/BD_PR_3_wrapper.vhd | 1 | 8354 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Aug 5 18:37:52 2017
--Host : knuff running 64-bit Debian GNU/Linux 9.0... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
bgottschall/reloc | zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/imports/new/wrapper.vhd | 1 | 19020 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity wrapper is
generic (
DATAWIDTH : integer := 32
);
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/async_fifo_fg.vhd | 12 | 121997 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- ********************************************... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd | 19 | 17676 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/builtin/builtin_prim_v6.vhd | 19 | 37128 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/builtin/builtin_prim_v6.vhd | 19 | 37128 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_pf_sshft.vhd | 19 | 20160 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_fwft.vhd | 19 | 38466 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/rd_dc_as.vhd | 19 | 10777 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | mit |
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