Search is not available for this dataset
text stringlengths 75 104k |
|---|
def _ceil(self, address):
"""
Returns the smallest page boundary value not less than the address.
:rtype: int
:param address: the address to calculate its ceil.
:return: the ceil of C{address}.
"""
return (((address - 1) + self.page_size) & ~self.page_mask) & self... |
def _search(self, size, start=None, counter=0):
"""
Recursively searches the address space for enough free space to allocate C{size} bytes.
:param size: the size in bytes to allocate.
:param start: an address from where to start the search.
:param counter: internal parameter to ... |
def mmapFile(self, addr, size, perms, filename, offset=0):
"""
Creates a new file mapping in the memory address space.
:param addr: the starting address (took as hint). If C{addr} is C{0} the first big enough
chunk of memory will be selected as starting address.
:pa... |
def mmap(self, addr, size, perms, data_init=None, name=None):
"""
Creates a new mapping in the memory address space.
:param addr: the starting address (took as hint). If C{addr} is C{0} the first big enough
chunk of memory will be selected as starting address.
:para... |
def map_containing(self, address):
"""
Returns the L{MMap} object containing the address.
:param address: the address to obtain its mapping.
:rtype: L{MMap}
@todo: symbolic address
"""
page_offset = self._page(address)
if page_offset not in self._page2ma... |
def mappings(self):
"""
Returns a sorted list of all the mappings for this memory.
:return: a list of mappings.
:rtype: list
"""
result = []
for m in self.maps:
if isinstance(m, AnonMap):
result.append((m.start, m.end, m.perms, 0, ''))... |
def _maps_in_range(self, start, end):
"""
Generates the list of maps that overlaps with the range [start:end]
"""
# Search for the first matching map
addr = start
while addr < end:
if addr not in self:
addr += self.page_size
else:
... |
def munmap(self, start, size):
"""
Deletes the mappings for the specified address range and causes further
references to addresses within the range to generate invalid memory
references.
:param start: the starting address to delete.
:param size: the length of the unmappi... |
def pop_record_writes(self):
"""
Stop recording trace and return a `list[(address, value)]` of all the writes
that occurred, where `value` is of type list[str]. Can be called without
intermediate `pop_record_writes()`.
For example::
mem.push_record_writes()
... |
def munmap(self, start, size):
"""
Deletes the mappings for the specified address range and causes further
references to addresses within the range to generate invalid memory
references.
:param start: the starting address to delete.
:param size: the length of the unmappi... |
def read(self, address, size, force=False):
"""
Read a stream of potentially symbolic bytes from a potentially symbolic
address
:param address: Where to read from
:param size: How many bytes
:param force: Whether to ignore permissions
:rtype: list
"""
... |
def write(self, address, value, force=False):
"""
Write a value at address.
:param address: The address at which to write
:type address: int or long or Expression
:param value: Bytes to write
:type value: str or list
:param force: Whether to ignore permissions
... |
def _try_get_solutions(self, address, size, access, max_solutions=0x1000, force=False):
"""
Try to solve for a symbolic address, checking permissions when reading/writing size bytes.
:param Expression address: The address to solve for
:param int size: How many bytes to check permissions... |
def mmapFile(self, addr, size, perms, filename, offset=0):
"""
Creates a new file mapping in the memory address space.
:param addr: the starting address (took as hint). If C{addr} is C{0} the first big enough
chunk of memory will be selected as starting address.
:pa... |
def _import_concrete_memory(self, from_addr, to_addr):
"""
for each address in this range need to read from concrete and write to symbolic
it's possible that there will be invalid/unmapped addresses in this range. need to skip to next map if so
also need to mark all of these addresses as... |
def scan_mem(self, data_to_find):
"""
Scan for concrete bytes in all mapped memory. Successively yield addresses of all matches.
:param bytes data_to_find: String to locate
:return:
"""
# TODO: for the moment we just treat symbolic bytes as bytes that don't match.
... |
def _reg_name(self, reg_id):
"""
Translates a register ID from the disassembler object into the
register name based on manticore's alias in the register file
:param int reg_id: Register ID
"""
if reg_id >= X86_REG_ENDING:
logger.warning("Trying to get registe... |
def values_from(self, base):
"""
A reusable generator for increasing pointer-sized values from an address
(usually the stack).
"""
word_bytes = self._cpu.address_bit_size // 8
while True:
yield base
base += word_bytes |
def get_argument_values(self, model, prefix_args):
"""
Extract arguments for model from the environment and return as a tuple that
is ready to be passed to the model.
:param callable model: Python model of the function
:param tuple prefix_args: Parameters to pass to model before... |
def invoke(self, model, prefix_args=None):
"""
Invoke a callable `model` as if it was a native function. If
:func:`~manticore.models.isvariadic` returns true for `model`, `model` receives a single
argument that is a generator for function arguments. Pass a tuple of
arguments for ... |
def write_register(self, register, value):
"""
Dynamic interface for writing cpu registers
:param str register: register name (as listed in `self.all_registers`)
:param value: register value
:type value: int or long or Expression
"""
self._publish('will_write_reg... |
def read_register(self, register):
"""
Dynamic interface for reading cpu registers
:param str register: register name (as listed in `self.all_registers`)
:return: register value
:rtype: int or long or Expression
"""
self._publish('will_read_register', register)
... |
def emulate_until(self, target: int):
"""
Tells the CPU to set up a concrete unicorn emulator and use it to execute instructions
until target is reached.
:param target: Where Unicorn should hand control back to Manticore. Set to 0 for all instructions.
"""
self._concrete... |
def write_int(self, where, expression, size=None, force=False):
"""
Writes int to memory
:param int where: address to write to
:param expr: value to write
:type expr: int or BitVec
:param size: bit size of `expr`
:param force: whether to ignore memory permissions... |
def _raw_read(self, where: int, size=1) -> bytes:
"""
Selects bytes from memory. Attempts to do so faster than via read_bytes.
:param where: address to read from
:param size: number of bytes to read
:return: the bytes in memory
"""
map = self.memory.map_containin... |
def read_int(self, where, size=None, force=False):
"""
Reads int from memory
:param int where: address to read from
:param size: number of bits to read
:return: the value read
:rtype: int or BitVec
:param force: whether to ignore memory permissions
"""
... |
def write_bytes(self, where, data, force=False):
"""
Write a concrete or symbolic (or mixed) buffer to memory
:param int where: address to write to
:param data: data to write
:type data: str or list
:param force: whether to ignore memory permissions
"""
... |
def read_bytes(self, where, size, force=False):
"""
Read from memory.
:param int where: address to read data from
:param int size: number of bytes
:param force: whether to ignore memory permissions
:return: data
:rtype: list[int or Expression]
"""
... |
def write_string(self, where, string, max_length=None, force=False):
"""
Writes a string to memory, appending a NULL-terminator at the end.
:param int where: Address to write the string to
:param str string: The string to write to memory
:param int max_length:
The siz... |
def read_string(self, where, max_length=None, force=False):
"""
Read a NUL-terminated concrete buffer from memory. Stops reading at first symbolic byte.
:param int where: Address to read string from
:param int max_length:
The size in bytes to cap the string at, or None [defa... |
def push_bytes(self, data, force=False):
"""
Write `data` to the stack and decrement the stack pointer accordingly.
:param str data: Data to write
:param force: whether to ignore memory permissions
"""
self.STACK -= len(data)
self.write_bytes(self.STACK, data, fo... |
def pop_bytes(self, nbytes, force=False):
"""
Read `nbytes` from the stack, increment the stack pointer, and return
data.
:param int nbytes: How many bytes to read
:param force: whether to ignore memory permissions
:return: Data read from the stack
"""
da... |
def push_int(self, value, force=False):
"""
Decrement the stack pointer and write `value` to the stack.
:param int value: The value to write
:param force: whether to ignore memory permissions
:return: New stack pointer
"""
self.STACK -= self.address_bit_size // 8... |
def pop_int(self, force=False):
"""
Read a value from the stack and increment the stack pointer.
:param force: whether to ignore memory permissions
:return: Value read
"""
value = self.read_int(self.STACK, force=force)
self.STACK += self.address_bit_size // 8
... |
def decode_instruction(self, pc):
"""
This will decode an instruction from memory pointed by `pc`
:param int pc: address of the instruction
"""
# No dynamic code!!! #TODO!
# Check if instruction was already decoded
if pc in self._instruction_cache:
re... |
def execute(self):
"""
Decode, and execute one instruction pointed by register PC
"""
if issymbolic(self.PC):
raise ConcretizeRegister(self, 'PC', policy='ALL')
if not self.memory.access_ok(self.PC, 'x'):
raise InvalidMemoryAccess(self.PC, 'x')
s... |
def _publish_instruction_as_executed(self, insn):
"""
Notify listeners that an instruction has been executed.
"""
self._icount += 1
self._publish('did_execute_instruction', self._last_pc, self.PC, insn) |
def emulate(self, insn):
"""
Pick the right emulate function (maintains API compatiblity)
:param insn: single instruction to emulate/start emulation from
"""
if self._concrete:
self.concrete_emulate(insn)
else:
self.backup_emulate(insn) |
def concrete_emulate(self, insn):
"""
Start executing in Unicorn from this point until we hit a syscall or reach break_unicorn_at
:param capstone.CsInsn insn: The instruction object to emulate
"""
if not self.emu:
self.emu = ConcreteUnicornEmulator(self)
... |
def backup_emulate(self, insn):
"""
If we could not handle emulating an instruction, use Unicorn to emulate
it.
:param capstone.CsInsn instruction: The instruction object to emulate
"""
if not hasattr(self, 'backup_emu'):
self.backup_emu = UnicornEmulator(se... |
def viz_trace(view):
"""
Given a Manticore trace file, highlight the basic blocks.
"""
tv = TraceVisualizer(view, None)
if tv.workspace is None:
tv.workspace = get_workspace()
tv.visualize() |
def viz_live_trace(view):
"""
Given a Manticore trace file, highlight the basic blocks.
"""
tv = TraceVisualizer(view, None, live=True)
if tv.workspace is None:
tv.workspace = get_workspace()
# update due to singleton in case we are called after a clear
tv.live_update = True
tv.v... |
def visualize(self):
"""
Given a Manticore workspace, or trace file, highlight the basic blocks.
"""
if os.path.isfile(self.workspace):
t = threading.Thread(target=self.highlight_from_file,
args=(self.workspace,))
elif os.path.isdir(se... |
def t_TOKEN(t):
'[a-zA-Z0-9]+'
#print t.value,t.lexer.lexdata[t.lexer.lexpos-len(t.value):],re_TYPE.match(t.lexer.lexdata,t.lexer.lexpos-len(t.value))
if re_TYPE.match(t.value):
t.type = 'TYPE'
elif re_PTR.match(t.value):
t.type = 'PTR'
elif re_NUMBER.match(t.value):
if t.val... |
def p_expression_deref(p):
'expression : TYPE PTR LBRAKET expression RBRAKET'
size = sizes[p[1]]
address = p[4]
char_list = functions['read_memory'](address, size)
value = Operators.CONCAT(8 * len(char_list), *reversed(map(Operators.ORD, char_list)))
p[0] = value |
def p_expression_derefseg(p):
'expression : TYPE PTR SEGMENT COLOM LBRAKET expression RBRAKET'
size = sizes[p[1]]
address = p[6]
seg = functions['read_register'](p[3])
base, limit, _ = functions['get_descriptor'](seg)
address = base + address
char_list = functions['read_memory'](address, siz... |
def _get_flags(self, reg):
""" Build EFLAGS/RFLAGS from flags """
def make_symbolic(flag_expr):
register_size = 32 if reg == 'EFLAGS' else 64
value, offset = flag_expr
return Operators.ITEBV(register_size, value,
BitVecConstant(regis... |
def _set_flags(self, reg, res):
""" Set individual flags from a EFLAGS/RFLAGS value """
#assert sizeof (res) == 32 if reg == 'EFLAGS' else 64
for flag, offset in self._flags.items():
self.write(flag, Operators.EXTRACT(res, offset, 1)) |
def push(cpu, value, size):
"""
Writes a value in the stack.
:param value: the value to put in the stack.
:param size: the size of the value.
"""
assert size in (8, 16, cpu.address_bit_size)
cpu.STACK = cpu.STACK - size // 8
base, _, _ = cpu.get_descripto... |
def pop(cpu, size):
"""
Gets a value from the stack.
:rtype: int
:param size: the size of the value to consume from the stack.
:return: the value from the stack.
"""
assert size in (16, cpu.address_bit_size)
base, _, _ = cpu.get_descriptor(cpu.SS)
... |
def invalidate_cache(cpu, address, size):
""" remove decoded instruction from instruction cache """
cache = cpu.instruction_cache
for offset in range(size):
if address + offset in cache:
del cache[address + offset] |
def CPUID(cpu):
"""
CPUID instruction.
The ID flag (bit 21) in the EFLAGS register indicates support for the
CPUID instruction. If a software procedure can set and clear this
flag, the processor executing the procedure supports the CPUID
instruction. This instruction op... |
def AND(cpu, dest, src):
"""
Logical AND.
Performs a bitwise AND operation on the destination (first) and source
(second) operands and stores the result in the destination operand location.
Each bit of the result is set to 1 if both corresponding bits of the first and
se... |
def TEST(cpu, src1, src2):
"""
Logical compare.
Computes the bit-wise logical AND of first operand (source 1 operand)
and the second operand (source 2 operand) and sets the SF, ZF, and PF
status flags according to the result. The result is then discarded::
TEMP = ... |
def XOR(cpu, dest, src):
"""
Logical exclusive OR.
Performs a bitwise exclusive Operators.OR(XOR) operation on the destination (first)
and source (second) operands and stores the result in the destination
operand location.
Each bit of the result is 1 if the correspondin... |
def OR(cpu, dest, src):
"""
Logical inclusive OR.
Performs a bitwise inclusive OR operation between the destination (first)
and source (second) operands and stores the result in the destination operand location.
Each bit of the result of the OR instruction is set to 0 if both c... |
def AAA(cpu):
"""
ASCII adjust after addition.
Adjusts the sum of two unpacked BCD values to create an unpacked BCD
result. The AL register is the implied source and destination operand
for this instruction. The AAA instruction is only useful when it follows
an ADD instr... |
def AAD(cpu, imm=None):
"""
ASCII adjust AX before division.
Adjusts two unpacked BCD digits (the least-significant digit in the
AL register and the most-significant digit in the AH register) so that
a division operation performed on the result will yield a correct unpacked
... |
def AAM(cpu, imm=None):
"""
ASCII adjust AX after multiply.
Adjusts the result of the multiplication of two unpacked BCD values
to create a pair of unpacked (base 10) BCD values. The AX register is
the implied source and destination operand for this instruction. The AAM
... |
def AAS(cpu):
"""
ASCII Adjust AL after subtraction.
Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked
BCD result. The AL register is the implied source and destination operand for this instruction.
The AAS instruction is only useful when it ... |
def ADC(cpu, dest, src):
"""
Adds with carry.
Adds the destination operand (first operand), the source operand (second operand),
and the carry (CF) flag and stores the result in the destination operand. The state
of the CF flag represents a carry from a previous addition. When a... |
def ADD(cpu, dest, src):
"""
Add.
Adds the first operand (destination operand) and the second operand (source operand)
and stores the result in the destination operand. When an immediate value is used as
an operand, it is sign-extended to the length of the destination operand fo... |
def CMP(cpu, src1, src2):
"""
Compares two operands.
Compares the first source operand with the second source operand and sets the status flags
in the EFLAGS register according to the results. The comparison is performed by subtracting
the second operand from the first operand a... |
def CMPXCHG(cpu, dest, src):
"""
Compares and exchanges.
Compares the value in the AL, AX, EAX or RAX register (depending on the
size of the operand) with the first operand (destination operand). If
the two values are equal, the second operand (source operand) is loaded
... |
def CMPXCHG8B(cpu, dest):
"""
Compares and exchanges bytes.
Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if
operand size is 128 bits) with the operand (destination operand). If
the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in
RC... |
def DAA(cpu):
"""
Decimal adjusts AL after addition.
Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register
is the implied source and destination operand. If a decimal carry is detected, the CF
and AF flags are set accordingly.
The CF and... |
def DAS(cpu):
"""
Decimal adjusts AL after subtraction.
Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result.
The AL register is the implied source and destination operand. If a decimal borrow is detected,
the CF and AF flags are set accor... |
def DIV(cpu, src):
"""
Unsigned divide.
Divides (unsigned) the value in the AX register, DX:AX register pair,
or EDX:EAX or RDX:RAX register pair (dividend) by the source operand
(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX or
RDX:RAX registers. The ... |
def IDIV(cpu, src):
"""
Signed divide.
Divides (signed) the value in the AL, AX, or EAX register by the source
operand and stores the result in the AX, DX:AX, or EDX:EAX registers.
The source operand can be a general-purpose register or a memory
location. The action of t... |
def IMUL(cpu, *operands):
"""
Signed multiply.
Performs a signed multiplication of two operands. This instruction has
three forms, depending on the number of operands.
- One-operand form. This form is identical to that used by the MUL
instruction. Here, the sourc... |
def INC(cpu, dest):
"""
Increments by 1.
Adds 1 to the destination operand, while preserving the state of the
CF flag. The destination operand can be a register or a memory location.
This instruction allows a loop counter to be updated without disturbing
the CF flag. (Us... |
def MUL(cpu, src):
"""
Unsigned multiply.
Performs an unsigned multiplication of the first operand (destination
operand) and the second operand (source operand) and stores the result
in the destination operand. The destination operand is an implied operand
located in reg... |
def NEG(cpu, dest):
"""
Two's complement negation.
Replaces the value of operand (the destination operand) with its two's complement.
(This operation is equivalent to subtracting the operand from 0.) The destination operand is
located in a general-purpose register or a memory lo... |
def SBB(cpu, dest, src):
"""
Integer subtraction with borrow.
Adds the source operand (second operand) and the carry (CF) flag, and
subtracts the result from the destination operand (first operand). The
result of the subtraction is stored in the destination operand. The
... |
def SUB(cpu, dest, src):
"""
Subtract.
Subtracts the second operand (source operand) from the first operand
(destination operand) and stores the result in the destination operand.
The destination operand can be a register or a memory location; the
source operand can be a... |
def XADD(cpu, dest, src):
"""
Exchanges and adds.
Exchanges the first operand (destination operand) with the second operand
(source operand), then loads the sum of the two values into the destination
operand. The destination operand can be a register or a memory location;
... |
def BSWAP(cpu, dest):
"""
Byte swap.
Reverses the byte order of a 32-bit (destination) register: bits 0 through
7 are swapped with bits 24 through 31, and bits 8 through 15 are swapped
with bits 16 through 23. This instruction is provided for converting little-endian
val... |
def CMOVB(cpu, dest, src):
"""
Conditional move - Below/not above or equal.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CP... |
def CMOVA(cpu, dest, src):
"""
Conditional move - Above/not below or equal.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CP... |
def CMOVAE(cpu, dest, src):
"""
Conditional move - Above or equal/not below.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current C... |
def CMOVBE(cpu, dest, src):
"""
Conditional move - Below or equal/not above.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current C... |
def CMOVZ(cpu, dest, src):
"""
Conditional move - Equal/zero.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
:pa... |
def CMOVNZ(cpu, dest, src):
"""
Conditional move - Not equal/not zero.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
... |
def CMOVP(cpu, dest, src):
"""
Conditional move - Parity/parity even.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
... |
def CMOVNP(cpu, dest, src):
"""
Conditional move - Not parity/parity odd.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.... |
def CMOVG(cpu, dest, src):
"""
Conditional move - Greater.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
:param... |
def CMOVGE(cpu, dest, src):
"""
Conditional move - Greater or equal/not less.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current ... |
def CMOVLE(cpu, dest, src):
"""
Conditional move - Less or equal/not greater.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current ... |
def CMOVO(cpu, dest, src):
"""
Conditional move - Overflow.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
:para... |
def CMOVNO(cpu, dest, src):
"""
Conditional move - Not overflow.
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
... |
def CMOVS(cpu, dest, src):
"""
Conditional move - Sign (negative).
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CPU.
... |
def CMOVNS(cpu, dest, src):
"""
Conditional move - Not sign (non-negative).
Tests the status flags in the EFLAGS register and moves the source operand
(second operand) to the destination operand (first operand) if the given
test condition is true.
:param cpu: current CP... |
def LAHF(cpu):
"""
Loads status flags into AH register.
Moves the low byte of the EFLAGS register (which includes status flags
SF, ZF, AF, PF, and CF) to the AH register. Reserved bits 1, 3, and 5
of the EFLAGS register are set in the AH register::
AH = EFLAGS... |
def LEA(cpu, dest, src):
"""
Loads effective address.
Computes the effective address of the second operand (the source operand) and stores it in the first operand
(destination operand). The source operand is a memory address (offset part) specified with one of the processors
add... |
def MOVBE(cpu, dest, src):
"""
Moves data after swapping bytes.
Performs a byte swap operation on the data copied from the second operand (source operand) and store the result
in the first operand (destination operand). The source operand can be a general-purpose register, or memory loc... |
def SAHF(cpu):
"""
Stores AH into flags.
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values
from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0,
respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding
reserv... |
def SETA(cpu, dest):
"""
Sets byte if above.
Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF, 1, 0) in the
EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix
... |
def SETB(cpu, dest):
"""
Sets byte if below.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.CF, 1, 0)) |
def SETBE(cpu, dest):
"""
Sets byte if below or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.CF, cpu.ZF), 1, 0)) |
def SETC(cpu, dest):
"""
Sets if carry.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.CF, 1, 0)) |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.