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def SETE(cpu, dest):
"""
Sets byte if equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.ZF, 1, 0)) |
def SETGE(cpu, dest):
"""
Sets byte if greater or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.SF == cpu.OF, 1, 0)) |
def SETNAE(cpu, dest):
"""
Sets byte if not above or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.CF, 1, 0)) |
def SETNB(cpu, dest):
"""
Sets byte if not below.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.CF == False, 1, 0)) |
def SETNBE(cpu, dest):
"""
Sets byte if not below or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.CF == False, cpu.ZF == False), 1, 0)) |
def SETNG(cpu, dest):
"""
Sets byte if not greater.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), 1, 0)) |
def SETNLE(cpu, dest):
"""
Sets byte if not less or equal.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, Operators.AND(cpu.ZF == False, cpu.SF == cpu.OF), 1, 0)) |
def SETNO(cpu, dest):
"""
Sets byte if not overflow.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.OF == False, 1, 0)) |
def SETNS(cpu, dest):
"""
Sets byte if not sign.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.SF == False, 1, 0)) |
def SETNZ(cpu, dest):
"""
Sets byte if not zero.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.ZF == False, 1, 0)) |
def SETO(cpu, dest):
"""
Sets byte if overflow.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.OF, 1, 0)) |
def SETP(cpu, dest):
"""
Sets byte if parity.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.PF, 1, 0)) |
def SETPE(cpu, dest):
"""
Sets byte if parity even.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.PF, 1, 0)) |
def SETPO(cpu, dest):
"""
Sets byte if parity odd.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.PF == False, 1, 0)) |
def SETS(cpu, dest):
"""
Sets byte if sign.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.SF, 1, 0)) |
def SETZ(cpu, dest):
"""
Sets byte if zero.
:param cpu: current CPU.
:param dest: destination operand.
"""
dest.write(Operators.ITEBV(dest.size, cpu.ZF, 1, 0)) |
def XCHG(cpu, dest, src):
"""
Exchanges register/memory with register.
Exchanges the contents of the destination (first) and source (second)
operands. The operands can be two general-purpose registers or a register
and a memory location. If a memory operand is referenced, the pr... |
def LEAVE(cpu):
"""
High level procedure exit.
Releases the stack frame set up by an earlier ENTER instruction. The
LEAVE instruction copies the frame pointer (in the EBP register) into
the stack pointer register (ESP), which releases the stack space allocated
to the sta... |
def PUSH(cpu, src):
"""
Pushes a value onto the stack.
Decrements the stack pointer and then stores the source operand on the top of the stack.
:param cpu: current CPU.
:param src: source operand.
"""
# http://stackoverflow.com/questions/11291151/how-push-imm-en... |
def POPF(cpu):
"""
Pops stack into EFLAGS register.
:param cpu: current CPU.
"""
mask = (0x00000001 |
0x00000004 |
0x00000010 |
0x00000040 |
0x00000080 |
0x00000400 |
0x00000800)
... |
def POPFQ(cpu):
"""
Pops stack into EFLAGS register.
:param cpu: current CPU.
"""
mask = 0x00000001 | 0x00000004 | 0x00000010 | 0x00000040 | 0x00000080 | 0x00000400 | 0x00000800
cpu.EFLAGS = (cpu.EFLAGS & ~mask) | cpu.pop(64) & mask |
def INT(cpu, op0):
"""
Calls to interrupt procedure.
The INT n instruction generates a call to the interrupt or exception handler specified
with the destination operand. The INT n instruction is the general mnemonic for executing
a software-generated call to an interrupt handle... |
def CALL(cpu, op0):
"""
Procedure call.
Saves procedure linking information on the stack and branches to the called procedure specified using the target
operand. The target operand specifies the address of the first instruction in the called procedure. The operand can
be an imme... |
def RET(cpu, *operands):
"""
Returns from procedure.
Transfers program control to a return address located on the top of
the stack. The address is usually placed on the stack by a CALL instruction,
and the return is made to the instruction that follows the CALL instruction.
... |
def JA(cpu, target):
"""
Jumps short if above.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.CF == False, cpu.ZF == False), target.read(), cpu.PC) |
def JB(cpu, target):
"""
Jumps short if below.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF == True, target.read(), cpu.PC) |
def JBE(cpu, target):
"""
Jumps short if below or equal.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.OR(cpu.CF, cpu.ZF), target.read(), cpu.PC) |
def JC(cpu, target):
"""
Jumps short if carry.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF, target.read(), cpu.PC) |
def JCXZ(cpu, target):
"""
Jumps short if CX register is 0.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CX == 0, target.read(), cpu.PC) |
def JECXZ(cpu, target):
"""
Jumps short if ECX register is 0.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ECX == 0, target.read(), cpu.PC) |
def JRCXZ(cpu, target):
"""
Jumps short if RCX register is 0.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.RCX == 0, target.read(), cpu.PC) |
def JG(cpu, target):
"""
Jumps short if greater.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.AND(cpu.ZF == False, cpu.SF == cpu.OF), target.read(), cpu.PC) |
def JGE(cpu, target):
"""
Jumps short if greater or equal.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, (cpu.SF == cpu.OF), target.read(), cpu.PC) |
def JNB(cpu, target):
"""
Jumps short if not below.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.CF == False, target.read(), cpu.PC) |
def JNE(cpu, target):
"""
Jumps short if not equal.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.ZF, target.read(), cpu.PC) |
def JNG(cpu, target):
"""
Jumps short if not greater.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, Operators.OR(cpu.ZF, cpu.SF != cpu.OF), target.read(), cpu.PC) |
def JNO(cpu, target):
"""
Jumps short if not overflow.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.OF, target.read(), cpu.PC) |
def JNP(cpu, target):
"""
Jumps short if not parity.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.PF, target.read(), cpu.PC) |
def JNS(cpu, target):
"""
Jumps short if not sign.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, False == cpu.SF, target.read(), cpu.PC) |
def JO(cpu, target):
"""
Jumps short if overflow.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.OF, target.read(), cpu.PC) |
def JP(cpu, target):
"""
Jumps short if parity.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.PF, target.read(), cpu.PC) |
def JS(cpu, target):
"""
Jumps short if sign.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.SF, target.read(), cpu.PC) |
def JZ(cpu, target):
"""
Jumps short if zero.
:param cpu: current CPU.
:param target: destination operand.
"""
cpu.PC = Operators.ITEBV(cpu.address_bit_size, cpu.ZF, target.read(), cpu.PC) |
def LJMP(cpu, cs_selector, target):
"""
We are just going to ignore the CS selector for now.
"""
logger.info("LJMP: Jumping to: %r:%r", cs_selector.read(), target.read())
cpu.CS = cs_selector.read()
cpu.PC = target.read() |
def LOOP(cpu, dest):
"""
Loops according to ECX counter.
Performs a loop operation using the ECX or CX register as a counter.
Each time the LOOP instruction is executed, the count register is decremented,
then checked for 0. If the count is 0, the loop is terminated and program
... |
def LOOPNZ(cpu, target):
"""
Loops if ECX counter is nonzero.
:param cpu: current CPU.
:param target: destination operand.
"""
counter_name = {16: 'CX', 32: 'ECX', 64: 'RCX'}[cpu.address_bit_size]
counter = cpu.write_register(counter_name, cpu.read_register(count... |
def RCL(cpu, dest, src):
"""
Rotates through carry left.
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
... |
def RCR(cpu, dest, src):
"""
Rotates through carry right (RCR).
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can ... |
def ROL(cpu, dest, src):
"""
Rotates left (ROL).
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a re... |
def SAL(cpu, dest, src):
"""
The shift arithmetic left.
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the ... |
def SAR(cpu, dest, src):
"""
Shift arithmetic right.
The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to
the right (toward less significant bit locations). For each shift count, the least significant bit of the destina... |
def SHR(cpu, dest, src):
"""
Shift logical right.
The shift arithmetic right (SAR) and shift logical right (SHR)
instructions shift the bits of the destination operand to the right
(toward less significant bit locations). For each shift count, the
least significant bit o... |
def SHLD(cpu, dest, src, count):
"""
Double precision shift right.
Shifts the first operand (destination operand) to the left the number of bits specified by the third operand
(count operand). The second operand (source operand) provides bits to shift in from the right (starting with
... |
def _getMemoryBit(cpu, bitbase, bitoffset):
""" Calculate address and bit offset given a base address and a bit offset
relative to that address (in the form of asm operands) """
assert bitbase.type == 'memory'
assert bitbase.size >= bitoffset.size
addr = bitbase.address()
... |
def BSF(cpu, dest, src):
"""
Bit scan forward.
Searches the source operand (second operand) for the least significant
set bit (1 bit). If a least significant 1 bit is found, its bit index
is stored in the destination operand (first operand). The source operand
can be a r... |
def BSR(cpu, dest, src):
"""
Bit scan reverse.
Searches the source operand (second operand) for the most significant
set bit (1 bit). If a most significant 1 bit is found, its bit index is
stored in the destination operand (first operand). The source operand
can be a reg... |
def BT(cpu, dest, src):
"""
Bit Test.
Selects the bit in a bit string (specified with the first operand, called the bit base) at the
bit-position designated by the bit offset (specified by the second operand) and stores the value
of the bit in the CF flag. The bit base operand c... |
def BTC(cpu, dest, src):
"""
Bit test and complement.
Selects the bit in a bit string (specified with the first operand, called
the bit base) at the bit-position designated by the bit offset operand
(second operand), stores the value of the bit in the CF flag, and complements
... |
def POPCNT(cpu, dest, src):
"""
This instruction calculates of number of bits set to 1 in the second
operand (source) and returns the count in the first operand (a destination
register).
Count = 0;
For (i=0; i < OperandSize; i++) {
IF (SRC[ i] = 1) // i'th bit... |
def CMPS(cpu, dest, src):
"""
Compares string operands.
Compares the byte, word, double word or quad specified with the first source
operand with the byte, word, double or quad word specified with the second
source operand and sets the status flags in the EFLAGS register accordi... |
def LODS(cpu, dest, src):
"""
Loads string.
Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The
source operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers
(depending on the ad... |
def MOVS(cpu, dest, src):
"""
Moves data from string to string.
Moves the byte, word, or doubleword specified with the second operand (source operand) to the location specified
with the first operand (destination operand). Both the source and destination operands are located in memory. ... |
def SCAS(cpu, dest, src):
"""
Scans String.
Compares the byte, word, or double word specified with the memory operand
with the value in the AL, AX, EAX, or RAX register, and sets the status flags
according to the results. The memory operand address is read from either
th... |
def STOS(cpu, dest, src):
"""
Stores String.
Stores a byte, word, or doubleword from the AL, AX, or EAX register,
respectively, into the destination operand. The destination operand is
a memory location, the address of which is read from either the ES:EDI
or the ES:DI re... |
def ANDN(cpu, dest, src1, src2):
"""Performs a bitwise logical AND of inverted second operand (the first source operand)
with the third operand (the second source operand). The result is stored in the first
operand (destination operand).
DEST <- (NOT SRC1) bitwiseAND SRC2;... |
def SHLX(cpu, dest, src, count):
"""
The shift arithmetic left.
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted i... |
def SARX(cpu, dest, src, count):
"""
The shift arithmetic right.
:param cpu: current CPU.
:param dest: destination operand.
:param src: count operand.
"""
OperandSize = dest.size
count = count.read()
countMask = {8: 0x1f,
16: ... |
def PMINUB(cpu, dest, src):
"""
PMINUB: returns minimum of packed unsigned byte integers in the dest operand
see PMAXUB
"""
dest_value = dest.read()
src_value = src.read()
result = 0
for pos in range(0, dest.size, 8):
itema = (dest_value >> pos... |
def PXOR(cpu, dest, src):
"""
Logical exclusive OR.
Performs a bitwise logical exclusive-OR (XOR) operation on the quadword
source (second) and destination (first) operands and stores the result
in the destination operand location. The source operand can be an MMX(TM)
te... |
def _PUNPCKL(cpu, dest, src, item_size):
"""
Generic PUNPCKL
"""
assert dest.size == src.size
size = dest.size
dest_value = dest.read()
src_value = src.read()
mask = (1 << item_size) - 1
res = 0
count = 0
for pos in range(0, size //... |
def PSHUFW(cpu, op0, op1, op3):
"""
Packed shuffle words.
Copies doublewords from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).
:param cpu: current CPU.
:param op... |
def PSHUFD(cpu, op0, op1, op3):
"""
Packed shuffle doublewords.
Copies doublewords from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).
:param cpu: current CPU.
:pa... |
def PMOVMSKB(cpu, op0, op1):
"""
Moves byte mask to general-purpose register.
Creates an 8-bit mask made up of the most significant bit of each byte of the source operand
(second operand) and stores the result in the low byte or word of the destination operand
(first operand). T... |
def PSRLDQ(cpu, dest, src):
"""
Packed shift right logical double quadword.
Shifts the destination operand (first operand) to the right by the number
of bytes specified in the count operand (second operand). The empty high-order
bytes are cleared (set to all 0s). If the value sp... |
def MOVZX(cpu, op0, op1):
"""
Moves with zero-extend.
Copies the contents of the source operand (register or memory location) to the destination
operand (register) and zero extends the value to 16 or 32 bits. The size of the converted value
depends on the operand-size attribute:... |
def MOVSX(cpu, op0, op1):
"""
Moves with sign-extension.
Copies the contents of the source operand (register or memory location) to the destination
operand (register) and sign extends the value to 16::
OP0 = SignExtend(OP1);
:param cpu: current CPU.
:... |
def CQO(cpu):
"""
RDX:RAX = sign-extend of RAX.
"""
res = Operators.SEXTEND(cpu.RAX, 64, 128)
cpu.RAX = Operators.EXTRACT(res, 0, 64)
cpu.RDX = Operators.EXTRACT(res, 64, 64) |
def CDQ(cpu):
"""
EDX:EAX = sign-extend of EAX
"""
cpu.EDX = Operators.EXTRACT(Operators.SEXTEND(cpu.EAX, 32, 64), 32, 32) |
def CWDE(cpu):
"""
Converts word to doubleword.
::
DX = sign-extend of AX.
:param cpu: current CPU.
"""
bit = Operators.EXTRACT(cpu.AX, 15, 1)
cpu.EAX = Operators.SEXTEND(cpu.AX, 16, 32)
cpu.EDX = Operators.SEXTEND(bit, 1, 32) |
def RDTSC(cpu):
"""
Reads time-stamp counter.
Loads the current value of the processor's time-stamp counter into the
EDX:EAX registers. The time-stamp counter is contained in a 64-bit
MSR. The high-order 32 bits of the MSR are loaded into the EDX
register, and the low-o... |
def SYSCALL(cpu):
"""
Calls to interrupt procedure.
The INT n instruction generates a call to the interrupt or exception handler specified
with the destination operand. The INT n instruction is the general mnemonic for executing
a software-generated call to an interrupt handler.... |
def MOVLPD(cpu, dest, src):
"""
Moves low packed double-precision floating-point value.
Moves a double-precision floating-point value from the source operand (second operand) and the
destination operand (first operand). The source and destination operands can be an XMM register
... |
def MOVHPD(cpu, dest, src):
"""
Moves high packed double-precision floating-point value.
Moves a double-precision floating-point value from the source operand (second operand) and the
destination operand (first operand). The source and destination operands can be an XMM register
... |
def PSUBB(cpu, dest, src):
"""
Packed subtract.
Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed
integers of the destination operand (first operand), and stores the packed integer results in the
destination operand. The sourc... |
def POR(cpu, dest, src):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand
(first operand) and stores the result in the destination operand. The source operand can be an MMX technology
register or a 64-bit memory location or it... |
def XORPS(cpu, dest, src):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand
(first operand) and stores the result in the destination operand. The source operand can be an MMX technology
register or a 64-bit memory location or ... |
def VORPD(cpu, dest, src, src2):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and second source operand (third operand)
and stores the result in the destination operand (first operand).
"""
res = dest.write(src.read() | src2.read()) |
def VORPS(cpu, dest, src, src2):
"""
Performs a bitwise logical OR operation on the source operand (second operand) and second source operand (third operand)
and stores the result in the destination operand (first operand).
"""
res = dest.write(src.read() | src2.read()) |
def PTEST(cpu, dest, src):
""" PTEST
PTEST set the ZF flag if all bits in the result are 0 of the bitwise AND
of the first source operand (first operand) and the second source operand
(second operand). Also this sets the CF flag if all bits in the result
are 0 of the bitwise ... |
def MOVQ(cpu, dest, src):
"""
Move quadword.
Copies a quadword from the source operand (second operand) to the destination operand (first operand).
The source and destination operands can be MMX(TM) technology registers, XMM registers, or 64-bit memory
locations. This instructio... |
def MOVSD(cpu, dest, src):
"""
Move Scalar Double-Precision Floating-Point Value
Moves a scalar double-precision floating-point value from the source
operand (second operand) to the destination operand (first operand).
The source and destination operands can be XMM registers or ... |
def MOVSS(cpu, dest, src):
"""
Moves a scalar single-precision floating-point value
Moves a scalar single-precision floating-point value from the source operand (second operand)
to the destination operand (first operand). The source and destination operands can be XMM
registers ... |
def VEXTRACTF128(cpu, dest, src, offset):
"""Extract Packed Floating-Point Values
Extracts 128-bits of packed floating-point values from the source
operand (second operand) at an 128-bit offset from imm8[0] into the
destination operand (first operand). The destination may be either an
... |
def PALIGNR(cpu, dest, src, offset):
"""ALIGNR concatenates the destination operand (the first operand) and the source
operand (the second operand) into an intermediate composite, shifts the composite
at byte granularity to the right by a constant immediate, and extracts the right-
... |
def PSLLDQ(cpu, dest, src):
""" Packed Shift Left Logical Double Quadword
Shifts the destination operand (first operand) to the left by the number
of bytes specified in the count operand (second operand). The empty low-order
bytes are cleared (set to all 0s). If the value specified by ... |
def PSRLQ(cpu, dest, src):
"""Shift Packed Data Right Logical
Shifts the bits in the individual quadword in the destination operand to the right by
the number of bits specified in the count operand . As the bits in the data elements
are shifted right, the empty high-order bits are clear... |
def VPSHUFB(cpu, op0, op1, op3):
"""
Packed shuffle bytes.
Copies bytes from source operand (second operand) and inserts them in the destination operand
(first operand) at locations selected with the order operand (third operand).
:param cpu: current CPU.
:param op0: de... |
def XLATB(cpu):
"""
Table look-up translation.
Locates a byte entry in a table in memory, using the contents of the
AL register as a table index, then copies the contents of the table entry
back into the AL register. The index in the AL register is treated as
an unsigned... |
def XLATB(cpu):
"""
Table look-up translation.
Locates a byte entry in a table in memory, using the contents of the
AL register as a table index, then copies the contents of the table entry
back into the AL register. The index in the AL register is treated as
an unsigned... |
def constrain(self, constraint):
"""Constrain state.
:param manticore.core.smtlib.Bool constraint: Constraint to add
"""
constraint = self.migrate_expression(constraint)
self._constraints.add(constraint) |
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