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/*
*
* Clock, reset generation unit for ML501 board
*
* Implements clock generation according to design defines
*
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.O... |
/////////////////////////////////////////////////////////////////////
//// ////
//// CRP ////
//// DES Crypt Module ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// DES TEST BENCH ////
//// ////
//// Author: Rudolf Usselmann ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : des3_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DES3 core
//
module des3_top #(
parameter remove_parity_bits=0)
(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
w... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : des3_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-DES3 core
//
module des3_top_axi4lite (
// Clock & Reset
input logic c... |
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL ////
//// Select one of 16 sub-keys for round ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : dft_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-DFT core
//
module dft_top_axi4lite (
// Clock & Reset
input logic clk_... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : dft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DFT core
//
module dft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
/*------------------------------------------------------------------------------
* This code was generated by Spiral IIR Filter Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/lice... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : fir_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-FIR core
//
module fir_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : fir_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-FIR core
//
module fir_top_axi4lite (
// Clock & Reset
input logic clk_... |
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : idft_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-IDFT core
//
module idft_top_axi4lite (
// Clock & Reset
input logic c... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : idft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-IDFT core
//
module idft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
/*------------------------------------------------------------------------------
* This code was generated by Spiral IIR Filter Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/lice... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : iir_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-IIR core
//
module iir_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : iir_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-IIR core
//
module iir_top_axi4lite (
// Clock & Reset
input logic clk_... |
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.... |
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.... |
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.... |
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : md5_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-MD5 core
//
module md5_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : md5_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-MD5 core
//
module md5_top_axi4lite (
// Clock & Reset
input logic clk_... |
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic
applications.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is fre... |
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic applicati
-ons.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is fr... |
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission not... |
module wbram_top_axi4lite #(
parameter MEMORY_SIZE = 32'h0002_0000
)(
// Clock & Reset
input logic clk_i,
input logic rst_ni,
// AXI4-Lite Slave Interface
AXI_LITE.Slave slave
);
// Clocks and resets
wire wb_clk;
wire ... |
module wbram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output reg [31:0] wb_dat_o
);
reg mem_instr;
... |
module wbram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output reg [31:0] wb_dat_o
);
reg mem_instr;
... |
module ram_top_axi4lite #(
parameter MEMORY_SIZE = 32'h0002_0000
)(
// Clock & Reset
input logic clk_i,
input logic rst_ni,
// AXI4-Lite Slave Interface
AXI_LITE.Slave slave
);
// Clocks and resets
wire wb_clk;
wire ... |
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------... |
//======================================================================
//
// tb_modexp.v
// -----------
// Testbench modular exponentiation core.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, wit... |
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------... |
//======================================================================
//
// adder.v
// -------
// Adder with separate carry in and carry out. Used in the montprod
// amd residue modules of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.... |
//======================================================================
//
// blockmem1rw1.v
// --------------
// Synchronous block memory with one read and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
// paremeter OPW is operand word ... |
//======================================================================
//
// blockmem2r1w.v
// --------------
// Synchronous block memory with two read ports and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strom... |
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. The pointer is automatically increased
// when the... |
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. But write address is explicitly given.
//
// The m... |
//======================================================================
//
// modexp.v
// --------
// Top level wrapper for the modula exponentiation core. The core
// is used to implement public key algorithms such as RSA,
// DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
... |
//======================================================================
//
// modexp_core.v
// -------------
// Modular exponentiation core for implementing public key algorithms
// such as RSA, DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a le... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : modexp_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-RSA core
//
module modexp_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
//======================================================================
//
// montprod.v
// ---------
// Montgomery product calculator for the modular exponentiantion core.
//
// parameter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Peter Magnusson, Joachim Strombergs... |
//======================================================================
//
// residue.v
// ---------
// Modulus 2**2N residue calculator for montgomery calculations.
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : rsa_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-RSA core
//
module rsa_top_axi4lite (
// Clock & Reset
input logic clk_... |
//======================================================================
//
// shl.v
// -----
// One bit left shift of words with carry in and carry out. Used in
// the residue module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
/... |
//======================================================================
//
// shr32.v
// -------
// One bit right shift with carry in and carry out.
// Used in the montprod module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// R... |
//======================================================================
//
// sha256_core.v
// -------------
// Verilog 2001 implementation of the SHA-256 hash function.
// This is the internal core with wide interfaces.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights rese... |
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : sha256_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-SHA256 core
//
module sha256_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : sha256_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-SHA256 core
//
module sha256_top_axi4lite (
// Clock & Reset
input logic... |
//======================================================================
//
// sha256_w_mem_regs.v
// -------------------
// The W memory. This version uses 16 32-bit registers as a sliding
// window to generate the 64 words.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights ... |
`include "orpsoc-defines.sv"
`timescale 1 ns / 1 ps
import axi_pkg::*;
module axi_top (
sys_clk_in_p,
sys_clk_in_n,
`ifdef RESET_HIGH
rst_pad_i,
`else
rst_n_pad_i,
`endif
uart_srx_pad_i,
uart_cts_pad_i,
uart_stx_pad_o,
uart_rts_pad_o
);
input sys_clk_in_p;
input sys_clk_in_n;
`ifdef RESET_HIGH
... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : orpsoc_defines.v
// Project : Common Evaluation Platform (CEP)
// Description : Defines file for the CEP
// Notes : Core licensing information may be found in licenseLog.txt
//
`ifdef SYNTHESIS
`define RESET_HIGH
`endi... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-MOR1KX processor
//
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define... |
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_defines.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_top.v ////
//// ////
//// ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : uart_top_axi4lite.sv
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-UART core
//
module uart_top_axi4lite (
// Clock & Reset
input logic ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_transmitter.v ////
//// ////
//// ... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ... |
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applica... |
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applica... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-AES core
//
module aes_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applica... |
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applica... |
/////////////////////////////////////////////////////////////////////
//// ////
//// CRP ////
//// DES Crypt Module ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// DES TEST BENCH ////
//// ////
//// Author: Rudolf Usselmann ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : des3_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DES3 core
//
module des3_top #(
parameter remove_parity_bits=0)
(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
w... |
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL ////
//// Select one of 16 sub-keys for round ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ... |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : md5_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-MD5 core
//
module md5_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
... |
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic
applications.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is fre... |
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic applicati
-ons.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is fr... |
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------... |
//======================================================================
//
// tb_modexp.v
// -----------
// Testbench modular exponentiation core.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, wit... |
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------... |
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