KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

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////////////////////////////////////////////////////////////////////// //// //// //// uart_top.v //// //// //// //// ...
////////////////////////////////////////////////////////////////////// //// //// //// uart_transmitter.v //// //// //// //// ...
////////////////////////////////////////////////////////////////////// //// //// //// uart_wb.v //// //// //// //// ...
/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...
/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...
/* Copyright (c) 2013 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publi...
/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...
`timescale 1ns/1ps module AEStopwrapper(MASRST, clk, mode, rst, kld, ld, done, key, text_in, text_out, Pause, WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1); input clk, rst, mode, ld, kld, MASRST; output done; input SPCREQ; input SPCDIS; input [127:0] key; ...
// AES cipher/decipher unit // Controlled by the "mode" signal // "mode = 1 => cipher, mode = 0, => decipher //`include "timescale.v" // the top-level module `timescale 1ns/1ps module aes_encoder_decoder(clk, mode, rst, kld, ld, done, key, text_in, text_out, w01, w02, w03, w04); input clk, rst, mode; input ld; in...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
/************************************************************************* * FILE: clkgen.v * Written By: Michael J. Kelley * Written On: March 4, 1996 * Updated By: Michael J. Kelley * Updated On: March 4, 1996 * * Description: * * This modules is used to generate a one-phase clock to be used with ...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
`include "./dlx.defines" `timescale 1ns/1ps module DAP (clk, MRST, s1,s2, DB1, DB2, DCP, SEL); input clk; input MRST; input [31:0] DB1, DB2; input s1, s2; output reg[31:0] DCP; output reg[1:0] SEL; always @(posedge clk) begin if (MRST == 1'b0) begin DCP <= 32'b0; SEL <= 2'b00; end else if ((s2 == 1'b1) && (s1 == 1'b...
`include "./dlx.defines" `timescale 1ns/1ps // assuming external read and write through memory as well (here just external) highlighted by E // DInE won't be inserted into test boundary chain // DOUT and DIN are reverse with respect to that of Dcache module Dcache (DOutE1, DOutE2, DOutE3, DOutE4, DOutE5, DOut, DAdd...
`include "./dlx.defines" `timescale 1ns/1ps // assuming external read and write through memory as well (here just external) highlighted by E // DInE won't be inserted into test boundary chain // DOUT and DIN are reverse with respect to that of Dcache module SystemMem (DOutE1, DOutE2, DOutE3, DOut, DAddrE1, DAddrE2,...
`timescale 1ns/1ps module debug_AES(clk, MRST, mode, ld, pause, done, key, t_in, t_out, DCP, Sel, EV, Val, TP, TPE, w01, w02, w03, w04); input clk, MRST, mode, ld, done, pause; input [127:0] key, t_in, t_out; input [31:0] DCP; input [1:0] Sel; input [31:0] w01, w02, w03, w04; output reg [31:0] Val, TP; output reg TPE;...
`include "./dlx.defines" `timescale 1ns/1ps module debug_DLX1 (clk, MRST, MRSTproc, stop, pause, IIn, IAddr, DIn, DOut, DAddr, DRead, DWrite, SPR1, SPR2, DCP, Sel, TP, TPE, EV, Val); // SPR - Special Purpose Register // DCP - Debug Configuration Port // EV - transfer of event occurence info from debug logic to securi...
`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" module debug_FFT (clk, MRST, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, DCP, Sel, EV, Val, TP, TPE); `FFT128paramnb //nb is the data bit width input clk; input MRST; input START; input [3:0] SHIFT; input [nb-1:0] DR, DI ; input RDY, OVF1, OVF2; inp...
`include "./dlx.defines" `timescale 1ns/1ps module debug_mem (clk, MRST, din, dout, daddr, dread, dwrite, din1, dout1, daddr1, dread1, dwrite1, din2, dout2, daddr2, dread2, dwrite2, din3, dout3, daddr3, dread3, dwrite3, DCP, Sel, EV, Val, TP, TPE); input clk, MRST; input [31:0] din, din1, din2, din3, dout, dout1, dou...
`include "spi_defines.v" `include "timescale.v" module debug_SPI(clk, MRST, go, last_bit, dat_i, we_i, tx_sel, err_i, divider, s_out, DCP, Sel, EV, Val, TP, TPE); input clk, MRST, go, last_bit, we_i, err_i; input s_out; input [31:0] dat_i; input [3:0] tx_sel; input [15:0] divider; input [31:0] DCP; input [1:0] Sel;...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" module FFT128wrapper(MASRST, CLK, RSTT, ED, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1); `FFT128paramnb //nb is the data bit width output R...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
`include "./dlx.defines" `timescale 1ns/1ps // extending it for memory operations (here external represented by E) module IcacheSP ( PHI1, MRST, IAddr, IIn, IAddrE, IInE, IWriteE ); parameter WORDS = 128; input PHI1; input MRST; input [`WordSize] IAddr; output reg[`WordSize] IIn; input [`WordSize] IAddrE; input IWrit...
`include "./dlx.defines" `timescale 1ns/1ps // extending it for memory operations (here external represented by E) module Icache ( PHI1, MRST, IAddr, IIn, IAddrE, IInE, IWriteE ); parameter WORDS = 64; input PHI1; input MRST; input [`WordSize] IAddr; output reg[`WordSize] IIn; input [`WordSize] IAddrE; input IWriteE;...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
// FFT active signal - RSTF from 1-0, STARTF from 1-0 (time is 880+10 clock cycles OR above signals back to 1) // DLX processor (also ICache) - MRSTD from 0-1 (have to be MRSTD back to 1 as progs are of var length) // Memory (DCache) - DReadED and DWriteED must be low (practice should be followed although functionally...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
`include "./dlx.defines" `timescale 1ns/1ps module securitypolicy( PHI1, MASRST, // One-Phase clock for DLX DAddr, DAddrE1, DAddrE2, DAddrE3, DAddrE4, DAddrE5, DRead, DWrite, DWriteE1, DWriteE2, DWriteE3, DWriteE4, DWriteE5, DOut, DOutE1, DOutE2, DOutE3, DOutE4, DOutE5, DIn, // Data Cac...
////////////////////////////////////////////////////////////////////// //// //// //// spi_clgen.v //// //// //// //// This file is part of the SPI I...
////////////////////////////////////////////////////////////////////// //// //// //// spi_define.v //// //// //// //// This file is part of the SPI I...
////////////////////////////////////////////////////////////////////// //// //// //// spi_shift.v //// //// //// //// This file is part of the SPI I...
////////////////////////////////////////////////////////////////////// //// //// //// spi_top.v //// //// //// //// This file is part of the SPI I...
`timescale 1ns / 1ps
`include "./dlx.defines" `timescale 1ns/1ps module together ( PHI, MASRST, // One-Phase clock for DLX DAddr, DAddrE, DAddrE2, DAddrE3, DRead, DWrite, DReadE, DWriteE, DReadE2, DWriteE2, DReadE3, DWriteE3, DOut, DOutE, DOutE2, DOutE3, DIn, DInE, DInE2, DInE3, STATE, IAddr, IAddrE, IRead, I...
/************************************************************************* * FILE: dlx.v * Written By: Michael J. Kelley * Written On: December 18, 1995 * Updated By: Michael J. Kelley * Updated On: March 4, 1996 * * Description: * * This file contains the hardware description of the DLX architectu...
`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" `include "./dlx.defines" `include "spi_defines.v" `include "timescale.v" // connection FFT - DLX - AES - (probably USB)-external (F - D - A) // same clocks for all modules // adding the securitypolicycontroller // needs to modify the DAAddrESP to other types (FFT-D...
`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" `include "./dlx.defines" `include "spi_defines.v" `include "timescale.v" module test; `FFT128paramnb // FFT signals reg MASRST; reg CLKF, RSTF, EDF, STARTF; reg [3:0] SHIFTF; reg [nb-1:0] DRF; reg [nb-1:0] DIF; wire RDYF; wire [nb+3:0] DOIF; wire [nb+3:0] DORF; re...
///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...
/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...
/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...
/* Copyright (c) 2013 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publi...
/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...
/* * Copyright 2012, Homer Hsing <homer.hsing@gmail.com> * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applica...
/* * Copyright 2012, Homer Hsing <homer.hsing@gmail.com> * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applica...
// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : aes_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-AES core // module aes_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...
/* * Copyright 2012, Homer Hsing <homer.hsing@gmail.com> * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applica...
/* * Copyright 2012, Homer Hsing <homer.hsing@gmail.com> * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applica...
////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// CRP //// //// DES Crypt Module //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// DES //// //// DES Top Level module //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// DES TEST BENCH //// //// //// //// Author: Rudolf Usselmann ...
// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : des3_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-DES3 core // module des3_top #( parameter remove_parity_bits=0) ( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, w...
///////////////////////////////////////////////////////////////////// //// //// //// KEY_SEL //// //// Select one of 16 sub-keys for round //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...
////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...
// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : md5_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-MD5 core // module md5_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...
/***************************************************************** Pancham is an MD5 compliant IP core for cryptographic applications. Copyright (C) 2003 Swapnajit Mittra, Project VeriPage (Contact email: verilog_tutorial at hotmail.com Website : http://www.angelfire.com/ca/verilog) This library is fre...
/***************************************************************** Pancham is an MD5 compliant IP core for cryptographic applicati -ons. Copyright (C) 2003 Swapnajit Mittra, Project VeriPage (Contact email: verilog_tutorial at hotmail.com Website : http://www.angelfire.com/ca/verilog) This library is fr...
////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...
//------------------------------------------------------------------ // Simulator directives. //------------------------------------------------------------------ `timescale 1ns/100ps //------------------------------------------------------------------ // Test module. //------------------------------------------------...
//====================================================================== // // tb_modexp.v // ----------- // Testbench modular exponentiation core. // // // Author: Joachim Strombergson, Peter Magnusson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, wit...
//------------------------------------------------------------------ // Simulator directives. //------------------------------------------------------------------ `timescale 1ns/100ps //------------------------------------------------------------------ // Test module. //------------------------------------------------...
////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...
//====================================================================== // // adder.v // ------- // Adder with separate carry in and carry out. Used in the montprod // amd residue modules of the modexp core. // // // Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved....
//====================================================================== // // blockmem1rw1.v // -------------- // Synchronous block memory with one read and one write port. // The data size is the same for both read and write operations. // // The memory is used in the modexp core. // // paremeter OPW is operand word ...
//====================================================================== // // blockmem2r1w.v // -------------- // Synchronous block memory with two read ports and one write port. // The data size is the same for both read and write operations. // // The memory is used in the modexp core. // // // Author: Joachim Strom...
//====================================================================== // // blockmem2r1wptr.v // ----------------- // Synchronous block memory with two read ports and one write port. // For port 1 the address is implicit and instead given by the // internal pointer. The pointer is automatically increased // when the...
//====================================================================== // // blockmem2r1wptr.v // ----------------- // Synchronous block memory with two read ports and one write port. // For port 1 the address is implicit and instead given by the // internal pointer. But write address is explicitly given. // // The m...
//====================================================================== // // modexp.v // -------- // Top level wrapper for the modula exponentiation core. The core // is used to implement public key algorithms such as RSA, // DH, ElGamal etc. // // The core calculates the following function: // // C = M ** e mod N ...
//====================================================================== // // modexp_core.v // ------------- // Modular exponentiation core for implementing public key algorithms // such as RSA, DH, ElGamal etc. // // The core calculates the following function: // // C = M ** e mod N // // M is a message with a le...
module modexp_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, wb_ack_o, wb_err_o, wb_dat_o, wb_clk_i, wb_rst_i, int_o ); parameter dw = 32; parameter aw = 32; input [aw-1:0] wb_adr_i; //Address input wb_cyc_i; //bus cycle input [dw-1:0] wb_dat_i; //Data IN...
//====================================================================== // // montprod.v // --------- // Montgomery product calculator for the modular exponentiantion core. // // parameter OPW is operand word width in bits. // parameter ADW is address width in bits. // // // Author: Peter Magnusson, Joachim Strombergs...
//====================================================================== // // residue.v // --------- // Modulus 22N residue calculator for montgomery calculations. // // m_residue_2_2N_array( N, M, Nr) // Nr = 00...01 ; Nr = 1 == 2(2N-2N) // for (int i = 0; i < 2 * N; i++) // Nr = Nr shift left 1 // if...
//====================================================================== // // shl.v // ----- // One bit left shift of words with carry in and carry out. Used in // the residue module of the modexp core. // // // Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // /...
//====================================================================== // // shr32.v // ------- // One bit right shift with carry in and carry out. // Used in the montprod module of the modexp core. // // // Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // // R...
//====================================================================== // // sha256_core.v // ------------- // Verilog 2001 implementation of the SHA-256 hash function. // This is the internal core with wide interfaces. // // // Author: Joachim Strombergson // Copyright (c) 2013, Secworks Sweden AB // All rights rese...
//====================================================================== // // sha256_k_constants.v // -------------------- // The table K with constants in the SHA-256 hash function. // // // Author: Joachim Strombergson // Copyright (c) 2013, Secworks Sweden AB // All rights reserved. // // Redistribution and use in ...
// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : sha256_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-SHA256 core // module sha256_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...
//====================================================================== // // sha256_w_mem_regs.v // ------------------- // The W memory. This version uses 16 32-bit registers as a sliding // window to generate the 64 words. // // // Author: Joachim Strombergson // Copyright (c) 2013, Secworks Sweden AB // All rights ...
////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...
/* * This source file contains a Verilog description of an IP core * automatically generated by the SPIRAL HDL Generator. * * This product includes a hardware design developed by Carnegie Mellon University. * * Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project, * Carnegie Mellon University * * ...
// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : dft_top_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-DFT core // module dft_top_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...

////////////////////////////////////////////////////////////////////// //// //// //// uart_top.v //// //// //// //// ...

////////////////////////////////////////////////////////////////////// //// //// //// uart_transmitter.v //// //// //// //// ...

////////////////////////////////////////////////////////////////////// //// //// //// uart_wb.v //// //// //// //// ...

/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...

/* Copyright (c) 2013 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publi...

/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...

`timescale 1ns/1ps module AEStopwrapper(MASRST, clk, mode, rst, kld, ld, done, key, text_in, text_out, Pause, WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1); input clk, rst, mode, ld, kld, MASRST; output done; input SPCREQ; input SPCDIS; input [127:0] key; ...

// AES cipher/decipher unit // Controlled by the "mode" signal // "mode = 1 => cipher, mode = 0, => decipher //`include "timescale.v" // the top-level module `timescale 1ns/1ps module aes_encoder_decoder(clk, mode, rst, kld, ld, done, key, text_in, text_out, w01, w02, w03, w04); input clk, rst, mode; input ld; in...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

/************************************************************************* * FILE: clkgen.v * Written By: Michael J. Kelley * Written On: March 4, 1996 * Updated By: Michael J. Kelley * Updated On: March 4, 1996 * * Description: * * This modules is used to generate a one-phase clock to be used with ...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

`include "./dlx.defines" `timescale 1ns/1ps module DAP (clk, MRST, s1,s2, DB1, DB2, DCP, SEL); input clk; input MRST; input [31:0] DB1, DB2; input s1, s2; output reg[31:0] DCP; output reg[1:0] SEL; always @(posedge clk) begin if (MRST == 1'b0) begin DCP <= 32'b0; SEL <= 2'b00; end else if ((s2 == 1'b1) && (s1 == 1'b...

`include "./dlx.defines" `timescale 1ns/1ps // assuming external read and write through memory as well (here just external) highlighted by E // DInE won't be inserted into test boundary chain // DOUT and DIN are reverse with respect to that of Dcache module Dcache (DOutE1, DOutE2, DOutE3, DOutE4, DOutE5, DOut, DAdd...

`include "./dlx.defines" `timescale 1ns/1ps // assuming external read and write through memory as well (here just external) highlighted by E // DInE won't be inserted into test boundary chain // DOUT and DIN are reverse with respect to that of Dcache module SystemMem (DOutE1, DOutE2, DOutE3, DOut, DAddrE1, DAddrE2,...

`timescale 1ns/1ps module debug_AES(clk, MRST, mode, ld, pause, done, key, t_in, t_out, DCP, Sel, EV, Val, TP, TPE, w01, w02, w03, w04); input clk, MRST, mode, ld, done, pause; input [127:0] key, t_in, t_out; input [31:0] DCP; input [1:0] Sel; input [31:0] w01, w02, w03, w04; output reg [31:0] Val, TP; output reg TPE;...

`include "./dlx.defines" `timescale 1ns/1ps module debug_DLX1 (clk, MRST, MRSTproc, stop, pause, IIn, IAddr, DIn, DOut, DAddr, DRead, DWrite, SPR1, SPR2, DCP, Sel, TP, TPE, EV, Val); // SPR - Special Purpose Register // DCP - Debug Configuration Port // EV - transfer of event occurence info from debug logic to securi...

`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" module debug_FFT (clk, MRST, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, DCP, Sel, EV, Val, TP, TPE); `FFT128paramnb //nb is the data bit width input clk; input MRST; input START; input [3:0] SHIFT; input [nb-1:0] DR, DI ; input RDY, OVF1, OVF2; inp...

`include "./dlx.defines" `timescale 1ns/1ps module debug_mem (clk, MRST, din, dout, daddr, dread, dwrite, din1, dout1, daddr1, dread1, dwrite1, din2, dout2, daddr2, dread2, dwrite2, din3, dout3, daddr3, dread3, dwrite3, DCP, Sel, EV, Val, TP, TPE); input clk, MRST; input [31:0] din, din1, din2, din3, dout, dout1, dou...

`include "spi_defines.v" `include "timescale.v" module debug_SPI(clk, MRST, go, last_bit, dat_i, we_i, tx_sel, err_i, divider, s_out, DCP, Sel, EV, Val, TP, TPE); input clk, MRST, go, last_bit, we_i, err_i; input s_out; input [31:0] dat_i; input [3:0] tx_sel; input [15:0] divider; input [31:0] DCP; input [1:0] Sel;...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" module FFT128wrapper(MASRST, CLK, RSTT, ED, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1); `FFT128paramnb //nb is the data bit width output R...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

`include "./dlx.defines" `timescale 1ns/1ps // extending it for memory operations (here external represented by E) module IcacheSP ( PHI1, MRST, IAddr, IIn, IAddrE, IInE, IWriteE ); parameter WORDS = 128; input PHI1; input MRST; input [`WordSize] IAddr; output reg[`WordSize] IIn; input [`WordSize] IAddrE; input IWrit...

`include "./dlx.defines" `timescale 1ns/1ps // extending it for memory operations (here external represented by E) module Icache ( PHI1, MRST, IAddr, IIn, IAddrE, IInE, IWriteE ); parameter WORDS = 64; input PHI1; input MRST; input [`WordSize] IAddr; output reg[`WordSize] IIn; input [`WordSize] IAddrE; input IWriteE;...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

// FFT active signal - RSTF from 1-0, STARTF from 1-0 (time is 880+10 clock cycles OR above signals back to 1) // DLX processor (also ICache) - MRSTD from 0-1 (have to be MRSTD back to 1 as progs are of var length) // Memory (DCache) - DReadED and DWriteED must be low (practice should be followed although functionally...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

`include "./dlx.defines" `timescale 1ns/1ps module securitypolicy( PHI1, MASRST, // One-Phase clock for DLX DAddr, DAddrE1, DAddrE2, DAddrE3, DAddrE4, DAddrE5, DRead, DWrite, DWriteE1, DWriteE2, DWriteE3, DWriteE4, DWriteE5, DOut, DOutE1, DOutE2, DOutE3, DOutE4, DOutE5, DIn, // Data Cac...

////////////////////////////////////////////////////////////////////// //// //// //// spi_clgen.v //// //// //// //// This file is part of the SPI I...

////////////////////////////////////////////////////////////////////// //// //// //// spi_define.v //// //// //// //// This file is part of the SPI I...

////////////////////////////////////////////////////////////////////// //// //// //// spi_shift.v //// //// //// //// This file is part of the SPI I...

////////////////////////////////////////////////////////////////////// //// //// //// spi_top.v //// //// //// //// This file is part of the SPI I...

`timescale 1ns / 1ps

`include "./dlx.defines" `timescale 1ns/1ps module together ( PHI, MASRST, // One-Phase clock for DLX DAddr, DAddrE, DAddrE2, DAddrE3, DRead, DWrite, DReadE, DWriteE, DReadE2, DWriteE2, DReadE3, DWriteE3, DOut, DOutE, DOutE2, DOutE3, DIn, DInE, DInE2, DInE3, STATE, IAddr, IAddrE, IRead, I...

/************************************************************************* * FILE: dlx.v * Written By: Michael J. Kelley * Written On: December 18, 1995 * Updated By: Michael J. Kelley * Updated On: March 4, 1996 * * Description: * * This file contains the hardware description of the DLX architectu...

`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" `include "./dlx.defines" `include "spi_defines.v" `include "timescale.v" // connection FFT - DLX - AES - (probably USB)-external (F - D - A) // same clocks for all modules // adding the securitypolicycontroller // needs to modify the DAAddrESP to other types (FFT-D...

`timescale 1 ns / 1 ps `include "FFT128_CONFIG.inc" `include "./dlx.defines" `include "spi_defines.v" `include "timescale.v" module test; `FFT128paramnb // FFT signals reg MASRST; reg CLKF, RSTF, EDF, STARTF; reg [3:0] SHIFTF; reg [nb-1:0] DRF; reg [nb-1:0] DIF; wire RDYF; wire [nb+3:0] DOIF; wire [nb+3:0] DORF; re...

///////////////////////////////////////////////////////////////////// //// //// //// FFT/IFFT 128 points transform //// //// //// //// Authors: Anatoliy Sergienko, Volod...

/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...

/* Copyright (c) 2013 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publi...

/* Copyright (c) 2013-2017 by the author(s) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, ...

/* * Copyright 2012, Homer Hsing <homer.hsing@gmail.com> * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applica...

// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : aes_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-AES core // module aes_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...

/* * Copyright 2012, Homer Hsing <homer.hsing@gmail.com> * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applica...

////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...

///////////////////////////////////////////////////////////////////// //// //// //// CRP //// //// DES Crypt Module //// //// ...

///////////////////////////////////////////////////////////////////// //// //// //// DES //// //// DES Top Level module //// //// ...

///////////////////////////////////////////////////////////////////// //// //// //// DES TEST BENCH //// //// //// //// Author: Rudolf Usselmann ...

// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : des3_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-DES3 core // module des3_top #( parameter remove_parity_bits=0) ( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, w...

///////////////////////////////////////////////////////////////////// //// //// //// KEY_SEL //// //// Select one of 16 sub-keys for round //// //// ...

///////////////////////////////////////////////////////////////////// //// //// //// SBOX //// //// The SBOX is essentially a 64x4 ROM //// //// ...

////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...

// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : md5_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-MD5 core // module md5_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...

/***************************************************************** Pancham is an MD5 compliant IP core for cryptographic applications. Copyright (C) 2003 Swapnajit Mittra, Project VeriPage (Contact email: verilog_tutorial at hotmail.com Website : http://www.angelfire.com/ca/verilog) This library is fre...

/***************************************************************** Pancham is an MD5 compliant IP core for cryptographic applicati -ons. Copyright (C) 2003 Swapnajit Mittra, Project VeriPage (Contact email: verilog_tutorial at hotmail.com Website : http://www.angelfire.com/ca/verilog) This library is fr...

////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...

//------------------------------------------------------------------ // Simulator directives. //------------------------------------------------------------------ `timescale 1ns/100ps //------------------------------------------------------------------ // Test module. //------------------------------------------------...

//====================================================================== // // tb_modexp.v // ----------- // Testbench modular exponentiation core. // // // Author: Joachim Strombergson, Peter Magnusson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, wit...

//------------------------------------------------------------------ // Simulator directives. //------------------------------------------------------------------ `timescale 1ns/100ps //------------------------------------------------------------------ // Test module. //------------------------------------------------...

////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...

//====================================================================== // // adder.v // ------- // Adder with separate carry in and carry out. Used in the montprod // amd residue modules of the modexp core. // // // Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved....

//====================================================================== // // blockmem1rw1.v // -------------- // Synchronous block memory with one read and one write port. // The data size is the same for both read and write operations. // // The memory is used in the modexp core. // // paremeter OPW is operand word ...

//====================================================================== // // blockmem2r1w.v // -------------- // Synchronous block memory with two read ports and one write port. // The data size is the same for both read and write operations. // // The memory is used in the modexp core. // // // Author: Joachim Strom...

//====================================================================== // // blockmem2r1wptr.v // ----------------- // Synchronous block memory with two read ports and one write port. // For port 1 the address is implicit and instead given by the // internal pointer. The pointer is automatically increased // when the...

//====================================================================== // // blockmem2r1wptr.v // ----------------- // Synchronous block memory with two read ports and one write port. // For port 1 the address is implicit and instead given by the // internal pointer. But write address is explicitly given. // // The m...

//====================================================================== // // modexp.v // -------- // Top level wrapper for the modula exponentiation core. The core // is used to implement public key algorithms such as RSA, // DH, ElGamal etc. // // The core calculates the following function: // // C = M ** e mod N ...

//====================================================================== // // modexp_core.v // ------------- // Modular exponentiation core for implementing public key algorithms // such as RSA, DH, ElGamal etc. // // The core calculates the following function: // // C = M ** e mod N // // M is a message with a le...

module modexp_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, wb_ack_o, wb_err_o, wb_dat_o, wb_clk_i, wb_rst_i, int_o ); parameter dw = 32; parameter aw = 32; input [aw-1:0] wb_adr_i; //Address input wb_cyc_i; //bus cycle input [dw-1:0] wb_dat_i; //Data IN...

//====================================================================== // // montprod.v // --------- // Montgomery product calculator for the modular exponentiantion core. // // parameter OPW is operand word width in bits. // parameter ADW is address width in bits. // // // Author: Peter Magnusson, Joachim Strombergs...

//====================================================================== // // residue.v // --------- // Modulus 2**2N residue calculator for montgomery calculations. // // m_residue_2_2N_array( N, M, Nr) // Nr = 00...01 ; Nr = 1 == 2**(2N-2N) // for (int i = 0; i < 2 * N; i++) // Nr = Nr shift left 1 // if...

//====================================================================== // // shl.v // ----- // One bit left shift of words with carry in and carry out. Used in // the residue module of the modexp core. // // // Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // /...

//====================================================================== // // shr32.v // ------- // One bit right shift with carry in and carry out. // Used in the montprod module of the modexp core. // // // Author: Peter Magnusson, Joachim Strömbergson // Copyright (c) 2015, NORDUnet A/S All rights reserved. // // R...

//====================================================================== // // sha256_core.v // ------------- // Verilog 2001 implementation of the SHA-256 hash function. // This is the internal core with wide interfaces. // // // Author: Joachim Strombergson // Copyright (c) 2013, Secworks Sweden AB // All rights rese...

//====================================================================== // // sha256_k_constants.v // -------------------- // The table K with constants in the SHA-256 hash function. // // // Author: Joachim Strombergson // Copyright (c) 2013, Secworks Sweden AB // All rights reserved. // // Redistribution and use in ...

// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : sha256_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-SHA256 core // module sha256_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...

//====================================================================== // // sha256_w_mem_regs.v // ------------------- // The W memory. This version uses 16 32-bit registers as a sliding // window to generate the 64 words. // // // Author: Joachim Strombergson // Copyright (c) 2013, Secworks Sweden AB // All rights ...

////////////////////////////////////////////////////////////////////// //// //// //// timescale.v //// //// //// //// ...

/* * This source file contains a Verilog description of an IP core * automatically generated by the SPIRAL HDL Generator. * * This product includes a hardware design developed by Carnegie Mellon University. * * Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project, * Carnegie Mellon University * * ...

// // Copyright (C) 2018 Massachusetts Institute of Technology // // File : dft_top_top.v // Project : Common Evaluation Platform (CEP) // Description : This file provides a wishbone based-DFT core // module dft_top_top( wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i, wb_stb_i, wb_we_i, ...