KlaraHDL/hardware_code_and_sec_small · Datasets at Hugging Face

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name: .NET Core 5.0 on: push: branches: [ master ] pull_request: branches: [ master ] jobs: tests: name: Samples and unit tests runs-on: ${{ matrix.os }} strategy: matrix: os: [ ubuntu-latest, macos-latest ] # TODO windows-latest steps: - uses: actions/checkout@v2 ...
<filename>src_files.yml ariane-sdhc: incdirs: [ include, ] files: - rtl/IDDR.sv - rtl/ODDR.sv - rtl/sd_emmc_bistable_domain_cross.v - rtl/sd_emmc_clock_divider.v - rtl/sd_emmc_cmd_master.v - rtl/sd_emmc_cmd_serial_host.v - rtl/sd_emmc_controll...
<reponame>slaclab/atlas-rd53-atca-dev GitBase: .. TopRoguePackage: atlas_rd53_atca_dev RoguePackages: - submodules/atlas-atca-link-agg-fw-lib/python - submodules/atlas-rd53-fw-lib/python - submodules/axi-pcie-core/python - submodules/rce-gen3-fw-lib/python - submodules/surf/python - python RogueConfig: ...
<filename>.github/workflows/push.yml name: 'push' on: [ push, pull_request ] env: DOCKER_REGISTRY: docker.pkg.github.com # https://github.com/tox-dev/tox/issues/1468 PY_COLORS: 1 jobs: fmt: runs-on: ubuntu-latest steps: - uses: actions/checkout@v1 - uses: actions/setup-python@v1 with: ...
<gh_stars>100-1000 sudo: false language: c++ os: - linux matrix: exclude: - os: linux include: - os: linux docker: true compiler: gcc env: LLVM_VERSION=6.0 HWLOC_VERSION=1.11 DOCKERFILE=Ubuntu/16_04.64bit - os: osx compiler: clang env: LLVM_VERSION=6.0 HWLOC_VERSION=2...
language: python dist: Xenial python: "3.7" env: - TEST: 'test.test_axi' - TEST: 'test.test_bist' - TEST: 'test.test_downconverter' - TEST: 'test.test_ecc' - TEST: 'test.test_examples' - TEST: 'test.test_upconverter' install: - var1="$(pwd)" ## Get migen - git clone https://github.com/m-labs/migen - cd migen...
# Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Run functional regression checks name: ci on: [push, pull_request] jobs: ################## # Verilator Lint # ################## verilator_...
# Pad types must be one of digital, analog, or supply; pad names must be unique! # This just shows you how you can template things with {{}}, if/else, and the following parameters: # isInput: Boolean (each digital pad entry should be configurable between both input and output) # isHorizontal: Boolean (each pad entry s...
div_sqrt_top_mvp: files: [ hdl/defs_div_sqrt_mvp.sv, hdl/control_mvp.sv, hdl/div_sqrt_mvp_wrapper.sv, hdl/div_sqrt_top_mvp.sv, hdl/iteration_div_sqrt_mvp.sv, hdl/norm_div_sqrt_mvp.sv, hdl/nrbd_nrsc_mvp.sv, hdl/preprocess_mvp.sv, ]
icache_mp_128_pf: incdirs: [ ../../rtl/includes, ] files: [ RTL/cache_controller_to_axi_128_PF.sv, RTL/central_controller_128.sv, RTL/icache_bank_mp_128.sv, RTL/icache_bank_mp_PF.sv, RTL/icache_top_mp_128_PF.sv, RTL/merge_refill_cam_128_16.sv, RTL/pf_miss_mux.sv, RTL/prefetcher...
<filename>fpga/modules/bram_accumulator/config.yml<gh_stars>10-100 --- name: bram_accumulator board: boards/red-pitaya cores: - fpga/cores/comparator_v1_0 - fpga/cores/averager_counter_v1_0 - fpga/cores/delay_trig_v1_0 - fpga/cores/edge_detector_v1_0 control_registers: - avg # set to 1 to perform averaging ...
# Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Azure template for archiving pipeline step outputs and uploading them. # # This template will archive all of $BIN_DIR, and upload it for use by # downstream jobs using do...
<reponame>pan185/UnarySim # This file defines single architecture set for tlut systolic array performance projection - proj_16_16_bank8_block8 - proj_32_32_bank8_block8 - proj_64_64_bank8_block8 - proj_128_128_bank8_block8
# .readthedocs.yml # Read the Docs configuration file # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details version: 2 # Declare the Python requirements required to build your docs python: version: 3.8 install: - requirements: docs/requirements.txt
name: hls4ml-tutorial-0.4.0 channels: - conda-forge dependencies: - python=3.7 - jupyterhub - pydot - graphviz - pip - pip: - jupyter - tensorflow==2.3.1 - hls4ml[profiling]==0.4.0 - git+git://github.com/google/qkeras.git#egg=qkeras
name: Build on: pull_request: push: branches: - master - develop - release/ tags: '[0-9]+.[0-9]+.[0-9]+' paths-ignore: - 'doc/' - 'README.md' - 'CODE_OF_CONDUCT.md' - 'CONTRIBUTING.md' - 'LICENSE' - 'SECURITY.md' - 'data/' - '.github/' - '!.github...
## Uses the deployment flow described here: https://github.com/peaceiris/actions-gh-pages#%EF%B8%8F-deploy-to-external-repository-external_repository # The cucapra/calyx-docs repository contains the public deployment key and the main Calyx repository contains the private key enabling it to write to the docs repository....
<gh_stars>10-100 derived_clks: tb_i: abspath: 'tb_i' emu_clk: 'emu_clk' emu_rst: 'emu_rst' emu_dt: 'emu_dt' dt_req: 'dt_req' gated_clk_req: 'clk_val' gated_clk: 'clk_i'
<reponame>sergev/vak-opensource execution: - concurrency: 10 hold-for: 5m ramp-up: 2m scenario: yaml_example scenarios: yaml_example: retrieve-resources: false requests: - http://example.com/ reporting: - module: final-stats - module: console settings: check-interval: 5s default-executor: j...
sudo: false language: c os: - linux - osx compiler: - gcc - clang env: global: - BUILD_LIBPCAP=true # encrypted COVERITY_SCAN_TOKEN from # https://scan.coverity.com/projects/<project_id>/submit_build?tab=travis_ci - secure: "<KEY> # Coverity run condition (avoid matrix multiple runs), n...
<gh_stars>10-100 package: name: timer_unit sources: # Level 0 - rtl/timer_unit_counter.sv - rtl/timer_unit_counter_presc.sv # Level 1 - rtl/apb_timer_unit.sv - rtl/timer_unit.sv
# Adapted from Garnet and ButterPHY name: submodule commands: - cd outputs - cp ../../../build_prbs/18-cadence-innovus-signoff/results/prbs_generator_syn-merged.gds ./prbs_generator_syn.gds - cp ../../../build_prbs/21-synopsys-ptpx-genlibdb/outputs/design.db ./prbs_generator_syn.db - cp ../../../build_prbs/21...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
# Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: pspin authors: - <NAME> <<EMAIL>> dependencies: axi: {path: deps/pulp_platform_axi} common_cells: {path: deps/pulp_platform_common_cells} tech_cells_generic: {path: deps/pulp_platform_tec...
configMapGenerator: - name: challenge-skeleton-config files: - pow - nsjail.cfg generatorOptions: disableNameSuffixHash: true labels: type: generated annotations: note: generated
<reponame>milad621/livehd<gh_stars>100-1000 # my global config global: scrape_interval: 15s # Set the scrape interval to every 15 seconds. Default is every 1 minute. evaluation_interval: 15s # Evaluate rules every 15 seconds. The default is every 1 minute. # scrape_timeout is set to the global default (10s). ...
<filename>scripts/prometheus/alert.rules.yml groups: - name: Execution-time(task_THREAD_POOL_pool1_thread_pool_test) rules: - alert: 'Execution time spikes' expr: (task_THREAD_POOL_pool1_thread_pool_test_secs) > 0.4 labels: severity: 'critical' annotations: title:...
<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...
<gh_stars>10-100 --- name: laser-controller board: boards/red-pitaya version: 0.1.1 cores: - fpga/cores/redp_adc_v1_0 - fpga/cores/redp_dac_v1_0 - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/pdm_v1_0 - fpga/cores/pulse_generator_v1_0 - f...
derived_clks: tb_emu_io: abspath: 'tb_i' emu_clk: 'emu_clk' emu_rst: 'emu_rst' iacore_clk_adc: abspath: 'tb_i.top_i.iacore' emu_clk: 'emu_clk' emu_rst: 'emu_rst' gated_clk_req: 'clk_adc_val' gated_clk: 'clk_adc_i'
package: github.com/hitchnsmile/go-hangman import: - package: github.com/nsf/termbox-go - package: github.com/mattn/go-sqlite3 version: ^1.2.0 - package: github.com/mattn/go-runewidth version: ^0.0.2
<filename>models/AI-Model-Zoo/model-list/cf_inceptionv4_imagenet_299_299_24.5G_2.0/model.yaml<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # ...
cryoAsicGen1: enable: True ForceWrite: False dataWriter: enable: True dataFile: '' open: False bufferSize: 0 maxFileSize: 0 XilinxKcu1500Pgp3: enable: True AxiPcieCore: enable: True AxiPciePhy: enable: True AxiVersion: enable: True ScratchPad...
<filename>ultra96/ROOT_FS/app/fad/data/Handler/param.yaml %YAML 1.2 --- Basis: terminate_distance: 0.40 # 終了地点からこの距離以内に車体が到達したら終了する optor_dev_filename: "/dev/ttyUSB0" # 立ち上がり時間(s) StartupDelay: wo_calculating: 0.001 io_calculating: 0.001 vo_calculating: 0.001 localizationing: 0.001 planning: ...
language: minimal services: docker script: docker run --rm -tv $(pwd):/src -w /src ghdl/vunit:llvm python3 /src/run.py
resolver: nightly-2018-11-24 packages: - . allow-newer: true extra-deps: - git: <EMAIL>:clash-lang/clash-compiler.git commit: 67d36495cc108afad767e92d1ee21e12411cc9e2 extra-dep: false subdirs: - clash-ghc - clash-lib - clash-prelude compiler-check: newer-minor
<gh_stars>1-10 language: vhdl os: linux before_install: - sudo apt-get update - sudo apt-get install -y gnat zlib1g-dev - git clone https://github.com/ghdl/ghdl install: - cd ghdl - git pull origin master - ./configure --prefix=/usr/local - make - sudo make install - sudo ldconfig ...
<reponame>micprog/pulp overrides: tech_cells_generic: { git: "<EMAIL>:pulp-platform/tech_cells_generic.git", version: 0.2.2 } axi: { git: "<EMAIL>:pulp-platform/axi.git", version: 0.7.2 } # really old (now 0.24?) common_verification: { git: "<EMAIL>:pulp-platform/common_verification.git", version...
<gh_stars>1-10 KerasJson: example-keras-model-files/KERAS_1layer.json KerasH5: example-keras-model-files/KERAS_1layer_weights.h5 OutputDir: my-hls-test ProjectName: myproject XilinxPart: xc7vx690tffg1927-2 ClockPeriod: 5 IOType: io_parallel # options: io_serial/io_parallel ReuseFactor: 1 DefaultPrecision: ap_fixed<1...
<reponame>sil2100/Vitis-AI<filename>models/AI-Model-Zoo/model-list/tf_vgg16_imagenet_224_224_30.96G_2.0/model.yaml # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License a...
<filename>Bender.yml package: name: Pulpissimo authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependenc...
# Copyright 2020-2021 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: riscv-dbg authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: tech_cells_generic: { git: "https://github.com/pulp-platf...
<gh_stars>0 package: name: mkdv version: 0.0.1 dev-deps: - name: colorama src: pypi - name: jinja2 src: pypi - name: pyyaml src: pypi - name: allure-python-commons src: pypi - name: markdown src: pypi - name: jsonschema src: pypi - name: toposort ...
<filename>ci/vivado-builds.yml build:kc705_basex__2020.2: extends: .template_vivado_build variables: VIVADO_VERSION: "2020.2" dependencies: - quick_check:kc705_basex__2020.2 build:kc705_basex__2019.2: extends: .template_vivado_build variables: VIVADO_VERSION: "2019.2" dependencies: - quick_c...
<gh_stars>0 filespec: - vlnv: tblink-rpc-gw::tblink-rpc-cmdproc_1_1-synth out: - name: MKDV_VL_SRCS type: - verilogSource - systemVerilogSource flags: sv - name: MKDV_VL_INCDIRS type: - verilogSource - systemVerilogSource flags:...
defaults: - do_blink/figures - override hydra/job_logging: colorlog - override hydra/hydra_logging: colorlog
<reponame>tblink-bfms/tblink-bfms-i2c package: name: tblink-bfms-rv version: 0.0.1 setup-deps: - tblink-bfms deps: - name: tblink-bfms url: https://github.com/tblink-bfms/tblink-bfms.git - name: pytblink-rpc url: https://github.com/tblink-rpc/pytblink-rpc.git - name: tblink-rpc-co...
on: - push name: macOS CI jobs: build: name: Build (macOS) runs-on: macos-10.15 steps: - uses: actions/checkout@v2 with: submodules: true - name: Get LLVM and Bison run: \| brew install llvm bison echo "LLVM_CONFIG=$(brew --prefix llvm)/bin/llv...
<reponame>cromulencellc/hackasat-final-2021<filename>flatsat/docker-compose.yml version: "3.6" services: mosquitto: image: eclipse-mosquitto:2-openssl ports: - 1883:1883 networks: default: ipv4_address: ${MQTT_IP} user: ${DOCKER_USER_UID}:${DOCKER_USER_GID} volumes: - ./m...
<reponame>SubjeBilisim/anasymod<gh_stars>10-100 verilog_sources: osc_checker: files: "osc_checker.sv" fileset: "sim" sim_ctrl: files: "sim_ctrl.sv" fileset: "sim" defines: DT_MSDSL: name: DT_MSDSL value: 0.1e-6 SIMULATION_MODE_MSDSL: name: SIMULATION_MODE_MSDSL fileset: "sim"
<reponame>aappl/reg-mapper # Create list of register maps register_maps : # First map map1 : width : 32 base_address : 0x0 # Declare registers in map registers : # First register register1 : description : "The first register." RW : "READ_ONLY" # Declare bits in r...
name: Playground Deployment on: push: branches: - master jobs: playground: name: Web Demo runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - uses: actions/setup-node@v2 with: cache: yarn cache-dependency-path: web/yarn.lock - name: Build...
language: python matrix: include: - env: CONFIG="Trusty,Python3.6,libgnat-4.8,grc-1.11" os: linux sudo: required dist: trusty python: "3.6" before_install: - sudo apt-get -qq update - sudo apt-get install -y libgnat-4.8 - sudo ./tools/Travis-CI/grc.setup.sh ...
# # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # 'domain' refers to the two soc,cluster domains for FPGA # emulator synthesis # components: domain: [soc,cluster] pulp_soc: domain: [soc]
<filename>.github/workflows/fw-ci.yml name: fw-ci on: schedule: - cron: '0 0 * * *' pull_request: branches: [develop] jobs: fw-release: runs-on: ubuntu-18.04 steps: - name: Git Checkout uses: actions/checkout@v2 - name: Build lattice_digitizer run: \| . /setup-...
.template_base: image: ${IPBUS_DOCKER_REGISTRY}/ipbus-fw-dev-cc7:2019-09-17__ipbb0.5.2 before_script: - source /software/Xilinx/Vivado/${VIVADO_VERSION}/settings64.sh .template_vivado_quick_check: extends: .template_base tags: - docker - xilinx-tools stage: quick_checks script: - ipbb ini...
--- name: mars_star_tracker board: boards/mars_zx3 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000000' range: 4K - name: status offset: '0x50000000' range: 4K control_registers:...
name: 'coverage' on: push: schedule: - cron: '0 0 * * 5' jobs: coverage: runs-on: ubuntu-latest env: DOCKER_REGISTRY: docker.pkg.github.com IMAGE: docker.pkg.github.com/vunit/vunit/dev:llvm steps: - uses: actions/checkout@v2 with: submodules: recursive - uses...
device: XC7A35T-1CSG324 filetype: MIXED optimize: Speed top: test_top src: ./vhdl_src vhdl_2008: True
<filename>.github/workflows/ci.yml<gh_stars>1-10 name: CI on: push: branches: [ master ] pull_request: branches: [ master ] jobs: Verible: # The only runner that matches Verible binary target runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 with: # needed by git-auto-c...
<filename>.gitlab/ci/soc.gitlab-ci.yml soc_picorv32_test: before_script: - cd soc/picorv32/test stage: test script: - make soc_picorv32_kc705: stage: synthesis before_script: - cd soc/picorv32/project/kc705/synth script: - XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE XILINX_VIVADO=/non-free/X...
<gh_stars>0 name: Main on: push: branches: - '' tags-ignore: - v pull_request: release: types: - created jobs: build: runs-on: ${{ matrix.os }} strategy: matrix: os: - ubuntu-20.04 - macOS-10.15 - windows-2019 steps: ...
<filename>.github/workflows/hardware_design_default.yml name: Hardware Design Default on: push: paths: - 'hardware_design/**' - '!hardware_design/README.md' - '.github/workflows/hardware_design_default.yml' defaults: run: working-directory: hardware_design shell: bash jobs: build: r...
--- # Constants NLIST_MAX: 65536 NPROBE_MAX: 128 # stage 3 priority queue size D: 128 M: 16 K: 256 TOPK: 1 QUERY_NUM: 10000 LARGE_NUM: 99999999 # used to init the heap # stage 1 OPQ_ENABLE: True OPQ_UNROLL_FACTOR: 4 # 4 or 8, the larger the better performance, left None if OPQ_ENABLE=False, o...
<reponame>Kamran-10xe/fwrisc variables: build_num: $(Build.BuildNumber) jobs: - job: FWRISC pool: vmImage: 'ubuntu-18.04' steps: - bash: echo "##vso[task.prependpath]$CONDA/bin" displayName: Add conda to PATH - script: \| sudo apt-get install zlib1g-dev echo "Which Conda: `which cond...
--- algorithm: class: Nsga2 population_size: 200 probabilities: crossover: 0.5 mutation: 0.3 injection: 0.5 shorten_individual: true init: method: ramped # grow or full or ramped sensible_depth: 7 inject: method: grow # grow or full or random sensible_depth: 4 term...
<reponame>BearerPipelineTest/google-ctf<gh_stars>1000+ name: <NAME> # Long form description. description: \|+ Sometimes, what's more important is not what you have, but what you're missing. # The flag flag: CTF{!-!OLE-E-COM!7RESSION} # Task category. (one of hw, crypto, pwn, rev, web, net, misc) category: misc # === ...
apiVersion: kctf.dev/v1 kind: Challenge metadata: name: fullchain spec: deployed: true powDifficultySeconds: 60 network: public: true healthcheck: enabled: true podTemplate: template: spec: containers: - name: challenge volumeMounts: - name: kvm-...
<reponame>slaclab/kpix<filename>software/cfg/Test1Ch.yml DesyTrackerRoot: enable: 'True' ForceWrite: 'False' # DataWriter: # enable: 'True' # dataFile: '' # open: 'False' # bufferSize: '0' # maxFileSize: '0' DesyTracker: enable: 'True' AxiVersion: enable: 'True' ScratchPad: '0x...
<filename>ips_list.yml<gh_stars>10-100 # Copyright 2020 OpenHW Group # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # No external dependencies. Everything has been flattened into `rtl/`
<gh_stars>10-100 name: ghdl on: push: schedule: - cron: '0 0 * * 0' jobs: synth: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Build run: make build - name: Prepare run: make -C xilinx prepare - name: Verifying ghdl with examples from Xili...
toplevel: "" name: qoi files: - name: "circular_cam/circular_cam.sv" file_type: systemVerilogSource is_include_file: false include_path: "" logical_name: circular_cam - name: "circular_cam/Makefile" file_type: "" is_include_file: false include_path: "" logical_name: circular_cam -...
name: "fhw workflow" on: # Trigger the workflow on push, # but only for the main branch push: branches: - main jobs: build: runs-on: "ubuntu-latest" steps: - uses: "actions/checkout@master" - name: "TODO to Issue" uses: "Tiltedprogrammer/todo-to-issue-action/@v4.0.7.2" ...
riscv: incdirs: [ include, ] files: [ include/riscv_defines.sv, include/riscv_tracer_defines.sv, alu.sv, alu_div.sv, check_tag.sv, compressed_decoder.sv, controller.sv, cs_registers.sv, debug_unit.sv, decoder.sv, enable_tag.sv, exc_controller.sv, ex_stage.sv...
theme: jekyll-theme-dinky title: APB4 GPIO description: Fully Parameterized APB4 General-Purpose-IO show_downloads: true show_license: true license: Non-Commercial License
package: name: generic_FLL authors: - "<NAME> <<EMAIL>>" sources: - target: not(synthesis) files: - fe/model/gf22_DCO_model.tc.vhd - fe/model/gf22_FLL_model.vhd - fe/rtl/FLLPkg.vhd - fe/rtl/FLL_clk_divider.vhd - fe/rtl/FLL_clk_period_quantizer.vhd - fe/rtl/FLL_clock_...
zeroriscy: incdirs: [ include, ] files: [ include/zeroriscy_defines.sv, include/zeroriscy_tracer_defines.sv, zeroriscy_alu.sv, zeroriscy_compressed_decoder.sv, zeroriscy_controller.sv, zeroriscy_cs_registers.sv, zeroriscy_debug_unit.sv, zeroriscy_decoder.sv, zeroriscy_int_c...
<reponame>wonwooddo/vim_setup sudo: required services: docker env: - VIM_VERSION="7.4" PYTHON_IMAGE=2.7-stretch TAG=vim_74_py2 - VIM_VERSION="8.0" PYTHON_IMAGE=2.7-stretch TAG=vim_80_py2 - VIM_VERSION="git" PYTHON_IMAGE=2.7-stretch TAG=vim_git_py2 - VIM_VERSION="7.4" PYTHON_IMAGE=3.6-stretch TAG=vim_74_py3 -...
<filename>src/main/resources/config/application-jenkins.yml<gh_stars>1-10 # =================================================================== # Jenkins specific properties: this file will only be loaded during startup if the profile jenkins is active # # This configuration overrides the application.yml file. # ======...
<gh_stars>1-10 dut : dut_mio_sim.yaml dut_configuration : "" working_dir : modules : module_0 : activate : True configuration : # FE configuration file, text (.cfg) or HDF5 (.h5) file. If no value is given, the latest valid configuration (run status 'FINISHED') will be taken. If a number i...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
# # code.yml # # Copyright (C) 2019-2021 ETH Zurich, University of Bologna and GreenWaves Technologies # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LIC...
<filename>doc/ja/akane/05_bitonic_sorter.yml --- input_file : 05_bitonic_sorter.akd output_file : ../05_bitonic_sorter.md image_url : "Fig.1 バイトニックソートのソーティングネットワーク例" : "image/05_bitonic_sorter_1.jpg" link_list : - id : "「はじめに」" title: "「VHDL で書くマージソーター(はじめに)」" url : "./01_introduction.md" - id : ...
<reponame>mfkiwl/axi<gh_stars>1-10 package: name: axi authors: - "<NAME> <<EMAIL>>" # current maintainer - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 ...
<gh_stars>0 ibex: incdirs: [ ] files: [ ibex_defines.sv, ibex_tracer_defines.sv, ibex_alu.sv, ibex_compressed_decoder.sv, ibex_controller.sv, ibex_cs_registers.sv, ibex_debug_unit.sv, ibex_decoder.sv, ibex_int_controller.sv, ibex_ex_block.sv, ibex_id_stage.sv, ibex_...
<filename>Tools/JohnTheRipper-bleeding-jumbo/.travis.yml<gh_stars>1000+ language: c dist: trusty services: docker env: global: # The next declration is the encrypted COVERITY_SCAN_TOKEN, created # via the "travis encrypt" command using the project repo's public key - secure: "<KEY> matrix: include: -...
<reponame>sarnold/chiptools<gh_stars>0 name: Smoke on: workflow_dispatch: pull_request: push: branches: - master - develop jobs: tests: runs-on: ${{ matrix.os }} defaults: run: shell: bash env: OS: ${{ matrix.os }} PYTHON: ${{ matrix.python-version }} ...
<gh_stars>1-10 apb_aes: incdirs: [ ., ] files: [ prim_assert_standard_macros.svh, prim_assert.sv, prim_subreg_pkg.sv, prim_util_pkg.sv, prim_pkg.sv, prim_cipher_pkg.sv, entropy_src_pkg.sv, edn_pkg.sv, keymgr_reg_pkg.sv, keymgr_pkg.sv, lc_ctrl_state_pkg.sv, lc_ct...
<reponame>Nic30/hwtLib # Read the Docs configuration file # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details # Required version: 2 build: image: latest # Build documentation in the docs/ directory with Sphinx sphinx: configuration: doc/conf.py conda: environment: doc/environment.yml #...
<reponame>LarsAsplund/vunit_tdd name: Tests on: push: pull_request: workflow_dispatch: schedule: - cron: '0 0 * * 6' jobs: # GNU/Linux: VUnit Action (uses Docker image ghdl/vunit:mcode) lin-vunit: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - uses: VUnit/vunit_action...
sim.inputs.top_module: "hdc_sensor_fusion" sim.inputs.tb_dut: "dut" sim.inputs.tb_name: "hdc_sensor_fusion_tb" sim.inputs.input_files_meta: "append" sim.inputs.input_files: - "src/HDC_Sensor_Fusion_SmallRule90/hdc_sensor_fusion.sv" - "src/HDC_Sensor_Fusion_SmallRule90/hdc_sensor_fusion_tb.sv" - "src/HDC_Senso...
# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...
on: push: branches: - master jobs: docs: name: Build documentation runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v1 - name: Set up Python uses: actions/setup-python@v1 - name: Install dependencies run: \| python3 -m pip install --up...
<gh_stars>0 template: "../doc/core/template.lyx" source_list: bus_sampling: vhdl_file: "../src/bus_sampling/bus_sampling.vhd" lyx_output: "../doc/core/entity_docs/bus_sampling.lyx" fault_confinement: vhdl_file: "../src/can_core/fault_confinement.vhd" lyx_output: "../doc/core/enti...
steps: - label: "Pruning docker images" commands: - yes \| docker image prune -a --filter "until=24h" --filter=label='description=garnet' \|\| true - wait - label: ":wrench: Build and Test Garnet Unit Test" commands: - source /aha/bin/activate - source /cad/modules/tcl/init/sh - module load base xcelium/19.03...
<gh_stars>1-10 language: bash dist: focal before_install: - sudo apt-get install iverilog - sudo apt-get install yosys script: - ./flow.sh sim
language: cpp compiler: gcc dist: trusty sudo: required before_install: - sudo apt-get -qq update - sudo apt-get install -y verilator golang-go script: make verilator && make run-all-tests
# Adapted from Garnet name: openram-gen-sram-small commands: - \| ### Option 1 (slow): Run OpenRAM ## generate config file for OpemRAM #python gen_config.py ## run OpenRAM #python $OPENRAM_HOME/openram.py myconfig ## fix metal names in LEF file #cd temp #sed -i 's/LAYER\s+m1/LAYER met...
<gh_stars>10-100 # Copyright 2020 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...
<reponame>AdamChristiansen/fpga_ethernet_udp<filename>ether_tester/src/app.yml<gh_stars>10-100 name: Ethernet Tester about: Tests the Ethernet stream from an FPGA. The FPGA must be configured to stream pseudo-RNG sequences. args: - bytes: value_name: BYTES short: b long: bytes help: ...

name: .NET Core 5.0 on: push: branches: [ master ] pull_request: branches: [ master ] jobs: tests: name: Samples and unit tests runs-on: ${{ matrix.os }} strategy: matrix: os: [ ubuntu-latest, macos-latest ] # TODO windows-latest steps: - uses: actions/checkout@v2 ...

<filename>src_files.yml ariane-sdhc: incdirs: [ include, ] files: - rtl/IDDR.sv - rtl/ODDR.sv - rtl/sd_emmc_bistable_domain_cross.v - rtl/sd_emmc_clock_divider.v - rtl/sd_emmc_cmd_master.v - rtl/sd_emmc_cmd_serial_host.v - rtl/sd_emmc_controll...

<reponame>slaclab/atlas-rd53-atca-dev GitBase: .. TopRoguePackage: atlas_rd53_atca_dev RoguePackages: - submodules/atlas-atca-link-agg-fw-lib/python - submodules/atlas-rd53-fw-lib/python - submodules/axi-pcie-core/python - submodules/rce-gen3-fw-lib/python - submodules/surf/python - python RogueConfig: ...

<filename>.github/workflows/push.yml name: 'push' on: [ push, pull_request ] env: DOCKER_REGISTRY: docker.pkg.github.com # https://github.com/tox-dev/tox/issues/1468 PY_COLORS: 1 jobs: fmt: runs-on: ubuntu-latest steps: - uses: actions/checkout@v1 - uses: actions/setup-python@v1 with: ...

<gh_stars>100-1000 sudo: false language: c++ os: - linux matrix: exclude: - os: linux include: - os: linux docker: true compiler: gcc env: LLVM_VERSION=6.0 HWLOC_VERSION=1.11 DOCKERFILE=Ubuntu/16_04.64bit - os: osx compiler: clang env: LLVM_VERSION=6.0 HWLOC_VERSION=2...

language: python dist: Xenial python: "3.7" env: - TEST: 'test.test_axi' - TEST: 'test.test_bist' - TEST: 'test.test_downconverter' - TEST: 'test.test_ecc' - TEST: 'test.test_examples' - TEST: 'test.test_upconverter' install: - var1="$(pwd)" ## Get migen - git clone https://github.com/m-labs/migen - cd migen...

# Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Run functional regression checks name: ci on: [push, pull_request] jobs: ################## # Verilator Lint # ################## verilator_...

# Pad types must be one of digital, analog, or supply; pad names must be unique! # This just shows you how you can template things with {{}}, if/else, and the following parameters: # isInput: Boolean (each digital pad entry should be configurable between both input and output) # isHorizontal: Boolean (each pad entry s...

div_sqrt_top_mvp: files: [ hdl/defs_div_sqrt_mvp.sv, hdl/control_mvp.sv, hdl/div_sqrt_mvp_wrapper.sv, hdl/div_sqrt_top_mvp.sv, hdl/iteration_div_sqrt_mvp.sv, hdl/norm_div_sqrt_mvp.sv, hdl/nrbd_nrsc_mvp.sv, hdl/preprocess_mvp.sv, ]

icache_mp_128_pf: incdirs: [ ../../rtl/includes, ] files: [ RTL/cache_controller_to_axi_128_PF.sv, RTL/central_controller_128.sv, RTL/icache_bank_mp_128.sv, RTL/icache_bank_mp_PF.sv, RTL/icache_top_mp_128_PF.sv, RTL/merge_refill_cam_128_16.sv, RTL/pf_miss_mux.sv, RTL/prefetcher...

<filename>fpga/modules/bram_accumulator/config.yml<gh_stars>10-100 --- name: bram_accumulator board: boards/red-pitaya cores: - fpga/cores/comparator_v1_0 - fpga/cores/averager_counter_v1_0 - fpga/cores/delay_trig_v1_0 - fpga/cores/edge_detector_v1_0 control_registers: - avg # set to 1 to perform averaging ...

# Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # Azure template for archiving pipeline step outputs and uploading them. # # This template will archive all of $BIN_DIR, and upload it for use by # downstream jobs using do...

<reponame>pan185/UnarySim # This file defines single architecture set for tlut systolic array performance projection - proj_16_16_bank8_block8 - proj_32_32_bank8_block8 - proj_64_64_bank8_block8 - proj_128_128_bank8_block8

# .readthedocs.yml # Read the Docs configuration file # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details version: 2 # Declare the Python requirements required to build your docs python: version: 3.8 install: - requirements: docs/requirements.txt

name: hls4ml-tutorial-0.4.0 channels: - conda-forge dependencies: - python=3.7 - jupyterhub - pydot - graphviz - pip - pip: - jupyter - tensorflow==2.3.1 - hls4ml[profiling]==0.4.0 - git+git://github.com/google/qkeras.git#egg=qkeras

name: Build on: pull_request: push: branches: - master - develop - release/** tags: '[0-9]+.[0-9]+.[0-9]+' paths-ignore: - 'doc/**' - 'README.md' - 'CODE_OF_CONDUCT.md' - 'CONTRIBUTING.md' - 'LICENSE' - 'SECURITY.md' - 'data/**' - '.github/**' - '!.github...

## Uses the deployment flow described here: https://github.com/peaceiris/actions-gh-pages#%EF%B8%8F-deploy-to-external-repository-external_repository # The cucapra/calyx-docs repository contains the public deployment key and the main Calyx repository contains the private key enabling it to write to the docs repository....

<gh_stars>10-100 derived_clks: tb_i: abspath: 'tb_i' emu_clk: 'emu_clk' emu_rst: 'emu_rst' emu_dt: 'emu_dt' dt_req: 'dt_req' gated_clk_req: 'clk_val' gated_clk: 'clk_i'

<reponame>sergev/vak-opensource execution: - concurrency: 10 hold-for: 5m ramp-up: 2m scenario: yaml_example scenarios: yaml_example: retrieve-resources: false requests: - http://example.com/ reporting: - module: final-stats - module: console settings: check-interval: 5s default-executor: j...

sudo: false language: c os: - linux - osx compiler: - gcc - clang env: global: - BUILD_LIBPCAP=true # encrypted COVERITY_SCAN_TOKEN from # https://scan.coverity.com/projects/<project_id>/submit_build?tab=travis_ci - secure: "<KEY> # Coverity run condition (avoid matrix multiple runs), n...

<gh_stars>10-100 package: name: timer_unit sources: # Level 0 - rtl/timer_unit_counter.sv - rtl/timer_unit_counter_presc.sv # Level 1 - rtl/apb_timer_unit.sv - rtl/timer_unit.sv

# Adapted from Garnet and ButterPHY name: submodule commands: - cd outputs - cp ../../../build_prbs/18-cadence-innovus-signoff/results/prbs_generator_syn-merged.gds ./prbs_generator_syn.gds - cp ../../../build_prbs/21-synopsys-ptpx-genlibdb/outputs/design.db ./prbs_generator_syn.db - cp ../../../build_prbs/21...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

# Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: pspin authors: - <NAME> <<EMAIL>> dependencies: axi: {path: deps/pulp_platform_axi} common_cells: {path: deps/pulp_platform_common_cells} tech_cells_generic: {path: deps/pulp_platform_tec...

configMapGenerator: - name: challenge-skeleton-config files: - pow - nsjail.cfg generatorOptions: disableNameSuffixHash: true labels: type: generated annotations: note: generated

<reponame>milad621/livehd<gh_stars>100-1000 # my global config global: scrape_interval: 15s # Set the scrape interval to every 15 seconds. Default is every 1 minute. evaluation_interval: 15s # Evaluate rules every 15 seconds. The default is every 1 minute. # scrape_timeout is set to the global default (10s). ...

<filename>scripts/prometheus/alert.rules.yml groups: - name: Execution-time(task_THREAD_POOL_pool1_thread_pool_test) rules: - alert: 'Execution time spikes' expr: (task_THREAD_POOL_pool1_thread_pool_test_secs) > 0.4 labels: severity: 'critical' annotations: title:...

<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...

<gh_stars>10-100 --- name: laser-controller board: boards/red-pitaya version: 0.1.1 cores: - fpga/cores/redp_adc_v1_0 - fpga/cores/redp_dac_v1_0 - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 - fpga/cores/pdm_v1_0 - fpga/cores/pulse_generator_v1_0 - f...

derived_clks: tb_emu_io: abspath: 'tb_i' emu_clk: 'emu_clk' emu_rst: 'emu_rst' iacore_clk_adc: abspath: 'tb_i.top_i.iacore' emu_clk: 'emu_clk' emu_rst: 'emu_rst' gated_clk_req: 'clk_adc_val' gated_clk: 'clk_adc_i'

package: github.com/hitchnsmile/go-hangman import: - package: github.com/nsf/termbox-go - package: github.com/mattn/go-sqlite3 version: ^1.2.0 - package: github.com/mattn/go-runewidth version: ^0.0.2

<filename>models/AI-Model-Zoo/model-list/cf_inceptionv4_imagenet_299_299_24.5G_2.0/model.yaml<gh_stars>1-10 # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # ...

cryoAsicGen1: enable: True ForceWrite: False dataWriter: enable: True dataFile: '' open: False bufferSize: 0 maxFileSize: 0 XilinxKcu1500Pgp3: enable: True AxiPcieCore: enable: True AxiPciePhy: enable: True AxiVersion: enable: True ScratchPad...

<filename>ultra96/ROOT_FS/app/fad/data/Handler/param.yaml %YAML 1.2 --- Basis: terminate_distance: 0.40 # 終了地点からこの距離以内に車体が到達したら終了する optor_dev_filename: "/dev/ttyUSB0" # 立ち上がり時間(s) StartupDelay: wo_calculating: 0.001 io_calculating: 0.001 vo_calculating: 0.001 localizationing: 0.001 planning: ...

language: minimal services: docker script: docker run --rm -tv $(pwd):/src -w /src ghdl/vunit:llvm python3 /src/run.py

resolver: nightly-2018-11-24 packages: - . allow-newer: true extra-deps: - git: <EMAIL>:clash-lang/clash-compiler.git commit: 67d36495cc108afad767e92d1ee21e12411cc9e2 extra-dep: false subdirs: - clash-ghc - clash-lib - clash-prelude compiler-check: newer-minor

<gh_stars>1-10 language: vhdl os: linux before_install: - sudo apt-get update - sudo apt-get install -y gnat zlib1g-dev - git clone https://github.com/ghdl/ghdl install: - cd ghdl - git pull origin master - ./configure --prefix=/usr/local - make - sudo make install - sudo ldconfig ...

<reponame>micprog/pulp overrides: tech_cells_generic: { git: "<EMAIL>:pulp-platform/tech_cells_generic.git", version: 0.2.2 } axi: { git: "<EMAIL>:pulp-platform/axi.git", version: 0.7.2 } # really old (now 0.24?) common_verification: { git: "<EMAIL>:pulp-platform/common_verification.git", version...

<gh_stars>1-10 KerasJson: example-keras-model-files/KERAS_1layer.json KerasH5: example-keras-model-files/KERAS_1layer_weights.h5 OutputDir: my-hls-test ProjectName: myproject XilinxPart: xc7vx690tffg1927-2 ClockPeriod: 5 IOType: io_parallel # options: io_serial/io_parallel ReuseFactor: 1 DefaultPrecision: ap_fixed<1...

<reponame>sil2100/Vitis-AI<filename>models/AI-Model-Zoo/model-list/tf_vgg16_imagenet_224_224_30.96G_2.0/model.yaml # Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License a...

<filename>Bender.yml package: name: Pulpissimo authors: - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependenc...

# Copyright 2020-2021 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 package: name: riscv-dbg authors: - <NAME> <<EMAIL>> - <NAME> <<EMAIL>> dependencies: tech_cells_generic: { git: "https://github.com/pulp-platf...

<gh_stars>0 package: name: mkdv version: 0.0.1 dev-deps: - name: colorama src: pypi - name: jinja2 src: pypi - name: pyyaml src: pypi - name: allure-python-commons src: pypi - name: markdown src: pypi - name: jsonschema src: pypi - name: toposort ...

<filename>ci/vivado-builds.yml build:kc705_basex__2020.2: extends: .template_vivado_build variables: VIVADO_VERSION: "2020.2" dependencies: - quick_check:kc705_basex__2020.2 build:kc705_basex__2019.2: extends: .template_vivado_build variables: VIVADO_VERSION: "2019.2" dependencies: - quick_c...

<gh_stars>0 filespec: - vlnv: tblink-rpc-gw::tblink-rpc-cmdproc_1_1-synth out: - name: MKDV_VL_SRCS type: - verilogSource - systemVerilogSource flags: sv - name: MKDV_VL_INCDIRS type: - verilogSource - systemVerilogSource flags:...

defaults: - do_blink/figures - override hydra/job_logging: colorlog - override hydra/hydra_logging: colorlog

<reponame>tblink-bfms/tblink-bfms-i2c package: name: tblink-bfms-rv version: 0.0.1 setup-deps: - tblink-bfms deps: - name: tblink-bfms url: https://github.com/tblink-bfms/tblink-bfms.git - name: pytblink-rpc url: https://github.com/tblink-rpc/pytblink-rpc.git - name: tblink-rpc-co...

on: - push name: macOS CI jobs: build: name: Build (macOS) runs-on: macos-10.15 steps: - uses: actions/checkout@v2 with: submodules: true - name: Get LLVM and Bison run: | brew install llvm bison echo "LLVM_CONFIG=$(brew --prefix llvm)/bin/llv...

<reponame>cromulencellc/hackasat-final-2021<filename>flatsat/docker-compose.yml version: "3.6" services: mosquitto: image: eclipse-mosquitto:2-openssl ports: - 1883:1883 networks: default: ipv4_address: ${MQTT_IP} user: ${DOCKER_USER_UID}:${DOCKER_USER_GID} volumes: - ./m...

<reponame>SubjeBilisim/anasymod<gh_stars>10-100 verilog_sources: osc_checker: files: "osc_checker.sv" fileset: "sim" sim_ctrl: files: "sim_ctrl.sv" fileset: "sim" defines: DT_MSDSL: name: DT_MSDSL value: 0.1e-6 SIMULATION_MODE_MSDSL: name: SIMULATION_MODE_MSDSL fileset: "sim"

<reponame>aappl/reg-mapper # Create list of register maps register_maps : # First map map1 : width : 32 base_address : 0x0 # Declare registers in map registers : # First register register1 : description : "The first register." RW : "READ_ONLY" # Declare bits in r...

name: Playground Deployment on: push: branches: - master jobs: playground: name: Web Demo runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - uses: actions/setup-node@v2 with: cache: yarn cache-dependency-path: web/yarn.lock - name: Build...

language: python matrix: include: - env: CONFIG="Trusty,Python3.6,libgnat-4.8,grc-1.11" os: linux sudo: required dist: trusty python: "3.6" before_install: - sudo apt-get -qq update - sudo apt-get install -y libgnat-4.8 - sudo ./tools/Travis-CI/grc.setup.sh ...

# # List of RTL sources. Contrarily to IPs, these reside in # the current Git repository. # Uses the YAML syntax. # 'domain' refers to the two soc,cluster domains for FPGA # emulator synthesis # components: domain: [soc,cluster] pulp_soc: domain: [soc]

<filename>.github/workflows/fw-ci.yml name: fw-ci on: schedule: - cron: '0 0 * * *' pull_request: branches: [develop] jobs: fw-release: runs-on: ubuntu-18.04 steps: - name: Git Checkout uses: actions/checkout@v2 - name: Build lattice_digitizer run: | . /setup-...

.template_base: image: ${IPBUS_DOCKER_REGISTRY}/ipbus-fw-dev-cc7:2019-09-17__ipbb0.5.2 before_script: - source /software/Xilinx/Vivado/${VIVADO_VERSION}/settings64.sh .template_vivado_quick_check: extends: .template_base tags: - docker - xilinx-tools stage: quick_checks script: - ipbb ini...

--- name: mars_star_tracker board: boards/mars_zx3 version: 0.1.1 cores: - fpga/cores/axi_ctl_register_v1_0 - fpga/cores/axi_sts_register_v1_0 - fpga/cores/dna_reader_v1_0 memory: - name: control offset: '0x60000000' range: 4K - name: status offset: '0x50000000' range: 4K control_registers:...

name: 'coverage' on: push: schedule: - cron: '0 0 * * 5' jobs: coverage: runs-on: ubuntu-latest env: DOCKER_REGISTRY: docker.pkg.github.com IMAGE: docker.pkg.github.com/vunit/vunit/dev:llvm steps: - uses: actions/checkout@v2 with: submodules: recursive - uses...

device: XC7A35T-1CSG324 filetype: MIXED optimize: Speed top: test_top src: ./vhdl_src vhdl_2008: True

<filename>.github/workflows/ci.yml<gh_stars>1-10 name: CI on: push: branches: [ master ] pull_request: branches: [ master ] jobs: Verible: # The only runner that matches Verible binary target runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 with: # needed by git-auto-c...

<filename>.gitlab/ci/soc.gitlab-ci.yml soc_picorv32_test: before_script: - cd soc/picorv32/test stage: test script: - make soc_picorv32_kc705: stage: synthesis before_script: - cd soc/picorv32/project/kc705/synth script: - XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE XILINX_VIVADO=/non-free/X...

<gh_stars>0 name: Main on: push: branches: - '*' tags-ignore: - v* pull_request: release: types: - created jobs: build: runs-on: ${{ matrix.os }} strategy: matrix: os: - ubuntu-20.04 - macOS-10.15 - windows-2019 steps: ...

<filename>.github/workflows/hardware_design_default.yml name: Hardware Design Default on: push: paths: - 'hardware_design/**' - '!hardware_design/README.md' - '.github/workflows/hardware_design_default.yml' defaults: run: working-directory: hardware_design shell: bash jobs: build: r...

--- # Constants NLIST_MAX: 65536 NPROBE_MAX: 128 # stage 3 priority queue size D: 128 M: 16 K: 256 TOPK: 1 QUERY_NUM: 10000 LARGE_NUM: 99999999 # used to init the heap # stage 1 OPQ_ENABLE: True OPQ_UNROLL_FACTOR: 4 # 4 or 8, the larger the better performance, left None if OPQ_ENABLE=False, o...

<reponame>Kamran-10xe/fwrisc variables: build_num: $(Build.BuildNumber) jobs: - job: FWRISC pool: vmImage: 'ubuntu-18.04' steps: - bash: echo "##vso[task.prependpath]$CONDA/bin" displayName: Add conda to PATH - script: | sudo apt-get install zlib1g-dev echo "Which Conda: `which cond...

--- algorithm: class: Nsga2 population_size: 200 probabilities: crossover: 0.5 mutation: 0.3 injection: 0.5 shorten_individual: true init: method: ramped # grow or full or ramped sensible_depth: 7 inject: method: grow # grow or full or random sensible_depth: 4 term...

<reponame>BearerPipelineTest/google-ctf<gh_stars>1000+ name: <NAME> # Long form description. description: |+ Sometimes, what's more important is not what you have, but what you're missing. # The flag flag: CTF{!-!OLE-E-COM!7RESSION} # Task category. (one of hw, crypto, pwn, rev, web, net, misc) category: misc # === ...

apiVersion: kctf.dev/v1 kind: Challenge metadata: name: fullchain spec: deployed: true powDifficultySeconds: 60 network: public: true healthcheck: enabled: true podTemplate: template: spec: containers: - name: challenge volumeMounts: - name: kvm-...

<reponame>slaclab/kpix<filename>software/cfg/Test1Ch.yml DesyTrackerRoot: enable: 'True' ForceWrite: 'False' # DataWriter: # enable: 'True' # dataFile: '' # open: 'False' # bufferSize: '0' # maxFileSize: '0' DesyTracker: enable: 'True' AxiVersion: enable: 'True' ScratchPad: '0x...

<filename>ips_list.yml<gh_stars>10-100 # Copyright 2020 OpenHW Group # Solderpad Hardware License, Version 2.1, see LICENSE.md for details. # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # No external dependencies. Everything has been flattened into `rtl/`

<gh_stars>10-100 name: ghdl on: push: schedule: - cron: '0 0 * * 0' jobs: synth: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - name: Build run: make build - name: Prepare run: make -C xilinx prepare - name: Verifying ghdl with examples from Xili...

toplevel: "" name: qoi files: - name: "circular_cam/circular_cam.sv" file_type: systemVerilogSource is_include_file: false include_path: "" logical_name: circular_cam - name: "circular_cam/Makefile" file_type: "" is_include_file: false include_path: "" logical_name: circular_cam -...

name: "fhw workflow" on: # Trigger the workflow on push, # but only for the main branch push: branches: - main jobs: build: runs-on: "ubuntu-latest" steps: - uses: "actions/checkout@master" - name: "TODO to Issue" uses: "Tiltedprogrammer/todo-to-issue-action/@v4.0.7.2" ...

riscv: incdirs: [ include, ] files: [ include/riscv_defines.sv, include/riscv_tracer_defines.sv, alu.sv, alu_div.sv, check_tag.sv, compressed_decoder.sv, controller.sv, cs_registers.sv, debug_unit.sv, decoder.sv, enable_tag.sv, exc_controller.sv, ex_stage.sv...

theme: jekyll-theme-dinky title: APB4 GPIO description: Fully Parameterized APB4 General-Purpose-IO show_downloads: true show_license: true license: Non-Commercial License

package: name: generic_FLL authors: - "<NAME> <<EMAIL>>" sources: - target: not(synthesis) files: - fe/model/gf22_DCO_model.tc.vhd - fe/model/gf22_FLL_model.vhd - fe/rtl/FLLPkg.vhd - fe/rtl/FLL_clk_divider.vhd - fe/rtl/FLL_clk_period_quantizer.vhd - fe/rtl/FLL_clock_...

zeroriscy: incdirs: [ include, ] files: [ include/zeroriscy_defines.sv, include/zeroriscy_tracer_defines.sv, zeroriscy_alu.sv, zeroriscy_compressed_decoder.sv, zeroriscy_controller.sv, zeroriscy_cs_registers.sv, zeroriscy_debug_unit.sv, zeroriscy_decoder.sv, zeroriscy_int_c...

<reponame>wonwooddo/vim_setup sudo: required services: docker env: - VIM_VERSION="7.4" PYTHON_IMAGE=2.7-stretch TAG=vim_74_py2 - VIM_VERSION="8.0" PYTHON_IMAGE=2.7-stretch TAG=vim_80_py2 - VIM_VERSION="git" PYTHON_IMAGE=2.7-stretch TAG=vim_git_py2 - VIM_VERSION="7.4" PYTHON_IMAGE=3.6-stretch TAG=vim_74_py3 -...

<filename>src/main/resources/config/application-jenkins.yml<gh_stars>1-10 # =================================================================== # Jenkins specific properties: this file will only be loaded during startup if the profile jenkins is active # # This configuration overrides the application.yml file. # ======...

<gh_stars>1-10 dut : dut_mio_sim.yaml dut_configuration : "" working_dir : modules : module_0 : activate : True configuration : # FE configuration file, text (.cfg) or HDF5 (.h5) file. If no value is given, the latest valid configuration (run status 'FINISHED') will be taken. If a number i...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

# # code.yml # # Copyright (C) 2019-2021 ETH Zurich, University of Bologna and GreenWaves Technologies # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LIC...

<filename>doc/ja/akane/05_bitonic_sorter.yml --- input_file : 05_bitonic_sorter.akd output_file : ../05_bitonic_sorter.md image_url : "Fig.1 バイトニックソートのソーティングネットワーク例" : "image/05_bitonic_sorter_1.jpg" link_list : - id : "「はじめに」" title: "「VHDL で書くマージソーター(はじめに)」" url : "./01_introduction.md" - id : ...

<reponame>mfkiwl/axi<gh_stars>1-10 package: name: axi authors: - "<NAME> <<EMAIL>>" # current maintainer - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" - "<NAME> <<EMAIL>>" dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 ...

<gh_stars>0 ibex: incdirs: [ ] files: [ ibex_defines.sv, ibex_tracer_defines.sv, ibex_alu.sv, ibex_compressed_decoder.sv, ibex_controller.sv, ibex_cs_registers.sv, ibex_debug_unit.sv, ibex_decoder.sv, ibex_int_controller.sv, ibex_ex_block.sv, ibex_id_stage.sv, ibex_...

<filename>Tools/JohnTheRipper-bleeding-jumbo/.travis.yml<gh_stars>1000+ language: c dist: trusty services: docker env: global: # The next declration is the encrypted COVERITY_SCAN_TOKEN, created # via the "travis encrypt" command using the project repo's public key - secure: "<KEY> matrix: include: -...

<reponame>sarnold/chiptools<gh_stars>0 name: Smoke on: workflow_dispatch: pull_request: push: branches: - master - develop jobs: tests: runs-on: ${{ matrix.os }} defaults: run: shell: bash env: OS: ${{ matrix.os }} PYTHON: ${{ matrix.python-version }} ...

<gh_stars>1-10 apb_aes: incdirs: [ ., ] files: [ prim_assert_standard_macros.svh, prim_assert.sv, prim_subreg_pkg.sv, prim_util_pkg.sv, prim_pkg.sv, prim_cipher_pkg.sv, entropy_src_pkg.sv, edn_pkg.sv, keymgr_reg_pkg.sv, keymgr_pkg.sv, lc_ctrl_state_pkg.sv, lc_ct...

<reponame>Nic30/hwtLib # Read the Docs configuration file # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details # Required version: 2 build: image: latest # Build documentation in the docs/ directory with Sphinx sphinx: configuration: doc/conf.py conda: environment: doc/environment.yml #...

<reponame>LarsAsplund/vunit_tdd name: Tests on: push: pull_request: workflow_dispatch: schedule: - cron: '0 0 * * 6' jobs: # GNU/Linux: VUnit Action (uses Docker image ghdl/vunit:mcode) lin-vunit: runs-on: ubuntu-latest steps: - uses: actions/checkout@v2 - uses: VUnit/vunit_action...

sim.inputs.top_module: "hdc_sensor_fusion" sim.inputs.tb_dut: "dut" sim.inputs.tb_name: "hdc_sensor_fusion_tb" sim.inputs.input_files_meta: "append" sim.inputs.input_files: - "src/HDC_Sensor_Fusion_SmallRule90/hdc_sensor_fusion.sv" - "src/HDC_Sensor_Fusion_SmallRule90/hdc_sensor_fusion_tb.sv" - "src/HDC_Senso...

# Copyright 2019 Xilinx Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing,...

on: push: branches: - master jobs: docs: name: Build documentation runs-on: ubuntu-latest steps: - name: Checkout uses: actions/checkout@v1 - name: Set up Python uses: actions/setup-python@v1 - name: Install dependencies run: | python3 -m pip install --up...

<gh_stars>0 template: "../doc/core/template.lyx" source_list: bus_sampling: vhdl_file: "../src/bus_sampling/bus_sampling.vhd" lyx_output: "../doc/core/entity_docs/bus_sampling.lyx" fault_confinement: vhdl_file: "../src/can_core/fault_confinement.vhd" lyx_output: "../doc/core/enti...

steps: - label: "Pruning docker images" commands: - yes | docker image prune -a --filter "until=24h" --filter=label='description=garnet' || true - wait - label: ":wrench: Build and Test Garnet Unit Test" commands: - source /aha/bin/activate - source /cad/modules/tcl/init/sh - module load base xcelium/19.03...

<gh_stars>1-10 language: bash dist: focal before_install: - sudo apt-get install iverilog - sudo apt-get install yosys script: - ./flow.sh sim

language: cpp compiler: gcc dist: trusty sudo: required before_install: - sudo apt-get -qq update - sudo apt-get install -y verilator golang-go script: make verilator && make run-all-tests

# Adapted from Garnet name: openram-gen-sram-small commands: - | ### Option 1 (slow): Run OpenRAM ## generate config file for OpemRAM #python gen_config.py ## run OpenRAM #python $OPENRAM_HOME/openram.py myconfig ## fix metal names in LEF file #cd temp #sed -i 's/LAYER\s+m1/LAYER met...

<gh_stars>10-100 # Copyright 2020 ETH Zurich # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed...

<reponame>AdamChristiansen/fpga_ethernet_udp<filename>ether_tester/src/app.yml<gh_stars>10-100 name: Ethernet Tester about: Tests the Ethernet stream from an FPGA. The FPGA must be configured to stream pseudo-RNG sequences. args: - bytes: value_name: BYTES short: b long: bytes help: ...