Search is not available for this dataset
content stringlengths 0 376M |
|---|
SPI_SLAVE_FREERTOS:
IP: __SPI_SLAVE_FREERTOS
CMD: SPS
ALT: a
ss_sck_freertos:
PIN: A34
DIRECTION: IN
ss_mosi_freertos:
PIN: A36
DIRECTION: IN
ss_ssel_freertos:
PIN: A37
DIRECTION: IN
ss_miso_freertos:
PIN: A38
DIRECTION: OUT... |
pip_test:
- src_wire: R3C3_PLC.PLC/JDI0_SLICEA
dst_wire: R3C3/JF0
bel_pin_test:
- bel: R7C3_PLC.PLC/SLICEA_LUT0
pin: D
wire: R7C3_PLC.PLC/JD0_SLICEA
|
#Descriptions:
#CMD: cpld command
#A: Assitant Board
#T: Target Board
#FUNC0: the function of this pin connection
#DIRECTION: A2T T2A T2T
#FRDM A-B-C-D DEFINITION
#| NAME | SIZE | CPLD_SCH | FRDM_SCH
#| A | (10*2) | JJ_2 | ?
#| B | (8*2) | JJ_1 | ?
#| C | (5*2) | JJ_3 | ?
#| D | (8*2) |... |
<gh_stars>1-10
#
# List of IPs and relative branch/commit-hash/tag.
# Uses the YAML syntax.
#
# Examples:
#
# or10n:
# commit: tags/PULP3_final
# domain: [cluster]
# udma:
# commit: 62b10440
# domain: [soc]
# axi_slice:
# commit: master
# domain: [soc,cluster]
# If a *tag* or *commit* is r... |
<reponame>slaclab/epix-hr-10k-2m
ePixHr10kT:
enable: True
ForceWrite: False
EpixHR:
enable: True
PowerSupply:
enable: True
DigitalEn: True
AnalogEn: True
|
<reponame>CSEYJ/Flightplan
all: # All experiments must contain these fields
- description
- experiment
- repositories:
- P4Boosters
- files:
- documentation.md
memcached: # Memcached must contain these in addition
- files:
- data
- bitstream.tar.gz
e2e:
... |
name: Regression Tests
on: [push, pull_request]
jobs:
build:
name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10)
runs-on: ubuntu-20.04
strategy:
matrix:
python-version: [3.9]
group: [1, 2, 3, 4, 5]
steps:
- uses: actions/checkout@v2
- name: Set up Pytho... |
name: usb_phy
clock_port: clk
verilog:
- timescale.v
- usb_phy.v
- usb_rx_phy.v
- usb_tx_phy.v
|
---
name: integration
# Build and test starting from latest bootstrap release.
on:
pull_request: {branches: master}
push:
concurrency: ci
jobs:
AMD64_DARWIN:
uses: modula3/cm3/.github/workflows/amd64_darwin.yml@master
AMD64_LINUX:
uses: modula3/cm3/.github/workflows/amd64_linux.yml@master
AMD64_M... |
<reponame>Hog-CERN/Hog
# Copyright 2018-2021 The University of Birmingham
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Un... |
kind: NetworkPolicy
apiVersion: networking.k8s.io/v1
metadata:
name: allow-dns
namespace: default
spec:
podSelector: {}
policyTypes:
- Egress
egress:
- to:
ports:
- protocol: UDP
port: 53
- protocol: TCP
port: 53
|
name: Test Github Action
on: [push, pull_request]
jobs:
test:
runs-on: ubuntu-latest
steps:
- name: Set up Git repository
uses: actions/checkout@v2
- name: Run VUnit tests
uses: VUnit/vunit_action@v0.1.0
with:
run_file: run.py
|
---
input_file : ../akane/11_merge_sort_core_2.akd
output_file : 11_merge_sort_core_2.md
image_url :
"Fig.1 マージソートコアの構成" : "https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/24981/1afcda19-1ee7-2c05-96b4-d682c1876da9.jpeg"
"Fig.2 4-way マージソートツリーによる16ワードデータのソート例" : ... |
<reponame>rits-drsl/ZybotR2-96-fpt19<gh_stars>10-100
%YAML 1.2
---
param:
opencv_tm_method: 5 # CV_TM_SQDIFF = 0, CV_TM_SQDIFF_NORMED = 1, CV_TM_CCORR = 2, CV_TM_CCORR_NORMED = 3, CV_TM_CCOEFF = 4, CV_TM_CCOEFF_NORMED = 5
search_range_degree: 10 # 探索する角度の範囲(+-)
nof_divisions: 20 # 角度の分割数(角度分解能 : 2... |
language: python
dist: xenial
matrix:
include:
- python: 3.5
env: TOX_ENV=py35
- python: 3.6
env: TOX_ENV=py36
- python: 3.7
env: TOX_ENV=py37
install:
# Install riscv-dv using pip to ensure dependencies are downloaded correctly.
- pip install -r require... |
################################################################################
#
# \file .travis.yml
#
# \brief Configuration file for Travis continuous integration
#
# Copyright (c) 2017, B&R Industrial Automation GmbH
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# m... |
<gh_stars>10-100
language: c
compiler: clang
matrix:
include:
# works on Precise and Trusty
- os: linux
addons:
addons:
apt:
sources:
- george-edison55-precise-backports
packages:
- cmake-data
- cmake
- os: osx
osx_image: x... |
description: Featherweight IP RISC-V processor
compatible: "fwrisc"
include: [base.yaml]
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
|
<reponame>sil2100/Vitis-AI
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable l... |
#template_tql < $RDI_TEMPLATES/sdx/sdaccel/swhw/template.tql
description: testinfo generated using import_sdx_test.py script
level: 6
owner: vallina
user:
allowed_test_modes: [sw_emu, hw_emu, hw]
force_makefile: "--force"
host_args: {all: sincos.xclbin}
host_cflags: ' -DDSA64 -DFLOW_HLS_CSIM'
host_exe: host.e... |
<gh_stars>10-100
!!omap
- ATIMER_DOWNCOUNTER:
fields: !!omap
- CVAL:
access: rw
description: When equal to zero an interrupt is raised
lsb: 0
reset_value: '0'
width: 16
- ATIMER_PRESET:
fields: !!omap
- PRESETVAL:
access: rw
description: Value load... |
# Adapted from Garnet and ButterPHY
name: analog_core
commands:
- |
mkdir -p outputs
tar -xvf /home/sjkim85/dragonphy_tarballs/analog_core-latest.tar.gz -C outputs
mv outputs/analog_core-0.9.0/* outputs/
python alt.py
mv outputs/analog_core_alt.lef outputs/analog_core.lef
outputs:
- analog_co... |
power.inputs.waveforms_meta: "append"
power.inputs.waveforms:
- "/tools/B/daniels/hammer-tsmc28/build/sim-par-rundir/vcdplus.vpd"
power.inputs.database: "/tools/B/daniels/hammer-tsmc28/build/par-rundir/latest"
power.inputs.saifs_meta: "append"
power.inputs.saifs:
- "/tools/B/daniels/hammer-tsmc28/build/sim-par-... |
GitBase: ..
TopRoguePackage: KpixDaq
RoguePackages:
- common/python
RogueScripts:
- ../software/scripts/KpixGui
- ../software/scripts/KpixRun
- ../software/scripts/KpixCalibration
- ../software/scripts/KpixPromLoader
- ../software/scripts/KpixServer
- ../software/scripts/KpixClientGui
- ../softwa... |
<reponame>wallento/ibex
on: [push, pull_request]
jobs:
lint:
runs-on: ubuntu-latest
name: Linter
strategy:
matrix:
config: ['small']
fail-fast: false
steps:
- name: Checkout
uses: actions/checkout@v1
- name: Test and display fusesoc config for ${{ matrix.config... |
name: Artifacts
on:
push:
branches: ['master']
jobs:
artifacts:
name: "Create artifacts"
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: julia-actions/setup-julia@latest
with:
version: '1'
- uses: technote-space/get-diff-action@v5
with:... |
package:
name: ariane
authors: [ "<NAME> <<EMAIL>>" ]
dependencies:
axi2per: { git: "<EMAIL>:pulp-open/axi2per.git", version: 0.1.0 }
axi_mem_if: { git: "<EMAIL>:pulp-open/axi_mem_if.git", version: 0.1.0 }
axi_node: { git: "<EMAIL>:pulp-open/axi_node.git", version: 1.0.1 }
axi_slice: { git: "<EMAIL>:pulp-o... |
name: language-dataset-ci
on:
push:
branches:
- master
pull_request: {}
jobs:
lint-black:
name: lint (black)
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
with:
fetch-depth: 1
- uses: actions/setup-python@v1
with:
python-version: '3... |
<filename>blocks/eventpacket/test/test_osd_event_packetization_fixedwidth.manifest.yaml
module: test_osd_event_packetization_fixedwidth
sources:
- ../../../interfaces/common/dii_channel.sv
- ../common/osd_event_packetization.sv
- ../common/osd_event_packetization_fixedwidth.sv
toplevel: osd_event_packetization_... |
description: >-
This is an example of a submission to the
archive which was submitted with a
--label "my_label" tag during the submission
process
experiment: memcached
repositories:
P4Boosters: 7f4905bf
files:
documentation.md: ../memcached/Memcached.md
data: ../memcached/output/
anal... |
jtag_pulp:
incdirs: [
../../rtl/includes,
]
files: [
src/bscell.sv,
src/jtag_axi_wrap.sv,
src/jtag_enable.sv,
src/jtag_enable_synch.sv,
src/jtagreg.sv,
src/jtag_rst_synch.sv,
src/jtag_sync.sv,
src/tap_top.v,
]
jg_slint_top_name: [
tap_top
]
jg_slint_elab_opt: [
]
... |
<reponame>mballance/vte<filename>azure-pipelines.yml
variables:
build_num: $(Build.BuildNumber)
jobs:
- job: PyPi_Linux
pool:
vmImage: 'ubuntu-18.04'
steps:
- bash: echo "##vso[task.prependpath]$CONDA/bin"
displayName: Add conda to PATH
- script: |
python -m pip install wheel
python... |
derived_clks:
tb_emu_io:
abspath: 'tb_i'
emu_clk: 'emu_clk'
emu_rst: 'emu_rst'
emu_dt: 'emu_dt'
dt_req: 'dt_req'
iacore_clk_adc:
abspath: 'tb_i.top_i.iacore'
gated_clk_req: 'clk_adc_val'
gated_clk: 'clk_adc_i'
iacore_clk_indiv:
abspath: 'tb_i.top_i.iacore.iindiv'
emu_clk: '... |
name: Build Docker test image
on:
push:
branches:
- master
paths:
- docker/test/Dockerfile
- docker/lint/Dockerfile
- docker/tcl/Dockerfile
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Build docker test image 📦
shell: bash
... |
<reponame>bluetiger9/Vitis-AI<gh_stars>100-1000
name: vitis-ai-optimizer_pytorch
channels:
- pytorch
- defaults
dependencies:
- python=3.6
- vai_optimizer_pytorch_gpu
|
name: glb_tile_syn
commands:
- bash get_glb_tile_syn_outputs.sh
outputs:
- glb_tile.syn.v
- glb_tile.syn.sdc
- glb_tile.syn.sdf
- glb_tile.syn.spef
- glb_tile.syn.namemap
|
ePixHr10kT:
enable: True
ForceWrite: False
InitAfterConfig: False
EpixHR:
enable: True
RegisterControl:
enable: True
GlblRstPolarity: True
ClkSyncEn: False
SyncPolarity: False
SyncDelay: 0
SyncWidth: 0
SR0Polarity: False
SR0Delay1: 10
SR0Width1: 1600... |
name: fpu
clock_port: clk
verilog:
- except.v
- fpu.v
- post_norm.v
- pre_norm.v
- pre_norm_fmul.v
- primitives.v
|
<filename>Sources/ospboard/opt/osp/src/kernel/Documentation/devicetree/bindings/rtc/rtc.yaml<gh_stars>0
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RTC Generic Binding
maintainers:
- <NAME> <<EMAIL>>
... |
<filename>ips_list.yml
#
# List of IPs and relative branch/commit-hash/tag.
# Uses the YAML syntax.
#
# Examples:
#
# or10n:
# commit: tags/PULP3_final
# domain: [cluster]
# udma:
# commit: 62b10440
# domain: [soc]
# axi_slice:
# commit: tags/pulpissimo-v1.0
# domain: [soc,cluster]
# If a ... |
# Private CI trigger. Used to run tooling that can't currently be shared
# publicly.
# The runner used for private CI enforces the use of the template below. All
# build steps need to be placed into the template.
resources:
repositories:
- repository: opentitan-private-ci
type: github
endpoint: lowRISC
... |
package:
name: pulp
authors:
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
- "<NAME> <<EMAIL>>"
dependencies:
pulp_soc: { git: "<EMAIL>:micprog/pulp_soc.git", rev: "5847b1d45bceb9cf6275c3468e9a0180c94a... |
<gh_stars>0
---
file_list:
- "*.vhd"
rule:
constant_004:
case: upper
generic_007:
case: upper
port_025:
disable: false
variable_007:
disable: true
variable_012:
disable: false
signal_007:
disable: true
signal_008:
disable: false
signal_015:
consecutive: 1
...
|
<reponame>JeffDeCola/my-systemverilog-examples<gh_stars>1-10
# my-systemverilog-examples task-readme-github-pages.yml
platform: linux
image_resource:
type: docker-image
source:
repository: golang
tag: 1.7.1
inputs:
- name: my-systemverilog-examples
outputs:
- name: my-systemverilog-examples-updated
run... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
<filename>.travis.yml<gh_stars>0
language: python
python:
- '2.7'
- '3.8'
install:
- pip install -r requirements.txt
- pip install --editable .
script: ./test.sh
after_success: coveralls
notifications:
slack:
rooms:
secure: <KEY>
|
<filename>rtl/axi_slice/src_files.yml
axi_slice:
files: [
src/axi_single_slice.sv,
src/axi_ar_buffer.sv,
src/axi_aw_buffer.sv,
src/axi_b_buffer.sv,
src/axi_r_buffer.sv,
src/axi_slice.sv,
src/axi_w_buffer.sv,
src/axi_slice_wrap.sv,
]
jg_slint_top_name: [
axi_slice
]
jg_slint... |
<filename>ips/ip/i2c_slave_for_lpc8_polling/i2c_slave_for_lpc8_polling.yml
I2C_SLAVE_FOR_LPC8_POLLING:
IP: __I2C_SLAVE_FOR_LPC8_POLLING
CMD: ICS
ALT: a
scl_slv_polling:
PIN: A34
DIRECTION: IN
sda:
PIN: A36
DIRECTION: INOUT
I2C_SLAVE_FOR_LPC8_POLLING1:
IP: __I2C_... |
<gh_stars>0
name: Emscripten Build
on: [push, pull_request]
jobs:
emcc:
runs-on: ubuntu-latest
steps:
- uses: mymindstorm/setup-emsdk@v11
- uses: actions/checkout@v2
- name: Cache sources
id: cache-sources
uses: actions/cache@v2
with:
path: .
key... |
# This is a basic workflow to help you get started with Actions
name: CI
# Controls when the action will run. Triggers the workflow on push or pull request
# events but only for the main branch
on:
push:
branches: [ main ]
pull_request:
branches: [ main ]
jobs:
build:
# The type of runner that the ... |
<reponame>RoaLogic/ahb3lite_apb_bridge<gh_stars>10-100
theme: jekyll-theme-dinky
title: AHB-Lite to APB Bridge
description: Parameterised Asynchronous AHB-Lite to APB Bridge
show_downloads: true
show_license: true
license: Non-Commercial License
|
<reponame>ShreyasR46/Chip_Security_Advanced_Project<gh_stars>0
common_cells_all:
files:
- src/fifo_v1.sv
- src/fifo_v2.sv
- src/fifo_v3.sv
- src/lfsr_8bit.sv
- src/spill_register.sv
- src/stream_register.sv
- src/stream_mux.sv
- src/stream_demux.sv
- src/cdc_2phase.sv
- src/one... |
<reponame>es-ude/elastic-ai.creator
name: Checks
on:
pull_request:
workflow_call:
jobs:
integration-tests:
name: Integration Tests
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions/setup-python@v2
with:
python-version: 3.9
- uses: Gr1N/setup... |
<reponame>Charmve/BLE-Security-Att-Def
os: Visual Studio 2017
clone_depth: 1
configuration:
- Release
init:
- C:\"Program Files (x86)"\"Microsoft Visual Studio 14.0"\VC\vcvarsall.bat %PLATFORM%
install:
# Dependencies for libHackRF
- appveyor DownloadFile "https://github.com/libusb/libusb/releases/download/v1... |
<filename>libs/EXTERNAL/capnproto/appveyor.yml
# Cap'n Proto AppVeyor configuration
#
# See https://www.appveyor.com/docs/appveyor-yml/ for configuration options.
#
# This script configures AppVeyor to:
# - Use CMake to ...
# build Cap'n Proto with VS2017.
# build Cap'n Proto samples with VS2017.
# ... |
---
project:
description: "Time to Data Converter with Fine Delay"
foundry: "SkyWater"
git_url: "https://github.com/tgingold/OpenTDC.git"
organization: "N/A"
organization_url: "N/A"
owner: "<NAME>"
process: "SKY130"
project_name: "OpenTDC"
tags:
- "Open MPW"
category: "Sensor"
top_level_netlis... |
# File auto-generated by Padrick 0.1.0.post0.dev49+g9979c54.dirty
# IPApprox dependencies for alsaqr_periph_padframe
common_cells:
commit: v1.21.0
domain: [cluster, soc]
server: https://github.com
group: pulp-platform
register_interface:
commit: v0.2.1
domain: [soc]
server: https://github.com
group: pul... |
sudo: required
language: python
- "3.6"
services:
- docker
script:
- docker pull ghdl/ext:vunit
- docker run -dt --name=vunit_docker ghdl/ext:vunit bash
- docker exec vunit_docker mkdir siaMiner
- docker exec vunit_docker bash -c 'curl -L https://github.com/pedrorivera/SiaFpgaMiner/archive/master.tar.gz ... |
<gh_stars>10-100
# Copyright (C) 2019-2021 The SymbiFlow Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
name: ibex
description: Full ibex core test
top_module: ibex_simple_sys... |
# supported task types are 'classification', 'object_detection' and 'semantic_segmentation'.
task_type: {{ task_type }}
network_name: {{ network_name }}
dataset:
format: {{ dataset_format }}
train_path: {{ train_path }}
test_path: {{ test_path }}
trainer:
batch_size: {{ batch_size }}
epochs: {{ training_ep... |
<reponame>ess-dmsc/dmg-build-scripts
---
- hosts: packet-generator
gather_facts: False
tasks:
- name: start carbon metrics collection
command: "{{daemonize_cmd}} {{script_path}}/pktgen_fpga_config/pktgen_carbon.bash"
tags:
- generator
|
<reponame>francof2a/landsat_soil_classifier
KerasJson: /media/data/projects/landsat_soil_classifier/models/ANN50x50.json
KerasH5: /media/data/projects/landsat_soil_classifier/models/ANN50x50_weights.h5
InputData: /media/data/projects/landsat_soil_classifier/data/sat_x_test.dat
OutputPredictions: /media/data/projects/... |
<gh_stars>0
parameters:
ibex_configs: []
steps:
- ${{ each config in parameters.ibex_configs }}:
# ibex_config.py will exit with error code 1 on any error which will cause
# the CI to fail if there's an issue with the configuration file or an
# incorrect configuration name being used
- bash: |
... |
<filename>dlk/examples/classification/lmnet_quantize_cifar10_max_pooling/config_dlk.yaml
BATCH_SIZE: 1
DATASET:
AUGMENTOR:
lmnet.data_processor.Sequence:
processors:
-
lmnet.data_augmentor.Pad:
bottom: 2
fill: 0
left: 2
right: 2
top: 2
... |
variables:
SYNOPSYS_DC: synopsys-2019.12 dc_shell -64bit
before_script:
- export PATH=~/.cargo/bin:$PATH
- mkdir -p build
vsim:
stage: build
script:
- export ARTIFACT="vsim-$VSIM_VER"
- >
case $VSIM_VER in 20*)
export VSIM="questa-$VSIM_VER vsim -64";
export VLIB="questa-$VSIM_... |
<reponame>GregAC/opentitan<gh_stars>1000+
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Pipeline variables, used by the public and private CI pipelines
# Quote values to ensure they are parsed as string (version numb... |
---
input_file : ../akane/12_merge_sort_core_3.akd
output_file : 12_merge_sort_core_3.md
image_url :
"Fig.1 マージソートコアの構成" : "https://qiita-image-store.s3.ap-northeast-1.amazonaws.com/0/24981/e34555ae-cc28-e15e-a2e1-40ad0fc83cdc.jpeg"
"Fig.2 4-way マージソートツリーによる16ワードデータのソート例" : ... |
KerasJson: /media/data/projects/landsat_soil_classifier/models/ANN50x50th.json
KerasH5: /media/data/projects/landsat_soil_classifier/models/ANN50x50th_weights.h5
InputData: /media/data/projects/landsat_soil_classifier/data/sat_x_test.dat
OutputPredictions: /media/data/projects/landsat_soil_classifier/data/sat_y_test.... |
<gh_stars>0
fpnew:
incdirs: [
../common_cells/include,
]
files: [
src/fpnew_pkg.sv,
src/fpnew_cast_multi.sv,
src/fpnew_classifier.sv,
src/fpnew_divsqrt_multi.sv,
src/fpnew_fma.sv,
src/fpnew_fma_multi.sv,
src/fpnew_noncomp.sv,
src/fpnew_opgroup_block.sv,
src/fpnew_opgroup_fm... |
env:
runner:
type:
"runTestTestRunner"
common_compile_option: &common_compile >-
-sverilog
-ntb_opts uvm-1.2
common_sim_option: &common_sim >-
+UVM_VERBOSITY=UVM_LOW
+UVM_CONFIG_DB_TRACE
builds:
build2:
compile_option:
- *common_compile
- -timescale=1ns/10ps
pre_sim_action:
... |
<reponame>ess-dmsc/dmg-build-scripts
- name: packages are installed
become: yes
package:
name:
- daemonize
- psmisc
state: present
- name: destination folder exists
file:
path: ~/deployment
state: directory
- name: old binaries are deleted
file:
path: ~/deployment/event-formati... |
name: vitis-ai-caffe
channels:
- conda-forge
- anaconda
dependencies:
- python=3.6
- caffe_decent
- vaic
- vart
- rt-engine
|
<reponame>youssefkandil/Dynamic_Power_Clock_Gating-<filename>environment.yml
name: Dynamic_power_clk_gate
channels:
- litex-hub
- conda-forge
dependencies:
- openroad
- iverilog
- yosys
- python
- pip
- pytest
- pip:
- pandas
|
on: [push, pull_request]
name: CI
jobs:
check:
name: Check
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
name: "source checkout"
- uses: actions-rs/toolchain@v1
name: "toolchain installation"
with:
profile: minimal
toolchain: stable
... |
<filename>models/AI-Model-Zoo/model-list/tf_yolov3_voc_416_416_65.63G_1.4/model.yaml
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.or... |
common_compile_option: &common_compile >-
-sverilog
-ntb_opts uvm-1.1
-timescale=1ns/10ps
-f $JVSUK_HOME/etc/jvs.f
builds:
jvs_memory:
test_discoverer:
type: "uvm_test"
attr:
test_dir: $JVSUK_HOME/testcases/jvs_memory
compile_option:
- *common_compile
- $JVSUK_HOME/tb/jvs_memory_tb.sv -... |
#
# List of IPs and relative branch/commit-hash/tag.
# Uses the YAML syntax.
#
# Examples:
#
# or10n:
# commit: tags/PULP3_final
# domain: [cluster]
# udma:
# commit: 62b10440
# domain: [soc]
# axi_slice:
# commit: tags/pulpissimo-v1.0
# domain: [soc,cluster]
# If a *tag* or *commit* is re... |
<gh_stars>0
# @package _global_
do_blink:
backend: vivado
figure: fig2
sub_figure: b
device: 6eg
part: xczu6eg-ffvb1156-2-e
num_luts: 8640
bft: bft8
use_abs: True |
<filename>.travis.yml
#=========================================================================
# .travis.yml
#=========================================================================
# Continuous integration with TravisCI
language: python
python:
- "3.6"
#--------------------------------------------------------... |
<reponame>ikwzm/merge_sorter
---
input_file : 13_argsort.akd
output_file : ../13_argsort.md
image_url :
"Fig.1 マージソートコアの構成" : "image/13_argsort_1.jpg"
"Fig.2 ArgSort IPの構成" : "image/13_argsort_2.jpg"
"Fig.3 ArgSort IPの動作" : "image/13_argsort_3.jpg"
"Fig.4 ArgSort IP のプレビュー... |
# Copyright 2019 Xilinx Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,... |
<reponame>ben-marshall/uc64
os : linux
language: c
dist : bionic
env :
global:
- TOOLS_DIR: ~/tools
- VERILATOR_ROOT: ~/tools/verilator
- YOSYS_ROOT: ~/tools/yosys
- RISCV: ~/tools/riscv64-unknown-elf
before_install :
- sudo apt-get --yes install flex bison libfl2 libfl-dev perl build-essential cl... |
<filename>software/mesa/appveyor.yml<gh_stars>1-10
# http://www.appveyor.com/docs/appveyor-yml
#
# To setup AppVeyor for your own personal repositories do the following:
# - Sign up
# - Add a new project
# - Select Git and fill in the Git clone URL
# - Setup a Git hook as explained in
# https://github.com/appveyor/we... |
<filename>ips_list.yml
common_cells:
commit: v1.20.0
group: pulp-platform
common_verification:
commit: v0.1.1
group: pulp-platform
|
<reponame>zstars/weblabdeusto<gh_stars>0
language: python
services:
- redis-server
python: 2.7
install:
- pip install -r server/src/requirements.txt -r server/src/requirements_recommended.txt -r server/src/requirements_suggested.txt -r server/src/requirements_testing.txt
- python server/src/develop.py --deplo... |
# Human readable task name
name: pythia
# Long form description.
description: |+
Yet another oracle, but the queries are costly and limited so be frugal with them.
# The flag
flag: CTF{gCm_1s_n0t_v3ry_r0bust_4nd_1_sh0uld_us3_s0m3th1ng_els3_h3r3}
# Task category. (one of hw, crypto, pwn, rev, web, net, misc)
category:... |
language: python
dist: Xenial
python: "3.6"
install:
# Get Migen / LiteX / Cores
- wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
- python3 litex_setup.py init install
# Install LiteX-Boards
- python3 setup.py develop
before_script:
# Get RISC-V toolchain
- wget https:/... |
<reponame>c-rus/legoHDL<filename>.github/workflows/test.yml<gh_stars>1-10
name: test
on: [push]
jobs:
test:
strategy:
fail-fast: false
matrix:
python-version: ['3.5', '3.x']
runs-on: windows-latest
steps:
- uses: actions/checkout@v2
#setup python
- uses: actions/setu... |
name: sim-compile
parameters:
tool: "XCELIUM"
commands:
- bash run_sim.sh
inputs:
- design.v
- header
outputs:
- sim.log
postconditions:
- assert File( 'outputs/sim.log' ) # must exist
- assert 'Error,' not in File( 'outputs/sim.log' )
- assert '*E,' not in File( 'outputs/sim.log' )
|
<filename>src_files.yml
fpu_interco:
vlog_opts: [
-L fpnew_lib,
]
incdirs: [
../cv32e40p/rtl/include,
]
files: [
../cv32e40p/rtl/include/riscv_defines.sv,
FP_WRAP/fp_iter_divsqrt_msv_wrapper_2_STAGE.sv,
FP_WRAP/fpnew_wrapper.sv,
RTL/AddressDecoder_Req_FPU.sv,
... |
<reponame>mundaym/ibex
- test: riscv_instr_cov_debug_test
description: >
Functional coverage debug test, this is not a functional test to the core.
iterations: 1
gen_test: riscv_instr_cov_debug_test
no_iss: 1
no_gcc: 1
no_post_compare: 1
- test: riscv_instr_cov_test
description: >
Parse the instr... |
name: eth_top
clock_port: wb_clk_i
verilog:
- eth_clockgen.v
- eth_cop.v
- eth_crc.v
- eth_defines.v
- eth_fifo.v
- eth_maccontrol.v
- eth_macstatus.v
- eth_miim.v
- eth_outputcontrol.v
- eth_random.v
- eth_receivecontrol.v
- eth_register.v
- eth_registers.v
- et... |
name: CI
on:
push:
paths-ignore:
- .git*
- scripts/**
- README.md
pull_request:
jobs:
all-build:
strategy:
matrix:
platform: [ubuntu-20.04, macos-latest]
rust: [stable]
runs-on: ${{ matrix.platform }}
steps:
- uses: actions/checkout@v2
... |
<gh_stars>10-100
name: verilator-tests
on: [push, pull_request]
jobs:
build:
runs-on: ubuntu-18.04
steps:
- uses: actions/checkout@v2
with:
lfs: true
- name: Install Verilator
run: |
wget https://github.com/sifive/verilator/releases/download/4.036-0sifive2/v... |
#
# List of IPs and relative branch/commit-hash/tag.
# Uses the YAML syntax.
#
# Examples:
#
# or10n:
# commit: tags/PULP3_final
# domain: [cluster]
# udma:
# commit: 62b10440
# domain: [soc]
# axi_slice:
# commit: tags/pulpissimo-v1.0
# domain: [soc,cluster]
# If a *tag* or *commit* is re... |
name: glb_tile
commands:
- bash get_glb_outputs.sh
inputs:
- design.v
outputs:
- glb_tile_tt.lib
- glb_tile.lef
- glb_tile.gds
- glb_tile.lvs.v
- glb_tile.vcs.v
- glb_tile.sdf
- glb_tile_sram.spi
- glb_tile_sram.v
- glb_tile_sram_pwr.v
- glb_tile_sram_tt.lib
- glb_tile_sram_ff.lib
- glb_... |
<filename>.github/labeler.yml
# See https://github.com/actions/labeler#common-examples for defining patterns.
# The globs use "minimatch" syntax found at https://github.com/isaacs/minimatch
#
# WARNING: Due to this file being yaml, any string starting with `*` must be
# wrapped in quotes.
# Tools
ABC:
- abc_with_bb_s... |
language: go
go:
- 1.11.x
script:
- GOOS=linux go build
- GOOS=darwin go build
- GOOS=freebsd go build
- go test -v -coverprofile=coverage.txt -covermode=atomic
- go test -v -race
after_success:
- bash <(curl -s https://codecov.io/bash)
|
<reponame>SubjeBilisim/anasymod
name: Regression
on:
push:
pull_request:
workflow_dispatch:
schedule:
- cron: 0 11 * * ?
jobs:
linux:
runs-on: ubuntu-latest
steps:
- name: Checkout
uses: actions/checkout@v2
with:
fetch-depth: 0
- name: Set up Python 3.7
uses: act... |
<reponame>diorga/snitch
# Copyright 2020 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
site_name: Snitch
theme:
name: material
icon:
repo: fontawesome/brands/github
repo_url: https://github.com/pulp-platfo... |
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