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//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : pdl_block
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// Each pdl block consists of two 6 input LUTs.
// Initialised to 64'h5655555555555555 which translates each LUT as an inverter.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module pdl_block(i,o,t);
(* KEEP = "TRUE" *) (* S = "TRUE" *) input i;
(* KEEP = "TRUE" *) (* S = "TRUE" *) input t;
(* KEEP = "TRUE" *) (* S = "TRUE" *) output o;
(* KEEP = "TRUE" *) (* S = "TRUE" *) wire w;
(* KEEP = "TRUE" *) (* S = "TRUE" *) wire t;
(* BEL ="D6LUT" *) (* LOCK_PINS = "all" *)
LUT6 #(
.INIT(64'h5555555555555555) // Specify LUT Contents
) LUT6_inst_1 (
.O(w), // LUT general output
.I0(i), // LUT input
.I1(t), // LUT input
.I2(t), // LUT input
.I3(t), // LUT input
.I4(t), // LUT input
.I5(t) // LUT input
);
// End of LUT6_inst instantiation
(* BEL ="D6LUT" *) (* LOCK_PINS = "all" *)
LUT6 #(
.INIT(64'h5555555555555555) // Specify LUT Contents
) LUT6_inst_0 (
.O(o), // LUT general output
.I0(w), // LUT input
.I1(t), // LUT input
.I2(t), // LUT input
.I3(t), // LUT input
.I4(t), // LUT input
.I5(t) // LUT input
);
// End of LUT6_inst instantiation
endmodule |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; int n = s.size(); int cz = 0; int co = 0; int ct = 0; for (int i = 0; i < n; i++) { co += (s[i] == 1 ); ct += (s[i] == 2 ); cz += (s[i] == 0 ); } if (cz == 0 || ct == 0) { sort(s.begin(), s.end()); cout << s << n ; return 0; } if (co == 0) { cout << s << n ; return 0; } string aux = ; int idx = -1; for (int i = 0; i < n; i++) { if (s[i] != 1 ) aux += s[i]; } string res = ; int occ = -1; for (int i = 0; i < aux.size(); i++) { if (aux[i] == 2 && occ == -1) { while (co--) { res += 1 ; } res += aux[i]; occ = 1; } else { res += aux[i]; } } cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int NN = 100 * 1000 + 5; map<pair<pair<int, long long>, int>, long long> dp; vector<int> adj[NN]; vector<long long> x; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int mod = (int)1e9 + 7; int rec(int node, int parent, long long g, int state) { pair<pair<int, long long>, int> p = make_pair(make_pair(node, g), state); if (dp.find(p) != dp.end()) return dp[p]; long long& res = dp[p]; res = gcd(g, x[node]); res %= mod; long long new_g = gcd(g, x[node]); for (int child : adj[node]) { if (child == parent) continue; if (state == 0) { res += rec(child, node, g, 0); res %= mod; } res += rec(child, node, new_g, 1); res %= mod; } return res; } int main() { int n; scanf( %d , &n); x.resize(n); for (int i = 0; i < n; i++) { scanf( %lld , &x[i]); } for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d%d , &a, &b); a--; b--; adj[a].push_back(b); adj[b].push_back(a); } long long ans = rec(0, -1, 0, 0); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int INF = 1000000007; const int MOD = 1000000007; const int MAXN = 100055; int dx[] = {2, 1, -1, -2, -1, 1, 2, 1, -1}; int dy[] = {0, 2, 2, 0, -2, -2, 0, 2, 2}; int main() { long long n; while (cin >> n) { n++; if (n == 1) { cout << 0 0 << endl; continue; } long long L = (n - 1 + 2) / 3; L = sqrt(L + 0.5); while (3 * L * (L + 1) + 1 < n) ++L; n -= 3 * L * (L - 1) + 1; int side = (n - 1) / L; n -= L * side; long long ansx = dx[side] * L + dx[side + 2] * n; long long ansy = dy[side] * L + dy[side + 2] * n; cout << ansx << << ansy << endl; } return 0; } |
module nkmd_arch #(
parameter NKMDDBG_WIDTH = 16*8
)(
input wire clk,
input wire rst,
input wire uart_rx,
output wire uart_tx,
input wire [23:0] dai_data_i,
input wire dai_ack_i,
output wire [23:0] dai_data_o,
input wire dai_pop_i,
output wire dai_ack_o,
`ifdef PROMW
input wire [31:0] prog_addr_i,
input wire [31:0] prog_data_i,
input wire prog_ack_i,
`endif
output wire [(NKMDDBG_WIDTH-1):0] dbgout_o,
input wire [(NKMDDBG_WIDTH-1):0] dbgin_i);
wire [31:0] cpu_data_i;
wire [31:0] cpu_data_o;
wire [31:0] cpu_addr_o;
wire cpu_we_o;
wire [31:0] cpu_c_data_i;
assign cpu_c_data_i = 32'hbaadf00d;
wire [31:0] cpu_prog_data_i;
wire [31:0] cpu_prog_addr_o;
nkmd_cpu cpu(
.clk(clk), .rst(rst),
.r_data_i(cpu_data_i),
.r_data_o(cpu_data_o),
.r_addr_o(cpu_addr_o),
.r_we_o(cpu_we_o),
.c_data_i(cpu_c_data_i),
.p_data_i(cpu_prog_data_i),
.p_addr_o(cpu_prog_addr_o));
wire [31:0] ram_data_o;
nkmd_ram ram(
.clk(clk),
.data_i(cpu_data_o),
.data_o(ram_data_o),
.addr_i(cpu_addr_o),
.we_i(cpu_we_o));
wire [31:0] uart_data_o;
nkmd_uart uart(
.clk(clk), .rst(rst),
.rx(uart_rx), .tx(uart_tx),
.data_i(cpu_data_o),
.data_o(uart_data_o),
.addr_i(cpu_addr_o),
.we_i(cpu_we_o));
wire [31:0] dai_rx_data_o;
nkmd_dai_rx dai_rx(
.clk(clk), .rst(rst),
.rx_data_i(dai_data_i),
.rx_ack_i(dai_ack_i),
.data_i(cpu_data_o),
.data_o(dai_rx_data_o),
.addr_i(cpu_addr_o),
.we_i(cpu_we_o));
wire [31:0] dai_tx_data_o;
nkmd_dai_tx dai_tx(
.clk(clk), .rst(rst),
.tx_data_o(dai_data_o),
.tx_pop_i(dai_pop_i),
.tx_ack_o(dai_ack_o),
.data_i(cpu_data_o),
.data_o(dai_tx_data_o),
.addr_i(cpu_addr_o),
.we_i(cpu_we_o));
wire [31:0] debug_data_o;
nkmd_debug debug(
.clk(clk), .rst(rst),
.dbgout_o(dbgout_o), .dbgin_i(dbgin_i),
.data_i(cpu_data_o),
.data_o(debug_data_o),
.addr_i(cpu_addr_o),
.we_i(cpu_we_o));
assign cpu_data_i =
ram_data_o |
uart_data_o |
dai_rx_data_o | dai_tx_data_o |
debug_data_o;
`ifdef PROMW
nkmd_progrom_w
`else
nkmd_progrom
`endif
rom(
.clk(clk),
.addr_i(cpu_prog_addr_o),
.data_o(cpu_prog_data_i)
`ifdef PROMW
,
.prog_addr_i(prog_addr_i),
.prog_data_i(prog_data_i),
.prog_ack_i(prog_ack_i)
`endif
);
endmodule
|
/*
-- ============================================================================
-- FILE NAME : uart_ctrl.v
-- DESCRIPTION : UARTÖÆÓù¥â¥¸¥å©`¥ë
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "uart.h"
/********** ¥â¥¸¥å©`¥ë **********/
module uart_ctrl (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
input wire as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire rw, // Read / Write
input wire [`UartAddrBus] addr, // ¥¢¥É¥ì¥¹
input wire [`WordDataBus] wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output reg [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output reg rdy_, // ¥ì¥Ç¥£
/********** ¸î¤êÞz¤ß **********/
output reg irq_rx, // ÊÜÐÅÍêÁ˸î¤êÞz¤ß£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
output reg irq_tx, // ËÍÐÅÍêÁ˸î¤êÞz¤ß£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
/********** ÖÆÓùÐźŠ**********/
// ÊÜÐÅÖÆÓù
input wire rx_busy, // ÊÜÐÅÖХե饰£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
input wire rx_end, // ÊÜÐÅÍêÁËÐźÅ
input wire [`ByteDataBus] rx_data, // ÊÜÐťǩ`¥¿
// ËÍÐÅÖÆÓù
input wire tx_busy, // ËÍÐÅÖХե饰£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
input wire tx_end, // ËÍÐÅÍêÁËÐźÅ
output reg tx_start, // ËÍÐÅé_ʼÐźÅ
output reg [`ByteDataBus] tx_data // ËÍÐťǩ`¥¿
);
/********** ÖÆÓù¥ì¥¸¥Ä¥¿ **********/
// ÖÆÓù¥ì¥¸¥¹¥¿ 1 : ËÍÊÜÐťǩ`¥¿
reg [`ByteDataBus] rx_buf; // ÊÜÐťХåե¡
/********** UARTÖÆÓùÕÀí **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
rd_data <= #1 `WORD_DATA_W'h0;
rdy_ <= #1 `DISABLE_;
irq_rx <= #1 `DISABLE;
irq_tx <= #1 `DISABLE;
rx_buf <= #1 `BYTE_DATA_W'h0;
tx_start <= #1 `DISABLE;
tx_data <= #1 `BYTE_DATA_W'h0;
end else begin
/* ¥ì¥Ç¥£¤ÎÉú³É */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
/* Õi¤ß³ö¤·¥¢¥¯¥»¥¹ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
case (addr)
`UART_ADDR_STATUS : begin // ÖÆÓù¥ì¥¸¥¹¥¿ 0
rd_data <= #1 {{`WORD_DATA_W-4{1'b0}},
tx_busy, rx_busy, irq_tx, irq_rx};
end
`UART_ADDR_DATA : begin // ÖÆÓù¥ì¥¸¥¹¥¿ 1
rd_data <= #1 {{`BYTE_DATA_W*2{1'b0}}, rx_buf};
end
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
/* ø¤Þz¤ß¥¢¥¯¥»¥¹ */
// ÖÆÓù¥ì¥¸¥¹¥¿ 0 : ËÍÐÅÍêÁ˸î¤êÞz¤ß
if (tx_end == `ENABLE) begin
irq_tx<= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
irq_tx<= #1 wr_data[`UartCtrlIrqTx];
end
// ÖÆÓù¥ì¥¸¥¹¥¿ 0 : ÊÜÐÅÍêÁ˸î¤êÞz¤ß
if (rx_end == `ENABLE) begin
irq_rx<= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
irq_rx<= #1 wr_data[`UartCtrlIrqRx];
end
// ÖÆÓù¥ì¥¸¥¹¥¿ 1
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_DATA)) begin // ËÍÐÅé_ʼ
tx_start <= #1 `ENABLE;
tx_data <= #1 wr_data[`BYTE_MSB:`LSB];
end else begin
tx_start <= #1 `DISABLE;
tx_data <= #1 `BYTE_DATA_W'h0;
end
/* ÊÜÐťǩ`¥¿¤ÎÈ¡¤êÞz¤ß */
if (rx_end == `ENABLE) begin
rx_buf <= #1 rx_data;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__EBUFN_PP_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_PP_SYMBOL_V
|
/*
* Wishbone switch and address decoder
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
* Copyright (C) 2008, 2009 Sebastien Bourdeauducq - http://lekernel.net
* Copyright (C) 2000 Johny Chi -
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module wb_switch #(
parameter s0_addr_1 = 32'h00000000,
parameter s0_mask_1 = 32'h00000000,
parameter s0_addr_2 = 32'h00000000,
parameter s0_mask_2 = 32'h00000000,
parameter s1_addr_1 = 32'h00000000,
parameter s1_mask_1 = 32'h00000000,
parameter s2_addr_1 = 32'h00000000,
parameter s2_mask_1 = 32'h00000000
)(
// Master interface
input [31:0] m_dat_i,
output [31:0] m_dat_o,
input [31:0] m_adr_i,
input [ 3:0] m_sel_i,
input m_we_i,
input m_cyc_i,
input m_stb_i,
output m_ack_o,
// Slave 0 interface
input [31:0] s0_dat_i,
output [31:0] s0_dat_o,
output [31:0] s0_adr_o,
output [ 3:0] s0_sel_o,
output s0_we_o,
output s0_cyc_o,
output s0_stb_o,
input s0_ack_i,
// Slave 1 interface
input [31:0] s1_dat_i,
output [31:0] s1_dat_o,
output [31:0] s1_adr_o,
output [ 3:0] s1_sel_o,
output s1_we_o,
output s1_cyc_o,
output s1_stb_o,
input s1_ack_i,
// Slave 2 interface
input [31:0] s2_dat_i,
output [31:0] s2_dat_o,
output [31:0] s2_adr_o,
output [ 3:0] s2_sel_o,
output s2_we_o,
output s2_cyc_o,
output s2_stb_o,
input s2_ack_i,
// Slave 3 interface - the default
input [31:0] s3_dat_i,
output [31:0] s3_dat_o,
output [31:0] s3_adr_o,
output [ 3:0] s3_sel_o,
output s3_we_o,
output s3_cyc_o,
output s3_stb_o,
input s3_ack_i
);
`define mbusw_ls 32 + 4 + 32 + 1 + 1 + 1 // address + byte select + data + cyc + we + stb
wire [3:0] slave_sel;
wire [31:0] i_dat_s; // internal shared bus, slave data to master
wire i_bus_ack; // internal shared bus, ack signal
wire [`mbusw_ls -1:0] i_bus_m; // internal shared bus, master data and control to slave
assign m_dat_o = i_dat_s;
assign m_ack_o = i_bus_ack;
// Bus Acknowlegement
assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i;
assign i_dat_s = ({32{slave_sel[ 0]}} & s0_dat_i)
|({32{slave_sel[ 1]}} & s1_dat_i)
|({32{slave_sel[ 2]}} & s2_dat_i)
|({32{slave_sel[ 3]}} & s3_dat_i)
;
// Bus Selection logic
assign slave_sel[0] = ((m_adr_i & s0_mask_1) == s0_addr_1) | ((m_adr_i & s0_mask_2) == s0_addr_2);
assign slave_sel[1] = ~(|slave_sel[0]) & ((m_adr_i & s1_mask_1) == s1_addr_1);
assign slave_sel[2] = ~(|slave_sel[1:0]) & ((m_adr_i & s2_mask_1) == s2_addr_1);
assign slave_sel[3] = ~(|slave_sel[2:0]);
assign i_bus_m = {m_adr_i, m_sel_i, m_dat_i, m_we_i, m_cyc_i, m_stb_i};
assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 0
assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[0];
assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 1
assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[1];
assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 2
assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[2];
assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cyc_o} = i_bus_m[`mbusw_ls -1:1]; // slave 3
assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[3];
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vl = vector<ll>; using pi = pair<int, int>; namespace output { void pr(int x) { cout << x; } void pr(long x) { cout << x; } void pr(ll x) { cout << x; } void pr(unsigned x) { cout << x; } void pr(unsigned long x) { cout << x; } void pr(unsigned long long x) { cout << x; } void pr(float x) { cout << x; } void pr(double x) { cout << x; } void pr(long double x) { cout << x; } void pr(char x) { cout << x; } void pr(const char* x) { cout << x; } void pr(const string& x) { cout << x; } void pr(bool x) { pr(x ? true : false ); } template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T> void pr(const T& x); template <class T, class... Ts> void pr(const T& t, const Ts&... ts) { pr(t); pr(ts...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T> void pr(const T& x) { pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } void ps() { pr( n ); } template <class T, class... Ts> void ps(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( ); ps(ts...); } void pc() { cout << ] << endl; } template <class T, class... Ts> void pc(const T& t, const Ts&... ts) { pr(t); if (sizeof...(ts)) pr( , ); pc(ts...); } } // namespace output using namespace output; const int MX = 200005; const int MOD = (int)(1e9 + 7); const ll INF = (ll)1e18; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vi a(n); vi cnt(101); for (int i = 0; i < n; i++) { cin >> a[i]; cnt[a[i]]++; } pi best = make_pair(-1, -1); for (int i = 1; i <= 100; i++) { if (cnt[i] > best.second) best = make_pair(i, cnt[i]); } for (int i = 1; i <= 100; i++) { if (i != best.first && cnt[i] == best.second) { cout << n << n ; return 0; } } int ret = 0; for (int v = 1; v <= 100; v++) { if (v == best.first) continue; int ans = 0; vi nv(n); for (int i = 0; i < n; i++) { if (a[i] == v) nv[i] = -1; else if (a[i] == best.first) nv[i] = 1; } vi mn(2 * n + 1, -2); mn[n] = -1; int sum = 0; for (int i = 0; i < n; i++) { sum += nv[i]; if (mn[sum + n] != -2) ans = max(ans, i - mn[sum + n]); else mn[sum + n] = i; } ret = max(ret, ans); } cout << ret << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A31OI_BEHAVIORAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_BEHAVIORAL_V |
function int hello(int a);
begin
$display("hello from unit 1");
hello = a;
end
endfunction
task hello1;
begin
$display("hello1 from unit 1");
end
endtask
task hello2;
begin
$display("hello2 from unit 1");
end
endtask
task hello3;
begin
$display("hello3 from unit 1");
end
endtask
class c1;
task hello2;
begin
hello1;
$display("hello2 from c1");
end
endtask
endclass
module m1();
int i;
c1 obj;
initial begin
#1;
i = $unit::hello(1);
obj = new;
obj.hello2;
hello1;
hello2;
hello3;
hello4;
end
task hello2;
begin
$display("hello2 from m1");
end
endtask
endmodule
module m2();
m1 m1inst();
task hello1;
begin
$display("hello1 from m2");
end
endtask
task hello2;
begin
$display("hello2 from m2");
end
endtask
task hello3;
begin
$display("hello3 from m2");
end
endtask
task hello4;
begin
$display("hello4 from m2");
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
ma ma0 ();
initial t.ma0.u_b[0].f(1);
initial t.ma0.u_b[0].f(clk);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
function [31:0] getName; input fake; getName = "t "; endfunction
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==2) begin
if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop;
if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop;
end
if (cyc==3) begin
if (ma0. getName(1'b0) !== "ma ") $stop;
if (ma0.mb0. getName(1'b0) !== "mb ") $stop;
if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop;
end
if (cyc==4) begin
if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop;
if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop;
if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop;
end
if (cyc==5) begin
ma0. checkName(ma0. getName(1'b0));
ma0.mb0. checkName(ma0.mb0. getName(1'b0));
ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0));
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef ATTRIBUTES
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
`else
`define INLINE_MODULE
`define INLINE_MID_MODULE
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
function [31:0] getName; input fake; getName = "gmod"; endfunction
function [31:0] getGlob; input fake; getGlob = globali; endfunction
endmodule
module ma ();
`INLINE_MODULE
mb #(0) mb0 ();
reg [31:0] gName; initial gName = "ma ";
function [31:0] getName; input fake; getName = "ma "; endfunction
task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask
initial begin
if (ma.getName(1'b0) !== "ma ") $stop;
if (mb0.getName(1'b0) !== "mb ") $stop;
if (mb0.mc0.getName(1'b0) !== "mc ") $stop;
end
endmodule
module mb ();
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 ();
mc #(P2,1) mc1 ();
global_mod #(32'hf33d) global_cell2 ();
reg [31:0] gName; initial gName = "mb ";
function [31:0] getName; input fake; getName = "mb "; endfunction
function [31:0] getP2 ; input fake; getP2 = P2; endfunction
task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask
initial begin
`ifndef verilator #1; `endif
if (ma. getName(1'b0) !== "ma ") $stop;
if ( getName(1'b0) !== "mb ") $stop;
if (mc1.getName(1'b0) !== "mc ") $stop;
ma. checkName (ma. gName);
/**/checkName ( gName);
mc1.checkName (mc1.gName);
ma. checkName (ma. getName(1'b0));
/**/checkName ( getName(1'b0));
mc1.checkName (mc1.getName(1'b0));
end
endmodule
module mc ();
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
reg [31:0] gName; initial gName = "mc ";
function [31:0] getName; input fake; getName = "mc "; endfunction
function [31:0] getP3 ; input fake; getP3 = P3; endfunction
task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask
initial begin
`ifndef verilator #1; `endif
if (ma.getName(1'b0) !== "ma ") $stop;
if (mb.getName(1'b0) !== "mb ") $stop;
if (mc.getName(1'b0) !== "mc ") $stop;
ma.checkName (ma.gName);
mb.checkName (mb.gName);
mc.checkName (mc.gName);
ma.checkName (ma.getName(1'b0));
mb.checkName (mb.getName(1'b0));
mc.checkName (mc.getName(1'b0));
end
endmodule
module b;
function void f(bit v);
$display("%m");
endfunction : f;
endmodule : b
bind ma b u_b[0:1];
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 1; int v[N], md[N]; vector<int> freq[N]; int lm[N], rm[N]; int cs[N]; int val(int x, int l, int r) { if (l > r || l < 0) return 0; return upper_bound(freq[x].begin(), freq[x].end(), r) - lower_bound(freq[x].begin(), freq[x].end(), l); } int main() { int n, k; scanf( %d%d , &n, &k); freq[0].push_back(0); for (int i = 1; i <= n; i++) { scanf( %d , &v[i]); md[i] = v[i] % k; cs[i] += v[i] % k; cs[i] += cs[i - 1]; cs[i] %= k; freq[cs[i]].push_back(i); } stack<pair<int, int> > s; for (int i = n; i > 0; i--) { while (s.size() && s.top().first < v[i]) { s.pop(); } if (s.size()) { rm[i] = s.top().second - 1; } else rm[i] = n; s.push(make_pair(v[i], i)); } while (!s.empty()) { s.pop(); } for (int i = 1; i <= n; i++) { while (s.size() && s.top().first <= v[i]) { s.pop(); } if (s.size()) { lm[i] = s.top().second + 1; } else lm[i] = 1; s.push(make_pair(v[i], i)); } long long ans = 0; int l, r, al, ar; int x, d; for (int i = 1; i <= n; i++) { if (lm[i] == rm[i]) continue; if (abs(lm[i] - i) + 1 < abs(i - rm[i]) + 1) { l = lm[i] - 1, r = i - 2; al = i + 1, ar = rm[i]; d = md[i]; } else { d = -md[i]; l = i + 1, r = rm[i]; al = lm[i] - 1, ar = i - 2; } for (int j = l; j <= r; j++) { x = cs[j] + d + k; x %= k; ans += val(x, al, ar); } ans += val(cs[i - 1], lm[i] - 1, i - 2); ans += val(cs[i], i + 1, rm[i]); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, bal; string s, t; int main() { ios_base::sync_with_stdio(false); cin >> s; n = s.length(); bal = m = 0; for (int i = n - 1; i >= 0; --i) { if (s[i] == 0 ) --bal; else { if (bal + m >= 0) { int j = i; while (j >= 0 && s[j] == 1 ) { s[j] = 0 ; --j; ++m; } --bal; } else ++bal; } } cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, v, arr[1000], c = 0; cin >> x >> v; for (int i = 0; i < x - 1; i++) { cin >> arr[i]; } while (1) { sort(arr, arr + x - 1); if (v > arr[x - 2]) break; arr[x - 2]--; v++; c++; } cout << c; return 0; } |
// -*- Mode: Verilog -*-
// Filename : fpga.v
// Description : Prototype FPGA setup for SPI device
// Author : Philip Tracton
// Created On : Fri Jul 8 20:51:04 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Jul 8 20:51:04 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module fpga (/*AUTOARG*/
// Outputs
sck_o, ncs_o, mosi_o,
// Inputs
clk_i, rst_i, miso_i, int1, int2
) ;
input wire clk_i;
input wire rst_i;
output wire sck_o;
output wire ncs_o;
output wire mosi_o;
input wire miso_i;
input wire int1;
input wire int2;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clear_spif; // From controller of spi_controller.v
wire clear_wcol; // From controller of spi_controller.v
wire clk; // From sys_con of system_controller.v
wire inta_o; // From spi of simple_spi_top_modified.v
wire nrst; // From sys_con of system_controller.v
wire [7:0] rfdout; // From spi of simple_spi_top_modified.v
wire rfre; // From controller of spi_controller.v
wire rst; // From sys_con of system_controller.v
wire [7:0] spcr; // From controller of spi_controller.v
wire [7:0] sper; // From controller of spi_controller.v
wire [7:0] spsr; // From spi of simple_spi_top_modified.v
wire [15:0] temperature; // From controller of spi_controller.v
wire [7:0] wfdin; // From controller of spi_controller.v
wire wfwe; // From controller of spi_controller.v
wire wr_spsr; // From controller of spi_controller.v
// End of automatics
//
// System Controller
//
// This module handles all clocks and synchronizes reset from the IO pins
//
system_controller sys_con(/*AUTOINST*/
// Outputs
.clk (clk),
.rst (rst),
.nrst (nrst),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i));
//
// SPI Controller
//
// This is a state machine to control interfacing with the ADXL362
//
spi_controller controller(/*AUTOINST*/
// Outputs
.wfdin (wfdin[7:0]),
.spcr (spcr[7:0]),
.sper (sper[7:0]),
.wfwe (wfwe),
.rfre (rfre),
.wr_spsr (wr_spsr),
.clear_spif (clear_spif),
.clear_wcol (clear_wcol),
.ncs_o (ncs_o),
.temperature (temperature[15:0]),
// Inputs
.clk (clk),
.rst (rst),
.rfdout (rfdout[7:0]),
.inta_o (inta_o),
.spsr (spsr[7:0]));
//
// SPI
//
// This is the SPI module that handles communication with ADXL362
//
simple_spi_top_modified spi(/*AUTOINST*/
// Outputs
.spsr (spsr[7:0]),
.inta_o (inta_o),
.rfdout (rfdout[7:0]),
.sck_o (sck_o),
.mosi_o (mosi_o),
// Inputs
.clk_i (clk_i),
.nrst (nrst),
.spcr (spcr[7:0]),
.sper (sper[7:0]),
.wfwe (wfwe),
.rfre (rfre),
.wr_spsr (wr_spsr),
.clear_spif (clear_spif),
.clear_wcol (clear_wcol),
.wfdin (wfdin[7:0]),
.miso_i (miso_i));
endmodule // fpga
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, c, d; cin >> a >> b >> c >> d; if ((a + b) % 2 == 0) { cout << Tidak Tidak ; if (b || c) cout << Ya ; else cout << Tidak ; if (a || d) cout << Ya ; else cout << Tidak ; } else { if (a || d) cout << Ya ; else cout << Tidak ; if (b || c) cout << Ya ; else cout << Tidak ; cout << Tidak Tidak ; } cout << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRSDFRTP_BEHAVIORAL_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_pr_pp_pkg_sn.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__srsdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire mux_out ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, RESET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( ( SLEEP_B === 1'b1 ) && awake );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 && awake );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_BLACKBOX_V
`define SKY130_FD_SC_LS__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_BLACKBOX_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_rom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "ddr3_s4_uniphy_example_if0_p0_sequencer_rom.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input debugaccess;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write & debugaccess;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "ddr3_s4_uniphy_example_if0_p0_sequencer_rom.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; template <typename T, size_t N> int SIZE(const T (&t)[N]) { return N; } template <typename T> int SIZE(const T &t) { return t.size(); } string to_string(const string s, int x1 = 0, int x2 = 1e9) { return + ((x1 < s.size()) ? s.substr(x1, x2 - x1 + 1) : ) + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(const bool b) { return (b ? true : false ); } string to_string(const char c) { return string({c}); } template <size_t N> string to_string(const bitset<N> &b, int x1 = 0, int x2 = 1e9) { string t = ; for (int __iii__ = min(x1, SIZE(b)), __jjj__ = min(x2, SIZE(b) - 1); __iii__ <= __jjj__; ++__iii__) { t += b[__iii__] + 0 ; } return + t + ; } template <typename A, typename... C> string to_string(const A(&v), int x1 = 0, int x2 = 1e9, C... coords); int l_v_l_v_l = 0, t_a_b_s = 0; template <typename A, typename B> string to_string(const pair<A, B> &p) { l_v_l_v_l++; string res = ( + to_string(p.first) + , + to_string(p.second) + ) ; l_v_l_v_l--; return res; } template <typename A, typename... C> string to_string(const A(&v), int x1, int x2, C... coords) { int rnk = rank<A>::value; string tab(t_a_b_s, ); string res = ; bool first = true; if (l_v_l_v_l == 0) res += n ; res += tab + [ ; x1 = min(x1, SIZE(v)), x2 = min(x2, SIZE(v)); auto l = begin(v); advance(l, x1); auto r = l; advance(r, (x2 - x1) + (x2 < SIZE(v))); for (auto e = l; e != r; e = next(e)) { if (!first) { res += , ; } first = false; l_v_l_v_l++; if (e != l) { if (rnk > 1) { res += n ; t_a_b_s = l_v_l_v_l; }; } else { t_a_b_s = 0; } res += to_string(*e, coords...); l_v_l_v_l--; } res += ] ; if (l_v_l_v_l == 0) res += n ; return res; } void dbgm() { ; } template <typename Heads, typename... Tails> void dbgm(Heads H, Tails... T) { cout << to_string(H) << | ; dbgm(T...); } const long long MOD = (int)1e9 + 7; string ascii_lowercase = abcdefghijklmnopqrstuvwxyz ; string ascii_uppercase = ABCDEFGHIJKLMNOPQRSTUVWXYZ ; long long inv(long long a, long long b) { return 1 < a ? b - inv(b % a, a) * b / a : 1; } const long long INF = 1e6; unordered_map<int, int, custom_hash> mp; long long gcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long distsq(long long x1, long long y1, long long x2, long long y2) { return (x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1); } long long n, m; double get(double x1, double y1, double x2, double y2, double x3, double y3) { if (x3 == x1) { return (x2 - x1) * (x2 - x1); } if (y3 == y1) { return (y2 - y1) * (y2 - y1); } double m = (y3 - y1) / (x3 - x1); double c = y1 - m * x1; double mm = -1 / m; double interx = (-m * c + m * y2 + x2) / (1 + m * m); double dx = interx - x2; double dy = mm * dx; return dx * dx + dy * dy; } double px[1005]; double py[1005]; double ans = -1; int main() { cin >> n; for (int i = 0; i < (n); i++) { cin >> px[i] >> py[i]; } double curr; for (int i = 0; i < (n); i++) { curr = get(px[i], py[i], px[(i + 1) % n], py[(i + 1) % n], px[(i + 2) % n], py[(i + 2) % n]); if (ans < 0) ans = curr; ans = min(ans, curr); } printf( %.12f n , sqrt(ans) / 2.0); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_TB_V
`define SKY130_FD_SC_HVL__DIODE_TB_V
/**
* diode: Antenna tie-down diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__diode.v"
module top();
// Inputs are registered
reg DIODE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
DIODE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 DIODE = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 DIODE = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 DIODE = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 DIODE = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 DIODE = 1'bx;
end
sky130_fd_sc_hvl__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_TB_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate variable left shift in assign
module main;
reg globvar;
reg [7:0] var1,var2,var3;
reg error;
reg [7:0] value;
function [7:0] lshft;
input [7:0] var1,var2;
begin
lshft = var1 << var2;
end
endfunction
initial
begin
error = 0;
#1 ;
var1 = 8'h1;
var2 = 8'h0;
value = lshft(var1,var2);
#1;
if(value !== 8'h1)
begin
error = 1;
$display ("FAILED - 1 << 0 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h1;
value = lshft(var1,var2);
#1;
if(value !== 8'h2)
begin
error = 1;
$display ("FAILED - 1 << 1 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h2;
value = lshft(var1,var2);
#1;
if(value !== 8'h4)
begin
error = 1;
$display ("FAILED - 1 << 2 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h3;
value = lshft(var1,var2);
#1;
if(value !== 8'h8)
begin
error = 1;
$display ("FAILED - 1 << 3 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h4;
value = lshft(var1,var2);
#1;
if(value !== 8'h10)
begin
error = 1;
$display ("FAILED - 1 << 4 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h5;
value = lshft(var1,var2);
#1;
if(value !== 8'h20)
begin
error = 1;
$display ("FAILED - 1 << 5 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h6;
value = lshft(var1,var2);
#1;
if(value !== 8'h40)
begin
error = 1;
$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8'h1;
var2 = 8'h7;
value = lshft(var1,var2);
#1;
if(value !== 8'h80)
begin
error = 1;
$display ("FAILED - 1 << 6 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h7;
value = lshft(var1,var2);
#1;
if(value !== 8'h80)
begin
error = 1;
$display ("FAILED - a5 << 7 is %h",value);
end
#1 ;
var1 = 8'ha5;
var2 = 8'h1;
value = lshft(var1,var2);
#1;
if(value !== 8'h4a)
begin
error = 1;
$display ("FAILED - aa << 1 is %h",value);
end
if(error === 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18 + 1; const int MAX = 200001; const long long MOD = 1000000007; struct trio { int first; int second; int third; }; struct long_trio { long long first; long long second; long long third; }; double dist_point_line(int x1, int y1, int x2, int y2, int x3, int y3) { double distance = abs((y3 - y1) * x2 - (x3 - x1) * y2 + x3 * y1 - x1 * y3) / (2 * sqrt((x3 - x1) * (x3 - x1) + (y3 - y1) * (y3 - y1))); return distance; } double dist_point_point(int x1, int y1, int x2, int y2) { double distance = sqrt((x1 - y1) * (x1 - y1) + (x2 - y2) * (x2 - y2)); return distance; } long long inq(long long k, long long q) { if (q == 0) return 1; long long l = inq(k, q / 2); if (q % 2 == 0) return l * l % MOD; else return l * l * k % MOD; } long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } long long cubr(long long a) { long long l = -1, r = 1e6 + 2; while (l < r - 1) { long long mid = (l + r) / 2; if (mid * mid * mid > a) r = mid; else l = mid; } return l; } long long max(long long a, long long b) { if (a > b) return a; return b; } long long min(long long a, long long b) { return -1 * max(-a, -b); } long long possible(long long q) { if (q == INF) return -1; return q; } bool correct(int x, int xx) { if (x < 0) return 0; if (x >= xx) return 0; return 1; } long long dsumm(long long x) { long long y = 1; long long z = 0; for (int i = 0; i < 18; i++) { z += x / y % 10; y *= 10; } return z; } int check_(vector<int> arr) { for (int i = 0; i < arr.size(); i++) { cout << arr[i] << ; } cout << endl; return 0; } void perms(vector<int> perm, vector<int> used, int n, int k) { if (k == 0) { check_(perm); return; } for (int i = 0; i < n; i++) { if (used[i] == 0) { used[i] = 1; perm.push_back(i); perms(perm, used, n, k - 1); perm.pop_back(); used[i] = 0; } } return; } void bins(vector<int> bin, int k) { if (k == 0) { check_(bin); return; } bin.push_back(0); bins(bin, k - 1); bin.pop_back(); bin.push_back(1); bins(bin, k - 1); bin.pop_back(); return; } string months[12] = { January , February , March , April , May , June , July , August , September , October , November , December }; int days[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; long long fact[13] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362280, 3622800, 39916800, 479001600}; int cx[6] = {1, -1, 0, 0, 0, 0}; int cy[6] = {0, 0, 1, -1, 0, 0}; int cz[6] = {0, 0, 0, 0, 1, -1}; long long n, m, ans, l, r, k; long long x[300000], abs_summ; string s; int main() { cin >> n >> l >> r; k = l + r; for (int(i) = 0; (i) != (n); i++) { cin >> x[i]; } for (int(i) = 0; (i) != (n); i++) { cin >> m; x[i] = abs(x[i] - m); } sort(x, x + n); reverse(x, x + n); while (k > 0) { x[0] = abs(x[0] - 1); sort(x, x + n); reverse(x, x + n); k--; } m = 0; for (int(i) = 0; (i) != (n); i++) { m += x[i] * x[i]; } cout << m; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int a, b, n; vector<int> div; cin >> a >> b >> n; if (b > a) swap(a, b); for (int d = 1; d * d <= b; d++) { if (a % d == 0 and b % d == 0) div.push_back(d); int d2 = -1; if (b % d == 0 and b / d != d) d2 = b / d; if (d2 != -1) if (a % d2 == 0) div.push_back(d2); } sort(div.begin(), div.end()); while (n--) { int l, r; cin >> l >> r; auto it = upper_bound(div.begin(), div.end(), r); it--; if (l <= *it and *it <= r) cout << *it << endl; else cout << -1 n ; } } |
module memory(
gm_or_lds,
rd_en,
wr_en,
addresses,
wr_data,
input_tag,
// wr_mask,
rd_data,
output_tag,
ack,
clk,
rst
);
input clk;
input rst;
input gm_or_lds;
input rd_en, wr_en;
input [31:0] addresses;
input [31:0] wr_data;
input [6:0] input_tag;
output [6:0] output_tag;
output ack;
output [31:0] rd_data;
reg[7:0] data_memory[50000:0];
reg[7:0] lds_memory[65535:0];
reg ack_reg;
reg [6:0] tag_reg;
//integer locrd = 4; // num of loc to read
assign ack = ack_reg;
assign output_tag = tag_reg;
integer i;
always@(posedge clk, posedge rst) begin
// if(rst) begin
// for(i = 0; i < 50001; i = i+1) begin
// data_memory[i] <= 0;
// end
// for(i = 0; i < 65536; i = i+1) begin
// lds_memory[i] <= 0;
// end
// end
// else
if(wr_en) begin
if(gm_or_lds) begin
lds_memory [addresses] <= wr_data[7:0];
lds_memory [addresses+1] <= wr_data[15:7];
lds_memory [addresses+2] <= wr_data[23:16];
lds_memory [addresses+3] <= wr_data[31:24];
end
else begin
data_memory [addresses] <= wr_data[7:0];
data_memory [addresses+1] <= wr_data[15:7];
data_memory [addresses+2] <= wr_data[23:16];
data_memory [addresses+3] <= wr_data[31:24];
end
end
end
always@(posedge clk) begin
if(rst) begin
ack_reg <= 1'b0;
tag_reg <= 7'd0;
end
else begin
ack_reg <= 1'b0;
tag_reg <= 7'd0;
if(rd_en | wr_en) begin
ack_reg <= 1'b1;
tag_reg <= input_tag;
end
end
end
wire [31:0] rd_lds;
wire [31:0] rd_dm;
assign rd_lds = {lds_memory[addresses+3],lds_memory[addresses+2],lds_memory[addresses+1],lds_memory[addresses]};
assign rd_dm = {data_memory[addresses+3],data_memory[addresses+2],data_memory[addresses+1],data_memory[addresses]};
assign rd_data = (gm_or_lds) ? rd_lds:rd_dm;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, e, z[509], x[509], pi, g, s; vector<int> v[509]; bool m, rr; pair<int, int> p[509]; void dfs(int w) { if (m == 1) return; z[w] = 1; for (vector<int>::iterator it = v[w].begin(); it != v[w].end(); it++) { if (x[(*it)] == c) { p[pi].first = w; p[pi].second = (*it); pi++; m = 1; g = (*it); return; } if (z[(*it)] == 0) { x[(*it)] = c; p[pi].first = w; p[pi].second = (*it); pi++; dfs((*it)); if (m == 1) return; } } x[w] = 0; } void dfss(int w) { if (rr == 1) { x[w] = 0; return; } z[w] = d + 1; for (vector<int>::iterator it = v[w].begin(); it != v[w].end(); it++) { if ((((*it) == p[d].second && w == p[d].first))) continue; if (x[(*it)] == d + 1) { s = 1; rr = 1; x[w] = 0; return; } if (z[(*it)] != d + 1) { x[(*it)] = d + 1; dfss((*it)); if (rr == 1) { x[w] = 0; return; } } } x[w] = 0; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> a >> b; for (c = 1; c <= b; c++) { cin >> d >> e; v[d].push_back(e); } for (c = 1; c <= a; c++) { if (z[c] == 0) { x[c] = c; dfs(c); if (m == 1) break; } } if (g == 0) { cout << YES ; return 0; } for (d = 0; d < pi; d++) { if (p[d].first == g) break; } for (c = 0; c <= 502; c++) z[c] = 0, x[c] = 0; for (d = d; d < pi; d++) { for (c = 1; c <= a; c++) { if (z[c] != d + 1) { x[c] = d + 1; rr = 0; dfss(c); if (rr == 1) break; } } if (rr == 0) { cout << YES ; return 0; } } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1010; string a[MAX]; int n, m; bool visit[MAX][MAX]; bool v[1000010]; int b[MAX][MAX]; int val[1000010]; void dfs(int x, int y, int cnt) { if (x < 0 || y < 0 || x >= n || y >= m) { return; } if (visit[x][y]) { return; } if (a[x][y] == * ) { return; } visit[x][y] = true; val[cnt]++; b[x][y] = cnt; dfs(x + 1, y, cnt); dfs(x, y + 1, cnt); dfs(x - 1, y, cnt); dfs(x, y - 1, cnt); } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } memset(visit, false, sizeof(visit)); memset(b, -1, sizeof(visit)); memset(val, 0, sizeof(val)); int cnt = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (!visit[i][j] && a[i][j] == . ) { dfs(i, j, cnt); cnt++; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == * ) { int temp = 1, t[5] = {0}; if (b[i - 1][j] != -1 && i - 1 >= 0) { t[0] = b[i - 1][j]; } if (b[i][j - 1] != -1 && j - 1 >= 0) { t[1] = b[i][j - 1]; } if (b[i + 1][j] != -1 && i + 1 < n) { t[2] = b[i + 1][j]; } if (b[i][j + 1] != -1 && j + 1 < m) { t[3] = b[i][j + 1]; } sort(t, t + 4); for (int k = 0; k < 4; k++) { if (t[k] != t[k + 1]) { temp += val[t[k]]; } } a[i][j] = 0 + (temp) % 10; } } } for (int i = 0; i < n; i++) { cout << a[i] << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, M; vector<set<int> > A; vector<set<pair<int, int> > > B; vector<int> d, f, F, G; vector<bool> v; inline void upd(int& a, int b) { if (d[a] > d[b]) a = b; } void ff(int x, int y) { f[x] = x, v[x] = 1; for (set<int>::iterator i = A[x].begin(); i != A[x].end(); i++) if (v[*i]) { if (*i != y) upd(f[x], *i); } else d[*i] = d[x] + 1, ff(*i, x), upd(f[x], f[*i]); } void ff(int x) { f[x] = f[f[x]], v[x] = 0; for (set<int>::iterator i = A[x].begin(); i != A[x].end(); i++) if (v[*i]) ff(*i); } bool gg(int x, int y, int fa) { if (x == y) return 1; for (set<pair<int, int> >::iterator i = B[x].begin(); i != B[x].end(); i++) if (i->first != fa) if (gg(i->first, y, x)) { v[i->second] = v[i->second ^ 1] = 1; return 1; } return 0; } int main() { scanf( %d%d , &n, &m); A.resize(n); for (int i = 0, x, y; i < m; i++) scanf( %d%d , &x, &y), --x, --y, A[x].insert(y), A[y].insert(x); if (n == 2) { puts( -1 ); return 0; } d.resize(n, 0), f.resize(n), v.resize(n, 0); ff(0, -1), ff(0); F.resize(n); for (int i = 0; i < n; i++) if (f[i] == i) F[i] = (int)G.size(), G.push_back(i); for (int i = 0; i < n; i++) F[i] = F[f[i]]; B.resize((int)G.size()); for (int i = 0; i < n; i++) for (set<int>::iterator j = A[i].begin(); j != A[i].end(); j++) if (F[i] != F[*j]) { set<pair<int, int> >::iterator p = B[F[i]].lower_bound(make_pair(F[*j], -1)); if (p != B[F[i]].end() && p->first == F[*j]) continue; B[F[i]].insert(make_pair(F[*j], M++)), B[F[*j]].insert(make_pair(F[i], M++)); } if ((int)G.size() == 1) { puts( 0 ); return 0; } if ((int)G.size() == 2) { puts( 1 ); for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) if (F[i] != F[j] && A[i].find(j) == A[i].end()) { printf( %d %d n , i + 1, j + 1); return 0; } } vector<int> L; for (int i = 0; i < (int)G.size(); i++) if ((int)B[i].size() == 1) L.push_back(i); printf( %d n , ((int)L.size() + 1) / 2); while (1) { random_shuffle(L.begin(), L.end()); bool F = 0, FF = 1; if ((int)L.size() & 1) F = 1, L.push_back(L[0]); v.clear(), v.resize(M, 0); for (int i = 0; i < (int)L.size(); i += 2) gg(L[i], L[i + 1], -1); for (int i = 0; i < M; i++) if (!v[i]) { FF = 0; break; } if (FF) { for (int i = 0; i < (int)L.size(); i += 2) printf( %d %d n , G[L[i]] + 1, G[L[i + 1]] + 1); return 0; } if (F) L.erase(L.end() - 1); } return 0; } |
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_multistage_adder(clock, resetn, clear, enable, result, dataa, datab, add_sub);
// This module tessellates the accumulator into SECTION_SIZE-bit chunks.
parameter WIDTH = 32;
parameter SECTION_SIZE = 19;
input clock, resetn, clear, add_sub, enable;
input [WIDTH-1:0] dataa;
input [WIDTH-1:0] datab;
output [WIDTH-1:0] result;
wire [WIDTH-1:0] dataa_inter;
wire [WIDTH-1:0] datab_inter;
function integer stage_count;
input integer width;
input integer size;
integer temp,i;
begin
temp = width/size;
if ((width % size) > 0) temp = temp+1;
stage_count = temp;
end
endfunction
function integer mymax;
input integer a;
input integer b;
integer temp;
begin
if (a > b) temp = a; else temp = b;
mymax = temp;
end
endfunction
function integer mymin;
input integer a;
input integer b;
integer temp;
begin
if (a < b) temp = a; else temp = b;
mymin = temp;
end
endfunction
localparam TOTAL_STAGES = stage_count(WIDTH, SECTION_SIZE);
assign dataa_inter = dataa;
assign datab_inter = datab;
// This little trick is for modelsim to resolve its handling of generate statements.
// It prevents modelsim from thinking there is an out-of-bound access.
// This also simplifies one of the if statements below.
reg [TOTAL_STAGES-1 : -1] pipelined_add_sub;
reg [TOTAL_STAGES-1 : -1] pipelined_carry;
reg [WIDTH-1 : 0] pipelined_datab [TOTAL_STAGES-1 : -1];
reg [WIDTH-1 : 0] pipelined_result [TOTAL_STAGES-1 : -1];
genvar i;
generate
for (i = 0; i < TOTAL_STAGES; i = i + 1)
begin: add_sub_stage
always@(posedge clock or negedge resetn)
begin
if( ~resetn )
begin
pipelined_add_sub[i] <= 1'b0;
pipelined_datab[i] <= {{WIDTH}{1'b0}};
end
else if (enable)
begin
if( clear )
begin
pipelined_add_sub[i] <= 1'b0;
pipelined_datab[i] <= {{WIDTH}{1'b0}};
end
else
begin
if ( i == 0) begin
pipelined_add_sub[i] <= add_sub;
pipelined_datab[i] <= datab_inter;
end
else begin
pipelined_add_sub[i] <= pipelined_add_sub[i-1];
pipelined_datab[i] <= pipelined_datab[i-1];
end
end
end
end
always@(posedge clock or negedge resetn)
begin
if( ~resetn )
begin
pipelined_result[i] <= {{WIDTH}{1'b0}};
pipelined_carry[i] <= 1'b0;
end
else if (enable)
begin
if( clear )
begin
pipelined_result[i] <= {{WIDTH}{1'b0}};
pipelined_carry[i] <= 1'b0;
end
else
begin
if (i > 0)
begin
pipelined_result[i][mymax(SECTION_SIZE*i - 1,0):0] <= pipelined_result[i-1][mymax(SECTION_SIZE*i - 1,0):0];
end
if ( i == 0 ) begin
{pipelined_carry[i], pipelined_result[i][mymin(SECTION_SIZE*(i+1), WIDTH) - 1 : SECTION_SIZE*i]} <=
dataa_inter[mymin(SECTION_SIZE*(i+1), WIDTH) - 1 : SECTION_SIZE*i] +
(datab_inter[mymin(SECTION_SIZE*(i+1), WIDTH) - 1 : SECTION_SIZE*i] ^ {{SECTION_SIZE}{add_sub}})
+ add_sub;
if (SECTION_SIZE*(i+1) < WIDTH)
begin
pipelined_result[i][WIDTH-1: mymin(SECTION_SIZE*(i+1), WIDTH-1)] <= dataa_inter[WIDTH-1: mymin(SECTION_SIZE*(i+1), WIDTH-1)];
end
end else begin
{pipelined_carry[i], pipelined_result[i][mymin(SECTION_SIZE*(i+1), WIDTH) - 1 : SECTION_SIZE*i]} <=
pipelined_result[i-1][mymin(SECTION_SIZE*(i+1), WIDTH) - 1 : SECTION_SIZE*i] +
(pipelined_datab[i-1][mymin(SECTION_SIZE*(i+1), WIDTH) - 1 : SECTION_SIZE*i] ^ {{SECTION_SIZE}{pipelined_add_sub[i-1]}})
+ pipelined_carry[i-1];
if (SECTION_SIZE*(i+1) < WIDTH)
begin
pipelined_result[i][WIDTH-1: mymin(SECTION_SIZE*(i+1), WIDTH-1)] <= pipelined_result[i-1][WIDTH-1: mymin(SECTION_SIZE*(i+1), WIDTH-1)];
end
end
end
end
end
end
endgenerate
assign result = pipelined_result[TOTAL_STAGES-1];
endmodule
// vim:set filetype=verilog:
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_multiplier.v
// Title : Pipelined multiplier.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_multiplier (
// ----- Inputs -----
clk_i,
rst_i,
stall_x,
stall_m,
operand_0,
operand_1,
// ----- Ouputs -----
result
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input stall_m; // Stall instruction in M stage
input [`LM32_WORD_RNG] operand_0; // Muliplicand
input [`LM32_WORD_RNG] operand_1; // Multiplier
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result; // Product of multiplication
reg [`LM32_WORD_RNG] result;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_WORD_RNG] muliplicand;
reg [`LM32_WORD_RNG] multiplier;
reg [`LM32_WORD_RNG] product;
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
multiplier <= {`LM32_WORD_WIDTH{1'b0}};
product <= {`LM32_WORD_WIDTH{1'b0}};
result <= {`LM32_WORD_WIDTH{1'b0}};
end
else
begin
if (stall_x == `FALSE)
begin
muliplicand <= operand_0;
multiplier <= operand_1;
end
if (stall_m == `FALSE)
product <= muliplicand * multiplier;
result <= product;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5050; int n, b, c[MAXN], d[MAXN], fa[MAXN], sum[MAXN], f[MAXN][MAXN], g[MAXN][MAXN]; int buff[MAXN], bufg[MAXN]; int main() { memset(f, 63, sizeof(f)); memset(g, 63, sizeof(g)); scanf( %d%d , &n, &b); for (int i = 1; i <= n; i++) { scanf( %d%d , &c[i], &d[i]); if (i > 1) scanf( %d , &fa[i]); sum[i] = 1; f[i][1] = c[i] - d[i]; g[i][0] = 0; g[i][1] = c[i]; if (f[i][1] > b && g[i][1] > b) sum[i] = 0; } for (int i = n; i >= 2; i--) { memcpy(buff, f[fa[i]], sizeof(buff)); memcpy(bufg, g[fa[i]], sizeof(bufg)); for (int j = 0; j <= sum[i]; j++) for (int k = 0; k <= sum[fa[i]]; k++) { f[fa[i]][j + k] = min(f[fa[i]][j + k], min(f[i][j], g[i][j]) + buff[k]); g[fa[i]][j + k] = min(g[fa[i]][j + k], g[i][j] + bufg[k]); } sum[fa[i]] += sum[i]; } for (int i = n; i; --i) { if (f[1][i] <= b || g[1][i] <= b) { printf( %d , i); return 0; } } printf( 0 ); return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 10.1.03
// \ \ Application : xaw2verilog
// / / Filename : ADD_48_48.v
// /___/ /\ Timestamp : 06/27/2012 17:05:38
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle H:/Firmware_archive/Ben/stopped40MHz/FONT5_9Chan/ADD_48_48.xaw -st ADD_48_48.v
//Design Name: ADD_48_48
//Device: xc5vlx50t-3ff1136
//
// Module ADD_48_48
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module ADD_48_48(AB_IN,
CEA2_IN,
CEB2_IN,
CEMULTCARRYIN_IN,
CLK_IN,
C_IN,
P_OUT);
input [47:0] AB_IN;
input CEA2_IN;
input CEB2_IN;
input CEMULTCARRYIN_IN;
input CLK_IN;
input [47:0] C_IN;
output [47:0] P_OUT;
wire GND_ALUMODE;
wire [2:0] GND_BUS_3;
wire [17:0] GND_BUS_18;
wire [29:0] GND_BUS_30;
wire [47:0] GND_BUS_48;
wire GND_OPMODE;
wire VCC_OPMODE;
assign GND_ALUMODE = 0;
assign GND_BUS_3 = 3'b000;
assign GND_BUS_18 = 18'b000000000000000000;
assign GND_BUS_30 = 30'b000000000000000000000000000000;
assign GND_BUS_48 = 48'b000000000000000000000000000000000000000000000000;
assign GND_OPMODE = 0;
assign VCC_OPMODE = 1;
DSP48E DSP48E_INST (.A(AB_IN[47:18]),
.ACIN(GND_BUS_30[29:0]),
.ALUMODE({GND_ALUMODE, GND_ALUMODE, GND_ALUMODE,
GND_ALUMODE}),
.B(AB_IN[17:0]),
.BCIN(GND_BUS_18[17:0]),
.C(C_IN[47:0]),
.CARRYCASCIN(GND_ALUMODE),
.CARRYIN(GND_ALUMODE),
.CARRYINSEL(GND_BUS_3[2:0]),
.CEALUMODE(VCC_OPMODE),
.CEA1(VCC_OPMODE),
.CEA2(CEA2_IN),
.CEB1(VCC_OPMODE),
.CEB2(CEB2_IN),
.CEC(VCC_OPMODE),
.CECARRYIN(VCC_OPMODE),
.CECTRL(VCC_OPMODE),
.CEM(VCC_OPMODE),
.CEMULTCARRYIN(CEMULTCARRYIN_IN),
.CEP(VCC_OPMODE),
.CLK(CLK_IN),
.MULTSIGNIN(GND_ALUMODE),
.OPMODE({GND_OPMODE, VCC_OPMODE, VCC_OPMODE, GND_OPMODE,
GND_OPMODE, VCC_OPMODE, VCC_OPMODE}),
.PCIN(GND_BUS_48[47:0]),
.RSTA(GND_ALUMODE),
.RSTALLCARRYIN(GND_ALUMODE),
.RSTALUMODE(GND_ALUMODE),
.RSTB(GND_ALUMODE),
.RSTC(GND_ALUMODE),
.RSTCTRL(GND_ALUMODE),
.RSTM(GND_ALUMODE),
.RSTP(GND_ALUMODE),
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.CARRYOUT(),
.MULTSIGNOUT(),
.OVERFLOW(),
.P(P_OUT[47:0]),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.PCOUT(),
.UNDERFLOW());
defparam DSP48E_INST.ACASCREG = 1;
defparam DSP48E_INST.ALUMODEREG = 0;
defparam DSP48E_INST.AREG = 1;
defparam DSP48E_INST.AUTORESET_PATTERN_DETECT = "FALSE";
defparam DSP48E_INST.AUTORESET_PATTERN_DETECT_OPTINV = "MATCH";
defparam DSP48E_INST.A_INPUT = "DIRECT";
defparam DSP48E_INST.BCASCREG = 1;
defparam DSP48E_INST.BREG = 1;
defparam DSP48E_INST.B_INPUT = "DIRECT";
defparam DSP48E_INST.CARRYINREG = 0;
defparam DSP48E_INST.CARRYINSELREG = 0;
defparam DSP48E_INST.CREG = 1;
defparam DSP48E_INST.MASK = 48'h3FFFFFFFFFFF;
defparam DSP48E_INST.MREG = 1;
defparam DSP48E_INST.MULTCARRYINREG = 1;
defparam DSP48E_INST.OPMODEREG = 0;
defparam DSP48E_INST.PATTERN = 48'h000000000000;
defparam DSP48E_INST.PREG = 1;
defparam DSP48E_INST.SEL_MASK = "MASK";
defparam DSP48E_INST.SEL_PATTERN = "PATTERN";
defparam DSP48E_INST.SEL_ROUNDING_MASK = "SEL_MASK";
defparam DSP48E_INST.USE_MULT = "NONE";
defparam DSP48E_INST.USE_PATTERN_DETECT = "NO_PATDET";
defparam DSP48E_INST.USE_SIMD = "ONE48";
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mn = 55; const int mm = 2505; const int mod = 1000000007; int n, m, T; int t[mm], g[mm]; int a[mn][mm]; int bc[mn][mn][mm]; int way[mn][mn][mn][3]; int cnt[3]; void init_a() { memset(a, -2, sizeof a); a[0][0] = 1; for (int k = 1; k <= n; k++) { if (g[k]) continue; for (int i = cnt[0]; i >= 0; i--) { for (int j = T - t[k]; j >= 0; j--) { if (a[i][j] <= 0) continue; int &ans = a[i + 1][j + t[k]]; if (ans < 0) ans = 0; ans += a[i][j]; if (ans >= mod) ans -= mod; } } cnt[0]++; } } void init_bc() { memset(bc, -2, sizeof bc); bc[0][0][0] = 1; for (int k = 1; k <= n; k++) { if (!g[k]) continue; for (int i = cnt[1]; i >= 0; i--) { for (int j = cnt[2]; j >= 0; j--) { for (int l = T - t[k]; l >= 0; l--) { if (bc[i][j][l] <= 0) continue; int &ans = bc[i + (g[k] == 1)][j + (g[k] == 2)][l + t[k]]; if (ans < 0) ans = 0; ans += bc[i][j][l]; if (ans >= mod) ans -= mod; } } } if (g[k] == 1) cnt[1]++; else cnt[2]++; } } void inc(int &a, int b) { if (a < 0) a = 0; a += b; if (a >= mod) a -= mod; } void init_way() { memset(way, -2, sizeof(way)); way[1][0][0][0] = way[0][1][0][1] = way[0][0][1][2] = 1; for (int i = 0; i <= cnt[0]; i++) { for (int j = 0; j <= cnt[1]; j++) { for (int k = 0; k <= cnt[2]; k++) { for (int last = 0; last < 3; last++) { for (int nxt = 0; nxt < 3; nxt++) { if (nxt == last || way[i][j][k][last] <= 0) continue; int uans = way[i][j][k][last]; if (nxt == 0) inc(way[i + 1][j][k][0], uans); else if (nxt == 1) inc(way[i][j + 1][k][1], uans); else inc(way[i][j][k + 1][2], uans); } } } } } } inline int getway(int i, int j, int k) { int ans = 0; for (int last = 0; last < 3; last++) { if (way[i][j][k][last] <= 0) continue; inc(ans, way[i][j][k][last]); } return ans; } int fact[105]; int main() { scanf( %d%d , &n, &T); for (int i = 1; i <= n; i++) scanf( %d%d , &t[i], &g[i]), g[i]--; fact[0] = 1; for (int i = 1; i <= 55; i++) fact[i] = (long long)fact[i - 1] * i % mod; init_a(); init_bc(); init_way(); long long ans = 0; for (int i = 0; i <= cnt[0]; i++) { for (int j = 0; j <= cnt[1]; j++) { for (int k = 0; k <= cnt[2]; k++) { for (int t = 0; t <= T; t++) { if (a[i][t] <= 0 || bc[j][k][T - t] <= 0) continue; ans = (ans + (long long)a[i][t] * bc[j][k][T - t] % mod * getway(i, j, k) % mod * fact[i] % mod * fact[j] % mod * fact[k]) % mod; } } } } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_1_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_1_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv5sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkdlyinv5sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkdlyinv5sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_1_V
|
#include <bits/stdc++.h> using namespace std; int n; int A[101]; string s; long long d[101][101][101]; long long f(int lo, int hi, int p) { if (lo == hi) return A[p]; if (d[lo][hi][p]) return d[lo][hi][p]; long long ret = f(lo + 1, hi, 1) + A[p]; if (s[lo] == s[lo + 1]) ret = max(ret, f(lo + 1, hi, p + 1)); for (int i = lo + 2; i <= hi; i++) if (s[i] == s[lo]) ret = max(ret, f(lo + 1, i - 1, 1) + f(i, hi, p + 1)); return d[lo][hi][p] = ret; } int main() { cout << setprecision(10); ios::sync_with_stdio(0); cin.tie(0); cin >> n; cin >> s; s = # + s; for (int i = 1; i <= n; i++) cin >> A[i]; for (int i = 1; i <= n; i++) for (int k = 1; k < i; k++) A[i] = max(A[i], A[i - k] + A[k]); cout << f(1, n, 1) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; void rom(long long W) { long long pot = 1LL; char val[20] = IVXLCDM ; long long w = 0LL, z, i; while (pot <= W) { pot *= 10LL; w++; } pot /= 10LL; w--; while (pot) { z = W / pot; if (z == 4) printf( %c%c , val[w * 2], val[w * 2 + 1]); else if (z == 9) printf( %c%c , val[w * 2], val[w * 2 + 2]); else { if (z >= 5) { printf( %c , val[w * 2 + 1]); z -= 5; } for (i = 0; i < z; i++) printf( %c , val[w * 2]); } W -= W / pot * pot; pot /= 10LL; w--; } printf( n ); } void nice(long long W, long long B) { if (W == 0LL) cout << 0; long long pot = 1LL; char val[300]; int i, j; for (i = 0, j = 0 ; j <= 9 ; i++, j++) val[i] = j; for (j = A ; j <= Z ; i++, j++) val[i] = j; while (pot <= W) { pot *= B; } pot /= B; while (pot) { printf( %c , val[W / pot]); W -= (W / pot) * pot; pot /= B; } printf( n ); } int main() { long long a; char b[10000], c[10000]; long long w, pot, i, j; long long val[300]; memset(val, 0, sizeof(val)); for (i = 0 , j = 0; i <= 9 ; i++, j++) { val[i] = j; } for (i = A ; i <= Z ; i++, j++) { val[i] = j; } cin >> a; scanf( %s%s , b, c); w = 0LL; pot = 1LL; for (i = strlen(c) - 1; i >= 0; i--, pot *= a) { w += (val[c[i]]) * pot; } if (b[0] == R ) rom(w); else { int q; sscanf(b, %d , &q); nice(w, 0LL + q); } return 0; } |
#include <bits/stdc++.h> using namespace std; int c[4100]; int s[4100]; vector<long long> g; string str; int main() { long long a; cin >> a; cin >> str; int len = str.length(); for (int i = 0; str[i]; i++) c[i + 1] = str[i] - 0 ; for (int i = 1; i <= len; i++) { s[i] = s[i - 1] + (long long)c[i]; } for (int i = 0; i <= len; i++) for (int j = i + 1; j <= len; j++) g.push_back(s[j] - s[i]); sort(g.begin(), g.end()); int sz = g.size(), sz1; sz1 = upper_bound(g.begin(), g.end(), 0) - lower_bound(g.begin(), g.end(), 0); long long ans = 0; for (int i = 0; i < sz; i++) { if (g[i] == 0) { if (a == 0) ans += sz; continue; } if (a % g[i] == 0 && *lower_bound(g.begin(), g.end(), a / g[i]) == a / g[i]) { if (a == 0) { ans += sz1; continue; } ans += upper_bound(g.begin(), g.end(), a / g[i]) - lower_bound(g.begin(), g.end(), a / g[i]); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q, A[1005], B[1005], x, y; int main() { scanf( %d %d , &n, &q); for (int i = 1; i <= q; i++) { scanf( %d %d , &x, &y); A[x] = 1; B[y] = 1; } int cev = 0; for (int i = 2; i < n; i++) { cev += !A[i] + !B[i]; } if (n % 2 == 1 && A[n / 2 + 1] == 0 && B[n / 2 + 1] == 0) cev--; printf( %d n , cev); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111OI_0_V
`define SKY130_FD_SC_HD__A2111OI_0_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111oi_0 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111OI_0_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_THRESHA (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 6: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 6: 0] data_out;
wire [ 6: 0] out_port;
wire [ 6: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {7 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[6 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
module ghrd_10as066n2_led_pio_altera_avalon_pio_171_yz2rppa (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 3: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire [ 3: 0] data_in;
reg [ 3: 0] data_out;
wire [ 3: 0] out_port;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign out_port = data_out;
assign data_in = in_port;
endmodule
|
module peripheral_audio(clk , rst , d_in , cs,wr,rd , addr, d_out, mclk, ledres, micLRSel,micData );
input clk;
input rst;
input [15:0] d_in;
input cs;
input wr;
input rd;
input [3:0]addr; // 4 LSB from j1_io_addr
output reg [15:0]d_out;
output ledres;
output mclk;
output micLRSel;
input micData;
wire doutmic;
wire full;
wire empty;
reg enable;
//------------------------------------ regs and wires-------------------------------
reg [2:0] s; //selector mux_4 and demux_4
//------------------------------------ regs and wires-------------------------------
microfono mic(.reset(rst),.clk(clk),.micLRSel(micLRSel),.empty(empty),.mclk(mclk),.micData(micData),.ledres(ledres),.enable(enable),.full(full));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 3'b001 : 3'b000 ;end //enable
4'h2:begin s = (cs && rd) ? 3'b010 : 3'b000 ;end //full
4'h4:begin s = (cs && rd) ? 3'b100 : 3'b000 ;end //empty
4'h8:begin s = (cs && rd) ? 3'b111 : 3'b000 ;end //dout
default:begin s=3'b000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1) begin
enable=1;
end
else begin
enable=0;
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b010: d_out[0]= full;
3'b100: d_out[0]= empty;
3'b111: d_out[0]= dout;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Peter Monsson.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
wire gain = 1'b0;
real in;
always_comb in = (cyc-4) * 1.0;
wire cmp;
adc_netlist netlist(.clk, .in, .gain, .cmp);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
$display("cyc=%0d cmp=%d", cyc, cmp);
if (cyc == 3) begin
if (cmp != 0) $stop;
end
else if (cyc == 4) begin
if (cmp != 1) $stop;
end
else if (cyc == 5) begin
if (cmp != 0) $stop;
end
else if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module adc_netlist(clk, in, gain, cmp);
input clk;
input real in;
input gain;
output cmp;
wire pga_out; //TODO: convert to real or support real
pga_model pga0(.in, .gain, .out(pga_out));
comparator_model cmp0(.clk, .in(pga_out), .cmp);
endmodule
module pga_model(in, gain, out);
input real in;
input gain;
output real out;
always_comb begin
out = in * 3.0;
end
endmodule
module comparator_model(clk, in, cmp);
input clk;
input real in;
output logic cmp;
always_ff @(posedge clk) begin
cmp <= in > 0.0;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dll_img_ram (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [15 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("dll_img_ram.mif"),
.C_INIT_FILE("dll_img_ram.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(65536),
.C_READ_DEPTH_A(65536),
.C_ADDRA_WIDTH(16),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(65536),
.C_READ_DEPTH_B(65536),
.C_ADDRB_WIDTH(16),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("NONE"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(1),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_COUNT_36K_BRAM("16"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 16.114201 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(16'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dir_in.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_dir_in(/*AUTOARG*/
// Outputs
lkup_wr_data_c5, rddata_out_c6, so,
// Inputs
lkup_wr_data_c4, rd_data1_out_c5, rd_data2_out_c5, rd_enable1_c5,
rclk, si, se, sehold
);
output [32:0] lkup_wr_data_c5; // Top 3 bits per bit pitch
output [31:0] rddata_out_c6;
output so;
input [32:0] lkup_wr_data_c4;
input [31:0] rd_data1_out_c5; // TOp 3 bits per bit pitch
input [31:0] rd_data2_out_c5; // Down 3 bits per bit pitch
input rd_enable1_c5; // Right
input rclk;
input si, se;
input sehold;
wire [31:0] rddata_out_c5;
wire clk_en;
// USE A MUX2 FLOP to replace sehold_mux & ff_lkup_wr_data_c5
//mux2ds #(33) sehold_mux(.dout (lkup_wr_data_c4_in[32:0]) ,
//.in0(lkup_wr_data_c5[32:0]), .in1(lkup_wr_data_c4[32:0]),
//.sel0(sehold), .sel1(~sehold));
clken_buf clk_buf (.clk(clk_en), .rclk(rclk), .enb_l(sehold), .tmb_l(~se));
// bits {0,1,2 } {3,4,5}.... occupy the same bit pitches
dff_s #(33) ff_lkup_wr_data_c5 // Use an 8X flop. no buffer following the flop.
(.q (lkup_wr_data_c5[32:0]),
.din (lkup_wr_data_c4[32:0]),
.clk (clk_en),
.se (se), .si (), .so ()
) ;
// bits {0,1,2 } {3,4,5}.... occupy the same bit pitches
mux2ds #(32) mux_rddata_out_c5(.dout (rddata_out_c5[31:0]) ,
.in0(rd_data1_out_c5[31:0]), .in1(rd_data2_out_c5[31:0]),
.sel0(rd_enable1_c5), .sel1(~rd_enable1_c5));
dff_s #(32) ff_rddata_out_c6 // Use an 16X buffer following a 1X mx flop.
(.q (rddata_out_c6[31:0]),
.din (rddata_out_c5[31:0]),
.clk (rclk),
.se (se), .si (), .so ()
) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[150000]; int find(int x) { if (x == f[x]) return f[x]; else { return f[x] = find(f[x]); } } int a[150000]; int num[150000]; int main() { ios::sync_with_stdio(false); int n, m; while (cin >> n >> m) { memset(a, 0, sizeof(a)); memset(num, 0, sizeof(num)); for (int i = 1; i <= n; i++) f[i] = i; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; a[x]++; a[y]++; x = find(x), y = find(y); if (x != y) f[x] = y; } for (int i = 1; i <= n; i++) { find(i); } for (int i = 1; i <= n; i++) { num[f[i]]++; } bool flag = true; for (int i = 1; i <= n; i++) { if (a[i] != num[f[i]] - 1) { flag = false; break; } } if (flag) cout << YES << endl; else cout << NO << endl; } return 0; } |
//----------------------------------------------------------------------------
//-- Ejemplo que saca una secuencia en los leds, usando una memoria
//-- rom de 16x4
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "divider.vh"
module romleds (input wire clk,
output wire [3:0] leds);
//- Tiempo de envio
parameter DELAY = `T_500ms; //`T_1s;
reg [3:0] addr;
reg rstn = 0;
wire clk_delay;
//-- Instanciar la memoria rom
rom16x4
ROM (
.clk(clk),
.addr(addr),
.data(leds)
);
//-- Contador
always @(negedge clk)
if (rstn == 0)
addr <= 0;
else if (clk_delay)
addr <= addr + 1;
//---------------------------
//-- Temporizador
//---------------------------
dividerp1 #(.M(DELAY))
DIV0 ( .clk(clk),
.clk_out(clk_delay)
);
//-- Inicializador
always @(negedge clk)
rstn <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); int i, j, n, m, k, l, r; cin >> n >> m; int a[n][m]; pair<int, int> start_end[n][m]; for (i = 0; i < n; i += 1) for (j = 0; j < m; j += 1) { cin >> a[i][j]; start_end[i][j].first = i; start_end[i][j].second = i; } for (j = 0; j < m; j += 1) for (i = 1; i < n; i += 1) if (a[i][j] >= a[i - 1][j]) start_end[i][j].first = start_end[i - 1][j].first; int min_l[n]; for (i = 0; i < n; i++) min_l[i] = 100010; for (i = 0; i < n; i += 1) for (j = 0; j < m; j += 1) if (start_end[i][j].first < min_l[i]) min_l[i] = start_end[i][j].first; cin >> k; while (k--) { cin >> l >> r; cout << ((min_l[r - 1] <= l - 1) ? Yes n : No n ); } return 0; } |
#include <bits/stdc++.h> char s[128]; bool ce(char r, char a, char b, char c) { return r == a || r == b || r == c; } bool spcmp(char a, char b, char c) { return ce( A , a, b, c) && ce( B , a, b, c) && ce( C , a, b, c); } int main() { int n, i; scanf( %s , s); for (i = 1; s[i + 1] != 0 ; i++) { if (spcmp(s[i - 1], s[i], s[i + 1])) { printf( Yes n ); return 0; } } printf( No n ); return 0; } |
#include <bits/stdc++.h> using namespace std; pair<long long, long long> add_pair(pair<long long, long long> a, pair<long long, long long> b) { return make_pair(a.first + b.first, a.second + b.second); } long long power(long long a, long long b) { long long res = 1; a = a % ((long long)1e9 + 7); while (b > 0) { if (b & 1) { res = (res * a) % ((long long)1e9 + 7); b--; } a = (a * a) % ((long long)1e9 + 7); b >>= 1; } return res; } long long fermat_inv(long long y) { return power(y, ((long long)1e9 + 7) - 2); } long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } long long mul(long long a, long long b) { return (a * (b % ((long long)1e9 + 7))) % ((long long)1e9 + 7); } long long sub(long long a, long long b) { return ((a - b) % ((long long)1e9 + 7) + ((long long)1e9 + 7)) % ((long long)1e9 + 7); } long long add(long long a, long long b) { return ((a + b) % ((long long)1e9 + 7) + ((long long)1e9 + 7)) % ((long long)1e9 + 7); } vector<vector<long long> > G; map<long long, long long> m[100005]; vector<long long> b; long long ans; void dfs(long long rt, long long par) { m[rt][b[rt]]++; if (rt != par) { for (auto it = (m[par]).begin(); it != (m[par]).end(); it++) { m[rt][gcd(b[rt], it->first)] += it->second; } } for (auto it = (m[rt]).begin(); it != (m[rt]).end(); it++) { ans = add(ans, mul(it->first, it->second)); } for (auto it = (G[rt]).begin(); it != (G[rt]).end(); it++) { if (*it != par) { dfs(*it, rt); } } } void solve() { long long n, u, v, i; cin >> n; G = vector<vector<long long> >(n + 1, vector<long long>()); b = vector<long long>(n + 1); for (i = (0); i < (n); i += (1)) cin >> b[i + 1]; for (i = (0); i < (n - 1); i += (1)) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } ans = 0; dfs(1, 1); cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { solve(); } return 0; } |
/*
* PS2 Mouse without FIFO buffer
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_nofifo (
input clk,
input reset,
input [7:0] writedata, // data to send
input write, // signal to send it
input inhibit,
output [7:0] readdata, // data read
output irq, // signal data has arrived
output command_was_sent,
output error_sending_command,
output buffer_overrun_error,
inout ps2_clk,
inout ps2_dat
);
// Unused outputs
wire start_receiving_data;
wire wait_for_incoming_data;
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse mouse (
.clk (clk),
.reset (reset),
.the_command (writedata),
.send_command (write),
.received_data (readdata),
.received_data_en (irq),
.inhibit (inhibit),
.command_was_sent (command_was_sent),
.error_communication_timed_out (error_sending_command),
.start_receiving_data (start_receiving_data),
.wait_for_incoming_data (wait_for_incoming_data),
.ps2_clk (ps2_clk),
.ps2_dat (ps2_dat)
);
// Continous assignments
assign buffer_overrun_error = error_sending_command;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ab(long long x) { return x > 0LL ? x : -x; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k, sum = 0, x; cin >> n >> k; vector<long long> v; for (long long i = 0; i < n; i++) { cin >> x; sum += x; v.push_back(x); } long long ans = -1; for (long long i = 0; i < k; i++) { long long sum2 = 0; for (long long j = i; j < n; j += k) sum2 += v[j]; ans = max(ans, ab(sum - sum2)); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000000 + 7; int main() { long long a, b; cin >> a >> b; long long ans = 0; for (long long r = 1; r < b; ++r) { long long tmp = (a * (a + 1) / 2) % mod; tmp = (tmp * r) % mod; tmp = (tmp * b) % mod; tmp = (tmp + (a * r) % mod) % mod; ans = (ans + tmp) % mod; } if (ans < 0) ans += mod; cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; float sum = 0; cin >> n; int k[n], count = 0; float a[n]; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) sum += a[i]; for (int i = 1; i <= n; i++) { if ((sum - a[i]) / (n - 1) == a[i]) { count++; k[count] = i; } } if (count > 0) { cout << count << endl; for (long long int i = 1; i <= count; i++) cout << k[i] << ; } else cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int f, a, b; scanf( %d , &f); scanf( %d:%d , &a, &b); if (b > 59) b %= 10; if (a > f or a == 24) a %= 10; if (a == 0 and f == 12) a = 10; printf( %02d:%02d , a, b); } |
module alt_vipitc131_common_sync_generation(
input wire rst,
input wire clk,
input wire clear_enable,
input wire enable_count,
input wire hd_sdn,
input wire start_of_vsync,
input wire field_prediction,
input wire interlaced,
input wire [13:0] total_sample_count,
input wire total_sample_count_valid,
input wire [12:0] total_line_count,
input wire total_line_count_valid,
input wire stable,
input wire [13:0] divider_value,
input wire [13:0] sof_sample,
input wire [12:0] sof_line,
input wire [1:0] sof_subsample,
input wire output_enable,
output reg sof,
output reg sof_locked,
output wire div);
parameter NUMBER_OF_COLOUR_PLANES = 0;
parameter COLOUR_PLANES_ARE_IN_PARALLEL = 0;
parameter LOG2_NUMBER_OF_COLOUR_PLANES = 0;
parameter CONVERT_SEQ_TO_PAR = 0;
parameter TOTALS_MINUS_ONE = 0;
wire enable_next;
reg enable_reg;
wire enable;
wire sof_next;
reg sclr;
wire [LOG2_NUMBER_OF_COLOUR_PLANES-1:0] sample_ticks;
wire [13:0] h_count;
wire [12:0] v_count;
wire div_next;
wire count;
wire count_div;
wire sof_subsample_next;
reg first_sof;
reg div_reg;
reg [3:0] sof_count;
wire start_of_vsync_f0;
assign enable_next = stable & total_sample_count_valid;
assign start_of_vsync_f0 = start_of_vsync & ~field_prediction;
assign enable = (start_of_vsync_f0) ? enable_next : enable_next & enable_reg & ~clear_enable;
assign count = enable & enable_count;
assign count_div = count & first_sof;
assign sof_subsample_next = (sample_ticks == sof_subsample[LOG2_NUMBER_OF_COLOUR_PLANES-1:0]) | hd_sdn;
assign sof_next = (count && sof_subsample_next && h_count == sof_sample && v_count == sof_line) ? 1'b1 : 1'b0;
assign div = div_reg;
always @ (posedge rst or posedge clk) begin
if(rst) begin
enable_reg <= 1'b0;
sof_count <= 4'd0;
sof <= 1'b0;
sof_locked <= 1'b0;
div_reg <= 1'b0;
sclr <= 1'b0;
first_sof <= 1'b0;
end else begin
enable_reg <= enable;
if(output_enable) begin
if(sof_count == 4'd0) begin
sof <= sof_next;
if(sof_next)
sof_count = 4'b1111;
end else begin
sof_count = sof_count - 4'd1;
end
sof_locked <= enable & total_line_count_valid;
div_reg <= div_next;
sclr <= sof_next;
first_sof <= enable & (sof_next | first_sof);
end else begin
sof <= 1'b0;
sof_locked <= 1'b0;
div_reg <= 1'b0;
sclr <= 1'b0;
first_sof <= 1'b0;
end
end
end
alt_vipitc131_common_frame_counter frame_counter(
.rst(rst),
.clk(clk),
.sclr(start_of_vsync_f0),
.enable(count),
.hd_sdn(hd_sdn),
.h_total(total_sample_count),
.v_total(total_line_count),
.h_reset(14'd0),
.v_reset(13'd0),
.sample_ticks(sample_ticks),
.h_count(h_count),
.v_count(v_count));
defparam frame_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
frame_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
frame_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES,
frame_counter.CONVERT_SEQ_TO_PAR = CONVERT_SEQ_TO_PAR,
frame_counter.TOTALS_MINUS_ONE = TOTALS_MINUS_ONE;
alt_vipitc131_common_frame_counter divider_counter(
.rst(rst),
.clk(clk),
.sclr(sclr),
.enable(count_div),
.hd_sdn(hd_sdn),
.h_total(divider_value),
.v_total(13'd0),
.h_reset(14'd0),
.v_reset(13'd0),
.new_line(div_next));
defparam divider_counter.NUMBER_OF_COLOUR_PLANES = NUMBER_OF_COLOUR_PLANES,
divider_counter.COLOUR_PLANES_ARE_IN_PARALLEL = COLOUR_PLANES_ARE_IN_PARALLEL,
divider_counter.LOG2_NUMBER_OF_COLOUR_PLANES = LOG2_NUMBER_OF_COLOUR_PLANES,
divider_counter.CONVERT_SEQ_TO_PAR = CONVERT_SEQ_TO_PAR,
divider_counter.TOTALS_MINUS_ONE = 1;
endmodule
|
`define ADDER_WIDTH 015
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
#include <bits/stdc++.h> using namespace std; pair<long long, long long> a[5]; long long k; int main() { for (long long i = 1, _b = (2); i <= _b; i++) cin >> a[i].first >> a[i].second; cin >> k; sort(a + 1, a + 2 + 1); if (a[1].second < a[2].first) return cout << 0, 0; long long res = min(a[2].second, a[1].second) - a[2].first + 1; if (k >= a[2].first && k <= min(a[1].second, a[2].second)) res--; cout << res; } |
#include <bits/stdc++.h> using namespace std; vector<int> V; void initSet(int _size) { V.resize(_size); for (int i = int(0); i <= int(_size - 1); i++) V[i] = i; } int findSet(int i) { return (V[i] == i) ? i : (V[i] = findSet(V[i])); } void unionSet(int i, int j) { V[findSet(i)] = findSet(j); } bool isSameSet(int i, int j) { return findSet(i) == findSet(j); } long long a, b, s, N, M, A, B, r[123450]; int find(int node) { if (r[node]) return r[node] = find(r[node]); return node; } int main() { int N = 0; cin >> N >> M; s = 1; for (int i = 1; i <= M; ++i) { cin >> a >> b; A = find(a); B = find(b); if (A == B) { s = s * 2 % 1000000009; } else { r[B] = A; } if (s > 0) cout << s - 1 << endl; else cout << 1000000009 - 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1E9 + 7; const long long N = 2E5 + 6; long long n, m, a[N], b[N], ans, zeros[N]; long long dp[N]; long long modexp(long long b, long long e) { long long res = 1; while (e) { if (e & 1) res = (res * b) % MOD; e >>= 1; b = (b * b) % MOD; } return res; } long long recur(long long ind) { if (dp[ind] != -1) return dp[ind]; if (ind == n + 1) { dp[ind] = 0; return 0; } long long ans = 0; if (a[ind] == 0 && b[ind] != 0) { ans = (m - b[ind] + MOD) % MOD; ans = (ans * modexp(m, zeros[ind + 1]) % MOD) % MOD; ans = (ans + recur(ind + 1)) % MOD; } else if (a[ind] != 0 && b[ind] == 0) { ans = (a[ind] - 1 + MOD) % MOD; ans = (ans * modexp(m, zeros[ind + 1]) % MOD) % MOD; ans = (ans + recur(ind + 1)) % MOD; } else if (a[ind] == 0 && b[ind] == 0) { ans = ((m * (m - 1)) % MOD * 500000004LL) % MOD; ans = (ans * modexp(m, zeros[ind + 1])) % MOD; ans = (ans + (m * recur(ind + 1)) % MOD) % MOD; } else { if (a[ind] > b[ind]) { ans = modexp(m, zeros[ind + 1]) % MOD; } else if (a[ind] == b[ind]) ans = recur(ind + 1) % MOD; } dp[ind] = ans; return ans; } long long modinv(long long x) { return modexp(x, MOD - 2); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); if (fopen( inp.txt , r )) { freopen( inp.txt , r , stdin); freopen( outp.txt , w , stdout); } cin >> n >> m; long long i; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) cin >> b[i]; memset(dp, -1, sizeof(dp)); zeros[n + 1] = 0; zeros[n] = (b[n] == 0) + (a[n] == 0); for (i = n - 1; i >= 1; i--) zeros[i] = zeros[i + 1] + (a[i] == 0) + (b[i] == 0); long long total = modexp(m, zeros[1]); cout << (recur(1) * modinv(total)) % MOD << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; string grid[60]; int main() { cin.tie(0); ios::sync_with_stdio(0); int t; cin >> t; int r, c; while (t--) { cin >> r >> c; for (int i = 0; i < r; i++) cin >> grid[i]; bool quina = false, borda = false, meio = false, all = true, tdb1 = true, tdb2 = true, tdb3 = true, tdb4 = true, tdm1 = false, tdm2 = false; for (int i = 0; i < r; i++) { bool at = true; for (int j = 0; j < c; j++) { if (grid[i][j] == A ) { if ((i == 0 && j == 0) || (i == 0 && j == c - 1) || (i == r - 1 && j == 0) || (i == r - 1 && j == c - 1)) quina = true; else if (i == 0 || j == c - 1 || i == r - 1 || j == 0) borda = true; else meio = true; } else { all = false; at = false; } } tdm1 = tdm1 || at; } for (int i = 0; i < c; i++) { bool at = true; for (int j = 0; j < r; j++) { if (grid[j][i] == P ) { at = false; } } tdm2 = tdm2 || at; } for (int i = 0; i < r; i++) { if (grid[i][0] == P ) tdb1 = false; } for (int i = 0; i < r; i++) { if (grid[i][c - 1] == P ) tdb2 = false; } for (int i = 0; i < c; i++) { if (grid[0][i] == P ) tdb3 = false; } for (int i = 0; i < c; i++) { if (grid[r - 1][i] == P ) tdb4 = false; } if (all) cout << 0 << endl; else if (tdb1 || tdb2 || tdb3 || tdb4) cout << 1 << endl; else if (quina || tdm1 || tdm2) cout << 2 << endl; else if (borda) cout << 3 << endl; else if (meio) cout << 4 << endl; else cout << MORTAL << endl; } } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 4010; double num1[Maxn]; int num2[Maxn]; double dif[Maxn]; int main() { int n = 0, N = 0; int cnt = 0, cnt1 = 0, cnt2 = 0; double sum = 0; double ans = 100000000.0; scanf( %d , &n); N = 2 * n; for (int i = 0; i < N; i++) { scanf( %lf , &num1[i]); num2[i] = num1[i]; dif[i] = (double)num1[i] - (double)num2[i]; } for (int i = 0; i < N; i++) { if (dif[i] != 0) { cnt1++; sum += dif[i]; } else { cnt2++; } } cnt = min(cnt1, n); for (int i = 0; i <= cnt; i++) { if (i + cnt2 >= n) { ans = min(ans, fabs(sum - i * 1.0)); } } printf( %.3f , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); cin.sync_with_stdio(0); long long n, a[5001], cnt = 1, maxn = 0; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (int i = 0; i < n - 1; i++) { if (a[i] == a[i + 1]) cnt++; if (a[i] != a[i + 1]) cnt = 1; maxn = max(maxn, cnt); } maxn = max(maxn, cnt); cout << maxn; return 0; } |
#include <bits/stdc++.h> using namespace std; int p[2010]; int main(void) { int N, ans = 0, i, j; cin >> N; for ((i) = 0; (i) < (int)(N); (i)++) cin >> p[i]; for ((i) = 0; (i) < (int)(N); (i)++) if (p[i] < 0) p[i] = -p[i]; for ((i) = 0; (i) < (int)(N); (i)++) { int a = 0, b = 0; for ((j) = 0; (j) < (int)(N); (j)++) if (p[j] < p[i]) { if (j < i) a++; if (j > i) b++; } ans += min(a, b); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[100000]; for (int i = 0; i < n; i++) cin >> a[i]; long long ans = 0; for (int i = 0; i < n - 1; i++) { int j = 1; while (i + j * 2 < n) j *= 2; ans += a[i]; a[i + j] += a[i]; cout << ans << endl; } return 0; } |
module meio_somador2 ( a, b, soma, cout);
input a, b;
output soma, cout;
assign soma = a ^ b;
assign cout = a * b;
endmodule
module meio_somador3 ( a, b, c, soma, cout);
input a, b, c;
output soma, cout;
wire carry_1, carry_2, soma_1;
meio_somador2 m1 ( a, b, soma_1, carry_1);
meio_somador2 m2 (soma_1, c, soma, carry_2);
or o (cout, carry_1, carry_2);
endmodule
module somador_4_bits (a1, a2, b1, b2, c1, c2, d1, d2, soma1, soma2, soma3, soma4, cout);
input a1, a2, b1, b2, c1, c2, d1, d2;
output soma1, soma2, soma3, soma4, cout;
wire carry_1, carry_2, carry_3;
meio_somador2 s1 ( a1, a2, soma1, carry_1);
meio_somador3 s2 ( b1, b2, carry_1, soma2, carry_2);
meio_somador3 s3 ( c1, c2, carry_2, soma3, carry_3);
meio_somador3 s4 ( d1, d2, carry_3, soma4, cout);
endmodule
module separa ( A, B, C, D, E, z0, z1, z2, z3, z4);
input A, B, C, D, E;
output z0, z1, z2, z3, z4;
assign z0 = (~A&E) | (~B&~C&~D&E);
assign z1 = (~A&~B&D) | (~A&B&C&~D) | (A&~B&~C&~D);
assign z2 = (~A&~B&C) | (~A&C&D) | (A&~B&~C&~D);
assign z3 = (~A&B&~C&~D) | (A&~B&~C&D&~E);
assign z4 = (~A&B&D) | (~A&B&C) | (A&~B&~C&~D) | (A&~B&~C&~E);
endmodule
module decodificacao ( A, B, C, D, h0, h1, h2, h3, h4, h5, h6);
input A, B, C, D;
output h0, h1, h2, h3, h4, h5, h6;
assign h0 = (~A&~B&~C&D) | (~A&B&~C&~D);
assign h1 = (~A&B&~C&D) | (~A&B&C&~D);
assign h2 = ~A&~B&C&~D;
assign h3 = (~A&B&~C&~D) | (~A&~B&~C&D) | (~A&B&C&D);
assign h4 = (~A&D) | (~A&B&~C) | (~B&~C&D);
assign h5 = (~A&~B&D) | (~A&C&D) | (~A&~B&C);
assign h6 = (~A&~B&~C) | (~A&B&C&D);
endmodule
module projeto (SW, HEX0, HEX1);
input [7:0]SW;
output [6:0] HEX0,HEX1;
wire z0, z1, z2, z3, z4, z5, z6, z7;
wire s1, s2, s3, s4, cout;
somador_4_bits soma ( SW[0], SW[4], SW[1], SW[5], SW[2], SW[6], SW[3], SW[7], s1, s2, s3, s4, cout);
separa s (cout, s4, s3, s2, s1, z0, z1, z2, z3, z4);
assign z5 = 0;
assign z6 = 0;
assign z7 = 0;
decodificacao dec1 ( z3, z2, z1, z0, HEX0[0], HEX0[1], HEX0[2], HEX0[3], HEX0[4], HEX0[5], HEX0[6]);
decodificacao dec2 ( 0, 0, 0, z4, HEX1[0], HEX1[1], HEX1[2], HEX1[3], HEX1[4], HEX1[5], HEX1[6]);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: reading.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module reading (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/reading.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/reading.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMIn
/// module function:because there are three kinds of uploadregs to
/// OUT_req: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_req.
module arbiter_for_OUT_req(//input
clk,
rst,
OUT_req_rdy,
v_ic_req,
v_dc_req,
v_mem_req,
ic_req_ctrl,
dc_req_ctrl,
mem_req_ctrl,
//output
ack_OUT_req,
ack_ic_req,
ack_dc_req,
ack_mem_req,
select
);
//input
input clk;
input rst;
input OUT_req_rdy;
input v_ic_req;
input v_dc_req;
input v_mem_req;
input [1:0] ic_req_ctrl;
input [1:0] dc_req_ctrl;
input [1:0] mem_req_ctrl;
//output
output ack_OUT_req;
output ack_ic_req;
output ack_dc_req;
output ack_mem_req;
output [2:0] select; // select 1/3
/// parameter for fsm state
parameter arbiter_idle=4'b0001;
parameter ic_uploading=4'b0010;
parameter dc_uploading=4'b0100;
parameter mem_uploading=4'b1000;
reg [3:0] nstate;
reg [3:0] state;
reg [1:0] priority_2;
reg ack_ic_req;
reg ack_dc_req;
reg ack_mem_req;
reg [2:0] select;
reg ack_OUT_req;
reg update_priority;
wire [2:0] arbiter_vector;
assign arbiter_vector={v_ic_req,v_dc_req,v_mem_req};
// next state and output function
always@(*)
begin
ack_ic_req=1'b0;
ack_dc_req=1'b0;
ack_mem_req=1'b0;
select=3'b000;
ack_OUT_req=1'b0;
nstate=state;
update_priority=1'b0;
case(state)
arbiter_idle:
begin
if(OUT_req_rdy)
begin
if(arbiter_vector[2]==1'b1)
begin
ack_ic_req=1'b1;
select=3'b100;
nstate=ic_uploading;
ack_OUT_req=1'b1;
end
else
begin
if(arbiter_vector[1:0]==2'b11)
begin
update_priority=1'b1;
begin
if(priority_2[1]==1'b1)
begin
ack_dc_req=1'b1;
select=3'b010;
nstate=dc_uploading;
ack_OUT_req=1'b1;
end
else
begin
ack_mem_req=1'b1;
select=3'b001;
nstate=mem_uploading;
ack_OUT_req=1'b1;
end
end
end
else if(arbiter_vector[1:0]==2'b10)
begin
ack_dc_req=1'b1;
select=3'b010;
nstate=dc_uploading;
ack_OUT_req=1'b1;
end
else if(arbiter_vector[1:0]==2'b01)
begin
ack_mem_req=1'b1;
select=3'b001;
nstate=mem_uploading;
ack_OUT_req=1'b1;
end
end
end
end
ic_uploading:
begin
if(OUT_req_rdy)
begin
if(ic_req_ctrl==2'b11)
nstate=arbiter_idle;
ack_ic_req=1'b1;
select=3'b100;
ack_OUT_req=1'b1;
end
end
dc_uploading:
begin
if(OUT_req_rdy)
begin
if(dc_req_ctrl==2'b11)
nstate=arbiter_idle;
ack_dc_req=1'b1;
select=3'b010;
ack_OUT_req=1'b1;
end
end
mem_uploading:
begin
if(OUT_req_rdy)
begin
if(mem_req_ctrl==2'b11)
nstate=arbiter_idle;
ack_mem_req=1'b1;
select=3'b001;
ack_OUT_req=1'b1;
end
end
endcase
end
/// fsm reg
always@(posedge clk)
begin
if(rst)
state<=4'b0001;
else
state<=nstate;
end
// reg for priority_2
always@(posedge clk)
begin
if(rst)
priority_2<=2'b01;
else if(update_priority)
priority_2<={priority_2[0],priority_2[1]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[300005]; int n, x, y; void resi(int x, int y, bool naopako) { int z = 0, j = -1, k = -1, c = 0; for (int i = 1; i <= n; i++) { z = a[i].first; c++; if (j == -1 && z * c >= x) { j = i; z = c = 0; } if (j != -1 && k == -1 && z * c >= y) { k = i; break; } } if (k != -1) { cout << Yes n ; if (!naopako) { cout << j << << k - j << n ; for (int i = 1; i <= j; i++) { cout << a[i].second << ; } cout << n ; for (int i = j + 1; i <= k; i++) { cout << a[i].second << ; } cout << n ; } else { cerr << naopako! n ; cout << k - j << << j << n ; for (int i = j + 1; i <= k; i++) { cout << a[i].second << ; } cout << n ; for (int i = 1; i <= j; i++) { cout << a[i].second << ; } cout << n ; } exit(0); } } void solve() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n >> x >> y; for (int i = 1; i <= n; i++) { cin >> a[i].first; a[i].second = i; } sort(a + 1, a + n + 1); reverse(a + 1, a + n + 1); resi(x, y, false); resi(y, x, true); cout << No n ; } int main() { solve(); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 555; int n, m; int a[maxn], b[maxn]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= m; i++) scanf( %d , b + i); int i1 = 1, i2 = 1; int res = 0; while (i1 <= n && i2 <= m) { if (a[i1] <= b[i2]) i1++, i2++, res++; else i1++; } printf( %d n , res); return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_memtest();
parameter fml_depth = 26;
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
wire [fml_depth-1:0] fml_adr;
wire fml_we;
wire fml_stb;
reg fml_ack;
reg [63:0] fml_di;
wire [63:0] fml_do;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
memtest #(
.fml_depth(fml_depth),
.csr_addr(4'h0)
) dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_we(fml_we),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x (%d)", address, csr_do, csr_do);
end
endtask
parameter memsize = 32*1024*1024;
reg [63:0] mem[0:memsize-1];
integer burstcount;
integer addr;
integer we;
initial burstcount = 0;
always @(posedge sys_clk) begin
fml_ack = 1'b0;
if(burstcount == 0) begin
if(fml_stb & (($random % 5) == 0)) begin
burstcount = 1;
addr = fml_adr;
we = fml_we;
//$display("Starting FML burst at address %x, data=%x", addr, fml_do);
fml_di = mem[addr/8];
if(we)
mem[addr/8] = fml_do;
fml_ack = 1'b1;
end
end else begin
addr = addr + 8;
burstcount = burstcount + 1;
fml_di = mem[addr/8];
if(we)
mem[addr/8] = fml_do;
//$display("Continuing FML burst at address %x, data=%x", addr, fml_do);
if(burstcount == 4)
burstcount = 0;
end
end
always begin
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_di = 64'd0;
fml_ack = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
$dumpfile("memtest.vcd");
$dumpvars(0, dut);
$display("WRITING");
csrwrite(32'h4, 32'd0);
csrwrite(32'h8, 32'd0);
csrwrite(32'hc, 32'd1);
csrwrite(32'h0, 32'd209716);
csrread(32'h0);
while(|csr_do) begin
#10000;
csrread(32'h0);
end
$display("");
$display("READING");
csrwrite(32'h4, 32'd0);
csrwrite(32'h8, 32'd0);
csrwrite(32'hc, 32'd0);
csrwrite(32'h0, 32'd209716);
csrread(32'h0);
while(|csr_do) begin
#10000;
csrread(32'h0);
end
csrread(32'h4); /* error count */
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int p[500005], q[500005], c[500005], f[500005], siz[500005], fx[500005], sizx[500005], cln[500005 * 2], ans[500005], qu[500005], id[500005]; struct edge { int u, v, w, nxt, id; } e[500005]; vector<int> a[500005]; inline int find(int); void swap(int& a, int& b) { int t = a; a = b; b = t; } bool cmpp(int x, int y) { return e[x].w < e[y].w; } bool cmpq(int x, int y) { return c[x] < c[y]; } inline int read() { int x = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + (c ^ 48); c = getchar(); } return x; } int main() { int i, j, n, m, u, v, nm, t, Q, tmp, top = 0, pos = 1, z; n = read(); m = read(); for (i = 1; i <= m; ++i) { e[i].u = read(); e[i].v = read(); e[i].w = read(); } t = read(); for (i = 1; i <= t; ++i) { nm = read(); for (j = 1; j <= nm; ++j) qu[j] = read(); sort(qu + 1, qu + nm + 1, cmpp); for (j = 1; j <= nm; ++j) { if (e[qu[j - 1]].w ^ e[qu[j]].w) { if (top) a[top][0] = Q; Q = 0; id[++top] = i; c[top] = e[qu[j]].w; a[top].push_back(0); } ++Q; a[top].push_back(qu[j]); } } a[top][0] = Q; Q = 0; for (i = 1; i <= max(top, max(n, m)); ++i) p[i] = q[i] = f[i] = fx[i] = i; for (i = 1; i <= n; ++i) siz[i] = sizx[i] = 1; sort(p + 1, p + m + 1, cmpp); sort(q + 1, q + top + 1, cmpq); for (i = 1; i <= top; ++i) { Q = q[i]; tmp = 0; while (pos <= m && e[p[pos]].w < c[Q]) { u = find(e[p[pos]].u); v = find(e[p[pos]].v); ++pos; if (u == v) continue; if (siz[u] < siz[v]) swap(u, v); cln[++tmp] = v; f[v] = u; siz[u] += siz[v]; } for (j = 1; j <= tmp; ++j) { fx[cln[j]] = f[cln[j]]; sizx[cln[j]] = siz[cln[j]]; } nm = a[Q][0]; tmp = 0; for (j = 1; j <= nm; ++j) { z = a[Q][j]; u = find(e[z].u); v = find(e[z].v); if (u == v) { ans[id[Q]] = 1; break; } if (siz[u] < siz[v]) swap(u, v); cln[++tmp] = v; f[v] = u; siz[u] += siz[v]; } for (j = 1; j <= tmp; ++j) { f[cln[j]] = fx[cln[j]]; siz[cln[j]] = sizx[cln[j]]; } } for (i = 1; i <= t; ++i) puts(ans[i] ? NO : YES ); return 0; } inline int find(int u) { while (u != f[u]) u = f[u]; return u; } |
#include <bits/stdc++.h> using namespace std; char s[1309]; bool a[5201][5201]; int n, i, j, k, f, dp[2][5201][5201]; int main() { for (scanf( %d , &n), i = 1; i <= n; ++i) for (scanf( %s , s), j = 0; s[j]; k = s[j] - ( 9 < s[j] ? A - 10 : 0 ), a[i][(j << 2) + 1] = 8 & k, a[i][(j << 2) + 2] = 4 & k, a[i][(j << 2) + 3] = 2 & k, a[i][(j << 2) + 4] = 1 & k, ++j) ; for (i = 1; i <= n; ++i) for (j = 1; j <= n; k = (bool)a[i][j], dp[k][i][j] = 1 + min(dp[k][i - 1][j - 1], min(dp[k][i][j - 1], dp[k][i - 1][j])), ++j) ; for (k = n + 1; --k; f ? (exit(printf( %d n , k) & 0)) : (void)0) for (f = !(n % (i = k)); f && i <= n; i += k) for (j = k; f && j <= n; f &= (dp[(bool)a[i][j]][i][j] >= k), j += k) ; } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_wr_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Writes between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_intr_wr_mem(
sw_clk,
rstn,
full,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_QOS,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
/* local parameters for interconnect wr fifo model */
input sw_clk, rstn;
output full;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg [axi_qos_width-1:0] WR_QOS;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [wr_fifo_data_bits-1:0] wr_fifo [0:intr_max_outstanding-1];
wire empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
task automatic write_mem;
input [wr_fifo_data_bits-1:0] data;
begin
wr_fifo[wr_ptr[intr_cnt_width-2:0]] = data;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
end
endtask
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
WR_QOS = 0;
state = SEND_DATA;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
if(!empty) begin
WR_DATA = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case(decode_address(wr_fifo[rd_ptr[intr_cnt_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1) begin
rd_ptr[intr_cnt_width-2:0] = 0;
end else begin
rd_ptr = rd_ptr+1;
end
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
endmodule
|
// NOTE: This test program is WRONG, in that it ignores the fact
// that continuous assigns drive with their own strength and drop
// any strength that the r-value may have.
module strength();
wire sup1; assign (supply0, supply1) sup1 = 1'b1;
wire str1; assign (strong0, strong1) str1 = 1'b1;
wire pl1; assign (pull0, pull1) pl1 = 1'b1;
wire we1; assign (weak0, weak1) we1 = 1'b1;
wire sup0; assign (supply0, supply1) sup0 = 1'b0;
wire str0; assign (strong0, strong1) str0 = 1'b0;
wire pl0; assign (pull0, pull1) pl0 = 1'b0;
wire we0; assign (weak0, weak1) we0 = 1'b0;
wire sup1_sup0;
wire sup1_str0;
wire sup1_pl0;
wire sup1_we0;
assign sup1_sup0 = sup1;
assign sup1_sup0 = sup0;
assign sup1_str0 = sup1;
assign sup1_str0 = str0;
assign sup1_pl0 = sup1;
assign sup1_pl0 = pl0;
assign sup1_we0 = sup1;
assign sup1_we0 = we0;
initial begin
#1;
$display("sup1_sup0 resulted in: %b", sup1_sup0);
$display("sup1_str0 resulted in: %b", sup1_str0);
$display("sup1_pl0 resulted in: %b", sup1_pl0);
$display("sup1_we0 resulted in: %b", sup1_we0);
end
wire str1_sup0;
wire str1_str0;
wire str1_pl0;
wire str1_we0;
assign str1_sup0 = str1;
assign str1_sup0 = sup0;
assign str1_str0 = str1;
assign str1_str0 = str0;
assign str1_pl0 = str1;
assign str1_pl0 = pl0;
assign str1_we0 = str1;
assign str1_we0 = we0;
initial begin
#2;
$display("str1_sup0 resulted in: %b", str1_sup0);
$display("str1_str0 resulted in: %b", str1_str0);
$display("str1_pl0 resulted in: %b", str1_pl0);
$display("str1_we0 resulted in: %b", str1_we0);
end
wire pl1_sup0;
wire pl1_str0;
wire pl1_pl0;
wire pl1_we0;
assign pl1_sup0 = pl1;
assign pl1_sup0 = sup0;
assign pl1_str0 = pl1;
assign pl1_str0 = str0;
assign pl1_pl0 = pl1;
assign pl1_pl0 = pl0;
assign pl1_we0 = pl1;
assign pl1_we0 = we0;
initial begin
#3;
$display("pl1_sup0 resulted in: %b", pl1_sup0);
$display("pl1_str0 resulted in: %b", pl1_str0);
$display("pl1_pl0 resulted in: %b", pl1_pl0);
$display("pl1_we0 resulted in: %b", pl1_we0);
end
wire we1_sup0;
wire we1_str0;
wire we1_pl0;
wire we1_we0;
assign we1_sup0 = we1;
assign we1_sup0 = sup0;
assign we1_str0 = we1;
assign we1_str0 = str0;
assign we1_pl0 = we1;
assign we1_pl0 = pl0;
assign we1_we0 = we1;
assign we1_we0 = we0;
initial begin
#4;
$display("we1_sup0 resulted in: %b", we1_sup0);
$display("we1_str0 resulted in: %b", we1_str0);
$display("we1_pl0 resulted in: %b", we1_pl0);
$display("we1_we0 resulted in: %b", we1_we0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[610000], i, j, k, l, n, m, p[610000], t, last, o, r, mid; char c[610000]; bool check(int mid) { int tmp = 1e9, res = 0; p[0] = mid; m = last; for (i = 1; i <= n; ++i) { p[i] = p[i - 1] + a[i]; if (p[i] == 0 && p[i - 1] == -1) m = max(m, i); } if (m == 0) return 1; for (i = 1; i <= m; ++i) { if (p[i - 1] == 0 && p[i] == -1) { o = i; tmp = min(tmp, res + (m - i) * 2); } if (p[i - 1] == -1 && p[i] == 0) { if (i == m) tmp = min(tmp, res + m - o); res += (i - o) * 2; } res++; } tmp = min(tmp, res - 1); return tmp + 1 <= t; } int main() { scanf( %d%d%s , &n, &t, c + 1); for (i = 1; i <= n; ++i) a[i] = c[i] == H ? -1 : c[i] == S ? 1 : 0; for (i = 1; i <= n; ++i) { if (a[i] == -1) r++, last = i; if (a[i] == 1) l--; } l += r; if (l < 0) l = 0; if (last > t) { printf( -1 n ); exit(0); } while (l <= r) { mid = (l + r) / 2; if (check(mid)) r = mid - 1; else l = mid + 1; } printf( %d n , r + 1); } |
#include <bits/stdc++.h> using namespace std; struct node { int leftColors[10], rightColors[10]; int leftParent[10], rightParent[10]; int components; node() { components = 0; } }; int n; node merge(node l, node r) { node ans; ans.components = l.components + r.components; for (int e = 0; e < n; e++) ans.leftParent[e] = l.leftParent[e]; for (int e = 0; e < n; e++) ans.leftColors[e] = l.leftColors[e]; for (int e = 0; e < n; e++) ans.rightParent[e] = r.rightParent[e]; for (int e = 0; e < n; e++) ans.rightColors[e] = r.rightColors[e]; for (int e = 0; e < n; e++) { if (l.rightColors[e] == r.leftColors[e] && l.rightParent[e] != r.leftParent[e]) { ans.components--; int tmp = l.rightParent[e]; for (int f = 0; f < n; f++) if (ans.leftParent[f] == tmp) ans.leftParent[f] = r.leftParent[e]; for (int f = 0; f < n; f++) if (ans.rightParent[f] == tmp) ans.rightParent[f] = r.leftParent[e]; for (int f = 0; f < n; f++) if (l.leftParent[f] == tmp) l.leftParent[f] = r.leftParent[e]; for (int f = 0; f < n; f++) if (l.rightParent[f] == tmp) l.rightParent[f] = r.leftParent[e]; } } return ans; } const int maxn = 100100; node tree[maxn << 2]; int grid[11][maxn]; void build(int id, int l, int r) { if (l == r) { for (int e = 0; e < n; e++) { if (e && grid[e][l] == tree[id].leftColors[e - 1]) tree[id].leftParent[e] = tree[id].leftParent[e - 1], tree[id].rightParent[e] = tree[id].rightParent[e - 1], tree[id].leftColors[e] = tree[id].leftColors[e - 1], tree[id].rightColors[e] = tree[id].rightColors[e - 1]; else { tree[id].leftParent[e] = l * 20 + e; tree[id].rightParent[e] = l * 20 + e; tree[id].leftColors[e] = grid[e][l]; tree[id].rightColors[e] = grid[e][l]; tree[id].components++; } } } else { int mid = (l + r) >> 1; build(id + id, l, mid); build(id + id + 1, mid + 1, r); tree[id] = merge(tree[id + id], tree[id + id + 1]); } } node query(int id, int l, int r, int x, int y) { if (x <= l && r <= y) return tree[id]; int mid = (l + r) >> 1; if (y <= mid) return query(id + id, l, mid, x, y); if (x > mid) return query(id + id + 1, mid + 1, r, x, y); return merge(query(id + id, l, mid, x, y), query(id + id + 1, mid + 1, r, x, y)); } int main() { int m, q; scanf( %d %d %d , &n, &m, &q); for (int e = 0; e < n; e++) for (int f = 0; f < m; f++) scanf( %d , &grid[e][f]); build(1, 0, m - 1); for (int e = 0; e < q; e++) { int l, r; scanf( %d %d , &l, &r); printf( %d n , query(1, 0, m - 1, l - 1, r - 1).components); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; long long d = (k / (n - 1)), r = (k % (n - 1)); if (r != 0) { cout << (d * n) + r << endl; } else { cout << (d * n) - 1 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; string name, host, sour; int main() { ios::sync_with_stdio(false); cin >> s; int i = 0; while (i < s.size() && s[i] != @ ) { name.push_back(s[i]); i++; } i++; while (i < s.size() && s[i] != / ) { host.push_back(s[i]); i++; } bool exist = 0; if (s[i] == / ) exist = 1; i++; if (i != s.size() + 1) while (i < s.size()) { sour.push_back(s[i]); i++; } if (sour.size() > 16 || name.size() == 0 || name.size() > 16 || host.size() > 32 || host.size() == 0) { cout << NO n ; return 0; } if (exist && sour.size() == 0) { cout << NO n ; return 0; } for (int j = 0; j < name.size(); j++) { char c = name[j]; if (!isdigit(c) && !isalpha(c) && (c != < && c != > && c != _ )) { cout << NO n ; return 0; } } int cnt = 0; for (int j = 0; j < host.size(); j++) { char c = host[j]; if (!isdigit(c) && !isalpha(c) && (c != < && c != > && c != . && c != _ )) { cout << NO n ; return 0; } if (c == . ) { if (cnt == 0) { cout << NO n ; return 0; } cnt = -1; } cnt++; if (cnt > 16) { cout << NO n ; return 0; } } if (cnt == 0) { cout << NO n ; return 0; } for (int j = 0; j < sour.size(); j++) { char c = sour[j]; if (!isalpha(c) && !isdigit(c) && (c != < && c != > && c != _ )) { cout << NO n ; return 0; } } cout << YES n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__AND2_PP_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int c, hi, hb, wi, wb; inline long long f(int x) { long long k1 = x; long long k2 = 1ll * (0ll + c - 1ll * x * wi) / wb; return k1 * hi + k2 * hb; } int main() { cin >> c >> hi >> hb >> wi >> wb; int kek1 = c / wi; int l = 0; int r = kek1; long long ans = 0; ans = max(ans, f(0)); ans = max(ans, f(kek1)); for (int i = 0; i <= 10000000; ++i) if (i <= kek1) ans = max(ans, f(i)); while (r - l > 1) { int m = (r - l + 1) / 3; int k1 = l + m; int k2 = r - m; if (f(k1) > f(k2)) r = k2; else l = k1; } for (int i = l - 9000000; i <= r + 9000000; ++i) if (i >= 0 && i <= kek1) ans = max(ans, f(i)); swap(wi, wb); swap(hi, hb); kek1 = c / wi; l = 0; r = kek1; for (int i = 0; i <= 10000000; ++i) if (i <= kek1) ans = max(ans, f(i)); while (r - l > 1) { int m = (r - l + 1) / 3; int k1 = l + m; int k2 = r - m; if (f(k1) > f(k2)) r = k2; else l = k1; } for (int i = l - 9000000; i <= r + 9000000; ++i) if (i >= 0 && i <= kek1) ans = max(ans, f(i)); ans = max(ans, f(0)); ans = max(ans, f(kek1)); cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { long long i, n, m; while (cin >> n) { m = n; for (i = 1; i < n; i++) { if (m <= i) break; m = m - i; } cout << m << endl; } return 0; } |
/*
* Verify that the continuous assignments support a delay that is
* greater than 32 bits. The top delays are in seconds and the other
* delays are in ps. The second delays all require more than 32 bits
* to work correctly. They will use the /d version.
*/
`timescale 1s/1s
module gt32b;
wire real rlval;
wire rval;
wire aval[1:0];
wire [7:0] psval;
assign #1 rlval = 1.0;
assign #2 rval = 1'b1;
assign #3 aval[0] = 1'b0;
assign #4 psval[1] = 1'b1;
initial begin
$timeformat(-12, 0, " ps", 16);
#1;
$display("dl:gt32b- %t", $realtime);
end
always @(rlval) begin
$display("rl:gt32b- %t", $realtime);
end
always @(rval) begin
$display("rg:gt32b- %t", $realtime);
end
always @(aval[0]) begin
$display("ar:gt32b- %t", $realtime);
end
always @(psval) begin
$display("ps:gt32b- %t", $realtime);
end
endmodule
`timescale 1ps/1ps
module ls32b;
wire real rlval;
wire rval;
wire aval[1:0];
wire [7:0] psval;
assign #1 rlval = 1.0;
assign #2 rval = 1'b1;
assign #3 aval[0] = 1'b0;
assign #4 psval[1] = 1'b1;
initial begin
#1;
$display("dl:ls32b- %t", $realtime);
end
always @(rlval) begin
$display("rl:ls32b- %t", $realtime);
end
always @(rval) begin
$display("rg:ls32b- %t", $realtime);
end
always @(aval[0]) begin
$display("ar:ls32b- %t", $realtime);
end
always @(psval) begin
$display("ps:ls32b- %t", $realtime);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int mod = 1e9 + 7; const int M = 2010; pair<int, int> p[M]; int n, m, k, s, x, y, cnt; int fac[2 * N], inv[2 * N], K[30], f[M][30]; bool pd1, pd2; int Pow(int a, int b) { if (b == 0) return 1; int ret = Pow(a, b / 2); ret = 1LL * ret * ret % mod; if (b & 1) ret = 1LL * ret * a % mod; return ret; } int com(int n, int m) { if (m > n) return 0; return 1LL * fac[n] * inv[m] % mod * inv[n - m] % mod; } int cal(int i, int j) { if (p[i].first > p[j].first || p[i].second > p[j].second) return 0; return com(p[j].first - p[i].first + p[j].second - p[i].second, p[j].first - p[i].first); } int main() { fac[0] = inv[0] = 1; for (int i = 1; i < 2 * N; i++) fac[i] = 1LL * fac[i - 1] * i % mod; for (int i = 1; i < 2 * N; i++) inv[i] = Pow(fac[i], mod - 2); scanf( %d%d%d%d , &n, &m, &k, &s); for (int i = 0; i < k; i++) { scanf( %d%d , &x, &y); if (x == 1 && y == 1) pd1 = true; if (x == n && y == m) pd2 = true; p[i] = make_pair(x, y); } if (n == 1 && m == 1) { if (pd1) printf( %d n , (s + 1) / 2); else printf( %d n , s); return 0; } p[k] = make_pair(1, 1); p[k + 1] = make_pair(n, m); sort(p, p + k + 2); if (pd1) s = (s + 1) / 2; for (int tmp = s; tmp != 1; tmp = (tmp + 1) / 2) K[cnt++] = tmp; K[cnt++] = 1; int tot = 0; for (int i = 0; i < k + 2; i++) if (i == 0 || p[i] != p[i - 1]) p[tot++] = p[i]; f[0][0] = 1; for (int i = 1; i < tot - 1; i++) { int tmp = 0; for (int j = 1; j < cnt; j++) { f[i][j] = com(p[i].first - 1 + p[i].second - 1, p[i].first - 1); f[i][j] = (f[i][j] - tmp) % mod; for (int q = 0; q < i; q++) f[i][j] = (f[i][j] - 1LL * f[q][j] * cal(q, i) % mod) % mod; tmp = (tmp + f[i][j]) % mod; } } if (!pd2) { int tmp = 0; for (int j = 0; j < cnt; j++) { f[tot - 1][j] = com(p[tot - 1].first - 1 + p[tot - 1].second - 1, p[tot - 1].first - 1); f[tot - 1][j] = (f[tot - 1][j] - tmp) % mod; for (int q = 0; q < tot - 1; q++) f[tot - 1][j] = (f[tot - 1][j] - 1LL * f[q][j + 1] * cal(q, tot - 1) % mod) % mod; tmp = (tmp + f[tot - 1][j]) % mod; } } else { int tmp = 0; for (int j = 1; j < cnt - 1; j++) { f[tot - 1][j] = com(p[tot - 1].first - 1 + p[tot - 1].second - 1, p[tot - 1].first - 1); f[tot - 1][j] = (f[tot - 1][j] - tmp) % mod; for (int q = 0; q < tot - 1; q++) f[tot - 1][j] = (f[tot - 1][j] - 1LL * f[q][j] * cal(q, tot - 1) % mod) % mod; tmp = (tmp + f[tot - 1][j]) % mod; } f[tot - 1][cnt - 1] = (com(p[tot - 1].first - 1 + p[tot - 1].second - 1, p[tot - 1].first - 1) - tmp) % mod; } int ans = 0; for (int i = 0; i < cnt; i++) ans = (ans + 1LL * K[i] * f[tot - 1][i] % mod) % mod; ans = 1LL * ans * Pow(com(n - 1 + m - 1, n - 1), mod - 2) % mod; ans = (ans + mod) % mod; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); double d, L, v1, v2; cin >> d >> L >> v1 >> v2; double distance; int i, r; cout << fixed << setprecision(20) << (L - d) / (v1 + v2); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:45:53 04/11/2014
// Design Name:
// Module Name: add_32bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module adder_1bit(a, b, ci, s, co);
// port declaration
input wire a,b,ci;
output wire s,co;//co is carry
and (c1,a,b), (c2,b,ci), (c3,a,ci);
xor (s1,a,b), (s,s1,ci);
or (co,c1,c2,c3);
//logical analysis omitted
endmodule
module adder_32bits(A, B, Ctr, S, Co); //Ctr- add or sub
parameter size=32;
input [size:1] A;
input [size:1] B;
input Ctr;
output [size:1] S;
output Co;
wire[size-1:1] Ctemp;
wire[size:1] Bo;
assign Bo={32{Ctr}}^B;
//if ctr=1, do sub (make b to be its 2's complement)
adder_1bit A1(.a(A[1]),.b(Bo[1]),.ci(Ctr),.s(S[1]),.co(Ctemp[1])),
A2(A[2],Bo[2],Ctemp[1],S[2],Ctemp[2]),
A3(A[3],Bo[3],Ctemp[2],S[3],Ctemp[3]),
A4(A[4],Bo[4],Ctemp[3],S[4],Ctemp[4]),
A5(A[5],Bo[5],Ctemp[4],S[5],Ctemp[5]),
A6(A[6],Bo[6],Ctemp[5],S[6],Ctemp[6]),
A7(A[7],Bo[7],Ctemp[6],S[7],Ctemp[7]),
A8(A[8],Bo[8],Ctemp[7],S[8],Ctemp[8]),
A9(A[9],Bo[9],Ctemp[8],S[9],Ctemp[9]),
A10(A[10],Bo[10],Ctemp[9],S[10],Ctemp[10]),
A11(A[11],Bo[11],Ctemp[10],S[11],Ctemp[11]),
A12(A[12],Bo[12],Ctemp[11],S[12],Ctemp[12]),
A13(A[13],Bo[13],Ctemp[12],S[13],Ctemp[13]),
A14(A[14],Bo[14],Ctemp[13],S[14],Ctemp[14]),
A15(A[15],Bo[15],Ctemp[14],S[15],Ctemp[15]),
A16(A[16],Bo[16],Ctemp[15],S[16],Ctemp[16]),
A17(A[17],Bo[17],Ctemp[16],S[17],Ctemp[17]),
A18(A[18],Bo[18],Ctemp[17],S[18],Ctemp[18]),
A19(A[19],Bo[19],Ctemp[18],S[19],Ctemp[19]),
A20(A[20],Bo[20],Ctemp[19],S[20],Ctemp[20]),
A21(A[21],Bo[21],Ctemp[20],S[21],Ctemp[21]),
A22(A[22],Bo[22],Ctemp[21],S[22],Ctemp[22]),
A23(A[23],Bo[23],Ctemp[22],S[23],Ctemp[23]),
A24(A[24],Bo[24],Ctemp[23],S[24],Ctemp[24]),
A25(A[25],Bo[25],Ctemp[24],S[25],Ctemp[25]),
A26(A[26],Bo[26],Ctemp[25],S[26],Ctemp[26]),
A27(A[27],Bo[27],Ctemp[26],S[27],Ctemp[27]),
A28(A[28],Bo[28],Ctemp[27],S[28],Ctemp[28]),
A29(A[29],Bo[29],Ctemp[28],S[29],Ctemp[29]),
A30(A[30],Bo[30],Ctemp[29],S[30],Ctemp[30]),
A31(A[31],Bo[31],Ctemp[30],S[31],Ctemp[31]),
A32(A[32],Bo[32],Ctemp[31],S[32],Co);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 10:40:00 09/11/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: TF_CLS_LED_Output_Fader
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: CLS LED Output Fader Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_CLS_LED_Output_Fader();
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
reg CLOCK_50;
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: CLS_LED_Output_Fader
//
reg LED_FULL_ON;
wire [6:0] PWM_CHANNEL_SIGS;
wire PWM_TIMER_TICK;
wire FADE_TIMER_TICK;
wire LEDR;
CLS_LED_Output_Fader uut
(
// Input Signals
.LED_FULL_ON( LED_FULL_ON ),
.PWM_CHANNEL_SIGS( PWM_CHANNEL_SIGS ),
.PWM_TIMER_TICK( PWM_TIMER_TICK ),
.FADE_TIMER_TICK( FADE_TIMER_TICK ),
// Output Signals
.LEDR( LEDR ),
// System Signals
.CLK( CLOCK_50 )
);
//
// Fadeout Timer Emulation
//
// Use the CLS_Fadeout_Timer module to generate the FADE_TIMER_TICK
//
localparam FADE_RATE_HZ = 10000; // 10 kHz
CLS_Fadeout_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.FADE_RATE_HZ( FADE_RATE_HZ )
)
fadeout_timer
(
// Output Signals
.FADEOUT_TICK( FADE_TIMER_TICK ),
// System Signals
.CLK( CLOCK_50 )
);
//
// PWM Channel Emulation
//
// Generate PWM waveform signals for each PWM channel
//
localparam PWM_DUTY_RATE = 100000; // 100 kHz
//
// PWM Interval Timer
//
CLS_PWM_Interval_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ), // Hz
.DUTY_RATE_HZ( PWM_DUTY_RATE ) // Hz
)
pwm_interval_timer
(
// Output Signals
.PWM_TICK( PWM_TIMER_TICK ),
// System Signals
.CLK( CLOCK_50 )
);
//
// PWM Duty Cycle Timer (one per LED channel)
//
// Note: A generate block is used here to simplify instantiating 8
// instances of the same module.
//
localparam [7*7-1:0] PWM_DutyCycle_List = { 7'd100, 7'd50, 7'd25, 7'd13, 7'd6, 7'd3, 7'd1 };
genvar i; // General purpose variable used by generate for loops
generate
begin
for (i=0; i < 7; i=i+1)
begin : PWM_Channels
//
// PWM Duty Cycle Timer
//
CLS_PWM_DutyCycle_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ), // MHz
.DUTY_RATE_HZ( PWM_DUTY_RATE ), // Hz
.DUTY_PERCENT( PWM_DutyCycle_List[7*i +:7] ) // Cycle On-time %
)
pwm_dutycycle_timer
(
// Input Signals
.PWM_INTERVAL_TICK( PWM_TIMER_TICK ),
// Output Signals
.PWM_OUT( PWM_CHANNEL_SIGS[i] ),
// System Signals
.CLK( CLOCK_50 )
);
end
end
endgenerate
//
// Test Stimulus
//
initial
begin
// Initialize Signals
LED_FULL_ON = 1'b0;
#1000;
//
// Begin Testing
//
// Wait for two PWM Timer cycles
@(posedge PWM_TIMER_TICK);
@(posedge PWM_TIMER_TICK);
// Activate the LED for one Fade Timer cycle
@(posedge CLOCK_50); // Align input signals with Clock
LED_FULL_ON = 1'b1;
@(posedge FADE_TIMER_TICK);
// Deassert the LED_FULL_ON signal
@(posedge CLOCK_50);
LED_FULL_ON = 1'b0;
// Verify Fadeout Sequence
//
// Simulate 1 mS of time for full sequence
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
`timescale 1ps/1ps
module ad_serdes_clk (
// clock and divided clock
mmcm_rst,
clk_in_p,
clk_in_n,
clk,
div_clk,
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ack_t,
drp_locked);
// parameters
parameter SERDES = 1;
parameter MMCM = 1;
parameter MMCM_DEVICE_TYPE = 0;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clock and divided clock
input mmcm_rst;
input clk_in_p;
input clk_in_n;
output clk;
output div_clk;
// drp interface
input drp_clk;
input drp_rst;
input drp_sel;
input drp_wr;
input [11:0] drp_addr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ack_t;
output drp_locked;
// internal signals
wire clk_in_s;
// instantiations
IBUFGDS i_clk_in_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_s));
generate
if (MMCM == 1) begin
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_mmcm_drp (
.clk (clk_in_s),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ack_t (drp_ack_t),
.drp_locked (drp_locked));
end
if ((MMCM == 0) && (SERDES == 0)) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (clk));
assign div_clk = clk;
end
if ((MMCM == 0) && (SERDES == 1)) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));
BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (div_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrtp (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void cp() { ios ::sync_with_stdio(false); cin.tie(0); cout.tie(0); } long long power(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } int main() { cp(); { long long a; cin >> a; ; long long b; cin >> b; ; if (a == b) cout << 0 ; else { long long y = log2(a ^ b) + 1; cout << power(2, y) - 1; } } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:167772160000 ) using namespace std; long long dp[5100][5100]; long long x[5100]; int a[5100], b[5100], c[5100], d[5100]; int main() { int leftminright = 0; int n, s, e; cin >> n >> s >> e; s--; e--; for (int i = 0; i < n; i++) cin >> x[i]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) cin >> c[i]; for (int i = 0; i < n; i++) cin >> d[i]; x[n] = 0; for (int i = 0; i < n + 2; i++) for (int j = 0; j < n + 2; j++) dp[i][j] = 1E18; dp[0][0] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i != 0) { if (j == 0 && leftminright != 1) continue; } if (i == s) { leftminright--; long long now = dp[i][j]; now += d[i]; dp[i + 1][j + 1] = min(dp[i + 1][j + 1], now + (x[i + 1] - x[i]) * ((j + 1) * 2 + leftminright)); now -= d[i]; now += c[i]; if (j + leftminright + 1 > 0) dp[i + 1][j] = min(dp[i + 1][j], now + (x[i + 1] - x[i]) * (j * 2 + leftminright)); leftminright++; continue; } if (i == e) { leftminright++; long long now = dp[i][j]; now += b[i]; dp[i + 1][j] = min(dp[i + 1][j], now + (x[i + 1] - x[i]) * (j * 2 + leftminright)); now -= b[i]; now += a[i]; if (j == 0) { leftminright--; continue; } dp[i + 1][j - 1] = min(dp[i + 1][j - 1], now + (x[i + 1] - x[i]) * (2 * (j - 1) + leftminright)); leftminright--; continue; } long long now = dp[i][j]; now += b[i]; now += d[i]; dp[i + 1][j + 1] = min(dp[i + 1][j + 1], now + (x[i + 1] - x[i]) * ((j + 1) * 2 + leftminright)); now -= d[i]; now += c[i]; if (j + leftminright > 0) dp[i + 1][j] = min(dp[i + 1][j], now + (x[i + 1] - x[i]) * (j * 2 + leftminright)); now -= b[i]; now += a[i]; now -= c[i]; now += d[i]; if (j > 0) dp[i + 1][j] = min(dp[i + 1][j], now + (x[i + 1] - x[i]) * (j * 2 + leftminright)); now -= d[i]; now += c[i]; if (j > 0 && j + leftminright > 0) dp[i + 1][j - 1] = min(dp[i + 1][j - 1], now + (x[i + 1] - x[i]) * ((j - 1) * 2 + leftminright)); } if (i == s) leftminright--; if (i == e) leftminright++; } cout << dp[n][0]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int n, bin[35], f[35][35][2]; void updata(int &x, int y) { x += y; x -= x >= MOD ? MOD : 0; } int main() { scanf( %d , &n); bin[0] = 1; for (int i = 1; i <= 30; i++) bin[i] = bin[i - 1] * 2; for (int i = 30; i >= 0; i--) if (n & bin[i]) { f[i][1][1] = f[i][0][0] = 1; break; } for (int i = 30; i >= 1; i--) for (int j = 0; j <= 30; j++) { if (f[i][j][0]) { updata(f[i - 1][j + 1][0], f[i][j][0]); updata(f[i - 1][j][0], (long long)f[i][j][0] * bin[j] % MOD); } if (f[i][j][1]) { if (n & bin[i - 1]) { updata(f[i - 1][j + 1][1], f[i][j][1]); updata(f[i - 1][j][0], (long long)f[i][j][1] * bin[j - 1] % MOD); updata(f[i - 1][j][1], (long long)f[i][j][1] * bin[j - 1] % MOD); } else updata(f[i - 1][j][1], (long long)f[i][j][1] * bin[j - 1] % MOD); } } int ans = 0; if (!n) ans++; for (int i = 0; i <= 30; i++) updata(ans, f[0][i][0]), updata(ans, f[0][i][1]); printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 1; i <= t; i++) { int x1, x2, y1, y2; string arr[8]; for (int i = 0; i < 8; i++) cin >> arr[i]; bool check = 0; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { if (arr[i][j] == K && check == 0) { check = 1; x1 = j; y1 = i; } else if (arr[i][j] == K ) { x2 = j; y2 = i; } } } if ((x1 == x2 && abs(y1 - y2) == 4) || (y1 == y2 && abs(x1 - x2) == 4)) cout << YES ; else if (abs(x1 - x2) == 4 && abs(y1 - y2) == 4) cout << YES ; else cout << NO ; cout << endl; } return 0; } |
#include <bits/stdc++.h> int a[200001]; int renew[200001]; int payoff[200001]; int maxpay[200001]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , a + i); int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int mode; scanf( %d , &mode); if (mode == 1) { int t1, t2; scanf( %d %d , &t1, &t2); a[t1 - 1] = t2; renew[t1 - 1] = i; } else { int t1; scanf( %d , &t1); payoff[i] = t1; } } maxpay[q - 1] = payoff[q - 1]; for (int i = q - 2; i >= 0; i--) { if (payoff[i] > maxpay[i + 1]) { maxpay[i] = payoff[i]; } else maxpay[i] = maxpay[i + 1]; } for (int i = 0; i < n; i++) { if (maxpay[renew[i]] > a[i]) a[i] = maxpay[renew[i]]; } for (int i = 0; i < n; i++) { printf( %d , a[i]); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int n, a[MAXN * 3], u[MAXN * 3], v[MAXN * 3], front, rear; int main() { int Q; long long x; scanf( %d%d , &n, &Q); front = 1; rear = n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= 2 * n - 2; i++) { u[i] = a[front], v[i] = a[front + 1]; if (u[i] < v[i]) a[++front] = v[i], a[++rear] = u[i]; else a[++front] = u[i], a[++rear] = v[i]; } while (Q--) { cin >> x; if (x > n - 1) x = x % (n - 1) + n - 1; printf( %d %d n , u[x], v[x]); } return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_datactl(
input sys_clk,
input sdram_rst,
input read,
input write,
input [3:0] concerned_bank,
output reg read_safe,
output reg write_safe,
output [3:0] precharge_safe,
output reg ack,
output reg direction,
output direction_r,
input tim_cas,
input [1:0] tim_wr
);
/*
* read_safe: whether it is safe to register a Read command
* into the SDRAM at the next cycle.
*/
reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
read_safe_counter <= 3'd0;
read_safe <= 1'b1;
end else begin
if(read) begin
read_safe_counter <= 3'd7;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 9-CL cycles, therefore we load :
* 7 at CAS Latency 2 (tim_cas = 0)
* 6 at CAS Latency 3 (tim_cas = 1)
*/
read_safe_counter <= {2'b11, ~tim_cas};
read_safe <= 1'b0;
end else begin
if(read_safe_counter == 3'd1)
read_safe <= 1'b1;
if(~read_safe)
read_safe_counter <= read_safe_counter - 3'd1;
end
end
end
/*
* write_safe: whether it is safe to register a Write command
* into the SDRAM at the next cycle.
*/
reg [3:0] write_safe_counter;
always @(posedge sys_clk) begin
if(sdram_rst) begin
write_safe_counter <= 4'd0;
write_safe <= 1'b1;
end else begin
if(read) begin
write_safe_counter <= {3'b100, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
write_safe_counter <= 4'd7;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 4'd1)
write_safe <= 1'b1;
if(~write_safe)
write_safe_counter <= write_safe_counter - 4'd1;
end
end
end
/* Generate ack signal.
* After write is asserted, it should pulse after 2 cycles.
* After read is asserted, it should pulse after CL+2 cycles, that is
* 4 cycles when tim_cas = 0
* 5 cycles when tim_cas = 1
*/
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
if(tim_cas) begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end else begin
ack_read1 <= read;
ack_read0 <= ack_read1;
end
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sdram_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
ack0 <= ack_read0;
ack <= ack0|write;
end
end
/* during a 8-word write, we drive the pins for 9 cycles
* and 1 cycle in advance (first word is invalid)
* so that we remove glitches on DQS without resorting
* to asynchronous logic.
*/
/* direction must be glitch-free, as it directly drives the
* tri-state enable for DQ and DQS.
*/
reg [3:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
counter_writedirection <= 4'd0;
direction <= 1'b0;
end else begin
if(write) begin
counter_writedirection <= 4'b1001;
direction <= 1'b1;
end else begin
if(counter_writedirection == 4'b0001)
direction <= 1'b0;
if(direction)
counter_writedirection <= counter_writedirection - 4'd1;
end
end
end
assign direction_r = write|(|counter_writedirection);
/* Counters that prevent a busy bank from being precharged */
hpdmc_banktimer banktimer0(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[0]),
.write(write & concerned_bank[0]),
.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[1]),
.write(write & concerned_bank[1]),
.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[2]),
.write(write & concerned_bank[2]),
.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_cas(tim_cas),
.tim_wr(tim_wr),
.read(read & concerned_bank[3]),
.write(write & concerned_bank[3]),
.precharge_safe(precharge_safe[3])
);
endmodule
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