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// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: ddio_out_1.v
// Megafunction Name(s):
// altddio_out
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddio_out_1 (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input datain_h;
input datain_l;
input outclock;
output dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout = sub_wire1;
wire sub_wire2 = datain_h;
wire sub_wire3 = sub_wire2;
wire sub_wire4 = datain_l;
wire sub_wire5 = sub_wire4;
altddio_out altddio_out_component (
.outclock (outclock),
.datain_h (sub_wire3),
.aclr (aclr),
.datain_l (sub_wire5),
.dataout (sub_wire0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Arria II GX",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: OE NUMERIC "0"
// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_refgen_new (VINREF, VOUTREF, REFLEAK_BIAS,
AMUXBUS_A, AMUXBUS_B, DFT_REFGEN, HLD_H_N, IBUF_SEL, ENABLE_H, ENABLE_VDDA_H, VOH_SEL, VOHREF,
VREF_SEL, VREG_EN, VTRIP_SEL, VOUTREF_DFT, VINREF_DFT);
output VINREF;
output VOUTREF;
inout REFLEAK_BIAS;
supply1 vccd;
supply1 vcchib;
supply1 vdda;
supply1 vddio;
supply1 vddio_q;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply1 vswitch;
supply0 vssa;
inout AMUXBUS_A;
inout AMUXBUS_B;
input DFT_REFGEN;
input HLD_H_N;
input IBUF_SEL;
input ENABLE_H;
input ENABLE_VDDA_H;
input [2:0] VOH_SEL;
input VOHREF;
input [1:0] VREF_SEL;
input VREG_EN;
input VTRIP_SEL;
inout VOUTREF_DFT;
inout VINREF_DFT;
reg ibuf_sel_final, vtrip_sel_final, vreg_en_final, dft_refgen_final, vref_sel_int_final;
reg [2:0] voh_sel_final;
reg [1:0] vref_sel_final;
reg vohref_int;
wire pwr_good_active_mode_1 = 1;
wire pwr_good_hold_mode_1 = 1;
wire pwr_good_hold_mode_2 = 1;
wire pwr_good_active_mode_2 = 1;
wire pwr_good_hold_mode_3 = 1;
wire pwr_good_active_mode_3 = 1;
`ifdef SKY130_FD_IO_TOP_REFGEN_NEW_DISABLE_DELAY
parameter STARTUP_TIME_VOUTREF = 0;
parameter STARTUP_TIME_VINREF = 0;
`else
parameter STARTUP_TIME_VOUTREF = 50000;
parameter STARTUP_TIME_VINREF = 50000;
`endif
integer startup_time_vinref,startup_time_voutref;
initial begin
startup_time_vinref = vref_sel_int_final===1 && vtrip_sel_final===0 ? STARTUP_TIME_VINREF : 0;
startup_time_voutref = STARTUP_TIME_VOUTREF;
end
wire notifier_enable_h, notifier_vtrip_sel, notifier_ibuf_sel, notifier_vref_sel,
notifier_voh_sel, notifier_vreg_en, notifier_dft_refgen, notifier_vref_sel_int;
always @(*)
begin : LATCH_ibuf_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode_1 || (ENABLE_H===1 && ^HLD_H_N===1'bx))
ibuf_sel_final <= 1'bx;
else if (ENABLE_H===0)
ibuf_sel_final <= 1'b0;
else if (HLD_H_N===1)
ibuf_sel_final <= (^IBUF_SEL === 1'bx || !pwr_good_active_mode_1) ? 1'bx : IBUF_SEL;
end
always @(notifier_enable_h or notifier_ibuf_sel)
begin
disable LATCH_ibuf_sel; ibuf_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode_1 || (ENABLE_H===1 && ^HLD_H_N===1'bx))
vtrip_sel_final <= 1'bx;
else if (ENABLE_H===0)
vtrip_sel_final <= 1'b0;
else if (HLD_H_N===1)
vtrip_sel_final <= (^VTRIP_SEL === 1'bx || !pwr_good_active_mode_1) ? 1'bx : VTRIP_SEL;
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_vreg_en
if (^ENABLE_H===1'bx || !pwr_good_hold_mode_1 || (ENABLE_H===1 && ^HLD_H_N===1'bx))
vreg_en_final <= 1'bx;
else if (ENABLE_H===0)
vreg_en_final <= 1'b0;
else if (HLD_H_N===1)
vreg_en_final <= (^VREG_EN === 1'bx || !pwr_good_active_mode_1) ? 1'bx : VREG_EN;
end
always @(notifier_enable_h or notifier_vreg_en)
begin
disable LATCH_vreg_en; vreg_en_final <= 1'bx;
end
always @(*)
begin : LATCH_vref_sel_int
if (^ENABLE_H===1'bx || !pwr_good_hold_mode_1 || (ENABLE_H===1 && ^HLD_H_N===1'bx))
vref_sel_int_final <= 1'bx;
else if (ENABLE_H===0)
vref_sel_int_final <= 1'b0;
else if (HLD_H_N===1)
vref_sel_int_final <= (^VREF_SEL[1:0] === 1'bx || !pwr_good_active_mode_1) ? 1'bx : (VREF_SEL[1] || VREF_SEL[0]);
end
always @(notifier_enable_h or notifier_vref_sel_int)
begin
disable LATCH_vref_sel; vref_sel_int_final <= 1'bx;
end
always @(*)
begin : LATCH_vref_sel
if (^ENABLE_VDDA_H===1'bx || ^ENABLE_H===1'bx ||!pwr_good_hold_mode_2 || (ENABLE_VDDA_H===1 && ENABLE_H===1 && ^HLD_H_N===1'bx))
vref_sel_final = 2'bxx;
else if (ENABLE_VDDA_H===0 || ENABLE_H===0)
vref_sel_final = 2'b00;
else if (HLD_H_N===1)
vref_sel_final = (^VREF_SEL[1:0]=== 1'bx || !pwr_good_active_mode_2) ? 2'bxx : VREF_SEL;
end
always @(notifier_enable_h or notifier_vref_sel)
begin
disable LATCH_vref_sel; vref_sel_final <= 2'bxx;
end
always @(*)
begin : LATCH_dft_refgen
if (^ENABLE_VDDA_H===1'bx || ^ENABLE_H===1'bx ||!pwr_good_hold_mode_2 || (ENABLE_VDDA_H===1 && ENABLE_H===1 &&^HLD_H_N===1'bx))
dft_refgen_final = 2'bxx;
else if (ENABLE_VDDA_H===0 || ENABLE_H===0)
dft_refgen_final = 2'b00;
else if (HLD_H_N===1)
dft_refgen_final = (^DFT_REFGEN=== 1'bx || !pwr_good_active_mode_2) ? 2'bxx : DFT_REFGEN;
end
always @(notifier_enable_h or notifier_dft_refgen)
begin
disable LATCH_dft_refgen; dft_refgen_final <= 2'bxx;
end
always @(*)
begin : LATCH_voh_sel
if (^ENABLE_VDDA_H===1'bx ||^ENABLE_H===1'bx || !pwr_good_hold_mode_3 || (ENABLE_VDDA_H===1 && ENABLE_H===1 && ^HLD_H_N===1'bx))
voh_sel_final = 3'bxxx;
else if (ENABLE_VDDA_H===0 || ENABLE_H===0)
voh_sel_final = 3'b000;
else if (HLD_H_N===1)
voh_sel_final = (^VOH_SEL[2:0]=== 1'bx || !pwr_good_active_mode_3) ? 3'bxxx : VOH_SEL;
end
always @(notifier_enable_h or notifier_voh_sel)
begin
disable LATCH_voh_sel; voh_sel_final <= 2'bxx;
end
always @(*)
begin
case (vref_sel_final[1:0])
2'b00, 2'b01 : vohref_int = VOHREF!==1'b1 ? 1'bx : VOHREF;
2'b10 : vohref_int = ^AMUXBUS_A!==1'b1 ? 1'bx : AMUXBUS_A;
2'b11 : vohref_int = ^AMUXBUS_B!==1'b1 ? 1'bx : AMUXBUS_B;
default : vohref_int = 1'bx;
endcase
end
wire vohref_final = ENABLE_VDDA_H===1'b1 ? vohref_int : 1'bx;
assign #(startup_time_voutref,0) VOUTREF = (REFLEAK_BIAS===1'bx) ? 1'bx : (REFLEAK_BIAS===1 ? vohref_final:1'bz);
assign VOUTREF_DFT = dft_refgen_final===1 ? VOUTREF : (dft_refgen_final===0 ? 1'bz : 1'bx);
assign REFLEAK_BIAS = vcchib!==1 ? 1'bx : (vreg_en_final || (ibuf_sel_final && vref_sel_int_final));
reg vinref_tmp;
always @(*)
begin
if (ibuf_sel_final===1'bx
|| (ibuf_sel_final===1 && (vref_sel_int_final===1'bx || vtrip_sel_final===1'bx))
|| (ibuf_sel_final===1 && vref_sel_int_final===1 && (vcchib!==1 || vohref_int!==1))
|| (ibuf_sel_final===1 && vref_sel_int_final===1 && vtrip_sel_final===0 && ^voh_sel_final[2:0]===1'bx))
vinref_tmp = 1'bx;
else
vinref_tmp = ibuf_sel_final===0 ? 1'bz : 1'b1;
end
assign #(startup_time_vinref,0) VINREF = vinref_tmp;
assign VINREF_DFT = dft_refgen_final===1 ? VINREF : (dft_refgen_final===0 ? 1'bz : 1'bx);
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [7:0] featurebits,
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // want to access RAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output cx4_enable,
output cx4_vect_enable,
output r213f_enable,
output snescmd_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* Cx4 mapper:
- LoROM (extended to 00-7d, 80-ff)
- MMIO @ 6000-7fff
- SRAM @ 70-7d/80-ff:0000-7fff
*/
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = |SAVERAM_MASK & (&SNES_ADDR[22:20] & ~SNES_ADDR[15] & (SNES_ADDR[19:16] < 4'b1110));
assign SRAM_SNES_ADDR = IS_SAVERAM
? (24'hE00000 | ({SNES_ADDR[19:16], SNES_ADDR[14:0]}
& SAVERAM_MASK))
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign IS_WRITABLE = IS_SAVERAM;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
wire msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign msu_enable = msu_enable_w;
wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
assign cx4_enable = cx4_enable_w;
assign cx4_vect_enable = &SNES_ADDR[15:5];
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 9'h3f);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, temp; int main() { scanf( %d%d%d , &n, &m, &k); if (n % 2 == 0 || m < (n / 2 + 1)) { printf( 0 n ); return 0; } long long minA = (m / (n / 2 + 1)) * k; for (int i = 0; i < n; i++) { scanf( %d , &temp); if (i % 2 == 0 && temp < minA) minA = temp; } printf( %d n , minA); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; string s; int main() { cin.tie(0); std::ios::sync_with_stdio(false); cin >> n >> k; cin >> s; if (k == 2) { string s1 = , s2 = ; for (int i = 0; i < s.size(); i++) if (i & 1) s1 += A , s2 += B ; else s1 += B , s2 += A ; int x = 0, y = 0; for (int i = 0; i < s.size(); i++) x += (s[i] == s1[i] ? 1 : 0), y += (s[i] == s2[i] ? 1 : 0); if (x > y) cout << s.size() - x << endl << s1 << endl; else cout << s.size() - y << endl << s2 << endl; return 0; } string h; int z = 1; map<int, char> mop; map<char, int> mops; for (char c = A ; c <= Z ; c++) { mop[z] = c, mops[c] = z, z++; if (z > k) break; } string t = s; int ans = 0; for (int i = 0; i < s.size() - 1; i++) { if (s[i] == s[i + 1]) { h = s[i], h += s[i + 1]; int f = i + 1; for (int j = i + 2; j < s.size(); j++) { if (s[j] != s[i]) break; f++; h += s[j]; } char prev = s[i - 1], next = h[1]; if (h.size() % 2 == 0) for (int j = 0; j < h.size(); j += 2) { for (__typeof((mops).begin()) it = (mops).begin(); it != (mops).end(); it++) if (it->first != prev && it->first != next) { h[j] = it->first; prev = h[j + 1], next = h[j + 3]; ans++; break; } } else { prev = h[0], next = h[2]; for (int j = 1; j < h.size(); j += 2) { for (__typeof((mops).begin()) it = (mops).begin(); it != (mops).end(); it++) if (it->first != prev && it->first != next) { h[j] = it->first; prev = h[j + 1]; next = h[j + 3]; ans++; break; } } } int n = 0; for (int j = i; j < f; j++) s[j] = h[n++]; i = f - 1; } } cout << ans << endl; cout << s << endl; return 0; } |
/*Allah Vorosha*/ #include<bits/stdc++.h> #define ll long long #define ld long double #define pb push_back #define in insert #define rev reverse #define all(x) (x).begin(),(x).end() #define all2(x) (x).rbegin(),(x).rend() #define sz(v) (int)v.size() #define yes cout << YES n #define no cout << NO n ; #define take for(auto &it : a) cin >> it; #define vi vector<int> #define vii vector<pair<int, int > > #define vl vector<ll> #define fi first #define se second #define l_b lower_bound #define u_b upper_bound #define ios ios_base::sync_with_stdio(0);cin.tie();cout.tie(); #define tail cout << n using namespace std; template<class T> void read(T &x) { cin >> x; } template<class T, class ...U> void read(T &x, U& ... u) { read(x); read(u...); } template<class T> void print1(const T &x) { cout << x << n ; } template<class T, class ...U> void print1(const T &x, const U& ... u) { print1(x); print1(u...); } template<class T> void print2(const T &x) { cout << x << ; } template<class T, class ...U> void print2(const T &x, const U& ... u) { print2(x); print2(u...); } int dx[] = {0, 0, 1, -1}, dy[] = {1, -1, 0, 0}; //int n, m; bool valid (int x, int y) { //return (x >= 0 && x < n && y >= 0 && y < m); } bool vis[55][55]; const int N = 1005, mod = 1e9 + 7, M = 5e5 + 5; const ll inf = 9e18; int cs = 1; void solve() { ll n, c; read(n, c); vi a(n); take; vi b(n - 1); for(auto &it : b) cin >> it; ll hi = c, low = 1, mid, ans; while(hi >= low) { mid = (hi + low) >> 1; ll day = mid; ll tk = 0; bool ok = 0; for(int i = 0; i < n; i++) { if(tk + a[i] * day >= c) { ok = 1; break; } else { if(i == n - 1) { if(tk + a[i] * day >= c) { ok = 1; break; } } else { if(tk >= b[i]) { tk -= b[i]; day--; } else { ll k = b[i] - tk; ll l = k / a[i] + (k % a[i] != 0); day -= l + 1; tk += l * a[i]; tk -= b[i]; } } } //if(mid == 6) print1(day); if(day < 0) { break; } } if(ok) { ans = mid; hi = mid - 1; } else { low = mid + 1; } } cout << ans << n ; } int main() { ios; int tc; read(tc); while(tc--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MXN = 1e5 + 1; int n, dp[MXN], k[MXN], ans = 1, rg[MXN], res, maxi; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> k[i]; dp[k[i]] += dp[k[i] - 1] + 1; } for (int i = 1; i <= n; i++) { if (dp[k[i]] > maxi) { maxi = dp[k[i]]; } } cout << n - maxi; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int func1(long long int i) { return i * (i + 1) * (2 * i + 1) / 6 - (i + i + 2) * i * (i + 1) / 2 + (i + i + 1 + i * i) * i; } long long int func2(long long int i) { return i + i * i - i * (i + 1) / 2; } int main() { long long int inp; cin >> inp; set<pair<long long int, long long int> > s; for (long long int i = 1; func1(i) <= inp; i++) if ((inp - func1(i)) % func2(i) == 0) { s.insert(make_pair(i, i + (inp - func1(i)) / func2(i))); s.insert(make_pair(i + (inp - func1(i)) / func2(i), i)); } cout << s.size() << n ; for (auto i = s.begin(); i != s.end(); i++) cout << (*i).first << << (*i).second << n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimization( O3 ) using namespace std; template <typename T> inline void Cin(T& first) { char c; T sign = 1; first = 0; for (c = getchar(); c < 0 || c > 9 ; c = getchar()) if (c == - ) sign = -1; for (; c >= 0 && c <= 9 ; c = getchar()) first = first * 10 + c - 0 ; first *= sign; } template <typename T> inline void Out(T first) { if (first > 9) Out(first / 10); putchar(first % 10 + 0 ); } template <typename T> inline void Cout(T first, char c) { if (first < 0) putchar( - ); first = abs(first); Out(first); putchar(c); } template <typename T, typename... Args> inline void Cin(T& a, Args&... args) { Cin(a); Cin(args...); } template <typename T, typename... Args> inline void Cout(T a, char c, Args... args) { Cout(a, c); Cout(args...); } const int mod = int(1e9) + 7; const int N = 2050; int f[N][N], a[N], n, k, nState; void Enter() { cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; } void add(int& first, int second) { if ((first += second) >= mod) first -= mod; } void Solve() { nState = 1 << k, f[0][0] = 1; for (int i = 1; i <= n; ++i) { for (int bit = 0; bit <= nState; ++bit) { if (!f[i - 1][bit]) continue; if (a[i] == 2 || a[i] == 0) { if (bit + 2 >= nState) add(f[i][nState], f[i - 1][bit]); else add(f[i][bit + 2], f[i - 1][bit]); } if (a[i] == 4 || a[i] == 0) { if ((bit >> 1) & 1) add(f[i][4], f[i - 1][bit]); else { if (bit + 4 >= nState) add(f[i][nState], f[i - 1][bit]); else add(f[i][bit + 4], f[i - 1][bit]); } } } } cout << f[n][nState]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); if (fopen( test .inp , r )) { freopen( test .inp , r , stdin); freopen( test .out , w , stdout); } Enter(), Solve(); return 0; } |
//////////////////////////////////////////////////////////////////
////
////
//// AES CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa,
//// Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module mix_columns
(
// OUTPUTS
output [31:0] mix_out_enc,
output [31:0] mix_out_dec,
// INPUTS
input [31:0] mix_in
);
localparam integer SIZE = 32;
localparam integer WORD_SIZE = 8;
localparam integer NUM_WORDS = 4;
wire [WORD_SIZE - 1 : 0] col [0 : NUM_WORDS - 1];
wire [WORD_SIZE - 1 : 0] sum_p[0 : NUM_WORDS - 1];
wire [WORD_SIZE - 1 : 0] y [0 : NUM_WORDS - 2];
//=====================================================================================
// Multiplication by 02 in GF(2^8)
//=====================================================================================
function [7:0] aes_mult_02;
input [7:0] data_in;
begin
aes_mult_02 = (data_in << 1) ^ {8{data_in[7]}} & 8'h1b;
end
endfunction
//=====================================================================================
// Multiplication by 04 in GF(2^8)
//=====================================================================================
function [7:0] aes_mult_04;
input [7:0] data_in;
begin
aes_mult_04 = ((data_in << 2) ^ {8{data_in[6]}} & 8'h1b) ^ {8{data_in[7]}} & 8'h36;
end
endfunction
//=====================================================================================
// Word to Byte transformation
//=====================================================================================
generate
genvar i;
for(i = 0 ; i < NUM_WORDS; i = i + 1)
begin:WBT
assign col[i] = mix_in[WORD_SIZE*(i + 1) - 1: WORD_SIZE*i];
end
endgenerate
//=====================================================================================
// Direct Mix Column Operation
//=====================================================================================
generate
genvar j;
for(j = 0; j < NUM_WORDS; j = j + 1)
begin:DMCO
assign sum_p[j] = col[(j + 1)%NUM_WORDS] ^ col[(j + 2)%NUM_WORDS] ^ col[(j + 3)%NUM_WORDS];
assign mix_out_enc[ WORD_SIZE*(j + 1) - 1 : WORD_SIZE*j] = aes_mult_02(col[j] ^ col[(j + NUM_WORDS - 1)%NUM_WORDS]) ^ sum_p[j];
end
endgenerate
//=====================================================================================
// Inverse Mix Column Operation
//=====================================================================================
assign y[0] = aes_mult_04(col[2] ^ col[0]);
assign y[1] = aes_mult_04(col[3] ^ col[1]);
assign y[2] = aes_mult_02( y[1] ^ y[0]);
assign mix_out_dec = mix_out_enc ^ {2{y[2] ^ y[1], y[2] ^ y[0]}};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_2_V
`define SKY130_FD_SC_HD__MUX2I_2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_2_V
|
#include <bits/stdc++.h> using namespace std; priority_queue<pair<long long int, int> > pq; vector<pair<int, int> > vp; map<long long int, int> mp, m; const int N = 1e5 + 6; long long int ans[N]; vector<int> v, v1; set<long long int> s, s1; int visit[N]; struct domingo { int val, left, right; } o[N]; bool used[102]; int main() { int a, b, c, ct = 1; cin >> a >> b >> c; a = a % b; a *= 10; for (int i = 0; i < 1e5 + 5; i++) { int x = a / b; a %= b; if (x == c) return cout << ct, 0; a *= 10; ct++; } cout << -1; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_BLACKBOX_V
`define SKY130_FD_SC_HD__XOR3_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long DP[20][4]; void init() { DP[0][3] = DP[0][2] = DP[0][1] = DP[0][0] = 1; for (int i = 1; i <= 18; i++) { DP[i][0] = 1; for (int j = 1; j <= 3; j++) { DP[i][j] = 9 * DP[i - 1][j - 1] + DP[i - 1][j]; } } } long long sol(int i, int j, string str) { if (i == 0) { if (j >= 0) return 1; else return 0; } int d = str[i - 1] - 0 ; if (d == 0) return sol(i - 1, j, str); else if (j == 0) return 1; return DP[i - 1][j] + (d - 1) * DP[i - 1][j - 1] + sol(i - 1, j - 1, str); } string tostr(long long x) { string rtn; while (x) { rtn += (x % 10 + 0 ); x /= 10; } return rtn; } string A, B; long long a, b; int cas; int main() { ios::sync_with_stdio(false); init(); cin >> cas; while (cas--) { cin >> a >> b; a--; A = tostr(a); B = tostr(b); cout << sol(B.length(), 3, B) - sol(A.length(), 3, A) << n ; } return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, d; long long k, now; int a[1005][1005]; void Dfs(int u, int i) { if (a[u][i] == k) { a[u][i] = 0; a[u][i + 1]++; Dfs(u, i + 1); } } int main() { n = read(); k = read(); d = read(); int t = n; for (int i = 1; i <= d; i++) t = t / k + (int)(t % k > 0); memset(a, 0, sizeof(a)); if (t == 1) { for (int u = 2; u <= n; u++) { for (int i = 1; i <= d; i++) a[u][i] = a[u - 1][i]; a[u][1] += 1; Dfs(u, 1); } for (int i = 1; i <= d; i++) { for (int j = 1; j <= n; j++) printf( %d , a[j][i] + 1); puts( ); } } else puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, a[20000], p[20000], i, l, j, mx, ans[20000], mxi; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n; i++) { mx = 0; for (j = i; j < n; j++) { p[a[j]]++; if (p[a[j]] > mx or (p[a[j]] == mx and a[j] < mxi)) { mx = p[a[j]]; mxi = a[j]; } ans[mxi]++; } for (j = i + 1; j <= n; j++) p[a[j]] = 0; } for (i = 1; i <= n; i++) { cout << ans[i] << ; } cout << endl; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_saturation_endEe_DSP48_0(
input [20 - 1:0] in0,
input [16 - 1:0] in1,
input [27 - 1:0] in2,
output [36 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in0);
assign b = $signed(in1);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_saturation_endEe(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_saturation_endEe_DSP48_0 hls_saturation_endEe_DSP48_0_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t > 0) { int a[3]; for (int i = 0; i < 3; i++) { cin >> a[i]; } sort(a, a + 3); long c; if (a[0] == a[1] && a[1] == a[2]) c = 0; else if (a[0] == a[1] && a[2] - a[0] > 1) { c = (a[2] - 1) * 2 - (a[0] + a[1] + 2); } else if (a[0] == a[1] && a[2] - a[0] == 1) { c = 0; } else if (a[1] == a[2] && a[2] - a[0] > 1) { c = (a[1] + a[2] - 2) - (a[0] + 1) * 2; } else if (a[1] == a[2] && a[2] - a[0] == 1) { c = 0; } else { c = a[1] - a[0] - 1 + a[2] - 1 - a[1] + a[2] - a[0] - 2; } cout << c << n ; t--; } } |
#include <bits/stdc++.h> #pragma warning(disable : 4996) template <typename T> T min(T x, T y) { return x < y ? x : y; } template <typename T> T max(T x, T y) { return x > y ? x : y; }; const int INF = 2000000005; const long long mod = 1000000007; const long long MAXN = 1000005; const double eps = 1e-6; int sgn(double x) { return x < -eps ? -1 : x > eps; } double SQ(double x) { return x * x; } struct point { double x; double y; point(double X = 0, double Y = 0) { x = X, y = Y; } point operator-(point t) { return {x - t.x, y - t.y}; } double operator*(point t) { return x * t.y - y * t.x; } double operator%(point t) { return x * t.x + y * t.y; } double norm() { return sqrt(SQ(x) + SQ(y)); } }; struct polygon { int n; std::vector<point> V; double S; void read() { double x, y; V.clear(); scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lf %lf , &x, &y); V.push_back({x, y}); } S = 0; for (int i = 0; i < n - 1; i++) S += V[i] * V[i + 1]; S += V[n - 1] * V[0]; S = 0.5 * fabs(S); } bool in(point p) { int cnt = 0; for (int i = 0; i < n; i++) { int j = (i + 1) % n; point u = V[i], v = V[j]; if (sgn(p.y - u.y) == 0 || sgn(p.y - v.y) == 0) return in({p.x, p.y + 3 * eps}); if (sgn(u.y - v.y) <= 0) std::swap(u, v); if (sgn(p.y - u.y) > 0 || sgn(p.y - v.y) <= 0) continue; cnt += sgn((v - p) * (u - p)) > 0; } return cnt & 1; } double dis(point a, point b, point p) { point ab = b - a, pa = a - p, pb = b - p; if ((ab % pb) * (ab % pa) < 0) return fabs(pa * ab) / ab.norm(); return min(pa.norm(), pb.norm()); } double dis(double x, double y) { double t = 1e15; for (int i = 0; i < n; i++) { int j = (i + 1) % n; point u = V[i], v = V[j]; t = min(t, dis(u, v, {x, y})); } return t; } bool judge(double x, double y, double r) { if (dis(x, y) < r + eps) return true; return in({x, y}); } }; double W, H; int N, Q; polygon P[MAXN]; int main() { scanf( %lf %lf %d , &W, &H, &N); for (int i = 1; i <= N; i++) P[i].read(); double x, y, r; scanf( %d , &Q); while (Q--) { scanf( %lf %lf %lf , &x, &y, &r); std::vector<int> q; double t = 0; for (int i = 1; i <= N; i++) if (P[i].judge(x, y, r)) q.push_back(i - 1), t += P[i].S; printf( %lf %d , t, q.size()); for (int i = 0; i < q.size(); i++) printf( %d , q[i]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int q, n, m, u1, d1, l1, r1, u2, d2, l2, r2, u3, d3, l3, r3; long long count(int a, int b) { return (1ll * a * b + 1) / 2; } long long count(int u, int d, int l, int r) { return count(d, r) + count(u - 1, l - 1) - count(d, l - 1) - count(u - 1, r); } int main() { scanf( %d , &q); while (q--) { scanf( %d %d , &m, &n); scanf( %d %d %d %d , &u1, &l1, &d1, &r1); scanf( %d %d %d %d , &u2, &l2, &d2, &r2); long long ans = count(n, m); u3 = max(u1, u2), l3 = max(l1, l2); d3 = min(d1, d2), r3 = min(r1, r2); ans -= count(u2, d2, l2, r2); ans += 1ll * (d1 - u1 + 1) * (r1 - l1 + 1) - count(u1, d1, l1, r1); if (d3 >= u3 && r3 >= l3) ans -= 1ll * (d3 - u3 + 1) * (r3 - l3 + 1) - count(u3, d3, l3, r3); printf( %I64d %I64d n , ans, 1ll * n * m - ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct info { int l, r, need, onemore, take; }; vector<string> solve(vector<int> a, int n) { vector<string> ans(n + 1, string(n, 0 )); vector<info> state = {{0, n, (n + 1) / 2, ((n + 1) & 1), 0}}; int pos = 0; for (auto i : a) { for (auto &j : state) while (j.need && i) { --i; --j.need; ++j.take; } for (auto &j : state) if (j.onemore && i) { --i; --j.onemore; ++j.take; } int j = 0; while (i > 0) { if (state[j].take != state[j].r - state[j].l + 1) { --i; ++state[j].take; } j = (j + 1) % state.size(); } vector<info> nstate; for (auto &k : state) { for (int p = k.l; p < k.l + k.take; ++p) ans[p][pos] = 1 ; if (k.take) nstate.push_back({k.l, k.l + k.take - 1, 0, 0, 0}); if (k.take < k.r - k.l + 1) nstate.push_back({k.l + k.take, k.r, 0, 0, 0}); } state = nstate; for (auto &k : state) { k.need = (k.r - k.l + 1) / 2; k.onemore = (k.r - k.l + 1) & 1; k.take = 0; } ++pos; } sort(ans.begin(), ans.end()); reverse(ans.begin(), ans.end()); while (!ans.empty() && ans.back() == string(n, 0 )) ans.pop_back(); return ans; } void validate(vector<int> a, int n, vector<string> ans) { for (auto &j : ans) for (int i = 0; i < n; ++i) if (j[i] == 1 ) --a[i]; assert(count(a.begin(), a.end(), 0) == n); for (int i = 1; i < ans.size(); ++i) assert(ans[i - 1] != ans[i]); } int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n; cin >> n; vector<int> a(n); for (auto &i : a) cin >> i; auto ans = solve(a, n); validate(a, n, ans); cout << ans.size() << n ; for (auto i : ans) cout << i << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_BEHAVIORAL_PP_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_BEHAVIORAL_PP_V |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2));
bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_2 : io_2_oe
<= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_3 : io_3_oe
<= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, a[5] = {0}; cin >> n; for (int i = 0; i < n; i++) { cin >> x; a[x]++; } int res = a[4]; res += a[2] / 2; a[2] = a[2] % 2; if (a[2] == 1) { res++; a[1] -= 2; } res += a[3]; if (a[1] > a[3]) { a[1] -= a[3]; res += (a[1] + 3) / 4; } cout << res; return 0; } |
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "deepgate_include.v"
module deepgate_top(
// 50MHz clock input
input clk50MHz,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0] led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//SDRAM interface
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
`include "param_include.v"
wire rst = ~rst_n; //becomes active high
wire clk;
//wire pllLock;
wire pllFeedbackClk;
/*
PLL_BASE#(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.0),
.CLKIN_PERIOD ("20"),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_DUTY_CYCLE (0.5),
.CLKOUT0_PHASE (0.0),
.CLK_FEEDBACK ("CLKFBOUT"),
//.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.REF_JITTER (0.1),
.RESET_ON_LOSS_OF_LOCK ("FALSE")
)
PLL_BASE_inst(
.CLKFBOUT (pllFeedbackClk),
.CLKOUT0 (clk),
// .LOCKED (pllLock),
.CLKFBIN (pllFeedbackClk),
.CLKIN (clk50MHz),
.RST (0)
);
*/
assign clk = clk50MHz;
wire [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
wire newTXData;
avr_interface AVR (
.clk (clk),
.rst (rst),
.cclk (cclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi),
.spi_sck (spi_sck),
.spi_ss (spi_ss),
.spi_channel (spi_channel),
.tx (avr_rx),
.rx (avr_tx),
.channel (4'd15),
.tx_data (tx_data),
.new_tx_data (newTXData),
.tx_busy (tx_busy),
.tx_block (avr_rx_busy),
.rx_data (rx_data),
.new_rx_data (new_rx_data)
);
wire [31:0] sdramDataTX;
wire [31:0] sdramDataRX;
wire [22:0] sdramAddr;
wire sdramBusy;
wire sdramTXValid;
wire sdramRXValid;
wire sdramRW;
sdram SDRAM (
.clk (clk),
.rst (rst),
// these signals go directly to the IO pins
.sdram_clk (sdram_clk),
.sdram_cle (sdram_cle),
.sdram_cs (sdram_cs),
.sdram_cas (sdram_cas),
.sdram_ras (sdram_ras),
.sdram_we (sdram_we),
.sdram_dqm (sdram_dqm),
.sdram_ba (sdram_ba),
.sdram_a (sdram_a),
.sdram_dq (sdram_dq),
// User interface
.addr (sdramAddr), // address to read/write
.rw (sdramRW), // 1 = write, 0 = read
.data_in (sdramDataTX), // sdram data to write
.data_out (sdramDataRX), // sdram data from read
.busy (sdramBusy), // controller is busy when high
.in_valid (sdramTXValid), // pulse high to initiate a read/write
.out_valid (sdramRXValid) // pulses high when data from read is valid
);
wire procBegin;
wire procComplete;
wire [7:0] networkDataIn;
wire [7:0] networkOut;
wire networkIdle;
wire networkRead;
wire inputRead;
wire [7:0] weightData;
wire [NUM_TILES - 1'b1 : 0] pipelineLock;
wire [NUM_TILES - 1'b1 : 0] weightRAMwrEn;
//neural network
tile_network ANN(
.clk_i (clk),
.en_i (procBegin),
.data_rd_o (inputRead),
.data_rd_i (networkRead),
.data_i (networkDataIn),
.network_idle_o (networkIdle),
.data_o (networkOut),
.proc_complete_o (procComplete),
.weight_wr_i (weightRAMwrEn),
.weight_data_i (weightData),
.pipeline_lock_o (pipelineLock)
);
master_control MCU(
.clk (clk),
.rst (rst),
//AVR SPI
.TXBusy (tx_busy),
.newRXData (new_rx_data),
.RXData (rx_data),
.TXDataBuffer (tx_data),
.newTXData (newTXData),
//MLPNN
.inputRead (inputRead),
.networkIdle (networkIdle),
.procComplete (procComplete),
.networkOut (networkOut),
.networkDataIn (networkDataIn),
.procBegin (procBegin),
.networkRead (networkRead),
.weightRAMwrEn (weightRAMwrEn),
.weightDataOut (weightData),
.pipelineLock (pipelineLock),
.sdramBusy (sdramBusy),
.sdramRXValid (sdramRXValid),
.sdramDataRX (sdramDataRX),
.sdramDataTX (sdramDataTX),
.sdramAddr (sdramAddr),
.sdramTXValid (sdramTXValid),
.sdramRW (sdramRW),
.LED (led)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; vector<string> s(n); for (long long i = 0; i < n; i++) cin >> s[i]; vector<long long> g[n * n]; for (long long i = 0; i < n; i++) for (long long j = 0; j < n; j++) { if (i + 1 < n) g[i * n + j].push_back((i + 1) * n + j); if (j + 1 < n) g[i * n + j].push_back(i * n + (j + 1)); } vector<long long> kval(n * n); vector<char> cval(n * n); vector<char> cval2(n * n); for (long long i = 0; i < n; i++) for (long long j = 0; j < n; j++) { cval[i * n + j] = s[i][j]; cval2[i * n + j] = s[i][j]; } kval[0] = k; if (cval[0] != a && kval[0]) { cval[0] = a ; kval[0] -= 1; } string ans; queue<long long> q; ans += cval[0]; q.push(0); while (q.size()) { set<long long> tq; long long maxkval = 0; char mincval = z ; while (q.size()) { long long x = q.front(); q.pop(); for (auto y : g[x]) { tq.insert(y); if (kval[x]) { kval[y] = max(kval[y], kval[x] - (cval[y] != a )); cval2[y] = a ; } maxkval = max(maxkval, kval[y]); mincval = min(mincval, cval2[y]); } } ans += mincval; for (auto v : tq) if (cval2[v] == mincval) q.push(v); } cout << ans.substr(0, 2 * n - 1) << n ; } |
#include <bits/stdc++.h> #pragma GCC optimize(3, Ofast , inline ) using namespace std; const long long maxn = (long long)4e5 + 5; const long long mod = 1000000007; const long long inf = 0x3f3f3f3f; long long a[maxn], b[maxn], n, ans; bool cal(long long L, long long R) { long long sum = 0; for (long long i = n, l = 1, r = 1; i >= 1; --i) { while (l <= n && b[i] + b[l] < L) ++l; while (r <= n && b[i] + b[r] <= R) ++r; sum += r - l - (l <= i && i < r); } return (sum >> 1) & 1; } bool solve(long long k) { for (long long i = 1; i <= n; ++i) b[i] = a[i] & ((1 << (k + 1)) - 1); sort(b + 1, b + n + 1); return cal(1 << k, (1 << (k + 1)) - 1) ^ cal(3 << k, (1 << (k + 2)) - 2); } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i <= n; ++i) cin >> a[i]; for (long long i = 0; i <= 30; ++i) ans |= solve(i) << i; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007; const long long int inf = 0x3f3f3f3f3f3f3f3fLL; const double eps = 1e-9; const double PI = acos(-1); long long int i, j, k; void solve(void); inline bool equal(double a, double b) { return fabs(a - b) < eps; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(10); int t = 1; while (t--) solve(); return 0; } void solve() { int n, a, b, T; cin >> n >> a >> b >> T; char c[n]; for (i = (0); i <= (n - 1); ++i) cin >> c[i]; int lo = 1, hi = n, mid, ans = 0, left[n], right[n]; left[0] = right[0] = 1 + (c[0] == w ? b : 0); for (i = (1); i <= (n - 1); ++i) left[i] = left[i - 1] + a + (c[n - i] == w ? b : 0) + 1; for (i = (1); i <= (n - 1); ++i) right[i] = right[i - 1] + a + (c[i] == w ? b : 0) + 1; while (lo <= hi) { mid = (lo + hi) >> 1; bool pos = 0; for (i = (mid - 1); i >= (0); --i) { long long int time1 = right[i] + left[mid - i - 1] - left[0] + i * a; if (time1 <= T) pos = 1; long long int time2 = left[i] + right[mid - i - 1] - right[0] + i * a; if (time2 <= T) pos = 1; } if (pos) { ans = ((ans) > (mid) ? (ans) : (mid)); lo = mid + 1; } else hi = mid - 1; } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, InfI = INT_MAX, Mod = 998244353; const long long InfL = LONG_LONG_MAX; int n, m, sqn; vector<int> adj[N]; vector<int> ind; bool vis[N] = {}, indpen[N] = {}; int ent[N], par[N], back_edge[N], back_min[N]; int dfstimer = 0, idma = 1; void dfs(int x) { vis[x] = 1; ent[x] = dfstimer++; int back_edg = 0, back_mi = x; bool pen = 1; for (int v : adj[x]) { if (!vis[v]) { par[v] = x; dfs(v); } else if (ent[v] < ent[x]) { back_edg++; back_mi = (ent[v] < ent[back_mi]) ? v : back_mi; } if (indpen[v]) pen = 0; } back_edge[x] = back_edg; back_min[x] = back_mi; idma = (back_edg > back_edge[idma]) ? x : idma; if (back_edg < sqn - 1 && pen) { ind.push_back(x); indpen[x] = 1; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; sqn = ceil(sqrt(1.0 * n)); for (int i = 1; i <= m; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } back_edge[1] = 0; dfs(1); if (back_edge[idma] >= sqn - 1) { cout << 2 << endl; vector<int> path; int j = idma; path.push_back(j); while (j != back_min[idma]) { j = par[j]; path.push_back(j); } cout << path.size() << endl; for (int i : path) cout << i << ; return 0; } cout << 1 << endl; for (int i = 0; i < sqn; i++) cout << ind[i] << ; } |
#include <bits/stdc++.h> using namespace std; int a[100][100], n, row[55][100005], col[55][100005]; bool valid(int i, int j) { for (int k = 0; k < n; k++) { if (k == i) continue; int x = a[i][j] - a[k][j]; if (x > 0 && row[i][x] && (x != a[i][j] || row[i][x] > 1)) return 1; } return 0; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { scanf( %d , &a[i][j]); row[i][a[i][j]]++; col[j][a[i][j]]++; } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (a[i][j] != 1 && !valid(i, j)) { printf( No n ); return 0; } printf( Yes n ); } |
#include <bits/stdc++.h> using namespace std; int a[10]; int main() { int n; while (~scanf( %d , &n)) { memset(a, 0, sizeof(a)); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); printf( %d n , a[(1 + n) / 2]); } } |
#include <bits/stdc++.h> using namespace std; template <class T> ostream &operator<<(ostream &out, const vector<T> &data) { out << [ ; for (int i = 0; i < data.size(); ++i) out << data[i] << (i == data.size() - 1 ? : , ); out << ] ; return out; } template <class T> ostream &operator<<(ostream &out, const set<T> &s) { out << { ; for (typename set<T>::iterator itr = s.begin(); itr != s.end(); ++itr) out << *itr << ; out << } ; return out; } template <class T> ostream &operator<<(ostream &out, const multiset<T> &s) { out << { ; for (typename multiset<T>::iterator itr = s.begin(); itr != s.end(); ++itr) out << *itr << ; out << } ; return out; } template <class T1, class T2> ostream &operator<<(ostream &out, const pair<T1, T2> &p) { out << ( << p.first << , << p.second << ) ; return out; } template <class T1, class T2> ostream &operator<<(ostream &out, const map<T1, T2> &m) { for (typename map<T1, T2>::const_iterator itr = m.begin(); itr != m.end(); ++itr) out << itr->first << -> << itr->second << ; return out; } const double eps = 1e-6; const double pi = acos(-1.0); const double INF = 1e20; inline int sign(double d) { return d < -eps ? -1 : d > eps; } inline double sqr(double x) { return x * x; } struct Point { int id; double x, y; Point() { x = 0.0; y = 0.0; } Point(double nx, double ny) : x(nx), y(ny) {} Point turnLeft() const { return Point(-y, x); } Point turnRight() const { return Point(y, -x); } Point rotate(double ang) const { return Point(x * cos(ang) - y * sin(ang), x * sin(ang) + y * cos(ang)); } inline double length() { return sqrt(x * x + y * y); } void normalize() { double r = length(); if (sign(r) != 0) x /= r, y /= r; } inline bool equal(const Point &other) const { return sign(x - other.x) == 0 && sign(y - other.y) == 0; } friend ostream &operator<<(ostream &out, const Point &point) { out << ( << point.x << , << point.y << ) ; return out; } friend istream &operator>>(istream &in, Point &point) { in >> point.x >> point.y; return in; } }; bool comPointByX(const Point &a, const Point &b) { return a.x < b.x; } bool comPointEqual(const Point &a, const Point &b) { return a.equal(b); } inline Point operator+(const Point &a, const Point &b) { return Point(a.x + b.x, a.y + b.y); } inline Point operator-(const Point &a, const Point &b) { return Point(a.x - b.x, a.y - b.y); } inline Point operator*(const Point &a, double d) { return Point(a.x * d, a.y * d); } inline Point operator/(const Point &a, double d) { if (sign(d) == 0) return Point(); return Point(a.x / d, a.y / d); } inline bool operator==(const Point &a, const Point &b) { return a.x == b.x && a.y == b.y; } inline bool operator!=(const Point &a, const Point &b) { return a.x != b.x || a.y != b.y; } inline double dist(const Point &a, const Point &b) { return sqrt(sqr(a.x - b.x) + sqr(a.y - b.y)); } inline double sqrdist(const Point &a, const Point &b) { return sqr(a.x - b.x) + sqr(a.y - b.y); } inline double operator^(const Point &a, const Point &b) { return a.x * b.y - a.y * b.x; } inline double cross(const Point &p, const Point &a, const Point &b) { return (a - p) ^ (b - p); } inline double operator*(const Point &a, const Point &b) { return a.x * b.x + a.y * b.y; } inline double dot(const Point &p, const Point &a, const Point &b) { return (a - p) * (b - p); } inline double segDegree(const Point &p, const Point &a, const Point &b) { double d = dot(p, a, b); double cosd = d / dist(a, p) / dist(b, p); if (cosd > 1.0) cosd = 1.0; if (cosd < -1.0) cosd = -1.0; return acos(cosd); } inline double segDegree(double a, double b, double c) { double ret = a * a + b * b - c * c; ret = ret / a / b / 2; if (ret > 1.0) ret = 1.0; if (ret < -1.0) ret = -1.0; return acos(ret); } inline double triangleArea(double a, double b, double c) { double p = (a + b + c) / 2; return sqrt(p * (p - a) * (p - b) * (p - c)); } inline bool onSeg(const Point &p, const Point &a, const Point &b) { return (sign(cross(p, a, b)) == 0 && sign(dot(p, a, b)) <= 0); } inline bool onRay(const Point &p, const Point &a, const Point &b) { return (sign(cross(p, a, b)) == 0 && sign(dot(a, p, b)) >= 0); } inline bool onLine(const Point &p, const Point &a, const Point &b) { return sign(cross(p, a, b)) == 0; } pair<Point, Point> onLine(double A, double B, double C) { if (sign(A) == 0) return make_pair(Point(0, -C / B), Point(1, -C / B)); if (sign(B) == 0) return make_pair(Point(-C / A, 0), Point(-C / A, 1)); if (fabs(A + B + C) < eps) return make_pair(Point(-(C + B) / A, 1), Point(2, -(C + A * 2) / B)); return make_pair(Point(-(C + B) / A, 1), Point(1, -(C + A) / B)); } vector<Point> interLine(const Point &a, const Point &b, const Point &c, const Point &d) { vector<Point> inters; double u = cross(a, c, b), v = cross(a, b, d); if (sign(u + v) == 0) return inters; Point p = (c * v + d * u) / (u + v); inters.push_back(p); return inters; } vector<Point> interSeg(const Point &a, const Point &b, const Point &c, const Point &d) { vector<Point> inters = interLine(a, b, c, d); if (inters.size() == 0) return inters; const Point &p = inters[0]; if (onSeg(p, a, b) && onSeg(p, c, d)) return inters; else { inters.clear(); return inters; } } pair<Point, Point> getVerticalEquallySegment(const Point &a, const Point &b) { Point mid = (a + b) / 2; Point dir = mid - a; dir = dir.turnLeft(); Point begin = mid - dir; Point end = mid + dir; return make_pair(begin, end); } Point getMinimumDistPointOnLine(const Point &a, const Point &b, const Point &p) { if (onLine(p, a, b)) return p; pair<Point, Point> vertical = getVerticalEquallySegment(a, b); const Point &q = p + (vertical.second - vertical.first); vector<Point> inter = interLine(a, b, p, q); return inter[0]; } Point getMinimumDistPointOnSeg(const Point &a, const Point &b, const Point &p) { Point q = getMinimumDistPointOnLine(a, b, p); if (onSeg(q, a, b)) return q; if (dist(a, p) < dist(b, p)) return a; else return b; } Point getMinimumDistPointOnRay(const Point &a, const Point &b, const Point &p) { Point q = getMinimumDistPointOnLine(a, b, p); if (onRay(q, a, b)) return q; if (dist(a, p) < dist(b, p)) return a; else return b; } Point getReflectionPointByLine(const Point &a, const Point &b, const Point &p) { Point q = getMinimumDistPointOnLine(a, b, p); return q * 2 - p; } vector<Point> interCir(const Point &a, const Point &b, double r1, double r2) { vector<Point> ret; double d = dist(a, b), d1 = ((sqr(r1) - sqr(r2)) / d + d) / 2; if (sign(r1 + r2 - d) < 0 || sign(abs(r1 - r2) - d) > 0) return ret; Point mid = a + ((b - a) / d) * d1; if (sign(r1 + r2 - d) == 0) { ret.push_back(mid); return ret; } Point incr = (b - a).turnLeft() / d * sqrt(sqr(r1) - sqr(d1)); ret.push_back(mid - incr); ret.push_back(mid + incr); return ret; } double interCirArea(Point a, Point b, double ra, double rb) { double d, dA, dB; d = dist(a, b); if ((d < eps) || (d + ra <= rb) || (d + rb <= ra)) return sqr((rb < ra) ? rb : ra) * pi; if (d >= ra + rb) return 0; dA = (sqr(d) + sqr(ra) - sqr(rb)) / d / 2; dB = d - dA; return sqr(ra) * acos(dA / ra) - dA * sqrt(sqr(ra) - sqr(dA)) + sqr(rb) * acos(dB / rb) - dB * sqrt(sqr(rb) - sqr(dB)); } vector<Point> interLineCir(const Point &o, double r, const Point &a, const Point &b) { vector<Point> ret; double d = dist(a, b), h = fabs(cross(a, b, o)) / d; if (sign(r - h) < 0) return ret; double d1 = ((sqr(dist(o, a)) - sqr(dist(o, b))) / d + d) / 2; Point mid = a + (b - a) / d * d1; if (sign(r - h) == 0) { ret.push_back(mid); return ret; } Point incr = (b - a) / d * sqrt(sqr(r) - sqr(h)); ret.push_back(mid - incr); ret.push_back(mid + incr); return ret; } vector<Point> interSegCir(const Point &o, double r, const Point &a, const Point &b) { vector<Point> temp = interLineCir(o, r, a, b); vector<Point> ret; for (int i = 0; i < temp.size(); ++i) if (onSeg(temp[i], a, b)) ret.push_back(temp[i]); return ret; } vector<Point> tangentCirPoint(const Point &o, double r, const Point &a) { vector<Point> ret; double d = dist(a, o); if (sign(d - r) < 0) return ret; if (sign(r - d) == 0) { ret.push_back(a); return ret; } return interCir(o, a, r, sqrt(sqr(d) - sqr(r))); } inline bool inCircle(const Point &p, const pair<Point, double> &circle) { double dis = dist(p, circle.first); return sign(dis - circle.second) <= 0; } double distOnCircle(const Point &a, const Point &b, const Point &o, double r) { double costheta = (a - o) * (b - o) / r / r; double theta = acos(costheta); return r * theta; } pair<Point, double> minCoverCircle(const Point &a, const Point &b, const Point &c) { if (a.equal(b)) return make_pair((b + c) / 2, dist(b, c) / 2); if (b.equal(c)) return make_pair((c + a) / 2, dist(c, a) / 2); if (c.equal(a)) return make_pair((a + b) / 2, dist(a, b) / 2); if (onLine(a, b, c)) { if (onSeg(a, b, c)) return make_pair((b + c) / 2, dist(b, c) / 2); if (onSeg(b, a, c)) return make_pair((a + c) / 2, dist(a, c) / 2); return make_pair((a + b) / 2, dist(a, b) / 2); } pair<Point, double> minCircle; minCircle.second = INF; pair<Point, double> cir1 = make_pair((a + b) / 2, dist(a, b) / 2); pair<Point, double> cir2 = make_pair((b + c) / 2, dist(b, c) / 2); pair<Point, double> cir3 = make_pair((a + c) / 2, dist(a, c) / 2); if (inCircle(c, cir1) && cir1.second < minCircle.second) minCircle = cir1; if (inCircle(a, cir2) && cir2.second < minCircle.second) minCircle = cir2; if (inCircle(b, cir3) && cir3.second < minCircle.second) minCircle = cir3; Point mid1 = (a + b) / 2; Point mid2 = (b + c) / 2; Point turn1 = (b - a).turnLeft(); Point turn2 = (c - b).turnLeft(); turn1 = mid1 + turn1; turn2 = mid2 + turn2; vector<Point> inters = interLine(mid1, turn1, mid2, turn2); pair<Point, double> cir4 = make_pair(inters[0], dist(inters[0], a)); if (cir4.second < minCircle.second) minCircle = cir4; return minCircle; } double getCircleTriangleInterArea(const Point &o, double r, const Point &a, const Point &b) { vector<Point> abcir = interSegCir(o, r, a, b); if (abcir.size() == 2 && dist(a, abcir[0]) > dist(a, abcir[1])) swap(abcir[0], abcir[1]); abcir.insert(abcir.begin(), a); abcir.push_back(b); double ret = 0; for (int i = 0; i < abcir.size() - 1; ++i) { Point &t1 = abcir[i]; Point &t2 = abcir[i + 1]; if (inCircle((t1 + t2) / 2, make_pair(o, r))) ret += fabs(cross(o, t1, t2) / 2); else ret += segDegree(o, t1, t2) * r * r * 0.5; } return ret; } class Polygon { public: vector<Point> pt; inline void clear() { pt.clear(); } inline int size() const { return (int)pt.size(); } inline void addPoint(Point a) { pt.push_back(a); } inline void removePoint() { pt.pop_back(); } inline Point &operator[](int offset) { return pt[offset]; } inline void getSeg(int offset, Point &a, Point &b) { a = pt[offset]; b = pt[(offset + 1) % pt.size()]; } int inside(const Point &p) { int N = (int)pt.size(); bool positiveSign = false; bool negativeSign = false; for (int i = 0; i < N; ++i) { Point &now = pt[i]; Point &next = pt[(i + 1) % N]; Point t1 = next - now; Point t2 = p - next; int s = sign(t1 ^ t2); if (s == 0) { if (onSeg(p, now, next)) return 0; else return -1; } if (s > 0) positiveSign = true; if (s < 0) negativeSign = true; } if (positiveSign && negativeSign) return -1; else return 1; } double interCirArea(const Point &o, double r) { int N = (int)pt.size(); double ret = 0; for (int i = 0; i < N; ++i) { Point &now = pt[i]; Point &next = pt[(i + 1) % N]; double area = getCircleTriangleInterArea(o, r, now, next); if (cross(now, next, o) >= 0) ret += area; else ret -= area; } return ret; } int interCircle(const Point &o, double r, vector<Point> &inters) { inters.clear(); bool ok = true; for (int i = 0; i < pt.size(); ++i) if (!inCircle(pt[i], make_pair(o, r))) ok = false; if (ok) return 1; if (inside(o) == 1) { double mindis = 1e20; for (int i = 0; i < pt.size(); ++i) { Point a = pt[i]; Point b = pt[(i + 1) % pt.size()]; Point p = getMinimumDistPointOnSeg(a, b, o); mindis = min(mindis, dist(p, o)); } if (mindis >= r) return 2; } for (int i = 0; i < pt.size(); ++i) { Point a = pt[i]; Point b = pt[(i + 1) % pt.size()]; vector<Point> ps = interSegCir(o, r, a, b); inters.insert(inters.end(), ps.begin(), ps.end()); } return inters.size() > 0 ? 3 : 4; } Point getMinDistPointInPolygon(const Point &p) { if (inside(p) >= 0) return p; int N = (int)pt.size(); double minDis = INF; Point ret; for (int i = 0; i < N; ++i) { Point &a = pt[i]; Point &b = pt[(i + 1) % N]; Point nowMin = getMinimumDistPointOnSeg(a, b, p); double nowDis = dist(nowMin, p); if (nowDis < minDis) minDis = nowDis, ret = nowMin; } return ret; } Polygon cut(const Point &a, const Point &b) { Polygon newPoly; Point temp; for (unsigned int i = 0; i < pt.size(); i++) { Point &nowP = pt[i]; Point &nextP = pt[(i + 1) % pt.size()]; if (sign(cross(a, b, nowP)) <= 0) newPoly.addPoint(nowP); if (sign(cross(a, b, nowP)) * sign(cross(a, b, nextP)) < 0) { vector<Point> inters = interLine(nowP, nextP, a, b); if (inters.size() > 0) newPoly.addPoint(inters[0]); } } return newPoly; } vector<Point> polyInterLine(const Point &a, const Point &b) { int N = (int)pt.size(); vector<Point> ret; Point temp; for (int i = 0; i < N; ++i) { Point &now = pt[i]; Point &next = pt[(i + 1) % N]; if (sign(cross(a, b, now)) * sign(cross(a, b, next)) <= 0) { vector<Point> inters = interLine(a, b, now, next); if (inters.size() > 0) ret.push_back(inters[0]); } } return ret; } double area() { int size = this->size(); if (size <= 2) return 0.0; addPoint(this->pt[0]); double ans = 0; for (int i = 0; i < size; ++i) ans += (pt[i] ^ pt[i + 1]); removePoint(); return fabs(ans / 2); } double length() { int size = this->size(); addPoint(pt[0]); double ans = 0; for (int i = 0; i < size; ++i) ans += dist(pt[i], pt[i + 1]); removePoint(); return ans; } pair<Point, Point> getDiameter() { if (this->size() == 0) return make_pair(Point(0, 0), Point(0, 0)); if (this->size() == 1) return make_pair(pt[0], pt[0]); if (this->size() == 2) return make_pair(pt[0], pt[1]); pair<Point, Point> answer; double diameter = 0.0; for (unsigned int i = 0; i < pt.size(); ++i) for (unsigned int j = i + 1; j < pt.size(); ++j) { double now = sqrdist(pt[i], pt[j]); if (now > diameter) { diameter = now; answer = make_pair(pt[i], pt[j]); } } return answer; } pair<Point, double> getMinCoverCircle() { vector<Point> &points = pt; if (points.size() == 0) return make_pair(Point(0, 0), 0); if (points.size() == 1) return make_pair(points[0], 0); if (points.size() == 2) return make_pair((points[0] + points[1]) / 2, dist(points[0], points[1]) / 2); Point a = points[0]; Point b = points[1]; Point c = points[2]; pair<Point, double> nowCircle = minCoverCircle(a, b, c); while (true) { bool found = false; double maxDis = nowCircle.second; Point maxDisPoint; for (unsigned int i = 0; i < points.size(); ++i) { double dis = dist(points[i], nowCircle.first); if (sign(dis - maxDis) > 0) { maxDis = dis; maxDisPoint = points[i]; found = true; } } if (!found) break; Point d = maxDisPoint; Point newa, newb, newc; pair<Point, double> cir1 = minCoverCircle(a, b, d); pair<Point, double> cir2 = minCoverCircle(a, c, d); pair<Point, double> cir3 = minCoverCircle(b, c, d); pair<Point, double> minCircle; minCircle.second = INF; if (inCircle(c, cir1) && cir1.second < minCircle.second) { minCircle = cir1; c = d; } else { if (inCircle(b, cir2) && cir2.second < minCircle.second) { minCircle = cir2; b = d; } else { if (inCircle(a, cir3) && cir3.second < minCircle.second) { minCircle = cir3; a = d; } } } nowCircle = minCircle; } return nowCircle; } friend ostream &operator<<(ostream &out, const Polygon &poly) { int size = poly.size(); for (int i = 0; i < size; ++i) out << poly.pt[i] << t ; return out; } }; bool comPs(const pair<Point, int> &a, const pair<Point, int> &b) { int s = sign(a.first.x - b.first.x); if (s < 0) return true; if (s > 0) return false; return a.second < b.second; } double unionArea(vector<Polygon> &polys) { double ans = 0; int N = (int)polys.size(); if (N == 0) return ans; vector<pair<double, double> > lines; for (int i = 0; i < N; ++i) for (int j = 0; j < polys[i].size(); ++j) { Point a, b; polys[i].getSeg(j, a, b); if (fabs(a.x - b.x) < eps) continue; double deg = atan2(b.y - a.y, b.x - a.x); double bb = a.y - (b.y - a.y) * a.x / (b.x - a.x); bool close = false; for (int k = 0; k < lines.size(); ++k) if (fabs(lines[k].first - deg) < eps && fabs(lines[k].second - bb) < eps) close = true; if (close) continue; lines.push_back(make_pair(deg, bb)); vector<pair<Point, int> > ps; for (int k = 0; k < N; ++k) { bool isPar = false; for (int l = 0; l < polys[k].size(); ++l) { Point c, d; polys[k].getSeg(l, c, d); if (fabs(c.x - d.x) < eps) continue; if (onLine(c, a, b) && onLine(d, a, b)) { int dir = (c.x < d.x) ? 2 : 1; if (c.x > d.x) swap(c, d); ps.push_back(make_pair(c, dir * 2)); ps.push_back(make_pair(d, dir * 2 + 1)); isPar = true; break; } } if (isPar) continue; vector<Point> inters; for (int l = 0; l < polys[k].size(); ++l) { Point c, d; polys[k].getSeg(l, c, d); vector<Point> t = interLine(a, b, c, d); for (int z = 0; z < t.size(); ++z) if (onSeg(t[z], c, d)) inters.push_back(t[z]); } sort(inters.begin(), inters.end(), comPointByX); inters.resize(unique(inters.begin(), inters.end(), comPointEqual) - inters.begin()); if (inters.size() >= 2) { ps.push_back(make_pair(inters.front(), 0)); ps.push_back(make_pair(inters.back(), 1)); } } sort(ps.begin(), ps.end(), comPs); int cntPosi = 0, cntNega = 0; int cntIn = 0; for (int k = 0; k < ps.size(); ++k) { double x2 = ps[k].first.x; double y2 = ps[k].first.y; double x1 = 0, y1 = 0; if (k > 0) { x1 = ps[k - 1].first.x; y1 = ps[k - 1].first.y; } double area = (x2 - x1) * (y2 + y1) / 2; if (cntPosi > 0 && cntNega == 0 && x2 - x1 > eps && cntIn == 0) ans += area; if (cntPosi == 0 && cntNega > 0 && x2 - x1 > eps && cntIn == 0) ans -= area; int id = ps[k].second; if (id == 2) cntPosi++; if (id == 4) cntNega++; if (id == 0) cntIn++; if (id == 3) cntPosi--; if (id == 5) cntNega--; if (id == 1) cntIn--; } } return ans; } struct ConvexHull { static inline bool cmp(const Point &a, const Point &b) { return a.y < b.y || (a.y == b.y && a.x < b.x); } static Polygon convexHull(const vector<Point> &points, bool needInnerEdgePoint = false) { vector<Point> p(points.begin(), points.end()); vector<int> stack(p.size() + 1); Polygon poly; poly.clear(); if (p.size() == 0) return poly; if (p.size() == 1) { poly.addPoint(points[0]); return poly; } sort(p.begin(), p.end(), ConvexHull::cmp); int threshold = 0; if (needInnerEdgePoint) threshold = 1; int N = (int)p.size(); int top = -1; stack[++top] = 0; stack[++top] = 1; for (int i = 2; i < N; i++) { while (top >= 1 && sign(cross(p[stack[top - 1]], p[i], p[stack[top]])) >= threshold) top--; stack[++top] = i; } int temp_top = top; stack[++top] = N - 2; for (int i = N - 3; i >= 0; i--) { while (top >= temp_top + 1 && sign(cross(p[stack[top - 1]], p[i], p[stack[top]])) >= threshold) top--; stack[++top] = i; } for (int i = 0; i < top; ++i) poly.addPoint(p[stack[i]]); return poly; } }; class HalfPlanes { public: Polygon poly; HalfPlanes(double maxRange) { poly.addPoint(Point(-maxRange, -maxRange)); poly.addPoint(Point(maxRange, -maxRange)); poly.addPoint(Point(maxRange, maxRange)); poly.addPoint(Point(-maxRange, maxRange)); } void intersect(const Point &a, const Point &b) { poly = poly.cut(a, b); } void intersect(double A, double B, double C) { pair<Point, Point> ab = onLine(A, B, C); pair<Point, Point> cd = getVerticalEquallySegment(ab.first, ab.second); Point a = ab.first, b = ab.second, c = cd.first, d = cd.second; double vc = A * c.x + B * c.y + C; if (vc > 0) { if (sign(cross(a, b, c)) > 0) swap(a, b); } else { if (sign(cross(a, b, d)) > 0) swap(a, b); } poly = poly.cut(a, b); } void intersect(const Point &a, const Point &b, const Point &c) { if (sign(cross(a, b, c)) <= 0) poly = poly.cut(a, b); else poly = poly.cut(b, a); } }; class Voronoy { public: vector<Point> ps; vector<HalfPlanes> planes; Voronoy(vector<Point> &points, double maxRange) { int N = (int)points.size(); ps = points; planes.resize(N, HalfPlanes(maxRange)); for (int i = 0; i < N; ++i) for (int j = i + 1; j < N; ++j) { pair<Point, Point> v = getVerticalEquallySegment(ps[i], ps[j]); planes[i].intersect(v.first, v.second, ps[i]); planes[j].intersect(v.first, v.second, ps[j]); } } }; struct Point3D { double x, y, z; Point3D() {} Point3D(double xx, double yy, double zz) { x = xx; y = yy; z = zz; } double len() { return sqrt(x * x + y * y + z * z); } }; Point3D operator+(const Point3D &a, const Point3D &b) { return Point3D(a.x + b.x, a.y + b.y, a.z + b.z); } Point3D operator-(const Point3D &a, const Point3D &b) { return Point3D(a.x - b.x, a.y - b.y, a.z - b.z); } double dist(const Point3D &a, const Point3D &b) { return sqrt(sqr(a.x - b.x) + sqr(a.y - b.y) + sqr(a.z - b.z)); } double dot(const Point3D &a, const Point3D &b) { return a.x * b.x + a.y * b.y + a.z * b.z; } Point3D cross(const Point3D &u, const Point3D &v) { Point3D ret; ret.x = u.y * v.z - v.y * u.z; ret.y = u.z * v.x - u.x * v.z; ret.z = u.x * v.y - u.y * v.x; return ret; } Point3D planeVector(const Point3D &a, const Point3D &b, const Point3D &c) { return cross(a - b, b - c); } double distToPlane(const Point3D &p, const Point3D &s1, const Point3D &s2, const Point3D &s3) { Point3D plane = planeVector(s1, s2, s3); return dot(plane, p - s1) / plane.len(); } Point ps[4]; Point a, b, c, d; class State { public: double x, y, z; State operator+(const State &other) { State ret; ret.x = x + other.x; ret.y = y + other.y; ret.z = z + other.z; return ret; } State operator-(const State &other) { State ret; ret.x = x - other.x; ret.y = y - other.y; ret.z = z - other.z; return ret; } State operator*(double k) { State ret; ret.x = x * k; ret.y = y * k; ret.z = z * k; return ret; } friend ostream &operator<<(ostream &out, const State &state) { out << state.x << << state.y << << state.z; return out; } }; double func(const State &s) { Point p(s.x, s.y); double ret = dist(Point(0, 0), p); ret += dist(getMinimumDistPointOnLine(c, d, p), p); return ret; } class GoldSplitSearch { public: static State findMinimum(State &begin, State &end, double (*func)(const State &s)) { const double tou = (sqrt(5.0) - 1) / 2; State a = begin; State b = end; for (int k = 0; k < 200; ++k) { State x1 = a + (b - a) * (1 - tou); State x2 = a + (b - a) * tou; double f1 = func(x1); double f2 = func(x2); if (f1 > f2) a = x1; else b = x2; } return a; } }; double getAns(Point aa, Point bb, Point cc, Point dd) { c = cc; d = dd; double scale = 100000 / (bb - aa).length(); Point na = (aa - bb) * scale + bb; Point nb = (bb - aa) * scale + aa; State begin; begin.x = na.x; begin.y = na.y; State end; end.x = nb.x; end.y = nb.y; State s = GoldSplitSearch::findMinimum(begin, end, func); return func(s); } int N; vector<Polygon> polys; void init() { double ans = 0; cin >> N; polys.clear(); for (int i = 0; i < N; ++i) { vector<Point> ps(4); for (int j = 0; j < 4; ++j) cin >> ps[j]; Polygon poly = ConvexHull::convexHull(ps); polys.push_back(poly); ans += poly.area(); } ans = ans / (unionArea(polys)); printf( %.10f n , ans); } void york() {} int main() { init(); york(); return 0; } |
// This modules defines a DPI interface for a counter that can be read
// periodically using DPI
`include "bsg_defines.v"
module bsg_nonsynth_dpi_cycle_counter
#(
parameter int width_p = 1
,parameter bit debug_p = 0
)
(
input clk_i
,input reset_i
,output logic [width_p-1:0] ctr_r_o
,output logic debug_o
);
export "DPI-C" function bsg_dpi_init;
export "DPI-C" function bsg_dpi_fini;
export "DPI-C" function bsg_dpi_debug;
export "DPI-C" function bsg_dpi_width;
export "DPI-C" function bsg_dpi_cycle_counter_read;
export "DPI-C" function bsg_dpi_cycle_counter_is_window;
// Tracks whether init has been called
logic init_l;
// Print module parameters to the console and set the intial debug
// value.
initial begin
$display("BSG INFO: bsg_nonsynth_dpi_cycle_counter (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: width_p = %d", width_p);
$display("BSG INFO: debug_p = %d", debug_p);
end
bsg_cycle_counter
#(.width_p(width_p)
,.init_val_p('0))
counter_inst
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ctr_r_o(ctr_r_o));
// We track the polarity of the current edge so that we can notify
// the user of incorrect behavior.
logic edgepol;
always_ff @(posedge clk_i or negedge clk_i) begin
edgepol <= clk_i;
end
// Initialize this Module
function void bsg_dpi_init();
if(init_l)
$fatal(1, "BSG ERROR (%M): init() already called");
init_l = 1;
endfunction
// Terminate this Module
function void bsg_dpi_fini();
if(~init_l)
$fatal(1, "BSG ERROR (%M): fini() already called");
init_l = 0;
endfunction
// Set or unset the debug_o output bit. If a state change occurs
// (0->1 or 1->0) then module will print DEBUG ENABLED / DEBUG
// DISABLED. No messages are printed if a state change does not
// occur.
function void bsg_dpi_debug(input bit switch_i);
if(!debug_o & switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG ENABLED", $time);
else if (debug_o & !switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG DISABLED", $time);
debug_o = switch_i;
endfunction
// Returns width_p
function int bsg_dpi_width();
return width_p;
endfunction
// The function bsg_dpi returns true if the interface is in a
// valid time-window to call bsg_dpi_fifo_rx()
function bit bsg_dpi_cycle_counter_is_window();
return (clk_i & edgepol & ~reset_i);
endfunction
// Read and return the current counter value.
function void bsg_dpi_cycle_counter_read(output bit [width_p-1:0] data_bo);
if(init_l === 0) begin
$fatal(1,"BSG ERROR (%M): read() called before init()");
end
if(reset_i === 1) begin
$fatal(1, "BSG ERROR (%M): read() called while reset_i === 1");
end
if(clk_i === 0) begin
$fatal(1, "BSG ERROR (%M): read() must be called when clk_i == 1");
end
if(edgepol === 0) begin
$fatal(1, "BSG ERROR (%M): read() must be called after the positive edge of clk_i has been evaluated");
end
data_bo = ctr_r_o;
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { bool ok = 0; int res = 0; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; if (c == - ) ok = 1; else res = c - 48; while ((c = getchar()) >= 0 && c <= 9 ) res = (res << 3) + (res << 1) + (c - 48); return ok ? ~res + 1 : res; } const int N = 4e5, M = 4e5; int h[N], net[M], go[M], val[M], dep[N], ecnt = 1, cap[M]; void add(int u, int v, int w) { go[++ecnt] = v; cap[ecnt] = w; net[ecnt] = h[u]; h[u] = ecnt; swap(u, v); go[++ecnt] = v; cap[ecnt] = 0; net[ecnt] = h[u]; h[u] = ecnt; } int s, t, n, m; int bfs() { memset(dep, 0, sizeof(dep)); queue<int> q; q.push(s); dep[s] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int e = h[u]; e; e = net[e]) { int v = go[e]; if (!dep[v] && cap[e]) { dep[v] = dep[u] + 1; q.push(v); } } } return dep[t]; } int dfs(int u, int flow) { if (u == t) return flow; int res = 0, tot = 0; for (int e = h[u]; e; e = net[e]) { int v = go[e]; if (dep[v] == dep[u] + 1 && cap[e]) { res = dfs(v, min(flow, cap[e])); tot += res; cap[e] -= res; cap[e ^ 1] += res; flow -= res; } } if (tot == 0) dep[u] = 0; return tot; } int a[100000], v[100000]; int g; int main() { int cntg = 0; int sum = 0; int sum1 = 0; s = N - 2; t = N - 1; n = read(); m = read(); g = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) { v[i] = read(); if (a[i] == 0) sum -= v[i], add(s, i, v[i]), sum1 += v[i]; else add(i, t, v[i]); } for (int i = 1, w, k, u, op; i <= m; i++) { op = read(); w = read(); k = read(); while (k--) { u = read(); if (op) add(u, i + n, 1e9); else add(i + n, u, 1e9); } int newop = read(); if (op == 0 && newop == 1) sum -= g; if (op == 0) add(s, i + n, w + (newop ? g : 0)), sum1 += w + (newop ? g : 0); else add(i + n, t, w + (newop ? g : 0)); if (op == 1) sum += w; } int ans = 0; int res = 0; while (bfs()) { ans += dfs(s, 1e9); } printf( %d n , sum + sum1 - ans); return 0; } |
module uart_ctrl(wr, trx_req, trx_ack, trx,
clr, clk);
// Entrades
input [6:0] wr;
input trx_req;
input clr, clk;
// Sortides
output reg trx_ack, trx;
// Registres
reg [7:0] et, etrx;
reg [6:0] data_wr;
// Algorisme de transmissi�
always @(negedge clk)
if (clr)
begin
et <= 8'd00;
etrx <= 8'd00;
trx <= 1'b1;
trx_ack <= 1'b0;
end
else
case (et)
8'd00: if (trx_req) et <= 8'd05;
8'd05:
if (~trx_req)
begin et <= 8'd00; etrx <= 8'd00; end
else
case (etrx)
8'd00: begin data_wr <= wr; trx <= 1'b1; etrx <= 8'd05; end
8'd05: begin trx <= 1'b0; etrx <= 8'd10; end // Start bit
8'd10: begin trx <= data_wr[0]; etrx <= 8'd15; end
8'd15: begin trx <= data_wr[1]; etrx <= 8'd20; end
8'd20: begin trx <= data_wr[2]; etrx <= 8'd25; end
8'd25: begin trx <= data_wr[3]; etrx <= 8'd30; end
8'd30: begin trx <= data_wr[4]; etrx <= 8'd35; end
8'd35: begin trx <= data_wr[5]; etrx <= 8'd40; end
8'd40: begin trx <= data_wr[6]; etrx <= 8'd45; end
8'd45: begin trx <= 1'b0; etrx <= 8'd50; end
8'd50: begin trx_ack <= 1'b1; trx <= 1'b1; etrx <= 8'd00; et <= 8'd10; end
endcase
8'd10: if (~trx_req) begin trx_ack <= 1'b0; et <= 8'd00; end
endcase
endmodule |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = 3e5 + 10; template <typename value_t> class fenwick { public: fenwick(int n) { memset(c, 0, sizeof c); this->n = n; } void add(int i, value_t x) { while (i <= n) { c[i] += x; i += Lowbit(i); } } value_t sum(int x) { value_t sum = 0; while (x > 0) { sum += c[x]; x -= Lowbit(x); } return sum; } value_t sum(int x1, int x2) { return sum(x2) - sum(x1 - 1); } private: value_t c[MAXN]; int n; inline int Lowbit(int x) { return x & (-x); } }; class lfs { public: lfs(int N) { memset(head, -1, sizeof head); ecnt = 0; n = N; } void adde(int from, int to, int w) { e[ecnt].to = to; e[ecnt].w = w; e[ecnt].next = head[from]; head[from] = ecnt++; } void addde(int a, int b, int w) { adde(a, b, w); adde(b, a, w); } void solve() { memset(ans, 0, sizeof ans); arr = new fenwick<long long>(n); dfs(1, 0, 1); } vector<pair<int, int>> opr[MAXN]; long long ans[MAXN]; protected: struct Edge { int to, next, w; } e[MAXN * 2]; int head[MAXN]; int ecnt; int n; fenwick<long long>* arr; void dfs(int u, int fa, int dep) { for (auto& i : opr[u]) { arr->add(dep, i.second); arr->add(dep + i.first + 1, -i.second); } ans[u] = arr->sum(dep); for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].to; if (v != fa) dfs(v, u, dep + 1); } for (auto& i : opr[u]) { arr->add(dep, -i.second); arr->add(dep + i.first + 1, i.second); } } }; template <typename T = int> inline T read() { T X = 0, w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) { X = (X << 3) + (X << 1) + (ch ^ 48); ch = getchar(); } return w ? -X : X; } int main() { int n = read(); lfs* tree = new lfs(n); for (int i = 1; i < n; i++) { tree->addde(read(), read(), 1); } int m = read(); for (int i = 1; i <= m; i++) { int u = read(); int d = read(); int x = read(); tree->opr[u].push_back(make_pair(d, x)); } tree->solve(); for (int i = 1; i <= n; i++) { cout << tree->ans[i] << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; pair<long long, int> ar[200003 + 2]; long long DP[200003 + 2][2]; long long n; long long dp(int i, bool fl) { if (i == n + 1) { if (fl == 0) return 0; return 2e18; } if (i > n + 1) return 2e18; long long &ret = DP[i][fl]; if (ret != -1) return ret; ret = 2e18; if (fl == 0) ret = min(ret, -ar[i].first + dp(i + 2, 1)); else { ret = min(ret, dp(i + 1, 1)); ret = min(ret, +ar[i].first + dp(i + 1, 0)); } return ret; } int team[200003 + 2]; long long res; int cnt = 0; void print(int i, bool fl) { if (i == n + 1) return; if (fl == 0) { res += ar[i].first; team[ar[i].second] = ++cnt; team[ar[i + 1].second] = cnt; print(i + 2, 1); } else { long long kop = dp(i + 1, 1); if (kop == res) { team[ar[i].second] = cnt; print(i + 1, 1); } else { team[ar[i].second] = cnt; res -= ar[i].first; print(i + 1, 0); } } } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> ar[i].first; ar[i].second = i; } sort(ar + 1, ar + n + 1); memset(DP, -1, sizeof DP); res = dp(1, 0); long long ans = res; print(1, 0); cout << ans << << cnt << endl; for (int i = 1; i <= n; i++) { if (i > 1) cout << ; cout << team[i]; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, a, b, k, p[N]; int main() { cin >> n >> a >> b >> k; int sum = a + b; for (int i = 1; i <= n; i++) { cin >> p[i]; if (p[i] % sum == 0) p[i] = sum; else p[i] %= sum; p[i] -= a; } int ans = 0; sort(p + 1, p + 1 + n); for (int i = 1; i <= n; i++) { if (p[i] <= 0) ans++; else { int t = ceil(p[i] * 1.0 / a); if (t <= k) k -= t, ans++; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Tp> inline void read(Tp& x) { x = 0; int f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } int buf[22]; template <typename Tp> inline void write(Tp x) { int p = 0; if (x < 0) { putchar( - ); x = -x; } if (x == 0) buf[++p] = 0; else while (x) { buf[++p] = x % 10; x /= 10; } for (int i = p; i; i--) putchar( 0 + buf[i]); } int m, b; int main() { scanf( %d%d , &m, &b); long long int ans = 0; for (int y = 0; y <= b; y++) { int x = m * (b - y); ans = max(ans, 1ll * (1 + x) * (1 + y) * (x + y) / 2); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int mod = 1e9 + 7; long long int powmod(long long int a, long long int b) { long long int res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } int nxt() { int x; scanf( %d , &x); return x; } vector<string> type; vector<vector<int> > edge; vector<bool> ans; void dfs(int u) { if (type[u] == IN ) { ans[u] = edge[u][0]; return; } if (type[u] == NOT ) { dfs(edge[u][0]); ans[u] = !ans[edge[u][0]]; return; } dfs(edge[u][0]); dfs(edge[u][1]); if (type[u] == AND ) { ans[u] = ans[edge[u][0]] & ans[edge[u][1]]; } if (type[u] == OR ) { ans[u] = ans[edge[u][0]] | ans[edge[u][1]]; } if (type[u] == XOR ) { ans[u] = ans[edge[u][0]] ^ ans[edge[u][1]]; } } void dfs2(int u, vector<int>& a) { if (type[u] == IN ) { a.push_back(u); return; } if (type[u] == NOT ) { dfs2(edge[u][0], a); return; } bool l = ans[edge[u][0]]; bool r = ans[edge[u][1]]; int x = edge[u][0]; int y = edge[u][1]; if (type[u] == AND ) { if (!l && r) { dfs2(x, a); } if (l && !r) { dfs2(y, a); } if (l && r) { dfs2(x, a); dfs2(y, a); } } if (type[u] == OR ) { if (!r && !l) { dfs2(x, a); dfs2(y, a); } if (!l && r) { dfs2(y, a); } if (l && !r) { dfs2(x, a); } } if (type[u] == XOR ) { dfs2(x, a); dfs2(y, a); } } int main() { int n = nxt(); type.resize(n); edge.resize(n); ans.resize(n); vector<int> q; for (int i = 0; i < n; i++) { cin >> type[i]; if (type[i] == IN ) { edge[i].push_back(nxt()); q.push_back(i); } else if (type[i] == NOT ) { edge[i].push_back(nxt() - 1); } else { edge[i].push_back(nxt() - 1); edge[i].push_back(nxt() - 1); } } dfs(0); vector<int> req; dfs2(0, req); set<int> s; for (int x : req) s.insert(x); for (int x : q) { if (s.count(x)) printf( %d , ans[0] ^ 1 ? 1 : 0); else printf( %d , ans[0] ? 1 : 0); } return 0; } |
#include <bits/stdc++.h> using namespace std; int p[110]; int main() { int n, cnt; cin >> n; for (int i = 0; i < n; i++) cin >> p[i]; string s; getline(cin, s); for (int i = 0; i < n; i++) { cnt = 0; getline(cin, s); for (int j = 0; j < s.size(); j++) if (s[j] == a || s[j] == e || s[j] == i || s[j] == o || s[j] == u || s[j] == y ) cnt++; if (cnt != p[i]) { cout << NO ; return 0; } } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, T, t[1005] = {0}, v; int main() { std::ios::sync_with_stdio(false); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &v); t[v]++; } scanf( %d , &T); int ans = 0, sum = 0; for (int i = 1; i <= 1000; i++) { sum += t[i]; if (i > T + 1) sum -= t[i - T - 1]; if (sum > ans) ans = sum; } printf( %d n , ans); return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2011 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Rounding "macro"
// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation)
module round_tb();
localparam IW=8;
localparam OW=4;
localparam EW=IW-OW+1;
reg signed [IW-1:0] in;
wire signed [OW-1:0] out;
wire signed [EW-1:0] err;
round #(.bits_in(IW),
.bits_out(OW),
.round_to_zero(0), // original behavior
.round_to_nearest(1), // lowest noise
.trunc(0)) // round to negative infinity
round (.in(in),.out(out),.err(err));
initial $dumpfile("round_tb.vcd");
initial $dumpvars(0,round_tb);
wire signed [IW-1:0] out_round = {out,{IW-OW{1'b0}}};
initial
begin
in <= -129;
#1;
repeat (260)
begin
in <= in + 1;
#1;
$display("In %d, out %d, out_rnd %d, err %d, real err %d",in,out,out_round,-err,out_round-in);
#1;
end
$finish;
end
endmodule // round
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_4_V
`define SKY130_FD_SC_HDLL__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A31O_FUNCTIONAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a31o (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n; string ss; int dp[200005][4]; char s[] = { R , G , B }; int calc(int u, int c) { if (u == n) return 0; if (dp[u][c] != -1) return dp[u][c]; int ret = n; for (int i = 0; i < 3; i++) { if (i == c) continue; if (s[i] == ss[u]) ret = min(ret, calc(u + 1, i)); else ret = min(ret, 1 + calc(u + 1, i)); } return dp[u][c] = ret; } void print(int u, int c) { if (u == n) return; for (int i = 0; i < 3; i++) { if (i == c) continue; if (s[i] == ss[u]) { if (dp[u][c] == calc(u + 1, i)) { printf( %c , s[i]); print(u + 1, i); return; } } else { if (dp[u][c] == 1 + calc(u + 1, i)) { printf( %c , s[i]); print(u + 1, i); return; } } } } int main() { memset(dp, -1, sizeof dp); cin >> n; cin >> ss; int ans = calc(0, 3); cout << ans << endl; print(0, 3); return 0; } |
// Testbench for WS2812 driver.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
`timescale 1ns/1ps
module ws2812_tb;
reg rst;
reg clk;
wire [8:0] address;
reg [7:0] r;
reg [7:0] g;
reg [7:0] b;
wire strip_o;
ws2812 #(.LED_COUNT(8), .REVERSE(0)) uut (
.rst_i(rst),
.clk_i(clk),
.address_o(address),
.r_i(r),
.g_i(g),
.b_i(b),
.data_o(strip_o)
);
initial
begin
rst = 1;
clk = 0;
r = 0;
g = 0;
b = 0;
#100 rst = 0;
end
always
#10 clk = !clk;
always @(posedge clk) begin
if (rst == 0) begin
r <= address;
g <= address + 100;
b <= address + 200;
end
end
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ()
//
// Brief Description:
// Simple-dual-port block memory (using Altera block memory).
// 2-cycle pipeline delay on reads.
//
//------------------------------------------------------------------------------
`ifndef _ZL_SDP_RAM_V_
`define _ZL_SDP_RAM_V_
module zl_sdp_ram #
(
parameter Write_data_width = 0,
parameter Write_addr_width = 0,
parameter Read_data_width = 0,
parameter Read_addr_width = 0
)
(
input clk_wr,
input clk_rd,
//
input [Write_addr_width-1:0] wr_addr,
input [Write_data_width-1:0] wr_data,
input wr_en,
//
input [Read_addr_width-1:0] rd_addr,
output [Read_data_width-1:0] rd_data
);
altsyncram #
(
.address_aclr_b("NONE"),
.address_reg_b("CLOCK1"),
.clock_enable_input_a("BYPASS"),
.clock_enable_input_b("BYPASS"),
.clock_enable_output_b("BYPASS"),
.intended_device_family("Cyclone IV E"),
.lpm_type("altsyncram"),
.numwords_a(2**Write_addr_width),
.numwords_b(2**Read_addr_width),
.operation_mode("DUAL_PORT"),
.outdata_aclr_b("NONE"),
.outdata_reg_b("CLOCK1"),
.power_up_uninitialized("FALSE"),
.ram_block_type("M9K"),
.widthad_a(Write_addr_width),
.widthad_b(Read_addr_width),
.width_a(Write_data_width),
.width_b(Read_data_width),
.width_byteena_a(1)
)
altsyncram_component
(
.address_a (wr_addr),
.clock0 (clk_wr),
.data_a (wr_data),
.wren_a (wr_en),
.address_b (rd_addr),
.clock1 (clk_rd),
.q_b (rd_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
endmodule // zl_sdp_ram
`endif // _ZL_SDP_RAM_V_
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A311O_BEHAVIORAL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_BEHAVIORAL_V |
//#############################################################################
//# Purpose: SPI top (configurable as master or slave) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi #( parameter AW = 32, // address width
parameter PW = 104, // packet size
parameter UREGS = 13 // number of user slave regs
)
(//clk, reset, irq
input nreset, // asynch active low reset
input clk, // core clock
input hw_en, // block enable pin
output spi_irq, // interrupt output
//packet from core
input access_in, // access from core
input [PW-1:0] packet_in, // packet from core
input wait_in, // pushback from io
//packet to core
output access_out, // access to core
output [PW-1:0] packet_out, // packet to core
output wait_out, // pushback from core
//master io interface
output m_sclk, // master clock
output m_mosi, // master output
output m_ss, // slave select
input m_miso, // master input
//slave io interface
input s_sclk, // slave clock
input s_mosi, // slave input
input s_ss, // slave select
output s_miso // slave output
);
//1. set manual_CS mode
//2. assert ss (0000)
//4. write to tx fifo
//6. deassert ss (1111)
//###############
//# LOCAL WIRES
//###############
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire m_access_out; // From spi_master of spi_master.v
wire [PW-1:0] m_packet_out; // From spi_master of spi_master.v
wire m_wait_out; // From spi_master of spi_master.v
wire s_access_out; // From spi_slave of spi_slave.v
wire [PW-1:0] s_packet_out; // From spi_slave of spi_slave.v
wire [511:0] s_spi_regs; // From spi_slave of spi_slave.v
wire s_wait_out; // From spi_slave of spi_slave.v
// End of automatics
//###########################################################
//# SPI SLACE
//###########################################################
/*spi_master AUTO_TEMPLATE (.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.\(.*\)_in (\1_in[]),
.\(.*\) (m_\1[]),
);
*/
spi_master #(.AW(AW),
.PW(PW))
spi_master (/*AUTOINST*/
// Outputs
.sclk (m_sclk), // Templated
.mosi (m_mosi), // Templated
.ss (m_ss), // Templated
.wait_out (m_wait_out), // Templated
.access_out (m_access_out), // Templated
.packet_out (m_packet_out[PW-1:0]), // Templated
// Inputs
.clk (clk), // Templated
.nreset (nreset), // Templated
.hw_en (hw_en), // Templated
.miso (m_miso), // Templated
.access_in (access_in), // Templated
.packet_in (packet_in[PW-1:0]), // Templated
.wait_in (wait_in)); // Templated
//###########################################################
//# SPI SLAVE
//###########################################################
/*spi_slave AUTO_TEMPLATE (.clk (clk),
.spi_irq (spi_irq),
.nreset (nreset),
.hw_en (hw_en),
.\(.*\)_in (\1_in[]),
.\(.*\) (s_\1[]),
);
*/
spi_slave #(.AW(AW),
.PW(PW),
.UREGS(UREGS))
spi_slave (/*AUTOINST*/
// Outputs
.spi_regs (s_spi_regs[511:0]), // Templated
.spi_irq (spi_irq), // Templated
.miso (s_miso), // Templated
.access_out (s_access_out), // Templated
.packet_out (s_packet_out[PW-1:0]), // Templated
.wait_out (s_wait_out), // Templated
// Inputs
.clk (clk), // Templated
.nreset (nreset), // Templated
.hw_en (hw_en), // Templated
.sclk (s_sclk), // Templated
.mosi (s_mosi), // Templated
.ss (s_ss), // Templated
.wait_in (wait_in), // Templated
.access_in (access_in), // Templated
.packet_in (packet_in[PW-1:0])); // Templated
//###########################################################
//# EMESH MUX
//###########################################################
assign wait_out = s_wait_out | m_wait_out;
emesh_mux #(.N(2),
.AW(AW),
.PW(PW))
emesh_mux (// Outputs
.wait_out (),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.access_in ({s_access_out,m_access_out}),
.packet_in ({s_packet_out[PW-1:0],m_packet_out[PW-1:0]}),
.wait_in (wait_in)
);
endmodule // spi
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; long long const MAXN = 5e1 + 8; long long const INF = 3e3 + 8; long long const delta = 1000000007; long long a[MAXN]; long long dp[MAXN][MAXN][INF]; double calc(long long t, long long n, long long b) { double ans = t; for (long long i = b + 1; i <= n; i++) ans /= (double)i; for (long long i = 1; i <= n - b; i++) ans *= (double)i; return ans; } int main() { std::ios::sync_with_stdio(0); ; cin.tie(0); cout.tie(0); long long n; cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; long long p; cin >> p; cout.precision(10); cout << fixed; double ans = 0; dp[0][0][0] = 1; for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= n; j++) { for (long long k = 0; k < INF; k++) { dp[i][j][k] = dp[i - 1][j][k]; if (j && k >= a[i]) dp[i][j][k] += dp[i - 1][j - 1][k - a[i]]; } } } for (long long i = 1; i <= p; i++) { for (long long j = 1; j <= n; j++) ans += calc(dp[n][j][i], n, j); } cout << ans; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 12:45:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_xlconstant_0_3 -prefix
// system_xlconstant_0_3_ system_xlconstant_0_3_sim_netlist.v
// Design : system_xlconstant_0_3
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module system_xlconstant_0_3
(dout);
output [9:0]dout;
wire \<const0> ;
wire \<const1> ;
assign dout[9] = \<const0> ;
assign dout[8] = \<const0> ;
assign dout[7] = \<const0> ;
assign dout[6] = \<const0> ;
assign dout[5] = \<const0> ;
assign dout[4] = \<const1> ;
assign dout[3] = \<const0> ;
assign dout[2] = \<const1> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module UART(
clk_x4,
rst_x,
// UART interfaces
i_rx,
o_tx,
// Control interfaces
i_data,
i_valid,
o_busy,
o_data,
o_valid,
// Error interfaces
o_tx_error,
o_rx_error);
input clk_x4;
input rst_x;
input i_rx;
output o_tx;
input [7:0] i_data;
input i_valid;
output o_busy;
output [7:0] o_data;
output o_valid;
output o_tx_error;
output o_rx_error;
SerialTransmitter tx(
.clk_x4 (clk_x4 ),
.rst_x (rst_x ),
.i_data (i_data ),
.i_valid(i_valid ),
.o_tx (o_tx ),
.o_busy (o_busy ),
.o_error(o_tx_error));
SerialReceiver rx(
.clk_x4 (clk_x4 ),
.rst_x (rst_x ),
.i_rx (i_rx ),
.o_data (o_data ),
.o_valid(o_valid ),
.o_error(o_rx_error));
endmodule // SerialTransmitter
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { while (a && b) a > b ? a %= b : b %= a; return a + b; } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } int main() { int n; cin >> n; int i, j, sum = 0, in; int a[n]; for (i = 0; i < n; ++i) { cin >> a[i]; sum += a[i]; } int x = n / 2; int avg = sum / x; for (i = 0; i < n; i++) { if (a[i] == 0) continue; cout << i + 1 << ; for (j = i + 1; j < n; j++) { if (a[j] == 0) continue; if ((a[j] + a[i]) == avg) { cout << j + 1 << ; a[j] = 0; a[i] = 0; break; } } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; short c1[25001], c2[25001]; int a[12][12]; int main() { int n, m, res = 0; cin >> n >> m; char c; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> c; if (c == W ) a[i][j] = 2; else if (c == P ) a[i][j] = 1; else a[i][j] = 0; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (a[i][j] == 2) { if (a[max(i - 1, 0)][j] == 1) { res++; a[max(i - 1, 0)][j] = 0; continue; } if (a[i][max(j - 1, 0)] == 1) { a[i][max(j - 1, 0)] = 0; res++; continue; } if (a[i + 1][j] == 1) { res++; a[i + 1][j] = 0; continue; } if (a[i][j + 1] == 1) { a[i][j + 1] = 0; res++; } } cout << res; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:46:53 01/13/2015
// Design Name:
// Module Name: auxOut_select
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module auxOut_select(
input clk,
input FONT5_detect,
input auxOutA,
input auxOutB,
(* IOB = "TRUE" *) output reg auxOutA1,
(* IOB = "TRUE" *) output reg auxOutB1,
(* IOB = "TRUE" *) output reg auxOutA2,
(* IOB = "TRUE" *) output reg auxOutB2
);
(* IOB = "TRUE" *) reg FONT5_detect_a;
reg FONT5_detect_b;
always @(posedge clk) begin
FONT5_detect_a <= FONT5_detect;
FONT5_detect_b <= FONT5_detect_a;
auxOutA1 <= (FONT5_detect_b) ? auxOutA : 1'bz;
auxOutB1 <= (FONT5_detect_b) ? auxOutB : 1'bz;
auxOutA2 <= (FONT5_detect_b) ? 1'bz : ~auxOutA; // NB: auxOuts on FONT5A boards use inverting buffers
auxOutB2 <= (FONT5_detect_b) ? 1'bz : ~auxOutB; // NB: auxOuts on FONT5A boards use inverting buffers
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_8_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64 // LFSR shift register length
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_soc_interface_wb_8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg output_axis_tready = 0;
reg [7:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire [35:0] wb_adr_o;
wire [7:0] wb_dat_o;
wire wb_we_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
output_axis_tready,
wb_dat_i,
wb_ack_i,
wb_err_i);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
wb_adr_o,
wb_dat_o,
wb_we_o,
wb_stb_o,
wb_cyc_o,
busy);
// dump file
$dumpfile("test_soc_interface_wb_8.lxt");
$dumpvars(0, test_soc_interface_wb_8);
end
soc_interface_wb_8
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
// WB interface
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
// status
.busy(busy)
);
endmodule
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone register
*/
module wb_async_reg #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
// master side
input wire wbm_clk,
input wire wbm_rst,
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
// slave side
input wire wbs_clk,
input wire wbs_rst,
output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address
input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
output wire wbs_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
output wire wbs_stb_o, // STB_O strobe output
input wire wbs_ack_i, // ACK_I acknowledge input
input wire wbs_err_i, // ERR_I error input
input wire wbs_rty_i, // RTY_I retry input
output wire wbs_cyc_o // CYC_O cycle output
);
reg [ADDR_WIDTH-1:0] wbm_adr_i_reg = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i_reg = 0;
reg [DATA_WIDTH-1:0] wbm_dat_o_reg = 0;
reg wbm_we_i_reg = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i_reg = 0;
reg wbm_stb_i_reg = 0;
reg wbm_ack_o_reg = 0;
reg wbm_err_o_reg = 0;
reg wbm_rty_o_reg = 0;
reg wbm_cyc_i_reg = 0;
reg wbm_done_sync1 = 0;
reg wbm_done_sync2 = 0;
reg wbm_done_sync3 = 0;
reg [ADDR_WIDTH-1:0] wbs_adr_o_reg = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i_reg = 0;
reg [DATA_WIDTH-1:0] wbs_dat_o_reg = 0;
reg wbs_we_o_reg = 0;
reg [SELECT_WIDTH-1:0] wbs_sel_o_reg = 0;
reg wbs_stb_o_reg = 0;
reg wbs_ack_i_reg = 0;
reg wbs_err_i_reg = 0;
reg wbs_rty_i_reg = 0;
reg wbs_cyc_o_reg = 0;
reg wbs_cyc_o_sync1 = 0;
reg wbs_cyc_o_sync2 = 0;
reg wbs_cyc_o_sync3 = 0;
reg wbs_stb_o_sync1 = 0;
reg wbs_stb_o_sync2 = 0;
reg wbs_stb_o_sync3 = 0;
reg wbs_done_reg = 0;
assign wbm_dat_o = wbm_dat_o_reg;
assign wbm_ack_o = wbm_ack_o_reg;
assign wbm_err_o = wbm_err_o_reg;
assign wbm_rty_o = wbm_rty_o_reg;
assign wbs_adr_o = wbs_adr_o_reg;
assign wbs_dat_o = wbs_dat_o_reg;
assign wbs_we_o = wbs_we_o_reg;
assign wbs_sel_o = wbs_sel_o_reg;
assign wbs_stb_o = wbs_stb_o_reg;
assign wbs_cyc_o = wbs_cyc_o_reg;
// master side logic
always @(posedge wbm_clk) begin
if (wbm_rst) begin
wbm_adr_i_reg <= 0;
wbm_dat_i_reg <= 0;
wbm_dat_o_reg <= 0;
wbm_we_i_reg <= 0;
wbm_sel_i_reg <= 0;
wbm_stb_i_reg <= 0;
wbm_ack_o_reg <= 0;
wbm_err_o_reg <= 0;
wbm_rty_o_reg <= 0;
wbm_cyc_i_reg <= 0;
end else begin
if (wbm_cyc_i_reg & wbm_stb_i_reg) begin
// cycle - hold master
if (wbm_done_sync2 & ~wbm_done_sync3) begin
// end of cycle - store slave
wbm_dat_o_reg <= wbs_dat_i_reg;
wbm_ack_o_reg <= wbs_ack_i_reg;
wbm_err_o_reg <= wbs_err_i_reg;
wbm_rty_o_reg <= wbs_rty_i_reg;
wbm_we_i_reg <= 0;
wbm_stb_i_reg <= 0;
end
end else begin
// idle - store master
wbm_adr_i_reg <= wbm_adr_i;
wbm_dat_i_reg <= wbm_dat_i;
wbm_dat_o_reg <= 0;
wbm_we_i_reg <= wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
wbm_sel_i_reg <= wbm_sel_i;
wbm_stb_i_reg <= wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
wbm_ack_o_reg <= 0;
wbm_err_o_reg <= 0;
wbm_rty_o_reg <= 0;
wbm_cyc_i_reg <= wbm_cyc_i;
end
end
// synchronize signals
wbm_done_sync1 <= wbs_done_reg;
wbm_done_sync2 <= wbm_done_sync1;
wbm_done_sync3 <= wbm_done_sync2;
end
// slave side logic
always @(posedge wbs_clk) begin
if (wbs_rst) begin
wbs_adr_o_reg <= 0;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= 0;
wbs_we_o_reg <= 0;
wbs_sel_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= 0;
wbs_done_reg <= 0;
end else begin
if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
// end of cycle - store slave
wbs_dat_i_reg <= wbs_dat_i;
wbs_ack_i_reg <= wbs_ack_i;
wbs_err_i_reg <= wbs_err_i;
wbs_rty_i_reg <= wbs_rty_i;
wbs_we_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_done_reg <= 1;
end else if (wbs_stb_o_sync2 & ~wbs_stb_o_sync3) begin
// beginning of cycle - store master
wbs_adr_o_reg <= wbm_adr_i_reg;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= wbm_dat_i_reg;
wbs_we_o_reg <= wbm_we_i_reg;
wbs_sel_o_reg <= wbm_sel_i_reg;
wbs_stb_o_reg <= wbm_stb_i_reg;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= wbm_cyc_i_reg;
wbs_done_reg <= 0;
end else if (~wbs_cyc_o_sync2 & wbs_cyc_o_sync3) begin
// cyc deassert
wbs_adr_o_reg <= 0;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= 0;
wbs_we_o_reg <= 0;
wbs_sel_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= 0;
wbs_done_reg <= 0;
end
end
// synchronize signals
wbs_cyc_o_sync1 <= wbm_cyc_i_reg;
wbs_cyc_o_sync2 <= wbs_cyc_o_sync1;
wbs_cyc_o_sync3 <= wbs_cyc_o_sync2;
wbs_stb_o_sync1 <= wbm_stb_i_reg;
wbs_stb_o_sync2 <= wbs_stb_o_sync1;
wbs_stb_o_sync3 <= wbs_stb_o_sync2;
end
endmodule |
#include <bits/stdc++.h> using namespace std; const double SUCK = 999999999999999999.99; const int MX = 51 * 101; int n; int r; int f[55]; int s[55]; int p[55]; double cp[55]; double dp[55][MX]; bool isOk(double det) { for (int i = 0; i <= r; i++) { dp[n][i] = 0; } for (int i = n - 1; i >= 0; i--) { for (int j = 0; j <= r; j++) { dp[i][j] = det; double togo = 0; if (j + f[i] > r) { togo = det; } else { togo += cp[i] * (f[i] + dp[i + 1][j + f[i]]); if (j + s[i] > r) togo += (1 - cp[i]) * (s[i] + det); else togo += (1 - cp[i]) * (s[i] + dp[i + 1][j + s[i]]); } dp[i][j] = min(det, togo); } } if (dp[0][0] >= det) return false; return true; } const double eps = 0.000000001; time_t bg; double getTime() { time_t en = clock(); double ret = (double)(en - bg) / CLOCKS_PER_SEC; return ret; } double bsearch(double l, double r) { double m = (l + r) / 2; if (r - l < eps) return m; if (getTime() >= 1.95) return m; if (isOk(m)) return bsearch(l, m); else return bsearch(m, r); } int main() { bg = clock(); scanf( %d%d , &n, &r); for (int i = 0; i < n; i++) scanf( %d%d%d , &f[i], &s[i], &p[i]); for (int i = 0; i < n; i++) cp[i] = 0.010000 * p[i]; double ans = bsearch(n, 50000000); printf( %.12f , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; long long f = 1; for (long long i = 0; i < 100000; i++) { n += (n % m); if (n % m == 0) { f = 0; break; } } if (!f) cout << Yes << endl; else cout << No << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_TB_V
`define SKY130_FD_SC_HS__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 SCD = 1'b1;
#160 SCE = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 SCD = 1'b0;
#260 SCE = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SCE = 1'b1;
#380 SCD = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SCE = 1'bx;
#480 SCD = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_TB_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block1.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block1
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block1
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
//MATLAB Function 'Open_Loop_Control/Sin_Cos/Mark_Extract_Bits1/MATLAB Function': '<S38>:1'
// Non-tunable mask parameter
//'<S38>:1:8'
//'<S38>:1:10'
assign y = u[8:0];
//'<S38>:1:14'
endmodule // controllerHdl_MATLAB_Function_block1
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_axi_trn_bridge.v
// Version : 1.8
//
// Description : AXI - TRN Bridge for Root Port Model.
// Root Port Usrapp's require TRN interface.
//-----------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_axi_trn_bridge # (
parameter C_DATA_WIDTH = 64,
parameter RBAR_WIDTH = 7,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
)
(
// Common
input user_clk,
input user_reset,
input user_lnk_up,
// AXI TX
//-----------
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
output s_axis_tx_tvalid, // TX data is valid
input s_axis_tx_tready, // TX ready for data
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
output s_axis_tx_tlast, // TX data is last
output [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
output m_axis_rx_tready, // RX ready for data
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Usrapp I/O //
//---------------------------------------------//
// TRN TX
//-----------
input [C_DATA_WIDTH-1:0] trn_td, // TX data from usrapp
input trn_tsof, // TX start of packet
input trn_teof, // TX end of packet
input trn_tsrc_rdy, // TX source ready
output trn_tdst_rdy, // TX destination ready
input trn_tsrc_dsc, // TX source discontinue
input [REM_WIDTH-1:0] trn_trem, // TX remainder
input trn_terrfwd, // TX error forward
input trn_tstr, // TX streaming enable
input trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
output [C_DATA_WIDTH-1:0] trn_rd, // RX data to usrapp
output trn_rsof, // RX start of packet
output trn_reof, // RX end of packet
output trn_rsrc_rdy, // RX source ready
input trn_rdst_rdy, // RX destination ready
output reg trn_rsrc_dsc, // RX source discontinue
output [REM_WIDTH-1:0] trn_rrem, // RX remainder
output wire trn_rerrfwd, // RX error forward
output [RBAR_WIDTH-1:0] trn_rbar_hit // RX BAR hit
);
//DWORD Reordering between AXI and TRN interface//
generate begin:gen_axis_txdata
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32]};
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tdata = {trn_td[31:0],trn_td[63:32],trn_td[95:64],trn_td[127:96]};
end
end
endgenerate
//Coversion from trn_rem to s_axis_tkeep[7:0]//
generate begin: gen_axis_tx_tkeep
if (C_DATA_WIDTH == 64)
begin
assign s_axis_tx_tkeep = (trn_teof && ~trn_trem) ? 8'h0F : 8'hFF;
// always @*
// begin
// if (trn_teof && ~trn_trem) begin
// s_axis_tx_tkeep <= 8'h0F;
// end else begin
// s_axis_tx_tkeep <= 8'hFF;
// end
// end
end
else if (C_DATA_WIDTH == 128)
begin
assign s_axis_tx_tkeep = (trn_teof) ? ((trn_trem == 2'b11) ? 16'hFFFF :
((trn_trem == 2'b10) ? 16'h0FFF :
((trn_trem == 2'b01) ? 16'h00FF : 16'h000F ))) :
16'hFFFF;
// always @*
// begin
// if (trn_teof)
// begin
// case (trn_trem)
// 2'b11: begin s_axis_tx_tkeep <= 16'hFFFF; end
// 2'b10: begin s_axis_tx_tkeep <= 16'h0FFF; end
// 2'b01: begin s_axis_tx_tkeep <= 16'h00FF; end
// 2'b00: begin s_axis_tx_tkeep <= 16'h000F; end
// endcase
// end
// else
// begin
// s_axis_tx_tkeep <= 16'hFFFF;
// end
// end
end
end
endgenerate
//Connection of s_axis_tx_tuser with trn_tsrc_dsc,trn_tstr,trn_terr_fwd and trn_terr_fwd
assign s_axis_tx_tuser [3] = trn_tsrc_dsc;
assign s_axis_tx_tuser [2] = trn_tstr;
assign s_axis_tx_tuser [1] = trn_terrfwd;
assign s_axis_tx_tuser [0] = trn_tecrc_gen;
//Constraint trn_tsrc_rdy. If constrained, testbench keep trn_tsrc_rdy constantly asserted. This makes axi bridge to generate trn_tsof immeditely after trn_teof of previous packet.//
reg trn_tsrc_rdy_derived = 1'b0;
always @*
begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof)
begin
trn_tsrc_rdy_derived <= 1'b1;
end
else if(trn_tsrc_rdy_derived && trn_teof && trn_tsrc_rdy && trn_tdst_rdy)
begin
trn_tsrc_rdy_derived <= 1'b0;
end
end
assign s_axis_tx_tvalid = trn_tsrc_rdy_derived || trn_tsof || trn_teof;
assign trn_tdst_rdy = s_axis_tx_tready;
assign s_axis_tx_tlast = trn_teof;
assign m_axis_rx_tready = trn_rdst_rdy;
generate begin:gen_trn_rd
if (C_DATA_WIDTH == 64) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata[63:32]};
end else if (C_DATA_WIDTH == 128) begin
assign trn_rd = {m_axis_rx_tdata[31:0],m_axis_rx_tdata [63:32],m_axis_rx_tdata [95:64],m_axis_rx_tdata [127:96]};
end
end
endgenerate
//Regenerate trn_rsof
//Used clock. Latency may have been added
reg in_packet_reg;
generate begin:gen_trn_rsof
if (C_DATA_WIDTH == 64)
begin
always @(posedge user_clk)
begin
if (user_reset)
in_packet_reg <= 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready)
in_packet_reg <= ~m_axis_rx_tlast;
end
assign trn_rsof = m_axis_rx_tvalid & ~in_packet_reg;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rsof = m_axis_rx_tuser [14];
end
end
endgenerate
generate begin: gen_trn_reof
if (C_DATA_WIDTH == 64)
begin
assign trn_reof = m_axis_rx_tlast;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_reof = m_axis_rx_tuser[21]; //is_eof[4];
end
end
endgenerate
assign trn_rsrc_rdy = m_axis_rx_tvalid;
//Regenerate trn_rsrc_dsc
//Used clock. Latency may have been added
always @(posedge user_clk)
begin
if (user_reset)
trn_rsrc_dsc <= 1'b1;
else
trn_rsrc_dsc <= ~user_lnk_up;
end
wire [4:0] is_sof;
wire [4:0] is_eof;
assign is_sof = m_axis_rx_tuser[14:10];
assign is_eof = m_axis_rx_tuser[21:17];
generate begin:gen_trn_rrem
if (C_DATA_WIDTH == 64)
begin
assign trn_rrem = m_axis_rx_tlast ? (m_axis_rx_tkeep == 8'hFF) ? 1'b1 : 1'b0: 1'b1;
end
else if (C_DATA_WIDTH == 128)
begin
assign trn_rrem[0] = is_eof[2];
assign trn_rrem[1] = (is_eof[4] || is_sof[4] ) ? ( (is_sof[4] && is_eof[4] && is_eof[3]) || (!is_sof[4] && is_eof[4] && is_eof[3]) || (is_sof[4] && !is_eof[4] && !is_sof[3]) ) : 1'b1;
end
end
endgenerate
assign trn_rerrfwd = m_axis_rx_tuser[1];
assign trn_rbar_hit = m_axis_rx_tuser[8:2];
endmodule
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ()
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* spi_regs.v
* State machine which handles reading and writing from the test registers.
* Currently, the test bus width is hardcoded as 37 bits wide, generalize
* later.
* Autogenerated code from the register .csv definition file.
*/
module spi_reg(
// Register read signals
// INSERT_RD
// Register write signals
// INSERT_WR
// Inouts
vio_data_regs, io_success, vio_tbus,
// Inputs
i_rstb, i_clk_ext_osc, i_spi_active, vi_data_rx, i_rx_valid,
vi_byte_num);
// This global variable defines the number of registers
// INSERT_NUM_REG
// Global reset
input i_rstb;
// State machine clock
input i_clk_ext_osc;
// SPI interface
input i_spi_active;
input [7:0] vi_data_rx;
input i_rx_valid;
input [2:0] vi_byte_num;
inout [7:0] vio_data_regs;
// Test bus
inout io_success;
inout [36:0] vio_tbus;
// Register read and write controls
// INSERT_RD_DECLARATION
// INSERT_WR_DECLARATION
/*
* These vectors define the data mask for the test bus reads
*/
reg [7:0] rv_addr;
reg [36:0] rv_rd_mask;
always @( * ) begin
case ( rv_addr )
// INSERT_MASK
default : rv_rd_mask = {NUM_REGS{1'b0}};
endcase // case ( rv_addr )
end
/*
* These vectors define the number of bytes transmitted for the
* corresponding register. In the MSB register, unused bits are 0
* due to the data coming in the test bus being masked off.
*/
reg [NUM_REGS-1:0] rv_num_rd_bytes;
always @( * ) begin
case ( rv_addr )
// INSERT_NUM_BYTES
default : rv_num_rd_bytes = 0;
endcase // case ( rv_addr )
end
/*
* This register groups all the _rd wires into a single bus, such that
* rv_rd_bus[n] corresponds to the _rd wire associated with the register
* at address n.
*/
reg [NUM_REGS-1:0] rv_rd_tbus;
// INSERT_RD_BUS
/*
* This does the same for the _wr wires
*/
reg [NUM_REGS-1:0] rv_wr_tbus;
// INSERT_WR_BUS
/*
* Local reset
*/
wire active = i_rstb && i_spi_active;
/*
* This state machine simply captures the opcode on the arrival
* of the first (0th) byte, and enables the oscillator
*/
reg r_read_tbus;
reg r_write_tbus;
reg r_clamp_success;
always @( posedge i_rx_valid or negedge active ) begin : opcode_fsm
if ( !active ) begin
r_read_tbus <= 0;
r_write_tbus <= 0;
r_clamp_success <= 1;
end else begin
if ( 0 == vi_byte_num ) begin
if ( 128 == vi_data_rx ) begin
r_write_tbus <= 1;
r_clamp_success <= 0;
end
if ( 192 == vi_data_rx ) begin
r_read_tbus <= 1;
r_clamp_success <= 0;
end
end
end
end // block: opcode_fsm
assign io_success = r_clamp_success ? 1'b0 : 1'bz;
/*
* This state machine captures the address arriving on byte 1 regardless
* of whether the register interface is active or not.
*/
always @( posedge i_rx_valid or negedge active ) begin : address_fsm
if ( !active ) begin
rv_addr <= 0;
end else begin
if ( 1 == vi_byte_num )
rv_addr <= vi_data_rx;
end
end
/*
* This state machine handles register reads. When the address is loaded,
* ena_reg_read triggers the state machine clocked by the internal oscillator
* The data which is read from the test bus is then serialized out one
* byte at a time, from the LSB chunk to the MSB chunk.
* The shadow byte is initialized to an invalid value (7) which makes
* the output mux drive a 0.
*/
reg [2:0] rv_shadow_byte;
reg [7:0] rv_reg2spi;
reg r_ena_reg_read;
always @( posedge i_rx_valid or negedge active ) begin : read_fsm
if ( !active ) begin
rv_shadow_byte <= 7;
r_ena_reg_read <= 0;
end else begin
if (( 1 == vi_byte_num ) && r_read_tbus )
r_ena_reg_read <= 1;
if ( rv_num_rd_bytes >= vi_byte_num )
rv_shadow_byte <= vi_byte_num - 1;
else
rv_shadow_byte <= 7;
end
end
// The byte of the shadow register is addressed by the byte number
reg [36:0] rv_read_shadow;
always @( * ) begin
case ( rv_shadow_byte )
0 : rv_reg2spi = rv_read_shadow[7:0];
1 : rv_reg2spi = rv_read_shadow[15:8];
2 : rv_reg2spi = rv_read_shadow[23:16];
3 : rv_reg2spi = rv_read_shadow[31:24];
4 : rv_reg2spi = {3'b000,rv_read_shadow[36:32]};
default : rv_reg2spi = 0;
endcase // case ( rv_shadow_byte )
end
/*
* This state machine handles parallelizing the byte-widge chunks coming
* from the SPI into the full 37 bit test bus vector. When the parallel
* shadow bus is loaded, ena_reg_write is raised which initiates the state
* machine clocked by the internal oscillator.
*/
reg [36:0] rv_write_shadow;
reg r_ena_reg_write;
reg r_ser2par_done;
always @( posedge i_rx_valid or negedge active ) begin : write_fsm
if ( ! active ) begin
r_ena_reg_write <= 0;
r_ser2par_done <= 0;
rv_write_shadow <= 0;
end else begin
if ( !r_ser2par_done ) begin
// Serialize the data while the byte number is within the register size
if ( 2 == vi_byte_num )
rv_write_shadow[7:0] <= vi_data_rx;
if ( 3 == vi_byte_num )
rv_write_shadow[15:8] <= vi_data_rx;
if ( 4 == vi_byte_num )
rv_write_shadow[23:16] <= vi_data_rx;
if ( 5 == vi_byte_num )
rv_write_shadow[31:24] <= vi_data_rx;
if ( 6 == vi_byte_num )
rv_write_shadow[36:32] <= vi_data_rx[4:0];
if ( rv_num_rd_bytes < vi_byte_num ) begin
// When enough bytes are loaded, stop loading data
r_ser2par_done <= 1;
r_ena_reg_write <= r_write_tbus;
end
end
end
end
/*
* This state machine is clocked on the external oscillator. It
* sends the appropriate _rd signal, waits for the success line to go
* high, then latches the data on the test bus to the shadow register
*/
reg [1:0] rv_rd_state;
localparam READ_IDLE = 0;
localparam READ_WAIT = 1;
localparam READ_DONE = 2;
always @( posedge i_clk_ext_osc or negedge active ) begin
if ( !active ) begin
rv_read_shadow <= 0;
rv_rd_tbus <= 0;
rv_rd_state <= READ_IDLE;
end else begin
if (( READ_IDLE == rv_rd_state ) && r_ena_reg_read ) begin
// A read was just initiated, and we need to send the right _rd
rv_rd_tbus[rv_addr] <= 1;
rv_rd_state <= READ_WAIT;
end
if (( READ_WAIT == rv_rd_state ) && io_success ) begin
// The read had been initiated, and now data has appeared on the bus
rv_read_shadow <= vio_tbus & rv_rd_mask;
rv_rd_tbus <= 0;
rv_rd_state <= READ_DONE;
end
if ( READ_DONE == rv_rd_state ) begin
// Wait here forever until SPI goes inactive again
rv_rd_tbus <= 0;
rv_rd_state <= READ_DONE;
end
end
end
/*
* This state machine handles writing data to the register interface
*/
reg [1:0] rv_wr_state;
localparam WRITE_IDLE = 0;
localparam WRITE_WAIT = 1;
localparam WRITE_DONE = 2;
always @( posedge i_clk_ext_osc or negedge active ) begin
if ( !active ) begin
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_IDLE;
end else begin
if (( WRITE_IDLE == rv_wr_state ) && r_ena_reg_write ) begin
// A write was just initiated, now send the right _wr and wait
rv_wr_tbus[rv_addr] <= 1;
rv_wr_state <= WRITE_WAIT;
end
if (( WRITE_WAIT == rv_wr_state ) && io_success ) begin
// The success signal indicates the data on vio_tbus was latched in
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_DONE;
end
if ( WRITE_DONE == rv_wr_state ) begin
// Stay here until bus resets
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_DONE;
end
end
end
/*
* Tristate bus driver: drive the test bus when in register write mode,
* otherwise leave it floating.
*/
assign vio_tbus = r_write_tbus ? rv_write_shadow : 37'bz;
/*
* Tristate bus driver: only drive data back to SPI when we are in
* register read mode, otherwise float bus.
*/
assign vio_data_regs = r_read_tbus ? rv_reg2spi : 8'bz;
endmodule // spi_regs
|
#include <bits/stdc++.h> using namespace std; string ko(int k, int y) { string g = ; while (y > 0) { g = char(y % k + 48) + g; y = y / k; } return g; } int main() { int k; cin >> k; int i, j; for (i = 1; i <= k - 1; i++) { for (j = 1; j <= k - 1; j++) { cout << ko(k, i * j) << ; } cout << endl; } } |
`define LSU_SMRD_FORMAT 8'h01
`define LSU_DS_FORMAT 8'h02
`define LSU_MTBUF_FORMAT 8'h04
`define LSU_SMRD_IMM_POS 23
`define LSU_DS_GDS_POS 23
`define LSU_MTBUF_IDXEN_POS 12
`define LSU_MTBUF_OFFEN_POS 11
module lsu_addr_calculator(
in_vector_source_b,
in_scalar_source_a,
in_scalar_source_b,
in_opcode,
in_lds_base,
in_imm_value0,
out_ld_st_addr,
out_gm_or_lds
);
input [2047:0] in_vector_source_b;
input [127:0] in_scalar_source_a;
input [31:0] in_scalar_source_b;
input [31:0] in_opcode;
input [15:0] in_lds_base;
input [15:0] in_imm_value0;
output [2047:0] out_ld_st_addr;
output out_gm_or_lds;
`define ADD_TID_ENABLE in_scalar_source_a[119]
reg [63:0] out_exec_value;
reg [2047:0] out_ld_st_addr;
reg out_gm_or_lds;
wire [383:0] thread_id;
wire [2047:0] mtbuf_address;
wire [2047:0]ds_address;
always @(*)
begin
casex(in_opcode[31:24])
`LSU_SMRD_FORMAT:
begin
//Only 32 bits of the result is the address
//Other bits are ignored since exec mask is 64'd1
out_ld_st_addr <= in_scalar_source_a[47:0] + (in_opcode[`LSU_SMRD_IMM_POS] ? (in_imm_value0 * 4) : in_scalar_source_b);
out_gm_or_lds <= 1'b0;
end
`LSU_DS_FORMAT:
begin
out_ld_st_addr <= ds_address;
out_gm_or_lds <= 1'b1;
end
`LSU_MTBUF_FORMAT:
begin
// We suffer a architectural limitation here wherein we cannot support
// both an offset and index value as inputs into the address
// calculation, as that would require two vector register reads
// instead of the one that we currently do. Proposed future solution
// is to have the LSU be able to utilize two read ports to the VGPR to
// facilitate two reads in a cycle instead of just one.
out_ld_st_addr <= ({in_opcode[`LSU_MTBUF_IDXEN_POS],in_opcode[`LSU_MTBUF_OFFEN_POS]} == 2'b11) ? {2048{1'bx}} : mtbuf_address;
out_gm_or_lds <= 1'b0;
end
default:
begin
out_ld_st_addr <= {2048{1'bx}};
out_gm_or_lds <= 1'b0;
end
endcase
end
mtbuf_addr_calc mtbuf_address_calc[63:0](
.out_addr(mtbuf_address),
.vector_source_b(in_vector_source_b),
.scalar_source_a(in_scalar_source_a),
.scalar_source_b(in_scalar_source_b),
.imm_value0(in_imm_value0),
.idx_en(in_opcode[`LSU_MTBUF_IDXEN_POS]),
.off_en(in_opcode[`LSU_MTBUF_OFFEN_POS]),
.tid(thread_id)
);
ds_addr_calc ds_address_calc[63:0](
.lds_base(in_lds_base),
.in_addr(in_vector_source_b),
.out_addr(ds_address)
);
// %%start_veriperl
// my $i;
// my $high;
// my $low;
// for($i=0; $i<64; $i=$i+1)
// {
// $high = (($i+1)*6) - 1;
// $low = $i * 6;
// print "assign thread_id[$high:$low] = `ADD_TID_ENABLE ? 6'd$i : 6'd0;\n";
// }
// %%stop_veriperl
assign thread_id[5:0] = `ADD_TID_ENABLE ? 6'd0 : 6'd0;
assign thread_id[11:6] = `ADD_TID_ENABLE ? 6'd1 : 6'd0;
assign thread_id[17:12] = `ADD_TID_ENABLE ? 6'd2 : 6'd0;
assign thread_id[23:18] = `ADD_TID_ENABLE ? 6'd3 : 6'd0;
assign thread_id[29:24] = `ADD_TID_ENABLE ? 6'd4 : 6'd0;
assign thread_id[35:30] = `ADD_TID_ENABLE ? 6'd5 : 6'd0;
assign thread_id[41:36] = `ADD_TID_ENABLE ? 6'd6 : 6'd0;
assign thread_id[47:42] = `ADD_TID_ENABLE ? 6'd7 : 6'd0;
assign thread_id[53:48] = `ADD_TID_ENABLE ? 6'd8 : 6'd0;
assign thread_id[59:54] = `ADD_TID_ENABLE ? 6'd9 : 6'd0;
assign thread_id[65:60] = `ADD_TID_ENABLE ? 6'd10 : 6'd0;
assign thread_id[71:66] = `ADD_TID_ENABLE ? 6'd11 : 6'd0;
assign thread_id[77:72] = `ADD_TID_ENABLE ? 6'd12 : 6'd0;
assign thread_id[83:78] = `ADD_TID_ENABLE ? 6'd13 : 6'd0;
assign thread_id[89:84] = `ADD_TID_ENABLE ? 6'd14 : 6'd0;
assign thread_id[95:90] = `ADD_TID_ENABLE ? 6'd15 : 6'd0;
assign thread_id[101:96] = `ADD_TID_ENABLE ? 6'd16 : 6'd0;
assign thread_id[107:102] = `ADD_TID_ENABLE ? 6'd17 : 6'd0;
assign thread_id[113:108] = `ADD_TID_ENABLE ? 6'd18 : 6'd0;
assign thread_id[119:114] = `ADD_TID_ENABLE ? 6'd19 : 6'd0;
assign thread_id[125:120] = `ADD_TID_ENABLE ? 6'd20 : 6'd0;
assign thread_id[131:126] = `ADD_TID_ENABLE ? 6'd21 : 6'd0;
assign thread_id[137:132] = `ADD_TID_ENABLE ? 6'd22 : 6'd0;
assign thread_id[143:138] = `ADD_TID_ENABLE ? 6'd23 : 6'd0;
assign thread_id[149:144] = `ADD_TID_ENABLE ? 6'd24 : 6'd0;
assign thread_id[155:150] = `ADD_TID_ENABLE ? 6'd25 : 6'd0;
assign thread_id[161:156] = `ADD_TID_ENABLE ? 6'd26 : 6'd0;
assign thread_id[167:162] = `ADD_TID_ENABLE ? 6'd27 : 6'd0;
assign thread_id[173:168] = `ADD_TID_ENABLE ? 6'd28 : 6'd0;
assign thread_id[179:174] = `ADD_TID_ENABLE ? 6'd29 : 6'd0;
assign thread_id[185:180] = `ADD_TID_ENABLE ? 6'd30 : 6'd0;
assign thread_id[191:186] = `ADD_TID_ENABLE ? 6'd31 : 6'd0;
assign thread_id[197:192] = `ADD_TID_ENABLE ? 6'd32 : 6'd0;
assign thread_id[203:198] = `ADD_TID_ENABLE ? 6'd33 : 6'd0;
assign thread_id[209:204] = `ADD_TID_ENABLE ? 6'd34 : 6'd0;
assign thread_id[215:210] = `ADD_TID_ENABLE ? 6'd35 : 6'd0;
assign thread_id[221:216] = `ADD_TID_ENABLE ? 6'd36 : 6'd0;
assign thread_id[227:222] = `ADD_TID_ENABLE ? 6'd37 : 6'd0;
assign thread_id[233:228] = `ADD_TID_ENABLE ? 6'd38 : 6'd0;
assign thread_id[239:234] = `ADD_TID_ENABLE ? 6'd39 : 6'd0;
assign thread_id[245:240] = `ADD_TID_ENABLE ? 6'd40 : 6'd0;
assign thread_id[251:246] = `ADD_TID_ENABLE ? 6'd41 : 6'd0;
assign thread_id[257:252] = `ADD_TID_ENABLE ? 6'd42 : 6'd0;
assign thread_id[263:258] = `ADD_TID_ENABLE ? 6'd43 : 6'd0;
assign thread_id[269:264] = `ADD_TID_ENABLE ? 6'd44 : 6'd0;
assign thread_id[275:270] = `ADD_TID_ENABLE ? 6'd45 : 6'd0;
assign thread_id[281:276] = `ADD_TID_ENABLE ? 6'd46 : 6'd0;
assign thread_id[287:282] = `ADD_TID_ENABLE ? 6'd47 : 6'd0;
assign thread_id[293:288] = `ADD_TID_ENABLE ? 6'd48 : 6'd0;
assign thread_id[299:294] = `ADD_TID_ENABLE ? 6'd49 : 6'd0;
assign thread_id[305:300] = `ADD_TID_ENABLE ? 6'd50 : 6'd0;
assign thread_id[311:306] = `ADD_TID_ENABLE ? 6'd51 : 6'd0;
assign thread_id[317:312] = `ADD_TID_ENABLE ? 6'd52 : 6'd0;
assign thread_id[323:318] = `ADD_TID_ENABLE ? 6'd53 : 6'd0;
assign thread_id[329:324] = `ADD_TID_ENABLE ? 6'd54 : 6'd0;
assign thread_id[335:330] = `ADD_TID_ENABLE ? 6'd55 : 6'd0;
assign thread_id[341:336] = `ADD_TID_ENABLE ? 6'd56 : 6'd0;
assign thread_id[347:342] = `ADD_TID_ENABLE ? 6'd57 : 6'd0;
assign thread_id[353:348] = `ADD_TID_ENABLE ? 6'd58 : 6'd0;
assign thread_id[359:354] = `ADD_TID_ENABLE ? 6'd59 : 6'd0;
assign thread_id[365:360] = `ADD_TID_ENABLE ? 6'd60 : 6'd0;
assign thread_id[371:366] = `ADD_TID_ENABLE ? 6'd61 : 6'd0;
assign thread_id[377:372] = `ADD_TID_ENABLE ? 6'd62 : 6'd0;
assign thread_id[383:378] = `ADD_TID_ENABLE ? 6'd63 : 6'd0;
endmodule
|
#include <bits/stdc++.h> using namespace std; #define endl n typedef long long int lli; #define __ ios_base::sync_with_stdio(false);cin.tie(NULL); int main(){__ int t= 1,n; cin>>t; while(t--){ string s; cin>>s; n = s.size(); bool flag = true; int idx1,idx2,cont =0; for(int i = 0;i<n;i++){ if(s[i]== ) ) idx1 = i; if(s[i]== ( ) idx2 = i; if(s[i]== ? )cont++; } if(idx1>idx2&& cont%2 ==0){ cout<< YES <<endl; } else if(idx1>idx2 && cont&1){ cout<< NO <<endl; } else{ int cont1 = 0,cont2 =0; for(int i = 0;i<idx1;i++){ cont1++; } for(int i= n-1;i>idx2;i--){ cont2++; } if(cont1>0 && cont2>0 && (cont-(2))%2 ==0) cout<< YES <<endl; else cout<< NO <<endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; map<pair<long long unsigned, long long unsigned>, pair<long long unsigned, long long unsigned> > dp; long long unsigned n; void read() { cin >> n; return; } pair<long long unsigned, long long unsigned> find(long long unsigned s, long long unsigned mx) { if (s <= 9) return make_pair(0, s); if (dp.find(make_pair(s, mx)) != dp.end()) return dp[make_pair(s, mx)]; long long unsigned t, r, m; pair<long long unsigned, long long unsigned> &ans = dp[make_pair(s, mx)]; t = 1; while (t * 10 <= s) t *= 10; r = s % t; s = s / t; while (1) { m = max(mx, s); pair<long long unsigned, long long unsigned> f = find(r, m); ans.first += f.first; if (s == 0) { ans.second = f.second; break; } if (f.second >= m) { ans.first += 2; r = t - m; } else { ans.first++; r = t - (m - f.second); } s--; } return ans; } void solve() { read(); pair<long long unsigned, long long unsigned> cvp = find(n, 0); cout << cvp.first + !!cvp.second << endl; return; } int main() { solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_SYMBOL_V
`define SKY130_FD_SC_MS__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; int main() { long long n = 1, k = 1; int t; cin >> t; for (int i = 1; i <= t; i++) { n %= mod; k %= mod; n *= 27; k *= 7; } while (n < k) n += mod; n -= k; cout << n % mod << endl; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; const long long xx = 2e7; const long long MOD = 1e9 + 7; const long long inf = 1e18; long long isprime(long long n) { if (n == 2) return 1; if (n % 2 == 0) return 0; for (long long i = 3; i * i <= n; i += 2) { if (n % i == 0) return 0; } return 1; } signed main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; if (isprime(n)) { cout << 1 << n ; } else if (n % 2 == 0 || isprime(n - 2)) { cout << 2 << n ; } else cout << 3 << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s; cin >> n >> s; int sum = 100; bool res = false; for (int i = 0; i < n; i++) { int temp1, temp2; cin >> temp1 >> temp2; if (temp1 < s) { res = true; if (temp2 != 0 && temp2 < sum) sum = temp2; } if (temp1 == s && temp2 == 0) res = true; } if (res) cout << 100 - sum; else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long LIM = 1e18; long long root(long long x) { long long L = 0LL, R = 1e9 + 7; while (L < R - 1) { long long mid = (L + R) >> 1LL; if (mid * mid <= x) L = mid; else R = mid; } return L; } int main() { set<long long> s; for (long long i = 2; i <= 1e6; i++) { for (long long j = i * i * i; j <= LIM; j *= i) { long long val = sqrt(j); if (val * val != j) s.insert(j); if (j > LIM / i) break; } } vector<long long> v(s.begin(), s.end()); int t; scanf( %d , &t); while (t--) { long long L, R; scanf( %lld %lld , &L, &R); long long ans = upper_bound(v.begin(), v.end(), R) - lower_bound(v.begin(), v.end(), L); ans += root(R) - root(L - 1); printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char jz[1000006][5]; int cnt2 = 0, cnt3 = 0, dp[1000006][8]; int cal(int x) { int ans = 0; while (x > 0) { if (x & 1) ans++; x /= 2; } return ans; } bool check_3(int x, int y) { int sum = cal(x / 2) + cal(y / 2); if (sum % 2 == 0) return false; if (x >= 4) x -= 4; if (y >= 4) y -= 4; sum = cal(x) + cal(y); if (sum % 2 == 0) return false; return true; } bool check_2(int x, int y) { if ((cal(x) + cal(y)) % 2 == 0) return false; return true; } int change(int x, int y) { return cal(x ^ y); } struct s3 { int x; vector<int> v; } a3[10], a2[5]; int main() { memset(dp, 0x3f3f3f3f, sizeof(dp)); cin >> n >> m; if (n > 3 && m > 3) { cout << -1; return 0; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (m >= 4) cin >> jz[j][i]; else if (m < 4) cin >> jz[i][j]; } getchar(); } if (m >= 4) swap(n, m); if (m == 1) { cout << 0; return 0; } else if (m == 2) { for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) { if (check_2(i, j)) { a2[i].v.push_back(j); } } if (n == 1) { cout << 0; return 0; } int num1 = 0; for (int i = 1; i <= m; i++) { num1 *= 2; if (jz[1][i] == 1 ) num1++; } for (int i = 2; i <= n; i++) { int num = 0; for (int l = 1; l <= m; l++) { num *= 2; if (jz[i][l] == 1 ) num++; } if (i == 2) { for (int j = 0; j < 4; j++) { for (int k = 0; k < a2[j].v.size(); k++) dp[i][j] = min(dp[i][j], change(j, num) + change(a2[j].v[k], num1)); } } else { for (int j = 0; j < 4; j++) { for (int k = 0; k < a2[j].v.size(); k++) dp[i][j] = min(dp[i][j], dp[i - 1][a2[j].v[k]] + change(j, num)); } } } int ans = 2100000000; for (int i = 0; i < 4; i++) ans = min(ans, dp[n][i]); cout << ans; } else if (m == 3) { for (int i = 0; i <= 7; i++) { for (int j = 0; j <= 7; j++) { if (check_3(i, j)) { a3[i].x = i; a3[i].v.push_back(j); } } } int num1 = 0; for (int i = 1; i <= m; i++) { num1 *= 2; if (jz[1][i] == 1 ) num1++; } if (n == 1) { cout << 0; return 0; } for (int i = 2; i <= n; i++) { int num = 0; for (int l = 1; l <= m; l++) { num *= 2; if (jz[i][l] == 1 ) num++; } if (i == 2) { for (int j = 0; j < 8; j++) for (int k = 0; k < a3[j].v.size(); k++) { dp[i][j] = min(dp[i][j], change(j, num) + change(a3[j].v[k], num1)); } } else { for (int j = 0; j < 8; j++) for (int k = 0; k < a3[j].v.size(); k++) { dp[i][j] = min(dp[i][j], dp[i - 1][a3[j].v[k]] + change(j, num)); } } } int ans = 2100000000; for (int i = 0; i < 8; i++) ans = min(ans, dp[n][i]); cout << ans; } } |
// cog_ram
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ram
(
input clk,
input ena,
input w,
input [8:0] a,
input [31:0] d,
output reg [31:0] q
);
// 512 x 32 ram
reg [511:0] [31:0] r;
always @(posedge clk)
begin
if (ena && w)
r[a] <= d;
if (ena)
q <= r[a];
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_0 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 3: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 3: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 3: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1100; int n, m, t; int a[N]; int main() { scanf( %d , &n); memset(a, 0, sizeof(a)); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); a[x]++; } scanf( %d , &t); int mx = -1; for (int i = 1; i <= 1000; i++) { int j = i; int sum = 0; int k = t + 1; while (k && j <= 1000) { sum += a[j]; j++; k--; } if (sum > mx) { mx = sum; } } printf( %d n , mx); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int a, b, c, d; cin >> a >> b >> c >> d; string w, x, y, z, k = Ya , l = Tidak ; if (a == 0 && d == 0) { if (b % 2 == 1) { cout << Tidak Ya Tidak Tidak n ; } else { cout << Tidak Tidak Ya Tidak n ; } } else if (b == 0 && c == 0) { if (a % 2 == 1) { cout << Ya Tidak Tidak Tidak n ; } else { cout << Tidak Tidak Tidak Ya n ; } } else { if ((a + b) % 2 == 1) { cout << Ya Ya Tidak Tidak n ; } else { cout << Tidak Tidak Ya Ya n ; } } } } |
#include <bits/stdc++.h> using namespace std; long long a[1000007], b[1000007], i, n, x, s, f, t; int main() { cin >> n; for (i = 1; i <= 2 * n; i++) { cin >> x; if (a[x] == 0) a[x] = i; else if (a[x] != 0) b[x] = i; } s = a[1] - 1; for (x = 2; x <= n; x++) { t = a[x] - a[x - 1]; if (t < 0) t = -t; s = s + t; } s = s + b[1] - 1; for (x = 2; x <= n; x++) { t = b[x] - b[x - 1]; if (t < 0) t = -t; s = s + t; } cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, mas[1000], ans[1000], anss; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) cin >> mas[i]; for (int i = 2; i <= n; i++) { if (mas[i] + mas[i - 1] < k) { anss += k - mas[i - 1] - mas[i]; mas[i] = k - mas[i - 1]; } } cout << anss << n ; for (int i = 1; i <= n; i++) cout << mas[i] << ; } |
/**
* testbench.v
*/
module testbench();
import bsg_cache_non_blocking_pkg::*;
// parameters
//
parameter id_width_p = 30;
parameter addr_width_p = 32;
parameter data_width_p = 32;
parameter block_size_in_words_p = 8;
parameter sets_p = 128;
parameter ways_p = 8;
parameter miss_fifo_els_p = `MISS_FIFO_ELS_P;
parameter data_mask_width_lp=(data_width_p>>3);
parameter mem_size_p = 2**15;
parameter dma_read_delay_p = `DMA_READ_DELAY_P;
parameter dma_write_delay_p = `DMA_WRITE_DELAY_P;
parameter dma_data_delay_p = `DMA_DATA_DELAY_P;
parameter dma_req_delay_p = `DMA_REQ_DELAY_P;
parameter yumi_max_delay_p = `YUMI_MAX_DELAY_P;
parameter yumi_min_delay_p = `YUMI_MIN_DELAY_P;
localparam lg_ways_lp = `BSG_SAFE_CLOG2(ways_p);
localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p);
localparam lg_block_size_in_words_lp = `BSG_SAFE_CLOG2(block_size_in_words_p);
localparam byte_sel_width_lp = `BSG_SAFE_CLOG2(data_width_p>>3);
localparam tag_width_lp = (addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp);
localparam block_offset_width_lp = lg_block_size_in_words_lp+byte_sel_width_lp;
// synopsys translate_off
integer status;
integer wave;
string checker;
initial begin
status = $value$plusargs("wave=%d",wave);
status = $value$plusargs("checker=%s",checker);
if (wave) $vcdpluson;
end
// clock and reset
//
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(100)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(8)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
// synopsys translate_on
// non-blocking cache
//
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
logic cache_v_li;
logic cache_ready_lo;
logic [id_width_p-1:0] cache_id_lo;
logic [data_width_p-1:0] cache_data_lo;
logic cache_v_lo;
logic cache_yumi_li;
`declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p);
bsg_cache_non_blocking_dma_pkt_s dma_pkt;
logic dma_pkt_v_lo;
logic dma_pkt_yumi_li;
logic [data_width_p-1:0] dma_data_li;
logic dma_data_v_li;
logic dma_data_ready_lo;
logic [data_width_p-1:0] dma_data_lo;
logic dma_data_v_lo;
logic dma_data_yumi_li;
bsg_cache_non_blocking #(
.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.miss_fifo_els_p(miss_fifo_els_p)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.cache_pkt_i(cache_pkt)
,.v_i(cache_v_li)
,.ready_o(cache_ready_lo)
,.data_o(cache_data_lo)
,.id_o(cache_id_lo)
,.v_o(cache_v_lo)
,.yumi_i(cache_yumi_li)
,.dma_pkt_o(dma_pkt)
,.dma_pkt_v_o(dma_pkt_v_lo)
,.dma_pkt_yumi_i(dma_pkt_yumi_li)
,.dma_data_i(dma_data_li)
,.dma_data_v_i(dma_data_v_li)
,.dma_data_ready_o(dma_data_ready_lo)
,.dma_data_o(dma_data_lo)
,.dma_data_v_o(dma_data_v_lo)
,.dma_data_yumi_i(dma_data_yumi_li)
);
// synopsys translate_off
// random yumi generator
//
bsg_nonsynth_random_yumi_gen #(
.yumi_min_delay_p(yumi_min_delay_p)
,.yumi_max_delay_p(yumi_max_delay_p)
) yumi_gen (
.clk_i(clk)
,.reset_i(reset)
,.v_i(cache_v_lo)
,.yumi_o(cache_yumi_li)
);
// dma model
//
bsg_nonsynth_non_blocking_dma_model #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.els_p(4*ways_p*sets_p*block_size_in_words_p)
,.read_delay_p(dma_read_delay_p)
,.write_delay_p(dma_write_delay_p)
,.dma_data_delay_p(dma_data_delay_p)
,.dma_req_delay_p(dma_req_delay_p)
) dma_model (
.clk_i(clk)
,.reset_i(reset)
,.dma_pkt_i(dma_pkt)
,.dma_pkt_v_i(dma_pkt_v_lo)
,.dma_pkt_yumi_o(dma_pkt_yumi_li)
,.dma_data_o(dma_data_li)
,.dma_data_v_o(dma_data_v_li)
,.dma_data_ready_i(dma_data_ready_lo)
,.dma_data_i(dma_data_lo)
,.dma_data_v_i(dma_data_v_lo)
,.dma_data_yumi_o(dma_data_yumi_li)
);
// trace replay
//
localparam rom_addr_width_lp = 26;
localparam ring_width_lp =
`bsg_cache_non_blocking_pkt_width(id_width_p,addr_width_p,data_width_p);
logic [rom_addr_width_lp-1:0] trace_rom_addr;
logic [ring_width_lp+4-1:0] trace_rom_data;
logic tr_v_lo;
logic [ring_width_lp-1:0] tr_data_lo;
logic tr_yumi_li;
logic done;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) trace_replay (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(trace_rom_addr)
,.rom_data_i(trace_rom_data)
,.done_o(done)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(ring_width_lp+4)
,.addr_width_p(rom_addr_width_lp)
) test_rom (
.addr_i(trace_rom_addr)
,.data_o(trace_rom_data)
);
assign cache_pkt = tr_data_lo;
assign cache_v_li = tr_v_lo;
assign tr_yumi_li = tr_v_lo & cache_ready_lo;
bind bsg_cache_non_blocking basic_checker #(
.data_width_p(data_width_p)
,.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.cache_pkt_width_lp(cache_pkt_width_lp)
,.mem_size_p($root.testbench.mem_size_p)
) bc (
.*
,.en_i($root.testbench.checker == "basic")
);
bind bsg_cache_non_blocking tag_checker #(
.data_width_p(data_width_p)
,.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.tag_width_lp(tag_width_lp)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
,.cache_pkt_width_lp(cache_pkt_width_lp)
) tc (
.*
,.en_i($root.testbench.checker == "tag")
);
bind bsg_cache_non_blocking ainv_checker #(
.data_width_p(data_width_p)
) ac (
.*
,.en_i($root.testbench.checker == "ainv")
);
bind bsg_cache_non_blocking block_ld_checker #(
.data_width_p(data_width_p)
,.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.cache_pkt_width_lp(cache_pkt_width_lp)
,.mem_size_p($root.testbench.mem_size_p)
) blc (
.*
,.en_i($root.testbench.checker == "block_ld")
);
// //
// FUNCTIONAL COVERAGE //
// //
bind bsg_cache_non_blocking cov_top _cov_top (.*);
bind bsg_cache_non_blocking_tl_stage cov_tl_stage _cov_tl_stage (.*);
bind bsg_cache_non_blocking_mhu cov_mhu _cov_mhu (.*);
bind bsg_cache_non_blocking_miss_fifo cov_miss_fifo _cov_miss_fifo (.*);
// waiting for all responses to be received.
//
integer sent_r, recv_r;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= '0;
recv_r <= '0;
end
else begin
if (cache_v_li & cache_ready_lo)
if (cache_pkt.opcode == BLOCK_LD)
sent_r <= sent_r + block_size_in_words_p;
else
sent_r <= sent_r + 1;
if (cache_v_lo & cache_yumi_li)
recv_r <= recv_r + 1;
end
end
initial begin
wait(done & (sent_r == recv_r));
$display("[BSG_FINISH] Test Successful.");
//for (integer i = 0; i < ; i++)
// @(posedge clk);
#500;
$finish;
end
// synopsys translate_on
endmodule
|
module test;
reg fail = 1'b0;
reg [3:0] in = 4'b0;
wire [3:0] bus;
assign (pull1, pull0) bus = in;
initial begin
// Check the initial value.
#1 if (bus !== 4'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1'b1;
end
// Check a bit force and verify a normal bit assign does nothing.
#1 force bus[0] = 1'b1;
#1 in[0] = 1'bz;
#1 if (bus !== 4'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
fail = 1'b1;
end
// Check a part force.
#1 force bus[3:2] = 2'b11;
#1 if (bus !== 4'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
fail = 1'b1;
end
// Check that we can change an unforced bit.
#1 in[1] = 1'bz;
#1 if (bus !== 4'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus);
fail = 1'b1;
end
#1 in[1] = 1'b0;
// Check a bit release.
#1 release bus[0];
#1 if (bus !== 4'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
fail = 1'b1;
end
// Check a part release.
#1 release bus[3:2];
#1 if (bus !== 4'b000z) begin
$display("FAILED: release of bus[3:2], got %b, expected 000z.", bus);
fail = 1'b1;
end
// Check a force from the upper thread bits (>= 8).
#1 force bus[2:1] = 2'bx1;
#1 if (bus !== 4'b0x1z) begin
$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", bus);
fail = 1'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mx = (1 << 22); long long f[mx], ans[mx]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; memset(ans, -1, sizeof(ans)); for (long long i = 0; i < n; i++) { f[a[i]]++; ans[a[i]] = a[i]; } for (long long j = 0; j < 22; j++) for (long long i = 0; i < mx; i++) if (i & (1 << j)) { f[i] += f[i ^ (1 << j)]; if (f[i ^ (1 << j)]) ans[i] = ans[i ^ (1 << j)]; } for (long long i = 0; i < n; i++) { long long p = (mx - 1) & (~a[i]); cout << ans[p] << ; } cout << n ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/08/2017 06:03:02 PM
// Design Name:
// Module Name: DUAL_PORT_MEMORY_SIMULATION
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DUAL_PORT_MEMORY_SIMULATION();
parameter MEMORY_WIDTH = 512 ;
parameter MEMORY_DEPTH = 512 ;
parameter MEMORY_LATENCY = "LOW_LATENCY" ;
parameter INIT_FILE = "" ;
// Inputs
reg clk ;
reg [$clog2(MEMORY_DEPTH-1) - 1 : 0] write_address ;
reg [MEMORY_WIDTH-1 : 0] data_in ;
reg write_enable ;
reg [$clog2(MEMORY_DEPTH-1)-1 : 0] read_address ;
reg read_enble ;
// Outputs
wire [MEMORY_WIDTH-1 : 0] data_out ;
// Instantiate the Unit Under Test (UUT)
DUAL_PORT_MEMORY uut(
.CLK(clk),
.WRITE_ADDRESS(write_address),
.DATA_IN(data_in),
.WRITE_ENABLE(write_enable),
.READ_ADDRESS(read_address),
.READ_ENBLE(read_enble),
.DATA_OUT(data_out)
);
initial
begin
// Initialize Inputs
clk = 1'b0 ;
write_address = 9'b1 ;
data_in = 512'b11 ;
write_enable = 1'b1 ;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_address = 9'b0 ;
data_in = 512'b1 ;
write_enable = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
write_address = 9'b0 ;
data_in = 512'b0 ;
write_enable = 1'b0 ;
read_address = 9'b0 ;
read_enble = 1'b1 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
read_enble = 1'b0 ;
#100;
clk = 1'b1 ;
#100;
clk = 1'b0 ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 200005, m1 = 998244353, m2 = 1e9 + 9; char s[N], c[N]; long long n, z[N], p1[N] = {1}, p2[N] = {1}, a[N]; pair<long long, long long> tr[N << 2]; struct Hash { long long h1[N], h2[N]; char s[N]; void init() { h1[0] = h2[0] = s[0] - a ; for (long long i = 1; i < n; i++) { h1[i] = (h1[i - 1] * 31 + s[i] - a ) % m1; h2[i] = (h2[i - 1] * 255 + s[i] - a ) % m2; p1[i] = p1[i - 1] * 31 % m1; p2[i] = p2[i - 1] * 255 % m2; } } pair<long long, long long> query(long long l, long long r) { return make_pair( (h1[r] - (l == 0 ? 0 : h1[l - 1] * p1[r - l + 1] % m1) + m1) % m1, (h2[r] - (l == 0 ? 0 : h2[l - 1] * p2[r - l + 1] % m2) + m2) % m2); } } h1, h2; struct node { long long x, y, l, p, k; node() {} node(long long _x, long long _y, long long _l, long long _p, long long _k) : x(_x), y(_y), l(_l), p(_p), k(_k) {} bool operator<(const node zh) const { return l + l + k < zh.l + zh.l + zh.k; } } ans; long long check(long long i, long long m) { return h1.query(i - m, i) == h2.query(n - (i + m) - 1, n - i - 1); } void build(long long k, long long l, long long r) { if (l == r) { tr[k] = make_pair(a[l - 1], l - 1); return; } long long mid = l + r >> 1; build(k << 1, l, mid); build(k << 1 | 1, mid + 1, r); tr[k] = max(tr[k << 1], tr[k << 1 | 1]); } pair<long long, long long> query(long long k, long long l, long long r, long long a, long long b) { if (l == a && r == b) return tr[k]; long long mid = l + r >> 1; if (b <= mid) return query(k << 1, l, mid, a, b); else if (a > mid) return query(k << 1 | 1, mid + 1, r, a, b); else return max(query(k << 1, l, mid, a, mid), query(k << 1 | 1, mid + 1, r, mid + 1, b)); } pair<long long, long long> xzh(long long x, long long y) { long long l = 0, r = (y - x) / 2 + 1; while (r - l > 1) { long long m = l + r >> 1; pair<long long, long long> k = query(1, 1, n, (x + m) + 1, (y - m) + 1); if (k.first >= m) l = m; else r = m; } return query(1, 1, n, (x + l) + 1, (y - l) + 1); } signed main() { scanf( %s , s); n = strlen(s); for (long long i = 0; i < n; i++) c[i] = s[n - i - 1]; c[n] = $ ; for (long long i = n + 1; i <= 2 * n; i++) c[i] = s[i - n - 1]; long long l = 0, r = 0; for (long long i = 1; i <= 2 * n; i++) { if (i > r) { l = i, r = i; while (r <= 2 * n && c[r - l] == c[r]) r++; z[i] = r - l; r--; } else { long long k = i - l; if (z[k] < r - i + 1) z[i] = z[k]; else { l = i; while (r <= 2 * n && c[r - l] == c[r]) r++; z[i] = r - l; r--; } } } if (z[n + 1] == n) { printf( 1 n1 %I64d n , n - !(n & 1)); return 0; } for (long long i = 0; i < n; i++) { h1.s[i] = s[i]; h2.s[i] = s[n - i - 1]; } h1.init(), h2.init(); for (long long i = 0; i < n; i++) { long long l = 0, r = min(i, n - i - 1) + 1; while (r - l > 1) { long long m = l + r >> 1; if (check(i, m)) l = m; else r = m; } a[i] = l; } build(1, 1, n); for (long long i = 0; i < n; i++) { long long x = i, l = z[i + n + 1], y = n - l; if (l == 0 || x + l > y - 1) continue; pair<long long, long long> zh = xzh(x + l, y - 1); long long k = zh.first; k = min(k, y - x - l); k = min(k, min(zh.second - (x + l), y - 1 - zh.second)); long long p = zh.second - k; k = 2 * k + 1; node q = node(x, y, l, p, k); if (ans < q) ans = q; } long long zh = 0; for (long long i = 0; i < n; i++) if (a[i] > a[zh]) zh = i; if (2 * a[zh] + 1 > ans.l + ans.l + ans.k) printf( 1 n%I64d %I64d n , zh - a[zh] + 1, 2 * a[zh] + 1); else printf( 3 n%I64d %I64d n%I64d %I64d n%I64d %I64d n , ans.x + 1, ans.l, ans.p + 1, ans.k, ans.y + 1, ans.l); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; const int maxn = 200100; map<int, long long> m1; map<int, long long> m2; int a[maxn]; int main() { m1.clear(); m2.clear(); int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { cin >> a[i]; } long long sum = 0; for (int i = n; i >= 1; i--) { if ((long long)a[i] * k <= 1e9 && (long long)a[i] * k >= -1e9) { sum += m2[a[i] * k]; m2[a[i]] += m1[a[i] * k]; } m1[a[i]]++; } cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; const int infi = 1e9 + 7; const long long infl = (long long)1e18 + (long long)7; const long long mod = 998244353; long long sum[300500]; long long get_sum(int l, int r) { if (l > r) { return 0; } if (l) { return sum[r] - sum[l - 1]; } return sum[r]; } long long ar[300500]; long long pow(long long a, long long p) { long long ans = 1; while (p) { if (p & 1LL) { ans *= a; ans %= mod; } a *= a; a %= mod; p >>= 1; } return ans; } long long norm(long long a, long long n) { return (a * pow(n, mod - 2)) % mod; } int32_t main() { cin.sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < (n); ++i) { cin >> ar[i]; } sort(ar, ar + n); reverse(ar, ar + n); for (int i = 0; i < (n); ++i) { if (i) sum[i] = sum[i - 1]; sum[i] += ar[i]; sum[i] %= mod; } for (int len = 1; len < n; ++len) { long long ans = 0; for (long long w = 1, l = len; l < n; l += len, ++w) { long long r = min(l + len - 1, n - 1LL); ans += get_sum(l, r) * w; ans %= mod; } if (ans < 0) ans += mod; cout << norm(ans, n) << ; } cout << 0 << endl; return 0; } |
module switch_fabric(
clk, reset, data_in0, data_in1, data_in2,
data_in3, data_in4, data_in5, data_in_valid0,
data_in_valid1, data_in_valid2, data_in_valid3,
data_in_valid4, data_in_valid5, data_out0,
data_out1, data_out2, data_out3, data_out4,
data_out5, data_out_ack0, data_out_ack1,
data_out_ack2, data_out_ack3, data_out_ack4,
data_out_ack5
);
input clk, reset;
input [7:0] data_in0, data_in1, data_in2, data_in3;
input [7:0] data_in4, data_in5;
input data_in_valid0, data_in_valid1, data_in_valid2;
input [7:0] data_in_valid3, data_in_valid4, data_in_valid5;
output [7:0] data_out0, data_out1, data_out2, data_out3;
output [7:0] data_out4, data_out5;
output data_out_ack0, data_out_ack1, data_out_ack2;
output [7:0] data_out_ack3, data_out_ack4, data_out_ack5;
(* gentb_clock *)
wire clk;
switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
.data_in_valid(data_in_valid0), .data_out(data_out0),
.data_out_ack(data_out_ack0));
switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
.data_in_valid(data_in_valid1), .data_out(data_out1),
.data_out_ack(data_out_ack1));
switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
.data_in_valid(data_in_valid2), .data_out(data_out2), .
data_out_ack(data_out_ack2));
switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
.data_in_valid(data_in_valid3), .data_out(data_out3),
.data_out_ack(data_out_ack3));
switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
.data_in_valid(data_in_valid4), .data_out(data_out4),
.data_out_ack(data_out_ack4));
switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
.data_in_valid(data_in_valid5), .data_out(data_out5),
.data_out_ack(data_out_ack5));
endmodule
module switch (
clk,
reset,
data_in,
data_in_valid,
data_out,
data_out_ack
);
input clk;
input reset;
input [7:0] data_in;
input data_in_valid;
output [7:0] data_out;
output data_out_ack;
reg [7:0] data_out;
reg data_out_ack;
always @ (posedge clk)
if (reset) begin
data_out <= 0;
data_out_ack <= 0;
end else if (data_in_valid) begin
data_out <= data_in;
data_out_ack <= 1;
end else begin
data_out <= 0;
data_out_ack <= 0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3100; int n, m; vector<int> eds[MAXN]; vector<int> reds[MAXN]; vector<pair<int, int> > go[MAXN]; vector<pair<int, int> > rgo[MAXN]; int dd[MAXN]; int ddg[MAXN][MAXN]; void bfs(int v) { for (int i = 0; i < n; ++i) dd[i] = -1; dd[v] = 0; queue<int> qu; qu.push(v); while (!qu.empty()) { int x = qu.front(); qu.pop(); for (int u : eds[x]) if (dd[u] == -1) dd[u] = dd[x] + 1, qu.push(u); } } void rbfs(int v) { for (int i = 0; i < n; ++i) dd[i] = -1; dd[v] = 0; queue<int> qu; qu.push(v); while (!qu.empty()) { int x = qu.front(); qu.pop(); for (int u : reds[x]) if (dd[u] == -1) dd[u] = dd[x] + 1, qu.push(u); } } int main() { cin >> n >> m; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; --a; --b; eds[a].push_back(b); reds[b].push_back(a); } for (int i = 0; i < n; ++i) { bfs(i); int mn1 = i, mn2 = i, mn3 = i; for (int j = 0; j < n; ++j) { if (i == j) continue; if (dd[j] == -1) continue; if (dd[mn3] < dd[j]) mn3 = j; if (dd[mn3] > dd[mn2]) swap(mn2, mn3); if (dd[mn2] > dd[mn1]) swap(mn1, mn2); } go[i].push_back(make_pair(mn1, dd[mn1])); go[i].push_back(make_pair(mn2, dd[mn2])); go[i].push_back(make_pair(mn3, dd[mn3])); for (int j = 0; j < n; ++j) ddg[i][j] = dd[j]; rbfs(i); mn1 = i, mn2 = i, mn3 = i; for (int j = 0; j < n; ++j) { if (i == j) continue; if (dd[j] == -1) continue; if (dd[mn3] < dd[j]) mn3 = j; if (dd[mn3] > dd[mn2]) swap(mn2, mn3); if (dd[mn2] > dd[mn1]) swap(mn1, mn2); } rgo[i].push_back(make_pair(mn1, dd[mn1])); rgo[i].push_back(make_pair(mn2, dd[mn2])); rgo[i].push_back(make_pair(mn3, dd[mn3])); } int bst = -1; int ba = 0, bb = 0, bc = 0, bd = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) { if (i == j) continue; if (ddg[i][j] == -1) continue; for (int i1 = 0; i1 < (int)rgo[i].size(); ++i1) for (int j1 = 0; j1 < (int)go[j].size(); ++j1) { if (rgo[i][i1].second <= 0) continue; if (go[j][j1].second <= 0) continue; int a = rgo[i][i1].first; int b = go[j][j1].first; if (a == b || a == j || b == i) continue; int sum = ddg[a][i] + ddg[i][j] + ddg[j][b]; if (sum > bst) { ba = a; bb = i; bc = j; bd = b; bst = sum; } } } cout << ba + 1 << << bb + 1 << << bc + 1 << << bd + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int v[6][4]; for (int i = 0; i < 6; i++) { for (int j = 0; j < 4; j++) cin >> v[i][j]; } int cnt1 = 0, cnt2 = 0, cnt3 = 0; for (int i = 0; i < 3; i++) if (v[0][i] == v[0][i + 1] && v[2][i] == v[2][i + 1]) cnt1++; for (int i = 0; i < 3; i++) if (v[1][i] == v[1][i + 1] && v[5][i] == v[5][i + 1]) cnt2++; for (int i = 0; i < 3; i++) if (v[3][i] == v[3][i + 1] && v[4][i] == v[4][i + 1]) cnt3++; vector<int> a; a.push_back(0); for (int i = 0; i < 6; i++) { for (int j = 0; j < 4; j++) a.push_back(v[i][j]); } if (cnt1 == 3 && cnt2 != 3 && cnt3 != 3) { if (a[5] == a[6] && a[7] == a[8] && a[17] == a[18] && a[19] == a[20] && a[21] == a[22] && a[23] == a[24] && a[13] == a[14] && a[15] == a[16]) { if (a[5] == a[15]) { if (a[13] == a[23] && a[21] == a[19] && a[17] == a[7]) cout << YES ; else cout << NO ; } else if (a[5] == a[19]) { if (a[13] == a[7] && a[17] == a[23] && a[21] == a[15]) cout << YES ; else cout << NO ; } else cout << NO ; } else cout << NO ; } else if (cnt1 != 3 && cnt2 == 3 && cnt3 != 3) { if (a[1] == a[2] && a[3] == a[4] && a[18] == a[20] && a[17] == a[19] && a[11] == a[12] && a[9] == a[10] && a[15] == a[13] && a[16] == a[14]) { if (a[1] == a[17]) { if (a[18] == a[9] && a[11] == a[16] && a[15] == a[3]) cout << YES ; else cout << NO ; } else if (a[1] == a[16]) { if (a[18] == a[3] && a[11] == a[17] && a[15] == a[9]) cout << YES ; else cout << NO ; } else cout << NO ; } else cout << NO ; } else if (cnt1 != 3 && cnt2 != 3 && cnt3 == 3) { if (a[1] == a[3] && a[2] == a[4] && a[5] == a[7] && a[6] == a[8] && a[9] == a[11] && a[10] == a[12] && a[24] == a[22] && a[23] == a[21]) { if (a[1] == a[6]) { if (a[5] == a[10] && a[9] == a[23] && a[24] == a[2]) cout << YES ; else cout << NO ; } else if (a[1] == a[23]) { if (a[5] == a[2] && a[9] == a[6] && a[24] == a[10]) cout << YES ; else cout << NO ; } else cout << NO ; } else cout << NO ; } else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; long long a[maxn]; pair<long long, long long> st[maxn]; long long top, n, m, k, l, r, rec, rec2; long long ans; int main() { cin >> n >> k >> m; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = 1; i <= n; i++) { if (!top || st[top].first != a[i]) st[++top] = make_pair(a[i], 1); else st[top].second = (st[top].second + 1) % k; if (st[top].second == 0) top--; } for (long long i = 1; i <= top; i++) { rec += st[i].second; } l = 1, r = top; while (l < r && st[l].first == st[r].first && (st[l].second + st[r].second) % k == 0) { rec2 += st[l].second + st[r].second; l++; r--; } if (l == r) { if (st[l].second * m % k == 0) ans += m * rec - rec2 * (m) - (st[l].second * m / k * k); else ans += m * rec - rec2 * (m - 1) - (st[l].second * m / k * k); } else { if (st[l].first == st[r].first) rec2 += (st[l].second + st[r].second) / k * k; ans = m * rec - rec2 * (m - 1); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long inf; const double eps = 1e-8; const double pi = acos(-1.0); template <class T> long long chkmin(T &a, T b) { return a > b ? a = b, 1 : 0; } template <class T> long long chkmax(T &a, T b) { return a < b ? a = b, 1 : 0; } template <class T> T sqr(T a) { return a * a; } template <class T> T mmin(T a, T b) { return a < b ? a : b; } template <class T> T mmax(T a, T b) { return a > b ? a : b; } template <class T> T aabs(T a) { return a < 0 ? -a : a; } template <class T> long long dcmp(T a, T b) { return a > b; } template <long long *a> long long cmp_a(long long first, long long second) { return a[first] < a[second]; } struct __INIT__ { __INIT__() { memset(&inf, 0x3f, sizeof(inf)); } } __INIT___; namespace io { const long long SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; long long f, qr; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char first) { *oS++ = first; if (oS == oT) flush(); } template <typename A> inline bool read(A &first) { for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; else if (c == EOF) return 0; for (first = 0; c <= 9 && c >= 0 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) first = first * 10 + (c & 15); first *= f; return 1; } inline bool read(char &first) { while ((first = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) == || first == n || first == r ) ; return first != EOF; } inline bool read(char *first) { while ((*first = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) == n || *first == || *first == r ) ; if (*first == EOF) return 0; while (!(*first == n || *first == || *first == r )) *(++first) = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); *first = 0; return 1; } template <typename A, typename... B> inline bool read(A &first, B &...second) { return read(first) && read(second...); } template <typename A> inline bool write(A first) { if (!first) putc( 0 ); if (first < 0) putc( - ), first = -first; while (first) qu[++qr] = first % 10 + 0 , first /= 10; while (qr) putc(qu[qr--]); return 0; } inline bool write(char first) { putc(first); return 0; } inline bool write(const char *first) { while (*first) { putc(*first); ++first; } return 0; } inline bool write(char *first) { while (*first) { putc(*first); ++first; } return 0; } template <typename A, typename... B> inline bool write(A first, B... second) { return write(first) || write(second...); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io ::putc; using io ::read; using io ::write; char strs[1000005]; char *s[100005]; long long to[100005][26], t = 1, fail[100005]; long long c[100005]; long long ed[100005]; long long q[100005], *l, *r; long long cnt[201][100005]; long long is[100005]; long long ans[100005]; vector<pair<long long, long long> > ask[100005]; const long long S = 500; long long dfn[100005], low[100005], su[100005]; long long cl; void add(long long first, long long second) { for (; first <= cl; first += first & -first) su[first] += second; } long long sum(long long first) { long long second = 0; for (; first; first ^= first & -first) second += su[first]; return second; } vector<long long> son[100005]; void dfs(long long first) { dfn[first] = ++cl; for (auto i : son[first]) dfs(i); low[first] = cl; } signed main() { long long n, m; read(n, m); s[1] = strs; for (long long i = 1; i <= n; ++i) { read(s[i]); s[i + 1] = s[i] + strlen(s[i]); long long at = 1; for (char *j = s[i]; j < s[i + 1]; ++j) { if (!to[at][*j - a ]) to[at][*j - a ] = ++t; at = to[at][*j - a ]; } ed[i] = at; } *(l = r = q) = 1; fail[1] = 1; while (l <= r) { for (long long i = 0; i < 26; ++i) if (to[*l][i]) { *(++r) = to[*l][i]; if (*l == 1) { fail[*r] = 1; } else { long long at = fail[*l]; while (at != 1 && !to[at][i]) at = fail[at]; if (to[at][i]) fail[*r] = to[at][i]; else fail[*r] = 1; } son[fail[*r]].push_back(*r); } ++l; } l = q; while (l <= r) { for (long long i = 0; i < 26; ++i) if (!to[*l][i]) { if (*l == 1) to[*l][i] = 1; else to[*l][i] = to[fail[*l]][i]; } ++l; } long long ct = 0; for (long long i = 1; i <= n; ++i) { if (s[i + 1] - s[i] > S) { is[i] = ++ct; long long at = 1; for (char *j = s[i]; j < s[i + 1]; ++j) { at = to[at][*j - a ]; ++c[at]; } for (long long *j = r;; --j) { c[fail[*j]] += c[*j]; if (j == q) break; } for (long long j = 1; j <= n; ++j) cnt[ct][j] = cnt[ct][j - 1] + c[ed[j]]; for (long long j = 1; j <= t; ++j) c[j] = 0; } } for (long long i = 1; i <= m; ++i) { long long l, r, k; read(l, r, k); if (s[k + 1] - s[k] > S) { ans[i] = cnt[is[k]][r] - cnt[is[k]][l - 1]; } else { ask[r].push_back(make_pair(k, i)); ask[l - 1].push_back(make_pair(k, -i)); } } dfs(1); for (long long i = 1; i <= n; ++i) { add(dfn[ed[i]], 1); add(low[ed[i]] + 1, -1); for (auto j : ask[i]) { long long aid = j.second, tp = 1; if (aid < 0) { aid = -aid; tp = -1; } long long at = 1; for (char *l = s[j.first]; l < s[j.first + 1]; ++l) { at = to[at][*l - a ]; ans[aid] += tp * sum(dfn[at]); } } } for (long long i = 1; i <= m; ++i) write(ans[i], n ); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000000000 ) using namespace std; const long long int INF = 2e9 + 1; char s[50000], s2[50000]; struct automato { struct leaf { int link, len; map<char, int> nex; bool cl; leaf() : cl(false) {} }; vector<leaf> tree; vector<int> cnt, used; int sz, pre; automato() {} void init() { sz = 1; pre = 0; tree.resize(2 * 50000); cnt.resize(2 * 50000, 0); used.resize(2 * 50000, 0); tree[0].link = -1; tree[0].len = 0; }; void add_s(char c) { int cur = sz++; tree[cur].len = tree[pre].len + 1; int temp = pre; for (; temp != -1 && !tree[temp].nex.count(c); temp = tree[temp].link) { tree[temp].nex[c] = cur; } if (temp == -1) { tree[cur].link = 0; } else { int p = tree[temp].nex[c]; if (tree[p].len == tree[temp].len + 1) { tree[cur].link = p; } else { int clone = sz++; tree[clone].nex = tree[p].nex; tree[clone].len = tree[temp].len + 1; tree[clone].link = tree[p].link; tree[clone].cl = true; tree[p].link = clone; tree[cur].link = clone; for (; temp != -1 && tree[temp].nex.count(c) && tree[temp].nex[c] == p; temp = tree[temp].link) { tree[temp].nex[c] = clone; } } } pre = cur; }; void add_str(char *s) { int n = strlen(s); for (int i = 0; i < (n); i++) { add_s(s[i]); } } void dfs() { vector<pair<int, int> > len; for (int i = 0; i < (sz); i++) { len.push_back(make_pair(tree[i].len, i)); } sort(len.begin(), len.end()); reverse(len.begin(), len.end()); for (int i = 0; i < (sz); i++) { int id = len[i].second; if (!tree[id].cl) cnt[id]++; if (tree[id].link != -1) cnt[tree[id].link] += cnt[id]; } } int nx(int id, char c) { if (!tree[id].nex.count(c)) return -1; return tree[id].nex[c]; } int get_cnt(int now) { return cnt[now]; } }; int main() { scanf( %s%s , &s, &s2); int n = strlen(s), m = strlen(s2); automato a, b; a.init(); b.init(); a.add_str(s); b.add_str(s2); a.dfs(); b.dfs(); int out = INF; for (int i = 0; i < n; i++) { int st = 0, st2 = 0; for (int j = i; j < n; j++) { st = a.nx(st, s[j]); st2 = b.nx(st2, s[j]); if (st == -1 || st2 == -1) break; if (a.get_cnt(st) == 1 && b.get_cnt(st2) == 1) { out = min(out, j - i + 1); break; } } } cout << (out == INF ? -1 : out); } |
#include <bits/stdc++.h> using namespace std; const int N = 5000 * 100 + 5; int n, m, a, b, c, av, bv, cv, t, h[N], cnt, par[N], y, ans[N], cntA, col, ca[N], o, uwu; vector<int> adj[N], pa; bool mark[N], vis[N], flag2, g[N]; void bfs(int v) { queue<int> q; par[v] = -1; q.push(v); flag2 = false; while (q.size() && !flag2) { v = q.front(); q.pop(); for (auto u : adj[v]) if (!par[u]) { par[u] = v, q.push(u); if (adj[u].size() % 3 == 1 && !flag2) y = u, flag2 = true; } } } void dfs3(int v, int co, int p = -1) { pa.push_back(v); if (!flag2) for (auto u : adj[v]) if (u == bv && u != p) { for (auto i : pa) vis[i] = true; flag2 = true, uwu++; } for (auto u : adj[v]) if (u != p && !flag2 && ca[u] == co) dfs3(u, co, v), pa.pop_back(); } void dfs(int v) { ca[v] = col; for (auto u : adj[v]) if (!ca[u] && u != bv) dfs(u); } void dfs2(int v, int p = -1) { ans[cntA++] = v; g[v] = true; int l = 0; bool flag = false; for (auto u : adj[v]) if (h[u] > h[l] && u != p) { l = u; } if (!cnt && l) for (int i = 0; i < cntA; i++) { if (l == ans[i]) flag = true; if (flag) mark[ans[i]] = true, cnt++; } for (auto u : adj[v]) if (!cnt && !h[u] && adj[u].size() % 3 == 2) h[u] = h[v] + 1, dfs2(u, v), ans[--cntA] = 0; } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); cin >> t; for (o = 1; o <= t; o++) { cin >> n >> m; for (int i = 0, v, u; i < m; i++) { cin >> v >> u; adj[v].push_back(u); adj[u].push_back(v); } for (int i = 1; i <= n; i++) { if (adj[i].size() % 3 == 0) a++, av = i; else if (adj[i].size() % 3 == 1) b++, bv = i; else c++, cv = i; } if (a) { if (n == 1) cout << NO n ; else { cout << YES n << n - 1 << n ; for (int i = 1; i <= n; i++) if (i != av) cout << i << ; } } else if (b > 1) { bfs(bv); while (par[y] != -1) mark[y] = true, y = par[y], cntA++; mark[y] = true, cntA++; if (cntA == n) cout << NO n ; else { cout << YES n << n - cntA << n ; for (int i = 1; i <= n; i++) if (!mark[i]) cout << i << ; cout << n ; } } else { fill(h, h + n + 1, 0); cnt = 0; for (int i = 1; i <= n; i++) if (!g[i] && adj[i].size() % 3 == 2) h[i] = 1, cntA = 0, dfs2(i); if (cnt == n) cout << NO n ; else if (cnt) { cout << YES n << n - cnt << n ; for (int i = 1; i <= n; i++) if (!mark[i]) cout << i << ; cout << n ; } else if (!cnt) { bool flag = true; if (b != 1) flag = false; if (adj[bv].size() < 4) flag = false; if (flag) { cntA = 0, flag2 = false, col = 1; fill(vis, vis + n + 1, false); fill(h, h + n + 1, 0); uwu = 0; for (int i = 1; i <= n; i++) { if (i != bv && !ca[i]) dfs(i), col++; } for (int i = 1; i < col && uwu < 2; i++) { cntA = 0, flag2 = false, pa.clear(); dfs3(bv, i); } cnt = 0; for (int i = 1; i <= n; i++) { if (vis[i]) cnt++; } if (cnt == n || uwu != 2) cout << NO n ; else { cout << YES n << n - cnt << n ; for (int i = 1; i <= n; i++) if (!vis[i]) cout << i << ; cout << n ; } } else cout << NO n ; } } for (int i = 0; i <= n; i++) adj[i].clear(), h[i] = par[i] = 0, vis[i] = mark[i] = false, ans[i] = 0, g[i] = false, ca[i] = 0; a = b = c = av = bv = cv = 0, cnt = 0, y = 0, flag2 = false, cntA = 0; } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(const T &x) { return x * x; } inline long long sqr(int x) { return sqr<long long>(x); } template <class T> T binpow(const T &a, long long n) { return n == 0 ? 1 : sqr(binpow(a, n / 2)) * (n % 2 ? a : 1); } long long binpow(long long a, long long n, long long modulo) { return n == 0 ? 1 : sqr(binpow(a, n / 2, modulo)) % modulo * (n % 2 ? a : 1) % modulo; } long long gcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } inline long long phi(long long n) { long long result = n; for (long long i = 2; i * i <= n; ++i) if (n % i == 0) { while (n % i == 0) n /= i; result -= result / i; } if (n > 1) result -= result / n; return result; } inline vector<long long> inverseAll(long long m) { vector<long long> r(m); r[1] = 1; for (int i = 2; i < m; ++i) r[i] = (m - (m / i) * r[m % i] % m) % m; return r; } inline long long gcd(long long a, long long b) { return gcd(a, b, a, b); } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long llrand() { const long long lsbToFill = (sizeof(long long) << 3) - 1; const long long bitsFilledInIteration = __builtin_popcountll(RAND_MAX); long long number = 0; for (long long lsbFilled = 0; lsbFilled <= lsbToFill; lsbFilled += bitsFilledInIteration) { number ^= (((long long)rand()) << lsbFilled); } return number & numeric_limits<long long>::max(); } inline long long llrand(long long begin, long long end) { return begin + llrand() % (end - begin); } struct Dinic { struct Edge { int u, v; long long cap, flow; Edge() {} Edge(int u, int v, long long cap) : u(u), v(v), cap(cap), flow(0) {} }; int N; vector<Edge> E; vector<vector<int>> g; vector<int> d, pt; Dinic(int N) : N(N), E(0), g(N), d(N), pt(N) {} void AddEdge(int u, int v, long long cap) { if (u != v) { E.emplace_back(Edge(u, v, cap)); g[u].emplace_back(E.size() - 1); E.emplace_back(Edge(v, u, 0)); g[v].emplace_back(E.size() - 1); } } bool BFS(int S, int T) { queue<int> q({S}); fill(d.begin(), d.end(), N + 1); d[S] = 0; while (!q.empty()) { int u = q.front(); q.pop(); if (u == T) break; for (int k : g[u]) { Edge &e = E[k]; if (e.flow < e.cap && d[e.v] > d[e.u] + 1) { d[e.v] = d[e.u] + 1; q.emplace(e.v); } } } return d[T] != N + 1; } long long DFS(int u, int T, long long flow = -1) { if (u == T || flow == 0) return flow; for (int &i = pt[u]; i < g[u].size(); ++i) { Edge &e = E[g[u][i]]; Edge &oe = E[g[u][i] ^ 1]; if (d[e.v] == d[e.u] + 1) { long long amt = e.cap - e.flow; if (flow != -1 && amt > flow) amt = flow; if (long long pushed = DFS(e.v, T, amt)) { e.flow += pushed; oe.flow -= pushed; return pushed; } } } return 0; } long long MaxFlow(int S, int T) { long long total = 0; while (BFS(S, T)) { fill(pt.begin(), pt.end(), 0); while (long long flow = DFS(S, T)) total += flow; } return total; } }; vector<long long> Dijkstra(const vector<list<pair<int, long long>>> &g, int s) { vector<long long> d(int((g).size()), numeric_limits<long long>::max() / 2LL); priority_queue<pair<long long, int>> q; d[s] = 0; q.emplace(-0, s); while (!q.empty()) { while (q.top().first > d[q.top().second]) { q.pop(); } int v = q.top().second; q.pop(); for (const auto &cw : g[v]) { if (d[v] + cw.second < d[cw.first]) { d[cw.first] = d[v] + cw.second; q.emplace(-d[cw.first], cw.first); } } } return d; } struct BinarySearchIterator : public std::iterator<std::forward_iterator_tag, bool> { long long value; typename iterator_traits<BinarySearchIterator>::difference_type operator-( const BinarySearchIterator &it) const { return value - it.value; } BinarySearchIterator &operator++() { ++value; return *this; } bool operator!=(const BinarySearchIterator &it) const { return value != it.value; } bool operator*() const { return true; } }; template <int ALPHA> class AhoCorasick { public: static const int ILLEGAL_INDEX; static const int ROOT; struct Node { bool leaf; int parent; int parentCharacter; int link; int next[ALPHA]; int go[ALPHA]; int outputFunction; Node(int parent = ILLEGAL_INDEX, int parentCharacter = ALPHA) : leaf(false), parent(parent), parentCharacter(parentCharacter), link(ILLEGAL_INDEX), outputFunction(ILLEGAL_INDEX) { fill_n(next, ALPHA, ILLEGAL_INDEX); fill_n(go, ALPHA, ILLEGAL_INDEX); } }; vector<Node> tree = vector<Node>(1); AhoCorasick() {} AhoCorasick(int maxStatesNumber) { tree.reserve(maxStatesNumber); } template <class Iterator> void add(int length, const Iterator begin) { int vertex = ROOT; for (int i = 0; i < length; ++i) { if (ILLEGAL_INDEX == tree[vertex].next[begin[i]]) { tree[vertex].next[begin[i]] = int((tree).size()); tree.push_back(Node(vertex, begin[i])); } vertex = tree[vertex].next[begin[i]]; } tree[vertex].leaf = true; } int getLink(int vertex) { assert(0 <= vertex && vertex < tree.size()); if (ILLEGAL_INDEX == tree[vertex].link) { if (ROOT == vertex || ROOT == tree[vertex].parent) { tree[vertex].link = ROOT; } else { tree[vertex].link = go(getLink(tree[vertex].parent), tree[vertex].parentCharacter); } } return tree[vertex].link; } int go(int vertex, int character) { assert(0 <= character && character < ALPHA); assert(0 <= vertex && vertex < tree.size()); if (ILLEGAL_INDEX == tree[vertex].go[character]) { if (ILLEGAL_INDEX == tree[vertex].next[character]) { tree[vertex].go[character] = ROOT == vertex ? ROOT : go(getLink(vertex), character); } else { tree[vertex].go[character] = tree[vertex].next[character]; } } return tree[vertex].go[character]; } int getOutputFunction(int vertex) { assert(0 <= vertex && vertex < tree.size()); if (ILLEGAL_INDEX == tree[vertex].outputFunction) { if (tree[vertex].leaf || ROOT == vertex) { tree[vertex].outputFunction = vertex; } else { tree[vertex].outputFunction = getOutputFunction(getLink(vertex)); } } return tree[vertex].outputFunction; } }; template <int ALPHA> const int AhoCorasick<ALPHA>::ILLEGAL_INDEX = -1; template <int ALPHA> const int AhoCorasick<ALPHA>::ROOT = 0; int main(int argc, const char *argv[]) { ios::sync_with_stdio(false); cin.tie(0); srand((unsigned int)time(NULL)); int n; while (cin >> n) { vector<long long> s(n); for (int i = (0); i < (n); ++i) { cin >> s[i]; } vector<long long> ps(n + 1, 0); partial_sum((s).begin(), (s).end(), ps.begin() + 1); int q; cin >> q; for (int i = (0); i < (q); ++i) { int l, r; cin >> l >> r; --l; --r; cout << (ps[r + 1] - ps[l]) / 10 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300005; struct Point { int x, y; Point(int _x = 0, int _y = 0) { x = _x; y = _y; } Point operator-(const Point &R) const { return Point(x - R.x, y - R.y); } long long operator^(const Point &R) const { return (long long)x * R.y - (long long)y * R.x; } long long operator%(const Point &R) const { return (long long)x * R.x + (long long)y * R.y; } bool operator<(const Point &R) const { if (x != R.x) return x < R.x; return y < R.y; } }; int n, m, p; Point W[N], K[N]; map<Point, int> Hash; long long res[N], ans[N]; int a[N]; bool cmpP(const int &A, const int &B) { return W[A] < W[B]; } bool cmpQ(const int &A, const int &B) { return (long long)K[A].x * K[B].y < (long long)K[B].x * K[A].y; } void update(vector<int> &P, vector<int> &Q) { if (P.empty() || Q.empty()) return; sort(P.begin(), P.end(), cmpP); vector<int> A, B; for (int i = 0; i < Q.size(); ++i) if (K[Q[i]].y >= 0) { A.push_back(Q[i]); } sort(A.begin(), A.end(), cmpQ); vector<Point> s(P.size() + 1); int t = 0; for (int i = 0; i < P.size(); ++i) { Point D = W[P[i]]; while (t > 1 && ((D - s[t - 2]) ^ (s[t - 1] - s[t - 2])) <= 0) --t; s[t++] = D; } for (int i = 0, j = 0; i < A.size(); ++i) { while (j + 1 < t && (K[A[i]] % s[j + 1]) >= (K[A[i]] % s[j])) ++j; res[A[i]] = max(res[A[i]], K[A[i]] % s[j]); } t = 0; for (int i = 0; i < P.size(); ++i) { Point D = W[P[i]]; while (t > 1 && ((D - s[t - 2]) ^ (s[t - 1] - s[t - 2])) >= 0) --t; s[t++] = D; } } int del[N]; void divide(const vector<int> &A) { if (A.size() <= 1) return; vector<int> P, Q; int r = A.size(), mid = r / 2; for (int i = 0; i < mid; ++i) P.push_back(A[i]); divide(P); P.clear(); for (int i = 0; i < r; ++i) if (A[i] > 0 && (A[i] & 1)) del[A[i] >> 1] = 1; for (int i = 0; i < mid; ++i) if (A[i] > 0 && (~A[i] & 1)) { if (!del[A[i] >> 1]) P.push_back(A[i] >> 1); else del[A[i] >> 1] = 2; } for (int i = mid; i < r; ++i) if (A[i] < 0) Q.push_back(-A[i]); update(P, Q); Q.clear(); int c1 = 0, c2 = 0; for (int i = r - 1; i >= mid; --i) { if (A[i] > 0 && (A[i] & 1) && del[A[i] >> 1] == 2) { Q.push_back(A[i] ^ 1); ++c1; } else if (A[i] < 0) { Q.push_back(A[i]); ++c2; } } for (int i = 0; i < r; ++i) if (A[i] > 0 && (A[i] & 1)) del[A[i] >> 1] = 0; if (c1 && c2) divide(Q); P.clear(); for (int i = mid; i < r; ++i) P.push_back(A[i]); divide(P); } int iid[N]; void work() { scanf( %d , &n); vector<int> A; for (int i = 0; i < n; ++i) { Point S; scanf( %d , &a[i]); if (a[i] == 3) { scanf( %d , &S.x); S.y = 1; ++m; res[m] = -1LL << 60; K[m] = S; a[i] = -m; } else { if (a[i] == 1) { scanf( %d%d , &S.x, &S.y); W[++p] = S; iid[i] = p; a[i] = p << 1; } else { int j; scanf( %d , &j); a[i] = iid[j - 1] << 1 | 1; } } A.push_back(a[i]); } divide(A); for (int i = 1; i <= m; ++i) { if (res[i] == -1LL << 60) { puts( EMPTY SET ); } else { printf( %lld n , res[i]); } } } int main() { work(); return 0; } |
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