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#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const double eps = (double)1e-8; const int mod = (int)1000000007; const int maxn = (int)2 * 1e5 + 5; int n, x, y, mx; int u[maxn], pr[maxn]; pair<int, int> t[maxn]; vector<pair<int, int> > a[maxn]; vector<int> ans; list<int> q; list<int>::iterator it1; void dzen(int v, int p) { pr[v] = p; if (a[v].size() > 1 || v == 1) { q.push_back(v); u[v] = 0; if (a[v][0].first == p) u[v] = 1; } mx = max((int)a[v].size(), mx); for (int i = (0); i < (a[v].size()); i++) { if (a[v][i].first == p) continue; dzen(a[v][i].first, v); } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = (2); i <= (n); i++) { cin >> x >> y; a[x].push_back(make_pair(y, i - 1)); a[y].push_back(make_pair(x, i - 1)); } mx = 0; dzen(1, 0); memset(t, -1, sizeof t); cout << mx << n ; while (mx--) { ans.clear(); for (list<int>::iterator it = q.begin(); it != q.end();) { if (t[pr[*it]].first == mx && t[pr[*it]].second == *it) { it++; continue; } t[*it] = make_pair(mx, a[*it][u[*it]].first); ans.push_back(a[*it][u[*it]].second); u[*it]++; if (u[*it] < (int)a[*it].size() && a[*it][u[*it]].first == pr[*it]) u[*it]++; if (u[*it] == (int)a[*it].size()) { it1 = it; it++; q.erase(it1); } else it++; } cout << ans.size() << ; for (int i = (0); i < (ans.size()); i++) { cout << ans[i] << ; } cout << n ; } return 0; }
|
// tuner_slice.v - one leg of real->complex tuner
// 07-17-16 E. Brombaugh
module tuner_slice #(
parameter dsz = 10,
psz = 10
)
(
input clk, reset, shf_90,
input signed [dsz-1:0] in,
input [psz-1:0] phs,
output reg signed [dsz-1:0] out
);
// split acc into quadrant and address and delay sign bit
wire [1:0] p_quad = phs[psz-1:psz-2] + {1'b0,shf_90};
reg [1:0] quad;
reg [psz-3:0] addr;
reg sincos_sign;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
quad <= 2'b0;
addr <= 8'b0;
sincos_sign <= 1'b0;
end
else
begin
quad <= p_quad;
addr <= phs[psz-3:0] ^ {8{p_quad[0]}};
sincos_sign <= quad[1];
end
end
// look up 8-bit 1/4 cycle sine
reg signed [15:0] sine_lut[0:255];
reg signed [15:0] sincos_raw;
initial
begin
$readmemh("../src/sine_table.memh", sine_lut);
end
always @(posedge clk)
begin
sincos_raw <= sine_lut[addr];
end
// invert sign of lut output and delay to align
reg signed [15:0] sincos_p, sincos;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
sincos_p <= 16'h0000;
sincos <= 16'h0000;
end
else
begin
sincos_p <= sincos_sign ? -sincos_raw : sincos_raw;
sincos <= sincos_p;
end
end
// multiply, round, saturate
reg signed [dsz+16-1:0] mult;
wire signed [dsz+1:0] out_rnd = mult[dsz+16-1:14] + 12'd1;
wire signed [dsz-1:0] out_sat;
sat #(.isz(dsz+1),.osz(dsz))
u_sat(.in(out_rnd[dsz+1:1]),.out(out_sat));
always @(posedge clk)
begin
if(reset == 1'b1)
begin
mult <= {dsz+16{1'b0}};
out <= {dsz{1'b0}};
end
else
begin
mult <= in * sincos;
out <= out_sat;
end
end
endmodule
|
`timescale 1ns / 1ps
// @module
// display time on segment
// @input
// clk_src: clock source
// sec_data: raw seconds info
// min_data: raw minutes info
// hour_data: raw hours info
// @output
// anodes: bind to board for displaying time
// cnodes: bind to board for displaying time
module time_displayer
#(parameter WIDTH = 32)
(
input clk_src,
input [(WIDTH-1):0] sec_data,
input [(WIDTH-1):0] min_data,
input [(WIDTH-1):0] hour_data,
output reg [7:0] anodes,
output reg [7:0] cnodes
);
reg [2:0] count; // 2^3 = 8
wire [15:0] sec_seg, min_seg, hour_seg;
time_to_segment SEC_SEG (
.time_data(sec_data),
.seg_data(sec_seg)
);
time_to_segment MIN_SEG (
.time_data(min_data),
.seg_data(min_seg)
);
time_to_segment HOUR_SEG (
.time_data(hour_data),
.seg_data(hour_seg)
);
initial begin
count <= 0;
anodes <= 0;
cnodes <= 0;
end
always @(posedge clk_src) begin
count = count + 1;
end
/*
* use a 1000Hz to switch which segment light on,
* making looks like there are multiple lights on at the same time.
*/
always @(count) begin
case (count)
3'b000: begin
anodes = 8'b11111110;
cnodes = sec_seg[7:0];
end
3'b001: begin
anodes = 8'b11111101;
cnodes = sec_seg[15:8];
end
3'b010: begin
anodes = 8'b11111011;
cnodes = 8'b10111111;
end
3'b011: begin
anodes = 8'b11110111;
cnodes = min_seg[7:0];
end
3'b100: begin
anodes = 8'b11101111;
cnodes = min_seg[15:8];
end
3'b101: begin
anodes = 8'b11011111;
cnodes = 8'b10111111;
end
3'b110: begin
anodes = 8'b10111111;
cnodes = hour_seg[7:0];
end
3'b111: begin
anodes = 8'b01111111;
cnodes = hour_seg[15:8];
end
default: begin
anodes = 8'b11111110;
cnodes = 8'b11111111;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 2) { cout << 1 2 << endl; return 0; } bool usedN = false; for (int i = 0; i < n; i++) { int maxi = 0; for (int j = 0; j < n; j++) { int a; cin >> a; if (a > maxi) { maxi = a; } } if (maxi == n - 1 && !usedN) { usedN = true; maxi = n; } cout << maxi << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x, y = 0, z = 0; for (int i = 0; i < n; i++) { cin >> x; if (x != y) { z++; } y = x; } cout << z; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int x1, x2, a, b; int main() { while (cin >> x1 >> x2 >> a >> b) { bool ch = false; if (x1 > x2) { swap(x1, x2); swap(a, b); a = -a; b = -b; ch = true; } int dif = abs(x1 - x2); if (a <= 0) { if (dif <= b) cout << FIRST << endl << (ch ? x1 : x2) << endl; else cout << DRAW << endl; } else { int rem = dif % (a + b); if (rem == 0) cout << SECOND << endl; else if (rem >= a && rem <= b) cout << FIRST << endl << (ch ? x2 - rem : x1 + rem) << endl; else cout << DRAW << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, m, pos[N], ans[N]; vector<int> g[N]; map<int, int> tot; struct data { int a, i; } a[N]; bool cmp(data u, data v) { return u.a > v.a; } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i].a), a[i].i = i; ++tot[a[i].a]; } sort(a + 1, a + 1 + n, cmp); for (int i = 1; i <= n; ++i) pos[a[i].i] = i; for (int i = 1, x, y; i <= m; ++i) { scanf( %d%d , &x, &y); x = pos[x], y = pos[y]; g[x].push_back(y); g[y].push_back(x); } int cnt = n; a[0].a = -1; for (int i = 1; i <= n; ++i) { int s = g[i].size(); if (a[i].a != a[i - 1].a) cnt -= tot[a[i].a]; ans[a[i].i] = cnt; for (int j = 0; j < s; ++j) if (g[i][j] > i && a[g[i][j]].a != a[i].a) --ans[a[i].i]; } for (int i = 1; i <= n; ++i) printf( %d , ans[i]); return 0; }
|
`timescale 1ns/1ps
module test;
reg pass;
reg c1reg,c2reg;
wire rla, rlc, rlo;
wire rha, rhc, rho;
wire c1 = c1reg;
wire c2 = c2reg;
// Pull the pins opposite to the arm.
pulldown pd1 (rla);
pullup (weak1) pu1 (rlc,rlo);
pulldown (weak0) pd2 (rhc,rho);
pullup pu2 (rha);
SPDT_RELAY rl (.COIL1(c1), .COIL2(c2), .ARM(rla), .NC(rlc), .NO(rlo));
SPDT_RELAY rh (.COIL1(c1), .COIL2(c2), .ARM(rha), .NC(rhc), .NO(rho));
initial begin
pass = 1'b1;
// Test both coil terminals low.
c1reg = 0;
c2reg = 0;
#10;
if (rla !== 1'b0 || rlo !== 1'b1 || rlc !== 1'b0) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b0 || rhc !== 1'b1) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
// Test c1 low and c2 high.
c2reg = 1;
#10;
if (rla !== 1'b0 || rlo !== 1'b0 || rlc !== 1'b1) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b1 || rhc !== 1'b0) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
// Test both coil terminal high.
c1reg = 1;
#10;
if (rla !== 1'b0 || rlo !== 1'b1 || rlc !== 1'b0) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b0 || rhc !== 1'b1) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
// Test c1 high and c2 low.
c2reg = 0;
#10;
if (rla !== 1'b0 || rlo !== 1'b0 || rlc !== 1'b1) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b1 || rhc !== 1'b0) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
if (pass) $display ("PASSED");
$finish;
end
endmodule
module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO);
inout COIL1, COIL2, ARM, NC, NO;
wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) ||
((COIL1===1'b0) && (COIL2===1'b1));
wire #1 dly_coil = coil;
wire coil_on = coil & dly_coil;
wire coil_off = !coil & !dly_coil;
tranif1 t1 (ARM,NC,coil_off);
tranif1 t2 (ARM,NO,coil_on);
endmodule
|
// hps_design_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
hps_design_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int SQ = 350; const int MAX_N = 100000; deque<int> a[MAX_N / SQ + 10]; int num[MAX_N / SQ + 10][MAX_N + 10]; int N, Q, lastans = 0; void print() { for (int i = 0; i <= N / SQ; i++) { for (int j = 0; j < a[i].size(); j++) { cout << a[i][j] << ; } } cout << endl; return; } int main() { scanf( %d , &N); for (int i = 0; i < N; i++) { int x = i / SQ, k; scanf( %d , &k); a[x].push_back(k); num[x][k]++; } scanf( %d , &Q); for (int i = 0; i < Q; i++) { int type, l, r, k; scanf( %d , &type); if (type == 1) { scanf( %d %d , &l, &r); l = (l + lastans - 1) % N; r = (r + lastans - 1) % N; if (l > r) swap(l, r); int lx = l / SQ, ly = l % SQ, rx = r / SQ, ry = r % SQ; if (lx == rx) { int f = a[rx][ry]; a[rx].erase(a[rx].begin() + ry); a[rx].insert(a[rx].begin() + ly, f); } else { int f = a[rx][ry]; a[rx].erase(a[rx].begin() + ry); num[rx][f]--; for (int j = lx; j < rx; j++) { int b = a[j].back(); a[j].pop_back(); a[j + 1].push_front(b); num[j][b]--; num[j + 1][b]++; } a[lx].insert(a[lx].begin() + ly, f); num[lx][f]++; } } else { scanf( %d %d %d , &l, &r, &k); l = (l + lastans - 1) % N; r = (r + lastans - 1) % N; k = (k + lastans - 1) % N + 1; if (l > r) swap(l, r); int lx = l / SQ, ly = l % SQ, rx = r / SQ, ry = r % SQ; int ans = 0; if (lx == rx) { for (int j = ly; j <= ry; j++) if (a[lx][j] == k) ans++; } else { for (int j = ly; j < SQ; j++) if (a[lx][j] == k) ans++; for (int j = lx + 1; j < rx; j++) ans += num[j][k]; for (int j = 0; j <= ry; j++) if (a[rx][j] == k) ans++; } lastans = ans; printf( %d n , ans); } } return 0; }
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#include <bits/stdc++.h> using namespace std; long long int modExp(long long int base, long long int power) { if (power == 0) { return 1; } else { long long int cur = modExp(base, power / 2); cur = cur * cur; cur = cur % 1000000007; if (power % 2 == 1) cur = cur * base; cur = cur % 1000000007; return cur; } } void solve() { long long int n, k, l, r, sall, sk; cin >> n >> k >> l >> r >> sall >> sk; vector<long long int> ans; long long int temp = sk / k; long long int num = sk - temp * k; for (long long int i = 0; i < num; i++) { ans.push_back(temp + 1); } for (long long int i = 0; i < k - num; i++) { ans.push_back(temp); } if (n - k != 0) { temp = (sall - sk) / (n - k); num = (sall - sk) - (temp * (n - k)); for (long long int i = 0; i < num; i++) { ans.push_back(temp + 1); } for (long long int i = 0; i < n - k - num; i++) { ans.push_back(temp); } } sort(ans.begin(), ans.end()); for (long long int i = 0; i < n; i++) { cout << ans[i] << ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> const long long pinf = ((long long)2e18); const long long ninf = ((long long)-2e18); const long long mod = 1000000007; using namespace std; long long power(long long x, long long n, long long M) { if (n == 0) return 1; else if (n % 2 == 0) return power((x * x) % M, n / 2, M); else return (x * power((x * x) % M, (n - 1) / 2, M)) % M; } bool vowel(char c) { return (c == a or c == e or c == i or c == o or c == u or c == A or c == E or c == I or c == U or c == O ); } int32_t main() { ; ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { long long n; cin >> n; vector<long long> a(n), b(n); map<long long, long long> make_pair; for (long long i = 0; i < n; i++) { cin >> a[i]; make_pair[a[i]]++; b[i] = a[i]; } sort(b.begin(), b.end()); long long p = 0; long long ans = 0; long long l = 0, r = n - 1; while (l < r) { if (make_pair[b[p]]) { if (a[l] == b[p]) { make_pair[a[l]]--; p++; l++; } else if (a[r] == b[p]) { make_pair[a[r]]--; r--; p++; } else { make_pair[a[l]]--; l++; ans = l; } } else { p++; } } cout << ans << n ; } return 0; }
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//
// Paul Gao 06/2019
//
// This is an adapter from bsg_noc_ready_and_link to bsg_wormhole_link
// It assumes that wormhole link and bsg_noc link are in different clock regions, two
// asynchronous fifos are instantiated in this adapter to cross the clock domain.
//
// It also assumes that the ral (ready_and_link) packet always have fixed width
//
// Note: Just because you can connect the wormhole network to the mesh network does not
// mean that it will not deadlock if traffic classes are not correctly separated.
//
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_ready_and_link_async_to_wormhole
#(// ral link parameters
parameter `BSG_INV_PARAM(ral_link_width_p )
// Wormhole link parameters
,parameter `BSG_INV_PARAM(flit_width_p )
,parameter dims_p = 2
,parameter int cord_markers_pos_p[dims_p:0] = '{5, 4, 0}
,parameter `BSG_INV_PARAM(len_width_p )
,localparam ral_link_sif_width_lp = `bsg_ready_and_link_sif_width(ral_link_width_p)
,localparam wormhole_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
,localparam cord_width_lp = cord_markers_pos_p[dims_p]
)
(// ral (ready_and_link) side
input ral_clk_i
,input ral_reset_i
,input [ral_link_sif_width_lp-1:0] ral_link_i
,output [ral_link_sif_width_lp-1:0] ral_link_o
// ral_dest_cord_i is logically associated with ral_link_i, and that the value must
// be held constant until the element is removed from ral_link_i.
,input [cord_width_lp-1:0] ral_dest_cord_i
// Wormhole side
,input wh_clk_i
,input wh_reset_i
,input [wormhole_link_sif_width_lp-1:0] wh_link_i
,output [wormhole_link_sif_width_lp-1:0] wh_link_o
);
// 8 elements should be enough to handle roundtrip latency across async clock domain
localparam lg_fifo_depth_lp = 3;
genvar i;
/********************* Packet definition *********************/
// Define wormhole packet
`declare_bsg_wormhole_router_header_s(cord_width_lp, len_width_p, bsg_wormhole_hdr_s);
typedef struct packed {
logic [ral_link_width_p-1:0] data;
bsg_wormhole_hdr_s hdr;
} wormhole_packet_s;
// Determine PISO and SIPOF convertion ratio
localparam wormhole_width_lp = $bits(wormhole_packet_s);
localparam wormhole_ratio_lp = `BSG_CDIV(wormhole_width_lp, flit_width_p);
// synopsys translate_off
initial
begin
assert (len_width_p >= `BSG_SAFE_CLOG2(wormhole_ratio_lp))
else $error("Wormhole packet len width %d is too narrow for convertion ratio %d. Please increase len width.", len_width_p, wormhole_ratio_lp);
end
// synopsys translate_on
/********************* Interfacing ral and wh link *********************/
`declare_bsg_ready_and_link_sif_s(ral_link_width_p, bsg_ral_link_s);
bsg_ral_link_s ral_link_i_cast, ral_link_o_cast;
assign ral_link_i_cast = ral_link_i;
assign ral_link_o = ral_link_o_cast;
// declare wormhole packet
wormhole_packet_s ral_piso_data_li_cast, ral_sipof_data_lo_cast;
always_comb
begin
// to wormhole
ral_piso_data_li_cast.hdr.cord = ral_dest_cord_i;
ral_piso_data_li_cast.hdr.len = wormhole_ratio_lp-1;
ral_piso_data_li_cast.data = ral_link_i_cast.data;
// from wormhole
ral_link_o_cast.data = ral_sipof_data_lo_cast.data;
end
`declare_bsg_ready_and_link_sif_s(flit_width_p, wormhole_link_sif_s);
wormhole_link_sif_s wh_link_i_cast, wh_link_o_cast;
assign wh_link_i_cast = wh_link_i;
assign wh_link_o = wh_link_o_cast;
/********************* ral -> wormhole link *********************/
// PISO signals
logic [wormhole_ratio_lp*flit_width_p-1:0] ral_piso_data_li;
assign ral_piso_data_li = (wormhole_ratio_lp*flit_width_p)'(ral_piso_data_li_cast);
// Async fifo signals
logic ral_async_fifo_valid_li, ral_async_fifo_yumi_lo;
logic [flit_width_p-1:0] ral_async_fifo_data_li;
// piso
bsg_parallel_in_serial_out
#(.width_p(flit_width_p)
,.els_p (wormhole_ratio_lp)
) piso
(.clk_i (ral_clk_i )
,.reset_i(ral_reset_i)
,.valid_i(ral_link_i_cast.v )
,.data_i (ral_piso_data_li )
,.ready_and_o(ral_link_o_cast.ready_and_rev)
,.valid_o(ral_async_fifo_valid_li )
,.data_o (ral_async_fifo_data_li )
,.yumi_i (ral_async_fifo_yumi_lo )
);
// ral side async fifo input
logic ral_async_fifo_full_lo;
assign ral_async_fifo_yumi_lo = ~ral_async_fifo_full_lo & ral_async_fifo_valid_li;
// This async fifo crosses from ral clock to wormhole clock
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (flit_width_p )
) ral_to_wh
(.w_clk_i (ral_clk_i )
,.w_reset_i(ral_reset_i)
,.w_enq_i (ral_async_fifo_yumi_lo)
,.w_data_i (ral_async_fifo_data_li)
,.w_full_o (ral_async_fifo_full_lo)
,.r_clk_i (wh_clk_i )
,.r_reset_i(wh_reset_i)
,.r_deq_i (wh_link_o_cast.v & wh_link_i_cast.ready_and_rev)
,.r_data_o (wh_link_o_cast.data)
,.r_valid_o(wh_link_o_cast.v )
);
/********************* wormhole -> ral link *********************/
// Async fifo signals
logic ral_async_fifo_valid_lo, ral_async_fifo_ready_li;
logic [flit_width_p-1:0] ral_async_fifo_data_lo;
// ral side async fifo output
logic ral_async_fifo_deq_li;
assign ral_async_fifo_deq_li = ral_async_fifo_ready_li & ral_async_fifo_valid_lo;
// Wormhole side async fifo input
logic wh_async_fifo_full_lo;
assign wh_link_o_cast.ready_and_rev = ~wh_async_fifo_full_lo;
// This async fifo crosses from wormhole clock to ral clock
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (flit_width_p )
) wh_to_ral
(.w_clk_i (wh_clk_i )
,.w_reset_i(wh_reset_i)
,.w_enq_i (wh_link_i_cast.v & wh_link_o_cast.ready_and_rev)
,.w_data_i (wh_link_i_cast.data )
,.w_full_o (wh_async_fifo_full_lo)
,.r_clk_i (ral_clk_i )
,.r_reset_i(ral_reset_i)
,.r_deq_i (ral_async_fifo_deq_li )
,.r_data_o (ral_async_fifo_data_lo )
,.r_valid_o(ral_async_fifo_valid_lo)
);
// SIPOF signals
logic [wormhole_ratio_lp*flit_width_p-1:0] ral_sipof_data_lo;
assign ral_sipof_data_lo_cast = ral_sipof_data_lo[wormhole_width_lp-1:0];
// sipof
bsg_serial_in_parallel_out_full
#(.width_p(flit_width_p)
,.els_p (wormhole_ratio_lp)
) sipof
(.clk_i (ral_clk_i )
,.reset_i(ral_reset_i )
,.v_i (ral_async_fifo_valid_lo)
,.ready_o(ral_async_fifo_ready_li)
,.data_i (ral_async_fifo_data_lo )
,.data_o (ral_sipof_data_lo )
,.v_o (ral_link_o_cast.v )
,.yumi_i (ral_link_o_cast.v & ral_link_i_cast.ready_and_rev)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_ready_and_link_async_to_wormhole)
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#include <bits/stdc++.h> using namespace std; template <class T> void read(vector<T> &a, long long n) { T x; a.clear(); for (long long i = 0; i < n; i++) { cin >> x; a.push_back(x); } } template <class T> void write(vector<T> &a) { for (T x : a) cout << x << ; cout << endl; } const int N = 300005; const int S = 500; long long sum[S][S]; long long ans[N]; vector<pair<pair<int, int>, int> > q; int n, m; int w[N]; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) cin >> w[i]; cin >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; q.push_back(make_pair(make_pair(a, b), i)); } sort(q.begin(), q.end()); reverse(q.begin(), q.end()); int pos = n; for (int i = 0; i < q.size(); i++) { int a = q[i].first.first; int b = q[i].first.second; int id = q[i].second; while (pos >= a) { for (int j = 1; j < S; j++) sum[j][pos % j] += w[pos]; pos--; } if (b < S) ans[id] = sum[b][a % b]; else { long long res = 0; for (int j = a; j <= n; j += b) res += w[j]; ans[id] = res; } } for (int i = 0; i < m; i++) cout << ans[i] << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int MN = 1 << 8; int exp(int x, int n) { int ret = 1; while (n) { if (n & 1) ret = 1LL * ret * x % mod; x = 1LL * x * x % mod; n >>= 1; } return ret; } int inv(int x) { return exp(x, mod - 2); } int fact[MN], invf[MN]; int comb(int n, int k) { return 1LL * fact[n] * invf[k] % mod * invf[n - k] % mod; } int fa[MN]; void init() { for (int i = 0; i < MN; i++) fa[i] = i; } int find(int u) { if (fa[u] == u) return u; else return fa[u] = find(fa[u]); } void mrg(int u, int v) { u = find(u); v = find(v); if (u == v) return; fa[v] = u; } int cc[MN][MN]; int dp(int n, int k) { int &ret = cc[n][k]; if (ret != -1) return ret; if (k == 0) return ret = n == 0; ret = 0; for (int i = 1; i <= n; i++) { ret += 1LL * comb(n - 1, i - 1) * fact[i - 1] % mod * dp(n - i, k - 1) % mod; ret %= mod; } return ret; } int N; int A[MN], B[MN], del[MN], chk[MN], tcnt[3], ans[MN]; int main() { fact[0] = 1; for (int i = 1; i < MN; i++) { fact[i] = 1LL * fact[i - 1] * i % mod; } for (int i = 0; i < MN; i++) { invf[i] = inv(fact[i]); } memset(cc, -1, sizeof(cc)); scanf( %d , &N); for (int i = 0; i < N; i++) { scanf( %d , &A[i]); A[i]--; } for (int i = 0; i < N; i++) { scanf( %d , &B[i]); B[i]--; } int ccnt = 0; init(); for (int i = 0; i < N; i++) { if (A[i] != -1 && B[i] != -1) { if (find(A[i]) == find(B[i])) { del[find(A[i])] = 1; ccnt++; } else mrg(A[i], B[i]); } } vector<int> V; for (int i = 0; i < N; i++) if (!del[i] && fa[i] == i) V.push_back(i); if (V.size() == 0) { for (int i = 0; i < N; i++) { printf( %d , (N - i == ccnt)); } return 0; } for (int i = 0; i < N; i++) { if (A[i] != -1 && B[i] == -1) { chk[find(A[i])] |= 1; } if (A[i] == -1 && B[i] != -1) { chk[find(B[i])] |= 2; } } for (int i = 0; i < V.size(); i++) { tcnt[chk[V[i]]]++; } for (int i = 1; i <= (int)V.size() - tcnt[3]; i++) { int tmp = 0; for (int j = 0; j <= min(tcnt[1], tcnt[2]); j++) { if (j % 2) tmp += mod - 1LL * comb(tcnt[1], j) * comb(tcnt[2], j) % mod * fact[j] % mod * dp((int)V.size() - tcnt[3] - j, i) % mod; else tmp += 1LL * comb(tcnt[1], j) * comb(tcnt[2], j) % mod * fact[j] % mod * dp((int)V.size() - tcnt[3] - j, i) % mod; tmp %= mod; } ans[ccnt + i] = tmp; } for (int i = 0; i < N; i++) { printf( %d , 1LL * ans[N - i] * fact[tcnt[0]] % mod); } }
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#include <bits/stdc++.h> using namespace std; int n, ans, v[1009], m, c[1009]; vector<int> e; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 2; i <= n; i++) { if (v[i] == 0 and v[i - 1] == 1 and v[i + 1] == 1) c[++m] = i + 1; } ans = m; for (int i = 1; i < m; i++) { if (c[i] + 2 == c[i + 1]) { ans--; c[i] = -1e9, c[i + 1] - 1e9; i++; } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; int main() { string pixels; getline(cin, pixels); getline(cin, pixels); int len = 0, flen = 0, last = pixels.at(0) - 0 ; bool first = false; for (int i = (0); i < (pixels.size()); i += (2)) { if ((pixels.at(i) == 0 && last == 0) || (pixels.at(i) == 1 && last == 1)) len++; else { if (!first) { flen = len; first = true; } else if (flen != len) { printf( NO ); return 0; } len = 1; last = 1 - last; } } if (!flen || flen == len) printf( YES ); else printf( NO ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkbuf (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long pow(long long x, long long v) { if (v == 0) return 1LL; if (v % 2) return (x % MOD) * pow(x % MOD, v - 1) % MOD; return pow((x * x) % MOD, v / 2) % MOD; } int main() { int n; long long x, sum = 0, v, mx = 0; scanf( %d%lld , &n, &x); map<long long, int> cnt; vector<long long> a(n); for (int i = 0; i < n; ++i) scanf( %lld , &a[i]), sum += a[i], mx = max(mx, a[i]); for (int i = 0; i < n; ++i) cnt[sum - a[i]]++; for (map<long long, int>::iterator it = cnt.begin(); it != cnt.end(); ++it) { v = it->first; if (it->second % x == 0) { cnt[v + 1] += it->second / x; } else break; } v = min(v, sum); printf( %lld , pow(x, v)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[50]; double dp[51][51][51]; bool viz[51][51][51]; long long choose[51][51]; double go(int i, int j, int k) { if (i == m - 1) return j <= a[i] * k; double &d = dp[i][j][k]; if (viz[i][j][k]) return d; double res = 0; for (int l = 0; l <= min(j, a[i] * k); l++) { res += choose[j][l] * pow(m - i - 1, j - l) / pow(m - i, j) * go(i + 1, j - l, k); } viz[i][j][k] = 1; return d = res; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) cin >> a[i]; for (int i = 0; i <= n; i++) choose[i][0] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= i; j++) choose[i][j] = choose[i - 1][j - 1] + choose[i - 1][j]; double r = 0; for (int i = 1; i <= n; i++) { double p = go(0, n, i) - go(0, n, i - 1); r += i * p; } printf( %.9lf n , r); }
|
#include <bits/stdc++.h> using namespace std; int MOD = 1000000007; int dp[1001][1001]; int main() { int k; cin >> k; int balls[1000]; int n = 0; for (int i = 0; i < k; i++) { cin >> balls[i]; n += balls[i]; } long long l = 1; for (int i = 0; i <= n; i++) { dp[i][0] = 1; dp[i][i] = 1; for (int j = 1; j <= i; j++) { dp[i][j] = (dp[i - 1][j] + dp[i - 1][j - 1]) % MOD; } } long long ans = 1; int cur = balls[0]; for (int i = 1; i < k; i++) { cur += balls[i]; ans = ((ans % MOD) * (dp[cur - 1][balls[i] - 1]) % MOD) % MOD; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int main() { long long n; scanf( %lld , &n); if (n <= 1) { printf( -1 ); } else { printf( %lld %lld %lld , n, n + 1, n * (n + 1)); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_SYMBOL_V
`define SKY130_FD_SC_HDLL__PROBEC_P_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probec_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_SYMBOL_V
|
#include<bits/stdc++.h> #include<algorithm> #include<iostream> #include<cstdio> #include<cmath> #include<cstring> #include<stack> #include<queue> using namespace std; typedef long long ll; const ll INF=0x7f7f7f7f; const int maxn=2e5+7; const ll mod=1e9+7; ll read(){ ll f=0,x=0;char ch=getchar(); while(!isdigit(ch)){if(ch== - ) f=1;ch=getchar();} while(isdigit(ch)){x=x*10+ch- 0 ;ch=getchar();} return !f?x:-x; } int tt,n,s[maxn]; bool check(int x,int y){ if(x==3){ if(s[y]>=s[y+1]&&s[y+1]>=s[y+2]) return false; if(s[y]<=s[y+1]&&s[y+1]<=s[y+2]) return false; return true; } else{ for(int i=0;i<4;i++){ for(int j=i+1;j<4;j++){ for(int k=j+1;k<4;k++){ if(s[y+i]>=s[y+j]&&s[y+j]>=s[y+k]) return false; if(s[y+i]<=s[y+j]&&s[y+j]<=s[y+k]) return false; } } } return true; } } int main(){ scanf( %d ,&tt); while(tt--){ ll ans=0; scanf( %d ,&n); for(int i=1;i<=n;i++){ scanf( %d ,&s[i]); } ans+=2*n-1; for(int i=3;i<=4;i++){ for(int j=1;j<=n-i+1;j++){ if(check(i,j)) ans++; } } printf( %lld n ,ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtn (
VPWR ,
VGND ,
Q ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input D ;
input GATE_N;
// Local signals
wire gate buf_Q ;
wire gate GATE_N_delayed;
wire gate D_delayed ;
wire GATE ;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; char s[100001], a[5] = hard ; int x[100001]; long long d[5][100001]; const long long inf = 0x3f3f3f3f3f3f3f3f; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %c , &s[i]); for (int i = 1; i <= n; i++) scanf( %d , &x[i]); memset(d, 0x3f, sizeof(d)); for (int i = 0; i < 4; i++) d[i][0] = 0; for (int i = 0; i < 4; i++) { for (int j = 1; j <= n; j++) { if (s[j] == a[i]) { if (i >= 1) d[i][j] = min(d[i - 1][j - 1], d[i][j - 1] + x[j]); else d[i][j] = d[i][j - 1] + x[j]; } else d[i][j] = d[i][j - 1]; } } printf( %lld n , min({d[0][n], d[1][n], d[2][n], d[3][n]})); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long g, x, y, z; int n, m; int nn, mm; deque<long long> q; long long a[3010][3010]; long long b[3010][3010]; long long c[3010][3010]; int main() { scanf( %d%d%d%d , &nn, &mm, &n, &m); scanf( %lld%lld%lld%lld , &g, &x, &y, &z); for (int i = 1; i <= nn; i++) { for (int j = 1; j <= mm; j++) { a[i][j] = g; g = g * x + y; g %= z; } } for (int i = 1; i <= nn; i++) { for (int j = mm; j >= 1; j--) { while (!q.empty() && a[i][q.back()] >= a[i][j]) { q.pop_back(); } q.push_back(j); while (!q.empty() && q.front() - q.back() + 1 > m) { q.pop_front(); } if (j <= mm - m + 1) b[i][j] = a[i][q.front()]; } while (!q.empty()) q.pop_front(); } for (int i = 1; i <= mm - m + 1; i++) { for (int j = nn; j >= 1; j--) { while (!q.empty() && b[q.back()][i] >= b[j][i]) { q.pop_back(); } q.push_back(j); while (!q.empty() && q.front() - q.back() + 1 > n) { q.pop_front(); } if (j <= nn - n + 1) c[j][i] = b[q.front()][i]; } while (!q.empty()) q.pop_front(); } long long ans = 0; for (int i = 1; i <= nn - n + 1; i++) { for (int j = 1; j <= mm - m + 1; j++) { ans += c[i][j]; } } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int p[200010], q, l[200010], c[200010], par[20][200010]; stack<int> st; int main() { int j, i, q, u, v, n; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d , &p[i], &l[i]); l[i] += p[i]; } scanf( %d , &q); memset(par, -1, sizeof(par)); for (i = n - 1; i >= 0; i--) { c[i] = 2e9; while (!st.empty() && l[st.top()] <= l[i]) st.pop(); if (!st.empty()) { int last = st.top(); c[i] = c[last] + max(0, p[last] - l[i]); par[0][i] = last; } else c[i] = 0; for (j = 1; ~par[j - 1][i] && j < 20; j++) { par[j][i] = par[j - 1][par[j - 1][i]]; } st.push(i); } while (q--) { int u, v, lo; scanf( %d%d , &u, &v); u--; v--; lo = u; for (i = 19; i >= 0; i--) { if (~par[i][lo] && par[i][lo] <= v) lo = par[i][lo]; } printf( %d n , c[u] - c[lo]); } }
|
#include <bits/stdc++.h> using namespace std; int n; int x[5001]; int ans[5001][5001]; int init() { int i, j; for (i = 1; i <= n; i++) ans[i][1] = x[i]; for (j = 2; j <= n; j++) { for (i = 1; i + j - 1 <= n; i++) ans[i][j] = ans[i][j - 1] ^ ans[i + 1][j - 1]; } for (j = 2; j <= n; j++) for (i = 1; i + j - 1 <= n; i++) ans[i][j] = max(max(ans[i][j], ans[i][j - 1]), ans[i + 1][j - 1]); return 0; } int main() { int i; cin >> n; for (i = 1; i <= n; i++) cin >> x[i]; init(); int j, k, p, q; cin >> k; while (k--) { cin >> p >> q; cout << ans[p][q - p + 1] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; cout << min(a, b) << << (max(a, b) - min(a, b)) / 2; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_1_V
`define SKY130_FD_SC_HD__NAND3B_1_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3b_1 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3b_1 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_1_V
|
// This counter will counter down from val_i to 0. When the counter
// hits 0, the output clk_r_o will invert. The number of bits wide
// the counter is can be set with the width_p parameter.
//
// Random ideas: could have a variant of this that takes two inputs
// one for the high duty cycle and one for the low duty cycle.
//
`include "bsg_defines.v"
module bsg_counter_clock_downsample #(parameter `BSG_INV_PARAM(width_p ), harden_p=0)
(input clk_i
,input reset_i
,input [width_p-1:0] val_i
,output logic clk_r_o
);
wire strobe_r;
// asserts a "1" every val_i cycles
bsg_strobe #(.width_p(width_p), .harden_p(harden_p)) strobe
(.clk_i
,.reset_r_i(reset_i)
,.init_val_r_i(val_i)
,.strobe_r_o(strobe_r)
);
// Clock output register
always_ff @(posedge clk_i)
begin
if (reset_i)
clk_r_o <= 1'b0;
else if (strobe_r)
clk_r_o <= ~clk_r_o;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_clock_downsample)
|
#include <bits/stdc++.h> using namespace std; int main() { map<char, int> ma; char a; int b; cin >> b; for (int i = 0; i < b; i++) { cin >> a; ma[a]++; } for (auto i : ma) for (int j = 0; j < i.second; j++) cout << i.first; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a; b = 1; while ((b * b + 1) / 2 < a) b += 2; cout << (a == 3 ? 5 : b); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long int n, k, t; cin >> n >> k >> t; if (t < k) cout << t << endl; else if (t > n) cout << k - (t - n) << endl; else cout << k << endl; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_rec #(
parameter BASEADDR = 0,
parameter HIGHADDR = 0,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 2*1024,
parameter IN_BITS = 8
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SEQ_CLK,
input wire [IN_BITS-1:0] SEQ_IN,
input wire SEQ_EXT_START
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
seq_rec_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES),
.IN_BITS(IN_BITS)
) seq_rec_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SEQ_CLK(SEQ_CLK),
.SEQ_IN(SEQ_IN),
.SEQ_EXT_START(SEQ_EXT_START)
);
endmodule
|
/*
DCPU16 Verilog Implementation
Copyright (C) 2012 Shawn Tan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version. This program is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU Lesser General Public
License along with this program. If not, see
<http://www.gnu.org/licenses/>. */
module dcpu16_alu (/*AUTOARG*/
// Outputs
f_dto, g_dto, rwd, regR, regO, CC,
// Inputs
regA, regB, opc, clk, rst, ena, pha
);
output [15:0] f_dto,
g_dto,
rwd;
output [15:0] regR,
regO;
output CC;
input [15:0] regA,
regB;
input [3:0] opc;
input clk,
rst,
ena;
input [1:0] pha;
wire [15:0] src, // a
tgt; // b
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg CC;
reg [15:0] regO;
reg [15:0] regR;
// End of automatics
reg c;
reg [15:0] add;
reg [33:0] mul;
reg [31:0] shl,
shr;
assign f_dto = regR;
assign g_dto = regR;
assign rwd = regR;
assign src = regA;
assign tgt = regB;
// adder
always @(/*AUTOSENSE*/opc or src or tgt) begin
{c,add} <= (~opc[0]) ? (src + tgt) : (src - tgt);
mul <= {1'b0,src} * {1'b0,tgt};
shl <= src << tgt;
shr <= src >> tgt;
end
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
CC <= 1'h0;
regO <= 16'h0;
regR <= 16'h0;
// End of automatics
end else if (ena) begin
// 0x1: SET a, b - sets a to b
// 0x2: ADD a, b - sets a to a+b, sets O to 0x0001 if there's an overflow, 0x0 otherwise
// 0x3: SUB a, b - sets a to a-b, sets O to 0xffff if there's an underflow, 0x0 otherwise
// 0x4: MUL a, b - sets a to a*b, sets O to ((a*b)>>16)&0xffff
// 0x5: DIV a, b - sets a to a/b, sets O to ((a<<16)/b)&0xffff. if b==0, sets a and O to 0 instead.
// 0x6: MOD a, b - sets a to a%b. if b==0, sets a to 0 instead.
// 0x7: SHL a, b - sets a to a<<b, sets O to ((a<<b)>>16)&0xffff
// 0x8: SHR a, b - sets a to a>>b, sets O to ((a<<16)>>b)&0xffff
// 0x9: AND a, b - sets a to a&b
// 0xa: BOR a, b - sets a to a|b
// 0xb: XOR a, b - sets a to a^b
if (pha == 2'o0)
case (opc)
4'h2: regO <= {15'd0,c};
4'h3: regO <= {(16){c}};
4'h4: regO <= mul[31:16];
4'h7: regO <= shl[31:16];
4'h8: regO <= shr[15:0];
default: regO <= regO;
endcase // case (opc)
if (pha == 2'o0)
case (opc)
4'h0: regR <= src;
4'h1: regR <= tgt;
4'h2: regR <= add;
4'h3: regR <= add;
4'h4: regR <= mul[15:0];
4'h7: regR <= shl[15:0];
4'h8: regR <= shr[31:16];
4'h9: regR <= src & tgt;
4'hA: regR <= src | tgt;
4'hB: regR <= src ^ tgt;
default: regR <= 16'hX;
endcase // case (opc)
/*
if (pha == 2'o0)
case (opc)
4'h0: {regO, regR} <= {regO, src};
// 0x1: SET a, b - sets a to b
4'h1: {regO, regR} <= {regO, tgt};
// 0x2: ADD a, b - sets a to a+b, sets O to 0x0001 if there's an overflow, 0x0 otherwise
// 0x3: SUB a, b - sets a to a-b, sets O to 0xffff if there's an underflow, 0x0 otherwise
// 0x4: MUL a, b - sets a to a*b, sets O to ((a*b)>>16)&0xffff
// 0x5: DIV a, b - sets a to a/b, sets O to ((a<<16)/b)&0xffff. if b==0, sets a and O to 0 instead.
// 0x6: MOD a, b - sets a to a%b. if b==0, sets a to 0 instead.
4'h2, 4'h3: {regO, regR} <= (opc[0]) ?
{{(16){c}},as} :
{15'd0,c,as};
4'h4: {regO, regR} <= {1'b0,src} * {1'b0,tgt}; // force 17x17 unsigned
// 0x7: SHL a, b - sets a to a<<b, sets O to ((a<<b)>>16)&0xffff
// 0x8: SHR a, b - sets a to a>>b, sets O to ((a<<16)>>b)&0xffff
4'h7: {regO, regR} <= src << tgt;
4'h8: {regR, regO} <= {src,16'h0} >> tgt;
// 0x9: AND a, b - sets a to a&b
// 0xa: BOR a, b - sets a to a|b
// 0xb: XOR a, b - sets a to a^b
4'h9: {regO, regR} <= {regO, src & tgt};
4'hA: {regO, regR} <= {regO, src | tgt};
4'hB: {regO, regR} <= {regO, src ^ tgt};
default: {regO, regR} <= {regO, 16'hX};
endcase // case (opc)
*/
// 0xc: IFE a, b - performs next instruction only if a==b
// 0xd: IFN a, b - performs next instruction only if a!=b
// 0xe: IFG a, b - performs next instruction only if a>b
// 0xf: IFB a, b - performs next instruction only if (a&b)!=0
if (pha == 2'o0)
case (opc)
4'hC: CC <= (src == tgt);
4'hD: CC <= (src != tgt);
4'hE: CC <= (src > tgt);
4'hF: CC <= |(src & tgt);
default: CC <= 1'b1;
endcase // case (opc)
end
endmodule // dcpu16_alu
|
#include <bits/stdc++.h> using namespace std; const long int m = 1000000007; int prsb(long long int n) { int pos = 0; long long int m = 1; while (!(n & m)) { m = m << 1; pos++; } return pos; } int main() { int t; cin >> t; while (t--) { long long int a, b; cin >> a >> b; long long int x, y, z; int n, c = 0; x = min(a, b); y = max(a, b); z = y / x; if (y % x != 0) { c = -1; } else if (z == 1) { c = 0; } else if (z && (!(z & (z - 1)))) { n = prsb(z); c += n / 3; n = n % 3; c += n / 2; n = n % 2; c += n / 1; } else { c = -1; } cout << c << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 5 + 1e5; int main() { int a, b, c, m, ans = 0; ios::sync_with_stdio(0); cin.tie(); cin >> a >> b; c = a - b; if (c < 0) cout << 0; else if (c == 0) cout << infinity ; else { for (int i = 1; i * i <= c; ++i) { if (c % i == 0) { m = i; if ((m * (a / m)) == c) ++ans; if (i != (c / i)) { m = c / i; if ((m * (a / m)) == c) ++ans; } } } cout << ans; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300500; int n, m, q; vector<int> g[maxn]; bool used[maxn]; int p[maxn], sz[maxn], diameter[maxn]; int maxi, maxiV; void dfs(int v, int depth, int p) { if (depth > maxi) { maxi = depth; maxiV = v; } for (size_t i = 0; i < g[v].size(); i++) { int to = g[v][i]; if (to != p) dfs(to, depth + 1, v); } } int findLongestWay(int v) { maxi = -1; dfs(v, 0, -1); maxi = -1; dfs(maxiV, 0, -1); return maxi; } void init() { for (int i = 1; i <= n; i++) p[i] = i, sz[i] = 1, diameter[i] = 0; } int getSet(int v) { if (p[v] == v) return v; return p[v] = getSet(p[v]); } void unionSets1(int x, int y) { x = getSet(x); y = getSet(y); if (sz[x] > sz[y]) swap(x, y); sz[y] += sz[x]; p[x] = y; } int rad(int x) { return (diameter[x] + 1) / 2; } void unionSets2(int x, int y) { x = getSet(x); y = getSet(y); if (x == y) return; if (sz[x] > sz[y]) swap(x, y); sz[y] += sz[x]; p[x] = y; diameter[y] = max(rad(x) + rad(y) + 1, max(diameter[x], diameter[y])); } int query(int x) { return diameter[getSet(x)]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); ; cin >> n >> m >> q; init(); for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); unionSets1(x, y); } for (int i = 1; i <= n; i++) { int pp = getSet(i); if (!used[pp]) { used[pp] = 1; diameter[pp] = findLongestWay(i); } } while (q--) { int t, x, y; cin >> t; if (t == 2) { cin >> x >> y; unionSets2(x, y); } else { cin >> x; printf( %d n , query(x)); } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int i, n, d, e; cin >> n >> d >> e; e *= 5; int min = n % e; for (i = 0; i <= n / d; i++) { if ((n - (i * d)) % e < min) min = (n - (i * d)) % e; } if ((n % e) % d < min) min = (n % e) % d; cout << min; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7; const long long N = 60, K = 10000 + 5; long long dp[K][N]; long long prob[N][N]; long long n, k; long long inv[N]; long long power(long long a, long long k) { if (k == 0) return 1; long long ans = power(a, k / 2); ans = (ans * ans) % M; if (k % 2) ans = (ans * a) % M; return ans; } void pre() { for (long long i = 1; i < N; i++) inv[i] = power(i, M - 2); } void calc(long long id, long long s) { memset(dp, 0, sizeof dp); dp[0][s] = 1; for (long long i = 1; i <= k; i++) for (long long cur = 0; cur <= s; cur++) for (long long prev = cur; prev <= s; prev++) dp[i][cur] = (dp[i][cur] + dp[i - 1][prev] * inv[prev + 1]) % M; for (long long i = 0; i <= s; i++) { prob[id][i] = dp[k][i]; } } vector<pair<long long, long long> > vec; bool next(vector<long long> &cur) { for (long long i = 0; i < vec.size(); i++) { if (cur[i] < vec[i].second) { cur[i]++; return true; } cur[i] = 0; } return false; } int main() { pre(); cin >> n >> k; long long id = 0; for (long long i = 2; i * i <= n; i++) { if (n % i) continue; long long cnt = 0; while (n % i == 0) n /= i, ++cnt; vec.push_back({i, cnt}); calc(id, cnt); ++id; } if (n > 1) { vec.push_back({n, 1}); calc(id, 1); ++id; } vector<long long> cur(id, 0); long long ans = 0; do { long long val = 1; for (long long i = 0; i < id; i++) { for (long long j = 0; j < cur[i]; j++) val *= vec[i].first; } val %= M; long long pr = 1; for (long long i = 0; i < id; i++) pr = (pr * prob[i][cur[i]]) % M; ans = (ans + pr * val) % M; } while (next(cur)); ans = (ans + M) % M; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { bool tr = false; int n; cin >> n; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; if (x != y) tr = true; } if (tr) cout << Happy Alex n ; else cout << Poor Alex n ; return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pci_exp_usrapp_pl.v
// Version : 2.4
//--
//--------------------------------------------------------------------------------
module pci_exp_usrapp_pl (
pl_initial_link_width,
pl_lane_reversal_mode,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_link_upcfg_capable,
pl_ltssm_state,
pl_received_hot_rst,
pl_sel_link_rate,
pl_sel_link_width,
pl_directed_link_auton,
pl_directed_link_change,
pl_directed_link_speed,
pl_directed_link_width,
pl_upstream_prefer_deemph,
speed_change_done_n,
trn_lnk_up_n,
trn_clk,
trn_reset_n
);
input [2:0] pl_initial_link_width;
input [1:0] pl_lane_reversal_mode;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input pl_link_upcfg_capable;
input [5:0] pl_ltssm_state;
input pl_received_hot_rst;
input pl_sel_link_rate;
input [1:0] pl_sel_link_width;
output pl_directed_link_auton;
output [1:0] pl_directed_link_change;
output pl_directed_link_speed;
output [1:0] pl_directed_link_width;
output pl_upstream_prefer_deemph;
output speed_change_done_n;
input trn_lnk_up_n;
input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1;
reg pl_directed_link_auton;
reg [1:0] pl_directed_link_change;
reg pl_directed_link_speed;
reg [1:0] pl_directed_link_width;
reg pl_upstream_prefer_deemph;
reg speed_change_done_n;
initial begin
pl_directed_link_auton <= 1'b0;
pl_directed_link_change <= 2'b0;
pl_directed_link_speed <= 1'b0;
pl_directed_link_width <= 2'b0;
pl_upstream_prefer_deemph <= 1'b0;
speed_change_done_n <= 1'b1;
if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin
wait (trn_lnk_up_n == 1'b0);
pl_directed_link_speed <= 1'b1;
pl_directed_link_change <= 2'b10;
wait (pl_ltssm_state == 6'h20);
pl_directed_link_speed <= 1'b0;
pl_directed_link_change <= 2'b00;
wait (pl_sel_link_rate == 1'h1);
speed_change_done_n <= 1'b0;
end
end
endmodule // pci_exp_usrapp_pl
|
#include <bits/stdc++.h> using namespace std; void read(vector<long long> &v) { for (int i = 0; i < v.size(); i++) cin >> v[i]; } void print(vector<long long> v) { for (int i = 0; i < v.size(); i++) cout << v[i] << ; } long long n, m, a, b, temp, x, y; string str; set<string> strings; unordered_map<string, vector<int>> mp; bool check(int l, int r) { for (auto s : strings) { if (r - l + 1 < s.size()) continue; auto it = lower_bound(mp[s].begin(), mp[s].end(), l); if (it == mp[s].end()) continue; int val = *it; if (val <= (r - s.size() + 1)) return 0; } return 1; } int start; int solve() { int l = 0; int r = 0; int ans = 0; for (int l = 0; l < str.size(); l++) { while (r < l) r++; if (!check(l, r)) { if (r - l > ans) { ans = r - l; start = l; } continue; } while (r < str.size()) { if (check(l, r)) r++; else break; } if (r - l > ans) { ans = r - l; start = l; } } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> str; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; strings.insert(s); } for (auto s : strings) { string temp; if (s.size() > str.size()) continue; for (int i = 0; i <= str.length() - s.length(); i++) { temp = str.substr(i, s.length()); if (temp == s) mp[s].push_back(i); } } long long ans = solve(); cout << ans << << start; }
|
module t_multiply;
wire Ready;
wire [15:0] PR;
reg [7:0] multiplier, multiplicand;
integer i, j;
reg start, clock, reset, passed;
multiply uut(clock, reset, start, multiplier, multiplicand, PR, Ready);
always #5 clock = ~clock;
initial
begin
passed = 1;
clock = 0;
start = 0;
reset = 0;
#100;
reset = 1;
#20;
reset = 0;
@(negedge clock)
multiplier = 8'd3;
multiplicand = 8'd4;
start = 1;
@(negedge Ready) start = 0;
@(posedge Ready) #5
if (PR != 16'd12) begin
passed = 0;
$display("#1 test failed.");
end else
$display("#1 test passed.");
@(negedge clock)
multiplier = 8'd20;
multiplicand = 8'd20;
start = 1;
@(posedge Ready) start = 0;
#5
if (PR != 16'd400) begin
$display("#2 test failed.");
passed = 0;
end else
$display("#2 test passed.");
@(negedge clock)
multiplier = 8'd20;
multiplicand = 8'd20;
start = 1;
#40 reset = 1;
#10 reset = 0;
@(negedge Ready) start = 0;
@(posedge Ready) #5
if (PR != 16'd400) begin
passed = 0;
$display("#3 test failed.");
end else
$display("#3 test passed.");
#10;
for (i=0; i<=8'hff; i=i+1)
for (j=0; j<=8'hff; j=j+1) begin
@(negedge clock)
multiplier = i;
multiplicand = j;
start = 1;
@(negedge Ready) start = 0;
@(posedge Ready) #5
if (PR != i*j) begin
passed = 0;
$display("Test failed:", i, "*", j);
end
end
if (passed) $display("All tests passed.");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_SYMBOL_V
`define SKY130_FD_SC_MS__O31AI_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_SYMBOL_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_zextend(clock, reset,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 32;
parameter DATAOUT_WIDTH = 64;
input clock, reset;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
assign o_dataout = {{DATAOUT_WIDTH{1'b0}}, i_datain[DATAIN_WIDTH-1:0]};
assign o_datain_stall = i_dataout_stall;
assign o_dataout_valid = i_datain_valid;
endmodule
|
// Interface control
module ifctl(
input clk_sys,
input clo,
input gotst1,
input zgi_j,
input zgi_set,
input ifhold_j,
input ifhold_reset,
input zw,
input ren,
input rok,
output reg ok$,
output zg,
output zwzg,
output talarm
);
parameter ALARM_DLY_TICKS;
parameter ALARM_TICKS;
// Cała obsługa interfejsu potencjalnie też powinna być zrobiona jako automat.
// Być może powinna znaleźć się (po części?) w strobgen - oczekiwanie na interfejs między
// GOT a S1 jest niczym innym jak kolejnym stanem.
wire oken = ren | rok;
assign zwzg = zgi & zw;
assign zg = zgi | ifhold | (zw & oken);
// (zw & oken): trzymamy zg aż nie spadnie ok|en
// ifhold: trzymamy zajęty interfejs przez cały rozkaz z wymogiem atomowych odwołań do pamięci
// * wejście do zgi_set zaczyna zgłoszenie
// * każdy kolejny strob1 kończy zgłoszenie
// * każdy kolejny got zaczyna następne zgłoszenie
// * zgi_j mówi w jakich stanach zgłaszanie się odbywa
reg zgi;
always @ (posedge clk_sys, posedge clo) begin
if (clo) zgi <= 1'b0;
else if (zgi_set) zgi <= 1'b1;
else if (gotst1) case (zgi_j)
1'b0: zgi <= 1'b0;
1'b1: zgi <= ~zgi;
endcase
end
// ten rejestr trzyma zgłoszenie na interfejsie dla rozkazów, które robią
// odczyt+zapis, który powinien być zrobiony w tym samym dostępie do I/F (atomowo)
// (ifhold wypełnia sygnał ZW pomiędzy stanami WR a WW)
// Przypadek specjalny:
// IS dokonuje zapisu do pamięci warunkowo względem wskaźnika zera WZI,
// więc jeśli w W& przy rozkazie IS podczas STROB2 WZI będzie zapalone, to zdejmujemy zajętość (ifhold_reset)
reg ifhold;
wire ifh_reset = ifhold_reset | clo;
always @ (posedge clk_sys, posedge ifh_reset) begin
if (ifh_reset) ifhold <= 1'b0;
else if (ok$) case ({ifhold_j, ifhold})
2'b00: ifhold <= ifhold;
2'b01: ifhold <= 1'b0;
2'b10: ifhold <= 1'b1;
2'b11: ifhold <= ~ifhold;
endcase
end
// ok$ - koniec pracy z interfejsem (niezależnie od finału: ok/en/alarm)
wire ok_clk = ren | talarm | rok;
always @ (posedge clk_sys, negedge zgi) begin
if (!zgi) ok$ <= 0;
else ok$ <= zwzg & ok_clk;
end
// alarm przy braku odpowiedzi z interfejsu
wire alarm = zwzg & ~ok$;
alarm #(
.ALARM_DLY_TICKS(ALARM_DLY_TICKS),
.ALARM_TICKS(ALARM_TICKS)
) ALARM(
.clk_sys(clk_sys),
.engage(alarm),
.talarm(talarm)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/* verilator lint_off STMTDLY */
module emesh_monitor(/*AUTOARG*/
// Inputs
clk, nreset, dut_access, dut_packet, wait_in, coreid
);
parameter PW = 104;
parameter IDW = 12;
parameter INDEX = 0;
parameter NAME = "not_declared";
//clock and reset
input clk;
input nreset;
//monitors transaction on the wire
input dut_access;
input [PW-1:0] dut_packet;
input wait_in;
input [IDW-1:0] coreid;
//core name for trace
reg [31:0] ftrace;
reg [255:0] tracefile;
//Dumps into
initial
begin
//TODO: Figure out these delays
#10
//index should be core ID
$sformat(tracefile,"%0s_%0h%s",NAME,coreid,".trace");
ftrace = $fopen({tracefile}, "w");
end
always @ (posedge clk or negedge nreset)
if(nreset & dut_access & ~wait_in)
begin
$fwrite(ftrace, "%h_%h_%h_%h\n",dut_packet[PW-1:72],dut_packet[71:40],dut_packet[39:8],dut_packet[7:0]);
//$display("%h_%h_%h_%h\n",dut_packet[PW-1:72],dut_packet[71:40],dut_packet[39:8],dut_packet[7:0]);
end
endmodule // dut_monitor
|
`include "example1.generated.vh"
`default_nettype none
module Example1 (input wire CLK, input wire nRST,
input wire request$say__ENA,
input wire [31:0]request$say$v,
output wire request$say__RDY,
output wire indication$heard__ENA,
output wire [31:0]indication$heard$v,
input wire indication$heard__RDY);
reg busy;
reg [1:0]busy_delay;
reg [31:0]v_delay;
reg [31:0]v_temp;
wire RULE$delay_rule__ENA;
wire RULE$delay_rule__RDY;
assign indication$heard$v = v_delay;
assign indication$heard__ENA = busy_delay == 2'd2;
assign request$say__RDY = !busy;
// Extra assigments, not to output wires
assign RULE$delay_rule__ENA = ( busy && ( busy_delay == 2'd0 ) ) != 0;
assign RULE$delay_rule__RDY = ( busy && ( busy_delay == 2'd0 ) ) != 0;
always @( posedge CLK) begin
if (!nRST) begin
busy <= 0;
busy_delay <= 0;
v_delay <= 0;
v_temp <= 0;
end // nRST
else begin
if (busy_delay == 2'd1) begin // RULE$delay2_rule__ENA
busy_delay <= 2;
if (v_delay == 1)
busy <= 0;
end; // End of RULE$delay2_rule__ENA
if (RULE$delay_rule__ENA & RULE$delay_rule__RDY) begin // RULE$delay_rule__ENA
busy_delay <= 1;
v_delay <= v_temp;
end; // End of RULE$delay_rule__ENA
if (( busy_delay == 2'd2 ) & indication$heard__RDY) begin // RULE$respond_rule__ENA
busy_delay <= 0;
if (v_delay != 1)
busy <= 0;
end; // End of RULE$respond_rule__ENA
if (!( busy | ( !request$say__ENA ) )) begin // request$say__ENA
v_temp <= request$say$v;
busy <= 1;
end; // End of request$say__ENA
end
end // always @ (posedge CLK)
endmodule
`default_nettype wire // set back to default value
|
#include <bits/stdc++.h> using namespace std; const int N = 105; char s[N], t[N]; int dis(char a, char b) { int t = abs(a - b); return min(t, 26 - t); } int main() { int n; scanf( %d , &n); scanf( %s , s + 1); t[1] = A , t[2] = C , t[3] = T , t[4] = G ; int ans = 1e9; for (int i = 1; i + 3 <= n; i++) { int sum = 0; for (int j = 1; j <= 4; j++) sum += dis(t[j], s[i + j - 1]); ans = min(ans, sum); } cout << ans; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_BEHAVIORAL_PP_V
|
module AUDIO_DAC_FIFO ( // FIFO Side
iDATA,iWR,iWR_CLK,
oDATA,
// Audio Side
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_XCK,
// Control Signals
iCLK_18_4,
iRST_N );
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
// FIFO Side
input [DATA_WIDTH-1:0] iDATA;
input iWR;
input iWR_CLK;
output [DATA_WIDTH-1:0] oDATA;
wire [DATA_WIDTH-1:0] mDATA;
reg mDATA_RD;
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output oAUD_BCK;
output oAUD_XCK;
reg oAUD_BCK;
// Control Signals
input iCLK_18_4;
input iRST_N;
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [3:0] SEL_Cont;
////////////////////////////////////
reg [DATA_WIDTH-1:0] DATA_Out;
reg [DATA_WIDTH-1:0] DATA_Out_Tmp;
reg LRCK_1X;
reg LRCK_2X;
FIFO_16_256 u0 ( .data(iDATA),.wrreq(iWR),
.rdreq(mDATA_RD),.rdclk(iCLK_18_4),
.wrclk(iWR_CLK),.aclr(~iRST_N),
.q(mDATA),.wrfull(oDATA[0]));
assign oAUD_XCK = ~iCLK_18_4;
//////////// AUD_BCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
end
else
begin
// LRCK 1X
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
// LRCK 2X
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// Read Signal Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
mDATA_RD <= 0;
end
else
begin
if(LRCK_1X_DIV == REF_CLK/(SAMPLE_RATE*2)-1 )
mDATA_RD <= 1;
else
mDATA_RD <= 0;
end
end
//////////////////////////////////////////////////
////////////// DATA Latch //////////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
DATA_Out_Tmp <= 0;
else
begin
if(LRCK_2X_DIV == REF_CLK/(SAMPLE_RATE*4)-1 )
DATA_Out_Tmp <= mDATA;
end
end
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
DATA_Out <= 0;
else
begin
if(LRCK_2X_DIV == REF_CLK/(SAMPLE_RATE*4)-3 )
DATA_Out <= DATA_Out_Tmp;
end
end
//////////////////////////////////////////////////
////////// 16 Bits PISO MSB First //////////////
always@(negedge oAUD_BCK or negedge iRST_N)
begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = DATA_Out[~SEL_Cont];
//////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 3e6; long long n, m; long long a[N]; long long read(void) { long long s = 0, w = 0; char c = getchar(); while (c < 0 || c > 9 ) w |= c == - , c = getchar(); while (c >= 0 && c <= 9 ) s = s * 10 + c - 48, c = getchar(); return w ? -s : s; } long long point(long long x) { if (x % 2 == 1) return x * (x - 1) / 2 + 1; if (x % 2 == 0) return x * (x - 1) / 2 + x / 2; } signed main(void) { n = read(), m = read(); for (long long i = 1; i <= m; ++i) { long long q = read(); a[i] = read(); } sort(a + 1, a + m + 1); reverse(a + 1, a + m + 1); long long sum = 0; for (long long i = 1; i <= m; ++i) { if (point(i) > n) return cout << sum, 0; sum += a[i]; } cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long n, m, a, b, x, y; int main() { cin >> n >> m >> x >> y >> a >> b; long long k = gcd(a, b); long long kk = min(n / (a / k), m / (b / k)); a = a * kk / k, b = b * kk / k; long long x1, x2, y1, y2; x1 = x - (a + 1) / 2, x2 = x1 + a; y1 = y - (b + 1) / 2, y2 = y1 + b; if (x1 < 0) x1 = 0; x2 = x1 + a; x2 = min(n, x2), x1 = x2 - a; if (y1 < 0) y1 = 0; y2 = y1 + b; y2 = min(m, y2), y1 = y2 - b; cout << x1 << << y1 << << x2 << << y2 << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A222O_FUNCTIONAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int a[200]; int main() { int t; cin >> t; while (t--) { int m, n; cin >> m >> n; for (int i = 1; i <= m; i++) { cin >> a[i]; } map<int, int> mp; for (int i = 1; i <= n; i++) { int x; cin >> x; mp[x] = 1; } for (int i = 1; i < m; i++) { for (int j = m - i; j <= m; j++) { if (j + 1 <= m && a[j] > a[j + 1]) { if (mp[j]) { swap(a[j], a[j + 1]); } } } } int flag = 1; for (int i = 1; i < m; i++) { if (a[i] > a[i + 1]) { flag = 0; } } if (flag) cout << YES << endl; else cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; int arr[60]; signed main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; ++i) cin >> arr[i]; sort(arr, arr + n); bool aliceWins = (arr[0] < arr[n >> 1]); cout << (aliceWins ? Alice n : Bob n ); }
|
typedef logic [3:0][1:0] sometype_t;
module top
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
/*AUTOINPUT("^x.*\|v.*")*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [X-1:0] xb, // To XX of xx.v, ...
// End of automatics
/*AUTOOUTPUT("^c.*\|k.*")*/
/*AUTOOUTPUT("^y.*")*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [X-1:0] cb, // To XX of xx.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foobar, // From XX of xx.v
output [4:0] [2:0] foobar2 // From YY of yy.v
// End of automatics
);
xx (/*AUTOINSTPARAM*/
// Parameters
.X (X),
.Y (Y))
XX(/*AUTOINST*/
// Outputs
.st (st[1:0]),
.foobar (foobar),
// Inputs
.clk (clk),
.rstb (rstb),
.xc (xc/*[X-1:0][1:0]*/),
.xa (xa[X-1:0]),
.xb (xb[X-1:0]),
.cb (cb[X-1:0]),
.yb (yb[X*Y-1:0]));
yy (/*AUTOINSTPARAM*/
// Parameters
.X (X),
.Y (Y))
YY(/*AUTOINST*/
// Outputs
.xc (xc/*[X-1:0][1:0]*/),
.xa (xa[X-1:0]),
.yb (yb[X*Y-1:0]),
.foobar2 (foobar2/*[4:0][2:0]*/),
// Inputs
.clk (clk),
.rstb (rstb),
.xb (xb[X-1:0]),
.cb (cb[X-1:0]),
.st (st[1:0]));
endmodule // top
module xx
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
input [X-1:0][1:0] xc,
input [X-1:0] xa,
input [X-1:0] xb,
input [X-1:0] cb,
output sometype_t [1:0] st,
input [X*Y-1:0] yb,
output foobar
);
endmodule // xx
module yy
#(parameter X=4,
parameter Y=1)
(input clk,
input rstb,
output [X-1:0][1:0] xc,
output [X-1:0] xa,
input [X-1:0] xb,
input [X-1:0] cb,
input sometype_t [1:0] st,
output [X*Y-1:0] yb,
output [4:0][2:0] foobar2
);
endmodule // xx
// Local Variables:
// verilog-typedef-regexp:"_t$"
// verilog-library-directories:("." )
// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
// End:
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Demux packets from a fifo based on the contents of the first line
// If first line matches the parameter and mask, send to data1, otherwise send to data0
module fifo36_demux
#(parameter match_data = 0,
parameter match_mask = 0)
(input clk, input reset, input clear,
input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
output [35:0] data0_o, output src0_rdy_o, input dst0_rdy_i,
output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
localparam DMX_IDLE = 0;
localparam DMX_DATA0 = 1;
localparam DMX_DATA1 = 2;
reg [1:0] state;
wire match = |( (data_i ^ match_data) & match_mask );
wire eof = data_i[33];
always @(posedge clk)
if(reset | clear)
state <= DMX_IDLE;
else
case(state)
DMX_IDLE :
if(src_rdy_i)
if(match)
state <= DMX_DATA1;
else
state <= DMX_DATA0;
DMX_DATA0 :
if(src_rdy_i & dst0_rdy_i & eof)
state <= DMX_IDLE;
DMX_DATA1 :
if(src_rdy_i & dst1_rdy_i & eof)
state <= DMX_IDLE;
default :
state <= DMX_IDLE;
endcase // case (state)
assign dst_rdy_o = (state==DMX_IDLE) ? 0 : (state==DMX_DATA0) ? dst0_rdy_i : dst1_rdy_i;
assign src0_rdy_o = (state==DMX_DATA0) ? src_rdy_i : 0;
assign src1_rdy_o = (state==DMX_DATA1) ? src_rdy_i : 0;
assign data0_o = data_i;
assign data1_o = data_i;
endmodule // fifo36_demux
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description: For those situations where you need to attach one PPFIFO with another
*
* Changes:
*/
module adapter_ppfifo_2_ppfifo#(
parameter DATA_WIDTH = 32
)(
input clk,
input rst,
input i_read_ready,
output reg o_read_activate,
input [23:0] i_read_size,
input [DATA_WIDTH - 1:0] i_read_data,
output reg o_read_stb,
input [1:0] i_write_ready,
output reg [1:0] o_write_activate,
input [23:0] i_write_size,
output reg o_write_stb,
output [DATA_WIDTH - 1:0] o_write_data
);
//registes/wires
reg [23:0] read_count;
reg [23:0] write_count;
assign o_write_data = i_read_data;
always @ (posedge clk) begin
o_read_stb <= 0;
o_write_stb <= 0;
if (rst) begin
o_write_activate <= 0;
o_read_activate <= 0;
write_count <= 0;
read_count <= 0;
end
else begin
if (i_read_ready && !o_read_activate) begin
read_count <= 0;
o_read_activate <= 1;
end
if ((i_write_ready > 0) && (o_write_activate == 0)) begin
write_count <= 0;
if (i_write_ready[0]) begin
o_write_activate[0] <= 1;
end
else begin
o_write_activate[1] <= 1;
end
end
//Both FIFOs are available
if (o_read_activate && (o_write_activate > 0)) begin
if ((write_count < i_write_size) && (read_count < i_read_size))begin
o_write_stb <= 1;
o_read_stb <= 1;
write_count <= write_count + 1;
read_count <= read_count + 1;
end
else begin
if (write_count >= i_write_size) begin
o_write_activate <= 0;
end
if (read_count >= i_read_size) begin
//Both FIFOs should be released, this way the output is never blocked on the input
o_read_activate <= 0;
o_write_activate <= 0;
end
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_TB_V
`define SKY130_FD_SC_MS__A2BB2O_TB_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2o.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__a2bb2o dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; int n, m, B, a[N], c[N], ans[N]; struct Node { int l, r, id; Node() {} Node(int _l, int _r, int _id) { l = _l, r = _r, id = _id; } bool operator<(const Node &p) const { return r < p.r; } } Q[N]; vector<int> V, q[400]; int calc(int l, int r) { int ret = 0; for (int i = (l); i < (r + 1); ++i) { int x = a[i]; ++c[x]; ret += c[x] == V[x]; ret -= c[x] == V[x] + 1; } for (int i = (l); i < (r + 1); ++i) c[a[i]] = 0; return ret; } int main() { scanf( %d%d , &n, &m); B = sqrt(n); for (int i = (0); i < (n); ++i) { scanf( %d , &a[i]); V.push_back(a[i]); } sort(V.begin(), V.end()); V.erase(unique(V.begin(), V.end()), V.end()); for (int i = (0); i < (n); ++i) a[i] = lower_bound(V.begin(), V.end(), a[i]) - V.begin(); for (int i = (0); i < (m); ++i) { int l, r; scanf( %d%d , &l, &r); Q[i] = Node(l - 1, r - 1, i); } sort(Q, Q + m); for (int i = (0); i < (m); ++i) if (Q[i].r - Q[i].l + 1 <= B) { ans[Q[i].id] = calc(Q[i].l, Q[i].r); } else { q[Q[i].l / B + (Q[i].l % B > 0)].push_back(i); } for (int i = (0); i < (B + 1); ++i) { int j = 0, k = 0, cnt = 0; for (j = B * i; j < n && k < ((int)(q[i]).size()); ++j) { ++c[a[j]]; cnt += c[a[j]] == V[a[j]], cnt -= c[a[j]] == V[a[j]] + 1; while (k < ((int)(q[i]).size()) && j == Q[q[i][k]].r) { int tmp = cnt; for (int r = (Q[q[i][k]].l); r < (B * i); ++r) { ++c[a[r]]; tmp += c[a[r]] == V[a[r]], tmp -= c[a[r]] == V[a[r]] + 1; } for (int r = (Q[q[i][k]].l); r < (B * i); ++r) --c[a[r]]; ans[Q[q[i][k++]].id] = tmp; } } for (int r = (B * i); r < (j); ++r) c[a[r]] = 0; } for (int i = (0); i < (m); ++i) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct rec { double x, y; } v, p, w1, w2, m1, m2, p_, m; double eps = 1e-10; inline rec operator+(rec a, rec b) { return (rec){a.x + b.x, a.y + b.y}; } inline rec operator-(rec a, rec b) { return (rec){a.x - b.x, a.y - b.y}; } double mul(rec a, rec b, rec c) { return (b.x - a.x) * (c.y - a.y) - (c.x - a.x) * (b.y - a.y); } double dist(rec a, rec b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } bool line(rec a, rec b, rec c) { return fabs(dist(a, c) + dist(b, c) - dist(a, b)) < eps; } bool cross(rec a, rec b, rec c, rec d, int k) { if (!k && line(a, b, c) && line(a, b, d)) return 0; if (line(a, b, c) || line(a, b, d) || line(c, d, a) || line(c, d, b)) return 1; return mul(a, c, b) * mul(a, b, d) > eps && mul(c, a, d) * mul(c, d, b) > eps; } rec point(rec a, rec b, rec c, rec d) { double t1 = mul(a, c, b), t2 = mul(a, b, d); return (rec){(c.x * t2 + d.x * t1) / (t1 + t2), (c.y * t2 + d.y * t1) / (t1 + t2)}; } rec turn(rec a, double th) { return (rec){a.x * cos(th) - a.y * sin(th), a.x * sin(th) + a.y * cos(th)}; } rec oppo(rec c, rec a, rec b) { rec h = point(a, b, c, c + turn(b - a, acos(-1.0) / 2)); return h + (h - c); } int main() { cin >> v.x >> v.y >> p.x >> p.y >> w1.x >> w1.y >> w2.x >> w2.y >> m1.x >> m1.y >> m2.x >> m2.y; if (!cross(v, p, w1, w2, 1) && !cross(v, p, m1, m2, 0)) { puts( YES ); return 0; } p_ = oppo(p, m1, m2); if (cross(v, p_, m1, m2, 0)) { m = point(v, p_, m1, m2); if (!cross(p, m, w1, w2, 1) && !cross(m, v, w1, w2, 1)) { puts( YES ); return 0; } } puts( NO ); }
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#include <bits/stdc++.h> using namespace std; void Get(int &T) { char C; bool F = 0; for (; C = getchar(), C < 0 || C > 9 ;) if (C == - ) F = 1; for (T = C - 0 ; C = getchar(), C >= 0 && C <= 9 ; T = T * 10 + C - 0 ) ; F && (T = -T); } int N; void Init() { Get(N); } int T[55][55]; void Mul(int A[][55], int B[][55], int N, int K, int M) { for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) { T[i][j] = 0; for (int k = 1; k <= K; k++) (T[i][j] ^= (A[i][k] & B[k][j])); } for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) A[i][j] = T[i][j]; } int A[55][55]; int B[55][55]; int T2[55][55]; void Pow(int X[][55], long long P) { for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) T2[i][j] = (i == j); for (; P; P >>= 1) { if (P & 1) Mul(T2, X, N, N, N); Mul(X, X, N, N, N); } for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) X[i][j] = T2[i][j]; } long long Factor[100005]; int FactorTop; bool I() { for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) if (B[i][j] != (i == j)) return 0; return 1; } bool Check() { for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) B[i][j] = A[i][j]; Pow(B, (1ll << N) - 1); int Ans = I(); if (Ans == 0) return 0; for (int k = 1; k <= FactorTop; k++) { for (int i = 1; i <= N; i++) for (int j = 1; j <= N; j++) B[i][j] = A[i][j]; Pow(B, ((1ll << N) - 1) / Factor[k]); int Ans = I(); if (Ans == 1) return 0; } return 1; } void Debug() { FactorTop = 0; long long X = 1ll << N; X--; Factor[0] = 1; for (long long i = 2; i * i <= X; i++) { for (;; X /= i) { if (X % i != 0) break; Factor[++FactorTop] = i; } } if (X > 1) Factor[++FactorTop] = X; for (int i = 1; i < N; i++) A[i + 1][i] = 1; for (;;) { for (int i = 1; i <= N; i++) A[i][N] = rand() & 1; int Ans = Check(); if (Ans) break; } } void Work() { Debug(); } void Output() { for (int i = N; i >= 1; i--) printf( %d , A[i][N]); puts( ); for (int i = N; i >= 1; i--) printf( %d , 1); puts( ); } int main() { srand(time(0)); Init(); Work(); Output(); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_SYMBOL_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputisolatch (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; long long n, a[100100]; bool vis[100100]; vector<long long> v; int main() { long long n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (a[n - 1] >= a[n - 2] + a[n - 3]) { cout << NO << endl; return 0; } cout << YES << endl; for (int i = n - 1; i >= 0; i -= 2) { vis[i] = true; v.push_back(a[i]); } for (int i = 0; i < n; i++) { if (!vis[i]) v.push_back(a[i]); } for (int i = 0; i < v.size(); i++) cout << v[i] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long bigmod(long long p, long long e, long long M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return ret; } long long extended(long long a, long long b, long long &x, long long &y) { a = abs(a); b = abs(b); long long g, x1, y1; if (!b) { x = 1; y = 0; g = a; return g; } g = extended(b, a % b, x1, y1); x = y1; y = x1 - (a / b) * y1; return g; } long long modinverse(long long a, long long M) { return bigmod(a, M - 2, M); } long long bpow(long long p, long long e) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p); p = (p * p); } return ret; } int toInt(string s) { int sm; stringstream ss(s); ss >> sm; return sm; } int toLlint(string s) { long long int sm; stringstream ss(s); ss >> sm; return sm; } string convertInt(long long number) { if (number == 0) return 0 ; string temp = ; string returnvalue = ; while (number > 0) { temp += number % 10 + 48; number /= 10; } for (int i = 0; i < temp.length(); i++) returnvalue += temp[temp.length() - i - 1]; return returnvalue; } long long ncr[1001][1001]; void NCR() { for (int i = 1; i <= 1000; i++) { ncr[i][i] = 1; ncr[i][0] = 1; for (int r = 1; r < i; r++) { ncr[i][r] = (ncr[i - 1][r] + ncr[i - 1][r - 1]) % 1000000007; } } } vector<int> vec[100009]; long long n; long long dp[100005][2], ar[100009]; void dfs(int V, int pv) { dp[V][0] = 1 - ar[V]; dp[V][1] = ar[V]; for (int i = 0; i < vec[V].size(); i++) { long long old[2]; memset(old, 0, sizeof(old)); int v = vec[V][i]; if (v == pv) continue; old[0] = dp[V][0]; old[1] = dp[V][1]; dp[V][0] = dp[V][1] = 0; dfs(v, V); dp[V][0] += (old[0] * dp[v][1]) % 1000000007; dp[V][1] += (old[1] * dp[v][1]) % 1000000007; dp[V][1] += (old[1] * dp[v][0]) % 1000000007; dp[V][1] += (old[0] * dp[v][1]) % 1000000007; dp[V][0] += (old[0] * dp[v][0]) % 1000000007; } } int main() { cin >> n; for (int i = 1; i < n; i++) { int v; cin >> v; vec[i].push_back(v); vec[v].push_back(i); } for (int i = 0; i < n; i++) { int val; cin >> val; ar[i] = val; } dfs(0, -1); cout << dp[0][1] % 1000000007 << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { long long a, b; scanf( %I64d %I64d , &a, &b); long long t = 0; while (b) { t *= 10; t += b % 10; b /= 10; } printf( %I64d n , a + t); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int n, m, t, k; int d[((int)1e5 + 5)]; int countt[105]; int l = 1; int r = 100; void lbulma() { while (countt[l] == 0) l++; return; } void rbulma() { while (countt[r] == 0) r--; return; } int asal[4] = {2, 3, 5, 7}; int main() { long long int sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> d[i]; sum += d[i]; countt[d[i]]++; } lbulma(); rbulma(); long long minn = INT_MAX; for (int j = 100; j >= l; --j) { if (countt[j]) for (int i = 10; i >= 2; --i) { if (j % i == 0 && (j / i) + (l * i) < j + l) { long long int tmp = sum - ((j + l) - ((j / i) + (l * i))); minn = min(minn, tmp); } } } cout << min(minn, sum) << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_4_V
`define SKY130_FD_SC_HD__MAJ3_4_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__maj3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__maj3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 16; int n, m; int d[2][N]; int get_n(int x, int n) { int tmp = 3 << (n * 2); tmp = x & tmp; tmp >>= n * 2; return tmp; } int set_n(int x, int n, int y) { int tmp = 3 << (n * 2); x = x & (~tmp); y <<= (n * 2); x |= y; return x; } void update(int &x, int y) { if (x == -1 || x < y) x = y; } int solve() { int i, j, k; int t = 0; memset(d, -1, sizeof(d)); d[0][0] = 0; int tot = 1 << (n * 2 + 2); for (i = 0; i < m; ++i) { for (j = 0; j < n; ++j) { memset(d[1 - t], -1, sizeof(d[1 - t])); for (k = 0; k < tot; ++k) { if (d[t][k] == -1) continue; int t0 = get_n(k, j); int t1 = get_n(k, j + 1); int st = set_n(k, j, 1); st = set_n(st, j + 1, 1); update(d[1 - t][st], d[t][k]); if (t0 > 0) { st = set_n(k, j - 1, 2); st = set_n(st, j, 0); st = set_n(st, j + 1, 0); update(d[1 - t][st], d[t][k] + 1); if (t0 == 1) { st = set_n(k, j - 1, 0); st = set_n(st, j, 2); st = set_n(st, j + 1, 2); update(d[1 - t][st], d[t][k] + 1); } } if (t1 > 0) { st = set_n(k, j, 0); st = set_n(st, j + 1, 0); update(d[1 - t][st], d[t][k] + 1); if (t1 == 1) { st = set_n(k, j, 2); st = set_n(st, j + 1, 2); update(d[1 - t][st], d[t][k] + 1); } } if (t0 == 1 && t1 == 1) { st = set_n(k, j - 1, 0); st = set_n(st, j, 2); st = set_n(st, j + 1, 2); update(d[1 - t][st], d[t][k] + 2); } } t = 1 - t; } memset(d[1 - t], -1, sizeof(d[1 - t])); for (k = 0; k < tot; ++k) { int st = set_n(k, n, 0); st <<= 2; update(d[1 - t][st], d[t][k]); } t = 1 - t; } int ans = -1; for (k = 0; k < tot; ++k) { update(ans, d[t][k]); } return ans; } int main() { int i, j, k, t, nc = 0; while (scanf( %d%d , &n, &m) != EOF) { if (n > m) swap(n, m); int ans = solve(); printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_BLACKBOX_V
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#include <bits/stdc++.h> int main() { std::map<long, long> map; long q, id, leftMAX = 0, rightMAX = 0, firstTime = 0; char c; std::cin >> q; while (q--) { std::cin >> c >> id; if (!firstTime--) { map.insert(std::pair<long, long>(id, 0)); } else { if (c == ? ) std::cout << std::min(map[id] - leftMAX, rightMAX - map[id]) << std::endl; else if (c == R ) map.insert(std::pair<long, long>(id, ++rightMAX)); else map.insert(std::pair<long, long>(id, --leftMAX)); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_TB_V
`define SKY130_FD_SC_LP__SRSDFSTP_TB_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 SLEEP_B = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 D = 1'b1;
#240 KAPWR = 1'b1;
#260 SCD = 1'b1;
#280 SCE = 1'b1;
#300 SET_B = 1'b1;
#320 SLEEP_B = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 D = 1'b0;
#440 KAPWR = 1'b0;
#460 SCD = 1'b0;
#480 SCE = 1'b0;
#500 SET_B = 1'b0;
#520 SLEEP_B = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 SLEEP_B = 1'b1;
#720 SET_B = 1'b1;
#740 SCE = 1'b1;
#760 SCD = 1'b1;
#780 KAPWR = 1'b1;
#800 D = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 SLEEP_B = 1'bx;
#920 SET_B = 1'bx;
#940 SCE = 1'bx;
#960 SCD = 1'bx;
#980 KAPWR = 1'bx;
#1000 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__srsdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j; int n; cin >> n; long long int a[n + 1]; map<long long, long long> m; for (i = 1; i <= n; i++) { cin >> a[i]; m[a[i]]++; } long long ans = 0; multiset<long long> s; for (auto it = m.begin(); it != m.end(); it++) { s.insert(it->second); ans = max(ans, it->second); } vector<long long int> v1; long long ans2 = 0, ans1 = 0; for (i = 1; i <= ans; i++) { v1.clear(); long long p = i; ans1 = 0; while (1) { auto it = s.lower_bound(p); if (it == s.end()) break; v1.push_back(*it); s.erase(s.find(*it)); ans1 += p; p = p * 2; } ans2 = max(ans2, ans1); for (j = v1.size() - 1; j >= 0; j--) { s.insert(v1[j]); } } cout << ans2 << endl; }
|
`define ADDER_WIDTH 020
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
/*******************************************************************************
* Module: fifo_same_clock
* Date:2014-05-20
* Author: Andrey Filippov
* Description: Configurable synchronous FIFO using the same clock for read and write
*
* Copyright (c) 2014 Elphel, Inc.
* fifo_same_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fifo_same_clock.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
//`define DEBUG_FIFO 1
module fifo_same_clock
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4
)
(
input rst, // reset, active high
input clk, // clock - positive edge
input sync_rst, // synchronously reset fifo;
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output [DATA_WIDTH-1:0] data_out, // output data
output nempty, // FIFO has some data
output reg half_full // FIFO half full
`ifdef DEBUG_FIFO
,output reg under, // debug outputs - under - attempt to read from empty
output reg over, // overwritten
output reg [DATA_DEPTH-1:0] wcount,
output reg [DATA_DEPTH-1:0] rcount,
output [DATA_DEPTH-1:0] num_in_fifo
`endif
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why?
reg [DATA_DEPTH-1:0] fill=0; // RAM fill
reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa;
// wire [DATA_DEPTH-1:0] next_fill;
reg wem;
wire rem;
reg out_full=0; //output register full
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg ram_nempty;
// assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
`ifdef DEBUG_FIFO
assign num_in_fifo=fill[DATA_DEPTH-1:0];
`endif
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
// else fill <= next_fill;
else if ( wem && ~rem) fill <= fill + 1;
else if (~wem && rem) fill <= fill - 1;
if (rst) wem <= 0;
else if (sync_rst) wem <= 0;
else wem <= we;
if (rst) ram_nempty <= 0;
else if (sync_rst) ram_nempty <= 0;
// else ram_nempty <= (next_fill != 0);
// else ram_nempty <= wem || (|fill[DATA_DEPTH-1:1]) || (fill[0] && !rem);
else ram_nempty <= (|fill[DATA_DEPTH-1:1]) || (fill[0] && wem) || ((fill[0] || wem) && !rem) ;
if (rst) wa <= 0;
else if (sync_rst) wa <= 0;
else if (wem) wa <= wa+1;
if (rst) ra <= 0;
else if (sync_rst) ra <= 0;
else if (rem) ra <= ra+1;
else if (!ram_nempty) ra <= wa; // Just recover from bit errors
if (rst) out_full <= 0;
else if (sync_rst) out_full <= 0;
else if (rem && ~re) out_full <= 1;
else if (re && ~rem) out_full <= 0;
`ifdef DEBUG_FIFO
if (rst) wcount <= 0;
else if (sync_rst) wcount <= 0;
else if (we) wcount <= wcount + 1;
if (rst) rcount <= 0;
else if (sync_rst) rcount <= 0;
else if (re) rcount <= rcount + 1;
`endif
end
// no reset elements
always @ (posedge clk) begin
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
if (wem) ram[wa] <= inreg;
if (we) inreg <= data_in;
if (rem) outreg <= ram[ra];
`ifdef DEBUG_FIFO
under <= ~we & re & ~nempty; // underrun error
over <= we & ~re & (fill == (1<< (DATA_DEPTH-1))); // overrun error
`endif
end
endmodule
|
module spi_rx(
clk,
reset_n,
sdi,
sck,
ss_n,
adrs,
data,
rx_valid);
input wire clk, reset_n, sdi, sck, ss_n;
output wire rx_valid;
output wire [7:0] adrs, data;
reg [15:0] shift_reg, rx_buf1, rx_buf2;
reg [3:0] rx_cnt;
reg [2:0] valid_sync;
wire rx_done;
assign rx_done = &rx_cnt;
assign adrs = rx_buf2[15:8];
assign data = rx_buf2[7:0];
assign rx_valid = valid_sync[2];
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
valid_sync <= 0;
rx_buf2 <= 0;
end
else
begin
valid_sync <= {valid_sync[1:0], rx_done};
if(valid_sync[1]) rx_buf2 <= rx_buf1;
else rx_buf2 <= rx_buf2;
end
end
always @(negedge sck, negedge reset_n)
begin
if(!reset_n)
begin
shift_reg <= 0;
rx_buf1 <= 0;
rx_cnt <= 0;
end
else if(!ss_n)
begin
shift_reg <= {shift_reg[13:0], sdi};
rx_cnt <= rx_cnt + 1;
if(rx_done) rx_buf1 <= {shift_reg, sdi};
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:05:38 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k160tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [31:0]probe2;
input [31:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [0:0]probe7;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void pr(vector<T> &v) { for (int i = 0; i < (int)(v).size(); i++) cout << v[i] << ; cout << n ; ; } template <typename T> void pr(vector<vector<T>> &v) { for (int i = 0; i < (int)(v).size(); i++) { pr(v[i]); } } template <typename T> void re(T &x) { cin >> x; } template <typename T> void re(vector<T> &a) { for (int i = 0; i < (int)(a).size(); i++) re(a[i]); } template <class Arg, class... Args> void re(Arg &first, Args &...rest) { re(first); re(rest...); } template <typename T> void pr(T x) { cout << x << n ; ; } template <class Arg, class... Args> void pr(const Arg &first, const Args &...rest) { cout << first << ; pr(rest...); cout << n ; ; } void ps() { cout << n ; ; } template <class T, class... Ts> void ps(const T &t, const Ts &...ts) { cout << t; if (sizeof...(ts)) cout << ; ps(ts...); } const long long MOD = 1000000007; long double PI = 4 * atan(1); long double eps = 1e-12; int LPS[200005] = {}; vector<pair<long long, char>> t; vector<pair<long long, char>> s; vector<pair<long long, char>> tcp; vector<pair<long long, char>> scp; void computeLPS() { int M = scp.size(); int i = 1; int j = 0; LPS[0] = 0; while (i < M) { if (scp[j] == scp[i]) { j++; LPS[i] = j; i++; } else { if (j == 0) { LPS[i] = 0; i++; } else { j = LPS[j - 1]; } } } } vector<int> KMP() { int M = (int)scp.size(); int N = (int)tcp.size(); computeLPS(); int i = 0; int j = 0; vector<int> matches; while (i < N) { if (scp[j] == tcp[i]) { i++; j++; } if (j == M) { matches.push_back(i - j); j = LPS[j - 1]; } else if (i < N && scp[j] != tcp[i]) { if (j != 0) { j = LPS[j - 1]; } else { i++; } } } return matches; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { long long k; cin >> k; char dash; cin >> dash; char c; cin >> c; if (t.size() == 0 || c != t.back().second) { t.push_back(make_pair(k, c)); } else { t.back().first += k; } } for (int i = 0; i < m; i++) { long long k; cin >> k; char dash; cin >> dash; char c; cin >> c; if (s.size() == 0 || c != s.back().second) { s.push_back(make_pair(k, c)); } else { s.back().first += k; } } long long ans = 0; if (s.size() == 1) { for (int i = 0; i < t.size(); i++) { if (t[i].second == s[0].second) { ans += max(0ll, t[i].first - s[0].first + 1ll); } } cout << ans << n ; ; return 0; } else if (s.size() == 2) { for (int i = 0; i < t.size() - 1; i++) { if (t[i].second == s[0].second && t[i + 1].second == s[1].second && t[i].first >= s[0].first && t[i + 1].first >= s[1].first) { ans += 1; } } cout << ans << n ; ; return 0; } for (int i = 1; i < t.size() - 1; i++) tcp.push_back(t[i]); for (int i = 1; i < s.size() - 1; i++) scp.push_back(s[i]); vector<int> matches = KMP(); for (int ind : matches) { if (t[ind].first >= s[0].first && t[ind].second == s[0].second && t[ind + s.size() - 1].first >= s.back().first && t[ind + s.size() - 1].second == s.back().second) { ans++; } } cout << ans << n ; ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; const long long MOD = 1e9 + 7; long long f[N << 2], lazy[N << 2], a[N], b[N], c[N]; void up(int x, int l, int r, long long y) { f[x] = (f[x] + y * (r - l + 1)) % MOD; lazy[x] = (lazy[x] + y) % MOD; } void push_down(int x, int l, int r) { int mid = (l + r) / 2; up(x << 1, l, mid, lazy[x]); up(x << 1 | 1, mid + 1, r, lazy[x]); lazy[x] = 0; } void update(int x, int l, int r, int left, int right, long long y) { if (left > r || right < l) return; if (left <= l && right >= r) { up(x, l, r, y); return; } push_down(x, l, r); int mid = (l + r) / 2; update(x << 1, l, mid, left, right, y); update(x << 1 | 1, mid + 1, r, left, right, y); f[x] = (f[x << 1] + f[x << 1 | 1]) % MOD; } long long query(int x, int l, int r, int left, int right) { if (left > r || right < l) return 0; if (left <= l && right >= r) return f[x]; push_down(x, l, r); int mid = (l + r) / 2; return (query(x << 1, l, mid, left, right) + query(x << 1 | 1, mid + 1, r, left, right)) % MOD; } int sz[N], son[N], l[N], r[N], n; vector<int> p[N]; long long res, ans; void getsize(int x, int fa) { sz[x] = 1; son[x] = -1; for (int v : p[x]) if (v != fa) { getsize(v, x); sz[x] += sz[v]; if (son[x] == -1 || sz[v] > sz[son[x]]) son[x] = v; } } void calc(int x, long long y, int op) { if (op) { long long tmp = a[r[x]] - a[l[x] - 1] - query(1, 1, 100000, l[x], r[x]) * 2 - y * (r[x] - l[x] + 1); tmp = (tmp % MOD + MOD) % MOD; res = (res + tmp * y) % MOD; } update(1, 1, 100000, l[x], r[x], y); } void clear(int x, int fa) { calc(x, -c[x] + MOD, 0); for (int v : p[x]) if (v != fa) clear(v, x); } void add(int x, int fa) { calc(x, c[x], 1); for (int v : p[x]) if (v != fa) add(v, x); } void gao(int x, int fa) { for (int v : p[x]) if (v != fa && v != son[x]) { gao(v, x); clear(v, x); res = 0; } if (son[x] != -1) gao(son[x], x); for (int v : p[x]) if (v != fa && v != son[x]) { add(v, x); } calc(x, c[x], 1); ans = (ans + res) % MOD; } long long qpow(long long x, long long y) { long long z = 1; while (y > 0) { if (y & 1) z = z * x % MOD; x = x * x % MOD; y /= 2; } return z; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &l[i], &r[i]); long long t = qpow(r[i] - l[i] + 1, MOD - 2); c[i] = t; a[l[i]] = (a[l[i]] + t) % MOD; a[r[i] + 1] = (a[r[i] + 1] - t + MOD) % MOD; } for (int i = 1; i < N; i++) b[i] = (b[i - 1] + a[i]) % MOD; memset(a, 0, sizeof(a)); for (int i = 1; i < N; i++) a[i] = (a[i - 1] + b[i]) % MOD; for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); p[u].push_back(v); p[v].push_back(u); } getsize(1, 0); gao(1, 0); for (int i = 1; i <= n; i++) { ans = ans * (r[i] - l[i] + 1) % MOD; } printf( %lld , ans); return 0; }
|
module instruction_arbiter
(/*AUTOARG*/
// Outputs
simd0_alu_select, simd1_alu_select, simd2_alu_select,
simd3_alu_select, simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select, lsu_lsu_select,
salu_alu_select, lsu_wfid, alu_wfid, issued_wfid, alu_valid,
lsu_valid, issued_valid,
// Inputs
clk, rst, salu_ready_to_issue, simd_ready_to_issue,
simf_ready_to_issue, lsu_ready_to_issue, simd0_alu_ready,
simd1_alu_ready, simd2_alu_ready, simd3_alu_ready, simf0_alu_ready,
simf1_alu_ready, simf2_alu_ready, simf3_alu_ready, salu_alu_ready,
lsu_ready
);
input clk, rst;
input [`WF_PER_CU-1:0] salu_ready_to_issue, simd_ready_to_issue,
simf_ready_to_issue, lsu_ready_to_issue;
input simd0_alu_ready, simd1_alu_ready,
simd2_alu_ready, simd3_alu_ready,
simf0_alu_ready, simf1_alu_ready,
simf2_alu_ready, simf3_alu_ready,
salu_alu_ready, lsu_ready;
output simd0_alu_select, simd1_alu_select,
simd2_alu_select, simd3_alu_select,
simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select,
lsu_lsu_select, salu_alu_select;
output [`WF_ID_LENGTH-1:0] lsu_wfid, alu_wfid, issued_wfid;
output alu_valid, lsu_valid, issued_valid;
wire [`WF_PER_CU-1:0] c_issued_arry, issued_arry, inegible_wf_arry;
wire [`WF_PER_CU-1:0] f_salu_ready_to_issue, f_simd_ready_to_issue,
f_simf_ready_to_issue, f_lsu_ready_to_issue;
wire f_simd0_alu_ready, f_simd1_alu_ready,
f_simd2_alu_ready, f_simd3_alu_ready,
f_simf0_alu_ready, f_simf1_alu_ready,
f_simf2_alu_ready, f_simf3_alu_ready,
f_salu_alu_ready, f_lsu_ready;
wire c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select;
wire c_issued_valid;
wire [`WF_ID_LENGTH-1:0] c_issued_wfid;
decoder_6b_40b_en c_issued_decoder
(.addr_in(c_issued_wfid),
.en(c_issued_valid),
.out(c_issued_arry)
);
decoder_6b_40b_en issued_decoder
(.addr_in(issued_wfid),
.en(issued_valid),
.out(issued_arry)
);
// Hack: make sure the wf that are being chosen right now and the one
// that was chosen last cycle are not issued.
assign inegible_wf_arry = c_issued_arry | issued_arry;
dff input_flops[(40*4 + 10)-1:0]
(.d({salu_ready_to_issue & ~inegible_wf_arry, simd_ready_to_issue & ~inegible_wf_arry,
simf_ready_to_issue & ~inegible_wf_arry, lsu_ready_to_issue & ~inegible_wf_arry,
simd0_alu_ready & ~simd0_alu_select & ~c_simd0_alu_select,
simd1_alu_ready & ~simd1_alu_select & ~c_simd1_alu_select ,
simd2_alu_ready & ~simd2_alu_select & ~c_simd2_alu_select,
simd3_alu_ready & ~simd3_alu_select & ~c_simd3_alu_select,
simf0_alu_ready & ~simf0_alu_select & ~c_simf0_alu_select,
simf1_alu_ready & ~simf1_alu_select & ~c_simf1_alu_select,
simf2_alu_ready & ~simf2_alu_select & ~c_simf2_alu_select,
simf3_alu_ready & ~simf3_alu_select & ~c_simf3_alu_select,
salu_alu_ready & ~salu_alu_select & ~c_salu_alu_select,
lsu_ready & ~lsu_lsu_select & ~c_lsu_lsu_select}),
.q({f_salu_ready_to_issue, f_simd_ready_to_issue,
f_simf_ready_to_issue, f_lsu_ready_to_issue,
f_simd0_alu_ready, f_simd1_alu_ready,
f_simd2_alu_ready, f_simd3_alu_ready,
f_simf0_alu_ready, f_simf1_alu_ready,
f_simf2_alu_ready, f_simf3_alu_ready,
f_salu_alu_ready, f_lsu_ready}),
.clk(clk),
.rst(rst));
dff output_flops[(6*1 + 11)-1:0]
(.d({c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select,
c_issued_wfid,
c_issued_valid}),
.q({simd0_alu_select, simd1_alu_select,
simd2_alu_select, simd3_alu_select,
simf0_alu_select, simf1_alu_select,
simf2_alu_select, simf3_alu_select,
lsu_lsu_select, salu_alu_select,
issued_wfid,
issued_valid}),
.clk(clk),
.rst(rst));
wire lsu_wf_valid, salu_wf_valid, simd_wf_valid, simf_wf_valid;
wire [`WF_ID_LENGTH-1:0] lsu_wf_chosen, salu_wf_choosen, simd_wf_choosen, simf_wf_choosen;
arbiter lsu_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_lsu_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(lsu_wf_valid),
.choosen_wf_id(lsu_wf_chosen)
);
arbiter salu_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_salu_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(salu_wf_valid),
.choosen_wf_id(salu_wf_choosen)
);
arbiter simd_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_simd_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(simd_wf_valid),
.choosen_wf_id(simd_wf_choosen)
);
arbiter simf_arbiter
(
.clk(clk),
.rst(rst),
.input_arry(f_simf_ready_to_issue),
.issued_en(c_issued_valid),
.issued_wf_id(c_issued_wfid),
.choosen_valid(simf_wf_valid),
.choosen_wf_id(simf_wf_choosen)
);
alu_issue_logic alu_issue_logic
(/*AUTOINST*/
// Outputs
.c_issued_valid (c_issued_valid),
.c_simd0_alu_select (c_simd0_alu_select),
.c_simd1_alu_select (c_simd1_alu_select),
.c_simd2_alu_select (c_simd2_alu_select),
.c_simd3_alu_select (c_simd3_alu_select),
.c_simf0_alu_select (c_simf0_alu_select),
.c_simf1_alu_select (c_simf1_alu_select),
.c_simf2_alu_select (c_simf2_alu_select),
.c_simf3_alu_select (c_simf3_alu_select),
.c_lsu_lsu_select (c_lsu_lsu_select),
.c_salu_alu_select (c_salu_alu_select),
.c_issued_wfid (c_issued_wfid[`WF_ID_LENGTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.f_lsu_ready (f_lsu_ready),
.f_salu_alu_ready (f_salu_alu_ready),
.f_simf3_alu_ready (f_simf3_alu_ready),
.f_simf2_alu_ready (f_simf2_alu_ready),
.f_simf1_alu_ready (f_simf1_alu_ready),
.f_simf0_alu_ready (f_simf0_alu_ready),
.f_simd3_alu_ready (f_simd3_alu_ready),
.f_simd2_alu_ready (f_simd2_alu_ready),
.f_simd1_alu_ready (f_simd1_alu_ready),
.f_simd0_alu_ready (f_simd0_alu_ready),
.lsu_wf_valid (lsu_wf_valid),
.simd_wf_valid (simd_wf_valid),
.simf_wf_valid (simf_wf_valid),
.salu_wf_valid (salu_wf_valid),
.lsu_wf_chosen (lsu_wf_chosen[`WF_ID_LENGTH-1:0]),
.simd_wf_choosen (simd_wf_choosen[`WF_ID_LENGTH-1:0]),
.simf_wf_choosen (simf_wf_choosen[`WF_ID_LENGTH-1:0]),
.salu_wf_choosen (salu_wf_choosen[`WF_ID_LENGTH-1:0]));
assign alu_wfid = issued_wfid;
assign lsu_wfid = issued_wfid;
assign alu_valid = simd0_alu_select | simd1_alu_select | simd2_alu_select |
simd3_alu_select | simf0_alu_select | simf1_alu_select |
simf2_alu_select | simf3_alu_select | salu_alu_select;
assign lsu_valid = lsu_lsu_select;
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("f32.reinterpret-i32.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("f32.reinterpret-i32_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 32'hc0000000);
`assert(result_type, `f32);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; vector<int> cnt(n + 1, false), idx(n + 1), ans(m + 1), b(m + 1); for (int i = 1; i <= n; i++) { int x; cin >> x; cnt[x]++; idx[x] = i; } for (int i = 1; i <= m; i++) { cin >> b[i]; if (!cnt[b[i]]) { cout << Impossible << endl; return 0; } } for (int i = 1; i <= m; i++) { if (cnt[b[i]] > 1) { cout << Ambiguity << endl; return 0; } ans[i] = idx[b[i]]; } cout << Possible << endl; for (int i = 1; i <= m; i++) cout << ans[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { char c = getchar(); int x = 0; bool f = 0; for (; !isdigit(c); c = getchar()) f ^= !(c ^ 45); for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); if (f) x = -x; return x; } int n, m, k, s; vector<int> e[200005]; vector<int> dfn, res[200005]; bool vis[200005]; void dfs(int u) { vis[u] = 1; dfn.push_back(u); for (auto v : e[u]) if (!vis[v]) dfs(v), dfn.push_back(u); } signed main() { n = read(), m = read(), k = read(), s = ceil(2.0 * n / k); for (register int i = (1); i <= (m); ++i) { int u = read(), v = read(); e[u].push_back(v), e[v].push_back(u); } dfs(1); for (register int i = (0); i <= ((int)dfn.size() - 1); ++i) res[i / s + 1].push_back(dfn[i]); for (register int i = (1); i <= (k); ++i) { if (!res[i].size()) res[i].push_back(1); cout << res[i].size() << ; for (auto x : res[i]) cout << x << ; puts( ); } return 0; }
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_pio_0 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int n, k; int A[25], B[2]; int fact[25]; int mod(long long int a) { return (a % MOD + MOD) % MOD; } int poww(int pw) { if (pw == 0) return 1; return 3 * poww(pw - 1); } int result = 0; int precompute(int U1) { int ret = 0; int el = (n + 1) / 2, fl = n - el; int EL = (1 << el), FL = (1 << fl); map<pair<int, int>, int> store; int cnt, sum; for (int i = 0; i < FL; i++) { sum = cnt = 0; for (int bit = 0; bit < fl; bit++) { if (i & (1 << bit)) sum += A[el + bit], cnt++; if (sum > MOD) sum = MOD; } if (sum != MOD) store[pair<int, int>(sum, cnt)]++; } for (int i = 0; i < EL; i++) { sum = cnt = 0; for (int bit = 0; bit < el; bit++) { if (i & (1 << bit)) sum += A[bit], cnt++; if (sum > MOD) sum = MOD; } if (sum > U1) continue; for (int x = 0; x < fl + 1; x++) { pair<int, int> t = pair<int, int>(U1 - sum, x); if (store.count(t)) { int ff = mod((long long int)store[t] * fact[x + cnt]); ff = mod((long long int)ff * fact[n - x - cnt]); ret = mod(ret + ff); } } } result = mod(result - ret); return result; } int pc2(int U1, int U2) { int el = (n - 1) / 2, fl = n - el; int EL = poww(el), FL = poww(fl); precompute(U1); precompute(U2); if (U1 > U2) swap(U1, U2); U2 = U2 - U1; map<pair<pair<int, int>, int>, int> store; int sum1, sum2, ret = 0; int c1, c2; for (int i = 0; i < FL; i++) { sum1 = sum2 = c1 = c2 = 0; int t = i; for (int bit = 0; bit < fl; bit++) { if (t % 3 == 1) sum1 += A[el + bit], c1++; if (t % 3 == 2) sum2 += A[el + bit], c2++; t /= 3; if (sum1 > MOD) sum1 = MOD; if (sum2 > MOD) sum2 = MOD; } if (sum1 != MOD && sum2 != MOD) store[pair<pair<int, int>, int>(pair<int, int>(sum1, sum2), (c1 << 8) | c2)]++; } for (int i = 0; i < EL; i++) { sum1 = sum2 = c1 = c2 = 0; int t = i; for (int bit = 0; bit < el; bit++) { if (t % 3 == 1) sum1 += A[bit], c1++; if (t % 3 == 2) sum2 += A[bit], c2++; if (sum1 > MOD) sum1 = MOD; if (sum2 > MOD) sum2 = MOD; t /= 3; } if (sum1 > U1 || sum2 > U2) continue; for (int x = 0; x < fl + 1; x++) { for (int y = 0; y + x <= fl; y++) { if (x + y > fl) continue; pair<pair<int, int>, int> t = pair<pair<int, int>, int>( pair<int, int>(U1 - sum1, U2 - sum2), (x << 8) | y); if (store.count(t)) { int ff = store[t]; ff = mod((long long int)ff * fact[c1 + x]); ff = mod((long long int)ff * fact[c2 + y]); ff = mod((long long int)ff * fact[n - c1 - x - c2 - y]); ret = mod((long long int)ret + ff); } } } } result = mod((long long int)result + ret); return ret; } int main() { B[0] = B[1] = -1; fact[0] = 1; for (int i = 1; i < 25; i++) fact[i] = ((long long int)fact[i - 1] * i) % MOD; cin >> n; for (int i = 0; i < n; i++) { cin >> A[i]; } cin >> k; for (int i = 0; i < k; i++) cin >> B[i]; result = fact[n]; if (k == 1) precompute(B[0]); else if (k == 2) { pc2(B[0], B[1]); } cout << result << endl; return 0; }
|
#include <bits/stdc++.h> int x[2002], y[2002]; using namespace std; int main() { int n; cin >> n; set<int> S; for (int i = 1; i <= n; ++i) { cin >> x[i]; S.insert(x[i]); } for (int i = 1; i <= n; ++i) { cin >> y[i]; S.insert(y[i]); } int val = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if (S.find(x[i] ^ y[j]) != S.end()) val++; } } if (val & 1) cout << Koyomi n ; else cout << Karen n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool cmpDouble(const double& a, const double& b) { return std::fabs(a - b) < std::numeric_limits<double>::epsilon(); } int main() { int n, k; cin >> n >> k; int arr[5001]; int ans[5001]; for (int i = 0; i < n; ++i) { cin >> arr[i]; ans[i] = 0; } map<int, set<int>> seen; for (int i = 0; i < k; ++i) { ans[i] = i + 1; seen[arr[i]].insert(i + 1); } for (int i = k; i < n; ++i) { if (seen[arr[i]].size() >= k) { cout << NO << endl; return 0; } for (int j = 1; j <= k; ++j) { if (seen[arr[i]].find(j) == seen[arr[i]].end()) { ans[i] = j; seen[arr[i]].insert(j); break; } } } cout << YES << endl; for (int i = 0; i < n; ++i) { cout << ans[i] << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int seq[100]; void display(const int n) { for (int i = 0; i < n; ++i) printf( %d , seq[i]); putchar( n ); } int compute_sum(const int n) { int sum = 0; for (int i = 0; i < n; ++i) { int x = seq[i]; for (int j = i; j < n; ++j) { x = min(x, seq[j]); sum += x; } } return sum; } bool solve(const int n, int m) { for (int i = 0; i < n; ++i) seq[i] = i + 1; int best = 0; do { const int sum = compute_sum(n); best = max(best, sum); } while (next_permutation(seq, seq + n)); for (int i = 0; i < n; ++i) seq[i] = i + 1; do { const int sum = compute_sum(n); if (sum == best) { if (--m == 0) { display(n); return true; } } } while (next_permutation(seq, seq + n)); return false; } void s(const long long x, const long long y, const int first) { printf( visiting with x=%lld, y=%lld, first=%d n , x, y, first); if (x <= 0) return; assert(y < x); long long delta = max(1LL, x >> 1); long long index = 0; int movements = 0; for (;;) { printf( index = %lld, delta = %lld, movements = %d n , index, delta, movements); if (index + delta <= y) { movements += 1; index += delta; } else { cout << first + movements << << endl; s(x >> 1, y - index, first + 1); break; } delta = max(1LL, delta >> 1); } } vector<int> v; void compute(const int l, const int r, long long m) { if (l > r) return; if (l == r) { v.push_back(l); return; } const long long x = 1LL << (r - l); long long delta = max(1LL, x >> 1); int movements = 0; for (;;) { const long long new_m = m - delta; if (new_m >= 0) { m = new_m; movements += 1; delta = max(1LL, delta >> 1); } else { const int first_digit = l + movements; v.push_back(first_digit); compute(first_digit + 1, r, m); for (int i = l + movements - 1; i >= l; --i) v.push_back(i); break; } } } void solve_fast(const int n, long long m) {} void test() { for (int n = 1; n <= 5; ++n) { for (int m = 1; m <= 100; ++m) { if (m <= 1LL << (n - 1)) { if (solve(n, m)) { v.clear(); compute(1, n, m - 1); for (int i = 0; i < v.size(); ++i) printf( %d , v[i]); putchar( n ); } } } putchar( n ); } } void run() { int n; long long m; cin >> n >> m; v.clear(); compute(1, n, m - 1); for (int i = 0; i < v.size(); ++i) printf( %d , v[i]); putchar( n ); } int main() { run(); return 0; }
|
// Check that packed arrays of all sorts get elaborated without an error and
// that the resulting type has the right packed width.
package p;
typedef logic [2:0] vector;
endpackage
module test;
typedef bit bit2;
typedef logic [1:0] vector;
bit2 [1:0] b;
vector [2:0] l;
p::vector [3:0] scoped_pa;
typedef enum logic [7:0] {
A
} E;
typedef E [1:0] EP;
typedef EP [2:0] EPP;
E e;
EP ep1;
E [1:0] ep2;
EP [2:0] epp1;
EPP epp2;
EPP [3:0] eppp;
enum logic [7:0] {
B
} [1:0] ep3;
typedef struct packed {
longint x;
} S1;
typedef struct packed {
time t;
integer i;
logic [1:0] x;
bit [3:0] y;
int z;
shortint w;
E e;
EP ep;
S1 s;
} S2;
localparam S_SIZE = 64 + 32 + 2 + 4 + 32 + 16 + 8 + 8*2 + 64;
typedef S2 [3:0] SP;
typedef SP [9:0] SPP;
S2 s;
SP sp1;
S2 [3:0] sp2;
SP [9:0] spp1;
SPP spp2;
SPP [1:0] sppp;
struct packed {
S2 s;
} [3:0] sp3;
bit failed = 1'b0;
initial begin
// Packed arrays of basic types
failed |= $bits(b) !== 2;
failed |= $bits(l) !== 2 * 3;
failed |= $bits(scoped_pa) !== 3 * 4;
// Packed arrays of enums
failed |= $bits(e) !== 8;
failed |= $bits(ep1) !== $bits(e) * 2;
failed |= $bits(ep2) !== $bits(ep1);
failed |= $bits(ep3) !== $bits(ep1);
failed |= $bits(epp1) !== $bits(ep1) * 3;
failed |= $bits(epp2) !== $bits(epp1);
failed |= $bits(eppp) !== $bits(epp1) * 4;
// Packed arrays of structs
failed |= $bits(s) !== S_SIZE;
failed |= $bits(sp1) !== $bits(s) * 4;
failed |= $bits(sp2) !== $bits(sp1);
failed |= $bits(sp3) !== $bits(sp1);
failed |= $bits(spp1) !== $bits(sp1) * 10;
failed |= $bits(spp1) !== $bits(spp2);
failed |= $bits(sppp) !== $bits(spp1) * 2;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Top module for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, ////
//// - Younjoo Kim, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module HIGHT_CORE_TOP(
rstn ,
clk ,
i_mk_rdy ,
i_mk ,
i_post_rdy ,
i_op ,
i_text_val ,
i_text_in ,
o_text_done ,
o_text_out ,
o_rdy
);
//=====================================
//
// PARAMETERS
//
//=====================================
//=====================================
//
// I/O PORTS
//
//=====================================
input rstn ;
input clk ;
input i_mk_rdy ;
input[127:0] i_mk ;
input i_post_rdy ;
input i_op ;
input i_text_val ;
input[63:0] i_text_in ;
output o_text_done ;
output[63:0] o_text_out ;
output o_rdy ;
//=====================================
//
// REGISTERS
//
//=====================================
//=====================================
//
// WIRES
//
//=====================================
wire[31:0] w_rnd_key ;
wire[2:0] w_xf_sel ;
wire w_rf_final ;
wire w_key_sel ;
wire[4:0] w_rnd_idx ;
wire w_wf_post_pre ;
//=====================================
//
// MAIN
//
//=====================================
// CYPTO_PATH instance
CRYPTO_PATH u_CRYPTO_PATH(
.rstn ( rstn ) ,
.clk ( clk ) ,
.i_op ( i_op ) ,
.i_wrsk ( w_rnd_key ) ,
.i_text_in ( i_text_in ) ,
.i_xf_sel ( w_xf_sel ) ,
.i_rf_final ( w_rf_final ) ,
.o_text_out ( o_text_out )
);
// KEY_SCHED instance
KEY_SCHED u_KEY_SCHED(
.rstn ( rstn ) ,
.clk ( clk ) ,
.i_mk ( i_mk ) ,
.i_op ( i_op ) ,
.i_key_sel ( w_key_sel ) ,
.i_rnd_idx ( w_rnd_idx ) ,
.i_wf_post_pre ( w_wf_post_pre ) ,
.o_rnd_key ( w_rnd_key )
);
// CONTROL instance
CONTROL u_CONTROL(
.rstn ( rstn ) ,
.clk ( clk ) ,
.i_mk_rdy ( i_mk_rdy ) ,
.i_post_rdy ( i_post_rdy ) ,
.i_text_val ( i_text_val ) ,
.o_rdy ( o_rdy ) ,
.o_text_done ( o_text_done ) ,
.o_xf_sel ( w_xf_sel ) ,
.o_rf_final ( w_rf_final ) ,
.o_key_sel ( w_key_sel ) ,
.o_rnd_idx ( w_rnd_idx ) ,
.o_wf_post_pre ( w_wf_post_pre )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Juan Jos� Rojas Salazar
//
// Create Date: 08/01/2016 03:34:00 PM
// Design Name:
// Module Name: DESNORMALIZADOR_DESLINEALIZADOR
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DESNORMALIZADOR_DESLINEALIZADOR(
input wire CLK,
input wire [31:0] I,
input wire [31:0] V,
input wire RST_EX_FF,
input wire Begin_FSM_I,
//input wire Begin_FSM_V,
output wire ACK_I,
//output wire ACK_V,
// output wire U_F,
// output wire O_F,
output wire [31:0] RESULT_I
//output wire [31:0] RESULT_V
);
// wire ACK_EX;
wire ACK_FF;
wire [31:0] FLOATING;
I_DESNORM_FIXED_TO_FLOAT DESNORM_I_FIXED_FLOAT(
.CLK(CLK), //system clock
.F(I), //VALOR BINARIO EN COMA FIJA
.RST_FF(RST_EX_FF), //system reset
.Begin_FSM_FF(Begin_FSM_I), //INICIA LA CONVERSION
.ACK_FF(ACK_FF), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(FLOATING) //RESULTADO FINAL
);
DESLINEALIZADOR #(.P(32)) DESLINEALIZADOR_FLOAT (
.CLK(CLK), //system clock
.T(FLOATING), //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
//.T(I), //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
.RST_EX(RST_EX_FF), //system reset
.Begin_FSM_EX(ACK_FF), //INICIA EL CALCULO
//.Begin_FSM_EX(Begin_FSM_I), //INICIA EL CALCULO
.ACK_EX(ACK_I), //INDICA QUE EL CALCULO FUE REALIZADO
.O_FX(), //BANDERA DE OVER FLOW X
.O_FY(), //BANDERA DE OVER FLOW X
.O_FZ(), //BANDERA DE OVER FLOW X
.U_FX(), //BANDERA DE UNDER FLOW Y
.U_FY(), //BANDERA DE UNDER FLOW Y
.U_FZ(), //BANDERA DE UNDER FLOW Y
.RESULT(RESULT_I) //RESULTADO FINAL
);
/*V_DESNORM_FIXED_TO_FLOAT DESNORM_V_FIXED_FLOAT(
.CLK(CLK), //system clock
.F(V), //VALOR BINARIO EN COMA FIJA
.RST_FF(RST_EX_FF), //system reset
.Begin_FSM_FF(Begin_FSM_V), //INICIA LA CONVERSION
.ACK_FF(ACK_V), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(RESULT_V) //RESULTADO FINAL
);*/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 08:42:14 AM
// Design Name:
// Module Name: ROM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ROM_test #(parameter W=32)
(
input wire [9:0] address,
output reg [W-1:0] data
);
//localparam ROM_FILE32 = "F:/VECTOR_Rango.txt";
//localparam ROM_FILE32 = "/home/jjrojas/Documents/0.-0.58495_HEX.txt";
localparam ROM_FILE32 = "/home/carlos/Documents/Theta_2_ptofijo.txt";
//localparam ROM_FILE32 = "/home/carlos/Documents/0.58495-1.3485856_HEX.txt";
//localparam ROM_FILE32 = "/home/jjrojas/Documents/VECTOR_V_NORM_HEX.txt";
localparam ROM_FILE64= "C:\Users\Adri�n\Desktop\RTL\NORMALIZACION_V.txt";
//(* rom_style="{distributed | block}" *)
reg [W-1:0] rom_test [1023:0];
generate
if(W==32)
initial
begin
$readmemb( ROM_FILE32 , rom_test, 0, 1023);
end
else
initial
begin
$readmemh(ROM_FILE64, rom_test, 0, 1023);
end
endgenerate
always @*
begin
data = rom_test[address];
end
endmodule
|
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