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module test_1; // Very simple testbench to check A = 1234 B = 1234, Winning in the first step.
reg I1,I2,I3,I4,enter,reset;
wire win,lose;
wire equal,bigger,smaller;
wire [0:3]nums;
test test_v1(I1,I2,I3,I4,enter,win,lose,reset,equal,bigger,smaller,nums);
initial begin
I1 = 0;
I2 = 0;
I3 = 0;
I4 = 0;
enter = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
end
endmodule
module test_2; // Very simple testbench to check A = 42413 B = 4241, 42413, Winning in the 2nd step.
reg I1,I2,I3,I4,enter,reset;
wire win,lose;
wire equal,bigger,smaller;
wire [0:3]nums;
test test_v1(I1,I2,I3,I4,enter,win,lose,reset,equal,bigger,smaller,nums);
initial begin
I1 = 0;
I2 = 0;
I3 = 0;
I4 = 0;
enter = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 enter = 1;
#5 enter = 0;
end
endmodule
module test_3; // A testbench to check A = 14321 B = 1234, 12341, 14321, winning in the third step.
reg I1,I2,I3,I4,enter,reset;
wire win,lose;
wire equal,bigger,smaller;
wire [0:3]nums;
test test_v1(I1,I2,I3,I4,enter,win,lose,reset,equal,bigger,smaller,nums);
initial begin
I1 = 0;
I2 = 0;
I3 = 0;
I4 = 0;
enter = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 enter = 1;
#5 enter = 0;
end
endmodule
module test_4; // A testbench to check A = 14321 B = 1234, 12341, 14324, losing.
reg I1,I2,I3,I4,enter,reset;
wire win,lose;
wire equal,bigger,smaller;
wire [0:3]nums;
test test_v1(I1,I2,I3,I4,enter,win,lose,reset,equal,bigger,smaller,nums);
initial begin
I1 = 0;
I2 = 0;
I3 = 0;
I4 = 0;
enter = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
end
endmodule
module test_5; // A testbench to check for invalid values of input A, A first enters 123 and then 12 and then 1234 and B also 1234.
reg I1,I2,I3,I4,enter,reset;
wire win,lose;
wire equal,bigger,smaller;
wire [0:3]nums;
test test_v1(I1,I2,I3,I4,enter,win,lose,reset,equal,bigger,smaller,nums);
initial begin
I1 = 0;
I2 = 0;
I3 = 0;
I4 = 0;
enter = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
#5 I1 = 1;
#5 I1 = 0;
#5 I2 = 1;
#5 I2 = 0;
#5 I3 = 1;
#5 I3 = 0;
#5 I4 = 1;
#5 I4 = 0;
#5 enter = 1;
#5 enter = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1e5 + 10; int n, S; long long tot; struct Node { long long val; long long num; long long sum; bool operator<(const Node &rhs) const { return num < rhs.num; } }; vector<Node> a, b; long long work(long long ls, vector<Node> &a) { int id = upper_bound(a.begin(), a.end(), Node{0, ls}) - a.begin(); long long ret = 0; if (--id >= 0) { ret = a[id].sum; } if (id + 1 != a.size()) { long long left = ls - (id == -1 ? 0 : a[id].num); ret += left * a[id + 1].val; } return ret; } long long cal(long long x) { long long ret = work(x * S, a); ret += work((tot - x) * S, b); return ret; } long long solve(long long l, long long r) { while (r > l) { long long m1 = (2 * l + r) / 3; long long m2 = (2 * r + l + 2) / 3; long long ret1 = cal(m1); long long ret2 = cal(m2); if (ret1 > ret2) r = m2 - 1; else l = m1 + 1; } return cal(l); } int main() { scanf( %d%d , &n, &S); long long cnt = 0; long long now = 0; for (int i = 0; i < n; ++i) { int x, y, z; scanf( %d%d%d , &x, &y, &z); cnt += x; now += 1ll * x * min(y, z); if (y > z) a.emplace_back(Node{1ll * y - z, 1ll * x, 1ll * (y - z) * x}); else if (y < z) b.emplace_back(Node{1ll * z - y, 1ll * x, 1ll * (z - y) * x}); } sort(a.begin(), a.end(), [](Node x, Node y) { return x.val > y.val; }); sort(b.begin(), b.end(), [](Node x, Node y) { return x.val > y.val; }); tot = cnt / S + (cnt % S > 0); for (int i = 0; i < a.size(); ++i) { if (i) a[i].sum += a[i - 1].sum, a[i].num += a[i - 1].num; } for (int i = 0; i < b.size(); ++i) { if (i) b[i].sum += b[i - 1].sum, b[i].num += b[i - 1].num; } printf( %I64d n , solve(0, tot) + now); return 0; }
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#include <bits/stdc++.h> using namespace std; long long c[100001]; void init() { long long n, x; long long ans = 0; cin >> n >> x; for (int i = 0; i < n; i++) cin >> c[i]; sort(c, c + n); for (int i = 0; i < n; i++) { ans += c[i] * x; if (x > 1) x--; } cout << ans << endl; } int main() { init(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:36777216 ) using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; const int oo = 0x3f3f3f3f; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline T lowbit(T n) { return (n ^ (n - 1)) & n; } template <class T> inline int countbit(T n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } template <class T> inline T gcd(T a, T b) { T c; while (a != 0) { c = a; a = b % a; b = c; } return b; } template <class T> inline T mabs(T a) { if (a < 0) return -a; else return a; } typedef vector<int> VI; typedef vector<VI> VII; typedef vector<string> VS; const int N = (int)21; const int MOD = (int)1e9 + 7; int g[N][N]; inline int solve(int testnum) { int n, k; cin >> n >> k; map<string, int> names; names.clear(); map<int, string> idx2name; idx2name.clear(); for (int i = (0); i < int(n); i++) { string s; cin >> s; names[s] = i; idx2name[i] = s; } for (int i = (0); i < int(n); i++) for (int j = (0); j < int(n); j++) g[i][j] = 1; for (int i = (0); i < int(k); i++) { string a, b; cin >> a >> b; int ia = names[a]; int ib = names[b]; g[ia][ib] = 0; } int best = 0; for (int mask = (0); mask < int((1 << (n))); mask++) { int f = 1; for (int i = (0); i < int(n); i++) { if ((mask & (1 << (i))) > 0) { for (int j = (0); j < int(n); j++) if ((mask & (1 << (j))) > 0) { if (g[i][j] == 0) { f = 0; } } } } if (!f || !mask) continue; if (countbit(mask) > countbit(best)) { best = mask; } } VS ret; ret.clear(); for (int b = (0); b < int(n); b++) if ((best & (1 << (b))) > 0) { ret.push_back(idx2name[b]); } sort((ret).begin(), (ret).end()); printf( %d n , ret.size()); for (auto &j : ret) printf( %s n , j.c_str()); return 0; } int main(int argc, char *argv[]) { ios::sync_with_stdio(false); int t = 1; if (argc > 1) t = atoi(argv[1]); for (int _t = (1); _t < int(t + 1); _t++) { int ret = ::solve(_t); if (ret == -1) { cerr << Failed test # << _t << endl; break; } cerr << Solved test # << _t << endl; } return 0; }
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
* Author: Darrell Harmon
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
* clock must be same as FPC FIFO and TPC FIFO
* reset is sync, active high
* fpc_ signals go to a from PC fifo
* tpc_ signals go to a to PC fifo
*
* User logic interface:
* wvalid: indicates valid write data is available on wdata and address
* rvalid: indicates a valid read request
* address: address for read and write. qualified by wvalid or rvalid
* wdata: write data. qualified by wvalid
* rdata: read data, present read data here RPIPE cycles after rvalid.
* status: inputs for wait condition instruction
*
* sequencer instructions:
* NOP: fpc_data[63:0] = 0
* WRITE: fpc_data[63:62] = 2
* fpc_data[ABITS-1:0] = address
* fpc_data[61] = increment
* fpc_data[47:32] = count
* fpc_data[31:0] = address
* READ:
* fpc_data[63:62] = 3
* fpc_data[61] = increment
* fpc_data[47:32] = count
* fpc_data[31:0] = address
* WAIT:
* fpc_data[63:62] = 1
* fpc_data[31:0] = timeout (clock cycles)
* fpc_data[39:32] = status bit
* fpc_data[41:40] = mode
* mode = 0: unconditional wait
* mode = 2: wait for status bit to be clear
* mode = 3: wait for status btt to be set
*/
module sequencer
(
input clock,
input reset,
// FPC FIFO
output fpc_read,
input fpc_valid,
input [63:0] fpc_data,
// TPC FIFO
input tpc_ready,
output tpc_write,
output [63:0] tpc_data,
// user logic interface
output reg rvalid = 0,
output reg wvalid = 0,
output reg [ABITS-1:0] address = 0,
output reg [DBITS-1:0] wdata = 0,
input [DBITS-1:0] rdata,
input [SBITS-1:0] status
);
parameter RPIPE = 2; // > 2
parameter ABITS = 16; // 1 to 32
parameter DBITS = 64; // 1 to 64
parameter SBITS = 16; // 1 to 64
parameter CBITS = 24; // 2 to 28
reg [CBITS-1:0] count = 32'hDEADBEEF;
reg [1:0] state = 0;
reg inc = 0;
wire rvalid_next = (state == 3) && tpc_ready;
wire wvalid_next = (state == 2) && fpc_read;
assign fpc_read = fpc_valid && ((state == 0) || (state == 2));
always @ (posedge clock)
begin
rvalid <= rvalid_next;
wvalid <= wvalid_next;
address <= (state == 0) ? fpc_data[ABITS-1:0] :
address + (inc && (rvalid || wvalid));
wdata <= fpc_data[DBITS-1:0];
inc <= (state == 0) ? fpc_data[61] : inc;
case(state)
0: count <= fpc_data[CBITS+31:32];
1: count <= count - 1'b1;
2: count <= count - wvalid_next;
3: count <= count - rvalid_next;
endcase
if(reset)
state <= 2'd0;
else
begin
case(state)
0: state <= fpc_read ? fpc_data[63:62] : 2'd0; // idle, nop
// wait, read, write
default: state <= (count[CBITS-1:1] == 0) ? 2'd0 : state;
endcase
end
end
// delay tpc_write RPIPE cycles from rvalid to allow for a read pipeline
delay_n #(.N(RPIPE)) delay_tpc_write
(.clock(clock), .in(rvalid), .out(tpc_write));
assign tpc_data = rdata;
endmodule
module delay_n
(
input clock,
input in,
output out
);
parameter N = 2;
reg [N-1:0] sreg = 0;
assign out = sreg[N-1];
always @ (posedge clock)
sreg <= {sreg[N-2:0],in};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 55, p = 1e9 + 7; int n, m; long long inv[Maxn], f[Maxn][Maxn], g[Maxn][Maxn], sum[Maxn][Maxn]; long long get_inv(int x) { return x <= 1 ? 1 : (p - p / x) * get_inv(p % x) % p; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) inv[i] = get_inv(i); f[0][1] = sum[0][1] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= i + 1; j++) for (int k = 1; k <= i; k++) (g[i][j] += sum[k - 1][j] * sum[i - k][j]) %= p; for (int j = 1; j <= i + 1; j++) { (g[i][j] += p - g[i][j + 1]) %= p; for (int a = n; a >= 0; a--) for (int b = n + 1; b >= 0; b--) { long long now = 1; for (int d = 1; i * d <= a && j * d <= b; d++) { (now *= inv[d] * (g[i][j] + d - 1 + p) % p) %= p; (f[a][b] += now * f[a - i * d][b - j * d]) %= p; } } } for (int j = i + 1; j >= 1; j--) sum[i][j] = (sum[i][j + 1] + f[i][j]) % p; } printf( %lld , f[n][m]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-8; const long long SZ = 1010, SSZ = 100010, APB = 26, one = 93, INF = 0x3f3f3f3f3f3f3f3f, mod = 1000000007; long long n, m, bg, fn, cnt; long long to[SSZ], wt[SSZ], head[SZ]; long long nex[SSZ], mk[SSZ]; long long dfn[SZ], low[SZ], tot; bool vst[SZ]; void add(long long u, long long v, long long w) { ++cnt; nex[cnt] = head[u]; head[u] = cnt; to[cnt] = v, wt[cnt] = w; } bool dfs(long long x) { vst[x] = 1; if (x == fn) return 1; for (long long i = head[x]; i != -1; i = nex[i]) { long long t = to[i]; if (!vst[t]) { mk[i] = 1; if (dfs(t)) return 1; mk[i] = 0; } } return 0; } stack<long long> stk; void tar(long long x, long long p, long long &res2, long long &eg2) { dfn[x] = low[x] = ++tot; vst[x] = 1; for (long long i = head[x]; i != -1; i = nex[i]) { if (i != (p ^ 1) && mk[i] != 2 && mk[i ^ 1] != 2) { long long t = to[i], w = wt[i]; if (!dfn[t]) { tar(t, i, res2, eg2); low[x] = min(low[x], low[t]); } else low[x] = min(low[x], low[t]); if (dfn[x] < low[t] && dfn[fn] >= dfn[t]) { if (w < res2) { res2 = w, eg2 = i; } } } } } void init() { cin >> n >> m >> bg >> fn; cnt = -1; memset(head, -1, sizeof(head)); for (long long i = 1; i <= m; ++i) { long long a, b, c; cin >> a >> b >> c; add(a, b, c); add(b, a, c); } dfs(bg); if (vst[fn] == 0) { cout << 0 << endl << 0; return; } long long res = INF, vt1 = -1, vt2; for (long long i = 0; i <= cnt; ++i) { if (mk[i]) { mk[i] = 2; memset(vst, 0, sizeof(vst)); tot = 0; memset(dfn, 0, sizeof(dfn)); memset(low, 0, sizeof(low)); long long res1 = wt[i], res2 = INF, eg1 = i, eg2; tar(bg, -1, res2, eg2); if (!vst[fn]) res2 = 0, eg2 = -5; if (res1 + res2 < res) { res = res1 + res2; vt1 = eg1 / 2 + 1, vt2 = eg2 / 2 + 1; } mk[i] = 1; } } if (vt1 == -1) { cout << -1 << endl; return; } cout << res << endl; cout << (vt2 == -1 ? 1 : 2) << endl; cout << vt1 << ; if (vt2 != -1) cout << vt2 << endl; } void work() {} int main() { std::ios::sync_with_stdio(0); long long casenum; { init(); work(); } return 0; }
|
// file: clk_wiz_v3_6_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_wiz_v3_6_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
clk_wiz_v3_6 clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; bool solve(string temp, string p) { int i = 0, j = 0; while (i != temp.size()) { if (temp[i] == p[j]) { i++; j++; } else i++; if (j == p.size()) break; } if (i <= temp.size() && j >= p.size()) return true; else return false; } int main() { string s, p; cin >> s >> p; int n = s.size(); int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int lo = 0, hi = n - 1, mid = (hi + lo) / 2; while (lo <= hi) { string temp = s; for (int i = 0; i < mid; i++) temp[arr[i] - 1] = 0 ; if (solve(temp, p)) lo = mid + 1; else hi = mid - 1; mid = (hi + lo) / 2; } cout << mid; }
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DEBUG INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
integer test_nr;
integer test_var;
integer dco_clk_counter;
always @ (negedge dco_clk)
dco_clk_counter <= dco_clk_counter+1;
integer dbg_clk_counter;
always @ (negedge dbg_clk)
dbg_clk_counter <= dbg_clk_counter+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_I2C
`ifdef ASIC_CLOCKING
test_nr = 0;
#1 dbg_en = 0;
repeat(30) @(posedge dco_clk);
stimulus_done = 0;
// Make sure the CPU always starts executing when the
// debug interface is disabled during POR.
// Also make sure that the debug interface clock is stopped
// and that it is under reset
//--------------------------------------------------------
dbg_en = 0;
test_nr = 1;
@(negedge dco_clk) dbg_clk_counter = 0;
repeat(300) @(posedge dco_clk);
if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) =====");
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");
test_var = r14;
// Make sure that enabling the debug interface after the POR
// don't stop the cpu
// Also make sure that the debug interface clock is running
// and that its reset is released
//--------------------------------------------------------
dbg_en = 1;
test_nr = 2;
@(negedge dco_clk) dbg_clk_counter = 0;
repeat(300) @(posedge dco_clk);
if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) =====");
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");
// Make sure that disabling the CPU with debug enabled
// will stop the CPU
// Also make sure that the debug interface clock is stopped
// and that it is NOT under reset
//--------------------------------------------------------
cpu_en = 0;
dbg_en = 1;
test_nr = 3;
#(6*50);
test_var = r14;
dbg_clk_counter = 0;
#(300*50);
if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) =====");
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) =====");
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");
cpu_en = 1;
repeat(6) @(negedge dco_clk);
// Create POR with debug enable and observe the
// behavior depending on the DBG_RST_BRK_EN define
//--------------------------------------------------------
dbg_en = 1;
test_nr = 4;
@(posedge dco_clk); // Generate POR
reset_n = 1'b0;
@(posedge dco_clk);
reset_n = 1'b1;
repeat(300) @(posedge dco_clk);
`ifdef DBG_RST_BRK_EN
if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
`else
if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
`endif
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`endif
// Make sure that DBG_EN resets the debug interface
//--------------------------------------------------------
test_nr = 5;
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge dco_clk);
dbg_i2c_wr(CPU_CTL, 16'h0000);
dbg_i2c_wr(MEM_DATA, 16'haa55);
dbg_i2c_rd(CPU_CTL);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");
test_var = r14; // Backup the current register value
@(posedge dco_clk); // Resets the debug interface
dbg_en = 1'b0;
repeat(2) @(posedge dco_clk);
dbg_en = 1'b1;
// Make sure that the register was not reseted
if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");
repeat(2) @(posedge dco_clk);
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Make sure that RESET_N resets the debug interface
//--------------------------------------------------------
test_nr = 6;
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge dco_clk);
dbg_i2c_wr(CPU_CTL, 16'h0000);
dbg_i2c_wr(MEM_DATA, 16'haa55);
dbg_i2c_rd(CPU_CTL);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");
test_nr = 7;
@(posedge dco_clk); // Generates POR
reset_n = 1'b0;
repeat(2) @(posedge dco_clk);
reset_n = 1'b1;
// Make sure that the register was reseted
if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");
repeat(2) @(posedge dco_clk);
test_nr = 8;
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
test_nr = 9;
// Generate IRQ to terminate the test pattern
irq[`IRQ_NR-15] = 1'b1;
@(r13);
irq[`IRQ_NR-15] = 1'b0;
stimulus_done = 1;
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
`else
tb_skip_finish("| (serial debug interface I2C not included) |");
`endif
`else
tb_skip_finish("| (serial debug interface not included) |");
`endif
end
|
#include <bits/stdc++.h> int main() { long long int a, b = 1, i; scanf( %I64d , &a); for (i = 1; i <= a; i++) { b += 12 * (1 + i - 2); } if (a == 1) printf( 1 ); else printf( %I64d , b); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:30:15 03/30/2016
// Design Name: MAIN
// Module Name: Y:/TEOCOA/EXP3/TEST.v
// Project Name: EXP3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MAIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST;
// Inputs
reg [2:0] ALU_OP;
reg [2:0] AB_SW;
reg [2:0] F_LED_SW;
// Outputs
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
MAIN uut (
.ALU_OP(ALU_OP),
.AB_SW(AB_SW),
.F_LED_SW(F_LED_SW),
.LED(LED)
);
initial begin
// Initialize Inputs
ALU_OP = 4;
AB_SW = 3;
F_LED_SW = 3;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 4;
AB_SW = 3;
F_LED_SW = 2;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 4;
AB_SW = 3;
F_LED_SW = 1;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 4;
AB_SW = 3;
F_LED_SW = 0;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 2;
AB_SW = 6;
F_LED_SW = 3;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 2;
AB_SW = 6;
F_LED_SW = 2;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 2;
AB_SW = 6;
F_LED_SW = 1;
// Wait 100 ns for global reset to finish
#100;
ALU_OP = 2;
AB_SW = 6;
F_LED_SW = 0;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void test_case(); long long power(int n, int p); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { test_case(); } return 0; } void test_case() { int n, x; cin >> n >> x; vector<int> arr(n); for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr.begin(), arr.end()); int teams = 0; int cnt = 1; for (int ptr = n - 1; ptr >= 0; ptr--) { if (arr[ptr] * cnt >= x) { teams++; cnt = 1; } else cnt++; } cout << teams << n ; } long long power(int n, int p) { long long ans = 1; if (p == 0) return 1; long long temp = power(n, p / 2); if (p % 2 == 0) ans = (temp * temp) % 1000000007; else { ans = (ans * n) % 1000000007; ans *= (temp * temp) % 1000000007; } return ans; }
|
#include <bits/stdc++.h> using namespace std; void openfile() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } const int nmax = 1 << 16; int n, k; int a[nmax]; vector<string> name; map<string, int> num; vector<vector<int> > g; int main() { cin >> n >> k; g.resize(n); name.resize(n); for (int i = 0; i < n; i++) { cin >> name[i]; num[name[i]] = i; } for (int i = 0; i < k; i++) { string s1, s2; cin >> s1 >> s2; int v1 = num[s1], v2 = num[s2]; g[v1].push_back(v2); g[v2].push_back(v1); } int ans, cans = 0; for (int i = 0; i < nmax; i++) { int cur = 0; for (int j = 0; j < n; j++) { if (i & (1 << j)) cur++; } for (int j = 0; j < n; j++) { if (i & (1 << j)) { for (int q = 0; q < ((int)((g[j]).size())); q++) { if (i & (1 << g[j][q])) { cur = 0; break; } } } } if (cur > cans) { ans = i; cans = cur; } } cout << cans << endl; set<string> b; for (int i = 0; i < n; i++) { if (ans & (1 << i)) { b.insert(name[i]); } } for (set<string>::iterator it = b.begin(); it != b.end(); it++) { cout << *it << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1000 * 1000 * 1000 + 7; const int N = 1000 * 1000 + 7; long long a[N]; multiset<long long> st; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) scanf( %I64d , a + i); long long ans = 0; for (int i = 0; i < n; ++i) { if (st.size() > 0) { if (*st.begin() < a[i]) { ans += a[i] - *st.begin(); st.erase(st.begin()); st.insert(a[i]); } } st.insert(a[i]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename type> type input() { type var; cin >> var; return var; } template <typename type> void input(type &var) { cin >> var; return; } template <typename type> void output(type &var, const char *ch) { cout << var << ch; } int main() { long long a, b, N, p, r, c, d, e, f; cin >> N >> p; vector<pair<long long, long long> > v(N); vector<double> w(N); for (int i = 0; i < N; i++) { cin >> a >> b; v[i].first = b - a + 1; v[i].second = b / p - (a - 1) / p; } double s = 0; for (int i = 0; i < N; i++) { c = v[i].first, e = v[(i + 1) % N].first, d = v[i].second, f = v[(i + 1) % N].second; w[i] = 2000 * ((c * e - (c - d) * (e - f)) / (c * e * 1.0)); s += w[i]; } cout << setiosflags(ios::showpoint) << setiosflags(ios::fixed) << setprecision(9) << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x, zhan[100500], tree[100500], o, ans[100500], now = 1; struct edge { int x, t, id, r; bool operator<(const edge &xx) const { if (x != xx.x) return x < xx.x; return id < xx.id; } } aa[100500]; void add(int x, int y) { for (int i = x; i <= n; i += (i & (-i))) tree[i] += y; } int get(int x) { int ans = 0; for (int i = x; i >= 1; i -= (i & (-i))) ans += tree[i]; return ans; } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d%d%d , &aa[i].r, &aa[i].t, &aa[i].x); aa[i].id = i; zhan[++o] = aa[i].t; } sort(zhan + 1, zhan + o + 1); o = unique(zhan + 1, zhan + o + 1) - zhan - 1; for (int i = 1; i <= n; i++) { aa[i].t = lower_bound(zhan + 1, zhan + o + 1, aa[i].t) - zhan; } sort(aa + 1, aa + n + 1); memset(ans, -1, sizeof(ans)); for (int i = 1; i <= n; i++) { if (aa[i].x != aa[i - 1].x) while (now != i) { if (aa[now].r == 1) add(aa[now].t, -1); if (aa[now].r == 2) add(aa[now].t, 1); now++; } if (aa[i].r == 1) add(aa[i].t, 1); if (aa[i].r == 2) add(aa[i].t, -1); if (aa[i].r == 3) ans[aa[i].id] = get(aa[i].t); } for (int i = 1; i <= n; i++) if (ans[i] != -1) printf( %d n , ans[i]); }
|
module test();
typedef bit [63:0] bit64;
typedef logic [63:0] vec64;
byte byte_array [];
bit [15:0] bit_array [];
logic [31:0] vec_array [];
real real_array [];
bit64 bit_result;
vec64 vec_result;
reg failed = 0;
initial begin
byte_array = new [8];
foreach (byte_array[i]) byte_array[i] = i*16 + i;
bit_result = bit64'(byte_array);
$display("%h", bit_result);
if (bit_result !== 64'h0011223344556677) failed = 1;
vec_result = vec64'(byte_array);
$display("%h", vec_result);
if (vec_result !== 64'h0011223344556677) failed = 1;
bit_array = new [4];
foreach (bit_array[i]) bit_array[i] = i*4096 + i*256 + i*16 + i;
bit_result = bit64'(bit_array);
$display("%h", bit_result);
if (bit_result !== 64'h0000111122223333) failed = 1;
vec_result = vec64'(bit_array);
$display("%h", vec_result);
if (vec_result !== 64'h0000111122223333) failed = 1;
vec_array = new [2];
vec_array[0] = 32'b01xz_0001_0010_0011_0100_0101_0110_0111;
vec_array[1] = 32'b1000_1001_1010_1011_1100_1101_1110_1111;
bit_result = bit64'(vec_array);
$display("%h", bit_result);
if (bit_result !== 64'b0100_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111) failed = 1;
vec_result = vec64'(vec_array);
$display("%h", vec_result);
if (vec_result !== 64'b01xz_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111) failed = 1;
real_array = new [1];
real_array[0] = 1.;
bit_result = bit64'(real_array);
$display("%h", bit_result);
if (bit_result !== $realtobits(1.)) failed = 1;
vec_result = vec64'(real_array);
$display("%h", vec_result);
if (vec_result !== $realtobits(1.)) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// delay_in.v
`timescale 1 ns / 1 ps
/* parameter delay [ns] sampling point position
0_0000_0 0.00 19
0_0000_1 1.25 18
0_0001_0 2.50 17
0_0001_1 3.75 16
0_0011_0 5.00 15
0_0011_1 6.25 14
0_0111_0 7.50 13
0_0111_1 8.75 12
0_1111_0 10.00 11
0_1111_1 11.25 10
1_0000_0 12.50 9
1_0000_1 13.75 8
1_0001_0 15.00 7
1_0001_1 16.25 6
1_0011_0 17.50 5
1_0011_1 18.75 4
1_0111_0 20.00 3
1_0111_1 21.25 2
1_1111_0 22.50 1
1_1111_1 23.75 0
*/
module delay_in
(
// avalon clock interface
input csi_clock_clk,
input csi_clock_reset,
// avalon mm slave: control
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
input sync,
input clk400,
input sig_in,
output reg sig_out40,
output sig_out80
);
// avalon ctrl interface
wire clk80 = csi_clock_clk;
wire reset = csi_clock_reset;
reg [5:0]delay;
always @(posedge clk80 or posedge reset)
begin
if (reset) delay <= 0;
else if (avs_ctrl_write) delay <= avs_ctrl_writedata[5:0];
end
wire [5:0]delout;
// 1.25 ns delay step
delay_ddrin half_stage
(
.clk(clk400),
.reset(reset),
.select(delay[0]),
.in(sig_in),
.out(delout[0])
);
// 4 x 2.5 ns delay step
delay_in_stage d1(clk400, reset, delay[1], delout[0], delout[1]);
delay_in_stage d2(clk400, reset, delay[2], delout[1], delout[2]);
delay_in_stage d3(clk400, reset, delay[3], delout[2], delout[3]);
delay_in_stage d4(clk400, reset, delay[4], delout[3], delout[4]);
// clock crossing register
reg ccreg;
always @(posedge clk80 or posedge reset)
begin
if (reset) ccreg <= 0;
else ccreg <= delout[4];
end
// 12.5 ns delay stage
delay_in_stage d5(clk80, reset, delay[5], ccreg, delout[5]);
assign sig_out80 = delout[5];
always @(posedge clk80 or posedge reset)
begin
if (reset) sig_out40 <= 0;
else if (sync) sig_out40 <= delout[5];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A41O_FUNCTIONAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; struct box { long long int x1, x2, y1, y2; box() : x1(0), x2(0), y1(0), y2(0) {} box(int x1, int x2, int y1, int y2) : x1(x1), x2(x2), y1(y1), y2(y2) {} }; struct edge { long long int to, c, f; edge() : to(0), c(0), f(0) {} edge(int to, long long int c, int f) : to(to), c(c), f(f) {} }; bool ins(box a, box b) { if (a.x1 >= b.x1 && a.x2 <= b.x2 && a.y1 >= b.y1 && a.y2 <= b.y2) { return 1; } return 0; } const int M = 5000000; edge edges[M]; vector<int> g[M]; int cnt = 0; int nxt[M]; int d[M]; int oy[40000]; int ox[40000]; int lasty[10000]; vector<int> how; int n1; void addedge(int v, int u, long long int c) { edges[cnt] = edge(u, c, 0); g[v].push_back(cnt++); edges[cnt] = edge(v, 0, 0); g[u].push_back(cnt++); } void buildy(int v, int l, int r) { if (l == r) { addedge(100000, v, 1); return; } int m = (l + r) / 2; buildy(2 * v, l, m); buildy(2 * v + 1, m + 1, r); addedge(2 * v, v, 1000000); addedge(2 * v + 1, v, 1000000); return; } void buildx(int v, int l, int r) { if (l == r) { addedge(v + 40000, 100001, 1); return; } int m = (l + r) / 2; buildx(2 * v, l, m); buildx(2 * v + 1, m + 1, r); addedge(v + 40000, 2 * v + 40000, 1000000); addedge(v + 40000, 2 * v + 1 + 40000, 1000000); return; } void gety(int v, int l, int r, int l1, int r1) { if (l >= l1 && r <= r1) { how.push_back(v); return; } if (l > r1 || l1 > r) return; int m = (l + r) / 2; gety(2 * v, l, m, l1, r1); gety(2 * v + 1, m + 1, r, l1, r1); } void getx(int v, int l, int r, int l1, int r1) { if (l >= l1 && r <= r1) { for (auto c : how) { addedge(c, 40000 + v, 1000000000); } return; } if (l > r1 || l1 > r) return; int m = (l + r) / 2; getx(2 * v, l, m, l1, r1); getx(2 * v + 1, m + 1, r, l1, r1); } void makepr(int x1, int x2, int y1, int y2) { how.clear(); gety(1, 0, n1 - 1, x1, x2); getx(1, 0, n1 - 1, y1, y2); } bool bfs(int s, int t, int n) { for (int i = 0; i < n; i++) d[i] = 1000000; d[s] = 0; queue<int> q; q.push(s); while (q.size()) { int v = q.front(); q.pop(); for (auto c : g[v]) { int to = edges[c].to; if (d[to] <= d[v] + 1 || edges[c].c == edges[c].f) continue; d[to] = d[v] + 1; q.push(to); } } if (d[t] == 1000000) return 0; return 1; } long long int dfs(int v, int t, long long int f) { if (v == t) return f; if (f == 0) return 0; long long int sum = 0; for (; nxt[v] < g[v].size(); nxt[v]++) { int id = g[v][nxt[v]]; int to = edges[id].to; if (d[to] != d[v] + 1 || edges[id].c == edges[id].f) continue; long long int del = dfs(to, t, min(edges[id].c - edges[id].f, f - sum)); sum += del; edges[id].f += del; edges[id ^ 1].f -= del; if (sum == f) break; } return sum; } long long int dinic(int s, int t, int n) { long long int mf = 0; while (bfs(s, t, n)) { for (int i = 0; i < n; i++) nxt[i] = 0; mf += dfs(s, t, 1e9); } return mf; } bool cmp(box a, box b) { return (a.y1 < b.y1); } void solve() { cin >> n1; int m; cin >> m; vector<box> all(m); for (int i = 0; i < m; i++) { cin >> all[i].x1 >> all[i].y1 >> all[i].x2 >> all[i].y2; all[i].x1--; all[i].x2--; all[i].y1--; all[i].y2--; } sort(begin(all), end(all), cmp); buildy(1, 0, n1 - 1); buildx(1, 0, n1 - 1); for (auto c : all) { int x1, x2, y1, y2; y1 = c.x1; y2 = c.x2; x1 = c.y1; x2 = c.y2; int cur = 0; for (int i = 0; i < n1; i++) { if (lasty[cur] != lasty[i]) { if (cur >= y1 && i - 1 <= y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, cur, i - 1); for (int y = cur; y <= i - 1; y++) lasty[y] = x2 + 1; } if (cur < y1 && i - 1 > y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, y1, y2); for (int y = y1; y <= y2; y++) lasty[y] = x2 + 1; cur = i; } if (cur < y1 && i - 1 <= y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, y1, i - 1); for (int y = y1; y <= i - 1; y++) lasty[y] = x2 + 1; } if (cur >= y1 && i - 1 > y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, cur, y2); for (int y = cur; y <= y2; y++) lasty[y] = x2 + 1; } cur = i; } if (i == n1 - 1) { i++; if (cur >= y1 && i - 1 <= y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, cur, i - 1); for (int y = cur; y <= i - 1; y++) lasty[y] = x2 + 1; } if (cur < y1 && i - 1 > y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, y1, y2); for (int y = y1; y <= y2; y++) lasty[y] = x2 + 1; } if (cur < y1 && i - 1 <= y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, y1, i - 1); for (int y = y1; y <= i - 1; y++) lasty[y] = x2 + 1; } if (cur >= y1 && i - 1 > y2) { if (lasty[cur] != x1) makepr(lasty[cur], x1 - 1, cur, y2); for (int y = cur; y <= y2; y++) lasty[y] = x2 + 1; } } } } int cur = 0; for (int i = 0; i < n1; i++) { if (lasty[cur] != lasty[i]) { if (lasty[cur] <= n1 - 1) makepr(lasty[cur], n1 - 1, cur, i - 1); cur = i; } if (i == n1 - 1) { i++; if (lasty[cur] <= n1 - 1) makepr(lasty[cur], n1 - 1, cur, i - 1); cur = i; } } cout << dinic(100000, 100001, 100002); } int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); int t; t = 1; while (t) { t--; solve(); } }
|
#include <bits/stdc++.h> using namespace std; char getDiffColor(char a, char b) { map<char, bool> mp; mp[a] = true, mp[b] = true; if (mp.find( R ) == mp.end()) return R ; else if (mp.find( G ) == mp.end()) return G ; else return B ; } int main() { int cnt = 0; string st; cin >> cnt >> st; cnt = 0; int i = 0; while (i + 2 < (st.size())) { if (st[i] == st[i + 1] && st[i] == st[i + 2]) st[i + 1] = getDiffColor(st[i], st[i]), cnt++; i++; } char pre = st[0]; for (int i = 0; i < st.size() - 1; i++) if (st[i] == st[i + 1]) st[i] = getDiffColor(pre, st[i]), pre = st[i], cnt++; else pre = st[i]; cout << cnt << n << st; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; t = 1; while (t--) { long long n, m; cin >> n; cin >> m; string s[n]; for (long long i = 0; i < n; i++) { string cur = ; for (long long i = 0; i < m; i++) { long long k; cin >> k; cur += to_string(k); } s[i] = cur; } if (n & 1) cout << n << endl; else { long long ans = n; while (n % 2 == 0) { n = n / 2; bool flag = 1; for (long long i = 0; i < n; i++) { if (s[i] != s[2 * n - i - 1]) { flag = 0; break; } } if (!flag) break; else ans = n; } cout << ans << endl; } } return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module sram_fifo #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter DEPTH = 21'h10_0000,
parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent
parameter FIFO_ALMOST_EMPTY_THRESHOLD = 5 // in percent
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [15:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
input wire USB_READ,
output wire [7:0] USB_DATA,
output wire FIFO_READ_NEXT_OUT,
input wire FIFO_EMPTY_IN,
input wire [31:0] FIFO_DATA,
output wire FIFO_NOT_EMPTY,
output wire FIFO_FULL,
output wire FIFO_NEAR_FULL,
output wire FIFO_READ_ERROR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
sram_fifo_core #(
.DEPTH(DEPTH),
.FIFO_ALMOST_FULL_THRESHOLD(FIFO_ALMOST_FULL_THRESHOLD),
.FIFO_ALMOST_EMPTY_THRESHOLD(FIFO_ALMOST_EMPTY_THRESHOLD)
) i_sram_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(USB_DATA),
.FIFO_READ_NEXT_OUT(FIFO_READ_NEXT_OUT),
.FIFO_EMPTY_IN(FIFO_EMPTY_IN),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR(FIFO_READ_ERROR)
);
endmodule
|
module grid_PWM(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_pwm_writedata,
output [31:0] avs_pwm_readdata,
input [2:0] avs_pwm_address,
input [3:0] avs_pwm_byteenable,
input avs_pwm_write,
input avs_pwm_read,
output avs_pwm_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
input [31:0] asi_fm_data,
input asi_fm_valid,
output asi_fm_ready,
input [31:0] asi_pm_data,
input asi_pm_valid,
output asi_pm_ready,
output coe_PWMOUT
);
assign avs_pwm_readdata = read_data;
assign avs_pwm_waitrequest = 1'b0;
assign asi_fm_ready = fm_ready;
assign asi_pm_ready = pm_ready;
assign coe_PWMOUT = (out_inv) ? ~pwm_out : pwm_out;
reg [31:0] read_data = 0;
reg out_inv = 0;
reg asi_gate_en = 0;
reg asi_dtyc_en = 0;
reg r_reset = 1;
reg [31:0] r_gate = 0;
reg [31:0] r_dtyc = 0;
/*
* GRID_MOD_SIZE 0x0
* GRID_MOD_ID 0x4
* PWM_CTRL 0x8
* PWM_PRD 0xC
* PWM_DTYC 0x10
*/
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_pwm_address)
0: read_data <= 32;
1: read_data <= 32'hEA680002;
2: read_data <= {7'b0, asi_gate_en, 7'b0, asi_dtyc_en, 7'b0, out_inv, 7'b0, r_reset};
3: read_data <= r_gate;
4: read_data <= r_dtyc;
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_inv <= 0;
asi_gate_en <= 0;
asi_dtyc_en <= 0;
r_reset <= 1;
r_gate <= 0;
r_dtyc <= 0;
end
else begin
if(avs_pwm_write) begin
case(avs_pwm_address)
2: begin
if(avs_pwm_byteenable[3]) asi_gate_en <= avs_pwm_writedata[24];
if(avs_pwm_byteenable[2]) asi_dtyc_en <= avs_pwm_writedata[16];
if(avs_pwm_byteenable[1]) out_inv <= avs_pwm_writedata[8];
if(avs_pwm_byteenable[0]) r_reset <= avs_pwm_writedata[0];
end
3: begin
if(avs_pwm_byteenable[3]) r_gate[31:24] <= avs_pwm_writedata[31:24];
if(avs_pwm_byteenable[2]) r_gate[23:16] <= avs_pwm_writedata[23:16];
if(avs_pwm_byteenable[1]) r_gate[15:8] <= avs_pwm_writedata[15:8];
if(avs_pwm_byteenable[0]) r_gate[7:0] <= avs_pwm_writedata[7:0];
end
4: begin
if(avs_pwm_byteenable[3]) r_dtyc[31:24] <= avs_pwm_writedata[31:24];
if(avs_pwm_byteenable[2]) r_dtyc[23:16] <= avs_pwm_writedata[23:16];
if(avs_pwm_byteenable[1]) r_dtyc[15:8] <= avs_pwm_writedata[15:8];
if(avs_pwm_byteenable[0]) r_dtyc[7:0] <= avs_pwm_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire pwm_reset, pwm_gate_reset, pwm_dtyc_reset;
reg [31:0] pwm_gate = 0;
reg [31:0] pwm_dtyc = 0;
reg [31:0] pwm_cnt = 0;
reg pwm_out = 0;
reg fm_ready = 0;
reg pm_ready = 0;
assign pwm_reset = rsi_PWMRST_reset | r_reset;
assign pwm_gate_reset = (asi_gate_en) ? rsi_PWMRST_reset : r_reset;
assign pwm_dtyc_reset = (asi_dtyc_en) ? rsi_PWMRST_reset : r_reset;
always@(posedge csi_PWMCLK_clk or posedge pwm_reset)
begin
if(pwm_reset) begin
pwm_cnt <= 0;
pwm_out <= 0;
end
else begin
if(pwm_cnt != pwm_gate) pwm_cnt <= pwm_cnt + 1; else pwm_cnt <= 0;
if(pwm_cnt < pwm_dtyc) pwm_out <= 0; else pwm_out <= 1;
end
end
always@(posedge csi_PWMCLK_clk or posedge pwm_gate_reset)
begin
if(pwm_gate_reset) begin
pwm_gate <= 0;
fm_ready <= 0;
end
else begin
if(asi_gate_en) begin
fm_ready <= 1;
if(asi_fm_valid) pwm_gate <= asi_fm_data;
end
else begin
fm_ready <= 0;
pwm_gate <= r_gate;
end
end
end
always@(posedge csi_PWMCLK_clk or posedge pwm_dtyc_reset)
begin
if(pwm_dtyc_reset) begin
pwm_dtyc <= 0;
pm_ready <= 0;
end
else begin
if(asi_dtyc_en) begin
pm_ready <= 1;
if(asi_pm_valid) pwm_dtyc <= asi_pm_data;
end
else begin
pm_ready <= 0;
pwm_dtyc <= r_dtyc;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[3010], id[3010], num[3010]; vector<int> ans; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } int m; scanf( %d , &m); int need = n - m; while (true) { int tot = 0; memset(id, -1, sizeof(id)); memset(num, 0, sizeof(num)); for (int i = 1; i <= n; i++) { if (id[i] == -1) { id[i] = tot; int now = a[i]; while (now != i) { id[now] = tot; now = a[now]; } tot++; } } for (int i = 1; i <= n; i++) { num[id[i]]++; } if (tot == need) break; if (tot > need) { for (int i = 2; i <= n; i++) { if (id[i] != id[1]) { ans.push_back(1); ans.push_back(i); swap(a[1], a[i]); break; } } } else { for (int i = 1; i <= n; i++) { if (num[id[i]] == 1) continue; for (int j = i + 1; j <= n; j++) { if (id[i] == id[j]) { ans.push_back(i); ans.push_back(j); swap(a[i], a[j]); break; } } break; } } } printf( %d n , ans.size() / 2); for (int i = 0; i < ans.size(); i++) { if (i) printf( ); printf( %d , ans[i]); } puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_SYMBOL_V
`define SKY130_FD_SC_HS__A41O_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 300100, maxv = 100, mod = 1e9 + 7, maxa = 1005, maxs = 820, maxb = 20, base = 737, base2 = 3079, mod3 = 998244353, delt = 10513; const long long inf = 2e16; const long long infint = 1e9 + 11; long long max(long long x, long long y) { return (x > y ? x : y); } long long min(long long x, long long y) { return (x < y ? x : y); } vector<long long> v[maxn]; long long dp[maxn][2]; bool visited[maxn]; long long ans = 0; void dfs(long long x) { visited[x] = 1; long long kid = v[x].size(); vector<long long> tmp; if (x != 0) { kid--; } for (auto u : v[x]) { if (!visited[u]) { dfs(u); ans = max(ans, dp[u][1] + 1); dp[x][0] = max(dp[x][0], dp[u][0] + kid); tmp.push_back(dp[u][0]); sort(tmp.begin(), tmp.end()); reverse(tmp.begin(), tmp.end()); if (tmp.size() > 2) { tmp.pop_back(); } } } dp[x][1] = dp[x][0]; if (tmp.size() == 2) { dp[x][1] = max(dp[x][1], tmp[0] + tmp[1] + kid - 1); } ans = max(ans, dp[x][1]); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long q; cin >> q; while (q--) { ans = 1; long long n; cin >> n; for (long long i = 0; i < n; i++) { visited[i] = 0; v[i].clear(); dp[i][0] = 1; dp[i][1] = 1; } for (long long i = 0; i < n - 1; i++) { long long a, b; cin >> a >> b; a--; b--; v[a].push_back(b); v[b].push_back(a); } dfs(0); cout << ans << endl; } return 0; }
|
/*
* Copyright (c) 2015 Steven Stallion
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
`timescale 1ns / 10ps
module clk_div(input reset,
input clk_in,
output reg clk_out);
reg [2:0] count;
always @(posedge clk_in) begin
if (!reset) begin
clk_out <= 1'b0;
count <= 3'b111;
end
else if (count == 5) begin
clk_out <= ~clk_out;
count <= 0;
end
else begin
count <= count + 1;
end
end
endmodule
|
/*
* Programing Notes:
1, there are four SPRs in uartlite, access using mtspr/mfspr instructions
2, the four register are:
control register
ctrl[0]: tx_start
ctrl[1]: rx_disenable
ctrl[2]: tx_interrupt_ebable - currently not in use
ctrl[3]: rx_interrupt_enable - currently not in use
ctrl[4]: interrupt status clear
Reset Status: 8'h00
bit[0]/[4] are auto-cleared when writing true-"1" into it.
status register - READ ONLY
sta[0]: transmitter status which 1 means transmitter is busy, 0 means transmitter is idle
sta[1]: receiver status which 1 means receiver is busy, 0 means receiver is idle
sta[2]: interrupt status which 1 mean interrupt status, 0 means normal status
sta[3]: transmitter interrupt status which means transmitter interrupt
sta[4]: receiver interrupt status which means receiver interrupt
receive data register
transmit data register
* Note:
1, there is no flow control, after received a byte, if second byte is coming, first byte is covered
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rst;
// uart inout
input rxd;
output txd;
// spr access interface
input [7:0] spr_dat_i;
input reg_txdata_we;
input reg_ctrl_we;
input reg_rxdata_we;
input reg_sta_we;
output [7:0] reg_txdata;
output [7:0] reg_ctrl;
output [7:0] reg_sta;
output [7:0] reg_rxdata;
// sram interface
output sram_ce;
output sram_we;
output [63:0] sram_wdata;
output [`IOCM_Word_BW-1:0] sram_addr;
// backdoor control
input download_enable;
//
// four internal SPRs for uartlite
//
reg [7:0] reg_ctrl;
reg [7:0] reg_sta;
reg [7:0] reg_txdata;
reg [7:0] reg_rxdata;
//
wire tx_start;
wire rx_enable;
reg tx_busy_d;
reg interrupt_tx;
reg interrupt_rx;
//
//
//
wire txd;
wire rxd;
wire [7:0] rx_data;
wire [7:0] rx_data_to_sram;
wire rx_data_rdy;
wire tx_busy;
wire rx_idle;
wire interrupt;
//
// SPR: control register
//
// [TBV]: coding style of auto-cleared
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_ctrl <= 8'h00;
else if(reg_ctrl[0]) // the tx_enable bit (ctrl[0]) will auto cleared after write 1
reg_ctrl[0] <= 1'b0;
else if(reg_ctrl_we)
reg_ctrl <= spr_dat_i;
else if(reg_ctrl[4]) // the int_clear bit (ctrl[4]) will auto cleared after write 1
reg_ctrl[4] <= 1'b0;
end
assign tx_start = reg_ctrl[0];
assign rx_enable = !reg_ctrl[1];
assign int_clear = reg_ctrl[4];
//
// SPR: status register
//
// tx interrupt detect
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
tx_busy_d <= 1'b0;
else
tx_busy_d <= tx_busy;
//when detect the negedge of tx_busy that means transmitter is finished
//if the tx_interrupt enable then generate interrupt of transmitter.
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_tx <= 1'b0;
else if(!tx_busy && tx_busy_d)
interrupt_tx <= 1'b1;
else if(int_clear)
interrupt_tx <= 1'b0;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_rx <= 1'b0;
else if(rx_data_rdy && rx_enable)
interrupt_rx <= 1'b1;
else if(int_clear)
interrupt_rx <= 1'b0;
assign interrupt = interrupt_rx || interrupt_tx;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
reg_sta <= 8'h00;
else if(reg_sta_we)
reg_sta <= spr_dat_i;
else
reg_sta <= {3'b000, interrupt_rx, interrupt_tx, interrupt, !rx_idle, tx_busy};
//
// SPR: receive data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_rxdata <= 8'h00;
else if(rx_data_rdy && rx_enable )
reg_rxdata <= rx_data;
end
//
// SPR: transmit data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_txdata <= 8'h00;
else if(reg_txdata_we)
reg_txdata <= spr_dat_i;
end
//
// transmitter and receiver
//
dsu_Tx tx(
.clk(clk),
.rst(rst),
.TxD_start(tx_start),
.TxD_data(reg_txdata),
.TxD(txd),
.TxD_busy(tx_busy)
);
dsu_Rx rx(
.clk(clk),
.rst(rst),
.RxD(rxd),
.RxD_data_ready(rx_data_rdy),
.RxD_data(rx_data),
.RxD_endofpacket(),
.RxD_idle(rx_idle)
);
//
// back door mode: burn sram using received data
//
assign rx_data_to_sram = download_enable ? rx_data : 8'h00;
dsu_sram_ctrl sram_ctrl(
.clk(clk),
.rst(rst),
.rxd(rx_data_to_sram),
.rxd_ready(rx_data_rdy && download_enable),
.sram_ce(sram_ce),
.sram_we(sram_we),
.sram_addr(sram_addr),
.sram_wdata(sram_wdata),
.download_enable(download_enable)
);
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:42 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_2_stub.v
// Design : gcd_block_design_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/*
* data_ram.v
* Synchronous RAM module used for data storage
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module data_ram(data_out, clk, address, data_in, write);
// Width of data values stored
parameter DATA_WIDTH = 8;
// Width of addresses (max stack size = 2^ADDR_WIDTH)
parameter ADDR_WIDTH = 15;
// True to initialize RAM in an initial block
// This can be disabled for synthesis when it is very slow and unnessesary
parameter INIT_RAM = 1;
// Inputs and outputs
output [DATA_WIDTH - 1:0] data_out; // Data currently at the given address
input clk; // Clock
input [ADDR_WIDTH - 1:0] address; // Address of the byte in use
input [DATA_WIDTH - 1:0] data_in; // Incoming data
input write; // If high, writes on a clock edge
// The RAM storage and output buffer
reg [DATA_WIDTH - 1:0] data[0:(1 << ADDR_WIDTH) - 1];
reg [DATA_WIDTH - 1:0] output_buffer;
// View of the output buffer
assign data_out = output_buffer;
// RAM initialization
integer i;
initial
begin
output_buffer = 0;
if (INIT_RAM)
begin
for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1)
data[i] = 0;
end
end
// RAM update code
always @(posedge clk)
begin
if (write)
begin
data[address] <= data_in;
output_buffer <= data_in;
end
else
begin
output_buffer <= data[address];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, max1 = 0; cin >> n; long long int a[n]; long long int b[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } b[n - 1] = 0; max1 = a[n - 1]; for (int i = n - 2; i >= 0; i--) { if (a[i] > max1) { b[i] = 0; max1 = a[i]; } else { b[i] = max1 - a[i] + 1; } } for (int i = 0; i < n; i++) cout << b[i] << ; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef enum {TEN=10,
ELEVEN=11,
SIXTEEN=16} enum_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
int i;
int i_const;
int cyc;
enum_t en;
// Constant propagation tests
initial begin
en = SIXTEEN;
i_const = $cast(en, 1);
if (i_const != 0) $stop;
if (en != SIXTEEN) $stop;
en = SIXTEEN;
i_const = $cast(en, 10);
if (i_const != 1) $stop;
if (en != TEN) $stop;
end
// Test loop
always @ (posedge clk) begin
i = $cast(en, cyc);
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en);
`endif
cyc <= cyc + 1;
if (cyc == 10) begin
if (i != 1) $stop;
if (en != TEN) $stop;
end
else if (cyc == 11) begin
if (i != 1) $stop;
if (en != ELEVEN) $stop;
end
else if (cyc == 12) begin
if (i != 0) $stop;
if (en != ELEVEN) $stop;
end
else if (cyc == 16) begin
if (i != 1) $stop;
if (en != SIXTEEN) $stop;
end
else if (cyc == 17) begin
if (i != 0) $stop;
if (en != SIXTEEN) $stop;
end
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter [31:0] TWENTY4 = 24;
parameter [31:0] PA = TWENTY4/8;
parameter [1:0] VALUE = 2'b10;
parameter [5:0] REPL = {PA{VALUE}};
parameter [7:0] CONC = {REPL,VALUE};
parameter DBITS = 32;
parameter INIT_BYTE = 8'h1F;
parameter DWORDS_LOG2 = 7;
parameter DWORDS = (1<<DWORDS_LOG2);
parameter DBYTES=DBITS/8;
// verilator lint_off LITENDIAN
reg [DBITS-1:0] mem [0:DWORDS-1];
// verilator lint_on LITENDIAN
integer i;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (REPL != {2'b10,2'b10,2'b10}) $stop;
if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop;
end
if (cyc==2) begin
for (i = 0; i < DWORDS; i = i + 1)
mem[i] = {DBYTES{INIT_BYTE}};
end
if (cyc==3) begin
for (i = 0; i < DWORDS; i = i + 1)
if (mem[i] != {DBYTES{INIT_BYTE}}) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - time3.v - Verify glitch doesn't propagate with non-blocking
//
// D:
module main ();
reg a;
reg error;
wire c;
reg d;
assign c = a;
always @(c)
#5 d <= c;
always @(posedge d)
error <= 1'b1;
initial
begin
/*
$dumpfile("/root/testsuite/dump.vcd");
$dumpvars(0,main);
$dumpon;
*/
a =1'b0;
error = 1'b0;
#10;
a = 1'b1;
# 3;
a = 1'b0;
# 10;
if(error)
$display("FAILED");
else
$display("PASSED");
#5;
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:06:24 05/25/2014
// Design Name: qdiv
// Module Name: D:/temp/TestDiv1/TestDiv.v
// Project Name: TestDiv1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestDiv;
// Inputs
reg [63:0] i_dividend;
reg [63:0] i_divisor;
reg i_start;
reg i_clk;
reg [13:0] count;
reg [8:0] temp_divisor;
reg [8:0] temp_dividend;
// Outputs
wire [63:0] o_quotient_out;
wire o_complete;
wire o_overflow;
// Instantiate the Unit Under Test (UUT)
qdiv #(32,64) uut (
.i_dividend(i_dividend),
.i_divisor(i_divisor),
.i_start(i_start),
.i_clk(i_clk),
.o_quotient_out(o_quotient_out),
.o_complete(o_complete),
.o_overflow(o_overflow)
);
initial begin
// Initialize Inputs
i_dividend = 0;
i_divisor = 0;
i_start = 0;
i_clk = 0;
count = 0;
temp_divisor = 0;
temp_dividend = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 i_clk = ~i_clk;
end
end
always @(posedge i_clk) begin
if (count == 1) begin
i_start <= 1;
end
if (count == 3) begin
i_start <= 0;
end
if (count == 220) begin
count = 0; // reset the count
if (temp_divisor > 255) begin // if divisor maxed;
temp_divisor <= 0; // reset to zero
temp_dividend <= temp_dividend + 1; // and increment dividend
end
else begin
temp_divisor <= temp_divisor + 1; // otherwise, increment divisor
end
i_dividend <= temp_dividend << 32; // Set i_dividend
i_divisor <= temp_divisor << 32; // Set i_dividor
end
count <= count + 1; // Update count
end
always @(posedge o_complete) begin
$display ("%b,%b,%b,%b", i_dividend, i_divisor, o_quotient_out, o_overflow);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long fact[3000002], n, inv[3000002]; long long pw(long long b, long long e) { long long ans = 1; while (e) { if (e & 1) ans = (ans * b) % 1000000007; b = (b * b) % 1000000007; e >>= 1; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; ++n; fact[0] = inv[0] = 1; for (int i = 1; i <= 2500000; ++i) { fact[i] = (fact[i - 1] * i) % 1000000007; inv[i] = pw(fact[i], 1000000007 - 2); } long long ans = 2LL * fact[2 * n - 1] * inv[n]; ans %= 1000000007; ans = ans * inv[n - 1]; ans %= 1000000007; cout << (ans - 1 + 1000000007) % 1000000007; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverydEe_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 1;
parameter AWIDTH = 13;
parameter MEM_SIZE = 7500;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverydEe_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverydEe(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd7500;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
contact_discoverydEe_ram contact_discoverydEe_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of Instruction cache data rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_ram(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we[0]),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
// file: Clock70MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock70MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70MHz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e5 + 10; struct node { int l, r, id; friend bool operator<(node A, node B) { return A.r == B.r ? A.l < B.l : A.r < B.r; } }; node a[N]; bool add[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ll n, m; ; cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> a[i].l >> a[i].r; a[i].id = i; } sort(a + 1, a + 1 + n); multiset<int> b; for (int i = 0; i < m; ++i) b.insert(0); for (int i = 1; i <= n; ++i) { auto p = b.lower_bound(a[i].l); if (p != b.begin()) { add[a[i].id] = 1; --p; b.erase(p); b.insert(a[i].r); } } vector<int> ans; for (int i = 1; i <= n; ++i) if (!add[i]) ans.emplace_back(i); cout << ans.size() << endl; for (auto i : ans) cout << i << ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007ll; const long long int MOD = 1000000009ll; int local_debug = 0; long long int bit_count(long long int _x) { long long int _ret = 0; while (_x) { if (_x % 2 == 1) _ret++; _x /= 2; } return _ret; } long long int bit(long long int _mask, long long int _i) { long long int x = 1; return (_mask & (x << _i)) == 0 ? 0 : 1; } long long int powermod(long long int _a, long long int _b, long long int _m = mod) { long long int _r = 1; while (_b) { if (_b % 2 == 1) _r = (_r * _a) % _m; _b /= 2; _a = (_a * _a) % _m; } return _r; } long long int power(long long int _a, long long int _b) { long long int _r = 1; while (_b) { if (_b % 2 == 1) _r = (_r * _a); _b /= 2; _a = (_a * _a); } return _r; } long long int add(long long int a, long long int b, long long int m = mod) { a %= m; b %= m; long long int x = a + b; while (x >= m) x -= m; return x; } long long int sub(long long int a, long long int b, long long int m = mod) { long long int x = a - b; while (x < 0) x += m; return x; } long long int mul(long long int a, long long int b, long long int m = mod) { a %= m; b %= m; long long int x = a * b; x %= m; return x; } long long int gcd(long long int a, long long int b) { if (a < b) { a = a ^ b; b = a ^ b; a = a ^ b; } if (b == 0) return a; long long int t; while (b) { t = b; b = a % b; a = t; } return a; } long long int lcm(long long int a, long long int b) { return (a * b) / gcd(a, b); } long long int maxSubArraySum(vector<long long int> a, long long int size) { long long int max_so_far = a[0]; long long int curr_max = a[0]; for (long long int i = 1; i < size; i++) { curr_max = max(a[i], curr_max + a[i]); max_so_far = max(max_so_far, curr_max); } return max_so_far; } int main() { long long int n; scanf( %lld , &n); ; vector<long long> hrr(n); vector<long long> grr(n); for (int i = 0; i < n; i++) { scanf( %lld , &hrr[i]); ; scanf( %lld , &grr[i]); ; } int count = 0; for (int i = 0; i < n; i++) { for (int j = 0; j <= n; j++) { if (hrr[i] == grr[j]) { count++; } } } cout << count << endl; return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( -ffloat-store ) using namespace std; clock_t time_p = clock(); void aryanc403() { time_p = clock() - time_p; cerr << Time Taken : << (float)(time_p) / CLOCKS_PER_SEC << n ; } const long long int INF = 0xFFFFFFFFFFFFFFFL; long long int seed; mt19937 rng(seed = chrono::steady_clock::now().time_since_epoch().count()); inline long long int rnd(long long int l = 0, long long int r = INF) { return uniform_int_distribution<long long int>(l, r)(rng); } class CMP { public: bool operator()(pair<long long int, long long int> a, pair<long long int, long long int> b) { return !(a.second < b.second || (a.second == b.second && a.first >= b.first)); } }; void add(map<long long int, long long int> &m, long long int x, long long int cnt = 1) { auto jt = m.find(x); if (jt == m.end()) m.insert({x, cnt}); else jt->second += cnt; } void del(map<long long int, long long int> &m, long long int x, long long int cnt = 1) { auto jt = m.find(x); if (jt->second <= cnt) m.erase(jt); else jt->second -= cnt; } bool cmp(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return a.first < b.first || (a.first == b.first && a.second < b.second); } const long long int mod = 1000000007L; const long long int maxN = 100000L; long long int T, n, i, j, k, in, cnt, l, r, u, v, x, y, ans; long long int m; string s; vector<pair<long long int, long long int> > a, e[maxN + 5]; long long int d[maxN + 5]; priority_queue<pair<long long int, long long int>, vector<pair<long long int, long long int> >, CMP> pq; int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); { cin >> n >> m >> k; a.clear(); a.reserve(k); for (i = 0; i < (m); ++i) { cin >> x >> y >> in; e[x].push_back({y, in}); e[y].push_back({x, in}); } for (i = (1); i <= (n); ++i) d[i] = INF; d[1] = 0; for (i = 0; i < (k); ++i) { cin >> x >> in; a.push_back({x, in}); pq.push({-x, in}); } for (auto x : e[1]) pq.push({x.first, x.second}); while (!pq.empty()) { auto z = pq.top(); pq.pop(); long long int u = abs(z.first); if (d[u] <= z.second) { ans += (z.first < 0); if (z.first < 0) ; continue; } d[u] = z.second; for (auto x : e[u]) pq.push({x.first, x.second + z.second}); } cout << ans << n ; } aryanc403(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_BLACKBOX_V
`define SKY130_FD_SC_HD__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 105; long long l, r, dp[N]; long long gao(long long n) { long long m = n, ans = 0; int bit[N], len = 0; while (n) { bit[++len] = n % 2; n /= 2; } for (int i = 2; i < len; i++) { memset(dp, 0, sizeof(dp)); dp[1] = 1; for (int j = 2; j < i; j++) { if (i % j) continue; dp[j] += 1LL << (j - 1); } for (int j = 1; j <= i; j++) { for (int k = 2; k * j < i; k++) if (i % (k * j) == 0) dp[j * k] -= dp[j]; } for (int j = 1; j <= i; j++) ans += dp[j]; } for (int i = len; i <= len; i++) { memset(dp, 0, sizeof(dp)); for (int j = 1; j < i; j++) { if (i % j) continue; for (int k = len; k > len - j; k--) { if (k != len && bit[k] == 1) { dp[j] += 1LL << (k - (len - j) - 1); } } long long sum = 0; for (int k = len; k > len - j; k--) { if (bit[k] == 0) continue; for (int r = k; r > 0; r -= j) { sum += 1LL << (r - 1); } } if (sum <= m) dp[j]++; } for (int j = 1; j <= i; j++) { for (int k = 2; k * j < i; k++) if (i % (k * j) == 0) dp[j * k] -= dp[j]; } for (int j = 1; j <= i; j++) ans += dp[j]; } return ans; } int main() { while (cin >> l >> r) { cout << gao(r) - gao(l - 1) << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n], b[n]; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; int ans = 0; for (int i = 0; i < n; ++i) { int x = a[i], y = b[i]; ans = max(ans, x + y); for (int j = i + 1; j < n; ++j) { x |= a[j]; y |= b[j]; ans = max(ans, x + y); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; struct Edge { int from, to, w; } edges[maxn]; int val[maxn]; long long ans; int size[maxn], fa[maxn]; bool cmp(Edge a, Edge b) { return a.w > b.w; } int Getfa(int x) { if (fa[x] == x) return x; else return fa[x] = Getfa(fa[x]); } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) scanf( %d , &val[i]); for (int i = 1; i <= m; ++i) { int u, v; scanf( %d %d , &u, &v); edges[i].from = u, edges[i].to = v; edges[i].w = min(val[u], val[v]); } sort(edges + 1, edges + 1 + m, cmp); for (int i = 1; i <= n; ++i) size[i] = 1, fa[i] = i; ans = 0; for (int i = 1; i <= m; ++i) { int u = edges[i].from, v = edges[i].to; int fx = Getfa(u), fy = Getfa(v); if (fx == fy) continue; ans += (long long)size[fx] * size[fy] * edges[i].w; fa[fx] = fy; size[fy] += size[fx]; } printf( %.6lf n , (double)2.0 * ans / n / (n - 1)); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FAH_PP_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j; char map[9][9]; bool ok = false, ok1 = false; for (i = 0; i < 8; ++i) { scanf( %s , map[i]); for (j = 1; j < 8; ++j) { if (i == 0 && map[i][j] == W ) ok1 = true; if (map[i][j] == map[i][j - 1]) ok = true; } if (i == 0 && map[i][0] == W ) ok1 = true; if (map[i][0] == map[i][7]) ok = true; } if (!ok1 || ok) puts( NO ); else puts( YES ); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by engr248.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] in = 0;
wire [31:0] out;
Test test(
.out(out[31:0]),
.clk(clk),
.in (in[31:0])
);
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
interface Intf ();
endinterface
module Select
#(
parameter int NUM_MASTER = 1
)
(
Intf Upstream,
Intf Downstream[NUM_MASTER]
);
endmodule
module Crossbar
#(
parameter int NUM_MASTER = 1,
parameter int NUM_SLAVE = 1
)
(
Intf Masters[NUM_MASTER]
);
Intf selectOut[(NUM_MASTER * (NUM_SLAVE+1))-1 : 0]();
genvar i;
for (i = 0; i < NUM_MASTER; i = i + 1) begin
Select #(
.NUM_MASTER(NUM_SLAVE+1)
)
select_inst (
.Upstream(Masters[i]),
// Following line triggered the dearrayAll segfault
.Downstream(selectOut[(i+1)*(NUM_SLAVE+1) - 1 : i*(NUM_SLAVE+1)])
);
end
endmodule
module Test
(
input clk,
input [31:0] in,
output reg [31:0] out
);
always @(posedge clk) begin
out <= in;
end
Intf MST[2](); //MST must have >1 array size to trigger dearrayAll segfault
Crossbar #(
.NUM_MASTER(2),
.NUM_SLAVE(1)
)
xbar_inst (
.Masters(MST)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; long long c[N], d[N]; int main() { long long sum = 0, ans = 0; int n, k; scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %lld , &c[i]); sum += c[i]; } for (int i = 1; i <= k; i++) { scanf( %lld , &d[i]); sum -= c[d[i]]; ans += sum * c[d[i]]; c[d[i]] = 0; } for (int i = 2; i <= n; i++) { ans += c[i] * c[i - 1]; } ans += c[1] * c[n]; printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, x, y, a, b; int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> t; while (t--) { cin >> x >> y >> a >> b; int tmp = (y - x) / (a + b); if (x + tmp * a == y - tmp * b) cout << tmp << n ; else cout << -1 << n ; } return 0; }
|
module counter_n (clk,sig,n_clk_out);
/*This module takes an input signal and implements a period counter,
taking the reciprocal to deliver the frequency in kHz.
USAGE:
counter c(clk,sig,f);
clk and sig are 1-bit inputs representing the clock and RF signal whose frequency
is to be measured.
f is a 4-bit output corresponding to the frequency of sig, IN UNITS OF HUNDREDS
OF Hz. This is because hundreds of Hz is the highest requeired frequency
resolution, and we want to use integer arithmetic.
Reference: Agilent Technologies. "Fundamentals of the Electronic Counters".
Application Note 200, Electronic Counter Series.
Design notes:
In a period counter, pulses of the clock are counted in a register, with the
totaling (counting) action gated by pulses from the RF input whose frequency
is being measured. Averaging over multiple RF cycles reduces error.
The total time elapsed between RF edges will be
n_clk*tau_c+err = m/f
=>f= m/(n_clk*tau_c+err)
where tau_c is the clock period, n_clk is the number of clock cycles actually counted
by the register, err is the error in the time estimate, m is the number of RF
positive edges, and f is the RF frequency.
Contributions to error include the +-1 count error, timebase deviations, etc.
The +-1 count error, or quantization error, arises because time is only measured
in discrete steps, and a measurement of four clock time units may be produced by
RF pulses which are acutally separated by 3+delta or 5-delta clock units.
The nominal frequency estimate
f_nominal=m/(n_clk*tau_c)
converges with the value that would arise from an average after many cycles
if n_clk is very large.
With just the +-1 count error, the spread in maximum and minimum possible
frequency estimates
fmax-fmin=m/tau_c*(1/(n_clk-1)-1/(n_clk+1))=2*m/tau_c * 1/(n_clk^2-1) ~= 2*f_nom^2*tau_c/m
=2*f_nom^2/(f_clk*m)
The error increases with frequency for a fixed number of RF pulses, but decreases
as the clock frequency increases and as the number of RF pulses averaged over
increases.
We require about 3 kHz resolution at the highest frequencies (around 300 kHz)
and about 500 Hz resolution at the lowest frequencies - these values are about
half the frequency interval between adjacent bins in these sub-bands. With
a clock speed of 4 MHz,
m=2*f_high^2/(f_clk*Delta_f_high)=2*(3E5^2)/(4E6*3E3)=18E10/(12E9)=15
with m=15, at the lower frequencies,
fmax-fmin=2*5E4^2/(4E6*15) = Delta_f_high/36 ~= 83 Hz
while m/5E4=15/5E4=3.0E-4=300 us is the maximum time elapsed per measurement.
At high frequency, Delta_t = m/300E3=50 us.
Since we are willing to accept a reaction time on the order of 1 ms, we can
actually improve accuracy by increasing m such that Delta_t_max = 1 ms = m/5E4
=>m=50.
So choose m=50, which gives fmax-fmin~=900 Hz at f_rf=300 kHz.
f_nom = m*f_clk/n_clk => n_clk = m*f_clk/f_nom,
n_clk_max=50*4E6/5E4=80E2=4000
=>n_clk needs to be at least 12 bits. Make 13.
13 Jan 2012
In general, the phase of clk edges relative sig edges will change. Some phases produce floor(M*tau_s/tau_c) clock counts, while others produce floor(M*tau_s/tau_c)+1 clock counts. This results in a jitter in n_clk. By itself, this might not be so bad, but when many bits are changing (since we are not using a Gray code), this can be problematic. Further, in practice, the spread in clock counts seems to reach +0+2, instead of +0+1.
The fix implemented is to compare the value of n_clk at the 50th sig interval to the value of n_clk used in the last frequency calculation. If the absolute value of the difference is larger than MIN_CHANGE=2, then the frequency is re-computed. Otherwise, the frequency is not changed. This seems to take care of the jitter.
//Error (10239): Verilog HDL Always Construct error at counter.v(102): event control cannot test for both positive and negative edges of variable "clk"
*/
parameter CLK_COUNTER_SIZE=14; //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 7 //Number of bits in signal edge counter.
input clk,sig;
output reg [CLK_COUNTER_SIZE-1:0] n_clk_out; //Output clock counts.
reg [13:0] n_clk; //Register to hold number of clock counts between RF signal.
reg [13:0] n_clk_last; //Holds value of n_clk used in the last frequency computation. Compared with current value to determine whether frequency should be recomputed.
reg [6:0] n_sig; //Register to count the number of RF cycles.
reg cnt_flg; //Counter flag.
reg reset; //Internal flag to reset clock counter.
//Clock frequency in hundreds of Hz.
parameter F_CLK=40000;
//parameter F_CLK=35795; //This clock was used to test whether incorrect firing of state happens at different frequencies depending on clock frequency and precession of this with sync signal freq.
//Number of cycles of RF signal over which to average period.
parameter M=50;
//Define macros to set counter sizes for convenience (so that don't have to make multiple changes if counter size needs to be adjusted).
parameter MIN_CHANGE=2'b10; //n_clk must change by at least this amount (up or down) from last n_clk in order for a change in computed frequency to be allowed.
initial begin
#0
n_clk=1'b0; //Initialize clock edge counter.
n_sig=1'b0; //RF Cycle counter.
reset=1'b1; //Initialize reset flag to block clock counter until signal counter gate opens.
n_clk_last=1'b0;
cnt_flg=0;
end
//Clock loop
//always @(posedge clk) begin //Triggering on reset was there in case there were two sig edges before the next clk edge, in which case the reset call would get skipped. But maybe false triggers are causing clock count to drift or flicker. Remove this edge detector and see what happens. Result - no, that didn't fix the problem.
always @(posedge clk or posedge reset) begin
if (reset) begin
n_clk=1'b0; //Reset clk counter.
end else begin
n_clk=n_clk+1'b1; //Increment clk counter.
end
end
//Gate on positive edges of signal
always @(posedge sig) begin
//Initially, the gate is closed and n_sig=0.
//When the gate is opened, n_sig is incremented, so n_sig=1.
//The gate is closed again at the (M+1)th positive edge on n_sig, but before n_sig is incremented,
//so n_sig=M still.
//As such, the gate is open between the 1st and (M+1)th positive edges of n_sig, corresponding to M sig intervals.
//The gate is closed between the (M+1)th=0th and 1st signal edges.
//THEN dt = (M)*tau_sig = (M)/f_sig = (n_clk-1+[-0+2])/f_clk
//It is n_clk-1 because this is the number of clock time intervals in n_clk positive edges.
// [-0+2]=error on time measurement - time is at least (n_clk-1)*tau_c, but could be as much as
// (n_clk-1+2-delta)*tau_c, so on average, elapsed time is actually (n_clk-1 - (average error = (0+2)/2=1))*tau_c
// => f_sig = f_clk * (M)/(n_clk-1-(0+2)/2) = f_clk * (M)/n_clk
if (n_sig==M) begin //This is actually the M+1th edge, and the Mth interval
//After M sig edges and n_clk clock edges,
//Handle case where n_clk=0 by saturating frequency at f=M*F_CLK.
if(n_clk==1'b0) n_clk_out=n_clk; //Case where no counts on clock are registered.
//Disallow jitter from changes in n_clk by +-2; only update frequency
//when clock counter is different by a number other than +-MIN_CHANGE.
else if ((n_clk>n_clk_last && n_clk-n_clk_last>MIN_CHANGE) || ( n_clk_last>n_clk && n_clk_last-n_clk>MIN_CHANGE) ) begin
n_clk_last=n_clk; //Store clock counter at last frequency change.
n_clk_out=n_clk; //Re-compute RF frequency.
end
n_sig=1'b0; //Zero out rf cycle counter.
reset=1'b1; //Set reset flag high to restart clock counter.
end else begin //Start incrementing signal positive edge counter.
reset=1'b0; //Set reset low and start counting clock cycles again.
n_sig=n_sig+1'b1; //Increment RF cycle counter.
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:05:44 03/13/2014
// Design Name:
// Module Name: Longest_Run_of_Ones
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// m-files: longest_run_of_ones.m, longest_run_of_ones_limits.m
//
//////////////////////////////////////////////////////////////////////////////////
module Longest_Run_of_Ones(
input wire clk,
input wire rst,
input wire rand,
output wire pass
);
parameter n = 16, M = 8, k = 3, U = 448018; // U is multiplied by 1024
reg [7:0] count_bits0, count_bits1, count_bits2;
reg [4:0] count_blocks, v0, v1, v2, v3;
reg [2:0] count_run, count_run_max;
wire [20:0] chi_sqr;
/*maximum possibel value of chi_sqr calculated as ((16^2)/0.1875)
16 is the maximum possible value of Vi, where all other Vjs are 0. (x+y)^2 > x^2 + y^2, for x, y > 0
0.1875 is the minimum value from the pi table.
10 more bits are added as we multiply chi_sqr by 1024 to increase precision*/
wire en0;
reg en1, en2;
assign en0 = (count_blocks == 0);
calculate_chi_sqr calculate_chi_sqr1(
.v0(v0), .v1(v1), .v2(v2), .v3(v3),
.en(en2 & en0),
.chi_sqr(chi_sqr)
);
assign pass = (chi_sqr < U);
always @(posedge clk)
if (rst) begin // initialize
count_bits0 <= 8'HFF;
count_bits1 <= 8'H00;
count_bits2 <= 8'H00;
count_blocks <= 0;
count_run <= 0;
count_run_max <= 0;
v0 <= 0;
v1 <= 0;
v2 <= 0;
v3 <= 0;
en1 <= 0;
en2 <= 0;
end
else begin
en1 <= en0;
en2 <= en1;
count_bits0 <= count_bits0 + 1;
if (count_bits0 == (M-1)) begin
count_bits0 <= 0;
count_blocks <= count_blocks + 1;
if (count_blocks == (n-1)) begin
count_blocks <= 0;
end
end
count_bits1 <= count_bits0;
count_bits2 <= count_bits1;
if (rand) begin
if (count_bits0) count_run <= count_run + 1;
else count_run <= 1;
end
else begin
count_run <= 0;
if (count_run > count_run_max) count_run_max <= count_run;
end
if (count_bits1 == (M-1))
if (count_run > count_run_max) count_run_max <= count_run;
if (count_bits2 == (M-1)) begin
count_run_max <= 0;
case(count_run_max)
0: v0 <= v0 + 1;
1: v0 <= v0 + 1;
2: v1 <= v1 + 1;
3: v2 <= v2 + 1;
4: v3 <= v3 + 1;
5: v3 <= v3 + 1;
6: v3 <= v3 + 1;
7: v3 <= v3 + 1;
8: v3 <= v3 + 1;
endcase
end
if ((en1) & (~en0)) begin
v0 <= 0;
v1 <= 0;
v2 <= 0;
v3 <= 0;
end
end
endmodule
module calculate_chi_sqr(
input wire [4:0] v0, v1, v2, v3,
input wire en,
output wire [20:0] chi_sqr
);
(* KEEP = "TRUE" *) (* S = "TRUE" *)
reg [9:0] v0_sqr, v1_sqr, v2_sqr, v3_sqr;
/*
(1024/pi) =
12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 1 0 1 0 0 1 1 1 1 1
0 1 0 1 0 1 1 1 0 0 1 0 0
1 0 0 0 1 0 1 0 1 1 0 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1
*/
assign chi_sqr = (v0_sqr<<0) + (v0_sqr<<1) + (v0_sqr<<2) + (v0_sqr<<3) + (v0_sqr<<4) + (v0_sqr<<7) + (v0_sqr<<9) + (v0_sqr<<12)
+ (v1_sqr<<2) + (v1_sqr<<5) + (v1_sqr<<6) + (v1_sqr<<7) + (v1_sqr<<9) + (v1_sqr<<11)
+ (v2_sqr<<1) + (v2_sqr<<3) + (v2_sqr<<4) + (v2_sqr<<6) + (v2_sqr<<8) + (v2_sqr<<12)
+ (v3_sqr<<0) + (v3_sqr<<2) + (v3_sqr<<4) + (v3_sqr<<6) + (v3_sqr<<8) + (v3_sqr<<10) + (v3_sqr<<12);
always @(*)
if (en) begin
v0_sqr <= v0 * v0;
v1_sqr <= v1 * v1;
v2_sqr <= v2 * v2;
v3_sqr <= v3 * v3;
end
endmodule
|
#include <bits/stdc++.h> template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } constexpr long long MAX = 5100000; constexpr long long INF = 1LL << 60; constexpr int inf = 1 << 28; using namespace std; int main() { int n; scanf( %d , &n); vector<long long> a(n); for (int i = 0; i < n; i++) scanf( %lld , &a[i]); vector<pair<long long, long long>> vp; for (int i = 0; i < n; i++) { vp.emplace_back(a[i], 1); while (vp.size() >= 2) { auto s = vp.back(); vp.pop_back(); auto f = vp.back(); vp.pop_back(); if (f.second * (f.first + s.first) < f.first * (f.second + s.second)) { vp.emplace_back(f.first + s.first, f.second + s.second); } else { vp.emplace_back(f); vp.emplace_back(s); break; } } } for (int i = 0; i < vp.size(); i++) { auto p = vp[i]; for (int j = 0; j < p.second; j++) { printf( %.12f n , (double)p.first / p.second); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; void solve(void) { string a, b, c; cin >> a >> b >> c; int n = a.length(); for (int i = 0; i < n; i++) { if (c[i] != a[i] && c[i] != b[i]) { cout << NO n ; return; } } cout << YES n ; } int main(void) { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, i, k, j, lg, el, maxi, ok2; int ok[5010][5010]; char v[5010], sol[5010]; int main() { cin >> t; for (; t--;) { cin >> v + 1; n = strlen(v + 1); int st = 1, dr = n; while (st <= dr && v[st] == v[dr]) st++, dr--; if (st > dr) { cout << v + 1 << n ; continue; } for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) ok[i][j] = 0; for (i = 1; i <= n; ++i) { ok[i][i] = 1; if (i < n && v[i] == v[i + 1]) ok[i][i + 1] = 1; } for (lg = 3; lg <= n; ++lg) { for (i = 1; i + lg - 1 <= n; ++i) { j = i + lg - 1; if (ok[i + 1][j - 1] && v[i] == v[j]) ok[i][j] = 1; } } maxi = 0; for (i = 1; i <= n; i++) { if (ok[1][i] && i > maxi) { maxi = i; for (j = 1; j <= i; j++) sol[j] = v[j]; } if (ok[i][n] && (n - i + 1) > maxi) { maxi = n - i + 1; for (j = i; j <= n; j++) sol[j - i + 1] = v[j]; } } dr = n; for (i = 1; i <= n; i++) { st = 1, ok2 = 0; for (j = n; j >= n - i + 1 && j > i; j--) { if (v[st] != v[j]) { ok2 = 1; break; } st++; } if (j == n) continue; if (st != i + 1) { int nr = n - j; if (2 * nr > maxi) { maxi = 2 * nr, el = 0; for (j = 1; j <= nr; j++) sol[++el] = v[j]; for (j = n - nr + 1; j <= n; j++) sol[++el] = v[j]; } if (ok[nr + 1][i]) { if (i + nr > maxi) { maxi = i + nr, el = 0; for (j = 1; j <= i; j++) sol[++el] = v[j]; for (j = n - nr + 1; j <= n; j++) sol[++el] = v[j]; } } } else { for (j = i + 1; j <= n - i; j++) { if (ok[j][n - i]) break; } int lg = n - i - j + 1; if (2 * i + lg > maxi) { maxi = 2 * i + lg, el = 0; for (k = 1; k <= i; k++) sol[++el] = v[k]; for (k = j; k <= n; k++) sol[++el] = v[k]; } } } for (i = 1; i <= maxi; i++) cout << sol[i]; cout << n ; } return 0; }
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for cam_bram
*/
module test_cam_bram;
// Parameters
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 5;
parameter SLICE_WIDTH = 9;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] write_addr = 0;
reg [DATA_WIDTH-1:0] write_data = 0;
reg write_delete = 0;
reg write_enable = 0;
reg [DATA_WIDTH-1:0] compare_data = 0;
// Outputs
wire write_busy;
wire [2**ADDR_WIDTH-1:0] match_many;
wire [2**ADDR_WIDTH-1:0] match_single;
wire [ADDR_WIDTH-1:0] match_addr;
wire match;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
write_addr,
write_data,
write_delete,
write_enable,
compare_data
);
$to_myhdl(
write_busy,
match_many,
match_single,
match_addr,
match
);
// dump file
$dumpfile("test_cam_bram.lxt");
$dumpvars(0, test_cam_bram);
end
cam_bram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using db = double; using pii = pair<int, int>; using pll = pair<ll, ll>; const int N = 2e5 + 10; const ll inf = 1e15 + 42; vector<vector<int> > g(100007); int flg, root, cnt; vector<int> ans; void dfs(int u, int par) { if (flg) return; int val = 0; for (int v : g[u]) { if (v != par) { val++; dfs(v, u); } } if (val == 2 && u == 1) { return; } if (val > 1 && cnt == 0) { cnt++; root = u; } else if (val > 1) { flg = 1; } } void dfs1(int u, int par) { int ok = 1; for (int v : g[u]) { if (v != par) { ok = 0; dfs1(v, u); } } if (ok) ans.push_back(u); } void testCase() { int n; cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } dfs(1, -1); if (flg == 1) { cout << No << n ; return; } if (root == 0) root = 1; dfs1(root, -1); cout << Yes << n ; cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) cout << root << << ans[i] << n ; } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); testCase(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int tc; cin >> tc; while (tc--) { int test = 0; int t[1005]; int n, x, nb1 = 0, nb2 = 0, i; cin >> n >> x; for (i = 0; i < n; i++) { cin >> t[i]; if (t[i] % 2 == 0) nb1++; else nb2++; } if (nb1 > 0 && x - nb1 > 0 && nb2 >= x - nb1 && (x - nb1) % 2 != 0) cout << Yes << endl; else if (nb1 > 0 && x - nb1 + 1 > 0 && nb2 >= x - nb1 + 1 && (x - nb1 + 1) % 2 != 0) cout << Yes << endl; else if (nb1 > 0 && x - nb1 <= 0 && nb2 >= 1) cout << Yes << endl; else if (nb1 == 0 && x % 2 != 0 && nb2 >= x) cout << Yes << endl; else cout << No << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int base = 998244353; int sum(int a, int b) { int c = a + b; if (c >= base) return c - base; return c; } int diff(int a, int b) { int c = a - b; if (c < 0) return c + base; return c; } int mul(int a, int b) { return (int)(a * (long long)b % base); } int pow(int a, int b) { if (!b) return 1; if (b == 1) return a; int d = pow(mul(a, a), b / 2); if (b % 2) return mul(d, a); return d; } int divis(int a, int b) { return mul(a, pow(b, base - 2)); } struct segment_tree { public: segment_tree() : ts(0) {} explicit segment_tree(vector<int> &p) : ts(1) { size_t n = p.size(); while (ts < n) { ts <<= 1u; } st.resize(2 * ts); for (int i = ts; i < ts + n; ++i) { st[i] = p[i - ts]; } for (int i = (int)ts - 1; i; --i) { st[i] = mul(st[i * 2], st[2 * i + 1]); } } int get_mul(int l, int r) { l += ts; r += (int)ts - 1; int res = 1; while (l <= r) { if (l % 2) { res = mul(res, st[l++]); } if (r % 2 == 0) { res = mul(res, st[r--]); } l /= 2; r /= 2; } return res; } private: size_t ts; vector<int> st; }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q; cin >> n >> q; vector<int> p(n); for (auto &x : p) { cin >> x; } segment_tree st(p); vector<int> deg100(n + 1), pref(n + 1); deg100[0] = pref[0] = 1; for (int i = 1; i <= n; ++i) { deg100[i] = mul(100, deg100[i - 1]); } for (int i = 1; i <= n; ++i) { pref[i] = mul(pref[i - 1], p[i - 1]); } vector<int> dot_product(n); dot_product[0] = 100; for (int i = 1; i < n; ++i) { dot_product[i] = mul(100, sum(dot_product[i - 1], pref[i])); } int ans = divis(dot_product.back(), pref[n]); set<pair<int, int>> ind = {{0, ans}, {n, 0}}; function<int(int, int)> func = [&](int l, int r) { if (r - l == 1) { return 100; } int res = dot_product[r - 1]; int a = 0; if (l) { a = mul(deg100[r - l], dot_product[l - 1]); } res = diff(res, a); return divis(res, pref[l]); }; while (q--) { int i; cin >> i; --i; auto v = ind.lower_bound({i, 0}); if (v->first != i) { int r = v->first; --v; int l = v->first; ans = diff(ans, v->second); int fst = divis(func(l, i), st.get_mul(l, i)); int snd = divis(func(i, r), st.get_mul(i, r)); ind.insert({v->first, fst}); ind.erase(v); ind.insert({i, snd}); ans = sum(ans, fst); ans = sum(ans, snd); } else { auto u = prev(v); ans = diff(ans, v->second); ans = diff(ans, u->second); ind.erase(v); int l = u->first, r = next(u)->first; int val = divis(func(l, r), st.get_mul(l, r)); ans = sum(ans, val); ind.insert({u->first, val}); ind.erase(u); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int t[n]; for (int i = 0; i < n; i++) cin >> t[i]; int left_cnt, left_time, right_cnt, right_time; int left_idx = 0, right_idx = n - 1; left_time = left_cnt = right_time = right_cnt = 0; while (left_idx <= right_idx) { left_time += t[left_idx]; left_cnt++; while (right_idx > left_idx && right_time < left_time) { right_time += t[right_idx--]; right_cnt++; } left_idx++; } cout << left_cnt << << right_cnt << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O2111AI_PP_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a, b, c[101], d[101], mx = -1e9, cnt; int main() { cin >> a >> b; for (int i = 1; i <= a; ++i) { cin >> c[i]; } for (int i = 1; i < a; ++i) { d[i] = c[i] - c[i + 1] - b; } for (int i = 1; i <= a; ++i) { mx = max(d[i], mx); } cout << mx; return 0; }
|
module VGA1Interface(clock,reset,framebuffer,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock;
input wire reset;
input wire [63:0] framebuffer;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
reg [9:0] CounterX;
reg [8:0] CounterY;
wire value;
reg clock2 = 0;
always @ (posedge clock) begin
if (reset) begin
clock2 = 0;
end
else begin
clock2 = ~clock2;
end
end
reg vga_HS;
reg vga_VS;
wire inDisplayArea = CounterX < 640 && CounterY < 480;
wire CounterXmaxed = (CounterX==767);
always @ (posedge clock2) begin
if(CounterXmaxed) begin
CounterX <= 0;
end
else begin
CounterX <= CounterX + 1;
end
end
always @ (posedge clock2) begin
if(CounterXmaxed) begin
CounterY <= CounterY + 1;
end
end
always @ (posedge clock2) begin
vga_HS <= (CounterX[9:4]==0);
vga_VS <= (CounterY==0);
end
assign vga_hsync = ~vga_HS;
assign vga_vsync = ~vga_VS;
reg [2:0] ix;
reg [2:0] iy;
always @ (posedge clock2) begin
if (CounterX < 80) begin
ix = 0;
end
else if (CounterX < 160) begin
ix = 1;
end
else if (CounterX < 240) begin
ix = 2;
end
else if (CounterX < 320) begin
ix = 3;
end
else if (CounterX < 400) begin
ix = 4;
end
else if (CounterX < 480) begin
ix = 5;
end
else if (CounterX < 560) begin
ix = 6;
end
else if (CounterX < 640) begin
ix = 7;
end
end // always @ (posedge clock2)
always @ (posedge clock2) begin
if (CounterY < 60) begin
iy = 0;
end
else if (CounterY < 120) begin
iy = 1;
end
else if (CounterY < 180) begin
iy = 2;
end
else if (CounterY < 240) begin
iy = 3;
end
else if (CounterY < 300) begin
iy = 4;
end
else if (CounterY < 360) begin
iy = 5;
end
else if (CounterY < 420) begin
iy = 6;
end
else if (CounterY < 480) begin
iy = 7;
end
end // always @ (posedge clock2)
assign value = framebuffer[{iy,ix}];
assign vga_r = value & inDisplayArea;
assign vga_g = value & inDisplayArea;
assign vga_b = value & inDisplayArea;
endmodule // VGA1Interface
|
#include <bits/stdc++.h> using namespace std; int n, pos, l, r, ind, ans = 0, ans1 = 0, ans2 = 0; int main(void) { ios ::sync_with_stdio(0); cin.tie(0); cin >> n >> pos >> l >> r; if (pos < l) { ans += l - pos + 1; if (n - r > 0) { ans += r - l + 1; } } else if (pos > r) { ans += pos - r + 1; if (l - 1 > 0) { ans += r - l + 1; } } else { ind = pos; if (l - 1 > 0) { ans1 += ind - l + 1; ind = l; } if (n - r > 0) { ans1 += r - ind + 1; } ind = pos; if (n - r > 0) { ans2 += r - ind + 1; ind = r; } if (l - 1 > 0) { ans2 += ind - l + 1; } ans = min(ans1, ans2); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[26][26]; int main() { int n; cin >> n; memset(a, 0, sizeof(a)); char ch[20]; int len; for (int i = 1; i <= n; i++) { scanf( %s , ch); for (len = 0; ch[len]; len++) ; for (int j = 0; j < 26; j++) if (a[j][ch[0] - a ]) { a[j][ch[len - 1] - a ] = max(a[j][ch[len - 1] - a ], a[j][ch[0] - a ] + len); } a[ch[0] - a ][ch[len - 1] - a ] = max(a[ch[0] - a ][ch[len - 1] - a ], len); } int ans = 0; for (int i = 0; i < 26; i++) ans = max(ans, a[i][i]); cout << ans << endl; return 0; }
|
/**************************************************************************
UART Receiver Module
-Sampling speed
x4
-parameter BAUDRATE_COUNTER
Uart Baudrate Parameter (Clock / Baudrate)/4-1
BAUDRATE_COUNTER is must be greater than 4. (BAUDRATE_COUNTER >= 20'h4)
Example : Clock : 50MHz
9600bps : 13'd1301
115.2Kbps : 13'd108
-SDF Settings
Asynchronus Clock : b_bd_clock
-Make : 2013/2/21
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032sa_uart_receiver #(
parameter BAUDRATE_FIXED = 1'b1, //0:Use iEXTBAUD_COUNT | 1:Use Parameter BAUDRATE_COUNTER
parameter BAUDRATE_COUNTER = 20'd108 //(Clock / Baudrate) / 4 - 1
)(
//Clock
input wire iCLOCK,
input wire inRESET,
//External Baudrate Timing
input wire [19:0] iEXTBAUD_COUNT,
//R Data
output wire oRX_VALID,
output wire [7:0] oRX_DATA,
//UART
input wire iUART_RXD
);
/**************************************************************
Parameter & Wire & Register
**************************************************************/
localparam IF_IDLE = 2'h0;
localparam IF_RECEIVED = 2'h1;
localparam IF_IDLEWAIT = 2'h2;
localparam RXD_IDLE = 2'h0;
localparam RXD_RECEIVING = 2'h1;
localparam RXD_RECEIVED = 2'h2;
//UART Metastable Cancel
wire uart_rxd;
//RXD Module
reg bn_rxd_init;
reg [1:0] b_rxd_state;
reg [7:0] b_rxd_buffer;
reg [5:0] b_rxd_counter;
reg b_rxd_data_req;
reg b_rxd_idle_req;
//Metastable Cancel
wire dflipflop_idle_req;
wire dflipflop_data_req;
//Async 2 Sync
wire sync_idle_req;
wire sync_data_req;
//Interface
reg [1:0] b_if_state;
reg [7:0] b_if_data;
reg b_if_end;
//Baudrate
reg [19:0] b_bd_wait_counter;
reg b_bd_clock;
/**************************************************************
RxD
**************************************************************/
//Metastable Cancel
mist1032sa_uart_receiver_double_flipflop #(1) RXD_DOUBLE_FLIPFLOP(
.iCLOCK(b_bd_clock),
.inRESET(inRESET),
//Input
.iREQ_DATA(iUART_RXD),
//Output
.oOUT_DATA(uart_rxd)
);
//Uart State
always@(posedge b_bd_clock or negedge inRESET)begin
if(!inRESET)begin
bn_rxd_init <= 1'b0;
b_rxd_state <= RXD_IDLE;
b_rxd_buffer <= 8'h0;
b_rxd_counter <= 6'h0;
b_rxd_data_req <= 1'b0;
b_rxd_idle_req <= 1'b0;
end
else if(!bn_rxd_init)begin
bn_rxd_init = 1'b1;
b_rxd_buffer <= 8'hFF;
end
else begin
case(b_rxd_state)
RXD_IDLE:
begin
//Stat bit Check
if(b_rxd_buffer[5:4] == 2'h0)begin
b_rxd_state <= RXD_RECEIVING;
end
b_rxd_buffer <= {uart_rxd, b_rxd_buffer[7:1]};
b_rxd_counter <= 6'h0;
b_rxd_data_req <= 1'b0;
b_rxd_idle_req <= 1'b0;
end
RXD_RECEIVING:
begin
b_rxd_idle_req <= 1'b0;
if(b_rxd_counter == 6'd32)begin
b_rxd_state <= RXD_RECEIVED;
b_rxd_data_req <= 1'b1;
end
else begin
if(b_rxd_counter[1:0] == 2'h1)begin //Uart center pickup
b_rxd_buffer <= {uart_rxd, b_rxd_buffer[7:1]};
end
b_rxd_counter <= b_rxd_counter + 6'h1;
end
end
RXD_RECEIVED:
begin
b_rxd_state <= RXD_IDLE;
b_rxd_buffer <= 8'hFF;
b_rxd_data_req <= 1'b0;
b_rxd_idle_req <= 1'b1;
end
endcase
end
end
//Metastable Cancel
mist1032sa_uart_receiver_double_flipflop #(2) DOUBLE_FLIPFLOP(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iREQ_DATA({b_rxd_idle_req, b_rxd_data_req}),
//Output
.oOUT_DATA({dflipflop_idle_req, dflipflop_data_req})
);
//Async 2 Sync
mist1032sa_uart_receiver_async2sync #(2) ASYNC2SYNC(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Ena-Signal
.iSIGNAL({dflipflop_idle_req, dflipflop_data_req}),
.oSIGNAL({sync_idle_req, sync_data_req})
);
//Interface State
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if_state <= IF_IDLE;
b_if_data <= 8'h0;
b_if_end <= 1'b0;
end
else begin
case(b_if_state)
IF_IDLE:
begin
if(sync_data_req)begin
b_if_state <= IF_RECEIVED;
b_if_data <= b_rxd_buffer;//dflipflop_data;
b_if_end <= 1'b1;
end
end
IF_RECEIVED:
begin
b_if_state <= IF_IDLEWAIT;
b_if_end <= 1'b0;
end
IF_IDLEWAIT:
begin
if(sync_idle_req)begin
b_if_state <= IF_IDLE;
end
end
default:
begin
b_if_state <= IF_IDLE;
b_if_data <= 8'h0;
b_if_end <= 1'b0;
end
endcase
end
end
/**************************************************************
Baudrate Counter
**************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b0;
end
else begin
if((BAUDRATE_FIXED && b_bd_wait_counter == BAUDRATE_COUNTER) || (!BAUDRATE_FIXED && b_bd_wait_counter == iEXTBAUD_COUNT))begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b1;
end
else begin
b_bd_wait_counter <= b_bd_wait_counter + 20'h1;
b_bd_clock <= 1'b0;
end
end
end
assign oRX_VALID = b_if_end;
assign oRX_DATA = b_if_data;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); map<pair<int, int>, int> f; int t, it, n, res, tmp, x, y, resr, resl, i; string s; cin >> t; for (it = 1; it <= t; it++) { cin >> n; cin >> s; s = + s; x = 0; y = 0; resr = 1e8; resl = -1e8; for (i = 1; i <= n; i++) { if (s[i] == D ) { x--; if (f[{x, y}] != 0) { if ((i - f[{x, y}] - 1) < (resr - resl)) { resr = i; resl = f[{x, y}] + 1; } } if ((x == 0) && (y == 0)) { if ((i - 1) < (resr - resl)) { resr = i; resl = 1; } } f[{x, y}] = i; } else if (s[i] == U ) { x++; if (f[{x, y}] != 0) { if ((i - f[{x, y}] - 1) < (resr - resl)) { resr = i; resl = f[{x, y}] + 1; } } if ((x == 0) && (y == 0)) { if ((i - 1) < (resr - resl)) { resr = i; resl = 1; } } f[{x, y}] = i; } else if (s[i] == L ) { y--; if (f[{x, y}] != 0) { if ((i - f[{x, y}] - 1) < (resr - resl)) { resr = i; resl = f[{x, y}] + 1; } } if ((x == 0) && (y == 0)) { if ((i - 1) < (resr - resl)) { resr = i; resl = 1; } } f[{x, y}] = i; } else if (s[i] == R ) { y++; if (f[{x, y}] != 0) { if (((i)-f[{x, y}] - 1) < (resr - resl)) { resr = i; resl = f[{x, y}] + 1; } } if ((x == 0) && (y == 0)) { if ((i - 1) < (resr - resl)) { resr = i; resl = 1; } } f[{x, y}] = i; } } if (resr == 1e8) { cout << -1 << n ; } else { cout << resl << << resr << n ; } f.clear(); } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p0_odd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p0_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px, sctag1_pcx_stall_bufp0odd_pq,
// Inputs
arbpc1_pcxdp_grant_bufp1_pa_l, arbpc1_pcxdp_q0_hold_bufp1_pa,
arbpc1_pcxdp_qsel0_bufp1_pa_l, arbpc1_pcxdp_qsel1_bufp1_pa,
arbpc1_pcxdp_shift_bufp1_px_l, arbpc3_pcxdp_grant_bufp1_pa_l,
arbpc3_pcxdp_q0_hold_bufp1_pa, arbpc3_pcxdp_qsel0_bufp1_pa_l,
arbpc3_pcxdp_qsel1_bufp1_pa, arbpc3_pcxdp_shift_bufp1_px_l,
arbpc4_pcxdp_grant_bufp1_pa_l, arbpc4_pcxdp_q0_hold_bufp1_pa,
arbpc4_pcxdp_qsel0_bufp1_pa_l, arbpc4_pcxdp_qsel1_bufp1_pa,
arbpc4_pcxdp_shift_bufp1_px_l, sctag1_pcx_stall_pq
);
output arbpc1_pcxdp_grant_pa;
output arbpc1_pcxdp_q0_hold_pa_l;
output arbpc1_pcxdp_qsel0_pa;
output arbpc1_pcxdp_qsel1_pa_l;
output arbpc1_pcxdp_shift_px;
output arbpc3_pcxdp_grant_pa;
output arbpc3_pcxdp_q0_hold_pa_l;
output arbpc3_pcxdp_qsel0_pa;
output arbpc3_pcxdp_qsel1_pa_l;
output arbpc3_pcxdp_shift_px;
output arbpc4_pcxdp_grant_pa;
output arbpc4_pcxdp_q0_hold_pa_l;
output arbpc4_pcxdp_qsel0_pa;
output arbpc4_pcxdp_qsel1_pa_l;
output arbpc4_pcxdp_shift_px;
output sctag1_pcx_stall_bufp0odd_pq;
input arbpc1_pcxdp_grant_bufp1_pa_l;
input arbpc1_pcxdp_q0_hold_bufp1_pa;
input arbpc1_pcxdp_qsel0_bufp1_pa_l;
input arbpc1_pcxdp_qsel1_bufp1_pa;
input arbpc1_pcxdp_shift_bufp1_px_l;
input arbpc3_pcxdp_grant_bufp1_pa_l;
input arbpc3_pcxdp_q0_hold_bufp1_pa;
input arbpc3_pcxdp_qsel0_bufp1_pa_l;
input arbpc3_pcxdp_qsel1_bufp1_pa;
input arbpc3_pcxdp_shift_bufp1_px_l;
input arbpc4_pcxdp_grant_bufp1_pa_l;
input arbpc4_pcxdp_q0_hold_bufp1_pa;
input arbpc4_pcxdp_qsel0_bufp1_pa_l;
input arbpc4_pcxdp_qsel1_bufp1_pa;
input arbpc4_pcxdp_shift_bufp1_px_l;
input sctag1_pcx_stall_pq;
assign arbpc1_pcxdp_grant_pa = ~arbpc1_pcxdp_grant_bufp1_pa_l;
assign arbpc1_pcxdp_q0_hold_pa_l = ~arbpc1_pcxdp_q0_hold_bufp1_pa;
assign arbpc1_pcxdp_qsel0_pa = ~arbpc1_pcxdp_qsel0_bufp1_pa_l;
assign arbpc1_pcxdp_qsel1_pa_l = ~arbpc1_pcxdp_qsel1_bufp1_pa;
assign arbpc1_pcxdp_shift_px = ~arbpc1_pcxdp_shift_bufp1_px_l;
assign arbpc3_pcxdp_grant_pa = ~arbpc3_pcxdp_grant_bufp1_pa_l;
assign arbpc3_pcxdp_q0_hold_pa_l = ~arbpc3_pcxdp_q0_hold_bufp1_pa;
assign arbpc3_pcxdp_qsel0_pa = ~arbpc3_pcxdp_qsel0_bufp1_pa_l;
assign arbpc3_pcxdp_qsel1_pa_l = ~arbpc3_pcxdp_qsel1_bufp1_pa;
assign arbpc3_pcxdp_shift_px = ~arbpc3_pcxdp_shift_bufp1_px_l;
assign arbpc4_pcxdp_grant_pa = ~arbpc4_pcxdp_grant_bufp1_pa_l;
assign arbpc4_pcxdp_q0_hold_pa_l = ~arbpc4_pcxdp_q0_hold_bufp1_pa;
assign arbpc4_pcxdp_qsel0_pa = ~arbpc4_pcxdp_qsel0_bufp1_pa_l;
assign arbpc4_pcxdp_qsel1_pa_l = ~arbpc4_pcxdp_qsel1_bufp1_pa;
assign arbpc4_pcxdp_shift_px = ~arbpc4_pcxdp_shift_bufp1_px_l;
assign sctag1_pcx_stall_bufp0odd_pq = sctag1_pcx_stall_pq;
endmodule
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:55:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.v
// Design : system_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module system_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
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#include <bits/stdc++.h> using namespace std; long long n, h[100005], num = 0, lt = 0, rt, dp[100005], dp1[100005], cur; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> h[i]; for (long long i = 1; i <= n; i++) { long long temp = dp[lt] + (i - lt); if (h[i] - cur <= 0 || temp <= cur) { dp[i] = min(h[i], temp); lt = i; continue; } else { dp[i] = cur + 1; cur++; } } cur = 0; lt = n + 1; for (long long i = n; i >= 1; i--) { long long temp = dp1[lt] + (lt - i); if (h[i] - cur <= 0 || temp <= cur) { dp1[i] = min(h[i], temp); lt = i; continue; } else { dp1[i] = cur + 1; cur++; } } long long ans = 0; for (int i = 1; i <= n; i++) { dp[i] = min(dp[i], dp1[i]); ans = max(ans, dp[i]); } cout << ans; }
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#include <bits/stdc++.h> char s[100][100]; int main() { int n, m, ans = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 1; i < n; i++) { for (int j = i + 1; j <= n; j++) { int f = 0, g = 0; for (int k = 1; k <= m; k++) if (s[i][k] != . || s[j][k] != . ) { if (s[i][k] == s[j][k]) f = 1; else g = 1; } if (f == g && f) { printf( No ); return 0; } } } printf( Yes ); }
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#include <bits/stdc++.h> using namespace std; int n, m, k; int n1, n2, n3; int c[510]; int sc[510]; int pai[100010]; int type[100010]; int peso[100010]; int dp[510][510]; vector<pair<pair<int, int>, int> > edges; int find(int i) { return pai[i] = (pai[i] == i) ? i : find(pai[i]); } void join(int i, int j) { i = find(i); j = find(j); if (i == j) return; if (peso[i] < peso[j]) swap(i, j); pai[j] = i; if (peso[i] == peso[j]) peso[i]++; } void init() { for (int g = 1; g <= n; g++) { pai[g] = g; peso[g] = 0; } } int main() { scanf( %d %d %d , &n, &m, &k); init(); for (int g = 1; g <= k; g++) { scanf( %d , &c[g]); sc[g] = sc[g - 1] + c[g]; } for (int g = 0; g < m; g++) { scanf( %d %d %d , &n1, &n2, &n3); edges.push_back(make_pair(make_pair(n1, n2), n3)); if (n3 == 0) join(n1, n2); } for (int g = 1; g <= k; g++) for (int h = sc[g - 1] + 1; h <= sc[g]; h++) type[h] = g; bool error = false; for (int g = 1; g < n; g++) if (type[g] == type[g + 1] && find(g) != find(g + 1)) error = true; if (error) { printf( No n ); return 0; } printf( Yes n ); for (int g = 1; g <= k; g++) for (int h = 1; h <= k; h++) dp[g][h] = 1000000010; for (int g = 1; g <= k; g++) dp[g][g] = 0; for (int g = 0; g < m; g++) { int i = edges[g].first.first; int j = edges[g].first.second; int w = edges[g].second; i = type[i]; j = type[j]; if (i != j) dp[i][j] = dp[j][i] = min(dp[i][j], w); } for (int p = 1; p <= k; p++) for (int q = 1; q <= k; q++) for (int r = 1; r <= k; r++) dp[q][r] = min(dp[q][r], dp[q][p] + dp[p][r]); for (int q = 1; q <= k; q++) { for (int p = 1; p <= k; p++) printf( %d , (dp[p][q] == 1000000010) ? -1 : dp[p][q]); printf( n ); } }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; long long a[maxn], x[maxn], y[maxn], c[7], d[7], ans; int n, m; bool cmp(long long x, long long y) { return x > y; } void sol(int pos, int num, int flag) { memset(d, 0, sizeof(d)); if (flag) { for (int i = 1; i <= pos; i++) { long long w = y[i]; for (int j = 0; j < 4 - num; j++) { w -= a[(c[j] - 1) * m + i]; } d[num] = w; sort(d, d + num + 1, cmp); } long long ac = 0; for (int i = 0; i < num; i++) { ac += d[i]; } for (int j = 0; j < 4 - num; j++) { ac += x[c[j]]; } ans = max(ans, ac); } else { for (int i = 1; i <= pos; i++) { long long w = x[i]; for (int j = 0; j < 4 - num; j++) { w -= a[(i - 1) * m + c[j]]; } d[num] = w; sort(d, d + num + 1, cmp); } long long ac = 0; for (int i = 0; i < num; i++) { ac += d[i]; } for (int j = 0; j < 4 - num; j++) { ac += y[c[j]]; } ans = max(ans, ac); } } int main() { scanf( %d%d , &n, &m); long long sum = 0; for (int i = 1; i <= n * m; i++) { scanf( %lld , &a[i]); sum += a[i]; } memset(d, 0, sizeof(d)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { x[i] += a[(i - 1) * m + j]; } d[4] = x[i]; sort(d, d + 5, cmp); } for (int i = 0; i < 4; i++) { ans += d[i]; } long long xxx = 0; memset(d, 0, sizeof(d)); for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { y[i] += a[(j - 1) * m + i]; } d[4] = y[i]; sort(d, d + 5, cmp); } for (int i = 0; i < 4; i++) { xxx += d[i]; } ans = max(xxx, ans); if (n <= 4 || m <= 4) { printf( %lld n , sum); return 0; } for (int i = 1; i <= n; i++) { c[0] = i; sol(m, 3, 1); } for (int i = 1; i <= m; i++) { c[0] = i; sol(n, 3, 0); } if (n > m) { for (int i = 1; i <= m; i++) { for (int j = i + 1; j <= m; j++) { c[0] = i; c[1] = j; sol(n, 2, 0); } } } else { for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { c[0] = i; c[1] = j; sol(m, 2, 1); } } } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long sumfirst = 0, sumsecond = 0; long long n; vector<long long> first, second; long long arr[200000]; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] > 0) sumfirst += arr[i]; else if (arr[i] < 0) sumsecond += arr[i]; if (arr[i] > 0) first.push_back(arr[i]); else second.push_back(arr[i]); } if (sumfirst > (sumsecond * -1)) { cout << first << endl; return 0; } else if (sumfirst < (sumsecond * -1)) { cout << second << endl; return 0; } for (int i = 0; i < min(second.size(), first.size()); i++) { if (first[i] > (second[i] * -1)) { cout << first << endl; return 0; } else if ((second[i] * -1) > first[i]) { cout << second << endl; return 0; } } if (arr[n - 1] > 0) { cout << first << endl; return 0; } else cout << second << endl; return 0; return 0; }
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module QcmMasterControllerMain(clk, sig, codeSer, codePar, enableSer, enablePar, ioPowerEnable, clkEnable, serCodeOutput, parCodeOutput, nclkOutput);
/*
This is the master controller module which instantiates the sub-modules responsible for master controller operation:
counter=frequency counter (really, a period counter with inversion) for
determining the RF frequency from the square-wave input on "sig"
lut=look-up-table for mapping from a frequency to a capacitor state.
Currently, the same state number is assigned to both the series and parallel outputs
driver=responsible for mapping from look-up-table output to encoded
signal for decoder boards (in present implementation, no adjustment
needs to be made to lut output), and also determines whether the state
has settled and the cap boards may act on the change.
PIN ASSIGNMENT FOR EPM2210F256C5N (MANY MACROCELL CPLD)
To arrive at this pin assignment,
(1) consult pin assignment for CapBoardDecoder (for tuning code pins) OR "BurkeCPLDBoardConfigurationTemplate.doc" (for signal input)
(2) map to pins on standard 84-pin CPLD
(3) consult Bill Parkin's 84-256-pin adapter schematic to map to 256-pin pin values.
Ok clk Location PIN_H5 Yes
Ok sig Location PIN_K1 Yes (PIN_04 on socket - see Willy Burke's doc and note we are using Slot 1 for sync input on board front panel)
Ok enableSer Location PIN_F1 Yes AC24 on backplane
Ok enablePar Location PIN_G1 Yes AC25
Ok codeSer[0] Location PIN_R16 Yes AC3
Ok codeSer[1] Location PIN_L16 Yes AC6
Ok codeSer[2] Location PIN_E16 Yes AC9
Ok codeSer[3] Location PIN_A13 Yes AC12
Ok codeSer[4] Location PIN_A8 Yes AC15
Ok codeSer[5] Location PIN_A5 Yes AC18
Ok codeSer[6] Location PIN_B1 Yes AC21
Ok codePar[0] Location PIN_N16 Yes AC4
Ok codePar[1] Location PIN_G16 Yes AC7
Ok codePar[2] Location PIN_D16 Yes AC10
Ok codePar[3] Location PIN_A12 Yes AC13
Ok codePar[4] Location PIN_A7 Yes AC16
Ok codePar[5] Location PIN_A4 Yes AC19
Ok codePar[6] Location PIN_D1 Yes AC22
Ok ioPowerEnable Location PIN_T12 Yes Connects to I/O 27. This needs a signal - e.g. clock divided down - to demonstrate CPLD is working. But really should go to Pin56 out of CPLD - this is not connected to 256-pin CPLD, so need to make a jumper wire on board.
Ok clkEnable Location PIN_T15 Yes Connects to I/O 28. The clock needs Pin73 out of CPLD to be high to work, but Pin73 is not connected to 256-pin CPLD, so need to make a hardware jumper on the board.
Ok serCodeOutput Location PIN_N1 Yes Encodes the logic state for the series capacitors into a time series going out on LEMO I/O 4
Ok parCodeOutput Location PIN_T2 Yes Encodes the logic state for the series capacitors into a time series going out on LEMO I/O 4
Ok nclkOutput Location PIN_T4 Yes Encodes n_clk - the number of clock counts in a signal count period. Goes out on I/O #6 - J16 on 84-pin footprint, and connected to PIN_T4 on 256 pin adapter.
Ted Golfinopoulos, pin assignment made on 24 Oct 2011
Revised 9 January 2012
*/
input clk, sig; //1 bit inputs corresponding to clk and RF signal.
output wire [6:0] codeSer, codePar; //Capacitor state encoded in a number which is interpreted by CapBoardDecoder to determine which caps to turn on.
output enableSer, enablePar; //"Ready" bits indicating codes are ready for decoding.
output ioPowerEnable; //Bit which receives clock-like signal and allows IO circuitry to receive power on LH timing board.
output clkEnable; //Bit which, when high, enables clock.
output serCodeOutput; //Bit containing encoded version of serial cap code.
output parCodeOutput; //Bit containing encoded version of parallel cap code.
output nclkOutput; //Bit containing (time)-encoded version of clock counts per M signal count period.
//wire [13:0] f; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [13:0] n_clk; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [6:0] stateSer; //Intermediate variable to hold lut output for series levels.
wire [6:0] statePar; //Intermediate variable to hold lut output for parallel levels.
reg [4:0] clkCntr; //Divide clock signal down.
initial begin
#0
clkCntr=4'b0; //Initialize clock counter.
end
//Instantiate frequency counter object.
//counter c(clk, sig, f); //Use period counter instead of frequency counter.
//fcounter c(clk, sig, f); //Use frequency counter instead of period counter.
counter_n c(clk, sig, n_clk); //Use period counter, but don't use division step. Instead, pass number of clock counts.
//10 August 2012 double clock speed and halve number of signal edges so that matching
//network can respond faster to frequency chances.
defparam c.M=25; //Number of signal edges counted inside period counter.
defparam c.F_CLK=80000; //Clock frequency in hundreds of Hz.
//79 corner frequencies in HUNDREDS OF Hz,
//from about 50 kHz (500 hundred Hz) to 300 kHz (3000 hundred Hz)
//Instantiate look-up table which determines state from frequency.
//lut tab(clk,f,state);
lut_n tabSer(clk,n_clk,stateSer); //Tell series lut to use table 1
lut_n tabPar(clk,n_clk,statePar); //Tell parallel lut to use table 2
defparam tabSer.LOOKUP_ID=1; //Tell series lut to use table 1
defparam tabPar.LOOKUP_ID=2; //Tell parallel lut to use table 2
//defparam tabSer.OFFSET=4'b1000;
//defparam tabPar.OFFSET=4'b0111;
//lut_n tabSer(clk,n_clk,stateSer);
//lut_n tabPar(clk,n_clk,statePar);
//At this point, the look-up table outputs a state in the same format required for the encoded cap states, and
//the cap index for the series board is the same as for the parallel board.
assign codeSer=stateSer;
assign codePar=statePar;
//Instantiate drivers for serial and parallel states - primarily, this determines when the states are ready for decoding by CapBoardDecoder.
driver dSer(clk, codeSer, enableSer);
driver dPar(clk, codePar, enablePar);
//Instantiate encoders to put out the series and parallel codes in a pulse sequence on the LEMO outputs.
//Give a slower version of clock so that the digitizer, with 2.5 MHz sample rate, can resolve the pulses.
stateEncoder seriesStateEncoder(clkCntr[4], codeSer, enableSer, serCodeOutput);
stateEncoder parallelStateEncoder(clkCntr[4], codePar, enablePar, parCodeOutput);
defparam nclkEncoder.STATE_LENGTH=4'b1110; //Need to redefine the parameter dictating the size of the bit pattern to encode.
stateEncoder nclkEncoder(clkCntr[4], n_clk, enableSer, nclkOutput); //Instantiate encoder for n_clk
always @(posedge clk) begin
clkCntr=clkCntr+4'b1; //Increment clock counter.
end
//Give ioPowerEnable bit a divided version of the clock. The rationale behind this is
//that (a) the ioPowerEnable bit needs a clock-like signal and (b) you should do an operation
//on the clock to prove that the CPLD is working (otherwise synthesis can just connect a wire,
//and so passing the clock to the ioPowerEnable bit may not demonstrate functionality). This
//is in accordance with the new version of the LH Timing Board. Pin 56 on the CPLD must receive
//the ioPowerEnable bit.
assign ioPowerEnable=clkCntr[1];
assign clkEnable=1'b1;
endmodule
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#include <bits/stdc++.h> using namespace std; FILE *in; FILE *out; const int MAX = 1048576; const int TREE = 2097152; const int MOD = 1000000007; int n; int a[MAX]; int tree[TREE]; bool seen[MAX]; int query(int idx1, int idx2) { idx1 += (TREE >> 1); idx2 += (TREE >> 1); if (idx1 == idx2) return tree[idx1]; int ret = 0; ret += tree[idx1]; if (ret >= MOD) ret -= MOD; int flag1 = !(idx1 & 1); idx1 >>= 1; ret += tree[idx2]; if (ret >= MOD) ret -= MOD; int flag2 = (idx2 & 1); idx2 >>= 1; while (idx1 != idx2) { if (flag1) { ret += tree[(idx1 << 1) + 1]; if (ret >= MOD) ret -= MOD; } if (flag2) { ret += tree[(idx2 << 1) + 0]; if (ret >= MOD) ret -= MOD; } flag1 = !(idx1 & 1); idx1 >>= 1; flag2 = (idx2 & 1); idx2 >>= 1; } return ret; } void update(int idx, int val) { idx += (TREE >> 1); while (idx) { tree[idx] += val; if (tree[idx] >= MOD) tree[idx] -= MOD; idx >>= 1; } } int main(void) { in = stdin; out = stdout; fscanf(in, %d , &n); for (int i = 0; i < n; i++) fscanf(in, %d , &a[i]); int ans = 0; memset(tree, 0, sizeof(tree)); for (int i = n - 1; i >= 0; i--) { int cur = ((long long)a[i] * (query(a[i], MAX - 1) + 1)) % MOD; ans += cur; if (ans >= MOD) ans -= MOD; int sub = query(a[i], a[i]); ans -= sub; if (ans < 0) ans += MOD; update(a[i], (cur - sub + MOD) % MOD); } fprintf(out, %d n , ans); return 0; }
|
#include <bits/stdc++.h> template <typename T> class IntegerIterator : public std::iterator<std::input_iterator_tag, T, std::ptrdiff_t, T*, T> { public: explicit IntegerIterator(T value) : value(value) {} IntegerIterator& operator++() { ++value; return *this; } IntegerIterator operator++(int) { IntegerIterator copy = *this; ++value; return copy; } IntegerIterator& operator--() { --value; return *this; } IntegerIterator operator--(int) { IntegerIterator copy = *this; --value; return copy; } T operator*() const { return value; } bool operator==(IntegerIterator rhs) const { return value == rhs.value; } bool operator!=(IntegerIterator rhs) const { return !(*this == rhs); } private: T value; }; template <typename T> class IntegerRange { public: IntegerRange(T begin, T end) : begin_(begin), end_(end) { ; } IntegerIterator<T> begin() const { return IntegerIterator<T>(begin_); } IntegerIterator<T> end() const { return IntegerIterator<T>(end_); } private: T begin_; T end_; }; template <typename T> class ReversedIntegerRange { using IteratorType = std::reverse_iterator<IntegerIterator<T>>; public: ReversedIntegerRange(T begin, T end) : begin_(begin), end_(end) { ; } IteratorType begin() const { return IteratorType(IntegerIterator<T>(begin_)); } IteratorType end() const { return IteratorType(IntegerIterator<T>(end_)); } private: T begin_; T end_; }; template <typename T> IntegerRange<T> range(T to) { return IntegerRange<T>(0, to); } template <typename T> IntegerRange<T> range(T from, T to) { return IntegerRange<T>(from, to); } template <typename T> IntegerRange<T> inclusiveRange(T to) { return IntegerRange<T>(0, to + 1); } template <typename T> IntegerRange<T> inclusiveRange(T from, T to) { return IntegerRange<T>(from, to + 1); } template <typename T> ReversedIntegerRange<T> downrange(T from) { return ReversedIntegerRange<T>(from, 0); } template <typename T> ReversedIntegerRange<T> downrange(T from, T to) { return ReversedIntegerRange<T>(from, to); } template <typename T> ReversedIntegerRange<T> inclusiveDownrange(T from) { return ReversedIntegerRange<T>(from + 1, 0); } template <typename T> ReversedIntegerRange<T> inclusiveDownrange(T from, T to) { return ReversedIntegerRange<T>(from + 1, to); } std::vector<int> linearSieve(int maxN) { ; std::vector<int> leastPrimes(maxN + 1); std::vector<int> primes; for (int i = 2; i <= maxN; ++i) { if (leastPrimes[i] == 0) { leastPrimes[i] = i; primes.push_back(i); } for (int prime : primes) { if (i * prime > maxN) { break; } leastPrimes[i * prime] = prime; } } return leastPrimes; } template <typename T> T gcd(T a, T b) { while (b) { T tmp = a % b; a = b; b = tmp; } return a; } template <typename R> void sort(R& range) { std::sort(range.begin(), range.end()); } template <typename R, typename Comp> void sort(R& range, Comp comp) { std::sort(range.begin(), range.end(), comp); } template <typename R> void reverse(R& range) { std::reverse(range.begin(), range.end()); } template <typename R, typename T> auto lower_bound(const R& range, const T& value) -> decltype(range.begin()) { return std::lower_bound(range.begin(), range.end(), value); } template <typename R, typename T, typename Comp> auto lower_bound(const R& range, const T& value, Comp comp) -> decltype(range.begin()) { return std::lower_bound(range.begin(), range.end(), value, comp); } template <typename R, typename T> auto upper_bound(const R& range, const T& value) -> decltype(range.begin()) { return std::upper_bound(range.begin(), range.end(), value); } template <typename R, typename T, typename Comp> auto upper_bound(const R& range, const T& value, Comp comp) -> decltype(range.begin()) { return std::upper_bound(range.begin(), range.end(), value, comp); } template <typename R> auto min_element(const R& range) -> decltype(range.begin()) { return std::min_element(range.begin(), range.end()); } template <typename R> auto max_element(const R& range) -> decltype(range.begin()) { return std::max_element(range.begin(), range.end()); } template <typename R> bool next_permutation(R& range) { return std::next_permutation(range.begin(), range.end()); } template <typename T> void unique(std::vector<T>& range) { range.erase(std::unique(range.begin(), range.end()), range.end()); } template <typename R> R sorted(R range) { sort(range); return range; } template <typename R, typename Comp> R sorted(R range, Comp comp) { sort(range, comp); return range; } template <typename R> R reversed(R range) { reverse(range); return range; } using namespace std; class TaskF { public: void solve(std::istream& in, std::ostream& out) { int n; in >> n; vector<int> a(n); int magic = 300000; auto lp = linearSieve(magic); int globalGcd = 0; for (int i : range(n)) { in >> a[i]; auto& c = a[i]; while (c != 1 && c % (lp[c] * lp[c]) == 0) { c /= lp[c]; } globalGcd = gcd(globalGcd, a[i]); } if (globalGcd != 1) { out << -1; return; ; } sort(a); unique(a); vector<int64_t> cnt(magic); for (int x : a) { ++cnt[x]; } vector<int64_t> cntsev = cnt; for (int i = 1;; ++i) { if (cntsev[1]) { out << i << n ; return; } vector<int64_t> cntsum(magic); for (int x : downrange(magic, 1)) { for (int t = x; t < magic; t += x) { cntsum[x] += cnt[t]; } } vector<int64_t> cntsevsum(magic); for (int x : downrange(magic, 1)) { for (int t = x; t < magic; t += x) { cntsevsum[x] += cntsev[t]; } } vector<int64_t> cntnextsum(magic); for (int x : downrange(magic, 1)) { cntnextsum[x] = cntsevsum[x] * cntsum[x]; } vector<int64_t> cntnext = cntnextsum; for (int x : downrange(magic, 1)) { for (int t = 2 * x; t < magic; t += x) { cntnext[x] -= cntnext[t]; } } for (int x : downrange(magic, 1)) { if (cntnext[x] != 0) { cntnext[x] = 1; } } cntsev = cntnext; } } }; int main() { std::ios_base::sync_with_stdio(false); TaskF solver; std::istream& in(std::cin); std::ostream& out(std::cout); in.tie(nullptr); out << std::fixed; out.precision(20); solver.solve(in, out); return 0; }
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#include <bits/stdc++.h> using namespace std; template <class TH> void _dbg(const char *sdbg, TH h) { cerr << sdbg << = << h << endl; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cerr << *sdbg++; cerr << = << h << , ; _dbg(sdbg + 1, a...); } template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto vv : V) os << vv << , ; return os << ] ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class T> using min_heap = priority_queue<T, vector<T>, greater<T>>; template <class T> using max_heap = priority_queue<T>; const int mod = 1e9 + 7; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } struct PairHash { template <typename T1, typename T2> std::size_t operator()(const pair<T1, T2> &p) const { return hash<T1>()(p.first) ^ hash<T2>()(p.second); } }; void solve(int ncase) { int a, b, c, d; cin >> a >> b >> c >> d; int minx = min({a, b, c}); a -= minx; b -= minx; c -= minx; cout << (((a % 2 + b % 2 + c % 2 + (d + 3 * 1LL * minx) % 2) <= 1) || (minx >= 1 && ((a + 1) % 2 + (b + 1) % 2 + (c + 1) % 2 + (d + 3 * 1LL * minx - 3) % 2) <= 1) ? Yes : No ) << endl; } void solve_all_cases() { int T = 1; cin >> T; int ncase = 0; while (T--) { solve(++ncase); } } int main() { cout << std::fixed; cout << setprecision(6); solve_all_cases(); }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MX = 2e2 + 5; const long long INF = 1e18; const long double PI = 4 * atan((long double)1); const int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; namespace io { void setIn(string second) { freopen(second.c_str(), r , stdin); } void setOut(string second) { freopen(second.c_str(), w , stdout); } void setIO(string second = ) { ios_base::sync_with_stdio(0); cin.tie(0); if ((int)second.size()) { setIn(second + .in ); setOut(second + .out ); } } } // namespace io using namespace io; namespace input { template <class T> void re(complex<T>& x); template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } void re(long double& x) { string t; re(t); x = stold(t); } template <class Arg, class... Args> void re(Arg& first, Args&... rest) { re(first); re(rest...); } template <class T> void re(complex<T>& x) { T a, b; re(a, b); x = cd(a, b); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& a) { for (int i = (0); i < ((int)a.size()); ++i) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = (0); i < (SZ); ++i) re(a[i]); } } // namespace input namespace output { template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T, size_t SZ> void pr(const array<T, SZ>& x); template <class T> void pr(const vector<T>& x); template <class T> void pr(const set<T>& x); template <class T1, class T2> void pr(const map<T1, T2>& x); template <class T> void pr(const T& x) { cout << x; } template <class Arg, class... Args> void pr(const Arg& first, const Args&... rest) { pr(first); pr(rest...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T> void prContain(const T& x) { pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? , : , a), fst = 0; pr( } ); } template <class T, size_t SZ> void pr(const array<T, SZ>& x) { prContain(x); } template <class T> void pr(const vector<T>& x) { prContain(x); } template <class T> void pr(const set<T>& x) { prContain(x); } template <class T1, class T2> void pr(const map<T1, T2>& x) { prContain(x); } void ps() { pr( n ); } template <class Arg> void ps(const Arg& first) { pr(first); ps(); } template <class Arg, class... Args> void ps(const Arg& first, const Args&... rest) { pr(first, ); ps(rest...); } } // namespace output using namespace output; using namespace input; long long add(long long a, long long b) { a += b; if (a >= MOD) { a -= MOD; } return a; } long long sub(long long a, long long b) { a -= b; if (a < 0) { a += MOD; } return a; } long long mul(long long a, long long b) { return (a * b) % MOD; } void add_self(long long& a, long long b) { a = add(a, b); } void sub_self(long long& a, long long b) { a = sub(a, b); } void mul_self(long long& a, long long b) { a = mul(a, b); } int main() { setIO(); long long t; re(t); for (int ii = (0); ii < (t); ++ii) { long long N, W; re(N, W); vector<long long> v; for (int i = (0); i < (N); ++i) { long long a; re(a); v.push_back(a); } bool done = false; for (int i = (0); i < ((int)v.size()); ++i) { if (v[i] >= (W + 1) / 2 && v[i] <= W) { ps(1); ps(i + 1); done = true; break; } } if (done) { continue; } long long lind = -1; long long cs = 0; long long ignore = 0; for (int i = (0); i < ((int)v.size()); ++i) { if (v[i] > W) { ignore++; continue; } cs += v[i]; if (cs >= (W + 1) / 2 && cs <= W) { lind = i; break; } } if (lind == -1) { ps(-1); continue; } ps(lind + 1 - ignore); for (int i = (0); i < (lind + 1); ++i) { if (v[i] > W) { continue; } cout << i + 1 << ; } ps(); } return 0; }
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`timescale 1ns/1ns
module Timer_tb();
reg clk,
rstn;
reg[1:0] set;
wire ready;
Timer DUT (
.clk(clk),
.rstn(rstn),
.set(set),
.ready(ready)
);
always
#20 clk = ~clk;
always@(ready or rstn or set) begin
$display("\tTEMPO: %0t // reset: %b // ready: %b // set: %b\n", $time, rstn, ready, set);
end
initial begin
$display("==================================//\\\\==================================");
$display("| Testbench Modulo Timer: Clock = 40ns |");
$display("==================================\\\\//==================================");
clk = 0;
rstn = 0;
set = 2'b0;
/* Reset */
#40 rstn = 1;
#40 rstn = 0;
/* Teste */
#40 $display("==================================//\\\\==================================");
$display("| Teste 1: Contagem de 1s (set = 2'b01) |");
$display("==================================\\\\//==================================");
set = 2'b01;
#400060 set = 2'b00;
#40 $display("==================================//\\\\==================================");
$display("| Teste 2: Contagem de 2s (set = 2'b10) |");
$display("==================================\\\\//==================================");
set = 2'b10;
#800080 set = 2'b00;
#40 $display("==================================//\\\\==================================");
$display("| Teste 3: Contagem de 10s (set = 2'b11) |");
$display("==================================\\\\//==================================");
set = 2'b11;
# set = 2'b00;
#400
$display("==================================//\\\\==================================");
$display("| Fim do Testbench |");
$display("==================================\\\\//==================================");
$stop;
end
endmodule
|
// megafunction wizard: %ROM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cm_rom_final.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module cm_rom_final (
aclr,
address_a,
address_b,
clock,
q_a,
q_b);
input aclr;
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [3:0] q_a;
output [3:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "output_CM_final.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "output_CM_final.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 4 0 OUTPUT NODEFVAL "q_a[3..0]"
// Retrieval info: USED_PORT: q_b 0 0 4 0 OUTPUT NODEFVAL "q_b[3..0]"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 GND 0 0 4 0
// Retrieval info: CONNECT: @data_b 0 0 4 0 GND 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: CONNECT: q_b 0 0 4 0 @q_b 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_final_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; const long long int N = 1e5 + 5; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int i, j, tc; cin >> tc; while (tc--) { long long int n, w; cin >> n >> w; long long int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } vector<long long int> v; for (i = 0; i < n; i++) { if (a[i] <= w && a[i] >= (w + 1) / 2) { v.push_back(i + 1); break; } } if (v.size() == 1) { cout << 1 << n ; cout << v[0] << n ; continue; } long long int sum = 0; for (i = 0; i < n; i++) { if (a[i] <= w) { sum += a[i]; v.push_back(i + 1); if (sum >= (w + 1) / 2) break; } } if (sum >= (w + 1) / 2 && sum <= w) { cout << v.size() << n ; for (i = 0; i < v.size(); i++) cout << v[i] << ; cout << n ; } else cout << -1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, ans = 0; string s; void go(vector<char> k, pair<int, int> start, vector<string> a) { for (int i = 0; i < s.size(); i++) { if (s[i] == k[0]) { start.first--; } if (s[i] == k[1]) { start.first++; } if (s[i] == k[2]) { start.second--; } if (s[i] == k[3]) { start.second++; } if (start.first >= n || start.first < 0) { return; } if (start.second >= m || start.second < 0) { return; } if (a[start.first][start.second] == # ) { return; } if (a[start.first][start.second] == E ) { ans++; return; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; pair<int, int> start; vector<string> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; for (int j = 0; j < m; j++) { if (a[i][j] == S ) { start.first = i; start.second = j; } } } cin >> s; vector<char> k = { 0 , 1 , 2 , 3 }; do { go(k, start, a); } while (next_permutation(k.begin(), k.end())); cout << ans; return 0; }
|
/*
RC4 PRGA module implementation
Copyright 2012 - Alfredo Ortega
This library is free software: you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation, either
version 3 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
`include "rc4.inc"
module rc4(clk,rst,output_ready,password_input,K);
input clk; // Clock
input rst; // Reset
input [7:0] password_input; // Password input
output output_ready; // Output valid
output [7:0] K; // Output port
wire clk, rst; // clock, reset
reg output_ready;
wire [7:0] password_input;
/* RC4 PRGA */
// Key
reg [7:0] key[0:`KEY_SIZE-1];
// S array
reg [7:0] S[0:256];
reg [10:0] discardCount;
// Key-scheduling state
`define KSS_KEYREAD 4'h0
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO 4'h4
// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] K;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
i <= 8'h0;
KSState <= `KSS_KEYREAD;
output_ready <= 0;
j <= 0;
end
else
case (KSState)
`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
if (i == `KEY_SIZE)
begin
KSState <= `KSS_KEYSCHED1;
i<=8'h00;
end
else begin
i <= i+1;
key[i] <= password_input;
$display ("rc4: key[%d] = %08X",i,password_input);
end
end
/*
for i from 0 to 255
S[i] := i
endfor
*/
`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
S[i] <= i;
if (i == 8'hFF)
begin
KSState <= `KSS_KEYSCHED2;
i <= 8'h00;
end
else i <= i +1;
end
/*
j := 0
for i from 0 to 255
j := (j + S[i] + key[i mod keylength]) mod 256
swap values of S[i] and S[j]
endfor
*/
`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
j <= (j + S[i] + key[i % `KEY_SIZE]);
KSState <= `KSS_KEYSCHED3;
end
`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
S[i]<=S[j];
S[j]<=S[i];
if (i == 8'hFF)
begin
KSState <= `KSS_CRYPTO;
i <= 8'h01;
j <= S[1];
discardCount <= 11'h0;
output_ready <= 0; // K not valid yet
end
else begin
i <= i + 1;
KSState <= `KSS_KEYSCHED2;
end
end
/*
i := 0
j := 0
while GeneratingOutput:
i := (i + 1) mod 256
j := (j + S[i]) mod 256
swap values of S[i] and S[j]
K := S[(S[i] + S[j]) mod 256]
output K
endwhile
*/
`KSS_CRYPTO: begin
S[i] <= S[j];
S[j] <= S[i]; // We can do this because of verilog.
K <= S[ S[i]+S[j] ];
if (discardCount<11'h600) // discard first 1536 values / RFC 4345
discardCount<=discardCount+1;
else output_ready <= 1; // Valid K at output
i <= i+1;
// Here is the secret of 1-clock: we develop all possible values of j in the future
if (j==i+1)
j <= (j + S[i]);
else
if (i==255) j <= (j + S[0]);
else j <= (j + S[i+1]);
//$display ("rc4: output = %08X",K);
end
default: begin
end
endcase
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Logic Core: PCI/Avalon Bridge Megacore Function
// Company: Altera Corporation.
// www.altera.com
// Author: IPBU SIO Group
//
// Description: Avalon to PCI Variable Address Translation Table
//
// Copyright (c) 2004 Altera Corporation. All rights reserved. This source code
// is highly confidential and proprietary information of Altera and is being
// provided in accordance with and subject to the protections of a
// Non-Disclosure Agreement which governs its use and disclosure. Altera
// products and services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. Altera
// assumes no responsibility or liability arising out of the application or use
// of this source code.
//
// For Best Viewing Set tab stops to 4 spaces.
//
// $Id: //acds/main/ip/pci_express/src/rtl/lib/avalon/altpciexpav_clksync.v#8 $
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// This module contains the clock synchronization logic for a signal from clock
// domain 1 to clock domain 2.
// if the cg_common_clock_mode_i is active, signal1 will be passed through to
// signal 2 with a direct connection
module altpciexpav_clksync ( cg_common_clock_mode_i,
Clk1_i,
Clk2_i,
Clk1Rstn_i,
Clk2Rstn_i,
Sig1_i,
Sig2_o,
SyncPending_o,
Ack_o);
input cg_common_clock_mode_i;
input Clk1_i;
input Clk2_i;
input Clk1Rstn_i;
input Clk2Rstn_i;
input Sig1_i;
output Sig2_o;
output Ack_o;
output SyncPending_o;
wire input_rise;
reg input_sig_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg output1_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg output2_reg;
reg output3_reg;
reg sig2_o_reg;
reg req_reg;
reg ack_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ack1_reg;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ack2_reg;
reg ack3_reg;
reg pending_reg;
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
input_sig_reg <= 1'b0;
else
input_sig_reg <= Sig1_i;
end
// detect the rising edge of the input signal to be transfer to clock domain 2
assign input_rise = ~input_sig_reg & Sig1_i;
// input signal toggles req_reg flop. The other clock domain asserts single cycle pulse
// on edge detection
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
begin
req_reg <= 1'b0;
pending_reg <= 1'b0;
end
else
begin
if(input_rise)
req_reg <= ~req_reg;
if (input_rise)
pending_reg <= 1'b1;
else if (ack3_reg^ack2_reg)
pending_reg <= 1'b0;
end
end
// forward synch reg with double registers
always @(posedge Clk2_i or negedge Clk2Rstn_i)
begin
if(~Clk2Rstn_i)
begin
output1_reg <= 1'b0;
output2_reg <= 1'b0;
output3_reg <= 1'b0;
sig2_o_reg <= 1'b0;
ack_reg <= 1'b0;
end
else
begin
output1_reg <= req_reg;
output2_reg <= output1_reg;
output3_reg <= output2_reg;
// self clear
if (output3_reg^output2_reg)
sig2_o_reg <= 1'b1;
else
sig2_o_reg <= 1'b0;
if (output3_reg^output2_reg)
ack_reg <= ~ack_reg;
end
end
// backward synch reg. double register sync the ack signal from clock domain2
always @(posedge Clk1_i or negedge Clk1Rstn_i)
begin
if(~Clk1Rstn_i)
begin
ack1_reg <= 1'b0;
ack2_reg <= 1'b0;
ack3_reg <= 1'b0;
end
else
begin
ack1_reg <= ack_reg;
ack2_reg <= ack1_reg;
ack3_reg <= ack2_reg;
end
end
// Muxing the output based on the parameter cg_common_clock_mode_i
// the entire sync logic will be synthesized away if the same clock domain
// is used.
assign Sig2_o = (cg_common_clock_mode_i == 0) ? sig2_o_reg : input_sig_reg;
// Ackknowlege out
assign Ack_o = ack2_reg;
/// sync is pending
assign SyncPending_o = (cg_common_clock_mode_i == 0) ? pending_reg : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_PP_V
|
module uart ( input[15:0] din, output[15:0] dout, input a0, input rnw, input clk, input reset_b, input cs_b, input rxd, output txd);
// CLKSPEED is the main clock speed
parameter CLKSPEED = 32000000;
// BAUD is the desired serial baud rate
parameter BAUD = 115200;
// DIVISOR is the number of clk cycles per bit time
parameter DIVISOR = CLKSPEED / BAUD;
// Registers
reg [15:0] rx_bit_cnt = 0;
reg [15:0] tx_bit_cnt;
reg [10:0] tx_shift_reg;
reg [9:0] rx_shift_reg;
reg rxd1;
reg rxd2;
reg rx_full = 1'b0;
reg [7:0] rx_data;
wire rx_busy;
wire tx_busy;
// Assignments
assign rx_busy = rx_shift_reg != 10'b1111111111;
assign tx_busy = tx_shift_reg != 11'b1;
assign txd = tx_shift_reg[0];
assign dout = a0 ? {8'h00, rx_data} : { tx_busy, rx_full, 14'b0};
// UART Receiver
always @ (posedge clk) begin
rxd1 <= rxd;
rxd2 <= rxd1;
if (!cs_b && rnw && a0) begin
rx_full <= 1'b0;
end
if (!reset_b) begin
rx_shift_reg <= 10'b1111111111;
end else if (!rx_shift_reg[0]) begin
rx_shift_reg <= 10'b1111111111;
rx_data <= rx_shift_reg[9:2];
rx_full <= 1;
end else if (rx_busy) begin
if (rx_bit_cnt == 0) begin
rx_bit_cnt <= DIVISOR;
rx_shift_reg <= {rxd1 , rx_shift_reg[9:1]};
end else begin
rx_bit_cnt <= rx_bit_cnt - 1;
end
end else if (!rxd1 && rxd2) begin
rx_shift_reg <= 10'b0111111111;
rx_bit_cnt <= DIVISOR >> 1;
end
end
// UART Transmitter
always @ (posedge clk)
if (!reset_b) begin
tx_shift_reg <= 11'b1;
end else if (tx_busy) begin
if (tx_bit_cnt == 0) begin
tx_shift_reg <= {1'b0 , tx_shift_reg[10:1]};
tx_bit_cnt <= DIVISOR - 1;
end else begin
tx_bit_cnt <= tx_bit_cnt - 1;
end
end else if (!cs_b && !rnw && a0) begin
tx_shift_reg <= {2'b11, din[7:0], 1'b0};
tx_bit_cnt <= DIVISOR - 1;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file spartan3adsp_dmem.v when simulating
// the core, spartan3adsp_dmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module spartan3adsp_dmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3adsp"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3adsp_dmem is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_4_V
`define SKY130_FD_SC_HDLL__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); ; long long t, i, j, r, k, x, y, n, m, l, a, b, c, d = 0; cin >> t; string s, cm = abacaba ; while (t--) { cin >> l >> r; if (2 * l <= r) { cout << l << << 2 * l << n ; } else cout << -1 -1 n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, arr[100], res, maxi, mini, g; int gcd(int a, int b) { for (; b != 0; b = b % a) swap(a, b); return a; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &arr[i]); maxi = g = arr[0]; for (int i = 0; i < n; i++) { maxi = max(maxi, arr[i]); mini = min(mini, arr[i]); g = gcd(g, arr[i]); } res = (maxi / g) - n; if (res & 1) printf( Alice ); else printf( Bob ); }
|
#include <bits/stdc++.h> using namespace std; int n, b, g, ans; int main() { scanf( %d%d%d , &b, &g, &n); for (register int i = 0; i <= n; ++i) { register int a = i, f = n - i; if (a <= b && f <= g) ++ans; } printf( %d n , ans); return 0; }
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/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: hash pipelines
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
module sha256_pipe2_base ( clk, i_state, i_data, out );
parameter STAGES = 64;
input clk;
input [255:0] i_state;
input [511:0] i_data;
output [255:0] out;
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
genvar i;
generate
for (i = 0; i <= STAGES; i = i + 1) begin : S
reg [511:0] data;
reg [223:0] state;
reg [31:0] t1_p1;
if(i == 0)
begin
reg [223:0] o_state;
always @ (posedge clk)
begin
data <= i_data;
state <= i_state[223:0];
t1_p1 <= i_state[`IDX(7)] + i_data[`IDX(0)] + Ks[`IDX(63)];
end
end else
begin
reg [511:0] data_buf;
reg [223:0] state_buf;
reg [31:0] data15_p1, data15_p2, data15_p3, t1;
always @ (posedge clk)
begin
data_buf <= S[i-1].data;
data[479:0] <= data_buf[511:32];
data15_p1 <= `S1( S[i-1].data[`IDX(15)] ); // 3
data15_p2 <= data15_p1; // 1
data15_p3 <= ( ( i == 1 ) ? `S1( S[i-1].data[`IDX(14)] ) : S[i-1].data15_p2 ) + S[i-1].data[`IDX(9)] + S[i-1].data[`IDX(0)]; // 3
data[`IDX(15)] <= `S0( data_buf[`IDX(1)] ) + data15_p3; // 4
state_buf <= S[i-1].state; // 2
t1 <= `CH( S[i-1].state[`IDX(4)], S[i-1].state[`IDX(5)], S[i-1].state[`IDX(6)] ) + `E1( S[i-1].state[`IDX(4)] ) + S[i-1].t1_p1; // 6
state[`IDX(0)] <= `MAJ( state_buf[`IDX(0)], state_buf[`IDX(1)], state_buf[`IDX(2)] ) + `E0( state_buf[`IDX(0)] ) + t1; // 7
state[`IDX(1)] <= state_buf[`IDX(0)]; // 1
state[`IDX(2)] <= state_buf[`IDX(1)]; // 1
state[`IDX(3)] <= state_buf[`IDX(2)]; // 1
state[`IDX(4)] <= state_buf[`IDX(3)] + t1; // 2
state[`IDX(5)] <= state_buf[`IDX(4)]; // 1
state[`IDX(6)] <= state_buf[`IDX(5)]; // 1
t1_p1 <= state_buf[`IDX(6)] + data_buf[`IDX(1)] + Ks[`IDX((127-i) & 63)]; // 2
end
end
end
endgenerate
reg [31:0] state7, state7_buf;
always @ (posedge clk)
begin
state7_buf <= S[STAGES-1].state[`IDX(6)];
state7 <= state7_buf;
end
assign out[223:0] = S[STAGES].state;
assign out[255:224] = state7;
endmodule
module sha256_pipe130 ( clk, state, state2, data, hash );
input clk;
input [255:0] state, state2;
input [511:0] data;
output reg [255:0] hash;
wire [255:0] out;
sha256_pipe2_base #( .STAGES(64) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
always @ (posedge clk)
begin
hash[`IDX(0)] <= state2[`IDX(0)] + out[`IDX(0)];
hash[`IDX(1)] <= state2[`IDX(1)] + out[`IDX(1)];
hash[`IDX(2)] <= state2[`IDX(2)] + out[`IDX(2)];
hash[`IDX(3)] <= state2[`IDX(3)] + out[`IDX(3)];
hash[`IDX(4)] <= state2[`IDX(4)] + out[`IDX(4)];
hash[`IDX(5)] <= state2[`IDX(5)] + out[`IDX(5)];
hash[`IDX(6)] <= state2[`IDX(6)] + out[`IDX(6)];
hash[`IDX(7)] <= state2[`IDX(7)] + out[`IDX(7)];
end
endmodule
module sha256_pipe123 ( clk, data, hash );
parameter state = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
input clk;
input [511:0] data;
output [31:0] hash;
wire [255:0] out;
sha256_pipe2_base #( .STAGES(61) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
assign hash = out[`IDX(4)];
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datram.v when simulating
// the core, cx4_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [11 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("77"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3072),
.C_READ_DEPTH_B(3072),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3072),
.C_WRITE_DEPTH_B(3072),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
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