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printVectorListFour
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) { // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D<n>. SStream_concat0(O, "{"); printRegName(MI-...
pushq %rbp pushq %r15 pushq %r14 pushq %rbx pushq %rax movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 leaq 0x76a98(%rip), %rsi # 0xd4f74 movq %rdx, %rdi callq 0x44686 movq 0x320(%r14), %r15 movq %r14, %rdi movl %ebp, %esi callq 0x445a8 movq %rax, %rdi callq 0x445fe movl %eax, %edi callq *0x80(%r15) movq %rbx, %rdi...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printAddrMode6Operand
static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); unsigned tmp; SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI-...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx pushq %rax movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx callq 0x445a8 movq %rax, %r12 incl %ebp movq %rbx, %rdi movl %ebp, %esi callq 0x445a8 movq %rax, %r15 leaq 0x7ed8c(%rip), %rsi # 0xddd83 movq %r14, %rdi callq 0x44686 movq %rbx, %rdi movl $0x...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printAddrModeTBH
static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op+1); SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operan...
pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx movq %rsi, %r14 movq %rdi, %rbx xorl %esi, %esi callq 0x445a8 movq %rax, %r12 movq %rbx, %rdi movl $0x1, %esi callq 0x445a8 movq %rax, %r15 leaq 0x7da76(%rip), %rsi # 0xddd83 movq %r14, %rdi callq 0x44686 movq %rbx, %rdi movl $0x1, %esi callq 0x606ad movq 0x320...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printFBits32
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp; tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (tmp > HEX_THRESHOLD) SStream_concat(O, "#0x%x", tmp); else SStream_concat(O, "#%u", tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[M...
pushq %rbp pushq %r14 pushq %rbx movq %rsi, %r14 movq %rdi, %rbx movl $0x2, %esi callq 0x445a8 movq %rax, %rdi callq 0x44606 movl $0x20, %ebp subl %eax, %ebp cmpl $0xa, %ebp leaq 0x749b1(%rip), %rax # 0xd5136 leaq 0x749b2(%rip), %rsi # 0xd513e cmovaeq %rax, %rsi movq %r14, %rdi movl %ebp, %edx xorl %eax, %eax c...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printBitfieldInvMaskImmOperand
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); uint32_t v = ~(uint32_t)MCOperand_getImm(MO); int32_t lsb = CountTrailingZeros_32(v); int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; //assert(MO.isImm() && "Not a valid bf_inv...
pushq %rbp pushq %r15 pushq %r14 pushq %r12 pushq %rbx movq %rdx, %r14 movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x44606 xorl $-0x1, %eax movl $0x20, %r12d movl $0x20, %ebp je 0x60906 bsfl %eax, %ebp testl %eax, %eax je 0x60912 bsrl %eax, %r12d xorl $0x1f, %r12d addl %ebp, %r12d movl $0x20, %r15d subl %r12d, ...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printT2SOOperand
static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); unsigned Reg = MCOperand_getReg(MO1); printRegName(MI->csh, O, Reg); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->de...
pushq %rbp pushq %r15 pushq %r14 pushq %r12 pushq %rbx movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 callq 0x445a8 movq %rax, %r12 incl %ebp movq %r14, %rdi movl %ebp, %esi callq 0x445a8 movq %rax, %r15 movq %r12, %rdi callq 0x445fe movl %eax, %ebp movq 0x320(%r14), %rax movl %ebp, %edi callq *0x80(%rax) movq %rbx, %...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printRotImmOperand
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (Imm == 0) return; SStream_concat0(O, ", ror #"); switch (Imm) { default: //assert (0 && "illegal ror immediate!"); case 1: SStream_concat0(O, "8"); break; ...
pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r15 movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x44606 movq %rax, %r14 testl %r14d, %r14d je 0x61677 leaq 0x73c6e(%rip), %rsi # 0xd5266 movq %r15, %rdi callq 0x44686 cmpl $0x2, %r14d leaq 0x7d2e9(%rip), %rax # 0xde8f4 leaq 0x7d2cb(%rip), %rcx # 0xde8dd c...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
printT2AddrModeImm8s4Operand
static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); int32_t OffImm; bool isSub; if (!MCOperand_isReg(MO1)) { // For label symbolic references. printOperand(MI...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx pushq %rax movl %ecx, %ebp movq %rdx, %r14 movl %esi, %r13d movq %rdi, %rbx callq 0x445a8 movq %rax, %r12 leal 0x1(%r13), %esi movq %rbx, %rdi callq 0x445a8 movq %rax, %r15 movq %r12, %rdi callq 0x445e6 testb %al, %al je 0x61dd9 leaq 0x7c042(%rip), %rsi ...
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
ARM_reg_name
const char *ARM_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARM_REG_ENDING) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif }
cmpl $0x6e, %esi jbe 0x6231c xorl %eax, %eax retq movl %esi, %eax shlq $0x4, %rax leaq 0x1205e7(%rip), %rcx # 0x182910 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/ARM/ARMMapping.c
ARM_blx_to_arm_mode
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) { int i; for (i = 0; insn_blx_rel_to_arm[i]; i++) if (id == insn_blx_rel_to_arm[i]) return true; // not found return false; }
cmpl $0xa90, %esi # imm = 0xA90 sete %al retq nopl (%rax)
/sidneyp[P]capstone-tricore/arch/ARM/ARMMapping.c
DecodeTestAndBranch
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, uint64_t Addr, void *Decoder) { uint32_t Rt = fieldFromInstruction(insn, 0, 5); uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5; int32_t dst = fieldFromInstruction(insn, 5, 14); bit |= fieldFromInstruction(insn, 19, 5); // Sign-extend 1...
pushq %rbp pushq %r14 pushq %rbx movl %esi, %r14d movq %rdi, %rbx movl %esi, %eax andl $0x1f, %eax testl %esi, %esi leaq 0x703c2(%rip), %rcx # 0xd6640 leaq 0x704bb(%rip), %rdx # 0xd6740 cmovnsq %rcx, %rdx movl (%rdx,%rax,4), %esi callq 0x44631 movl %r14d, %ebp shll $0xd, %ebp sarl $0x1f, %ebp movl %r14d, %eax s...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64Disassembler.c
AArch64_printInst
void AArch64_printInst(MCInst *MI, SStream *O, void *Info) { // Check for special encodings and print the canonical alias instead. unsigned Opcode = MCInst_getOpcode(MI); int LSB; int Width; char *mnem; if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) return; // SBFM/UBFM should print to a nicer aliased ...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x38, %rsp movq %rdx, %rbx movq %rsi, %r12 movq %rdi, %r13 callq 0x445a1 cmpl $0x7c2, %eax # imm = 0x7C2 jne 0x6693f movq %rbx, (%rsp) movq %r12, 0x10(%rsp) movq %r13, %rdi xorl %esi, %esi callq 0x445a8 movq %rax, %r14 movq %r13, %rdi mo...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
printTypedVectorList
static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind, MCRegisterInfo *MRI) { char Suffix[32]; arm64_vas vas = 0; arm64_vess vess = 0; if (NumLanes) { cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); switch(LaneKind) { default: break; c...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x38, %rsp movq %r9, %r15 movq %rdx, 0x8(%rsp) movl %esi, %ebp movq %rdi, %r14 movsbl %r8b, %ebx testl %ecx, %ecx je 0x81682 movl %ecx, %r12d leaq 0x5c851(%rip), %rdx # 0xdde76 movl $0x0, 0x4(%rsp) leaq 0x10(%rsp), %rdi movl $0x20, %esi xorl %e...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
printSysCROperand
static void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); SStream_concat(O, "c%u", MCOperand_getImm(Op)); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat...
pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r15 movq %rdi, %rbx callq 0x445a8 movq %rax, %r14 movq %rax, %rdi callq 0x44606 leaq 0x52edf(%rip), %rsi # 0xd5120 movq %r15, %rdi movq %rax, %rdx xorl %eax, %eax callq 0x446cd movq 0x320(%rbx), %rax cmpl $0x0, 0x68(%rax) je 0x822b5 movq 0x310(%rbx), %rax movq 0xe8(%rax)...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
printLogicalImm64
static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) { int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); Val = AArch64_AM_decodeLogicalImmediate(Val, 64); switch(MI->flat_insn->id) { default: printInt64Bang(O, Val); break; case ARM64_INS_ORR: case ARM64_INS_AND: case ARM64...
pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r14 movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x44606 movl %eax, %edi shrl $0x6, %edi andl $0x3f, %eax movl %edi, %ecx andl $0x40, %ecx orl %eax, %ecx xorl $0x3f, %ecx movl $0xffffffff, %edx # imm = 0xFFFFFFFF movl %edx, %esi leal 0x1(%rsi), %edx cmpl $0x1d, ...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
printArithExtend
static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); // If the destination or first source regi...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx pushq %rax movq %rdx, %r15 movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x44606 movq %rax, %r14 shrl $0x3, %eax andl $0x7, %eax leaq 0x558cc(%rip), %rcx # 0xd815c movslq (%rcx,%rax,4), %rax addq %rcx, %rax jmpq *%rax movl $0x5, %r12d jmp 0x829...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
AArch64_group_name
const char *AArch64_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET // verify group id if (id >= ARM64_GRP_ENDING || (id > ARM64_GRP_JUMP && id < ARM64_GRP_CRYPTO)) return NULL; // NOTE: when new generic groups are added, 2 must be changed accordingly if (id >= 128) return group_name_maps[id - ...
cmpl $0x84, %esi setae %al leal -0x2(%rsi), %ecx cmpl $0x7e, %ecx setb %cl orb %al, %cl je 0x82e57 xorl %eax, %eax retq leal -0x7e(%rsi), %eax cmpl $0x7f, %esi cmovbel %esi, %eax shlq $0x4, %rax leaq 0x103685(%rip), %rcx # 0x1864f0 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64Mapping.c
DecodeCOP3Mem
static DecodeStatus DecodeCOP3Mem(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); Base = g...
pushq %rbp pushq %r15 pushq %r14 pushq %rbx pushq %rax movq %rdx, %r15 movl %esi, %r14d movq %rdi, %rbx movq %rdx, %rdi movl $0x3, %esi callq 0x475fa movq 0x8(%rax), %rax movl %r14d, %ecx shrl $0xf, %ecx andl $0x3e, %ecx movzwl (%rax,%rcx), %ebp movq %r15, %rdi movl $0x8, %esi callq 0x475fa movq 0x8(%rax), %rax movl %r...
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo >= 4) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0x3, %esi ja 0x86af9 pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rdx, %rdi movl $0x14, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo >= 4) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0x3, %esi ja 0x86b33 pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rdx, %rdi movl $0x15, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0x1f, %esi ja 0x86c1b pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rdx, %rdi movl $0x1b, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0x1f, %esi ja 0x86d47 pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rcx, %rdi movl $0x2d, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeFGRCCRegisterClass
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0x1f, %esi ja 0x873ee pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rdx, %rdi movl $0x6, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0x1f, %esi ja 0x87428 pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rdx, %rdi movl $0x2, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
DecodeDaddiGroupBranch_4
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier // ISA's instead). // // We have: // 0b011000...
pushq %rbp pushq %r15 pushq %r14 pushq %r12 pushq %rbx movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx movl %esi, %r15d shrl $0x15, %r15d andl $0x1f, %r15d movl %esi, %r12d shrl $0x10, %r12d andl $0x1f, %r12d movl $0x111, %esi # imm = 0x111 cmpl %r12d, %r15d jae 0x875c7 movl $0x103, %esi # imm = 0...
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
printMemOperand
static void printMemOperand(MCInst *MI, int opNum, SStream *O) { // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) set_mem_access(MI, true); printOperand(MI, opNum + 1, O); SStream_concat0(O, "("); printOperand(MI, opNum, O); SStream_concat0(O...
pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r14 movl %esi, %r15d movq %rdi, %rbx movl $0x1, %esi callq 0x89953 leal 0x1(%r15), %esi movq %rbx, %rdi movq %r14, %rdx callq 0x894a6 leaq 0x429c0(%rip), %rsi # 0xcc1b7 movq %r14, %rdi callq 0x44686 movq %rbx, %rdi movl %r15d, %esi movq %r14, %rdx callq 0x894a6 leaq 0xbd...
/sidneyp[P]capstone-tricore/arch/Mips/MipsInstPrinter.c
printUnsignedImm8
static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, opNum); if (MCOperand_isImm(MO)) { uint8_t imm = (uint8_t)MCOperand_getImm(MO); if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%x", imm); else SStream_concat(O, "%u", imm); if (MI->csh->detail) { M...
pushq %rbp pushq %r15 pushq %r14 pushq %rbx pushq %rax movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx callq 0x445a8 movq %rax, %r15 movq %rax, %rdi callq 0x445ee testb %al, %al je 0x8993c movq %r15, %rdi callq 0x44606 movq %rax, %r15 movzbl %r15b, %edx cmpl $0xa, %edx leaq 0x5d9a4(%rip), %rax # 0xe7265 leaq 0x4280...
/sidneyp[P]capstone-tricore/arch/Mips/MipsInstPrinter.c
Mips_reg_name
const char *Mips_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= MIPS_REG_ENDING) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif }
cmpl $0x87, %esi jbe 0x899d7 xorl %eax, %eax retq movl %esi, %eax shlq $0x4, %rax leaq 0xfcb6c(%rip), %rcx # 0x186550 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsMapping.c
Mips_group_name
const char *Mips_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET // verify group id if (id >= MIPS_GRP_ENDING || (id > MIPS_GRP_JUMP && id < MIPS_GRP_BITCOUNT)) return NULL; // NOTE: when new generic groups are added, 2 must be changed accordingly if (id >= 128) return group_name_maps[id - 128 ...
cmpl $0xa1, %esi setae %al leal -0x2(%rsi), %ecx cmpl $0x7e, %ecx setb %cl orb %al, %cl je 0x89af6 xorl %eax, %eax retq leal -0x7e(%rsi), %eax cmpl $0x7f, %esi cmovbel %esi, %eax shlq $0x4, %rax leaq 0xfd2c6(%rip), %rcx # 0x186dd0 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/Mips/MipsMapping.c
Mips_map_register
mips_reg Mips_map_register(unsigned int r) { // for some reasons different Mips modes can map different register number to // the same Mips register. this function handles the issue for exposing Mips // operands by mapping internal registers to 'public' register. unsigned int map[] = { 0, MIPS_REG_AT, MIPS_REG_DS...
xorl %eax, %eax cmpl $0x189, %edi # imm = 0x189 ja 0x89b45 movl %edi, %eax leaq 0x59b5e(%rip), %rcx # 0xe36a0 movl (%rcx,%rax,4), %eax retq nop
/sidneyp[P]capstone-tricore/arch/Mips/MipsMapping.c
decodeMemRIOperands
static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the memri field (imm, reg), which has the low 16-bits as the // displacement and the next 5 bits as the register #. uint64_t Base = Imm >> 16; uint64_t Disp = Imm & 0xFFFF; // assert(Base < 32 ...
xorl %eax, %eax cmpq $0x1fffff, %rsi # imm = 0x1FFFFF ja 0x8aff0 pushq %r15 pushq %r14 pushq %rbx movq %rsi, %r14 movq %rdi, %rbx movq %rsi, %r15 shrq $0x10, %r15 callq 0x445a1 leal -0x262(%rax), %ecx cmpl $0x30, %ecx jbe 0x8afa4 leal -0x347(%rax), %ecx cmpl $0x29, %ecx ja 0x8aff1 movabsq $0x20001042001, %rdx ...
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCDisassembler.c
printS16ImmOperand
static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); if (Imm >= 0) { if (Imm > HEX_THRESHOLD) SStream_concat(O, "0x%x", Imm); else SStream_concat(O, "%u", Imm); }...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x445ee testb %al, %al je 0x9cc6b movq %rbx, %rdi movl %ebp, %esi callq 0x445a8 movq %rax, %rdi callq 0x44606 movswl %ax, %ebp testl %ebp, %ebp js 0x9cc7c cmpl $0xa, %ebp jb 0x9cc8e leaq 0x4a5fc(%rip), %...
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
printU16ImmOperand
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); if (Imm > HEX_THRESHOLD) SStream_concat(O, "0x%x", Imm); else SStream_concat(O, "%u", Imm); if (...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x445ee testb %al, %al je 0x9cdb6 movq %rbx, %rdi movl %ebp, %esi callq 0x445a8 movq %rax, %rdi callq 0x44606 movzwl %ax, %ebp cmpl $0xa, %ebp leaq 0x4a51f(%rip), %rax # 0xe7265 leaq 0x2f389(%rip), %...
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
printMemRegReg
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin // assembler requires that we print r0 as 0 (no r) when used as the base. if (MCOperand_getReg(MCInst_getOper...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 callq 0x445a8 movq %rax, %rdi callq 0x445fe cmpl $0x36, %eax jne 0x9d1d5 leaq 0x4aad8(%rip), %rsi # 0xe7ca3 movq %rbx, %rdi callq 0x44686 jmp 0x9d1e2 movq %r14, %rdi movl %ebp, %esi movq %rbx, %rdx callq 0x8c65c leaq 0x37e59(%rip), %rs...
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
set_mem_access
static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (status) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.b...
movq 0x320(%rdi), %rax cmpl $0x3, 0x68(%rax) jne 0x9d6ab movb %sil, 0x70(%rax) movq 0x310(%rdi), %rax movq 0xe8(%rax), %rax testb %sil, %sil je 0x9d6a8 movzbl 0x39(%rax), %ecx shll $0x4, %ecx movl $0x3, 0x3c(%rax,%rcx) movq 0x310(%rdi), %rax movq 0xe8(%rax), %rax movzbl 0x39(%rax), %ecx shll $0x4, %ecx xorl %edx, %edx ...
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
PPC_group_name
const char *PPC_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET // verify group id if (id >= PPC_GRP_ENDING || (id > PPC_GRP_JUMP && id < PPC_GRP_ALTIVEC)) return NULL; // NOTE: when new generic groups are added, 2 must be changed accordingly if (id >= 128) return group_name_maps[id - 128 + 2]....
cmpl $0x8a, %esi setae %al leal -0x2(%rsi), %ecx cmpl $0x7e, %ecx setb %cl orb %al, %cl je 0x9d808 xorl %eax, %eax retq leal -0x7e(%rsi), %eax cmpl $0x7f, %esi cmovbel %esi, %eax shlq $0x4, %rax leaq 0xea344(%rip), %rcx # 0x187b60 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCMapping.c
printDstIdx
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) { if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx movq 0x320(%rdi), %rax cmpl $0x0, 0x68(%rax) je 0xa0bba movq 0x310(%rbx), %rax movq 0xe8(%rax), %rax movzbl 0x5c(%rax), %ecx leaq (%rcx,%rcx,2), %rcx shll $0x4, %ecx movl $0x3, 0x60(%rax,%rcx) movb 0x328(%rbx), %al movq 0x310(%rbx), %rcx m...
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
printopaquemem
static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "ptr "); switch(MI->csh->mode) { case CS_MODE_16: if (MI->flat_insn->id == X86_INS_LJMP || MI->flat_insn->id == X86_INS_LCALL) MI->x86opsize = 4; else MI->x86opsize = 2; break; case CS_MODE_32: if (MI->flat...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 leaq 0xa4534(%rip), %rsi # 0x146ec0 movq %rdx, %rdi callq 0x44686 movq 0x320(%r14), %rax movl 0x4(%rax), %eax cmpl $0x8, %eax je 0xa29f1 cmpl $0x4, %eax je 0xa29ca cmpl $0x2, %eax jne 0xa2a16 movq 0x310(%r14), %rax movl (%rax), %eax an...
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
printRoundingControl
static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O) { int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3; switch (Imm) { case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break; case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI...
pushq %rbp pushq %r14 pushq %rbx movq %rsi, %r14 movq %rdi, %rbx movl $0x2, %esi callq 0x445a8 movq %rax, %rdi callq 0x44606 andl $0x3, %eax leaq 0xa4314(%rip), %rcx # 0x146ea0 movslq (%rcx,%rax,4), %rsi addq %rcx, %rsi leal 0x1(%rax), %ebp movq %r14, %rdi callq 0x44686 movq %rbx, %rdi callq 0xa3e55 movq %rbx, %rdi...
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
printMemReference
static void printMemReference(MCInst *MI, unsigned Op, SStream *O) { bool NeedPlus = false; MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); MCO...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x28, %rsp movq %rdx, 0x18(%rsp) movl %esi, %ebp movq %rdi, %rbx callq 0x445a8 movq %rax, %r12 leal 0x1(%rbp), %esi movq %rbx, %rdi callq 0x445a8 movq %rax, %rdi callq 0x44606 movq %rax, %r13 leal 0x2(%rbp), %esi movq %rbx, %rdi movl %esi, 0xc(%rsp...
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
printMemOffset
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) { MCOperand *DispSpec = MCInst_getOperand(MI, Op); MCOperand *SegReg = MCInst_getOperand(MI, Op + 1); int reg; if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail...
pushq %rbp pushq %r15 pushq %r14 pushq %rbx pushq %rax movq %rsi, %r14 movq %rdi, %rbx xorl %ebp, %ebp xorl %esi, %esi callq 0x445a8 movq %rax, %r15 movq %rbx, %rdi movl $0x1, %esi callq 0x445a8 movq 0x320(%rbx), %rcx cmpl $0x0, 0x68(%rcx) je 0xa305c movq 0x310(%rbx), %rcx movq 0xe8(%rcx), %rcx movzbl 0x5c(%rcx), %edx ...
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
X86_get_insn_id
void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->re...
pushq %rbp pushq %r15 pushq %r14 pushq %rbx pushq %rax movl %edx, %ebp movq %rsi, %rbx movq %rdi, %r15 leaq 0x78(%rdi), %rcx leaq 0x189181(%rip), %r14 # 0x22c3f0 movq %r14, %rdi movl $0x1726, %esi # imm = 0x1726 callq 0x47614 testw %ax, %ax je 0xa3793 movzwl %ax, %eax imulq $0x2e, %rax, %rax movzwl 0x2(%ra...
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
X86_insn_reg_intel
x86_reg X86_insn_reg_intel(unsigned int id) { unsigned int i; for (i = 0; i < ARR_SIZE(insn_regs_intel); i++) { if (insn_regs_intel[i].insn == id) { return insn_regs_intel[i].reg; } } // not found return 0; }
xorl %eax, %eax leaq 0xa3b49(%rip), %rcx # 0x1472f0 movzwl (%rcx,%rax,8), %edx cmpl %edi, %edx je 0xa37bb incq %rax cmpq $0x6f, %rax jne 0xa37a7 xorl %eax, %eax retq movl 0x4(%rcx,%rax,8), %eax retq
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
X86_insn_reg_att2
bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2) { unsigned int i; for (i = 0; i < ARR_SIZE(insn_regs_intel2); i++) { if (insn_regs_intel2[i].insn == id) { // reverse order of Intel syntax registers *reg1 = insn_regs_intel2[i].reg2; *reg2 = insn_regs_intel2[i].reg1; return true; ...
cmpl $0x37f, %edi # imm = 0x37F jne 0xa3820 leaq 0xa3e54(%rip), %rcx # 0x147670 movb $0x1, %al jmp 0xa384c movq $-0x1, %rax leaq 0xa3e42(%rip), %rcx # 0x147670 cmpq $0x4, %rax je 0xa3857 movzwl 0xc(%rcx), %r8d addq $0xc, %rcx incq %rax cmpl %edi, %r8d jne 0xa382e cmpq $0x5, %rax setb %al movl 0x4(%rc...
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
add_cx
static void add_cx(MCInst *MI) { if (MI->csh->detail) { x86_reg cx; if (MI->csh->mode & CS_MODE_16) cx = X86_REG_CX; else if (MI->csh->mode & CS_MODE_32) cx = X86_REG_ECX; else // 64-bit cx = X86_REG_RCX; MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = cx; MI->flat_ins...
movq 0x320(%rdi), %rax cmpl $0x0, 0x68(%rax) je 0xa3c5a movl 0x4(%rax), %eax testb $0x4, %al sete %cl shlb $0x4, %cl addb $0x16, %cl testb $0x2, %al movzbl %cl, %eax movl $0xc, %ecx cmovel %eax, %ecx movq 0x310(%rdi), %rax movq 0xe8(%rax), %rax movzbl 0xc(%rax), %edx movb %cl, (%rax,%rdx) movq 0x310(%rdi), %rax movq 0x...
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
op_addReg
void op_addReg(MCInst *MI, int reg) { if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].siz...
movq 0x320(%rdi), %rax cmpl $0x0, 0x68(%rax) movslq %esi, %rax je 0xa3cef movq 0x310(%rdi), %rcx movq 0xe8(%rcx), %rcx movzbl 0x5c(%rcx), %edx leaq (%rdx,%rdx,2), %rdx shll $0x4, %edx movl $0x1, 0x60(%rcx,%rdx) movq 0x310(%rdi), %rcx movq 0xe8(%rcx), %rcx movzbl 0x5c(%rcx), %edx leaq (%rdx,%rdx,2), %rdx shll $0x4, %edx...
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
op_addImm
void op_addImm(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v; // if op_count > 0, then this operand's size is taken from the destination op ...
movq 0x320(%rdi), %rax cmpl $0x0, 0x68(%rax) je 0xa3dbb movq 0x310(%rdi), %rax movq 0xe8(%rax), %rax movzbl 0x5c(%rax), %ecx leaq (%rcx,%rcx,2), %rcx shll $0x4, %ecx movl $0x2, 0x60(%rax,%rcx) movslq %esi, %rax movq 0x310(%rdi), %rcx movq 0xe8(%rcx), %rcx movzbl 0x5c(%rcx), %edx leaq (%rdx,%rdx,2), %rdx shll $0x4, %edx...
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
Sparc_getInstruction
static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn) { uint8_t Bytes[4]; if (len < 4) // not enough data return MCDisassembler_Fail; memcpy(Bytes, code, 4); // Encoded as a big-endian 32-bit word in the stream. *Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << ...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x28, %rsp cmpq $0x4, %rdx jae 0xa3ebc xorl %r15d, %r15d jmp 0xa4b8f movq %r9, %rbx movq %r8, 0x20(%rsp) movzbl (%rsi), %ebp movzbl 0x1(%rsi), %r15d movzbl 0x2(%rsi), %eax movzbl 0x3(%rsi), %esi movq %rax, 0x18(%rsp) shll $0x8, %eax movl %r15d, %r1...
/sidneyp[P]capstone-tricore/arch/Sparc/SparcDisassembler.c
DecodeJMPL
static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { DecodeStatus status; unsigned rd = fieldFromInstruction_4(insn, 25, 5); unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); unsigned isImm = fieldFromInstruction_4(insn, 13, 1); unsigned rs2 = 0; unsigned simm13 =...
pushq %r15 pushq %r14 pushq %rbx movl %esi, %r14d movq %rdi, %rbx movl %esi, %eax shrl $0x17, %eax andl $0x7c, %eax leaq 0xa51ed(%rip), %r15 # 0x149e80 movl (%rax,%r15), %esi callq 0x44631 movl %r14d, %eax shrl $0xc, %eax andl $0x7c, %eax movl (%rax,%r15), %esi movq %rbx, %rdi callq 0x44631 btl $0xd, %r14d jb 0xa4c...
/sidneyp[P]capstone-tricore/arch/Sparc/SparcDisassembler.c
DecodeReturn
static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { DecodeStatus status; unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); unsigned isImm = fieldFromInstruction_4(insn, 13, 1); unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) simm13 = SignExtend32(fieldFromI...
pushq %r15 pushq %r14 pushq %rbx movl %esi, %r14d movq %rdi, %rbx movl %esi, %eax shrl $0xe, %eax andl $0x1f, %eax btl $0xd, %esi jb 0xa4d28 andl $0x1f, %r14d movl %eax, %eax leaq 0xa5172(%rip), %r15 # 0x149e80 movl (%r15,%rax,4), %esi movq %rbx, %rdi callq 0x44631 movl (%r15,%r14,4), %esi movq %rbx, %rdi callq 0x4...
/sidneyp[P]capstone-tricore/arch/Sparc/SparcDisassembler.c
printOperand
static void printOperand(MCInst *MI, int opNum, SStream *O) { int Imm; unsigned reg; MCOperand *MO = MCInst_getOperand(MI, opNum); if (MCOperand_isReg(MO)) { reg = MCOperand_getReg(MO); printRegName(O, reg); reg = Sparc_map_register(reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { if (MI->fla...
pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r14 movq %rdi, %rbx callq 0x445a8 movq %rax, %r15 movq %rax, %rdi callq 0x445e6 testb %al, %al je 0xbb3d4 movq %r15, %rdi callq 0x445fe movl %eax, %r15d leaq 0x912ad(%rip), %rsi # 0x14c60b movq %r14, %rdi callq 0x44686 leal -0x1(%r15), %eax leaq 0x8f01f(%rip), %rcx #...
/sidneyp[P]capstone-tricore/arch/Sparc/SparcInstPrinter.c
set_mem_access
static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (status) { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_co...
movq 0x320(%rdi), %rax cmpl $0x3, 0x68(%rax) jne 0xbb673 movb %sil, 0x70(%rax) movq 0x310(%rdi), %rax movq 0xe8(%rax), %rax testb %sil, %sil je 0xbb670 movzbl 0x38(%rax), %ecx leaq (%rcx,%rcx,2), %rcx movl $0x3, 0x3c(%rax,%rcx,4) movq 0x310(%rdi), %rax movq 0xe8(%rax), %rax movzbl 0x38(%rax), %ecx leaq (%rcx,%rcx,2), %...
/sidneyp[P]capstone-tricore/arch/Sparc/SparcInstPrinter.c
Sparc_get_insn_id
void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned short i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); ...
pushq %r15 pushq %r14 pushq %r12 pushq %rbx pushq %rax movl %edx, %ebx movq %rsi, %r14 movq %rdi, %r12 leaq 0x78(%rdi), %rcx leaq 0x1b78ce(%rip), %r15 # 0x2730a0 movq %r15, %rdi movl $0x1b9, %esi # imm = 0x1B9 callq 0x47614 testw %ax, %ax je 0xbb8ae movzwl %ax, %eax imulq $0x2e, %rax, %rax movzwl 0x2(%rax...
/sidneyp[P]capstone-tricore/arch/Sparc/SparcMapping.c
Sparc_group_name
const char *Sparc_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET // verify group id if (id >= SPARC_GRP_ENDING || (id > SPARC_GRP_JUMP && id < SPARC_GRP_HARDQUAD)) return NULL; // NOTE: when new generic groups are added, 2 must be changed accordingly if (id >= 128) return group_name_maps[id - ...
cmpl $0x87, %esi setae %al leal -0x2(%rsi), %ecx cmpl $0x7e, %ecx setb %cl orb %al, %cl je 0xbb8f6 xorl %eax, %eax retq leal -0x7e(%rsi), %eax cmpl $0x7f, %esi cmovbel %esi, %eax shlq $0x4, %rax leaq 0xd3016(%rip), %rcx # 0x18e920 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/Sparc/SparcMapping.c
decodeBDLAddr64Disp12Len8Operand
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); }
pushq %r15 pushq %r14 pushq %rbx movq %rsi, %rbx movq %rdi, %r14 movl %ebx, %eax shrl $0xc, %eax andl $0xf, %eax je 0xbd528 leaq 0x91e3d(%rip), %rcx # 0x14f360 movl (%rcx,%rax,4), %esi jmp 0xbd52a xorl %esi, %esi movl %ebx, %r15d andl $0xfff, %r15d # imm = 0xFFF shrq $0x10, %rbx movq %r14, %rdi callq 0x44...
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZDisassembler.c
printCond4Operand
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) { static char *const CondNames[] = { "o", "h", "nle", "l", "nhe", "lh", "ne", "e", "nlh", "he", "nl", "le", "nh", "no" }; uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(Imm > 0 && Imm < 15 && "Invalid condition"); SStre...
pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r15 movq %rdi, %rbx callq 0x445a8 movq %rax, %rdi callq 0x44606 movq %rax, %r14 leaq 0x902ce(%rip), %rax # 0x14e434 movslq -0x4(%rax,%r14,4), %rsi addq %rax, %rsi movq %r15, %rdi callq 0x44686 movq 0x320(%rbx), %rax cmpl $0x0, 0x68(%rax) je 0xbe195 movq 0x310(%rbx), %rax...
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZInstPrinter.c
printU6ImmOperand
static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O) { uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<6>(Value) && "Invalid u6imm argument"); if (Value > HEX_THRESHOLD) SStream_concat(O, "0x%x", Value); else SStream_concat(O, "%u", Value); if (MI->csh-...
pushq %r15 pushq %r14 pushq %rbx movq %rsi, %r15 movq %rdi, %rbx movl $0x5, %esi callq 0x445a8 movq %rax, %rdi callq 0x44606 movq %rax, %r14 cmpl $0xa, %r14d leaq 0x28b88(%rip), %rax # 0xe7265 leaq 0xd9f2(%rip), %rsi # 0xcc0d6 cmovaeq %rax, %rsi movq %r15, %rdi movl %r14d, %edx xorl %eax, %eax callq 0x446cd mo...
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZInstPrinter.c
SystemZ_reg_name
const char *SystemZ_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= SYSZ_REG_ENDING) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif }
cmpl $0x22, %esi jbe 0xbe930 xorl %eax, %eax retq movl %esi, %eax shlq $0x4, %rax leaq 0xd00a3(%rip), %rcx # 0x18e9e0 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZMapping.c
SystemZ_insn_name
const char *SystemZ_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET unsigned int i; if (id >= SYSZ_INS_ENDING) return NULL; // handle special alias first for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { if (alias_insn_names[i].id == id) return alias_insn_names[i].name; } return insn_nam...
leal -0x2aa(%rsi), %eax cmpl $0xfffffd57, %eax # imm = 0xFFFFFD57 jae 0xbea28 xorl %eax, %eax retq movl %esi, %eax shlq $0x4, %rax leaq 0xd01db(%rip), %rcx # 0x18ec10 movq 0x8(%rax,%rcx), %rax retq
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZMapping.c
SystemZ_map_register
sysz_reg SystemZ_map_register(unsigned int r) { static unsigned int map[] = { 0, SYSZ_REG_CC, SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F2, SYSZ_REG_F3, SYSZ_REG_F4, SYSZ_REG_F5, SYSZ_REG_F6, SYSZ_REG_F7, SYSZ_REG_F8, SYSZ_REG_F9, SYSZ_REG_F10, SYSZ_REG_F11, SYSZ_REG_F12, SYSZ_REG_F13, SYSZ_REG_F14, SYSZ_REG_F15, SYS...
xorl %eax, %eax cmpl $0x61, %edi ja 0xbea81 movl %edi, %eax leaq 0x8fa22(%rip), %rcx # 0x14e4a0 movl (%rcx,%rax,4), %eax retq nop
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZMapping.c
DecodeGRRegsRegisterClass
static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder) { unsigned Reg; if (RegNo > 11) return MCDisassembler_Fail; Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; }
xorl %eax, %eax cmpl $0xb, %esi ja 0xbf5d0 pushq %rbp pushq %rbx pushq %rax movl %esi, %ebp movq %rdi, %rbx movq %rdx, %rdi movl $0x1, %esi callq 0x475fa movq 0x8(%rax), %rax movl %ebp, %ecx movzwl (%rax,%rcx,2), %esi movq %rbx, %rdi callq 0x44631 movl $0x3, %eax addq $0x8, %rsp popq %rbx popq %rbp retq
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
Decode2RUSInstruction
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(I...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %r14 movl %esi, %eax movq %rdi, %rbx leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx leaq 0x4(%rsp), %rcx movl %eax, %edi callq 0xc0175 movl %eax, %ebp cmpl $0x3, %eax jne 0xbf68f movl 0xc(%rsp), %esi movq %rbx, %rdi movq %r14, %rdx callq 0xbf597 movl 0x8(%rsp), %e...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeR2RInstruction
static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 leaq 0x8(%rsp), %rsi leaq 0xc(%rsp), %rdx movl %ebp, %edi callq 0xbffb9 cmpl $0x3, %eax jne 0xbf6ec movl 0xc(%rsp), %esi movq %r14, %rdi movq %rbx, %rdx callq 0xbf597 movl 0x8(%rsp), %esi movq %r14, %rdi movq %rbx, %rdx ca...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
Decode2RImmInstruction
static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); MCOperand_CreateImm0(Inst, Op1);...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx movl %ebp, %edi callq 0xbffb9 cmpl $0x3, %eax jne 0xbf7b5 movl 0xc(%rsp), %esi movq %r14, %rdi callq 0x4465e movl 0x8(%rsp), %esi movq %r14, %rdi movq %rbx, %rdx callq 0xbf597 movl...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
Decode2RSrcDstInstruction
static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Ins...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx movl %ebp, %edi callq 0xbffb9 cmpl $0x3, %eax jne 0xbf82b movl 0xc(%rsp), %ebp movq %r14, %rdi movl %ebp, %esi movq %rbx, %rdx callq 0xbf597 movq %r14, %rdi movl %ebp, %esi movq %r...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeRUSSrcDstBitpInstruction
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClas...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx movl %ebp, %edi callq 0xbffb9 cmpl $0x3, %eax jne 0xbf8ae movl 0xc(%rsp), %ebp movq %rbx, %rdi movl %ebp, %esi movq %r14, %rdx callq 0xbf597 movq %rbx, %rdi movl %ebp, %esi movq %r...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeRUSBitpInstruction
static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %r14 movl %esi, %ebp movq %rdi, %rbx leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx movl %ebp, %edi callq 0xbffb9 cmpl $0x3, %eax jne 0xbf9bd movl 0xc(%rsp), %esi movq %rbx, %rdi movq %r14, %rdx callq 0xbf597 movl 0x8(%rsp), %eax cmpq $0xb, %rax ja 0xbf9af leaq 0x...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
Decode2RUSBitpInstruction
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterCla...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %r14 movl %esi, %eax movq %rdi, %rbx leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx leaq 0x4(%rsp), %rcx movl %eax, %edi callq 0xc0175 movl %eax, %ebp cmpl $0x3, %eax jne 0xbfa39 movl 0xc(%rsp), %esi movq %rbx, %rdi movq %r14, %rdx callq 0xbf597 movl 0x8(%rsp), %e...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
Decode3RImmInstruction
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { MCOperand_CreateImm0(Inst, Op1); DecodeGRRegsRegisterClass(Inst, Op2, Address, Dec...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %rbx movl %esi, %eax movq %rdi, %r14 leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx leaq 0x4(%rsp), %rcx movl %eax, %edi callq 0xc0175 movl %eax, %ebp cmpl $0x3, %eax jne 0xbfa9b movl 0xc(%rsp), %esi movq %r14, %rdi callq 0x4465e movl 0x8(%rsp), %esi movq %r14, %r...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeL4RSrcDstInstruction
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2, Op3; unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success...
pushq %rbp pushq %r14 pushq %rbx subq $0x10, %rsp movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 movzwl %bp, %edi leaq 0xc(%rsp), %rsi leaq 0x8(%rsp), %rdx leaq 0x4(%rsp), %rcx callq 0xc0175 cmpl $0x3, %eax jne 0xbfbf5 shrl $0x10, %ebp andl $0xf, %ebp movl 0xc(%rsp), %esi movq %r14, %rdi movq %rbx, %rdx callq 0xbf597 ...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeL5RInstruction
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2, Op3, Op4, Op5; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S != MCDisassembler_Success) return DecodeL5RInstructionFail(Inst, Insn, A...
pushq %rbp pushq %r14 pushq %rbx subq $0x20, %rsp movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 movzwl %bp, %edi leaq 0x1c(%rsp), %rsi leaq 0x18(%rsp), %rdx leaq 0x14(%rsp), %rcx callq 0xc0175 cmpl $0x3, %eax jne 0xbfd3e movl %ebp, %edi shrl $0x10, %edi leaq 0x10(%rsp), %rsi leaq 0xc(%rsp), %rdx callq 0xbffb9 cmpl $0...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeL6RInstruction
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Op1, Op2, Op3, Op4, Op5, Op6; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S != MCDisassembler_Success) return S; S = Decode3OpInstruction(fie...
pushq %rbp pushq %r14 pushq %rbx subq $0x20, %rsp movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 movzwl %bp, %edi leaq 0x1c(%rsp), %rsi leaq 0x18(%rsp), %rdx leaq 0x14(%rsp), %rcx callq 0xc0175 cmpl $0x3, %eax jne 0xbfdfc shrl $0x10, %ebp leaq 0x10(%rsp), %rsi leaq 0xc(%rsp), %rdx leaq 0x8(%rsp), %rcx movl %ebp, %edi ...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
Decode2OpInstructionFail
static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { // Try and decode as a 3R instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); switch (Opcode) { case 0x0: MCInst_setOpcode(Inst, XCore_STW_2rus); return Decode2RUSInstruction(Inst, I...
pushq %rbp pushq %r14 pushq %rbx movl %esi, %eax shrl $0xb, %eax andl $0x1f, %eax cmpl $0x19, %eax ja 0xc00ad movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 leaq 0x8f5be(%rip), %rcx # 0x14f5f0 movslq (%rcx,%rax,4), %rax addq %rcx, %rax jmpq *%rax movq %r14, %rdi movl $0xe4, %esi jmp 0xc015f movq %r14, %rdi movl $0...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeL2OpInstructionFail
static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { // Try and decode as a L3R / L2RUS instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | fieldFromInstruction_4(Insn, 27, 5) << 4; switch (Opcode) { case 0x0c: MCInst_setOpcode(Inst, ...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 movl %esi, %ecx shrl $0x10, %ecx andl $0xf, %ecx movl %esi, %eax shrl $0x17, %eax andl $-0x10, %eax orl %ecx, %eax cmpl $0x10b, %eax # imm = 0x10B jg 0xc024a cmpl $0x5b, %eax jg 0xc028a cmpl $0x2b, %eax jle 0xc02f8 cmpl $0x2c, %...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
DecodeL5RInstructionFail
static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { unsigned Opcode; // Try and decode as a L6R instruction. MCInst_clear(Inst); Opcode = fieldFromInstruction_4(Insn, 27, 5); switch (Opcode) { default: break; case 0x00: MCInst_setOpcode(Inst, XC...
pushq %rbp pushq %r14 pushq %rbx movq %rdx, %rbx movl %esi, %ebp movq %rdi, %r14 callq 0x44557 cmpl $0x7ffffff, %ebp # imm = 0x7FFFFFF ja 0xc0485 movq %r14, %rdi movl $0xa3, %esi callq 0x4459a movq %r14, %rdi movl %ebp, %esi movq %rbx, %rdx popq %rbx popq %r14 popq %rbp jmp 0xbfd53 xorl %eax, %eax popq %rbx popq...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
XCore_insn_extract
void XCore_insn_extract(MCInst *MI, const char *code) { int id; char *p, *p2; char tmp[128]; // make MSVC shut up on strcpy() #ifdef _MSC_VER #pragma warning(push) #pragma warning(disable : 4996) #endif strcpy(tmp, code); // safe because code is way shorter than 128 bytes #ifdef _MSC_VER #pragma warning(pop) #endi...
pushq %r15 pushq %r14 pushq %rbx subq $0x80, %rsp movq %rdi, %rbx movq %rsp, %r14 movq %r14, %rdi callq 0x43060 movq %r14, %rdi movl $0x20, %esi callq 0x43090 testq %rax, %rax je 0xc0710 movq %rax, %r15 incq %r15 movq %r15, %rdi movl $0x2c, %esi callq 0x43090 testq %rax, %rax je 0xc056e movq %rax, %r14 movb $0x0, (%rax...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreInstPrinter.c
printOperand
static void printOperand(MCInst *MI, int OpNum, SStream *O) { if (OpNum >= MI->size) return; _printOperand(MI, MCInst_getOperand(MI, OpNum), O); }
movzbl 0x4(%rdi), %eax cmpl %esi, %eax jle 0xc1063 pushq %r15 pushq %r14 pushq %rbx movq %rdx, %r15 movq %rdi, %rbx callq 0x445a8 movq %rax, %r14 movq %rax, %rdi callq 0x445e6 testb %al, %al je 0xc0f82 movq %r14, %rdi callq 0x445fe movl %eax, %r14d leal -0x1(%r14), %eax leaq 0x8ebe8(%rip), %rcx # 0x14fb10 movl (%rc...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreInstPrinter.c
XCore_reg_id
xcore_reg XCore_reg_id(char *name) { int i; for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { if (!strcmp(name, reg_name_maps[i].name)) return reg_name_maps[i].id; } // not found return 0; }
pushq %r15 pushq %r14 pushq %rbx movq %rdi, %rbx movl $0x18, %r14d leaq 0xd068c(%rip), %r15 # 0x191720 movq (%r14,%r15), %rsi movq %rbx, %rdi callq 0x430d0 testl %eax, %eax je 0xc10b5 addq $0x10, %r14 cmpq $0x1a8, %r14 # imm = 0x1A8 jne 0xc1094 xorl %eax, %eax jmp 0xc10ba movl -0x8(%r14,%r15), %eax popq ...
/sidneyp[P]capstone-tricore/arch/XCore/XCoreMapping.c
A64NamedImmMapper_fromString
uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid) { unsigned i; for (i = 0; i < N->NumPairs; ++i) { if (compare_lower_str(N->Pairs[i].Name, Name)) { *Valid = true; return N->Pairs[i].Value; } } *Valid = false; return (uint32_t)-1; }
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x18, %rsp movq %rdx, 0x8(%rsp) movq %rsi, 0x10(%rsp) cmpq $0x0, 0x8(%rdi) je 0xc12a6 movq %rdi, %r14 xorl %r15d, %r15d xorl %ebx, %ebx movq (%r14), %rax shlq $0x4, %r15 movq (%rax,%r15), %r13 movq 0x10(%rsp), %rdi callq 0x476ec movq %rax, %r12 mov...
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64BaseInfo.c
bool sptk::ReadStream<unsigned long>(bool, int, int, int, std::vector<unsigned long, std::allocator<unsigned long>>*, std::istream*, int*)
bool ReadStream(bool zero_padding, int stream_skip, int read_point, int read_size, std::vector<T>* sequence_to_read, std::istream* input_stream, int* actual_read_size) { if (stream_skip < 0 || read_point < 0 || read_size <= 0 || NULL == sequence_to_read || NULL == input_stream ||...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx pushq %rax movl %ecx, %r15d movl %edx, %r13d movl %edx, %eax orl %esi, %eax sets %al testl %ecx, %ecx setle %cl orb %al, %cl testq %r8, %r8 sete %al testq %r9, %r9 sete %dl orb %al, %dl orb %cl, %dl jne 0xb1a4 movq %r9, %rbx movq (%r9), %rax movq -0x18(%...
/sp-nitech[P]SPTK/src/utils/sptk_utils.cc
sptk::reaper::EpochTracker::GetVoiceTransitionFeatures()
void EpochTracker::GetVoiceTransitionFeatures(void) { int32_t frame_offset = RoundUp(0.5 * time_span_ / internal_frame_interval_); if (frame_offset <= 0) { frame_offset = 1; } voice_onset_prob_.resize(n_feature_frames_); voice_offset_prob_.resize(n_feature_frames_); int32_t limit = n_feature_frames_ - f...
pushq %rbp pushq %r15 pushq %r14 pushq %rbx pushq %rax movq %rdi, %rbx cvtss2sd 0x1a8(%rdi), %xmm0 movsd 0x1bd3a(%rip), %xmm1 # 0x2a028 mulsd %xmm1, %xmm0 cvtss2sd 0x174(%rdi), %xmm2 divsd %xmm2, %xmm0 cvtsd2ss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 cvttsd2si %xmm0, %eax cmpl $0x2, %eax movl $0x1, %eb...
/sp-nitech[P]SPTK/third_party/REAPER/epoch_tracker/epoch_tracker.cc
sptk::reaper::LpcAnalyzer::~LpcAnalyzer()
~LpcAnalyzer(void) { }
pushq %rbx movq %rdi, %rbx movq 0x18(%rdi), %rdi testq %rdi, %rdi je 0x10cd0 callq 0x4300 movq (%rbx), %rdi testq %rdi, %rdi je 0x10cde popq %rbx jmp 0x4300 popq %rbx retq
/sp-nitech[P]SPTK/third_party/REAPER/epoch_tracker/lpc_analyzer.h
sptk::reaper::LpcAnalyzer::Durbin(float*, float*, float*, int, float*)
void LpcAnalyzer::Durbin(float* r, float* k, float* a, int p, float* ex) { float bb[BIGSORD]; int i, j; float e, s, *b = bb; e = *r; *k = -r[1] / e; *a = *k; e *= (1.0 - (*k) * (*k)); for (i = 1; i < p; i++) { s = 0; for (j = 0; j < i; j++) { s -= a[j] * r[i - j]; } k[i] = (s - r...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x1c8, %rsp # imm = 0x1C8 movq %r9, 0x10(%rsp) movss (%rsi), %xmm0 movss 0x4(%rsi), %xmm1 xorps 0x16ab6(%rip), %xmm1 # 0x2aa40 divss %xmm0, %xmm1 movss %xmm1, (%rdx) movss %xmm1, (%rcx) movss (%rdx), %xmm1 mulss %xmm1, %xmm1 cvtss2sd ...
/sp-nitech[P]SPTK/third_party/REAPER/epoch_tracker/lpc_analyzer.cc
sptk::swipe::im2m(sptk::swipe::intmatrix)
matrix im2m(intmatrix yr_matrix) { matrix nw_matrix = makem(yr_matrix.x, yr_matrix.y); int i, j; for (i = 0; i < yr_matrix.x; i++) for (j = 0; j < yr_matrix.y; j++) nw_matrix.m[i][j] = yr_matrix.m[i][j]; return(nw_matrix); }
pushq %r15 pushq %r14 pushq %rbx movq %rsi, %rbx movq %rdi, %r14 movq %rdi, %r15 shrq $0x20, %r15 movl %r15d, %esi callq 0x16c00 testl %r14d, %r14d jle 0x17233 andl $0x7fffffff, %r14d # imm = 0x7FFFFFFF xorl %ecx, %ecx testl %r15d, %r15d jle 0x1722b movq (%rbx,%rcx,8), %rsi movq (%rdx,%rcx,8), %rdi xorl %r8d, %r8d...
/sp-nitech[P]SPTK/third_party/SWIPE/vector.cc
sptk::world::fft_plan_dft_r2c_1d(int, double*, double (*) [2], unsigned int)
fft_plan fft_plan_dft_r2c_1d(int n, double *in, fft_complex *out, unsigned int flags) { #if 0 void makewt(int nw, int *ip, double *w); void makect(int nc, int *ip, double *c); #endif fft_plan output = {0}; output.n = n; output.in = in; output.c_in = NULL; output.out = NULL; output.c_out = out; ou...
pushq %r15 pushq %r14 pushq %r12 pushq %rbx pushq %rax movslq %esi, %rbx leal (%rbx,%rbx,4), %eax leal (%rbx,%rbx,4), %esi addl $0x3, %esi testl %eax, %eax cmovnsl %eax, %esi sarl $0x2, %esi movslq %esi, %r15 shlq $0x3, %r15 testl %ebx, %ebx movq $-0x1, %rax cmovsq %rax, %r15 leaq (,%rbx,4), %r12 testl %ebx, %ebx cmovs...
/sp-nitech[P]SPTK/third_party/WORLD/fft_world.cc
nga_sdot_patch_
Real nga_sdot_patch_(Integer *g_a, char *t_a, int alen, Integer *alo, Integer *ahi, Integer *g_b, char *t_b, int blen, Integer *blo, Integer *bhi) #endif { Real retval; Integer atype, btype; pnga_inquire_type(*g_a, &atype); pnga_inquire_type(*g_b, &btype); if (atype != btype || atype != C_FLOAT) pn...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x28, %rsp movq %r9, 0x8(%rsp) movq %r8, %r13 movq %rcx, %r14 movq %rdx, %r15 movq %rsi, %r12 movq %rdi, %rbp movq (%rdi), %rdi leaq 0x20(%rsp), %rbx movq %rbx, %rsi callq 0x6697b movq (%r13), %rdi leaq 0x10(%rsp), %rsi callq 0x6697b cmpq $0x3eb, (...
/GlobalArrays[P]ga/global/src/fapi.c
ga_cadd_patch_
void FATR ga_cadd_patch_(SingleComplex *alpha, Integer *g_a, Integer *ailo, Integer *aihi, Integer *ajlo, Integer *ajhi, SingleComplex *beta, Integer *g_b, Integer *bilo, Integer *bihi, Integer *bjlo, Integer *bjhi, Integer *g_c, Integer *cilo, Integer *cihi, Integer *cjlo, Integer *cjhi) { Integer atype, btype, ct...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x38, %rsp movq %r9, 0x18(%rsp) movq %r8, 0x10(%rsp) movq %rcx, 0x8(%rsp) movq %rdx, %r12 movq %rsi, %rbp movq %rdi, %r13 movq 0xa0(%rsp), %r15 movq 0x78(%rsp), %r14 movq (%rsi), %rdi leaq 0x30(%rsp), %rbx movq %rbx, %rsi callq 0x6697b movq (%r14),...
/GlobalArrays[P]ga/global/src/fapi.c
pnga_copy_patch_dp
void pnga_copy_patch_dp(t_a, g_a, ailo, aihi, ajlo, ajhi, g_b, bilo, bihi, bjlo, bjhi) Integer g_a, ailo, aihi, ajlo, ajhi; Integer g_b, bilo, bihi, bjlo, bjhi; char *t_a; { Integer atype, btype, adim1, adim2, bdim1, bdim2; Integer ilos, ihis, jlos, jhis; Integer ilod, ihid, jlod, jhid...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0xa8, %rsp movq %r9, (%rsp) movq %r8, 0x10(%rsp) movq %rcx, 0x8(%rsp) movq %rdx, 0x48(%rsp) movq %rsi, %r14 movq %rdi, 0x18(%rsp) movq 0xe0(%rsp), %rbp xorl %eax, %eax callq 0x685c6 movq %rax, 0x30(%rsp) movq $0x0, 0x20(%rsp) leaq 0xa784c(%rip), %r...
/GlobalArrays[P]ga/global/src/DP.c
pnga_add
void pnga_add(void *alpha, Integer g_a, void* beta, Integer g_b, Integer g_c) { Integer ndim, type, typeC, me, elems=0, elemsb=0, elemsa=0; register Integer i; void *ptr_a, *ptr_b, *ptr_c; Integer a_grp, b_grp, c_grp; int local_sync_begin,local_sync_end; Integer _dims[MAXDIM]; Integer _ld[MAXDIM-1]; Integer _lo[M...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x148, %rsp # imm = 0x148 movq %r8, %r13 movq %rcx, %r12 movq %rdx, 0x58(%rsp) movq %rsi, %r15 movq %rdi, 0x38(%rsp) leaq 0xc576b(%rip), %rax # 0xd7160 movl (%rax), %r14d leaq 0xc5765(%rip), %rcx # 0xd7164 movl (%rcx), %edx movl ...
/GlobalArrays[P]ga/global/src/global.nalg.c
pnga_patch_intersect
logical pnga_patch_intersect(Integer *lo, Integer *hi, Integer *lop, Integer *hip, Integer ndim) { Integer i; /* check consistency of patch coordinates */ for(i=0; i<ndim; i++) { if(hi[i] < lo[i]) return FALSE; /* inconsistent */ if(hip[i] < lop[i]) return FALSE;...
testq %r8, %r8 jle 0x12516 xorl %eax, %eax xorl %r9d, %r9d movq (%rsi,%r9,8), %r10 cmpq (%rdi,%r9,8), %r10 jl 0x12577 movq (%rcx,%r9,8), %r10 cmpq (%rdx,%r9,8), %r10 jl 0x12577 incq %r9 cmpq %r9, %r8 jne 0x124fa testq %r8, %r8 jle 0x1253c xorl %eax, %eax xorl %r9d, %r9d movq (%rsi,%r9,8), %r10 cmpq (%rdx,%r9,8), %r10 j...
/GlobalArrays[P]ga/global/src/global.npatch.c
pnga_dot_patch
void pnga_dot_patch(Integer g_a, char *t_a, Integer *alo, Integer *ahi, Integer g_b, char *t_b, Integer *blo, Integer *bhi, void *retval) { Integer i=0, j=0; Integer compatible=0; Integer atype=0, btype=0, andim=0, adims[MAXDIM], bndim=0, bdims[MAXDIM]; Integer loA[MAXDIM], hiA[MAXDIM], ldA[MAXDIM]; Integer l...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x8b8, %rsp # imm = 0x8B8 movq %r9, 0x10(%rsp) movq %rcx, %r12 movq %rdx, %r13 movq %rsi, 0x28(%rsp) movq %rdi, %r15 xorl %eax, %eax movq %rax, 0x78(%rsp) movq %rax, 0x58(%rsp) movq %rax, 0x70(%rsp) movq %rax, 0x18(%rsp) movq %rax, 0x48(...
/GlobalArrays[P]ga/global/src/global.npatch.c
pnga_print_patch_file2d
void pnga_print_patch_file2d(file, g_a, ilo, ihi, jlo, jhi, pretty) FILE *file; Integer g_a, ilo, ihi, jlo, jhi, pretty; /* Pretty = 0 ... spew output out with no formatting Pretty = 1 ... format output so that it is readable */ { #define BUFSIZE 6 #define FLEN 80 Integer i, j,jj, dim1, dim2, t...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x178, %rsp # imm = 0x178 movq %r9, %rbx movq %r8, %r14 movq %rcx, 0x68(%rsp) movq %rdx, 0x48(%rsp) movq %rsi, %r12 movq %rdi, %r13 movq $0x1, 0x18(%rsp) movq %rsi, %rdi callq 0x6071a movq %rax, %r15 movq %rax, %rdi callq 0x6979c leaq 0x...
/GlobalArrays[P]ga/global/src/global.util.c
pnga_summarize
void pnga_summarize(Integer verbose) { #define DEV stdout Integer i, j, g_a; Integer printed, arr_no; Integer type, active; char *name; Integer ndim, dims[MAXDIM]; Integer lop[MAXDIM], hip[MAXDIM]; Integer nproc = pnga_nnodes(); fprintf(DEV, " Summary of allocated global arrays...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0xf8, %rsp movq %rdi, %r14 xorl %eax, %eax callq 0x68602 movq %rax, %rbx movq 0xbbf1c(%rip), %rbp # 0xd6ef0 movq (%rbp), %rcx leaq 0x9828f(%rip), %rdi # 0xb326e movl $0x24, %esi movl $0x1, %edx callq 0x3570 movq (%rbp), %rcx leaq 0x9829a(%r...
/GlobalArrays[P]ga/global/src/global.util.c
printBlock
void printBlock(char * banner, Integer type, void *ptr, Integer lo[], Integer hi[], Integer ld[]) { Integer i,j; Integer offset; printf("p[%d] %s lo[0]: %d hi[0]: %d lo[1]: %d hi[1]: %d\n", (int)pnga_nodeid(),banner,(int)lo[0],(int)hi[0],(int)lo[1],(int)hi[1]); printf(" "); for (i=lo[0]; i<=hi[0]...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x28, %rsp movq %r9, 0x20(%rsp) movq %r8, %r12 movq %rcx, %r15 movq %rdx, 0x10(%rsp) movq %rsi, 0x18(%rsp) movq %rdi, %r13 xorl %eax, %eax callq 0x685c6 movl (%r15), %ecx movl 0x8(%r15), %r9d movl (%r12), %r8d movl 0x8(%r12), %edx movl %edx, (%rsp)...
/GlobalArrays[P]ga/global/src/matmul.c
pnga_set_diagonal
void pnga_set_diagonal(Integer g_a, Integer g_v) { Integer vndim, vdims, dim1, dim2, vtype, atype, type; Integer me = pnga_nodeid (), i, nproc = pnga_nnodes(); Integer andim, adims[2]; Integer loA[2], hiA[2], ld; Integer num_blocks_a; int local_sync_begin,local_sync_end; char *ptr; _iterator_hdl hdl; ...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x3e8, %rsp # imm = 0x3E8 movq %rsi, 0x48(%rsp) movq %rdi, 0x38(%rsp) xorl %eax, %eax callq 0x685c6 xorl %eax, %eax callq 0x68602 leaq 0xae1bc(%rip), %rax # 0xd7160 leaq 0xae1b9(%rip), %rcx # 0xd7164 cmpl $0x0, (%rax) movl (%rcx)...
/GlobalArrays[P]ga/global/src/matrix.c
pnga_shift_diagonal
void pnga_shift_diagonal(Integer g_a, void *c) { Integer loA[2], hiA[2]/*, dim1, dim2*/, ld; Integer andim, adims[2], type, atype; Integer me = pnga_nodeid (), i, nproc = pnga_nnodes(); char *ptr; Integer num_blocks_a; int local_sync_begin,local_sync_end; _iterator_hdl hdl; local_sync_begin = _ga_sync_...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x368, %rsp # imm = 0x368 movq %rsi, %rbx movq %rdi, %r14 xorl %eax, %eax callq 0x685c6 xorl %eax, %eax callq 0x68602 leaq 0xadcb9(%rip), %rax # 0xd7160 leaq 0xadcb6(%rip), %rcx # 0xd7164 cmpl $0x0, (%rax) movl (%rcx), %edx movl ...
/GlobalArrays[P]ga/global/src/matrix.c
pnga_diag_reuse
void pnga_diag_reuse(Integer reuse, Integer g_a, Integer g_s, Integer g_v, DoublePrecision *eval) { #if ENABLE_PEIGS # if ENABLE_F77 gai_diag_reuse_(&reuse, &g_a, &g_s, &g_v, eval); # else pnga_error("ga_diag:peigs interfaced, need to configure --enable-f77",0L); # endif #else pnga_error("ga_dia...
leaq 0x8a51d(%rip), %rdi # 0xb4858 xorl %esi, %esi jmp 0x18f07 nop
/GlobalArrays[P]ga/global/src/peigstubs.c
pnga_lu_solve
void pnga_lu_solve(char *tran, Integer g_a, Integer g_b) { Integer dimA1, dimA2, typeA; Integer dimB1, dimB2, typeB; Integer dimsA[2], dimsB[2], ndim; /** check GA info for input arrays */ pnga_check_handle(g_a, "ga_lu_solve: a"); pnga_check_handle(g_b, "ga_lu_solve: b"); pnga_inquire (g_a, &typeA, &ndi...
pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0x40, %rsp movq %rdx, %rbx movq %rsi, %r14 movq %rdi, %r15 leaq 0x87bf1(%rip), %rsi # 0xb1f60 movq %r14, %rdi callq 0x5d393 leaq 0x87bf1(%rip), %rsi # 0xb1f6f movq %rbx, %rdi callq 0x5d393 leaq 0x28(%rsp), %rsi leaq 0x18(%rsp), %r12 leaq 0x30(%rsp), %...
/GlobalArrays[P]ga/global/src/sclstubs.c
pnga_bin_index
void pnga_bin_index(Integer g_bin, Integer g_cnt, Integer g_off, Integer *values, Integer *subs, Integer n, Integer sortit) { int i, my_nbin=0; int *all_bin_contrib, *offset; Integer type, ndim, nbin; pnga_inquire(g_bin, &type, &ndim, &nbin); if(ndim !=1) pnga_error("ga_bin_index: 1-dim arr...
pushq %rbp pushq %r15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx subq $0xa8, %rsp movq %r9, %r13 movq %r8, %rbp movq %rcx, 0x58(%rsp) movq %rdx, 0x60(%rsp) movq %rsi, 0x80(%rsp) leaq 0x98(%rsp), %rsi leaq 0xa0(%rsp), %rbx leaq 0x30(%rsp), %rcx movq %rdi, 0x50(%rsp) movq %rbx, %rdx callq 0x6688f movq (%rbx), %rsi cmpq ...
/GlobalArrays[P]ga/global/src/sparse.c
pnga_sprs_array_column_distribution
void pnga_sprs_array_column_distribution(Integer s_a, Integer iproc, Integer *lo, Integer *hi) { Integer hdl = GA_OFFSET + s_a; Integer nproc = SPA[hdl].nprocs; Integer jdim = SPA[hdl].jdim; *lo = (SPA[hdl].jdim*iproc)/nproc; while (((*lo)*nproc)/jdim < iproc) { (*lo)++; } while (((*lo)*nproc)/jdi...
pushq %r14 pushq %rbx movq %rdx, %r8 leaq 0x9fcbb(%rip), %rax # 0xdc0c0 movq (%rax), %rax imulq $0xc8, %rdi, %rdx movq 0x30d48(%rax,%rdx), %r11 movq 0x30d90(%rax,%rdx), %rbx movq %r11, %rax imulq %rsi, %rax cqto idivq %rbx movq %rax, %r9 leaq -0x1(%rax), %r14 movq %rbx, %r10 imulq %r14, %r10 leaq -0x2(%rax), %rdi i...
/GlobalArrays[P]ga/global/src/sparse.array.c