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--- |
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license: bsd-3-clause |
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--- |
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# ChiPBench-D |
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ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms |
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Chip placement is a critical step in the Electronic Design Automation (EDA) workflow, which aims to arrange chip modules on the canvas to optimize the performance, power, and area (PPA) metrics of final designs. |
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Recent advances show great potential of AI-based algorithms in chip placement. |
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However, due to the lengthy EDA workflow, evaluations of these algorithms often focus on _intermediate surrogate metrics_, which are computationally efficient but often misalign with the final _end-to-end performance_ (i.e., the final design PPA). |
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To address this challenge, we propose to build **ChiPBench**, a comprehensive benchmark specifically designed to evaluate the effectiveness of AI-based algorithms in final design PPA metrics. |
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Specifically, we generate a diverse evaluation dataset from 20 circuits across various domains, such as CPUs, GPUs, and NPUs. |
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We present an end-to-end evaluation workflow for placement stages of the EDA flow. |
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To evaluate a stage-specific algorithm, the output from the preceding stage serves as its input, and the algorithm's output is reintegrated into the original design flow. |
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Final PPA metrics provide a comprehensive assessment, avoiding the limitations of isolated stage-specific metrics. |
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This approach facilitates algorithm optimization by ensuring improvements translate into practical chip design enhancements. |
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We believe ChiPBench will effectively bridge the gap between academia and industry. |
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This project represents the dataset part of ChiPBench. The code can be found on GitHub: [ChiPBench](https://github.com/MIRALab-USTC/ChiPBench). |
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## Details |
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### data |
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```bash |
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data |
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├── case_name |
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│ ├── def |
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│ ├── lef |
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│ ├── lib |
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│ ├── case_name.v |
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│ ├── constraint.sdc |
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``` |
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- **def**: DEF files. |
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- `pre_place.def`: Floorplan initialization completed; macros and standard cells are not yet placed. |
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- `macro_placed.def`: Macros are fixed in place (placed using OpenROAD's Hier-RTLMP method); standard cells are not yet placed. |
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- **lef**: Case-specific LEF files. |
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- **lib**: Case-specific LIB files. |
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- **case_name.v**: Synthesized netlist files for the case. |
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- **constraint.sdc**: Timing constraint files for the case. |
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**Download Using Croissant Format** |
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You only need to download the following files first: |
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- [`download_dataset.py`](https://huggingface.co/datasets/MIRA-Lab/ChiPBench-D/blob/main/download_dataset.py) |
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- [`chipbench_meta_data.json`](https://huggingface.co/datasets/MIRA-Lab/ChiPBench-D/blob/main/chipbench_meta_data.json) |
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Then run the following commands: |
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```bash |
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mkdir ChiPBench-D |
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cp download_dataset.py ChiPBench-D/ |
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cp chipbench_meta_data.json ChiPBench-D/ |
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cd ChiPBench-D/ |
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python3 download_dataset.py |
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``` |
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